From 0bd93292b3b058ceb1c28eabfc757d993b37ac06 Mon Sep 17 00:00:00 2001 From: Fan YANG Date: Tue, 15 Aug 2023 18:41:20 +0800 Subject: [PATCH] [bsp][hpmicro] Update libraries, add new BSPs - Updated hpm_sdk in libraries - Updated rt-thread driver adapter - Updated bsp for hpm6750evkmini - Updated bsp for hpm6750evk - Added bsp for hpm6750evk2 - Added bsp for hpm6300evk - Added bsp for hpm6200evk Signed-off-by: Fan YANG --- bsp/hpmicro/.ignore_format.yml | 11 + bsp/hpmicro/hpm6200evk/.config | 1043 + bsp/hpmicro/hpm6200evk/Kconfig | 21 + bsp/hpmicro/hpm6200evk/README.md | 114 + bsp/hpmicro/hpm6200evk/README_zh.md | 115 + bsp/hpmicro/hpm6200evk/SConscript | 17 + bsp/hpmicro/hpm6200evk/SConstruct | 75 + .../applications}/SConscript | 2 +- bsp/hpmicro/hpm6200evk/applications/main.c | 38 + bsp/hpmicro/hpm6200evk/board/Kconfig | 289 + bsp/hpmicro/hpm6200evk/board/SConscript | 18 + bsp/hpmicro/hpm6200evk/board/board.c | 710 + bsp/hpmicro/hpm6200evk/board/board.h | 423 + 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.../openocd/probes/nds_aice_micro.cfg | 0 .../debug_scripts/openocd/soc/hpm6360-csr.cfg | 50 + .../debug_scripts}/openocd/soc/hpm6360.cfg | 0 bsp/hpmicro/hpm6300evk/board/eth_phy_port.c | 299 + bsp/hpmicro/hpm6300evk/board/eth_phy_port.h | 85 + bsp/hpmicro/hpm6300evk/board/fal_cfg.h | 40 + bsp/hpmicro/hpm6300evk/board/fal_flash_port.c | 254 + .../board/linker_scripts/flash_rtt.ld | 304 + .../board/linker_scripts/flash_sdram_rtt.ld | 297 + .../board/linker_scripts/ram_rtt.ld | 259 + .../board/linker_scripts/ram_sdram_rtt.ld | 252 + .../hpm6300evk => hpm6300evk/board}/pinmux.c | 40 +- .../hpm6300evk => hpm6300evk/board}/pinmux.h | 6 +- bsp/hpmicro/hpm6300evk/board/rtt_board.c | 122 + bsp/hpmicro/hpm6300evk/board/rtt_board.h | 59 + bsp/hpmicro/hpm6300evk/figures/board.png | Bin 0 -> 535149 bytes bsp/hpmicro/hpm6300evk/rtconfig.h | 242 + bsp/hpmicro/hpm6300evk/rtconfig.py | 108 + .../startup/HPM6360/SConscript | 1 + .../startup/HPM6360/startup.c | 22 +- .../startup/HPM6360/toolchains/gcc/port_gcc.S | 23 + .../startup/HPM6360/toolchains/gcc/start.S | 4 +- .../startup/HPM6360/toolchains/gcc/vectors.S | 2 +- .../startup/HPM6360/trap.c | 138 +- bsp/hpmicro/hpm6300evk/startup/SConscript | 13 + bsp/hpmicro/hpm6750evk/.config | 77 +- bsp/hpmicro/hpm6750evk/README.md | 116 + bsp/hpmicro/hpm6750evk/README_zh.md | 115 + bsp/hpmicro/hpm6750evk/board/Kconfig | 38 +- bsp/hpmicro/hpm6750evk/board/SConscript | 1 - bsp/hpmicro/hpm6750evk/board/board.c | 183 +- bsp/hpmicro/hpm6750evk/board/board.h | 97 +- .../debug_scripts/openocd/soc/hpm6750-csr.cfg | 51 +- .../openocd/soc/hpm6750-dual-core.cfg | 49 +- bsp/hpmicro/hpm6750evk/board/eth_phy_port.c | 13 +- bsp/hpmicro/hpm6750evk/board/eth_phy_port.h | 3 - bsp/hpmicro/hpm6750evk/board/fal_cfg.h | 5 +- bsp/hpmicro/hpm6750evk/board/fal_flash_port.c | 11 +- .../board/linker_scripts/flash_rtt.ld | 150 +- .../board/linker_scripts/flash_rtt_enet.ld | 166 +- .../board/linker_scripts/flash_sdram_rtt.ld} | 117 +- .../board/linker_scripts/ram_rtt.ld | 133 +- .../board/linker_scripts/ram_sdram_rtt.ld | 252 + bsp/hpmicro/hpm6750evk/board/pinmux.c | 63 +- bsp/hpmicro/hpm6750evk/board/pinmux.h | 5 +- bsp/hpmicro/hpm6750evk/board/rtt_board.c | 5 + bsp/hpmicro/hpm6750evk/board/trap_gcc.S | 12 - bsp/hpmicro/hpm6750evk/figures/board.png | Bin 0 -> 69601 bytes bsp/hpmicro/hpm6750evk/rtconfig.h | 24 +- bsp/hpmicro/hpm6750evk/rtconfig.py | 42 +- .../hpm6750evk/startup/HPM6750/SConscript | 1 + .../hpm6750evk/startup/HPM6750/startup.c | 22 +- .../startup/HPM6750/toolchains/gcc/port_gcc.S | 23 + .../startup/HPM6750/toolchains/gcc/start.S | 10 +- .../startup/HPM6750/toolchains/gcc/vectors.S | 2 +- bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c | 138 +- bsp/hpmicro/hpm6750evk2/.config | 1036 + bsp/hpmicro/hpm6750evk2/Kconfig | 21 + bsp/hpmicro/hpm6750evk2/README.md | 116 + bsp/hpmicro/hpm6750evk2/README_zh.md | 115 + bsp/hpmicro/hpm6750evk2/SConscript | 17 + bsp/hpmicro/hpm6750evk2/SConstruct | 75 + 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.../hpm_sdk/drivers/inc/hpm_femc_drv.h | 293 + .../hpm_sdk/drivers/inc/hpm_ffa_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_gpio_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_gpiom_drv.h | 24 +- .../hpm_sdk/drivers/inc/hpm_gptmr_drv.h | 125 +- .../hpm_sdk/drivers/inc/hpm_hall_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_i2c_drv.h | 181 +- .../hpm_sdk/drivers/inc/hpm_i2s_common.h | 23 +- .../hpm_sdk/drivers/inc/hpm_i2s_drv.h | 154 +- .../hpm_sdk/drivers/inc/hpm_jpeg_drv.h | 33 +- .../hpm_sdk/drivers/inc/hpm_lcdc_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_lin_drv.h | 340 + .../hpm_sdk/drivers/inc/hpm_mbx_drv.h | 6 +- .../hpm_sdk/drivers/inc/hpm_mcan_drv.h | 1577 + .../hpm_sdk/drivers/inc/hpm_mchtmr_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_mono_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_pdm_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_pdma_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_pla_drv.h | 560 + .../hpm_sdk/drivers/inc/hpm_pllctl_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h | 3 +- .../hpm_sdk/drivers/inc/hpm_pmon_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_pmp_drv.h | 17 +- .../hpm_sdk/drivers/inc/hpm_psec_drv.h | 10 +- .../hpm_sdk/drivers/inc/hpm_ptpc_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_pwm_drv.h | 241 +- .../hpm_sdk/drivers/inc/hpm_qei_drv.h | 24 +- .../hpm_sdk/drivers/inc/hpm_rng_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h | 4 +- .../drivers/inc/hpm_romapi_xpi_nor_def.h | 2 +- .../drivers/inc/hpm_romapi_xpi_ram_def.h | 11 +- .../hpm_sdk/drivers/inc/hpm_rtc_drv.h | 8 +- .../hpm_sdk/drivers/inc/hpm_sdm_drv.h | 468 + .../hpm_sdk/drivers/inc/hpm_sdp_drv.h | 529 +- .../hpm_sdk/drivers/inc/hpm_sdxc_drv.h | 37 +- .../hpm_sdk/drivers/inc/hpm_spi_drv.h | 427 +- .../hpm_sdk/drivers/inc/hpm_synt_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_trgm_drv.h | 9 +- .../hpm_sdk/drivers/inc/hpm_tsns_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_uart_drv.h | 314 +- .../hpm_sdk/drivers/inc/hpm_usb_drv.h | 93 +- .../hpm_sdk/drivers/inc/hpm_vad_drv.h | 2 +- .../hpm_sdk/drivers/inc/hpm_wdg_drv.h | 78 +- .../hpm_sdk/drivers/src/hpm_acmp_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_adc12_drv.c | 57 +- .../hpm_sdk/drivers/src/hpm_adc16_drv.c | 161 +- .../hpm_sdk/drivers/src/hpm_cam_drv.c | 94 +- .../hpm_sdk/drivers/src/hpm_can_drv.c | 150 +- .../hpm_sdk/drivers/src/hpm_crc_drv.c | 96 + .../hpm_sdk/drivers/src/hpm_dac_drv.c | 59 +- .../hpm_sdk/drivers/src/hpm_dao_drv.c | 10 +- .../hpm_sdk/drivers/src/hpm_dma_drv.c | 95 +- .../hpm_sdk/drivers/src/hpm_dram_drv.c | 338 - .../hpm_sdk/drivers/src/hpm_enet_drv.c | 436 +- .../hpm_sdk/drivers/src/hpm_femc_drv.c | 379 + .../hpm_sdk/drivers/src/hpm_ffa_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_gpio_drv.c | 44 +- .../hpm_sdk/drivers/src/hpm_gptmr_drv.c | 20 +- .../hpm_sdk/drivers/src/hpm_i2c_drv.c | 486 +- .../hpm_sdk/drivers/src/hpm_i2s_drv.c | 328 +- .../hpm_sdk/drivers/src/hpm_jpeg_drv.c | 84 +- .../hpm_sdk/drivers/src/hpm_lcdc_drv.c | 112 +- .../hpm_sdk/drivers/src/hpm_lin_drv.c | 357 + .../hpm_sdk/drivers/src/hpm_mcan_drv.c | 1685 + .../hpm_sdk/drivers/src/hpm_mchtmr_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_pcfg_drv.c | 12 +- .../hpm_sdk/drivers/src/hpm_pdm_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_pdma_drv.c | 310 +- .../hpm_sdk/drivers/src/hpm_pla_drv.c | 201 + .../hpm_sdk/drivers/src/hpm_pllctl_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_pllctlv2_drv.c | 43 +- .../hpm_sdk/drivers/src/hpm_pmp_drv.c | 32 +- .../hpm_sdk/drivers/src/hpm_ptpc_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_pwm_drv.c | 39 +- .../hpm_sdk/drivers/src/hpm_rng_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_rtc_drv.c | 39 +- .../hpm_sdk/drivers/src/hpm_sdm_drv.c | 184 + .../hpm_sdk/drivers/src/hpm_sdp_drv.c | 267 +- .../hpm_sdk/drivers/src/hpm_sdxc_drv.c | 297 +- .../hpm_sdk/drivers/src/hpm_spi_drv.c | 270 +- .../hpm_sdk/drivers/src/hpm_tsns_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_uart_drv.c | 95 +- .../hpm_sdk/drivers/src/hpm_usb_drv.c | 130 +- .../hpm_sdk/drivers/src/hpm_vad_drv.c | 2 +- .../hpm_sdk/drivers/src/hpm_wdg_drv.c | 116 +- bsp/hpmicro/libraries/hpm_sdk/env.sh | 27 - .../libraries/hpm_sdk/hpm_sdk_version.h.in | 24 + bsp/hpmicro/libraries/hpm_sdk/index.md | 15 - bsp/hpmicro/libraries/hpm_sdk/index_zh.md | 15 - .../libraries/hpm_sdk/soc/HPM6280/SConscript | 25 + .../hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c | 42 + .../hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h | 64 + .../hpm_sdk/soc/HPM6280/hpm_batt_iomux.h | 59 + .../hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h | 74 + .../hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h | 205 + .../soc/{ip => HPM6280}/hpm_bgpr_regs.h | 4 +- .../inc => soc/HPM6280}/hpm_bpor_drv.h | 53 +- .../soc/{ip => HPM6280}/hpm_bpor_regs.h | 4 +- .../hpm_sdk/soc/HPM6280/hpm_clock_drv.c | 498 + .../hpm_sdk/soc/HPM6280/hpm_clock_drv.h | 324 + .../hpm_sdk/soc/HPM6280/hpm_csr_regs.h | 6512 + .../soc/{ip => HPM6280}/hpm_dmamux_regs.h | 4 +- .../hpm_sdk/soc/HPM6280/hpm_dmamux_src.h | 88 + .../hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h | 105 + .../hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h | 29 + .../hpm_sdk/soc/HPM6280/hpm_interrupt.h | 1040 + .../hpm_sdk/soc/HPM6280/hpm_ioc_regs.h | 311 + .../libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h | 958 + .../hpm_sdk/soc/HPM6280/hpm_l1c_drv.c | 135 + .../hpm_sdk/soc/HPM6280/hpm_l1c_drv.h | 485 + .../hpm_sdk/soc/HPM6280/hpm_mcan_soc.h | 91 + .../libraries/hpm_sdk/soc/HPM6280/hpm_misc.h | 38 + .../hpm_sdk/soc/HPM6280/hpm_otp_drv.c | 181 + .../hpm_sdk/soc/HPM6280/hpm_otp_drv.h | 137 + .../inc => soc/HPM6280}/hpm_pcfg_drv.h | 346 +- .../hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h | 925 + .../soc/{ip => HPM6280}/hpm_pgpr_regs.h | 4 +- .../hpm_sdk/soc/HPM6280/hpm_plic_drv.h | 186 + .../hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h | 61 + .../inc => soc/HPM6280}/hpm_ppor_drv.h | 2 +- .../soc/{ip => HPM6280}/hpm_ppor_regs.h | 4 +- .../hpm_sdk/soc/HPM6280/hpm_romapi.h | 1021 + .../soc/HPM6280/hpm_romapi_xpi_soc_def.h | 80 + .../hpm_sdk/soc/HPM6280/hpm_ses_reg.xml | 44747 +++++ .../soc/HPM6280/hpm_ses_riscv_cpu_regs.xml | 770 + .../libraries/hpm_sdk/soc/HPM6280/hpm_soc.h | 709 + .../hpm_sdk/soc/HPM6280/hpm_soc_feature.h | 179 + .../hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c | 303 + .../hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h | 1521 + .../hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h | 1403 + .../hpm_sdk/soc/HPM6280/hpm_trgm_regs.h | 233 + .../hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h | 734 + .../hpm_sdk/soc/HPM6280/soc_modules.list | 40 + .../libraries/hpm_sdk/soc/HPM6280/system.c | 71 + .../soc/HPM6280/toolchains/gcc/flash.ld | 212 + .../soc/HPM6280/toolchains/gcc/flash_uf2.ld | 216 + .../soc/HPM6280/toolchains/gcc/flash_xip.ld | 234 + .../soc/HPM6280/toolchains/gcc/initfini.c | 75 + .../hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld | 208 + .../soc/HPM6280/toolchains/gcc/ram_core1.ld | 201 + .../soc/HPM6280/toolchains/gcc/start.S | 128 + .../hpm_sdk/soc/HPM6280/toolchains/reset.c | 113 + .../soc/HPM6280/toolchains/segger/flash.icf | 99 + .../HPM6280/toolchains/segger/flash_uf2.icf | 101 + .../HPM6280/toolchains/segger/flash_xip.icf | 111 + .../soc/HPM6280/toolchains/segger/ram.icf | 95 + .../HPM6280/toolchains/segger/ram_core1.icf | 93 + .../soc/HPM6280/toolchains/segger/startup.s | 392 + .../hpm_sdk/soc/HPM6280/toolchains/trap.c | 257 + .../hpm_sdk/soc/HPM6280/toolchains/vectors.h | 234 + .../hpm_sdk/soc/HPM6360/HPM6360_svd.xml | 103475 ----------- .../libraries/hpm_sdk/soc/HPM6360/SConscript | 1 + .../hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c | 2 +- .../hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h | 2 +- .../hpm_sdk/soc/HPM6360/hpm_batt_iomux.h | 26 +- .../hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h | 74 + .../hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h | 205 + .../hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h | 115 + .../hpm_sdk/soc/HPM6360/hpm_bpor_drv.h | 129 + .../hpm_sdk/soc/HPM6360/hpm_bpor_regs.h | 79 + .../hpm_sdk/soc/HPM6360/hpm_clock_drv.c | 45 +- .../hpm_sdk/soc/HPM6360/hpm_clock_drv.h | 21 +- .../hpm_sdk/soc/HPM6360/hpm_csr_regs.h | 4 +- .../hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h | 64 + .../hpm_sdk/soc/HPM6360/hpm_dmamux_src.h | 4 +- .../hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h | 58 +- .../hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h | 28 +- .../hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h | 2 +- .../hpm_sdk/soc/HPM6360/hpm_interrupt.h | 424 +- .../hpm_sdk/soc/HPM6360/hpm_ioc_regs.h | 42 +- .../libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h | 392 +- .../hpm_sdk/soc/HPM6360/hpm_l1c_drv.c | 19 +- .../hpm_sdk/soc/HPM6360/hpm_l1c_drv.h | 8 +- .../libraries/hpm_sdk/soc/HPM6360/hpm_misc.h | 2 +- .../hpm_sdk/soc/HPM6360/hpm_otp_drv.c | 2 +- .../hpm_sdk/soc/HPM6360/hpm_otp_drv.h | 2 +- .../hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h | 639 + .../soc/{ip => HPM6360}/hpm_pcfg_regs.h | 6 +- .../hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h | 211 + .../hpm_sdk/soc/HPM6360/hpm_plic_drv.h | 2 +- .../hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h | 26 +- .../hpm_sdk/soc/HPM6360/hpm_ppor_drv.h | 133 + .../hpm_sdk/soc/HPM6360/hpm_ppor_regs.h | 194 + .../hpm_sdk/soc/HPM6360/hpm_romapi.h | 415 +- .../soc/HPM6360/hpm_romapi_xpi_soc_def.h | 2 +- .../hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h | 27 +- .../hpm_sdk/soc/HPM6360/hpm_ses_reg.xml | 3593 +- .../libraries/hpm_sdk/soc/HPM6360/hpm_soc.h | 20 +- .../hpm_sdk/soc/HPM6360/hpm_soc_feature.h | 51 +- .../hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c | 13 +- .../hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h | 385 +- .../hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h | 32 +- .../hpm_sdk/soc/HPM6360/hpm_trgm_regs.h | 4 +- .../hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h | 28 +- .../hpm_sdk/soc/HPM6360/soc_modules.list | 4 +- .../libraries/hpm_sdk/soc/HPM6360/system.c | 12 +- .../soc/HPM6360/toolchains/gcc/flash.ld | 55 +- .../HPM6360/toolchains/gcc/flash_sdram_uf2.ld | 58 +- .../HPM6360/toolchains/gcc/flash_sdram_xip.ld | 54 +- .../soc/HPM6360/toolchains/gcc/flash_uf2.ld | 55 +- .../soc/HPM6360/toolchains/gcc/flash_xip.ld | 55 +- .../soc/HPM6360/toolchains/gcc/initfini.c | 75 + .../hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld | 69 +- .../soc/HPM6360/toolchains/gcc/start.S | 43 +- .../hpm_sdk/soc/HPM6360/toolchains/reset.c | 30 +- .../soc/HPM6360/toolchains/segger/flash.icf | 184 +- .../toolchains/segger/flash_sdram_uf2.icf | 181 +- .../toolchains/segger/flash_sdram_xip.icf | 204 +- .../HPM6360/toolchains/segger/flash_uf2.icf | 184 +- .../HPM6360/toolchains/segger/flash_xip.icf | 205 +- .../soc/HPM6360/toolchains/segger/ram.icf | 169 +- .../soc/HPM6360/toolchains/segger/startup.s | 47 +- .../hpm_sdk/soc/HPM6360/toolchains/trap.c | 18 +- .../hpm_sdk/soc/HPM6360/toolchains/vectors.h | 8 +- .../hpm_sdk/soc/HPM6750/HPM6750_svd.xml | 133497 --------------- .../libraries/hpm_sdk/soc/HPM6750/SConscript | 1 + .../hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c | 2 +- .../hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h | 36 + .../hpm_sdk/soc/HPM6750/hpm_batt_iomux.h | 4 +- .../hpm_sdk/soc/HPM6750/hpm_bcfg_drv.h | 105 + .../soc/{ip => HPM6750}/hpm_bcfg_regs.h | 4 +- .../hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h | 115 + .../hpm_sdk/soc/HPM6750/hpm_bpor_drv.h | 129 + .../hpm_sdk/soc/HPM6750/hpm_bpor_regs.h | 79 + .../hpm_sdk/soc/HPM6750/hpm_clock_drv.c | 37 +- .../hpm_sdk/soc/HPM6750/hpm_clock_drv.h | 5 +- .../hpm_sdk/soc/HPM6750/hpm_csr_regs.h | 4 +- .../hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h | 64 + .../hpm_sdk/soc/HPM6750/hpm_dmamux_src.h | 4 +- .../hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h | 71 +- .../hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h | 28 +- .../hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_interrupt.h | 366 +- .../hpm_sdk/soc/HPM6750/hpm_ioc_regs.h | 4 +- .../libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h | 249 +- .../hpm_sdk/soc/HPM6750/hpm_l1c_drv.c | 22 +- .../hpm_sdk/soc/HPM6750/hpm_l1c_drv.h | 8 +- .../libraries/hpm_sdk/soc/HPM6750/hpm_misc.h | 34 +- .../hpm_sdk/soc/HPM6750/hpm_otp_drv.c | 16 +- .../hpm_sdk/soc/HPM6750/hpm_otp_drv.h | 9 +- .../hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h | 639 + .../hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h | 927 + 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.../HPM6750/toolchains/gcc/flash_sdram_xip.ld | 100 +- .../soc/HPM6750/toolchains/gcc/flash_uf2.ld | 79 +- .../soc/HPM6750/toolchains/gcc/flash_xip.ld | 100 +- .../soc/HPM6750/toolchains/gcc/initfini.c | 75 + .../hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld | 98 +- .../soc/HPM6750/toolchains/gcc/ram_core1.ld | 88 +- .../soc/HPM6750/toolchains/gcc/start.S | 42 +- .../hpm_sdk/soc/HPM6750/toolchains/reset.c | 40 +- .../soc/HPM6750/toolchains/segger/flash.icf | 200 +- .../toolchains/segger/flash_sdram_uf2.icf | 198 +- .../toolchains/segger/flash_sdram_xip.icf | 216 +- .../HPM6750/toolchains/segger/flash_uf2.icf | 205 +- .../HPM6750/toolchains/segger/flash_xip.icf | 224 +- .../soc/HPM6750/toolchains/segger/ram.icf | 177 +- .../HPM6750/toolchains/segger/ram_core1.icf | 173 +- .../soc/HPM6750/toolchains/segger/startup.s | 71 +- .../hpm_sdk/soc/HPM6750/toolchains/trap.c | 16 +- .../hpm_sdk/soc/HPM6750/toolchains/vectors.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h | 46 +- .../libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h | 52 +- .../libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h | 12 +- .../libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h | 9 +- .../libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_butn_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_cam_regs.h | 313 +- .../libraries/hpm_sdk/soc/ip/hpm_can_regs.h | 4 +- .../hpm_sdk/soc/ip/hpm_conctl_regs.h | 61 +- .../libraries/hpm_sdk/soc/ip/hpm_crc_regs.h | 182 + .../libraries/hpm_sdk/soc/ip/hpm_dac_regs.h | 125 +- .../libraries/hpm_sdk/soc/ip/hpm_dao_regs.h | 15 +- .../libraries/hpm_sdk/soc/ip/hpm_dma_regs.h | 31 +- .../libraries/hpm_sdk/soc/ip/hpm_dram_regs.h | 834 - .../libraries/hpm_sdk/soc/ip/hpm_enet_regs.h | 1525 +- .../libraries/hpm_sdk/soc/ip/hpm_exip_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_femc_regs.h | 981 + .../libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h | 18 +- .../libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h | 93 +- .../libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h | 57 +- .../libraries/hpm_sdk/soc/ip/hpm_hall_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h | 51 +- .../libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h | 9 +- .../libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h | 14 +- .../libraries/hpm_sdk/soc/ip/hpm_keym_regs.h | 4 +- .../hpm_sdk/soc/ip/hpm_keyman_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h | 421 +- .../libraries/hpm_sdk/soc/ip/hpm_lin_regs.h | 355 + .../libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h | 3583 + .../hpm_sdk/soc/ip/hpm_mchtmr_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_mon_regs.h | 6 +- .../libraries/hpm_sdk/soc/ip/hpm_mono_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_otp_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h | 37 +- .../libraries/hpm_sdk/soc/ip/hpm_pla_regs.h | 1708 + .../libraries/hpm_sdk/soc/ip/hpm_plic_regs.h | 12 +- .../hpm_sdk/soc/ip/hpm_plic_sw_regs.h | 4 +- .../hpm_sdk/soc/ip/hpm_pllctl_regs.h | 4 +- .../hpm_sdk/soc/ip/hpm_pllctlv2_regs.h | 30 +- .../libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_psec_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h | 229 +- .../libraries/hpm_sdk/soc/ip/hpm_qei_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_rng_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h | 753 + .../libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h | 5 +- .../libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h | 305 +- .../libraries/hpm_sdk/soc/ip/hpm_sec_regs.h | 18 +- .../libraries/hpm_sdk/soc/ip/hpm_spi_regs.h | 204 +- .../libraries/hpm_sdk/soc/ip/hpm_synt_regs.h | 111 +- .../libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h | 39 +- .../libraries/hpm_sdk/soc/ip/hpm_uart_regs.h | 529 +- .../libraries/hpm_sdk/soc/ip/hpm_usb_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_vad_regs.h | 8 +- .../libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h | 4 +- .../libraries/hpm_sdk/utils/hpm_ffssi.c | 2 +- .../libraries/hpm_sdk/utils/hpm_sbrk.c | 2 +- .../libraries/hpm_sdk/utils/hpm_swap.c | 4 +- 685 files changed, 135406 insertions(+), 258066 deletions(-) create mode 100644 bsp/hpmicro/.ignore_format.yml create mode 100644 bsp/hpmicro/hpm6200evk/.config create mode 100644 bsp/hpmicro/hpm6200evk/Kconfig create mode 100644 bsp/hpmicro/hpm6200evk/README.md create mode 100644 bsp/hpmicro/hpm6200evk/README_zh.md create mode 100644 bsp/hpmicro/hpm6200evk/SConscript create mode 100644 bsp/hpmicro/hpm6200evk/SConstruct rename bsp/hpmicro/{libraries/hpm_sdk/boards/hpm6300evk => hpm6200evk/applications}/SConscript (57%) create mode 100644 bsp/hpmicro/hpm6200evk/applications/main.c create mode 100644 bsp/hpmicro/hpm6200evk/board/Kconfig create mode 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hpm6750evk2/board/debug_scripts}/openocd/boards/hpm6750evk.cfg (100%) rename bsp/hpmicro/{libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg => hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg} (82%) create mode 100644 bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/cmsis_dap.cfg create mode 100644 bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft2232.cfg create mode 100644 bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft232.cfg create mode 100644 bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/jlink.cfg create mode 100644 bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/nds_aice_micro.cfg rename bsp/hpmicro/{libraries/hpm_sdk/boards => hpm6750evk2/board/debug_scripts}/openocd/soc/hpm6750-csr.cfg (100%) rename bsp/hpmicro/{libraries/hpm_sdk/boards => hpm6750evk2/board/debug_scripts}/openocd/soc/hpm6750-dual-core.cfg (78%) rename bsp/hpmicro/{libraries/hpm_sdk/boards => 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bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dram_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dram_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/env.sh create mode 100644 bsp/hpmicro/libraries/hpm_sdk/hpm_sdk_version.h.in delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/index.md delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/index_zh.md create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/SConscript create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h rename bsp/hpmicro/libraries/hpm_sdk/soc/{ip => HPM6280}/hpm_bgpr_regs.h (98%) rename bsp/hpmicro/libraries/hpm_sdk/{drivers/inc => soc/HPM6280}/hpm_bpor_drv.h (55%) rename bsp/hpmicro/libraries/hpm_sdk/soc/{ip => HPM6280}/hpm_bpor_regs.h (97%) create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h rename bsp/hpmicro/libraries/hpm_sdk/soc/{ip => HPM6280}/hpm_dmamux_regs.h (97%) create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h rename bsp/hpmicro/libraries/hpm_sdk/{drivers/inc => soc/HPM6280}/hpm_pcfg_drv.h (60%) create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h rename bsp/hpmicro/libraries/hpm_sdk/soc/{ip => HPM6280}/hpm_pgpr_regs.h (99%) create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_plic_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h rename bsp/hpmicro/libraries/hpm_sdk/{drivers/inc => soc/HPM6280}/hpm_ppor_drv.h (98%) rename bsp/hpmicro/libraries/hpm_sdk/soc/{ip => HPM6280}/hpm_ppor_regs.h (99%) create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi_xpi_soc_def.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/initfini.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h rename bsp/hpmicro/libraries/hpm_sdk/soc/{ip => HPM6360}/hpm_pcfg_regs.h (99%) create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/initfini.c delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_drv.h rename bsp/hpmicro/libraries/hpm_sdk/soc/{ip => HPM6750}/hpm_bcfg_regs.h (99%) create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/initfini.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_crc_regs.h delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_femc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lin_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pla_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h diff --git a/bsp/hpmicro/.ignore_format.yml b/bsp/hpmicro/.ignore_format.yml new file mode 100644 index 0000000000..cad99bf470 --- /dev/null +++ b/bsp/hpmicro/.ignore_format.yml @@ -0,0 +1,11 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: + - hpm6200evk/startup + - hpm6300evk/startup + - hpm6750evk/startup + - hpm6750evk2/startup + - hpm6750evkmini/startup + - libraries/hpm_sdk diff --git a/bsp/hpmicro/hpm6200evk/.config b/bsp/hpmicro/hpm6200evk/.config new file mode 100644 index 0000000000..0917aa8c06 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/.config @@ -0,0 +1,1043 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# CONFIG_RT_USING_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6000=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_DMA_CHANNEL=0 +CONFIG_BSP_UART0_TX_DMA_CHANNEL=1 +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDXC is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm6200evk/Kconfig b/bsp/hpmicro/hpm6200evk/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm6200evk/README.md b/bsp/hpmicro/hpm6200evk/README.md new file mode 100644 index 0000000000..c494026161 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/README.md @@ -0,0 +1,114 @@ +# HPMicro HPM6200EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM6200EVK development board. + +The document consists of the following parts: + +- HPM6200EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6200EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| RTC | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6200EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6200evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/README_zh.md b/bsp/hpmicro/hpm6200evk/README_zh.md new file mode 100644 index 0000000000..95ad6a5a94 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/README_zh.md @@ -0,0 +1,115 @@ +# 先楫 HPM6200EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6200EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6200EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + + HPM6200EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | 由RT-Thread Industry IO扩展板提供支持 | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6200EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6200evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/SConscript b/bsp/hpmicro/hpm6200evk/SConscript new file mode 100644 index 0000000000..014c428d0a --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm6200evk/SConstruct b/bsp/hpmicro/hpm6200evk/SConstruct new file mode 100644 index 0000000000..3dadc575c0 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/SConscript b/bsp/hpmicro/hpm6200evk/applications/SConscript similarity index 57% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/SConscript rename to bsp/hpmicro/hpm6200evk/applications/SConscript index 7c742f69d0..a65aa4d855 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/SConscript +++ b/bsp/hpmicro/hpm6200evk/applications/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') CPPDEFINES=[] CPPPATH = [cwd] -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/hpmicro/hpm6200evk/applications/main.c b/bsp/hpmicro/hpm6200evk/applications/main.c new file mode 100644 index 0000000000..0bbf637038 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/applications/main.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" +#include + +void thread_entry(void *arg); + + +int main(void) +{ + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT); + + while(1){ + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON); + rt_thread_mdelay(500); + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6200evk/board/Kconfig b/bsp/hpmicro/hpm6200evk/board/Kconfig new file mode 100644 index 0000000000..5f352d3fba --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/Kconfig @@ -0,0 +1,289 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6000 + bool + select SOC_SERIES_HPM6000 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_DMA_CHANNEL + int "Set UART0 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART0_TX_DMA_CHANNEL + int "Set UART0 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_DMA_CHANNEL + int "Set UART2 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART2_TX_DMA_CHANNEL + int "Set UART2 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_DMA_CHANNEL + int "Set UART6 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART6_TX_DMA_CHANNEL + int "Set UART6 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default y + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH + if BSP_USING_ETH + choice + prompt "ETH" + config BSP_USING_ETH0 + bool "Enable ETH0" + endchoice + endif + + menuconfig BSP_USING_SDXC + bool "Enable SDXC" + default n + select RT_USING_SDIO if BSP_USING_SDXC + if BSP_USING_SDXC + config BSP_USING_SDXC0 + bool "Enable SDXC0" + default n + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + endif + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + endif + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select PKG_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + default n + endif + + + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + endif + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n + config BSP_USING_MCAN2 + bool "Enable MCAN2" + default n + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default y + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default y + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + endif +endmenu + + + +endmenu diff --git a/bsp/hpmicro/hpm6200evk/board/SConscript b/bsp/hpmicro/hpm6200evk/board/SConscript new file mode 100644 index 0000000000..c86c1ebc3f --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/SConscript @@ -0,0 +1,18 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6280'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6200evk/board/board.c b/bsp/hpmicro/hpm6200evk/board/board.c new file mode 100644 index 0000000000..2fe5ce3f98 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/board.c @@ -0,0 +1,710 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_pwm_drv.h" +#include "hpm_trgm_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_pcfg_drv.h" + +static board_timer_cb timer_cb; +ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE); + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t)BOARD_CONSOLE_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); + printf("axi:\t\t %dHz\n", clock_get_frequency(clock_axi)); + printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); + printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_print_banner(void) +{ + const uint8_t banner[] = { "\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_delay_us(uint32_t us) +{ + static uint32_t gptmr_freq; + gptmr_channel_config_t config; + + if (init_delay_flag == false) { + init_delay_flag = true; + clock_add_to_group(BOARD_DELAY_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_DELAY_TIMER_CLK_NAME); + gptmr_channel_get_default_config(BOARD_DELAY_TIMER, &config); + gptmr_channel_config(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH, &config, false); + } + + gptmr_channel_config_update_reload(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH, gptmr_freq / 1000000 * us); + gptmr_start_counter(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH); + while (!gptmr_check_status(BOARD_DELAY_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_DELAY_TIMER_CH))) { + __asm("nop"); + } + gptmr_stop_counter(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH); + gptmr_clear_status(BOARD_DELAY_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_DELAY_TIMER_CH)); +} + +void board_delay_ms(uint32_t ms) +{ + board_delay_us(1000 * ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + init_i2c_pins_as_gpio(ptr); +} + +void board_init_i2c(I2C_Type *ptr) +{ +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + /* SPI1 clock configure */ + clock_add_to_group(clock_spi1, 0); + clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); /* 80MHz */ + + return clock_get_frequency(clock_spi1); + } else if (ptr == HPM_SPI2) { + /* SPI3 clock configure */ + clock_add_to_group(clock_spi2, 0); + clock_set_source_divider(clock_spi2, clk_src_pll0_clk0, 5U); /* 80MHz */ + + return clock_get_frequency(clock_spi2); + } else if (ptr == HPM_SPI3) { + /* SPI3 clock configure */ + clock_add_to_group(clock_spi3, 0); + clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */ + + return clock_get_frequency(clock_spi3); + } + return 0; +} + +uint32_t board_init_lin_clock(LIN_Type *ptr) +{ + if (ptr == HPM_LIN0) { + clock_add_to_group(clock_lin0, 0); + clock_set_source_divider(clock_lin0, clk_src_pll0_clk0, 20U); /* 20MHz */ + + return clock_get_frequency(clock_lin0); + } + return 0; +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_led_toggle(void) +{ +#ifdef BOARD_LED_TOGGLE_RGB + static uint8_t i; + switch (i) { + case 1: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_ON_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + break; + + case 2: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_ON_LEVEL); + break; + + case 0: + default: + gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_ON_LEVEL); + gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + break; + } + i++; + i = i % 3; +#else + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +#endif +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_usb_pins(void) +{ + /* set pull-up for USBx ID pin */ + init_usb_pins(); + + /* configure USBx ID pin as input function */ + gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); +} + +uint8_t board_get_usb_id_status(void) +{ + return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ +} + +void board_init_pmp(void) +{ + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + start_addr = (uint32_t)__noncacheable_start__; + end_addr = (uint32_t)__noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; + } + + /* Init share memory */ + extern uint32_t __share_mem_start__[]; + extern uint32_t __share_mem_end__[]; + start_addr = (uint32_t)__share_mem_start__; + end_addr = (uint32_t)__share_mem_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; + } + + pmp_config(&pmp_entry[0], index); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahbp, 0); + clock_add_to_group(clock_axic, 0); + clock_add_to_group(clock_axis, 0); + + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_lin0, 0); + clock_add_to_group(clock_lin1, 0); + clock_add_to_group(clock_lin2, 0); + clock_add_to_group(clock_lin3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_mot1, 0); + clock_add_to_group(clock_mot2, 0); + clock_add_to_group(clock_mot3, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_msyn, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); + + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_adc2, 0); + + clock_add_to_group(clock_dac0, 0); + clock_add_to_group(clock_dac1, 0); + + clock_add_to_group(clock_tsns, 0); + clock_add_to_group(clock_crc0, 0); + clock_add_to_group(clock_sdm0, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Add the CPU1 clock to Group1 */ + clock_add_to_group(clock_mchtmr1, 1); + + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); + + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); + + /* Configure CPU to 600MHz, AXI/AHB to 200MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clk_src_pll1_clk0, 1, 3, 3); + /* Connect CAN2/CAN3 to pll0clk0*/ + clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1); + clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1); + + /* Configure PLL1_CLK0 Post Divider to 1 */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0); + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000); + clock_update_core_clock(); + + /* Configure AHB to 200MHz */ + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, 0); + clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr0); + } + else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, 0); + clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr1); + } + else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, 0); + clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr2); + } + else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, 0); + clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr3); + } + else { + /* Invalid instance */ + } +} + +uint32_t board_init_adc12_clock(ADC16_Type *ptr) +{ + uint32_t freq = 0; + switch ((uint32_t)ptr) { + case HPM_ADC0_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc0); + break; + case HPM_ADC1_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc1); + break; + case HPM_ADC2_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc2); + break; + default: + /* Invalid ADC instance */ + break; + } + + return freq; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr) +{ + return 0; +} + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_DAC0) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 133MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ana3); + clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac0); + } + + return freq; +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + /* Set the CAN0 peripheral clock to 8MHz */ + clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_MCAN1) { + /* Set the CAN1 peripheral clock to 8MHz */ + clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_MCAN2) { + /* Set the CAN2 peripheral clock to 8MHz */ + clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 5); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_MCAN3) { + /* Set the CAN2 peripheral clock to 8MHz */ + clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 5); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); + break; + case BOARD_RGB_GREEN: + pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); + break; + case BOARD_RGB_BLUE: + pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); + break; + default: + while (1) { + ; + } + } +} + +void board_enable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); + break; + case BOARD_RGB_GREEN: + pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); + break; + case BOARD_RGB_BLUE: + pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); + break; + default: + while (1) { + ; + } + } +} +void board_init_dac_pins(DAC_Type *ptr) +{ + init_dac_pins(ptr); +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_pll1_clk0, 6); + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_pll1_clk0, 6); + clock_add_to_group(clock_uart1, 0); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_pll1_clk0, 6); + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART6) { + clock_set_source_divider(clock_uart6, clk_src_pll1_clk0, 6); + clock_add_to_group(clock_uart6, 0); + freq = clock_get_frequency(clock_uart6); + } else { + /* Not supported */ + } + return freq; +} diff --git a/bsp/hpmicro/hpm6200evk/board/board.h b/bsp/hpmicro/hpm6200evk/board/board.h new file mode 100644 index 0000000000..173be58bcd --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/board.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm6200evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +#define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* uart section */ +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART0 +#define BOARD_APP_UART_IRQ IRQn_UART0 +#else +#ifndef BOARD_APP_UART_IRQ +#warning no IRQ specified for applicaiton uart +#endif +#endif + +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart0 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX + +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_BASE HPM_UART0 +#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#else +#define BOARD_CONSOLE_BASE HPM_UART2 +#define BOARD_CONSOLE_CLK_NAME clock_uart2 +#endif +#endif +#define BOARD_CONSOLE_BAUDRATE (115200UL) +#endif + +#define BOARD_FREEMASTER_UART_BASE HPM_UART0 +#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 +#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 + +/* sdm section */ +#define BOARD_SDM HPM_SDM +#define BOARD_SDM_IRQ IRQn_SDFM +#define BOARD_SDM_CHANNEL 3 +#define BOARD_SDM_TRGM HPM_TRGM3 +#define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_SDM_TRGM_GPTMR_CH 2 +#define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 +#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 + +/* lin section */ +#define BOARD_LIN HPM_LIN0 +#define BOARD_LIN_CLK_NAME clock_lin0 +#define BOARD_LIN_IRQ IRQn_LIN0 +#define BOARD_LIN_BAUDRATE (19200U) + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (16 * SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR2 +#define BOARD_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_PWM HPM_GPTMR2 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr2 + + +#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL +#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX +#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN + +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL +#define BOARD_LED_TOGGLE_RGB 1 + +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 + +/* pinmux section */ +#define USING_GPIO0_FOR_GPIOZ +#ifndef USING_GPIO0_FOR_GPIOZ +#define BOARD_APP_GPIO_CTRL HPM_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#else +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#endif + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI1 +#define BOARD_APP_SPI_CLK_NAME clock_spi1 +#define BOARD_APP_SPI_IRQ IRQn_SPI1 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PB02 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (1U) +#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) +#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) +#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) +#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 +#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 +#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 +#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 +#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT + +/* DAC section */ +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_DAC_CLOCK_NAME clock_dac0 + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN0 +#define BOARD_APP_CAN_IRQn IRQn_CAN0 + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR3) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +/* USB section */ +#define BOARD_USB0_ID_PORT (HPM_GPIO0) +#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC) +#define BOARD_USB0_ID_GPIO_PIN (23) + +/*BLDC pwm*/ + +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (15U) + +/*HALL define*/ + +#define BOARD_BLDC_HALL_BASE HPM_HALL0 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) + + + +/*QEI*/ + +#define BOARD_BLDC_QEI_BASE HPM_QEI0 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI0 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +/*Timer define*/ + +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (11U) +#define BOARD_BLDC_ADC_CH_V (9U) +#define BOARD_BLDC_ADC_CH_W (4U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A + +/*PLA*/ +#define BOARD_PLA_COUNTER HPM_PLA0 +#define BOARD_PLA_PWM_BASE HPM_PWM0 +#define BOARD_PLA_PWM_CLOCK_NAME clock_mot0 +#define BOARD_PLA_TRGM HPM_TRGM0 +#define BOARD_PLA_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) +#define BOARD_PLA_IN_TRG_NUM (TRGM_TRGOCFG_PLA_IN0) +#define BOARD_PLA_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLA0_OUT0) +#define BOARD_PLA_IO_TRG_NUM (TRGM_TRGOCFG_TRGM_OUT5) +#define BOARD_PLA_PWM_CMP (8U) +#define BOARD_PLA_PWM_CHN (8U) + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 + +/* APP HRPWM */ +#define BOARD_APP_HRPWM HPM_PWM1 +#define BOARD_APP_HRPWM_CLOCK_NAME clock_mot1 +#define BOARD_APP_HRPWM_OUT1 0 +#define BOARD_APP_HRPWM_OUT2 2 +#define BOARD_APP_HRPWM_TRGM HPM_TRGM1 + +#define BOARD_CPU_FREQ (480000000UL) + +/* LED */ +#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_R_GPIO_PIN 27 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_G_GPIO_PIN 1 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_B_GPIO_PIN 19 + +/* RGB LED Section */ +#define BOARD_RED_PWM_IRQ IRQn_PWM3 +#define BOARD_RED_PWM HPM_PWM3 +#define BOARD_RED_PWM_OUT 7 +#define BOARD_RED_PWM_CMP 8 +#define BOARD_RED_PWM_CMP_INITIAL_ZERO true +#define BOARD_RED_PWM_CLOCK_NAME clock_mot3 + +#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 +#define BOARD_GREEN_PWM HPM_PWM1 +#define BOARD_GREEN_PWM_OUT 1 +#define BOARD_GREEN_PWM_CMP 8 +#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 +#define BOARD_BLUE_PWM HPM_PWM0 +#define BOARD_BLUE_PWM_OUT 7 +#define BOARD_BLUE_PWM_CMP 8 +#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 + +#define BOARD_RGB_RED 0 +#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) +#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); + +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); + +void board_init_can(MCAN_Type *ptr); + +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +uint8_t board_get_led_gpio_off_level(void); +uint8_t board_get_led_pwm_off_level(void); +void board_init_led_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_init_rgb_pwm_pins(void); + +void board_led_write(uint8_t state); +void board_led_toggle(void); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + +uint32_t board_init_spi_clock(SPI_Type *ptr); + +uint32_t board_init_lin_clock(LIN_Type *ptr); + +uint32_t board_init_adc16_clock(ADC16_Type *ptr); + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); + +void board_init_adc16_pins(void); + +void board_init_dac_pins(DAC_Type *ptr); + +uint32_t board_init_can_clock(MCAN_Type *ptr); + +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint8_t board_get_usb_id_status(void); + + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); + +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); + +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +/* Initialize the UART clock */ +uint32_t board_init_uart_clock(UART_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg new file mode 100644 index 0000000000..a9bc40baae --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg @@ -0,0 +1,33 @@ +# Copyright 2023 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 0000000000..0aa1eed3da --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 8000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 0000000000..782edbcf50 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 0000000000..e2c01a2d78 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 0000000000..5d565c0ecc --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 0000000000..a9421a8387 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg new file mode 100644 index 0000000000..1db506d3cf --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg @@ -0,0 +1,61 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# + + +set _CHIP hpm6280 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +proc dmi_write {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc dmi_read {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc dmi_write_memory {addr value} { + dmi_write 0x39 ${addr} + dmi_write 0x3C ${value} +} + +proc dmi_read_memory {addr} { + set sbcs [expr { 0x100000 | [dmi_read 0x38] }] + dmi_write 0x38 ${sbcs} + dmi_write 0x39 ${addr} + set value [dmi_read 0x3C] + return ${value} +} + +proc release_core1 {} { + # set start point for core1 + dmi_write_memory 0xF4002C08 0x20012588 + + # set boot flag for core1 + dmi_write_memory 0xF4002C0C 0xC1BEF1A9 + + # release core1 + dmi_write_memory 0xF4002C00 0x1000 +} + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +$_TARGET1 configure -event examine-start { + release_core1 +} + +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET0 arp_poll + release_core1 +} + diff --git a/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg new file mode 100644 index 0000000000..24cbdeddd0 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg @@ -0,0 +1,13 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6280 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/hpm6200evk/board/fal_cfg.h b/bsp/hpmicro/hpm6200evk/board/fal_cfg.h new file mode 100644 index 0000000000..dbfd570fff --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/fal_cfg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6200evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6200evk/board/fal_flash_port.c new file mode 100644 index 0000000000..1ed9fdffd6 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/fal_flash_port.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-01-31 hpmicro Fix random crashing issue if the global interrupt is always enabled + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + + +#define FAL_ENTER_CRITICAL() do {\ + disable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_EXIT_CRITICAL() do {\ + enable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + s_flashcfg.device_info.clk_freq_for_non_read_cmd = 0U; + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld new file mode 100644 index 0000000000..2ab3b52bac --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,285 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 144K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = 64K + AXI_SRAM (wx) : ORIGIN = 0x01090000, LENGTH = 176K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + +} diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld new file mode 100644 index 0000000000..07055ad462 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,244 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x2000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x8000; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x10000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 96K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x90000, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x01084000, LENGTH = 224K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > DLM +} diff --git a/bsp/hpmicro/hpm6200evk/board/pinmux.c b/bsp/hpmicro/hpm6200evk/board/pinmux.c new file mode 100644 index 0000000000..3a6337faec --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.c @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2023 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06; + } else if (ptr == HPM_UART1) { + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART_TXD; + } else if (ptr == HPM_UART6) { + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_UART6_RXD; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART6_TXD; + } +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + /* I2C0 */ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_GPIO_B_22; + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23; + } else { + while (1) { + } + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_I2C0_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_I2C0_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB22].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB23].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else if (ptr == HPM_I2C3) { + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_I2C3_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_I2C3_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + while (1) { + } + } +} + +void init_sdm_pins(void) +{ + /* channel 3 */ + HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_SDM0_CLK_3; + HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_SDM0_DAT_3; +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + + /* Button */ +#ifdef USING_GPIO0_FOR_GPIOZ + HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02; +#endif +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SPI1_CSN; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_SPI2_CSN; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_GPIO_B_02; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_GPIO_C_22; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);; + } +} + +void init_pins(void) +{ + init_uart_pins(BOARD_CONSOLE_BASE); +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR2) { + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; + } +} + +void init_hall_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07; + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_TRGM0_P_08; +} + +void init_qei_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07; +} + +void init_butn_pins(void) +{ + /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */ + /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */ +} + +void init_acmp_pins(void) +{ + /* configure to CMP1_INN5 function */ + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* configure to ACMP_COMP_1 function */ + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_ACMP_COMP_1; +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_PWM0_P_5; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_PWM0_P_3; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_PWM0_P_1; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_PWM0_P_4; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_PWM0_P_2; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_PWM0_P_0; + } +} + +void init_hrpwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM1) { + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_PWM1_P_0; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_PWM1_P_2; + } +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_BUS:ADC0.INA1 */ + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.INA12/ADC1.INA8/ADC2.INA4 */ + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.INA13/ADC1.INA9/ADC2.INA5 */ + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.INA11/ADC1.INA7.ADC2.INA3 */ +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; + HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN0) { + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAN0_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAN0_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAN0_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + + HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = 0x10; + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = 0x810; + HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = 0x810; + } + if (ptr == HPM_MCAN3) { + HPM_IOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_CAN3_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_CAN3_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_CAN3_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + + HPM_IOC->PAD[IOC_PAD_PZ03].PAD_CTL = 0x10; + HPM_IOC->PAD[IOC_PAD_PZ04].PAD_CTL = 0x810; + HPM_IOC->PAD[IOC_PAD_PZ05].PAD_CTL = 0x810; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05; + } +} + +void init_clk_obs_pins(void) +{ + /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_GPIO_B_01; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_GPIO_A_27; +} + +void init_dac_pins(DAC_Type *ptr) +{ + if (ptr == HPM_DAC0) { + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC0.OUT */ + } else if (ptr == HPM_DAC1) { + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC1.OUT */ + } +} + +void init_trgmux_pins(uint32_t pin) +{ + /* all trgmux pin ALT_SELECT fixed to 16*/ + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); +} + +void init_pla_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_TRGM0_P_05; +} + +void init_lin_pins(LIN_Type *ptr) +{ + /** enable open drain and pull up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); + if (ptr == HPM_LIN0) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_LIN0_TXD; + HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_LIN0_RXD; + HPM_IOC->PAD[IOC_PAD_PA11].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_LIN0_TREN; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl; + } else if (ptr == HPM_LIN2) { + HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_LIN2_RXD; + HPM_IOC->PAD[IOC_PAD_PA07].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_LIN2_TXD; + HPM_IOC->PAD[IOC_PAD_PA06].PAD_CTL = pad_ctl; + /* missing TREN pin */ + } +} + +void init_led_pins_as_pwm(void) +{ + /* Blue */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM0_P_7; + /* Green */ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_PWM1_P_1; + /* Red */ + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM3_P_07; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h b/bsp/hpmicro/hpm6200evk/board/pinmux.h similarity index 58% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h rename to bsp/hpmicro/hpm6200evk/board/pinmux.h index f772a0fc31..bd75fed427 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2022 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,16 +7,12 @@ #ifndef HPM_PINMUX_H #define HPM_PINMUX_H -#include "hpm_soc.h" #ifdef __cplusplus extern "C" { #endif void init_uart_pins(UART_Type *ptr); -void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); -void init_cap_pins(void); -void init_sdram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); @@ -24,30 +20,23 @@ void init_pins(void); void init_gptmr_pins(GPTMR_Type *ptr); void init_hall_trgm_pins(void); void init_qei_trgm_pins(void); -void init_i2s_pins(I2S_Type *ptr); -void init_dao_pins(void); -void init_pdm_pins(void); -void init_vad_pins(void); -void init_cam_pins(CAM_Type *ptr); -void init_fpga_power_pins(void); void init_butn_pins(void); void init_acmp_pins(void); -void init_enet_pins(ENET_Type *ptr); void init_pwm_pins(PWM_Type *ptr); +void init_hrpwm_pins(PWM_Type *ptr); void init_adc_pins(void); -void init_usb_pins(USB_Type *ptr); -void init_can_pins(CAN_Type *ptr); -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); -void init_adc12_pins(void); -void init_adc16_pins(void); +void init_dac_pins(DAC_Type *ptr); +void init_usb_pins(void); +void init_can_pins(MCAN_Type *ptr); void init_adc_bldc_pins(void); - +void init_rgb_pwm_pins(void); void init_i2c_pins_as_gpio(I2C_Type *ptr); - -void init_beep_pwm_pins(void); -void init_led_pins_as_pwm(void); void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); void init_trgmux_pins(uint32_t pin); +void init_pla_pins(void); +void init_lin_pins(LIN_Type *ptr); +void init_sdm_pins(void); #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm6200evk/board/rtt_board.c b/bsp/hpmicro/hpm6200evk/board/rtt_board.c new file mode 100644 index 0000000000..d4d344287a --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/rtt_board.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_mchtmr_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_manager.h" + +void os_tick_config(void); + +extern int rt_hw_uart_init(void); + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_manager_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void app_led_write(uint32_t index, bool state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + + +void BOARD_LED_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + + enable_mchtmr_irq(); +} + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_HOT &= ~(1UL << 31); + HPM_PPOR->RESET_COLD |= (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm6200evk/board/rtt_board.h b/bsp/hpmicro/hpm6200evk/board/rtt_board.h new file mode 100644 index 0000000000..f0dc3974ce --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/rtt_board.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include + +/* gpio section */ +#define APP_LED0_PIN_NUM GET_PIN(B, 19) +#define APP_LED_ON (1) +#define APP_LED_OFF (0) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* CAN section */ +#define BOARD_CAN_NAME "can0" + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6200evk/figures/board.png b/bsp/hpmicro/hpm6200evk/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..a59ddca974409f4597e4682da9dfb5dbf15877a1 GIT binary patch literal 596514 zcmV)=K!m@EP)UM{_{f{{MpRoOl?Z6HPfo(v58f-KGJxELvAPJ!Xm1C&2 znR_q)kl!o(e!B18Z#bD}=iY0twf2#hU-?c%sH%vN6p;`TRF^JpFco1?jG&MpLd8z6 zj0hF+fS>~^N)SK-oDPbLhP#LW5P&%SBPjw=?EpcAm@@=jAaoH?2B|SFN!3IoI>Z_& zgfbuusEEMB1*(dOP>G-*K$su^01AXqph2jJdlywu7|aSH03i?%h=3&3K!PL$LVIAt(Zf1V~bZ45+F{ z*#B?m1WJU6jQ2tiBmgC#IzC-U6$!!kHX#KRQ6T{YX{zHs5)4rg1Vt5u0wf7nH3p#y zp!cpS*|d4^^nnrxQ6*teh%B40#K3eHK!6mfsP#)h$BQK2o)sN z)|*+9Q>ciKFAYLP6#yavPwtJ15JHBkV(hHwDbOO+3}kmVH9q;Rj_m?Z!4HV&*i3+; z!eB&TL^V%$M<8T~Dubu%21uG&M34}Hszy-cbk_tRL`T7(CK zB1vuRU6A7f#y*gIYYieQb+A)iU|mgSTZwr$7ut{#e}K;{U)BW2oNNR zv5s*d+|6v9cvS-kP*uGAL~tAhGmQukAOfdbXye7;TbW#h z0#iH1B&e$D;S8Sg9YVw+x~ee7xf@~4lv8*R^k7LA9Op|SM(9HX5UQGpx`(O)jBpVf zyFi9}H&Zhkr$ZGGp-0Mz3<&_}>|_Ay-cvGAgA_2Li-$8aQ6^35zqliW)ZBd_lT5DP28i`noALgyN`gJ=Q$z*jNVt%s-$d| z!bBh@f?)R^E_0oa_1N7@O37@Rim5?mWR=7502=A5b+Me3Mo4!zNK%s`-ur&H7t>@Z zrKGB@H8abljMM570OxrrrR1Ces3aiho^w7dwbq`eVyb4AvNAxT^&al3R!Vm7t#uKI zP$Z2LU0e0;rYV;U#?qQ;TIRXdrL5Mi)>`XWf_pWyGEK+BA?HGhyO)#?^Fa;SvZ%J& zbIv5)z4z98PiDzy1U(=s!AL?X!UJj=IDORVBvVDYI|W@#zyuQJ z5fsz$aUzHy;6iv47)Vi!aw9N`jLMxL>KyokbRZEyGDs7uQh^A7M7X;rP2n2C5P&cO zX3j=}7$pz@6*7)32@`!%k_mzkkfO?P4I-(D3dWm-LaO!dX6o)8_7?JR1R+4ED2dJ( zKuEwC>6;=03W^c%2stgAs>ahne+xT_gGvby{^ULdNhl(L1R5JKP@=kriViF$!A^>* zcZz@_-GgM#5;3+wRI^7X`1eIwNJ=;X^%&K2Ty{VQZUL!dNf3rd3>+FEmO%9&C=eNo z5D}H+?j8=c#d}K0N$*`$N68e?03{>_l%dL;SnJ~76!+*0@2MBsx4w9 zYZYZM$nIe|jl#KjPin#N?j>geZknN^qNomFN4IiHHt=b6Lr!VKqyqzRMY{T3W7$6s%np*syavgPV|5&MKXkf z9>Jif4crhQAW9_5Bs&8P6N!ja3S*#KsEQb;Rq}Al0a%e3*o)NGBPAQfAlV22oI*%N z%QlH1qE94X0~Ha$fpkS2q9miJMqu2g6Y3QSAE)aCxI~1A9$}(L!ibc!d#IQQj`N}R zDgrXpnNyA$OFbmh*4Rx7G#*t!*(gvs9OPsq=QdR*_zp2=`t~N+fHmW(Fc9YoLS* zWAP<`B$h;jNUOD_(p&F6d^9(7%UQwJnJjznwbi<`X(}n_X(}ERNL`NmFmnc8xJ1;T zfyIe#;XufM5TOvdLdg>>8C^?6h?$&_Jt>MHBLKwc-AB&>I4LRy4FSVV5<$X+3P?wz zs0M_fz%k0L00=OP0tf^UN(rb89tg@nARJT-3>BsZ8HmXO0YOAa2vjAgDnW-(puM@8 zIXs9dR_0tfB{Hw;FvO{T5AMznFeM8EKER>?&=Y|pqkY#1ALwnA2d6Va z#6a5M7!Z8YdV2V1+e{QhM~GO`>>idBjP5RgBw>WYL=;LRV<31lh9@&o>-6ryU`d5^ z5vBW}bpjzY0E7!EFn~b>!$eG#B0<^{b`1=LikPFTh+;%Bpmc{qsbqA8Vep%PA~_up zRi#s*aZ3IKp{Ae=+M`8NRi5sMi6B}}Dh@*6?4aaSTCYh5^(f9zn27}>*yti6$7MfF zMMPAT42486>pkVHBCWRhIGbsJt+r&z zooW!^IM0BToJe{^PFWS<;StO6xL&W!3{M!y`B)#5z(qQ@8Q&BP!&;ANkK_!5W<9lWG2C6hLGMHBSw3##L^qXRSkrhMU2kS1qMNn zPJcq!+lf}~-a$#4R0WC%ASe(D&1^J#;SRvWx;qpnfIf(3QlKKBgsPCIJZ>TkS2KX? z^{OsiL^O$lQz}=lU;W9S`0*eAkr$R_X|<|Q5c2Y?uXQj(Vq7Mnst_`s2ofS8P`Zqk z`NXq6p^IfO4^9b(5IXQqAXH??Na1c2RgG{egitjHfgncZ)9|JgP`bq6yt7(o*ooAJ z02C*Tq!NS#oD4B*-X%1NghI`V86rRpkSZrILkNg)K*#$Ta5@w+cnlQ}hKC@9kgCN@ ziQZk4K*X1YqJtMzs!M1|N`N5(QLsA#NXmdI7%rkTRoLK8y!YyEsSHg>Mx7BA2~kn8 zARrN~r<5FoyNCiBgExv00i*yV-NdLtKq2TpAcKho3851plWO;#%ub?}iE5&gprz!! ztB8p8UdQ2Kz!{{w$23i~RnugeOeN(M5fQFt-Q%#-sjQ0G((2NCHWR2OHQ}jFM|e09 z0wp0Z9eRN(!`&n2JOE`xB(qu0L zEMjUhFGmJj@6jE?vfZ@foUITcL{1ijh|KfRQi>k6Ejj1fIviAvUf(RWwnT)bB*E^z zOr_Qy;S5@`oU^LsoIAYL-fPdLnAyeS3m{T1VrnAZPB^diK20kT)HZkT3QL1WIUR4a zluOC(jf`HK2&Oy*XeF`7yi_v;`*FXhrFl8Dy5w90P}Q7MwAde)AtDAD&Xf{N43bOn zh@7VIW~QPz%yUv(uU55HIzk zVl{1LoU|ba^VC9ncT)+HU|U-Et|F4P&2`GFG?j>+Qbw@HIA}QT4^&Zs_mRn2>mp*w zQg^qcB+YV!yE}s=m)aJns90-VRgTN-wTX&|HTKQ45z4$A%u?@to|kD=mU*tN=afA9 z=#>xqqnfPOtKLT9s;iO#Rgrl)LR6u>bu%GYdpC^Z3=?Us*Iqa4Rnn<>Z~dsE$HStk zREp`ktQcdJ(QC|eONjwwP0sM%ha^>7n>H(fE=v<~y)GWCbM@|`>fTL7#7Zfeuq@Sk z%*)(+T}>NPO{JKn>@05^5<60v=8-97r zYmyv5rBethh^5uCnv|wVd-HHtF+yD3oheQAc!04rpVF$eI;|#9EQx5od+(`~1P^jyGvDoo>U|gL(m#za$^U@LI(W6@Cr~)CW0q2?CEDg3%4O| zlcdK;W+DMm9Vkmehul0^dGQ#+ivR)AovJC=g)}PU)K;o0Bl=K5L_I`>D#D09_zeNV z0Z0o zY}cFKB03;QQrx4Y0??gm`EZ!cKyP$6MMSjT$}|mp0Eh%BbeG<{s9KsxwX_`ehovrM zwJ9lE(q&nex?Emdw%X6HoL#wcew^pyVQHx^b8rZ0K16=DZpN?7SR(X%OkXLtvI` zTU4y%yx$)J0m7q~GWF!5)_8k?GM~~amA3S&<(6Y+QGPiljmOb3moLCM=F;$31FS*n< z&)!#gLV$?PW(|*JKGxbA!&|$0el>)(wyBi)a2$?+*866?o>r@+&+WLRRQB_6Ri^b+ zb{CgDIQtwuHq*wE9F7MDRTHx2ln~fGz97)u=X%U3PpRxKF4yacip%}ZEEzP&GL_bQ zPC4f+fFahb);dlNGy#dMx)YZZh;=v{;etX2~lA-dn~x7)3|i%47M-g_#= zBSbW5^4{j9Zr1DG+q9YH$VFd&`yNJuDdjEe0x{paelt z<*=2I80u2asV*%g8%7HEP7Z+;fb_QHl#`iKdatV1!QrN8y~$8=PsorasrL%7hp0)9 zZlWn=4G9GxNv-wf3{jLc4f$5poH5KCJ-oG+EnzoT@5zi#f74S+07W&a4RSq6T7|ED)V7>%9X2Ej>n5JH{iJ1UwcWUV>mUBi&pr2!XCvY_Kk-|C@~3}#b=qXp2=BcsL6O$kd(CD5EbE9| z5urjYC1?nd$)LFR-dkr*i7M;$c6jjU6cx2WJqJliM#k_SKm;muno10M|0J@DnbKo4 zKXKx-2b=I#)192mxp;Izf^>lf3Dt!#)fORC3LrK}6A`#eb&7-{qIVI4a=$ERXIJ*e z`QLy3PyWHb`fm=)vDH}>X)FOMT?mG$79?`GCx)-khwH+H5w4?AIr;yL!wJEWR0QPk z$=b;y3XmEA7(-Bb(u8Y=h(Z{Qj^UNnKxohu!JwTC0hD2Zae)vF1{C40mZJ5XQchAz znO3VW{q)S8hy?v)G^Ke1#4|9;=9?sQv)4kTZxchdsQ5|hMG^N)1#pSLy*OdiQ zSzp<%*WY>dwbe8o4~GX2ANAI6-MY2jOzX2vo$E=50}y>GN@q!ljMX$PbJeUlS*w*1 zJ>t>jPEwkeHcgwe^Q+w>rF1y#_s3;-*iX4E$72MadB;08tLYnm_u?=v+_-V`u-`Ao z!?Y^<{a($koS%!Lx87Q##BslroMGB~6JWd9>~}jeF}2=$N(Qj?x>>KoyO}CvIAh2# zlir-EjF5fw_;RUBF4JaO3ADr4>-Bs%UOc+k&->eVZs%Oyynnxxa(1@;&a1EAy>ss) zKk_4={mf@S{Wo8^dE@qawF+QfmI$AZ`(#N(Q?i^=j}Azy%`6?~gNm4G$&(t6^Fo*7 zyzf0kL`}`C1xf5KFUl%`%HUM8N(#nivsOtLmyey&dUWp*EvIB@Qc-vB-XVcdHFfvH z;jmtrPjOUlyh27(`voCJnW9U!|`yu za^<}B4k!bU_m8Ji*3-7N1|byD!h2tBH{NR!h1gP;GNq|Z4<9_9m*x7+8}8lRg~A{d zIVJC>x>!o_As{lk1|jZTmD~=Cnygl<2za==M}$bIsK{`AVu)_7)d-SdB{6~lQ;DFO zg~zaToRnfs47a3D^khP&i+yD@vl7Am{z2~^!jzIya6F2j<9;kE~&KRhe+Tg!e5Ka`5S*9MnHTT}lQd+G@Cd;>P z-dwL%_aEG^y+?$%mZr(O2bt3_W@@;fO>2_1w{Tk>_>)odM>#wt-7-_oR_;xsGM)lhTOd@bDqjaUwDD& zfAz&L%*Ug*Mm3W$)G=!;zFZ($%4NNtrYWhUq`9L9U639^L;Zzc_|Kky{`*Qv ztv15G`Qo=9UhGQA>+Sg;{?Whx)E|B310Vdr3m^T_U;DNHYro(B;y?PYHrw;VvZzQY z`-gx0$$$I%Z+rTgTeoif>aYGEufG1>&E}jD&prG7&ph+&@BH@fQiQ6% z{EPqe_1C`p`@jFG)l^=2_2up6ET^gU#(-+}U_dm{B=sTs2SlQIs3{5Q;oc=#XE1_` zd+S%Oo!`6nHc=k-`v(sm0ECLs=3`AsMJ0S7Yy^VD=(ItBk0F~bVgs891Ax1Ow3K?M z2*N}Oh!0DlySpFFvPV}zJ9+zDOubi7htx|K%jyxqr~!pIJef_Zj8LdcBCssW=Rg1X z4}IW$@A<)ZJ)Dmeq==Ju5+~=a_|Pmw1kMOR903L#Lrf+RfT#h`pgIvqhr@0WP%U@%d0rx5Ilun{?|bgK=Rf_2 zpZnTNe|qQ6&D*zbee>`B?&`IxPru{oZ+!h5wa$O`7k{QIt%sE?rp40M5`2*edemhW z1j$^awwBW>B}pYWCWb8GOY`nL&h6H%TOa=D3t#=>mmgp5KKjCk?>~I}+AFX8_)q=R zv(G*EJD>RECqMabpSpAR-c$El>zBL7KmYSTb8O%F^dI~IJ+5548gzyykvcb+nJF2` z#_RyW$eN;e%d#wsL7d1*Qc_V>NQ~|+Cjvc`P6jpQhCoC#9OvC;dp;i)4{kTBkpABH zzIV0W%=5h3tlsw2(|`S!Uw-kWmw)Uhe&YPf)mOgr#&=$QL$c{GrHYU70To%6W!Ssa z>^SdLZM~kt-2;c?akD-P(#9MF#Dgj#s-xjG)BW*4x>*uJH7WGXHy^u456@bL2Q!&g zH1~PXEFlaDf+xSbS!>?B1{sXV9s-2b%cF`QmhNsT<+2`qcIyq#(&kvevF@x#T2fsl@Q!3Wbu@K!;cW zDoF^-le0!dkFH`#!|9ZW=q8BhDVujkKY4%5(o!qHI;lp;ig z3#3;BX~{g;YOUV&G?_3=-hvntgv>dwQn94TZ0UWF)qSqD_ZFR4WLc6*1Yf`ZMn~kq zxvM5KIm{wLdTk9*LUOj&`pFYMq+5sxYHzBVhnciY^L$WXTCJ-u^I;h|S=DkjB2-k9 z5n9Aj&WkVEER{*2cADc9B!m0K?johsmU?+SZnxW%%)8IWxl9uyirK~G2u>X*Or^>4m>|I?rSi^{9h_RgU86-va?eQ*$TjxiiSdpJZPihv`A-Nxw% zno6?Ndatei>wo>npZM+HxP9lTWuD7))qk_<-hsb&;HEMeEpl>OqP0W zKm6ej-GBJz*_EreZ{L0O_1B(y>Zzxnd-iYs_HV!Pw_k(8z$=?8huDp=7u6$NBPdKgJRfahezcp@J3&go%otW=93^@ujB`2DV{? z6&o6`3Wcsd{^-LaC?*m9#QJyg#Yd3vx7s*^QX@h?R1c{ele(4Ke_`*vsy(AL%AG~SF*qtzutkPBMrdaoW@nD(fg%C^I-m@hY z(h;gDI`7?k>c;hJb)IuE_IkG2-nwz~YhU`xotw9=U%CG9{{5f)*vDRc}8j&%4y8$&%1957o&=!A$1X(}FO z*2h>9#apY>k*L9rCoqk0vYm!l;m!_Yc=pe@=n zET_rTG{jWR6wun*;D`3dU4(){xQY#P4-vvxucu^rD%QQjw6;z{EDdX`_b!28Xp&$o z>?!B-D_aG!B|-QEQSH&qc{$f>*YD2ra{vAtDW#mUC14B?iEOs(RZ>t%i)bLtQV5Q< zUAua<*4A2W`y-NNGpbtA^|WeUubp4@HiBOWIHPyJdE@5YyLaFC-uD1*R+}*ZpQm#B z&g}_R7}vLANTuA*lJ}!O4&WG zUB9Y1T|eI*mbphxXmSL$p(od=8Gf` zSJVE#_{Tr_kq^CaGe)s?R zgHL~cw-hP2lBFrzr0QTp4+VG{4>ZeTK!kKsM2!&uO%p+P&_hfgK76!a4vTwt|GoeB z57w&-KV(Kll01l~wuhM?Sn-ud^kH zh$Uw{zPud3<;53YymNQGJ-f0j^W5rx`VW8RcYp8qe&Aj2`o&-RrGN8p{`-&r%C9_r z@bFWg{?vS&-}k=vs>)Zs@|E+=Hl-8+j~G)t03!TkGa(5u{FEi44{lC`lj3mL_vqh# z`K4F><9|5L^Y!c3wpXq!^SsQ>%rrvP*g?8ddiNkj#>m@~u|tHV60J+N)|)}IScrJ^ zXiTCi;s|#Up!WcvW+y8moZU^d3mKkMaSsaET|{df#sHw%lX*r2*ov7mT60tNDMYmU z$%R9R0qOLZ0D(}FSTM#zJwW%su*Z-#W`Bq=;fgV*2Qfwm2o0Xb83PhyBgf)J6W-FE zXh{U)Spwmz0#zas%)=c{5rd0Jco#w~1$vOrm?ZoD_q=a= zc71OC&S$^xTQ9zL?dqLiJ}iBIsQX$U9FEs--^uCx(WCF4T{$n3obbdHb6OrmPX6^FQ!?Pe1?sJD1kq_};@m|MS24_P4+L*I#{^(^Iy-l2tX8#l0eit^K*@-}$G1 z`Nigb_2!L-7mq2JyYF^~);;HZd3pK5M_>5yAN#RyeEl1r{q!G}yoQ({O(mD2A%I#E zXv)1+6H7^KxTr+LHOYkVh`ld+=W=$ozIx+YHobD?YR-uaI&1H>`hzzgJh-^1w6eaF zrfVTyR8U(8!}`VJ2Ef!L*>C*TZ@l=@D>)@FcDv*E?%%JiK78D0L=ZqOCCO}6f z2b?TcmNw7JY&0=Z!TI*g9TcwVmUDtE^L%xCWqZEu@a`Rud0tFpwO*ZVHtey~ zBSV{afZl7)D^R9YS+6H8xwqDKvt(I%(`a1~b6sj{b4zMAnM4;#?*WY(xN-gZv(LWc z@x^X`IPQ15I@k4Pb?w^u)oa%tJ$&@qYp>n7apQ2T5fKuONNVe{e)gGnJpJ~kE$8{T zm?FdIVXItY{_5Ah`rVhlrz8-|a->itCABh5Z-4f=5C6yuuYdRT%iT_ZJ9qEoGR=qm zVSo6`FaG71zVz3(Zf%k#1anHY)qou4`lBEF(GP#*Bds+%&2q!kD7gQ|8=v^Z{~a~5 zr3FoeX0lCZt+n$TH$V8{4}Jd+{$R9zJRELZzdlV9Aj|Ri^{;>9Q=j^M?^O*Zs+yo6 z`jn>Q;qa3`|8wtt_q+Sjx7)2I6%kFT*ZOzg`1=3$zyInbuw89LBzluK@Z~Rk`FDQ%6Vobhx0}sW7;Fv?fBg88f*=0y3-|8cG3a)? zCA~&0$0e)&)^Gpj7r*f5_wL^F?x#n{KuLMMzy9ny-tm3k|HHR#-Ogo7YR)zu8M3?F z{fB?|AHVXIFK;&Ml(Om=%|`FBpO4Qx^Y$Nn*Sl`sy<04sW-5d2csM-1xcKsy{_1bO z{N+2hZ!5Ics+zXz&0)WPaPjzkA9(){z5j#j^=flvdwE=nq;)QDzIp$$?Z5uFUwi$P z*NkYj?&l?dP`|vmymsa4PyN`(-t`aO^~|$xzq-D9etzD2A5L?g3a|knJ^KI0(|d+l zc3yS9YpwTvcRHa?rS7ikoD^C)S&}8$l7nnt2MkUFIKU8mJz&6KxI>s>X6~ICF3$`e z=E8;HVz3Pc3mm|fEoVtq&fSWw4%N9UoC+uI@P@VShh3sR)TestIdz^>d%t_F|Nr;1 zj4I9AWw{3Se5WbbU32MAe()`=_LkvL@}d}wt)O_e1ju2t?k-AuYFKos)r>Y%%V^ciw6-DW&sQaH9OX%nQLZF-M2zE=w0<% z(hF*sPzWAG0Rao6f&f5(tQ3Ht(%#$pqN@Qz2&7c-9#9big?h@vE{G;2QojNqO;KuC zScJW>77&G0=j{nVNW2I#A`&A8snKT`HUS#}MTvkyL?8)nlduvP71i$p)HAsn=UXYUD~pL=#t&H-h9oD?X%OA_dmbf?W?E}CB`UZzz}4j-OiE>kY0H4g@rR0jER8gy6dmsI=8Fc*|Ko*?7>S9 z?%c7f-|ty#2{4Z1qAY^*q?FNyh2uDGwI{~KXfPVZs2ztoQb?#d04W&s`$)tH0Avgy z0wEcU4{@VH8DCWZLZsYwc(}URml^r3KF}xYCze>o|@{={SmJx6CvfP45E$ zI$Jdx4QpL#UDilfmX_8x*2~HU7g&i>1^|>sqs`>h^r1tCg7@gX(#mMVKClQ&c=gp+ zFPu9Mii)COmL!QuDa%1Cedy4k9Xoa+N~EJYI#AhCD}zEWy!7JBue=nYHVqTfh7Znp zk4nvMnZ4%fYv$(WNl_9TqqNrAI`6$_;je!6E8V5l%p@*&AP``TqS-Cm=H}-vz2sn) zWvEDLrAS34Qlvn_nbW5qc<}zp1{SI3D=|Cqq1Ri_vgEcq->`Mdw#-C2jR8ZdjJ2K+ z9)94#XP$lrO>Aw&9O`qXQrf#}xhyWb?D8wGx>gwzHxi9Vg08A;RXz6juV!V82Ww0_DZ1k(D%o>d#ffz*`OHt&@ z-Lh%d_(C>G< z-N|-~1cQW4=pw>!I2;xEH}3uB#(J;SXr4WPj)>AE2_Z~$CSH2}MPxME6lH~=7)2@% zNQhxHEbjTzm*%(c;2=>P5lRptQF$?3IDR713M}`_zRl9a#8qXTI7N8j+=VaS^AFp$ z&Wb=j&ZEdsWCXwfo<4c9nIwb$hSre?+A1imkjOg!;)^exJ%6s&ZBIjLTFj^Ny-fU%gJ|1igTFu7dxr+d# zB7=ZyxS@5VP4wgwPd@kTv)1`2N%B#iCP|iMd1b3|C_$1WQ7Qs}&1$_smZsxz{*7;b zGkojoH{blaPyNy-MZ|mY-Xj3jDP0bPpeZT9>yTq$l9j8kocY+t-oI=6{@(guNv0SO@p5Y=QP_FOlmH&0a*P*L3|cESXzu6{Dt zTvN0hkO_&L^8oC;)=0n-td|;k3ZQFDs;a4Rn~4!5Bu1%Q%Jsen0hpz37%I>x0#c{; zkWdM8O&ee)#JYAxHCang5U|EF*1xU(K%mqJ3Y6eC1N*RvrD6&A8mUGEf)7MGFc8#e zt<97Q2zc+SqH3fKSIKx(ASs1B=v_Fld-hj9{l5btj5lm|#fN~}2?&UeOnT!RZke2& z`?tUI$Ca>B+PjcLd1m3rv7@h!MuWY3_BGHg_m>;6|2=QJ)dN2Ny@w<2Kk?uV!4Zwl^w)fjv{*D^+@CX6xMi_M2`p?|R4EUwL)mv!DC&iF0F$=i=rh zhOw(`zdslk{-H;nur>sSeS7!baQ%${R8{uI8*h5^Ti)cXx7IB#FWqy`-xqnF#tDNo znys>`B=Bg|pX^M(?d^AO+d8ilX{~F7tF0`cI(huW;pboUY>hEQng}Xu6;fGMQ!_Jn z-TB6exlWoS5`+YV5Mr238!x|f^!%yQ2ow-Fcu}YjgFtC*v)z2pJKvS082~n0jUbZ7 zal$Yh504&ywY$6$h=>t1pwzoTw!u5=eHFHC-Kvdpt_(it$mF)_E-fE@;bmt_ZH(5N zq#Pkt`O;N(eQoWA>uylmSnq0vtWxB?Us>rMKekYgbFIZ>S@52;LLf$2IJGbw4EOIp z2*65FKF<3aJ%-S1bSgJGvv5|xJE)X`00@YyWzI+^P8@&iiN|IqXMj*gdN>>wd4T|t zQn{^)Vw7dAEJ=J|v3|sY05-Vw-ulA=kt3N%RPbWGQyP;< zi}$hC!=m`sx4z*(>eDX~CXrTPs;UAG3@{oEl}-djB@v3WniJL*7tUQcckW^pobx;$ z3^ZcaX{K>xKrw-)$VA2m6@)bquvbc_&6fB4$iojm^zg$~UfHTdMM)#os1=ckqDHg9 zfkh-pASCb@d_{o${_uz2{eed_M`7nhwlV@xASn^}}ZQ5vNvRF$l?LJZ&C#C#FhQ-v7e~ilSWYc9}5C z8d(~rQKTc9otlnR+^0t2u);k z0P)J!!)GBPnwo0oMS0@*@v^Me*49D@pv}xwr;()1EFncG;F*C9pb*6(RfL#MOpHpq zwti~R8y-FSG7B@|WM`_=XwA+}E3H|Sc;q@wpo9!XNJ{IxEXVn%yS_RcjWp_Jqmisf zovF!*&ZGjwsHsiL#EMV}3Nk8~kTwKwqUhyg$1tD-w{?DQX3JJ14HIe7u>g4v%wQC- zco3bWI%rkd@{xxg`HABn~1f6prG!&7-?vy!z@Z`}XZ! zS?NwrPWr(A_>cei*yE4g{g$_F-Lm!T|NM3Ke)s$iLUPu{NqobNH(#>%(y#o}SG2BK zZP4yCMS^qwz=2Cvx+{P8#lI!eAOFRV@7}v7|5o|K2Y&R1*WY$xVZp@lc$|+0gW49yyZF6QBYE(bY7N0AWq_{6u$}Q-2AHHq7v%+ za}75a0D@5C%(xz8)>tfGzw0##ML>kaGZHZf2oO+R@k1imy!nH3-WXG#ngIZ%UWKaw zObAjZPl!as2T>r#VEuuw3+-i5tt_t@ZEBv8rut`V_7N!nuBmc>fklkevy-~PgThj` zfNF4U%}=vcsgM|i6cAxi=30@`T38U7MVMJDLI4KN^E^qC5ExJ+VO8c)9K+@iWfNbA z5M;AmRD-us#DWN;)Ko5zu!-7bL=4`Q!I!OO+}l{%dtlf6mV+Pt*av`kw+S^0?rUUGPlCXQ%w#%-)yjovWfD;p0Z)2msIuMlEEn7Ox*6Ql| z%9&Hw-F)zm{@d^T?tlKmu#A#MYkqpty6T7b-+$X}cYvb9M~-;!ckS9eH8peb!o>?` z&u^KYIlp-E(MKPfXtlb_%X{}9=yW;@Cl=0Myhuodq>Waj5lAbP;6=c*6JcObFpkZ} z!Aqxp{5>DJ{<>?6!WMZo9$A!76F~(@1lY1h3L?n9a#kP!LYAdhUb*N0{qsNg>Q}z? zz{AhK^y<-x>A5Iv-h1CSgBKu5(m0CZrKP2>|MNGJEDaoX?by+5HoyM$uRr|oqrJg^ z2oWiW4Z)4ZBM@XjLbbHA@|S=0*ICxcveb$n42GR%3s{PxD2hBu8l*H^6~uckYle;1 zdShkvi=Y47MyqKe(_7yNJ|t;Eo1GM$B@JN^AY+UJXM@$CvN-X1_4&_!wiFg$QwBwA z<6Tg(ij#Pv+14i2paKK|5N6UUB87|({NVnoDsopi??k|P*Uqwbqt$G-bevUzgNG0( zNbsS|Ox%ncE32#b-uw05pcogqj#N!4Nz$~_?j$CQ8!bjbij)aT2?8;CZ)tgD<=nXo z<9sw8j}Q?B<5`MLQ<*08Q> zx7%@)T87*@#jKTRrQ)DP8*6PC4#(rsXfzaI7B@S+6(K~5yelgh0G1I_G32DZg<=yB zlQ>eMGox27uB{IGt}2sA?b)_7Nz&5gS{p4s6pNJ|vO-YpG@HzlSfyFzS*mJddBp*< zQq4$rCZ-8O;Vh!D)kfZ5j58>Gs#TI@%`{FVA(KYyYa2s1be=IVD%Y8v1YPq}Ad~~= zDrR9YjjRC*0V&N=W?{!ht6YM2K8>>J>5d3%WqehQsudZDGooy0bvkj}V5P11lby-I zaBQ+TB5KBICL+3FNJss_KoA3g5HuPMAjqp? zJYG-YVqjU&1osVs^)tqQGM#A+~USL#~{c&CjhgQ}! zs>O^7KqDqfKl9YnN?{xu7d$FZgjyjmpa-o$Y_HWQKK-drT>HAKSI%Fsl@Ne2z)S*~ z#Y2soWJX{l@e+t?pfQEON-24*zotk53lRoHlFg2Y(kfKWJGW!!&Q_zfaO%ucho5=fEjPdO9q$NRmseL; z|MbuP#8q}`YKqzS`hBD0pZU3;zv7C^UwHn7w2^)M7e78RG4Z|cfA8g2UTI_v#L(@o z9(nFXSA{r=G{7TIKQp#gk-zu5_uX{ub&)X-J@W8WXY!|h`lkoIjc1K2S7y(EWijVY)TpcQ3(pyv0to#jQ}FdT*tO*%q-RvNI+yzpu|gHk3>ps!sR%i z(nbVoh*=%lC9DH>xcSYoV+H^pHqTQ4pn+Ks1J;@G`b7y!P#y(XFo*zwdd)*50rOlWkkw8Q%z13`Pn^H!TlvOz%ZWuLX zqS%E10z_Ks>OBGyLST^qfC|yGLju(qwM)0nhR@&o#9Lo?+l^OWRk`ZK ziDS<__v|D(Cb605G|w+z z6cnRl2w{G9rqyl_%F>lNx-#bw7!V}MGVdKRB-;2W-qD&`UG9#nJcys!Iy*Bn!TC`gi4trt;5StHX%*Z**~teROvI)v`eijLty5@{sYzo9 zF;Yq;X_AzsA{dW`m8*8nZ_DCzd3l+F)9mtLudO3Qw!s96jEY#mBq?i-BPxm!2Oz-N znaM~;<6d{`Y;$%?xxRYx*6Z)wSi>itUg(FWQm82cWm@faSyqKBE0Ex;ExYH3y>V

92P$KRB~z=k#dINZBJ# zJuND3w(`dB3cX>WU9KY|Kx6N)0;0eN_3%SS`(qmQN1}j|1Q>}7MpRb0YBeW2 zlY`-)9FKO)PJHU$e9Y&k*D1wCKT!on~_V z{J?RML;JALMi_aRNwjlsIoRN35nrz6VC(XQ?KcYf^? zYfEP++40@S&ffcj=T)i_W%8nMRaIkLL?9oJBW(Zzdrl1g?9aV_+oVd8*2L_#Kl`hD zo;iG`ZDv)Z$K!EcmQif9R^xK)z4zWlN;@B_YJAtNyAJH%(e1e+gu_pt8jK2vaO|pl zT%bT}qFGkOcr3WUg9gn=@#j_v$&|8;Qd!PT(16#N4A`;J_Gzp^;sM{ieYh4-(X{;qi zK%~T1l~H))@Uzc6{Y(}7XjGg#fBw|Mxn`D)hNG44;`G#%bsQ9CS$6E$$us9JL`FYw z|AWsz|NQFeN@4B2-}ojXJaPEhR-+XHXdRtCb#meONeL_unCbR60zH)Tb z?@vrjj7Q^dedpT`-2cPzcwCOhLAa4L1%SB@m@5Dvz#yA}P9gBY*XR41_Y))p4hl55 zpcorji>R9yw%KYJ6C;ujV-9sbuYSq`6he@&2{A|96n-Jp-DyBX2+V>E%m8(;?={LC z0Fh=1inQ?NK|IvLAZD$V_b%Add1vCd-7srw-C=*Rne5CAR=)Jk z+Oi8#Y)BLFT5oy0(Qica3Y|8zw7e+gs;;sqOEaBZJo_pOv4bdS+R~yJR7L~{(Tk_#XcT^RXB~&KS!cvwcfG{usSZfL6 z$*F^vUVkH+5}*vdK~*@6CW-S_yAdgqWNA6BOk?8siDMgsvXM2M%Y(C#(t^Ygn^>)H zj3jt8Q}6%KPaV4QiZiFqEuTN}Qy+Ny-+uXf zt;CGS<9q(`p1bdU+ners(~o}e!)va*deB>6URt(Qb$03EflDu$+cq~dGu>!s{o$b9 zYTj_&)kj}^xtTRCzx2|_9(*v(8jUOq!5L7%EFq9V0qcw9nTGwvU-;;)cfGN-;*LS{|}Vlr|)SESi+FE_h#-d1j)j z7*f!k41VgzZY&m0&dlt)?8=+|`3EoF^Q}iaQ!@@qF&adwBCp0HQYe;-(O81`vLfGo z>pQN!>y|fUktsQQ{?zERU;2Jtlv$Pr>x_<=xYyfgG*j|29v4X`VX|q=fA}9ih0rCO zFv+gJ{QNgQ`-SgKc4kRQ>D`6%7YF@eKI%uxxWHvmIIcn|Fkb!eC;!zQw_lsDuVtOx z|NO&~k36{mNM&igKorHUEQ56d^y*8m#6X=+XEf-lF!*o(>Ay77!r7i_9DL}3=l-uh z`WqHYNFv(jrE?V$6}GHr;0WTXV%zM*|M~mBJ->CD1CUDY{oeh*`}==5IWZkrl%~;O zM1;mf!+uW#0&cBB06(6d!gt<&#pPGt2D}V3bH}Z3{`p`1&xx~Wh*?}^gY!~4jC5HP zgfj>jyp*nZ`>v_4K7Ns{DcIT#E91iS^Qd-S4#Jcr@1e_;R3?|t7-gI@)`W$pea zNJK=u^TE}wF7e*i#6=M%6$S5XvGTE>{H24JUw`njO8~bYKlja4dlOONLsdHOH=jo( zFaZW;30^!~z^kvm?y`gX0USW|b01R+=l;K{3WD64XcCFDRZYf2MT7w2jiSmGZ@BH| zyY9MMc!1P;;IX6s>Hq#;kue%cfl!bTd~H6dd0T;<1|7=rtyf*LXa6DRM#jue&&>bc zzyCub*t&J=`o{V=&qt$CQ50G!j3R}`P=rLxZfX74wrTgi_y2hJ{Bo!~0Dw3K?Lye} zzn~*TWt2t=J}@#0k})8fz=(L{z(N2hwW$)7QYtt->=lt-{_uz1`P?%v9Y4FAwx$%K z^FdgI^rn%fZn}ryD^QAnFaWc!g}?I3E3bIZS+ms}4AUeX=cA>?bB#1BiehzbZE9+| zs$?)2Bql4W5%K*2mS6^w~;iG zIJLeEUyko1RjByYbvV;AgC|(0Wn};4%KjjhKRDUdPW%?+^WJ!L^T>*Bn;lKXFQST8ze(yN~kSv6so)`q}`rDB4CTi zHI-jD)G1x87iBB}BmzdGp!jN(W_sVAt+UeKqbt+rbkzm@UA`k zW_RvR+Iy>BmnFA0uL{eaB1Hj|5>q+BN^}-)YiysJpF4eKVKD3shwGU!+K^78vR5Et ztKG292jIj23l?Ri6t`RHa4^`nZ}0T<#Kc77si&TL?4bt^9@y7Rqfm}aQta5;3S2eY z?OnTeDS}3t9yoAtZf@>7_kHupM;>W*rlV%IXXj1fLecflvL~N1`}gK6lZ(QY%I3HJyOGhWDy{djf$0QHTUU zNECp6P3$WKpv0^#Z-9s2`ggx}%{LzSlh58)7O62RisOmSbfeLjXt$nt{3&*R;n?wo zg@rxa=1h`iM&A35nF`|V$S>+LuD;>=PvKeOup@Q=T^(YGd62qLHv zRhnezJ)jt)EAK^+0)OHcKXmI&hX4wI+2ytVJ3shI$01ePT8m0mQo0a=gcz_I=he8d zWhGp`|6O+-y6O@D0!R+Oxb&(2@aKiCVqiiAEWjLTQ#z}Oj8Vn7$|6NiaGlVU|D)dXr-mk|-|9k*0_x#E{?p#v3lX{vZt2puOYl>a&SfI!@rV zs+}+kfF=bL0<*U^F|@XJ=EB9J`}glC^C7_M%Icy*jigyzVBc)C#={b!-YNrFpXj($ zRz+Ui8YrJ83gY;gXP&M(>%rL|2#P#G9iWd?3@BA)HBsU6jkVLdiAX~*Tb_UZ>EJ8F znTl%NvBJ7b9@qsBfD(iVx~mtTeDv|_uDf(@+xAGgZ+_!zoz^t4guqB)kdL9ZK|yVx zA_;*IrOa*72UvH5bz|HYzVJ7Us1*TA6+-a7VUn>8-nu#+03^mxsARRfJU5Nw^_6zk zdF+YDN5f&9wLKyVvaM~{L4n!?$`NWH?`&`dNZ$^7QK#|X{SRhY>OyeNvIqfb#K3iH zKok*^VhT3T7Zy$e_|=t*GxMF3Cl-iRlo%fZvltVP$75#g9FriURx0As6WdOVer?fd zpH4K-pFZtfl|)fqIUPj+XsZeUD2i$pyHZ972ZNPo4?la^!95#;-ekMIeBq+2EHg$J zlOPE&ZW>DnDby)L2u9;`hY#O%*Be5yp&R(bqYvdpu60wVDl!IPQ$<=cy$op(kI07n z^5VHYJGOS0F3xNXnPH=dfti3vrD+;PkwOBIP?b7KSwMkLwVUYhAO6>WKkSXmqB7ce zcEAcy5pm^%QW%+L9JfcKa&^78(d!3*5FA_IY^6~It!CVrn2aN3tq&~7K%@vj6dQtK zTy&-yzx!Li@TuSaqcZq{nFyh#p$Z{j;GjYMi=O?p1q8AnA%qYb&Gx(B`R>2`++WYl z?|8$VZ&*Bk{_3l*dh+qdk39eU@=|x--hGFzIP{(Gepjm~P2-zie+zT)KCCP)zH;=~ z2R`tD$msDnKXc~HvE#=N9y~ZRGjr{=SAFJxe#Tih&c`45@JH@{@cv^9C*Jaw*S-Fh zTZ8wZs;aVFIJxkpd%mP7}CfX#Mh1)0OUHU0SrjN^X7PCa~o63v?VZC&bG3K z(WWXZV~kd6GqEd(2#8q2TfJkY2si!S3`js;p!Pl?QVk2*T;VXY(G>iq_FOjI^_#n! z8te$Q-<+VvQ4$dn3J56zf)IkYY~l#(-&!Al0~kZF>9iLK;?XOkH^G1+jHtbM5kXY7 zi4bd)A&MEi%yUoUAWVV%6AJH2_2txxJBzOrCDaY)+ zgZh;!B^)q_HU?2Mu!#v`h3I$hnpUbE%F)`&A__Ot287z2Dj-6N0)t7?t1iD%PtO8K z(LGuY$0diRX&RN9W+XOf)Fz6ob)+Li?Df|q_RS-hId7+UT>NyRSL56%kLLIk|1i)+kOolM{>G)xpY= z2iY?}A2@X4;rriyaNDlkV7n0QJaG;Wzx?WGXq#;!1|-GKLtt@E5fw$@nVXp*JG}XI zmt1zuAt+ZN+28v1^N6ft!w3kBLIU7ftaHX_2!J4I5(_2M(=BMVitbw4p1gAZ{JYN^yz%iXCJW%L0lA> z8qRA=@7Yaf831Tf{jz-a$;WQJX=l-2N+%`A7!?`xjkVqgK$smt<2&Db2tb-iG|tCWRUwdwIBN+=Kzw1xSf)vA z^yI?H#r^xQN-_qRUtRY>Kx=Y>0_ZB|z4P8_g)ER;o5Wc&O$ViR&;godtrcuJdtnhI zfcU^{od>IBlSs*0q0$Nvh{#0I#yH=xb+7X==tk)=Ab0_Gp$aZZ4S;wb7y%R(wo-(k zRFbw9yK8Uk%tXoLaJUkLl+j3p%z-&lI!)8@c+3DwYhVc+jE)(2;oR_=n7v zttE(6U_xL4uH}n?B(V3v*QQ@E>CuymSKW9+lT*-Jv`IA?B1OUhgrTmF)(W-FP9%Zq zw5K2X(UWg`=bceA0yTN&;;J^LP6{9hAXG(3w27R?nnJ9Rg@P!6q&2k_py@^8Mm)~P zX_}U$6=9_`04RdsgG!WlULgv^5H)o+t<$tB&9g5Y1vEwJymLxx#?8gP^G-wvYTPbo zN&4Kg&)<3b&GU2n0K$=%j*W*yon|Z%0J(TU#ljEXzn?@J@8h6kJg? zi~}Bg1}B#1=jPu1<3Dl9{!3mxeiVpqxb~Wdhl7>Hi+A36=f%aPGiT1e=}mWD zd);*>Pn|sW>am+{y5Y@leX|f2qwymTJ#_BExp)3=Z~ofXzO{YF+)b~$@t%LU=lbif zjiPvdZu^|iHg=guBHuz%~^*6vz2)JQ|3 zAWT@tdRRn!ZFFJ`!u4c~>y}K|G{rJA5CRhcT5I#7U=eR^5rT8B{&dyjoH{s2NHt=9 zGnyg-^*p9_Io2f`AVeh8B0(WB)My^5i_P`H1z=OTLV$<_vZ;_mtb6IqfORG*c8r zFV+{kTn@8|nP78Y7H%|78jT5~^6@xQv@#m(?o7C1nS3Zm1LR?($dE0^-7MvmZf|n3 z!!mT01v~WPb&8`@`+PV=h9ru$8k2zYmXSe>h)3`w;Jt?m5hW0cCk3dC0iqhLTMk(p z5Lfj3y;dXDT7nMqi-Eb3WsbeI z1rd~a-kF}BZco`fAFU5`qUN@2Z>Ejz;^M`#XZBsPKi$9o)QRJsu+?nWm)TCI4IpPv zFErDvktRyR^vq>YCV<#_OxNzlFhw3m2O9%i_l;ow2442jV8*jh8*>0^a zudskZVPTC}1A+hvI3Pii7_FnydRw0Yi5f{$k(Bw!`l9Y)X`|~UVGtij$+!@=c>ZU8 z<^wOibo%k9kEg9^#_IU7qb7<6!(kAYX6d*r`s3bAClNm1oM?mOw)Bz8zx4NCUR_zs z8k3#_iK(0;U=FM(vaVw9;yBjg@}gYt4FNnT1CTxU;t>H)h}Ju6E2ASMQbf#LORORk z)~eSZKlS+2m)&%8x+QWO`QuMLaqSg%EDiZbPdqy_-SI)#13>T`5K#~WF$fcKLk2X`)`NFS$c4ZHfvr-yu<1ijy?EQ3Zlul*knG|r z_eW!Akra4eQ6rTgh-jj?D2L3x*=P)hHk+RN%g^7}p5DD@|8+;6J@M$Hue2v7l$PN} z!5V7@Xnj0DL;=u>%5mwr@x#Z@?Y+!uJ$2-fCr_U4Die=}IV)m;;4LZi3VdMD6d1%+ zX{;>8U;O*;{vW^b+k-JKA3gchk)tk1B%yNbf-@0|fG99XrLRyca25b{)Ebojsl%_{ zczydb|KqbOYh$H!2ws99ZAumD&Q0ZjCMUj8oa-JvxkAQ7QB;mcCN?6q_FSBGYAW&~s0c+` zld}&WKKJXt{pVL)acFsY{rI{5?5-VU>HEDAAu`mE1_{g}61eu*V3JP$@X=$J-uL~z zd-pFcKk?+VFOY&bik)?F95H)l7lH^#5Ya3Oz2{&W(|`K8uYUShf3v%B;r<^!b>_mb zIW;N59#ErzNL5vF94SRaq!d=pX&nW@Q)j!s`yW5^^S|(kr=EQFfk$78qIRp+$k<>#7P~DC2^h--|l#EB!D3>TwXmD-NOVdOv?SfNU6~hq%xZo8b2eH)t z%6-qBxn%MVht=jIc-VLa3O{=g{EP%=YEQ(Z$6=n|G0}FxrIfTM+U-tjyWhTj=gy7Z#^mJW-FM%8(@i%nE-$JmT3uaz?8zsD z83@LCe*DDA?K^hP&u<^+`LoYFw|m!at&)w6;V=F2JIkt=oSeA*j@JiURb_Sf@N?@M z>$l%}t1*$$8tV9{_e`4&6+{HA5v&0ao%i%Fh96Y5#*0HhK<7PZD$7EXvRqkfo6V;8 z9ubvNwP~)7rPd6pDAEERq~^7R*8sB`6-wQ~VMZb%0 zuCpZ1W*77-USs$-aACBT&0MF8I@?<3;_cGdkz|u zMi9x@*B7Unk|u_oAlo=j%W`DNw>q>jSR0M~#N@VobS_Kmc-#+uhd_waPz)EVGQrM# znGecQzsfhZOm{jBBj}4_U`Ku3X=X+#3Pux%GbXSvz+3U0Bypsqv;_wTiczu4haoT$ zGK*0WfJBB^m>saKl&X0^wciQzvZx*5K%@x;1%kIW%+Aj4zV12zwSMMQF&IoXTMkri zDUF&UD$SZ=3y}~Ct3XVYjbscqD8Sk=>%C|1+pX!z&djM3ubw`6_Q3wVS01|Z*wL5A zG}Qk;QEwV+S$5s`tzqwd&bjx#sb0OBdnTLR;@ng>2T>wr$P!~pVH_lO5KBss07;O< zF=7Z1k`E3H1Tv5h8Id@EKO~MJ$#eqAwj@&&Nt?}Xs!4W}&7S9~>YD4ldgGnW*?SH7 zuy0%SsZe-8J>22!wbxqz-!Fzpv0uza?Rb5>ar@5gVVOC?Xp~0X`1o*I=0jdAou~-j zx^e6Jt>MhhxmRC$nVBfY{e#2l`uj(;0_f z_~l>ik-z$tuYUjO@9rPmJKo=a_<{Q_o;#bD%lXMkij@^;{c;h^DK4J;*$@BnFa4$Y z(Nxt4kyn5;K_CNXvbGzU!~556nuXo{`Es#j^3iCrdFoWx!uHOji=kgGr$>iDL))}! z^(HTX)-U~V@6EsW-~X5Y^>6*pue^1OQ#f;a=hA%_UwiYdqsvEeebhmW0HaA0`cv~6 zPBu=b^|Qw_{^q}YkyC@%@J{ZJlgr`+qYx4PRvq@0h$;RlR)ikl6wRi`jWcI>+kNq_4eNOnbW(w zciw(~%1tZMlLj?K=9Vpf+`N8uIlTGZXJ5@(+Yze+kXIB$ zm2|2NBc@BJ(7**qr(1 zGwH^w)FR3pR1^S+X~@|fiO5l6NTbQw!~NOc`MbZ@jQ;q} zt&{QkX4A&p_lV>Q6uCk$i5O%+l^QI(aPg7vJpJ-Fzw=`Rn$3r^XU;}uT|Kn`9HWsN z8%n|ehA~h~JX+g%;l&&O(SP>0m&;+k=*Qi9o7$Q)ft3f?RE$$>I5bUg_drf)FTC*P zv(NnWWcK$7X?3*M?W(mqPn@`_Nhx(t{?pM-~6pMwCdE3*H52bABr=vnN}P#5$CcTHw`P!3gZI&JAd#0a3BCYeRg|& za}yyfdW!Bt`jkb5boSw{`PvZ=YLYGO7AN9;vJ6kI_yHjP=>y<7gjKm2w|>3h$<96}m*A#zf+5P~9< zlFbakpojy6){D;n&AgY5LL~Q7X7ewn*M{o@mK%$-~9(`8xO|NsAq8i zcO>*;Ok{)rl>o~Q5Rg?}#s2(ze}3t~2M?#S_pV<5m5*FRY$iUT z(yLEA@x-;ZWWBrDda&^jfrYMET!}pvm2<(sR0qIWsH!_+#Lv< zLogGlOj&ZmDl@_r6s;26>Xt69IJu5BQ{-;Ogw=XxZs-752`Na7H7`U+$SW&YMeDm- z6&J1GCT4Z>hLFmj2rHEsI0meU-WvHLc6DN!9vv+g_h3Ap&*o?@MPRhnj@p3Q=bV?* z1(ycS^oygM`|)V~00tg48YHRCxBpNMl#6YTjuAQ8DTxp(+4zVWA*&Tpq~e7LuJ=l0!EA_8GZs@}D7{@nP#_|N|n zVw&Y8fCdQW1gJn{>LFr^qdR;1SFYTc&j#c!#?4W)*>zC?jt=DjmM8Pvw(+6+FP+-j zdHdZrhGoCDKB)q+-~@oP!=tUq_SgQ6r(S*SADuq;&~NWd0|A@XWF_qqeD&(V{{e!M$o7DqGe}oJcTz=h;{8?iY3V-GA~& zv$=GmE~~hMshiqju_&cz$~fya${Ajf(;I+2t*{Mu$#DzCu_j* zh4+r1e(5KSx-}UiVsS4f?xbdJhCnKoO9r+O$(nGmf2d`W(y5{Ew>D3OHVtLy7t0vO zU{-N|pzZ`55^+F9CYtyC{r5d|cyuI^w@y*pPWpbCHIoH12;?CIWuRgJ76Y|iE4er2 z(c0Fs%+6l86e#ZP9%gZ^9e56Ph(ds_o=Zk?=8!%2{V*K_0Ym6Q2!KSyeJN(nNK9nt zL(WwpRB{O+s-P4#=gIig+S(Za&sIWga?v6Rgn%&Q0V;jLS8ytG9(rlR1qU=FB;t+DjSzy{n3>ksN5|7?(HxtWDc;?^3+NF8I5r`q zWb0k`=}&+B@Myo7kOQ~_k-LhOix(fbduRUMd%ImXVFo65C!!G$K@GFIR_GrFGx2V` zA>Lno|NT)rUf(!1n;l0=02l(XyOHO7RUN8Vs7j)oz-yt1 zXu%O2IItr!r-vW-&?{%&{K?C&JoUxT74ePD?RT$SJvyFmY@XUaa}GoN_{Tp97#4lb zg8*>Tv|HQT?_Rn5${TO~{1<;N`*8i%jr$+CcxGq&-581Kkqz103Pe;(N*70}5o`FMbaJS! zZ1W1v_<#soV@O!z@Q4(M9l_jH9T38*7xS;ZKn7R`QLMStWnlzRQ?7dMu!_7pA*o?t zurkyBu;5U;?S4lql3d3c*u*j zwaLlJR7#E^s5wDY&uWTD9M}ol)Bzwixy+Lfmn9?YuKtw7Arc#bR^Qk8{Hzr31`zCb=Vs)u57{<`VhF*K^t-E(m z2*;z*wll=ogpdHqL6{hQv{?FlCbOd}kNwQUkAL#Bx88g8_~fu1tvMnA5gUha_x6=v z`pT#N;n%;Oy?4NIH+tleN6zf*+`M}?28wO7xxSr;<;!pE{{H{_znm-tLbo;K>U92FdEl0|lTkXlczDDYl83(s*qs0|!Ji6$2(UKs1cO1EaYNWwBWLwo}Au z-xK1QGdpEtxtO1b6fjm3t4|z2Vp4T8g-B|sNU9Q=7O5GsA~L6lU}BCOi;4nB5d;9j zf*=H09Wg-SVj6+Fu01?nAjCyKH!&hCIwWoZ+}t!5RU0*Fv_3L50YCsT6{WN1F7^HJ z{`Fl%GIVoACs=VH3=jz^P>@p0EH({Oq^fa3?{lu1Nks!NGXZpBM4|#E#YRjVAW$q^ z`(#i6D8!=0)TAiJfCL1PO+|zVV~D1vChC|%T=t8UA_rG50#?l=geYdlE5AdC0SJlN zYDPm;ML7^~Fn}W3=OJ)h=H3y+wQWYS?2AdA*ob-795^r{5gPci7gbf)LA_~5$mHN^ zYGw}L?3hByMRVW8loC~FYnD=qfTOs{a#8ai$fzP}>X0hiLbP^L41gAcM$TrSs^~UO z<01kCfw|Aw0hoh%sdg2P9NgGQ!I8tD1=ZX@%$BN%SaP0BMk1o_=E$pte-$|(0-A$4 zf}@JY(4^F;s1$7i#{^AF$HzCG{KdxtQO>z)meBzN=3=L}&k~JZeeJdJ+75>R2u4Ie zbqSh?>m-E0hEg06*$L9x`q}x+-@9_!_lLeVf)|f(y$xKd8PE`8wWI{v%aV}-l zjn6#tn4>Ii?;alub3FfV zAAMl+lOJCD#ixGeo$GtQ|DBg#c)z!9V+;LQz|0#z!*;qe&_Vn#Lx7CWN0nlvG-?@9lVQW0L ztlIaB4~D{S2uvs{Y6faV*lR%scQ2~rwT*V{LlMY}QXrQiMykeyD;%>s5{a2362!p^ zsxe|ptvWQsR)mOZN7T)zW_gIJFj$Hbhhj=j4JS3@aY{ZaMF3H9Z(i*fNQ6LO;y{6r zLriGuV8$G~wb)?a_sgLuV5tUOM3KzIh#;a&41`0;%-p8vfZceUM3(*13>;m}RUw!I zQebj4HD?FLfEd7?$YKBstnOSjUkH>U2)ettL1YKWDg;pTL+YmLMkG3DDb-d7E~@H8 zszRAoj7wLocO|3VfZbiS0;K>XXUSd(({8$Ybg4SCsfelxy9+ca8e%U6D2Sq|H~=al z1Yjg4a4-Gfh=IusV~n|EuPrZ1?_9aj1_pEmQD+ARwP4On0$^&6jzsDjW00cAD5^-b z%IP>2u|fvkqZm10AaDyIW~^nciwXeDhr!fDOWU>(Lk4pPFz3~z+?a`(6kJSGh^l3& z*$IkDpECvqL@DYB;z$HQplXAdXaRR~4}^dqN))kZG0_;C5S%!x6>?aX!W_X79D%ux zm+C^mpvB!8soqnO2prHrzbV>Dh67sC;%`ps|UNe zF_KzU%nO1OAv)CQ0x_vsajhJ9LvsWq)FNK5wkr*e1CuF`R#T}n2M3fQZd3)IMqs%5 zB6DCykAVR|(GBeQcm@W{P07U^N24(S6v?TXq~s_0=x0CkGt58^z$B&>qz(w{8)tv~ z{5zx3shE<15(WoCB4Q+nP=(zHRRCYzGU6DpYuj`4`OTX*u3bELZhsg=3n2m^Gpp(B z`0xv#d-BGbtC-$-rOO*a1WFa71`pa1da zKL5GJbPm9g`PS}@_us!V8g+d?Y;0~A__FVtrcF(Adgt8M#;M02f1H`Swvpv>Hl0l! zkEipT_3+>@w&{=my-~Y1SmDKuN96ifzWC86e)01?=YD_M z=Ymc}3Cw0Hw$Q+NvpatHwEw5S{MgP5cb|S||9I-2+7JQ;LI*;Rjox?v*^P~@gL?;{ zMvP{}NOj@5?V7jVdH3)zPsXRYNshpbM2rBABv{k$41@-*=oHd;vVHCSdoj?Z3lF_> z`HifyKG_rzaB{PQd&fWb)ECa5{qEhncc;?@u%Ekl-)KCZ_dNlcF+uA4zU!J`f*Dnk zs<CqOg^ETVZ(q6#=9L{#%Y7?8|8P&HhjxT!&)NC@T? zv_O>#RoB#+SXJ!KXd}Vi-oB{B6axnnD=Og7bdYo1pJg>KZt4Kyh?sLRFcfij z5f#;}0*r)|h`}7qOBNGFXK|?}TeV7*5JVJk>5HlWBM^z(V!1?OaPh$mh(qKMmdoDV z2}#r(VCa_|0zfsPgcwqymHtOr>L}<)RQjAt)sM3gND(t3a=?`@#of^=fYZzriA1Dp z+9HO)YKjDop0!rZZfL45B2C+ngP2xvqkZ5RuYh){0oY>TARvUKNB~&f>}ql!zo4;RWq$>8%G0cLOYw;;bA{o-@s61 zH;H)_XeT5fHWNfPH{z%|ATT2Wlo(pV(f+;t3+H!I3=WQHuh@T<)8oj|MY+U zBX=-2z-X#eb4}_%5CWSy04Z|G17SQqKKklczecgUaNmP(z570K*gHI&&K93~;xqs1 zUwtQ}Q9D@|rT4B}|NXE3+GtYeIJKz4z-~5fyxcj*;e!i5vHd)(P z+o&F5HF2xDV{&%_>e@EvTuP}E_NrW>O5am81P%dI8w{8#xdcTrhrkq6r3x}l0g(XF zQF&#DE_MIOtGK={&Y2rHk)sg+B7>U&AUYGWg4PAv3KLp!BR`>2UUV6xUW0lY~%%i z2Y_(tz7KcX=lg>j^Zi3dj?B3(awc{HcL>PZFC{g`3Svf19ERL0;rjWD!|vXEHbsYS zYr-7*<;lUFy-C|qgl;@u%(DufI&~{*(=fgKsV_hD#b5oEVOsL>Tn9_38+=F{%*2HW zz{QW}i&3|^y{(`B(B#g&*^ln+Qy_Ixk1pE80Jb=_)q!dmmVvO60jtWdX`B81!yDIk zQ?rJVfCw=dFc2e=s*@8%ay4+z0OlUR$V1|_H(!5$`}D`}J9ppRJMX(>L;$4fgHV$v zKKaQ%`Nj*QQ8!!6X4C1z4?Xho8?QNHQ8(mbmA#1SV1xz%M2W!3)gc%*As&HAQFl}U zr+}eZ_980GoE62em~o|8iU8Fcp_|s)2c*tJ0hwv2UuZQ)21XDgGXqz3WkMyjCF+kmgNFIT~ zRE0x`fDG(e710b(2p}cM1;qr6o$B74Cl7$;DCpcYPUu9v`g}PUTHrX8oJE09Ypg>= z&0|2Sj&(++APU4pfTawMq~MC~MPRjvVrb-yPF`H1a0pGP`5eF@mm<2V@Inv~1tO?( z7*|m@S9eEH1u+AlqvOM2$V9;a#Ff+n1vd~~W^#9EN`n9j9w>;)(ebfYEEOOzmqCgc z5d&Z@B3Wy=K#QUiQ9>jNP{-iKOhp_iiGB%tLLBv#a<);M% zq(J0Q;U+=)3}&fqFa!~cm?)4GCE$_^5^7OEsH&6@g08Sx2K821hmP)`;6_EkKxMIH z;tZf_y2!`pNh*S$0uev)5WF`icgTC57Rx54>TD$n*^-BZhjOI{x zvP_-GYv;;bOO4nVLBXn~jR`P@CVzj>T z&Xrrg`}Kd$0Y3Jzk3IeTOUs#@1--+~wV)!wmbEuV21#Go|JSfBwU3 zx2}ywYmw=9fA1e3?B1R&=Z`-6*r;h=eeLBZ+9%$7=Pe?ZWp=Y?pZVV2?K_e9`5!%h zcz9@ThX+SHJ7;d*z7CPs*Ed9E7zQf_?u1ZW!Mv7PAw_UUtw~=nt!=jOfq0T?&^@N8 zA~j63iU9$+JGe8VBT}fOD0HkFzN^g`uRt%WNJTVr5U(Ml+R3ZCx2u(21aqg_`yzBV za|b0@MFwgF8q6%l=;rp|2;%?%AOJ~3K~yP4Q!zJos>#Gks{=z~0y4ttn*&ijIzA3H zdE*!e*{cqU+`-KY158E}z#bS8fEm#V7~E{xFQgP^$~niFI7LQh0@aMDY6ZFWK@8Cx zj1VJ-`g*D6lp-@DGQrAjSfm&@r=aS{WGar1NRdfZnS;A4sITJU4uo#z3d96R;2{zq zvbviY#fCyWf8qYMOAlzCp6nksAp)>yare=pCiE%U;E&Bn?VrU4dhQC$S=gX#T z=ks}BA`Gq`k)a78wcbZNKR0am7-D*BZ8PY zvzjgEy|($om(G6S@$T|ozqgdoB$w&y)3z(cI0hg$gZXmVtWUrE z^H2WqA3x{N#?%c%?%K8uvA7wytUOiqF#v(d+04mcMF24KMIOuzsfsWP)R{dP0G1-^ zW}*S>)zlE{wJbDEH=EA5O1`bO5D@^2Db{1P8crO*pz@lTQ{5{>qQI=hLc$e33fxTU z#jsYx*^C^`L>opX6LG`r!hu21#ENRKLyW-;l*kO47}?NN6rA17HPj2bfmwBn83Aii zuSiNl%!Uj`28IM^1{KudUZa7$SPqEDiNQd$7&3Ws|R5^KR;hu2xGEKqmlIExCjkVr)%aN4z=^m{MgU1lb_aA2 z(F#6|M21lf7+u{6qMC-lt_~0!)vTDPiPj3s-D`RQBcUU$+?n;|c0&+RA~I1i0~9x! z_DfJnlpI!9Ms=V->H-c10A@LtiUVIRmTlWDa^JNL7%Yaqt|=N5V`!QH;K)Ixh-Bh= z)}jDpC}s-ep|U}}Mx`Kz7EBGq0hk$yfLOs&BGp0^D&nGU2f%7o6bONc&74D6k;I4- z2dj-nH!~qZuL&DuLs3;E25~ZkDz9~2RXzp;SVPX}&G^rL^u|LEJg_$}zxRjV zJy|a2GEUe^?!WmjpVodc>f-ujWNvr&ZiD6&=)HH|M8vhV@tbeFcJ=Z*?mjG*ZA!1d z{%SzpKD~YW)~)w0zl(&-sqYtyez~?bnJ<^<=HdVV4o2?ePL9ZGh6;g$y4H3BRK5v- ziqv#b4HJYW4W(E=#Px`kLI*333o}={u&V*AI)dg-AJigHlgzdGiuKDtHLg_KDzy@# znp;Lf1XCvOWP=4fMgxqEQ!^7-@U?%myA_GM65^m+H_c&YJ^{`5z^ zuPH`O8>tO$mcX0g;0vGl`P6nt2geSSl?qHm0m2vpLBF(|&D|VAY}I5CTTl6+_3+fA z_kHunmmyezp$--|)|-p>UpUx1av+C-D`JaaXk^*r|goKDh93$&0 zj{xT8#SrV}DS+^NA=CMcW00I9Avgd9Oukqg?3~`Ybm`Q!TPLxZ5TKe8AVY->8W9sh z;Na?@fTl*yzJg5xDj^19$x;hy7t<_etNW{JffW?V5$d3lR29I9863e7!8o7{Mj@gJ zfteI35;y>2MdnosbvGFw9UoWpt*DM5*4c@Px|pGv84?Nt`3GWqM*v8`H9#967;62b zF`*%HY{)zSA)u*oN*>UPs;Rkyt}a0CAga#hCJd+`#3&ppzM5P)M04|^NaiX!3@wL6 zUSL2#U?LDt%tnC3=H7%3001mTW(o*uY9YlKc)1ubtWGsFj~pSoBZCS%SO9R3TD5u* z0tZ~xspLqj5xF}cIRUx)>eS{Gts)v~-=EnLLrBb0-yao0A_aB8kh)O&J%p-8U}A+7 zrAUl14}#8W3g9uYt&n9{yHe(Wgkt&up$(E#Q6ux(dt+o3A~ykNKrpFW43T4^m=Ol> z*hKJ(7GiQYvO45PVpj-(RSPn?W8%cT3PQN6nuU5uG8rR@1Av%15|E*RJ1~)_XoQI9 zjomvs*xA`h$VEz*+Lj@k2{<4(Z9+0PS62+R?zXxVOhjr{J$|*R4Q{4N7ywmWk)XH_ zrIasU}0(rb&s3oL5;F<2pNI%wB*)tv?Ce0Ep4ifL1+GBJc|HH>@&U zcdIa81t%g^iO3}e(NZPqhDPKrWinY)Jr1dbRWg6Ix=}CjPF}>_uaZ$MK`y%j)|u-_tV>_yU`|i%e3CmsO(;Or9%odZiiI|8;8S)2GNvH;9L?ogLXfZPrTP?5Dj%fWKarNRLVBLFl2V|@Y z~HAbqFO+;|7i|6nGD8}6bvzdh$ z!%8a803Ljmaq~)vAw+Ya7%*`RiCj#DIhDSsWRU{wY!qXh&5kK>jEw=ucG3^W4nbWN zkzyJa3j^ZVP>Q0O`##20G7MQlj7^)4kEcwDW81_@j+lp{f`-8W!~`8&6@iFT+coA8 z(`d1nb7+`Z%*_OlP&I^hzU-Gn&xxDRbln7-mfV($Wk^Z=Fa7{hMKmYiJ`W0EJeiaMFj*LPp@c&Z{NIg|9xlg&F;EbJx9rik-PC|YomMj>TWmL zo-a=tthYbPS^AvYm@p7lfG(qnu_F9hSskQ zGrL(SL!G}Opo+Mffvc^&od6U#AfmZpU{oh$B3$Mk2-Fl5z$+%vh*&kNsj4BfSMKNP zM3EY^6SKes4oX;xy6GUr%>#Huu4W4i4#2LCfgo`y5-BMtIina85U?wlqXR?-af{5R zMjQgNs>YB~)0UC}G}HklOnIWUK?=!e<>P$&Qhfypgs z5c5F6(7*v5-ALTqCNAeh98?VqYeSxiOvH*(VqER#VT_Hsfhs5)A#*^eR1VXkpx(x& zZbT9hJE57nxiKRF0WuPkj1gCx<6*zx|#%Bu-2=I4Tw)U*h=xFbOzIv|tQ+RcDD|tvK#XQ;LZnp1F|=Y}s4GGxpn*AHjM2=DATXi> zeULb1VsxtVylN&UM0SMQw6+WYfjDtOM-HHBh+Lok4p7_>k%=n%&dm{sAan_GQKpr( z43UZyQy|B{k$@`#1naV7$+fmIKv%~|O^oA|n3$0e9EcDJ3`;*)@emqBqPqSP1DFE< zRnUi-gPCOFKwNt*tI#--6R^1gA_cNi+=!hJNs2OBmDGT%NH%lEgg}JE%;pvd-JOX_ zDM+YhP&q~zj!x#==Rfj=Fa7l+U3=;9gG`Y?uH0p;N*a{$f24+=DHIjS!x0|5JT`{8kkpj7&olXXM?)GUx%>8v`KAX%EO|F zBGw_e2S!2^aIDiNB0jt~9d%vKivl(ojl0-{fXiVaLs2nwO3moP#Y->0@)LI#Rm9-B z66mUdD~8xLVIiVj;@CD9PMt2AFaQ5My=kyz*;U{9Uu*4s&bi~8bE+Y05JD==5&|O$ zBM6WITeOL$3Cq~n-3=JG9pP|?y9wLSrXAhwu%qedc6R_alN&l1Obf(lu#jk3Dh(xp zN&`}rs15Z$+InrNPw9ESJnIP16pmoJxvuytTbE^l3Jmr=cgJ$z;Y% zBq0R3eEG$a`ZH%QQ0PuyxkeJOZjyi!2nG-Z;mF0anRi_iLM)ncQR)Y7T9E)IiA^X< zAqEyAHe~_VJ9uas%e|YAx|wGq(0DW(2E|F5%;u@&8tz&wR{OX2yHWVMcYNcQU%GMQ z+Rf2qG@=x8|M120TO0GEd-tziKX~YC-?FoNap#dY@ccY1qYQ|SG+=Rm@xoWW@cEBF zyf+CUD7c;SbjeRXcK!=D@1(4;3o*!SGKHF~rxBD&UpajIpOFS$@)MkHr5C6y+~=Eg<{p=g3@(TvC`^;#@|eZ7JL zQGjO=0oV*qby5sBU(2T*S_Ne6a7YwacR0sJi`Gj66Pa2F>~3Z%63q%gL_#QP1rP27 zRl>+%t3^~0a}t)~){($0^*zleB-OgufO5r@wHUK0xp@&VF+%~Ol(R%}Hz!hN2nUEj z9I(1gvpQQfQ|e;VcI{%hASYo`c*>d95^Aol3?Z&f_iWYA#s)8DrVtKhN(2bIRIa3#$^LSP9M#uuZT6wiaV^6m|l$n<5#p7{Rj=goq+UO-nA5(Rk^WaxR){@;Pe; zoWSeH4YQj0TG;BLYlx+oG1agMmD>AdCd4jM^;L}Q#KcfHfe=y7K8{V!i3m(0Yy@Kg zh3MuE3QPs!Uf@Q;nHA>3&cwyJD$eT9s%k=v9bR|jT*S5hznc}yYR1NS$Xd@q#ZkYW zX-&aY;5$I-Y@OU$otcVTacxAJu9>>2mLP2b70tpR^F~C;l3T3X4FKw;FAraM2#&s# z*hCO|O;MyCh5!%+Hd7dZySA%lS!Zex#011FWCSP&3GQZ|K~5rMXhKU4c9;6wQM7HE zN(|JGA~75Yp(%CpYzBA)5mVNZOKzJ^O|@#j9PHxsRS)Spu2D+}h`1C5ixpx*Y+}y2 z)VV)|-OUt^+9gyht3jBYU@&u6)voLMeg%+7RPBwykSZV3WF&%O#0Z3>UWz43ZP&RK zS52xxm>DGOL=uF+>%5n`yDwNHNsr8W(EEt+0%y^VNxX8vrYsEV$bs9Lzntt$!u5Dxu!*+v5FV z8JaknPJB>zPs>#Z3HvSR9uv~9zll}Vt=O`~Zw48vsHG0SSTn$0JvlvTe9ZR8-t z4X`kVk#Fv7z3OXU`)6Oc(2FhLE>IS#1zEr1b6j7P6|W<)L}3do{mSA{4lae z!oouu99kDnfKlCsGOfufxTD%EZ9QZpCk6;4l5z^tIMs52+Jq!rymFL8Tm`J|FjMzx z-Q)*jGq2*2wJ)(~r6mc@XxQs+8`1;_71LU%0W$SUu-8$rIx~5VWje>G!@z-tGOQ_- zDqUZ9iE&N!A*(Pcd$B?u$%&W*JXk62AU4;!qT(i0y2RBG7^>M!z(UkW)3X*;1(b}4 zjNIY%;0aY1*Y#!6oLpg6inFp)as#Nqi+G4^#sZXVOekh7Vn8iysU~ayMYTTq$-RaQ zM5Lxy43&0*F{017OC5kt*`8r7cIP!+u`07D5x?zx(>z$`+ZRfR0O)+)--r+zp& zT@E>iuE|4UmIP&D4#5GdOuK_wV%HWzL!_>-nysLES9Kb=>eU^>!2vVPs$JVUTn%ju zOG_;5b!hMOpfZif*J&drxSAQFH^lX)S=3#EIBb1htML#vHLa1L`f0bCBw-2^oXyN? zwWJk|aH`*P<^o4`Yyhsz6f`5HBthUN!XTKLLtt*40g4jW&M^vZW^5qjlt^tlorEaL zRMc`m^nFUJK1x&=0aY&g|@5 zyMAMY5$c`5v4*WYgea5Q_$!w#F;mN7G#bEq_vTjnAq3hpswpejH+2nt_(NU zK0B}SH?N2{RFq-CIk;`ZZ$(!Av1Ch1i04Yl&?*? zF@oo-MOqH0&XR{gb#!uaJmf-lOfoAYf3ADkX^ zZI^~}_wN1U#W5mtBTyV3_xrbB>XXf9+ueApX}kI|aN^_B(;9~) zkN_YJ0}*iufn_?IF8V=pJ~=ujrlQuwX`Jrn#qD1ENF9ezv$c&h{b~phX6EeNMWT>P z>f+cz02OjeStOQ{R5c1Y5a$ze4(?8t`d$DO%ei!2hY+M4YaTLT@EkRbxH&jD7O5@T zG8)f{p&Ly&wgwkr<`7~$T^%dR*5>xT)OdmsTaB3& zHR1I(pNQ1frL2THse>1Vxf2D61agAH9j;n9aMLybPp6x-@)+8^jh%Z(hr%3!RC-Ib zfUML9&w7mFMD-qDo8c)*Qde^`HANO-Bvm&OQiU*x*{qgh;j6z29D@THT3m(dx``-I z{hPoK`oTb4A4ZNKVMs$asibPE8|5HG#M!b0_M*h@06Sa@u`?rv#>~h}$O8l5p{T-4 zl^_NK6h*mB{dYhMvD60-7}1dhM^bQXdx!Zsk{>X9Xxx|=dW2*JI8V(cXF zYUoMGA7Fn#{aGmyXU|%^ZNVYb*1c48aP6&kub%SaY7J4c;^sB_NCXO0V7Zj&7#dC` zwJd$k#WYA@r+Nlr=9KF^9Q9vUQw}0QES08dS;W@qX(gt?y;dNSkmdw~n}w$7OBNAx zbuY#B;PBw!=)h{Rg}XQv*C5erGf+Jc3#YVhz6c>w5OZaz9$YeIFw`C5Mp}P)nSFgk zCn*n%{lsk930hw{PB8HL1){EQ0ww|zn^_Zso7LuWkfNSLnarG7OfyIwP)CT3nQ76= zstr28AwUIY1M~X(6$oh^r7l{CRAN+EAS$i}PU2u^F*w1+N$NPJSkC~n)bKD!0|$2u zL&>Tkh=*`^bZ~fbKLqakp=kuD1ZXiU8=KR6_wEr*0qHP;8 zH)Qug^K3RdDf#}Q-)40~txmaCNrMK5WUV-uqU zHLGohzFxa~9gWmM%lZt1nkj;<4wn4mIpGe(rip=8OY8Fh2b()QP>qbT!yQVw6ydg;o|(<2 zV=EvGC)djAc)oou-o8`%{_NhFt<7n7X7j0wkALiU-`~Uu(WIH5Yf^T+5T)JOdAxh{ z)%og6(}P1NY;B#{d(9iiw{IRDoJgFUIrrGsW3STX@t=SCGaN=RiLp(p)9F@h##?)5 zxNFPtacsLn7!D7m;ijD&?%(Z)eD0A)!GMTozj^hQ`S!zG%$hw;r&>;~eB}%6cm$BG zhWgD7p<$MkdnTGRqah~i;7yY?p2@JLnxFm&HC($8hmc5jeK@^w>WGpO_b0#+}gP5}x zp*3Y`X66>NC$v`p03ZNKL_t&n18%Hr4<0}O37M%^M`bO74us^@`2OJO;B{*qjhG({ zjEM*y3EcN8nMx#bmYj1S#K3*Z5oGX89=IW6285ASnWzT9$w~|X&Tum*F{x(Z znB7Upin4A=+%&h@= zPElCh;C0Kc=B0kbOf{Q1LoG!KAnIc4O0gLgQ^1G3VsfeaUm_9+aWPY~D1m4oLe-qG zLtR1O*c2+EglalpPxUyItSRTFi4GScVsY0%Qq(HWDl8gBgu1TnOFxM%lQ0P!UF>>Y z5CPn_2u|J#7w(6COFTHqM^WYN5oLJXKcBeY)G{C8DXANp_ zFP?)@DGFbl+1uKfw5g<`E-Y&9YHFDpzO#Qn)$&*rvo#Y_JHOmvu)1mzkeQw?PByzP z5eLgzjU7VGPHZLeh55F+T1hd;B9^=N@1Y&R3>>oQm%jA;r$7Cv_n!amo7ZlZoZA?G z|M!0P)~y?D6nEv?@JCc%^MLlNE7P% z;o;#Z#?|R^Jl>WNG$jV=tWHE&g6F~As~wvv%~}@`0D~B`&g%kN%7fb@2&Ab5W+PIq z#Phnh84nzE07S%LOl)woQoZ{i)>3Mv5m7Mms+N&@pjRg*7y@&2y`c0wTb@m9pv3Rp;ZK2zqv%OQnAp`DM~&2}`N&3B=Kt=Z5g|0`biou@+P0mGD04J(4jrVNd+1_G#U)5=JxrzP&h9;Q^Xd)2QlElT+r^?v z&W*%CfkaX%)d0x3G~-yOhz56W`qZzMX*%0%=G#cFtCfUUQi)w~2ZU%8?fxMkVbr1b zp8 zM9C!|9vxPnX%j}uC0kbYCh#c6?7hQWp*cg1m`zPc%z+2ZSYW_iSb_w1g=q|piKu|m z%86LmVa(zL*WzFzDn;9_RV}#;K_ph=5L{uV#hJ($fRQ-R`!%;Pj>R>TK@3~T0xuht80CO*{W7Dgf2(iveb^ zwZ+TbOED{&nHAEynX3^Xf@0z<6ag+-nb}Z?f{>`Wh&T$9c*zgS>8&smxxm>V!W>Bo zTrG&WCG*165eJImZmU&>6$?yG4O0-27=}Cu2Q6B(NMJ?iScr6))HK6_LWxLAh6Ey3 z&Fq{_t@6cyLEH+7F!Ji;P8kXir5Q^T2ep=j!MRunAq_(aaY%j21IPlO(dz78OLVGc%mHdl!E!FP+TI%<92`$3 zTg<`Ciw!Ne4)s!H9LCJ1mP-mu`4hmtVT{@|BlA_xWeZ>FSlM&;R+Cx>3h0Y(!83k-^9X1@JDkFMZ|m?OV4t z&!2ng#Y_EaIiHS+=y3nu=U=$}_>*TZz4%g)u*O8xpZU}?k39VFrOTHK)D0bXV0C#aPD+*Vy5%?e0z6idAg`Pa=p#eOK%gq?8(ekOYMzzb7Ef) zxYwxeI+R4@AX)Dfofpex#YLHTjo^ZaDpydq^!4wkZ4RuS2~3X4=+t{B0dQYu_nnBy ztgPoP^*jy=B-O@Dj6e_ijA~PnYK}30$u+YjAeaUUBjPk2Pb?)Z9@$`q+>a*{5O3`4 zpy@!di!*bi)ex2|3fzrnl9g2T_*mxi$$aBvd3(87PCO$ObsA4+)6r%aZy+=V1_T~3 zI3UQDPmW_V$z_m~B?N#E?j26&b58@ggIGcnq;V%W10ki{%|@`?4~dDhn@G&12nny^oVCx2}HWxmUj7+uuB&b!`)g zW&5GCfC%&M;};)IrJ9nMY$FmY%kl_d41K_G&vc5O$cUz{ujAuAjd zV=yZM&aOd1ly;5pk%_~}Vni!!C8vBs@V+=ptc#=y6b0s$rh+G93gs$Z5R+nBoPbUG#BC?Xszs<}0x zp;D}P4NruIN?I)!w_?6?W_xm~-Tvt?vds`hD}MzsH3^|Fy@cAr-k@m7Lw|gGA{x4| zOvCYgn(aO!F_`7-MvR8V%tMG|7MOxikf^r_}R~0K3epX$sPyxVioH#uBl`jF9k+KzF1v(?UVDjy!D$jp8LS>ero^rGO#qGh9tO| zS}9s4(~SyC6Pp(2vfP^6LT{eGFni5Y->@vZAN=D_HSKsb86{;9+9r~qYe&WG=yWxX z&HlaP*Sxlsz*>VQOo7_vDxIG0zx6GT|Ir_PWay=7Hxy9!b-NAM37uN0D5$5>dw~{8 zno2ron)K+SuNjIJH4#xAiWeQqbTl2c(-&TRB|9}RwNeUd2cMZ%W1fN5O$1Pem6E|R z0OB|N|1R!kFzd~7>-uAO^&8R60fkfBc6aVwed5u#zWT|>x|YA?-S7IN z-~Yqa@!{U?rUR>04|7$EA-Iu|n|S2Vg74hEbK~~Wx%204UcWx>no$>rVYqeY_WOVH zcYf?gf9TKt>`yC$F`I6*-RM7kjnz@Yyd6 ztNzI+pB#u*V+{@ z^V+u$uk;l&d2PyOcx4J}k|>0){yAYWINZp|ii&WEfgT`4L=X-{#7qhk4qggXBAbXo zN`R2L*PNq}hbk$m@um7z)QV~n4o(T0i913SOj!sd64%092>^9%SCUB!lIY|mXVacg zP{16S!9&Mv@>EsG|$6?BZ10mFjZW;qc{Zwdz-3&zWWxt5??y5*vVQ zNZCU-pOZxEdn1zqA}1r3riQ_+??;=P6gZ!pY*0r`MNbUAxwAbUj{`Sp$oKBuCy~v~ z&G~$GZ~wluQMg?d9JkxgzO?_1C3V3TtHeS?1`;z@*Cv1?Z|!cC!B?wOE;^oew+|Ql z)(qXoOZN`Dwu><=hMbBW9G$??wO#55MIm=pi*a=R;fwosZkk)5QDkwD85AHbA%w~| zK=!4?m71lz%6S-1&T}rzZd!8b zsp;+?9*){s$xUE&FC^wdnn59ma4idkR||C(&}1|ohJ12#l!uaYZpWQ8tg1w^4jFm< zAThCnpv6OEFTNTSX=!HtYBis2WI_=O)OhuuY6cVFx#Xgm$h#Ol_sGjG=t;lmSEtf+ zP1_Jr6{87@rZVQZ@RV|Ka)*Yjy1ISi64F6xwB{g;E(>(AAac5ikZX^ z!OB9+)Q}CvMch5-+%z$8gyz}k{`bH4ZQuMCzxm!#`lVn0@W(#&!ep}PLIx1KT8>R) zW+$tqsWB5U=y3Pp&C{R!>HoRgXxnc4zx^lw$EQB?(#G~q(=?_QW6V^7a^*aPS>0Nu zl8zqQ_FwvipLYzgJNGlc@W(&TviC5ka|?855w@Z#q1fB)jY zAOytCfA$kU{d*sMe&^h|we`Y54P=A_QTKw|Q{tp)~KCX%%`g{NQ%B|CGG^4s?g{hGPp$V$VQeW4w{qp4E z`JJEq7eCgF0c^KC{ntPH2b0-kHl8h08jZSQ%8al^bHKy}(l1Zn`E76f;lK0a%nq48 z_x$n`Pk(k$b@PfA&1W;P=aMGfr0B4*{m7qub0w{+?#ZB3O@7$yiqd&J2-1%3F=mJ24qfNQcB`H>&D_)LR9rf;^LM3x%uqMum99P zedMu+PVL-}{QRGO^v~|%ktg5-$XAQibljdfySKAF|L_O@@W1@QAO7^#?9!dUViD)3omSMZ@ljHue)^V(*FMb^Iy62>+k>g$3O9@ z$z(L1j$XWS`2)Z6fo9ZQy>`{z3}s{ItOve-|6pf(XKQckm20o$l3)AOQ#Wqhc;Tf> zyW2ZzdU|v?pU>f@X3P!<0l5@cSZ!1{t4l*O0}Fw?F81BkRVc2*Ltcv`E0t3->;RdO z69iNj_H|Y5L?ksj#O!c|i8NB9L$FGZ)%gu5m_yA#rCC!oRL!moiX1{4%@pP&Qip1_ z%-U-Ii*PfnhQK+eVKUoXJ7mCp%GvaEx!RmhDks*BCNQiPt9CL6xD*R9lv=040nUuT zvEizTLNt+-dRwi;WN|ullc{FQrL^3DWVI?A96d0(AU5Vi3Q&weisj5btQPf|12J^P zK+=?)r7jy>b53<==<4pmNkVCiTKLPFCQKp$99xe3Dm@#c}`(eBFR)*{qZSgDADaUAJ}TC_Q`S=)!Bh{?Bjr zeJZ22QKk^vY_>|nz1z3DcHA#kQawu`GYcXY9=dqV2KIxY?-~FyP5xARdf8alS zbkyv1?I^1{q~s(*HJefq${1o49!l@Sop1f7*Ic~##O+&0zxN-XfsebU8%njIn}FEK z)kOk(h7}2|SxLj<@BZN53SIch+uM{mWl@`jgMkXPY2#egM`J*t}ZxN->e3{esf+fBjegT)03k{C7Y83!nVLrJbz{ zPJ?HHqmd>`L{SC_Ik~DAQx}wP{id(~zVG|q>o>0c%rE@EPk-(PoWvCs@dv{|3V?(> z5Kz47LVx$pQ;+Yx?zN9M-|)6m8~@{f`LmC0K4w~qtsSeXaB-B<#2DNaoYZ!9Cx7?9 z`GIcK0h8x%o&Ld}e7=ik$kiOd1DlCDC9NevH7StNYG>NM=iTpU+wt4q{4LYb|MpA& z{v*6KYn+7PMorV64hv9V;!)e?zGvY;)F0jZfxr1*fSQXK9USx@{P1TclbLv^a1=|d z$*L&KBDFDFhyLNmH+J_Thk}s5_pf}%)1Uas2rAh^U~&f7K_Nu5dUdlvAW#Szx`@-8 zz&3`%l9z>dnh=QCfK*CoSP;C}T3lw{kWWcN+hdV2oxJmHZ}^Q5e%8%H2-)h+q>}Hb zZeM4L(z-?M@8#TY&RXQ#Z+P{?k@CtcG-%p5>PCH^)D%Q8tMmIl<$}|u$@AGnSNk$L zx4Yfxu;M9&w$YTu1xhXkcuBdPG~`5;uCW-(xa=x^6u)0PZ!7S zc&m|Ul+D3G;MJ$##GJIbbou7xmoGo|==KcBk zvqRQM(TK^RX5Im2Nz} zcXIR_zxn>KF z#6ncVr>tru0Fg zgt!5Zghbf^^6CjT2s0s^>>q4A@|X(`DM?Y!1^oc0oJ*eu*NkQ|pU;O<%!FA02({U= zgD5nByQ;Yd3YLwUNu2xY?uuYFaO>n0M%FJa>pD~gM=^IsGn!22xs=qewstl{Fa5Fy zM7=}_9A#C87y=uLnvsjdlcS@W*UbH@6eT5&W1f!0m7RDLT??`Spf+k+RqiwQtF~$S zv^qLD+L+Cp=(#UH??4E$ST6d$Ctx)0R;hO)Apy`vUnaYeSVD> z3B)zEKY7he3>AH&UHMZry5N;x<<{^-*m`>TKDyN?g4 zIte(48)YpHd)=G9X8+zNa_UQIIdoKW5GGZup}CZG6fHm%R*ZuA06S=!boT5sB z9PSPwirrYk^zuv3_bCb~371k9i_@*q-r?cl+3lUx$&HKW^+&${uU)-zc{F+Cr~ciC ze)adB+1a^RAy8&w65(iox(cWXameN5_~6~&_{2Z|C+`Cp;*-~|U;E7GZ*K0L192%O zvPct%QOuw!!jY(vCih2AJlg%(kNzDX0OxMp{%0S0`o(V4iGw7FaL&cmC9jKqUk<_O=tX}uj#qW9Vw*zB< zcel2G_xC@%gFSbp+DYLcC4Z1QAcy9q>T*1e|M_40>i`3@Z~2Q~_wi3Y2d1WJREt>& zA(SC8Ab`M1PNSw7QWlo!{DSa(gxTMG-}ip#6F;%NZ46N0T+Fw3-tsNq2OI(O zcKU21&}`fU&Zbr*26A<YQA#AXJklrs~%mMZiXap6Ef;E?i4OCIg)fi^H9U~=W^jm?c& zQ5}b7H7w1D*A>kGGZbV&$nqDthYsB>UuFoE0^#7wRbB13Rv_UE4a(vSSeU%r3&1b8TO8!>&=d72>~ z>AI=|tNz?WTg&B1H)_B6-S1wm(i@(7{hMC%nj6=zfBaLQJ~~;sR8ZBK2qh==Vk#_7 zbaHY^L@~%PET8?{XUC)Q=4|8e=%|S9?(XoQ!|`G|>SEiZY@?utkXvCmn8TDE$}n>z=QVd?D3$`KDvP)o z$7rqqu33lOk!lW2%`pyvH&b;VVvQgU1G^5zY)ijIaLlzoLT+O&1 z3>rWLZbXDJfDo`l41j54W1Lo9S<)n+Y-J;#I#S8;8aXo5axDml65QVB5HTTZu@BjFh|IUy9z@_tB{mDUzomeCQ z03ZNKL_t)adeu@(2*4yrD6PepZ?CT2UC{Q!o7<0GKVIHFnt?RNk?TsNW_C~I@O}#f z^{CEW%N*3!Lt4!#g!ra6zv(MqegU#XLUSfYD^6^Nq*?%p1B0qtaU%sa>nhGqKJ_{? zoX_V0!;t4-Ftvms6o{Yt+*d*~>H4l)bWPKw)DvQ;L}J|C+1=gUgL?Dg!>imxVLi|Al})(Uyqui#ty*f z2ySXc5s?78)D`tmiGy!%Z-ONt1YoM`*hEKnEDokctGaRkU;(rt_|~>9GjC4E92o!r zq${hYu1$-u6mk>l zS1re?FZKOH{=%1TO{dez#)Uur)91$HZDjW1>Yhqr<}!?22(_4LpBToZ z^633LclR?hF&i3yx`~^WlHIK$GE@Yu4b%Wr@7xtH5EgYXyr{Q7ib&j6s9#9(O1>%*zJ1V)#wF)I zB@!|Bl(V_VSP@|=TCx%gRMQu4p1t(aK0&ZZS$xRkPv8Mfh|! zJHNSk{m$Lzzj5`+$Dg=&Z(jzq831@;mSS{#badg|bkw}=)$9AmC$|G{88^g%iF2Qb zbIE58^H|$M4?ncEx!I-`)rnaF+$`lp1dP77z5T_ny?o=&3ChlL*_mcX@j-6z8m)i$ z)y0g^0j+q>sTGK|z{+3>q$%%>_}r!QpZfISFZ|jceE;|V;Kj?O+8kZDa`|k3iF@Za za)*(}Rru=HzVgSP{?xnv{r}(-pZw%ko_Xf+CmvPvJNviRc$~p^frES!2i0E;I2n)Y zCYBC`qqCGKbtRF3Bjq$Qosu<0^5E~c{XO#|KG`j(lm@5Fes-g1`r*<9^vV)2UhZ)JBI7A>IGg~_c)-+;t z@WJu`Lp$1hz$L@rAOa9(7-%g3{F?vS%#dNdSRwEL0stVwVSFbd!-_}DGK6v+y{v~~ zpqc=TEdT|845rQrAZ?$Y-n-Se^AqNcDFFkF$J2ZFZl2rOi%kt^)9K{o=ulV7dOU^s z47{vX?Q}8?nblc| z+@PU)j~|;t?6nxM*tE+cSLf~feNBIqeB&{+;+~+ zwG=IdWqSD$J)IrT4#%EpWktszO2491R@?8+ArlaP!Q~cJ+r}efJN%@u^21HCO;;kg7AMK-cdaUcYy8_bfg3 zo$t8t#2Y^Pna_Ul%g-O4o=vL?M23@v;x0IS>7^Ujuf2NZp@)yU9*1rF@Ky_$x^&^v zxhI}Hed)#Ph>Eg_$%u+u5s6?Z0-nIk&6vN`wVfMq!gwUooc^Q(p zT8t=eZk>PW+6nN5dh;T{_U(h4A|g!4+-r#(0HeYxgAxilDPVR*8l_SLJkpFd0Y;0? znkMGl69=RLEVxHZ1W_((f11M`~{=q-_`Cr;Qcb-tb{>@kG zsu@mW2gsfy7ghxDfk=)>LV;^D__=@j%NH+P)Iv#VW4gUq%pDkj09nll7|Spoa3urA zw)fMv`Nd!PgPpyHl7}0w-rL;VYIA2uz+{GM=8hs%g$NDc%J^vd;Xvqk5aEm zefQ#pF7*mfOiRuj#Ig_BKn2fcwUav>FX7L=eEaUrTZTN{-5R=7%!~*CE)s}vU5Id3 z%}g%!_Mg9eeDz=}biOrO1whjo;5pu~P2xGO#qYr-Ut5>hy z=u_F+*=i;`%kC7IdM^ex{2DbiL~}DVXPVF3Z+_$Y7ryw7mv7vxLhS|W@m4B1r94!} z6gXAYv$;s&|r_ITP zNS0kUH2n);E;i6*9B{TsJDZbGUHQNVKk_sG^?xyL>aHup2ZfAlPK=iM?2H1x`OQz< zz58G_v-#p=*|*xNn+Nut-SOte*52MZGw!FpY`{2N=-Pk<;-~8M^x%|}A zarF3wN58ws`OsiFeNbB$%jqlMy79J)Z~fkPes5D%v6eSJ{pLv(UwHAQygK`#zx1Z> zc>Kx3qtmLYLI@Pt%?L0Gk4DYz-u9J89{T*}zxLseJtMRM>N)j{AwpGhN?qUP?C!IZ z)71A>HO{N7$-S1qQi{3)5rQy!Q2+?+VM5fPFOh_K5R`zrvM~^-X96Y^ptUn-u(%Ua zF^%MiL^wna00y4rP}(}>!}OlY8kwQT(j0A?m@NAF;) zHC07s1rH&tyQQx&=*&$K0=TFfngcl@A__ra0s!@a?=Aq4ES)V+ZuN^J6EG~x+3C65 z1Ek5;Snm71ySHAyy9K#lE*1{?^y~o&?KD@wRneB+?EbeNJo&b_9v$s#-=55lw$JaS z`Hf>)2bQm>axschgM1$ZvxYU{To6xLYRy< zlc`fB64@|p)oHOPeFs2P*X?|UOiaZO7$lSuV3vv%3umKr;{*FW?Z?j0QvShy*Od3OF=)m-BhHQq?sxZEsFYdkiva z#%>0nG|0^n`;-?&k4#tJK7QfqXa3W_{@335wl^Oh9xeLRTUPahUdX`jiaz|0<16$2J64r;DB_l)K8<;la3Jw#)U%^;t)}GB z5y;G|0K!Bv1V@n=S*F_;Ub(gSM?do~zVr2$56}8P`|2y(Tj!YB00IyINeJL*#W*5V zH6khy$;Qjqj{fB@zh`f6=j+eEeCyu5@u-Pmv`ks8NDxvZW@JJnG;qRV&T+DTfA;@; z@S|~ z-4P6(i9}p+z@G?-shc~qNSM5O<6hg}Hcd?}Thk2#F7B*ONL7pu9!S(Qm)wj-)|)9y zwe#S3b@$%2t}o+p9Rn4^Kx_=a?BoCl!fHJrlw61d5M-5Ao?N@NboCIZuA3NRDkanm zL(|k1(IPN0_bX$!I*xLpXTG{$`a1|9HCIjT#fpM(Ftdh(nIF# zQ~(9YW)vlas+8WGfP#SZnlzVKMQ7OB+DN^%ov~Dil5^o0U5z9-QBuvhLmq96H`-Mv zTsC5)fcN(Ib8f481jG)WvxQ0=ELl+p7FJLKL>EK6dGC-3Vuc&ch$yxtn?cH6Jhfdn z#5a>>1+zleZ=F5<==qmkdj9u*?|pyw@BaPUx9;Vft5_j8;2pshHVfx$1Kw zmMT`G@p#mXupR?cn>Bp=Lm$ljDfZDy&&jeupI6xmA?4IRbn(Kub639p{EPENL6Yv| z$W*JUDJ7SZkO>J5z=gR{|#-nO6JDYAcuKn!jZnr#1+M<&gyY+{+ zu3swMH=g@~5VWn`e)*+`UiTy=^y|3 ztB$z>3{W(1<*vgR%5x4PCG`cYq(VsJaRcZr#O{gXa1Y6sur^|0X_tK49clHmCntIAC$mH&1zFhUa`efP^ zcf*ZueS81vD>oj0?Ba1g)?!0sTR{Q9)fe;S-rmk%eb@K>`JaE|@WFn+xtv~PsKTQ?%*)2Dw z8|LxFS08-ysTur#{tHz0m0=KK;d{prs^pw+4m5+v|=G6fjW5+Fjr?1&YHUc2N4%*W$N z3gPOt+kKaXLo;fKQPq1JkfTsiVjMUN9yt`iocmR2+dFNHp(5&XV)wdg)-)Y=CpW@6 zR8SPwxmYYI1Al^Sjj+x z3>z4kS*%zPv0RuqfvS6q)oR&ICez8*M(n%3BqnANaWc&XwPC^HsOWAX#DPy^=zZ!X zNQ_Mkqwxe)6OadBE$Rm3>Gy+E}gI6&xR_PK zL0H`o$kY@FhGTWaaW$$(n>i=*60sJRtVP`ek{28B9A*Ygxu`RnVYgbuNZYaj=1pCh zy8;n0W(~1IEftBEBE(t@%mD{Ru!;nhFdW>lNO7kqp3T*oDuxh?8MwNc3Tbjc9&e2h z2~FIgXhy=^caR}a;24IQDFG5OFi;@^D(Y%36fuGmO2r1^kk*0&0b&{0k4>z6xQ0ax zu*)4)zyaMMs|zB_sPskMfO$L}_eqIyJQ;(7sXOw(wibzd<8jeK#8nJtuHa~(*_l}l z3=qr#UCl#PTY{AFk;mThC!c-(`@ZMu>z{mle}7+H*^wMc*bEd<$hG98>Og=#2@dpKdr|jwL#kihyzc= z)z)DN7zAeoi{)x>bm_*hv)w6OV{7` zp+5ujz=mkqnXA$JKKNc?o}Hd@DQ|n*oBNzMHm0ZZvs3NK7eiIlR`VGJ+1$GF`lp_H;)y5falO5<=_I#q-uT2PKk@wY zF97oP)|Qs+#+6JFEon)`v=})Vc17j>X@9!Xjp?OTU(At&1~&=}bCcI#9A?VQ2965I zXoHP)@TcN>+A7RuPRL+3j5PoT$lCz3a2tHlL*>SSh}I#$L1qLtC|e}3yASd#LcyV{ zMgtnAFmu;-rLG8h&?~O-Er5bRKm(~67!gs_t=Ni2la0{?z!0kK=5jfWCnxt$4<0}T z#Z+CPBf#x)wk{9 z;D9B>Pz?$)GbQ37UW3el;3egvmJ(UvO4=@I&Y@|n=yW_bE2S$Az!KD*S!Rn72 zQC)ETO*5a(05Gs240U2a_1yKy@V)PN`@OsOx-Op_&6BnST~)C(@yeyW zjp;_;<>h?g=5ff4`?}&lY&aca910SEQ%V7R8@>s?D}?NTBkk@ zC(6i3rierUB#vwjNWk;evcj;$RzwPxDGTwTpL#JZ{K zx-ruP2E~SW4G5vr@COl60R_j%v8+i=)aQ&LOeDBl&S?M-fTOC0I)bPWX(|J?27y?p z6kVJx0kLjsD+13D8q6-BTjfK>=d zOED|v3{>3JhfE$1^+h#8CNyUWUCsh35QNt8FK}>#qD80z1VI2scdt;?4Aw_3YkSD> zQe^;OSx3BE?{EJgb_)QdQTL1n6(%8;FyyY z%|V=rnZ-;qf)PZi+(Fd>v8hW%E{GU%mxY{wi$QS(2kp!iO%;7`3pxQ>&e?TuXV=v^ z2%0;xBX=ni4v}vFBy&?FVd+z;>blP}Rg57DOABCtMgZvOZl$=Yv17)R`cgE8Sk!lS zx8C&h(;xi9KNLVjRs(g9As!qqN29IeTmR}8-~03b^k*+#-rV0mbPtMHOa-vAp)zRZ zP6%3xgCm+b2n2Iu1^@>|Ll|H?!v)C*7aw}$&z||lul?>HhtY+j`F#KW14kyJ!TL4y zO<)Z(a~S&Q2tYuA91Y!fH>dZG=TLGJD)B|XY?~NwT)*`b?|L`9?#;BbcW&oNZ64_p z0CTT7qE!<2AKX7XnlOzOj*gFNiKmN`W;{a0<*F~GJ3F2i!;8C;nk0P;`ztk@I4>-)aRfWnhTNwm@5I>aFFBZ zww4+KfE%pWw>5Zf$ke*|khit<;ynB;5`Z(Ifvuy_gn)w)n$2wRDhyu?*h565z=UM} z7fyL60B{fqx$A_<%!vnV_#m7D29(#DN`?SxL;yg3d~&Cq-zGo+1uZ$}(zjhduj*<% zs*aB4UDvKsS66k(rS-N7qIYk*Y1=N4&`dR_las@~UqnGG70k|3TD8k#lGwNN#R;FD zoaT1PTs=6rS5+GfbhN*JdVCV2c+s|7ls-EmpetxcTE}9jHecms9sYD^vjRFGlnyW?x#Exjr=o#H(C8gN1g{!aL z{nQ_S>Tmq`-%RbIFaDaD$JA6%Ou@1)@@#u^Bka+0Iec{)C^TU7g%vBB>2gmy#{Ls~Z{M0|5x2ySLIo;SgfByX5xpODS$A(Bq z90m@Un3xsvZJkpllYZv1$>(oO)&f zFc%r#>5#-FSaGT9Q9VI`QXD{$iJ7yinhKziqX7{nH6svaP>T{d1}7?p#Ic!9g`{m; zHv=Mb2WHdtDX*+QXCNkyQGqa40G?E7EdT=wQc4+2l0@uC5+H_^qZ=~5pg5;8C=6>w~GiAcQykvKBAF%qC4m;yo|5JEsRkM#(I zQ>Otr5aptS10EuSxjVV=CPHvwS4sS}wY;edxHVUgOh4N6CjG3VllhDZT3QE>=NYDU6j zU|lW<6r+>^s-U?ERbPhQxtJ>=1CaqELjfe9@pz05M~6qqBo;dDfh0=w%E<UwwY;g5gfE5Gz>@9%IkJIxQzOucIARnF@K zr>%R<{+cdoxFyY8)s}s0>Fo6MeXUJL>IPq9y~Z~Dr#!vp1F?F zR8cB)0{{b*iW=TXqEZP~3HK}5_! zf)q^yaU0NWaHf_49x!(E(yfBT;sqE(=L@}f`m0b4DZ9}^-(-10=5n*rEBavw= z87`i?JPaERoP-Pt8abk&$*96cvf8X&F;R@62MAR(PiKpnUbf*ku4wp9B}Ro(`m|bE5CO8`SyJ+_K}HsG zX8`$x97>sXOQ33-u95U}CNx2CF_nI&!%jKV>3&gdSQ&A@>X2C^hDO3q#kGPs%dZO+*o#jTL@ zpj#m%aNsIvDTodR#S9QQ2G^p1UDjk;HC5N8zLYK%ktiZV#dv_~)y+8d{cPD6$6|V*DnW*p6s`MCQ&K*~AzG|gzSj5al;%loFk~ktLo2Hb( zyw3`*2+nBkH}Brs+}uVIz(`OO2R_95al+_;&OzE)UUVx$sw5tr9EGaBaPgvMrGXvc z5-6IRqB(e|xws>T`FwtSav~v`+kCk^Jzazt03n7@%n%4ghIP}jkqCJyW{0OoN!{Fw z>8j67SAroBAq)lB0qZH|&Ky!vLd@=GXUp7YVllJS=adyFsP>3RA!Ic`cC@wK8Z0Xu z9v$C1Iwk-|5{^d)hdaAF02rzo0R@nV(8F5e;!X~Rx|l7Fj*f`Pm`Y!6-nx6~(nSt& zh))uWgJ(5F1{x?^*!BIv(XD0bOUVR$bb5+6Z;r>K5JCtct|{$^P6Lr2m{ZaHqoc)q zl~M=D?zn36H@^A8!;d`N)Rh{#hyu1L50n5RL87F#TAnWY)tkQS&28Trcob3d7+AF^ zSR`I8m)+7Hf9yM5&;F->_MUhBmAC#!fAc@IQV^&gU|Oz>U{3CTLChmH1u)O+O-8a7 z3%a`o+}t}KstbSk;jjGKZ~PI)?c!vhW+?^%2Vp6yW}x6i=*5u+i`2U2f`CL6Q5K~< zeBr|7^B3BRrA0>%b&RyPQc#w}a1&Zp~Y`z<+Ai+y6 zUfSeXGWW}?FTQYkcJ}#apE*7}*c^|~UAT-68`G`Pbo|bDyyL>o`Fpo+?p?lE!RY?| zyAMw8H%&dNCq+lXNDxqh8h}Aljh2hK7OUz&1KG>K!HX4e1@L~=CreJnB}$xBlX1IT zalwMhf!)m43=2nqtOa41ak!ZeF$5aM8SAsML50FYx?#9S0M~SuHE?A;8n?9--T{ZX z$(lE~M$9uJ5U3U$PLzNE6=>-5557i1fRvNv5QK;&NEm2pswxT~fCM-Q7XZDaOy;#j zP-kM-&M@~`C!^8q=&H?^ERDO>5W zLkez==p5J`D3`O<=|(#$S*y*xjq{gI_HQDGP}go2t2%^AmmNlLq@J}4Mv)NQT#Ff4 ztSdm!RG0;kOx257-;szHPiYAVkXyAJ1Sg}WPm9H3X=dZe7*JE6=4}r$Qa=XfSWoXA ztUmRpU%Yek`Y1GPY#{?Ocy=@$Fob}Mt|Bm##kh z<>yXMXVXHliNpjBTF_aUkX%enVvty^Qo3=kd++-`{9palf4s4=ai(g0c6DNQw_&g> zgJ961cqSvWA(mQjE%@c(9fO=5y;xx=O{gZ@=U#ec|DXRKzhm({5Lzh#;`hA$ojZGb z!t~^mPu#nA@7($GpZ=3Sbpk|kLJ6FUA&_ceVgy4%Vt2%%kR29nD6wEXgAaFN!FqB@qU<7U<1`0-`6#JuYJba43OlTVgXz@eyv6=V@&KvGq6MHCXw?ec7PIwU%^*nGaMt9m_hMs&qt z{)ym#>}JKyN-0HC)?|uEMeXkW`{#Dg)uRy_^eLGSr2F-I39y)%nI0XU%-c4wIM}LP z9vvM{Mw1{B5zv)6IASp!oPiFWQc5Y!=L=0*%n)F{Sl!#dKbcO1g^1jcBoe^Dq#@!y zB>+DGthA^W{QKRZEQV?%jLc zvO~cbqew`73L+wbk@4J36Z&_r3G3*~4EmwIm88KrBNhHwvfExfHARvr;OSKHJ^H2c3Ey z>na8kasxFJ5~Cq0M19-N=ko_ghg$NenWmBj;iaor5wRMLcDFXGSPf73we_uNDWzCH zpD&M&Pu6t_$F4g*ozFHV)A3}&%)-Ppz$`N{AzI&+lFMv1J3cygu;C+~_vv(%b~ZOc zjB7(B3HHf`i`T8~y5(|ta&nscG-T$`{C3|R9NypA-ffyutSUffB%wSoY#dP)R*U)3 z?5OMe)F}{#$Zg4O>Zco<`A(;gxR0y$(vF^J0&D;0SZEu9pqo4Zx^;d8G z?vMVpAAaK-p5*0WJD&-2p9?y;4O{&(%!M7HP!426f~BeJs@@!JK6K;u;cx%mZ+-3y z-=?@hSg|mb4#NOh5uME3qr}a6{ObL~%jYiuV)3j*qpB7F zb^=oXg%kkKb-Llb9QBLQ&g5{pcYYJDs723zskL z?C!ku^0%92)Xo;GW$L<=(`k6@5deMa^{=C7ZE9fjtB>d ztb5U{r8tO#^Tx=`7Htc>31M$z@38<;U)>)VFwS7$16JDsgk%6yIXJDGLxw==KLUN0r2ib19>yy1#$0T%PUh zOkeqS7sg|-+|5rP+`AdjwdrBvdOxY*@m0e0u%va=Ey4<9D5e5J) z3lBnOrlBNH4&>+#1&71`p_JxcH``6K``OPv|9^epkB?WCIc-j2-=}6e9c@m&{@imX zXQ#_$d*#wYKk%2o_lsY8_Ug4)LZ~E2+b7{lhX-MdmXe#tIwH|(Hak8$?NdrQZ*OmJ zY)tRnze|D}lZ`;qBL@yl4DJf9swEdKdDX7kwy$EcmmWTrIg7>!4&+HQ3Xl^rv>$)s|g1QY~B zm65VM?;4m%69PMK6)l(fA}@f+%p@8zXbj%viqxPQVnC`?=N1?1x~BFc`5k{nKnP%Iu`pQ;V*c00*Uiae{EW-=+wAjC$@a&|DK zAt;mUbbAUgnT)&LUePYZrX~M+JYfO^2vLx@$bFV&p$V;4dvR$#&vFwmi^PCP&bhj7 z%Cg)U463T$SYNN|3K9f8C_7Zt@vyw~@=M-v*PS88BS&7}yLa!*Y(Gd?IlDX@j+(jx z00fVOfSPAHJC>-eqP1u5?%ligg3-~}U&{-B(ZRz};`!B;6UR?(Zf=8tf{eyPLe6~V zGk@;h2E!Ovt#3Z`&7-gU z=)ODe_{X0ez5Bs;Pll7_^L2=jwY;v6Lp_k39d z^d@`&NdQHartM}zLNiHU8Ddfs0!piJWK0VxVpcWBY@$hYXeno#82yNeh>#XWrsnf3 zAr-PL53x)c0|bmBj=&`p9fGPUASWME3~^`uyjjfiEMrm;g;0Y7uy*D~qmg$Ont{cp zt_CWtP`h%NE%Z9WjdRFG+Q4Wh){~sDnGD*L#o@p*0x2;S~gEUrh!G zXjslpwp&a440yP;RkYiT7(x}b_MB}Gcjo%@ld>F4Mn$`gNXT5*wfCMqn*b*j8Uc_( zXn@g}QdkR3k;2aT_0W`AhDAYV&K^H~;@CxpuT=>lO6ChR4WpA6UohFT|Hh|ZSsM&@ z=DLf5NQ__>vB5fQ0~O|3m(YCx!HD$4jK4hVr9&G#25-~G_{p8uOK|6r&c!mURK8yWLoa zs%#LOD57er!bE21d=_FPqE@GS>E&~x=6wcWs@5us5JS~82xt-kvE6EsW6#7s_MCIh zAz}#806eoJ_MRJwh^!I;fgLAV9iSnA_a4zXN9igF3Xa)%pXE6iR8^f$8dL5yVR~=@ zfOCw9jyHGVwW-o)H$agI*bvu0o7LAxXhX9D!G|lGb)?hdwL{$;dPNyRXtvp|x zo1dSb@Avz8o+DDz)G0(D*DPz;?UM%m7dnEksBi^%w(+5|HyO z3I+&d-Z?QzK0-?_WkzO)q|7eMy<-PP>>L893LvUL2n`X27+XcF-EKef$ivS(^X#WT z{pqT#TJ07QJLl5+jhPh`rq99DVIV*QLPw~kh$teHNvR^6Tbs{4|FgU9x%al4Z^^UF zIaif65axO2QsN#ks5tL3=TNONNgft7R^9@#x^4^!0YcLNB#%s<8Ba!&R;%6ablOK>W8%@MTwY#YUtepQx|O$@CPWoPD4WLTt#mAgSqExG zo;mMlXJ$4wx1MPgxu<{fbaF>XRL7(W>PQesB=;S5F<4*^0$6nCTG_7eKY8@= zCttk!nnTxIzW309`9lYnI$2wdY6$>_s$`%J#*LmlwR8Ub<`18G>4le1C}&OZMW;vJ zi>io96BG>8qKFZufV|pNe*>xXk7z1@V1&tTIG7A)`f;}3x4Mzgpg>uNXf~`XLI%!Z zf{^!%D{m^zy{^I#jEt|t#-M-ms%6x<-0w_AKQ5Y@HJ+o_?n6L>xjOLu3FoM%Jj#djK&2w4{xhx@r-@r5BZ?Cmo~-5F>I_%?O*OLC>w+NdT!! zF!foE08-aG>+4N9+`X_^j|Ob9%Gn$5nwwu+KR=1pnb%)loarr>gBVnxUO#twacNgC zFUFIBNyq?0mhYOKKeKXHHI&2d`26|q?Cw4LFWOo?&CaF1iT8Om4s~6|C}tRAWJ(KK zD+ePpK!y+_aYm+uR+r^?U)q1gwe6(~;;2EWYw`b4#>hig>CobH- z&!P~!jB|hs6H|IGJ)_QGrT-}S)NS6}mQe(Qhuzy8mEzcU>6dVNMx z0OqW$1FNBh{!F1JqbdwWVKC;uf9U0BUp(`RAHDyggG=M8tjZAU##ABz83KTUL{T<= zbHt*=hK5Yu=Q;b?7ml2L^vNfleg2Jcq$*a7QU|M=7^4lhciwydJ;RMv-|k;=)z$y- z#V@{cos7|d7-DejyWM^Q2DE!UA{JHWoO8b2ZWGbY_V(uHMp>0$06-zs-gzdSIj zwGPn4l+hs&F?i2N(s5Kr#aS6+GM*=H{}c<`V9 z`hRB<)6W2iCYt3L5!F>y6a@fRb=}mpfibi9OzigUJ&;6|A!YYO*}L3(Qz+}n>e^aW zR$>-n2u+}50CA3;OT(nHs#PrpA)=j~A%L>;F$$Qe##T{G>Z&fQnO4snMH2!%ckbMH zGH&WRQGbw#nN&@wdP8 zomXCYd3|&9l1mOxCS@He1R`P!A)-=}V=x;NqzWbxf(Zh%vk)6oRLP6h+2!T4=hnXd zt#1#9lfl;3&R~dyXqIPefH4M%maJH2X)LS~8$f09W+oz%j(e)pgdqSC6DKzXMiER1 z%O*f_n;@japQywt0$LR-Z)m0fnCERoO=~OwM8G`rke0}55+mUBlcuUkyj+%(R^DlK zT7%&ZA(>fhA^?RL3?a*=C-`(iBxD3KO&JhNage62ywB2|A%vI~cPWz)gM<*+xpq

VfB7}GdvSqf|!%(P+g!T=~|R-mdOY=|i|x>JsGY!m>96ZAzO`plceyx#u! zeYbq~o8KO9p6_=08Y^d^m-+2#EYQTs<|jVz!1B4_m%sk~+B!vRzTJhoi7J-+*39hU zQ$IWUf%iUe&pq!Rl=7pepMUYiBb`ovI2jscDyks@i=iTdDUvU0sn&NIb4AuJIM31f zbcnzNt^u=zaKv$I# z5_!%jRm)+Da!Ffao8AOTSv3kobmYCyJR=fwf`n;$x<(V162pWJY+5%2_Ri(&>sy5< z6=j4ydl&lseqD{hz-N?sH`DDMyx`zuw0Y^FLr?wq2lcq(1zK2KB!qf0-m`ZfBKCIg z?e%6(zVYfs7hlHC0os*UT=DWN&o3-2>^*!rsCGN~Xt=q$HCSCgdHbz*ZtaBmeGBs! zE`-fZP+?|ZM{^6%?!a&;TN_+-fCxH00D!6nv2@IXq6^(Q7*)^x@QH?;Ly(qu2g|P= zJ$T(s{fiD)t0(KNEiPJYq^LWCL0+^#O==C?bUJgMUD~%{R7}$d6IDy}$=E0oWbB~h zV;F6&twd=KUViD;%F5AWN4j~Ypdv=dAmhA%0~gFoy;C@>2FLczb^gP@{ng+9^KU%y z^hwGWVqUGw*&FY?;yoX}i&^VQG!;NHkiz*|>#fmFJMUh1{gszpa>eVfto+x{efAR{ z{*`Oqa_u|r{)I1n>8tHd$GHrN30--mLlJBDUdjQ~^xO@JLBBdP&lk$2e_?Az72*&fK>eEI87KYyx;92+oa5TsT>l(f0L z=BlgS{lLBV-FtTsD+=cjpZxJtbBhayFTS*_WPW~6e|BL~R#nr8N>x?uA_s#57hEtN zPsDU*Fl@E*POo=r`RsT&K5$?^0xm8r_B*{vS*GeRptV~$A!v|RyNBL4P2JRW95v`z zMMG!+u&hb}aL#8g14L;;=2)8G@{F7xkE_vWyfYj`l~~oi+1aM4Ha0eQ@7}vGw=iiY zu?pR8|J12dh=vHu=T_UDc2m`p(EwDpw|7L92%FF(s?ww^HOhE0HnYrS-h1bL@;CrM z2w`Vu(1g0FgU>SWJ({&zEme&Yk+`laCTg010C|=*Apl|wVk%-HD$Gs{T-qY3`OH&F zzo~*+h%s11GmC;uhG>9H6q?%Ser5UW@BQxY;mRPd001BWNkl&ogAq z^A;gCO&vl5z##-?P6$_f^NNxra72(&O=`e|F~%6vdQ1ZVkvCONMrdXe^^OfdMae)^ zWm+`?P$Ne{Qu-TJHC6O1UE@Ti0B}H4MIs~;jfhCZU=~%uF{)6ATg)zd}E@C zQp&Vv@7|TQ^JiAip#e?Xs!4@PYN`Mk5;8i+)@k0+k zk}-!E9J3mD0uc?OqFQ8`sWnYyfTBWRE^}Tnun7EFo+TGk|3Ob%l($Rq!1%QDF9Uw-HsEAXPn1#9tO#_xHdgLbYfy5W0-0#g z7%*sqAR@$mXJiEZW=I>`00gPs% zK+cOqQ)6~0nqII8Y8F8WovN}!0PJ?!JA)=xlWw~^8kdkUXa&TbJ^Lu@W{B-;Z^r{S zjJJcF+k!lU{yeCGG|=vz-56cDzsF<>k&(#=MU_oaM{DQrzUh*G{mFa(^2=Y}SUcCw zTXO|nb@74ce)?Q9*tq(l&hB{{4cKQM)FC4RQHD`8HrVSeOv;^af9J6WAAGRf+Bkar zOhlYCWtL|Ktd6N*@0|ihQE9}ntIKj@bHf!a=i3p$c~9gqu~C5E+yEFs=f05>n28uN zx%34C#B{JAW9Nbh0GbL+j~+${BF5y9%~S{xjZHP3brn)OI+>jlswMTJDVfGGZOP35 z(Ystzh26wdQ#K}zLmAOT((c~G3=9cDz@@e|Bmy8(6D2R)%-rnyDjHe4*KNk-=GFkn zg*vwLRum%N8I6vw96z>v?lhWBMiVdy(b(nBJoV(-+PS>QPMc==dFj~M z*1`4%?|t`!@4hc;7>!0~j;7URRa0U{gW+V9bJLrhzva$rG4L0@{CCFmp^tv#si%Ls zdVY0reo30fNMaObWTvgbjx%(gAx0uY#@TLvbLhYFy_diDyl zC^{GnMdNscAOFaE?H}L|{@@QMWwmS9zQtX;CRMfnzyU`7{NH|ladENTYAwvoUvu4c z|M-tTdimv7_V3?+k28__9mhIDTSnb;B{a%#-t-cK@m?ui3SKcfa3TAB-M;_~BiP3)fzE zt(uNU!$-dRNL5w$-*>+OEG;gMCzFT1_06iT3+5(PsNl1#iOtWo8b)kjoNk3+sAd3B zgpmNvkYW>nfY~8H)l`_M5u1jHq5=Sp9U|5-0%(ll*kyU9DrjJUjxeeKVADi3Rn@w# zrmsA+Jj;;CCE-TlbUHRbLUhjOj+?qMfU2se(0n9`;>b01$TAO#O^7kn>>Q=mF+k>= zh`^hO1T!^>0B8z<00BkJIYf4O=9L_YMv-Y)+k@wnk-|_n2<*}|%@hpSah}cxDI5Rh zL=ed!l4auo$!4CqDu)+naYU(<$eQ zQj=y1j!+Yk(3sECqDUlNAc4{kgGNLxpQoK*$8vJqY89%XszO!PbyG7zr_&P2%c>-o zYlvW=&QPSql(jo5=`M|?28cu^0;xzWO--aIR#$c2DvEX#B}mbt`}8hML?Rej}T4GRKQYpM+^-8^h6Ad)7J`MDu%El=ZsS=77ze^ ziWw1lBvWH%H4p>O&X6!&w-JpAnbM-fQ~()L{REOBj}%Q}WFj;r$6)A?4V4@srmYPl zk@Fnt5Y1F0Fp65y?ID^%Waq?u3Kt`OSa#{EuEa+4$~-d-iPC z;|B9CN4JxmT`TwWSw*Lx34kC{AS3y;tzn<*fA!1nyZ!pZU;5g2UOm3LcJkpk&-nPct*<`v*c)%08jh+w_kc()R~1gA zU^7c<9?xdL&bd5m>e|RuBj8k*XNe-0Qp=_|eQ->RKk48QMKbSHl*l21s31&}R7m6r zR1}n_Uo|u&Mw|NDQpG4eYH-SxGfTM`g9L>_A_ADwU63?|e3g(uHAXd;c{2e(Nh3Y8 z>4z{W0T2<1%!H6aY!tIr*6nq9abeeTb4E?p);HR%PF0UP-A>+_DeL;gu~$Q_29j~s z)Ybag<4fxU~N#KY9wmZS73D zbFIDe7aw`y*iU})dRAm0l_yW$qj%(sE_Fey(TbR|yi3KTsV0+AP2>&1XGNZMs;Hrv zWV}_PKX}1~bzS?+RdpHHW2e*JSv_;~>A@v8+}_%Axiu%su&EK0iF$0DL0K2wZZ#Z9 z9UWzj1VD7{*3RZ;r`tBuyl6ShiN<-yNmHI*IZ;)0r`yTf+0j>zSP-B2sA|zdC`W_U zg6f6YE|UT0F_ujo7Iy6!4F|pU+OK}%-e37&{_p**3-7q|=BBA9RmJGYqK_01j4YU1 zG(}-gQDtrWe6KyZ{qE~FH?|*p^3gqe55D!5o4@q;U#hA)&pa|&43kM6C0=~!P^aBm zIe)H^hK)6<+Gt^R39P@ix&DnukFvfnGgHhj%=UXTp2NcYLc24gVkgd=*xngQq@AtF z)_7t?M@m!hl}wsgGkXM#AOa|6v2I+ubMa-DmQ~%<6%j^Lbg*~to~E|4j<3Fc+9=|-OX=(>$A^2_u#wUb@erGIrjRo-MjZ5KYrq>tFJzE@K9Bi^NS1BXn6F< zYjZQR%jcHI46G>%p?++QADN- z);A^Cne!3N%+R37GqIRB@v4!TlQ}HGnSw?SNC?h5Qzax*HAKqTqPoO30OLgD1~iLc zph`Z=f=IiaO9+#u&a%v>`iA4od+-?|?le0YL6+r4M1U3>Buo(fm^q&jgYz6>Kudo~oE#%*TV|4IUDH$v00lz9^q!_P=}Fuj zBw{laaO^w+QR1ALL&!2>BA+|V$Xjpu?Ah2@Z)Rp(*N!NCNYbk?{Yz+qh)5_gN^H9A ze!JE7-sb1Kjsby~X)>JTdBNUoZm!jJqiQP6!tC4w?|RqkZ@hkPyS>`jJ z8B;2+Y6Ju@iWr#ykuezxQxO`?fV`Q2rpX>yFu)|8wP_dDG|g-rvx1@`B6(sJF-|jT zWMWE@2qGm+FG3JWm{e6$Fk)mSRRu^yJ4!FnG;Ib^WDaC#hH35t7=<({FbD#XQ#1!; zs4*tqWmeaspfR;E(2O{m8leHi5XV*BgvbWbVwM*nG-XqR0wWi#Tvehz$VP*suRn9@{N>kNe#uw9`qYz;f4(XXLI2`YYwN9+o5Xq| z&2F%~-9e&$XC{W|GiM;oWD079wH9%e!}RE>a$i3h8o3L?=M6*P!4IgwIS zJY|W|+=OO|RKWxwB1okp(L@jh1VCkUrUXO=KtSm!Xr^dnVn5f4p-ue&2q`(1I+fFS zZW0G!0z{-b7NCLvD1wV>X~V8+$RrX|1B1~KM722ed;*qL$u8;sz-h7}6N(rE8YzMY z=(Rgbo@>BjZhmQdu)~Ck-cUsg&RT~LUv>J0Cvq;pwI`EFw>`7Ex?WZlQ9(S@@68@L z_OkPt_nmIu-ZQ&vxIN5@F2rm&8O5fkO09!5u>&x-a<-g|yScSoZ($I|WQs-}i%#Ah z8z5t(UWkniL5BjE8Fe&@8A1aF6)G7p(8v)va$;6hwTOf!HnCRKav+#iQ;C*Y<}ifKwbkwIwQ^Fn zJ2SoBOj%Y{UFCV!)MHga1i+Yk$*8{d=Ifez>|J|vH4eY+U;sm7rwyEIR+B)=pr$I5?Z>}*C9+s%R2G zua3u~_dfX1JKz5H#l@wcJ^Qmi|BL_D>GnSLsb9>q%sc+(H@^A3M<2cA#%tdF;C-=< zue|WWqmMrxDhO1p4klou+`A$hZSHIrt**~qRff7UlqT!+%i18+A(V=gQdr8Msqh8_ zguQ;h-O6Ga-#i>+1PDgNSQL4Pq21}MtepQZ|MkD@-Mi;gpZw%_GP&r`g-2d~>4#50 zU5zHr`Bz?f`PCO+I&tRo$3OnD0|zbu#MxeZzDrkM_KsIxKlQ{@&wTZ(Uv4q~)^Gm$ z{KEWy{7-+pwl(g~%_CE%)3FdIRn=Inp+UiW@3`sK+u!z|{`gPNubp2zzqV(o|D7*> z=GXtHfB%!`p4-3g;EA)#+uK{KYilQtpKP^@EcYi)oxJO=ciwd44eJ~0Kl#aXD`!uS zC*#%iH85CTT@Nv~+pR2fq$ns6fsiaoOU=NPIHgw7El?0i2n~#l(~u(FHk@+=Q*N(< zX%r&zDaJ+w1`b)wkO;vNrERJd15gA~V9#R7&7qvRv~hOMrA#hZ;$EW}B*}Q1#CRq& zBW6&`cxrYe@(#(I<+&HtENda6niw#2is-y^%&MA3Hqtav z>VNw2k3Mkk-E+N;nRa{p`G0uq_kQp9Yv&7}2U9~7RqvRmHWNz`|vyN zylu9VJD1>Pl!jPDgh+%?H%-%oey2xj4eEXO-r)q8iHJgoAx2XrharUD`Zxaqn6u2I z%a)h79{SFs|L~P>ZLF^E+Oyy@*VGZg*vt%K2%z@qU-{$*KXiYrCLuH*`rzI3^Zozr z-~PK4S2Bps<)8v4h)e{W)+>mKG0}wZsZV_36aVBx!@*#7rhVw}WiP#W=PR!sX%#Jz zR1GlGi0DOaJRJVc|M=VY-F@@9<&6-UvYG$LN8kV7KKnTpQK#vT%<$$b#ejM0bU~bw z)CCk(kUavbh!GPrr=}g53K)QzGJ62z=_w;A_8`W{%t%N;21<@Bq_6~;rud{e#AzSa zfE>S>yiUIXnPHMvOH?5wBM>uF10zENL;{njrm1$vq=;0jf~cZ}I;N%%q7rdb4WMMC zKuKcW1nG8XYC{CfJTISH-WgZ>_8pj=n>q5@Yjvq$+K4VK?FWXH_0?Xh>)N{oFl^Ki zU~K4{5JD3~L)ApZL;H8xWc%z(k1ap^`+xT6(f{L59@#ZFcYJ5N)tO~S85S;UA%#{u z7gIz4AVftpSM>hFAO6*yH(wn_1MeKNLxj9wmDMJ^>Ri_Db<3E&eC$LJat^>441z=u zLw1fRBL?%NXwwZNA~FD(g2ZSj%o!p$?*t6NA=M_TQOqnxVW5mX0+OcZ8!)k`siXlR zfl9)_rEnb}Ac7)@Mg)R1I7=v6HNdn2bqJJ0*;0yG*9RF!Kg%rXngLn4V8S4gd^M4GB?AKqW@(_4iGN=O*PkmRQG3{k+Ta zax`{;|N8sWSqd zUHdL8tI5X8FKujB2QRv2b7$CNK7IQ1spS`l*uiY8H&?|hAg-PA*bVT#bt&N@Sk*T&j-CW{NpZMZsH@N18C$ z*~wZN1I=}3L#Wiuc_gT2XIe4D$z(7;xBvMUkGyj1#Eoy=xcag~tLM)bdG@wjZk%g% zb0I3)8^h7o${;i$DhO~Q`$el`3<7q+{tFfs=7+;^*$g}0@7cF_?)=$9`!4OYT9b0P zxVUiY_{nd4{hJpbzW9CbfA3%Y)nEU^m%j4h557MJ+`Vh}{M^FrZ-2+J<11TR8@Jzf z`>>pR|M5pjT&vSYz;Zk(n;KnvR0o+%0HDYV)C|~h6Gef2L5O0ahN_^zQKa2!N3rv( ztB*hSZ`lv{3>Tt`gx7~W% z9cRxj|M_P>I~tAh%w2c&HJ2a0?8iU)(V3OAr=|MjgKz(hfA+~2kDvYJ|NgfjLcx0T z4VUd*n)Sc=YtO&F{Q0kbE%Ui^-cc6fxM`X@-g^C&mtXk6JMXyh$}1jvn^!)_paUNw+C;WJbC8K>HF@v_qJPZJ-fU-Da-ZI`q#htH3Qqbd+&SR{q8S( z;q&9k?i8j6w;707OKXc}~heP(|Q3r(J5QWYa^@llC>3dZUBt_Yx_1`dsVh|v<~O_hxVH0=QqNEA#X@RVH!WIzgPiX6p~!$<+r)WHA% z?D|`7z2)t99yxa6*`NI6)Xxi5U- zlEc^BaQ)lRw~riKdGe{(T)#hQ8j#4&jR`Y^T;tw$n2jgn;OxJC=cNZ{_WZ^le~bNm z2?9~)+U-0q>UxqFep1$8mS#(;+V1yXJGu7a(eHs;qY+IRs0jhkJUYN=pblNH*J-yq zz9`z>4+o42ook zPQ?slS{N1s0zqXYPy#dqg>-vG08~&jH9|C213={jr~*s%qNF@b4LL{&6+~rX1Z2RV z>Y3Gq9lt5e2G1^vBteWPH*LS0vSZI4KmpWwmuH2gq%M*p1T|0qp8jtJHLb;Ey^AJI zJ}R?re}4hsUA8obO*J@m_Q?KSySlCJ+|os}bKR!d`N0n!QQx`oh8uG4+EqNUS)MQT z_B-Bz2C=Sw`s@$R4F|X0c308r>(8{o1`churCvPx-Fp`E zc3y?5AlY-_p3Rl*CInyPalB)uo7+2&J^sX*qKqKIlka8nXADc<70EVWD%&rk5;89r;k|HYtFp6+W zf+Jz!Ga|NFPs;i){_5|G_RLMUTvJtHds6?wAN!U; z?&ZyByQ=D@EKi(xcm^~JA#qg`a}c1wbaNT*%A{{!zSM_cF5EXOOa=yvj!;~Ha( zwRf<-zJAwz?>)V`@ys*NnCkI2URSlIiKkASWU@!T_Z>4^oL~C%FaJ`z(;?3C5Rblo z^v*l)xc2(%AN$^S4Zvp(M4Ki!c9Om$Nz7x2pv0W4B#_Y68bv}?)*y-woq6XN0U8kl zAb=z%G_xoX5!Ez=1`NFOrews^^e9tQVMI_&dO0vaGgJ|2AQd{n5GcM0sZ2y=b}nUQ zQp+Q4m{cQkmc~4$MnI-kWO;hTPt%o1kR(+&^`R27m;s=wdG>-vY9f+n86bjynTRSd zff;JrBO@pv_0w4?TRq1cL0GcwIoFy5i&Je zmy=P5QB^#<$zVj3D&nXB8IZt~F6=OcB7h0i#Cz`;AT*sU+Zb%CAxHpVju54)r*Y#TYO0JNSjS4^+TQuufAt%`c>dhVV^93h%{a$s%uOA# zqO*VBE>;M2C1y^+5e~P?k9_olfBS_mdyCv1#c&0bm%s5i)rRv1tNjjKp9RBq$gG0JxM_NC8^t1@Q`#P{H8rS@qLBzxg{F}qF`{m7CNzRz(IO+Js7T6{nkhS}q#{gd$qc5`Zjp!}0uqK09H#khS51wC(uk3H&k_Xz4QxCb5xEdU48b{? z?{k*X>gLYQ*uDJ9@k=kiYH87*dE*tm{iIzx?%M$Dero2RGb!!-W@K;PR|85X#hL zRn)So2n<}7x@CYGRYi?Z13>b2f~o`|PmmsDl!nCE&O3nGSp3XieC{v5@c$9@X3=t7 z*O}%X&WVW3ym?0e7r@0#fCLB-;5>_iL`l?STb4C>sivfZ_8uU_@i{Zv)1 zD);Itw`JL~EL*ZQS)wS4qBx7BIRKnMf|x;!cb+pdG9u32yB|(mi4S<;UBJCSMx1^2 z|Nr0LP{F0u#ntW#APE2xqjP)r?z?#T%1bZ3bnv=^n>KAaefo42f+2WC0yLG~yLbKK zCqJ3zz2m1&iAvGQ$9GH!53H6jHP-=&3c8~-Fszr_U&WGKJ)2c-gnKO znYo#rSM6L}?(E#Uz141Q-n4n&{sWgTT^<`5T3T9~o}3&R87a%MECX3gxtqk|as&hd zPyno7+!&uO0|n9VM#zBDTg-K#Vql$X%$H6zo9N z5ye;yfU!v=@|yv&Gbx#&mW~YA`}ngNfvFLbxg=JUMM`XpJ28M7Qmtg!S_a$5K;ti1 z6D?I00i9!uU@I~eNmK6=uV4V|Jpn-4Y%&2cCro7&wwbZ+1~vu)R74;o=Tk@GJ*WgC zE~WH|7iDS=Bxyq6R87<;g; zy?FOscT`n4efsnZFa8^mOHvPLjvRrygxN6|mSw2ag9)LjXx{G=IiGq^W5=#mZA?Y_ zRYgQhMo6Ysg({Tg8qMECl^_v;s!)+oR;ATtgv{&=5eW&*J13$LqbY_QpCmJO-pnG; zgNVe`#U`vI>vUJEvP`oqIyM2Z5{X0rKode$K_kF5A9s`(&)Aom3OM#E!cTeog!mu=s)b#7&4_s-p~FC4ji;uH)I=I@?)d;P0--Fg4( z&piWUdqXAtP$^mB5>y=9xaYAK-)(7cY-Gi9;L;!%$Kxam(h{_TQ@4cBs zYJvtqrX+<>R*dKf0hy81Owia6Rfv+92P0$+0%oBK&O7HCdB5UhFaY+8fIy&3gx;BG z$xcnm1StA_(SV4HP^gG#={>U}^078ijLa-VDtBzp6;nix8yk+EWi(MmS5t1W4kNQ^ zZ1n^J3SdZBL-If=Vt64MS}*;IGBCo|-SL49Td#WZ$;XzaSGC!@<+hvN^ZwRTk3XVI1vtL>&Rah6ixc1Z z#y^#P%|@@9*s}e@Tdw=wL*HF3LqQF7O|+t{Dp3PKP8zCGl!6#T;@D^n11MBMFo>y% zu((EJ{o=}L^qU@e^!Z=@&DKY=f#Syic=6b8dFF-5zYUhgX-D z=jZ1LvES`xX@lQ^H}`KB$Kg!G>GX+&kjkQL4~&|*)lMJ1%Zq$&X@L+nZQAto zPoC?R#c(4%_SV~{PoMtOCqFebHu860`RXS>^~pVZ_H=tiS%eT^d8HGYMud4;ImVb7 z1A{tZiXH%vTo7esc4S~m=qX7OuBxgi3jiQa47A;DEiJAfQNq5FHboVb$a7FJv-$a@ z*WY||bZqp&4}R#&lV85~-g~dUdXH9NdAZXoi%)@U7l>z%2o z`LvP!^Y?ym`qY_guDy1{y0Ig#z54k-{`2wm>sEgF<8CkCwR6Y27tV{SRMp{EUTiiS zRax!7cK?R;>%rimAAIlSS6(TL{zpIdQ9?d?^!0b&Jr~L{%@XgJ5X(@QiBkpy6(Is- zG&R*|K1Brq0|i4vG*pqyd50`$&bt_Scd`Bwof)WBQR#`roCuP~GGHQ>6=HL7YkK z*Fr)tMk2?C5EF(3#7r^1!D$k|5-qCY#DHbgW!BhJYs3aq0*avkqKLr&LQ`17HW;yw z?Pf}XbseN=j4uHD#JR)+a;S=a)gKuh@h%lpjh;|c;OHVo0t-a}Oor4*d{rrcs0jdR zFf>4qje+4SGt2LscwH)4zixe5R_NF{H#K#6ad~lMcx30c9sRsKdh}>xptW(+#^w3B z)z#JY>o;zmm{^#b8fhgr-Ecrb`zsw&Q`Bx}>FTRC{pp|n```GTKg>lvU<2LGZR_9r z-dmSvmr4;v2JZ|EtRO2s`^%qx_UUI-g+%Ma#S{@!@5`zJQ#AXfU;McZV}p~EGt4y5 z7<%pXca~R{vLvmliU6f5(0e9Q)xHGB3_%L%KmGUdI1{7wBB#IdVvY1YkCR zvS0S|KC1a7$+FDAL`$eJukz3>(ljB0P>E?Mf`lqCbDoz&LxarR?R6bfb7)|BX^FXx zF_%>l&(w|U*KOUp6$$fxe|BMR>he_TvNBZcFiBm%6a-);WM>#J;1L5~18C6zkOTw~ z0jMadp60_$(V_vdrx$?ZIIO_v)|1_7cwq%2D!2B4V6ib9Er zAV8L-dD$;R#cHZSLr_(AE^#SH6zSp?i;Z!h<P3x-A(9cOGKgQ}V$6EG77sG$ZBe~Cz;n)wn!s55X8UO)hXk%QognOUTW zJ2_@vOF0CGXiOYb)HG(b(SX^-*Pe+HBA7Xcs#GC{sv_6eIJ$mrW^uB6WvSnuU2bmK zb?2_7WNB$(HH^$Hr|IZ{od@vL>31vMFuxj-_SW|J{$95?v3dJ^x7lp$+PwXSvllKb z=Ys>qP?`>p@4R!ktTv5rmQs6V>EcQUT#$IHWmPrMN-6|UH3V}^A!t=&xbDu8v5myp z%4Dua3K*qe0qaBmtt%({RplI4c^N_#z*2H1*w4$c_Mn>Ub#g`+9vpt=$)}DUed`bY z;D6t^anqY`9=+$zyA$v7UdJcM3x&`;(PcBV)ttJyfJ3#2{wgr%ycf)Wp_pfc~L} z9~o%0R+blEKYXN>Br|ifZ@qE!^5x6VJ^$R))YS6Qq9<-P8cE{1-HwRPP0xCEt%25D zX92-hR~Fu!pCuv(nON-kZxQj|RqjIsC0ix)!PyKr{-+^N&#Ju{_g zVd;IZhfCI+= zsl+G}Fml|POcjwCv=mwCRzAzd);oum4ERT%I$9G!Bp?zQm?Eec0uV9#n5eFTIG0qR zsEQI15RHt?Xs8e+CI@Qqy)8KVpTwmIGmN0 z&braD>uaj1MSQ-C?K($o}GX4sb}AK zs)=P~1Dcs=MTlTz1OTWA zVrXcLkvTxo)Qw63jUsOozywMKBr5ZMRh5wEoA&HSrqz|a%!=ie1)rws;gx5ekky3; z-gp1xl`AjL&TQU!Rj<-L6I)wZa;2LaVYIaOiejoG8*hF9Z+*ad2MCj^L6Y`xI?%u> z1x3hAx*UU6pjD_S@$q$0l!ck4N!n;;WxrfpSgy*|22}%@+rDKhb2_)!pP89KGYgHZ z*$@p8gg=xuir(V%;=9(nJT{0s_ilLb10P1f?|k>+#g%YndRjZ9t~JaFt5(qv6y>)h zO&n9G`c)7UaV`Z=WMZWVN-$Lw0mNv+_pV z=fIqE5_h-oGu0`ow-Wgb5uy}<&cvXIb%6{pu_qL;AmRdH!Xjm?dIg9&5jjzuCXIGS(V>A&>QLWSMjBnmHI5OUBwgR~M#nsK5w=`Oh|)!h3jv*cW}db=hG@^QB>C*Jfw&wQk6yGoT(s^su9P~ z8lWNod1L?#m55XrIo8T%Fwh)e_E%qh)tNK0)Jw*;>>8Wcx_QSnGZ!zubNtNNcTc{1 z_Lxd=+1RNwXK%ml?yE*NPEAd2*|Gy#6W@9COXCx}KK$YLw$cm?dPTS4eVS#ReoktR z{X%EnIo>e3v8oDYs6-l#=Howl{OB964z`DHzxO`XYU8GfBxyYMqetF4`f{i$04{@$ zjE#Q&_dh?-ax=@T$>4Bb(<_s!Y1R@8eJ!93&mVt&XlPxt)vT&wCGQj%j-5L`Haa{s zJd|)E6(@uaQ49tKN5)3hoj!J@?03AQQzuV%@}8;w;0F&+Y}+Gg*W z?b^9(?={zUd-?I>$BrC6a_P$Cz{qf(m!T?Lk_@-ovx|$U;9IRC&)+(IradsYe)Bff zs?B!#+_{q{P5@|{Cd2Lau{Ym*^~fs{0s;_GBWpN^j=}qc5sOfsIeWI@k}PXB2H1j` zfvAWE29k)3Ms!IUgq&kyM*zo;9SahYG-^4o6xjk*Wa%Gc!UF1(hJ8(N`CU*^5e0UF+(LetQBymFTg@8a-*T^bXC05CA|- zEf|p@uwmqnArJ*stj+m=XmxVL%;J6ng@j`1I4~mADd-5cB%(Ul5^cB$1{6gmsxy`~ zi6g$h2vHD0l!-&66i4SwU3d^HCgc7G35n`KNT4QAX_}?q`~G8#i@8X@(P(x`edwWw zeVP_UAAl;Y7$HanOklvuU_i#Ak`SvS5!2X(go=bj9uY5JzEt!&X~Nx34rWZgLc+RN z$nst;roezo1VUskV@8$`vTOj!7MGU)`fvX3_kZhG4({Evys}*77RoAX4_$lRb@Z~olJJ`#HU8v16`NPM(1R9dw_{_qcf_fP-q(!%^ax`dI@F!h;ASxJ>O(qH@a zU)`}|>%!D501PyT=H?ckdG0yq;Pb!p>-XJ#-Ld1-zx{h(i1l?Gfy4k-=`~kv|I+{Z zzbXYnND+=+T>kCf`a&~FU77{a)x7h;_uuz>U--=pBaM}%UN9g#wwteh?1lrwgM+u-c~fNJ4-KmYCTexF1} zMw-9+*-wAy!S{tC^j20o-Bstv)YNR<=-_Yv=4ZVB%-6pD$UlAkpUZ&GH<+mkf!HaL z)hbxMkW&D5E`m2if=iPGLC`=dWHw}w2-878Bqjt9Gld8x12AR8HSNO1&gZDG0W@dHt1(7vKH(gCB53_wlEGa`ja^r0h{B*0ocY08~9>cI*sI zQ7g~{P?dmazAV$!x7w|Cd%&ZEPELy#Jn0 z+wtA@|7#g%S#VFcz;>Rcfa?<6HgsJcII+bWXL{9NyK8L296y7E{2Yv0dPMA zP|T1zs%pkQerr@mlgR+hl*|B$EHY_h7oFMKx+oY(L{CJM5E0dNw$Xb6s%ENE#{gAh zjt`NEEI>`xuWx>8@x~PwEOm&CSb`V>Bbq9pk7_nKQZWP+RcBJ~bJrX&x<&xPxXRJU z6*p4Vh^`EPRV6NK4Q2x(R%j)mO0&j>Mngq=MZsXsyG`cR&)RG}{lT0#{9u$c*?k1+-Wt>-2LB@hLq$jd=+iC6$LPJFLlHnXhJXiZMe ztakMLh2>XYJ#ypi@9ECw8z=UTjIL`B4>{tz-y7SwWBvFxC0`U}qnVNCqGX`<(&EbW z^xV4P(aFindh@zUoVKK&YXSgo#T1lfAOWm@4f%NBuRGe-jy|)Pdxd=7r*$W;gONK`8h%~G*a}< z0q2~W0)a$Cp<@+eaw-DRI8L!tu68`#e%tN0-FoY4w>LFAgFuI_zhT?6CFhi2yI z*||eU9zV|-y?6bY9c;NmAUV8DR?!w|tcieg1{{5{qed0$Czw_ps&2|el7(i7O zsrRY#Mo@?V7(+cA*JX{48@}Pt5k&x$nu>E2R0T9bdo}JM9f6X80dvDOO>NEb7uU@g zP?#JF$KAU#Q?S%IKyd5t< z5Gpewc9s&0M!p6h5|YMaC8koD+0@vfX{?@!9tLyHi<)=rRSXRjf`q)^FSHT`=Q;L< zCCpWoN9QRZ8Z&~4DgvPbB8o()KOx1UCP8FSGmfwl14LD;Ih6*;8XKw2ObF^w37{gx zCcGp`in0K(5ClQY7#JhSFWOOJpuo`3NMa){*3ecn1q1|!5M6j{Qqh`XwPqgXjVm1V!vncKE`{L`QM z?0^5uzZgh-ymguxlFJx1zN^Gxzy0h@4Qj;yG@^( z!ra1KtJOTT_v&B!>_>O+xq5nX?zO`wUVZ&Yx8FyTG_xCSIIwr$<{$s~r8nO?ztqVi z!nza*N@|klz46f|C(X0xFKFO=d2rqE7yvkC3xX8E{TTIJv0!T+IMWz1Cqyw?L*gNU znu5l5W^#ZAL4?_Fd5+|V*YW#Ba~e*_E>yqbX+A|bJ=7`muTRl%a~4G_?|qAFvx3VUZ} z-BJMszzi9kscA5iypKdc+%1b)h$$0w{^c8wY@WDkc)-An$b^iS6!-rpQ4-IbFwq?)QXi?gc!>=K^ zk)aW(UcYpCDoHcqY-Yav$AA3xpZwwHHmo0;o}KePx&F|-x7_$XL6oZO_g7bzX1(_l zTlW3s-#_&96GvN(@gF|*?Ed%M0IilM1cM-k9vr)@a8gM&&{hQlk}@C?BxzpixpR|u z>^<<-(Njm?e9I?^s%_b{`PzNg^z-fqKlGu8|MdrlUww6EYU-J%pW3%~Z?}_QxNyNa zzhmdFq9|^^{kDVG?ccCr!{7bw-(S3NWz*)3u_r8^67g^qQy?TEMwFPHMF?Uc*yizx zyjT3=SHE`Z^r_+DksUjCJoth4vtu(*kx+$Zv%O)rJBWPwVl|E9h>(>RS6=;=Z7PS(Ex;r0Uf9~P>H9wfhvHK zf-(~#i(=8wckSARhR07HZ;y;1VF(pCskUoZ!w?vniUN@UBm_lKhzc@Ch8Q#B8f3Osc?@fElnS$hS`tSlhA924xo2Wu68uyc zQjIz{qN^iLRuHyeI{*M607*naRGVKAjR*mli3OApnQX&`v1a0jh6YW=2HbFg!F^l%YN&Q7EE#Rmpi|M~=Or1Vw-lN(FR2I*!15QWcI% zXaMJc6RJW502)G`=VhrP0*q$H0F8!kHdw9pbjTduW|_rL$>ll!jO^}z?; zr*m_mU(QZ-Z@&2u0y|3ClTW-apCqgEdHV2ox#q{O*R+@|s4=_Qm*UiiP#N^!Pf8`ffRyyDQ_74Y!hu9Gq3)Dmy ztKD2E5(rU3Wf4ndREtLOUl;0wzz|df(2xjB$)ds2YUdW38i**wmcQtBi8D0V`mvGM zUVQPHr=Qw6Jmi_rzw?fejt{lEi}Oo!Gozy;hhKXB`KKOpL}D;FG}H`bK7A=!Ka@Il zz^oR)6ww)GRiyx9&324hi2?(tP$;dGo>ZY(hHmH$jJBFttK02^LG)avNm3U5JnvK? zM{+AG#o^bEdBfFCcYbN{+_?)2(^HF!^Ili~@BjF@-Fx>AtRG#PonDz)$jg!msS4*$ zUqHvmwq@JIuI)Q}y`E!6hOx2a^S^a9u#d29m7vk@4BGGK?5Nx8Pfd58d*Rfvb2Aq& zUuKuY`>Dl@GNR+iGlHV32oVqj%|T2Ep~kc`5*nKYimn2Kcr%IBtu=j)SVRcDS`AW& zCD9fK9z>?PHQFHh58?)bi4+mpKrNPM#n4iu?rK~C#m@@>IzU51MvO!#MvSIHs6&Ys zQ}{J4j~v9RxYE=SdaJB>okddIAVRajm!uh!DgO zKshc0*CsSYiXaLGAcG2#E$#>b3JKtRKP1jOb~HCH|Kq>>#ee)ies_G=mhQ}aFE5mY z%oGJtT3Omi2MZki&wuf?H{U+HVZ)}?PSwqOLqqL}i5(l(Z76!x*t!iz4j*ncTUpX7 zD>O@r5^ulb)_d=}dv0#wZ@vI)L6pAuB_Il-qOGafr7wNy%fJ0QpWV25xaw3zuUi3C zTA>zdGQ4i1%QpUxzj^4J-~G2%GTKL7nq7YR@X;3UQq)l2-($L z^U4Hk1{DK9=X@RYbi`&+G6Q5vSVKT2RB%kWs;b<6`)#4>U%Gsy)f$L5zGw$CB|;7& zfJPXDjD(C)W&%?rRx=EW#)>8iOr&B4N@?cQLRHn|66fm#j@1jPHF+4K6W{7kP>d2q z84P~5cR>{p17rXb1ppvGGa@vs$=!&grT~NnprI_yw8mwa2_lCe-jkxl0zzC10wAEp z-H#!f(NBjcjVLNr00)uzROh{GE--T4H)z7-VsU|)5@K}7m}tM~-FNT%e)Cs9&18x5 zL1O_S8lrO^1rPuu1)Qi-aSl|YSP(?aRQq|qC)mQeH=xd8R75>YNlL+yc^59|j~FjSG$^WyaC z+@7p5- z-}v@p=iWWPV`Af{Kk+dFv8rm13_tjx2cLQF1qBpPPmYkyG;3vuHIFn%InYkCGy{b! z!$0{C|KZ?)JyVmH5io6LE^GXMfBoft-phNrcgg4e-LG!jx=s{MoValM)Ty!2F~{+R zONJGaB}ofh-C5B{=$bJlwO63YTOtcdFACdo_qeq3l}d84-Xx@ zcHd1m9+;Te77`g1GY|Ls>l{qPT-k}4n|dIX4AyEu@TssKW5tuO<_IE%+Gh|Sxe zh76z@jbSl=vqo->f&kRVBN|xLg#?&Xfxr}iJrY>UQR+!8xCAKXv>4wr#l_jd#0J@f6A@uFGaE`8M6S_nxP%RW&=N0h{K`_^@dR)CUV z+3znGMIH)bVqyXbS(03}ZJU%;!zYTUVr5BX(NhQk0xP2lFsPb01dyUvG3)qf>)JWiYR1g`ERD_9RF_MY7cm*Phya{9^ zL5sgT#SwQcoTyPYx7gIprp5@Wh@@0|^y+Pmn4rU`nq2{?x~} zZW(U^1O$;-b5CVu&mTVao$r19_^H{kkufw4s)_f6ROHp$Z@qo`^r;(eICR~?L;Ze{ zq>Xn@oP6hzaYV5dh~*h(oWF zzjJQ-`;UL~iD!>C*Kg^rt}@$T(tPSWFJ{!b;jaCQtBXFPDp1u|LRPetU6dr8V{ol* zuYg`QcW(Zv7r#+KkjE|i>_LhXQEV_e(ZE|wWo~xPz*_EluTW-E}VPR>{ z>D^1qi;ZToytMf4*)!X2IgdzbAJ+m4{dWX~>5LKiKG)=u(SktuYT%Ljef>@wfVvTFu0t+C5byrU$zybgR z5))~VSVs`)k_f;G6{@OHO?}4*^XPPXV7PV1_H*aY$9_bM^&JT02m{3Hi`L&zZ8tLj zQUXE~0U|?K+eSnS8i|C&c`!)4PrU~;MfBiJE7h0-g4n2|YG#4}Kn!SVxMtk{X;ErK zs8LKvW8Lnfh^(T{v05-d6=h~cLICdo5sk<+=1eIr;zfgF3V^6a^))U|c_^x8H8rjl z#}NonG*-IQK7{%Nf~W|XAuyBbn(;-23<=0ogBYT&c2@T7-80xq=NG0|gE2W!Q6h_6 zU0vJXAVpgavVoFHP%t9LOd^6vkqLod1TZ=>68p5C+p}wBan>}jnRg8XxHviM$@X2n^RC+u&P**K8aZc- zDpjZ7RgH}Ajch8y2}<7hke36T+3X5J?lKXL+O&}=4I zn&hjifAsr*aL3IDrl;o#x!r2EM~46B7r*-QOD}KRwsmf9HuKrv{nI~RbM@8d&!4|= z;UYT6CJIUnhGGU;V<5@eU;Ebg9)IcyCdWj*-s*q*&;Kb!Sm<;RVPtIdMU zrL4;N#qi>hBQvv;zyF2bGJvAnSzYO@8y~;xuDc$8{KtdMK~Mt*6-A5aXVJ()W-=r+ zj5lrollr4fP=BRGb9cOW)So5QtP&2mnDvO)E20tyIM`n;8jNs6-)1D2jp- zYc_}9I(5PgZ+BT5NL@r98v&9tKr~T71CB996J{d7pCt~YhTEE&NsX^0BqRLkfgT@5 z1vMm!m*KbzL~`{zC0gb{RZN8IO}~<%2ypCOM=&)eFvrYnri6s??MxhB$gZYIQ9Y)_ zcaVV~#4vsQrpY2k0LcIq6x8aQ6Cx-QLM$}{Ktu-u#8xQ)Dk>)IDy_g&f$RFT7^BxX z=NVeipz|f9rI6+jj1pnVD@5wi`YPre&3#I$vF!ntt?|hmzFYeEoIX zw{Ht-E4|expL}L+xsxP=S!0AieVR#CYK~O4|K+d0*A1)h{m|Xrm0rJ>=NQBkK+)9s z42cC`a(ZbX8Cg6#bN2PiWjA=ArUb&)ZZu3}Xk<_zj1CUv{Q^Ko)(u~{aM3weR%JKu zrHy3A@U|>XMu$fSTf+|E+?lf?)zI*8uhZSMX}zieaF(Wk_U^myPESpZuivn9$4P%xFU-w< z`5(SAIX(N~2j2IAyKddNYsZB%XNa74iJ@J&bOpf;4z-fZ8)(rhhsQ>D9N5upwXV#} zEX>cXEG|hE5|{eS&(6=5RoF1TF-y}B`b#UlyeQO+h=zxTEQDUK7eZ-jNs{2uVB%}E z2>~k!)U9qz1O%W2U`7!Y0)T9)Ypv%oN@E5RAy?4v=RlaSxB3bJOrRPN6J{6dff`xb zSy_4GwKu?Hnr0O1!VHl}RnQQ~R3i!zBA%1XMR~AF zI1T_n=$Jw4I44JtEyWZV7$C=-&rf5Sja{C30p}T~t;td?_{x z82 z@VZ9Us;a8!=EcC!Cw}4Q4j*})oCkp6_Tc7?oAbQr7bPHO&BmD%r)TG80i=>D2qY=@ z`UREJa?8G6O=97aH})8YCkwaW0`v6C0OTJ9$wU+St0GSB|{(%uk*l z92%USo)*=z?93fK`uZDhB%aNr-D)FqC8DvvN~AS3^mkwV?hhXR;poUf%vCiK-)=Tn z<`*j|8(A~S+~5EGSLat2n@O6oBR~~>`<>&555IoPjfeWGg&HCp*uU=wKX@1h;-jG= zRUAy2qoKPtO@c+mP*vkl42Ylc)Ga>=3VuU|Jhdg9n|_I~5WjTg>d=vR5j zb!u|9;rp+=eB>8@?)^MC1OUSu)^FRfGtbMSldrC>j*N~Z%`DIR?;caE48A(+O6 zQ{3hPLa0iPlvqTApjNtcWMF6*vmpi_K#;i31x5CW#6S>HWH=DkvYHtH27r2k0gJ?# z+I<#7%Q1Y467PidMQP1MhZMWA(E#h_QmYU07;6GBbVlrcwwiX15vowB8KMIaRSOb= zff@mbi@v#<-W?SoG*NJ15!0~tX^DU*tA(Lxd?KRy2LmFI05M2OgfW9;rqMI&AVRU? zi;+~K_n6EA)z@E&&s%g>sVPP@gT{7ntC4yb<3qI*P}R&pMXO56svvZZk<+A?ThRwq zx-eP2_0DsSQB(n`s8qx^vebJgRPX0SOoJv#quFRRvev=<*FE~f%PPdoZ@qbRdTM5B za-MyXWXWr99vvJRTfct1+v`+Sm9nFh&1Xfw6h$Hb(vg!-|KtsgwnR<`2gZTKF#&M5 zo11`|Q~?@({Ucv}Y2~uqbN}tFp&=>f94C&OX6n2HX`DK7@$EOxFU)op=T@+gJy&hJ zaPeZXDv3{ed0ylN0t^qdJDuLT_2XG%aC&ZW)5MnUYNsr!)F)RiP43^fw+bSrj-3K* z-MV#XXt>+$yyvdF?!WJTQHhCJ@7;?p{oCUF^3Av0+{t@496Ho$H72iIdGyCWe(Kqu zNKe}XL*9FG7AhSdTmSy|-S_y@PaivZ8UUC%h;;MbJ$K!`eaqI3 zy7kuEcT7wa{j!-R0@6rRMqcSI|EE9ylPi~IzVWZ$nZ7a$$b&FgGoflBn466DJ%~)@ZCvHu1c7sv!bjRb%j$YxsegbMYBgQ_$M^ z?jr0Z&QAu$%+70_LpO2>Ap#nz3YZW%#2Dv^0YL?g4^JdH*_yUXan>s(T0Wwx_N)g=81pzE1wx2${2-2ROzN0u2&QTD$4SX z+itt}?z=)2s;bv~^-@XQhK+LSTUJ z96QtNTYY=YcxIMk?n3vmMmMMD4IbOMN*&`#7qzX2@(W| zobhtL@tnP@YW~>gvHKsax3Jbjxc9!ZYuEREzt3~Qa7MzwDg*=+2DRaQ3>9cWW9Y+$6^>)6=1h;KIPMA+ZkQ;MVRYS)DeqxE{DlElsW z9Ee*sG}x$5D~gTG_(b!c?tgk{N&ogMw@Jf}PI+!OS1euB?6il^jV>J=s8wqxPn?dE z#CzZAbQm@B-o}-3xu>0h7jGj|t8{lVKi_K2x12hepPe~?BrM^_+=LgcIJ^Z4p9-K702m-a5h4vBZz$fY1qc%%1OuT8p^92E!ePB# zc=7?l4>N_G86g%UgbE=k8cq1%n;P!u$iwjxg+z!`+dJt-gc_M!E1?C;|kEA};*FL=;kP zqTI?eGQ`XjM{13zl+whD^Frg(P0~2`A*5}rwNWI-pmRmMzDQ9y%SLs@AH2RBtrz`^ir?Y`ploYp&h1 zd+&=czud{%*IadtF|o_Fo;5oFi~D=6wFt8Q;)~{+^TMpc&%N;c>XoZDZQA5nHe9^^ zfB*Bpm>3(o>w|aBH5;F~_cLeDjl^mEjc@$vp+kq0C`!wzK~t-ickkKDp#cQ3Ge7&< zYcF5AZTt3Z+aLM)FZS%&SE-Z+7x!PZc3l$D=@UmrM@D17PP@&Dr6m5~-8b|YY`ezw z*S>FhcJ9CY^>igQLuuEvJ@s1 zT`+$Eh!2+bpm`~R2|5g-8q#9b1c>N$LBI#KfLdHOibZ>&UxoZ)xF~7BjlWkig2K+k z1{j0HV+^S*nGrOKY*57k)TC)w zclTUd|L?#1@1%$ZE5=-P<+jG`ED-@pZ0$^=dH&q6vB*l})6=i+-TUDW-PXyP;sw}u zn$6FA`eQG?_{!o%eP8|Z|I%o;L>wZN(#rf?>zQYstya6NP0n2yZFll=ccmPsta-E1 zSif#)%hoLi-Z>NlpelN_r^*1Mp2L; z9{?CdP!d)~1w{3#h!jSD4O>+}P!R8f$rACsTCNbe2L(_sWC&0IkwpMdfS96oi*nPw zc+EEPI;7Gi-ivw#-MBF$&Am&NnAtFcdIwN4wi3bI*~4egpFe-0G&woFe8sBEwqCM) z$zYO1kNo`MclPh^saBtU=DA9_eAy*i#x7hqcjnB-&6_uG-Y`0RVSM=H$n@|R|KcwW zpBVn$U;Vefp1w4uMzhI{;s575-(0q2na|EV{;MapZQpVEl{;o8XaDf)Ux`cUij_-h z)jo(8y>aN=_-rO#fxS}^w7DY>U~I&Kd6t(-aa5V<>+4fN_G}D502u;>FqUVJ1{n~P zB1L0KKvg*8g#%~=6v?3Xp2$d1{VoTVdghy=%BS2xeOeDjb#=m zjELoOrIY7|>~&XPUn$ofc<7(^cU;;(+V z_0nYr4<1>ue8uLCo1TC6Hybu=yyCLU_wCu6q>)$IdGifRh6WEEI`YoD$4;L)r=rJB z9G_fLc3J=cAOJ~3K~xwYwO}SE$D<@V@Xo=-BcrQVu3EokT^rz$M;@Q6&qr~Zxtzs~ zj*Ry9b{lJwBsq2R)YSCkrI%i^Y}wM$(UH;d@$dcchhO;J&-eE)K6diBbJ@igUv&R{ z4PtR=HwBeqQ-g)};*_U5==Ji*fT{pDk zW}|Eb&HJ7>n@#9p*FFg07fBEOU-TBsE z{^iNDXXfVTdTO;|a}hY6Xv%3h%iHZv)@gNead8}7ddb!#Ny(T>snlJqmC9xDesX?p zdU6Jo+O5`+!$(?qmZm9Gl#DUq{$Wf&-v+0c_Z*&fD&SR&5+EWG6sw4^I|%R_RTZEh zqi9%q2Tz%zunMvUkGUd;O{og9c<stRI@IU?BOl$lUj2vHFM7$LB@1ra4& z4G>ruL`;EPU?M^guc8V}03rfH2!w{ijZ{?$gP27IAryQdG718cDq0ibW+25Qtk|&| zBY|^^l6e=Waj1s`LjXlILahfF6 z7hgYc?Bpq{fs*S1adv9Dr>BQOMMVXyG2Z8_qQ3LhFMY0S%f^X`42|{T0buFUCC82( z4^>D}6elLi^SoNBPR~sM5|X!(!8GCAsfWmf*aRA5sMys}65DdM(gFLMeFvY~^~~tR zc!{EBo_F<>N(fE%A$*^fO1qzV(Pf=dsggNpcG|n1dV1@Yi`TANH9j^DC|Rr7)i-e2 zWm{A7WQFrAckLuC_x98tcyL#}-l$Y-?X2TE?RO5Hxb5ca8_juD?c|xu;bR}U`|WoQ z3W8ORk~C+}1Wp;zlCfyQ<{i{CfC<+pYr(N^=ba>q6x69hLo5p7D2@pYfOb0VQYi%n z3GY2ZwNeun?-@{|C_)hsF=V`Rko!elU3u0fFbJ5GQiF!bA^=MmNq_{BG?|({+iqq= zhC*^JY(T;X5Lgww_YizgXf<3-35*&DDg&YlBO;3$0E0#AI0hJV5fA}YAvED`9WZkt zMre@E~&(97HEjfPT*y=TFheWGUR4J8h5znOcJbJA-0N_p|j+~{lj_kHw(x39l=&D7N7 z4}SRln|7XDGO!#BTZ>n1zhdRe^<#DW;1heJazBc3oU36$U?a6kHICB``?AD&JFnHc zA{)2cSpb{_p(b>R0w@^@!Uz>k7XTGQ#j6`~UZK6y+Bo?0rLe#TN{$vHi75nT5k@dT z2pGz=1Q%{Eg&9czNL9lAF8t-8l`Y(~ln9Nngpg%fSbKng4GWrLp{#|2gbG1Cd~QKh z-$OD4K}ggi7zDuuJv&@J!uBS7QFw7f)jI&I8X_pb5h|hvY#5J0vGXrybOQ}!XToIY7?@-N>eo3iR1U4k*by~tBMK{7=z4mTFuSVadRd_i*#ho8LZg;K-CCckpFVf?JKy=6MLk_f93MM&e7@0cwOiG$uFYFEPK-~q z>n#Lyo&2%Ker}9ewR$xoo;!E`r59hWcGc?j`jMkYKJkf<_x1LracTWU8x`RG`|dw` z{>+}ed%pC=FOrkt65l0*bJH$9#EP9;sR zy=wdR?N@g9R9CHAjY?^p8VjPRf`$x5Hp_FDah|nKojTKQw+|eA=Qq#4Xd)9?o5X35 zZ>cb>A;i?q@(9S1Ar=g}xxSa(K@lK&Pq=(fa|uGpdy7OO;lj(J81U-FT2UZL5)(y| ztB7aMxVVI1WGDo5in?cj&~*1+?8i{#0=&yuFQlqOh5$oOAQZ1Ie7gd& zK@bRMOn7NUf|rggsDx})WQ|QD1qA^EmYL%O5)*?LAZ;|-maG8RY8CdZfX0wh@0}Qe zIEo#zNn%AJLiS{cl%ZCudgM4xkb%WTNj$V<(B;nMIgyRiM6l$Tl5$rP5tu;v07HNX z%wQ0vXBx+kk3RkEGq3F4TdQ^_K-Se7H#Rw2sgwvQGL{IlJX^nhgEh9vUXZ~v`;Z1l4k>zNB4ac(%M{m9MGcr$01Q$E zv$rNz^+AOY5g>T4UrU4e4@ku$gnc1}D726bH{jq;D2`hJLXg4=AHD$>!nYwpx3F*w z22KE5>uR%l0TmP!Cv1pF!GN?|t)6PRl*E~LE$>j6y<~BzMI2{Yqd8lzci(u^txoaT z-~6V#R+*cjgNF{4%az>w#E>YQJau|;Z_o8Rwx?-z@1A|H?B1=e{f)o)_Xpp4ZP&9e z#HDUl<3YSh`})^Dwd?s$-+f0jpTB0?=A}ble(ITBPe1w4_AMJOziji86-%(X^r8D7 z@sP$r5|yOmGecwzc_(QaAS%>^oISsHE+Zlq+HE-EVL<`6MgCIhe;A$%;7S3=R#gxv zIJ$+j3*j~brr7EdqJ$i^qKGpP38BT}rMGBUg|H}7q{4GY0K~{wrbU?vuDrdx!b&X^Wh^$2x(+&VsOd872CGG{KAWa zL;YFaK6d2D&iCI^E?3^%`-TF}&DMK+`$mRGoXVob{U=YKK6B>6@x#ZxcZMiUOQc#$ z<3*J;FQ?NZqs>MmiId*`-aO9^A3F5*n+Hp!QeR)U0w!^E=)l2UT|GySAD@|=N~0tx zr&*R+6Fu_K&!6q;TC?t=mtT9Ot6Xc&H}~w_w{G1Z9WbLlrTE(Vg<64ez^ZFI!^ItspV70pvS?g4diJWttyxnntsMer37a1s( zN?Gn$*o(GX8K8;cI7)$%6hRx!1^`TqP7px5)%xvw@4fcwYZoo~gj@B7LENxz)#pC<*}=gW!fF3*RLpPZPS93H;F z?7e40mWVp86GzEqmtSGiO8>y(fklh2y=up&KK_aOes3 zt$_p)k&G&Z{-*E@qj36=>12VoZkc`Xv{=-c$%#@NI{`)y01~nV04$-tiIE7rBc;5< zh=?MnVKEF7laq#wjf|p3-T)~Bi%Li-lQqpu@B7&!opxjSvZYCq43CVSA30x6lUi4; zlV$apdZX0_0^e%X(xegiKsXU?7n1ocV)d7j5{`PAw2 zdtTpj?KM|4+lCbz^KMola}<#54Q5AcfLM5ch84! z`^}5HFI*TVV?fj>Mrgcpeg##pOpz=Y#KL||yips*ld2yP&eO(V`D$duX7H}XIE zw}1SF-~VHZZ7D8^XtPycv1IVtE4QnFGEfvnC1VW{Xs%)~60ZViLbz5#c}>B>0pS0U z%m*|i%)H>1Bt!u~QC}EY!jZ&*B^@XSMJzw?f*cVRq9YoGeu=S`{qOJDpGHQhwE zlVuozf>l$RY@~nw?H_&pE5FlQD{tuSukorThgM@+I(ByE^%vfK^T5d@DH{|b zWs%|`q~yKSTODJ=mKVJ*8Uz)H1korcD}*X(VpIVmI3QAN zJP5rCr~)e?sDLpR6c{uLX+iNw5dt6qLO?f%*tiM^D4D{agc48+;R8bGoi8*eEI<_& z0F?+hyyJj~RPetAiY>GTlO6zAGU1tvfXab%LZSeoM4`ciR0K#0bZww4sD`H25KARQ z49X&4sJaqm0Dw@{R7^HNO01#^7$!Fr0HflH2~H6KtuZLlQ>_YzkSQCmsA{}XgAQEG z#Nrup4#WyIXhPMSkPw10J3~epgf+GX)hM%#2#}H}bBjVvyu>o%-Ea`*^41%*zhwRyv) z!v_z~OwVNP`Y(R@$gMkX`>lKKDOW04CwuFycP1t#F1_TEQXGwqoL6?$v}@%>t1k?X zd(P*lXUnl|O^xvE`1O}gWth=`-iKDTx@qzwb$J^QZSarMO;Hyl2Cyk4*Gyy?c9 zci!-$fBxAMPdvV2#fsG{R=)Y>o3nE>wVobpDYE3fC&f;yefapX%PzmfcYI$p8on^n z@tqo0)1*{N(#dSHop)NzW?uw7y?rmg`r1c7+7AFK`oi-seeG*sx%0L=Uf;WKetxc0 zGJ;U;E}y$_Ax$&|7+TWXX*Vufzy5cB=gzpZ=k2%MaQ*e8qoYTU9GaS%nHU=pk;T1>(zLXG&1xG*oaM~y#Cgf; z^Q|KX-ZCqX7mCNO5KsU=S1qBoG!ajtmi4_MCGbkiKLh_26?4k)o2dBqF6!NmW{{P85|Y z)v`8VWPD;`Vsd(B4h`8jDwR?&CNUP!umFf}wVJ@9L{V&08=)~S%gI`_$j%dBF5GIh zn7LZ1pf#m(Iqzi6dOb-}N^I6@Wt}|KCsGu}#@finX_{qiP)L(_W_mi@Es`Wj(?o>X zbE#DJ-p|d?CrOmEbec_{dsHNgWQaXG@0oq2T16WraU8`_tJ4wh0m0|a<+(UltCYKY zx@}~@E0IwYV`5;hUc+X?f(0P2tSY2r3^W=I8^w-Mn8ARxQE<7DLH5p&K{VkmqpVXC zv!N1+y^sYW$XXd8Az)+)l9<__K7P9Y^36m>71Jmgo|rv-`lPsgdUUkaYAKPT&Wv{! zE>RfA*0W>Bv5B%)D~@ADShZyN>NV@UbDVi=Op?S$Pn`rZD#d)Mz`66Nvg_$*uh?-( zDNUVYKyl6^q02ksF|AhX^Rp+89Bs9lUbR#zlW49v2=9Jl|4p~t7{%6eCgNE9+O=!q zBn1E@J6mr%R#7oXM3Ex+oSh_3|7Q2r4I5*dSoMx`&h?I4cK+;vhvpiMEO+2}V4#29 z+SRpc<>0}C6O+?DeZ8y#3Ph1o4hWL@AfnjFB51wQeCp{JZh8N;wjC);v)Np+a`^{u zzw^zv-mKT>BCtsu-FV$K%a-(wk54)0(pn|!z)LT^>YcY_3VA^#+)o8U9Z*ne3fxyP zRErb~_u%vj=Olzskpfra3#NrqNBs5TXCqYG-Ip~fIVgNx4kw{gI2_6n)W&oq= z0hQ25pcXl4*6S?N=FBU2K}8^I1Xx^NE7i(L+FR@Djw_8$>-5}QIrEt@0Gh-p3rx?? zO^uE1diL4I{M_8+lD%*2>+9_;mr6Z7T?yLR*_kYFCsE0kN+-^oUcO@0ZMWUt+uifO z{rkTj9&ZiwRsj_)SQ|Cw=WUD~?S10qb1%L5t&iV*^YZ0OF1~pE>h)_696s{$-nXB5 ze*c9FqrJVgN~OfYS*{2`*04aEU1Tky0GKRys%i~-C+x)-5Kse_f^F3VKSmHb#2|?% z5D;NFp$jS>f+DGUz|aMz;dmEC56MG4WX2wP(i(0iu;?mpUA+j90;2(O zf|i6Zjw7FY8^vS_;HavYJZC?z)bieU@|=tXG1m4}s!N3(5E~{Si%2d2P=kjTiKt8l z;wY-mO=K=lQ?fQDLIY+Y-AP22Ju8@qV&~h^X{$RQ$1`PXV^hurXIoH*?j-3?lQL?q zO4n@Lv2x|=g9nd}oE_e@dCPS-y#L_gqj%o%!4oG=ogW_EuyNzjqeofr>Z`6B85#9? zzJ9~{qeoAC@XouoZr$3yxOZe^EbFxUdbn-gpKXmx``gMb!y!TV{osa(P;m05U#jm=$YO7bTx?18o;yNpG@6e*@{2QPP8*<;r%sj9RK(BC)#sr>1}A6c zMkeMAz{<7DyZZ*FW;-S>RjbwUvGMQxU;kCWJLg;Njpfsa9N`?|<{`^vuk^KKS6LKl#alfx+pSnXaC$b7#+tUbxUzsTnea(5TP$5A@!9 z??>adorRJbmWOxpU{n#zs5NM^T*TPF077h6eiw&z?K$Rhskj>^V(SQfW5ZsGuwe zuwm;ZO9uvazrK5Rey*Km!n}FYrc>w6j!n<(*tTu;%9X-m48DEf;KbM%SyOK|ESZ79 zf#WAmeBjnwdVBlk8_m~tzcyQ+Uph3DJ3lcofyQjwwDH{8bJNq)*Ij$<`gIpgPEL%D zkC#fN^%t%0?d~Q+Pd)u~v)ODlvzhss!J#E%|@lV>F4k!SVgkixLR>_<<(yo+BhU`;Mzi`RsO?^FGjoJCUow3Y(?e{)A zHTl6jZzI}Dxzt^)j*U&%vvy*m?w+25htK@#*S{{6QV>OpUc8C~wGNa5Bq(gdK^9z= z680aes-a}F$n}Rit_qP66bgQeaKR0h-f#dTymwv%(trk2ZTN!10Tk}a65JB1K%}`B zPzWYZO9Ud3v1ybvBulKd2Fhv814W7Lsg=?=ifzoXcBR(WTZxqp3bQ9e?L0p}I@*_{ z7p+@2-)uen$RpKq($m#N#(3w1ePkmt5XbR+qw(agb|s0On`@jpbwYrKhL#u`0}6l$ zfQd+1tW5?6m*(x}KmO#&G)+sjiZxNQ-WZ*jODpB2%N8RT$GHG18P5(7JTOMqsj6tP z2q-oWN`xY8j0wsbkQC@xMGT&lAk`I7uAp;-uStV|1^^0{LeLiiPA>_}&pb64@h8ZaEQbdH_F`xoT9LEc>Ah3d91B@b|yeSYALUFVf1&xA2 zM4|r-QB{0EHwZY8h4cY3f?_e11A%~1mXNj=3cYNhWeph^0fJE&kqiV%hH${-p@E{H z4kd6qLsK@Qh(l8#Uof-^0I7jAjWJM(fK-i0=CTPR6RTGaEM2i?%f?NWu9_D;efsPh z`wqYT&h9Ag>+V?^Csh>@bx}-_5*cFf7*Q^gMu}KbD~1UPMcA51RV^774)w7H(5QFq z8Sx{fl&-nv;yZ7@e8uvmQB;YOuKfp&{OhC7y?yA+)Og&zctvE>$+4Le$485K32YOGQI{DO7kM>n7U;g}ODwcOW{>aG4>7ky%)r>#>D_1Tzk%=NZ*uQvuVr?RD2} z+0cLgeQ&i|JUTvl_?<(X`{8rvzx??xo*zE9ci*0Jxpd3U_y735`}V!@MjXfe0|S$j zlT&jOJw4s!Ql(k1&&*8B%}%8e<*fz)&CkyCcGY_NdQYA{H9t4s)z#hKKlIoypGAzw zma4VB|MzeHzTNIjPKwcjbG^}i>e*+0cK^SuUcK(tTW{a8<&Xa9U+(+qeGe{Oxx7^Ciel@XCu0C0PU0-j zLjXsD|C@}p5gOZWcZdj0${+zz0)~i8L}bVsGENoIqAD{BiZLe3@+^18M#1)y=Z-~I zu3CNhw#&=q^7-?_Pd)eSZ++rZzkd4HFTC>N7eD*EJ+-dPj$3v)ss&?`NX=_YrgumKRk5! z@L&Gt|Kz>ib=Tcpwd$*{y*4>D^@T5d@$k{Z-~RSr{lOo6WpVG~&6~I0e9O&;j~u(| znsv9_a`PYk$-lk&>g!gmTJ>MP^PP{}b^CAM^YOp^?sqSoAHL&`J4ePwZrHkYc6RpU z$rEJF@|7z$Y*>Hv_=%qGp0#V%ee*y5hZQSVfB2&x`}w0kpPR2=e%WPf)~~sE)y+VMn264)kOoWjWSL^9b z<7ie$gR>YQNn)2f6M0}%r8ejNi+dq+z)Wa`rB=bnn%UVoMUCPZ0c}*GjSK()AOJ~3 zK~$mit8*Svm6ZU6(6c8Y@3~efUwPG)^YioK94MGLo|>t@x&N(ZyJd{Y*sFpeLzb9* z?(|nrKD%T4C8bgly44w!#Fi@v3O{@BQ7XkOVidfvGN)-Io<@ep&YeGh<+e-e^K+`= zT~;f>+I6c&M@GW)-5SUY0U;U#2-aAq(rUZMo_zN5%eO9HGB7bVjO4R+qqn=XxUZs! zC?w)FYqfGWFx2-upWL};-@eI-nU04jP1-IKk;VPpo;fsowL5L^{kd}^yMF!3m%i|k zI9@a}JtcX|6ApBDv6dAP6zi>71}c@x{R6#m1V8@CzoLy4i6}xtOV1XUb`fA@;ZBx^tPR;HcRV~kQR(R|mC80s zJSu`wK~f-8QUdh?oj8sAm#u5JTAf@wS!OXET2f)`hzNmcJ9fg6jXet!7>ZZ`kpPTi zMnVN(m4I;qFyU7A2O^0up^CWRZ3Qrhp)Fep#CxH@P(sLrjTR$)5%*<{jS0RW zuM!1*KUoOzXB0(?A(Utk0=}H6FvkRsY=Ku%6g9@cLi$oAOd_Zvc46HZ* zpwrn~@0lImxBInSKY!t+-Fp}HZ=$4vRLp?P6~vgn^#`GVaNNn9eexW_kR5RGcTT8x?;o8 z(`C7WM!7ndijkjb`(k z-~86l;J_RE_W`J|5TT9j@VT?8@xT4CyDf@uj4dv?HCr|c8AY1Pv#GJEUNM7<2mAX5 zD&?B6wp%R_6%k{hfAQeXn{HXuyO@YJZ{9L9J$vrl+0k*i=bldxnIlJ!ja+rr(xIXI z@Bdl7)mXk_#i~^+ufP84EbDyugLkuYyZ7u~zjn>^W5a@e|&ws4tgFXb2I{oIT^&l}gp=+3Crt zNnsyF>HK`_!G|8Akk$d))m5W3ou8YVo15#cRYoqH6Y-TwwbRK|HA#~^%NjG&8#k=@ z@*jL5YtH}lC(ov7dh^bm7p-13IyQ3r#L;%M-D);x=chr)7}L&MD25D>VyD&28}-oU zl_YUvcG||t;>G=ggG=uH#61_rMjv|QvG0HX@9+Ke?|kADAFEVr4?O(ydZS(IskNXL zk{$2q;*Jz!D-7gB30$S8K^y0JTVc zJw5GCXLfG3Z&9Bi6Q$|?x8E8bAN};FKJ)6HJ&!#4i`(zGYwIPK?0fT#JMQ}66OTXf z;KL7p^0z**iBD86Fb6<2J%?AWoR|MZGU z506x<<;`2R*aUv{^mErj0JmR?q`h{(*=T2M4(nZ0w;YITqyrX<(g zgA%}ey#Wxw3*cOCV$<&A)wo1JVo0M%1WIXnf~V5d5RgR^3Oa#7LbBEng9=MTktirj zUw3c0g0uCUnT?G~)#~WU(|mc=VDl0A0%4!#7@L@DcACb< z*2aT<-M@Ht&-Bz-6d3`d5L$RFvx?{3^V^5sz4n?*lTsziGbWn>3=IqhLSv)e@(!$x zl{!k1_YjlG<~wL(QbE|tqec|X${FnlvcaCoX6*0d8gHE z3Y*c1R;^}DrH3MFG+W{W$4^7VEQ;gjUVIS@T(Wt?){W~qZ@1f7yEU&?8G)E0jLPLw z+Ese`J)>VbZ1K-H;0 zOs3DqCtu$O*1-HUj2v0L?UGK`89jQivwoxP>#G>s6aYb=<*wbS43(GkFZ%vJ{Qc0- z;AejOo)?~fs?lgvYc*qyumjaJPK3pn0IW{MLZ%ZgAxcSDi|adv4q7^4M2en zT2&+i4%8YOZ2xf-8&&p>*^6>`e*-bDSbk~&p9-mj0%r%n8U&!in5`6O{S*kC9Gtu$ zY7p25YK4f3S+L-GRR*!5tZax>Iq3Ve@c#`_Gzz{R@g`Um3tx|b3K9r202)#ife_+H zVNei>3<0x6WnszlYN>tw`-Z;u^)JSY`ap!|Cpwvy(j?1shM7t=-Ff?MJ8!<}u?HS` z;DIMIHmYJA5}G`7rKFUW(t5j7D)lz%9TY7m#%B&0K_E$@jO*Ria z`FpRrW(Sr_(yY%;&nM*w09@9YoM_o8ShsfNUw`ZCKlstE`ybzfwn7wnc8eA*+Iqv* zM<4s8jgot=?&P>mI=tCcFw_Aq}9WrEwhKBCG`|kcli=4}U`O9BE|NQgSu1a@r z&&1gHlA&ega%pCEzSh<2#IuW}-Lb+GBj=N@Zm{KYwZ_0`5Xf}(bVsoz1Yk)bgNVO= z>Y3XIrkieZ zdA{q(Cs(dq(dpzHH*CCc_Uzt$uY0FtNm%Mx9Tic{fdhyB?(e^M@rLzdqvJVCr&Y&h zE3!61;ye?@Eb9ynuI%oujZKWB8fMSx8_oH*-kdN16dN)Y1iZ9uY?HLc!UnD5ywPm< z+(%Jl6B9?)P^Ht!R5*?!)EGT?+KuhoHvPrF`$nrd_r$IzH*emsb<XqKyGBC$k(3PfHQ0IZFTF@)-zR}nG@jMfAY zHV_6kE+LXr7E~|<9CFASx+8!zNmC@_eCO1eQ_e|Gtu{M7Jv%pdVfeytedHq(V-pYk z>jPUiZ(hGZ*IzRlUAKZAujlcKhFYVd=n#mn z=Vu!jK~gs4(x{wRfL5pJS(6Y%F%U;F8WWXEv2+Z@X{q7_I_-|CGDB>LCG1Ght4c@! zsz*cf3(QM78J zG))d28h!M!$KO5tu47k9%j1)iOP8-qOF#x*eQ94DCx|4#7L9YRoh=PD|ZAylrMlElzb*0FTPz zjR}(i1dI=OSxFJ)u|=x!eI^ z1SCaKEvRw<*3uw#YJp|};jlhpPpB#ooH2%w)w!&>e5iL~auTA68+NR{>#iHxt;U(N zr;<2PA+QwL#JS8n<2vnnr{2GG;Ii$T(u!@i+TA_9kuA69=0`_I^W63I_BiLqr)CvR zl9sGV*m+}3Yrc*Nba$5&InNw{l*<1z6k({r`;j!$|9X}plU(G0tCEL0VW9ur60)t425-C!NnIM=6f*>*)=x%iG zK7G;-Rkharu@7|d8$ZzJp!cp?>-*kUN1+}Xj9+>AfJ8ymF<=0+1){W~Ul4Xr*b?dgxm1?r{yq)iO`#bNx=kB@Fb8ox#mNjEz zU;N@1=I7^ES6BA$f9>+!mv7m!`N}J=I(GaxX-wk81Egu{y^M^GKKzs*Es>-~8@(iY!NzmtT1)FN!!$ zwr$;Z;@I(H$4+EfD(tMcnp7Bs4EWH44>g-BN1_0p2Bq|^H{U{9B}vtJPozVw8KqLG z0*As!5)^R%=xV)~{dR?zB7YPPf||9UV=xtWu9F z%B-v`2Ni9Fr6e{86L6MholeJj7snOnEm`uh*Gefu4Pb>4RC8hJvdho?tIz)N3okr7 zJ2U;3n{F5w8eCakJaXu;7mnj7?WHJ!jA57{ic(qtvNU(jf}jG-@|;6Mz)E4YQd3%Y z((b~_+)8Wd^x(jo-gM0^Z+`Q-@wMN%>z*iz-g5J;AOF~I{?kAIuQ&=-1eQh0>$evb zC;|k}S(*w+5E{>3kPBzaUW`)2+*e_6DP9H!#KKt+4?vEYh;q)2F;N`1+HDaG!!V3v zFY@@~kBtqFtr;Eu)#Hy{bM@74yXCfLpWQn-H4#_B!-wD4v-jz*eEILs-LZY@)XAmU znbpO)zxazkeeQ+5&p!Xmx#yl=6h)pDPd@qNIXkwq@O4*TyLrR<&70S4TtEJ`LkFt0 z!42!yhK53;jvPApmK(48$G`v5Q%^th#({k|UVp>DK&{hG=4Of$$BwZpF1h$(t@Y+j z8!K@n017ZPN}*TitSuB_+HG6w9(nko!AAXEx83&n|MA~XojiW$ogbf^oczg;9}s~o zv#-DUYPoIHfQ02UREQL_qtYgzh^-u-n7;Z-6;}sJ(B{dh)n1wki1XF}KtIF5XCT7; z-eT!=4CCnFv7;~SJF<22#%e7pyqucvbhDn)O1uZ91cVel@#M1??K*e+&P~j4bYkwn z>-$$$R)_#md5_+)R@yl)eZM7o@hq%~h%t9AcYbzm?&W<)H?AKa8XnAZfB*fD-hJ== zfeD@WM2H~nj98$s9zc}f@@n_~2Oj+7@W+RTYu>@0=Z}8(JNGO#7ZH{2dnXt`2!sW+ zBFDbd$-evDdl#3ND~(2x*`ml^+rQs=E2$`jKe+F{thmj)A`Ih)9{Oc&drB$s+I!Yo zpEz~ui6Rto-k0RVlDQ>kc6{XkrhMs@=urX$@n!22%ey{dxs58T9;HU6 zWMzm5A|p_L%wN(q%3Fhg_dX0mVYbeb@+APC`=wa`LDJAGdU2$!vt4$9z#uSi%b3Y; zfAO<(6MF$>*QoYy-?HW3?w=lY#Vkikkw@==8DMB|(6L>+c5OH9&d)Dw-n>~6zWT~5 zoo<^Dlr{`b0IV&@C?bW-TEe22t>3WL7e$t*B^;gzfLJi+LZZNSo0Cg(vm$J*XHlN2 zLu)n)8c&*qiC9<^qGNvsVj@CZesQkropp$!`(9E81t8=-g8(V?PD;LtXC@$py6+My zktt<$R~Sk|YuPL)BSX|j7?)_JU#rBh&$?lS1OlW$ggv7A{|_tuo^_wyT{gP_S-9-? z1xh1`fJaq!g&72N$!smlT_mMzwm;ZFB=LPwuochsJZvO@2!_yFm6*ka_l&>473Hoz3Ux=CeGF<0y`kfq@}lfG_|L5Jcr? z(OsBrHk$)AedO4oS6_ZrL^`XjxEhTNk0wd7b<5UTt=^nph)DgxC*S*l-~Uon9c0Uu zC<#oER3mHiEKh6os&lr}>kQdpqZJW^fq7=np2$SIcJ2Dw{P@A2vaVJKN1`x9tqR8` z(2d3rfDEl^WLcVLd81aXH|mq8PG}Ph)*I~>At53-=gQz)sP%i^bK8!cJ7%UA9)0w& zhaP#jv)VlStg}3VcaFVSwo0jby=JX<)&{z&l@^7F7ke}MrCGhrYz8zFag0EuDP<>sQ>igpOH3k zSPirWfFQt7>rP%QFD?$%qd)q+PoFw@{KSdlx7>X5nvvmCr%vtP|C&Z3MYhPpD2Stq z%?m;bqe#3jio#o~Ks-A{QW}|^(E+ifSq315^6qfl#Kh%jrdO<*)B5y^@y2m)bDlGp*PuB`sz=fBWeZ{51J+iQF8FS~5_!NUjA zw0r)Rb9-sJZta-Odx54(9Cp)ougKP~Ul+a-u=5oY_}sdzcl7wtty?#rvvte%?Popv z>@$VS-~Fz4Z`!o+$*R6F$maiFG zGf=PZ-}mZ$_uf;fR&IXF%_BntN8UKRasB#huf1ma^mMn=JuxwH#Z{NbNoCWf^`s;) zboj_&qXS{+rD-LuTz}2Afx>kg*3C{$fdC;g2{MUi#u8wo0K}N^i6{3?PR@f!ty;~k zJ$&Ryr`rxpAk1Doh(=OQoMK(p$cYG5xs@g$e`Mn5m%sWiVT5EP*gf$oz@ggFk6nZb#76%VceBq1#sEi_| zr>0J)c^8S5GJMAT>4XWuS;vZmxxiw%+5FD;@3M~b!g}w6FsQ^;0ddYxOiX?4pZ-^x zX5Kq(bP$+0423y$E-wlZijw&B?EDWNcnBE6C;;HXT36US&%Fqe7^UJM3XFQ~!2W%& z?<1ljEfkSbMjOp6&ig0`(G#;JEkPWmX)!fD^}W0A4U9>9Igud+Y1R`&&m!JipNscV zphy&yG8zCDM}1%^B9;e}e&yJC4JeLR1{!~T;O9CR4ylN;f3J9pmVT8hR`C2xB z;Mc37vcW6hnAx*0FZ~SSy$b>pCsDiG4V11Vi7nm2N(D$&qvw`p6@msN0n6lkJ~X5+ z-*M5J#_${r0gN|>#v1@8!iChyKoBZLTrguN&6ZbIo_zB0AN=S?*4hXV#dlYlm4RBV zQHfNT^}5Pv5q2(3TfHC*t5Ku^$z7^In4l<}(pmwsFnJW0x?Xc`Y5%tM;qU$F`^VO- zao#uE>7f(tfBV)?g0NPrkD>%x8vyZ4LEnHRN-IUW^!J6NVx^UUhzBf}v1Q#^dC%UJ zXT>rYtC5lW((IBYf`9}dOhAbJ{Tug%J|ZH&j=duF4cjGpxF1L=UAU~Y>JtV5fU#WW zh=|gvWV!;NQL41RdS*qMy>re9lx8SagxY}+iUl#E5YYEStocc&#>fPPWT?ThEi2&c3MA~GiUj~b0eBFj6^kHv(%@`rRM2U!1|bl_yFT*v z^L7lT?Y7dvn$Z!@f+XHM=Qs!hFBFH>ZM&`k!)%wxB-6(aFDyE92Dy>^EPg_I^^f^cljCKY!QpUmy>=aHe&Hx3@W<(AtT z^~UkT$6kN!^(0CVl~Tq!9v@rN>9&s^J^ay+eE5+^ezy0yy&yoE4jno1SD*XhZMVJS z1HbW!fBTnz{kt!Hja^R2yDz`;;tO{z%pHF8C%^pey}trfMUidZyz$7y!t{LaTi^bE zr4la8&)2Ip5nrnfz55++U0zx}@W#QVm8GfW<*i#c@7%VLS!U-K7gw6CsWx~jqeyhk7e^32|QK+#GOkd)FA@xomG)`_47Ov0$w z?nEXGK%;d_r%xVxwYc_@&C@IS5AXd^uUBl|u;I=-e2-e0l%A3wE75 zzIHr`!^!E>14F}){_4?MTrpADOS4|5yKZ#w&;R&$eUVKapSb;8#)QWRw^ZX2ZNFk9hJ78c?WoM5l&vRu0&(d4%G^&*_NG2zzoGmWA;Np#& zHhuDAANkt9{HrbUKm46L=VxYLdg+z=z<@2Kv0%Un=)S2(oHr&=M(4eJ?bukJrHAK_ zj*pEi6I%9R5N6huH_JRtt+(aQI0&>-I?u8)2ye6|0c-Qy@A%+`4V#KQ>*T%GYMU5O zO&r~|b7!Dbb9rTDe(^KE`#W(QXIa{6HUp&!?~Wcla_IFp@^-K2cBiK&HOim=>7Qh_ zm^gm?f}J~OXHUO=VE@F)Q`^tkv31kdcC)j%xZs%)A&!!#o_>1E)-72tGe#{eEG*8= zv2}q`4kS=&;^?vVO7rl+LuYN<+H1E58;!lsKYRJ*mt1zq?%fw%JTr6pg7eP1VArms zQfaQNKL5h=p$QgdXP--NqI+70%g6jZ&PC~Y@wZ* zK7D$2b~Y~x6pW1lF0Y$fz?UWijpR!)C4y()&C>4lw9-ldY>}HlBN~n9sm#qFcyGZG z_GfRX$a_JgC^Dpsb6#sj0G@>uIWNKx=-4Ui3g;0zMOXSS6Q_ePPg7)Hn&7N06afPl zg=1m%UJ6g4NjdY@YC$0_0&y4?-g)+5krV+y;VmK{Dn!f*gfUzI03ZNKL_t(@Ulw#a zX=(~jMC@{f+Js@Z*99OzinIYDjp&$-G0r(*TNW%3QETI@6>$uth`3Kk|Mj%2&*&lo z08)hD&wvX-otdd|3AEMyzx?Y{PCu;B=ZKZF+j2Wwu8aV4YqjS}7{@`(?45Vwy&_e% zJ}O2n^t#KmS7iTDrUp_Q_*H6E!hc>?B_FLv%BdCqWOlzY`!dTOp zGGS}AGji@ZA9(K_^?E(;wV2)OukPFX+;dv1NC^nx9=-~ZizuGA}|BcpTEvkOa$8#aeKcfgykzxw<4J^JvY zuP9wF9F&1nBw^2ts7wG^MudvA2n!bqye6=g`#d%Q0axZ$q(8x;5}qdFh!kS~B+=)L zC}dZ{DNF2#5TR#gWUT^!CNV<{Wi`PAYo!&G-c}&c3Q@TH!bOBjBozp-uYY==GZI zg~RpAKo#nw{Y$UxC1RzMDy@l=MF9eNRZQIsO&pdr< z_ocg7vcciHT85{eev*_rXZ!ZfT&L4%UVGK04?gxKRNlmyYHVqJy%;h^zOI6b#S0AhwL?1?*8GAeuMx< z8C6!(Q2qKc1OiIP_lxRM#<>9i2-$lDsnu#n-q`<%JKl2LHJ_Sq!yo?1 zUr(Q!df$6*T{k{bq-{mK=G+~-cVDvS**)D(YtyDn-*Mya3}Cefk3RaCFnj0HBDaP6 z_(y(oY;@q6r=Ps>#v4PU(zG~!>}X-L^0=?HM$g_`=UwJ*K9>mP^}V*n837py_QyW*g)jg8C6`|MnNQ#O>CgN@ zmgj(=bON(-@biI3kzwUwc4En2M%hY=U;enVPR=*X0}nS z&CSjIca&)bw;U zNt|;m@{Mo&zY1}+)&AahzPHkBhG7UGvva4v{P$nhq@p-JaPYutt63Cz99NR0a&mfV z`tG|LjRqhbo0$0Kx4xAZ)@XIlJ$J1gTf5S1YGc~1_R+&fwblm@A8fZfwfcbf{wx3Z zl`selL2G&G```WU-29w)5odK6pbh}MLS$j*xGXa`_6S5QY;#Y-;y@@4A}JMQQr?xz zHF*EB$1Dnf5WRShjFz&TDNvwlUfi(CJLf3OyVRf3ZuEO9s~-@ETn;)m!c?iph;`zJg`Xr9|9~M zM3@zeMH1&M3OOzSL|DWYB8-ZNRA|DYuygY>xlJ{O-id(JYn5891_VpX%iVU@dv8J` z3`2v1VHhaVrS*bJR0fsA4iOabaEAOQWxL3;!;*MgDmIZyh=}i7@cJj15|$*+Ngpj; zvcAxH&ax~pK_y9;InQ%1tVEk602E|IAR_IGJTwq!RR7r=TG)xUGkS5g@G zm#=;sx4dcaoGa2LH`UE!w1d#o7!;}V-px);E^6(aRSMqyo_7K8o@e%QW{n~%))h9; zbnDGGpMBO@zx>57et7>~ig0m$w!7q5Y_(P&8K}=MoNC0Cjq64~^c%Mg4c0r>|NPM> z9{bg=io$j}E0rX={q_&u`CIQAs+nh>d$HZij0zN?wHYd9EjOF1#%LYTQnT=SurjvG zn8XiCEmm;G@;B18maAVxtf*rOtis#Jm~B!wiv zBHW*!v1df36cZwp6cr?3K`gz?!csPV%5IGSASebQC^tO>2+aLM3M!?w0#|;8EQSz7 zNTFCuN>F+5S%4ukXyLMxgu=b}X zkDi{NIyyeSUPXd-rn%fa`111`)^BbM3{+roapL6E@n>{Ux#Z&A^`JF1`$~7=5c+mL zHjq@SQnU%k+T0@+{bGn_bm%cpi*B!1vNGeK!nvx|VeMEnKWn?4)!~7vLPQ@3IzojQ zXu)>TJMW?^!&-&&*7E#mmlu_|8c8G`fi z=jqvJZJU~!Jg|TNrcImcW8=kY6O}mY#XBw-Dqh5=Sr?d#EG2*>P7b_&pjsQcX!j-B z7@MZvIYJdDNzWBtc>RVAw>AbUaop~7k?5v3zok~M@7}%p=Rf<|_}H3@FS@ANYs;leu`Y#`Sbo1uT*I##Skr%Ubi^iyX?zvkjy6*a`=jIk( zeBq^fz2Ok5)!OpHqA|hXz+kJnbkj|5KKHB*%$CB+%u@5`4?ptK%P+q5=IaIq>WzW= zIcJ~!`s+tdO-y=cy_dCX$4A$UgMnJTGCeb^sA`OH<$BpO_G1L4Jy`m87?!eq=tWQ| zVRk5jV!iY1QDG1S%2B;BG(9sP53B=p1*gl+*)(g-O;0=LheqVsiBluPYo31csUt^^ z2`EHmttA!_Vds0D?$uZA-no6-lTSQ$&N*jSE48V~$>Yb4cCsF`S46gO((WiSVH_*Z zidEX{WiCgLBBFz!{GC;SF{qujS!!88A);rklqQOdS(=|686LDOvokZ#+2`UY*tvDx z2j74DPk#KsAO6vwTy@2p9)J4Dq0ymgCFvCfGlNGWvc6#9fuRO_URqozip&`L>;Lj! z{_EfVx6`L*2Zx8ygSXDI0}!o)p`l^#J$s*KJr+i-%Ew1$bEWlgqw&IXd!Ncur3g?f zrD~N*tGWElsmUac8kGtVzP#^cS6D)dD@h#1MC6$lmzNYk97SZ*?85Bi^dz%HQ4|G% zFe@Zrx4g9EoCTuAqYGgacDrq(m2;9?s}KeUhY0A<;UiipR}_qxL{Sn)F3-zb?#fDY zc%YF4$?WN=R&zOyE4^M%DcJwoJRk-^G}x$zQOF3T;Bei#bxSMD6B8$t(ad5y-Abe4 z#g%eYqcoRB#d4603Q@`$Vd*d;P=d_VZ#g2CfU!O+({tH2LZni3Pe5Y5ML>mRKLV8@ z0`#8y5J*5|@0q=|WDK3@YzmQ}Qbf+%a#zainH`jY3I)QTNtZ5VGJ!^AU0L;1tW@Eh zXU8Qlo`tcyCkh!yo|XjUojI z0J$pwN(Kd#^gr*)#)s-hVib1Tot@jye*bTNpw(=ybR=QF+4GgNjI z2TuB&3sRCo`7h!jUr3H2|m1&}C;3TLw-*Bp>mN)vKk zH#|9UXrM!n{IgS`R7Qh^6Vw#lQ4YsrI$|}JO0A+&j&#`IuyVA zt=C*};krhBWN>V)D!NYm+{|L`?dC08R$3{G9~&8d{~hmFNWx%36@(_K>d$=aoxkzE z>#ef}7!_J!RFtPS>vlma7S~I|haP=>a?#B%EeQ&d;_|$J2!N!By_G)PMo3Xf`qO77 zi!2NZ5l8``FVVMLy0Nj0s0b6GlxN!#dsNo{%IYtaAb2AsL=K>Y8VLBlR2e`Kov|rE z*%?$?LFs}*v_)Q;6`XgvWY~G;K9nECvk-`(ytOicwk=^CC9y)Er#)vmi6iSfwlh0C zmMqU6TA4mLP^(rnWXra@_?qu6a7H8JXZKc)H)jte*j|~LJNLpX)(mD(KL4{YYc;}J zjchf~jvd|ORu5Lkw}h&>GT-*?;~~s7qQT8$;d0)r*Ej@|F*y>2kz`hc0hMQ8PXZV* z*5=GefS#=c?wT9UTUi(xY7DaX-W8;j_oz)^trx+wwwx8#>REF>Z7v2{d7>bS+lRyx_1R53YJomg4Cy&p}oVIyht=3zuRyB#jAnta% zz&@!YLwU^Z{tx^~^#7hid$wc6US<*e$!@SbP)3UicHre|iowRxU3SDTeMy8lNH zJ~=!bYQ5BI?%Vh3mMvR6=)d{9uMP|iPaHqCyxJTY8jhkMxAL`r|5h)}I;~!oXAHPz zbd4=+nq^@edlsb?c=qBL5JeOcvj+gBG=X;gP`VHTd-mQ3K@e6FFCLJ(X`Wkt;3p4_ zZ#g%q*26eim|e`f+1%Ws_bw|`ubU4vhQzDMQ`1Y$CIAIWZ(O$l6)emz*5csCH(km_ zciq}`JGSqbo1Z;#>`2<{p=Y)Q1L`0^P+=6X__z{jM5VFQ?g_AWUTh{>BVwpEB6*() zI8u;hDG5eN6b8Cht!lk>X>m!IBNMDNmmYikvC%tjzvafOj~qGt&`%!t@CWZWe&SfW z-NKl~+R_V3f`MS1#NMU=aKm-iyyu~s6UEkA=cHN<5usYERI3$2Vb9{(`=TBN)i7YsS)LK0u0|lSLSoO( zX3p}3yLO#-?#@o9bNKM#FbuWU-gy=_T3hb}tx0LEDT$MTfyVIgNUc^a^1R*cCQ%$m zabDz4?|J6Pk)s3k>cBt}hmlq~&vWNo7)3^#Jj;7owqwVRb9d}0^5VspUfQ>RUy@Y9 zFb1~NKwCHw2!bGtbr?i(6t_B^O1-x0g7bHteNKH~z=6E5XYb>W{vyx@i2zDVGJ0`{ z#L$=5l`RoMLMVX{<*0)-s!}zJrCt^U6$ny)T;WUPW69DMFANMQVy!1d1e9fY5g4Vl zD{=rJ&>B#j7X$}Bh)fbC&E{&_ZC8>+DU)TX_g1NZG-aI(NmY`HQ3gB#ac-^i9*{(w z^8#dA?OvYeNt_sC0I0|~_|(aGqt(d1l|QS_lI`;an1hQJ8=$)o}m> zNf;{=thSq3FRj&TL@qD#Jh$F+tyr(Bjlqw8?4zFy z?)>`K|KsrCBkguGPGTYwArMg7Fk5Cu(1?h_Wj??;hh@)|rR0u#@k+3;EWk*L@C-nt zJjn=($kNi1Hu|0KeAjFH-&mYqx@`9)Cr_UG)Tci6Phb1T!n#j<;*-oWJ2%J7+js2v zzz05X@4fe=SsDhRKjRiJ4?iMu#-J%>iKBeAB0*_y`9I<639>$6lQ{ej+qcHH_xx7n8UOA|pdXBv2ZX z9k{~fX|Ii1hxKYKqyR`j0KDf$1*E~bcc`3Jm4*4PI zVsXDdnF5vh7*c?w(6a=(?{X(9gEy=Yv~S69-`Y8+_i@WiXxN#Lca z<4Kq-O&r)aH4#N|p7yFqJe~xvKl2moJ$qk|l49}Dt52_Zc22o!z3#+IVU^KYmO1Nm zUGuq~J^n#e)LbGm)o4ngqFvnbIb0>k5L!{M>c^h7i3j8+?IFT(#A<(D%}`(rAp0jZIBW&&|(uJDtJN;a)GR zBwCOh1E5NCr-P7~d$#CyvT72Xy=_z0?Vdb&vfenGlu6TGtdn{azqI%H)s^N-yLIs3 zkw#-+WqI-5yYJT8c=jwjGc)`0zE>Ip1L9?7c1DEbFbM;4)`8#!7hW_ybNc@K?;ENQ zHU=84X6swu{&u}y|L})CbnuNsiz~~UH*FT@Cy$;ud+WA|Qxn5MgdkxQI9Dt$ubgw) z?n6h8-gn=FMu#Hq+;h*~efjPvO7=YS+{uaQrIk*#TD$D>%N7?Gx14p>N~^VJ&tC6& zX>swhpZ$xq>o)xBzx?a$%xoCP;BDa;fRZE<5hOrB?U|Hf1nWErTIXz*De<7tGLym3 z1d5S#*ebYi#1xn)Nh(#1L6+u@p>VENiNhes({30?CXU<9o(Tz9WvM$s99SOsW_=JduM&Uo~*W4pL*u0x4re|_uqc|-+ulJ zqie=L`jHQR>C0aZ!k9$Z7bUz1kphLSrRCv~k=++wDBdNBQ5qh8=;78%(-t<%Qym0R zkN`sz$6;t}o-Zyh$5A5IdG@Vd*E+xLtaH*Vo1Q*Zuhopvo}Drp#2ElYAYjzWQ0$md zAt1$JROEJXdD(=)Ioq}_&dpg@tQ{X+m|e&^T|p3#o?}AD5Tp#o0h~n9r0ey8@$vC3 zn>W9H;K1zc>_DU8@}gRa06aU}^HvG=vXlkVtP_Wcb6i+^{P?k@rKPoN*9B3uytKlO zw`|@NMh#nJ&Nvh>TDP)Zp7wgZz!r{~UtL&UonP|c>y7%gZ@O;J(@)tf*OiKO9u*Y1 zEob;a7#eNLc?p#ASMjCkwM1ik1=R0EqX3hXfxi-qCFO>aMHB!cSSgTHy4nc?LyDN; zqKhtm?X_3(G!3J$Tz`nQT8JW}1byyS)0M#Ji>|oh;Gsh+E6r_ZZQHP6-KkTPv(u+< zyY+3az5d40qlZUF)|5NkJkLSM6}HIJq*m?a>1CH(x?|_|U;N_Hh2?qgrJB@Rt1BQ` z5Cx@JhrO^smi4Z=`pQik))OhM0#brX1!2%?ckjLX2U(VBtqf@a_JU&F^76`!H(fKj zX8eI4KV*A0s)Qf?$j4uN@ufX`o*fuy7-PH#rAlmJ`Ht~K3V;R0DE+7Z#~(-9yz9NU zfByge+{$wHcYpi0$BrKh<4Eh$0Lg%;lo25i@yM$0=P5BN-nl}fDiwICE4=p#bzn-f zibo;=Uj`&hpj(~RRaaa!GQ8%|U;g9Ie)iDAkNoVHzxdUsKlAC2{MJXFeCp}3@v*Od zO1(j4>uJkUzVz$ z+eP3$ssl)sD#UVsE#A|apGZW2$XhGI&e_5$KvJX&XRA@Hl`_&p$qYIoBCQF1V8X0e ztye1hUfF-gZ6DAVUOzan&im?`9oJPW)uv=%3s8cDSud@Q4@IFdS_>%?P!O23muXV2 zu$Bl7B8x((CT019g>h_bIL%s?Rd;EjvNll;S5D6W>bMeBk|Yi+_@dM6iU6V#VjwJo zRVugEbwEfFaX`*9Ao#+1TNECQ_DPh_PM;hfJ6owqWCC3llBCT1lw%J8Dl-@eNPuO6 zij^u$$Yr9XELNRizm;KJ1yJ&Iu+Mh|CP7`gpZX1J=%ZlEKY%6PR=^PwN*QG*7SBjZ z#Gr!G>fq0OQ~fy&3ZfQZ0k1>|$b&FjMLINulB0B-Z8|5NPF56oWoWow8|0!JP*ykH z>BG;Ms1h3E$UxzGHuH|70Ah`&Pad`22RafTMkbg)^;$3OdhaWv8(h%}4flHU-Ci1o zYgU)1i_T13jZGzr0^jLOO&xv}B2vb!%!v+!7>JbCLGF8W`4_(npg-#Sw7=@Kk zS9+OFB}|eq2m|kxcq|BAUg$Wf43D*DPPW?3IILJ9(ByNmy)KG#&Jt-5wg4nRT5A;o zit`1sDnZ1|&I2e?wMMPeX;p`Y*E)at)RgtURvXaRvw2Z?mu0r(PYe4n4BL5L*nHcz zjoY?vYByH`ZAj~x`T1_Q*QjgfY{BVEFT7ylxK>R7xZP~cpPoZSy(|-vATR>FxUis9 z5JfR5DY052fZmR;U9)%Zo_4DRB8#ibfPk|nGK=>PQLMA-zY(=#J?L6)E z+AUWUdD@wpnm&8`jx_rd{Phu=+4>}m!X&gHiZpo) z!mxa)h>#FncIEY~LlcCnt>#K|xmrzXwd&IR!q~bkQKC;yFJZ@2sufo_YYXR!@7;A* zQil*V9@RX@Nk235Y03A_VcS$U0qSsl*kf2+#N<3h#+f zyzk__Zjr{!h=@v8!hitVt*%04OkkaJ;t_<|=V@9=qSG@otF89hk;e7cUi;IZKJc-R z-?{s;%U*tIf3=o)FHxWY(X$kJ0U%3@^Z)zX|Jww#^PF=Q78hT9`L!?z9fM~`jEO6e z%iZAMkWx6kvKWTZhkoOOwQBXQ@85mo@ZqFdSu-;H)ShP$I0-}Vy=TxOnJ<970bME) z6`)qeqbN;?5JgcOMo}DfJDn#Vf7}=yMUmF@4tR!)iL;^n4WsOBNQC8$}RL#;ZkV1g8o6gTI*gUV+>q!!itr>A* zed@qkDIbW=8B{>Zv31@SsmiT8aPUB{+ugclbAIWi7hJIG#TT9rqfi*SX|I>&8`p0@ zq^aqtC<+JaHSql|Lb(Abqm?8?f{ZL63j5HlGbNHTt3bm2o+q=nw#c*WtvA2r6Ce4& zH^2FPB>jhf^r_cgJMj6x`(oDX0V&TujFLEx^PC>P3Pj|lm_M1NYS6{5v zs(=3Hf4X+G`tT!9%r7o}?6=;R7VyO{ef8iQhqMWlM&~&&ddrqAAN}Zuh25ur=lB2Y z&;H=uH(lCpFMsPh_nd#;`Cs_L-`w;4AK!o950uuVwRau_yJ`1*x4-+h@4UmN-~_Dm zT1XoN4TBXp_{QOq zgcckl5Ta4qNlC+ik}!&h;u#qocv5J4nYD!%4zwsxCNS&;rHnzdXRkfgD)oK)_Rq|m zzVo*~{yV?>nW3SPTD|)Gi!VfhAyVCL_r33Z?={z4oy5uT$ngAp*IFAGBLE(NxDR{h zlG{--OGHR%&*k~V!x@b)Apx*Lb!N6y)|5+-E-0XWq1q7;mf*Ag>r^1FBuLchcET`3 zO`6CvdVqqh0`cCK#=fdihE%G-Xrovfl>sm{*G(6er=Sbn8;M(0-hc46Y z&WfQCWi%n$+#w)^N?YSsyGENJ49HO4>2ZH}B;q`SdGhIJHjX7%?Y;^?0KzpJx2>6+ zB6NXP0t~>FN(~WQKOaJ*3GCp$D+D;+$hq6e@}aM`l}6F;Q%Dr~2?% zKC|>>K_Nibj{#x1f$kT7NHg?nTqICCPy(g^03ZNKL_t)_gcX*CCdHonLotN%GuLFG z%mxsN=WeWdcoCu_dd1SSs+irV1+eetP8N` zU3RHfn7TZv#!+OvSkQ#RB$(z|r`xGj2Y|>k4m5`2YK3&gJ58pFI_WgqM~_UTS%DPg z-ufKIHf>2p$2$wt?dDRYK0st_mU{MKB@(R>2%M-8JpzjaMCwe3-vm(^#{dv?S}OoU z-L%_ox0TXKr8+b`(&}^;=jH~620PvM^73*p9z;n+gr0cf>Dz973wZ1D?1md|3Iek@ zyRc?-{c6`e_x!7IQW4-NHc%ECQK7~l47ComG4*=AoA%o6R-ld68W0?V(z;BTiwFQk zL9n#Ac=06{@7eooo@dEGBhRupim%#z#p25H(G$l<2Zsh~gJ++;ZO4wCL0~Sq=#s~t zctQlSEG>t-Cr%!(N71@XYi!1=tF4EB{)^F(kxd)d4GuJJzx~~lQ>T_Yt=Z|>$*IXG zia+t`-`>4@_ftAn2Ne|-IiKY37!!aIB8%{Sk8(@mozqhJ5V*MIS=UnxaOYZ1=U zo--PeoO2*<`}Xah`|Rg>S@-cL9)E7{-n^S--Ck-fd8ea&e4I9TdY&~b^c`v-Uf7{t-|IL5Ca8%k=m zwAamg-SV3w1ON#FUHV*8eoh@u3EJ~?%w_}|(nox;&0pVV!Q+h*} zmX?Vihyp|~fsW%q5e1o16W_ zCqI^@`P}Smnx(y7cXW7Agjq7BFboVzP!twH8LbPO3riRT!Xl0f=RBY`6ozJLd8yv0 zYOS4hiXbj;MvAl&1PV1eYXe0|wPuBt3I+xTo6Qv@0Pur@gOz&KAO%KyCb2$50+1kz zYH?HuvqI-Rf+B$7!3Lr%%+0P}I~GTAnx|R|i`Pt^y#N?ZmI(n!q4SPVD)m~UTA5#5 z_{oD0W@%QfR2i|^X(QsBZ@TFNANtV9@bE8x@yqXh?>oI-8b@(?vnxv|3PHq`CbzO8 zEB);cAfX_X6Bg(P89)%c7fp(ly8fE0Hm@JJ;l^t_t&S`FuJd>PUw`*EhYlU-r0I!? ziI-pAR}@(og)F?VH2>zCZ+!22Zkn0xTy^DT%)Dh|b$&h-U)*r*HMW2_f;FRSUVH6z z4-!(Swf5fKaMQI{UAeX0gFEiHz1vNf3b=IlWrvPT{rR8$-rxX^uNxKc&U*!@l@{-Y zh6msE?sv93(pqVrm^_65)hMo4ldxVHstgVf4d-djbuO8tf+8RnUwrA<+Oa2IofsOb zefrZMfA8(@V%Kd{qtAWrFJIaB@{uFQpL*&UWQn2#uq1O@BozixUf5HU6N5v8S&=2R zczJPt;@Gh`sj|0W6k6wdSsK@?y)4bsUKsc=3I)WA2WBrqq=G0cQufSIplj8kIEvW& zrKKhB^TK+C3Xr^K>mAVlN7S2!OIBTHnrp2+oO5E1JLf!*Ku#oNf)F5t5CWme8ZBE` z_T!-*yKGt2?JB$Mr@K{cwa2on+|_o;l3gxIF3ZLmkOc@K1c)&ibAlw3Omd#@95>=d z#2NQqtACt}eE;Xo%!qj6?7i0ay)UF$W{efifBe)_tJX}dU%lr3fBL6=`}UnVf36xv zXV0Gd`>%a{_nzIAYAuYSxw-kj|NF0>J$tTJs}Z3f2#K%&kN^-MLkVEyl}*q}fp z=h>lBE87fsdvYKG0B+@G!bD`Pb*@;cAeFNlcHUF7-R$*x0-|YU)0kwLC;;I`HCQyA zWmB7NyGDZ+C%99zxD?kS#T|+}h2m1&-CZ8s-GdYYMFJFeTHGn_ZpHWge%OB?lSyVS zJC9?nZrh{9v`(!W^qf>i#n{ead4wSN`XI#W&7FV4U>oI{=xuXmk`J7?fSJhuiVogZ zLz6OBB9}!$zssslW^VF1ga!pNIW2&8((b;%I$7}cns_Hv;naCZk)|JbH>$K(9Z#q? z`Z+fCT2V39p8`nqfN^j$uceqR(fngiOP%Pu;$jhvp||bm!zXoNS3@eIu|CG+hcBXP6RF`hfcli^*R1J1^%Q-6*W%EnSO?o7>Ul( z<~)7aONT0@;NxDn40Phtw{K(l5G&Q?l=C!(?%o8>^O)eQq1PE`d!Y}FRttLOKx+xu^)dzf~x%B+Whr|#RH%}}TD36AG!j+f^N{&Oxu@aC9F+gm}` z_i5qIy(7Eh_`9a5Gvy|GGv_K&Ef8I;Oc*l; zt&D1ES}{+;44t6onSF`zDJyI9QT!*h%>m+Vuxzm`b5`?Fv|1-sCja&GnpY&4ze%Pz*VDZ>Xje0bU(7 zoIP)ud7*vrpKFxPz&FI~6=(Te%5K#8{j9gm((d`u!Js}@w9R~>uKU#~@ZT_Y;Pdh( zt-RQE*8%n;)Y5e!;Z(Pm+dgd3o4;B*4#wTiGr}9rV*{~7pX~^kGRg|os<@b$DXFc*H4))x&_kzO;i${v zFb58nma@vqRIHW3%L=+UQ)qPVh5~T=x<99@5uQYp5z2yo5$BcL2q{e#i18C+y$ju( zJ(9OjiM%`*9`3nK5iyrBC5YhrebPv!tiniA4tLy^bvQ6EIedUZh2o3&%{}vj^k$kg za}X~YDhtgYAX3!^`pDPrb(x~REXd#Gb363OeM9WI-sz<6aIZe_B~ZC8`}xHGp6xch z>w3Z|!fcokZT${08h8VD>13rDM$~9gTpyH7N=2}j4IAIe!tA9u@49UOu zztYI3;lL7P|nz!z>uP zy4R>19o-z!D$i=RJ2z|dR>Kc}5eu+^{8T_|-X)nh~poKfyrsH?ld`?ns7 zO;k`2!o;_v_2e?6cPor=D49u)&?WB!CK~QbG+yBy(m+II`nphgG5eZdI z@ogp8srh%mwG^GUxJLVH0A^jvD!g9x?@IhwCsMtpX-cD4| zc$wT-v#@(j0kbEpnKT?A!kX*kih26DxVTN79UnvYHu={x4Nmd|?qPc`sy-g9lg!SC zy-sg?R!%T?1E}%SvZ-<(M89@&!>-tM*(fLZgO4vz2)NmTD=%nx^Z%*W46hSEjQ4j>CnVE1`f|77Ovb=roHfCHf zB&gx}GpMJhcfR_Ui)t*Il4vz)#;zg}hX;qDZOgGaZAqw?1TB3iU7HAnR*pLO$5a|z z#^A9Iq)sO7Y&u0!a!b3(p?QM4n@7|Mz9V35&(W$;?7(+nVwhlb)?5PR;X6mIhW25#W!u&G)~~75RXDeiTc2A z`{r#Ge&sxxT>b94Wk=(mUa#3~z@pVakHG@-vJ9}X?&);DyE-FlX&uyC`HikAqr*m6 zA{Oxav^^L0Cw`Zjegwrsak2z!wG zA7?gt47m$G_WjzVjeHks=4m4jCo@+)r=6LG2|_~Yqr!-n(doQc{m*mbw#$|nCdi-B zDCU2sM2z@StlRB87To7_w`JcK0a)wnHhk9Hr(ka1yZEWTrTh|SaowCQ^MSxs=6fAI zywp=vY1Ry_i*Oy>C(r&{{5QLJFuUlLTk4JL>1$+O+W`J*&DJm#8xmy?)v(Coh>_^d zU{o$Gu3WZnAy8j^FTgwxG5%7+KbbFV2cg!IF0_R@#(S_Mz&V@(hTlK!#xHBF4 z7I739=})kH4vPhM;gSX+u4!wi!Kr>z6Q>xrF!x8khZUd;Vs5^Dorh%ky$vB*rJ|2! zd)u75=~^PloV2dPa_sp8PFz#LfD8-y&=ee7sPWhvjvgxEw{~ZQQri3@_|n@^oQX%B z{%`H^4@acDohZ3wsp9GuZ6tcq395;<@4<~SWXfR)Fb*KNdPUv7o}E1C;%W9%#4s0Y zu$&KBJ<}?S1uZ_6!GK1?D77eKkRes=OF2-0v~a~33r{FbcvQmm zmEzrY!K2L(=gAO9*Tv}a+?NIWHcL)&k=yP4>)K(oz@u>zL~7}EZ_^e&fy=$ zNP{PXDtSRpLEszgJ}!>eIAB*C=Sh@*!|&;|_3a=su|}L}deRr@s}KP4WFh~nS->Ir z$#;X{8lRarkLZ%W>$1|EHKunNjEY$mgGqi!cYH3^@CG|?yPfD`08S3zd6r%`mvff4 z=e$VOT%T)>x8wJn+k?jmfSK&?@1h7t{PlN5F9$>GB?L-JwLWKA`*j=6%JdjK(q-zcg`iB1l zOT|=ffd57?-Jz2q_n(}CymPGH9?NjN%Y;J{^9Gh0W4$BxhhE>ixrVDV&y96!o-2`+ z?!Y%d*PvI=`+B4L=4I>R&FBDU?lP3$@M@^O+kr1RMIwDDG+-{p2Wxz!tzhkj z7hTe^s#T57HLLk=ADZ3LmT2Kpk$|gAP|) zmvmFosVr!rrKvK?;)s+W);NAiGWK#ku`vpKiP9sw7E)az=W)FhA5*&T(q@oJ^g1c^ z^wQYa*!TZ_!*b^9Np3pKOv&OOOAVo4iy6`W&2jp2Lx^-j87W zzr63_Zq>wh<|45p$n0s?qWOo^@FQa4Sfu)B5*gd^IpNu5}7$e^6R04 zH1)6U;_q-{t|>HNL+{8rg~j&%lOW@wvkYBYQ#v!#y);VUhCKrIfT}jP-Tv_ukJKeJ zW-cMMEp$MKwuxjmu^E5Kyj`1I zb^|=t`*acsJAwnMd1t;rdUqR<44$S=4G7jur+z^kbIE$6#(Ze2zW2K=isbaG@d~(H z*GX>zusS^&f%+aA&2Fv$1LGn&MSLVGBRcq@%qFpL1iy~4$sKgCRN;-oacNX; zv$ZHLM9yaA#*blTqG6b9m@frXUl-eqK zdB20I;_Lw1ZLqUx0F z?Isc=k_1}^Q&}DXN&Cd$=7LG!&O0%sSQ-wO^UZkv1S&O8fX#{$a{4D(riQoUHxLl> zSH_bmg3b#emobUQcKIBg?D8k(t^V+K&E0$1T_o~0_Zt`P=G-77AtO511NL8b%t-mx z8JpIX40cuQ|9*;oijchZIo*0-Y29!>20Y3C*)1e|x*i`3ys8MSlfyX*`C^VqB{0>u zDIWXO_?mD+OwwIh?Nn>UgXIWYV;UycsaOIfX z=hWR?sbw+?&%iHaCcE^3C1-@tb_PF;VzV!WP1f1Zdjlj1TsKT6gtF52Q@w|ho z*vqT|gKC{IRA|ba5a%ze=Y%cN_4=gyO=S052YLpFDD3|4Sfna@M+|=qDDRz_$2yaS z{vpj2tBpFT+7k~&4dKS?5s{VU)O-K!f5$_F@4Ze;A-ppBEa`L;_NMT5RvZ(heF6;; zOJojeS#3+)-M3BwFBM|1pMuB>A7i^O0lJ~Cbwb<$u=?Q7<=&qNR%?!ah=%gHO5;qu zY@WX!VRp0tXVJ4o1Md64^Q9!zp|}m#XpV$1BhucsyNR zT@6kctUuJPH1jefm>jU*)pZB7MgdzUG@@ChNt2wjgClS^(PwPcas^pFz`Ol_ zzxh!<6Vh+en%C#4zzear!;N!)oBEcP@3jQs5}H+r`k!G-h6u-3B4aW8bsA_XFLcQ>P3RT2^sk@&!t zkYi#5YS*kIhcAGr*_;lI7?YZW?kO)MLfr;VG)a#Dwng81pHl>J^K827Q zCra@*MdXM=Vd5J>0iEJ(`OaO9B4QU+{hLEoFdLC8z%eJL0A zW2={CTlI`#kj9db5sgTiT3B0wyF-Kn?fm#w<{_CWr+K}Du{uIu^f~l>*R`mni|f$u>&)#X#ThKPRDm0rA2ehU=^;Iw4P)d26>=mFxh#nC?<_M1 zR7GF6$(&Z*`))f@fcWN!)w+}@AUY@=Am*vg2s)fExUXIy%J0>B==~|JXAYD5o&JovlTQH)#N* zgM{(f!;n;p_<1F#Gc6016M>4EE?fa0!OPN;Z#0$J0{6E#{Vlp8k{1&jvr9(5bO%l` z<7ZMRyPq+)dTzh`wBof$_44a?c_#7jHWp3ONIju(?%$+%{y&#b(G;Q!%TR{e}x}o-;^mAvnpZ|S8y3$z5r>pq~ z^bA5Kk3lctF&DK`1b~AWO9#*l{dfNS)OOlw6ZU_7=8PX2l)0v(7##D2 z0df&erieqJ9683{4SP5_Y>L81j2OEiWFFEhA@#f3ey=Z#%Xagl(X!#P8k1ql*e#Ay zbMxU}G`Dr?wLPS2!FGw0Fm?PP1`03o=~H%@V}l6mqS);!cRl6e#(S)`;oOTwxu z)EbE{zl|etO^!uZQnNAU`j&w}dDpvidWdP-a-76i&3rO7pggERn{DUEX+!eRHc z?=CLYE2o|vFvgh9zTcYl9cMmjN0%Ac01{3Oi(QQ{Dqfu&(P}C$wpO`m=jISNQ8wkN zyn`Ayc|a{fK>Ah0erFV}jpqCA$8|7wpc~%-M6q@eWZ#aC6AN+_dDMvK=#)VcINs;t zIBMS0DkA@&$MeA&cz8AQ0T$OC>qMWfW}Pq|VU{JQXxM){UUunXg=1Yox{w7C-+1xA z1bbwyO7Qr4>)5PaZ|nD>uQwSh=H^kU7D!Y+cRxe0EyQouy*>V}QJlAzX*)rTVVm!0_c9+%JI8AA;7_J+cOAB`Pmn?#tB zsgY5%`|bMU@)1$>6mZyUiT!bMJr%01x(54E`g@ldIaW{IV|naaNp(zMW&*1eTE%85 z*pFkShiASUzNb(-)V~X#0)0Fj*_(?%KIaQ{CjVJtf!)A>n>{`;oQT~6i$dt9kL~S0 zFX4%AW{&ycyzn$OCAE+O5y2;5JL(45b%g1Utm68_vrDe~0AzoA?>Ymx^xV?clhnwW zZGJgtik=}dSq$9H7p+-Pc3c%$IxerQ(tvuyjpOP*|1y6{B=_b$fjj5OMOTa#nCm1Rh!PA*{0^Wywe7Zjec8!5!kF(rt z;uX)ore&nSIOTOU3w=5B_Lx7j2jAQ0rH%riBzUW1(^_t(S<}OZz%v$o9$b{ENiNT_ z(mlJ+Xg89wod;gEEn63k-7-X;_!G#Ny8MN~lWgqF@nUaFQz|Md!Qxf{jTYqpJpKmkX9)~yk%s7Aasx!$7)39)UEafT=W-)i_xeAk@ zFUU_ z>$T{-W#NQGs094cGu(@MQX|-lB!yi7K`3y05p|fj7p3&zaaTLlpe#liVJdR;>VFHE;Y)y zj04TO0bdzQW&KeNm*@s2>S%guVmO_o-}%ERG--!_rx6i*=uO)#uA74Xj#5XC{mY~R zF%3`|OHq%Y)uZF5JJ_m=kpu;EqT_xaar?8J7WI;*l9CiPk1UVRO`6v4?!Grnhkh27(1?qwVd~SlDf|CI1}`~`ZqAP|Fo9C>6sBig<%g)QGWsMDW*Xn z1*UWV4y`YL@i~jn+@D~(jzHV_FN`Qyrliq!LNldY9VU4qpNxXQgl${`{9922ZMBS5 zvif#ri06%T(jBeW=TT@lV38->6LyR;m(`3&im&G)G|>&RmUqFJz>R0sh&+NXzu=fJ zn-&;!-(X1Rm+Kv&V=1Q+tmd61K|F`?~ z6vT?XWie9{!3wkyAkY$6%EKNe6Ek$RSTtwD#kz=)j33f#tT@7JHTCx;y@uZgBCgeg z9-U82ChWZz!;?K)3IB_r>yI@+1PmW|xO(5S9*wVK0<~Gob_WF)3yFW7#8F3#f{g{?;1i3(b+rjUM;(-v{!>I* zCPrZV-`Lr>!*Xti__Oml?91AjOZ^OH$VLAB27%0<@$tVmZ8rOQ!ItkR4K?evs*^nv zNRn@M50~;T?+#gX>`fzW;87&PBC)&6v(~tci@T!%EcJ-p^)LKw z`|a@sorohGLI@v4Bq@cbNoF=}@H(B*^_c`EyJ zFHao#!cBJf!s#7jgZhvOg++B#Cf2cXL@9-|7D;4)3+T5w!&9SK?VUVFcFQ^y8T##V zOVoF-nDK{&*WFFlvFBP6opXtCV(-NSeg+1Tl4F4HXeqo$B2>Unol^&ht1J>0oJ zRNMEdus4XsY$D}rO_bL_rVcxAk2m%(8VX2CAs>fP+)^hSUq@RhY-_2JR@^RLBemZd zqK;`Vp!AiAOhOY^D)nATAHAVh+yFc&&+9|NT{u18bXDncehf9;c_b5i&DxNhSq%It zRHdBfwM|?YBpd%BTDbbVppfM}4dl)lsi*ihA zXoh=05y^it46z#A-~2tQI_$N}$mboHl|tFj^2=!X)hL!Mx)%*?h_TusZh{FHAwcHe zWJoeda$)Wb(^OFftKp$Fc}Yp)veJHq$Eei7nr`@U_?ga>wV$@S_2po*2i1Q?ZIN^tW0BY0|rC2xB3T`?` zU!0fJp)46mJyk;=u%c%?p$9|FbgMM0sZ!|l_F(tL_9&$#wwe&=^*B*Nnl*&LM^X(@ z^R5mgFXgR@n9YjHC@n`y9{M4=H|DxdZP7ka+6*N(rHFz%5;#7(^L~9_`j=3Hi~&;&4+|I$NGij{@+i9&aEsT>UnroRhc-+fvn47) z5@vW*@H7W8n|jA0YUYiFS19gm0vuJ6EhY9Tm?v1N`ulgJ`ir#2yZne8@Y|cgIPAHu z@&y(z?e0xYuCA`v62w4;f|_$`immfJzvFHD{FxG-((mQBd7_x0F#lT-w!gLC*R6;B zf}H&PLw4-C<>rT`g0{pZ*u`{g{aIjIID(zv{dzQwLo+fJOCbTyQ!^tEsU{`LFk;*= z%Ci2nL>b@Y{?fe$1Uu8yq?mcv->UU&SKFHv)_Py_*Kb30LeaQFI)t^MecE8Jm;FlTh zCZIz$dR429-g%#9TjF=dMI?<3N!G5>qXk(+%>>V-TIrQyGN%bws5x&MW#dF4s2NA$ za}xK{jQnE6j|>`D0mFzci=oIM&1{&gcv-4dWC#$u!LY$kWbGo?%2@ERkTliY?TsQq zafi)!dIj9on7j-cd2T>=v+dZ&bFb=jf$T&fw0h1qQe9a}8=}{7{rKl}rKRiNRgJ>1 zuWHEQ_n+=V2|(*$W5TdaM40~zWZ^%7Q?`4+Qc!=nV#_}uSs0dzhpiSQfWjQC>tKJj zm#fxKps{mp$V5vcoiAt(X@n}wp11ozL{DyO;?XKwwr@snSm6k=5W*}3Skd_TxNsMP zU>4pgm5905NjrC=ZdT0>(0rvrug$W)V9Xyp(q#^&KSWrrFm&o*_V{pLsWqzR0N@zD_x{0$9@jC}fyo22@N`eu-hh?D#b?pk78R^q(27KM; z`3B`jN53!2IG!swxO}Cy{YOvU4iW>cXu=*4AIDIWKk9R^v$NelMfglQoAzR_`Yx)G_H63mBBF~dcRuJy5@6@$$#S5+BcR#YP+c{YGVqbKFR^@fcN*nYWX$K|LZkOIFQ*1da8elId@&*Rwk zQm3FvVu1zfL8nfc4l#8Djw86H`xJO)>K389XT818ZQNEB<>l$^YbsVFzG89Pj;-CD zoqn&+NK*DZWQk&TeH<@y8QHY7()qZ5On* z2|>E*e|ut<8{803;mw&auX>6{nSCEtX)md$!a$X&*ZHGQNMDy)nNfWe4tpZJ_fj!a zL_U|P2jL6u$F=M-Crd>O5Q;4*{?c)R9nWz7@KKXP`hK`dHnQ|(#x>U0aq%Vb?E-o( z>hbgZ2XDasBX{r8?pP6HZSiENb9z8_o^aeor-6bMT`jY5?g_hMKw2Gl7hzXn&<90X=Q zm##{CNo%mCVTR(MTzOy`8*W1D;*{g?^{8!dp{&t~8NxQ?!YWy@$=d#NvqykXlNkcl z5cm0dn;l+8&tV#0#Hfifuf6yrAfE%d>z~cumDn;0j%jY3Q-JcH*!)(|k&&5~o*S(C zufkA;_Owc(v$IpA7Kt~a_hiIRwuQ|Do*UqqKo$%J3<%KvT=dD~5o_FL?j` z7b+m^eDZI@|Mq;o&fxw~_0_F)!G9Z4lK6HIO#v*^+k>86ebXa&3|%jI?;>p0Yqhp{ zv`WFmNH96m&(io|Ev>WB&03Xc?5XqH+jx252^yJ}Oh62y1gcJ&d{sQWB%OwmthPv? zfq&17p}1=Fyo5%=s35pB+#Zh_Ucn`=vo`RS%E&(f5ScGOi5j<50>z{?UOWE7K>#;S; zZ0p9H#U5RAf?}(2qjmdPg9#5@>}!#8_l#eQ!slN10M3}Di}Cg1?O|&@3Pg@%f+(;(~X5{E$|JNt9V3ShnAMzMkN1PxSuef7$3iR zJ9B#7>bZ1qnn#ezl?k4B|7=RsSkNzve$AWo({+4OD_Mk@)HjzAPN zhl3=Ar^-lvy$As@?!xjknWPx|OpUeggvB*!tl`A*h0HM9E&9^b@ytF*al}P|hU=Oc z!MI#RyPJ)g9td#3rt%AVOc?5dWNc;-mKN!rlw(y=MWkjbZ&S=2*gK6fjkqA5v=Eu! z4U&n}mO8Jm#lvZhcJ<5lnv(FEI}$-3rgcuWkX`(|Oy|^q?;c|mJja;xQ9nWt=UHSL zGwnaz(jAzqVPmki5JAPLymA>~*ss-_@qhgS4?#)2oK!R#3M`l>t^kh-Pft@ED>y40 zFM}`p)~Do%e1H8NL>s?QLqD^xQokO$N7R1nV@}Kf(XP=)ot0wq^iB&#f{PyOCE|)L zR6A7otVwUkHFhP_WCLL%jK$31XLA!03wS(i8wjUUg4O6>Rk%N@!KdujVJ6 z61g6qQ5CywDk*?097D8SUA{iwE?_Yg1E-Be+eO<}%9mH#zF*%bvbFBl{ikTLMRidn zHI|!Dimx@UXwB&9!X@eQ(Wi!m&dthtbO>vSPXGjSQoDAJKiW z0X$5=!(4`vbsAsU1sM`pQx}q3kiYacXaI}PvDz1s4fJ}J1^lMAwiAOBIu09+=A3c~ zF!!%*Vyxuc!Km;KAu1I>yA#j>c|S~gcH6y_yDvC)>_N5}&`m(%npI3?M#(^4ynm9! z;M-+r08v?~#OH_K?sbfdBpUrZVq)D54U6`Ce2%L-1LNZpZiIyV^&5-Ut&xWp&r7b- zxkmn{P`=uqbkgw3nho#nq_WjTxYLj^8Q;lu{#YUqm(&r^I6wlGvZ?}4$R55h1x>{! zi^cO~)KpLDd>e>#e;crE_CAQPO#7)sCV$kn+x6T08O8joY3dWfP-xTslu4IM*_^HD za4LuAL~x^sNihi%q|P(zItBF#?}j(G+4ofQ>p9fB@cyg1~m=}Po4atWlW<( zK+9M4l+nV2Nv2QYf)fsmUaOE*MUf z9h6cmY_gwwIsERro<0eX`{27jo-Bns-c#_Od+0ge^5$q3LL<4t z&t|WndC0~qc7YQw4PC(H!@^tl+x=LWE%A`{3NSPBl+n}q>HiLk;*;OaCBrgMl?*(% zjd+LES;V{kbHClP#K^Aa{mW&>eb+x1nDIjUbNUCa<*;C^&GBO*WB)?}oUZ$`juxj4 z0i}PppJh$FF2i+<*N15MnwLqXQwhSiX{g3y{bnNE`8PV-w5yD|xJp>tXu2P>0kiJV z>s?J?lk@hYk+0)-=^{X7yYGT!*j|AP$IgC z5bK+(-5X8i6jX8g_ew=tpxu~c!3+< zR@zusO)fcVhuwq{Ye}(8<;9CrDdn*3L7_|t$hJ&7&e_fhB*3mq<>RS>R8jXB@Mr`m!uw%a_#Y(-*=z< z{b*S}ACl9xt%Z3`dY2KzzLRt*M3yjdMhl(2TxaZLfergMK+48f@s zjnB6EY$I2!X_4@uR`%v(oZ-Qa?H9$m%0#v7j4^XsFyhYa@?Tnu(t3+OzJrY2j|0RBU z{aLM|tSSnSWS$=$jO!V2Yud-J;FC3;v$BlTT*#=(GWobcU+}0w&C&ZDa^O(M`nipR zx7P00nyU3w*~h$%heUuhAngBW$f($}Xyef%cLD#=1X@?qJ`J!foW{7Sr3<`0q_uZc zMP6rR0-OC8CXG5g&sWU) zdOWgAAout77Z8W`MH+X$M&yhq8~?STN&dC-xuP&G%(9wrhV&&coy{7pKMv*NyzTty zt)kxc&4qDQaAf4}Yp;0kBReqy7^ z^Ef`KYJ&)S)ZH(D z!x({c#lV%ymWETxj`$lTH~Fp8#>0b$SfP^IT_Z;8C=&!`OLq_a&G9)L83?3(>S*}a z8_TikJ(LGC-oMz?sqeg*wqx&p2JBg{XQ3Os@o{14A-H(B1ei*5C|~^ez~ZAq@;?XU zWl>C{+zFmu;>jF;ZU#Oqt`H6Vws(&E{@hQZR)XQ1CxT4%u43;|aSZ*_lxEuRi0zc* z&m=#{>)P*@b&N%!{zG-e7gj*(+W&4Gx?n;`t4W|)L?`=APfJT)DbhHADPqwU+QXNw zvv+^iUK#VyxGnn_DxtMt{Wpmk&3xKd-6##kV{f(h{B`|(;?vx^qQ}eK+bcTeJCuvQ z_Y{BvtOT~+tUueoqC?fAt3~pwEW_|BzTV%?+q;n*vmSQFpW6ewUuPg(Ih8S*XQojX z7#prV?3^+>`_4n0n@{HVy#4;|bmQ?9LC5HIzIDxisVqbEZkQHu)yyrAK5k|t^5j4m zGp)L+Z4rNiugAIZxb2qJqNu1VwRRWr_;RH6(!PA*rZIDHhnfdCU zz;B^ry~)O726*RwUEEHj^m{y9s;Z*lNY~c>(Mzw(>5RcS

>lOW`%S5K!1XGGe25Y9>R0eeC==kk9P(g z*GLhS3Ux72CR$Q7D_B`q*c$ok5%CvNUk!P(%t(0+0rg^nP`Ju!>+z=C%#bi*b7l|n zkHK#Vg!_3a7;?$4iW{a+;9YuTgH*@-2RF`l^jt3SsewziegA?(Qx*iLxDJ zB>^tC8jcwRRO9#jWtf?`<3L~I^pbOmgFJE|Q0T3Tq33em+#GQ4BP&KG`08lsZ8S$c zJA%9`KpXbU^tUyS%(jc|ipQDLO-8!#+F3$ghYk@Tp$fBX!xj|w zHAbmco+-XCdMxx;9I7V$80j_?R}^;Z;Iy*1ILxIMUE<6u-1JR^)Jkw34j_x}HMxiw zo0#MPlG^Mu3g25@tvO&3cH}c~3S3$7+q1H?#1ehm`fmPvJl41(PndGny=l%xuMW*N zrWDVj5)Q;t)lUj1Eis`ss}UL=XKIVAj_S-qp7U$@XnAlj;$E;aU&I+69J5MISR6Bw z7?r8?mH-Q`tF7}sUviGxa+uBWwz*o5% z9lg{s)-%?%<?KHhm~!n@GwI)7tCR4ra(6Qg=bwJ=r|W!|vm-{k5(4H!W|)Tf?oT#|^O&vY`} zDu)>Wn^O~qdq}AoMJ=J4W^B~9pM4)C=?ha?1!?lou9rw%jVb)7^t^+6=aiDPbW{@* zx@+tNK-bTzj{qsj)8fWjV0Sf-FdH}LM;aLqTTXU6ZgHFsSKc$4Nh$KO@xP-wiwa}q zi#~wFWkg692tz%wzA(f67o7SH3G~r6`=r{GLJJhGmh$iY`0Q5-)Sg{R(S>g$zdwGH zqqAj{l#(_EtJflMn#&;X;lReerlx8U)1y=dqccwmLV4WFFMlHbpaF7nn37Ltp08DN z)&(Xa3$`sFcL8FRd!IG!*kl|`-Vw4mPNeo^NzIa*Zwf|PtjH*Mm(=P@$sg}u`$u%% z*3RE{^XmN_)`vg6g>&TR0dq6%C$jEK;q!p|j`p>6&+hBrBmXhjp{~b2rRx+d0uHK%M+IHgqd0WfBjUX7(Zyyn^vggT}a*j`NQA!+CO=^qM9do zJB%IhR~%zD`7^J%#fKrkn}f!u^T3O$iUL8O6S$3r z)ijz_K3F9C+8);za+cNB#<6x^cHg}Z3w$1W%Od7;$bKBRdVT!$j?(M;c;oxnM63T> zLE!44+wzPk;%{Ou$#D_*Y{p`m|70aUijQ#<9kpBYsN{WmAqspYqA6!~7n~FcH}gLy z>i(DauA4<&%FV`1{;StsRfX~WvM@j=Nbmff@Y1{0+lMXYw+Cn{0V>kn!s`5ZPT%H5 zg7BHdb!PjWf-uVaN5!J0I7Gcu);Ro?{z#RS|;)>{Om;rx4 zdRnQURVf~cekB;iiK>I%QSQHP9f}OMxbC4^Z=-CQ;Ga)|Ta1Sa0-N7V>J-%->(dE< z&hvso;FxENYDcGq7lyg6j6-nsgq;+4(ok0j#D6Uo-@e6{Io~}sQE@V*LR@pd zkyM6MB9JEzA&V=~{7s3(WE=RJT^*v=!Oh#@fNqTxM1>~R(;HjAr$gzK= z5E@Bon!%er!RC9{cQZSm_G-OaaOmLZmK{&Ak`rs^ZltX2Wb4V-H$FT2_&B}wVC-w> z`84qR(4K6bMUjQON!Y{C4e4L4b+Z7+o#V<;HfCD3J_UGYGYM?PmmF@5MH_UkLfyt@ zt%Y)GIW~Spu~J=`SDeLrrISFBzutn`tBWXVE>p_)@e!^lI9iH(tP}4~oPV+)-mw3l zm1b0NjZ>$fLIQwo1AtO%zUCe&hdb*HIU|}`f>NBb_N7afsw1}dZj|)Wq?7O4zr5Ja zMQNu4LR+1sjvuuYG$=|QVIfha->J>lQIx}!3B-e=br$A_z8PzoIcr6JJM_ZE#1?l) zvi_S1oJaOzB?ABLKE0l?IdvURI0XRV)`$34nYW(ZjPvylBAk7qJ=Ht`?-6>U)@%FY zdA5zmJN^`db@7ySL^vF^-{KfiJbBUmndQm-)t03@AAYk-CdBl2{TZH~C=$0GJkj`7 zsQ)XBKb2}+W(QO>+_q#3tWp`<0|Nwlh7w_goYm$OlIj*jCY?_A`7ogQ$tW9|Q`d1; z?EfTbB0NK_Db3BYB3zO)#m&+BwwJWRb8_BnYxt~b)xGkTwZNKsf74Ob=war^vH z<98)<`CgNfl(vqJrWR(bOz3PxsG0hXbkoKE(R3DUQFd+H9y$aa>LwK!I;6W}K)R%n zZV)Ny?x7nQKvJ3^1*AbzY3UY;p}X_Do^RXUzW~>)b*}S>J>J5{sbk6>usgn*;1GJ~ zQ5||?Me3c1&io&WYds4Z7)Fy>&CDI^vGqf7ljk@#PIPo2WcZqr8;7gSa4+HsC@OGo?VOy~M^r>c9QZ*Ba zQDWuEtEpO9&VDVgk?05&h$d1_!{r9o#RsN%Vd8->b@1pbH0TJFzyzKW24qypm>8eC z>)3m}wLL`M7ydT_jmyy!0Ga*utbA`PXE4Vd1CuAw{tEWuHBGnP{%UKgYk4ZsH-G%f zBF-vOYEngG1XL)D39q7X4Qc_wHc=JfTDX(W5bT~ad9XsB6G9f9>#V^|NquzgKtJi0Bwa)SQU}XAI&-8Jk z_c;!>Dhxui7^J5N!9m$?T@(`+)io#$R3t_9f_O;X`unsz=9b9T6t zE$yNPmoaju1lL(C3ea02R7d>L^Pk-aWrHzOI`LD#VX8*^NsO1;mOQT;t+jfO_otmE zTfQ?K^-ON=yt{O+7^->PV|ob$oocJk3t=U_>zOc|y`RvcZ201bXpCUYRv7WuutG0@ z7%#L`UDslZUyYf@2-1-6{ER6Z@td|44}}CawSnfqc(#M z(z;{rQj1=@ff#g?p0>cymEHi!!yF~%Me5IlIm-mgPue%{sg<&A480!9es56Z(AZ`! zb~U;^vh5T$={-*^fIq?&#u~%?&s#`s-b^p7+<{yhQ8D0CBo#~+dNqgZHrA%EBQYE- zgohQU{Uhf!9gMXMMU;^qY&lq0feWEGvmk*lw30~eS1=Yn<*(TZkVo^BR`@i)kqbKy zs2*8w%)}^IEMYx9gg72Bo1wA9S-tCnrGT5AWwUv&T<*nx|59L9tF%@`5W*Am0({1j zxLh#`Lc(G;HzBf{cJH&l@BOZiR@%JA#q*y3Eu14me;40hy{)MZ0NQ4KcDFW4k=sp9 zORl@cUl7h!)V}Mtq_4!0ymN=DIvyU|BMYfa>PPb(?#NjL{Cr&e`9kjA(-bIbuvHsZ z6-X=R#b{k8?ybTAe$`z*%?5Fv0Bz+`aAkz`QoSznBRq4Lg9h zESb3Ps|tQ-?wswq?&MS-{k(Slbp1xu|MU65!PL08sMp!%ZA3qUmvn~q+eLm}<~iPk zHqm_N((VVJt#rWIB{w%4H*{&1iE+O$L3cTUdGKvKG z;mXR~hS6+WTS3)pDw=NF=cj__{jLYaNiNMx3E7_}&2t}{+Q*Mt_dk8PrF3p-i2=+2 zK|xMV{JQ+0O}RIGh(=3okJWdvWrPeRv_vcgveqNn{X*K=%0&lr zge%F-3uAKAsUlU5$Td{)G<5hVWGn+}Cx6E*z*q0~{=9Bpo3;0f3VWh{T&I4L%)4tq z=K9&#_%ixXYnuJ>?L}9_7_!J{Ps#W#%#R_x&F3v$SjOEq@8Cfp$IUUQu+#9n6I)T>`&lxPm<EnP?tR9M`+%t8S-k`V$@f{n`e`fwJS ziM&Y^_o2D?NDCWwwX~EQ^vLzohFEG7$HVYIJ{hAUDvu|V?>g^KysnQHn4|@qRyW<6 zf3)&EZ&0W9yvNGhQM;6Z$u+>VHlX}0IOAg~c4g3Xd+hYS31)xZ^B%5uMn*=J4k&yy z={!}4wEx{|TL}4(e%^6lx$%CyrHU+0_v^5js13!-!Ruvr^_n@yW>Mr=9%WqQ%BLuJ zGIKgRwoM_Xop;DX?uhIzcf>Du(MLT6FBVj=X+q_qVMF1g?fP%u9qR5cI#&B!ypuFB zGRlVUJ&mY8PdAK<2i#1YZIt*yw@iZz8XDU8eMlCI_XjQ`rNwbJ3Fc%V7k=45a=@P(%!&(kf}7ey%!8 z^~6&N`h&(529-s(c#mQc8lC_3D;6K1ZV)6zbFiCpCK>+8I|yaWVuoYmaAY>cMJIhE ze87N3q917Rmorbfqj0fUup89wgIVY-9Qd=-s?~Y1B2_;ANAL?h1P?o%ByGejMOho` zHxH|udyZ{&RWUh=!%)3R+WZYdhQj>^60{Z~lnkXWJBx zA{$QEakv@r)4Uw@Y|C(Ek2W5VH{0O(hUzXvR@NuxE)B^9aLa><)TEX;1VA7oAVV=O zBeW%%d|^72Li9hK_lmf;WCc@ph^lG?!kN9MN(9N-anOA!xB|ezOHCvm&VK%J*nWs^ znL4!DzgYg2K0^Zb-G(FaY8Q?+;p4PMA2KBc1?Ps&BiwDDx4VKEtrYJ}TI;wXJ7rEbMl%^YcMi=f}g@FtyJnLEytF*P9wdbq-u~bg0eiP}uh( zeF45O_(~!gG~RXc(6)NZo10Tng+Kti8(~wvn8=Dvxt=0TrBmEOOptjBZN2sR_5$4A z8YCBc`Y)CfbHeZ&>u|=nsNdDMuLLS4KO&)H()?&z^o7J=lmQ~$jZI zg_h;p5tZ{CzpwBwroKn~&0RJnI(@p6)Z3MnFFbVeya5p6qSl9Yb(HF^(?vLZSJQwu zd3gB;6$PvQa$Ugv^u>3tqnl_Vua$r~Ilt?t-np(OUESVO@2QMYhy$ypYDKput?Gxb zH8NX01t9RY_Vmn;wKZ5gBpf%y@4YyQChxggA&g9v+L9hZ^F_Z7#@v{;rO(G@%i7x1 zDIq@fernP#JRw=z0v*kwo{VT9BnfX+MHXAG$mi%Gbo`9{e5?fwp=IK33k@NNMIle6 zg8)_t8SMDNa_EqD{BKVGb!X#TYaa=Uc&bT&4Pm>~

lv3}YR^Q{ZytC1dP@(V|Mn z1fj{QP1av<&LMGrl|hhW<8+1RaViEy1p?$@qGRput1T7P1USK&!VYB>xFA`ELtQLv zi#R-q;go?;kmk(1If;X8_QA^gfF7EPn4S9emkc7hT(Y_tUJV#L`>AYtzt|kWjX@5Dw-OMKn(4 zS2&JU#4R37NCkr@f@vaoD&#e!!Zc{5O^8bbfc>(qP4ACC`5D4P6lU1n1uuP8A>Z-J z;QaHpgbp0_g>x)(QM(Nk+Gq0aRdg6y^io)WXhj>7GSg!rWd@Do{^q472j$oH7$E2U zVhy)8@M_JzQ) zGe);U&R63lG`BnTTB!CZz ziT1v@y1!7@>}eZOiP~7V6Z*(+*g2%b7hWN`tik&hFb1U`*~;?&3l~G@18M8%(5ei2 z)lX-_xeH5fDntnLvEC`fB>k+7Y4_fpP<|zGaHZ6g6tSr^WJuao|#r~BIt zz|emf!~BtOAD-_LAQEvk~n7EV;t!s|ci3I^4N&VPu455DSK%Fpg;bK0I=e z6s;QJksLnkeK311VZ#?Y&BCnDzQ)MUaIoiy2Q*1i9CRK0(MxD= zck(=MTf1JByq%IXFg5{F7=X}#9uSYq>M+zdYUA$Hp{of7^EOT{@Y?EFA8&nmBjN8Y zM6oG{yNMc;p_1=`$7S%cJ_Hz0qkyy+MTU`$z%`a^w7~q1-_=+fnRdkldkoNPZLTfL z0M*7L9Q|xryFS0>d+uoBdwcTx&shl~dmGu1S9!_$$iba@JQ41i_UR zHtMNN`cTy~2xSd^E8;->*!TJR&0SB6yF2w=%Qed+AXDZ_cAYc{c3r`3a|5<^>gJX` z&jA|vJwWblZ*6_*^y(1Tc6-+AJgr$f%>a7kfJvK)J)`TYvWtr>&9oDU4__a4eS9tk zG(<99Q?C_|SY(uO@_cr`rsZjs^YO9lP0+u!hvmDwom|f4>jBZ@<*w&{ zz<%TTPx6=2l2-UIL&dc|@lF7vri_7l+C2I7{=DF4}r@E6;NEEZ-oICEJRl>dB) zStP{)E$4P*h?KhxZ%M9UDx0xFnchkph0c{*w}H1|xJD{QOjdS+#_r(jbU`u__i6%Y z8Scvz)Sc4>!tvhb=H?UB9)|rrOr6(rc_tl)KzZlOhiSjn`&D;aHU5}^KmX2#IlE34 zML&HNb@lY|m`VE7aVQW4$V6e`O5eHypOBI_)ro;S;vC}(ycCovS!~MW31O^4Snt$1 zf-Wf&59d7|(OyZS#__Emvk+vWQV@k^au=%nCe@97BP`s{v~5Q(M-mNF39raEH*~NW|RDpip-(6RnA; zj@**BeNRMB7!Iy<5W84unziPCgR&()2$pS_jJcHWCG8%=DRFEz0&WNh}YUhRE*@3k@uL(?%B1_F(NY? z@W6btigwhN8k(OEa_Gj3>LK4Fuj}g!Gm0i}3zQSsOI-OseOzSSm^7Qu%i2S5aK6H# z165S)0rVJQ-v{7;9W9iOw8B1^FC<4ROqL_U5uo_ukhB$12Hc*^;N4NLuD9d$#l`1Q zCKCQ<)4QwF(?&^+B?P8>}N>PH7OWb+u(z{1g?jAccR|An>-@T+ZHZmA?TRZ$*({(FP;IqA3$^hMr z{xVJ0uU&+iS-{<9^;TDtKDU0N%+eU)`>+pX5^Wc)S!` zesBx?F?Cptct!BpCC~#96&U34@#iSwFvo-;Kx?v}7r>qk7<6i07ODQd)!!dQ?QJ%` z?`i6DOY*$;)=Tnih>qMcI>FsEqgX+~`(V9HeO1^^rz+Wn?~SsthX}&xQzvknl?Qfp z{qW9R@K`j?vn{blTkdbx>`Hz4Ep zVRdCmma*J3<(MUfBMHCOTsBk%mp}JPN}i27XvCwM1{1)bT-rJ|sQeI^G+1bu=lC@@ z6E=wma)Qyrwl}S(vGlk5cu#%U%p~d8fOw(8( z6f|xd0mXgy6P0|8cqJLk+`b7e4Zd<&DXy|)9$XKpLVYZoF&Py!mwp{q`%TZaA!pFvS;tooN5@Y+H4p!=D9ImhPD$U~9C-yD zr&605ynX`O74CwbUOfj^=zVB;PT^ejTRVQ-uKAR9*#Y!RF$FztED5M44sL|0OI+nP zccFj+FT$uFW}mMdznHc^_E3L#x;DLCJbu{bB=2rB5x)w0xK}r+b00R-e-%ZU_fYH= z4|-a9zBYC443tFq;IrGQeC2d+DtR$R&^@J2{m{qx{Iju5kdr-E((@rb=ziUcWBLRc zboxc|e5|?aF##>_Hw9|DOxAPQ?i_02Mtw&L55paRi}?0SkHx|+CtGp}!)wc6+y z_(Vkj=E~v@&MY8D#rdHGp(R02#|d{OVRiYGyEo#_IBSKV!#0r8Xfmvw{PYfmSI)Bx zm*CsW-b;SeY&hI!Yu=TYE;4RqnDcd(s4F1>S;6F~-qA`Ba=+SdF#G7^RSAlF+-Z4O zA~$l>)ArL*mF`B|Yuk4BC2MA|PU_bNycv1wBs>Ak{O*yI3M?xv+46LcwX0DhTLFB5 zSqGNaLSsB3Rz-}pFH#8`tqN+j$H|zPQMh<^`e@OUZd%L+u!F<7k zSd^I$UEd#~4%sO65h-gBUvccFf;8oLXw2~$-!N;M?6v-WEtsVmm0Hms4VP89rLn=Z zNev*z77o=wBlLb{SMa8?92Q)z2tA1``)}AyOqBOUZ-K3qJpT(Fi~|&$;usA+ZF4F# z)}($g-!zymACh&Rxvip8g^_yS3Bpt+pRVKi-mV$U3{o(54=Z1aD+(lb^@%M)qm@sL zjQ9K^t@q_W0jH$`8)0i7P1wA**r%IFias*&lo+skk!E;B0&SCFyHL=qk0ih7Xo7a* zjKj6yoy2&r-A7swEvjOYYmkBhw{E=W3rKZMO?l-DoKm%1Z33I$G3>(+wRmAYWh)M} zQbo+aQ;Hn;7>d%O^08UUY`ESWFL|B5_F6vOs_}1}bm+XdT?^PbQKqD%1iXhH6jq)# zcNe=;ra!J%o4YoEg3`ke2F5;z`=&uVzz=@0!x8Xx-F0E6s;#zf@i%uqdDNI18+4ow zP(J^?el}amaLT)xQ5U-#dL`*Kj`ZX+Oq-taM!~}c_C&k{vEk{B>E-3SuL4iPfbx~f zq6YxYB~I}&=*g0LG=^Q)#MngKZBs$l+eST@1}tX*rnf2~o6?>I;qkGiDvcOd(_k}J zjJDI7P4;1{PD(}FSqin<4O(MWciy$V@_)BC0Y4&;Hi*}o(=CcDHyMNu6ir%xF_CDq z-(DSGyI(YN4tO39FgqH7bNZXxTU(Ql){oTGBvOmsY!O^(U)g}5n#Z)|+r)bH=&Ir9F4(CJ%rztj0&>vrh4*#b`R z)q4D%u^eF!-@vCo$~E3A`=;0N&H;nnnFcz0t*gL(MhB}pOO$tRx9Q853@@jZK)_@{ z<$nclUVUuxdcGKcBjoZo0-0xEY~1$Hoz5`~l%~IhZ1nt{c)`gRQ#jT@(T8WeU2nqy z0xXQ3_tkCZVwDxFigYR;Z}5U^gA5Yn_Be&~(F+%jvV4m;?#mt+nH;?L?4ng?!)hpnJh7md786F~C#bePPfycm%=V=@d-iK4#+g+#m7cq)1H^ zMDkUcnqH~?aw)g5k&;egR#CvjtSHI+{v)%>Fb18-_(fJ3YJR!!pvvY@LuvdaNp!2v zIUZ5k78!`6WwWsHGTt3IZrtvNEFd)%bK7*G_;1$w2AK9Q-XD7pyYQJ9E$M$a{Niz# zvoufkX^HO;MA3-?;-r@BXm547If(_1`vAVG#E!GQ2g9|N68IZQ&$F1XMp7Q<2XQEI zO4(WPEXl5V=ea9t@vCV&K100~{r4IVrOuL{XKMWOIh0*=m2e;g)A z@)5bAJK$&(E7*{d=?Iy3(S{iQsi%?ooo$)9N&P#51&=;U#^QyV)J5c2vipLac44tL z3NJ{Lwot9%R{il_t$yig3a}v z0{r5Qtizh=-DmA~jZ1K3;|xQ?$Ne#5TjV&~qIW3TUNsFsX(FO z5&amv=PDo$Lt;K9Lux2*oDK~tw`MYHpN8J3T9M{-ERr;z3)zts4Yg|j+ovE!%pikq z1y&3-cT4im-!;b6){uqRNNG(G2M&!uxN(N3@vyBdj`z^XS9I?Zx8<7L@2h!j$FaLdN`Q5d+v)c10{eKg(~>-tu!v4j z+L-Au#qcf&7#dOk9yYH@P$U4c70ccV^gbt1PXVLRqIZc2k-e5oCf3L3e>{`L8{jka z=wO-UoooD%q%66HNrzbvviL~MN3~MN61%1!JQV2+M3=trSFLf13QOjUJw^{^-#YB^ z>gjC(#)Is&i|rO(_br!)1K#m)GXHI?{r%>ZtE@zzHWHw3Uq(qjOkTYfU48Dn&XEYX z>nAm>+RN&Y~|n17gqzQlW1 zL;x8elPe^j*3@pS0+y`@*m4%+vc_|S(lW;Viz*Bi?r=-N>UT??2diSD9kt$_GkfBf z2Mvkhryq+ZV+dzGFG=TS-}v4X*yaUw4lOSZh=e*eQRwJU|9FV8DY_kT9}oWDmf;nO zwL!-FpQjWyK2LqA>cEu{+t=S8!9FZ`wx0N~93^>h^nBKGe%{c)t7jZA^Q6ov5wNYo z%*Ge4FGwM$qw7AXo={PD?xO~WMe=+;_bi(9zWVF#lk8=*GSlC9`}8m{!dl2JDpw(E z=4nU9T5h43`~CoCC?l3k&PS;_*xgqMv8eb@20@qv^B+^;?jw^an$k_4G;_JTAZN_u zcT1-L8XYJ3lfaB=tQQ6)3cJg+p1akj!Cbp(3sd31*;kUG-E7}!?J)FGTM-OGWv2Z$ zVUp@!DwGzL%gKq%|D9wJro>7vVTlj1=M&ClJR^WumA^;}iEt zO%h^_@F|V(9M_N3B@%YmYHosOd;}@9K|n@TSUxk))Sj<3QS8jFbcKbEO7v5+u zi;iJFu9vY>f=ZEN53zrEN4ffFdH>L-zZ&VD9sz&gc~kga6;B!p!9Z7yBvx5zDQBcb z3x?d;G!PW^kpU)S3_R?&P^354p6%-4O5;87OOZNWGq~F7zRnrGJk_TX+fN7-_24bsOn|PfyI!0{SrmY zJ>%A^{k$~r=s%xWngT0zDgdv^Q=DY7ir|FW7}#OCyX?7ta&{qQRk*xo+hg( zBZC@3&((t(7LB@Cu(Ev>*4xNgayaPO+~ef6G&=REEx`2$85NX^9GZeB!%Tv!pi`l> z8Q}ySB7e?A_zSidE^G6it)j|jq zsTAE==S87|mo_C?m>rs|)!I3nh)cR@i5edp%Q)M5f%3PMXj)Hy)a?s9!eUtB6 zJL#fG;{l)I(L)NShh*`GLgRCaBWc9prOhJsT@deIV31>hs%5R z(~P(B>l`=fF)~uF%sS*=Pb@%`yeAY1r<_Rp^YiYW%v!AbXB}0gB!~Yk{oIc5 zY+;EySONO&-!FY8o@wV2e)F=evF^L%LE<|cP?4>s$oPw^myNRn*yk=n)2`nzRMNnf z#B#kK^EFVC&Oa)@z|KIAg+vp9VMX8AWB>BY7Qwourl}mO5mlQ8O`mLxi7tOGFJEkK zj@-e8RFPxs#yLhXVhXu$1zLc(+Ej$DkqoQ##&N>VRb+t{E0D_lf*l8}-M`pRWi~c6 zb>y#azbGz$t-=>wL)8%|!(YWOGa=hTOH?s1W9UO}nJ6pY8>2f`f1TH7B z%jwQf&B&at{pz+j0ie41vsQG+jbly6dcu;kq{rFxHTBce#dI1dquBatU$8pQpt;i! zF=pDTkI+8qxbM82+Hd}}Cs+?#&h0%) z0F@J)7gRg7tM|t$)0ULOILGt@5QdN0u*$^$>5t2fYabX`AfX!@e>IDgOOP@E@FhZ~ zB9+8-*JB2jD%grI8`|@%tu=L1zGcvx%(wnAK>F`?&=98Dp{T|f;BvHI`&GB|uzk>? zTwAWnz5UsYjnZyun+L?9fum*Hz+^rYLBM1!Y-JmLk=z>v%oXW%BSGiQL0_y5Is{4x z@QUP6f*l%LTU!_H_*fN1g!wyuwCBgIc09(sd*gGn{;spMaqoLuhY2UdDUST&en5j* z&OrBDx>7DaKMNwB(REBsU{3P(Ch@GjYPLeoB-~1kn4zF-8fBk3rU>0YsVP_?A9aRL ziX+JyO7ptFsu5f0SgM_r_I35^7{r{R-<#r+!99E#Y&b}_famb6i5!eVVh=?(gKRBC zS%pAeue#HjB?o)xvK6NX_P<7zPC_9z)1uF1nXizdEwt8!^@SGA?N|%GiDPc5u~I>G zN}Eu)sT`sS^~wlN<3{Bnvyo?U;=|_gcI_!thS8pfpvEz)z)Z+7LoLZPU{^pZPYkTwijJGj6o4*?7OgeTQ*ZdD=jXt%xjbG|IWH*`48JV!hssRN(qFzr2 zByH7Xl*%1ms|Ez=U*swqwJQ1l_~QRU|MlDN6qLJSwxc_H<{9L&_w!fYk)&1zt{7V} ztr$%~F|n|=AVEI3o(NS7wrYf+lQMG+hAN>&^|Ql}C*oZ9`B^aRSXm7Sq2U*X{AOv5 zN&;`eZ)avu^cNR<$!{Ro5X|&&GJ&{dJZUAiVL}39{jC@~t#E&GJUXee^cX;qb)ai9 z*u@GMJ2zQ%5Fm;CA?9YVZL6NU4Dai>s@MAa_0UrnzxCYR))Ht+WV6m7qFvIGQr719 zAk+Xi4w^Xq7%OIEU`S}Hk31_(b;uO=a&y?&ZtPF5$|H|kYG_DSvyA&NCqkAMF~i8Z zbclM+tTz8;CEePZm3M0Ye5SKhtU|kC8D()Mowv9_`o-tYZ}WCUBx9^su=S}7`Nj-u zSrlE(GzIOQ4|0qOmNU^MMh3sm0ZVa3^py9+9yT`F7I~Jv6QXf36HaAA?p>xwx$(H#!rua7YQkY`{#j0mfWYdcm`+nE`LZ}JXJO~H->cNA{lNhy z_~O39<*(>ncs%7;ULH`azwEM7Eo$lqXzg2)-~WI78^bbS_^`&%$PqBN*MGsk_whX3 zj{i2q>~8MqIdM$HQta~BYVS#eUZpK0`#L31?k@_2KwT<)r{_ho`=^ZoRYylh(rskw z_fLg8%kYLl0cz3=wbJ`;ED3KQ!h$ufNQ?#$PyQIKon`o$KHoiG**-rSOFkd{DlacC zj`-iR<>Buv*7KJ8zTl_3p`eGMo-aUQdKk6-`1Ok4xZ^Rv4VVGCa^@~tI|9ZJmYRHG zbt{--8jxzoD}LwB4}*#R`;==xP6x89mjkxoQ>8$VWMQuB=*aZ0-_-kdM^i7YdBrWZ z@ueSm-K+NVLymDZYE2|!bCmg+xMm!!~3V+L}Ix&(Ws$6zZ@P>=#P(yYDYBV znsYISyk-H){F?Jb1^w&;CCbZ$D){y;3)yXKvg8b^*f|~fX5>d-r0Ei-a-o2x9r=sm zYrlOK_M!ezxUQ3UARc!&q5&eV1rvk^YDqc1kk%%FLbrurEN{S2Vr&}U@$j-nLi4^I zw`EOY78DDx9Pyt^h)mf#QbN2ie$2Kw>V+aO^!pzZC<-?&Q3|uUjTym22p38S1O>L) z|6Zzv4pwWaE>kuU3y@6ZV6*9TvYf$_tO@_jO~@es)s5|Q0UfaC5`?%h=eaa}JUD5r z2)TI1g#7O@X(R;yVSwVYhGaGP;0v_z!R^f52O&R`l@CJt>1ZLo8Q>ytx5k}-VQYOb z7XeN=`?wa5E8(lC-j-PRjrcl!rV)z;n|>O~JKy3@u@*-U0IhGu-JSG4Y#o5EA1o|1 zl#W$rXQ2j1#D2l-efnde{9xEMml#KmxB1W#``6mO&V762;53zK&F+{XSQ$Bfy|hvs z(fDx)#6yOs99+*_dFk!>DPcj5^^=!KB^>zHkbWzx(Hpj}I{a@g;JoisDfQfiygUV> z*;YI!$J>-bY)|nFa^JBM{HMYGkKh*;UXBp1tr_h010yMR)Kr|zQM$B({9TB`jfG1Z z7AjsQrsFWd=QrVU#2P;y^{?pvc3dBb*LqnuY8g1)*0cK)qtv2XQPMcpvTLSg)mJgj zUaDWddUG)6n2*zrh3w(B!FyE8x6z_253vCWY{D_jN-8VX~%ADn&b+@Tp2fiYq2tTi~H(5d77PqVKZ~ z9=n_49a}oow=-D29b?O}ocB7Y(`Jz z!A3{J>vyaeFT_Wdt4a>vn&ghVn5FpxBb`->IAmfW>ZBpofF59cp1)%OacOQUzYBge z8E^aBhc?QC+HR(R&BI$CO~PslR{;@A8SeUO$XNm!zX0FjMHCtq!=gEW!xLDjVG)#{~rBV&tgvHfHSSPxO^ zlU$lQx_5_2xt#3FXXDm>uUA-Y!!0=ajUq2N(9zo7+W#@`QUjry@XQzO-sx&aqrHqmsrwGcFn$me`52{P-9)S4;Ludc$u9HAE0Uc}bpl z0z!-*Rl3D*TMw@UyB-n!x5aCZ^MlxZ47Y4M|gp!2GhVkM$cr)Z>PG&_7jcy0gkTKtk&)NAgmm%gKHjBQ_tlssP4JE=Yw zjcZ*a$EbwYUkxP1g#}l4UrjDXL_}}~+zvag9O2J>@H^z6`>5X)=o%;;F5PDr@b98L z`%`Dj0#%U18o&l@yWR)L(g}x4$1TW9B{^$z01=z_rRj6Eu*rho5+VxdaNjX{6>y{X zgw|l2@sv-k$C~cod-7NMcqIcMkz8Hf>t*NxBE#`(VK*y#b5~c_r@hLngZV~xi}P(# z6Ys!hWzNRA*$H=dhr+4d53PJPU`s>}C)_y0$ja+xC|cCH!{`3WiOsRH_$|OOjA0gN zVvm3&sqUWn3YGkKE3b*;`fd}C$Oalnb&q88mrTzGy+qmVD2i898IlPQY zpCQa50t;qCAj92Sg(I(4pWOYEDCT$zjm_agJKH&vI%Mv>$ulRg`0rge^RMR?7JfN~ zs0Q-DQ+>X$QS({G^-ks9vSCK+Q(BQNr48uY%g#GvT2Sr9_De6-IL z3?nT518L)iI_7BZob?={wAZ3YBS0GK3Lp@efO?k3+!E3Fvs+qTTZuPTtMA}luoV=Q z5S2iK)|pdEsXTd%dT7f$Rff3AHuT1Os+h-&SuONuZ6ob6q16WVlMzA!~z7mvp|qAQ5Yi7`!g4# zoyNi-<1vsLJ;i}gA_s_Fl}2dd68QG^@Jjj|!2|9+kCvN`;kJPn8%&sCt9{ecL3i`V z42(QkCceAHlF#SQ02}Spq2n&``OK_&DtDRdv7a;Glx^*1&qb(gU}o)cMe>7FGlk{M zap1A&pn9&5_sK~l{=UT1sbsYvBXsjVQS4!ZDbEhkR9eFHoVRwXPt{K;pce4tp69o- zzb52%Fmd&EN%AatjW2mpacgPqaqMjIUx6%>)UV^mCu&c>6{W_r#OI3zWNyHEcL*s{ zNePu70Vg|%>R&jqmSoYaEOs6q_Ra)|%2Q%UXwMdmj!H&i28ld|*`vR3EmAiGfr$$m zP`{-^kV-Z+VB)$-`hyTSSRt7+Geq2vkQha)DEKI(mlNnSy&OID{dM(k`PRfy74tO= zf5L7DTty=*s}-dL zg#S-HScV)O()~UQ(vF@g9MO3R6-h`jY;5}RWBTxt zYNNFr&O`lQF$Qq$=hqsT*z}qcQ#$rsiCXtON=qJoZ}1$9o--_>!SQun_g!);{6cyT zVG2oaux)5BLW&%LF|#oppkU>I4;&d*}=dCbuXT=%^g5KKrlvwW|7 zatB=xIsm)Otn1IX9+Xmjavsf;wAGdoT<%($KeaQLCKvh$-Y&DG`L-t)A*z=a<^KUU zgHHy2I#;x1_F;?LJK+)jay{MHaK6Gfw0#2?+{c%q!?9nQKF)hzjkFLksWB(n6wMkM ziG2Rs{qNsdZl#xLog;GH@|~vn$3h_Im{l|P^Qm|f+JoU{sd%WRFebB#Xrq!zk=eDgTz4Y0DXTLRSYRV!s$Pn_gWITU-^ zOuaYtmS)+z5Xn#D9x&2lXMbKY&Zbf?h`UZU_StRr&-^s!YD3DmiI>3r6pb9o)QqtSbzVI0IVCH+k4rK(VQT#=tug4ZA`S7BvKG^rqCwux@zsC7G4vu z;>gH2K<)Ps?b&wt!3Swv)A>Iy!8&gq3wv5|*H!EO>UpkLz;3LmFyIVmFrXGj2}Y4_ zpBoSwE|Qg&`OgR--w4KGM_}7(w3GGwsY7S@Fiv~Lcn#srNqwNoUyT<@VwTs(VrcCcK{=4n?<9rO_G!8>&f ze67^?rfU<<6L+9r( z$%jMJ+mm;u5^g)Bfx96NjZgbsk48X2!Q-QIfIAh_c*n`d;uP<1%sjOGGM^VFz__3Q zA=RJ#Xao@ieaf&w!ua`&p0(eoG=z3JU&83P>fN#J=xxOzk*p#zgq*7lHmZfv%vzY} z9k%p;lvqIW^pJ50RkqV4^{-#M)(7UQjJn)47Lj{Q2~Rtk%&&=20p1{u)?W;4D&HXz z?QD&_AEz;gdTN<9;um3qffqOT)HfRNS8x0-l8cLHlo+bDSxGsK4ULR$8x#FE-#;Il z(p7FSsgI6~kQEsocEY~dTQ1GM#xn6;FrcA#;$w07IR8@emh}1JbnS6#^>=?>z(z;& z+UF_YO;4ZRs#dzOr{DF_{}^k{bpJnl#2z#_fI$u1ADfi#b%2wm>Cm?%i!RMa`x|)Z z(NjT*B7EunP|$DDL&sI6aCj22KbYqcT@B=lqp%i-u1J9Fd&3ZB;WPQQQ2=iIO^Ze* zxn^4awTZo)Qbf5Dt;osW`IJhRa0S%-_yNuO1T;koIcP!3q=W%U({zkx>UFU$JziZ5 zE>Cf)Z%2jB@?MkN!Sv?z!%wPUq2seaKM#)?C{Aq*w~`7*a#iETMr!;WRDyZWa>Liv zpnV)GAp07hy!f+88m{GkFO5G$rd1PC;gXjOL^0^C0P8-f@T(8Genz_4 z(Uww$lk~8BeqT(2(*wHV$gfxM_oW#b8IF-JU(ZW6e3GYY_uu(Dz4>E)eR*LadRsrk zmUP_ohxfWnA>RwAJm*^u|8@7g*f@y>r~7hu+wZgP4W!Fl@1Z|$0BMs!b10bt)vbGE zy_uQj?*dvdspcXvMxL0fjp;cYnDc!QQzjn_#e8pI?oYqP{S+z(sh>~({XWz0AOMd& zO6z7=cS(+%heGG?fiNbpJh}u*61|^(Mku9JRaH;#Uy4!IUpF)$XJ=>I&u!K6R=65W z1~pmYMyzw^*vhL3V}G=Rf6~W*3%=_TSrA)WC%_c594ybasnbr`qe?qDiv%=Idd^vgw;WA3GG_jdNi*47lr$9?de|mr8dQaFpbaB@B7-F-E zN^AT01c#ZJMjze(-mY=HC`E5zw{(TJnmB%3Y&ZAtAP4ouN^cRw@vOcGwjg#5^!IhM z_9!;fqx%b>K-d*i7S06| z`}+Lw{SVH~ah`F1-XGUh_L$Cr&qCaPGAUS-!VT8p%GkPZm$4~F zK$Iu2@$w@J2@W0>A+3+KH47!4!&p`0Gg46!V?}P8v3L@;FP=Iv!>O@Gmv{f>oTda@ zUnJB%{cS^BOM`=lr)WzoK!_dhh$m;wM*8#vh(J;hi#cOd-2Q3E!@~0UsDIleja6U4 z!|hhH>+)?RzO;a_@clpAPkEAo@+J3WmbdI~Q^GSAXA_awffnK(NxG#-v@ZMj@Nxn* z#g=*VQbIZuVTk=a2TJ-oP#x#@S`qwwl~$lQ9?2np7?!dD!+aCz9evs5nZ4q5BHVF( zu+ngTase!^l>k`zVfWm$=3!SRbk9TjtO6L-p9CFVu4(V0t~OWh_Z~d^7@8k|0(!~H zZU4gtPRH?d&HdiW!^SeEMml8ua(2Bt{93z%5M+5f!+&?o|8R4G+8UWwzO(JP!0)(n z=}4ozr4GO9Sib)Hdb!?Vfi8UWF+l$8xc}pE`!o4h!TrEPz~S$Xz#$j+k6gER;lZc9 zF3s4k59_n*r>9fza1X+V=qLx{_B$|tK_Tuk*K{4%y$dzuUfKr>MhQwPsTcBWkYVXx zYq|s`I+a!ihTyFCoU*bX_oU3(JC%@?}^wzWS9*V65sgC?g+ zb-%x+2XDjMWZ4%cf^aqx)cf{PM}sT3|9EdKFP(gccR z)_H9W_qrLq!$-NNK9`sYyZxi^NwR(A{RAX70=K@3|G5TP)@ZC_-N|w{Qg`cV>?}++ z2Rm-h<&wYU3kzX%nCvM}JRzrO7~8HZMa6#%+)=7vG7=uuZ=~2N6~(p`r=6g`D14TZ zjLRV_8($MwAQS0eaZ0OoRnU8eoTz(g1{hBt)cq@hO44k}E!|T`-yX z0(xoEk!P3&MN)Bxd(FxhPouq4-%2!jU{1vyM)STKOxE|Oy~?q89lAO72>w;e%q$`1 zH(aTFDL;SypOlftm#1-XXxdg;a>-Gnv(|fGX$JL17AqrlF55LtPw652#BYsWu8%aU zN+#wzH%r;LV^v{q6q#hXbnBY6xEYMdn6fYU#)zo?@$+lA&yVLd13i`VM4O&IH9(Zd ztEBgjHV+hkQEkEKzspO|p!8q#zrlK`VJMl+ym}Wq(*DJ2bf<_Yj%Jklp8s9=Daalmh+s;ZOmR|~_{GU?_ z_dZiU*_tt=QYIn*kNra>CT@VySFf~479tUd2@BEi-{ks}u*zu*Q*$|aulw%t z68NienE7)xt5-MRmx;tKij9r+O<`-jZN^svLSydpt#1Q;H}+?i;SO&rmz?}zF}%Q; zf`(X#rA!TLH4l)eju-^EQ>Y{uP4G?U}76ma&YK&-O$} zI0Cgb$UUPuGBvTIuoC77ET&>FIeA#BY~&+oguB^riWq5e6eS}Ry>JL%eIN9j7rfD* zp=2*e>*VxyrAWBhyxaR5BBSO`sGnbNDm)EYT?#(mH8HVh+8~K&L)N{NpP%ofc>|N6 zKSd@GV9|a-$|{zA;Q6>FS}~(rabNf;dYRJX2~D)l>VLZmP%%?urlxx|s#$-cae*J* zy5V#4$?xWULXO(hI};Tm&k(h=+14n8w#Ie!1?uOV>$-_WrXfy#&~ZXc3@%ABk}7Iq zK9*LUi<0FOZOG-Mr>SI1_ChwBGVs}U5VF0k-unbOQ{1rnB^|un=w+LqwKX=j zzZ5(>G%@M!A66uNC+VKqDfi? zPKz|AnN|Px1Ym7JNr~{gy&Z!I%QK%gGMEv@59TSi; z9fkF;UtOm(i=Pu!p`31sCl(|rJrXV?CsJeq%ej*h ztnCfc2Q|=_OQx8}%dLsz68Vx(Xj+`?bM?iUSjTqI4M-!!Rv*$+KI`8G#7o^&gkY;IW5#-!z4?CcMe|C~f})RP(wcQn0jl=$ z_>a#Etr5);4gCpY2!8(evT#}B8f9S9>4wWJd39L{r>~JY;-mk`x#_N!CGBGp0<2fZ3he&D^5~n(R zN={;_p=72}B;ov`K-flTeg3<#nzbwj5wGKzYK2F_261btZ`+kLczkyJX9udKm%=h; z!3p1bKRrz;+oAssG_*3x&WPtp2m%h` zUkTCKW}CQdps)`KK9D5#j&@24d!#-G8*}it3fcCP4eA-C z&J;7;q1@z9^5Cr=uulA*m^IsXHZOpNRHUay@Oz$2SA`IcenKGoh1>zPVRshdb$mQYe>@57JzmW@a?S&TcN!7H8 zsflUMoG7ZTDf_FFF0n=U!BVb>2Pg&L6JllnG1iNMkexk%s5xz9Iq8get7P5ihgODv z2;ggTWY>t=RR|Zu3Oq`5e8nk?HICE7(~2-e!Zs#iK4J%a`inRLTsI6#Y9<*b^r2gE z+O91&H6NW-@nQZ{aHujj(OfI=wHseuiuoDy4C_X^Qyn2GZ3r9n(x zDo%=L&9MyCizYK&{>#bpmF*sWYqGoSGfnxkCIS-lXLeTz|B2MudPDxVC5CKKdp#otGaJ z6`4`>DeYB*Buo$ve)_`u$e$74EI6CVXgO~n1hUpSY@mo=Ah06^mV_c{-kaY}8wPJurOly~_X}0h)9CP*TMx z<%UN!(K6T}@+ng3ddv?bt0VK-_nx)>2P1oi7j!GvhBZrCY3t`kOFL`s;g#>mkL-1U*b}CelhKSX&7bYLe?>}U{8@M>&kG0exxEf>ZcdhR--4GT}Ktzbq#lL#N0@0#p@eZRS9sBP8PUCdR zYLIbG?Cx4xHC4V?g#|x(7n&anW?@xTS6j5bdJ2mBRPdkE#_p~SdqU;e^_4pSJHYTmTz^efHS|jBUBjCmCfF zs}mFZ#+JBNMc%$9gEkawot)+AjTgoh+vpZA@rapIQ4Sv*|JQ_@jFgRVuCX@tse##Y zu>SnDh7$ufZq`UCMU}^LunV;)&N0ugQsPi5l( ztgQD0Y--;z)SFptL>zPvr;|6;EzW&;Ku?Dvhej!tMUiTZy{Oo^1P@GXcHNn2rdG+3 zAm2?L54KRPJ*;Zl{o#&4oi8ymfaDHhP$WSvhN}Bbt0&QtPIYW-Qz(!f3qL)`!xP3CRqJhN#HxJ^$3}n-VqwC;Roa-#sdg(O0kCobyDTcM@tb=Mtn& zeqmPll#i!hJ^tDR?2vuRO3T4z`ekX+94rWfnwd|+{W({~ncmTULAdycp7%8TcloYOLhzhQM3v4HLVL~OlO z<|ZMHPejk-NGD^RS`eq=FVMIwx4CS22k%|h*(!cF@c=G*C}7mIqwPP;1s(hqBQYHk z7Cy^=%%e9S%v{`=rCK81YP5;MeBiT}%EQhKTX^ z1vhOz_mLMeo+AcEZi|h;D=R6fgTol3bO-^3+e(Y=TkE42H~By%e=4AamQyP6uSNOI ze={AVJx8^WAXKFM?YvP(ll940t!4@TKOrTCLL4+GTq%6`K)q4)um&_GB}Fp8P9N68 z0nYqgxZ*mMWVjp*N+ltY8z!n;gMbfw{$=TaAC}5xjK+5inwJIXsi^tPvcJ$YynV?d zh%uw@Db29mniYzou2D6bC`EtUd>^)Q=4uizOQ8gFIY3RQegku{aI5Qa4GFTKeELRn z-P@R(1&5FM!}b=+$IOjQEap(bpVW$l8mNmQfg>)K*qwkR1!A=pF5%8r< zBM^wA${uHUyN=~x2*ow}k@$t*^GcS`|Anl6A_aYGCw;#;q3)reBC)KoYIg&^o?L)! z>O;DtuRBgUi644H#6=`GP+HRWdf3G>v=1nLsEsG2zxYHi-q{K84dPyYeN7{IvP-m< zz6RwcwIey?+ue`B)eSsX{l>z(%BqBP4!!?-+u5U@KKW)j6JeOE6T0JZe?2@W#CVst z68NWwy59QeR_GIhl;7#EA^x-LJO9Op?`Ig19o0Lu$DN*1WyQde4}gAJbMr8JO^JFy z9o*cregX>e@QdUeB=bQ}Fk@@Fqy(EC)qxb3NbiqM+=cIC!yh{r^j<%^ll$5jw)v~* z)BW#)eW0dn)MiSQNAQ;3tf zELt&kK_m;mkU9BOaL~8_%iZvMu*@vnIsp03Mq6f zu$C1ocLg8hz2N{W7N<(7llE}5%+m6l$0XUrX#O{}t4OEn^cBVsFk|bk$ZCarooSQ#%t&m$gSasRHB`qM9W?^k4@lC3)LKLp(|`DjeKz z@yfn#z#Qvw-gIJ~W(lN9Q%XJqotQkEe)9Z3fi!Roo1t=x7ZuJ^S*GaakA`@lFSbl3N#g2^a|ylrba)0=0y3DfRjWUOwuYbdG`6E#2yHt2rJ-y4TM%}yp!@n^x2^BA`|6Rnbn*E$E`24wwEeSn1 zG5Gg8x*}ioZ>jhBZVPwyta)Y(Z{E2081$%1bVu7`)>Ylw((tb+0F@V z6fBh_N|uJaKR*6~sS}hRPlH8B#N{xCta}C_&Kp3_kw6~BG2;0ZD^D0xHPI;*T<=nI zIr$zWy=Lv|x%!BNmCex~q)}N9ebL|HF{6r^@PcV#mGyswl_WGHMZq@eOX?Us|B|$QSiJ9eTL#sVYc_&=VI-MGwNZTBQz9_&Hy) z8w0)ekTdSUJY09eBoY=hhPtr3DtuOEWD%&D=BT-|ULjOD#4S4rE1*_#C9~4EQ}%fN zt9H6Q@gJes8{%J!spAGTD#MVc5rpqNKY=1rKukm>(RL{WOwN=ra)m2@Sz#QyC_<^7 zPWmqvthr@4Pc^eOQz64S;9pozS(!Sm)9{$U6#O`%T=~?bczWVy5!uZAL&}KjeE+-K z#g@7EaZhe{_#eDWUiK1NO27M;Q(h3b8i~IT)Vq`{^qmKekLMSAfG^{*T3p`~eF0&D z1|sUh2~$s3qUL$$q)*!Jb8Te{2U;2$eiA6d%1LMB7vH2hK)bx$(pX#H)>vOFz?kY@ zIt@ooPnY!+&m5cy3LBcb)mXH?nqgdj^JZLtUxVT-SPB72wzWSWE|TtS2%wId=zg9( zC(#%6c3Vfz#O|#HqzsLQSt!1rZ*sfQwiLg-J>lP9Y$CF(Du@h(WTK8Rkkr* zvF+q?chUZk2Sa%6oy|NPs>t|_0#l364>q<7Bn#LE6n%Ee#}1639*aLLWKn=L#_6+$ zrrQrsum558(lH`Iy&hqhmEK$@pOBEZ6)_QK*T&m}YYtilX{D)#^>SX{ef?}~qI&#; zP>rxT;ij9z@vhk7y7|l6VW74w#x!5=Yx;BP{vjb~OjM#~XBo&lFDA8QCQHYMzg^f+ zsy8kEe94AIjFqVHSSmx7Z2rX=aCl1zRv;r!OBuoii-`2#(yzr<+6kMQHw~(OUS8PV zk{oNeu)wqj^tO0xCY_Euyz&|KIk&)E+=MY$2IU(8D`kShwxO^3c;vuKqp^lft+>Ma_|iYcMmRBxRdZmDL;l&7uTC2+IR z7KMZ=)>gq&fYe{ju3Je-P=E!>rqfxAfzC|Ah}1v)HY#+Zz+{uMi9Z*A1UKQ(3jT_t zZk2-rDZ(LavZFOtwPWIBdx8H1cyeBU90#4pHH;T*rB8bUBK(dMr>7EBKGr8bzn_|3_|Hxi`G;A>B*=*!c zr23~?(a+V>28mQ)p{T;52X6$)e^YLd6cu6P#ggUnd^f9?3?%)vo_0FiM(P_^MX7)G z*_R?2i61|{u6_;NrAi%QXr9y7QJMY8_H5JDUB)j;y9Fj( zW~!4|G1IDS55WqG^T?iARq1*(n`7lism!| zK7$lXt%$<&nyhYrk=@TY=#Qj7<(Ra zI6IJD@UTd|e3tAVx>fMtw08ZtbhYG4U8WM0g+&qZ0v{nZ}HjE5*ub>YS#3mQ!NTWjXQbAVa!nRX{3E6vWYpg&-o3qPIe z?w&O;GDo>DwNAd!nud+cwOmyk9a+kp$1`54w+8S3xH}KwJGmtqE079zAKDz5u?!yB z-JR;ZjXG#)2@(0AFz~C6lz_>O1PAUsZN!J|0iZv~86Pe;K4t|ORnyZmn9q+7M4U_? ze@)8uXxoofP_f9dgg9wJ#fMpvg$4VR)i;PgB|drlIJn)?Wvbl4;R$^!klSnmbu$y5 zY7-Px6g($=l>4GMzHIH4>C1XOy+`(1P@VxUI#7yIaU__dUjEx_fA++9FdMe_af-UQ zA`{t8OaQqOVSFZtBt}(FP|c1kUAl}tm!Oc&l_5lCxZwv^5zQS@o z((lqEfcERFQ4*BN-G_&@l{(=>tCF=$JF-M!Br2Ff@8ut!0;RL$>e1$hWeGpml{r+E zgQKIPo!$D^Tz42MrH<>)?Ay?vN%}tjyS215?)$n5?SM+US~H} zwKQHN5?K_HSa1d|m;=qp^YK68p~*;jq9;#)w{|54bLGmBH_d-U(_-snbWHwAQI6yN z@UQ=-r<1_EsW_)n_$j=y?Z%KsKZOMrZB*PcYjy(Iio_xe z-`2Gj$H$)#yT)Jwd*m~9L0sA`$!oXx4-WWuef#u*_ZEtWr8dSl4LpT$+8z-l_3n?yk{{lc z;aSsDwzgW4{T0<36pn{Pr-G$s++uLRB>!E6a*U~$XLx>x6GC_ls6L;?j*I7Nn+igi z2r|Aw(8{?#3526*Ps@gfj?JqskeVvmH8zF?*sbHzU{Jza9538-p9E$y-qP zOmce@uq+0Z{JF|+Qid)feS+zmMLd>oPld)9024@&K1z3?B@{SSy9nh}r7UajKO7-v z%vPL*?}2$}N<+?Zr= z!(~9y7d5_BQ3IvuwdThGZ>280AVu`>Sk{~NaKL4&1-B1BnR+83;=zt3bkYEK9=Lb| zYh&0%lY}u%f2(*_)iiOlle5VKD4-sZOXQB_{a&*)0G?d*oLoLnK0g8A$fG00DLu(rDlJGDySpnKr<;n0o-Wk`l75u>#WuZ%T4T$#?xH^fn^m=b`N6 zZ?k1f?7+0!VbcntDb*-dmO@I6yIg?PCB_iagoN zl(+2ZV|2`9{Czf{sBG`6TfkagF*6qOH=Qwj<>nwk^UKf{@PF`Qb4QA9W_P$uNVc#P zYG^g^?Mng)PBGIE6O~7fVkXbV#GH@E7xv<@@Oz&%R@?X3@5PhDFW)nUoR%=|o3{Vm zcF1R-%T0*@faxnJhnfEV{>8;Fn4qpMg+T*g`o8o1(>qC3{Cte`^*`3$Y$nwhU6&A7 z9@Vmp5}kM)zf5}O7@c8dLhGCXK_M0KFmeo0HOAhX);a}gU;E(pyzsTcbH}vnR^>>L z<0HkWG)+UifgEk<5V3|@_MCB7{6`8ql1$f5GkjSVmw2)xc|CSk0Z3}RP9gJqP^O$G z*(>J4?p+9IjsOQwPQ#T(jk5>jMNjoH#=Auxy?%0~++h8fvmzoVJ_ba@M3cjrtl)AA zJTQdy?3+t5s6Tlwd6-*X@LkwB{2p1e5;Qcua*ggFHrpAq^S)TVx#u+%;pgEAIS76z zqIVdZ4*m|`k-7jz<{!=vdTjnYmG(U7Tnt$`Zoj`LnoJiexSlFkR*u8Ra8m-rLXhfH8P-Ywq?!he5HgEHAWH> zlPG)`M9ll&P7o0H_ZE+%pUFomlE##IJ2j4f+naA`FL!`jKlE4L0iMgb5We&QZqEeU zda6>K6i7xLTMPvl^hmZ=xWACZmhE@i07txwG0tOCd#0iMtzIw4Y_ByzFPKC;c}q-> zQ+>TKBOaDU7WKGJ7Q}`F7SQE^XXw2$)wD9ytJMdoQGSB!C3_<{DtT!uDbzBeM5)#< z^`KcfO7$1QAV^h0$v3J?3+Wf>uE5sOkOt+AU5i$=&x-D~{&RG2!;RNR z7v$v+I1qJzm?PXKtjP59)%NwZY!3kxKIeY#&P3%$MlxgL_}v!TyH4Ifmfn4>6_7ay zs_@0MZc#&vlDn>STpAjG23t2}XuZY9i=B{@<7)m7{iijoqQ15?loL!>8Htc(OCZpw zQ|81a6BJFxv{t}MVAUGsQD3%hdd@|*ONYvWW}P7B;;ajRdK`aaH50;2~hAA4-H|Y>DMF#ulNKxuywClQGq1Ej9ybqfO^+AR{`5 z02@EQqT^o7798Z}#*wF1)@EZ$3Ob&v8b4Yb)}JK=AgO^pnVJ_5r{$%#Om&S7wl__@ zz>>(w$dF#GqxN2nYsfAV7g822FqJt(#Evri3ggB;*+IJ8pWHJxBPl~R>;-ei!mi(h za^Lha<_wk!)-XtTU3Hqsew*Iu&4whW{`UF;Lse(Iaa2!A(k`9M331)rr2af&SheQL zVN3fr){DM;oETe1SXfBr^3(%E;NA@y zXQm)_}P$0gIeN5NnItN7FVzx*XEYeavr${S=GKZ7fs`wo> zpYc}>t|9Q;PESFR{x4ToZyT@;Hzg*LQE-=nYkMKo~GM;+fkjRl%Rx+X^pT89L5EY zT3;n*qLu7pw_^U~%diQ#;*WD(Fs{;Qp~lmWDXZw@I%{~iR9=|aKX|yFy$C;KiB_f{tNp%AWu3SWm*^I%y80Q1+`wneizs4;ecT;8= z$tE45rSSXaxa6}>Z-U$g)p?(bMrFv(IgY+|A$PkvR5%D4z-49Ob3jP$@t z!~&&}F>F9KQqajI86Z_roB>jJe1B8t{MpO_3d7rM8pWQsCoj-Yho*5c(8JiUP(5KQ z(itkk`}4LG!AeyBS=YGpU31B4_0lmEhn5ktrJ^Oj+DHv8%Fa?ZD&DI>1sr*sNM*XQ zlV>9^r?6#Rnjg{=HUXp&5r`))|0=&t6N4{$G1VV)i(Yz}7Tv7ZO`=e!%B%~6?>^tw znwPvzxK+Z_)cjT1(q{HFgaNLdIvRhGob~jvV(ZsmGuULkeQF7Mldr^pICf1ggVJU z?1V~761&14>FSoU`%37z2r@=VIN{t{rQ79J+K~h5EUDm!7zThU7DidA#bx-@-WTm&LjmL2wc^YM@ZZpfdE!6XOEfcu=4 zc2}CDgu6x$Rt(hN#{0OJ&OPL+EUOX@P0ouS$v0%U2h8fv-i zE_tE4W50E}(n#v;)CY(s`FWsyV|{+Vy>OXew(*H+T&X_=K_xhacG3lg~wzc@~k ziS^rba72pU`!BO!5yp3Cv;{@3YW^4A`I_<~!=FaxT&X&LPTuI2_DNSgN3p1XNX4eKa~BXtR?L(=Oq+ zW&B7aC1coWs&iS|NNJJ?8E$xY2IezVJCz(l;-|DVFsyJCc~Dua`MCzkx9H>s%m*K7SZZ1-58}*dVXGF5{AJ$`I z!E+=md>@KH1OzdvAF7zxIm9%Z~5~Fvjb<~Klj6C zBxG)`_-UB>e8=)6fXUT4AluvWnUgQ_Jev*TCQ6hnYR*9~IYYi^ z?S~#DCJjrMi@8)-@z)?J@h)Ve&{Ibgq9!^5VFM$4c~m1+ag*h(|D$oE_8CbeC`|eL zZ3DuXlP;GG%3#W%kXK_NOQrycIOA^f{Oru8Nrfv$qJ80tZ0HEp-eM9x0=ti7rn;E@ zpWz;X9@;4MVF>(K(yUaR{iQaC*6Pbgxlfose49l}y%wT&`lxJE2%T=V`tuc>!UKP? zB>U~xNmRSOUqFDPv%U4+wdP1Id|-o!fdOfcnniQy1U@g~9z1hiIhI}-qxcx9w|qJ^ z9P3NhFy{)a=2MtEYelar7o?%(!8MSilnTZGiE+$v6>Iua3Rz~~DqX7*lgZC!eg0Az z)ecIYURHlQuTl-;lWo3UH@O*+feE*n`jm-QA@0r$*W0f8InSk*c9v@026lK`CfME} z#$9_d=@}W|P-+Q~*p~t_LMavKAN%?_Q9{f}Ynq-akg2+(yMA3{@?u1Krz(Z*Wg|I~ z%Tf~TicD(WO7Um$lc?mcX&QZhq5TDOz_@fC!!YS1WcS;bIrmYiPW3@Itm7&KN2}XS z@e#IIT@rz!rYlmb{H=KUeDlFC?i%{bTZe~#^Qhp94sR<@E31t`O2+%cI18yDQRl`c z%R1Z1Oik`A{}sOlH~c5NSrFh;(0O2XoX4_WILmV~gWfg1bGk7TBhK}b?srtLU}|V@ z_BXLS`0qbYDdL-;ApZOgo##!t|Ng%V0HIj+y;uV9DuHWBGe!st_)w`z93CEiEH_+F z+ku({0}HkPo3{3bw^a1}HY6*Zk5E}#97fWhl$mh;GMU8|k_#Of8LNSzoG+@SkTBjo ze1)#}E=DzD8-x=_7E;&VEilcu_3yh_-C9Cg3}w8oyJJV_>SIF2(#q1)eOk;&W$DAt zPSJ>k)+}C^smd1pUK&@@RdE(^0ai2Mj&A zK$t5els*Fcn3#~n%;BO&m_cT%0Ie_+G3uwBi1|YC{a?9-MA#-ATV-=|2wUO3{C8Nx z+*}=7V(v-V#Go&xAb6*_!++)=eJBBn6t`DI4_BQ;fEUYX(1*xv zZ;$cnpA^2O*m$bP!Rz5CJecjPL;Q!@?6LjX7C}%v7Rf4k!Oc$h>_6VuE8-GD;rD-m z5E%VEQ)2$-fOPQ(4L*?$rE-NgUgQ{m)tlN85HpwdP5hF znYd!=2(q7q4xzceA~@IS9Jw?Cd-lL!}Jb!MCofWvQt8eKPc%Lqe($s5^v5pgO{k z+wSC(^tof5u_t}`oU^hn4-Qw^Y!oK&WsDd7+3Be{AT|9Yef%#HyQUFI$*^%91||IS z!$Mt!pJ6t9ZyBgM`Yo*fI=nYJ53VjZP0dY<=u9J(2i2vdA$p=&ib|7h%f7Vd=L1c2 z$s@~8Kyb8ee1R})5888fxtd4K^rnXGY_FKL1snmdKxXrk*zy`0qda>SL4XTT>iBS% zTKXhsBUEY(b(&lL)>Zp-^N)EYsoGh-I0`7R9mOkAq2wS>IC* z6O-w%kh0{I(oz?QoduQV>RnZ6pkd@9Yk*>F2p6G)y#V=;$+M?XZibse7&Yr?%S*cu z{-?9#)9o?0<<;@ReyfY4Xa7?(d*DEh))R6in>BSu9Zj>U?1!&n*}Asqg)NvKd?-Hr zTc$n@y8|F9eQ{4wFa%oqMx|i6Ef9lo7&WfXRQ(~%qQYUQMTpP^o0kc&fQdlzA7TdE za=&`qjcnnnfcAXJ$3*@%9%F@q-oC?*a7l{w`d4;$)636*?OY!-SN9tTdeV8^@{B@hvU%~jO--&UH)KpjNc231o*pvWTrH|KgJ3!`eln+QV?slSPu z4qA`DKQ?VjBz{_=gUEjNdB$x%?0i?LerM`x2%xu?X!sh^k-ReRYzivnt@WlLLw7wR zWJ}>`scv~&`cnBvMdoN=&c`*iA#Lgx*5Bhez^5}nQQL7KGF00_j11bEB*X}hq*3o;L6Y0Z`Ve&wczWV@{aQ}bIY4~qjI2d?(o%o%qQb!mi1Hn-QK~Eot;W8dKrMle+I9)HCZja zziPjk;0)gwgd>$h)q-bsgk7}r0(hCR+3SUxs-j;hel!4U*8`n|6u%{s=eY^Afx4Htbb)A$!xpL(; z9Dzy3uvI4pe)&$^hXcltaNw{jEOx?#TtB7EkGV3bV%?HaG3@_$}&F z&+BPrnG_&6Voa}0K?#nDkKNWqp9ox>o$3$5(_bV@0BU0x?Nhik}B%XudELITk(P$e!RYJw|cEXLGcj~1Z~+cV2qoQ&B8m==S^BNhm2vD zf8L3syt=+73?y7#iLooTri2cet_1BOO8|7i5&i4*QJ~kuhuPcS-w#_YisMl36LGUB z7^2b>cdQwh5zQv!3QH)+1ajZIYhS zPfYXN)Xgb=QI*<(W$lVICRYF2eP$-3NKQG{+~XqwM}Rn(GrqpAco8AXhD#tzK|>lz zkx8pVN?xl;6_nVIlhNovN>(MoCi#>kQ4KEjNJK4+yq`}8H2eB2sFOv24)p%ZEotxk zJHL(li;g=5)0YNL6U`kbsI|W2WzW4c%ZEXS_7iQH%ZG4q1rl#ccb1j6MN^rR>J?(QKTQ^5~8-#~H+$>+@ zORRWr9g)8%FE4M%(J0fiF3exv*WhENx-cIY%CX^)1(leyP4bBCzO-RxfUFv0mYbTq zIrbo1SJ*099&n2Ch1LdsdKx_V6L9mgbE_Qe)hm`ouN#I*jQG%o)2qd*nu47C=hDF% zODQ=~>I}|BS zaSQJ5?hq(m+>1kj;##zLafh@2i*u2ijEr0)*?HHVYtH!?e-Jdzdg=?Q>%4vR8cyop z4A_Yt*Q&8GZfG*9R8^ixshU?Bb8x!iz%q()d)d#f^*LBSPw3~;Lx9j=B$|%S-Wq@S zMt;p$I?GV#k)S*EWSv3|21vPuJ#j|+= zn{QKZoa&Q-IQ^0q7HQ1#3V0yFSzU}sgaS3R%w*f@P?;i0?$r>PY+*J+tjr`K7FN5d z9UU4JSquDS&4khY^0IyZ$G>>-;unL>SBr0bPn$y+x0A!D_39(=bUKO=E{Su9y(ZuR zhuq_;RNG-{TIx_uh5O6bTfodx9N6l zXi6?}YB=&Y(KbvOiZU_uLBoX&;g_>T2E`w_KeYzg(-yPE<}^=6-u@mg|JEK9S8JC5 z+-JJ-0m7bK0`a|nf{Mgp91EJv=P!KI{bQkRqMfIiDiE-0V*4SN8)SJVscA$$(his6l+rxe-!UNWI16aTI{^;DN#mKbI&78=uI1;afPfkTnLGvqwY+1#VjZgSk_9+ylG8_j zv2-8X&2FrXr$RS+ZRT`6)8nk;7T-IOa2DVI&!rx?;^A>#S^==u;~d?b+`MkwwB+!s9%@&opLGp^B8pP%$!FFw0f6zD;hV?6s z6>Pn}etquC7hjpvU2A?CgZOl$^xqf+K~M<73%T00SopHo9M*&SF8UJT$Vk98=O-A- zYh4zjgZI)pUkF8_!<3fLpxCDrryq@c+&5oe$oOmGiz}+T%zf>j8N?stH>37MMaS*t zNp+vHhbgrgMbI1wf9XM>{4+t+a?)Sy$ECk4)G)EJHdQqPy3KoGH=FhLc?v@cj;{OQ zB)dOEd-WHiH)M;~x9lQbf2qJ?H@|tNMX&71!_1TCCcS?*m#k-epO4zNI#A6Oo11BI zlfO#>>`qpV&EE4zL483NGo!PRo4uEC*2IIySyz2nMW-6~M5fZ1dyYbLz1{p+u1HJ1 zh>yRoy-SN$)dKUXfTQjCUt#BMzRkOX{e7Oy>&xzLg)U*<4{P%?sVT^~KRN?T-lq(H zr={k2uSr}ZVL=!vN}fRk!-<%PE=V8JL}!8|^mALf2vHm_s`hZTsyzZ;W|6&j0F3eB z)OGq;&C|mTu~L(3HP7W`IN;?Nc-(7uKku>Ww}{?vNwu!I%)b-+*EgQd!NEEK)2aWU zKLRXS{W!XoY<@4+8E@LObl*1DF+AVAzP`SDe?Qv$PmaDZ0S%tkAS1iu1Fr<4BtM=$ z-cM>CvIg7fazttdL^vID@?lf(^pz`6-9`EGZ;Zv0&A2-Un0&AM2EsQUTUw2}y}r5m z8Wbp4yE;%fG@_%&e|TIv;;VK9wB+b%qq81f335~@RiEmfaEJFL1qJILs5WNjUEbZd z?tuMRo$=By+#bcUeK!LosP{hs!<%2l)1B9|K^y@OELX0jfQkS#%lHD# zC;$-r_3ZqmmilRB#$0$|(&|3`?LPkM>gwsP$NsBLA?tnXga^ka@dx>K3b;kA}vHN+3!V5DT0@H8czULiDU&CLA_raaof3>^UJ3LmanzhdZE(Gnne!7OlP<|VMk2Tj{Y1${UnzO}4gJKpaM#?xa8H;*%5Piwb2%G82k%*(on`sSW2xlQwmMVn3XFa-cM%177ab07~ZbG z0C?Nc=3$*|DxIZZ2sKHPf-i2Bl(a1Bf*ti5Wc893{{65Pie+R|tY2ljPgL@!8(A2n zWe(N5)!64QXyB<#v8u6gF6!(?WW(eBUr^0hdU4C~?OJD(()OUTe^1ss-6m_*K9SoYE;#R&z{R*zgu~TPYxa{S z!ReEIoKzETAdyrQSQYlE1;`i1FWc!1aXrq*Y>NxbvFHcvR*lOwlwLvk)BBCfA861t z=M`WYmDn1M8kz6KGVG53@htCEx9X9_8XVm{OSBy-N|`SNYcNNFi&CWd_)V>dNF@lE zLb>WwNSVegxnqxf*Q$7yXCdEgOag003DL%;NzK`@;)-Y*9hRp`DQc?&rI`)?Qf6o8 z8~*DAhp0n{l`zI5hyH6`7`ypezor8JOAlorjE_I{vNS1fr=1;`Bo_EbtQhCm6_#$*I+tiiboYY505g<>KeV~=h#n;>?joBlUaWaTVJF{nV9!!iHVP2JZ@gy z^dGLx?HEHxheBR&8m%=X|E&P1kyForgRR1lg{9NgIK7wL0lCXJ;Dg zj0iH3k+PXxUD%&KsgKCW$YPiESV-MK!ZxT|{vzy4h>wE*bbo}0M4?t`w9 zn}PTbNuw5i(;_!3kpMa+M|_j=WBpD$#EdxX^fY(KtZLb=>lx7WU7fmb(&B34tXOIm zvH>LS_^TgBuAuvvGdVwhZ7ckqEbKc;m^}%fK3R3IOv1PZd8BOq4nWgTidE_mH> z`iF}KQ#v@35$q5+X%J+b5s8Z~ngU+MWpYGr5R+a>k}yyX5d)XDUb6Y`cWDG^(!uOO zUummoMtq)RlO`wrp^PBJkzI2xXL_LsS=u1c9jcPK?#P>WVz+y@w@Uh}4F>@o=T+<4 z6hhu^Uc1|obJnkW2dYLtzVc&Q2E6Hlu7)^#E7f!u@uN7-eJ&n|^2aScjr*jF->n{S z+!$jP|Le$kTW=_hhtj-sUfy`uOMVq3`$a-$2;~iXfU)(DvZP zr}THo`v?1M%WlH!_Q3xJVf8cPe}&P#^a?@dVaVu)e!C^I^dDCSMr26v);wP3|5L)k zoH_}(g!`8^FmZ1Z&|A|Fg&G6~8Ply_05Y?z@O4Tyj@L~b1+J<5K|^hKYR_|Bk6LAC zZ1JaZRSyq0O+rEqNwvxfh`RFhl)i@Aw3hYnhCP{?n3Bm8jR%FtTj8Fs@5kSBZoWCO=3h15pj3yA| z1jx@sWJGFmYDrqe8t-TlKXFm*T8=~ecY$%YnAx4YILi1W19>zgCGaLxIw{wp`;C&%I0C_vFMU ze~mVx=4Oo-T79RN?zh?}MXJ^NCf#e7yaoUr*J;h&b^WpXEB|Tx-t68uS&QMky=)@C z^kB53JtC@oWFVVPQ$H?E2>uwlhLV=PIf>p)#cYJPR&5rE)AO@+&+E%(0DxZ8o|;xQ z7W8!VH@%G&Q2BiHpCUL}UNKTqxY>2_Gop&Kyl1oCx0jnB>pbE58f%%djK<%fnT7?a zK&ugW9;LxJR&CNE)|7;}B&AvPv)y~&QWy680f)Er3W4~=#;UV!07-Oy+^Z;CBV9YIyZ$c(8|J#Q!D0P}ln^3#8E^YznXQ+2qh*Ml|deMJr};D$1VVnc9o zxm9;*g&3^gpFNNQ0k{`)O5e9}hJfAVX}`0^IzQOWlV8slZ4Q#Z=Vw{(_1aFB3eB6B zAKP4ud3ZkYG&V+Qo=e>QC$P3;tJj~Plrrd?^}{!)ca9R2m_pg2bI`lU>s$Sc1v&&* zFuUU8EhCW;L<}ckP`uH0d8znzIo(sBR@B>h&?4Y>-zv@{%zfGH^XjqFZt2W}+W+s6 z!sqq!yr;=-D5~dS+n7~%R{sm{mHKPqaK8Vy^H(y*AO44hbQ~wX^>uXtqh*R;ZhkI7 z5A|I6Ck{e5Q3fgum_M^vmUGHC9*&a0{r;O%z%%p%$8#!Hg1rg@M)0X#LFk}hj?2`9 z$1&e`ZZmAu0Fj#csH8r@1U(}KXOceAm-AY9E`Gpn4~wF zlc0w0rpE^RyxH6Pbk@m}K0Y})#j4NmHB>f^Nhz#(%IvV=t9yI`7@*L0Ar%!XH_$w21y0dfId%T|{ zsuybEEs9+yt=3|89=xymp^+2Ij6^tN(Hv)w@#p>mD8aR7XJ6{tT}&>D09ND%>VeAx z*4x5I5$9uTtc`#x{mpi7o4vx2aOq!I!9ktB=g%2*s2^elXM>wVu`?v4BT}pz@6*K% ze$;#Ys`>ayoqgE#ibo-iE(dL=Hw#c!FRg1iIQQsWGR9g@^^TTf1o%WYyWnxz)W*W_mxZ=54k(46m*ErZpwSRnOB)N%@IJi``_3+wmSx z>diV1rP@vD6THNm!D*vOoa{W)PNHcmS2O5azOAj2`H#V{S(62zY!PonYu#L zK_vL#5M1nWtzKt^Zml@!ZYS_Ic{Bt8g>?$gw^v;4Wm-G%XyH znDV7U?+`9UYwhUxG`ns-EPQ(RYABkc+vctM>4~|t)zJO;h@d)-Qru(rZ=!XpIFX&} z!B}W+fR;erIO8 zI(#J1P{qHWEF4eO;$5cvL74q_0RX1-%^#N;;aBBix&G;pWY&@awud``6hXVk)x?8o zayy1dui&O!W*>Ibel~(%$ogKD$J%1g;O@%R&BI}4<(`xx$n9KW`m)c`xh%pV?I(#; zw*hNP^xqGBINTl}#u!%2gw%js8GImN1pcF0LLS_r*;KG9U&Sk_#JKxxhQi0mh{OHU z3KNM~mkEUIQUmhwQJ9LnvLYx|0}<#-;;6s!2Z3182oh+_a;X2`3xEuS`alqBi|Zk< z#5;*yzep;%?cP0z3}d%@L==S?HA+!MM{ANU0yZy2t9~xk2!aH$tZnsaIrCIKp%HNi zb@2CicbZ_&j6cV?$keB{%SP-Dq!dQ&W>Uk*Tw$^NHd0^M+aK>Ei%p_nnn9^DjM#R zu+g{YZMNG6sHVpH$34zB>V2lCI9VGVq2#%p^OoR4Cy6c+O zgE{t*nL^8m73$lsgPv3~BKJES1DxtBuAoW$QJQC?9|K;lc~mhm*~bYkO|cE{(puf_ zZrxTKQaLIOZY~_+_ltrrvXEqgqx^0cxR{J_@g=Avq|FYbLqVe2_{5;4dPeaPcNH=N zuBJgNisQ9s-xcv+Z!G{iW&PZ@e7$DRbQ$_!i|+NLU+eAtl>PDJG>6`bfT-wR4%y#2 z$Ij~{sgLnt>Is9kPO7TS8lyyL+3X#i2DKmlMZb%GFVyaR3P2IQflNUJHdJe^PWfDR z%iI3tbd%cwFVn^{!u3VS>B^2i{;kcrDd@ZpfuRaZx?e=Ur=&2ay4H~|^&Ib|%Y4^k zCPHiTrM7SRvTE!V76aG+$8})9T1Ccm$+0yAXk#rv8ve-vlJacRt6toZL{ip&~0V=-S211mXN?n&+0pM=W$5?dO$X2~nUy1v)DN zk$y?afmFzu%%QpCf{mt(6^xFa--&d0|NRLW`_)?{^Ppg9;dZ@SnS88OJ9VJkHO~l@ z^eiP6$d(?|O)HJ$%EGUA@89l)qvoXI!3&Y7p7CAm*!&FB@_#O-q!7Nhr@MiBX7 zKg!l>;JIt!;C0`uRsETju-{j6ipb~jahTyJ%luLHrrYV!JWCp@E^EIeF<`N1d!F6s z(rHy|$Og!IdH`7at$My)Di-}Pa2Z7xq(#pQ;o|8_pgetR`E?=Suc zm?1`hPimS$zA6NSQ`>!XBo&U8D=P3D=ef~xu=f(g1*pU{SZ|l<=?*KJm0F-&^YWBi zG<-=!Lim5XEJ#gX)1~oo7?d_XVn|19bIl^wjUV^v2Or` z>%P6p-=y3vvTGwAj%2XYsy2*b{9Src&!t&GEXOo~$HQ37R&V@+rieR>#6D{qf{REz z1Gd9aUJ;>D!amvT30SN(1iU^`{btQcgBPNA&&i;wUj-Uze`Xw1&%6$YL;x$e_(S6x z!`UE^aPZpI*57>UzWdA~n#cyF;qF7kAHxA; zfx|}ApPsXaE6UfShxpE`N8#Subd{GOA|MigQ^&!6pSq>1b*ILi# zfr#<4W%`=;_^Q#;!|YDH=tk0h-@v;$LF7NJYhTUV3`i&_lxKM-8(a$U19z|5Dl^-7 z6|aVJxNTsmNPpw&@=>U0iUh4QU7@~w6Uk+x%eLQ9wz;#jejy@Sf0TVaNbk8Q`%-I_ z%<)+}SI~(%|6M6{j0Em%&>b5J6*iQa<zud&umoRgu4q^e+PsT zx!44PC5e?L_}+Wj8+!^Z+VF=CRYUNp3hu+PxtU9wUSngXnM&d0$k_5m5I`7=G13b{ zQo@$wj8Pb55RUv27$FV#yE{Gc@~COh=z+i}m$5A0t)m-o zL8oh#8$p90`(N!!1*oCvv?i8uzXMqte&Ipl$ZdxP?P)_p>D7N`?dUZr956bM- zLoZ=P_qIgE4I0}6BtE4TLCcyCT`zml9BoY-XH-9`Yumf)oDN_8e5T^^427EZ+Xalo zzc=-)$B^BWVP0w}bll}4ecL6q=EOjYSsfBw|Z3Z^rIhzGo zDr9==PjX|&9r-D#&S*hoZ?KnZ6vPcJRRdjzLjsIX2)_&U!UrQ1f3$@Q#FIRjEsZAn zsD8HgSBE-3-dw+`w-#{CdUsI1?wMDIEl`RHasM!TP<rPFzHd`_It1WV|-2F&P}BJvSG+dwu;cn?E+jFe4{Rr`67q$+$_ETR;F7%e;p!CnzGKpM9P(zUNCl z+`HXdh*T)?j+9g0EPWZ!dKc$&2QN1Ke5&Tzi(_?0x33S&^U;;O_EOV<5Lepiw5W)f z*v6q-OXpq~S?%WK0Of|~Mc99e=~%b7p2a%pmRGS^uCt%njD6-)!{c+&il6(W!jaVE z=yFRsI-Ew6O2e^wR@Mz;A$(jshEBZr>eR+3N9UBJq*a>jR#yABr>m=HZf@ATS(DXu z-H%a|=^vVIp3h%4h6N0KFU|~oR!?QMOIfD~6~7VKQG^B8Jd0XTLs0`kN{Cx^^WKH> zEFhE#v4d?cYqXba+(+3O5DE_y1Vj;5TwJVe%Jg_jxGkLRtWwx z$i;-#PbH5l^Lzd?5<~_?+LRcL+IC$D7f*)LchQhRCGURTJf5zy>nwIrwEnbGCK_40 zmNE-Azayw<-*TE+Ue|q8RbAV*zu4m|h_}#Nh}v7m?+S8Rom|ueX}yk%j{C&I-#@3% z7KdYY9p^6I?FJv$8MvMdeo_5U4{K!rNm$|F46CpS4iY+sNK_=?2Y=m10mNK_V%a=#G)KBn%BC@%izehzD)dv-t5`dw=k&uPh?ycW6KB1`pi|PNRiv3W^Bg zEUn7(MQKnkY9OOb#F!pBTI{TC*5riB(6|rxyW@pgGO{)`CM{wU$1<_m(RLSPni@Xg zJ&k&e$~+RWt3mVC)!c>QfCHLE2ZIac0stSi-efucpOZnh)dvs9>y}lg|J}`1a_8k` zY;-uCAI(>@Z~8vS5Y@fKpZi*SIJT6RD&NLEPzdjW^}_8~;@lwop6@q||kH`CGw9NJhj|36No`5%Uah zv4TxA#Kkw38-1QAH~ogIpRi8+_vX#R@A3uFQaRb}A`CS5JkJWa z%;15T>nS3w7yrBQeV}}6AclrxQarah`EzI+V6>ae5tkAmc`g5}=2(3WbMk#EXD}wK zbGs|goSdD2tFLIH5WrIuwrL`5W6UAW=T?v7Wzvbjk2C`#VN9HaMqu0XcuJM)6SPY*f>NwXIHLk7fJ#x6;OF+AWEn)lw{j-At@u=S z?=XW>G+4JmF$}^#LSES8`V;dhb|Q;%eu z!3GEseTgVkTs}qu;BR$72&GHHgtXl7tW!H-iAd5Fnnywbrrf6`4|0?u{4U$OZSL6% z01Ae4(VoMw#cuEDCOD&=Rz9gsPvp!ks?@-?;24_gb97oVpRzRdd^F=g#@<#z8s=lX z?7DyQO}fj&rb45##Ma|+iRoZ%Puu?Nj9E2yzFf9^3M+q+RAH#rVY;)){=4;Qmiq_M z_vKub0D-<8RU(OYv_Zw-+-8S4I;xpC;Oizw^!$5j{DR;5rCCwwm;|iVx7Apf|(j)bVX5>3J0I;OGXqP}t@Aeq?Y-hD<RVCYo>VTckn^P`@tzi|@nu~0X3TA@JgNTgp1U@2bY(F` z7{9QiXCM@YhXXepx70onIr>rb<>f|8L`4{CKlMzW8*F8e`=q%%X1||>*@Lvcj0buL@o&2n87$UC=>+xk4A7< zk~mC#io*|8j=TZ+pQFO9xdN`0gc>9b$Cn?UsxfmWh(39mz#(mNYGUsS>JE^Ifm1%l zC_*LIi0em_A(N`As>lJ_g9gu+-(TEe?w-wxOj-HW!>59=c*P+G>>MiO-w~>nZ1nl3 zR!phwJXW%`>bf6bPV4nMNM*c~`{Sj!%zVBc_uJ8nhTry58&xO78*Uc;xCw(p<0Kgu<~9gPy9n2u))#2DGoV7uPtiJTGZ z)faVCSFbzbfRj{)8dp*n)}G%ct>NRX)bt|1b3kaoG!YTEw=($`zirfexj{+b;WhjD zurw?`;Jx$erYXh!w-G4se?26+{`~u8<6l_1vA6B=Y~Qs1ZKKI4OWnx>fUjO!U#A#8 z<*QzVn!5c@z_Xp(%T?*nU=n>8Y#A(bYC9~W8OBtdR2n+PL?JEh3&O<`ly=f~woMyP zWrP30il#|pYa`Q}Q%b^&5p(w2Y@D4tObs=9k{i_*uQxG40}&LuEp3nlAAyNcd^hl; z+pbvy)_LCLS*BaQe%K_Edx4IJ(1nm&Rzpl`#*iymnKA}Wz#6bC%_+65h^21=JFn<= zS{w!q)ZMt>Ir;2EgMwtH#T$2egAm#b{=K~U-$zZ7sdn){Un=^*7uPhaR(*6)3w1jHaj3=j%u2Ndpm_&pA& z;3`JXc!5Ti{_@40YEyz5jzOh*u|px^{ZVfMH7N%QdngY4>%6hArM;ORK75Decv{yF z>vMwEwfVWm>(`I(9e7uGTzS?FEv*|3YOBl3>nK{6E-!YkdJm@Z6!Anv-|;J3 zTbGs5mm?z+@>w4=ONgO4ExGtL&M*=vaD3?50m4rj$G*IRoI-D_XT$2YSsz+J#U_ zXn^II%Og5}lO*8(ohUO=Cnmumc{!Ai(8IBXbsCw7Bo&v#3ym z%?4S=BM?EOh(nB6D4FhoHf$+TblG}XeuRXR5mYsZey3^)%>vVKQ4n2|4=nijrf_b- zC`t7R+@agKbql)S@0fx3!nCkZ3MLN>f6Ji>#wcJmO!nB$u}ndFZlwGRDu6d5B#aJi zQlqrS*N6(utusczZD6E5nC}MD^R8j;f6>L?TS@b-xP%2fU99In{FBM%*jv#_DvNE( zw8E^BO5aCQw>7Ds;@EgR&b<@=_ZwR2ty%GXa+`I0FY3UEtovkkl7583|K``PO9H6b zMcY9hO_57I`Qh5LlEX{8VimMMb8#woz$$lI_j$!L@5fVdX{@$!mQ&1v_3&H?J2=yU zq_o&TyW3~4^3O`Z`cw2wq-?EDQ=b1RapZ?q#piI;npB))=_jc*YV;6B4UkD@qVF(D zVpB7dpd2?*`oUN0-2>(0Y~3)RAwv`A8NTq~4I3dV=WA~U6jQ$Ncj zD`X{$9G(<3Ul1sSKnuQlBvN2a89{N9uUH6dzm-g5D%XH0Bdz)7pPLZTHi&eu5A zT*0=A*0(?5`8pl`spdq;LCt9?@863BnEDp!oivNx*l?tA?_fF;H&AmVwo>UavfeZDLVKkK@C zCvktPzbPih&(9-5COs2=_6Yk_9{0A(05A^DiikXWnhukc+aT`)1#g^q;X(Y-&>;0F z=rf>IW^Mhh_q(}}9|r$v=-aFAc=A5@;;Q#fE{F<``W|^QxFWX39UvMaV1E;p`->Ps zm?K9O6JeG)K6H7#dky$ETCHx5zSOqeW__t!?(kG44x8g?1i;4QmgDK{hAnQ>-J+>3 zw$pj(#>+cRT;QY<+X{K6)Uw0Dr9tDDNzqBIep_K49ui`{U-J$_VsFp4@7{Oz7*#Vw zvZY+*Ib1!~9N##QMJ0Fz(4q<>1=|c_b+dwSlR@Yr5H{A}gs2+}@z_uhNjrvG5RJq; z$dUnb`BLME;{wS7fOR5?s*#=HNKV{V#bfbvNKW7 z?#8-Sd!@s~@b}{G9$u4=pYxx7f9&?2etQ6_Q_JPa^FQ3I^t^4AOZQGVC*9oMcJ0BO zeEt#j$l-cE4}L8)Snf7IXj}z;$CIsd_pk3Lsc2br7>QcM-zHAh465gu38TxyjS;Y| zbBmBNr0pnpY`9OzaV?n0Gy+GaPzyQ3>23Iq$T+(GTo8r3N`kh*<|E7{*jw(u>>1!R z3jRByivIMKl|8!ght?N@Tm-1JL~z=thJpwMLqGAQ$9|`P-Bv;l-Rtsz`%x*NMp*bo zk87-JFHE4-{6Kg{Nviv?ZZq0E=5izrAndhyLPkrKa0&gJl=-Eg?;H$| zvXzj?8|6xf6e*F34T{z94?mkD-PpBnG99*nKyZ;EP)3X*Y`KT~6k@1RJ$Y6Rc0@DP z$&zict~66aLCP$v784ciH6I^=&L58s0%(vIPxy{i@nH_5G|s|q-^6zMFOWYH^WSD2 zBh~-F1t>Z9CTU*UU05Pif*yIEOg1?9*r+1-viPNmx^hhU2cOaR?66rB9$MZtSQ1`V zisD*)M~}8Zgx_4kwUE?=U&!bcvZBJ#DuL2AE})`BH~-~iC}CG(c#sHqAro(ZolIZ5 zy=9w!r7KHDoS-Gg9^@BtYxj7gi9cWZCjBKjItm!ji1!J4|9vTM1+;R@bVH9BIx!qvSK)9RmMpY%wy4`|DX@9TYJ#v>shggk(gm!Gko$Lk=i+MK1mr;Y@Iwj5H`Qfr~GN zQp=pH*9qZ^L(FQaEJU2w6wDYn1w`&<;{Dvz12$`kjL69-2xOc^s7p6qTe54v4eXVx z{CDo}Y+R`knOxIReY~K**}?sj8ZpPHCipQXqpK4D_X}BF-jwiV^Vke&o@T_)&r1oAlUlDm2H^)`3enjZHwS z1HjTgsUr=?QR+9_xzEa{U327R=6*YBvmROjWOZ@i*_($MoLL2y)bRrW$E6ZEza4#J z;~qytYGWHd{dZXJfe6aAvVh~m#JZdZ=$7YPl}_)=o&jR)&K~ z43{K}vK$T*ZNY>P)``WzhvK{l4IHGR<|NHPx=HR{5BxAm>_;Ry*o-EjsZS z8%9P#5}O>_1o$<$mFM08O|q$7PsxHtT~_XGb;3gY7uT+N)?Di(#N<0EES|n0Ld_0>Evt3|DcgC4xUcaiBjRhxjzg}&2SiE0!IJ| zEbE15mih=v6V^3}y(f_1zqR=c(8qd|uAc3FvLmsros z!$FgJ$=6!`#nshC`vuh;LA}WX7xfB~V5;v6Q%cGKTT>$9_d%YFbYYrn@@_WW7j>I! zH`{R>0eenbFj6~D;eZ=Y?d(y@gF}t$1SUOI>do%t{Swpt+)Vi zDen%77*T?$P|iBe!>5)nB1b7@&uj1>CwSdBL-IM!O)DZ_UD^X7U~9&jf|eMvT{#h_4RFQ=eL?t zl7d!E`vtqoagD&fJ(eP>D0f6@P(cbR2uB)$5o~q9kzzE&idm!cHDfyc%jkBzFHmb` z|Gx8S$CF*(XS7O@{|km)Y#8_c-@}#kZjbY?U3jTutP}kb{Zm}hbq>@*?2*XHSlZfN4=D8ei1@?*N9+RumELpvXpO&eW1ER}bm| z8aCL1Uj}@^fh}<&&HEkneV*BZA;v;C0S0<-t~AFnJy?UpE?er^YKoE26h-2MQbd$s z4#u~mf=E&aor6nK!KI_}We5YTCA^>{h)0gjNB+q{U2E8!ZJI8+q)C%HBmXd8{{MRc zO60jY3@lBfArcA_5}iYuL0}WA|4s;OesC_C??WkCHtD!7YPV z$ia!Ph~nqF*Ex@2@n^5~ta&1s;p*JtT-<6g5xvI=Fo5yR+Yalo;2{^`3rZ*E*)3Y8 zJ4_G+Yv1;?Tc2ZKWQ7Qb8Ipw3>6zfac}T+4dz{CWB`W~f;Y{qJ zfr#Lb=b7R6=J~*Wh+a+H)?YZ6auPwS7ixsvpWVcI z+%AfSv<=!d3xRUEgR*@qNp&aHI|uz*CAbZrgQtAoZ7vGgOyx8zm`--$PjHr1bn3z)}n=6`M7?D>pp~N<+ z08 zrLa&ExDZAZc=IA(kx7peuZvNK>0DutP94?{kALe_-wS!{k=3rWJ(WTV)h4xjE;;TD zJRbIL^sbgh=l0IdWV`sexMw%#hD*pvoh5?hgpI3Owl!`g#?ZJlIXk zQ@BN6Y?jlwY z=1c+v#IhhxCo|F$i5?9;6*p1sziAhP=A}kVNGL>}XWWM)K}z+6ymo<6_P*!x0l+Cm z7p(zDFW+&qzEekYou`S#b$@Zs>t}~rBgXVg(b%%XH#X{c z-4?%Jv+fw1sZBR}*a+~wi@WRcJc#B1R51?!i|DSdJr9sL!B;{ffrsx}Dz?lUxo4Lu4TDQ2NAji`VXeGE&(E=W3x zm~m(UPEzHgZW^6@Rup3|6^0xRPqd(O5jJ1Z5>f^%KZrUCp?(Xy8I06R#ZNnF#Jo>{ zDIJ(mNP~T?OK4)eU~UDzoTG%74(bivS_(NOb-n3%Ezf78Flh0duGNm~B;5EwY-leYFvuP*?scn7#pgPimTE|ErvV3P)ENX*zt2Kb~7 zz!$}SW@Cv`sKHEP9?==wr=1po;_y?JEW30!-@XLD2!-=2aVUf8`!`_gwc*wky=XLN z*P`)7vLw|aR)tVj$P{_JfI^4a93i@D<5pZb<3(-egb!?vgW{xE!p%w`N=HuO??MwOSn312*AaFD zLs{YR9!nc66{pIkxb*2~3j#S^wGts)(2Qd6v5tgHwsk2=sQGd@Q8; zyTs=8_k~t_aCH~R1h9H1rV@kkzf*z6xSk#`9*f7yWxAr|Eeikca!9-`MiJ%EL|`tx zo6E!(9tVY@v*<#%W~3Oqq3^aW;KCS!LA!`NEfuN8>U6eQD>eMfwoSnBvYu!9d|mG%EFy3t3H?}U|j$0t=mr$yYniyHH*q?dz9hlPlhq*Y_ro3 zkAbl0<$jL$-W4;BtcKk8L3cfGEXJ>6_s~(8e(S=qK;DOMX7(=NiM`O$xu}2!_a`7R z=h@w~+E6wD&b&IH_rISruG9CKxhO7Q0*dppGBS>ugtzRik}X3N)v`ZJjVF~rvzlf= z3Ck&jF$~NT2Ub>Axp?E-4H!`Apx8#OawPa5ehHIYb2zZlHf`*jpmGYP#9@UFiX7l; z+-?`>uGC=?Z9Ax(`9 z>3H43>iN~`wPjBELfn2*ZTw>A=iibroe23_gl|VdD?iaY)y^8%JQMngn@oMw%Q&v3 z5nTu;A(O>MW|?E|fk8UR1!gXVH7nRk(}K-oz+(+Da!eX~8n$-c0Od`3jKF0z+9u?3^R59wdQefr76e z4nYHqYD!E&=mWix1scH?a?yh5tP@)j(U1@mMAX=ss1$epQC1N`d55e}+0vLmvQP!v`4CN^A=LP zvt6kfS@v)L89G^#4bcQEW>7_q)HTx?6KT=tKBe+jW_h|MJ}TuyS(X ze?Hf``C2PreY`Y-SNC4Ln9XNEfjol|{u*9Ur&;}r+-qrI1;c;gxUFABg zdg;nW#F^Q7lO(Ae8RGXL)9%|U9hpi>lk7(Akat0X$k2^B#rNxItT9=AgMwDjlt#h0&e~qj|)eI1H;E*hHW?9%)vJEv$MNi+mEG+m)sS) z6pg$tpjQLdlH0OrqObQnM8-|;u`f+c9UUBW7xQMyRXSn<03 zgY0S1yNR`D*31IULluz=01Q2r8Z{fF!F)IYrn5k@gmD43!6 zNO8Iaux2yVj|bb7PV1BQxq`G*#g~%Q+9)`j^4O>pIu>vqjBRx>ljHSy!7$FJ1vkL4t3RpusOt3(!)knIwWZ1K_MS+TPX#e3j6I% z1_zrOJ5~5&Fe|OZASi+rQywAc`#oKxJLEm(SOGp0npcokc|!~oL1Lgz;CE=szkUI{ z#HCg&5>%WNdJxznPLvkhxS)3+4PPoP{iG2EkN*$jo3sS2_`0DN$qk9?#XUPbHl}YY z{F3)J9aH!S)vj^P5*9;qL;)`LL1gU+V}EE=XwGIK`U^!%Y)NXN(QHQfFw7TIaR^$(S|=Gh(%Q${ z5}V}9#UzeJW4qm%o3AgUdntX;Ea$>POlM@GUZ1i+c;>G`=izb;FYQ~^~> zl}4xY;_f{!?0U&2sSd&@pR*}Px#GY5`+pLlbuORFYpos2_~i6`_x%JATb&jVwwm$W z+-&BuHG?Y#`g)2v(~3K}LNL(VH!(k-Q+X62q&V&fORL>36$^udgSE!IP18_m9R`h7 z6A?@KqR9nD1qcKPtya^ytdJ|VTJ7#Y=Zhr(H9b2Q+w}DCnY%yx+4;HIiHY%bYu1Ii zs8lY^&(B`8e(jZ)Z}JG2Bgc+*;!Z9XwX#mT(|&dT{>v}j_=Vs9!&Pfmv9-&VEdA6c zKDD^NfBQ2}uUs*7wB0Nh%Aq#%wHgzqk}-KjtaBuY5{3b?bI3Z-6lfQxtjK^;hybh% zi7*1AA?GqL5kpPZTINh^4FH7ToYh)+pJA3I#e5z};<%NILO|A9S&JY-ge;DbMH~p4 zKr?6cTCG1BsFX^rIAZ`3VPMvxEE7=%8HJeF1#JRg7EYB&u~KGcQVKGjYs`{C6KI10 z5jLB369hpJ7;O+Sb2f=nV~mLcW^qms6^4q*W!8d0XRReR7ywvAayBtx=oRHzn!SFO zfAj_qN=y z<;E>rcD}IlnWvs=wws-1^J8~?xRWLSbkA4*<6Ga_`Ql3tZ{50N$>Nc7=fHsp12U?o ztNfqe`%hr*?dcL`M5Rf!U2H9isL9#(nw1w-D~kbgbMuKNLK206W!s5kBBfC?rh@1M zLajmAq8QR33>JLCjF3cu2m>&IvdpN-Xl0Di#$0#ZH5Xm9=HRg-`}Q87PpgfaHlfn% zFWRtb<(iqt7lk{{NUd?{K@W>e|ma z*IIk;vroJI>Rzi$mfYlyalt0WU@$lsLnxt!5P}T^Fyy5}9?7GI1VcjTCNU5?*tmc@ z#x^e4vcX6$k}S!R)owZWp1Sv5YtH%p*hjplKlOc*zN35g+H;LL#&10LuUG%)si$r^ z^RzSm{og;^nm_#K@BFh@T>7%DTYvY_kA5m-xgjcifndp4#d5R)WH6vW0E&uGF2z*D z5U~aYSBn!CFA@?768Z?6m^y=&e=+AN&C6SzzhyG`t1{Y&N=fqL?1}r@8K?M|}AQCJg83dt%Jy|3}!U55s zQ&eAbG$Em_6H>Zw20d8WzK=I#*hWT5@u)d=;X^f)JTS+Vkxoc(6(X- zNrq_)FyxsD3?T(oRI~_Q81bktV7R|5_t~OHL)xX%q9Q6vL=0S}3QC))Dif6z7)G%q zDJp{~AWP|mK~RCCmUk&{YN#QEYPFiCX?t$ITCEo$^ah17kY?lIC$vbjvY_ONldYgl%}R8Ls3+!mCG-` zeBZu(3x|(n-fI+f2e~t*IWihqvQfk=QIujo^PER<5=Dvkq6Q-ug}hkqb*t5?K~h#h zi7SaOf`Zno^=h?Ruh$#3X0tJ}xUl%xV~?#{yKba85;*vxc<7;rHg7)mi6@_|H|j<3 zAr#$SkDQI!R;slkFDzO#NPy0fL2{8rLJXv;J`^HA)+SMGtrbv%ROJ59p#v;IM69#3 zv#SgBt$qQ7D#01k>9(Ic@LVmeSW9_P%*@O@|Ln8!Jb(I$CwD#dbhqCZ_K}MX8fNc< zAQ?icRAQfFTCHz6`Q(X-@#g4gqdxk}U*7xRV_T2R9sbrguU)lfWi72d`Q($wZQmXl zy6MKBjyCJBdG)J;=dD{GNh144e{}iUwQJLAH7|+>e)ZtZH{W#0B`>YS?)G2)a(czo z{=IuFgw30e9UE&NJg_$l1sb5(Dv7F==tWjwE&znZ88T=A4Jd+*BJkch10g64r)wo6 zAZP#-RTz+5Y(+G%SCznQtuY3TwLs9%`V(UlaqJXDm^lO>Kno%qMUim`1mpk>1>v!Y z(f**{tk*&jj3E#Xr5)6PhyVi_HP#BKhJc1b@G2ZQxX6eE_Cg53dt;2MiugPaAOR3V zQB*2PG3aOgZrmJ+jPdMM3(vkn@$hK{62edv);J@|5EP_5JCV6uUJH991Zxx-SdFoQ z5F`i(LNEkgH3XKxBEkE5t-5w?x?%nLhadgT%424W!ryk=EweMz&R8ULMAjM!p8LJS2M^Xq8mpTl z7o2zAamOE9t2g#OyYJPndgb=R9@w*I@771Ru3o!(dUASvY%I&O(PndgVQ%Zz zcJQ9kwD4Y-t+9eSHr705vU$Qx^Q^P}!xF>@ciwqR(Q9Av_SXZzs+XSko5x@N&2Rm1 zY{jIpcIZJI*2I7!kdk5m1wc|M!whU<69V_RpTQuuh77cpm(m(5(4g1%?8%@-5>-{T zhCB-^t1_0<9RxrW0|?3k52_-X6$J`2Qc`YMLI{Od6;>>deFJ9b1Xe&&6%{}e84~k* zw-6BpFOP5Av3kwS%!(QDia~=f78R%x4H(G4!TEV5;J`=bj;vd|>ii4OTU>bVoYPPF z!^DAt+m3ErWNnK2$x?{AS&alqQIfdEue%iY2O_EVx_#0Lnn$)i_L6f? z{NM+#eBImL)@j4eXTv>@9{k$>+y(&P9Mu{#BkAJ&Q&u&y)-$t65yYy3LSQZlj8PnO z@C0C8B)}vjfkBl>4S3K;NB zRa-hoSVaM->^dvAm*rzn;_b@H#PXzPAcKGyRBg#`K~)d~#PIuHN@U7KNT~{z9v{%s z7$bnM05)%LiFMa;}zERA`XpSzeGOwCF1hBX zJ{029T5ZtJ(zIGh(!n5KSX}J)`$ge<-JY{9ilWxiQu$MO=)ng!9lN19(%iXckI#!} zdTP1THr6I_!iA5mHE}GWD(r)Ax0f2VS`;U~@cnE62AgRu%LaqNU}9ndjagn^Oe@LE zirK}*r6+eh^T~hxa;=gIL9V#Cv>3+@LGwH-dF8P&0J3`3%7wYP2OhY;-|yv}J`q7s zvdTUuL#Qk&UKI+7;v_G!`MJ6KAAHbSw|VpNl{8gV0R8b#e^Rz3kBv5O`Pq%lk>>35 z^sTqt^4Oz~cG~T^xg(eU;VaL4-dRhnR^)6FMQc{iUVr^{J9j=+t5pX5eq!wpzW?2{ z;;c2@c1MLPm89T8K_vu(6h*Gc3lSe%C*p1S`y%Q?8TX8>Q4V>L$1YM*v}gbe&%rAh z^1dKrtg*(BD09##vZ4}#=TPL{$FVb!>2|tt66blI6@xfQ2*E3}hAhhvVbJee=T$Y1 z;^~=b?~6vgx!h?RYfzO#5YHq4sF87{j~t0Ykpro<)bICP5ml?zAh`;sNfbQic~+?; zdF~Bj$qJLeKFcKpV9{K&Uf&BRapL=#jZLkR&UgDFA+5$NURA7#VplPUM3{#_B6%?Y zKo>;>Ko-dw^-|=yaZzMV5rX#~t@GXsurZd7f+YonhqO50@`3|HB42r6KgnS0vS>iG&P1vl zJd=$CR8_OWw>w=ICjz8oHS0w&Rconpt|S?%DjzlBTIaf1cJ-O8-@W?aI-f`Fc zqm6n|4CW3mMx>wl+%<~ADtF&~f9w)v0Ha!NtPBw#C@6xeqLOMT(W3^9jVypz{98KnO+fAgUOFqA{xKgCMdq zL<9^32*!9Hjvnj^B`FzERLIz}z{r3Cf+43UaT2pHKK_Z%EG{jKjWmjWs8`c=fAF67 zej*P`_uhNoa;ts+BahCmS|vUVvVP{X>B-5(gZnD6ivdnK;kc!R!!uLk9Qvz|S+Uq^ z9a&uJ_q&lby?$YBys*$RWPkj_AN9K3w315TIF8AbTPk56m{nDcG0s?35EKD0WXi;d zMd08A=TnoTK1=2et(ln}9Lk>B`HTg6_3PgDKR>?vhM(PiXpZw_4Q*VPHYT%vdrd+! z(ek0Cr-a22<}5@c5;E^m#UdF)QEWXAeC`ROEcar>BB6+L21p5wf)bSOH%s6NfHCd& z+970l*7n6fArez3V=K-oL4aT*n|XEwplHYx!l0r-A^-_N%eAb4XI}LE? z3BZz5A{KC@%z~>01#RvVL=2!HH76NMpO`x&>$!XJ44895Xqncw18Z0Udja_ z0EA!-DUpyO1E~TkvH}Vr2s42c>=ls+d|rsMil8%qU>Vc`S|9}#98!Z+6#$6n_lqF_ zQYb@jC@S{?qyQ?RipE$2AY@&$*;riaj*U;XTF)>`WMc&d4$SOBh$5#fmQ4A%3NN5w zBWoRsqJSl1%f0Vl(2wId58eP((^OcBJa^6r+U3QTs!9+*E@|X!0D@X;iX!i1IYPJ7 z?H7eF?VQG7*6)&ul(A}T`3^&8IY^e}1QJ> zk4#QYu3Ejy7<1ma=kD46?4aF!>C0Zae#6F-PC6M7@3`|9X1G3iCXSM{QnA)1QPcrbtyR(_?RWceHQIl;)9W4pB+q%h zS<5o-y&oT+IOXJ%cI@00$F9f*oz7Cf-X+Y7#;4-nuxlw(uUDabUb? z9=KqhoSc4k?;au~Yx6-iHqtz1#dN=)c`ouCgZHh4MI;i2o$XyJVvW1`#+z@v>1JaL ziW*BQk|arQ&=H@j=ZwUXX)i71ML~w9C&$Ae?{(YNw8@2U_xht_BSh$&1BbrAEX&IG zqA|3z)KZZ~tsaC62}VpMuFTKRS!e6@2Iob;*GuA9m=~9p0ijW^`y%fZxwDRpQB`NG zSAXR2p=!1I`n$7;8U)}-w{l51x zB92dtFSS}hi%x%OdSYs!)k2kSzn5Y%==T*ANc;W1F_sWir6@#ou+-@wK($hdTvV&o z2EE>(+wbOCquJoVD<-G7!4h6wZX^K)}^ zKfmc`dGOF){=pBvf7z=pzv!ZiCMPF*z24TXTkpE_PGij{KmFjiGE%KppML78 zW~1@s(@%OIs+AgQuE2Rek0Zw%L?AGCJDof$EOikfNk^=+NYLr^*n2V%gp(v;filcu zg80A!w0gs)-OuhD8=HLhmG4&O?|=V0d-v{|Xf_Z@OO0C)>1ZV|tB9U<+G(ot{qKJl z0X}%uRd?KRXQ$i!hrj>3*<(h&dF>CkKDzbq|K@Mzj~w~J)t^H&&JrRPMP9Gh0_gw# z#OHfmzyG=2A?u4UvKSfM*v57uUgo8&un!VIDT*u$3o{BEGAc;cI6_7yw4f@8 zuIyA7NGh=}@`61WKt)7SP=m;#3J?e!Xc>NmG6#yR!wCz{d)}G#YWgSdeCuaF_r*JJ zzcbIWmtOLcpI-OlH@@i&o7S%Q;@5t7-Oq2XC)LPCy-t7i+ErPJ_p#nvS=pYon2n9F= z<%)}pVo)@tOi*%)L5v~-ct8kZBZ_Sl%s@pVB$nZ;90U+c-clJ)12iNh-(~nh2L!M% zeB%QE3$qAVAjH68kVF{}5z1Al;Pr-2vJy>kc5LF8svEhAmyxt#4z-NXizD8 zcY%;V1BY_TlTt6?VfkulXwe~bS<#Re@5q4&suGGI89`M+Bq&83#Zs!FGFxOwgv!q& z5|E4xmtD&2iOLue4?|dhqGc2tfq|$5Kp>zI^^9e#+_c-B-Fu&FEq6QZHaUtaNfcKm zlS$D+I4mr*5Gj+wbMDX>L@+3TEUbkpU@3hof+LHBEE?GeK#`Ehmfs%~A#0I9VVv2GCHzq#cZpx{QUFI&ic8izVQ4Dwr$(CV#UmX z1BXKJtQtiT5~zqVmRSs$YFb@vEtV5u6h|C5U@+ELW6NZkFMO66@3Yad#-X{x!Wbus zuq2T)L>N=I(>Zp-`n9XqjE{}~?(yF~{@7#7OG|MSkJPFH5~0idpjNFXHfC~xa}J6K zT!b7r2(yrA9!IV*Ho9j0x&wO;plH80NTN8cCXCP@45~?Gi1%>l#5m`WD1>0h0BG<5 zK#jEk5GSS(<|V!%bPy+r0Ti1bAxuV=JcDe&B=ey!DoQ zuDk9hANk0Kr=~|g^ufQp=p`?|>H}B&>u0}k+Z}g&`d>cw>jxjc?Y27wiizkcqc|MXX+SA5{SbIyGI8(#N` zPkwIaGml^S&UYVs-1<*_`szU^`-?07^nr(e`^#V6{f)1E;fxd4UiSJcS5C}a_>yyP zz5SQFcI^82mp-?+*!svvKRGcz`A`4!x8M5qkFWdb4XR)x8#$*&3JwOqhhR)ZAf(75 zkok$TV0*(8YqOK;FmDzS5JZfWV9 zb1r!2yRJNV=t!^Iotv9)&CkE>t$%Xuwcpsi`{~KaNnjBHYpCELO3KPUeBeFrn_rqw zD(-_HyeiL&dcFDN&L=+b-uE3oc=+CX@4f6*m!5m}*`0Q0*E73V*jR_4KI9hNa;w!F z3_kS9zdvEc$iutl_U_!9)*9FT_ccp%2d@9&wT=J){`4>Y?tzCM1B1p;Kqzsv7J-Xk z2!*f!At*h5phf`{!7y`TqO8|%5AryU7`2i#YL%qZ?;E8eD-0r#R;p=vsRbW$0STH! zF(I;uB}5u_8bA;NG=w^2?`ZHI06|cKki)WKi_5qtpi=@>1|=|xfS?>0t@S>PPK;jt zi4R5q0C4=~O?TXWd!tc(`=#d|Gc|d^i7Nr%FW&oxTkraX_dbrI`MLRrAA7u7X?*u5 zH$8iB`Qb+%ZY{OaO1f_C`nkEojb@_~CjzJ{jYjQz-}_!s>@I*+wK-& z&=?uX2Kk1SQ=3>*5_^C-u~xreDP(kylixA zJkNR1>&?$E{ra)r-FDv-_if!@NylnwqDF*l&{8cTP!!8XEdrV{ye(`&x$FwkVL1%J zaLPbbhsX|4)Bu$xQ4t|)RKyS>m=aSdfTr}05Gqg%6jWSU%mI!N%R&_nWs=-ja-w3% z0YDIO)|J+5TXrG=pn@R#AW0I3f<+JoDv@&zY-}A-S;i;|whXhC(h8$0>QPK3l)QEo zDTN~`V`+qXRP(cBRfLX`yH!NW528ARGL(ODIe-x9u%BK5fXcpK)T8WgP!&~0QdE*q z?)ykezmI^jC`$RS7-K>R)wFuwuO8UGedq3d&!K_{OiYf8kg!xMm83dSsl?06?L!BT zfHe#pA(66YIeIrjHIa)dQ5+jGKKLk#Lhy(~ir?=SWLW;EDzdN$@DN(91&7!=&m2XO zP|$$Js1LqSj=-=ef|9eW5{e*MW-Cq&5E^4l?(@Z^kdR$oUb^wd8}7UR-VlJ9jlugL zy#Jp2?u+9XQG4xfl2*U|wQqDgU4gLW_>&s7+QQ;OTB|tcDoHZ*RQm!^j5C8QBcNt; zq}S^fdBMWW+~+|pt$HpN+U+DsM5Wj5Wks>Dv>1FSvVlSUeY*+~)|+W-dEwe`{&#Ds zwPVNA0-UCmUZ*1C4c$XA9jwu@P&W-J{lRx?4_uYKg zqyOu#KXmD(7jE3J;ij8zT(xrgJ3aF^?|sYE+tEzHtQLrW*kee-L6dgFB)*Ui4*#Mc}?JXaLmzrEtk7hZ7w$3O8eD%qJE zXU{nOwDoJ(MF1zBv~Dn1zWfyzrT{BfO--*DJ>%G^Pkid{-|=TxTy){{HqMMc`r=Ct z9^CPc*S>7y`V9~M>KCV+ur>y$R;#C@08cR=B;Uhn@?DI))}Y9&K)}u zz5o4h`1x&j0f{IenaEkm3LkO-B~h|CY}f-tRN+8mkPuZ^(GrybB2-jB5dl;*SfZbX zccJq60s&P*Yth6>JU2hLbMI~ybjFO0O>kgg&Idgp=ybXVpMCCk+qW5md7di(7^qaz zc4rw7R5i;pF_7gMAefkJ?2y5G@0@ieGO00!L^$}+&$CKewWY%XPyqXbfi=Jv)mcuSAKUfI*`K3f(+g zzkcJY)yMqgrl0KC@$~!N^S)ZG@vU!v^U&OpiK#lw@fW}Rr59azPU6g`|KkhHMWs?f zWk5=jm{f&j!`cnUtQc7aShsHSxDAs8aLdnT_C53Dj%S|Puwk7d0@}bz#)QCJ(rOV( zNdN>Hxhy#`fO51Ko>ihGDw}!@nW8Afpb1$_772ZpM=n+XL=;dkh#nCr!0?6>MG@$* zvxqqu1SEq*rBbG%tisAfWSogn3t#|3H2VLUBN2yZs+L?IA|f&ti$U@6tN&}?p1qSZ zt9I?&Q>)hdgZzdEp1kS08+Y&Cve;@pwR<-x#FePX^ZC}|55D&UYhr8cb=UtiNt3Cm z=|hJP{(9>p&e^z<^ah!+u9~LCl2>*ZSK_qbz`$ppcW$#ex_i$vAOG0LK6KRww?6Xd zPp<#*t1o}`@h2Sr&!70%nWvxmidSCx^piWt(5_v(9(nZP*j0d1&&g62Mg$J~T+u|r zAukHk^__#&B#e$lMeFHkq}gbuZhW?EoB@QKB_`uVMJ0;kP~@musa1RJ_ELN4tmmEC z8w_^sd_tw(Y^Kg&uiGjHt&!2mB#Qg}L6DePJ1PKyfUFEUb33kl`>Wplr*A3puy^17 z+itsSW_Bia?)hh)c;fM=p8nv@&wus%IgcVaR#F0DQBfuZA_xS+o#kG2Y{ZZNBd7|h zDeu$9ih>$2hyZ~ls6v`nL*W;fI{*|JE4c?$M^-p+X&EGRXn+f}B%+ax2*^ut#u6C; zMuOZ20JL#(q_ynGfDEM-Q8C6FG$rMS6&wMgGIIz%3WQ*-v*I}fVTL02%%WP7n#HP; zDHS>_(MXD9Skw%|xQg`uzH_CU&Z|UZLBSxER3%lRAt_OYtcB8f1v2yw593S*bl5vp z2D%ZEltq-vJ)5d3s0PKdaK}gqutULeTo(`pLbOE2x+qTfADRy=%pr1dJ}A;^)x@#q z95Zmv9XvcY-�s^KoaLeO9#+8B|NA@P&fu^#;G&_T-*t_dDmn04n<+1`U+~a9eJ| zu&kgJ4WeMtltctXL4ZnR6^0xe03ZVZ;H-7%R3y(bKodEmH04jwqr@Ae|=fW>FI3aSc7XDrdg_B-8!3z@H`Qx;89t1IwcEv<>JV|F(%uY?DQxSaV zs&_o}z^{&7f6QdVoPGB5*RGiafDNl>H*Q*c(w1Y-qfIy5aNMd@Qx4$NlQ*qcF=Y*o zJ9zbLUd~0K0B4?d@-3^@SOZOfGtW3<{kjH+MAjjJcdngsCYSG?uU zyY8BunH7LnTzbj;To(XVubN%EakWj<0i1m57E}U&6*Hr&)~<_8i~y&ca=JPDJ1;8*}QZCsN$*Y7OKiso2z1eg^dGG^`S)jkwpqmgE#SsMp{YD~w>&LF4< zU|wvbX#ucq?dA{*P( z`htQ6AG8z{35n2v!tdXXWj?56Bb0$zL>$IR$S7#J^vOpd}!>?z-!5y7_0-B+awISTr@i|Z6aH6=yW<+o{1>vqH|7lcpp>M*g1o4-+||pFsW3C z%APfh<0LlpdT?pE zKgfFRZnxKIk+rpYeao?%vO#w6xkC%BMPq5xrcEz=;RUzce(UaC&t!QXCGq6U^ua@O zrYJ~>oQo4{&~Txxb{9~$KDza*U-`Y=nu|%{#hKt zZMWYxzp$`kdMb(ILh+)PT>8YpVtYR<6b0K@lo&&7181ssX6YzSwu8P3lmD^Sw#Z*`Nf4}kKM3g{kk9i;D<%gt5lLLr#x?Rq8_5w3} zw~$L1204d{;PcKOU2@*L-tqQl4<5MV=eK|BJKt$E#s=MNwAmORtDkVI!s=^{rtJXXRQ2``FWQU73QcTHvUtYK&dCc3r#O&htE}Bw1E0FZWE;N|Ge4#FpH0rxT}X z+^sb0b&J$l?xbl{ZH}&4vwCW3g_1evoU{Mo!~eVJb)rVyAcUeIYb-h-VrEjZCPF}! zAf>-hn3MonK?If57)1eP&`60v(V}`xl6YcbqP4hq;P4SEF#sDwHi|^WCD+evZ3_#FaT3?+>6SHXFMQF9_Uzg7 zm9Knte0)5Kq7^HqKsC=ZCF~9QwQ5@AzTeMAMw-q=-ChqYxg_cjde&HHqkNG05TZCL zJ4Z@0)a>jrt7cc7dFE-)?%%uAS~3dD%gYB39*!&+V`{bP^u&0PXTU5$(n{3pbwifd zV*fYqdCiIuJ-pC<;5X0ScK426Q603GjETw)IWVrw(3ZAD1+WIKAz@(_M+BgrgC$2~ zj%M7|5U~iL5SDc)N<<>;z1HfDpjrS-PEO6vjw(Q&hYcIolxpU2C#(q!3Q%oSS01x= zsnuzYH`cG)nB@fkEHC#?KY2?%tusKiks59)KpZ72W>+pOE>F&m&rGlCwL<|QD$RP` z00w|s(yYv+43Ou3-G;TskN}K~jgL)?0YI8mCdX&`gCZohl2#&P0N}_%f7Pm0k+T3W z(x`VjOAL@y+{#s}vO$2FTYv0E6Gx>^I6B%a+2_^NO^mGr0Pn-hidj%mfaw+EX|)Cb zNu@G1IT=(1pq|zTd7A+iTJ2RUXByRp0E{%Ml_U{>G)>oU*igP0Hm%z%5&$4}Q7wsj z{T{=FADGdx2>=)jidC!Dbo)iE79TS^lcrSwaL#U6zYYNzV0y)5YrZ1@4A5@(SRwbq z8nO@!#vCN5_#j3}q%^$+L!_eC8bFW|!U|Bzy``kWzy`{du~9h+wk|jKioi#kP6QBa zYF!9kjiQKU9(0z^x$M#n8`s|d!2J(DbWf#PU%7hqJKp}br=Q$*@W8?G@$rBB#}5wr zx-hq}-04=U)oPkH8zal@HUwF{YIby_`OMB;N}#}p4j-{5swAl>8*+$bEfqc!7DO7f z2h59Gww$nQ_cQHoFKRYawc?^M=)|L*p( zz#)#~va1Zu8T5-mF9S54e1S_x_?@uh-IvoqG=6dEalFjS2vscILS|o_J!Z_4M2R z`22NiS4_{WK6qfRvosG9qO@`TIcINw;_1bu*2u`nd*A!sN}P&kGH5Jy2mSV7|JDEc zZevWfS|KUv~baGM65H*Bg$Xa8xyhQ!Z;ThV+=(}QX-eF zv4Po|m^t|1jj>VWJO=`kM3oSVZk7cO$8Oj(Iej8P=b^2SKJ>_rA71zKM!j0vRg5i< z3qV9$Zb3>NK43sWP_am=T6$(n95f9%)~KKckX1p^B65kIM-UXFM2bixq5?ud1}LC{ zDj^C6)bduNG%STyRaH>{RA5yc);gCwVL}$h5|JcAL;x6kp+KTKHZl3gquc)LTi@$- zdqC9h4G@SG@}BSY`b$V@QmNFct7eW_F+O=@ZvNSy-xBhS5CJraqiQ8R=bUrTdBM4Y z8l;fCKm-d2K|n=O6f~%M87Q!`4xI_XgOWi5DrgjujHs|89fg()fLDN!c@5&Hrl)N+ zU7TN3E{(=MGOjV&?6&(eGc#+}tf^L0W6a@&BYB>UHAlS&2gu!$>*BKY83(jR0&CHKCywA5{Ps*QS{ z7o@}mhpb<#*A^D%+nu(vuG?+13QKr)&)(Im*YpQ@;lsLhYc1J3Z@sAqDmTORY{LtqXwXB5>w&j{sisLFN^J zOcci!1pbSkR?-MCMF3^B z#w{%`t(zSuG`(&o0F>O}URRqV5XH*g1HfP~uxJfg1ZdQ2-A=3A!~sI5ovofCD_$AU6oMMC$a}!rA9Tw?;}Y#D zpa??31ehc#Swc}&5R#*QLNLY*nbtf6_amVQmrgb%AOQp;q6Dl8prp(}#CuI$wEZ`a z{raK1^Sl7zq|vK`*T&Bq|_*xj*RFN5^X8<7-#1Ym7F=N1LPL z6Vp*NJvF`Ui6_U##?Lt8wCNQqRZoEOsh(f#DLqq~-w-(=e@uh$9u2)z9 zhVxPY1eiav@X)XCec2@!u9|29ocx=|cl_+u+pINQcDAWuPyiuDL@Xtrz(I!y^v)&8yf+uin@x8;<(%Gl8sb3s2FPr zkOMFEm#np9jU@{J3@FTjeR+*HrQ1?bfDwkxO+=s|fCK={630oSS)I>(oLEP;5LHS# z0KHDH%d+hAy?d4xT8kIG_(kj1uldxcKD&S4zG}U(W7n?do%K8fdS=(|cDt8Gm8YI~ za>vsl@#6`)#-E-1$UgY~ERd`e>0kk2s$#1K@&IeP#9l%>VGAIf#1@Ekl|@ zT!m&6P+`yo5J20EQ-F{#;I4l|1bNC3+dRZ%?o?>J-d5(x#etS|A7O8Y%no8v3_O^Sq#cf4WI;3 zk0Q*@kx^0xfdB-gNQmp!YY?=c#~+t0_2cckmzKIAgy7-`0hF-(DTqpG-*6^kWkH7$ zW@qa!yZD832c8;fjuAyAtRw`6a_LVEB5R3&%JzoR{wanmfe|e;%peksF(P8D0Z;~Z zkrUCP@Twr_yMquR#g5Xnf<}9ty-8X->-4kEI{kuQ-t*{uYta`l$Ondu0YyL#Z1E^H zVQ5=XKr&idZvj*60w4ec7bGWE?+Y*(vcZA<`|Gt4uUv05gk>-or~nzw^SsyZ z_Iv$TyyE4}MuQa?@Sz7EDzYr9#K#|he63cSnW6S_x8LuD5bD+X*=L_quh$IOu!N%Z@jWMqfwc9@7#XxIcM*^*89U53I&U3eiVb^9;waj|1-c3gS+`1lAgC@=WhSHH9K z;YXciql`E!%zoep*#NM`y*d@VWy=OYk|;rsv>$}XOHU4qqtv0NkcE**sU_8IuOIii z{gf;Oh&nYyB4T==CUPPm7Mu(HaLBJzDkY^A0R(}c&Ey?Gsgmnkm$0<}v2nQcxbl*1 z7a;I;;CTRGtz~A%q5$%_T&LX@fFwx>R3@7d00&$eEO-ExU9ON#^>NNJpa?*i%OEIc z82|{E99hDW&*#yh2C#9=762gdJm(xP!H1L>0RW{G5ygoCfF$XsQTc>9amE9ZbE?2} zm1?bZju9Zt_`>N7A4#F_dlsPG>1ag+V2!bsqc}oLX3KmN8~FBeZA|^U3>SvRH+Q6lqky}0;EW*G}bRHtd^(= zX*CjwQi_xlBoUYXiqlL!NlFYwtq8Dx(_61yv3x8S2JK#CfcES?u&>`%N*z47|Lb4> z%J9%|sgN~}=d0Dt>((BdoJ;`onOwWud2aW!ole{H(6O;DactU2B#zVXY+`H_M}80h z$=Z#p7pn6|jvU!>_0?meqo+@w39}hOY4ivkfwSt6YA1?_T$xYJ6zZu!a2SF9Y5 zB6IZEYt|*qti6;f4v=!diO%g=nGje+rP)b^;8+p)VIao#`u&2+g}DHf5_W|`Aq?x* zF%c6W3o6vg^NcZw5GS$LUXaP8)&iw8k(by+5Uh2I$oD-2u+FAu6jDox-*fp$OsCVN z(#bj!5ODfjgNV~w^^*8KAN=5{6AQj(&kI(sS-G%KecuN^H9J55^SggOeRif^uW#LY z(Zv^Ud+@;rcR%+`F3im=ER2kfTye$g4j*{U_x(?O;*(E2@x%)+?78))KmMD~eYU>1 zz~UIdiX&14N+kWWSWo9Y&+A9s(PbmGTJ^SDZ>bCoZQZ=pu^lWGmG3|L=+1Y&>)qok zS4>VGi%s&v-eeLAwWF zJC-y3emV|th)OANmPI_zuP@fEvz>mo)oD9N*?h?+PK4UssFe4Lxt#5p)04BC2A7{X zHNEGBmlUbx%f^cX*)R+(yM@{!h$T&&fKuqhIwDVL5a*2bw6^E~34jqLNenY+aGqBh z9W2k(;nm5bifBo_lMcTC9Dpzrq0*#?SV-6rSd@OVQFBJn3zb&ZS;qk42(@T}6h)T; zbMagQ2w0&`3qGWkV-9{gI9x7UYul~v$WTQqv1dt>V6XuIK1CYz*>dkuFLfY-CEw(DTVHNm|W}N_7I8G947y)9F zoI9cggO$pW*G`UHvL3V_^&2&I?HHx+x6I;ot_CZ zezn>htqj%{Tb+K70p@CnbP-0OS3_uFs#ZLO%+?>lBdC}eZSB-Yt? zzjyfH;UiHLWtURns7NDQ<@*Q#tOx!1HpZAfy)N=Q~ldanpGq;`?4= zjWITx&3*PWpS31obcI6ET01l}bmYj9ojV`B>9>F9J@0zgPjCAv2*lQAv)PY*^y7c~ zzrRqc)kj8$w_mgt0HPjfh4%F-5xi`H2niVU@L?D;ToSZyy<6GV`F}j=- z3b~V~&iwRexBueK``evXKklOVu2WkxULGAC-2KdRd!E(DCnx9Y)v>V&=NzH}O6AQ2 zS_=z{h;x`GYXI3nDtKacK6)s~N;I8iTU%YXMuQZ0*Wyy3XmKqCihFT)cXusLad(On zJW!m6;x5Gt6bbHbfwSKaCqE!pcDAiG=RL<*uwMx31tUy1?S@ex*n%~%A`v79Mi`@a zkwYyNa?-w@I*sd=zx`*({3%0;0y%X0utNC*B7x~X&P86L8cy^aYIomUgqUR%Z9iT> zx*$gXbinqTp%~vD{o^aP6A&|B=!>ckyrl|$*=#fLKTW)nxSZMA5r3^We%ULI+PppU zuGQ^+`cpN}xJADCl%ZawS);wbPb7AC`QyIhG}GvBryH~yybu2MGB^I?z35c`dq3NI ze8XyC%>pVLaC3IUM&)hk8U7EduFE#38~A*V-65H;-Ugl!Dhncga5u*pzLXb^1yAnu znvcbKE%DRLd8m7zn2%VU(MQR$2F`vN2LeyO^<}ImT`2}B5E?IX&yrI7EhI1_ zx75v+TD4Mfjgpnje?C{~=>C^j3sI<%CX$lXb&H6_QS-eJS0NJ`__Y3=78IM68IVPT z17e{!+Wy=C(#!BrE(viP3{7r?(v`C2HzPvnG%C1B-vILPf>h5rt8_feM=E~ zR8IJmxxSRSk~x%EP}xc%!F-B(J}%Cn+?W;)yyTxST8EhEkO9;XTE*vkYWB%u98Lr@ zH6a1FM91oI2oW#54idax6Mp_UVjL$PsL34nQUu&m$HC4%F`a(xD=pN@H(}Y)je=s> zFN-K|d$Ftwny^5?R%2x&0?=GRfOAMzf(A({->*|wMI`@_ZK`&K`<1`&6&8++4ZF$k zf4}jl=;Yxmb_3sU)O+_-!ydFlUU$)A#MfbVuhE;GmouvqGk_{!wI88RInUp7#obe% zlz%5_vj1E#X3>#frzLa)qd#K!Ui_nnif9~a?R6gHu~g^P85c%6JxzpWzgYJ?HMw~k z*t>MhAXk#!^Y7)lzUyji&FR?}+%aSGDK9lSIXQuxf04+Z<21M`iM19`M+|?{HuPP9 zB7}eWA$n&)AdP^40As!i6sM;J0tO%uk9G6Pjp%2oc7rK50sdZ`!BN>V3rcZ7;#$kY zTzw-m6r81NX;)>ThxWcd&cM zPPY~KNBJz00eG}9(_{Z)_^9Zy`6)fGBGr4PzfNtNF0k7rBX>&S{U|s zUfmm6+1YDNK`rw~p>vp_%-riToeO8$H83mt#%>*F9yZO~gu%#B{M1Z`Je^vt(#oYD zTQS34xyo}VH)!E2UjB`1hdLq66?^t^knF?9jf{l2TfN?ubE&_FH};cz+1ZD@$3w~# zg%cLdL`BZe30~%=jf@R-3nx=k1rSiaSEp9})YQbC$??mLgY0Kku1OhT<%zAO@>XLp zRcAJUH`GFEMQjK5@_2yI?cjg0o>sp1>tJ{DIUo%6EViq~i5{Bg zad&Jlns;2-Bi=hY#b=sgXa9pmCDvuR=9dW^=V3;;`LME}wF(f=GVbh}wNcK`@;e<^ z@e{T4?nK6-=(^~KFvgO_LA+|bFD_=Q=9yHK3s@|o5_`PZ&KT<73w}HQ^>Z^zFmQXb z_m+3205`EDnvzF2fu3z>SyS}S*&T<#TiB1llhW8|FoX1>5Yh#TC?N_D9$MqiR4v5F zuxPZ5J=PEYF&ZT!?I}f^=)#4MNgOfwQ@x>%-vg0#00)*M2 zj`%HlIhOR|$$iHS*h#@h{Z=6U@r?x_>O4PI9B?rh{PbFvj~#eD{^manT?73~HGbGPezV$d zvJ?XenW~3;&woelGNNbea;O<}NWMb@Dq56Bpr86M9hVZJ69DB;X#2p`qz8j?aT%T>U)udT@){6a8Rvrt3AN(18rcd0YoP2tGwdRj~pt>N@vTi1rVyo zv)*9u-`|zIH+@ygM5yB-dX9jP;yheKFPRHal#i6)}X7_rw`fF`Kr zP6)in-}^YZOdo_J(s~S#Ap)xBj}bk4^}y_lC_z?gGKB+R6j4YiT#gc!^oEBFJ!UgRr%#=<_QM)X z=+8doIF!bpgLPZWRY%0ypC3Q&JF{k9!;I9~RBE-}%~uWP+Z7?0Cn(^RreldjCW-Y8 zFfYc)fZa2i5p} zOi?ak*hM0-Oh&>@X%OSZ@`?dp9DK5zEcKpF@hwRAsb#lbmF?s?r$wGdiF$}kD<_&W z5mUI8T`E}4~^YnbQy8Y$f?HHNn`w92w_kh|#{HgSZkh8PBn>N^f=*3f3p??zZ)?syE+lQ+ zjG}}Z9j!4WDI|$H84t7{uX32CAF2ZfQl*Zdo)QFskcgP5&9bxUw&cr1gw(Tv8mNcE zH`xeTy?3$$%51dFHmXCUNPv39!fL#~oilUtVTita=)=-SEJW6oJR9E5FX0S@diNWb zbRMc>1IJpsX-i|)?sNcE?7tCJ#>BO5FA7Az`R~PAr8ytTTwD*1W72nOv{f{T_pw#@ z?s`00QVHZAQy|GnXfG5`La~mXrp20UL}=3Fx%A4hgZwO;BeC-YyTpc5<$xKMJEi=GFh{{)1 zcV>H9F>|zfPtsD4D8=erB+!?*PehatRrPljk2S+e8-tED-=2N+7N3nPsdRQT1zzHv z-F52G5${`M9w7YA}!ZGm1C!zhNe4LuKmMi1n< zszUtfzuY0FA)_GA;NN|Z`b(Kj@61zczdI5;`rj1iyHarI^9iZG7xTTEI5+Sfm0n}t zc%HlFNjUqi#0u-H=U;{E10IGh7FUpwiy=&MBqSuXNKRxID519K^-1$W7B6x%I)YVA#^>dRBeU_Dkp4*yPk?I)TC4_v80|7p9RL@AjRUiI5X1#h(`K+niUs zUMI|(!CJup&03K!UeQ46*I7qRu;1~t+sX-f-A2c8BPw!h$-gEA4j5GQK3~l94j>ah z97ny6E}=(vS%I#30a4GZm|672YU4U1T`;=^9N@S+DqO#F$9zf5-FO(_Q4y+Xtz~{W zbKZOiKYzP#O<)xbp{g}ptL5+#7QGUoPM5-k`?;{nP(Z+Hg+8Ul5)NbL8}idb?fg@h zvavB|@v$6Lao|n&Qyj>ITHe~KZcM#T)0AM1+N@0kU9F$ zZXg4q5Vp8%xe83cXq1x*kWN9Bl!#8D|J>M@Sf-VW9oE-`-bIbk3>kd7@A1DT6s|k) z?)U*fROf+4Pr-ff{Xh)9>B0H>{ma1eNQL;LEu05+yV=&Ip-RuoRVYvt%IE00nQNZz z!m&B^wHt4d^tP|JL#CnzCU zD}l65`RXCdcPf(DH)sJhv@{U2GzyATVq`uYtwf^(Vv?+&J??xQJ#!fV%X!*GElaVc zr%fV6Edb;dAw#bKfAoRC7~T_On}iu=J9xXI=;nGnG^yDs#TrYb$=}Ib4!}>Oa9b z30zQ`=kh(zgxPX5vm_$@G`iLFCq2kfg7dGZ{kF{x$Lk{pSF@ifx@~^#^|xz5z*K?g z!_1Gj6W!!G(#^7{%i(8} z8FUQ4Lbz??c0j`NZ>Ru~q#XpnY37G1c5-x&K)Hje3|P|Q^hB;crLrx+bZ|1}NF^oz zp-@lkCX5C?l8bw=!zK4!OD&TrNUqKwV!XpmxG>xi!UVBrsrkb z$&^ler5y8rM`o%!3P`BO5GRTA>By?!yYeB%}9Wr)L zz`vgoebGZwg8>Zkcn zsl+5kchLPoqxtmd%Dmme4t;FN@_m0*Rh7JDAK4dK>#01Y+HRlc$aDYm&RSmYm+iXW zUw^dZf;lnf$CKPMR?_9A%@x}Xo-U%q6%jMmgV(R-^*qH=F)1GMoxHCew)`rZ{eJth zprlGQ`38GgwQ{RgPEBK^A^W>-!lzceE1ExCrq=Airk--;n_!WRu3T|oQQ?YfNUE6g zPv;$qrBnJD4I0oG5>))q7XsF5)~bOBpUMQPeZWLnrIRqRQt{U#3Hb=z%V8Iij;~j& z>^z`-z-Tl3I||3tg;V^~r>sdUH#mo0pK(@>bESC0ZacHv>h#zac%5cH=qn7z(Ec#tLUaNkAOgngOn{4l)+)lEAIb&5KG(5eyNU>io6*_NB6tih~uIU zlr}C+{|R)w1P+>!&M5k%nngkd=K^Z*J3T^(GHPTCEmv=3j)&*uGeT{K4vhG$ux5^f zwdmlNn>^>y{R`ivvGv_4aB%a{f;O+0>5FOKNxUcZ!tFcqv^OJXin$DP8N32a>Bu0V z(?s=uQKTSF#zj5y5Jg7vr%;Fq0tp$Vl>{7#KA$ogPrC@5l+Vob|7QW>6WCP^3u6-)X^Wq>`{7&yJpn_j#nOFx9rVHUbWUyD~F1*KWe3F8Ly zVxETtH-%LxodSmQsuY$EsdAqRp};oj6Mdny^!`Zh8+AM)=uB z5+30oD2MmEB+yvZ>wLqIJzYKi2G;w+z*C>6Q=sF2j&R@mFgCtq;I34&?rVC!!DBt8 zX@6ZYrFi@7I4~d({*O}lWwjbo1MEM=FZy6%wdsjU@FA`g{A82aEA28hxl|O<`Jr-<0y7JCkY(09?1j}j6$1wZoyD`<$g|lhDJ~250QOxc|Tq92Xs$A&`8L6d{J%b(HmHP(s$1mN9X&hpV;cDap(pUFO z_4?2K8^maX>NN{bXZLTV27q}CD$`uY8;WPDm1LAAkURNQU>!ee6jEuPN{#of0LdhY zdIB*!uaPK(qP&7j*})-;<}B$LZkQTlRikfW@tU_`6tN)sn`|Hzp-^-JLAXPIHk-$< zA0Vj+WCO3`{9_79uLoHB@?KNWx79SD^@GC>X*h!tQBSuOo< z3{--HD+mP7i`9+fd0kHePDcgtqVX8ZG{EUv1qixhLHNlbcLd3_5@1yckQ{!fRv7a{ zfx1*}izF0<<~(MuQlShGWr}w`3Q(br_IeE=_bt&H`%F}SH)X+Ol;?4-R#^U^B zm4hz-hxbG}$3TXQ1FxTYv$86tFuYVU8{KP#et*Z}Mjh zFY6|XdK(8fL^@)iSaQ3pq|<-E*S=3FY&E-7W78kDayPeI@AFNUDmc_w#h{<*tSbCMG6u z?t^(XNl&~={efBbrMh8#@E${^!PQ^)=^ycI3J%+O>mD253CA;`?t{HgHN8_7+_sj~ zC}H$+(Mc<8Y!ilnu4)WQi;Ibk{UZ^B%E-VXYH>AUo3*aX;kTqktM6tZ^$zlvVQ4FpA$i8ua?dBtS@Hjnc z^QT;xQN6$2(Znc^wg2ede8u#{w6@wGpf)e=b+Wt&ZkMJ5YGxH{fH7|z+62UH=Fb-O zE*s66u-=P!JpCEXj&Hk%c9-t_rbG}9zE!Z(>YYILP;nbwLl(p?d1!Ki_OEJb7{`bKLm#eLJA6!h5tgc_s+h8Y5Z3X#)oyVh0Zl+Gt8{Mp038LL^0~^G5w@Pn~!-WE(zI!LT zhgRLZs&y|{nfL4ynpFNz*+y;GH)jU4dp)VPiib3w5PI9 zjv+VYyS3)W{zlES1=f`E9`Zb(K*q3%&UPld16BaKmdtbg=|yAyYU*iRS_{0uov zM|Yd`P(P?9M)=Cf_DylonO4lN2sB>)4!$U+mpkiuJ}dp2h=Gj>WbqnX@rMh}PXiCj zx;c7m;!p3N*El+NOXAu@FCXwLT^u~(WjV;}@&vdZk6_3klleX*^AvTOAM)1ly~Kml zXDd9Kq*nGMs8ZVky1Zg{9dT30T>f{;&VRlBYbqY=A->n#-)Bj`O5opcdFZqMapKpt z?x2OlnsvoH|CyIoKuz|rw{KK%;+xPKfox|^2qMO=RPq=UUEWkYM#;=WhE+my3|(?x zXBjSpkuaBe$9gX3r+E#e!s9@Pf?S=RTGpcWa}>2i1jf|IL!-V%g=c2lXxxY-IKmi0 zdc_~SYW!md|Cq#kd;>Vi;a}Fk*ul?hZ%mW8L<*z^la3&lAnDBT=;sn`QH^uYY8Q3^iuGIPkm8r zv4hthvP4Y!5kqaAIFKNgHZ6b zKoVhJD;)lSB)LVM4FfAg*H#{xj&>$)veS*Ay#@;_RlQ6FX5w*UdI9r zMY#S2f1IMLqDDbq!3dFXkf`d@o;+;MTMh`~)EIdX!ayrC5--Tl#qN(sYFT8FBI-Fw zQFy)hO+~|%?O?iD6BTq(`j(TOj}H46J6`|G=5!{TefKIo@YzUE(9=fWfl%{L*vu;?TD6 z`g$J};N_Rn613e|L1bkIh!Yg^E|z*duU8JMjM@qZyxv~BCp?}eMuVT*-fY@()+?{` zgJBzWQGj;j#D@eC8@4w~d?&^qcyu$m!zBLJ9-Nh%i`u-^`?`ibRZyTO#&`KgW12!d zsDz54!rH3mDZzQTTiLVm?us?4yu7FTI3}NNe5mI>|4qd0reXg%{L62uw}T4E*OIRK zK-k);){khcE{_XwBB5!qXExeRw{h?)dWq2|UQa;U`n0iIRVB%HJ@Vy8p<&iLWxvm7 z=kLTs|9`L_Uc#q(ygs{)hRDXkdSg)F z`(2LyjB0i2z9$iBc$=9u{~Av1f3ffzvig!;rIGEKt<~A{ONVF5t7En&(-zPm23uoj-5 zCw3qWKAo8zVR-MmdcDmIIK>|&dp3XMd7?-t*bsUo&KKsX>y@rxgC`}J#+ z8z%wJW!e=01&804cP{Q}Dp{Q@X{8Z@k)q=jKDd2c-+c$96gDrOj`^Mc`kaga^pbts zNoqQ%eA4JcD3fx(;vzZ>u;L)J{dH5QS$H_H7QaS5|5g632o8&?!2b>TjTyy#{`%Uv z^YY{QufuXn^H5p=p7rj-^@*NEdK4kxkUPvUCgs4xc4zT5ygWD1^)M z@M%pvVj5AX;it-As2)@BJSYh6cnm0@G1u4yT8x0{#s*h;R(M1r7Yr>5ZaA`ISp>g` zuskhRfsYk=0pjNL>9HN5&OoP{y!Gm15cZK(Pm>RXADl zB7g%W&`Q}pC+q+>dH(}Aas`-*YrAe&G;_!!@l?hSm6RQUUlg>*Kdo|S+anlcQi$N% zy748nl8^@dOp79rhN&03th6fSE@`d8luP;UCwhp%a!vAUpDL-h(Y?t&RxX90m?0ar zwm2>5^S@OZ?tn!Al!~&u?2)VsA0nfqp?=RzZy!;}%Xj z?hD=6;+H%1LFWgJ_+P%zeRxqRCi24i=H>IdH{e_w{bTpeRh-Q5SIP`eK?lAyY|) zBIW9UM}!`B*b@fIYj`L7gG|kW1i$Q?SuO25_>7Mq)N?>ty3wF{vC@h_WAjyQ#h7P> zV^cU;%(!T&=z)Rq#(vrT>1SbkR(|$Ms$=1RyTG8{XS<4D5PHqs@oLp zvTClZFgK(F?=m%{_Ng(z!^LK~bg;^tr$3 zZ(+2k_$5dLX4F#1%AeRiu8~jzgBcN|m^cFV(eG%KPFUzpOsbp`q>}8cKZZx+?%ST4 z?VAxJefhU9GW-~@I*Fh{(-=#S1c!*?S;UJA3K^!4C(3hA_MG~#&B;X-vg832=F2bhyF!syQ((zIqq|f`WyGq6S z)I)*!^ZZ&+qyKI7$i;-gH+u~Dz?+dq;qza@g&fM$$|_3viO+%4*Ba~Qe5r<=R-U#J z-9RgoiKymwHL<2HCpXs-qMwmZRH2%Dm3F?6n-Cs_1;l6|!^#xWkyX*Z=bzP&o&71GM&{Hx(I~o z$cBC&$S=jSS3&p*vXpd8`8jLHsD_vrC=Q}Eo%tD{&IQ7^19ECI5tW+=eA(2)w6s_f zx~?At2><&aDN`U6contz=GC_H_SDuZCc^zRsuFY~y!rUw?(XG%_rBpyDSoGys1_M> z;KBXo^NjQR_VW$o4X>RwcK`Lk!pE9v$G$omj5-95d%Yz;>ZeSLjB7khpvoeqQ=_gvL)KCSlk_3ewj z-Q%0n89!C@J|BMc7P;?_D}>c}pDj1S((ikkf^MHU0w0~J0(Y~6pRO|BmZ;w9$v2yJ zc7k8|yOlkTf4to?i3cC#Zaytmh+PgZ8F~*=1?*PxzyLxSy8nIG)xdtiQ~zeq&TXc1 z;B?e0TkiPVPG*nG&B0~v#^uJE6KocmY4pGpeD~O|`e-cnc9=iib624P%A5!j_v!r(S{!Va--cU1y$4z0dj1{xF6$ zqT@-!POrchZ1EYV+|9se|BaxPwT-v6C79KIDP-`dLj0wm`Sd{C`E_f}`DvZssPXa7 zVdT-@399br$#35`PXfA(YFNqy<#Q5*;7e2bt_{qjF=CZJR*T)EWqX5_GRIFaY+*(iuN6%_!YfH~HF1^l!C zyoGGv@o|a)(}^hT1iiD+@2Lxud<{Hh;Mucw?CtOB=sGLNI)G)sn2Mj)B3gtq*Y=72 z6iPQfEEDw=*`J(0!Liq4jpOVgowh0s=@_hRH%L<~!TP6T?a0vQzer+-6~BE$Z)DS7 zPLr#WRTNCFf6rO_uB!k05%BOk9H9&t$G7uFgG!chJM8!jK2$#kKe`mFW@lw(6&4D+ zZu|7;T!{P_q!e&5S!;EyP|*;NJ@2~T7@L_P6lUM_dwtr!>zcE>>*zM}Z-m`%w%eb^ zLLo=}e_w9KVlK1WkM=xs&)Tnh)^|!{lB2xE(kJ)kbFfX(=HNdnG{HJcP*s2E+%5-wp9wRDKcwQ0oU)`qkv zBAN;xkUlG((lBFDuneZ)*~JS;(1J|%(~1xf5ivpXx#G=@u; zTl6u{yx=NJVeWLS$~e>-QoYpcl`WpX@4)&<+=;0^R#wGpXAeOjl*J*rG=U_=?=Vgh z-5$TvZ+Vko<-@`3g$Q zHiAc@va}bKCF5jHx>>wHhO%9Fki6elb+iHb<^|L)7aJSWkScz>KbAFla5A59XR;b` zlHpl1l61D(SDO(MXtM<3NLa2=5ttJHYqXp}ESf83#A}NFJy4=lPY@e06q1c^4pa0y zK#Dp+%u}#MJiO8aF~pcNO)<)F-Qic>dqP;l+f$G}(ZV~VM3cgc7f$XIB*&y^)u5s< z9@>C1=^tbh;e}*$3-D0{pznSE5qIa`-O0?-3x9oPe3W#wlDHrBb)@lNIgsgA}9p=m<4W?{ed*f(s(~E&r z74h2}o&#$Av2!HF*iFnc0q;uEVtMMj(9{SZ|Ux$G4gdeEqtGwDu6tDe|(!`)7JG#r^F?-MR1~Q4s zFkx;QcEwa4(l58iE5halUBsCjvV_67Hb?l7n3yemCY1-!zGKcz!4&ip$RH33S2n{?UV6A3HDXAp4_@cUeeA~2A%MAM5%9lV>(%`;$FDhkbDnad% z2nT)JKb-u1(^1W{30d5D&b!9ET`;Itw{3M;X@Zi9gg822F!nK^o=LzP;K}~Vcljba zCwE`=B_u+b#7$U9b}m0DqH45{fSf$u(SdZjnO>oZ(OyfAp=!@rWdDEs2=P0no2c*m zvl`#j^PBIH-VT10B zDFzAwL`tec#D<<5DV#BGPr~zdE=|W`!5NFkTAb@P&+S|*hgGOIM)I|dQGB~PdkS# z`+GSIUV)l6oUz8T_+Lsl5=|2e$&);`)GnLCHLbNYZEhKAC4n?ngY&=H7r$;np0L&&!({EpJiN4|gS20oDA05J&qmKJg%Pu`xDPh!8;p!yz zQxP``CQpkKCW}G4RbT@>TE$esbYSIzy#!ySYfOH4Q@2mN)m}Y-M;hFl1NfmHMO>ny zgz|4k{~=U0$0(t=+StevVp9ndz6(IHi6s$ z!4TM6mYs!2T=WK^cXS^c^IYkeVMa0dkj zC!^fS8CHToB_In7TlFUwFR!W0M>hpKh+KcrPdaKpte9Auk8$sl6U2f*^rqDDXd-HO zpSiI@@l{o}rNKb0DV%?ZIZonTh;&#qH}mi4Icf#*UlkUgB`@vr<5I~L*io8y)AY~= zXmq}M3cnnMu82Rr@blN_l95u7P*hJ&5nY>-(dYG4Lvl;J2NHxFn>`xcF7T7NA{<*l&sag9t zRx*D`KNW+fCvVW-Zk^GD0#^36^K{!p5U&$`ji^R5tH`W58uBD=)9OIH7GG(GO=Pd= zb*q6F3VoikHJFssEtAV_Q#1`y`1F-B8IAh?`%-@zc)Ot7X^#0V1*pPvjOtTvp0?Ag z!SBTT6y9IaEBtsb+#2{?YOhs48h4gsuk}A;SUcpZ|C(c>P+TAUX9zh8z^0DxF!TNsA2d!Aj%M<3KJu zm`k3ke@`=zOzakN?8>k}nNICjW32Tn&G!py^_xIA#xhHXfBt7#PypER;R0n@B5^4Igrc=ij3+L_kwa!1N4>0>Kn^4| zOt#%CK*e@%GLyYPeCZvtg75Qm_vyoBD)~^Ga)L^pAWtEJhu-7Ez|3!Kk-Nnu!`ya6 z1R%38dKj~HnT_9EpP<4iS+DN_H^-*m>jblpQZeX;me@gh1loMeoNRXwdHMMCPg0uZHQw+R!BXx^#u5#O*$lrNonu7YJ2(rUwh)1d?4h>HB5sM!`a z9wkDYzo1vF`HfS8;f$nt0gsQOL_C*+ySux1$}mIu%qyqi1o?t8wem?$WiqehzQ8|2J43lp z1meAPW>iqG$2;rP#^qXcb$T9fUu9h=>T;l3vvPFjxA}PHz1r<%L=>SZ*F*)oc;$}B z=BW?{m-7IJ?6%PAC~WNOJ3P)obJYKMeOk6hhb_K(e5YI}Xb4`s>f4{1cv&Y7ZnN7O z{?YSENJL1G_f|Xjk$CKtL+qYOpWpca?d9q1+TS1hJtYN2ybD`j5F_z0W{AwV^{yCe z2nq^rbu`(RXj|SYGYCc`HXH#0a|88?2*(_O#3&w`&4mF0L&;W=MQ!xG0UnJ_v<3Pe z4!m{NyN{@|dgBx5*Y0C9N_f-%*&qHHB&Qp~tg<2aOpAw$W~N4f0C~#neR;$Mff_8{ z)(T;di{M=G>qg`3Th7COL#!OIe;jXf$U)chOxDV|i1rIY(RV`mbN;3M1l78hMS8h8 zIb@WS;ywp6$)#V1hQD^-!iafOO=zT#YVky$V5EF-rwJ%|Qfh4oK5f3CdC3wxmgpgLO>P4y8H0Ce^YDhF^ETWY()&v~x ze-TC0wU@oRayoDc%++>>;rF`gltc6%y7(>UPQ4N!wTsUpeuy}YY+WE^6SL0|O(!2r zYF32Z%YpjH3pCTv?f7G^alqrKQL;AAYRhV7_gPH#JWq3+T#8@6<5JIA$yTzLzb-u$ zDHwSa!MzzZPAS#WQ=@og(1a3ARu|Ejj0&w!%4(mOD0lsDxF@?DPQ$i3B1XtNcU^!D z(&1}&d(_qi1?MZ@|A$NkDEFKXMT>pko;Sp~xZXpi;a!eyNHuc+pkiO~Z{3Vy8;H8D zsA%BRO?LWXlc#KSI@_cHw`vV@rJ9KM6R;>IC$sS(Y{F7QC_-W%b2Bk9xh{|6t2ONW zCD04FL(&JOaY@N4cflDPSAOPw%!q>_+v@wZ8UXI4Lc`oA}d7*ZncKG)tD zW@B{i3(XG4W}UQRvcZs*jc>GQs#UMI zLYgJ97$T7^0~JxIT~zXI8x{DQE>X5^sHSzzv03Xq#^CP@OJ6@s974$X6O|HAe4y$3 z*nfX@&D~Z5triczNk874Z&8Jt!FF%2ziYIe1w{S*-W2`sZXTWLJFjOByX)Uq@sWuK z9mIe$jfD7kd+e7AkPCdi{Wt{GZ3YCz{fZp>8$4lVe#O>0ih`-+*w%E0Hv$eIh9&7Lo zlX11y@nVku+2huZiYQOJooCI;)5CdS$4!^-_|R9Xz@t|xF_u1!`I@(fRO3qi>LE=4 z+zT7+eOTK!^3k0Meno#PU3XfrL)e7fKfe!fd6sXs&4&SbqPdxW4VAA4pCYfBuGlnld{X>$+_(nN(Osy3I#Zz=MLT zBnK}K`rg0>fSGdn9abqM+j*;i{mWY@)ti7qidP#6iOnB7Uet|di}a3PjatG?ZWcvs z406p|TeHe)c-amOt%oI(D&o&2YLYFINZThmS-K;te4KMr^S!Tg-pAp*=eGBu;Rj?0 z;SeohZMd(E)5@9*h|aapf5yNfNxqEF{c88>YHaIwl%bh^x0#*Ww>IqzR@QJjI;xjG z*%q6$`q@MY}E#4A5-6Og|qCxPUE8Exx z*4qnEkL!D`5`~=<<{XB{g{gj>_ZSsuAFZ_3)Q#kJ>t%oo4CamWC>%byVZ}5aFM@+@ zm&AUG)!~u>i149Tde2sHuF^Ej*qW9P3!7cX`0QQ|9xy9{Z=zq+rR$ate0Uf z$PKU3S_%$PYqW_Cgc8OfZ;W)?bMiD#DO%`F)?Sa_8d9@RyGVj2edzw)S+fH9c&dCj zXR_T2y~{%OTkcOA>6OgK1#QD_|KUWY_iv*Nx%`_?LFBWD2?T1qS}x10nwn+b}v6afZ++d+j_^G%>Z zlr+Ft@Ym4Z}P{~eB)L>7A5Y( zxeg7C@!T>QBCvhS?hCpA9K7yml-H5dkj$$}q_ z+Vm#xMn-19ZCzV?xyHsdWS9BhN)rbD+s#o3IxQ^>JbjP^Z&YfkW5MIa(_~sGu#V?D zrKUxE0&7amlx3%U5EN*FwCKs&cz4RByi5UMlbdXwNiF;1vP?d*1Yr2?9Q(|;*X#7? z@Q`j83y_j~ZoVRrFF7MdRuuY|r&u5)_?2=s03WN#Ra%a--ZwFB&2jEby=ezrN{N3( z09@O%3T}*{frac#^}3OFNve3=gI9+h0b-uimnkyz44v>w9I-0TJ z(fp#HY?5!AA3cH~0PIImFJN3mN>|FWY~g7JS-in-VR!T8c9Xv93p~O=^~83zTzXl& zN;;hSg3)aJPgKcTEe$D_FQ4t^*mn9X)jIyr##X}-SR0z?+SX|{eR?oqYjWYOiFwkh z*LGbPSmB-?G=Zp3`gh|5q%g!x0%_;{8Inrm>Hm=B6Ht6M8RQ&k;i=0ss|mlf&Yu>k z*@NM2RV7^(V>!MNf_Y7{y5-c(4cpcmBjg4jam*UZ;`*({ESD`AtBKe-*Hz{mjv1?|v!iYh4in{G-OOC;sVtSV9A3r%r^CZR)f%83`*WkIRr7~+ zA(cr*>~R-Am(S4S;$ZgdYOEpM%YLfZtsXzXJIJ+apJCLFZb!o$KUHm)*^MAMe=arjze@m4N7yDb8%iAQ$0aq4o96~=l=&^L7={`f8ozQJH3AN zj<>wWT9>7jZnsO8Km-J1u@$p|MY#-RnpTZJnoKjRX%uNEpi8 zdv5nS^YaUxq6dfx*;T_MXpMCMVz{5z2du0rC?pUR1P~26FVbiX4Gs=_W)4Bf0163^ zu|TGejm4PufCezJP6<`P0w^GZ5cZ!diDY8{Lq-sOmJb+dw0$l<2LKR`^(i6(C{X-? zU=-1!G80k3;tY{MAXQL@s=~&QGp>@@purggDL?U_|5IbI-fg#S4AE607A7KLWl(Dk zhX6mz7E&cdjoP}%%2S2N2vS8rW;TdOC=kE`MshR&8N{d%M~$@#Aff_G3=fi0*bqfS zGlGBuTB8EWVvvvwiwZD-A_=Il0+BVwl->^w4YgWrGK5jK$*7=tS(YjW9TKQl1E^lS zFUY7tOpHk?NgcG=ZZ(@L!3zZ-haT(#{ zN(5Q6dR1ef?)LgK^Enzr1PWTIX5CI_x!EGq5mMuv1_neQm?)8;>Vyn3NSAYCUANcW zw(ZK1k&z=uk3ReCv-MhiU|?`?boj0Bct_Fe4mKK(Zr^_Iz4u>r)m7`(tgqLqcfI8; z(^Jz$UX&6PpjOG|=jVn-h87nVfsC?>4~%N9B_cyciGd&lAJ`)rU^Ld%Dz)X6X1m)l zmFkI^Q-ec|WXKdnsWxFUX|2X(=?FwQhLV6{-YWpGl2vl=S-?71uh&n`oL;wKBU$r? zo8H(hdW&;&yZ7ule*Ad7Uh8knF*aY=Cvppu5E!(H9U2}mpkRQ5kVHYGRe-{ml`K;v z4J@F>kTGC26~z#|2$#J)_%Jy&QA;a%FORGG6e_}O6NdnmdKCbyHDy_fsI?|Rtkx<7 z7(xIOk>LoawShrG>x}Us0Dv)6tJatqtWnjZQX!)Ld=^on9aou4CTn{kPsus!6rftG zNyNFTI_rG!2xJL8hbZ|27PJO{B8JCU5@u#Gh(++GPl}9@w}1!)rdF*g2qCd3B1lY? zBS47wMpOi(f!Mqxm6R|}NfSV{NT6zv6+jpgg=&pZF~%s^G%*GOYgNc3 z20)#48e>jX(|Rf*0+d$LP^JJhIzDpr$jSR3xNmZ7;)<)boj7@Hab48W+i# zpyG=nuurTBF$oV587x`PfmH|yNFlC^Bq9kI2o=B~dKCd`bvxI+{@M@x@_%^og_jl< z=3P=*vu@p?eFu=BnHL9-pFKY_6GH~hFE+bnGCnz$&(0X*KKVx<`^10#^QXW1cvf$8 zI!o2c_~wf@FRtt=d^t8YMhd~RO%fzj6=xGuG0Q7$GPXW2i~|_=@!eid221a)%T(dq z`SS)15il!S+JA6=v%Oq;uL5aW*?QS!)2pXXoIW)@F>&J!H+=v5-(Ogm%RAjITQ0us zmRpXlS-Wrl{-Ke9yWjKkQxiicX3kEItoq*QcmMal{fl9K=N)(5e%l*Fd1xTnaottt z7MHg_`Dklp(b~%3(4cckmb%rGgYSRuM<4vrBfitTGn7@8o;);UnJ zsOk_2NKLg?EsL_B&K(BnneUH6#!wuIARn030Pk-u9 zKF=WthmU;t1Gipx`A=Wi{mpOw(?dV`_nU6I?j7&?mAToOPyO*H0L<`E^=se!*Yju3 zfA~Z1I(l;9@X=$>JomzfF8;YU-*LwefAl~ltFed%wT7fG^ik6MQ)` zI#eI1zjpXgwOSXIm3G_bJy@8(ZrjCIUU})%s?nm|J25+V?@u0IDr=3#ST#)$H3D7@ zIkoCb20urwqwDJC_ka6cLjyxAxu2O`__uo=SZZf!eJaZaguOvQ1<(-9D~4QYe z5rsZ!P(k8j88Jo^a3`A>@q`wS86+}>n zC@c{@42UX9aa$@1sw5zY0DatBELk8u4`AtxlZT~Z_;1Xu$g6L!j8CC$iS9?jJX zzVKu)h(YUANq}tblNQf^4=dme*D0}1D9^OYk6Eu3(jWH%l%7Arvpdn>B)TkF_AteXGvBpU5i(J)c5Ry)h zu|Gy8Ktw|*Vq*!bw|+1VXu_uT!9cVD)3%l-G?-^qJv zwZejz z=$G#P!?G+Y)!M1qGvEH#?|$GtcWoZ5Y`f_Foi?l;goAtbyt3oPx4-KhYepLYFgw5U zm4Eu?D(8quq7EQ}vs4UWzfh29AXlRpMB+CdSQ2MM0;pQTk&(f~rgMwS-EI%SB}rn5 zgyKZskYbV~3T%M5D7s}qh6pVwmSv%l$WEqjRyP+wUmTDys&Ne&U{Z-%S8vcl5Fla@ z(>J#x3s7QLubZkSbfy=&d1rWVD0S%)!^HTcO6YjMan1A(EHLEa@GPukbW{S851*+y!VYt#bjyeOCwM>RjFn+O=>9( zVWmU1?Dme$o^INdBjo{r(3C1?XV15roz<(?96x@XMVrm#2OoGaORK$Jwl~U%b9j8R&WW;0NCOk>CH+d~*?f%_WtzR#6bKhM)+YMVa6Cx&Qi}TW`4@ z$O6{OfU{@j?z-i=A8mi-`wu+r+dioe6M=-%8UuaBAX#(>>e2*#AO)o8sSN;>7^@Vg zWPO5tJPOEB40nz1r(Pg0QD06?EMlz{)gX#7MF>$KAc10^??PnzaY6{7VvPNn@G5>V z5D1_)Rz3iL#Hx6K!V9FR8iGe_t+QoW#9&SkwLhzdn7PmFM@1DtisnEDFnxhVbR_rx zZ7xYlmKYTQphDz*K(Y!FJ;E_I#9)7g9ZlIts2m`MMk@dsiS-NFAb}7ZkV@P(ifB+Y zWD?={A`t?XWhn?no{x@9OioShKd?WmWE|D#L@}%cRefHRQW#?c3L$}jF%G~5z_RoO zYgq;EST?oCQT?AwoykD?Ax2OEyHpT;xTyUccm$End03+-a_~4MJ)S ziW)=(FvbBAD46~<8dO9;iHM9T0|!tOt9}9Q7mbKSqJR=zEb-%*=pm3G2*fOaV6+c< z7MA$Z3IG8rgNX_<6^v*LRv=_njM!0$taOT<1BwEY#XdzX?yDo>IVwH+87y(Y4uFUR zC>OpqL>se2L_`_T7z7bfKqRETa+N5C2?COFvePIjkUhWgRmvT%w-YK=s;rt1hOQ{yZPMNvyFPa)65yIbtp=y!!%0|9Xz;p zdQD#Tls#~gC20wHlBE4!2oQi&QPBW0a}=>L5(W`6WCLbtW#-KJPkj2%CRR2_ahYo`IpcvI2&t#>W>H&##)A zdczxT%+d@HPR-0LEv+;L8d;hWz)*c~{l<+;D=Y18r(~X+J^SjReRtk*M}45WYJA*T zb8dF-#IfU-Y+nDy8-L-F_0!brE}l7k{k2z>9G-mgv8~%KzxL|O6kzV$>EXtPjjIOU zdB<%>XU-iwa3IUlEX&TFJzcNEp#wAfi_ZDE<@k=A001BWNkl}GGur>+7gGN?v zf0Cg92u4HxYJhy3O|C*N)tD!?lMGA57CU-gHG?q-oj!`1;qsws+4fuerd;o<9Vx@rHuJx@LMXeCKf zYdh_gO07OLG(=JijgAhinqFxwJ@)*e6DMa*%^dx$-};Y_eD52-@!P-u(!QhE7!RBp z)R6bemGge_z(0QZ4{vz=RuwpPrgh(g52?bMRZ|nAQy+c*d*A++H+|&y|1|HKYPAXo zWhrFP5K8dmNP)UVsXh=A$PgJ4P-85K3dRfCCuMbddN7(V+2BMut{EVk7}Fh)A!OyUc&))1Ug>=RUu% zv@|$8T6ke$4hl%j-XgY(UZ6xXs>jX)e%*al#o43y#8fSy!`UZckkK# z$}6w9)SW(adj9-;rBbQXD!`%J?NqDP;gQkSa?81Fd8vg7st6$k5ki9Cy?P%4B085a zK_Kg;7*8mX*~}H|N6g9j?%aH0s>2>LCkfi5Kk17L5`bE*W}O?THRx zUf7kzj|qqbhDBA?0QG}yHEw_f042768jTjJqJ7~aVc&USN&8aU!zPw2~qk>WI!N6HI|V1XPK^KAhB+E zU`Rv{A308dK9sb$OfCh*r=Nay$Ie}4H&+ppIwb5gTbZ>Oc%V`J?|=DsUmF=ccJw3z zm!(gw>GpCwm-P=<=d7oU1)$IhL*URt&7b$4u7Kl#J^ z?>l*L4_JfFa_|*rzw@nsDt!80LtjBQeY!iT~aV-t-x4!`cN|L*T^dHv0|-*LzGhaa-_deJKe z28LIbmzU;ef9->x=v3F#hcC|0zw+K+fA>>Q{P;6}`nfNB_LKkd{qH*W+0QM_?XkTf z2FZvwtsVKD&wY05mUV}Y&g|Iv>h|qVpE@~n?)cuzIEb>avN2Hy%!ptN5Gbh_6;x0ujj;d%;>jccNJR1d&5|@rGw)0G zfrBVwYOJa^s;Plqo?DZWQAG-h#sGj7@B*O97TE%!T2Um6y`nQbvg+<%`sHu_+qYkL z!|S$fyXx6zpTFgexB9Xi8fuJ>jeYE6AMbS9_uhN&$>XP*?e;~NZdt#1^W^H)S6_AY z?matSc;>lkmgPk^&75!uMLCe#Tdu$6wF9pNUj#Ng_a1DFuC_J>V6PI8B(MQMV{Cxaab|V~ zl(RIAF(~a;%NHd$aE^laX_nTq0fX4MPz+h0f`#?q6Ff?No@M-(Mc5fL;9 zDuhHTM92}7h|fdT==x*(>sXdfcdU(sS86^aJ>T9)fY9 z3lNzj6wP-c9K$Yz6-|Fff)UQ#PnC!&F9afuJq+~4?fu_k{M>-Ru{Qp#h`5%#o-vP-9;f9K6q+OHZFY;}Rl8H9!hk zCCz{tj%t4CUuz` z9*~v!!;;TmyKQr~^hI-~xo|qQJXp(0gaBa4HCL9t^ymL&>-x##OYJ8fdG>~zU;jV< z=5L>T@`=y<@gKeGu3G@$4?gwZAAb1pdLy3khy=z zL^ueaUz&F&RkW-Oh>Ef3CnXRCtXL67V*{%MK|>(Sz`pcxw@1-r8gC|000_}l1kqV5 z6bT(FF+b6v^&qO?0J%SUW`>X?)mz?h(^Nf5Ak4#${-jo`yy1!slfUz^vGH`!!W9=y zJ@MQdpL^~ZW0SdsWdOM5b=N%j$YZve7I7({;i)H|yy?c9_U_wv^zcyyIKQ~Od2BLG z8-MU$KeBplWoG6~qh1FP0s=$;whoJ2taZ*1va$pKHHL(_-(!;@jIk2R%w)9$%L)cq z&K+Vzj$`=vkpjW@r3TOBk99N2k0hfW(t)r*Kq;v6as4~-<&1rA#_U$XPX7n0QF zzFb~h=(Jm-qZ9Yt|H$DJr;;S~!9Vo)_FsMXJ1@Iz+m9c-|Ls3_>)YP?x{v>tKX~%N zpX`10m5pns*KJ%sHa2p0b}7%z=;-vD-+V{4Qne-}YXPLS(wtg7ap%w7GC#k>K@g>o zfTrr4U6`Nmb&D)XPMn&5>cwM~@eQw@IMd6^TE$2RYAE_N08y9$kN^>Zg&Bm93_4>- z5n1A;ukmJ71(5)Nh79$0!D!JSA+!3@gQCQMhzr^g1yvRXBtrl|EI_fQQAMyKQOJ#G zqD)>zjI}5NsD?~n^`41HRBfzK;zza@HuP~aCK?b8GaIB>uRxRo%Y~$7(U?6IUmg=B zwV;G?c!4Yo${1ruL z%dhPJyRUrx%dOLv z5?3wC*vP0Nqadp0c|I|@>h52BcTg_M;>DL=Vv(W2#_-6m57tTD@95dgSoIeFw8Fx#QN`uDj}*?c29M|H3o%YHekC5kNajv(uye;ZOfYYH@J< zvOC`Pf1PX2J6F%L8X_~s<{W#W^r6g*sTiw8M>FW;J%BnmU#YIU^6G0|+<(To#Isiw z7DW^yqbiDMh{%`_f`A@6e7Ih#EiW&hICgA!csLKfmZe#eK%ywCKNd#9 z7;MX|L{TzG!~kSiS^8}OiZI5=5d}p-FcKqoV&ot72a8eHCK#nIG57`g%N;ZTOl06^ z$#MWhafTi>XMlb2nIe+10sssDAFAFoPOqyv^IgL}=e%Rhv!t>tS@I;=#uFH0umJ-B z66g*jq`}Y$4J0H@fF>l}Nt(=kbMvDy1OfyIfe?}=3U+s z3`4fzvH`iR>x~`uMUW!8ltd)B5J7U3M@WAO(~{z;tbG?dhkVeb;U8 zc8Ff{uG?E}q<&_!Ids*fwXw|r zU68EZMTd%Ll{8U=UN;A^@ySsDID6{sO|N+Q#CSG7J|-$jiU3dm%r7iP|06L=5Y;H` z8GyzLAplbd$Q+-gNS1TN)vVfu4jMS;*tlB+AA(Dq5d>35J;fO$IH2`Lm*|EBL^iVsVh}O~;5hRW5>Y#E-~PETPEU*p zz>`nxt<)-cUqAQtfA4g3czj5-ztZY0E-ut66-|=6@B7KcJ1(Eyw3#clyY7AD`GYSU zd*S5PE!*bLE#CQ^I}aT`e0E`>(Hyw_Z~ty~^VVBm^U901U-FfI`hKg`GP69-lQby` zZ{-Um8pq0|EitJPVC=JlpkiQInu>vAGK41d+EQ>f3ALJO9{?a50vKF4)gId@l|~gf z0nyy&43;=|?AXci$+25rar4B)nDlzrUvu5*bEg*;7pqwXYc()jSXhC)pE9ROc4*(B z&z}0bYp=ZclI>frzUk%LFW!+2&b<1~Z^|k#IX0PO$?96CD8kUd$jHbPA^<6Y^C2jy zm%;+}dNMRLLJ@eQf&>y|a$q9~0?JjFT->Y;o$6$d??333QXkSR%_T%Ya48K4Fp&hI zgqbPs^y7&OXh9?b;Xu(K>Ln!@Ma>u>K@LHEQ3Mqt1Oq}cGK+UjP2Z6CuiC<-r#_9@UUg;=lw(G4&HA z9|S`XMTbU+sumMQx}Fe<6&TD(q}3Rpn4UkWRTUA8P!&a#*gELD|c>r`HNpPF+FQ} z3!u04!tE!2elShTu!%;;_xe+UWIoSpmCUh?j*I|!S!(fkYifGDQL74Z-}fC@;+zBx z-UFem@7aTF$OLFEnzDcZ(UCKx*!hqUslu7F zr~cvgzudfea?id4=);DM8=KAM%5qChrZ-F-KeP1y|N5cd{>}Hk>Q%4k7ygr<{leXM z-OJ392M7un3$TJh%*mRfxWttP=U_+-K&C1nkxNL#q9OX(1(cA9NYyBI!x;ivd9$Zj z$VsM33PfyN&dOz)K&13$mN+ajFd|e@jGk95z4Qj_1C0?7vXP1spqiAvVl*&eU{j3^ zY%#)Z1VjiLcUu98Rg?)V!ixZi7|KJH%>p7r$?imQ1OTLw&4BCO$nj?~egwm4Wg#SB zjP~YuF$WTn(z&K)cz(GCOip}2ikEjFVnZ|wJ`_okR4SEs|Cj%~^THVfsMiJ`dg$So zTz~B))8hcp1u%fs9u$4;gcc@~_|c_SA;S@$qr*3qnAHzAv&YE%Jhps*P&3R&x{s4k3V9p@piN zWl1`_X{y_`Z+z>%#HBlTUeWD#2r(}T3DWL&OqzMW==byBi(bFum>QKDr&)k7$SzH@ zZhLiXXs|UtUT@SB?~^REq9}C*1VTmtH6>zIsby)UlEpM86(Yexu{zMKGeEUcFG8p! z8Hgt$L>_DoK$|NHjOeCpF*JacO9+`?R=J}@>hE)q&>GawQfN~C=fVC;$$Rb)a2wE%#@ z2SkWRTtehn^PoY+B4=(aN>&x`$EK%0^O-N_MW4wYedwoY#skA6Sz4PIo4nwHO@g-4UaMs3-hBu5 zK7DXtpz+=BeNP0kEU8tih?wU&BF2_nVq)UHFF4vZ5rPPjD=GhKYL=x=IdNcO-q=;s zB+Y%JQ4QPz03F;0Fg><$`bZ!C;*0mdz$k#!k($-oVhDHLbI%2{o05bdf9RoFy|QU) zLu;i4VB&q@3qZ`$zJhj(E{Lzxvx$kxnW>p`a|^4d7uub6V}pinXKrPw-Ofixhlhto z7$wj9y>_?X?-^mjENX_}QHYonuxm(hyJLU_0%}lDA=0ect5@7m(qv9jc3J8qW^Rbl zDBg4cO$696#)>~PjcN%3BT;mDVDF*Z^+>{m=7r3ucvBo~4ETO=u9zzdNz)9B2{{pD@xHsjcdm1mu6ohwb7%KF zvv06Du(Gzr(;1m-VE#mRA5Kc(MU7F7QlRsd}?|R^=oGB(NZ& z435F8nGzL6*uHh!r5Eq`;upSj%Pp^X&8@F_?6F6SA|I^QLyS9?^$b?#%gjnlIA9fN z!^RC4ZJeClxFKQ$6M~>%013fG8>im%i@$WsO)uLqI|cyn{Iz%9bN3G=gueBaP!UDE zsgkN0QsOA~)&d|QJ2oW|O%gWHq9~ZrFd!ocpqP<)5C<+AJ*@1|DD?`~STY+^ZeXgx z)Df3k3^Ox~xT)wPf%Qi>mV-i6IL^QIL9v{5P{AN3{)l4FOYB{X%uS8{6qRzlWELkd zK)@*NXlW~p7lo))t0^MKP%2p@wM)4*Dy?Htx>PKsn`rQlNjwu&214X@2&RaH5WLG$ zLyYz5Vu6sA6k<_m^? z|M%W==Uw-2*}M_Kf&^kDVi7?mQzZlgD|}&UqF4cdDvChf@0t0{8%71PrG=G0_=7*3 zUpgn=6O)Pplzl_--;82oy{HArA()x>9!$qa-%%8Oha4oJL-QJgaItmTED*Dqc@YEz zk)ofwgsM~(4xM%{;fx@OPZ5TKAVqR2;2;5H2my#!R+bl+7Ooqe2JlfL^FEJ=fNsAt zGBj}AHCLTH_QJ-E+m{xWjy`{6|8vj2^S0Zrz3!SPckTJcH@>sB){R&;3905lh$O0Al(ITK$>FGfr#8c+N9^gJ$^tRL-70hlmcPF;IQ^O;;~1EiEoB zhyKdrkN#-i-pcsoWLilUmRH6{Cosi+;Z@Nw_PSjr7BOb_z5oEQ=ui+OG_mqdf+cS@ zXd!~^TwWBe4&cK;y$%{G)k^00vWqVt^$q~KT6^~g{`8G+`Ss6!d(Yfj*f=^oC(2ps zoH=vN#z4xjyu2J#z--T+r;eRI(QMY$Of=ML17o8j-L*Cf`MhHm7F$ct96tD>OE%T3 zu96J_6pndfXgI58%~}HynV5;Hjk*u@Zm$Q1$SMjIU<3=HptS6MLIexuh@k3POV z##k5IORb&>kc;6Ka7rd-sA`Ig1dOiCps`ZSPXx5+00A&UR#i1q6*FVUW|8V3AqXL9 zS?3d%Hevv1Oo$;E5GBmRjcQy_5|OAeAuypLl@JTi_#Xt3Xl4Nb z1qKr!L)E}UOdLQJK~br+z#xii%wrdZ)NF}$`uHqDEipTO)YUOxt9>s1PRlU4o-l9nV08}6R}H~ zF-_CNI$^C{K(X9_&PV_IyI=OkUxI!&thAAmey>{_XukgK|MA8fcYgib_k8}VKOCOf zQ3T>Fom)8PmG|%8zuao2mBxX?N3u#LDxfk@txb$iJb(0v1|@W3lOvD){K=8Q!53eD z-Tgnjx083L#>RWCcC*oF)T;BKK(^RgnOj<$ynv}Pq6&wee_?uJs?#e}6;uF`m_kq{ zRufZDv!vei0l#<8PtPtDsl)k|&W|5{3XrojLqP=;)#$H_PXaMl(hM2ZbZTn)^2;yl z_IsnFBX9eaUp@5vp{IB485|vQ9Gxmih@!!9f`(=R5WsA3aOm&<;ooLvCiA>ESkDkd zHRS!g+in-4OKZKK|Lm#WS~shuORcptXXYnHh8e-kBNM6-05Sq1bE%g=>Cr7WrOvUL zI>(SEQp86P9J7@rBB~$+Zt@Qr001BWNklJK1-5?^U03llWbEg1EK#I0rW>+qcio%NuveLRP!%V7z z5^cQk%R!NlAOeDlX3jP1*|)y+&*2x|AQFxpJAw!&P8>Zqce-A$4Gs=Yj*cIB;iQnJ zsoSyRvL8SA2!Ik}T%+W94yxoBblvMuNY2GA-&$*>D2lZV4<6pL?SfYj)5Q4jt|uOw z*{~7Fye~x6%qm$W%d$!(Q!@$L&-<|=G)c4h#if3ybIpscOp+`C$bENa!&GZ^kt?YN zRa4^F=aPtNbop4xXSD;KV5aJI?bE3Btf=Yz`8F+wD%kXV)eZ%Il!A-Mc zwOV~A#sv|bkTD`Wsyw=HE83F)QYK@VxDR!hRd$=+uN= zbfM;XYjkvQY-I1#dj_jDLzEy>6T^r0?vj`lnByo!PiydS*scyS+~EYKonHZ)j}FB`H!6Q9^S-z6eXp z%Q;Z)lY@sBkFVHDPaFX-D-aW)bGZ*egAaj~)ikK4NkUPp5w&%@N(dnmEEIGd!38SH zL@~u5TCvXZZV0S&dwzYqH5)35R6MJErPK*FffXTBoU}l>~(eorU|F20_AjL z2H?t^BpP5ePnFJDLXa|0ig6!hYVo4Oih^e48a*N{Ex}Sxin<746i*buiHfSAAx8gG zX(s?PWMm}@5&$Fa*4Be(@gF6!vZ4{eV&$P1lb|M{QLA#ogF{0uabA^Oh6V!0?KJ z)9rTK^?JS0Xn0=?4h&_L6SBn$2u#sP=|i-*EBf4R?R}vny@wcciu2At%!_ z?y>WDAYGG-4v9&VT7+79y4K`{w zTzB2r=xAqcb^LvkdDn#+V41R3 z1v5$01R#yG4l%2mnPLPgDGCZX1~e1|L?#l|JTLma-e3P;fAQAW+$;c#?fwUT_oILO zM}M&Sf+<5oKt`HdY%TYCMXrNGGgn`G!(aZzpNj}0uD0937owKBB+D|dL2`A(Md1m#A4KqSs7`(95~`~4oE#plhr#D`GE9vMR@oWovk z?V@cLg}fjnGx92Apdx6d5=I7wpMCl$T(<3}kL;e=F!Rm5&ph(bLx^x-|DlZC0L1k`gaLt= zsaG{2L^PyzY(~tK#I1^&G9?5iq9Km{5zUTFgr-17>%%^-$4X1rL9~;rs3pL}%|_$) z|NW)^^=F?eu$^SJW__sB>Am;;AMJOG8*h5~;?leX+`s=>6)U7*mnv$KB{y7u-SWbU z1f8B5&(bV)0~cN}+v@t@g~_Q}sS;5{b|4}|7h~LFV4|i5YMD#af(ZZ`Gkfu%#^hY$ zGAWjqUKnfA$rp~CIWylcdcCz4IBLPd<}KO-a2Ve7%dfxo#y36k%*qp|+Q(O{f8qq7 zwzJM)H9L9c1emne)>clKK%2eKYQfxPj>x1BR_ZO@Xl?s%}PE!)qK&;OBWVa_dc`x8{fX8QXTAd zJ6W1cPK{CGHqKsra{kbF?|rm3*dzq?q1Wr90gC1tg7WfOkCUuksXIqmnnnvP2+M3#9?JJm?7kQA8`LV`f0~S{MQm1As%0pD&rlOb<9fi%C%gFokJ`I8e(_mnP=1@(2bS$T260i7R zhN^%}Dj^^sGe}HlqK8o5xpRB<&Wf24IwT(}B?+nT^BCWXE8Q6OV`gURcRLqN*SBw; ze(f#SPHz}TE8h2x*L&|n2%IK^^`;L+CCeO>D0I7BG^-?4A|U7bp$H)duy%VbajsTv zP7DvZ1Zo>*Ag3+!OV2#}!b-k$=In`J;l(ex{@mR1<3IlK^)I>UO>cO`9rrvCEJt&L z&5_r>?v3}}fB%mje)zU`-uBM7z3rZR?zN)-%9~%m|Cwi=dTRG;Z++F}m+g4+iJv|H z!VACh)?e+mSHE<}9WQ^y&DUJ_lHE@|dG6fY)~#Ec&1PQsB;njD-@fbNvu92<21dGl zUu%x$A$Ms4$c&t3SzhEK9svx|YkZZ77aPhNNd~<<$25~*g%>Y^%($fZy6x5m@+W}B*18jNI_%c6&RTJg=1$T1SDuil&lwY#LaA^oJDr6nISW(n2`c< zgwzp6H@Ok01~iTyvuK7rKOAVR2nCGxa7098L{trk8kOe~mj$3I#9TsIq9AD&S5#J7 zO4;HMpII5)h`U$?r05=7Z)Pb$32|{_=gntv#vw)(00ccB=qR@X5Z&@XXdxo3lK_Gk z6WtJ02uRA_86zfBhe)adNFYjp=#s(*AU<~d#FP6E508vK_uL^sn4ep0tt^vs2)x)@ zRdlQEyw~X{JpagJKNXQqC(kO`1)DD1vE#CSo*z80|Jj2F2L=X$g}$1aRMK>LW%-ir zTQ+T~SJO(~%>kgui=kRNH9dCx__6Nla`S4shKILridZ0%F8E*op-@wV5@n?+ zx~QvV?CK+f?bb@+^AcXJ9yK)tKt6r;jMwn^<4=73YhO>&Z z_aB@&ckax&h0Paji-vb7N0VswGe9&#L|}=ZO={si5hHS= z-fXS5S}SYI%gYyEdZ`&WAm@@i&($Gw3J~ubCL#ccj25W|0)l`z@S=%J&dtyD+U>FNaqo+SlPs+)ciIOI9IRHdtU|N1n@%2o;R|2--0Y^= zkNo~0KK;yryB~gPEe|0;l4WPkc52+79!_5Sy4Of=@inh_*+8}S>~n|v+MOERuyNzq zmhD&91~2{l|M6ExPITN{FcA@8M@*(cTtZ4LmQ{_sXk(zkj=iEXm?;yOqDztx)L=cj zTsrzpK|pamhKQiXjG(~8YHDhtQl3B<&j|qp!pJi)KvGeS@RI*`i4JHKNex7dprRqA zB$^w5OJW;FYk?V&P)ZDqbfO*kxCnWLXn)Nj(8K%g}re+BO7(rqocrpPEN&*J%JlrB)_>3_YUJIlN z8>#}NBA7q`09#2Zjbj}E5TXwu8YH1aKx#0IKwn}cO!6WRz3%LVWADH1m$D3dy}U10 zsHREPp&D3wtxv$cb{AO5C5{}JwfcQVA`Z^6&$ZWHlb~(rt*&;KPcPR7lFMhdLWURL ze9PF_bFE(g3t#$TZ>0-@W5Z+1t>vYq<>|@USKWBs_aA5a?(FGPXHTBov17;e*I%Dy$;!&g;=;np%E~~q(e8FT z{oeHSRISlGdi;2^UiBu`flS4$2Q`;^6%iw(YPFt+B51$J^E6H4H*BqwH<~gyG~Ck_ zG76y(Q~-{V;9Qj{MYM#|oI>tHN)7?$7v^7i%PSj=1|gby3G&nvPo&N@nl&WTU<^o+ z@eIg}8Vcm3l2oc({mBDQyy;ChU$kwe=oH4%>g30conpsKm2-1Tn>K7dd2(*=;NYeW zlTSVIRHHgT#F#MzF||SfQIeP$RzpGsU?WgdW(ETZMBr6ZO3;eD$kR#{0T|5G0-6|b z9ESlRn!YV&1XyFfnb0X9nn#0ZrHYIeBQ#KrCoeE#SJKML%F>4E$q#<;cLPAJ*6ek1a#h1D5T!;wc&@n(n>OBj)zv?^=f0a? zdDE87+c#{OJb38P-+ubjXV07+Xf}WKSKhjD)5e6|()_s-$4_>1Acw1~YXDHMXG^WM zFMR$BCypKO^}B_NshX55RfEzxL_kE8B#y`}E-gK?ci*X#Cw}jD-g|Iv_2B-4yLO#q zb=9O|UdD!o0;-BFFDNci@V2*Hf78u3NT8oSdGcTW?cvmAN)8exAVhU8>GXSQhU63gIf8+N7@1wluH9NQ zm86>0Yt6jZuT&aYrOA{;)knY_vug2@7hgV9ukO5j>r+qe-g(8P5B%t%+duiK4}auC z?|JuaMS%Cb_al$(+BL9!8%EwaSWpErQUZu%H(DnFMFbBbB?2BxCNp*O7`li%U==`6 zbwG*$31a{NOJdwZ(R)c#rx9Oeh-4{YFi{m`LLg88LnXjS5*I~wKoGSJRbwbg{Q^d~ zZuJ6V1j(gVt^D@;e|^(n6#$0Drat}YFK(Qkc;m}=c5Ua$`Q_~s!v(;uC!acT>UgbM zPmuF=e{E%LZgClzCO6C`m4$w;)T#M;hk+|N5Ix=K1Oc8)xRu zp1bwczwp5iexM)x?SK1s?Y?Azy6i)zU9rY94Y#Rfyl`}2V3d&vsqmiAL;}`1Nm3C|4?vJqD<0x_36a%H!D6Mhs3$bX z9K0~mdAEu{iC0z)$c{Cx1Y@$sm_W+YgUq0e>=3il%AeEMZDX&DPddy|;j77DC8_ z56*E20W3D8a!TyMm^cy(5FzjP*VbA^(eu5$uS!Cst0U9f0N9Egiws?b&LU^cfC5xBt@1F4?x_!qt`5me~ttW~T4D>#ozMPu%p< zm)-Ev8_v$1%@X(axBsUTr%o--EqTyuUvj;t*?IN)X?BP_ubpi^IE;J*6EHF zQmItQIY+EP`*}{_2+0u{s8@mDU6K-eBFyu=R;y-NTFtU?&OZIjGgn=8<>25zv(Ye7Bubt8`ak{Ca|aJJ2b+$Zh=Bw_ z3n8zhDF7Hj2)@~@-GARtPM==b_4Mv)hUis-3=Gr~N2~3=7k~WJiI0Ec6ZL_Cm8H&V zyEQQ}Qsjk85-$$?>VZdw2i! z-`w}%4}aiyKk&h?e&s8{7uzo0o~G&W;NbkZGuyXqWrAv!)T*^!5y0qy`yXhxR!4>g zx;-Z1b+8_)DHsGZ26RbMDzXM*5n zed5Wd`n~>+9hWXH%pE&+bZ}(s4R3t??%hw$%`GLI{NaE9z1CX$_S-+XxHw;{SDDdN z5DZMJ8Mo%o{>exG%jEj0o-P+pP=Iz;ubNvFqp${f%CMM0s5R*#*Hq34q9h?{(Oz*n$zKMy+ zty{NL5Fml8uiyE^o?Rl6q<~_;UF02$2PZgzJD&P>aAJ!SldWbQpiD ziUC)W&T8))cicBTJbv!fi68ysLGQch=-`>&zkdB2D|rXORkCz$agI45=G^-{6j`IW zYu}-57hm`AgOBv{{?TJc3E|{icgLchJhOla4h#>N!QA{pr`xV%6=HPAVBq^jZ0L%r zCt-|;u8W-j$e_ry{&j^sZ#Jsl=Ys>IgSG0Z)*AT!6+16H@W`&i2cMgq7zamGt=8(b z?Xw%tNTsb@#ZZIZ(Dcm0^G6+OmZm{Mnk0={%@>7pE=|+Lm6d9mTy@noJFmF3lG2N= z+EK4n4;*;@!N+(1-+%M*dZX5?4`@)Ta9VQ&;Of#yo_p)-Ua|es3m_fM z)lQr^^RuTOy!*j@=jN7%21a8mhz3bqQiw<9xE@gxOsEJ!RFDYRsrP80v0q04$RZ6+ zgF5C|wm@aUS-E2YBr^eG)qv6BZLvH}5s}W*XxC}|BC2M@W>Njs;Fu9e%>W}uPNG2U zg91QCtY(0UWjaSw$0}B-Cl7Nm=hC9GzZdWksSP6GT1?ssltJ6AcvO(BcgYlp+_@ za6OhmXapu=poT#;5IIH;P^P^h7Qi7|uyq2NI$}16+>u7DQLof<>yR%P(K!;e#9@}E zSgFJpg{mV*$Up=j7(#B!$Wm|AGEY>k6`)CyR8u!IyAhBvO(C7E)$@IO_q1ERyq{;4 ztSHiIrBbg|6*NR&kfG-NyYKq$spCggq+jI7&WleWJouv@E}T1)B+1g!5)oFjtlRD# zJ$`)uvrkV=Pq`r7Ja2c`R+p9v?{B>E#(ux|_)i}_^1`w4@zK2Soo>H$cd|t@zW@Xk zLSi){DtsWMsmZC<+FIY6C#$8PKL zK!C<^$rUjd7NcrJF&jxG$0dgMARcxx=x<1B$k8RXJ|)DV0ZXk^jU0huR58l<45n`y8>EY`5-FBY=EqLD>05oYU|ZtW^rjt>j=vzCdI>rkPrzVu9#z=x~jwSeOA8O zT=_9oh@6@^c4~_2tN-!~Q8R#-zx>9@Mgjo0{m0kcamRPAylUq}Jp}*-n0oPLm+ZK# zn?qg{j?&96yDTsID{Z*x|GZyxXE)D2_`oCYd*5#j4-L#M&OLwR@Y3Sa zqmMlDi?4reB?0GX!^Vx()IImy(dQ04TdgD(LTzZs=Xtl+jf#PRC20~uV0O-NOvwm< z7ej(VZn_~_{7Ef?H# z-}jf7J0kYu`Of1{ap zJDvy~rDERJ9|_K~ejaK7lN&b9pPVCufks-*Tu=#A%_<{fW1IKx+jsG$+r}m~9J&AL zZZ{tssCe&*D3;Ow%Rk=%pil04s#&Y<+q>`hv7?t?amD98`{hr3{4=M{oN9H8(ea6h zfry)-sLLxEmKLZ;+W{0n7Yzu}caG{1!0CDtHYWPb3=ma>nHW&e$f7C14Adc^5|}8M zi4cGoiR8{D@tFYx0#Xsc=!oG+Gm2FJQ814|5!MnDibx0&xp#!}FJJ%4+0#om-}F-S zmbs);GVd&M$Of0)#_kSk;R!2=eEx*oIN%DqN}5#<9q#~=HT37 zzl^vh?2$A{7-GAP7DZtSS(^F~LhvG@MY#Wg2OfI(ky<^y>Z&WUtn#zR9zSzxVP$f`thZLY>u@In{sSgO`(hLAqycVjE5I99s@qo&X4JfFQfrvuv z4}=KDO~pjZOiB)cQUCxT07*naR1hGh2B;?0YAQi`MS&3;9J%k#A-IBrp%~OdFp0vy zCd3rXfI!8}6v&t;sFd$85dtt|b$oKZb#A3QJu^-P8w5t=n3QtN#u4DI0wJi802(PL zsUjmV248eLtDUvAyb$U3R~8obKlA*}uYJ|rxrKZ0{K5R$bNzO=kT5kp<;_l?J@=w3 zcg{>rw>rINpF5gVhK7en*XHNji)SBtV2%ik*oz=QB}p5N=Hrh(9NUqI7>N>>WLaf( zapCl-RIxqIM5+>q7!;7os;_8TL5OVM63B}Rh7#dK@$c2> zeOLSc3N0}{T}qhI`h$@~SC(yH$<5YymvBiU(UO2=9Yu_OdI-#_W;k`d>)*8)$#?3ds;?j#R-?wj1zn_O72(Yxc*l%|tK6P<^ zVW?S0v{3lG+W`w;AVJbJB{W7z5VYvKB#U%oQV&70w5H<42Q7TR*Ur1$Z~x0bE-cPn zzHPGx>9yNGf9%2CyDGW&Ys(AYzvEvAGN@0~kldZ${nqkQYoO66`u^ORGtN0MBT?_Y z2@VdA&TPCC6E{4u31HC6)62`PT5YHZ9^&RXuIC6{l01Fj`QQDck8hZse*bU(r@ecQ z{PgF$Po6mExOVhZ>xn(jz2ur}w{E+5cyu_2YI|*^0*)*pq~HY&TWc#DHcZdXZo2=+ zKR$c<#BcuQd%pAS@BHk^C$7Ez`uDu|H0kcM^5PngI}uSeWL7a!jk81Si@^12 zGYP;L)1U-|A`*X}sKtI?10yxGD1gUKqIe@kiuD)}&5o?JzN9n~a;QiKKo;AsM3fjY zz7znXTT7!|C0gC$1RV8rFa-ht^#ve)?2rC<+XWl8%#QCnxbVS`{I|vV`49c(d*1%m zUp%|ief!(~!^C*w5C7;B4?X+{h!InxSzBC~A08N(7#n~7@bk;7Yn^^RYH;0k*B?H7 zxc|ckHeYz*Q%^qi=pzp+Q{tRjxhE(^bB3ZQ$bg))^S>fPk{FRx0KIAl0?lE6bV($7loOTDp0T>L-lHx-BP>n zms}e6);7jpoU15TD@MYE-x>a26;q^nE+mYa>^_-0)d#QnFe4cFcOn> zY^gDEl(*xw6070>l!#2qCld?^$pMl?3q7-Hv?gkFFUF;iX{p8|kQo#ZKmcPkP>Jy6 zApXdaqh=x^scR5;F>}hyrVu2)27)1JT@uUCobs+&%|b2gq#tW5iR!7Pyl7cEU6zlw)Vk4`{Kr_ z>7oCJsrL-i^QzAMSJ_W_>-3Q{>eaGk8QF3b*qClpY;veMfsjCG3H6@@Qcg@bkc2DY z4<>LZNo+6}2pIPQwy}wE!?tY8>b;Cc(#&YuJ8yf+-fNu?`x)o>gRjf7JRZ&UJo{by zUibaGdwUiy89s61*s0Uw0vbeN%uzWqafHhj*EerE_w3Xp0{8U}j!#ZZo}EF8kBy#a zwOcXL)a2Qr;r_YV)0ba#{xxqYZCt%Fy!MR;4;|V2(vBq0-}=_KHs)rQFI%={%LNW( z@BS0}_Kt@2MOmIPK)F%{!rVDSti^Vo^4wO-RYhfHLJmyOO}YZER;xv&lFf1}5~Z2V z^G?$4bUNj7xwm&9OVe&QF(!<{G9g&8;$(7q8WHOCzHT=o1Z2vxyxHtrcF7f&Ua~bP zhs|co022W-hei?0Q1C&7*jQ)9>hR!@6B#{ydU$wfYG$U}YMUU4E2RLrRE~|II5e$B z>zUs@E2v>$12D{mLDeu@>p~L-q3PyXsZ^Snn0xHSqn%E(IX%Ds;O>F`>N#uI&doFr z9yPnzrTEA?lg$vG)>|-oS$#@_pn-9kWPrLI8;XT2OYdDVIYu*uZa=wWk=uU z>-SRJ1p!q*sT*7vrBp3Lh>dU1OSIfA{v_5y4)f#vrohrAoffJ(o#7( zb#m;Sb?f_wdRy(e=KS2?V1IvqKQY9m%G_*gcD~h9jaj)=tIy2OHyX_>wcq~k_vTwo zo99US`K|ISZ0 zowKoC9SBO%y}x><6!ZmTnn^RPmPsg2b5W~^^?FaEF}HpD3nzw#uDRygjT_gdnf&IF z$E;wZkw5+Hu5FiJ+BZ}+fUP9ow|{RCFp4_o(TD_!>o%<2ymrZ5w|>Vzpr z`NuD>S=tW(6KDVAAHMSSg-#4qTkHY-bn4U@_AE~X5aSgT5ilMyK@94OtiF5M-Q;as zP8FC{R8)wOJhn&#i^s^Tc!Gcid?uBP`ZhmZ3j#u}P8l!|{;1iKq2Wb=3EF8p(%>)u^0PyW7T_F=eBQOxoXvU=bro6V~=N9{)x|gdi>1zqmTaP@WI2KcDJXm*RuoI zV3wu;z|82i%mSRO%>MT6y=vgZ0vQ$!(2SoRAD^6BxAMGdsd9SitW_NuuGLwiQaK0% zZ~_PrxU;8@T(D|m!_CJKl*l>nuMp=KnE`W_X3XTQWd)23f<_u@zyPjV3mI6QIu$D! zK#_D3aj4?c#R?d4oTMoSTr)kYnRS^{NK;TCvCbg**0BN>i6~AG6$z}mfK8qyLbj}B zbmCKuo*V@L$i6p_i6ym30HJeEeOjy#XA9BjG_uD3aXD{7nRbmup0Nq(;^+`55yw$CbDp! zLqPZPtO24tA{Iny-*%#&*HcL z?MF_^(rsl~w_5KZ!-!;^S`h>!L!fG128av>0JA*voeoIUN;+vbv(7OyfI4+y6opZ= za>dF&`{XAk&Q7+PEn-7}aTt11-)|p({Ml!p5#gv5<#|SA%5kZ$w`YESu2!#I_qMkY zu}_IdVJMzw%*aSl91*cN5mE1(aw50>_}2R$e4xMH)9R#$4jrnN%e7h+P}5G=IqB=| zJ#XW=d-m<-sAPiB77!6-V-(a820<`!=FIZNy)Qid$U_hRwzsD@4#Pt(o0*(CefreY z)Ld$%(V9oV|M@@P`{Yy4Jo4+`ELyQF3_>Sj)jFSxaUQiOq7DI_h$1+UKuOVu<(w`k z4JfLRp)OA{tu;vyb2;dbcD=Qq?Xh# zXaT@4cm43>?KmE;BBUfB9>RvIh!}+7LhxJ3yMqzEaoF0t;My^D%9a&D-8^wFNK$0Py0Gv-SR7P$Xki;ceId!RmEu-}#Q~x@mUT zop;@H@4cHgp4&}22M!&4=eyrEGBWbO{rB(QyXX41Tx+dsC(zs1pW3`9qSGf&W=WD} ziL+_FQax|uhSjT9&NW+)Kk-B-OQIk$sEC|f8=F8?8Ic2%CY?^V9S2bm27r)tyMf7_ z&Dz~2I21{R!jTm#U-hb2J^s6=`uggF1O2CtAIimXAid15ea*HX{q#RG=ZpzW5Qs_? zM{`Lhgh16i`0%s$-t`2UaIW2~)`vNaI$0W+fP9dFFn8drP0}n3Lnm_V&?YmAiHo3=yf48aP(WFMhyUSMN4o5GX+r9RjK^lt4ix zU?l(uh_%q`2*?q!hGfFv|9tnBuip6WTD5$3{Oq!kMJ{un|J>i692;A|VO^`;I&$cE zy{F#O)6-3ouu@KPEm!K-z5V*0di|+qpPp^b2j#fcX}8*)EnBwSeb3$d4;*;KE4KXc zht{;)?Hg~r@#xW`)oK+0oVEU9r#jP^O~sy>o6cQg zZ4QK^rzd-shgsIi)Pc>RV}W&kZvNT*2eNJoYLl{-(@rG_3`Tj9Ab<(jf>@g&Kpb+Z z6lPXC4p0;`1ttPj7G@NY5Q<G_*#uzqia~ni)rB?gh zv)kL2CJF?oQtRy`T?AOPXwjL8iM#K+ zKTVTPx7*j#Qz?~a=jO6JM}RO4owJ4w5;^C*f751J6h@hDj^0y4F1&uZ(b?()Bq|-Xtb#AWX~CZ!m;6v=b)lO zzPj1h8BsB@GhnX%V(TxTTIeFhXaas2^|ApC0UcNmAOPp1J$|~t!WT>4G4I8YBJ+&J z_D2Xk{Sf?Clz3tVZ41|VShwKN}vGZ1XPIFiLk#^dG!`VR0Pxj zJLi4Ioafd9OPE+iiY-{7KOs}l&DvWoUf%{y6T5rYzS+k7=&A9Ec6MrFZgz5NcDgY> z)9N1@D8&`!;Qo8>A6hiHZQJD!Kl&IUtXsEkWbxvQE7^=gZcqK>=;+w^>1t0s zVp4_NI$G#gvLJo^Jt}N5ICk_%o~5MHNxRN!lDTfPn`a#pma6sU?A(maQ*|!SvsOE^ zxr<_I2F>BY!FsKFV)Cp7RfR0e%asZt=Rip_1%OK2A4TPIZLvdXG-k5QR?0Q7np?{V zE-!j{fJm$@#ibLYqhJ1~uPk4-Y~swBI0};_*}3b`?p;TdtSe3on=lU9kn_d$gdQ*W zkSic9s=^Dk+m?WfD{3K3sQ$Y4e3QN_;pWnY_!&Pj8k_l>y`fDpTSJzxVnfI?>wtAw`9)0$SiB_`2 zv`c|FhYF-%od5#5+?L}g2%@Cjm1N!~O;N`fC=e0^0xpiJQq2PsSgR^Z92jGLV9{a@ zPLg(O_Dn9Rf2lK!6bzYCwNz&cGMA~U=XVQ$wK)-ogdid!7$D?gkTYk+ds2zKBBKk3 z7$F8^G$Ly=zZk`ropU0JB;L;I)W2@3&~>o_H9ddPDhgbn$#7Qp*qP}Bl=MhPGx5oX>1B*IJv{ppNCNa7ScVp-G= z(WHQc0<@t10Z_3LS3ssf!Ph6MQ6IN49Eh_5NKO%n0i1t49RM*Sk~;rUZJkeoFoLKn zBFVyp)>j6gf6b6sv&<5QJ~l$gz}o31%a*Q4k}R_hQCoQfIY45YJ7BhwqXP$y1C!gF z5Y;&naY1B=fk+?+qINqsTwz6ZhJ2!fA^{t49+gAG8W^;;>xp*|dfy8vQ04$BG;tIJ zJ#)DWrS>;px_SBXk>R0!ac=3z(xani4xBiBVsx_GPO7yU0&*C}l}esl@vSoAkzdS! zD$bjbJnG9J)N1u^mgXYP7NAu&0dd%EcV=fAM~|J@wP(N2)DTlex@9k z!XPXdBFs@#O420HT@;tc&rIfdrU3JEO~2kS93mk@S5(=MiUd)h0M5Cj+fBRO)vH&( z_NrG;kB?t<<+gWSf8~=;4Sajo&Uak**5O5qf*`PY`rF?=RxXthG0*duLj*Kz@-*i- z2!kj|(%!z_9s9>NZ(Qk68A2=he6z8%wlt2p*-5fI1*)DnJ@@S1Q>AJ=(`tudpjQ0O zB2czgK@i!1IK)6TCn5&`icTB?J7<|#0YVNC5dcNh(8A*n9&Mz|ED8byK0FKvsHC7s z0umsoQzrHtHx)%DbV90LAj}C-fJF-t9(^ytf;NMK$lf_yTt^hpusC6_iXe#;S5_4w z0`W{PB%or*P!S;Slf{Di;%~VA`$6;_%f9-~fmeJM{?dgM_rk(VM0{6@;i9+{1szy4 z1^^fkk(~k*JsjYQ4<8T}pFdJiHpW-X1F@=#xW$W?e(CSO`M23WM}{<)^&8hd_~0XV z+KTmtSE7LCYKX%iELF-`o@W*UMh;`h@=C2*j^kE4O*2c( zWRRGnuw;yOI_)&K<}( zx@-RH(MOgp8@c?#b6$DjIrAy>Meycr=lAvWeeLW2+Sl7#>+4^#c**qC?9P{VU3TfE zy?uRsLqm%OhH~eIhnH-B;YB3A;__|BPaG#hopzGvjwuL&z&XptsFJ8<@R$~2AY%X& ztco|`IQ3v74mk`k1i-jd%@yMyX2NEkX;j^HV&;)&_my%Nm!fB0c#>lL`mHB-pKy&d zt@l)V&)sOIPEu>uSsNfC27*YCt7;qssE}u_+isNY)CB{yaplmu)ytNQEOMFb+IjTp z1EYH;&-N}^8%1UIi$2gGKtfb!v)QpSk6*iG@Y1apEm^))T=3Wv2M?Z{*>imI>{PRN zU`ZH;&gO>LS|z5?M9v8#IuQnN)&^myR(&TLsCvqprx3pE$OT{j9z-h6Qy0V=mWb5{ zg`B832dD-+l7&5s7B62vKHrWjh7gAq2N+NgL}3^Ofia*l#vWl z*nRk}5(7wzN~+$NMMX5)7%p%v#(2-2bIxd?4Hdy3_IU>)1tD6Pp#5UryK_lNok12S z-qAw-K?ElVR)By31kuMT$cYjMPPO2c0wRGp^{jqT526qTqpA+c72-DofRfnU0vbW` z%suM@V+?{#({As;K&4WiYmA3sjhM2`B8#(5MVz<*0U2y=H4_NfQ-!UA)a98KKqijn zyImp5R1A_5g;7k%NtyyiQCLz13zSJJsjF2gKx7sCl!*uyawiI+X-AxNSlqGG`yk*f zNwO?chf%3+RS1QVfjBOgoOM#nk^l%O3Zly5FXbT4M@K-h*=){t+MOgrWm))wOY+^00Is*OEdok6`;4T59Uyubq13(MFB&RGmtp}ux!0B!OmKyz=;du zFgAe`a5e*9trJAZR5np3X`3KGh3Tp3EVZwG)vJ?EGfSZq$5(8+ahN^;MgCGP8H-G;}opfG0t$}JKh)kstty;c%Z0zKVI}dbo z$R&T`=_h}F_b-kgAIq|AN#B6y$5`jv`kbQk9a`dPa?UAO9 zZ%_Ti@e@(Nmu}tq{PWw79Y0a4)`&Q_mQ}GZyn+*_PLU|LHYNy|daCvJyyut6r*eFye;lP)5ffEtaYT8Wn|8)~<508q{5o1Nx-!#`k4 z7BA+&h)BI$P7~|=?vSV)mojVfJU0{oqBzf}*N6fiWL+4U6+w-HE40Uj{ib^FmscFY zi4c&F0I3%AFhKwm@|WC&@fZ}mMNHL0qzm=k2!SE14i}1DJRk#{BC%ichHP5R)+Zt7 zumAuc07*naRM)=w({forpOP*^x?xN2L}29@YJa@ zAO7ga`v(SZyX}toX0mF{y6rFQc<%?^KQuVRWOnb`HF0KQ#ZmZEU zWK>bfpcIpN(NKZF0jpwWEg}dCpovT*S?)lsbD-2|CtWMUt5%(DW_|UVA+3=csHS(^ z|MZ97aUrAr_VJe^hxFSlM>j)(=4Vy`MdF=OfSC{>2!V6)|9wIdu-F#}9AY z-1BFD_=znW*CQE+;cTP1VeR>Ijbz{9soQ_O{h3_{BN&Xs$XQVUb)Hd+xphd&Yyvlm%Vs zaBLFi(oVK|@vs1i%ScKNP{DbBE)y26JN4s|&$s%9B2*D%a*F7jAtWWQS*fb=-(n#Q zdFP5Ji7sr-W#KNjVE_lj z(q+#)^%Qe($we1D{mfI%PHVo^Tz}4n2OhZh(6Nal$H#Ij`}Xgb{Rc{=^7iMRzvQw@ zw{3gX{rBBxZH@?~Qe?%6IfBVez%-?_Ut9y3r$@828V~okuoTy-JDip=vfZ#*`R0s_g zv_o9z5GuSKSS*FS+T{EgOvQ=_3lP5e(KuH{;-bAsq^Q8tg_<6K1wFt!AJIS&j;Uh!$Bs>&Inzzjo}OMbMC{{HPQ)n+6N3maIRbG2;sV3fay+tR(b({Co@K}j@B;*A zGeR(7xNPaj^vnzyt^|>_kY;I}$S@;9-$1{JYs@!l^&VuJpKo{4L_wOJZknZ{VuC1) z!#vHAI2T*(sV^HD89g<6W@@6h+Eb27iiFmQ%Y)GLRO==P&Q47)UDWfLFMK8n@~57C z3NqTf`4vG_`Q~?Sx#Eh;ryH|-_w1=ws&Q1>xpU7qzW&I>nQ?J~q^Bpw2M34$?(e=F z#ig@T)6=u_QKcd}Q24-$1tqXCs-8@<37{0Ak~l$%^1a z$=^@~6cq#+7z(Rm@p55twNhX}2mVeAsz_`Qa+@;+{tYAs70ZUyIqF>)jn3|ne#h#wtJhwp@?Ao=v(@BW% zhA-SOG%)1Ue*4?sK7Z4ucB}j1OFL|y-}lS=A9(PA{{De1%TAp-U9OazYHssRvz=wu z7&3;4S*#PALt$GdE0SiZ>!eW-3L-_UhH~bPbF&EL!GT4C{ihqVJ>}|fzZu=Xv(r)p zyz{PKbiu6bS>9)ZlbwVrLrG$%^Q4A_tJEnlqvRfMV$(cn%$&aNt=IhF``&TiZys$< zoj8Bf`sGVTCgx|4Oz*k);>$kwnGbE=ddZFd_Mfe0S}K=;0u-5<8eO+kzxKsX8_wE} z_U;`0<*y!_YtJoTGI0527q4AC@VP&I-=BW|AI6&oPzT$A0T#9R9a$++PxL z;S^TYg`*5#{uM%04>k7+ySjpNB@5U$1p#*Air%$`;j$I;R3EV*Q(n%!p)&71ib`iVzd3WoBan006a;TN9X& zjUyq7ZEmegL9|?oHBc3dqlm*$kcf;GmnKrmTgXh!GV;IAI)ALt(+AK$QU{hMC*`Z$heXXlnKUA|_`YDDa<_m-k~cCK;r zt+!mc?Ump9a=|&9daJz;{`%J+ z`RK>y<{Ce^ ztFJh3S^s&@U z;w&J60dY>9m)q2MehGLz7d-Q^7|$7su5m5){Nfat7M7*z^U$am5P2L0AUe-S0Z)wf z)yf4crRZYx=6L`{7PTtk#|kVin}v^Lp|@H8d#AI&`BzavVc;Umgox^!1iZ>Yf|fmG ziM$Y3ybe}{y+^=TK!X}%RK1ZAeC4`#5f{PScNsk>pIWyI`>89IGj?SyXu6+kOR&$40 z+9lNKsp;b<$LjsP+b-X>ke!RkmKTwNxriO--MjnvUbR(@GGjx2H!1qAcs? zDF+4tvOHV2Zr$b!Huv=oE?qPU9qxMWl>_V0;<3OX>RNF>UaLnjTfvRi2&~X&F;_sf1kbf+Ka#ZxsQ!bwJK#Z zP>uoM>o?zh^Y?#P?d|EW_Wa~0KV7n9>D5=i_Nk|zJTq~6>GGBBPW$xuWS*v-PCJZC zK@|1(4=f&Dbo%rurw$Bdc?N*1Rp1JPQrAx1Q^IL!Ni+he8IkIu}`h8R3!ReU*((B)J ztyX$RPn{YX8tRYv#Mr4;3k{Nr)Z_HBOSV!}J$m%WbIj;esdbJD-odI(2mFTi_?=Dj+mrA`R3`O%icUJSR&6L6wL(6)4`)uANWMv8w zQ|F4SgKu+i4jF-%SXG^XV~6NVf~b(4)nKdBPP5eO9frMzp(?5t0T2Qt5nt5K&KImN zoWI4m4L;F^T;MQ3{28qZ;4i7*`7o$zP*mCf&qS46t}33A;*(ay^s=obV03;k^ktGz zggE_2gFz5$fzW~GxvkZD=Nfa96H_E8&LL3lBuP@I>O@2Ytlyv#LE%C3jnpE}5VNcisK`_7|?Z{(4nRTHRGES06fb;8zbmc+Q56Ten`cd-tB7|NQ6Iz3pwA&O3kc z(C}+tePv^AKHzA}g%_5pm8)O-nq#-zvi+H7ue|E&!J)xC%NLD|{Q9xS*00-e>7|>d zCRcs zPw(2b+l1!g3%As&wJ?mDt@&GickMTHPmop>H0APIO?TUor3wTKEMqPHa?D5)}% zfC_Noj4!N)ASw$%9?uW;(Y9hdqQcQud=mJ3sULXAa1kX}5mZ(XXB7b0-xCmseQ?h& zdT~L%CPm-m4oELoeG!4PRuzeu01MfvfYG7vJ}t`P!TIGEV6i@O&VkjUm&O}137m*n z%f2HO!MPk2nT?OaIuH~xCJ0P;>#aY0$Mx4vPL7YB7_C-&voyc&?jNsNy=G>vd3LTD z2W7{U=lP|VUm*->nq714wfpw$kD@S7(y*s@^ZDne-OiP-zUsaQe);gP9$dU=$@JN& zt*^Ln^yq=PM#nlUgn*i+Nf<@|;GD1_A~MXz7!?H-!r) zAUu0!>hAl0*_t?Y&1(z$TU=Ar&l46y6ymbkI%m+4)ukAOIuFM+Sx$jh#LP031iR-SNmR;>8QM?St}$;fM8|GFoic;dwuU;4zKerjmApAaAZ^`k%k z`Op9KqaRyQ2V!L3Y0SmMyD>p4@$0G%!Jpw9L$?8kgeS<~GmOxiAQ_PIv2TUUO{p)B_Ja zHZU;U*n4zsD*N~C8|)t#S$E!0t@)c@{-n3pTz18p8{YhBfc)`?9*N6*!3F1);&5VS zDii1(?E9O){mYO;5Ql71nk|nvdxwsq+GN3v!DuoXq02LHx1)SknoB~1= zMR5@1NjJ%I=fWtAvLvx!!#IeeI8C#Osk3n$FtG}Dvs6LFi37F(VMqXwXIW2A4-+R@ zLQWOIk`f>T3OWk~Qp7(ih-6IAoSi*+a#XVHoV9DVKl|K64?p;pYp=cN!Y!3bWyedq zj0yV(22PHiWTrSSjgFo?@7#^`T4{D>ZqMHR~TJ++>1ed`AoU%0i?Nutm+=I0*$&6%@P)1xPjA0Iu&gp=bFx8MFSpj65w zh@uO(Y;85$R)h?Xjhz}hIrh%q`@JPgM|SVsZJmAPD=$0$+>Jl`*-v-uc(D|fKs<(6 ztvVJsGc~j4;IXthJv%d%b>>T@pr=|f2Mvd2dN!SyX`VbeRxX!bbM=)64<4GFX%dKu z0-Gl4yc19m)gYm&LvQzE5rhB=f+K>0G5{5Kb5-^JcJRPzU@Ev;0HjJ#*vKs^sVbop zOGvp05EeFdprXPUUS2cFLfQwBjCYQSh_?uMyDk)hDmd^aTp&Q-5-a|bz=x=%xT5+m zDB_d=hzS%#{IP&OmO%?qKL6f=BO)K{_BUIvoyY>LYeClm0DnVq2uz5;SQsP$opb)v zO94Oy7XFlsBwT!?sfvOlFZ>azDvR$KQBe1jAOCRMmJJrb0et$CpL^#!uYdikUnu|% zpp&`ThE)!%SQCUF`q2A7`*-dr8GG?F*o1d zx9@O&35ORiK6Uz3yW16qabOK%x7|f&=eyl{xf+Bu`mOvi*)o*iWue$2hM^DY{*tPff-u>SFhYvdurx3@r9XpQ<4)y)= zm%rM-@8JLb(%=5eKmTi`(sOpId7{xgIePZH-?_Zu>pOdP5)VAS=;G!U77~!m`%A-+p^`tn{T>_ zO{trJRhgP@0P>*|r@r#7?{8evvt@11@4w^CD>f|0$`D9%xT4~eOqg`CwA=0L?On2X z2@|PvD2gUf5=6|EPz#=k0;*c|h&CtIyh0d2ga}~a68~P(5mQN z_WoERBw#MW1RzjUn>ixmA^ECE3J$rN|frG{(#|=94tLY}txV(wu3x zswxhghzrQCqy8I%DL~?K416RRnMhHsbB4%gN-$ut35qY!5>PZq=y_&7tBg>1RR~z5 z@SYS49dM}Z7eY`#N5xaGe6~o6QN#b-2mqZQNRSDD7679HT(|@rfcR-#7Sci9Zm6i> ziqw)Q_|gHVK5Kyl3UM5FyXn~JGhq|}LKsE@UM*H4Vgz;0qB0v5t3YfJ!~z;JV8XzA zi~zxk4MOs`7bJFSoy|d&5JH1tIi7DfleD8QK!6}HLC6A`f~}Uym1=c%ZhCfhX5E?% z%a$$fcH295?n%=wA{izGgG2(5*}T8EFEk+=&hj+iz=|rObyfx0kpDC(2mwCWY;7Eu z&Yqq6w}1bSx4-SJ?|8@mxcQb_R;*mPX7!p!fAe1xQ&T|jyJvs5YtNn!eeeVCdiT5T zx%b{?r~UcQ|5cji&%LR}UaR%K>CJEa$xnWg=5F`yJy*Zx>Q`NP(UB8Jlce*eH@u-SKMw#O{NRU( zU~YE)p+_D$b>>v1QYpnTsMdOV>-Ani>h10Q<3IYqvXPd#5*y0g@EB0T2;JcHn_S9&zvQl;V3vLDYe#-(&G` z<3iqnd=^QIg(xB-sXxJioIlqU1Ofes;~`q!O9sFI&I%EFQ>znK$nRRTB#Qb?EULe2 zf*NBSI9DJZJ*BCTZNv&PFp?-Dvw-zLQg5~O-?azH5t5He0jR14Bwsk=l}|)fPf}B` zRz!q7_Q!a~u`KLD*$1GAeC-mxjDA685XmwdMCIG>xO>&APnJsYu3dX)8?EulnW;|R zZg-lk_UP!TMoU_q#7Zs_OwG>Ex0(kJ9{AYDKKk6#+ZT;2>g(-WzI?^_=`&|epMLYT z*DM(x-tpoK8#Y|hH#k(ORw>{;yZ4^6e%+@&@}Ye@pWC;0-{8<<6EGmCSl@*N!XUt; zK*sOa5f)S>HlhwdMQk_Agoy+1a&a5ht@Fy2*reV&RIAtXJag)XhKDY^XiJiGi6yQK zO?Oy8kYUxD)umFYUazTQrCcN6Fb*6liWdtsOYPF7OJ?Tg(mWG^JkJM)2F~An{=vgX zkhw8Gj~r|~e^aSkZZzlj9y_{X#p-3N)|@d<_iR4@{Cgk#&54s^eSJf> z{o?kinJJD!GC{qs?@Ryqk0Q<(6NS;c-}8Y|xx8Z4^8dK$r{DPI_pMF4-6RT2xzpLX zMrcA-3dv~MSWM1LO=ekQLEBjpMqwO>&gEec3V?rWR8U13S)4;Jl=w9e6C$#TVo~kj z$rVJ#Ylj}q#bCq;&mzDV+_8biwKp}_tyamICLH_;9n_aj7w3w!<9;9 zc5ZI!&~zA>a-|#u#yPE*O7*_pX0z2uI$^m4q)Ds2Xwj1MH*I?QcfZ@ScW0$iNz!ET zqD8Yavl}+7U%!6c)YSOQ%*^4#$5t#~{^?JBdi(Rw|Lo^K>$F=YF!Rm%=bwLm^DADl zW9QDmm{luR-Erp~yASL==iGBI-Foq%Lk9ykKfLuvLyJa6maW`$-gyrkI~gz)ONa^ zlHpPqie%Ph$N)?s8H29Vm>RP!LUfu%hVpKw7BBAY?ak(0RB?H;vt#dp5?9K#a$jE! zS@Sf@l1$b4=$9bnq9%&PUqT$JbEsmN6hTzePTM*g1YsqP4A6>Y%K`T~_kW3c?{GV> z>fCpXG3WfgZ+)xns@^3FS+b1Wgq+-SZq7NJOYW1x4S|pl z6EGwYY>dIC7!xoyu5y)&EH_D3-_qXNebukbF~cM_KNYg4POFH$EV>onP zs0xL69w2)`qyWqavyW=1HODAQCZ?u4?XEEfs|P3c22}t6AOJ~3 zK~xr63&X>sm0C48GYk@uK~&+u)1gp#TIR*db?eW}%nigdl^Tw3Sko#RlB5~h(rdfban@DpNxjjGs?F02zBXiEe)-inih?FR z*wP>la(LknKmaBnLl}T@grouLgG`1rz(hbzSkjXzK}o>^D5`=0BM}jx59`K|WJWMZ z!X8nD5C&rbV1Q)dU{4e5C>o5n;nWUL*)S|aa0v^jf#A?J03j0>wl87GKtKs-E>Tb( ze5G{Y4j6cROT@vC7ga(Sh>@r=$WgNn-UXnZ83hN=XB`N*1IU~zh%#C-it;Oiu&Sa# z5nei%P!)_ZK~)wRqy-1dTtF6Y5G#>m=0_fV0fZp@Up;dG93$qLJrAXqE z_rL%B8@8O4q}BO_#jkwrtHUeS4z1gKd~$MG6n7UFUw{5(*S`I2-~H~lKk%WCeC?K7 zUVY`&`sh$4NlGpNC5qy-nvRZ+o;ZGj0WZG%@&_OI<%Jhqxc%(yt#13?dw+3y;`9)i z$VI-$$wVT+EH-j;^K-Y0owVqVc`|i8%sVAN| z@Y-wddH1_N{Nay$@rz%$_114ME-rRDoj?EY|Kr4o6ZhVCZ?&3w;kkvmBzDG<_gqPm zv{s#%nwp%N+O=!fk)y|wN`;V)9zQxgJ)Nd$UKTEjLD8b=70fB%KwPpdHjT4h*V@;4 zdS4fE|AGH~+lt{8BWYz8SX`>2b%>(Kd9R&r7AHD1)O4Uu8ITHJTC`khKQAG6CQjC_ z-#kAzGuQ4fbUQ1m>Ez5rk~kX^0J}6v(+U*gNKqshk;suDYY>ZmUNXnVfm%aChQNSP z^a2J^KmfGTtcquWGPYDA^vj$q8AK5dvYM(Okq8WqMDh5ar-ud)o8qAKT}1_$6b%It zfjmpqM8fDjgDBWyxPp-ssq-b44W5swKX>ZrvDaR1)EfX=dKOhn|2gRrqS62v1Yu+V z6jd8oxFMT>7(fhxFBFDol!45GUP?noeAvw|VKD>OA^3*@gXtn1X9mCnDT1J2&=5ft zIW!xA2r8MS=(lyRKqOe@5pYMfb&kwN{HT7#;d5F?wkdL5P05L!Y)Da*Vkg{nqmds31?VR2}Z zL@F-cb?%Pcm+bCz`geT)CkGC`7RPB4CoS%^XW6%>KXAjZ-EjT&fA!aYd;H*Yl#Y;A zt);c=H=LT9>}DLrR#Y3yhkWT@*!S|>!d$JME?c%t5Q?Ip$hv?O6%7DQRv^S)KN}ex zx$%Z~85iee-fFeZoH^61rB6Na#9QBb_1Mtx)Tz_!*Q~wzEmtirw2vG<{LlaRPt9s| z`plVo?|tR#|N4zpt5z08|JHBadHVF!)Wqpt)@#=4r%oP!^x;P)PHuSS*=Kg{IQxMI zetG{d?{7An*Ij>o6uUg@5$PBI;Y;s)$2;feX6lvnm-pTO*kgMd_4?(PUVhfr&BEGj z)O+2oHHKZ}z5n4)?>TVrmGgJ)+Ohqd=bnGz!ABlE@aoHd_9vgd_~J_*+VdbKX|RY| z=g!Q{{_&supJT^P%y-*sSFJRlTyz>0(z0mxy1hOZ9`3m7j-5MpKDy_zs8U(Ae3`Ss zZE8ZKCWPUZ)Cw|U!&A@>wy-)dj;Wy_mIbG(LGa=94QM!3AhWd57Y%h1yfl*_iwt;f z0)ZVW5UL^=2M#qNB{V3^018T|gRa^zR4EaQ7z7qZMbS{oh^jzK(n^3>g}j8aq9GPm z5VQnH2qYXNzd(jY1mwYU7Jw9yd|4Vp##rxtSib@SB6umoe2)XIQdE_UVPQ)S5mgxx ziL@-ebB+j#tWGlI_Id*184(MBZm&?qkg2rRsdxz8)gl7wRRU_&5Cw#( zwWefGXhbyYXU);^Y9)#+wcCq_UpuJG#wLVdjD6w7SD$?D`LXfki|y9rnKJ-(vD0x* zhg{{^=O4>@#q!bE8uBGOW0b`bfzddQ5h=E@FFlj`qC95Nrdd- ziZ{Grcx3!r-@a{fY6_58V0`83k(H}=oPXi{cmGH_?I#|8^r^=m$+PT+8*g~ud*Aov zf4teE9sH(=bn@)%b6@|lkA397{n?+5E+7B(4}WNEeA)ND^PNt+omA_?!=qDEQ(3>8 zR?;-8dMG_G0g-BKEV&57K9vQHF@h|tEEbI-lNv=7BMKN+YlG#xf~Ziag9)Q^cpxY! zNT`WHAO#_-f!!D;lVDbXz!^|fMIl8p;>8TC;2OMMBI-l335Zq6kTI@OOZsII#fi`Q zoqpD+)Y5vjEDJKO)9G7s&N%=jMS~VBDC?D6miFSHhI6wl7i3^g0WjmFSWqu=ch4-Y#R)oSVN^iibJoy{F@(r&tHD_Gefm?C=iv?by!?egXUO$ zIMJ!o$EVIrkByI~Pz7(#-FY#TMd>pYKR-7g8!UVY&LYt8=xAQ#y{tfkWGXIgidyR` z9>pj!psM6~R`$JUuT{v&wm&{O6Fa8@7Kv57hy?N^8YK*Ypuq|ys1cS79~R15OT0jnDPhk}hFv^G^ECg(f^B{suf(}stJQU$R zimfR{^1QWb^|EEl#`26^6nPjtc!R~ZWOYOy(0fn9iUQ1t5k)dRw@`NmB42c7=BJOY zURi(T<%!tXIJS|AtR0wjN5|4FYsXhF8(z7lnav-x5PkH$S3kA)#fj5r#>U4x3!P4P z=B@9#X6w3D`}h9*-S0Sm^UC;{7mrWQOI~!m?^V;9bzYHJC9z4rS7b#$tyMQ~-RfLa zvNtA_C?Ud9#e-8V_<$dcmZR{=fESZzjrz2~hefr7chhIB0I~_;nnY~XQ zJow6rmCIi{_}c9Bl(Y8nJ&!#8$Rit8tW+=m_OD;-_wr`F{US{I%CA6~~-^_qK00nvIjk4rTq^sQmaxcLDN45B*X_8_jyVyYS${4~&g8 zuX)Q`uekW)XP$lL^yKL%j?!AyB5c~QarMeon>L=cddgkK}B4%mPZP(e0828lrhyt0NNLrGcL zfWak7$^Z-+IG3mh!0ZuG)mvi#NrSslg@Sv=*l-j0l8rH;dy5%Vy)l;6gHRMl2;iB+ zW7e_*0#&dW7Owzc5vXD#w86!Kh$5=iSt4Zh))@jqG?hv$A_eCv;T-UR?k^s|2m%^G zLc{78TMM84?B}lBeJ%iOdH;LPOf7uuV;>xArT}o!>$d@b0JICJL=XXd_#L}%z4OPt zUa#oqBg@9NY}vT?slDC{THJNsu8S_Z$Qg6nt+)32{lq3CwINp6yk&D*Ns3&1S?1YW zWAoB82!dKPp>hlWed$B*ZeEmx775r3phmLH0 z-IlWOKl$0C&HBh0=h9mJ#L3f7?R}&-&5`j-F1zsLiIb%-&?J>c zQ$S~?XTA5eG~rT6(5tX|LQ@vRT$(tFT+Ckc!q=+Ret&-R#w}&xUpsg(sa8Gnvem2K zd(*q0c>Zt6`RsH1&%faOcfISzqeqX<&d#^n-La9;=5Uj}H;BM$$QWywIf&P& zAj+0Vy$1uKMM#K^3FLfM075|pFQuR&8*2;=gpd%VHQzItLg0gnfH9)#=efT3=&f3!N z_orvhJof0G;o)XIt+p2CSFc!QtYwgreW%;Kc=yF)qoe2UJoj_|-{**EZg%?eD=uHR ze)HJ! zTkzbZ_Z~s5F{p$GrbuR-Q!BP_sTXGS=$$5P`^A z#o$EJLC8k4qHr!E4Icm@W7zwET2>K*ga%6yLxzwX!9vy-he@RpS!An+_C4E#Y^c_V zd^tC9*jk%bstVv)thFTIg%JS)T3i&32@{f{s)#X`ym)2@mW7S6##ogyO)BCgBp>Zk zkZ`a;rvTIncRwN{h=KtV3a&!Wdmx1?Fo6XmP>;wCR9QrgDgu^6p(lz}Q7Dj!4xM zg-1js1xBMJ%7%;)!(0SMB9{Gzw%&2|MQ?udMZ@(WK>gsmUXKbOK*l&{Q5ZlGnT#=j zT>64D?{n`piE8JZv$-e=BFgg;Nk*E z`9+gB&t)&`6*6p+*i|Ax)Pi&0AC$HmL?9Fi-3VdC^xoUZis$|NUU=oetI8UgNC`yz z{KD+q{A{CMuceh^N00Wi%tcN`k|Y+9ey@uF(`DwpSYyy&p66*A)8O*g;7U!RsMT5w zHV9vq3b-&o2Y|-dG>udM2oTWwL4>W-S-9=?TmSG6exJ}>u=~PC9(r){)T!OOFKpCm zs`~JrJwN-|&o961;_Kge{duq7b>#5ThaP!keqp|nB%x-#EQ)3&-M-^>Ylo9{?|I9* zjT_di8C|t($N`iBF~QkeHa)ZN(2du>ZCMqT?c6vr{>l3vctBb7S0M0EZvqmul!0qK zv}GdrAYHN`X()(LBpdX=@c0{m5)Jd9Y&meQG;BN}>|O?g$iR6910qXkNBfoR9e#!) z86*Hy1%sdh9!fO0^gsZ=loe7{6-Gl4swWWCz`!930A%7MGGu&NGBcskAYKCUAetwU zu}K_@vM~-l_p?3$s9FG|2#p~Cj0_@)oc#G@Z$5SvoGv> zF0H1+%g5)=%ym0mn@nLCV}1YY`N+)mogJovqfYo6g!gH$78{6Ak**lHA5c0Rm(V3yb)~Q4~ka z+V@Ok`+3>x^tbH1VCcZfxieF+V)S*}b}Y=ypPZbz;tg+l^}vCf-oNVb@iQ;I{DNoP zuw`rR6)e<;R=sj?^0LdXoNp~eQIsT=UcaAI(kPC~ejgDLm`u0mE@XXXs;=9xd1Pet z<(Cf#s71{4f{3zSUql(8+v~1hzREgR_)-9yBO}cw+;P|U*R9_C!JFP?$JZQbXIEZv z#g>aMdE)8ke*V+{AY)2j_WKG%-gCR(otQY~nV;VK?3(qfM7h`NDQLeaw{AOI6}sJ? zwH5$o=4V|JC$Y=R(kZepuneDKBC>`CIa1>WQDh}BMVJ$gvh>R&q$z>Bblu9sF1|5FSXn0VubZ-eZI9|of{r%w%e^v^avv6MIP3hKCoGd0y!N4h)kndf99EI zZu#2Rw!UuL@e{}QKDoEmYCrJ618df-otv9~`pKtM^{cnseDzzesif&o@A=8pnaR*u+n2$X#`Ka}z%yS8sVYeT(W2Q3dBI{b@Y{B-%q$j0?+&e?t;HCNyM&tH4$rOEWz zB1p+nhQoo&GQ6yG-@@xO6l|Tz$0;vVVM73IqNEjg@ zh1|R~mdGST1(&fimAI~eWtoRiF_%SLNs7YPYiU4~6uyii7x3F&xe~d-t?Vognz(~t z;fPEiuX$!t!zvL`xYyN0p8a3_?Oz9OYvL>_eCdl{tk!CXSd@Njd~E*<`}geGLx|Qo z0Z!92a*?r^=f0988#iyf?T()|8^aT)PA)9WjSY{i->}Z0oSB-e)rV&n+jrmnA5T2_ z%(~4RH?CjvgFAm%O{>5_1{oBQP&r^X2kfJ;DR|aEf-|K@Kp<19qKG9Eyrs?< z&kO*nfxY7YGqg`A>Xid*97UNzUYZaTket^LqY1MUgr3A;$1-G=I)zvmEgHt91u6vJ ziWozHgprlf1E|qKD2$Auh{zaKAhG~x40#_gFb0$b#1O?%tg2b*t*WzeT1|bP1CTKU zpq@i94T&JL2S5u<0LEAZLtrvrddWf65D{WhO^vhOOBBUr$%yDZd+&*Gv9%Z_2_j0! zX^RZ_ry-IQrbH59agoc*GVlAT>`a~)2VdI1oqDJpcUjo_Y2u8<|{TY-HG% zzS^i(l4SMjHAjvftJNFMh8lW^jN_s-#wscq5*7d@LzWyyq)AQXvbV|49iDz7th^Y4-4aFuB z=31>bJ->M5__6gHw~UXCYeaeOPfnaXJ=s|{J~qENO^&8p?bYiyz54?nI`HC4w|woJ z5&GpLLvifNtO!Z_Bu*~8aCd#UxoYjIcDpk-zi{%@gcq*Y>la>d!CgQ2VP2NQ)dnbd z_EV=O<0JxQi!D!<^8PRUR-F@YmrT-=FSv8 zUpBI$x7e|fW8_Y^EgX}{I^D(2VxCmuyeN#Z-NjDn%Q#J}vm%N>d6~trODk!w*JCf$ zxEdNv(UA9^6inD~n$YP8U`%9fwGK}{`Sin&?jd99X|-Of-hco7zAOQ$TCG-VHAMQ! zJ$IMPqMX*NA@WwM*N#mbf92l~)N0iXERNPHkuex{gfL(?3_=x%s$y_J zB-cTcw$cD72jH1eoFyB(N;M8QmSqm*TDqjQEWK_CLDeEE@IW;W|0Wa#FcjP|p(sv4 zJQ>4fk>zbeAR)elr9o9Nc`m?(3y3S=zsCXjM(vq!N)aOTi9jMebQE!H5@@0jw(0 zE?B}5ZOM}L1(#AVOQ-|S%Ywc4dCmx&@!2~!fn;T`6~&b}u5|mY6DMa+otkWST8-iH zHLIHBT&LYNN~-9+uhwf!Qldg|7$N#4$1}4RR0|Z^VS=whA;6}|i2(&EIrDuDW_$!K zJpmXZ@uI%uK7@co@E=8l>PvwzccKR34U$2Gr3C;EYSR=DJu?Cr)Sw5ds4zQ2ag-nr znx%u?(?n4iwhW;)l+^3aIW*{uD}0`1S@?kp!cZ>Ex6;~Br_+1kxn~=Vk%?2M_ddP1 zR*jY~A4`(i7Z1F~fb*^Sw{E=h=&_^SZaYaU7}@ZvWA@=Q5W>3@gpRNPB!eJP&;K5QI_{3kZYe#9&z^5k(LMVZ}gr zlVE~{(0LIo(~qRQS2u;*%8F%hY1S$OA+_l1b4 zqP14lm1T|~mDCVXnH69S83Q5&f%O7GRWbmCW@e%Dn;-w^?|%HIASwOr7jAyOd$s29*syuaJ3oN{Mb>?G@7{H5*LAyHFoez=Jb2JryJ^FQC!c!i z`F$@KGII;f8C1JaU9z!y>8pt4?g(d#OYJbW|N5eSwGJ*6%J&x@cIj0ei918 zRmrMk-uu4m)uul>YwPd+@gM&Czu)n>fBMFFvswC_MF?CjrBOdVw!B(PzxCapuHwpU*J z&JS5*g+v$_y@?YBEz8m(KKaCB%f^;{Vbo=L{St)agp_{jns3Q<;-O*iq1QC*WPEJUhd4y?7U|!%WUPE)$jiJN56C1 zZKo$sUwiGfr|2c&Pq6zx}Ci-+J4=ef!^f^;O%qo&CK#?pV8a)o*{|6L;Nt*TDma z{^ZlY*Dv@l{^I}Lwe#%nfA5>0_^m&B?)jJg=l}e#JGXDY^2&Eydda0NxUc5hpPq3Q>Y-WNlUyBoIfDU6M9SVex@u4M~zZ8;atLfR<&c%FTMi8e@#9 zRw|VwA;dU}yrPJZ1vS`cR19~d><&4z*z2P;v4ut@s>KwM7>jv#p;oCFN8)oq0x3=( zJF>1G?K*eI$=CK)(}d6>3aEF^5J06iw9;<*!k51J(ESg;`~Oz3%e0YXFU~s(MP|!G=XZL_oFVG905a zn6khaVqrlfFf3{Sh{#LmJs=^9Ofhrp;PB9jvEha=gW}FzSN8L)QLT<{?j3&mKNc2G z4mFypKt$?24r-x6m1zJj1Q?K7f|zDhMZ9`o3POu=6h&EeiB(!AWBw}DPB!xEyJ)i+X#IoXJiHlw#EUHqgrIw(V_mOPY z&HGsg$i!n~0O;ptC(dN;%!@!#NWaqqz_Qn~al#5kQABZEmYzkCP?$lG46(9=20tZB z!pbHLw4{R?5YLS0kT^te4S=Wt0M7!YA&iXm%AUm-jfo7B7q5fF3tM5{^S3v-|JT^2_l9rlJK>n0e?R@$3;+r#)1G=5fFv2ltJ|&iNTO|CL8{%19J`n zJqH5NBcg@^Q>A)@;pB?HT~ z+p&H7?%lf|f9#1$~5t zHR>=f<~f-mv-aKKF%pyyMsY;j{nce|`Snzwz~d{mak( z#qQUwKJUu+UU0#ApZTvJUb}YfCqML&PkrM3n>KH_^ZR!p=x^WjrYD|y`h^$vee^@` zzy6AI{^jPI-+kkCpL*|AE5?T2b;Ad*d&gDl8r7fv_~EIk!>d!+w(abP_dLFF^~#HP zZmczGZ+qKYcdculyM4z$PX681SH11>bH;DGu8vs#VC~`h~$hjiUvtkEmCkbiFiWn_cBFM1gj1tU``1|2}mHcXQ?s9 zStsmCQ2?{NFocFIkqI$HHlRYHW!+>KR2Jq=KD2(rmZ)h$?1dB)jr|N)Y~yq(h;{(tVgCYoo z*SDfD7*M5>Sq+t;(H#sU8A}lQtigoq#|sB_Spwe$0T2R9mLdXBV=1_)ov|JUWkYBp zDd#8lJ+%7liy9-#yLnzPooOw0@?v~^_4ZwFcyZ6&-F{Z9)C^cK$||s=B?Q+kd#0db zs2ZgZ=|l?eP-PM8h}o+bGDd{01k@%VfHJ{S+MbMtpQ1qr0UV(7X;3;MWP)!;05LCp zKP$_ku%u-s#wOl#po|!64Mr?pJg^E9dG*dZgD4aPdjKF+WFFiMA!DH;0Zlj9F9nCA z3IwP*#sO)|>V<+|426{gRgqLn4P8Y5Bw7M^L)N)yvDJHK|KVM)-!`&(6^I%l0Y%Sf ziP>jaA7k4uGA{aab94QoL=pgQG@EIqYA~9aS!lQW049oI^QN;}-R}NpU#e7V$B$2b z_pYBzPIg?<*m3T8-QwAqxfv6=TC?fBpFA}IB_~OoWm&yZx5n~PYS)CG12rP0Kwz&T zsi2}4As`R{OFT%00e~tBgf1L1h|25%*mD5|hZs3ok`Vh1mz<(O2;J+VEJ3>gRYFk) z0Phu0S$*MihjGA{8ALD&5N>Y6DxqLOSpd}_;qwM1~Ypg=qkn1HvFQsdKJUNu7(Bx!3Cv0Dz!DFH*6I0*H7KDGQ&mkD~+$U1Xh& zh%BgA@giKUR*W&e^Z;m%CK_xbQx0{||#aGR;uDh`%e*tm5|qzVAr zww_(B*LR+?T>zTRp>R76k5uD0a?T(CI=^niS^#+edvCn^o}Vro9|3?%c3&L32mr>$ z$HrH#8(&rdfHaBGSOD;4;l+Da1yVxso{Wu*F+?F!4FI45L`#l)P?d1l1d5_{QBf4Z zfZ$C23x7|tN zB#8~_=Cd|so&Myh$tZTtMXOe?S?qK>Qp_(Dk#WvMm8wf38|;`I+9(wfje{Kg%T`#VWl!iG9nlR0YG9Y9Z^JxR2+HbnbBp-B#LrV>-KsJ;2I+Zwj=-z2dt@(Xafv<2*5nc$T~|DHa`ez2F8zY10V?t0a`@~ zr7avQi1t zL-J51p4j`tAKlw(m)2TC`5Q0Wb@erG|JPe?KXBma>>`-jP+k;i1-70O4Gj;?EX=9` zm(p%`vaD~2h$xC z;BSQP9T%EhLyq5&5l~^T5E)}^oOp$sZ@#@>c13-piC6C`v|{D*#ks}#`BppYx98{g zJo*GE_495iyn5M6Yb}fL5+UtZsF9Ghp%7bBv_v6tKZwpFgb%bZg`p#uR5Ubgq9URw zE0QXzGLc0QR0wT?Vc(;mgjPiX)r2!`ke)*Tr2tzKMFT8KXu{x$#;B+cXh#9tZ$teS z0RamUie~^&5HCKm&KTpBOYaGokeqW0uvEAR%*=+Jb0WejfpYCxh=>rw1xZ9{n%3*} zPNy4I7|cwB3YukI5Uw_>!dARG<0?sFi~&$)jvPB1Be^Wg5jDgC0!m=u;~`Mh;NS~O z+wdFUqG;muscWve=C?ojaZ7S?V&eAO?zrj38#iuTpG$#=Mea{c&f7{{s7FcAy8r$c z|4&lpMD)ZHk6(J(g@5q-zrVQ9nw^=x;oWa+w-uOv<2OG3z3+YR`0?W}z52>yk3YU; z)9P#9b}0Z1H)?58>9Za{y-Fo@&c$)UrKHtb=}QJhK~QjHNQJ#8(BYxs z^&8g#!05=b9b0#K00%HO-iRUx0C``Bn)M_}k_5KzIA`C!{c!zNn>TFTvUx)i*8yPd z+V%Cu2ms8?E{-l=5hwKyK(Cvp%?1FBFI!%#)(;&zw(-J^8#k=UdR_o1N`^*axrSHAK1>50;3m85ROIEUT~ ziV#@}&jOZEa7#pl6o^I$$Xps2pjyMj%&S-;RS;Gp6MW;k#BvG;LZCYb7B;K;05uR@ zqM@RIU=UV=r4Rs>5eSsTkW!_W8=J;E&)vP)-ZL@NI(TAI7CPV=z=DglwBQU_1n?dS zhlh7vc=?K|ZOxxpy?yIPKKg;fM~^Kmb~dbCT}h(tJGSqA`kBMWPnslB_T20EGK+=l zku%nmsz4^ZE=7bC(HIpmXc4t!Z;d5n0*q~3ur&n2Y6-iEc z;xaD)$PfXFih5xY40E*irCLG+5ir84w&cQqWc|F?X&*k-TC=J=@B9lMdE&`4bF~y_Wtq!ex@Ua)ab^Fh|nOGM))<`RN{`jGx@%8V0 z|HnT2SD!mIbFxt)Aa=W*pa1MtbsmQPF!ab*A_gF^ znzE>345)zPasLy)@DI90{QW=rG@8X2IOEBQ_Wqr{ox66QI=l3huYK+Mo38$ifBg&J zdg8_Z_TN6Yc=>cu%n`CS@%# z7Qw(O0?8nn5~^z8kg6IP)fExkfTf5qDo0F#5F-T#a)=1nuSW0$#a63jW@TB52oZB& zkFXSwWFn$j%qS;SV+t_~Rb8nlhagr*%sZV{ImU4+=cebRPW}Ey2<*>>DH<7o2BbzZ zOa>5Fm)GC(o;$BUv>N~p9o+lrKl=+sxcbmu02m9@DNSuFRgFWwyxJE@Kv1Wu*K0ri z*f*zj|x%+9{_(yP07@9YnTNKnKKr=~VGhi{!aeed0Oe9!m1 zI|4lZ%!`cKL}$WGDWaH-%8_f6N8`#2QdL(~?H@B#2+3Z0_Lajo9NM>YM^#sKUB|5P zIc9mbRF==b`sOw7cyFgOv1|7}z)&TrA+4;gZkwLsK*OpO6qV#7Y(TPF`lBHLtZ&vY zy!@6L0uh)+;!d|~n21otR8wrX`-9DmjrA-<5nWtbDo2}>-Oiu3yDl%Bjc>oT zoo5B}c(6I#Tq`1}jlb}v2iv`{xP0lc#~#1s#_K=-mk;dOv-1!C{IB=#yK3RmspaLV zzj^i2H@@{)FYg|G?uE6r;e{)U#p!c@`Hg3fJo(Iyo!kG#|NZZ8yy=#+=guR*fB4ix z-#U6!0)OT&zCJxOcX?$^m>&Gr@kbthpxY~c=fD2RfdhN{gTeki`>$MCKqLfUAP8h4 zmXtFFRUr0$F|Q(Wxss}QqOKS~gDoo=s3@~*>V1r{rig%1ecE=-9g?{80mv0s4iqI( z@1yoNiJBQ0lDjyyQmT0}wGY0rQa`)gudn~XUb{H__VC&pCqk0%e)oI&n;S=-dy(Zkf2&SORFR2IDzMs& zK#f>y#iSLcEW{*<7&s+nu62}AMwX#TN|q7~hUIWP&SF+%#kd|CStLdv1_U!r$=zfI zW+JKr$bo_iFp{rlL==G79J~iJQ{Q$RlRyMi@%C6V;-ElkVrm#z0YFvNkU)@EQW}Jw zX00lUR8|n9>E=*27nU~SnFB?b?qRFdD)Lqnd)37Cn>oK@Mu-4tsv&rM6|o^AiU_mk z8B(gtvMLFYh=MO|i0F~}HE8f}qFY`~QAGdYwaFznAX6ev4!MY@gnFnfnvnzc24?O@ zQq^V|MG>t9kfNEOB_s@9$<~D1nvp~Ls$xJS4ZdRLZ%zhNAPlvM$7^g3Hj^20Olk_I zl>(C}fC@6HY2a9?B&jpRT9jgp?M_`)fwLXkcgENn_siJrA~EF!5$9%-<%4>7|5v{C z-gmz%hR*U*_0^+~zWCy6p*0b+s?+I&KnTX;>Zzw*{h=TJ@t^-cfAM$!;8P11E{sNX ztCd$}xw^U@IE?D?U~{;+u@Q<`rtyyMj!s^TbXaMPfS^hSs!-L#vMlqw07L*Xb&I!{ zk%17R0k8oRo2ig0S}+6wVUM2D5VB6E2bRzkD+D1BDhf6jzad!DeLzgCs0{;v&9v%v z>*hUy=B0T^0t$|>eTQcuQ~z(NiDFYzLBg$WHLt({04VFKD$D(Q_wL@aeG1{<|MEXu zO%MY#S^Zmom1Vl~w%cZM{*ilc`@p@o-FeqXdXw5Tn5cmnF{$^dDFLynHpMssX28fq zppv#iXyrnlKEK3#93NbKflF<{R$ zB-r}@H9!-@;MpyvNPy~qWuo8*$nhFvVgw9s57 zl~h*9Uipl~te}9(My4w4kQ*v!Z93VT_?xeNd+Evs5FUH|wefiL=|BIA*N&f^eceo>Gl150KhsSbxyWbLAp$Bc-m zvui&igp8L>ZHTr$kf`c_Qfkpt@h-l)wSbqoO$!q(uoTjFTVNY+pbOzS+x zEXy}m*Fu)fO;7*oFaDCMJoNCFuPiRi&CSnGPVbtYJ$?2Rs^u|C5(5nZ0k}DJQlr<2 zBdJPqWE8>FyyYh5QR@VPRhfu5#`xFw-#;2|e(AmkckbBxr+@nCeFv_p>VB`?eeg>U zKmY7g+vaD!@|CYdidhzb=*tg%<>--TdQ-i#7tfq~;v%RlEnYr(`s|y>kLNLLpPM;z z=JfjN=(@vuo_PGJW5?c@-nMOZY5BiD{--3ezPfzu)z_Z<*0=ZW-Z8&zW@B?>xW2Jt z=gu2$IQaC_&rJ1t!{Nrb9H&&5gEFJ~%Hj&L?cKHeiJxCyUVZlH6SH&EKlno*X%!u*Qp~d1>B(|D z8uo{xDH-_B00^p9OGV5`ftXcmB&@WmEz7`I21^%CZ!KvAGNMY=43ep-ppyA&vPGc*qc-JkUT_8`iWC5~22)f6 zsDu{l{Em0Nuhp3tjz?B2!~j)#_0rPVv}kv?wP0i6wT*?-S>8b-AoXu<251b_v^E6G2@q|pMt~S8RduTB!Far~y0(4ijyF%7FanP3 zA!5j0>^ymHVdKkRJBlD{oBagT>rSWUI|$MM03ZNKL_t(kg)B;4htMih)$UEl-o*d$ ziC>tT-*Np7H(&j>YtNiHclN@C!DtW+h*<#YN+2U5+&Q~r*REaT@pv#85+WlbAraN7 z0)WZMNy3;U2`B@L)LWgvjxrGVCq!s~s>&Q)_2AXMno<^{&%&Anof82Ify_X)4lzdx zAh7iafU5;XMEpFv&#Xzpbe55w)MO;p#0N&ZHNbEyB0XMq}f_v3kd9JlS z_|+qmo%XRePAx24Nnq2H-Glr0Zf>p(HrJ1zys)^k@%*c=|K)?d-el{QmtTcIA!8&< zqTCRuKH!=61wkXSGEdwTGY~(S?C6}MmgdBzTZ|k!a^Q%`q=9D~qC^ByLjYnOeqm?IWCbX zkHRr{1W2nDhoga-B0vbCKkRqA9Rok#u6;v*@BFz&M2MuCTAkwDh4aKb8V}E(KiA2# z-b8Wo)X71AZfSXCG#+CmtLqom*EXkTckJA`ZE1DAXth$Auuh23?X)9v$TL4@S)O?c zcb)3Ujq(1i(-;2uPafIm4^N#sX{gJ~SIVkxwes#{>!KS;>l-Usgfi~cfaHA z$zB&ic>UNLb(N3;6HQG`O-%G^t&-Fn*h81qEW}7iUWuY)k@F;}$YQ6{5wX?PwL9;; zV|8V1X=!;}*0byY}wg{pmmZ z({8&%o&W@v01155h1zPO2xqpC`Op6xn0)MGfA0eyc>mA+y$@~Mw&OQ{^EZF^L+?ePm!CR1nT22crysp? zJR_(!sX>Jed&vDyZXRK z?mm3-`0e*U@W2P|z31(B-1v>J|IMB6yZa;Wy1qaBp+5S* zE??;nHh1jUzGHsdnbT+UEGrt%fn^~evZx9Ia8NUn6vmgwOUK`L`@WC;z{~+gWuR#kFBYlG31C4k(gpF$%qLka&XO}xN{OrRLKm9R2&udmJijfS0aUA z&B){LPcTMAG-kIc`>BWs9GZDwyNC3A_&&?Fs{%&^hjmH+xyxNTz zvP_V*;pQ_>gRi3rHGYpd?6lN9y zFJ3}q+tQ;UB2!RJ03hH_X-pz!2my#lMVW($YDx-91a+MxrQzCIx7!`|hln97!eB7$ zZw}k-*6hqojL~;=cMvs`IbqYAOD&Tq%L?KjbASL&Ndsn%FC?X@F_j#F_8pR+gbzQr2y-o?t5?J6+LaAt= z8kiM~n5uDNW>H~6^ZrsW07OMYRS*Rv0Yak?Vit+HEXN`ev%o}ERn;lwQ$-eIB~@M5 zPWdqhHLdCriPgYAth%l^FsgCjs;WW=u6Q#;5m5qSG%;psyjh}~o0~uUBOm?5Klup& z7yw^}4N)8^EAH7;dgFU0xgx2HkG2D2lqS-8ibIsN~~qG8>iS5W{ddzHs3}S=UpO zlkIjf91eGE-*M+{cbKI9+8Rg#NgHcx%S%gHjD#@Q>|gh`gRi~(!rJmut5tYdxPlNy zRR#580!qoZK~hy_QV+#vbP>bi#Va8TJ9h71SzfN{l8J7->3RUT?%G3>6H~2rcJ=JU z{LGG2B>>pDWBah*pPlLUx_Mx@>-Jl_1g&~yEL zZ{NOc+iV2bHaR=p?HzvGp%y|Bi+#IyF~E*(+l$Z^k;%@)RR^xF$E5+xPEB@;)?};Q z$>8d%uF7MU0IIUga%R-E62>F#50{GA4FSrsG(ti)10WI)*YubW^k@OVMqbfmSoxi# z3cgw6-wNH(Ek(_9__vLo0Eo=Nnif^pN3x+ZlPRcy5tt?fa5PsP(gr_y+#l3A=T%Yz z%K#8bfpWu9f4H=^NvO=m$AtWBwCD+60>D@Qqa&wY&{EcHV#En5eYi0Wm z?pt2Ga`xN>7rtI|%{7M)Upp~9@$}KBJKYX54F;R7UQbQXEOHR#Xfj$mwR>*($v^r3 zTCIp!3^uCa%F=hu>TS33$G-14!;*ruADCF^Sf1@0g7y}rd9}EF;f499o ztY3cR$)(dLx6RBUshWU+tD*fPQ&2L%=92l;~?`M6e#7BLcG*s6{T%pl02DR8P0iAdFIRW$1s z#pcFFmbGW5XG^JHf8&i1iY!JzCXUR(l8ov!H#N0u_nz8xb#d8}wAvjN1pqM}m7|r_ zWwMZmg0rY75xIfB2t>T<-IWxLV+(2vNQu+{ph`p#kvs*^pn=SoNB|M3uB$w6z5m1C zyKwQs6Gxu-!27>X&7OSb$-8g5`KB9hIdS5|6Gxut5Mk3Z?&E+F1xED;od5w)9Ds!; zUk*V4eZLVTr|p0cm|4YQmNjdT!8q0P^Yj1qS3fbq@QrW3G^|IxR_EYV2iomWSEIet z(_?^N`nSJ#&HjBq`wu@X0H1s4+yCJ|{dQHRR-PeIQt>PxCn+1NF`#&lv8!spkchqC zkDy7N+7gKQ-XLm-NNR+kVJrcGL0v~>4Q%26j3|mk-}#zn*nuZQKmdmn8?m|{86hQf zlXH`F@SP8A>xee71e^y9sAgVil;v4!dXZR6RRoz3)RK9Un;IH<&YvM5awAn!Gbf<{ zEQG*;1BW~>)C`zJWjr2Jpghm2G7(Wz*$QAuC}vV86U$<*s?33bYfp~Wrk;Qy7>IZC z`WwvW0m9H}cb3O#I2>)PY|Kp09DC#Vp|@Sr>Gn>(b#hdegF(H#zD|U-!e)Qm%G>1K zy*|GuH)W6!8CHm>AV~fdFw|gy8O5O8%2l=4Ttyc z-S@i6<4^q9KluE8UtC#TsD{H6uOFZ6O}*>xcf}CTU0&$-H#gTerAkC(pm|ng zts-w{7tWm*P17^8SuA(%+O=)l_SxyVPOBp#-Cmai-*?}AtE($Vk38}8)6c9dFHcTR zZftH!S#6u2`OK&P8~{RSm=1Tti3%e-xe4Y#wyGcoCoVnS9O_h-{lN#{fA5d}oexh; z^p;mQ|MUO*U#}p3`-!7J{^KA0_R*J$cDJnb;%YV69Piw@699(8@wqeSSuK^awz3*H z0DzdZ+MO$lOL?|W72Y~^Zh4fhEG%U)1A^7n^)qMAPILnTSY5BLEiGPLI<$AH)9PNj zc)1Vo%FAy~O-@%;Srl#JEU6&C`ST0?{+K8Q1k!5d%1Q-LRTUzpRGvLEJb&)oM0eWM zR8owwR_DGL{k%E>tcn2S4Hwv)a%@f@qNgB(ditp~d@F1{z0QUBO9Qmo_B^Up0%As7 zrQ{{;NfR{Xe+YzttZI!|6Oo9}167c7hNk8k0MKST?L35uRyPY-Z7FX}gaR*}J!NLW zpcOJuOGytNJT%pt`oO*KpU7HAjvk$unVOoKxNvdd?5T6DEEkXf1^}&A@y@&6apLti zHr7^RjQjQ<>~@P&Cr_CQa|ARfm#12rzwz(>4aN!O`20&JKL6Rj-dJDVyLb1F9kW+m zd&|%Klb>1{{`V)IKH2TH3{(w)Gf+??fRIEOh)^<4*p!|!CH3q$hbGV?B^Xuoe=;EZ zCg5fb5WqlwUlXVr@nowF1})}OYfJT|MMwy{cI@A^qr3|2+!#zh0#>%k%EkR9Pkp z6pbSnfG7dyW~TP-KbVr8Tey&Cq1WkToRu~0iuUc_ckr5P&uvyje8Uabl;e^J zOe8_mf9^kwp_wTd83F@&7cv--ku}2;sbWGvkjAK}i722ti)4N^fTGhvU>FP$Ot;$M zyw4no8+ENJqRTi?p;6W#K`qA4A-YP48sl7Tp7#e{%>wFDKusQqN2H7%;LQM1*OUcC zFx9_RDwru4t5IN|(}9o`l_0UOAsR$Krl8~Tcye;4VuHGk9J4Hz<(L9w7WI;ihN`lzG5^?LgC(Bu@d*bY^bm z)1Us_S0DZ#bv-_N=JeHv4!(8jZ>n2`$Eh@38QZ{K$3;XS+e&CE~k-Mizx?|JX-x7~66?D=P(fBv@H zZtoVYci(f*^we~(*XwlKD{CtkuPj!h(dzQ*`r6w1`o@*T<+Eqc4u^yO#>SrQyTAMW z_fAetjfX=p>UJmA)>cxgXD6qYE?@cNC;w=EZtj6gaiaaE5$@PYRgdC}>1yX|(j z(-{l~U-;q|PM$nPgkm)s5t_%9o1a8dFRj4fSGBW4fCwt4Vz=IUvoW$myC%2q z*uJoE?mh3mr^9f^9k)JygrFuQI0#8mHw8?FX`nQiks z_wMcj+;Qj4pTF<(olb8$hpVqXgjxZ>_rCvqkAM5gb~_IUVEEndeNP);-~I#h^V{a9 zCa<1_0|%};dFHJm7KYws8q|efh#*bCC98Udm>)m`aJ?h|pn78rrR2~IHbaZ!1B3#C z>Y0~n1eiS4rHLQ(#K7b|aG!Jogb^V)P<&Ud`yt|yN^S=XbLOQ+W}CM~OS)b9^Fts>(34YwZLchyxFE?j#3sh5BI zw|)=nP^Izdg=Nm->@&x&x%Qd@M_8|>(b%kZvOi;fxB zsZv`Rz? z1Cb_4RV`UGOQ|Nxvk;jK>Qq-&GcW)G)adhzOtk?4J|iEw|kI`s;7}-XH#6 zw=?nJ0}p=eV;_C?>1X@>{_Jc)XlhCZj38U13%X`iQeYMlm$QHh2ZkmO1pt(QyoXRk z*iV4VOw0(7nMUR4=l-wXs7AxGD%C>X$qBjB?FE3_6ao1Y=zan4aA}XAQfS_K&YAiR04Sbm>)-)`nUd>d z)jQCk@xws_W4itpo1g#yLu5b&H#|4-FwkHHDuVc(%zGqc5oxNWMVLcsyg_OJ3X)~H zi5g)tK|l}%uw>d4L;Du)iX29_&na#pOauU!1&)zLw5lo*RS_hL%;R#rva;OGCwkpZ zjO2!&)zwuZ3L#`!rd#D!K29-HO36&bgc<8pWAq-%##8_xgxv2B_U+yE!S}tp(`#S3 zy!iFM`TC7FUU$Rc!~6H`J$v@t>e^Z;+MB}?i9h)L@0;JY>jU5WcUtXkK&r8>rA8t^ zMgUVWLsGA+CNuZzTM~&BK%lBB7fBmpplD!#Aes=>2wdaj;Td3Pri2KlwWI*S%mU{V zlhbETpBoK_MKL|-Z_duoU%IpcOj*nxe(<5Qr_Wt~`0yhSKlIemr>{GF_>E)7{G$3+IwZr`uj$y380jL}r?qp5C!@*Ma@}j~zRvRyesp z2&SMWF$S;KAqrwfF5faSWon={OfmlT*B^cNJ-6?gDg~-Eq^UOBadp{P|PweeZ2^)3Z_~3^-0@Qkb914jsJe+JkDTCIU4JMV3a@ z<<-kE<|&nfkzHPIZ5@cA%M=>5HaSoj6jXSur5{B2OfO5 z)tML#`oz)K5+f|D6b%uuvf4`l34wuXO&JFNR-^HNL+BK3sY|oMR~XTxV?}@@WkPGk z78qm!t5hNoDq^JZaJ06%x@Xs(n{T@D^<%FA0*KZ1csLvqaV;qcwAyVo>2^9<%ubv* z5n{Od>Oax2UIb(@mR&CSIa0RWj3_>%%jQ$`+IZ^&qhl#)1$hNfypR9B@| ziCcM6uGDl`kVjkXMbwj)YOq@ zU)~(7?%lO_a&o5AX`2BvoLN}@s|UVxVDBw|_eVZ@@#2-o9zS~j1NT=|opY8XZ7FMf zB||haR0A_KR0JSl)P$sp)VzI2)dg|P3_u9lJj)7z*brI`Gt|&ZMxNE++j~=3;a$(T z_24r#gSB@^e8(N$5b6Mm0HR2wqUc>n;3{1L1N~0rp-O-Nget14k~|&JbztCMC-fRc z+G2lfYievl;7*$ZTAP49R%uLRSidq5y4w-BGoVWG}4bvvQixf;zQEC(N@+VbhA|N$IG_3`l z?rmiG#>|K;qF|_?2#5?x$`EKYs_(n+i}$|oy-z)LWPN>Yc6RpS!o?4M=z~A@V;}$A zU;Ndhk3PEZz}}m0x%r!qKDxMg`P%EQ`{{rD(`N9Q&wl32nbQ*!6JQxuvD0;c#f6b91w)maHh|X6EZ8s2Dhu!}6hr9%5o-P}Mxk z0>xw!Lwx5w@4EZ$yT1I$BPmJdlbQEAAc%^8OwFb3B(*5JUMdnGW-)ZTGY>ubY^Rl< zc=P1Rg^RP>x4-zx*}Vr3A3L`)xBse7ed+5r+;A9M^Uu6|{Do5+N1lEPim7v#M{k}! z$?e|bM_#zHI(Y8c7xPZ{&;H^o^E>7*FRdMY>bbk_xZ~v6vw64m&|g1&)wTQHIDV|i zI;Ym_=U;fmlz#m;f49@^42I*&msh{|=+lpX>&dxod;k3N|D)Z?kH2*SO&@#t%*(I7 z)$UEc_~Ki~j$a&C^7TibZck4A&EFi^yLbPm{_G2fuG;_VE3d>X1m+?ZPWu88A+nK( zy3iiC&Xk`Zzfk?(ZqXIZyUvV2mCY=$CSgR+VD!akH`JZ_2uO&O!k8x`DmVJR+j`JC8AZ2X#j-MNS`}u{>J@B|fLQAM>L;!|{Dfw@{sgkuVw6|%HRiNe<3+e+#b9w2$ z9s7u)NS(9I^m><`A8?xh03ZNKL_t(mR;RMi$#Shmgy0o{Xha|?;&U7TB+nub4z(D7 zkw?3!k^7d=A`vy~jURJlj&8^a=3ZoWFw*T00;1?kBqAcpR(+zX5fGrMG~z@6M>GI| z)XcjU5g~#4R~ozok&tQ;=R8z_5eG58Ve)XpH%Q9P+nL zoXTUXC~_h!%al}O$dU*XvXQDGQIeDabEHxv#0)rKEjjY`nRzno_PT@=nNg(4;Z=2(?wRaGDT$cOjt-hc7Z(yOl>Bg_J4mbBOI)lvrvLoHKEJ9g{{ z#3zm)PiEI%cdaHpb>dW=WZ&-Hl2VKzWH~U6MkD5!WwENN%p>6qiQ<;%T|)>}(v6Kl ztKFh3dITYeF*0`|5hbY|67bu|Sz$-j0BkVW{QH0ZAH41AYc5~9a$x_#8*jSd*z2!P zPfr~@xPN}zTq_SM3Cs*B1;P*-EKP(75jdeDhE^+#$72kP7SJ37aIg*lAh&Ba%4#2=YZp5^u>Og23CAU&&-DLy7!00k{YF?|Z0|Nj;0%On21w$8bhQKwX zRHxt+K7qnkSAZpAR%<-l9v2b(MeEubaCI;wsYO!bdtw%=(HHA!LL>p^sOq5b;b=rIP?5V5q`E%#1s#LLUv%A17)m1B;~8`G=Xmf@T5emwxRx$}x3%)BpZI{eD?h z-Cld;?8PI`zKDbqlapV#?~$smJKbVqu<>jE`ahPETJ821zWlI0I4)YPz{7v~v;RER z(rdM!eCGM8u6OO+cjU=uzw*^1trkwt&fjwxnxffo3?6D^)TD#pcRce}ejhIjkT^?!;5$s9w{`U8kxPcp;kH0uyIGBy|C`*&=-AgTd07$Q*MAW*eJ z+A*D-8eRIs-}t2i+s2>z^k+Z$JAZ7D5LzGnSKoN_^4hkEqD`E{#&yXte(QXekoU6_Gmr`5`{Y-4q$jI_SKwr}6T@o2MXbyipVPaS=NKqJHa z+>|G}EnK*4Qj>X%7A4V|1rSk`Rh1FN5JBBF0V;r$s-iWqu|eHdL=za_wBsfNt#C?4x24LWG5}ly%5A8^g{1`Y?uUx;L>|mFxYD`EB#~9RJx}4uOGcn!!!$11ukN)V#_wU~Q!n4o(z=uBcUGKPkb94Ot z-}?h!{qn<=)EEO8OI=5%oMSnz4A3$cV@fsFs;Zz)MN#;H@Ye?#2pT(atWF6U0TN+d zjzzVTch*)m{_4K3O-**|M5Ccm)K({&swAmRFI`-H^y^0!&n{hFT-+S24K|09-EJOG zpwXY8HH;1zXcJ08jo86srIG!SXJRuDFamKUtP+Tczwi_+G##X1Y$$GQYz&ZKE9$z=p!qK!nEjG$3*vH1q6sE7{E8UP>z zXcBI4MuMaP7=w*1kwV1a_mu&L5JZ!o0l(3GR0S1N;}9DGnTQym0u#knkd$hmCU%lc zl24ZAgf1gNU_by>P*7AgLsJIQB;xadDIiWy&V2cShtME0ojiH`?3uGCj=y>1jW;eY zFP}emQ32MM7VD&CrMKOFTUk}FA3Kp-%QFx?CBc8=TQHT95hI%j5hkcYhykH0D@0== zF=QenEX%P=+*VeugxKn~+XzNv6gYB5fkvZ>O$Dr$RE;a-I2u-;|J)beea|~vz0S9f z99>*k_^tovj}KjQs47!E9&N0yKKIPC)u^8AO+5edOD9jh^{c=BZ$M4QQcOn)G1UT~ zh#>-*rNAU$NdQ6Xx*`gxmhos~I2?>dBQc$ypD$Y3px6nN^WJScm`t#7o{x0EvMNRLzhAP{<-CH3cn-j--?TOr@68 zo9>RQ@#eE?$f#Fjt@Zx;cwC~wfQB!|gaFf&ikisi}!<1vjWy;{hs~VI#a(Y{H(Hs8LZ`G))G|gvcN&1#pgR z^?0`1J2gGUvAE{io2dLtfN*Ycao4up+vjH67nTViWU*z4YJ2zX*>`Z)-0b|$?b`?%Z?QSb$0F^9eDyd49u8qdy;lxC*JJG&)@gf*!SqC7_Zr|7I_3CPv1+P;g z5^ZIXD5k1PsW#Ir53DQ*h#CyYg2r0G0tFKh7BZk1kkX zZW>Y?m3CqXR0WX?snMq*n|iTsa{iHip!Y2e;3KkO{r+NtE!xuo-U<|F=N-_At7=C0}3o=mL?}Bn8P^L^| zgvY-5&2#6^)iR8PqpC~@s#wyLPRvt{Zc5WsoW75rKUb?zG$gKT~fW?%7q(0wx*|1VKR?wNV-sTcHPhv3*~sZWY_c2HOGUfuN|&Ng#nRNT#Yv zrRG%Ks$2KosyqJXbI#stt@n?8DsBB!Pt|jupd>-+tDOYi(hn$0n!N+m|b zIEj(Sd9R@ARYB1j7BLZq?rsGQ{Ks0Y_VsUkJukj`>C)xD{hPl^)8vkq-a$m4{6Bwx z*PVAcKqX2|($9zB3N%!DjmO8@lVdBFS7Wf=b4*dM-@ompcg)XUoL^jMHk)WsIMhW8 z0cdbQVx{tik$L1?5=BXx_|ly{cWPn&(){A(dX^9xW29ZHt9MH)8@;kr)~64B@AAgt zdbfA_%(2Odv4Xv|R#_-CGzYFs`H+IE7%`|FtlmI`L=`9S%CB&L6M}`s3%~G-@A=@re-8lU zBJY3Suity`J#T#D4;z4f!9cLKzR~Ru6==_%t!EcHZ~Liti;zX5$Y3al#em4{ECEaS zF<5J&(P(H0vs$`#dD)j9loh-+5dt*F+f&n%iAkS3di3o-^OMgVIsEifhhmeAkBzsQ zt)eKsD+i;#D+^W@Bv4A@WdAjLYgzi2fAz^E%UsDN`#=BW|8BP0lVjtxEVD_JwQBY8 z#@V@ZhYmfvXa7DH->5gZ@ZLK@O=2r58VPu(0w%O-83h2As>DP=ym!rJOA%_dTIrl3 zMp0~xO|4NBR7{OgB8A9W3yP>PHa>pl^qHeajz+b5nxus*A``Jf7)U?(TTguJFaG+kU$Xz2 zn{K#y>*m>4+;exCkFt90YhQchq0jvz3*%@M#}SLwHdckvpePrd2VWQakk?ZIVG%=-hzBAOp^6BE zA@~?Zd_)Lb?tqK~2p|I#t-_mEo|oWVS0aL{$zByJKA169RD*w?XcqOm@RUBYn^l}?jJ4W?%r zjh2wHX(Hl$@Bo5%1p^^>9*T)5up9KsF3waGc4c9*2#l5e$e?<*am3yuqUVs?21|%O zxSUk41nz)Aqaa!aX%5Vb3*_K%AtbGSxDtG~M#Fax3P7mB61MOlVu=+Hs+dK%_=e60 zy#lyHL{JGqN)cf}1z}}G5F$b>1G}ANgcuVTaYbCWQN3kyp%JwF_*?3$wXc*7<(&FVX5w?1{~(7Cx6RI@E(`>(!g z=luNT#mlR4WJh@}BJ=YXw`|^;X0fUp!lerbUvbxy zoy)7Mt1~k*`Di%ouI<=5`=f8T?}H!wk01=jBBBJicnIuZxST5)tHHZUMwt8k{$MzG z_dDLUZ|m4|7gnD?a^|Z2d#5KFV-Sd9wGUNH20kO@q{ z;HwcJ1x7^CU{qI8QG#H2Qm!yrWDJ9*Ny^?k=feKNv5zb=GZLjqq6ItW4H-~$-jN9d z9*6|`tpNoVwqyy>k}b+YNGzd>psDt}LBOTTj;Ls`*{)yi^?mNkvb^EO>-X)y>iqeI zte)jX(eDq?*gW?|Sw4Meu(~#EH`-21gUOYDabdN=Pk@#put-K#4N@(G&c>Q6M_C5H z|Hr>K>=)mD;)x%)^X?CS=)VjGgDso4TwYrG!P{>B4?p{6hBwb$SY2K3e&APsbJds4 zS~l$W?|SJSAO278Kfka%H9fhowDup~_iN|RUWn6_OmxHb*Z$X!{Q9t0io)W;!f*cO zM;?6e&HwVx|Mw4uYI*FiX@2#EQL5y5mjSIfi1;il>rPzL<*wB z0lHqO3K~( z2unjywIl*1dv&N980rvNqY6oy0;>qe01ZL%zDOe8TEj{bU`Z;YB1a??BcKKhi>Qio z9HOVe6cH{J)d3RJ`D!Oy+5brusWN7U#c4>Q|pW-&yKJ z(%$pMr#DWXzeueeNfcX<613fDJb&Wk+Qv#g99Urxe(h^sebv4_Cr_Pn!rgwq*IgfL zX7BpxpW3ozGa35w7ru1t`9n{9S1w&zIePq@s+>7_G9M0OW1~oJy6LJ{-*x?9z1Zk? zA9?ueYs(u#Ff}z9K^Y-!y=uSO*{^;58|&Q;BCBW|$KHDeDs$iI_q)BKkQi*dX?8Y= zV^(3$8dlAqL?$p9IK$#}x;-1+TifGf^?HNUG#kx0jfVNi8lwVe zqK)-VYOUdwy|eax?|xlT76>>T4rVuPu4PS)aeV7efF|gr$G-H{<0mejThK#KK67Dd zdA&Q#EY0rNUV2$sUhS=S(^}T=_gF-j5ztzj)Uws?hB_8oqN>K$G7u7b9&~!SFZ<=l z5Y=k+IEqL4us7(=PR%x3&DGV_$VLPZSu3hwZ8%~?s$2^y#ZhDt^P)83YFX{WANtMt zix+^Q9I9-AQsUjd?O=wsQS!=Y`prR!cZUBhrRVw`ml!1v+0IV^h zY@oVZ`ilFj0BB65U7@1$4&w+^ymOeOX_|&$wJ-yy=Q55GvSC641R`re)Tp_FY^oIU zD7KNcPCOz4qKRzeqSA{8AH_DHBRLe2p;#go5rUoDcKz;0|KO8<{>jyq)wQ+dR=eT7 z2cVrhw+%<5JTGjVc~;Mwm#%bX&)$8emI{$CWTUg5)-oHLPPdz;sdL=x^+siGh{oGv zef*J@W^eH9mc`o!@aJ9cl| zym?}3ve|A;jZZdGd+E|*dwTZz>#zIDSHGenMPAs*ieMZ?!W^5(ni!08g)@puB`8^A z4PjZ9>QMx&F@R`{vDO*_0x=+>AVU37Z#WteV7*Z%6RTG=3Wk&!48>Wpb=%g$mCH7A zxg)Ec?nYQ}AbZ+Uu@aUt1HFdYTSL zMI0xwiK8R|L|2xI;GGlijj`VQQp*@gy|2efIp|+rUNP1fFd|ww*BWaz8qGL~)-PS| zb^EQcHd^BxlQqp|!+93R7)E|V3KF9dt5l#+2*zr`V8;a&Bvcjkp}sZTHA2(5S0O;E zLZxAOrXUj5YJgQuD-sb|rxJ90gN9kq5HJgb?J^)CD5`Q;r&=`LF_J2a5pm8Xk=@*C z^#{H6jg4*XDZjn}d4Kz4%YaNx?ikyB>wA9d4^Lk5I(DG%=;m$PR@T?%=FZmQq*lwi z{hqaPJwuXGO82kdeX?NRZja@oQNK4FZ`9uM6A!f7t+VImEZN0{CBS6sw*CE4@z6hf z&6m0JLN-xFgyL&oe|)m_^LO9=k|av*x$9-;=T3D8-J;L!$(e0C_if*E$A9~yPk-*q z&t#1Z*h|PkAc>j)WK&W^Cd|w6F)-G#A{Yb%MkpL)5=?q(l!PdRpbZfkU||>b3lqJRsTX2B?Sy7%WxlMP={24iYO`< z3WYF=1_pB;;JijyjYFjrB2{+i0#Mw7hr}4qh6o54D%>6bqTx`74IpV2Qk`{Il+F*3 zBuykqY;5ANc|;9h8Y75cj6t--g_9V`l3_wi$i2?)>DudGbMKaEyJdEV14ib(dv+-( zD}!L^OIMbeO}%>O9FK}xnu=!;=?zE5SXC^Fks*6-eqKwS+B`G9b*CR*w2>UV^_J~h zul@G3^ACOD2}`th*N!b)cSK3HywP3T_{w77 z^!kHhWa5ZDi}*N+f^l)IIW{plxp--z$O}z%ywOIWUXYhClna6PswiYEF{%<7B4cbE zq3X-;zHM#e?ce^w=XOqxPs~jA*L#EhaPQ8YKm6LepLzO_`q5`T``N6PZQi`;k*|I& zj^i}Om)~(q)@a^w$1M;2)1&9kzK|FLULg`dB{ixVq!kn;AW;THQHazMAQ*#6g)2Vx zzy9j{`Grut9Ja^JdY0#-_5NtJ+uvBaWDGQ#bpv{F@xs>4Gf5l^N#Lm%R0Jcze2A!s zBnDJjHFT$k6$z`55-Q`1CKw{BVnJ#EAWYprA|Wsu?7x5^z@msqN~+AJ5)?&<0;z}) z1w#i=AixL#p^6eJl5ikis|mFj70`ts)G4BpfCh^o2msk2T2OUS03{9$D*{-pb_oeB ziUSUX4X$)qT4R>Nm4+xRt)eJqFL4}RYs?}6s!*%dJaebl0a1fCun^FY2?jV2gGN=@ z3mHQoaK$QQtqo!dhzf`y6I!DT5&<$2B6NCduX@$1KkzHR6vt2$#qaz-zkBeuTi*DF zA1O+QK#pZ;d8OdoU^Fp4nbaC@dFL-RppoYe0bgh(Cb^+tQ?((2sh z&goO9o`3$-!GpISJAR^(Wfmy5=J0bzuetW>?|%C`s_2mdw%X+AN=5l2K_u3hS){|01BQN3DFpE8q#DWiUewq zk-MwwufFG=>DieyO}1~@e*WU(-+b!tMx(s5zP@$a=AZk8fA_E7{r>6GXSQ$N^1}JE zCr_OrRj8W6j4>unQ!mb18|br0XethT$dm$L02@fC@iP?sq#;-JBBEA`Qam{$H!X65SdJrnI(u>qLGBM0)ugq zcu@*_azlX|u8JB~8Gr^2qbjR0h6p7LlM0F~ib7b~2UV2Opz$g!o|IyNdX_Hrx_RLy z>*K2BpudI)-jzf~B`{7A30Rpl*aRu~^MZ06q6uLRL4x4N7b37=$PgIuK0x(t078eR z2SW7TV4T%J`9F=REHcb(l)wPZ*3qzHsQKb|`3>78f z6+qA!(ntkV$p)9LGu9glQ!kOCGUF8>FN-5Iaa3be5eD>GLLR+pS(asB6oQ7?My)YE zKyQPYz!EsAY!3*ELI%s>(79}Vqo)MSF0mF66(|I{tsyT1MKuD<5(gxNAu&>vxvF=Z z6O(sR`m#S50)UA#zsM%=rijjyDm86#Cd9K!mqCaLCZ;$zs&zwHpYBz4b^UiO6^YQul zLAyPssH1#XOY1=wMFa&S5=g|sQKXG#^QmW^?G3v-r^k2R|AvXl_QKLqqu!*LqQpFK z{~O-=)(1i0?78#(-athn8+E&#ZCkfJ`Q(#Rvs+)7TT+&Z@o{4iDmyxWXefwQ4Awaa zpAZBI07W%aI!9{W@!hH40En#Y*|j?{QIy6f=9a$ot?$*-=*RB6Cu=r8 z_1VuKe&$dkbr{nX;RHlNpH+|p2@C;CXh5gn8RtMn!7GXjDyoPOkYL5`2x?t80TBI_ zS|w6}u!sSGaGk5Z5~@b6F!U&aa=5s#fEuVO69uZ~Bdz+JfmMMp_+|(YL_%#F2vX3! z!*9VejEJh1jH;puEteXI(Sbe6d*{iDe@*>~Tt4866iNuD`fT~~btiAq6 z-h1u7t>HiQ6AwOk!}TxOwQVN+(F1JWHoLmMff&^rjUN zf6aZbPvZD@{@ed|)q!j4jpo+Lv0wbfU;4;z{)R!z-ff!Q^vajr+8y$R-Fu&W>hLqq zJy);S1SE;$)2C0~ci+AD-22KTZG7tQ9$H;rjbhX5Z0y{%i%1Ua-?n$x14#JsPdv1~ zzGlcc=eKOx>U?ov=k&gv_nnwq{@#;^vDdBDlM^RTeD}%2w;jBFR21L*)?>Y1&srO$ zsX!HGsTQonYpaXzdg~9r{b%0|&;b~K@XhagVX;R^ok$Q#go!bn?*xRZ3@qiSneg9z z=97)ODL3+CCl~+IAAk1Z#eOrcTOv_%-i`8+swblEMkgN)!y3+#IeY4)a9KE)r0L}N z#OnH5lBBI>qqDZQX=Vd^W~J z4R3hUGcUYw{f#$_PmCQrc>AN@KDBMfw&|Hk5#MZ1J@(jR>uamKcJ17`WBa*t=WDfw z2$yB4s!1FhLlB4nMjSf~MiK-vCNGAgJiqted(Y0Dd-UsHyXpFyH*ejc>Jb$P$0sLd zXQsdZ{qN1s&95&n56eQ>zyDX>*XeZs`foqAWB2xz%d3|zEjPzn&N);tWP@8BkjMs% zrG|Syk*S;s7NgB3jx$vB^g?D%d1NxH=G_D8;%?@jz+nOv+?OE0sW<4{*Ud(mTYp@z|1TU+80-H zAZoXpMg~|$1Od45k)Ck3m^uG0c~1;^4P*NANa$Wsq{6k`hnS*F)qsWE}xh?_RzmP?n`PkTM8V4 zz%F;z5`=&yf>$<3s#17%s)+$45=021L=cNrAfQU|#WL8ca!vr8_hcgt#q}(zfE1K0 zHHw6QM7i^8^Go2}%r%qhwbf{ZdmkXFic0vWt_D-7QtT3rm2ffBiuMVh!0IC#k*Yz1 zNN7w^dH^)WSkTaJr+~sQa>VqCZ{@}OxYX#8|CC|$0MTJ?(B;Kn;hzOn?5}}4l z;jkpD7I4A>gaK&F!XV&91;N@VO%gR2rHKlrNrKj>g28|wLZZs}DdGXb4o(Zt!a!uL ziEH%+3R2sUp*V{H5N!jXF*zyo7ji}1ym`7i7+t=+Jhf>i&KmW4J&B^xXlTEg@12N^Y+6govRqkN-MVG#{rBI0^DVdR z*|+zRhaWk9{P-K+^rO!_^Gv7P&C*O2!eguoAr4Onv5g67;o`-)bsq| z=Gb^y}>kCy@$=NE^C?4O#gx)bz@5W$tl zN`vvfx(KN%10gCJWAbt^HWuByXU}cdy=Mqu8R`c9?XNpuamT)0(=!ABaL1iD-gW1X zl&-AXngSvj(a;cHjnsnb#G!(L;HFX{#E=ONpzdH_thOta$^wW2Y5);|LjklP1`|%G z)6xnw7d|~86?i{P@73N1AdrY-uv*nJf(ehMH3%T=01<$=D*DtwO7jRt5GcS$#HlxE z0-MeS_nCsRv9O3ic47eqq$1IPB7g}QR}my76NXqV$}+SBSTf2%qd@?0&VfP{Ma+x< zCZc?lCrM(g5oT4$vJ4E7F=>*F@*xX{FQ!m_NJL21kn^tkhXD=d8?ttMeDd?3|Ci2s zcWH59>C(b8Pkw**?%lWEeCseTTv-CZdZ*vd3ud-aRFps>^;$N}eY@SNHM4!!9H=*& zj(Ms*9wo`wAN$6I^XK>N+w+q@{-&$;?K^S&=uErb>2(nRt$E4b*)M(d(F=2PaU2c$ z{Z=EJpTEG&QCcSg5!t=H92Cd0G@o?*Po)++3C`F;!7`5L}>;9D~lJW zHt(63nm%=YHOuM{5wm*l#+$7{zstLKJ5p5|5AH`0|@y{rvjTkAKF* zH6l`{L^LW2=UBY=&d0{aN&NIvPai$}?Cm$-^ol$08gy6J`<*SDwv3OB5t-3wfKuLa z+spsx=GC*lWQ`%19JIRVPNE1hV!H#&Fj)H~k()~#D7|Kcw` zQI!14@BhVNfB3#%{=mmS{;_}e-uHa|AO7jhZ+`2+TW_t`#~yj~@xzCoo7ps-q|tE5 zM8xdXn-@J{HnPFB7Pg`QK&&eAg)e;J`RAT{%UkZBn_u{&Km7gH*f;XAc-zWjwR zz3E5pYqnaS`ON3$mzMH8Z?;?QR^#{n-`^genmKXu>_ zF>D3362tWaNrV9^8wyk=HbNxv9s$vs;P(>oQaQ)390sbSfC$!*V<93ZVlWiGdJPSx z!bk*)7OWR9zyyW5JTt~Jkct7x012oT#hW+H)RLq|=G?h+hade6Ozwczu6WnW%6JNF zWUS4i8W#~ewh?(RaTIyyP!$QfgU<5O((I;9D12f5f{0wcbos=w<3TsAWi_F&1J}~A z1wz8I9F^>paU^3)=epnh9}lB~D+=~N=*K78X~UX`M8LBEiZM|sg5*_HKn0O3A;cz% z)3m`XfJQmsf1q+hOU1DP0fY2^Js~K7plE_dAu6gCK~y<}t_+}OcCMIgw5GRg?dL-R zwImdrd?tqArUh`yMnj026fwM@wX#%eC5%*@97IECk(pC6zUuA;gQ%)jOfYy6i>K;C zfT74R=+t5S6p@HXwG!DNM3Ynzs5i)+^OKX4WTMsej`sp;l~oZ1n8*kqi&)eOW(uL) zAX4=RR#>%a*9(o4-utStSQQWq1RtXV0ApfnR<9^GA;(K(E{T*YAB#<5&qPLR2(rL&hDI^0M5yW5+vx`fW=u9IN5T zi@R|CVrOF|i=#rAki2qWHH#;%Qa`w{(b=?VcK^OTQ`4LF?Yrh1k3V_r`R9oY5elG1 zBtVa$yTM;M%&NCC2ivJAq8*=@IQ7EH(dQPPeCCVaQ0 zaxw=?7y$u=k*V5PfuSo7KqdhTYk-QP#&P0GAKQq9OJAa*h!7YcjN>@WI;!f~1EVnpK!fOl%1A^+ zS)3kz_He7w>TGN*T%1$oUax!n#Hm`n*6Ve%EFF&gM!)A-Z~uXpo}a&*rU`fvikO{LU`Pj^ww6EU75GWC;Edv5sh-#*eK4Nn_E~~U>5IKRoks*p3CvYK0Eo| z_n#}h8;wS-)>ysX#8H0enP*GyXJ%#-ii}_sneMRPN+S`lQKZDe#ooQUUVZPK0G)he z2{!kLR1F2?yeJD}qR7Sw1(-uRx$$;oMqqoMfBp|Um` zS?>*-6i^WBZQz#ih?a^iS*StJ}71`TXbqxmK&~ z+qZvaX6C?wtClV;KK#fdah7Vu z4?XoO?|a{mz2*)DV76cU>X*mH#u6L%NBO3i=~uqu6|FWLIecVkVNq2d|K_)U_FeC6 zw@p!$lamb_NBL+JvlYX6DTrunjDUziPz`-zfB_w-suWPAswjvCBsk^6GZeng__C~S zDQJR2Khy^a2!K+>BB`z;6ZoqRYL&ypRRH?6Gpyfbdp zy|}ax#gPDb2D5Xgb>Fo|PMmhdz=12uQ5uXOf%9bund8_f%jJs~yDKZA zQcny(Vvz*AvI9lo(w9mUg?otzI4lgti3K4Bl4hfxrHJeRW584#3pxT-E`4aN57r(+ z&w=}56(DRYfJ4i*Fo%sBsCZE&G{I96jIwA*kr8c`r$Ph(W(j@AgoKJ@)T%{G1d@=A z67s6eG|Q|(#3+uI7nYROQUqv7gh9xV7qJ07tQuKUkus<{&;rzr0udB2U?2*Xl#l>N zqhXMoZCF?lkO89@U;scs3TjY5q3ZBZQVIRH3`8o3ii+&m$2LeOd8sZVU0TUh?k@BYtC<5QcaC-)uLf8x}MVleD?Hw2t9 z)|Va)*@&jvt(X7ctu~hBl~wV=PH(#DWs55p{`&7e4T1#d)Qw6v(QZvnOf*}qxpNns zXI1^7A9~G=H{I6l%lg_;FujGRp6>StW9>GfWuF6RZ#Y0A=Nu8Ob=1Z-ij#84g?MER zFC+sd)GkHVOioUYhC^4d2uId}Xn#07dHlqezwpJMdH1{TzU$7>X!P83hrRa*#v&;y zt5>2J5YamI5kj-ph?1z5MZUi_8jV(0SJTv}a!9~NHWKiWi4l|u6%<+1DCzh6qTFoN z-9|pYbg`F9fPfimfR)vuim(PPy`p>}0#e9;#+J&0Z5n;_w}1Pk2X8%g{B)idS(Yp> zEw!3W=e-)ZFhBSF@e}P<^YyR0=ltA-Z$9y_yLav;8+j052&Fs*2qEP7S&*$7R00Y- zJE|Hq5mnXv8$pwhLM$z$dO#FOQArF43JQY;0){H84Gd@`K{ZH-1OP@W9~+=rHDRa# zLZ=cCFG5OQFmx1z9c+LcP_WHXn5{$477>ZEtzt(3XN7o$yUSR0VPMGV5Co^Qu%N0h z9b^iKQ501REkx#$9Xne(?~F0b-itR7391*#N5dpZym(7Ct7WAxT;Yq{3F;^x#U=_> zWQgRPi=qe!y>Q`*gpzPo5mhBH)pCpwfK}Eu*52`sxBkk{|8%$&z4P7gyXT%ef9fp{ zyr`M2_jOd30?-&w7~rSh@&48BAhIS+v*7^9(Dtp{UBSaa2`Zz0|E@dlJb3W7hrjZr z=Z+j@cH6gaxp?aA$Nu!srZ!DK`Q($!m)FvyhK8IkBO4t%e(DeY@V^i9;h7VslGr4* zY}4fQpf~)xzx{ig#vlIAA5o#xr%zv8yfiaA>z!xEpfWdi;qk}6ckav!$4;ME>#Q}J ztrxe(&04b<<{MfH8OIXY2qfSD!IH6AB;Iv$xwr;Xo3Gk-U>iV|d#l1;ot4NSfnvc9 z5v_?7$c-Em3q+>A^XbDY*Y4XjzGoKzu5~$qCt!cTEi5iwnx2|?_L;+~elYBQ;Y(j^)msAc^~b-C3hlA+ z%PW_Y$f!r}csT4gnhkc|224lTq#^)__wYBvz5Ckt`^ehzb_Tp$7%4iii%B#bdSb z4NXrL)O$a?`G)HkFRj$GhO4=piPA|+onbKofXy?TkDa-!fZ+Y~c)Om(w_kT4A=sGv z{>gI#+vM09La|^Rdk_z-HnP?rfCoj9*c;3hQ;iK+Ax4Yrm@EpSF{pq-WR$}VEKTFW zF;VExt%LU-H1}0C0V#8Upc_C@3&^0XjAVgPM7sU%K*y0B7Syu3Kp>Sy(q^Lbg8k3Vtf(9v^fF>Pd}E1fHv&1`0NW_4{tK_W7! zilR{zhvkYZ-N3oBg4$N^KB;o?Rc*TW9srUgId|^t@#80Mzx}pamSy$Y-+%hkQI8;#u9c>AV(FZs@Qz9*un;k}Lws-kE~s-zrp^ECb>B`3qk4-S2$o zzCC;Y=l}ZHzkd6hyJx10kvV?!_++zw?RD3zudm;9(~S>5{OHo9rS{~6W52w<+-@{} z=ryliU0-?QkG$?r|KwwrFE7`UbX4Rbym@;3f&1SuKY#IMFT3rFUwQQW#d+s>Fc=;? zethrl9oJp6Z=#*u{mQ%k>qmcQ*zb2bo&KQbK$0>8(9qi*rwIbEX9h4tj+x66DeCs~ z-~At-8f$;4EDIs~+{tq$iaj$ch>{Yj!6ZpN3o8(awN_2@!n*s}U;Uk#Et|K`ZXXQF z(li0C~vzih@WGq?leP^RnvNI+!gv@@_&zn^*}Qq{#Q21; zALe-!MF*}uuz6+%0Yun|FvH5qvW;w#Wo6-$B(B#R{lVb$siT``Ce}AbNfNi3EfB8N zYHxhQeXA?$4}a~^UAy*d**bgp(BbvvOKj zhL31?j;^So)u)n;dzw_`_ z*S!iXi9(Vl#jqR{!+bPi)d*n6&Yk-3cOXk)b|$Si3ZF|Ud6|z~E>$Cqssgi%2|>{t zw8}P$oGLLxIYKU-mt2V~#l{K)CK*yh;b=tyC8=1ezQ{{qF7v)9yCP=+W@y$LtSE|P ztkVJ^3QJ-^HG-nx*#+cNlEjEY20?-jL6yxS_6ck zgH^$>DuNP{fU+Avxbr=cB)C5 z8ii4R@a&7xVrf#nHr85MTf2Pu z^2LS4daDtqS%271;;hkXmdxFLH%rsRM$Wk_PE1h%_N59yWZ5%|Mv(U6T4;?ym`0$}^+qOipwG@5sbN_JD%{QFCa6V3xq8xcPEK&?dBGPO$f{!|@ zr3;Jmz3v7gL{S7P)&{%?8XE*t0tFGZmOx3A6_gAOhr={Ux}Ej3G4Yb?ZeUCh2}p@Z zy%-`9GB(&`MKNRzQCR?h3^7Y=P2qjFPmer({Mu`G&TiSe-tC%3os$GpUeEod%iWuA zI#>=z-#xytbw_*0o}H{f!YEcrNfATKp{*9)29UA(cm$RJ22@e_nZL-}21O!fMpZBd z4OXCd4Dtws9y+MHn}h5DDr$p1VgifKiU^PzBvH}8v~} z1QrD~mcmq{;T9*%9Kz@V8Uhm#ytj-(NREBpPvm#Xv@5u9_tN?{ik z8jKK7)F4@Fy$B((>g3qWSHAM-kt5Id2EFA=m$q)%bo9jY_doE~J-c_Uu5?Q;L^dyS zFgD8?Cr+M7>#eNS^d zTWg85)gH_9JkLvGLWh)L=kuc6vUw8#u*%341Qf@y`pNE6`Skf?UZmA(0*HlJkQ}IE z=eV&ejq3@87yD z{`ouZxP4)1vDfJgy1k{PMM5G&8q%+sha8@ij=WKiLtqIgi`XE=tR$kFRP_u#pDMf6@1D)i+jq8t!GMY7N|Ido3d)uFmV zSMA!Nc6`%HbBu96%(d~>r~0sW)edXTIl}Y&pUuq;HQ1WnUcRte*Om7^3bW$sB(}$9 zji-k>-XH*ED%w!m)c_!RM0Vu0fCd7AkO(P+5W|?86>)=wgUGvyJ&^uKG#;Quel9on zOw4{$08sYWWq<6Ed+vYu%uO%4ZGQK`s?0~l*b(+;XH}Y#3F;EM40*n`y?tQ%@cL-o zK?rJD)*>0RLsTIoP;t%^fG7n>0P13}oaQSB`mW#hg7tPtPOp=jJL1VX2}X|C0RTV^ z>WMrPOtx3cd@aRMiwfi{=hjx~);6TypC%#|BO_+0qlw!Z2bOcJrXfhD)s349&s+wv zSX0GY5*$JVtsyE1L~pRt57n{&)Z9lP3Pj+THpb(NkoIL+?r6OZjGR)^bN>Ft^RxR7 z?A?E~PR46XPoM@zBnTMYh-l!vnFTc$1A;sw#F-059jY-RkwX#{W*1~9m;}HH0*L}) z07DQ003t(WZQNOe3dD#Ig)8lu9&fl6(No)a(u;F!E^W>r;myPbBsbAEB@x@TVZ<~RT7SHJePJMZ}V zcs%;r*Y6yUCzDB@rtZka7w_G*d-3d95xM^P&wud22Om3rJV~>>tjeP3061{Su2S=4 zY{K9Xf#MLbiMdBG5K%%RL{D7Tl~Xx=>MZ!qjx4(oh!Bxzyo#gbiI_=D96?mfdCw+r z{L~Y7|Bw3#d1|Ut6*@CLg;<5M+}s>Keg2&HtzN%78Wo|cfkJ<(n|h{(^Bap)s8s-z zjbSHk2#qwx;q2(G0+^V%W(m$ zA~Ca0Vn{4#99kN*9ommYoD zOI|WRw|iqSIKQ-<=M_05q*iBI;r0K|pZu9s?ZkWXZt2{)k9_#{=Uo4s2OoH#+}<9B zaK~4^%nCun;`uYf(GZBM@nkX@0l-wNRTbsjOzWrL{!{OH_kUeTb`@prvm}&NnNNbk zzJ2pAe8CN0`1}{mC;4Q2@zDci5k}i#Oh{)9ticyZ_(!?hW8DhKJ60^FN#CvbLy|#r0((aL|LyUHPM;L&zEM!OYt#7+{2HP*b_2xahcRTi{&z}2>Kl}3o2M+keMapgT=|xzXsyau|Xvs}PX~*(|QQ8G@ zJ!M3MgeI{)0Bt}6*zo3>m)=wrkkt${P?H`CNDe_mEz!oJDnu+HV6+KF+=n6(PqnkH ziJUxja${7it*k*x-txV>FHMpR0WLjqF;o>yawzPvW5)+YcK-C4tnCj?7u|jr^3p(w zSuJqPW<>y0Dz_(tGgs{Ey!BOYc+m}4@7c3U4Notwe)T)Y{^BE_3$1xKyI>X=9HdNtJF57$bz?C;X@2ZQATm)G<8IFz}J9EdK58d&-hq_a{ecDaft3pa#tHqg7 zB>_Yb*!zT$9D0qN8{>}KpavpQ0M!^k7^kxUrqOk2hS&uA0g@TIM!)RRDij+l-Tq9P z_;%VtPSJ2Y8R`0k)_kv*WXG3J87el`22)kzAkx0oRqnJNw48=J`)sKo^7 z+B9B=&KlDMFoK|qKChjuxVZTvK|`>BNQO)bstzy?>#WfkgK$LcT725n#L>vXGmBsT=C?vsxvYbjOe$+-Ek~}dY<+tag19Ve zI~PLTOFQJ8fepr`5QMVoKpQ=a)SexH1E63wDFX-~V`U2DTa3U^6h)=MInL5PrG7k` z5R-R^H87E>f|(e`ye`w29m}TR6JJ#|a{_>BO600C3`Q#lF535>-uhz?KXmMd=RS|j zesI?h-tuE_zU%wE{3}}68{SSZZ|45VWKmFsswK@r~>t*z+TVDWmj#;|6QT_R!-`?w{ zzw;;W&hz3={``X{o;+1|G|fy^v56@pihBN72ABe2zz{Qyz`zg$0W_{c0SF_Kd1tr^ zW@r{AXF$Z!r>3Gt7`HHSc4Ek|Giz+xxaeL3P>QG(jI`;v`B61u#}HZ0G5!i2MKoi) zVH5xa&;cl@kP<+Y(hve05|9WOTVpyT5U?c1m@64tOnfFoNmLv#I4i}tS^Xo%GsMP& z@yzUunhgd63Bt@srWPb{fT?xoR`0n|8_dogt- z7&#@f&8_Ws{ru0o_9ZU@0J!GrFa7%+H{W#AD{gtA0uVqAus+nHDzhZ3rJ9*e|Ljjb z;MiwbR!N;WT73Gcv!|X)v#gz_`Ec_aU;08Y9S?@%@nB}A2WY`yxIF;?C17?%3CE5d zuS~b=JkJZM>zJ$H$&DuA@h49Ng|b!=KqNsmAfIHX&MdF4Z4`A4h$2!+MF^=&(=2^* zX?^X&T2bPeYt%7g0C8mV15+DHv4O@c|5tns|>^zbIq=eq_ z>C>l&gHd%rvMk*mkC8b`5@2=Y>L7I;lEeoE@~PEDC6Z;?f&KfImX_BCo1IPv*~j$L zZl~wTjYfm@^$h}Y&Y1+Oi#VSr0?}Y`Y>ZT+C?S|8NC5X`uM{l+G}!ve zDkUBTy{B_aXZ9>~f9)53jy*s5)S2J@o!>*IZ+z{JpLy$Rhm&BbV-JW9fk4a%(8W0f z5&*`xdx8TvXT5g&;K2jC_bk+RV=ayI2 zwl@IXbXq+8*psK8-t+8>4otNjY;U&?Tz<{VUf$pJj3>@dpdJ^6t0$FHGGMX5hzyJx z5W%5?da%8A;)U1l`Muxz#eG*@6;{p_##JciW|NQn0*=Q{oQH0cvU zT}x%#8y8O9cFWbj^=ofywbHaby}CA7UtiXGc;od)UvS-Z&%fdLpWXh6B2RkVwsTRH z1qLdJp3s0)!8s;kG^z4BuE_~N6%aiEMs3MX%@8NU6hM;@(J3r36P6tU22*6m=zFQ1 ze&PY&pQA;&Q%D|$l(rznVBWTM~*CB69xc6K-%0X%8o-&g;?v^V7U2< zzwnO#?Y)0ADRN6#(R=T}yUeE&OeJIlr3N*tLnx~be+> zC8=xEB=LK8?^BgL&w~gt5tC?Oio;KI$U!9f+z6P6RDqe3Bmuxs*M^W+d6p)xy6v{T z`({7+$>X2;^r!#(d;i;QuYToZQr>^xLy7lHytZ-Su_uossA%}y=Rdo=w3sGb*Cl)W z;upU7oGUMW;d8GN6No_)DgfxctLhvHQlA1~t-{Qv0$?J=%-r1Hef*2xyZ89@*FUGM z3Q-|Y09I5*2tiZ@36V@dGUw3|LBd2Kh;yzeis|0W)mL10XexRBGk;}s4CBdUrr(}R znr%)1SYCc}D@m`t{6GS5_>bTBBX9nRSmVcGj)6gZt|A5o;=ZC8MPSnon4&pA;O10= z9f26`j5{MMDn8y8(+CL>VrWcU3`H%j5W4u^?$|8R?>O<|dNs<7RP;YE0%}YMM2gMQ zJ+kQ_s>g{SN_PPbFvOi_6OI&3aoC6)qmfUW+6PUExh^VZZ*l+2h|D5UJ79#!?2KSs zjd4gx;?u2yYuNf2pgnUR$tWT`^{HB-^JmPG^vjAau$c=KD{`tT#CKL5Ep4qSXR?Q~VFEJ{n= z;fpUmx3qHm-~2;S2PB`hyIaHIO)t7>@%+-ieCD23r^B2){=^gAP8P-g90N#q6e^9} zOf?$TLR7H{5IK>$@wtGRMMDN6VQeeNcJ$L; zJ$>fMp|AiV$8-jY?0<|OXQmMy5eF_i zLCa`}3=Hx9Fk=J6s5((oG2$I*BAaTXrv)UyhVEtYXeK0rc!^?cc`;&kBUmY@G-VUU z+^WXMR+lmy4qkA>bAS1le(}%#;;;Aa-CG+Gg9bom5i?bhx*QCGXrAZZxe!V*WF)H< zf;dOFzWBvw&YXGZk(E{}LoiYxP)`mK@}K|`6c9OTGKmlrLRIyrrp9?5LLfvi@y?41 zS+trf5~6COr3hkH8bT#uw7oSmKR-V|f8oMfSyY@jBCJ&$JF#XG$JnTqV;CeNh7eSh z9n}&Pl$pxBt}E#F``e?@Uw!C9zxrSP%fjx3>6s}sK;p#nkG=7=2M+EVk0)Qf=4bFM@(K+&kvj&)L!1Q9hQKn6gd+5`|n2>Sq5L8-oW&7ECZ zT;Co{%}gh0Qky0|THirc5Wsscs3O6q-aB7uPzz!yBIfznA)@0ie)Zc)>Q0?H-|0>F zdQ+`5Nz+8@dV70CI5~0h>7{e$Pd*Ru!2s zpf>i-2r_3CRSa9(>z-ZY?ndc4?vz}02xgY&6G952Nt%?+pUQg|&w{G1n$p~M7DdhZ z4@ekElms}_pZerK{nOUQR#oTc&YYZ?o?cs9zw^$oJoozNpE~{2*5>xq)ZAb=9*zgk zeCGALcFo=Q@IzBsD?*sbNFy%_f!P2tPIL2ovS;sJX4>3bt1LYJ#F+<9EYD2OZ*1ou z{>b01Z*8V&YC+rW&bPmJ_lsZrB6fQJLl1u7uRfgmRvc2ct=z6H$`-#3zV=NFfN58xMxWwExh7Uat#8?Aesetgb^O z9TP=hhD4tm0HN8q7>gP+x4aL`A%s@9owPf(xwGdsyWM`f(=DrVVfSp2Z(e=nRmEf^ zW**!{hc9~GbFcr_x4&Hhlw~p1pTGV&&wBFlyu9U;De7i_C9k+(4U#T;ig+ff)VW5HTTW$+*Mb#80$ML0(Pp)E2<}*N#A&BCRa|plyLS**|5Q6}y8UO#7 zOgooXBaa|LRYL`2$EHd~V2r*NK~N+xg=lIaLPH1|%*0_jsHo!P@SY=`>0N`-HXt4B zyXA8aZEjbkRWEqfCHI^f{rTT~abhzY!!bkqqN|_5QiKanhERJDpyvCtnCpdAJwE%+ zpZqO^@Whi#fBeTEJh!yu(y1jG9=d4v%?BsC7EiS^ivVt;NZD$p+C*vw0BXQMVq!ps zkT^$7O@Om=W{?sBurb)~cDqF0ki6%*3TVxn8bY0>EyN~#!%Ueus4y~-|JQ&0%pG@r zb5i8(cIT-RPk-Pq{`%HiUc9)p*y(i%K#IJ@R*ts2Y3G&~z3A`$;qNiRASoGFMPAfC zNx>8`>Vu-9O&J+fjZ8EUl7&d1jP^D5M9#tPy$c55!7&mcT4f2lU}}+NAHb(15(tbO zlNp$@bD2-dviSD5zrVh*y}Z06ifOCWO0wyhX%yMo9&HVWrok~(<@nKu9@^a8>`r(4 z{Y#LTqjW?JBXBt&}9Du~s(gHvYN5k@WxYb~yk@WX|rwcq@WUwP-x{UobYG7ep zl;k*XtcScI;ih^y|!S zb8EBA^KPr1Ac)qTcDl5*_&dM*KSC*^JU7AVss6Z}2t&8qx#ymH?|<+S5gU)TnQ5xq zI(_!s!^e-QK#|we{b?zxt<8ckL z*J`2`V^bB~PrdV(LY-W5&9%L5r>g5tx4XI+CgWj>n5HcmkMnZ;_*0Kpu+c|ya)KgDAm1Z48CSp|u0W+)W(m98UqQ)G> zD2NsnvLULkf`;a(MbakE9Y~Rp4R(l+O;-zzGECJ#i8v}m)!d+z*Jr{6{AqrF2_z(|9{ zC{lUomNZB(b<*d zL%Rw!-AU1j7DuKud0gQm8**hYEQxgDEKu}Z@ zjIPgUOEE(Ohb$TlW6UFH%)?TM07Hme3ytwFg6K4sX@pZ#v(wLO(EtD-07*naR3H7= zr@!#oFBstR$}*BKLP;)FhPoCF(oU052j`u|N(u=LN-0w39eYy{2*4cb015~e%F;P! zRu_{()d&I6d2*y!hB9kq*IoS#LR?&28jZ$@&pc8P00JW*#Hy%69lU2C12ILY>x!8j zW?7bU%au}XZ*R}``g`{83CmUo0aKScMj(%cqM8!2cg%)r;+UM{vMdpRh#b2l&CV|` zf#bFH^)yLZtyB!|y6e963+q7wqCc>I|8#$v4A1F%-F#Y`GN z1=vTVJ~`sXcPnNF3PKDBfaC$FsLD!oerDE0gD5kapppSW6@(DL1OQ?rTr4Qb&;SCM zcSwL68-xG%L%)2z!10BP--GB6Nt^)D zL#zgX$Z-I}ObWni$RsGB+)Q^Ir&(rdrb_GxNs%D7jDQ#=UIY@vJMW!~uFg23AxCBk zX22w>S_cDV=AtUi3=jmBk%>r6nIlgWm8(Ro87;Fs(!%`rKjwYiZqLjrz6RX9T3;`rYv@1fil`@K|gxT5o#~wYd0JGDx zZU#bCZVfg>ab{+=)#;c>2z9^T&nF`TWa2%$cAIIt(-{p%p(>`Pr^-;Nsp}mAx1DoUS+&}}mLLf0>svwW z+0T3S;r;tL?FJsuY!=V&)LdAV#UXh&%wnIFh!w)&RuD_RP(DV~Sv+%_^C&uEThoZx6PdcT@do zRIOFlH@8%z({3k8f@HvGMiK-VQ{tk|2Lrn5#^+LR{_OfXsud=4S$kON`tteJsj3e7 zg$rkHcvk1VzxVEMKQ#F0ryn**R<|zf>GvG+L_|Z?a`E;x0?1m~#!`OC#Yd(WX8!*6 ze>rjD=^LKAZ#W#CT|76Mg!>+P;^D_0nV;*t;Q7z{k+=K=`6&x)Cr_N*HJ2v|Kqv>p zk)j>G=t$-=RKT<=Py^!p+%80j8f`Ga==36Ja*LIuE?)Dp7o9vedf@S`zxl_nAaLrO zMtiX#fFgsLnZzVYBZLql^(0cj4TC5JgP2Jc3=n~OS!;9UX|1*eF-dyDiJCD{HSU~V zT$%3oEWa|Qq9dyclvX?_g}Vp7Rrz#20~Yx5g`GZ#NT8buOTWZ84{Y9fr3&a zTM-E=3g)aCMHreAar_eFx}Rt#feI00b&ptE%^br@qXPmZl6}DtNlg_am?Da}V~GPQ zvcuF0YM`d7LecIS3#y$K!ggXf0TC=#IVdrv2&}P`ngj_x<&&pQO!CRh%$%uJL1Kli zqMjWRS5@Vl(+~_$KoJ-iIS@KThBWc@xEyY7Ii}P*LJJaN6tyu~Ld0pP0;q*hi&ROc z)9rNEH`bp%bILpK9ZM)3I}rg1Tf+?|%i7ssI4JAfF>4KlV7t?wnwnLu`|a7enf_ps z4@cvyo$a2RUtV2Pv%0R0Fi8@s1uSZYBaD_rLS5HMlB$X)Rxa}2R|N5Pa-&@YobaicIGRdc=x>X&_QB{>yFy~@UAgG8bkc;R8LuS#M zm|}}90*G-sDux(B=@TSEm+)XPSXo+K*t?sV4HSv%P)VaGAwU2I*)bELA_66eFUFIs zn|YTGt55>82`&us{fDohjvoOqfCE^{VSAV#*mr0PU>X2Z>U3M8K?0$`j@>t+)lA~B z7!g#75tvPanE|21fI*COBQwwlkh8}50+EuUJ0e>Ei%TMiH#2~l60kK=F2Tspq$mWp zM$Hb^7)cDYp~GqPtD`n@6*aJ(Jr6{0wKN3yA5Mt?2?+&E$sh<}lz4&w5E6i(sfi(( zi0#aVPz^}Iu@5Spc2*Rngb)Fqrusv}Mf9nH89EA8P*oQh!4W`W7*rfm+_I`RK`o&1 z>y6Q;3TQx0AVVC^Mrh{#1N;B^pFi`!0}qyEaq_7rX8Y4;&z}46|NO|l{rk>7eHIab zfYZc)(xi1^eXKs6p6R1PDRsP}70kO-RGA$C&iJGXwOAz*0J*O76K77g)Ap5DUopzZ zNuAY|WLfLrp@W_2Zdn(A;E)LT8(;tC@h2Xenx2~EV-X#X#!{7LR+SZ?V(J*2A(EL- zedVgTPCxNZ4XUE(cDub^Z)s^MgkZ)}7VHy8PD8k`zP7Zyx_JKl#_C#-(CKxqx#pU; zyyY$VIM3Rx9TFB0Q9c=a0+CRZMOl>q;G82O5i^Ba11BE9>Zf!`L?l`*%z)G^N(#V`xe6f!t*iRAFL~+3M-CH#sD0|w|FW{OIxdQfFFyK)A9>^S z%+$u(=A(~2e#gImrPXbfRr#9RUU|)R&)BsvYXp~Fb=Ai|{=c$R6LQ4S1ZXA^!L@_r zkK5LmovvbLD$&x?WL?Ll42C28f`qoQ0_>m^C4QWyk};N0U+KCp4& z1k@Mabo2Fx0A7CW)K|Y!J$UkjP%8jxl2J0nmaCPiqo4$6WvBsJ6(H#@on2DHjg7Va z`}dLel@#k6o4Xb|WszTTpL0$?(WU2ht=lF?5tqid=GnNWBDhEFr$T z3KpXzRX`QQR77eJL(QjV=bn1%^tq>tL;LqFt!`ez+IJ$sg3u5|n-rlP)4Mr}ws=*;I1P&GL5T6QutVt~ z#1Ib~aAM7H9^;eIAhQG@5P}MLB8vlOKrm1V@yv^bkE#$85lRR|1X0E!@H3anR0o-sj_GzlBX_i7I1ilX9y+$F#M*@r`eNBhu>HNtz~}+n$IflksRgdiASc zx_9q96JB!kNUN1v(6rUMusQkA2S0lJP zhhqb%LgjsO(ZK`zcg+t+1E0Hq!VjZt1(UgbPB-4TUOmV_d#Z)}uOIkdZf zaMy=!zkM{`6v5eWnJAVA7=xL)v27DKlP0mIx-n2Cga{{y2^UfK5mhoS9=0eJf(nxp2@)z! z61C{81SX8q-8iYVpovE_u$b+Q;K+$;P$fi>8bmz#`156-prKV2d9Fh(b)EG4c|I|) zPP^mSZ&n)y>N$}{H!a?IvFHUw5o6+Zr#&eqB0}t#IfT$ax>Nx%^FD+CfDmyUDu~U) zXpy7@s0MXW661|GzToDYZ$5eQsSp0;2iDiu-}i@quxro4#>TcszWd(0##L1Z`|-EF zwcVY1&0F3vo=j%@{W=e2EuM+ML`+Qp7%=ffKoShi#DXEKYT{f#BXY}2E5pfHz_uo%lP6EkFU-f8hKMY$tQs08 zPDSgYE<(LN*jiaz-Q3)*X>RwlZ}n_sos=#&Qy`vOr3XXwzj-< z%Z<;Q@3*xWRCV1P!2ryxh#pBq90B>Xs%z)btZ``?$C(R(NaC~g_0|9Dz5i|3zQe!$ zJHH=lF_qM(d-fiDz0J*Gr_%*+-~RR^58ik0bbspb!6Ogc_ds0GGXW?@ z;ex6FL5y_)H4rT(dA~P(VVtk6t-a!vFKM+}0q~1o{%X2C=ytnRRV~cS?LV;R@PUiU zU|+xU8{OVir=9)FXa2dY@>^f>lGA6;J@UvgtCdn>c2U}hKwx4>3XuSTjbbIXv5lH= zhad+4fXs31*@VMIAsaxXAvJPHA_BD#qz>U(&wlnb*Is-2)TzJy=-(xYf7{#McJSaq zm-uHr`?~l4;UE2{H^2GLZ+&C;?tMS=b3gaTfBGlG^$o$$?;kjF(Pa;Aivh7RfL5le z2);91XG``};T&TP06l=8efzDy{@%}NU`96dKq;UHs}PY4Nexkvd{G3Lj9&S&8@~F@ z&w))2??0F&X&u(eoHo`ruDtx3z55mb7>EE8RZ>MU1mdjSE~_db$DW;Y5;Qja@fRQJ z8bQ@6Rb@nix~vLCGSzmg4X(GoIiBQoMBqewLF~d1C@-$;ZihCqVmumSxL5-2Gd zAy}k%5!M7SNY9UgZrQVrDYzA=z2?H}n_(Jr{A~K>0m=vvqLp3f(+gOxc zc2X1){o|s7uw4}dvTI?cleMO&JJ(+GjKpUTK5*>5`yZ){ru(ywxg3uOgJ9I#2nVX&c;0OQcH-77P?|JZ%)eEaWZA~vMY;J4}^KrM; zO0%RKmx$f~ilS5yCIV)PIAQ}4ZM9M)a#>pExo3CL;X}udAHU`1n_v0r+rEF#4_ZVo ze8CGt9T0(uhugzLhxU&uEd&&3bA5VD(beg*Q4rRBxBgDD*L?ajpWWV`6ji-z*TTMq-b^=3J2MYHdivv^`s9JV3-5Z*FP9a3 z{_~&x!S}wqdu}d@Y-1U1X57#)fg7x>G404;W6D-6XUq`U42{vu0yOqAFk}V9=y@YC zEi z0-#S4Q`I2gDB7uN31E%1tdU&BmngP2P6dFNnVr@l4#^@7D1?9pNs>61h!jbhF_TaH zWRkaMIv(73Ja)`=sKiu6(&(q!R=H^xif{2`Y0(9((q5uGP3<|{D z%xcv*DsI3K@ch#G_y6JVzW${z0)S^)b^*;j7mKnzm} z0KiQ*z3`5&ex;KnM4Wn`=XrG6G(>n&3o$X0F05^&StcSrmGMi0w|R(@wXyw`S+(_w3nI z*EJJ`x@N6&qJRdL2&yPcW&wckJVIUN+P~`2bleMzCDnlKd z^M*Vc4rgcQe)B!=*}Z%BJ@@?J6QB6_&;R@{eB{F)dF+wnuYS#KKk*Yk{_#(I>e!>l zcJG<{a5W2VF>k3M$%xz|7M(MOLz z@x&9ay6qLudCs#x|M@SRUp`+{#pRb>a`VkEy5WT{Jh!-f?2$*-S1oXSe60W@B^6%VtvR{XGue-EbBwDo{ zi3E$t4K$zjPMlu4uzLQgEBgQYyMOA*W9J{Z>l^(pwKC~W*_D?p?C$Gh_kHK`>v(?u zl?KCWp7q?atR0o9m+g%UjFe_sRaUiVuRlYelkq4`d!u~NZg*#9W{@?a*bpJ8SSU;_ zsEmvD!hx&T%B}S$9u=*C7!8rg`$QEGL#P8X#vZ^sXQtjeBofusCx9jz<$cj%8M9`| zjDk@F`%A-4Fb435-B!;5fXM#6^WFKmtx>+Tys~$;TU295#N-MX+%Tb zMv8JbV5V_hd+%dQ?Ep~_K;nD`QPo+rl!l1GQWXUd6a*!p00Eg;3Cu);QnXDom;hRo z5m?OB1>#0ah^U|;D$xuLoVgn6NVf$sYM7x&!bl(>qzJ%(8qsD1ro^Oi_z!|2)!6ZZ z2F;SR+naI;ic%0z0HqiX6PO4?EZvO2G#1Dz^=Ju-m8DaUpYB~ad-{ZIEo0y@7_cSG zU{F+H&#u`Yd&S$978f@*7H@pkExQ(W9hx6+t^Qznot)ZW#v(vMWJ$2$=KmTuU|A`-c)lJWA_j^}ge%VW(c@O|@z4@v)yzXc6 zB2QZ_*jeN#f;AJTs1OHYXZHUw_1@8zU00d!3~TMZPrA9nttwS1m2#;hS=m9hF~%5U zTg1^oKd`~ZcmPd53_W<=3lb{7CFhLV2}b#sn{b4E@{`otZGq!GxCTkT*XSr zl5;Jnh$#V@2oVsIf<+YsCNfbbY!-=-It;ae)mAY=1a@5Hd0mH4)p?OS_Gn1NA%v>b zcB@m@ff-f7Ij?jgdoPfk;t*)x9XlOonHUe6PCKAG`1o_3 zq8)4DoT5hWeN-c6Q9%V{u0zd^^E{uMoq6_|n$%KFn1C^{mR{0P-T#m z&2#|Rxch_%NXd~i1XE!kjYiJ(CMM^mXNo*4$Mx==yD#6j|DJpASzGVF@ceV-xIBLJ z`1T$1XU?1sbxlBb-F45S2M^B8&dhJy{_T72+8C}+wR_+a8kJ)VM21XEYG!DZw_EJ# zLx26D3ohFGvp@IK*Is{vMq4yQ&IntNj>4&G-+W{KNzI zU3ku}`PaVgb&E^O$6q|wZWZlz8xfmm6)JPe=50bzkkCx5xx_17QyNYQK0Oih0s?a;BWeDtfZYyOju3_f}A&dV;` zS#4-pdz@@Ti?h02WX{(NASryHlB&kp+I=MTSd`0&v)OG~|p ziM{9VX(R8s^osr{d*28C4zvJ|Rb8qm2t|nzObs_S%H@9O&1^@f%w9y*G|MtmKtjh1 z&Il2FT0sy10g;+HW|Pg;79ng7h+t+&LIxU0EfHvt5CDpd`osR(+J+~GDpQkFDD~Ne z6Ixd^98EF^A{j~|Ko~M2!AtQjO7KiD6;tN4YiCe%&M7K_Ik4vLsEG)Q4PG?KT*-Uq zF}06V$_yoKh5?~*3q-W^boT=rmb1RVBm_gT+e~sFv|)c=(bFC;#eC-)&%m3L#Rf z-RgA9syzRKy_`>8bIm0$JbnB--+ki1V^4kmzWef`oq3#`Xe}Il?#7#Mdh<`d_LHCc zdeLqnq4OC@Q~_otYs3dl4qHehrR1b`F-9{$pxk@4dR&gz*4BF6?mhS38$wuHUpsZ; z^y3E)9((a1pf@$Kv|4@t2ai1R=wlB)wAa*5pE+5MN3B+Y z*z|xj9;Re3H%qQ2LKG22V0$T|hX|PB&<$kB00HWk@h& zB@?PON$IoCH zj=`I5-ew3XRCUzIl#4}Gi800)J!LTjRZZQE&|sVrqyjlzA_%7Hn7ZBWnUg2J@tyBX zbUJ6xp6ai!9qqlibN4x|Ry)Q}jjIr)R`EXTbbBXHt*&eg=C*DDq$GN#-K?28pj6N6 zy%UWw#sr^@Dv(<7Qg{oA9axm4o`NWtMU6i5hy)VTJqy8rh!eFWaZtg)A^^17?f&`( zIG&!JX?MDo&QPFL4Bqmps#TRZ$%86U^H!_XZmsoK&8*$x5JwWlb4FRas!+5taAcK4 zu{x?5fMXy9_0FRSqMDWxge)5QajDFdJCEQsmU#id)N*dUzxb6qzRZZ;J5j-ij8J0T zo$MVta(G;pAqK4~$O_|BNNH(RrU)t#Oo2dwkg18`n<=0mk#hh_tmJ$&J9grD(dnv4 zmb;(*`Jb8SO@8AW-&k8&`H45a;q#yWe7`?9d-lxo%F?l8FD{&2y!hh1uXy>*j~;lm zg~;S7fhRx1c;nG>f@KL5fC-@f-GvaBX2CmTmWa!4SV zCLgjU?n?8WPTw&|h5=1kWru8Nz)1kImqJyW&n-)4F~d~)XWnOJS;Y{B1BgM0D8_ny zeXXp<&U=^Tb*RVV@gomEa^=1&FS+!x7mgfK71fBzgo-c%ortl6h~z3YzUBr-*mc34 z*-keOs$;9mk8TXYsN6Z#=`xKq%}yz{p9 zSNrSzjmeqW`ExFD#g6yA{}XrKd$>C>XJD1ogf0dJ#2|qf!7v9H)~BXt=Ded?m54>m zP?CRyiPM{$a^%S{#Ds=u4FA8dm?0-M2^38%0qevwd2&gF(;|Ok+WoPS0J!-&a5qP zQ(K&(tgU31O(p{{;-c%jI6YU|uhH(lF;SZ2bru|YoyvqPrk)s=R;?bzM-z5825vG?2y=I3`@ape_{ z9elLEwhE>P4jkxCbSK+AWE}R_2E*ah^t6gh_BsI2X|Oz@Q=`3DS%R0FsQ; z&8h-X2_q>9C#uu1B~5Tq1z?427`qa(+U-}xus z8khCd#6$@3OLu(zqKnQi3a5fkzwrFY6K4^^iDNIS)=xh5)OqLZ@jgRHMqmIl2P7ux z-j?oTBFVCfXqZY9(UKK08KD4^6WYaV&va9US5=LX(j-7sS1M7MA`v4%JIh+F zR#D{Z{k0e)AhP$ZR=cihcASO@V)Q=qV+RIRU3u>{3W$Xm(={_349I&6;=FfA$eJX}nKa#GAB0>ArZJlc=A3|PzM;zEH>C~LJD=gZR_^Qi3v3Y zmm{!=7VS29x3RIlb;}kejv@r4isNdW<-W-BRC41yF`24%igp3nnbp&ysBCrHck-#8 z8OJa%tu_PUseHk@ov!yR5jk&LjArYxws8%Rx3jiK6Gy&^Hak1rn&>SrEqkA(J6ni# ztJU^dhR&Zlz3A9y87ruoh^i;H6psKiG(zB1^33AmVz1WH}@ruo5GK`q2+Rq@4UCX<;~AL^UQ+}KD4~Juy6krdv@*a_cyM)?%LPha`EA#<3Ibe zKRh&(Z=;AMY`O6nydiihv=5PJQ|N4K2 zgQ0>s#8#e%df75pn#t=e(}lGbfEP(v2T=RO3DW<(wt2(%6W3B2Kn#n`z9*oi=hsn?Gh$p-+S=^y5%g9kU?%oI>I zAOm3FG6eQs1dIp(naTNFYpllOJ-c_a_e*PQ=WOfkIcI0a;pCymH~LF?PAM~NW=2?x zv}lu~LntvVz|#N_9k8mg_oLx3#l)N-01yKL0!6V@5tmw~(*pnj8Io_-6R1dfSR~IS z6A{Fz>F(M}IX}PE=bdUi7!Ed2iBJH8N`)3cQ%wbtf}keWSK8v3DX{?{gEte82!H{M z9GIy0q-sPg5($CHftkeGBzmF{0y7mwOC$hnic8J)i3&)mhg+4XX{JEc$;npKGDtNl zN3~j(Wdf9CxdjDdKKXiybFV{#&D(VW9NjN`Z#4WX(5+{$XdGpMiF&n_##Mvh|c z+*Mazv$6i*(%Rzg-B%p=!M!t6?aQydyq&w2BNHWZF3<8TYAuLTWVwJOdKn<4?1rcj zV!|*qM+^gIFHsnAFdSAP##sOKTW`Jc%6$y3T@<@_?fSy)x7X!pII36H);zNJuARAd zyJHd4;|CDxD#RKPc|0C@@0mCw27stSNG=TkW{!M_sn-caAqqfUFPuI*9F1dCL@shi zs<94~w1tMXqsg$<%;*jrl8B7QgJ1oRx9-|9@ziriPA{$QIcGZp?AX4I4ci^R5#aqF z{Mh;DZ2RS(dsC(G=(9(D^Edu;doB}6(-XX8xQn2qM&uL|P5{!z)fx^<^C}6QSmRqn zW-|jK6?KqA98n~ZB*lW61+$E}v8s!5vy)NSJhL}`Z$>gx6(S^nr~-@$2iKG{8X~g9 zM3i>`2<*fn05(945G@L_XCjEw>$JV&a$HhIo_(I>L^vFdLLF1i-#OMGpvDNsR97`K zyTa#LVPIzFkn?Ukgs`%*GCx1x>2-my-RZ2Ytfk^30y0I7lI2;R=id93)s^I}cRnMg zs;W_fjm0g*yoiJ0Sz(TN%YNT`dV#q1E#A!pu~ zRW+(cv8*hbfRT}ibIxM5JSb1^?hS9b`Q|Tw8I+5M&Yg(8F02m9isx4bJ(tf^)p&h4?oM_MOhmE_4N|g{R77IvR6kKX+*SO$lwsbXStaT`YXG4>>OKBRT_e{iei5I z_NSkDj*$;N|HAU>%5~RY*I(e)TV{{Eczk+h z?z{Kg`y0RZ&NE9(*IswS4cFfAd%ypmfAS~ac*PaxXBm9u_WS?CFMjMV|JVE8_V!=- zqxb%?h&q=UqJpX_FEomkJNMKI`15POxOyHzO5=h*41k>i8*F2Zg z7Jp-~aoJ^;`ON>|``_=iJ8yi`n~GNZ;K4^e{5OAd@Uh26!|`pOzU_B^_dTz9#Vfw_ zr8}(1$e`EmXNQu;#Ga%5Q zU`U0V-1GEF`<*|zefPQZuYJvHF1m1U1pNN}4<0yh`_s>z=2kv4J)dP>4ePR$7{Nkb z^ageQcmH(Xr*8ZH?hDVk{Ibi>nLl@<4v#(YwfpWrSdXFGnKcwp4MygiNfa<6EmaK| zL4!b^w~SnBqJ|;@D#gUi{F#+ATFcbL zbQQv=uC`3J&n%r_H2p;7=#{#g)_1lETXd`#pmNS+l{GXPy(?oUt6_`D0C z7LAFbR*Y(Z$n4OAVT^)o5dr|Iqzb?W@h{0>W)Z+()4*YX=sgJ({;Rb=$UV zJAC+%DV(!=*Qw(tzy7sH;>)ofI6qIt1sq+i5K?u5@OKjrFyO=`Ci;#7JC)7!}xa1Y<-d1WkZ7 z#dNI^l0y@mY)zaxbEeznt=s02dSx9aXC^jEu^2X_Qs!>2-RaC6TUbgQ{oLo4{I5XG z#wWpIVe|TIptKmlFeQl)gNZi=#E51_4$;yePY9xpFs7_kSfRR$gIY81+4LykkWN-igs_0BLbpe4wDjpIube0!+6{@J> zy|1eZQqMEmMt?nuuwzDNW+qnGH8YzbF>%JJvPw-AG^%7iGqbW9s|tX5m(_LXw2cT< z5gD1V@GUHu7{nxDE~3<8GM&#%^d_yVRb936!VD5Ym5EapD``onstC*sYTyV>CnhHD z_}bU*y8G@^$6s7pI(y09i$47?pZ)kh{?pvdEE25`hNEg6#m3`ucFWeK<-RYvz3wEd z3WAt1I5Ddwc;Yn7fGLuf7(G(T1VP$nK_h5!)7=4$S;2s!sexlc07`gKNiuQ@cw<8K zs+uPbpa|;NJ4BHfGpDsVg&1Ngp)rZI1VkH+M&9{m*&I<6F%uK5Ru+Hejr-sEJHG(2 z{H0%i>%vL>nYaCE-kWaag^mLdfC3m~z=B#yC>R`Paj@8Pga7mXKW(2o4dgdY*}LEK z*QYlEI-liPo)zWVKuqgc7MKfT3JE%cQ4A|5R}LLHwz1w1<8r;OvfPh{BLhUUiQa^3 z=abV@qtPh$nbdJ*amf)QI*D<-u|B+(qNy8FTFZ*co2_D9j}+qOcG&-}}0fBUz8 zGuClqef=HpdPkn;|M-c2c;bmCe)?x`z2W-nrl%+V{%`-btje!`^{a|%Y@>3VO1ue4 zKmZiX$cV|WuMaQYd(p=}^0(vh@Y&~{{-ZzsllTAS`)_{vE4J@Ep1JJFgOBys*FOA_ zzqxqtMZf=^U)y)(Ra>^sFD?wvE-XHD;NivP#V4M4{57w+s?+O@heLpj8Up}=q%Siy z-UMs9FH{XVmFp&6BnT*DGgv3Gx+!3)Kmo?4o)>vDCJms@k@x-sANb(X@)8nu+r4jp z`|jh%Ph5Z9%l_?-uNJNL9bdZxkUa87Km3tlRZmQI2SFVH=h=!`DLm~+K@71X&O`?y ztxkJqkxz6wE$8Z3VWpK?rKJ**#IUxcbKsCz5eNi;f!GL$6}bYbt9<48^1!oqhzb)} zB(vD+Z6&f=L#S23s_~Eyl?z{M^tewB`!>6qr49*-Chzvj)96>wFjEu~vsRjTNBBZE>sE&vg z4Gej60ZU*O)1f8BC=Ap!b1XEu3^Waps_m&ZB}hI&1;Qr63ZQDqtB6P{QOzX4`d}P% zDTaDnsq-zPV8~#ql1ktV9THO1U;su0>J*}=IA(x`?%!x>fM&om_o__Y(Lx&F^ zs-v|!ou$>4L*F{IZFYKcdafSF=MSH(lu%@_K5%))DyPJ$rVaf9{^)XfQo9{g0pe)Y8&&ce2-+?7sK+-#uJ9JJ?uX z8drb)xBs+!`fR7&$}<1>QqZ$W_Ij| zGxCZ!7>-7xlFZesYgLTM6wM?C85<%|?i0T#0;(yf5t6B@21K7CyS~VZJpYGJe|gX! z=6TC!yiwN9XIo~sIC2{s8^=!`D#N&ncgK%NEXS&$*K)=LoK9N_&(J8@mKa9lAaxR= zF*QkOVpKJg#z)iWYpO{LN=dhri-v~g2C6_WffCcLjgS!{C=rOH4Lm{`dnwUjFo`Cq zdbU}DZJz5a5kiU5;)TIf#8d-XyVL4*yMy6SM3KpA7!KB3t&a0fq5y!J5R+#_qfPn@ zmR0GUW5-D3QY%5zOp9Pfj#O0DeCEokoZGf#G#U;D15ri8PTqE&W0di@tgEWkE~ty0 zc6()YWoB*$5l5rZ%$AufWaYRtHFgZPS=Is6Fs~uKXfT($3}`eQop=kMEh`Mw`{-D{?&rq!sb>-E8?tn2ml!If8ERR#Tn|MtgqEsQxLc#kot0uXWI z_TIE;5Yf5ko_pW@_W@d(z}UcufS?BR34TBXA^?b#IK>9ZVvz=qAe2#zF@64-&s0P- zrcaQGLLJhf#888Ta#Z=uGl7{9Q@hit>rj@Z^Umi^R1JifNXTc|{I)#+9T}`LwYJR9 zUvS>8m64TIsb)l^gef{_f`lLzT7Dv$ZrL{3K7TKqT7b!-H#>XL#e0_zo>XGbR8=Ks zuGt(gCbC0ag~52ZZFcK5S6%bKgAd(w<29G=y?AALS&=%ET_)^wTFc9eU%2hInc11u z)m0*D=dCxq;Y}Im3eYaHxotbKXdgYfw9+4M+p#C8DOl7vF*W_Q@71;pa0VB zUwrp(zWeOr;(hmj@5(Fp-Ts9y{^0vRxap>sPfksL>C0a{cKlek+s(W;HAJeV&e$Kl-kB{rdFG^k6u6=eyovfPeq-Pv&`k%d2m><<+kVVt_at4jw&t zq~Bk^^Bdo($D{Avcdr3-Cni++)1Ur!U6#!j9}?fGaq2X^TbdRppc;uN3LqnD;!6>s z!zM)rn9^bhX100sQZ(cg!ZS++#E6*Z`RP-q6|L23nHf8N{D~(XJn&$z)9rOS$*SLK z=i|C+6|KzEaJ1|}9jWO^un=_#p4veiTU~~-XaG?`uD*Feaa-iL)_Ev}lNwc{Pn={+lYsAthJuE~bsf>vHT&a4-)n*m0Kk-Hf+V4UG}u`{ zhpH(6yy+SvG=r#GmUU-pCOF@n+_IC3!^aNidFESr3}M^c%+i^m_n4t)0Exz!?vo(} zR1>z&DB0J@Gl)b~N_PNaG)F}2y+cH1uIf5ze=ZFx$=Z?x#Z47RfiOj&byJ^6k-N04 z7XTt7Vl+ZWRjpM$G7$7FLpBgGC4)o&Pvw7Nh76J{$mxg$F({fU0ErkSs5w!B)V&0t z6V;gT^0gt;dK5=f6FeR2P}Nnh=+>cDuo%?<0tfO>Oz;CqMW6 z3rC0m5eQ=DhWCH{Njd71zA- zfhSIW{wsG)PHtTvu4P3QLNF0FF6+h#BBp4XaA-^r5tG+atagrlGkXC5Fmusree+x2 ze0X~Lic2ruwQJ{@6DP-`k?*vC_~hwRFFg0`tM*?4uoVDKz4fgh{J;lW-Ih~W=@0UD z_tMMvJ^AG0hmN1_7R9M!FOJ7UV(Rv$m9mMcnRaKYtgGeIi`8(g*LD)Zkz>bq?3mv& zH@mPpuIspM`}S6^7e$dchNud}UL~qRG+{=EEU`8)L``s)ai}&1>;Lf=-+bfCuK4Q@ zePV5GJT>ji;_j^(dbi`+%bo4}=YRRvTI^5$$A5YLnZqCd)MwT=HdFu{0Z7t?Hc$J> z8fGfelnOS^C9_8KF+Zz7YLdheOtcsxerm#l_9%LW_ktyWv2m|=foV|$2sp7;BGVs6L{636AZEGyGw zuC-RX6_;XB6skHJ4Xcw?jMC}0i!4I`sYOJ9Hg)S{)-f}LO{+4julH|x)i3u*Uv z#z$u7wrt({`d7bF00Mw0h`^{6VyabpUG~mx4AxziC55M9VMnFrV|>XP1+2w{jK9 zeC7}i9(ZtR@$3Z`Uf3|*0Z6kT;~;e;0dPFo1@mUvU?Ag>8?zB6-31;VC2c65?PunA^7X6*POvg%?yI`W9z~G$(q-X{anMv zd{&~h+64e4bihlelg&g_@}?Lwrw|bv8E)b#n+_~(JpPCVirP#Dsrxs%TND8k>`{#f zdlS8=Qin=nB*v-fNyJGNlMo33h{Pnz^AL4;Wm#jCur}+*uh`ys=*0!gCdO60V`i%5 zJ!HNsnw1tpy}Gedmt*#vAx>u5?nxI7u0%pSI{no&eEiT>h(npXA4?Hp_wWuC^I*q&c+k) z5~9Zt03D%#xn#frU<9;=e{0Q1%V;L54hSHUV^YTs)I=H!HzTkqib^{4iU|@nk=CukiNz>m5K~sa0*1|zJh(r+;Q58i+KxPL>CJ<4;fQdNa zSPepm?L4bR`Wv=hhSkBsD{k7exH5kH>9f6d%X6vZ&=Ht{=&6PAiIc-_yPf6PuI<@I zy?E@z6Hh%mAsj(;-<0Og% z1p_29F%e})2oUPXRHs=g^NtYmqVUdFbxCZT(fabBu4*D;muXaqG8hb0R799u=DnD; z^BmQxs><`Cd36LL=8&{`!y9uOL}7N*Q#1G7cmJL}ySuI8;YS`_S?NFc(4+tOuV3@t zfA`*di4l?4R@Vok>gHFya(&Yv-tzzeAOJ~3K~ykYU0iBSOg0>DRR9zdP7#1K5vG%| z%Iew*5))G9U0nu2aEJtyCL1txDc@!Q|6a>Y*kFH=m>g&5P-<0?AS!0e?2yHT8l#aW z%B|EP!9LIc40E5Ab-5vufQVv{sxv?$d3LS2$DduD|L(!uWv%YSx9+-UxnCFUw!|99 ziwQF}=oHS-90Lc8WAi8azUsS`VcuU@{^D02I(j;j<3JtSAYG12fjBkHF?p6mmE5D=#on=e*4?s zarHI(GN0dg(@kLZ#V>vF>Z`Bbw{PG7^9O%WRW%VavPx9bIw~WOBV(r@J_uYU0)%*6Hvt$13!oqMc zICk{7s;CCAOp;ASMC4uSHHgS!-szHRj+#e;QT?b z!TM-rdF6pezQ4S@)Y-XXX2-6e^t!EMdZfGKAXa=!a9%(u)sVXQS8A!60nW1wcQq|EBHANyo7=Zz; z>A@yZ06-NZk3<*+a+ecw6)GZ!(1Z(La@Has8IX6;nh$~iQXNVv(6h~|@bvc`XXLd- zT6nD5e%SBt+OfOa@kQYY4eFtW%4Hn{21p2dO*AV^1n@Nb7^KgD0GpCngtXJZR6vxh z04C0-HWF~wShN#hv~fR)SQ6n8QxCNvfEW-Hh%uXp05cjz6gF<~vWl86GO$GEN_8+P zK$@f|L{LdLja$f*JriFpDCxF&dcqcDEg3 zj8H>}5fZ=LM3osVL^TZ-F_;AB+P+JEW3`{V_T21j46z#Y=O#N@uSEt-UZW6VjFqVy zj&xL3wXVN#_>sY2!x)%@_gM_a-nF_DbV!56P2SUR(xyv>1UskIxL)6B%^9vbGu!|@W6M! zf9CXgCyp;0whlb{)Y``A;=LEH^@n$U>;A0Wb*_Kp@X@Jju6p)`BS&65H90YPV&QCW zvbXD;9jlMMP}Om2dN$Od4oc)spIOLTtxl`0s)i7Pcp^_QuEy(we&Mss3!-^$7kMsK zb^L7qxajkTjxL^FFk0o0^rKZ(&R*UJR05cl`oxp?ykA%>5ajtzp*|XmuB$5 z{SOXC17QL{Pz9v)zJpQYNitB;m%jO?l2YttSraIkPZ>W4Y^k*a%z+aNWD(IBP>cZy z5gIAYqL>;8Ic7yO5zj6KqYzA^7($Ez0nueaHG-0&5R_IS6GY3iVs(9Ey4#f~-eUx_ zfFTz5KeqIZAKW29)YPNyId`{#RO4vm1R#ngAC#JwQkQFGQFzO{PaNNP+wc5U730F0 zH8t!_&kU<^6sxM*Ww|Rl1T0!J=4p%PGLA8J+TFUY^G>g5gChjTndkMvhL}uEPa%M3 zBqEXMydz}-4qPKJsWSUk+m|sU$IsN{mZhcDZ-4XdZnv}d;tM<7;)=^I|Hhr)`q;-m z`+L9lp1GMV-+$oYEnDWcZr!R9K6Be`VEFnUf5Y_5%-ZU5x7RZRB4+@h4wUCrUANlp zI)Y-1_Ppuf2A4W$i~^``Y*Z_dlxYP?hD4H{SG~-~ElZ zzw9@RgIMRNQLAW>S88X%oF`ye>w*Na{zx@Xfd@C!wcfKsks;aa<=*4<<{fW_$R$YbMdrRGF0Hg7U5sJL^ z-1AR;;BSuCW!Y)BOf;H_#&+JuI=!ak-2^lgRU$UErthQaHwMs#TM0l)3INeeZF4~^ zD5fsY%}fE+#K6)7vOXNCK$hnc;<&Ec?KWuL@_7v7=*bY6yl5a~H6)^_k(dn>sA=;d zLPN}$6R9N0K+tSn)BmC-=7RUf4nH$BJ-x9p7*+Msvdv6QkB93rGmMpKA^c)C<#B9;2N8-bhG9? zV}@vv5=o!Zzn&U_(;Q5y21q~zY6w6Hn~s>Sh-5%cqof%SyC~_+2QW%wvzP#&A*D7X z!OaaI113TTqY0LE%n-$}3b7nl0K-u=sH;$$0J@N7PB8MG7%fC#R#0bTVD)HNegG|viHJ^s=D5~b=#Hut~he!&sLyZw$U_g}vM>Z_l4>bXkvx^vGzefkV$`C7jp0Qzfd z-4LcHCLO!ccmn|XWjP!TM1u)rdCo*?Y6wd!Yk&4r!$Oaq}pjj_1~7pf{s@=|o4HzYj^3P$n~rXbi^4O&emfBE)~^zz_q7imC|anL~8! z3{=%z=EwCI43JnP8i02$1~mwN!l@D>28qP%*%etGL2HmKYU+>@sD(Ux$B0PAYUT)tC`XS(LBtHqP)yAen>EQ4 zLI4Qmm?kEIK?pG+F{7#0BSQ48oESTK7NQ_y1Xx-;Tb04JTMX!k5m8i3)gbG%C)PJM z&aC!xmlxfMs;-Bl5g_Jy3%xV6iOC6(fG!6#Q;b1JgHa%K-j^DkYT>h5qt@dPwW>m1 zWJQr9Vw99mbF~_P)^#*Ajbah=!iz=D92n$;udb|>6`PRjA7{#U{P?h)Bs1-V8K}yp#%OfY|{g;n=WY zk78=ZGBskNG|rlu1C$gkOw>AHCQI_GATu+w8D!pXo%{codhZ~;uItKohjZ?|U+4&Q z0}X&60Fj7{A}xxd6{tundTh}_j*^_;xE#uw=dqvTcx*q{lx00n(psuDZreYcYXP+bRhR2yhCPsZ%Jt&Un$6n3s2^bH_qrz*XEuc|8rD|~JW zrYXdoUQcXDiYd8E*4RYTKbC5Vj+`}|Ok(Fk6lqGB*}z020w6I{R)?~zs$IKwSE83M zUmod00U#^Q=GPOktWlaK{Q#HLV119)SRIT zD5~Uq;oX&m`Prp;HE`foSC(G}TUlD#vUO&9!(^{q8=abTO)}=NS!DnXuRI5nz<)t{%XNwqZ@Z5@1>nX@h$sY8nawj8i2zBBqMU zB-thNWkYfxGgSacfEsHQTuU4A_3pK#@EWI12$9qijQ~af7#e3EdxvnD+ zwc0HSQF1jhB1ENz(P79;imHm_e7cM(35Fn1`!+OYaxTyF;b342#2%26??zNIVnLvc z!N7aZF-EhX%4TX%hN_(vHJFBaSVvWH&UHtoLUcyxoEyohs-q9FDyyolUikL2*X_P; z^VV%E%PXO-BReHfRAN?<^mU*H;gi$@gG71&h#HxQky0@PB`^i^)-79ax^d6HfBH+O zPMWl`#T&FKVl+eG@Q5Vs~YJVe7VS+qYjErCwfJ>kUhn2UbiHy)NS%)IwL0}=0Bs7oaNqu=?jduF=NU0C?m zlh1A3FtugNrd`{o7|V_;0>B^tnkfv{h9~b21_jMKPCz zFhmng-t~mdwWe4J&?rTroue2Hku*dALqauU$09$d_lS#L9j)QLcb28MNA-E_+>;~oWIX`n?> z49melK~&G3n=Q+FX}Pzw)SH+X4-%h!;mFF;QqdV9!c@yjOcKR0C3Cb|T9YP}hOuJ+ zOtl_Sl`*w7NOBZ~P)jt=v`#}!8ZsCptqq*R5F!EtITHhq5+#aos%r&EbzOkwoQrjh zOtnT9U_${=wmi$C#99Kd0{{hzAWE21*6OqoKt){cYc(=hTwYmS?X}u%i&jBQ>j*%| zeO5;;d&^m?h#`)&I~<@t=+~k2-nZJL3FEVQ;}j`Cy1fvYIfNJhWLSbhcVtA+b-Lru zF_ir(u0_)zs>#5`EHNTt2sIkqaKjC&E2}3@zC?Kz`!cN7I<2<%QdbcG@}dRh@M9nS z*xTR!JvZKTu15nyt+fT5Z)J3x(Q zU?Nd^ODjM5qd)%aGym7x+Ddn%+i7((f*4iE0FwPm%CbfTi8T;-?@i75tc)Ql)}o4B zn<=v~*BWDpOvp?jMnnWfA|_KXa{!7ELRD6w+wNSy^A$_0%gakkbydYEt1EMxrl;DS z(K-fD%X~iUFLydE?-ACdtitIt=dauSidNAbtgIqJ9RhhqgjA2yumcPj5s^$4)*+=aoOAB<*)wl@+gr=JK6my^?l@zJRYh5G@ZiDW za4<18_R{g=hYlXxFgbyU!$Ggr>Vzn3%S-?D|NJjsc<{leo_cD0bUX>0h%mP}Kdj@m zyLP?#EpJ|&UwrVvFYn&JKhKJ8d-VIi|K3l3{erh7~CPdxQx7Pw$!LNJPA%PH?WSnk2* zO*7-8V=t}L*NkPi+`MmQ>y~Ob=w@A1l9cL6a^$)x&r?&hqK1SF1Y(k~&FSDmB}}&5 z#tct}CL-8);ny9x&D$aQ)(H(V$6!rT#vs`|A*RO#p(zq^x*gZ4MT)3kY^vaGSPq#O z7)@hpomEwk7y$+v2g6~OWoj0x3JD1@M5(HpnPeyknCH2gib%49rFG1(KR`eP8`h

0NTf#$1Q;%(=5Z%knHkRjI=;RHlZlVh{#qFni%rzu)sdL&D{iW#=3i zMu|*LVsy+%WHAB&H3&@O#?}K3uM2EqV#C7^KX(4?xl6N`7Ut*kmcMZE!UsS2i~IKO znVr43-0M}tdVXOgqK2xvc=7VqZ9ARwih{_PGOW~$dVt8pW|n1H(~4?fD$ZqUlJ?W$ zQsf%UG@4NaB4h&(WCTq}4a^`q=VOQfprQ;G4M|B+i2y_dEs~|dm&_Oh9ad#+f(kYa zb>_1i-C!_?D*ax6YHBLhfe1A~?p&666;M;}90I5G+SK%PcVu)pC^Z70AehU1I!kl! zTh4)r5ic(Ff1qX z;%eGXM2I;J>&O61olg6c_xRr5Tbo1g#q$N&D^xwEf&)os75gYIPY$9+5F{cX z^gP<_8g#^r*&{-Xv4L`9BX)>kD#rl@XGn;NlI94_n($+~*d23-XkefzUj^7S+Xxuu zS#jv`Lq}eC@z4{G4~BzK%RO&-^Rv%CYay(yt&NP1blR;@)`^>-1{g)DQ7hEUF$Pf~ z@|aK(fXIeQ%-<3IQ&@zFkk%-SNrE%`ujXD{G@8qtjCx#zyll)8Xfy(ke!V z)EnCl2OKZw4I#g0ah8XLD9T3!^PW4gF%tRXb1jq;)E3RtN zO9@R=x|KlL2%6SV*x1;x8bs5w zEJegQURqkt^IQ#>d3n$ywb1J!f$tRRc-ZgHp1(M?d8TN$Lsc6$%kLEQf|SBFXy7-R zdXzw+IUONos?4f78uIe;((}(fx3IWaR%N?YtgWto?4uv6LQP<|-*)5MUU%o*+{G=| z-}djHzyIN{KLTndIyN%a>kkvRuwGtER_Gh|?;bBaSN#L~u2a>rKfGc8-a3RD=)zKY z$E)A)d%yp?M)aoF-#tG+w^o*wglKy1;;a?z^OrC0+q3)KZ@K5prSl`*?uCmNzWU$; zgW+Jh)6Fs$s~Q+2TAt`i=RB*J)KFH#wcc{8Ranr!|9}4p zMK52zJhOFX!{nH#F*yS<6Eq?Mi2|T0ngIw#z^dtIoq;Irt(%Jv01Q(+4KOW3(~^>s z^tmo@8Z;xgky#43H4$k`33*UpFaa|FmohXEtqIQ|5Jn?1C8k(M=Q){SMHCS+8iFNi zBA|1QV~jD1im*Xc6*Z^I#ARJKeqmK+Ry2|(Vnl4J z;zWdq)j+9%qiPWI1ZKocW<*@oHAL~8nRmd%j@UU9an2D!S(k(UFo^W4iwbj+}$q8gUcXoDi zVsh)YZG$U4oZL7$If+?&(1|8Bm0G)|CxL4xuf5Q5C8c`j~+QzOYKm9``16TfA1?cPx=r2(ceCC=y^43 zcRPc@aA9@zuGf6`-rajX@~0mjn;7j6dI$C&xaH>C&YnAS%dIyP!seNorRC)heBdV^ zdF0@sg9p=dTN9}%+13*(3NVN|?-v&re(!gF=dJg=wcTo+Id$ssZ+=q^rZ-M~^1l1- zx#ynI?#R(&$4;I&G3fWYo%RC{KJeu)e#vEiQ1(rNMDflSMFy;BE~0T-2Z#`{i5Rog zvESFpg@=@)#)S#i>M3;M2O}PlZnO<8Oaeed|m{iB*cn^*d%R4$}n)= zDVlRm)0y6Ayug_Y~-OwAJz~HpNAN$s_eAK!9x{8Djg%Hbwdb%A*2a#z2w9I1tKL_38a$RCK!OG zqF_itDk#?&gvo8$FyS&+4F}8BYOBb{$Hrq_i$PHF1e#iAQB@^@DVaHl02&ggnLuQ8 z28hU-+I-SJh6&XYwiE!Is3MYqshVTfb#RjsnnH?pvZhoMf+lZmeFF;Y5|u_<&-FT50X6$Fl;txj7c4$6V| zzTGZX)>blCM2#W}nGaQDgerv<35(2`A%ahP1Ovbj*(CSQIY)%GhRk_Nq;>-XMIyW^ z#32)7sD{Jg>P5{XgFw5W@j%w|NQe44t?`rQTVsL;~ke47XJEg{>Bi| zXL(V4^T{Va_s~Pv?A-a9*WP6YGgF&=mW@wte9JxW_~bwQuR%3H%#qQIJKc5&adma= zUGKhU^QM&G!94%~AOJ~3K~$;Z$4?zUaeQWG#xY;JWm+@<WoYib#5cSu-W1BZ;nZJ23I30212) z5u-t}Q$QomTt(S}LR#oJOFQ!Pd0yW+B3fGaQWF6nhk!=ZK(GScy1uj*+Ovd0huEOR5_YtBQ&O88UhA5P^`4u&#`mnE9&HtZ|z$+ts=y!jw{s zs*H_>>b*~r3;?RB_ng8BjkOpNQ`|UxfztmI0g0Ol5YZ6SU}<&fC*SuYzxm4_Opo68 z|J<+KdFLHJ^AkS=>%SCW0H6x1J!y5g)hU+yeb1Sh7^WbDATgx)vRN|g7$G6Ea|RY- zNJ~&LgXTIxH35?-N{M=k=}(LpBPgRw4m?>8!;5NiIRGI5F>59+QdCj|@Z@6|+U+(m z7@~7oD2FR6E8TYYn(0mRYfBbFr_~u&<@t*XA%raRNRT-%s)*>lM+8JBVu{hjf~kfI z5k!I+EG@69NKo;_KFco6&1dambZnfRuj@KWtg9NBsBl%3oD2;m##Yg)>+0omXJa|| zsrUcL>tFwx<>ggX33X7-uD@>Au`{P0KXmA+Z++{AJ^SDA>YGPUMn`zZHP^lH+z|ut zS$5}Z_T~TruxrP4k38}eyG%sQtmXV2x4&xBrcJfPa~EdEC&mU}NiG_uY4Yw~b693QX2mjtEo$DM}>MUEhk-RV2e|q%Zd?!=5s8Qz0y8v; z80Va+F_4<9UsV5F@E%hOAJWw%cJu581xw3|L`}lf2&~%NnudtzeI8>pwRGk)GXjc+ zW^PeL03sw#IRHUSTN^-js$z(#Tiy&Ea14R6^=5WCF)h0D>X?*q)p9&rV|>#jFD6my#mcN)dGkbGl@n= zid3jss#GHbOMK%dEVX{juD2wCm|_ybjGEI6n@@^q3J!r0w(po~b@I$-Wxqm>QN_$urCqeulsLb5X>Rt)!rmR%^vl@m z4?1m&2BJi@uy^fl2MET;$B&$R$%xzSZcquTggiYp_1e4cdj9$6Up#s8yKcWNg!uTO z$6s~(?eG1;ANuq^{GCK`o>jH1DvR1`wSM6H-nu#Cc=zpxFRystEj&+lphMsR0N}ul z2QHt#{Jyu}1po^H9(v@lwO((u)0UL4HL}z|0zl+MYcO?9s09>E>zHR5Flf~E2Y@w9 zBvUg=zae5$NuH}z3#(?#41fvB(m)8*njDd(#V#gxe+Hb|HIlxVKGDSNkpxxL8h=JQ zAJK5V2?f)W&dfyE5JVug1t20~6!Az1lovS|)OC%>4xAxIjbPvafgr@_TWxJ3(5Z5W zMPt&I(v*>YR1HB@5m`ko8aNb{WXV$1MA&BU($DwerbMj zaegr$={WDrfKnt-H04B8^{NY6MFEhAV+_pQ7;7^^1d%8tD1>Ij7DdT%S(aqzh?t#d z5CCloa3Fad*f5%j1Z0nf1_EFrq9VYghA804mBV3_Xi-Zn`^&4ZzVlUk_wF5=m>g8) zpg&NNrTO`##igQEuw#wU0HZ`u2r(dlY4g2M(pm)88k?8Wm{jGfNtrfaUfaQX7EUlEbkbzZc~LFv7pnx3vg z%rf69s6ZBgSHAM5&wc*0Rb6%4#nBgMZ`(Vg05{xtAkQ;gpCdiF7mpsf?)q2!$dA46 z3t#xsov*&*jyqm;@bQD2H&5-|x95j`_y;#mPn|gSQl1yPcI}#-y%=LmVMb2*9RVU# zjmQqto(+kayPYv2MCVQ8pjYNu#=s-p5hlXSOIc90D&$=#uF_!g6x7$ocB7p3iH&a4t+#IGmov&j#@~Y;t&NALBbRiQ&LAk zJv)mAh#`g|%T>)##ngGHrUvGmHMAvzhM|(GMI5l2pro&KO2C6ALUtllr$rKxnnqE^ z#DTjS#4w}vl*W3rF@>1{fIxxK)GG*>I6zTQjr1K@O|nfTPKl)&UQpg$>@sB_A%(LJ1>eqbbD_>ohUoJ+w z7UIOzhVT9U_YOjR-zPuO?u?Fam|R&|K7a1qzCC-UHf}1bvfvhCju3L^0fj01;)9Q0 zd)<^MpFFXs5@)tfGooi$8!UtC{@Z82HhcEvjhosnZ!4>DSXU$MwkHZv1(X{2Z35E@ zH%@Ue1Mhu-I1G})f9sz+Xx42CconcuDW^}!DP*KfMC=HW5G7RwB@3vTbBur{=92D0 zsA`mwT|~*2Yp9TbFrW;e>&1sf-m2;<)kY=-HHaty88HJzTt_aTMIl6sCLrxr8vx3x zOcjhF)`;k{%#kyIs3C1>op*tgK1~ehy$`V#12Ap-B7|_&Nh~JR*y|cB{^Z!`;^Lwq zICgoKdv>dd*J>+h5i-ITvavM%umJ+OVuOpqi3l;v7hbv5xE-Qne&cVfsl|6^StlHMBTN zCL;haO^pzaUG8&Kk-7?m5D?pW8^B1E$g3o{lOr-fWaj`u6bzIBopW^^2`P#U>p_v{ z3P$7!J+c6xciDjh`{(8tK70QIJ9qBz-Y+gLEzVu(T)cB-{)OD?@=>0HM?3~N8(G6qMGt+a63;ore zV-|qL)ylU=N^lx92v|Qp_55>#e)-7P9v~UC}yq>Z0RRT4IhVZ@2IN-2E=|x8C;3x4+|^!+!6=g$qwV{mg~)v;XOP zzxPLe_VnY=rNCZ>Yurg9Bc_iluC`Lg5X2K+g8h}AL ztdPh#HUL#oq7VZSpdll%qgtXugn28k*H*(o+MQ17mu5sYZLDo6b&~Sfgs}cgcI_*MXtWM`>NgG9x-v<*nw zQOdvoH26rQWW%EbD-zY1ITuwVy#&;XEK_n{dg!4SUpzWCGJ4~U`(OY1yN#*aZc(BV zsg941uC1+#XrAS007i&cErXy@Q-_W;*cMbp!-kq;D2eBaiKb&v6y1orX>6k_+FPeK zwTnE)psH6c&klRbpo`y$41xVai1- zFd$$AZ~+w&ViYC@CNwc4Y*6NDwS@xBiii+2`Aej!ON|zjR;myIb$uW7+ zmHQ1FCN3@XKYjmGpZ(lpdA?zCe2U4DbKoch)u`Tkuqs2Z76^4>Y)sWch`v>X7)^Ds zwmQ9ODsw0*CJ~4XIX6-fVY8IYOT#}XDq3o{NzIjtQKNzoc<)^$)r&74x$Wj#ui0`< zyW8F|y6bz3_Z&NNs4 zyz=&I9{={--UBy2f8>RQrN!&7zwXU%esh**R~9bk#2GOmu%~vrsLK$m`ZJ%qe^?C` z7nerICqyNb^~T9@Q=OjK{MeyqmX}wH96xp6zn(sR;-#}^cka2~xjb>K9TJEn;$GsS zr0z5zRDjw7llMiADpAA{3z&jJR3ZQ-LBuFTboCtt3Ir%RMuSye{N& zst^D(%rc*6nS@A0d6soMo#9}JgoQ7nxHPJH@5MxGModDVHOWIrnQLJrHeOuq-F(A= zzxs<0Z)nkTC(r)r|M>HX@sVHs~u&uKIT zU{ys*$qQ3eB`|dW0U>h)XjKRz!8@)hWiWxr?9QIQFni@vufL{M92w~rMX|KHC<|iA zTFaodCWNjrvJoJO2or;IDiOf4EKA+XXh}s-$F7cbRhNXWGd9xcc9vFFM0I&(xeg&C zRE@*o+PQOOHLRF?e^5FX|M|X8MFkNV49ca&#iErjEiO!qj|{6ptTpr5lTSbY_!Hk= zTkQ>oYd`RV?;Q^7XTSaYvoE~(o4@-PMJu~-?)-4j^I3l7${Z87@?uyH{^LLH|I$NW zp4zZ+^YrH9$Bw^z>g64~c762k{(f%p$_;z=oqFliv(LXUGqah5B1!F3qI9S>S$e|;5|$hZgph_C zfHbM7YI7ekiYgf-K9-sRQ}UMyC?F$Zp67!BN32KM?Xs*wC=rQ_5``?Su>lbh?-c<6 zoTDtuswxm^Y&iOsW(G4(;fpjwrDQD!)K>O} zyRV;o+b{m-5W#N@J7KtNfq zn?+5sA`k$grUr3L2_RluUE8o_=gvL*%HCku@2{*aFRv``+;+{(^z@*UpFX`-tE8$A zKq53C6bbB_&Ap3u_7R3?9!-}OpThV;GjXN zaEdh{HO;Hg?1;75{iIno5z(7()_U-wS*x2VSo8>Kot|VpYVsS3geHbWnuM;T;29{Q zNJK=5Rr)-FqEZlzWP|{%+!MpdNY^=1qX?=9V!%oOR*bZytkqPLy@t?492aF-tLM47 z+0~`X5*HCy%6=pQfG|FiEnGSA#RpDrm}qaFn%KT|b6pLu-LZA|o_)Xa^Y@aU{cbv*O(>`JdcF+Nt7WgY6})s>AKH%c8ON+ps^ z#f)SIzzAw;%8434iSA%m6{BVsh=>5F_S92PZNFwafX>ff0Vc%MB#tW5TU|C$=Upvv zWqGkKOGIk5TA_~2oQPh8;E>UI$9(?MMFCk_Tq*|@I;t3kzpXPj(7=&22ZIIez5nLyugyZDz;J^s%FdAA9JlO<72Y zlsQrB4~JJS&Hm+I{mGtv*PT9d>G0uWMPA%^;JS&i7OG8-b{6~k7k~5d)s^M{@%z7O z2G6~4>Vv=VE5+unHL#SFY8IE4$LpRIO57zxPpn{3qN?~-(anoqZ*5rBd66*^u?s4; zzFtn?2SXzyBuuoC)M-J?!K~@803;#=Oavh`08v0rZ%HDGNfgoYrd<)Dl)5)m^4qNy}LRI2IpW5&9cAi?__%-C^J z6pT1AF?sIX`F3l>lS@<;10YANkkG!Wn(Q(@%N%nZf{4Trd;OlO7I`5m=?HGMTK!=^ zguu?RVR`|syZ969!U$x83qt z)*Z|1LFw6p8Zfkc0nVwZ8c0ljBNEX7>FJDM24tq>d-e2o;`p5mABpU%2(b70Lb>+zxi8x_wIfF z2R^vAwu;DCF3t>CYT|>`?&tfqUB-;zt^cxr{|%q`=l}1)2OgN5-T*1aku>!Lj0FT{O$tPeX=iAvlt2tB%&d+5U6_c8 zkj_(I?V6UfQm~eCV>U-TwN~P*>4X8?h8~LUxTiX&19P$ z9Q{6g@G6lMXhSD_Zq5t3N7oy6a9MkH#ax0XB%{g-`*dFeQ{qb<9mk`u3RK<^DuMdI z>}!4){r--(wYh#z6XXhT8msCH4&k-Spva+Ir1H{VHi(&WQ<6c^GWZKYMCIO$@9irXT=WB-ur2izIF_}pf$f6R5Yi+nQWYy znVEV#?vA3Od|B(fE++EM^>Fmw>N>>7fS50*V-qfjEW$4^bV#JMRn8np)WT7v&ooe5H6vq!Qhzu=q*7<$f}H#7W#rO zBqT^$!NDlVK5k?a)788l6}{@mhDp#1%QQ{5vEA! zDgNR)qMqfweER9rr;F<6O#gcl!qjXkP!t1O5&AzgLWu3PGe~59f1bf`yS$XSTA88M z;`y{YU)KGQoiOFRCRl+m>(=VG6(;PXDv;%9MXn~<@y9JX?cSB*-0F;MS8 ztgM~GW0I*DvDoL~=wa#T7=bI___Ec}hm?0-0A*M;$A+0^@Ok=0FCh`yi!5g0D*F z?96(xcUi1{XC7WzRWOtIMR372%bP6BHdQ+9+0L+MpU%4-8)d<;H|I? zcwQDd5M_IJbxO-F+O)zvc~GvE>*%|jZTBW2KB4m%9gaF}mdpz}yYcOO$fadxdpg~C zdML|wmGU|H=6PR>^c#Bnv@~=UgzS>^F?re*&G+A{X_flhzvDf(mH3jP05;4ixjLS! zUV@m-Y@NdgIHr%HU_I&+_~bc#sz((*huZ_KorkWIYs*KQf0CFtf|g9trvz#A+d4j1 zavha-o#?sJ;!4fHa5vU{dmNXN;@i0u|Mf(_kS3ezS6k4Sez%XkySH}Jd4(m-OlB*)}!A=#rc$h z#<5}Rjm)m&zQ>Ox!j2-$lq6*>Ag~}wxGkHSE^P${t`G%wQw6DI1y!u+vyry|Jp!Uo z>_}njSVk`GMx`O*9&%8YD1XT_n7TVXX^J3CiLL#Jri(l_zOWql^!8M|L$hOz%jl${ zS~bIlYd@C^TfygL%9~6(c$nXTaDT7GVN14X*VW{bOD;9CNeIgNF+PbN-6H_KsZ_Tv zS@3`}5RNrBe;1H^JEn$0?A1MtPEDGcv3$mbSbw+o_CbCpD!}@9xHa@$=kug~_ifE* zhLExrLbzRvS%=m2ye?xle$`e%3b$uOCJNS8_Xlbz%Y;50oqo7ok+A@q|Nz#}XoC3jS}%ic7cmsMK>~ z_WcS4Y-QXNmk2J=E(L&;-;xha@s!c-Ft`e#Kk#$pS)~GNP~v}A^PC53|Ln`t4!j8g zkSpAsVrIW2tt~LS8`^3fV(DzXJ$l~>w>8v^RZ3E;NV@-pI-tyWX;m$A6P?tMlr-kq zh^F@cAi>252a}fI5*NjVXebHXOk~qP_s`Jxh74d&0kQf2M(yIK=nVsaohW(M%v-R2 zA=8xc|78I*zCcy;wROqn!RPT{%~DNfNg*qR2Oy{jMhfycchZ^1&b1O*;3$cTk_Sn$ zMeuNsB2;;e z%xP@D0c{on#8EKhH55_Wnu{pf`Y5J8R#37h977Bs@k8E4^xC%uT)xPj17tO^aj*_j z>drbJW`rC*WzsR|g=wu{k4R0e-$fu#eT-D-im&i4&qrhIFAUdDHSb$x@2$p!1e7sZ z6fi{~jAjQA@u}%Z-rn&}l*+JrsC6jYQM4ufPu5(qH3TNBd&&=8wo0W7Z}tY`}c={K$D&FK}0B=Lj7;>h7thF?bfrY40g_vyv4 zf9o?Dz7+Jx6eaQPfn2N9@bG<=0uy;J&|dH?#@%Ez-rNkJXH(Dtx{jIryij@HxAWMP zFJJr)J{4%Y)GVo$FCB1Ai#&^u@A|kqEPMYTEAe^#PWEB=v-wlIdl`n;{ckViCL=`hetTvK9fiOP-o_fzq+4lpyPneu zadHU$+q@BkMmvdqPuuX&U;q$BvqgXIblU4{9#GV3Uf)F z2K3eU<-Q?P$dKQ57@IS82{}^VpU_*bJLKa=h{xaUPiZ%w@X$L7zz07Yo1YB+Xm@M- z-_OV(bX3xp=rIJbE^Jg+B{7#fVHAL@lguqCo=jda__|74FHkllw)sqh4px}FdO?&X zM=FTV)FxVqV9_Rb_>zPG>WTrm2!Mn?F9rvLzPPime5El?UO1-9eRR57cbX7KCN#fj zyG|JTQ~%lKaK#QyYPtD7HOC-xJ}uqtHMg>Ux9+>~PpI45|HJg@r6BT_n;Un#a{vgh zq=~1SGiW`|B%oD*SBf1#cy8!un0peQUA=3Gneg>N=#>!?kdYG#(sDJDWrgNj zej@iZt@rL+A^wo*mk4ZRC`=)j(m7IeC_Z2k@*F<-2~moqBMXo52P;B!1hBr2-*|nd zB%xHFGmeSouA!zq5eATEtAL1-3qA-+W(&YcEk<2w0bDWQ%ArC3<8t2|F@FmKJ~FT% zMw}xB1~lzIBrCC$BtR%mZU%!IGZE;IV?~Aw$r$7>u~pv<(n*(BipGX|vWUd6;HO%x zIZ#A%RddBRGGeNvgR}@-@EvXQqQ|ub=0!gEUD_OM{9DY(=u1*z0fUvDaLpn$d+^BO zbcvmmMMd7|3?$=c;J%N?{GH66T;TY@{ik`~DS{3o-A^;aw8`n}= zN-ibPXw3LHX$_Rg<%F6D#~Sh;k!}NL3m4-gVQUFTfOMNUIMh>9o)gbS93_!a2@1Fa z$#OD!IR>9$(!yD~pEc_oN4t@esurs53EcgwQ43_LHt5%dlGxB|Jvdylu z_(Cpe1)_@5Qf6+wohEkg=_PH`U*B(2cCR|MKA{)_f5Q*1f>8m!IWi5p2g=?SAZ!-Q z7q&%FKpiR=Pj3-Ncte;KrOtd2C)o#>LK`!)Few^m=U}@zJZ%{}QppaWmIN(g55M=E zO!IzM^r}nYcF;L}Lx+fj&hi%iE=`#qqA1{v3u7Z~tfnYchB7J232u)I1yrgEU_n4% zEI;i#I}_XzJhRR6IJE_j_p2fhumZMMft*q56$wD-I6Ow2h0rGCaQve%%u!Fz z7^SJ-BXD5Pq$(^oRH4&LkR;(@J3SIaKT4@Z52`X<&-<<6y3)>zD=E@wPn>c4!DB)~ z&eV{)W!aGW2-V_z=;i;}Jn+B$)j(mBR~JjwhOMjS>n%Ym=J$K~Pk$O10?+avD_5L^ z?zVu7wZH1WH4$n)URZ^^v|4R_+8voIH$FA1TaxhJzfcPBG4=mzgGcMoz#B>3d#-|Ase=hc7XdRq4nKi~-uOHXzayStAE zc~APt^`IT&jsG5K^JN85Vb@PaWJ}~P!N&}1r+(g&{qV~sE>Bf$+Oi34(V^_l)s3mSV*h}uDc*A0eAqiqdI zr1o=saX}XR!Pnl}p*_*KyKFybw2gDO^X`zm$Zurxov2-UmUl$89?yVTx+MmlC-2Hh zmHDkc*(#12>62P5V^e1ed`wOy!j0gr?fjjF_D=s9F4UoRf?9<15s6COod_+|huA+o zB5I)v4f;Tr|1>Mp7FP8XVTTN2U~3CYvX^qg)|PT)Nx~dyRJo`%DefvqWbupUmE3TL z((Y_+a)fy>d~70s z>GDeH9#x^9kkRRO~c0!+*-45lisP{-KeL6ze6EHhsjfPbCXQ3Tir#sPxwgj!go zmZwmPm(s@8u$!Bz20Wg76D@#@;6d zAeDNHqo9O z_mg9+wX8VW#3!nJ)?oS{fRWLZB7&ckKay%*xcNnrw#KplZWlY)BlXQg6qThH0B}S% z0Bp0zfLUc`|7!KSAFnbGsLWpW7;~9Qum2SD&L~!?!+PFLEO<{j)r#Yprm9MW~?6dAd=_kzUp#u5xEQ{$I4>Cbn$C;n5t@_);6_P%9 z>-WjY;TOJNo)g@44!#l%wcr0vxV@6Rovph+s_Xvq0&N5Q={q5^RLk=MJ!C%}Y|kp3 z#q?U-^fBBFn?KwPg&?nkcgnJZgCYAJeCwXOrD%I5efw>ietxcLmT^wN;c#^KV|I6* zQHQNf+f$x?x2>Q1VatkZuBljS@LCjK;NPn2HP0!n&YeNDtS2hu-}pv~nuEGpTcVdG zizOC}l#CWnJdT2~3l1Wb9hz-V;##MDYY%8>rv* zi_RxelD`9eZ_%y@zWwz&Lm_eLF18r;T2s%>%`G_Tm25ZiT)*?Ee}oL(hwyS<>b_~e zdlhVbU29ryHz{>LTs*}fG3)3%D-cO*Z;k1~DEQ@>L~?~g7N$eOfHiJZOw_nDn}gAA zE^3@qWUmzrA{l_n1=36b4AgOyp*W0he^UYQbw6t-iPN`7bJ%&TB90^uXKA+ZFvCgY z$QznsSye@7j0a51-VoLh8-u|MU?OUPa3iiUu~72$(notV0vn;zHH+-4==^t71$FuG z;qku4nD}gC!2p!?U)<#4Laj*XWcWI58|nEy%!1ID1}PUXk|2y%rvpq$COSl8o+~DpovJ+CJ*K zSQsRZgu6Lh!V|vgyBc97vXR2>*zwQe=QIZ7h^XsB_nAGPshm)8KuX~+;aWwc9~o^& z=3)4Y6#-c)ShW0&q}Vf+e;W=(oT53W1Q5x^JUjg}=Q)v()K_pI81&T>keX>!JX7$y zCASa3L*jmVE3!j2SM*$6TyEyfmC$_)UDpWtTk4nJ(aVvOZ7LSH3$9U!j9<$d5t+P^ z!+!lR%|U7<;a#>zoD2h&hUbX<47Fv0UkyA%cXZM$CMaDRe}4e0HGZ6K;+$uh0C^eO zMlFvYgpQPom0)Dn7^x+af=fPRhtd?hS@=*aoaX%Kl17!uc`Y**1jATJBmum8XE-=G z*m+IN$z7le&&;{qr+?vMBx{P31dL~pZL@Vm*zeJ(nUkZqxv!=F{3(m0mA$PD@t#yt z3diPGh>MxvcnL{Oq^UOffe2+)ERSRMpo5rSaZYnpcxnG%mMhDL|6Ypv^^8d{Q*Sc0}= zN0^cnYlLss)q6v~g4m1ZNwE5`^YE}#5iL~E)I|CK?9sqi$BCGhpdTlRDM|+FNm2>T zgYcgzb$!F)3GvF%=vYJUrHXMA^0pYlC@iG307fs^t%&+MBM^+>4FygL&}3io zbg@_Q^W)b3)cDlIYrfYmzXI38BDg=BuZCMOL8KwT@o1ChSO&4|kd9mur2MhoM z(;|Ba1eiK=V!*J-lSB*vJjZGfI}58XwW-+4TLGX85h`QB@3jYnzN+8*niYXbE<*{# zQPG7$nLi!|f5Pv_j&FX0sTMGTsJ4vNQ7~Ncd*4q5c3iT4!>c^fm=3nsA86B~bj^Q6 zGCc6@9Jt_Qu6Esp$)Y>Xl)qS#`NKUm0giFQfEdK@AhWkb3-&vZNA~U~b3l6UsN(0l zkc*kAoLuQr1QhBJ+w=HVMl;_==wLscGNbO>$$5Fc|Ly2lt<=ZOo(3}Z@+D0M$>6}H z+T6AEpJ%2Wh^>0W?WyZq=*IaX?aTeihg0^aC9TzeDUz*jl7H?|=)h}EcK*iKz5CAJ zJavS|rz159w3}*zwd76HZ}@%T%Y(&9GgA-c+MwrP!RouMtF{@h}JXfxQ~NNCR!aD2l>gM zUMKj3J(=Ia65s-!`>3CpeXtxM01}pTEMemFmv!m;?Q&i4O?qqhsmlx5i|Lc`L(tUR z`t-rC`f4b^GUsGZ&+61I7)6V`Yc^l;oT~&Ky9k-7B8CN{ zaAZG&wh-u`okJj! zc||5BOKT$>TbIPW_gS(ZSGAr_zCYZhSq$A6YvoJ${rjB+np$*Qo#u>5J!4jl&%Ka5 zi2VEx$pBXOzgd{pz4cIa6W10&a)8Q;X)wg(4h(o0X$nXsd2-ZpEirX8Xi*nVHD^26 z0QCj@=>M9{)6S3r^atwX0757veA%E*nub^>32wUF%_6IRs}3QFe#e@d9X3wL^uSJ4 z=nz#p#$3snNn>ER;4QZ>UO*34H!v(pG<=RjNJL;I{I)GD28?aB3HEhxR*3>o;VAT% zWTsP1`)$5dNwi1n)x)He&ii!MsyLl&tl0>rlx%Ie7>Uk$$(6wP+OzRMs!Z zRifw`_G{kH)MAQy>Qk?c$)VAOESLu>B}OK{?|8Cv^EuHam<&^a09SVhn|TK`7NPpn zilMg;PIbub?tO6r8uhKG^_q7vyY+0>TC&~RDlpu7s0|X>mf|?VPd^TBnmJvI4?}4 zA2yq-l9a<3iMZGV5JhXGWybbE!Xw8!QXN%CLi8wf02Ww^bdXZt;J&g;rLh-LeX&B= z4~u57^}eJNoS0ets2DWK15RGm_)B*3?$}{-^i;-9h{-X}_cS zN@>b7@p|N8@mup{|Mm3uZt6HRIowPb(Umd6N3=crZB{spYR<9RU*tMg4qrrFew;sS zvGESfq{^K1)5F&lA|Wv3wWhNK)->`sskT_K74428(t#v!64SgJp3fCb)%aNzC0Ql% zmMfy3=Mt>-JrtofhJw0wrx0lRUWIie&sa~^Z$m=Ns^L%b{OakX9{uB7q>A`V6^86c zCXj$VFJtB7PL5S{rQO@IQ81$;HtuGw71Aj84eT|~r2az1urV%{KyFqRi-M8`vM44z zE()zX^O2xOhrJA(eU0(uc7e1$;f6(H!oQ^CVwff;ayu*z;`#1T<&xNhe`@n@E|PY5t(6Ms3=NlFPvI8-E8Mv2+bN&)YR^%nI0W=6mmT`yehG&;?$c#EXumt= zQvN(VUD2kY1W-{o^rI?bPv&TTM_yUA`P}^7pV!=DG@+!fYOI0EOd?bWiBV8{x6*>7lXYA9v1K<{=G(NqR&5`>FgYy%ZLl3z zPv$0yqXYRNEve~Z0qHL%>GCqOCWY7qwA1z2nEF+%lntw`VjI#N*vITBU%m?Z_bA$Z zIP|zrmjC+&ZpdHJkf2`!0qakX8-LcJeUG`m>+23^DOhW;lLvwqvvtFLXsJ7x_Df~I zU7jD8)saukSlzetI5+>kWs!kGMbD5M{e0m8%_?J}w|#qiR8>}Q6V8^Ko!s63pfflx z4O=|#a57HXnrgQOY0VEF-pby!O@%z>fB!Q{yYY9Cwl>HXIg>4W{i|qA73Bl++LsHZ zuf*raq-rO>#}>wN*;TE;?6GuA2R4*A_M?Tz=vqws8anV|n!fkTVj2&C6vD=y5z%wH zMs7T9Jl+k}weM$n&mC*!$|yyVLP#v>5!$c$piTi+21}G~8&{Vh9e#d*jrNDhMT3LF zp}e1s2gw6lo2E#=CF`xTj=O+kQD;U0mbui|0G1LeESTWT{5-g0Ei2!gh7i{;$q@5f zF;fEN}GU%#My$@59-N z8*szlx2~9*J@eMCclE7K`#T{TvfqBZ9(c-K_bNW>U~)q0Pfu4vEt>VvXzSroy1{_- zi8f#XkxFPTuqo(5XELX;o&k97@==U%i|PiVa8;V zJhzW+*b9usfK%RG>VJP2UVCxcVLgR&ELw}^i1|IX9S{ld30^4M7V>25PYHgabqiea zcJqH&X9%o|cfXr7%`ge>{WY+~5Ol&&C1=$okYW$~QiOiuU*5Rpe7~*@(0`dRP_S~` z(!TRBquVMZgYdQy6OJSPGHKvOKI$c?{YGcOBEGGVMV!50{57Hytm)?2NM)6zM{flq z5yHjs(4Y}fh6yZse~N-nF)xOu{yS*KX8V|$Jtn(BTPZs#5w?P~85C zD9TWWhxhg4&D*CxF<)AwF8cIyb4@2>TBg<}Cuom!+Ri$ONN)D0g10uqg7P1~Y}8>t zUT(NP>^|K~?G=7B%aZ%X_Ed;LW#M6~Yx#zT^%V%1Me2{W0J>(ApGbCmPT)C7Ckf`_ z&BS0P=m)04Gl7XjMC8KCBqX+^z4MaHtY9*MMxVO5y|e8fqzB{gq;T*~$7jG3kSiB94460dg$8mI!T?_INm=>lBFh-^(P{Y^}d&)@SR_+S6_w%qW`jJN83=^cBI z6}gm=(Qy`u!p|or8>7#&75SMy7E}}|y=VNmjYpyot09X+SIidQZc$1iPZUlQ+BVL< z>~6my)BLB_x=8>3P*1nJW3}Hd?tFu30lM>SHc`Di0{+1IrDLxS zQz2RghPqL%`6TM-tio^-Mgbay*(6S2k&3g?Oy~$wt%pq+#&z_Jy-baJY);RquH)>M znU6mBWQ2XG)^x?i+tRe`(mfTX^5sFEn@_^8YQYgoI?I&ax`G;}hwRXrqczIIdC&Pe|7?F5oB7>l zmuG5XCO>4}aam>Dnlof!H^denr*Gk%#r{Je6fv;%u>0v#ckpeY?$9v-qI_Zeh$fIc!A&vqd_wbsMIrkK!US(d}XZH1~stMo{+bCzS z#qTy9Dd7(m2YR(6JZzkV3PsVhVwhF}&^Qan0%sP2V2p|aA{0*-I&1kYJqt!CpJ)kD z1V#dx1KbKonXTbvfKTuuAb%B;4nRb4NOPcQQAJyFALzs(OF;Lgg?LBft2eu_mLo5t0eH;%{gxAuqC%Ffbb|PVB+dI z6wHsZ~eo z%BB2ACX<(!&-`K3>Gk)M80NPLGB>*~4sN;O+xu~}G0_c_R}8|T1rn`I-)xRwzBkOv zSDVvOc%LS`BZ7_d&H~ep1F@eIQ&0ix=V9x|EG#V7RS@S=tTs;9(yBSFfpcNhwjCu? zYGpJmMjyUkaX6y}VD?Nte=Q~{G^cMba6jMScK^7Bri}QEUrK-g(WdxB#v`Q9rFpAn z$(o-DeO!m50sZ4&rSgXf3wVwzlGBL?A)gBni+|E|G;~5aiQbShs5?`%5dl;ZkE#V6 zP4&^b^G=JSV$#|xVkTC#&~aT~g7H{-$w{RW9&Tm10|*XL=&&v-eTIj$ux8Onu9qB< z`Qu%?L;?oCumD?30RepZs6`n{&B935f6*OXiGe<_@qlzN`Tf1tC3WbD@3?-f%WD*C zH>0FXcXB+}?--!$bdp#$niE4b}jm+KG}bBzZ%P}U^#8=h>!=- z5WCaSPP`BcRlI8+FeHZp!og(%Z3*vxpG zm`+R4uKc@Kdu~H5fd;H-(M>H&dl`H-ng;aLxY}UQGm~!pyFCn=l5Rx)vcqUt7`@{j z^9_26-?AsySklylc>i~Mh}PKL{*9#;d0ejRM4CQr#d)d~zn5e$>k7!148EObPLP49 z(H;BvuQjBleV;-N4ET}I5-N*!U9%zoodul92nli9c4_*GQAu5F_Dyzp9@wJaQ=&35 zJ{P5Zc2g7ax7<->m}7fA;%}0?A~1yxx)c#rI^uK`pL`A1O;`!D&ghv!Ng4TLsI!F2 z>B8F)3itrDG+P9Z86a59?ET--cy#k|+2i9}z7Y-Kp#PeOu&xeCrQ?y;7t|Zqap~6O zn#xKMm4AE2uD{wn?~o5?$j8GWS@$^&(VC5VCOc%(_ooL*$u-yZZGa`|bKy8zs36DK zSI52VsTH~iv^l(<|7|KpiI7GNNo}}~K8XTi@MIR5G{VV2rM)xuiOR|_J>%pTN=O#v zNv208Fnoayw%wWf4gxJrg#@w|y&q&Bhs@WmH~XFr@}F3*1|x>;#XR6so#tkS)cKh( zCLUfsNco<4xc;UU; zdD!{*@z0g-_pZ4^aCG(?m)qr<)|PYhpegS8YCauSGqbZ$HkA!`VYe**)<}PyhZ)- zGwxB;B&&9}$mz2$G&!C>?*(}x3y$Cm+F*aOox>aV>60cPL0T#V1A`i(E2A<{0FUl< zBw8j+B8w9i;RX_g%_Uf%?i8kN_xFpz*wfbbYD$;NTPFZWujP?M6%&Y>I#gJLMfrf7 z5Wi$bJE@2Uh)MgA!djR{&@R&GJySSmr~sS`TR=#joL@nkMAg9!ONb1hPp*vLzyE6* zMomaB=|j!`-U81&=Vs{1^Y|0x>5-4bwbXx`XbR(L-0`T=02^yTSo;$PF1|X=0KQxt%*5k80v02$ zScS(V^rfu0-T$)6tjlfVJJGRd=iY6r^Lo3D?LL~-;fWd@)pfHZ4CDONGmhXW2AVw} zoKUU@XLk(W&a<41PuE4VTTCuT^@GnEpT6-2oaG`PD=%q9?^iOu-}enMV1mswpNTm<;N9B2PgjnVZhK*;<}0 z>pQl+x_bY^qyIHe6|eC2NS{h z5#en)R?`T=393vJSc7R3il=Inv{UP^m_k#(vz!Wd9?(iJOjELk99xAjIg(tkk!tR2 zgYlQ021z(rPFPRGJG$@!$tX`oCLoPQS)nZ)+!2qeA*^GaS<&xe8`fMoKTvRCku`Ke zy(Dtm+Whz<`hA7Djcz=|8S}U4jTRQT;yF+Eb=1fE)yW#?XQRV7Dae2`+Dg1*tM%RA zoR(VFD4h*W4A9=DuDrwZFFxJdHu_5+w5_{FPudP%@Vvejbv3ze@$LNIrRl>rDKA4; zd-YYh*z6tK6u2shtOx;97MGAiBsL&+RAu50w z4Az%PN}C+wQQ(v|{S?ZiLw@2)wgL+#q9a3bBVP$2Lu&@~+|$Fq(JJ@t!wge#(GZ{0 zWg@kQdj4*Hn)gaciY!>@9=Wm)GWc3c1~qOr)cLI`aE!OL6U`pa&du)nm;Agn$MDP)4{=&wD0ADevNteSr{IJtG7fUvFuH4w(GYoUPBCqr~VC@f16mMYhH8c zJ<-kZ7Bf09)S4G?CeF6p;yrezf9k&(hR30l%6~b;X(KkRU1OLckD}BDiooG;0)WyC z+9Rp`Sz_X{*lUHJ1udeGd8LpkE=guJeqLRR1tN+n{z{{v8S5?iADSD&Aobs$;hCK; zC{%06ow0uB3F6QvZ{U2}#n_S_`Sh53ca6-aVo=m}VYG6ni&w_AAg+w}PIf<&{m(*} z>Z(0=SD4XgAcc{NgH3=5pX$SCMu`;VCYJ^!sS^PH)~4AH^%C%JHsgEKarm0-<(aSS z-+8i#nLpAXK`*camskabb+^(c0MP|;vyoKt3p#|9)Ab! zUYyj89>ux+*BA0_YltEEU$5lZzgMJ^ngR(WtKsd$xvs6lsJ*?kwGLmm)%q>u;~DZ5 znpZLBv=pxuFM!%fc>1_@aeGO-D2Y63AI}*xc@Bg?tolQiniY5({t$*SCP8QYFgSNs zt81A`UP1+>%4Pe=Ev=nW1tVDyg8*zAvMvDQmOX?Bg293aBTb3?9h5HB3`^(njV0I4 zA(6AHQIE@?w`Enk=Y98}UWPk*{FNtHnvRiQ$8osANDmVWWFa@OkFJXh9wHPS%3=VU zup-Q&a0f8>;&Aetsw<8h>okjR3JVQ?nC<%^7;s_QFC}W&1|K(iE^X3Chi2fNpa=&e z4b!vGaCT9&c{U=9D^h!*xsaJfKMPDi{gF^aB8F%cFNq4{r$Ex85yn@>c^iVwqM`=m zF1^5*v0wRId@~UBs92sCcx!K{EJvIFo1(4!qEwlufV(d=K4|~oHsb1jyTASN_&qK< zo%i4QZ#q(|)MXabOJRRiM}LTuwRU7ho<`3!I$MQ{iNy@Fz#iXBBq0Rzik}_vJ~`WvhlpFT++YZ|c0RGGH` z(_JS8LYleMShO)f)(Y>I{B-0lRx_OlN!?YHK&0hAt5BK~!zo#qI#mmm^)UjNa`-xU z53zzI7$9gIeq~7pNBbr}hS4mo5hS|uW_O&lSdSxuC&}JM|`OnP} zvl2i3tQdgC(*8QCeDS`|H}RDbHp}^Ql$u-H<0XUt##H&vy5^Rq*upTpueK#bEp ziNoQyf+@2k(ioQ{2(9Ox<|PhGZL~Ci8YGPBm@aJ#p7(=^sUh=(iqw;7o>n_MYm@Uo zMm@?!WM<%*(xQ#RnZABiD~IXDv!IG)en?GcvytZjhr;-4CskhcS3OcmF@p$@t@iL& zp2ZmJjfb;bzHaBKEBb@$!J(&%?gvA|&jSMkE-Ni#76s4xwl*pBO{KeB9p?r$x-Z6_ zX8gXLX~?=i1-&4S8td?JdFl!AN0vWcyV%)IRuiTh*W8=R`dOKg`)&k;;7$7l4?y`g zI*>PAT1a}{YjnWv?#j2*)7Ix|c8t%(yCdYPA;HIZE#bcRZHsHR|JEn8@g(P5Mic;e z=O<>ZP@wD;+oR$@Ww=|@x!`wHSx!l*zo>EHbGn{l_lfgly%|;8ah67<@%Qf#gMLHN z@XBerXFMD|KWOHQb_sX?x1N3p|J?W4OzdJ??ex8`zsGiO2Qp9G$Fh1Dd2{AVEd9`L z(H63Q0{`0}u+$U6vfy0=#Cii8umQ z#sI<#nN_OzgmBo{9bub6i^vz~hW>X{4N^+#@=tkfS2{-B_wzm3zgMlfGSVp8?!VvB zt}Azbx_I0^^qL>Nr{AHKy$@jU>pM0(4r)QdyJYVgpZ@kSJU%Razw(y7vT|GZwcn6* z4LrF19`c!_V24ZD`m4om;cu@f6gn4BJlLk^$sV73ySDMTX>h$i6#TDmu3QsM&NOu& zDaB+Y)xeR1)BOGDOtmPdBHw?v+F_!OJ-bgiueHu_+zV2FL;WB5{Nr0_#D;_F07T2AV!{lngxZBuk z5aiJh)4@@NGTYh!Y$41dN-RjrSn98(xlFcjlv1luH8*3+aFJLnRMLsU@XODRbX4f~ z70>TEnO^UVlh%>;&IPK^@blr9ZNKMDqjs6EX@Rz(+rSg zCKV{TR$HO8RNf(Skq$dN1dW6)O0?SuCMRP-%*I=Bw>CRf>0q z*Q@i#ak(<0E2IKSik|qS-fgmp5;2SA@wwGwGcBmr*Sx&qEH!VZr0>+rf15NN{D2GD z`LAhqZ#;d`x*w=}y1kQF%M1OQ6^+Sc)JHA9%{Ka~h=j2S=ebd7G#3+1G6{gHA_@Uw z%V;io58vXuUkzxDr2y1lTpcrn+ z3lLFOHBvExHxT*$g+o_IF-Zj_W-MXM2o=>?YgIxXtgl{^@4l&mu*iUdCTlG6mP%M3 z`rw#~5xes03RqLGJW%W091#))21}uvbP>^bm_kg|9Oh+Mq7IwGU_TOja+QbEUlBWrK`dhARCZFxP|u$i_ZED3i%Ht{!SHZZ{GhXc zIR00Me284+PD)BcJj`U*koWQFiw*EyI=ReH4=$rWOH3sD81dmBy+ap9G;{8YW$$-RjeW)^rpRlg;tP1* zR;q_PzUIB+fC~eF!ZBgiN*_Rd9;u#e@k#f--$OQRGR&AjtsCCgeX@Z^t3Q4$P8{Dp zJStI|d#!n+Sv~>VmF3;O2f2(_U%Ab%x;l{JqN2v>6t|O0ZXvtB8_3AIUN?-Q{a%DHI8p{=^R$>TAdSN3tSH3z)||2y=m3vHmAPwnjy z-eOIfCN!!kS~|ous1t4RMb154?eUp59T%bhdH)k5J@w~@Snfn!9+xczqvOo$-%;UC zXjr@S^~P}y^Eu*Z7+PrQI5{8xE1-P#o34g*HXKvPA=ctIEQOEJyH9tm7c7p7>fZ&E zyQhUz|Hu?0C$x1`jYp%cg5220KNac3zSCEaEK?^DHa>lw9cKSAUTYqT+k6xZvY*qo6!cDf&!72~ZzLYR zKHY<_LdqKVIoTZx8zVBB5UT5$;8*5qMYEctPr8N+KY##u&OeNKqjd9;Nff8#=;kWWa40-Wfd+?hD!fHu6j* ziy(U+OBLuA9wbt|O=G}p&St4ZpCWaaM5sS#Q;cI1kyg+!5-q;#%?#~Hgb-@S_{a;$ zJkEb-PU%8GJkCBv@a2jLG=Auli1vo+%ZxGH^pchT|7(xz>S?oPz7+Zwt+;xFOAZNY zWzs7l8`|&2$$P0WN?9#qOv<%^U!H;3?{OWo0?VBAJT2a#BAyZoi~V>~8dDRC!5A2F z8IsB^x)946kurQU#4&4C+Z#;^Tyhc1bTE>QR0t|xhCdp47}5tA9)`?S$OER^yi)3| zk>OwrfQY@O9(LL9PFZiC{U_EV>An-Rhw%}5C3CR)2FGO@Ka|7Sg5+HisM6Lbd4cuq z*Bv(YhT?ALf%sFF7RwcF7^yw&qdp1 zPUE%F@zaO=4}S=-^F9lG^F+!xbsqLX`b}1WitgSJMs4XHO%Sa*lZ}Lkl6>x+JeT)I=nCg#> zjTyJPo_gD{7jOM1e6h~#-RZk#wv3ScH>1jl z`|kRr>+II){{fysVZI``zxjvTkDoZnxfhU0S!z({__^nv{mvt6x7>0|RGpcbL8S3y z#O(I&-LDEe=CUcNRajYE zDktR+z5o5Uef(p;ciYGR{V)B8$z;sT&^Vt!Opu7u&&EVFbi2LW^RT~OSJhkJ{)Rml z?HY}SQR02yzVH0G^S$2G(W6JRB74W%-#Rlr)tjE$vU#&A{ImDI>oqrA|D`W}VSfJ1 z+}t+D?!du=r%#``{d2cx-VqZa#JUDThmf#DZJz-cs0FEQBb940wG*pL06YR!Re+)> zMAHp10#jlSfuRu)y7YDrv5ql%cFwVxP-=Zn>jOxU4l~0TB6?)v?$lJR(wXjFe#Mo` ztLuZoAZqB3;#a@=)k!%Xj|Q;@BpM8ct7|KS&}p}~&TYN&nk(Dw*5cwqRhN7A>>;F_ z9ia^deebh6#u#J1BU@jK`!C-2)YI$iGZAUG+TCvZndgq|-Lre=&h14jFYEI3=`%4# zMBKi6M+iZ+g(v`~2+rqGLfYD>nZ(HKI6cX6<0!i#SKVIa=C$7DxM1vfxr=) zibw=e0zzUn#KO|K zshJs#Afmwx$xzNwOAhuo=LR2vJQ%!80;ykPu?4?J`%CRb?WR$)s0@x~@;0JTVyd5AHv3=)lEy z-F??X4?Y-Too%%Bn%bnA0Kywz|N6|e%CbM(?QQB#EzO_#(wDxlyu36!J#D^lL{r_~ z#d|J3_Pt}o+-r5opq`9IgFbiK#9fUsO`n`>7J`OIfR24tRp z%gOZ2R8;)ZSMDD5R~MHqM6ry$5j#iKWIP#H%j^AiC*QJV^JhQ*`FroXXS6;#bm+iT zZyEqaV>$uN8s$9cb_v<&j5SG@24tXUYK>d7F^;LFbtI6XApv7kQ2dG?D^1`)wlR@H zGPQ^iq(pI9l?>GQc>qKt{nL_tD}fmd1&9e6ml`$>8!$xRvFP`4* z%$BNZ6W*0LNWb!?Y((=cghnDHu6qA{G&&M%V=B1VBSbpVIzt;F(mFePirM z+=2vJp!BtnOf|&7&Lt@vkZpta$4CYs1nF*8jz_=$dmo*dYL7*nFG|M(M6udekINJB;Xqv3ns_0BD`)7y5;{o()mqdaR7VT?iq!$JSj zgO^@?&6R`U_%A>6ckS6ui!%{Z6_u4k`}a@vx)<%;^QEu+y@Urp`Mch*8Y+^y$-`ZfEbFy^D)W{r>vQ>_4SvPu+{EX%!jaGFQQ2%YGJvBw_IozI=` zwHXmrvDfRKJ3C*N<)A+bF)l4HcRTHjodWpGNsuD*rpkmNR)x=UMvZYin%wZ}8~)|L z`am@qx7zKhs>Y)U0Exu2XV31wXjiw}9goL@!Jw`y0t%DK+_udh{NPWSfkeqNA0@V0 zt*bA&755-E`9}&hhNbrYE0#s=q#-KfiGG;VW->?Q8R*`0|&( z?7U}oNpVisC$V(y8JXo-j%X4S9r*M$3=9Q5c}Hl9VmcX(N8{1eS6~0eH@trS)aiTgzGv6m&JX|VpIKN~sOm|p z+oH+F12CF`m1TL;YhQox;DHe8Cmw#Fg*xu9%%3{FboT7@%uEZ`80 zI+T-p?z``euYH{(I8tDcBP{jakYcps5=HfKyeE zrOu0lf=pK64dRI*sz3_FsHNpGB5)ES5F{$m26fF0k|i(+UI5UvvLTp(qM30@JE4jh zFad5N-3MEXU)}E;{{Sqrqfpd3E8!LY}o!rDeuhWwjX~p$3a8u2nFCBj?Dy z?JaK^tgJo#^fL>K$A9?`KX&Ua*D1hPzxBi~e&p92Q=YZ!P}8LU-~RJ2^>WS;9J=56 z-P^X$?GTNjtn*Ai^@-au=C+4zbDMwrcmHr|_m1gqF@Nst%{N~2cc1$BqzbLvUvc=- z5BH_qv@j)({e3!aybKPJiK!`&TM!wK^}KJjo2EiN~5Ubyl>zN<4e^ z%pd>hCkDget*?Lmb=O|Iu()u?H}3G>rEXCmWJIaMfxUaLxb(8JELA}Px}E90doNyE zTo{gq0I+}mfp%v~RPVa?E}!LZe$$)gHqU(Imw)B6|M1z>m8DL*B`R5#r534B*AB4A z{BSr*Hmv7gc=m5T^SMyfCr_MccYCAJ`iT?AckGx0w3~0f<))i%Qju2Ct}5xTtv~+U z6J;pB{ouEqbKB>(PbOuSyDeKbpFVYZwo`20vh(!W`4CDaHH!^95J=6WuE}}lyh)6j z0P&m-2j{#fn4vac^MrL0i5APcKN?+iJLgG8_{ARmV5Ygk0KjB<l=g)Q8Q`f!khVj~P z^VH1YE3RO2?3{D{4Y$1R3!lF|)RlAoQ=k0v7)4c{efGIlE4$;L?u;Sq+%fm)qmQht zu6XYsc;NmJq|@zk#$bf14!{6%??ADv%E@F>mQ_(?jy+R~3Z{iD5u!sksz=OB4Vo#v zyOYmHGy;ecQIIOZxJ8VUgGIpkT+%8a;RMZM2u4VN5`~!w&;TrBB2qDSl%DVe2uz7X zjcAD87(hTo^S1NOFN7rl=4?5tu!ZC>VV0N;oROjG>Bz(56##M07QmKmyBC)3okDN``JOG;Uw{3JFMhAv>8d3O1P#<7q+Tl|6iJgpL;yB4wTNZ} z&KQ+}Oh}?`$bqjwfEsm>6f6xPU>h)9XjH(o5>-)VPR)9ls@M@2(;#n}s_Z4r-BF!q z15}|TghF$_N${7WW`?E=5JfP( z2+l8@U-*yz>9^0GK6QTne5WY3ZQlH)FMs8dOAjnBt1od{Xp|rfKKa=qC=jVca-6r@Pd@qNrkUyg?`J;v(ck#(@nF4GWVOg}G`{JkYh#d7 zG$%BbZc$LIhU0RaO~3x8Yk$4p*SR?&MnbWArr^`(7s}4mTW)>BXFl^;5zU>;DbKSU z0M=HP!}Ro(m+T{?c5ixd;ljD4rEytyTAd&vaW(-gs3<^&#O&I=-u17!aj>$IWjPWw zFE$|q8Z;rqw5cTW%oL;!QIeyv-Odr+XgKZ<*30o|G%lfb(X^_{Xd3DO63b8$gEI&S zmP)KtARTfDp$^-&Y;CtXCeSWAsTvp&8Q8#l=05-BJO2J}zg$<7&Q!PE>r6&v49XcR zDj5U7q^@^t-{gQi;mgNQoH%`=Doe*6z?glf+Zv39NX$O#cJn{^qyKv9O#HR~^lNA4 zPyND&-_?)s>HqW9zyG_x`Nr4p`{5sYmm&Pc|NZ;bm6dC+x%&HF_j)k+{###T694@F z{CVTPQUf$Xn(lS$P}foS@7ev{cfDi&{F(mx`rNkJ#igZv`}ek51<2g~1AAtsrXPLm zvETgYZ{2YHt6k=bqBR_jPn9I`-1a`dW-}y3^f#(M6*hCkGDh z-L-ww@w4ln`@%o|<3IjW-sa4aF~%tMxW9Y%-0@TM!(rKJb+arZ$fDM@1Y_<_b&8@G z4Myk)iBvW5hSXv-dChBX`sY9Tqj}+n!{Orc@?bQ)`s!D$4a>K`j*K9C4Tpb#~*v-Q6re!zCDCES|300#CN~*z=K9O-J5>+!H3JL z^jYS8-s?_JLiweyehmetXJ(j5#D3%l-_NF>{o>~?oLl^>|MQoMFe*p8cke#+^4Zzh zEe}5Ukci~In4aw}t*qR0-#xJotyY$21v@txkH7o)V}Ow7txm@gqDlm$n7VO54F!pP z?hOsh2pB!9#1vH%jl|BBR4vcFni-(8B$gyn3W9-S!;PbqiI7rD02-Ljm;ixX+K8Z% zN;FCq5kN*jAmntF1VCitbPEJamS;dqy{ynVjz^XZ7{TrtgA%>@-8cir;j{i0G&=-9XQO)5P<6t9UvNs#>{*6 zzT@)oxU6HzhDGK88qLU~MKrBTLS-XnfX3bxPmLM{5x~Q2N zFc49K`2rxQ1&QTkZTFr%Z+i2sL^v1^CUrG`_DrwaI&fg``E&Dk-*eB(%5tddx|+ZS zUyOt&W%>NGM-E=R@6dsR`wt$RjK@ch9^JZm_P~MtrY5HCR@*sOP9`tBa5Toaf8WKA zKmMqQ)KwWp=C*CibEjaE^4W;V^-aWio{2=~oS7nWqFg7_Q>xxbFQD_Bc!=$Gv9>n+ zFTe4zb}I|QM!<~I-Ko)FJg)mlt#juu#Buf0|L&t_PM-m?NxyD)yCJnjsx|I+vjjAj z#_dgH8}-bXngW{mdUA}X@>NLXr-&e_Ckmt)Q#82;pdsL3GisrMHCm{|C;%RllQ(f# zlItsZ%MB6OaWnt}mu7oNaiMhiAXQ1WUNeellp03?5i!Kj?4+8Gh=yvBYKs8DR2v+Q zHLZaeAG*Rz}&Ct{cadmBRs@J{s13&r5!w=ng=RX~P`K6!#`JaF7Yi~S%e$nN{`e=CO z%$ZiJyL;b7n`Y;J_UC^o#^^FrvuMIhYDQp4fCQOi=Nz>=FCBk*@xpwk-5C!1dw1`e znwgr^)o?PJ?e*UE_P2iR>tCO0wW7$(^eiCP5{AnQ2lwyz>7V+E+rRLQ&6{Tdt!NkN z+BO+YUUkW?Js0hG@ulNY)v<52Isj0cQ8~Wk;$4TYIJ~$#{KDtI#I3Ao7mhfHsHIfY zMsptH((=-`AH2WSDl%eEtfnC)N75cGsdCNS8R{TJ%tXCzo0%tN8A3>1+$o1OnN&&$ z3Wd)m2r-6G*WSArD58j}_gT8y5+eYJX`;Ml3CndLq!W-`zza6rV| z^AaS5=^34b7^?cl8*e&&>cqK)b9t!8gTY0+cWboaXb`PrHwA{BcKaW{{N;P@`4$1z zL7a29f9?x++;JD?G=J*MPyFal+;Y=(pZec_@%YovSd8sfar*3;-@EO1^HytpWv!Zw zTAd=)A#)ish{kj{FatAQcIm!%eBZSZu6_2Ur{~X(>u4rI5bLtFv`r_(t*f9|(_^S54j?&vRn|8?8PzxuUZOBWW3cH1$U2q35k zl2g+V<9IxFh@3e9szVtai*hRu^YC zO}CwV{I-u;U9F9W>|4iA3|#KA%sqGXXt&kPd=_KfF52E@ld^Q4m3+G>m^qpvVxG5{ zn3;n{W>y7q9?Wu=0ib9wvnQy!EF;jL26jYKykeLvpsv|-*BBy4+sn%qJ@EfA zNnRoaX>pF-ygk!HhO!Kk@ucN5m+%ouW#71ore6wxqRP#814tMe>j@Y%RuvCTqg+zY z(GT<7Tg-2Z|cNJ%qURR#`CWlBp@gfs0OeE5|&rWsM4qb03I2LMWS;A z#HKdYYl)yLswps=LPpMMR5CR~)pn;qD_Sm7)fnSsGHMqs4U#!-7db&9A9`RAQLKZ= zu+#C=o2SsQJJV%$=jT^eS10wjowqy!5>b{S386Msi$OK21O(kOGhM4pM&Z~?$F}d- z{=WD9v+q3k@b_Lk225MJ9cjSxNom4{^A5nw>1Q8fY@TdrNE}oSU3zHS)@}X%T3J<- zx;lI2G@{;p*PX4RwZ67omE&HwrxMtaXh=&wL~D17i}vh7rnQxob+SDd?eNY^tV0M0 zIEWEImzP#d1x?SLI~zlVfO(eXh(uJ@HGnxsM5rR1c|=k*?>W!&WXMWr$V4PFvlK9L z?94C(CC?#7i?PV_cf9S^g@yA+zxRSg>$TgLAKZZ^b6a;j_tJ@_3nzx-l`9V4diATW zx$mBDEuUZAG`9s24K&ezkSVQE2^h)5B4I+mQ*w>4QYxwdN?y|D=}l$=YQ!l^M@V9t zJoy_RJ%Cp_=#!aBRVi&OO_Gvfn6Mp~v{cx@1CcWWhU5@~6qFORq%EnW{bsVB*hamE zv&OlOjSrm=0VQQaREQ{D5U9b3CsIU8K?6{-ft#ujP*Z5Kaqnw(sQ}RQpCn^_L`VWC zqLG=9897vqkj!ifVnRwpBr4i;qH5C^|B72#mDwZM;?m-q-}I)B{@O1P!290%+8b`T z;n<5W{?gC=E7Yr3Vn`%L?EhWCUwkm$G%;M zs#;zovO@Nmmh>+)Qt-qG% z`EW3>1Uptx0A{i#c?--uH9eE&Z$JnkkT4=d*L2HdJ||)|t?LR1n5oEe1PBS_9KkUj z*uU@8>6aC?-7b1l#clC@7f!dB8+s>cAuyST0Z`lo3 zUh;2#`W=~r7p}hgzWX1@Ji07LfQ7|{bc$xqAwlx5nn9jo0D$HGWH1~T#njfVn~PR4F2_ii2;kRTefWw?E?HY2cUt)` z|H_9X%Aft&r_xo2JKK!A7{nKjj z-S0mBx!XVg&Ud}@t#5mKr_=fFlTUu?&;F!M^!7J@znMJr?T1Ih!F0P_mLn}kmtS$o z@+uvF`Q*WU`+ns8?_s7p@A&4alV{pR-sw&G?xqV%YiQ^@y*gCm@i=oC00fPKO3vlX z8l?_#T$ZAmXPG0e>PU{$C{aZt#u#b_EQ+kvZXuAUFnft1)RiUTt3h3r2q+TEvL;GE zN)8e+0aK8g(4d)!5fN_mUz(^|B;**Bm?o16Z8W7LBVg({WU~lrNv{?$#|Vk>uh9gu zjG3vbN>g;sIpz?=dHQqUE1_^pSh+`bG$`WE?|ap&uOAG?G15!Vf3Lr~)@iq2 z|9x+4rjO%W_eb$T2X?UR#l~@ zc~)dDTU%X^0T9$X&YE|Hfr??4^oeBB1h6zw5ivqj;wmB=GX#QJj1f~WHHazJAyP)~ ze)k);Ae-QAt@h z0iq;Va02`wHc~ zovIrvT6jg~1XF8JSICIS;M5upUNdqvRq~*a)?aDh0R}Y1CI$$UJj6smfWeHL8ZtFT zRRvT}9u-VwgTkwfWD)_XRkY8ZJ^xp?f4x)W<+yt2JKs5f?%XH;a`WDOd(NJj9}EX* zFs{lv#Hy}**1PkY-<+Q6fGQA!hy^2$s%8q*Ff<4e9WiAsAyO^RUO2zJvbt&0_OcF{ zhqD(Jr+c#i)N1+BcqFR6)!CYF_5dp@!#pEmpoEPFXis&WYnK2BWsR?%8sT3HJ= zyLEe!!TLnj)>qq|yeNu*D5_*=h8a7JMogwrW8AlECn@^eO?6wXqNwXQ98WfF+LWOZ zQWatqVu-O0k=YZmfe@gGu&FS$JMGN5s;aAc9BLVlC*DDpFR5)J#_Kz?K7=|`*&Amxwf```0$k)Lsf@XulLjwPmadJneF@T|MsJctNlY; zr$)m;Dx-;YMa1cHRTM46bgEm*eUYjH2*jwN+v*Yf2(Y>~n3?GvJb3Zaa{sX>o|3X! zSUCUU^G60ND|HN8w{5v-=Qb5J)!FHuSPVf&gTcwk2#}t6>bpez?2#AtUcC46%P-rt zYxndti(0QYy>-jB#S4qpQs*=8vVMP{V2?cd$dPBCeE$!Fx`I&@(B+?HOuV*lyY9vGxZD+a9iqWJLz+Siew}1OLJGO8Cg`fNI%GzLMsc!;V zmN8H?F|gD(4rb%Y=+L1Zzxmf9A-kv!_B84qtQC z&-|+oj7P&ezVxM=Z+Y#9fA)ia@IQZls^fp@7k>8a*^@6FJHC1I=FwnHLwMaS*H_nH zy?y(RE3dpfQt|OW`in;%f4a?iR%AmMAfh9xO_5yg-C!_SURy)8g9i?p%F@d6cv5CQ zTU}j^DqA;g+qQM?rQ^ru=H|k9JU@TF*X?=lV~n0T^Dg=Ml4K$hl9yCXqtvSEeGZt+ zm5OLmOFHEdv94?9DRK1xKot~ZV{*V46A)hr$Ou%8navW-AHdQICQ>u>gJ|SfRl;>0 zoMU7UL{USlT^v4q_`z>KaO}tnY6zj3(QVV!yWe{4HLtp&-3kBt zU%o-&LVvxFSVe#;l$&R=n{K>m&+c9K-t*<9)w(~yU%ldX+L{TGgf zI=<@qYY$y<`O{B4)n8g^&rBmzN|r^mRG@99%p{;ug3r7GI?fE$xBcnUCzqF&FPuKp z^;rpuA-KX{a$r9YojrSgdTN@Sk1B;DsfL+3E-omfe;Z$fdGWm%$zAA#gyYq zjle|OIIR+O01%O($=oH684(C$no*RTGZYa(ByNl@X^ay?CQe*`RRd&3jAkUp$giM! z5s;Xb2{h4-3@tW3SwJC3W)T20Q%b!70H$Clf~kzu8Ukfnx|#wqp)=C}Mvck>ir}ER zOhiN!MF48RbqI!vV2or&z(SyE>BFz88DUg1F!ZLVtVHG$--gkrzy)iAFjthK-Fo4L z@BPm2{=U{xLhUo}gf4)Z001BWNkl5Ck}d1f;J zqbh_Vc;`JiCc-E+vuAan0%*+ay%&jh-2Kqu!-s2$FTU{7(@#CO^P-(A%Zr)vb+OcN#%%m`If^1LA8pmAzux>dA8ImrRJm777Y)h)|% zG#S?h4k2hXkemu%_+Uv<5;bt%wcA~Yq7uZ!fw`=WEd+~%Tx6|i7ENZmom%0UXO3LB za3L$a7$cBau=M>9Cf}5(Niq*8s0cepsEE!Ch?;PrLpCsVgiI1514b1!g5k$eRLokQR_EcyO)ci)7|mH_l|$$ zBfq_6>$amWz33PUS2Q;(Q3ga6Koe6oWE5jYb}6%(IhvHisw@fM#HsnKXD;n9JbQZn z^Pl~!W9nwkIp|JJ)m3c8b(tZ1;=*|`VQ+)MXfP@_ZP~oGK3HELYJln9=8N_mP;isdPMtb=!>g}9bNT{T z)|x6JDjASrr)XU`H@~#FbYS29-52einVD(%?BvN4RXsU<=G^)73t>Dtcm8a<+a<>u zY6K)8R1mfPaP%L3f%#-go}Mw;p#n`-2jBa?O`A4VRr%S^eeT)kpZj;e@QWh4wz~eufBeTw zi>n|0@Xv1BIu{_WuC9FJ>))6^eR}hzX+vz#1uBZs3<=1VRS9`y&uPtEsw-Lw&MiVz`zIn^mbLaiup@(DDlQcIIm(xnrDfC<&m zz}SJQC^(Q>tt2*(KnP5vhLj{26BSVlB6YfNDxswk0|O6HEh3OgY9UUyKr#)4QL$ps zBvzvlyOb?efVHXVj;VR}8`60)0U!d1CJao1_>yB%17c(zz3w%8f9PHB*)=!U>SU^x zdFLHr%D*8c7O{IJtcggZZnX%}!05N?qIe3n#}DEr@>mcRpU%@Z!tQ?A>`$CvQ~}kqphq8UcX-1<{fNBh`YW z1X((M)Xad=M-UMq=?t&@SE^4;%h}|hf@GFbN*hg}|7WlSBw~OK&`T2OHg2&7De{-* z7i@g>n6Wo(OfRO^M9cs*#%4%iHnV7!>Qfn-9dNXmM649^XGr<~l#)h7N@?xnc1cVD zLKHMGLrRs%&2|-&O&%ddBNQ~D_R=?*%=BzccK~22wo)KKW7Wh-NGgwEpZ*KKZpf z?jkpfgwbNr&QoozsKpQ+dv+XC2`T^sGLds`ae48HXP!87=Jff+m6hf7^})IlaGqgZ zAASD$R@+~=aAD!XN;R3Z+N~HXGxhAsDz2@pjH|e^x(c9$$ACy^K6kB7Yj*SId@@Ex zpE+jd998wi5CIq*8$h0C-ucXDopx(98WKtb36(#@2e zLj?dUt1<%!7Ll;<-V{`1rq^q=+cD^HGA3}M7VGfr^Ut^2?Q${!)M&;&4ZD(TQ$PTm zl9+}B?RFsuqQ)wKl<0`$IJJN|W{nXXvu6!jOHByg<(*FF#K{w?+MQ}=83zMK9jveX z=U@GWi+A@foH_a8v6l&{JG&{Ar6crN7D6aT10+AS)lYZ*wz=8ER~(){e|COxQLMm? zc64S|6F_8SQOS^)nTQ!JL;=7&_XcVJ?6UN1J9qB!iHzzWd(wp7-4Ld$&y{lLzj-|M-a$ z(=(g)?%VP5@s~gISAU)7Szcsn(a?P6RTZdV#ZFI8jfVYL)$O8aXKu^ZZRgINTUuIf zxAPzQu^$->`rm!@;cq|q;H|H}<;p9s-hc6dg@v^|FY2ls4*CXm^7P5U`nsBBSzb;i zV&HtXy0+e)nXc=K5X~5AFzENX-FLs|Jtt1Q{LQ=X+__`t(dS>d z>hLw>vgeK-dCiSC-h9hzAAjtLLzi9p*kg~KJn{0|-}%n%JGP%Vc`T8;*)sr3T8XP} z6pEx0FQ(?Po~qOlfdrJ8)RYpL%@X^G4GmBUIf42y9VO`khS)4#m=OVtQAI^Emm^Z@ zA4u&uK!9kT9WzI%MMN~_t-`y4oaa_CsmhmMdg1CT4_|rd!TTRL)gO+E&ACgnC@)nuhEOEX2!f}l}UF-k;0wWNe& z3SyEZXnM0vNL_FMkyV2s0;nh_^ez%4v$Cn0sREnTR-;I(=pqpyDIu7VA|2$kUo{z@Er^aRZ7k~ec_k8QVKmT7J?RAQWAA9Q8e*Jff z?QQo;_yyQNl3AGnCH3|J5K@vd2+(3gO!&2AX9fdBAl&G@N=P(l)RiXOmZn_X&~u;&PYywD38z`N|6`Ksl8-Jn+!Kj9$Xz0>@Cs{)hB~g{3G0>QqYQrQ- zpM=KwqUrxBV31}8NQXfZTv9V2fT|#XQ&h8LdPg%r5L9gHS3%GSlf-0@&>N_N1cpW& zVok`VfvK_Wiz*vosZIn?mNqxHr#IV{0Af&;u)Z=_URkZ` zYB-+EZrwJ2?wo<7t6i350HBciP>qlY2?U7@kQ_Fk>&aw%<)xQgd)?K@eJO-?z`5KPoYpI6yX40~Jl0KjlT9vCo~;Smo%tS*sLu-n**r zmQO1{;9lrVcZ!Zh@t|tSIzt92(Fp+2kTO72D95oDQzU~}RqJ_{rLi6)ty2_Vu})jOu&p|LiBJ5vA;e{ z+%0R-XfnF*zWbfy+@dpOya4K#ho1i(9&YyzPSuJFf> zza%1R(fd}SJefwFK(oaQOIenMs{Z2VzxwcZ9`1BIW-1cO@dN;jkl8U3l6iK+(MZ(FQ1N)Q z@8XLA;M1S}i-m;+=iUGO_-&nT+oGI5e;%1sm5`a(rwZhVcY{q^5|W^HY4c4l)O!tCs(L4P1B z+vc`y-L}mL#^q$s-aR|#c8!Piv12EK>dJbbncMAxnb|o4Hj4;GLAL39Xl69ua-RF#_vd!KX=yL>eBZHGjLliZ z_f!-`N^z(|rG2G6MoUO>6cyq^W-<%vyLa66`~UrSS4^z1X@&+AlI}0e`;{UB0BrlA zP;uNU=KezqfDo;KE4}Qq(}4)3-L9`$Jy5O{lSX>(_>4iYsRaOQ0gzQ6gMkWYIT&TZ z-Q)lO8kF)81&mcjShTBd0RSY+jEF4Qhkc765m+Hn3efiy5`j{hps!!KRsj(O8i-jK z2^A0tA*nR)mP+xu)oasECrxr|T!`8rBA~M9F#>?g5?Z#vLJrA-sDr>~&MXUhN@TlHue4TL5n9V^EU}0+B5aKzQoiRo zmJlNpizSm}XmOxau>x6^Xh6_pfCbRH>xNMgTGvixxl}0+jSf~L+;-vC!kL+gu_2A9 z6arIiDB84T{mBz2YJ-(h(dL}4dLK>78yag$Xy39H>>Ed;QFz>6wmSEL4UF zbe1IuXe^UbE{Z}3!g(%8!dcQ9s>ErQcsfinZZtciD_0{ZLC}otPHNevMq2H5P%Mbx zQoU8H4WPz$H_7wN7&9<1;0Ixr<*inG#fmYdy}9|hv$N+4Q2_wLFc3v-tl^x90B~_} z{=)Mw*s~g4T7`@Y zvonqQQn6UEhFh)H*|W2yQgL?n+~k^}&{y?(S}YZN?JoB_dKksBu?i(nN)rwb4~NBq z(h7h)FC-ABXY~Y8U?*Xu7Sy-62#+1q>9eAAEkWG?%JKFPM^ib$2F!^w$+^R3y zw5OG};_y`H&Qi!ArXP9+r6{+#5CQbvdHuDP8)97Wm9(`+5VZ1<^~}sUMKw=HnZZnQ zP#F0kBD2FRp#l*`1p?S_m(5u$k>_w^%YI)az)tS>73K`!&b8#Ea{$m_fk8wxOFlX_ zVwp2zBc)uE94b_RB4~k?5Q=sBIpqC-bQqVF_CP!k>-*YT>-!-gfdWDBP$?n{EJ6ed zh?FK&N-QSbuHih60whl>4x(V?%5~*xE$y~^-$Pvy4=xO3UHurdQqKAZ?r&PQLZ|_knKja<-dh&O(G%^A>W-X5;P8b8 zKoFFGc5_RXXMx8PE638F9UK~HbUVjSpAEqCv^K~dfCBAw-dw~djm%aoCNG(UHCzL&JuY@B@8jXS^aKmPX7C!QJ^4TO*o zII~70S|LKPoSQuG1BDu_Ad0X>U*$ajpk9)lnV#;je!W06q@2Cw}zYpZ?Qbi8V1P-w&Ok zhu!dxY^^E9MFyR87i*>b?(h9Iq-`ivavT2UhyTC%*}14tvc@bnx!Og^rvA|t_}`bF(boc-}w6f9Up*)pFH@v&wnnY z&@TkJ6_3PIkc%avywmXoKK;p$ZQQWt=C|$oo!|NB1>3h3;s}A5u+eFgh}OaJ(`Wwa z+y7SflaGJs*DK{>r_=7HNg;}~r$Ld)@+9dNOGPh?4jw)9^>6%pp;WZU;5=B&((h71 zw?NN@eNSuht+j5EDkxc=dy0CE9s~HkA_B3{?sT+L%wmmEM3!@lpllALn34JmToM9@ zU_vHWV8>PrGrN!_01}2#=tMpOPLt%~3%7j!W4}Jv$-eUC|NVvE{Ul<3;`EsVuf4Wr z&4h6NzIWePuGNNy2NdZoTQ1!5`k}x0%0JxnuJ`OaaPZ~5uQTw+|I^2JTzOTq)tNhY zW^r)|mD;pr)6VNAe{lEkniHTt8u@GCMIz1!6^9wU4PEKo26OoW2R8cVs3Q;#r z0n~=c4b4`gQZ1i3-CDPH-Q4Wl-k0}2`>Ut7Y~Au(?|YwOc)-gs;85+F z%P;q|zU{rY7K(*8j~#pd`R7hdouFJu(fs_}wym45z2@p`uD!Ngt~MI=PPeNR-A>8_ zBCXoJ-eZqGe#af(%V+Xpq14M0lV?E?1@4DfJ%P(8^@WZd(^@F>g{M9o-xOCC>3xLh8>#u+NO>evJ z-k;eldB;ufxb&in28Sw1(*DVhpY~!;dkTd0TZ%XW^!uO?jb#U^zp{DlG|L9MiAFwgoq@lL;<*d z6AN;2sIH15Q=rS1#-H#h-0+DGHq1( zx|L-2?>;=b_VN`g#=2>f0FCD<^cYE@LF%yWiaXddq*UM2)V0dEf`c@+`VtwDMR;t!oW2IP$ z{V+H=eM$xX6<6%odf^4TAAfu(3{@Yp2h8Ycm04qQ14`Sz=}|=4ghAyUWt-TYy79sd zwPN+D7Y>|Qq@XrQN(YJ<#290(wZ^1L&wwx*5rdXJ-|M8k03_kG+3Z>nC7#v*NMRU; zQ6K`jNNO@b5JgHUYmMn;BZGrRBxlo0GvC;jBYx4PUlqzVVM*AKB4I|?8EM6p+k;!3fG`_pfpu4{1OYf1uHYSiUS02 z$iTjwgDx@c_#bRpDPrcg^i5af)knNw|F+B>ykA5}3|Ig_YnKU6xJ;AlZ?{l6B0%52 z;(km;efU`)#;DMWWSo!IYNcWnM7C56tHXn*&dp|du9Zdsi&hXcC?F6KX5+}eomTtO zORxCUN8jfh3V+^dqS*iTnGY{NMxc>Hug88s8QWG0zxTVJ{n;-btX3;3@GT=KBo;z) zjb%Up0Lw{3B4Dk(Bu$9q%=DR=xtXooE_m-PZ~Ln+zgnyfD73v^#}E7<2$N2>{elg< zcJBPn9Y3g)i=g5(?HX(67UnC3@|N{mhDSyYzd0SmQIZ;^{ejxxiBl&Q7v^^Ey85xF zUse&e4*2ET#Nv#U9EDdaLWPB}v;<-~4^5!k;Kysh7_9@9yK(xj< z04ob?PlaJ@ET$|TGUxzox_IXF!1#_rsWP`X`;LV5L2A1_@y1 zoP|x!%cpDTv^%z6XG4W3j*BG*`1#Ks7#tWdChfEqBTucG7&TeKEX9IWk~JE0aa>xc z&u!eai9y~tuy6J1wU0gifH3y_{iW*H}BfKZNt>DH;*4X=D+iuufFoi&wuf= zb?YWquAX?$d)|Fw>cpduK3ZQ|T)TSw@Bi+vlWuSN?CjpXua+vMC=9y21Q<%?VlV0S zdg(3idDr-=iNE~vUrnr8dD-M8ak1cOjYuq3^=q*R36)l15Gw8Me(Z^}r>7^^tX(xR z@sl6@Xk=`3>(;GFk{mp6XyvMja=G~6{SVEYz4*#2uGqY3^FMv-TgTsgbJxymi>2b~ zHLF|o#&y^3+;!c~;h`b4xiOt`*eEw)+RX-zj_9|Z+HUUy0v6H5jGffUY(W$% za0r^^2dQ#Z?H&>vD?(l{2uh`y$GR32OOb#eS~i3LfT2(Q_YJa$_?{L9V^UHGg2pUo zJ3&CKwf&ttkp@OVZA>mAjEo406#+sDECusRi|it!3fKrC3ZNjnG6+zL6j>1zWJs;e zwbDt)+jpe#dtds8pcve=^Eyw{_wV?A6c+(;s8$}Sg(j^}pE)x!I&kr&7Z&62+_}?f z+C6V_-3`~@z*zk1*S_0mOBfcCBn8iZ;GunircQ3pE;fy^k@lm&3xdezmIxN>OQ>jY zaIo2Gi%_%EZ6}FV>g@EH*Y>`)Y4fImfx-GxvsfvTqAbg7W|c?A8Uf)fPcjokeyFv( zi+z-&edbTT_|fa$c^O#z0_(5+(B#dDq2iTS zU4G=qk#lFxq&7S=+YlX9ss&>p1xo-a8&nwjp)s5!84>QEM!g>k|20XzT#$W6zy`4>L%0RVXSyWjSSPk-^`ndu6EB@qzCuEm)J z6o69h%3x;z?6cDdMG&np3aCEz)?L1cAl9zO0Xm65gX;I02)N--xbMexAVd{;# zyW0v;1-{qLZQqswmXR5?FlzvG%>jaiLh<0C15dqpun?&@j!vGOKKAC(Rcp^%J30CI z<4^Ru-L#j@&dp~gz4Gd-##T&x_3ytnF)>c0lz>HWJqa$N*k8Z_5+I{<0%De$Fbv{C zuyMosRcqFkD#1417)3E#Nldn8a&=q^<9J2f%OeGsUv=5{@A(BN=_bA5foSbuwXox| z+(_W5TW`Dlu_vDo3tpC+C=Sa7Z*uMGQzuT{dc!qq*KN7=whyfsA9EuuAvpj!I14r) zTM!Ws`t7WMdd0{(fGSl9AbjY_dzI3@r$nO`PY4*%301v zv`FI<RU8(}r62$Fp0Tmf zTW|aW0cLAXpFaK7zyInVf9X#Or4m~PR{#l~C(=vORV&7?xq4@9urfJ0nP*^3zG>rz zCjLR=wPK9TvTUio_`SRC_{4`k7KA~Tr%K8G{Rduq z>6I(5xbn=|>Bk;>?9hQj*1!!n?%KR@+ z)=97ZSO4p4&BghB2M(1hwdvER_TKwSu~cex+Qe8Y6pYP#NfL$82j2hw&wcU}&pz|a z$napXR3fcJEQ(?V1hiriQEQzfNtUFI#kyjw6-(16Pjp+I>Ez__@bL8X^nrtiPM$jH z`@xPKJMO&m2fzH~BiCGW<=Qo?Oq#UXP3@^>vso@g)))o2urLo<=KBoB+q7ZLp680~ zR-1_QTl0!Tm5cO;XaKTog+-(5AwpnuMsasIB84m@UJ8l+uWjTVq9tnT3tzC=4pYLrV(_d7hapFBU6gWpSx9q>C)}#Hn*j zjnY7EXvON4b2DdNdTHvKotJIia%nedUbkx}i~8Ap&o3-txm-3j8ypy5#%8lo@1};K zKuTf)(K*|FM~=in#FkYMg<;%mx5F^nyk%>tQYn?nk3aqx5*;~m^uh}-`Shngd*1{1 z?c2Xk#9n#%<#AMeV)t&X_3gL4w^S?~K632H@nhX)GfUHvQkj#yG&r_?%SDiT-T79$ zV(^0>eE)rq9bV`*b6q1>F(QJBYJ&r_b2DNkZTGBYnIbN}f!00zjLE$6&DOyKZyY$d?}|&Vs1E2(x9tM4=zv2aX_B#F1dM{X(bX>;UznYlUz%I0 zH(KK>#zC2KwG?~d{7n792cM0~)o^}q}08}`|c1oh?9W$L?X<6Pce~W(UNAc!icC~ z*^eOz1ZbEoV1UXx_c4lceoWVMNDgA)s*nW$Jyw9?GBRxY2_5ID#ePYb``5uaZygrd zq9CJkju%2$wASDvTQGK!VrT_6KiePE6xng*Dpj`R!5APYBSb+eDD$CMltM2*1 z>#rYp{f)y~D?jkqW$>7RwA(RL-wI9cNoUvyfFF2S#$)3vhsK6|54u4Z0$5hLpe6yp zf!b&-@;e5&%LLHqP!I(MI;ev6n>GPJ5Eha)1Hg+f?eqNr5G_y?7XY9b`YR_V0pOvB zpQzQ!nax0JrARFFmAQTjK{2@C3YjDYwm^lc1$yEauV_m$Ql0I^UR1JRLR}<5ARyn% ztdYzp01Yp%F(pz13HtwvpI zjUwG%cVKX^mnN-N+syICjT=OG-P$#qH*N@mXnJm@m*u5mA?qc^S{EBc0Hw%DmCO(T zWqI!VDvZKTw>>^ORw@=XK$>J!3J{^$Sn@nA0%9de5=}^fPg;9Hph?-xTCoC*gydox z&X^@8&yh)yqDG^E0J#zE`!3!>s6e4oy47sY&Cjo2yT;_KmA1-iLJN?YL@6YTVy&>1 zWlDmt^y1LRc|MI@a_Uzd+JTj1_X}z(yVth19lHbJb!q2$mF?> zQLJJPKx_I@89S7f#>_3R&QXSLIk}mPf|k$07Zw<2S4`HR2&^HRCAa@ESl!opy+^6v16hkcqL; z=bwJ6m!#VF;y6-hPri9{W@g5iZ0EICtr#6XcjoL3JFol2{SO>Gxc}tT31CD`fv@KU zherm_-+qCBy!P5FQzwoeee+m-X|Y_cL}8p;YmGr6^7K-3DO6q*7aHxBDj{ zUi<7DuX&_0%TGW3bds4;xsqjRx7mDg&z>|*Uw!@c=U;e^2wkyJ((X=7OpFWYjiG*h{S>djI5AEKr9GYjmVA%>XOH_9Q72=S*Q>9 zMiKB(AqfKdL4Xii7K@B*xIZi_5fBo?f=WBnq;*e1a6usMCpffcrQdz$V&h023oBGW zt_T|deb#8K%|UwIypwd)(oz(9hHa7?5dbDFz#z=lI=(4_wK)qn+bt%9EH_CKM{&E; z4T7MX_A=A+JRKL~JmdNK#b&c5!mZi%9d|xBIy|sp)22Ny-CeIYX6F}0R4>VlfX;x~ zWEQO`1D1SGAsS{&6sZ^xNh!l7?PVsLxZDRwr(038@lK2d$Kg!aPcL>!=tsqfoGoj6=>(8AR^^^2won?0N@=y zcpyo;9tCJDC`E+62n*(58Cmk22uyB@VFA6;Vq*@V1C{}8v)Smj+r=pEwcFZ@O_no& zp8ee#hfAKi5R=EM7sJo@OP)k0-*-Q6(LKnA(;eIk1K!iz10CQ$^&4lO(Er3AU zRk^yoPrqGU1i&ntT0BH+1vR??1Cfx~C1zN}f+%7Ke74rO!?-Xqf>NlQvH>|0C|51i zpF5b4`mSLR+yBa(qapyY3~D)}O|Ef}k%)y+1cexck%SCbRH8&|-v%#zu@jIONPry{ zOWq<9FrmhrjRtfbOt9>K2LVe$*yj_pdYOSxKzmVPsZl>OH=~_8FU$l4ime4gVFe8A zg97Pxy4K|X^3AVJtQ<`e^EY4lhZ9rBzVekn9~&9S(>!OGt2eC?h3NZ!Wq9zP{^k33 z-Ti~H;W0oYS9pT`C>e-&p2q;0Nd?3so#hq?x}EmF{rgW=Pp;j!Z@;ho>FGJ8RUG)N z^@%g*zWA4450q{+THQ`|?8Fo!1XRh{96NdTtKa?k(L;yN&CGZ~aQxVt)p8{>8FDte z(0u6GH-35FLnqFjRepGI|KW12*6p>~Ft8|vPB{RCEVI_KA_9xd4xVqokM4Ww`G=l+ zF$XNhQI<3l%KFNn@)4eTV)x{SejNq6?dI!mylN$vKmmY492yy!o0+Zz z-WUG+=L<157G@6adzBOhaWFbQoOUylC$+(9bznfOO}gz|vTa*8{_X$y-!H$i|LfoW zXUuzIg^;w8yq{VF2Qe2AB-OLI3y%v+5c+QGg8D?p^aRNr>d z#h?BBXaDdIzFcp$gD^78mSLg3v}feuhQJ~Qc_Julgmw{6Z^NOX=neDqauueyvMrY2=o}8Yx)+(iKKi6eNP-~rMIV#bB zaiL&APMkcI^-^E^q5u%J(s`ab4#f1CGf@;3OGU93ErPIkqCk+nqEL50lNm- zWl;%BcV86sZxe>5V5%tkihrjpwjNNdd7Hh44%$FN>NEG zl|#a4j0Qqa8ILn{ZXus}b{`Q1N_&3fg?=y1d_PFCjK%t4s71({EX#}tqhb^!LP2uv z#su2;*G{f2Rjc3p=WkW3)oZT2^4RfXmtJ^a`Vgk9RHB5Nay%@4n|LiyE{7?W_SH z&KqqkDW!uT%`#(65NJUh8(RSapdx@mJ2`h`>Qr1BAw=KPL}VR!j9nN9fJG@)C>D<$ zJNCrmyLVo5twH$7y+8ZV?|g9c=Jm5P=cbMy9~+;TI(6!$y?Za%{@a&by5o_@9z`V5 zT8vn*#0&_GywvHu?Z)eFz2Wk%z<2-S=iQ`t{aH*V&$e(0YG2@0>S<= z0)S9#-$Ltz5a}mtgcMmTgu+&kkepu}5CAkGSWBn{&{tmWg8m2|fniIiK!8vgm-Rsa z1_RcS%$LJ=LV|=SY@E}k&+vEOrMQ?Ux{5tvLx|+oF$_o~EFLP0{eZVy=`WuL`j|Tw z0TGQribO;UG7EYdE%UMiSs|bx0ibZ;>!o&kvDFNNU}kYK>GfFH_d?gs;SdW5qyz!1 z(WptIK(p1{wd=aoYgfe@;?Uo<^SV88Fg!XW1od7gP4ZSJskgfxX%w8P_vY*KzVG+z zG94_(A%mBfcjWL^&Lsih`GGb0{SQ4RV3}Ejlu)r4`A9;llO#_*{UY1k_akIMVlNCB zlph4Mi_JTK^ive@J(VSi^8HTQQ=~%Q+qduVp~K(ob`m5=IVlZSJl{86@RV|IMnqr{ z-}jlVWs4xBm0_y{8Bhc=1D3^tT{7(usSp+0Nw3}M5qf^$Ypn!0H`W0AASh&V417N^ znKc$kv54pU#&WCM697;;Gon0C5at%<&dr|t$VWc>iBEl|(P};YtH+h^-FDM^2S$fC zZ`(FJGWx=vmn)U(yKdatX7&+7fZAZS)v6b2RU*(p3{a_5te8^h4U`LUpcb3W@s%rn zP{tS_)$AqvkDXpIRy*>>o14~eDV2viy{`5{NUZ_NGc>}bxHvpG zM!LH9z{zJ`_~q&8xim9z6tOiC;D#9QnvcKeA!-`o>az>$`4w)xpZ(@UUiRwHu8_{j!TMeb+7T{O-Sgd)Irezi9jRXP$k2W^T6A z>xRC6`>);po$vm~fkTHbxa5-SckT*8J#}IVkw!;Hx1GQB+yDG8ciwf^?YI3JAhjCZ zk+G5S@zHB{UYjL}0QS1=dVMJf!d{YS==UuHLL3B{K@ngPvepD^_Xp5O2BZ?RlOr zEi9b3;k;U{`tr+rn~i1=hV6Dc&+?5M*B?KAEX}egimb_J=VpE1KkvMChYud=by~hp z#_(KA{oQwdskld^bN1#JT2Zl@n+yR-YxkRE5wzCr1wb&40U3w{4%R zHy(WK1%aU5X-9!)#jrsOB8G+zJ4?q0y=*UQJvNTUosmm_8_+P*M zoiK<;M#tvo7Z#S57M9wpR37(b@hvT_ta{Lw*PW-@pdE-AONONPPOz83-K#0KNAqk-sCLlpkNP^Z~&3*fVfOV^-{wE8$?m%`X6(OadKb|upS!Ru7 z98iZD39SQ`%3HUI;{qyn`+3XGoaRXD;I{^WmrISixu`T6icY$`=MC z%(ArI?u5Pu5%M*VMn$pbA+uJbh)63Iq1<|?kg(s!fJA}?KOzKQ>)ehmlrv$@cA-bK2JPz zVQc`79GhRLck?yH>vvuMv!DE&GwVeGYGQ!Y7zD|(?DpGl3j*wRN$*}xiC93M`5IVO{i;wW0w40X7B#-kN5B29~TM&wEI`P z3*|UV%`?wDm*@FI4?q0ubI)CL!3B>$@x;u`%)ZxO-S_%y=S`kRp11$tfnu?!6pGkD zd!YOzO&X2X?YF+|KfnJL1JE(>(8JH)`MvKSJ$}>={3r~ONO`JOs1aapOc488X%=AS zMyus1(n^DfVS^s{fj4{h^n(xH+iUF@sDzhZa(<@`?Ot;73}hw*2d($Zl~AltX(s{Y2)fOYlaHpRSV6=tFOH}P^(>b(bm~p-hSfv@q_yh4Ap9H zzxn3D!GVV#d8E;(->~b3$+c@3JJmF>;lnRc`Q(?)OK8Y*|RUaq?J?RC9^3a5@{6Fc5wg~b#UNCUKjO?pX#%rz$&=3?f8+2B^P@e>?Pl(IVQx*9fgdRJl&3Wq5yPqE zMp&#(ljNQ6c*o#CwOlNh;^NW8BlBlw8w*RwaAx{Ur`_4KapQ0N`fWe|`TdJa^;che zO)HhAiPFju`~u$>W?<2x@A&?MUvD%!NuK7cbRbB@IJRt>i;H=lwmLnV<{$s`7b}Hu zesQVW>5f!tXdL(fmoI9U<#3aP0swF|7?x3?a*{F#fh=ED$^fG~%Zm^K^<_bKWeNc} zgbV>%5m0^pv@_aTKqA%W-Lo541OSb&a`p@Nk1~o_cS!@laxD;w0I?fWoORa~Q1rWk z-BjahNL`Ji5D8iqAwU99M3(!JAIGoaWq1-1vIQUjA$C%TOSuTVg;+BEkD^jQ%pjrw zt%&M#a1juYv_l9Rv>@ndP2@SKr&Da$L$MBxM2KiC5Gh2~+BPpwPY@Gz#-Lhd_z1?keIt;RDUEX+nJt(7Xr z5dw8{YuK1HB@rJfb1ATXy3jqRfRK`2PwS$mbr?h@NxH4p*u=Q|&li@YnRoC+@7Pyj{l#p z{#{(CYDMKrsaPug;@rF6X`xVbV>kh5fQv4@^yw#`kc^WgN2DE>?O3^D`0+;{>2|wbT;$x*Cj|w7#R(7p zk1Y*gEvLN%0YC%^hlU2Vhe_J?Ramb#Klfk0u(WhGRQ}7ay`i*kvs{>oAUAoQW|>Qo z7|B4dI`6!8uX}j^FUD7|saA*2%*+&m=z`7LtkA{{Tb|tg_}-Ua9vd6`&!7DGLk~Yv zic9Ct&BSqZ;e{8WryhCi5zqJCk%X-^c^(%dmb_A~0KiHw{8C-v zpcs4L_5HcYjvYPz(yK4qUQg>n5QfEKxz%X}o}VV!?Cjjs@e{q?C9xkb&L2HX5 zeC^fO-#j{X=FB;zU~+QZ>Q$>uo-6HVY0s^<91zR*y*y9z%({El^+)ty{kbtF$N!(G z_YSb@D$l*&vUWLjx<+NxyDj&EF}TEFLQMhzQvxJF+Q;{in?PP-bZCM1VXP5=P@;$=QsS`y14d4XKmoE&zd1DU*MIewfA#Ud zf9Ba|CpJuY^}WI(uoN}`@s?Ukw#XfkFcB~VIbTqDjUfVLMee_QA98d%*as^ zBTy)YEorD=3_8(rL?A?P&a2vh0#WZm-z9N)S_6_3zkdCO!RBDM+upzbt~>YNH8HXA z@bgb^+q&tMFTXnP^$VYg_eWoN{=$9dRcbX8(fIhfJ$ugc&UumLrRC-2mM0n*8jOfK zolc`(165*LQ;YLF&+}Y@Fu;_MF*#ec2^(AF0tAA~EA2F@3=E9+om=R~F-P5QuW*2@ zacmTrIR*i6YQRv8Nxiz#S`pM*qn_EUIXJj}-G(zKPR=gPW6TE+A08QBdwTjTCX`gt z3ohEZX8iq=XQmE5{d8Kb0-#zYVl;*r1po@{XE}n~vupbcFP`b1JIiUYY2(I$MzvP0 zIJ=?UD{jC2w*Jb>HE+7nNuQ(m$;X};-#CHBc(>! zgc*R*1l+AMfL98mHKM3^@ufOQ!IZ0xN)&a;iwmw{wgLo;|F91>50uA1IVjzxGmAT~oLlEn|50LA!d?$>1pfi)Uh_U`$p4PsAYMtx$1d*f?7Nq9CxUEv!Z?hQzrD z$+;pz^j;85oW{LQ-xc0_X}7ykj2y*;oZDPQ84Vz*S_P--7`a~*9x=-@F(zi3o|$g9 z+tYIkpla1Im{9!@C5iW9i=y=HDib5HMo|)e697`!!aE<1ld&;Tl12$;S=P_{%q9T! z6{OwjCbinc`VHf2*LJ$?*7D*LhYqeA8yR0S_IIEB=E=4gh(SR;T+5uYdi{o!d#Bc-?=; zojx#F1tb*J5gSFT#t<_o?ZJ!N1BHoe{9eBJBJ1b zmgeWDrp|8OyxEJMIC)&NJW8UC+qZ7myzRg<&owHI(H(oHXJ@iP<`x!y@r|!*Hk&6; zPjz~|G)_l`MtAStv3)&_uU$KN_UzuhyWaCF?|$Hc2X^k+`^GoC;oG;|QcDsfR75g{ zIT{`sU0GQKfRiUD8}<6m9osgqUk6m*zG?H~;zC+UB8|d_e)Wn2XA3ff%82X%&=7)v zh(W&mvWvS*^FTN-&>$`rmwNRidChBIb@7E41M{T^&ine!Utd{TVt`Ctx7$JHZm-jA zcT8*)D6Z6p$2WM2Pn|enxC#ulW)no~Y2||-{Ot$szyJB8&%gh@?>lws4&DP3F zHBP&>ck|8P*uHbePk(ZEbD(*{4cFiN^_x=@FV4+Op6-hGNm3z3@10?TK-T6Sl%t3h z2-Mmlm;=QFk}@+Q8xGEW5)orKj$$tonP{j{71cb?!RAOB5snO|X%vgMxoZy&R9w*? z9H?J?_4Vu4j-S7GPu9;qBnVb%wq-z5kT|f*$)Gq-9MBX< zh{UKK6hM#!1W*i7X!KN3AQS{tMnm3vlwg+xKqW;$^x{?zuO#AqK=OllQD&0W*+@iD zNL5iGw5y1?5?rC+y^CTJu?G)5+wOFU(7K|RWlqIf4Gnok;li*Lo2UR$RBJsDD@tK) zQmHt^bMy091fAIhP^?UBQ_vq21x7~5a`+oI(n>KDd zed^Sj@zIyR{N>}LYo}*to_+qAPOqyfXJ@8sX+=d4(L|=7<*iP)$a7#aQ4}E?j`KV( zY|-oX7FU+$mzUxsMPt&WQc2T1NA#4Yah$|f3$M1@b=84-6vy6)v(9^~K4&1`^WOWQ zC_MhyV~Yz5iad4dloB?E2M<1b_}L>zyhw9k;Lba5zx(c=q?MF8ij$ZSIm8D_SG5T+ z{i4X<`;IrBzi|uz4xd?BSX$bci{>!44b}UV*+;B0xdJDJX=L zVvt=?J(cSp)KI(t=$$uawWt7;Kz#0*kd$oU1vO$Y2Ay-gURD%&OIb)oUObTz@3C6bP}C9< z+ujQSD8|(&GDcOCB(_cv02#Bq$O_l%^{ll~OwGZDiK3$Hr7q$Hxb+yW&+lckTYl4{v+o z#gj^EkgT&skvA&UPN&t$vX{N~%4(x72&Yb;by@e?Yp>a{V@Idgojfyn--8ddTJ0@c zxBT4oH{Nl_?UPey>S-MSlGspWL;?`emmQ;J-#VmGT!|w9Am(t1srQD-TD0DYNS@{1 zW}7!}u2)hLkA}kVZZH(amslkP5b=ghxYPl_FvZ45;jFi5oI2~aZ{Pm$zy6=9@bQoR z?eG20ZvoiFnVBb__}TU?o6~yb%$YM$l%&JpJI_CQ=IsCcUw`wPzy860`{EZ* zo|(Gnf(vfE@x~_)9Qf+Z-yq`k<7+R!;?j*9*BgLNyWQ)xe*VTA>-EYPzWAkI|Bc^x z(=Wd1@H5YxI&orXaKL*t#(+W+Ct+`!#L>*`OqOL#)b6xf%PY)AR23wI!$CnL7}Qjq zXU1|18-S&%Nm^-jdvP_*y4lKdtJWao%BGDIw%_~AXa31K_qMma^`js8{XhSUKR-8p zZm7{18XawSR#e@Ck33{;|C`_b{;3l)ODoIg&Yhi|nT=}?-T$*k+nrveQ9n6(=BM}G z`^=%Ir{`y z-{$?1!2yorUAy*f*)p+h>!v+>_S!set*mrAtt5#rxL{vWsl9v zAMogasoV|`mUb+a^5E+w96iIwS>h38zs8t0auIdX1j-R66qK0P)VwfcU1&AR2KMTD|29DtlH zyg^i8FG1T2=msEkA`ub*FcAb$nMn9MLV$IKXfjY4rzwX8)sV&xpHT7u21D>SR1y*( zhz7)&1XD{%iwMlw@b5sm8x6B+KZh)c6NmsS|0U^NCPwNDfUq#&#)3s?XS z=HyjL6tOIleu=ghs9$-$9fCazQ}&U$eQpvo8$69f=PrnK<`1ja+qd6^A>ci<5tPzm`cMe^bq zxpWO7d2g8jhzsw0x96-n@5H-haRYdUiOPzChzX;1>C;r^be7n^VkzT*o?sPhxju!TUi!K^px9*Go@#RBDjxg)5z2luf zckQ)@4?g9bwR!f6tFC_YO>eQ*4%U+2`^ZOM_xjhbv|8)dufO)X>;LFa|Ku%ie#@pU zTk5syC6`?G=}-Oh;=r ze=^hD zMjG|O;lVu16%7C!IdWuVWTa6|r_WCH@;prv;}sFPw5FFITvZ9zQ5d6rKp6qr!XjuI z$Cwa`SvxkK0({{=zgbJuG)_+(doeb&abiQi*Y0JVT9P&fMjAtdEA7syQzv$A-Wpdb zle6b`?b>(oB6GGy}IACOkAr~R$86DwNq!$ zj*h^#Or zyXeBZ?zwy0j%_=)@4D+JclPqk6)s7lsdKYm`{uXa{^qx=B(=qbrKrUr-43Df? zGd4Rr``BZTRnqEp*I(P|wzGa;oD|+~-n6;VtTr2s#rb(}ZM|7H9LI4KnaD)c?{>3x zCj=T0p;oJ^Xl%^z@Nl=&QxT)0K%yloE({5%=m7zhjg~EUl- zx8|?7_`D742O}(E!$^+f_{8bf<4+zLUb8WYs>VcsfG8kJh*pr;L?i&qY>ogfEccOvV~826m5LfzSXwT`5_1HM2w3*NQ4%_NDsciTNDyJf zDW^#U0KF_{!(g3Lk4U1z!B{}VY?`&`dq2GWfd_v!H$C0)8BxldB&kV~wBK$oEG%;r z4OG&P{O%ttEia!uJ9*LG^P9CAsao;5s&m#DGNK9;+J%CcVGykdtEze+meAN4BKV@j z=)@@jD@Fk>jDFSMO(A)-x}s3P;3`3YU`z;6;?)i;ed&>3f?Gs{2^0zBB}_``wF$8p z1t`Ck!uSFPIB1OwVcHNRB&6WU2+5h%lO=Gt!tf8B` z;LZ&|Q0RjV8_KReU4`SSV5oif0D-FKeZ*zUqDtWWlZujx3uV#@0s+vc%x0y#GCVN& znNNRmY;5${(HHN(_uj`Jee{q1@Q?QF*?jc)!x06v_z_MKp?7!~-~0LLsk;jG$s50#znf0U<^8=!l6? zK*g!eYAIj#ii?@hd(Tnzhqvt)tBmH#%P&Xmefra%T(fpvS{(q7wYXY1TbiDsGy{gSrj{gZB925n0xFQV4pmkGgB;#%Rk7mYCwkUa_^FfM`0p=n-@N_nU;kQ?B>g=5KVInxrO57go9x)n=no*}P@b(h^LcJy)ruQ4)(dr=qIePP+L)5ycbU%pP88fCFh(MpQh3Fb))N3np;_Jot-*&{P>HLlaq}8S8n>{?Hku^SifFXow&3T8#LZaW1t#=cmWNeSi5n<_|-4F+&NbiS+%;UR%`bAy&`wc`OM`-mNn~jMg~wP z-nznB@vS0?5J5%7yCO|uV(#?%&4IxviU~7NG@wXA!TlOSqkyOq0r;?z1;8M&cu++# z$R0!b5tPJvjlz;y5g_0@C4?1%jY;c-7Bc8gZ`{OS2lqQ86?;(zn&Se){w$KK*qVn5gprI3fo1 z)_bSEKvaW_6lviRl-MDdxKfKEll8OQX3Ch^{`BnB#)-`$brAuhje%;-)~(M8DNT~B z-v@v+jjb(+<4PsT`h}`mYhQNxD+UG!ymQ@d_pv7)Yc01T6NPAH>B;v3puy2y%c2pBF~xD_ITk9_#Ic5Yew$iq*r zWSw(QBFMi9miM(HI-@dWa z8O{0*0cU$KF)05Qqhv^Lk*s${s5KsubQzoxKpe8b2%G)|162L&3L{Vx?WNMX~b-hkeO_D6n zn$3YHo;a{}-KICZ?lmjj&V~&eddth-{LXh4mKQ-RBfa;gw_bVW#j~?38zn@(Qb z_}bT9IC<`c7iQbtb~no$=$_rX`&qBo&k(seIQY)@zP-QFnL0K3_?bsG?7nc#*l@~5 zeLj8vqfR5QGQZfmYVG>bvC&4g*6SC=5ASr|U4Ho$y?#DByLfJ9CazV+*R8EqVPI%@ z&6=@GFTHedXypEfAKrJ-#g|`k<&W>&@0`Rj3n&38fG`pW6I*AC9Ds|Iu~{2#S?FaQ z=L7&ICN??6cBgZ8W;RWlv-68!ZKKwtB!(z4D%N_h>OfQtBOrnUpBL6S6(BO^iYu;K z$%-h6C(oT*?6d|4250AHfb96%wE!?YJRDc!Ue=453I_(!+JY%%G=`%_tp=V%i2!nI zy#T7jaXdRaJ2yZ7f%ko2-`;)ITJ6zC9yxpZ+}?fXt@Pm4uY2|B$rE?oamSnA{7WDE z-+!@w)8=ExPo6mQVw$8L_}7U zDFXE#0D%m$GoB2p2LSfg0it2bZPDv>-}=k1|Ap7xuy&xzt5kq~w_U5%yZ!D;r_I18 zPM)~@vdgMb?Vh{uo!WkOpgCY-W4$eGq27;=uHS#x-Cz0I&BmCY-nIYmGtb6J1rZ*6 zMQet5sBd zyR+g|`kh5*Et@FZCqzWm8521tpc+NSc^7e{S_Uw~VpqHaz~#kOrP3~J*6a7uI3*w- zRv*Tw7erxZRAfR?&hmC-Ox`cTfTiL9fQ`vrZhc_@%Qq(+%@9|aRN>B7-n+vVA4>FR zfLDrmFDBgK0TjYopcIvZybPjY9|j7HYP~3uhW0`b1dkv{Xq_N|4@7?-0u=z@L4Y_? z=YkCGLpVv9(Bws*sW!hjXW|Gs8Xg)h`Z>hx5m5=O2%#_6--4(t>cz**94AYQ^KnY8 z?#kl){M4B756Ty*JWH~rF8 zEA7QkeCq3Qbu7kMpa3H43q`bEj7b}{G3$toCL9|!wR*)+1PWGt*3a_1V2V_=*XxOh zfEc1AsoB1@)+R~poJGVaGG4_wF~q9sob|pi5v56V=-82i2M=bQ9&?0MDvBHlfe^d~ zyqE`{rfHsA=WT8=j-uS!xw+}cn0lq=oEB=GdP1rssfOZZ5fzQ2gjD;|`{{l6bvvDl zFS_vE?|H8=u@mpSFb7+^l#hKa?M?tF0syQk&N)P41?wEJ0aX=WvNp&d;7V&{EZunN z)mP5X^+(oJt1)3J!vu)Vg&uVTEIXDIl-Q7}Q_(P#3LqLl6haClJt9z0B_#=l zp4?g!N9}I!%+xvWad4CxjhdA_iYUuFBE_p;eccVOdiAL@zjyGtV*^}`DNfR~RG&l@ z1qs108P1)pr16^Z(Y(l;jVi%##l%SJ)g^HPh{UON&RXk5m;>Gn5P%|n$+t|*N)DX* zux>&siya7)dfofZ;_Pg_TB+1xkMh7H4<0ylU}kBNkcMj2`MGnoYCJkL_Tus5o40Pd z%a4(+fUv7(__oMR$LM9*N-*ZDozDBefZ(Wx9!-qe*KUtcJq9xwVdbKC6`{h z((3-j$Np+*Ww~B&K5_8yU;pjDyy*>ZXbz2Zvm&$d!toQ- z%!Y{DosKOE1?W557#do;aYMCQ-MD#EqggpOy*xG^6Gh!#asGMRCTGt^$O}tL0MKkU zvMeKJMTt_A)>B*LB84(p)y&$I#fw(}U$`RAnGFJr4v&1}8{d5UJKk}@dFP!xd-n9y z)GJzxVabdf>LFHQ{&4W2$VH$FBPS8>hSk-_1iPQPCxc3#jCo50+oa2IvfsRvcH&PTE7XI{KR z;yl-x`SzLV8S$>!9KQKmKYH%DBa>5;xi3@+1&Sj7?svb_?e*)m`pD>zvlaln^XtaP ztJSK_ix-X@ot>KnaF0Cp$frK}H|Jk)ex+Lbqd)%mV~;%gnj2ream%K9qan_I?>pZB zfL1?SZe^9~fFdN-%H-79nVGXYckEnQS+c&~D~cv4A@#E^Gdk}SSiKGO696zK3T4H% zu)(wAeNg=weBdf65qa+!soU)l6S46n>p_Cz?aPT*3tL1{#6VueIVWBKl?a`)01(HK zF(v@}gR3drC_@W!dEbZNNC|Ygux!?{o63t2ga#HRg3#F#F{>BvEFl1)_kxJbiHIX2 z@ftIG0Z(Onix)>kDxly3XI!M*EGSCpG;~(LBNzZShyr5OqdEheTWOi3k|asLC`2;DJUl$?oC{5Rq$pAz*FwW`94Clqz4xjdSRe`_ zzEZ7PYae>};b)ILU#(Qf$Hv(hAdHL=0a1s6a05tD1mGtoCOVzY=`*Ku>p(P#qbOx& zuGUik;3)E-NffI#Jh}lweIhVW=pj-C3VlYwF)C7Wn_=~;DKkK&fJmhoBxHZW zItE46lts`~cpou?1T@S`LF`~92?qrwB`L4V5T29Ox@bTo2`^I*NC;#?-v=mAxza)| zE0e;b9ZL@k5Ry94D8vK9923ARSpEzzl`e%$Z#XaUYKj{%i2u8`Z>`lTX+mH5@>lcu z{FmSQ){(JM1rLZ>mKW9u0+SKo(^E4KJ@VM-*jVB6a#YfgmIjnotb;)nHQ3@va7!4(Z?T6)0EJV$f2hX&&*9X z2iC0gTNII(01pzTD0~va-Wpa%z|l3sY*@WTaU+9uLy>dNm_TA>MM@&h7{f@#Y`k~Y zI#8(8ssYktUBMI!sX-{5HE1k&CL^I$$@`-(9PRY8tXFK=xb}t{ZX6pMnVFe+=%I&H z{cnBX1BVYk#fS^DbD#U{7w)-d_vtg|7Ut)!xa_iKv;OH%|I_b&@c+C1`s?p~=z+ak zcir^1w=B%f{mW7^H6_>+6@Wy6(fWo~BX-#+`VgM-6UGc#V~x#yn$*<+8tQ6YdI4nVEZy6QIf<6{OQkr?u-BR z)oR?VR%^ykQDnnI0~|34J4GW%0IikQ(((!!L(JgZ^768H4`XA!Ue`NcsaDf8bv}10 zOlf<$D@YqRt)D)-Y36x<=>(Z&W7jRwaN66Qs|uvjorqf+%^1&tRphD>C_eb2itAMV7m0}&fjOzI+p-s+3edml%|G|!{ZBmf=$XUE=ksn?lzq2v;wXv|V~lveu&^*Z zJRGv@-uiI+B@$**MZ?Ca2P`cP%mKO*HwOluJaDkxX|G$ec6eYgX6kmkd11*AdSziI z^v(m4hU3ZO`Vg%Z`ry%s#J=ipQJGXGjmpCUPKj$m34onR7^f}$d5Kg%w;aNo`y zTmSp!AM}=6&n+%pa?#$4_wBCK2K}kY7i^Yw7MM1U4h=l`;JsPqDnqGCXedC`Fm8j2 z2D5e!PMxxnqB_NhI7oI-N&$pHUns{474gIzY62NqLfA+{f1;>31zIgxL?^3_zJa5w z8rDmQgcQQap*}Q>2D-}7*N_elUPMJiFN6pLVa|)0z4sdOu@D@vVMtIYy}b~86-bC0 zroHejq9IV>FjrxzafXXYHKg>s00Og7RSqX#@q|nOR+Ymo*N%GcQJn~ZGL(omU)gyNfGDzf zbvB5e0Ln}e3alR=uO*4IIk=({aTJ*(t$8IY5Kw(K&k!|2EIbgQ6%mvuO)7Crq1#f* zF*=G@@7%KWg1zTI_OnMPXXgeQO%!?SFTZVZX~Fqo|4;T`an;r9#@GJZufF%93wJLs z^gj15pZ)hQ{QKdUe&1urg15+L$9^u=+~1b`f1y6c`lKDoFw z<5?q9*|uX38+0BPd&R-$o^PfJ#nkO}ZDHr9XPL}~4HGYa^=me6+;a59>8B1JI&%EP z=85&YcWt|H-!3HIwz|^J^1MKCpkO$fn_HRfiFG0rot#=CjTaVXo_OSeSO44%qImMu zX=XQ~aZ;_V9T{KjK&4WD;=q%qCMPTPT2bWnX5;Pec>9iRJA1i%{`qIV_LZ*=j|~0N zn=bzG9X}#Ad6s!qX0vzi?lesdM>8{Xpa0?)uX)AGU;EnYhK7c2y6Np3)~|i$*=O&& z=bm#1|@A;Jt>(>3(e||NsRo1RupXUw%m;f1=$$KFnL?kv$r87?i@}fYbB<8{4 zq5JQBsN3ljF4sUqQ$!>dP?b1|V}M?-*XeY+{j5>1)~a;??DhIcN=(MEiZaKQxG_7w zI6Xh#TIoLb?6U%L+wFJuZ9j<<2B_7OhaSD}(9=&_Tbwy{=FF*+qa!23&4II%la&ZI zZrV6?=G5rO7$|_)N}A>cWLZCnB14=ciM7^yE8cPxF);!-?@JVCfSeGBh+*_fQhMbP zHPGI~iB(m`P~XNPD!y#GB_w1ZB_aYuTR3M009q^UV3RPbwnaoFAm9+P2Mxs~MC^T- zT!=MLuH`bKm8cT*jF9GA{xy^8{WaR1x)pV5|pUWQc^oyvHmyS^M)$GjW0iMsgpJ9X|kFwCV>CE z_5SaC=hn~s*@pn&Bfs;0}b!gix1XRXRUX_hK(@^kQlJmDxnGReFYFf z43&ruAcS87OqMkG%Sl3Dm=waIQ&qSucnd{5Du5;!YD={x=n!G*fPfPYg#fBr+CRbr zA6B7mASkMV0~A)dq^Rhmj8&A_6Aj#Y0bmK)-!Ql+fRt`uf{@wvUJ#H#OB7vr6%him zR~7V(NE-6Y;sA(9#Va@jG)N$-ARfV#U|uz4jWzkOho$mr4l#b`K-D7xAR&?)A zzz)TUCyXC_@IV|xrC$5d5AHsA@W|$En>TM>^T>lwBgQ~FJ3W{CTw@v<8vEX@-yI(t zLkZ^NGL{s?Dgv?sObAkzJBq3b8ZwL^!OATmFXDq9g+Vt$RS&$1i*h2wtN^{t8sd7T z>QtlHEG#TWCRXrSmQ8G&7#tcL8_g<7>V;4N8U0HuLMlV%OvFT$v|@|C*P<51^-8_S zy32F3)9qy_j59Kt4p!?mG}^Zo&>$dq2Z})6K>-j*t{#LWw=?q#y_J4H@25$;b=&4j zCCy!-KuMek0x_&#yKZo(8AW<-Zt4fOe}Bi0Ex+^&ZzPb2{i6>(T(4DEdaYi+muKB- zQvLjwKi^qinV*}x>)hQ>95^W6KlH%ECyt-2R;uECx6=c_#igbD?z?aQPwt$ZoxbIJ z-$lfgPHVZfR7sQD?zp{PuU~S>C9Pg(dTtu#Y2CVwg=;^4=s>I8J3BZ3!#i$2eB?+R zrPJqT2L=Y6^S9rA+jB>rjicmCU;2-0uDiC|&L+>E>*qzk?}#bltWm8pa_DIC2%-=n zccdG~^%qY~-+E~FndgpAojyH2T(2hhqaW`tvfO*ktp!vB*|zh%!NJD1E!*midJ-ki zK6CiU(W74E)*s#Fy-RDA!DdrAT5RXv{oy^I{L~lXI2F)VyPfrVacrzW-}a83JoWB( z|2B&6=lS=4aCdCj7J0YVst#@?6W@C49n0;NBu<)*=J4o9zsS#>oAH2YyD@nVwcFkc51BZQ*NzSU&7b}c2k?h~^0!&h zKkvLLEi=7kQop!3W|g#VgRVtD`q9~ zB1TuKS{gFr0EDPO-UFa0Iz&Y@06rDXitbiS&r4XnM`A<}@ zz+u=zPz>l(RduRy6shxu7!BtJhDI7*ZQkn?KJx(1*@zJxAh7ouM+QWQh>@%>qm0g@ zsyJT&ncNkmDk=(&D9XCaaq5W+(X7*5$g=+O;$o5}oN~1>xU{^~&w62%R;$;BMn)DF zmxw7cQP|>J=ZL7$XmmQAEXylt1SsA~npASM7%`I6Dlr;FbczCKYL#j~>le1*686pn zh~&$JDkykmA}d}6%GbX4(_LFP4iBt(>goT()Om(kc2#G3 zt+n?FH`lGyRh_%lEwx&$(A~-bWsxm`$Z0&|F$@M{590wmHXefU0|VG#6Abo@j7=1h z03iulNGPM+>YP(`Rd?ld)4AvDz1Nx_`;_ed(Ld^`=c#+E&fR;3?|Z+4VKGY6Bnl%Y zF~&Uk+)iDneB+1r_x6F|hf5`nT$Ln}$Ng|eORRn!HNdO9v z{g#Z7T<(SP!H(h?h+1m~76+(MmTEKyAb_IKi2yrqxArhOBE@VmcV*|I8AKt{jzMes z*0;VpK0Y#b=FGZNU$UfNsVF*bS{H3k&s<1td;1Q0W8SR@DnVZ&?#tyQ2|Y&UHT z4#s!B?lrm)0o(f@cxJZM4yyxk968IzIi+&Ij1P_#5-|*5n`v_Xxx-g(-MI0b&3g_V z`N_Qx^z|=SK_p0|#TrvA7N;BSsp-j~;pM_?js5ahzH5=o3#o1}%5x zWtYC;4Y$tCHF|1&PdxF&i z&P>KZ5Cu9D7X;cm*J(DBG%c!d-_iZAeD#11!a^M1a^ri>-MF%wSP=xrguv{yR^?I< zhTtqPLzcm%mu_N#%m67s1zG_Dbh{7)@X|~B_8!=$t?6_+%uXq6HClx@MnLNvGlyXi z2Z1q0SfaQX6$(GP_rZ3j6UEhHdC-Y#yP!M0*jSt^6e7oBt#!twY4@tDub!Ws|K_*9 z(^IXM%jLd${q1+&`S5RELV(M!xZ=4NpYsUgD2hBSFDewI(RgLgo@=kYcI(#d-}%mW zre|g`pfh9Rb2D?#JoohG3od9hS|cY;RmvqmOtVyLEdpt`yRf)mohua!%#?H*3{WV< zfzl!jgi7fs2>d+J0?apOonvrNj7!y8xmYY1$IcoRX=4ntE0u~`p&&YOKmbI*!fr|F zK~SpH2BLw%-oYOqx<`l#aolXRYPDJ%g@}1><-6bW?z!2S-oARHu`oL``|{3Lo_hM( zcB`!wsz4P2bk@#HPl?FuUiZ3V$BqM7Yb-)wGE=FPhlbaUoF2hUSPbPxNr7B8=Of-6 zV4iZOF!Z5;B7~SLUtuY$#5t=}m=8hz177fa9=`wpAOJ~3K~%vx3jo$x1XL=};!#?J zz@ia-*MbD3MHoa7NsHKgNGnVP4v2-dkD+BzL}`|SOY6PmiHWg+zIqsxvn(Y=NFgv; z1|-y4tmy*94nUmm*E1bxE41XzU;rWvI9E6VLK%geUobOU>lh*+WQUn`LJGC=I4?gx z5hCy$4nSp*NIS49-`acX1}YU;iYyj_0%H~kXoy5>L1a?oOsWZ$3VbioO^%^Q7?CBqj%RNXMpkC?eJvnyv<(H408Jne`NEjgMLaBxnDFqV~6B83t z*0Hs&Tqq)nwKnN?J4sS0m69Z>RI82AQ4p&GWvyivW{!i%&kQ0Ua2yl@am|Is;(V*! z?MfjkhkgC{l_Pg-T;PYcyM(P$@)2(or#1gpF3q zGJ^u+tcb8k97nz;@sG~G|4&4If{+_bgpe5h3djpPSe!%BUP@xwWZm}JGZPQo{|G=Z z+iWpPwOS06w(RB?W)|jW*Q{9n@S{(UojEf*HB&AYdItxyG-W3`3;}=ubr=yM31z8K zibyM;J%~!200DtU01LUC(%W8S$v#XjpIr-}cQe1rltTs|bPVVX#2(Y1FDkqd4jnsT zQT}*XYRdgDM57kSp`XME;5mvwew|B1j6@{PApsx>v!|$er7Y)Nc|I$CmBgj!Rh6y! zk2dRk!b7AE$e{9I@(%#wct5D=(WeNDKu!dh|x0ssoL4-)`(&PPgn^C0AbM@Zm6 zi1WFQ07I+Q`0PJ^{ems)8w>64eedpxv!_4znZFc})VWeInxE@5+ij%~2z1o5G2IQtByr5uO7CaO~$_ zfC`b2taTa{0uUerrdeavvfBIKctu-8*Fr^vVACwMEP(E%7hlX+2$aigT!`-Z z$xny-2Y&bT^ToK3wp!O;d(AsnZ@Rvlv{$dJ?c2F`^w$2Vf}_? zt24KFC=A0;M}g9nYNeYbS6y+{wbxuTK7RK7zyF`>_1fr}(PPJtb(6#u$V(4}|*S+Ry z5q|Q?r-z4^^_{!!?AV!w#YLr6zM8d0DOHHW`PrFmTP}FdyWc%IJ-hClbzk}F-yb`6 ztXwXmfLNQQsQ@IM4k7l`>!;6*MPaB=0YFp?lTI=>H&-sknRR{ry%(OhA&%gZOShi9 zZv+UfNE`%lA+Gntej;6nB8`|d+cwRHhKGlS$J_08r=1=>ex$kBC>0Caw_ea{w@;op z`HpwIqo=3VZZ(w(nQ?G%Xydt?06?p7-@XIJI8-1aT6tl8&cSjlK6Y8DPzQm{tONG? zMD)rPK&{ZRfGEc{hzl&n>jHc@t+m#lSO_T0ngql-B%+*;1mcss11 z0iciHWsVU80WsWFpfD(*pks8Tg19Icb+eY%TCq1)gYkildDG)E%S`AQyWS!qAWovg zC+AL2b~mi)*OBcsGrv~sBpu-6PdZ%8k7}U=^v*+gzJ&`QhVyR+-5R4Pya|3ZQEs06g~3D zZ{}v_qBy$Yh8u|V{(bw8pE#a$T5o*Qn>KDZ=ZPmC8yg>AwQAMnmtT6%J@?h5*4NkT z1EqwWN!qq`x~J?`tzZ7)o-+&0cD=u!t#XLsm@Eo{ih^RX&}=mTgsme0jnZi^a>__r z2s>G(SP0p#0*x`LIHgFD5&Ow@0og!kd5c4HY9wRC`9|C~*feI)_5N3q{ zLV^lK035q~R3VZ}=)n&J8GLN$(hJDNygnA)=UjM*oUgb*fC>F1ap^=rBw#Tl2tW?R zFUNc!x_}U%uvLga+Pmk-vl@}eOJkS`^5}72tNG$ggqibRhX4aq0^pnpLUE2)tzKRN zDD{-iJ#W*&gNH4sLIDo$J`qMi(zR1_?Q*pTK}aRLcI}G7NI{M=^2Q_u1d#97DBnPP z1rcc^3(hau#CyZMWC|o8Pc2f8#rHSDj*v-3%tAUEotWQs@KlnvR1gjf#O+p_h=Wpi z<<&Pn_SBxk2M!MoEEA!)Tm+?*QX(Qstn(%^jCBMcpp|7nB4=DRE@oLb?WWa2p|EZX zq)mtl<}7gdsmO0|JflWI|H92Ej@W2^Vp=U_2yW`k9_`P!>yCr3f4zW#zDEr@{* zQTdq=MTIcP`1I)Lb=SV;?eBWmj^F&|nWvr@TE4umx33t7aS)d3^<&3R-T&*I&33b| zcX0W#!L-w^S4ut0`a4Ny?t zztQa`fAS}P((R_Gc=_I(I@){mVNT$pZN1n|K+0(Kf3wCEf;OM==hPtjdr^d#|{8d z5nz^@Ac`)#{4zlGyBD8xY=VexzWMrf8&^L6{pTNi;K4BTNqHh7p^l9;fE;S2l?sBO z-Dn0;CSl?VUdkAL~(^SjrtUw7cp z0YwxjZA>;hH%F-AC_HiEL>LA2zA6Zmi$%p?yC$>d>Z`9zlVoCY`oashB;BO1r+)C@ z!GlK*8EfJ~K`USI1twM! z&ll!LhnEjmd#jyR2L+8y7Zw+n4GjFvXFfi0c6Rl$wUvPqf`nn1S}RDEQf1=o*^4f@ zaCmt6fqe%yZaOy#VrNacT1t{+YHF%lF7@=(T8oWxt>=a3Uzwg=uxuNP9miNK#=U)E zsZp&?96DV+Z90o z#Uj1+-nrR@HLKSdW1Ee|QlYebXo!@Wo1dGRnJt$}f|Q@u0!ouofn=EoTjKyxkzyYs zn0I}`0*bVsd^0mCuNG99wFvo9s7WcMoM8gk<3S=4VN!u(2O^|38^(}X06k9xi$DrI4Gh>K6DW3!D7@6f z0%-C3ED4=hAreOnh(s2&l~7ZdnT$1p*T?|)W|9P*(nyYky{VE|#IcSFI!q5AJofp& zIk0Z+@MV`>dSKs?ZYw)GIhmyMJr#W8O_yGOV76h!ORt$X&l=dv_iwrpr{aA4)i760~cKUg`mYVF!} z8_(Tv?8NbMp%}(GWfy=HRO3A#c>Qg+Tv_cOK6R@7$Um~0`xKnVx<%zncO`> znv|bL5RnpL$}v1kQw>H`h$O&qp`ghpaO520AdGLh^|cmY%c^B--}Q#Ev8;a}j3Uso zx`;pk*S_ZJ`MHI4YX(DrPyg{BG~4|1U;c7%a8MW#9D-yB0SkKSJfeswB4D5U2h0wH za~-Ro^RPk8CzKx9BA$Ta%_^V-z#%IpA|)Ws!%Dm%4iK5Wz}17sl=4VZAqE8^Y;$ry zpm9zR2vPa+2So`85qjpK2qOq6h2R`0f*gdnlrZ2gX5WH15+7_q#Nrsd7#%TB-T`t5 zfug`qw>)M>@{tx%An5-d2;P|tpuHKK{i+KUTOb8O04QFsPrx8blNj+RX9dX4iGqv` zAZj2HRHUt7=%rwYh`Qc8@Xc@jKWlkzc7A?-uG?+@;fFqa{q@(s{PHW46O(=Y{j<#^ zGh8YZCgqf zP=E+n5oor8h+!dWwi|cfd+*5U(^j}vF1H%ZO0|a(U*7fdMHgKXLi~yjB z+09H&7fNM`f{X+q14Wjt`%mnjtLb|5XEttr3(x57o305ZMVJl;T^xeblbMA z7jEe$Z6_v3o{C8jJ6G%Nsxbrym>}n=Zt9 zc&Pr#&wlfXC!Z@-i$qEzDa3W>tRt;vW@c;E>WeSDoTM2DD$<(Z@Trj}pM1JfE}cAe z!emw~hg!GW?Q*65r7wK8j4(C7SgzOJbmzNY+;{fApWpw`gAcv^ZEt)3e|m2a>PLR_ zNT|c@7jNx!60w%Mpo>Kii-=(uWR{zqWW%O&cRc=>j%3-g{_R`0x0-g@vLWlTN?1Td zBo0)70)@yWMn|6R}h&XOI=6u)l9$p<$BD zWtIy9?QR0|^Ma^UK!76H>a@Denb+NPf~b&XsWsUjedI%@ zPoKH}=f6b8TW`Ka2kOgT`tsb|T(#a~O_p?wb1dTgq_fqUX|`Ma{r%l;mlYUxItYII z=o4?d{nkq^I(JUs*=L`fn4DqYlOv}#1{!a?8NC?<4DFi@82uyjJn21tJz&Sw$3IViM&Oy>meD`J@J8|0200m!V zUC@%a7Coi~Kv44Y5kx#)+uO1M*g|gpjKV7Tg+7WVLIlf<00a!=H8=(Vv_flbZodFz zV9!TKl+;+i3bWP{l4B5O$)`Cog<~dfwhhq3<%H? z_dK%>90*wFR1kDc+U}U+qq7^&4|Hkh;YS_}P*;lNL_hk>;enymH{JMq?4a9ihdKgO zrAk>qj*pDr^}}B;cH&CCWTB0!s0y4U?a8@BLz+5Uu9U1b);T8-Mv;z!KnEb0cDn=p z1BF86zI*QrwZ8oF%eP#3;kxzfeth>&_U+wYtJOAd-n?nkrr-Yd(I^UUxZ%dWzTRa+ zg8(=@H0)5O$0sXL?5R{k>=r_I*`=GS{e7l2v3Biw+qQ0gZujx3t}_d19jH(dF)$HD zQA9+Fln%lI!ra2#B^O`zwzpnqx^EGveBmoUyzf`9)Owd$VPH`RsFW9gvRB)(0D7x3 zuybaq-Oq<``7#3i$j(>C{voo?C=8V%CyuRU;{r{)_8;6$`kuRgMMO!b9mjFCS`Z_k zvC~P$Mn?wvdcXS3A00e&cw}TGF=?${YqpvN<(Wl7j)e$CmNXyWH<LXa5D=*l!tu$;xrK#d zu^0+YPR)ja4uXgjKK|6xhmIaoiW&-)NZzFg>ZcO^opVS)~y#k_4IS-1du5RO6BtN zFFwC#@9szk(^Jz24<59@J=LD+so5X?@JC8fUvCcpojftZYzu`r2o;hR#L@AEp2*G4 z&T~}!>3zQ`_N;8RTA*NZZd!$?bWpBTv{t7^PH(yB!ZmBxo*g+Euu}-mS^;s)TB&li zVjV|>vvYIb_~ti0{NFyDn3Mq&`D_C))&PQGM~G1n5n-sP(`sy7zxKMTuR40{#HCkU ze&qPE@7?viayh#8sw=i_-Cm5;rVB3m;72}|I_~Wqc;LaG?fBLGSHI@Q*Ic!I=PP^O z|NamB@Sb~sC{UWLQK)sGyA}qPoim@5%C%(!8_S(kYRgx&oStho&fj!?sa&mAsylb> zT(Nw`MccO3d;40=76>{EyZ7!J868``Yv1@&6x^I!SL zcG6}mBgaqaDD+7z4p;|4(&->zT!^zocJAJ-19kY&kVUtf-aC$kwtr=O$;S zqA zGbRYaEXf3zD34r?qu4o@W!d4whp)f!hB%5%miYq}5eak7FCqbWiJqXM+`x?aELnI7 zH4gc-RfG{im;)6!=Kvs#B2R_TAmBrfnQ$pb$bW?ZofCE<3N$+B-JK#HC=LR^i>T0``a(Qr;Z-{?ISM?E$>^sdg#>Y<5Sa<%ZHW+f%cwQb`0W?4*~d1 zqfbo(e044efROuXWNF;O9tn^?LIMKfoKPND2!xn};aCXKd9lZmUC2v3LA<2dVxG*H zhu?WUh>xuBOGs3RIsMrR2rT9LAR@CMfdxSjC5)*3^2%>^FyFwT5@ZAx_V9cwf*>l7 zOUzeYe$2rj3TSB|=7l^SWrSj__V1b?f0+Ud&ZmlsI70Ndz9JG9A7q&y8H#-Jvty@3 z<(-RH;CiJDf(W*|Ne~3z`t}z}0040G%*^LM|Hc3FrN0UQF4%nT@_MO}!4+3r85eYt zLa7J(hgSZNKl?;ay`EzlG%+($P%0MZ8jEvtvkI_Y?_pm(h-e*Vna#3pnr1{4mkL1; zDAFp|P0P}6A9B(q3J6$sjb=kDEr5%SR+^<+2QzcCl}fd@-rH!jMoy1fo26ZYL{Svi zD%D(WotqRuDFp;XXfl`cbqEnq2T>FcK7U~D-5>hfC=4@WO=ff<2y|eKX|~&jofd+C zoO7*q#?BRnhg+SdKxn1UhW z{(gUb<*vPB|NPy%2r*DfDeV|ogspU%i3uzKY8`1MN+613V=NLzQ7D31YilziFj<#G zOvnA?M|XepgC8iAtmWXDXI{MHZ5y_1KCf0Uu3Ei@Ef{0V)#{ENJ05@LnNNM{lb2m_ zmumimu##$pa5PeAAt8{?G^BasPu4 zyzULRz4cAE{?W(&Y}1yF%YV1*%-JanDF`Bkp+NZj&O;+dk3Y8S%y}1YU6`2(wKgxF z965RF(2=8CFS!JDXpBRIpa0^%hkyHMl4fVmjP>>Px4UUiwR-04_{rlZqcC7LQCJ*3 zJ-Th%*0lr`t`dwd$JHtM=_b zP>f6EVtMWQb&bZtp(97$_SV}!@cwtMtf^0b?FT>n(LIWYg;Q$+My>Sx!u-taOi#6T z;g-#Bzw@T~#T!S?Onvgt|EgRrmrAACg@r;PPO`MoY=8Je|HD|Dv{T=%bec(q{PfdL zAKrhU(P%VVEoT1qcfK12y0=zaSeR#aaiJJQG@VsgRPXnc& zl)yEp2bxl_O5G4vV1-lSalwzHBtO;8bpU0l?=>a3sL_W8B~;QimQam4@1UW@PjwQU z$k{?1$v8}pRYG*H_W_?A7o`j&L0M|6fjB|Wt^?h>&`F5VQv*LKBOdkOLup62;0bk? z#|$h)KCD;}|BDFk&!8Bc?En{czcV5PLvPs z7plVsCX7KLjvdvuPEuk-$Q9s8-1;U5jr~!!V&z2~K|~i$AYaGI1(hgX882ZWZXz)W zm>&L}23T=@NM+u&XXjl3&4KOWhFk=}&z^Nf@>VsV%cDvKl+>POc-eT3G}YE4cN&nuO+GOeOshRi=?= zsf$xi9a?&a$hsJUq-Awi$6rC4TQn?4@xAw7XG-07%R*S*gK4a;hbMW1&6e-@y7IRfQ-s0MgsK`OSNi(W7}B;6u9q;Xr_ z8W}=;sgBV663?D90WoiU_=PF)I*=loF$v1rfRRudIA!_b#>Gss>vz4*qM> z`hPe#B$ATps|X2uZzRAV1$N`qitPg;1ZKn-73jSihB$+jdDeH?KX&v~EN0?bd7}=v zDUK>U{hZi^f&cm+cpa9HCnkfu-qQx0k8T9bjKSNk`$U(PUf4E;2HvDwt*tV=$Ukl9EnX;)U$??(V%kAuiM}^1# z_|>6hh;j*j4ZfW)=jwc^9#vc2oL!8XW3SFo25_3N=@~mMS}plMo^o=vAVL_%?A3r) zozBsz$-I05QOUzA_fYZN`qt_`*$ekRWhaWu*Kzmq>ojh- zojU}ENf$TYM%$hJFLO5*Cmbu%0LQqds>lnpP2YdRe`CS1?Pb5PSF@;cMWGD5Q*g1E z-EanK7PzQwWd#1^4Nr(!^SLs@uPl^%=UH2=O;kc&svd(x2uZgS_7tXJ}Lp% zRegvsPg$5tfPM9xeU$4}W_$PbkXT0-Z{J;t*hA??&)I6+``+1wh1Wu0K0zrGw4Kdd z;Mkt(-Mf{~x8|o=u_n;y{Mta{Cx`1{s3t)gf)R%x*eKzDHM_kL_*lOct(w<&FMPOq zPB7G2SJu$iu&xQ{;Qm`78&)bO%%>L6X3J3glIor)(adqYU!{Ne6tF;Q5wB-xc%>_z zX%!^;=Dz3`JjX`}>CtQ1n<@gCkN_x+HxRwtuEKzcU(!en zRSOg4K;exu?FBO<(8|!6Bj8%A|23oBjCtB!*m;v%xQU62Udk^cN$;G+p`qb+H_*dbE`SA#M@V>jIh%&YDvav^&Q~W6^g&Yh_ny&s13E0M1=*?6-ek^RCbSxzjU<_bfm7>16O4ZU|5#Q8{kmj0&SlMt*bJsEb4Pf;D(rH zF55eM!V9KZzRHCnWgF!=AKQ_{&99i5nEsO`*ejH7%?lK!@B!FJ2iELWzjHj)7A$)esnP zny?LTWcg7d-eQ3)qoMDnlONu;RBjDyw;m$QXIjlMDiI0BVwOVtcM=O$z|)6TA`JY4rZb~Y+0t01S;XR=3Q(>S#e zC((%gtL?Hq{L*mbTLr+taNat5q(agl844LacDO|Pc!UxYe~=N{9XkQ$bUhh0bxg^h zdBv}<4SjdBRcXxaPHR9`v*2EpIJ8Og5ov->~(ZpsG$5N&}Ia>IvPTVL00bH*8AmL(XZBXIqdaVGWefC_8tX z;|{}XR0>FusQ3(yy;dlxax1a1_(({|$-2)r74ubYkCuMx*WsY}Rg1juZhqZ6*Yr-e zclf_49*LZtxQYNusK!SgJFgdC2a|R0r+EXX0%4(Eiy$FMBk7E#`Bvqwl&LH;?Y>8hWmQ|M@-bQ>7`x5+x(IYguRgU}saI;S;P>AxLr9 zw?`t4gkN9^1eovNeW)9c=l$YVJf|Q3gI_-9E%O==K-C$yND_Iu+fqevSyqX9^qUz2 zg+P?RbL*Y+v2TQiW+3jjPfrr}_s=nv>Bf#c?-rYPfG7%<7A?z9DWLt_cn_pfO}fms zUXakF>Rz7Si?-R#EbF&DEHWfn6ghR@M?p$0UfmY@@V~GAkSxX}u*3D3_z$LDnTMi$ zaFiVx_;`CN*68f!h6vNC)9*09A9?95&}3FsPD~E-LfTIV;;+;Y1jq`ssZf=|}bU@-ZB;)`$rnZRUWLcFEdbb~-%FtvOsi9NljS>emT5%=ty(OWEHb}!*r;#65>l>lq)=)r1 zL=kfQ_8)0W;z<Hcn)b5x|S(1`wm99g+|Mh@bvR)rRh zcb}aDk3ZeMULb5Wn;VV{kZpm=%C;n%K2B>}aHo;wMk_9Ig0Ubm;9L!^cbRd*J6V*7 z17=xdX=QrZbx4ixFcFna2bwGNQzU_68xi9IOx83Q8^e$8As%6rtM_#TKFz|tmM#(E zV(D=Os{jl*=5qMS^A2Xx%Sq+@w?(^x>?|#P17s*h>9F9T6~6I%1eUNpWaOA>gUPnW z2(~jBLwZY7uOg&ROJa^e1oAo@`1+q?EhaliIFA9AUPI9F*xomcFvIG zXRkcw+rp)K`uz8owq#Y6mGX@I*Q1K9e$ESSKcx`k+6Y{=^KjA&;IStfp75O)kei

*(T4Sk8KA7e={98TYKO|Jh6?0=Zrp-3ub#|<9# ziBr-xZcE~d-DAmR$;X5evHlZ&!t956i@$G^$dU?#MG~=o*WE|Lr$q?EZoNE}bQ4bZ zbaLA~dVSfJJrv1U>bP&&f>fv`t^18C1K7xQ;5kwF}FLmQ=pEQJGz)y;!C+(_5kiXc7mZImIdxt$%k|i$WowesnRT>+ zLkTCavL)Xkp_6Z0<;M#fjn4)CG|#|h3PJ?B2lr<|Ytu~*?Xr&%(ip&WN{;17FyEuN zsR#%-r@UsA+mWM6SpR8V5%6c!P3ZgqI283-Be=E>(yXn6YNRDm%mqGA+rz(KzK5Pe2+}mSguI?Qb*h-<;fpC! z5=AlMi>zOsd#q>1*f+WoDPYg@-n|0d*I0e+1QUf=I?sRJ*nHiRFp%pv>a1k%M|Btc@w4+cQUKQnuOX@@;Z>>_mI zajWlcPzvX{Q;SVj{U4<8vBu=-;zgX~;QGO6<8eXP*w^Y31&*9z@2x-j87EquhnF|- zVB4o=20dJj^(}PV>u}Y5KJcWaurfWYbVx->rC?fuGMS0qlxMI=H>(&NHu_EDUH!+7 z)NJNK=8+7Iu9XvO)|guT9zo@ln7lqZQ};dG!%f5`mF zy<*EW<=&wMF|pS~BNq}9(#re3qoXCr`<}Bu{ePR09&a(ju+v{z?CP?zScD?tVrQty=2%;s%By1A1-5oqPQdWc_dp1W7!&s>>HDAt+rw z!{wr&Mr?B4R=g3`6F~HC*RMHUZcA(Z(7Zjx>8qLJk+!r%rkq1)4N@w~mSeS%>-Wtr z`(qpt9XdZqcG%1^HPLusj>brF8 z*HolMx$bWR;Sv2fLC+g&Va2LJ2Mp|)x2h@=Vh@Y%@O=M?PTrrJdGokLquv{VubPv> z*I)YX4ciC{M1`(pX&wijR_V>uu;{HZw;L2a<^|nY#LLjt>Cm~5nmsXkVidG`eQ{|m z@ep^ukkSHuyeamxL_Y+0OFp`M2>R02qI-$}dJIX#c6kBiAGTEg&jZYNcF4PV`P+<1 z6wrYXLNLFX{$|euN%MBbxtp~K-<>BO8~ukwFgkeHIna$Zu41XDy6oIvhq=gA9(=Sy z*x+p;)$xZ$tQ*Lj*_y2-Fqp97<#4=|1uw3ZRxvg&{^F ze)Bqh`1fzeE|W>#Kgj7_;+9U0cAZZ9rxoHzvrOyY>-|?F4&oj;5c4j9%>qL)B-6M>7)>9k_hDH@Z3juQOw^m z7a>o?B88hRdcq<-+hEPf5@lnOz+)3YHR1R`DE&I7yd_* z5)(-ZP=1oA-ySwG2)b@sf>S~BRk@3xyvdy76BqtH95nU+h#Hd7n`P;#qg{wuc)AqHcphKJ;-ZkflXQDkaAvc!rI`4{^!{?1pue2V{@cNn}L&3 z)bEI<_emA-kl=`2%$|t&U&y!{>HzYQhMEfE@V$n>Bi+8I$@W|S=VU_6X*MXR)AG@Z zS(Uo$?~{8pDBsKBd~dpzWw*TIgJa%OqgiqNQM__)&+V2JKqFSJpRt?*l0W+JaJJEuYF`7SMb)OGGyg_m4fTPG%D*f;avewZpfo0%|Q zU$Rw#QCGpKN2hP;VzX}?>(P2kE|poo@Z>lM4Ao`?bW7vIbH%%}%9(1a>RADQNMkB( zTeI>J5VGBC%hv$K+VKNDLF41e>&wn(Cjhi;Jrwh;voq-FuIcgQ@ntCZ+9Le>U!e7G zm{mC0JSL8-6smvx)twqt@BeEq_k;60*`E@9g<|7LB3?(GHSfe8mJ96(6FTch?G1fK zAaJk+c)bgnVoN;U^LS(IGyR|Y|NUi8(f}(R`i!jLQq?Gg$5*Z%rY!^|wd`uxMCz=P zPX6p_d55Y}wqB`RJh~Ys)Ea{+5roI7a@U#p^$48IfN871^A{OE3RHpzbKNASMM9BB z#?s-8mh;NF!--)VAs`oILNd~5(I$lbsS~(94y8}y`+&!VtkikC-&k#nVGHI8tCAwb zk5&qqeBP4r{P zlsK(V-J!F!?F`aDl0ihdG3M%LG~&&kkgOfDB2$Wwc`IR2Th|b+^JnN zQiCx|vc(qgg9-=Sxk$1DcesOtYGed8I4R!m5LmNtl2y;AL%p7$)5R*ynrHPCtMx9d z#`>}WT>es^Zc?%3$s{cDelz0|fd$)$Ig) zuto5j*;h!r83ja1RU&E%6%^wA{3Mi^FX%gml8gQ~Z2Z!>dq=rFcx!@#-Gy763*X!t zU%P};BSb5J*Y3Z1v(z?~aJkMs>AB=E=;x0oaxi6Nup=@?NWYv!

EwA{m2%J++qF z8LPilR==wyjGaD$dN$P(;nmwHjp=2ZqA832O6==GHQkq1OeIn$FF`U(Q(LU89Ga~% zEv1>w7=*t(4!SNsR#d;)6!5#uRzy)jWm)WhvtC$yEI=r;tdY!`_1`L0|qY@BUkzUO%V zcJi&G&t?@3zWc60G!B(a#8S4NEH$lmdYD|REf+Md(H-v2B)Eq&;#+ z`LyG(Uh(~kC?jW+@FaAggK?G{l*+nS_FqIyGl#_x8V=RdrE2i*1BLOv`v!~t5J^(- zY3Ql06^rcFT9>zp`?zO}*XA8eB6u&bxN4DzwQW|}V+Z#wMy1u51h0L1L8H4}AG-DP zzpQ|H4^g}W&DumW)_ zs(30{eG1$eckYdx3cMA%1tL8_8%1~& zqMAtB50&H$Jnv5-!J(wvbn5D|nS3X{ke%(d-j*vsnr@}Hy`=rVYcmw>q=ghD{=1Ys zwgeqND=H&nu9{8iE!%vKa8G%WBRdpnKbRsI-Xwd?CAzSr5VjhoD$ zL!U<~-}m1ANhk#ng$lj|^f@^>OC9bDMz;Z5ua60@e-WSvZ{*un_G2SujIZVwY^=+p z=Z5oMe{8(|%-y(}U%Jl*rqu_x3-dY)^A9~FH+|cAilQw#>v#Xsl6oFRaNdupdJ7$^ z)U2H1WCi+J3P$@p%tpkFTmPILFmLEP$ulr9?mH`q`@k`FD)!B}ZUK`^ZfeY?1f5<6 zBwjroW`l-`9D*oUj{ipZKb7i_BO;tBTEK4%mt)ZHTW`?80KTu+dR=Y(JI9Z>DLO6J z9g{)5e0$dqB3$lAX`Q*0HI53V<2qXt4Qtol!RLGq&vTgX_=E3fn`gK7_p5YTT-Q5n z0*^KVJ%0Weyk37e-x}(>uX7eX3x9-7(S@?6;=39R@xQ}4+UWDWwARM-{A52~A_2`r z#1Sjd{X6t<4xLxtg>rJ@@*mf0H_Bf^*hn=~@r2`+_rpm9yqFFK2I%}IwBDA4;!#xE zK|M2F?#fLEV0j6D9nH~|h>5j0U0^#=ncxf9CE=gB+~IeE)6S`!&;itG@o5%mA(WC> zL^bj*Q^benh<+8hHxL3%b7oNWK^!Wr$l2fLE`W*Tv0URI^4|xkxhy(GLFydqJfu*` zv1BL_Rag$+7)&``T>eeTJfZ%(_MFidm&UJ7paO35w2!QE6#{cCovVyAL>VC(ylJTF zY82Sf-x)7`M|M8%eAEWF6yK~Qtn$XPuxXQ(MBx6R(;IK*a1i8sr+6w?;&-Do;m=2o z1!K`qCnfEVf%7?Hu~j;9b5#Amh^!`p1pJKTSZfQdOiv@eSYk-swI5_=rcQ-VhDZ&_vYN|+rs>IY z!!Cad1Cf@A{_p#W9;u8fgEfRI4C2<^TPLSuN~%<%KHFz048Z#)$SG)*0y&}o4p89K z)dNdjOF|FNFBiYRR8af7d0CgwI7PX_px+Vcx%hdc3z<_Xs!`Ah_%Ga3KCz z@V$IwASdhrCRLMK>0wR}b{rVSV8cMRMaF}HmZl8-oGW}qVMMXwQG}d=R-7(Sd)kOH z8F55(YKL+R$D*hKTT(nMyJjN9nTQ>6BxDIGDME2%6kho{G;&J+pOwVp!i8Tw$>cgu zKpIpbWaXD3xK00AhIG*Az9A)57yLzEV#gzH8dF}`9~EnjoK7w>Hb8GG$j~Scl2QY? zna0XYbe!9I-0e+&cd5jGT_AapS1L)DUbpqG0JLsTdmT2Y&#o0~q868A(k(=6ivS-F zB6fQ}FuGm6 zZrJErD5Xe@vdL@06PGRh!((QZx*uBt7LpxPAK)TM2-qk_^1nUSB?7r9jmubAed<}V zFYX5#uht=lJ=ZEV9dUtq9XpI_Q1j;NnIB7`PTIfC)jNI?At}x=sef2x-!8!G@+={xVcPAn^6Kx$Tbp z7M-Aw(RP!k_j}Ttw!*-ox`iM01zgSd=i6VezK+A6=1iWi8-k9u3_dsonJoam z+@Jp=$YoUM%v1YbH8ocomg?zh>uGZh5L9GNF)}z?oBv3=GpBz`3m}7sc0P^^cX5nr za}2my`^k(0g#al(dvh!sXf!!nPn?;UA1RUslS57pI)MyU*9wc$;vN`_Z3K2lPFF8C zt|tr}Qd|WldNw+b$8>6jFP}0NdVs5gNRQQFCdFjuzq{WSo_d)(Q~pWuQ3uKLxEz^3 zr|)%*?!V)7-@<4_&+Ghq)fHU^D2R!%4oD9nADk)=NBn#Deq81z09f}u3m{dSRgf#- zx=C1!Baxb7dOo~4axwCa4Oo4UrmW~tH3dgy3BR~>G7*xF{}DsNSD_z5#TdjIb0n}c zzyeLzz;Y~mK_S2WQTopZt`sn2>_NDAoK{?K;_1j~Lt^Mt5R%C>QpMHOnCMWDxKRnk z1p@t~PI0xE>zuRjOLES1Fia~Y(h$>7bhzbOF|8aUZ=1Umu@HO!^B2y|L)ga57< zj04sM;2-x?+mFINQ2_p(zN0fQ=5|jk5?PQgs<+VGEORQ4jsZ+%+A&~HX+mb zDLje!S(_fUf8stJ9YHE`FFjid>Ra3oU!E19bq!mBZ~p39m>UK)m1VsAM}`y-408L?<@ z3IWlj9dez28sKbY^<~W|Zs5iAo0$_`#MI$+)^7p8NA-Ne_uAIp3#bO-I2`y^o+UQ0 zIKKcpP8fdkq#PNpFpx%kN;dBtDmUWrKzdQCz0`LN=@QPSY*X_K3MLLnNJ%y`D&#*- z-ool&IlKg95M9+;L>cjTI$pkDmUt{k4IPF%8<8A8JH}r;tyY3S;Fh{Bo(9)JPv&@= z7J}~(`X)VeyVV_y+57uIQaj8Hi+L`dUcpp;SxGi)`xJrGJBKWHL^1rA$5XBv2yd>x zSoM@4npB#JfeO@=%Nb7h-{a;$K{+~8RWvb4!|QK~;6t&OK^xI$lG`A7*UHxd`E*Mh zjRc8nl8x6FfN)YTwx?Un^9!io>uPJ$t$Msqn~s1gHA3@{#P|$9dRJl*S}X)^$vPjJGEHOKf7+COAI2RlmO)1TswHD5PVg^bW{!o6 zzQmn6W&n9ixQq0QEzwwddrru{`!J~l1Cj(*RG8fULnGs~VXT%8NlCLk#2QWhDpJ(mvc`S<0|tI*;qPt0f4nZF&bi@=c05P$1C$ zaN+5Ed8iRy%3XhQhZ_d%2S2IOIDg31+db&iNm=N*(RL0z1hx`;O`iIJg{79chXH2M z^Oe5a4bi*rIHI>t6Kj*l!d{yn3rG@V&Ie|M`d+sScCN4Aziurc6fHR|FafHpUZ3MO zU7VqRr?3AM(Qar09_vmGjZCDX=~J?CkBg(d#wN$7n|5e~ukIFly>1`H?iBrRPkeob z7=mB>oSnT_#Fjg3JOR#TQ1P1Gr{!)}-~Cydr|+lED_=kP+1qbLB^>K)4OD4LGtgj1 z_XIgRd6o0d=$Yu%Sx{zPbC?rK6PP<&_wP44QGZKJSltI_s zCo5$uK^WQh<3p(wSRsYt2*^gugn+}DyKw5yF%t4xB#Z7OkclAoo zOH|>J(m1Fe1#WV7R*EAFGx+Kx@*3t&LPCN=Eu4DKpmM7=uR`jSw6`)k8{#INbYqnTW?NlQ-uLEY_Z5P$}D6vBu$$`2m=2tU0atlVhV=>G@6; zP~rBMC8bUAaE)i(ofR|K{ad8L#^Z``8O?R_-3vw2)mc~+LZZM%^#s!m?q{rE{35kv3%JD^Rf|qc@@IbXWCnA#mXw{1NGzA zODDu=gbBjJ;*(#k!ka8JgPbCnO^R)=Q&hlQkUd>|iL z%IJM!m!#XtNLid+9z(#AjKItr5g#H_{81?%vtolXb5$62B8Td<`Aw5irER7tmGp-~ zl=yl|th9#gl?7t`uNZLETl{`u*SF_)f2zy`dT(+Z40YlMOG{ETchSX5KIHuJ5kB%L zZ|J@l0Tk^wy#VNOucXD~e#8OiIC%f7YEUO|Fv>t8Gq_Jb>+0ZDvBZ`FI@Z6x35I01 z)WO$(mY0(Xg8Vv#w72gsmfcEOqMn0@syUpIVF@xaO63&>6$mPiH$Ww}gV;>UU~q^h zp}7nc&wU~%!Mb9N<&aCR*(iLFvr>WEWul$6rd3B2vlagl7AuUSo-Ck}x3z!%xgu?FAOsmTq7CquD5b|j6VOrBjvKWCt78ex1PBtngJY_ys_lZGK(_6IJ#+u4+BZ5bf02l2l(JNwQHcfa zolTp(UcYii-M&2b^=;u1jZ*PpY|td=%=_bO1DDrMJ)+D^-Jn;T z7ndNXUTjytYX5(c@RpxIq&@gKQK%$BE!wMVX5Zr^_$>59>v1#g-N7vyaC5Je;tW3x zehnqLIqf-nx-2{r6QNE3s3m+H909v&!QZ-2T~|dWOW#MXcc8V z+#22vn8-7N@7<%0!DDhip}0=sT&ujk`94m|`-fF;$(pAr>w=0*4S_dWh5t8F&zHW$Oi)p5eA z2j1L02;!yFAN7p;fTX2ZTWc!bynbE%JLiHzF)v3~JG=d-%gKgAzfYgufc$F?ffn1R z)o<$GDXpNwcGW0IEgnu-1bQjg9_;?hKbUQ$6e9DDWh&%E!VtOiHg%Q9uA<67w)Vs6 zB{K2p^}$ecb7T*N;V7m9+lw+TZKi5oKexQHm){FtkX5)q(O_!{>FKF{ceYFj5(A?Y z3WArY`Vm-L>w9{<__@cN5LE4h^beLFA=P+VDWn>W1jCHwLtm=|m3&6P1EAd)m_WSL z^e~pIpLKP;6c5-OEV(Qtz3^x{_URGYvgjo$2% ztoDi|ZMY6igrgZ7_S!$%dZ_fZH^ckO<8Y|Ho#f~~RV2M`HUu1f{jxY2$5a|uOqk(n z6h>Zb19yOKcSjnbE&jeJv5h|v{Jp?F>X2{kZ|x^I>sjEhe)##Pbqj$sql{MM)s)-? zO$Zr3++0iQjb}1#$9r=sX(egO8CziM_`BbT@Tftd!7zW`Yc?}eSk^C2YpYY0)F4-IeQgVPa@TDgAj2nbXX$` zM(b=!ttXbWItRy?@}w$GFwa;s)^O+AjgMi%;NI|@hGs#PT;Iaw%&OxD^^7;{C<;qN zn)z}~!qaE*sS8BkV*)ikzP?wV2F2iWX29_J5n^((xWZ_Y$?YEQ)ri3TxCyw@c5X}| zJpW?KY4JLtmAT!R2+7}-tTtmgRj4LpOwqM0kc-m1l^>32h1x3ZvBw#*i(@%8X-j8m zv#M9snU`Fl5cwk#HIy$`%B;^sX87d_g8@b8E9_*mJOW;-!8z!Sn(9)BS{0ybad26s z0<=Wl?mq@<-MN&~A!J80ub0GzHQ%9yQ+<6AUNJt^*gbSCSdVwYKU+)j$D31%Bw6Rq zdz<=>?Y!^`$CYdY6^;geYg)F0~59Th6UT)2!NT>478 z0=WC-B{h~(?5e*hl%b52kqC!Sk6MWtsmd(a@XMT`cWm=mu71T5sQ+J4L-{-J(tnHY zyLmLaUq+u?gxSdJaKl3dByA!rk2FxK#Qo;bVS2Py98=I3Tv7olg>1=q`!*?5DA#`% zVTje0A;Z$sv`7lS5hG|rg-N7Se5RVJSuagF$=_I)mxE#g3j!pYD21$f2o-x=V6sXR z9i(ia7*|Pk(`dTP__eFCvx%gkFADr_+rxlFTG7E_G-6nMYyIzcDxs5y!TdQ>+S2J3 zRk6o}u2U>4UP|mtorMDb-G<8&%{c_nX~$#1ciV2)nca*w;{tg0XfoM%1U=4Um2nTF zc4G9sDWR6dJujtVAOpLA_R|8OI)ob%2md_A4 z2V`lCO$=;qS|IL;wzCE_*E$l&xTX4a_~G>DW2?0cGE8s&a9pTm0CQAe)LNT28dt({ z(aph*H{OD!{hQVu=sYJyF~FaHZw)OxgjZL)!DEF_Jp{9FZ3o5Ka;(T)F+}LI1e;BF zF9W=SZjypt2|S7PrRivWPbjj*4r}Z9*6*r!cGAMXC;vvGH(xqw&6YnPM`tc$2kmk! zAtZyb#-<3hdA?M7xMAll>ZeiW(UQu`NpQnbVw5Gs{|t>0s==t}=t|_&v~&7tg&DGA z86Ze>ZuZ2qxJtd1Qi-%4%PJN*Zuz)c!Wx}?6@hOEYB1EBN9L;&`^kp3+qt-5VW4D% zE$~MIT%l|d<&3cs32smPFmBQ;Mu!?1I#W&pF#6AIjB@S&qQtiYj6=MSt%Y2ux;42n zW>sp`Gr0IT|IJ)sTv>^T*I5HQXMRrssM%P&9Nj$rf1})9wy|8ulEm?qOeGUmdMR%PpU-VuT?Pl&{EZEb_4N*~V}(^O zIgoTcpIe-Lp0#xi&w&oAmNt;b4f68!wet#cva_?A#PkmWc9-*Wb6+EGpMOjkO$Kk( zcR}D3de(A>KVRw#L97@}3F)q6FdS9 zZ0hu7+bxxw13TC;*m%fzS?Is|)l%@oa?CkB{^FK4N*IMVajDy5nt$MI1(#2QL;s8= zB9~N=A!qYehr-Zhc*FI7!8@w?J;*Jstj5Iw&_nx4=hjN$eViC@sR2L&5ys+fE~w;# zUqXq=XvDmZ9tywx`^_B8I6~AvkK*{%!0&>PuJ|KSX-sP@RtWSLq~NGwG9=twSKhOU9!K zzEaor-~7$o%(3Eq*8f|xB39;nt|8F#{LXy01@3iBjuqW=?(%i!dcA6ZlNvzc(;`Ab z*ckBs%+3;KA>v_h#}?!7*l$vyr-mwU{HG5p6Sq(Gnya2aduNXv-dRmvClil=6~>kW zgUW2Mlh7SL{9EkNcn0>8hP3$@X|uj;}S8=`{97bU&)j+?Q&6e{J5lOc0WF zOje6G3Z8}byd^!p6xFOa86Im@RKy-@&0wic%{f4EcMG=T9at6!-u;>|M64QkWI^*f zDAHc&{<75GyY(rdM11bVqk=EK@0{ZG7nVgO+E%eMVYnM3lIvL2cY|sSJonR*Y-#tA zEWy@f3=SxRua4xKKlVIJzI3yu7)=~Q3xziD27=6kQt*z!Dt zx4nOP-k=imviA&ZbPf6k8=|4Xemus0-G9Av(0UwxAGlp*Q}}$m@w`^(KWad{OYHPm z5xm|8j})F1Q8(I;e)(DWfjj}}5rJ=1ELn6ZwS1-(bywyOOuMV96SXWpi~;!EZ~ zQ=eZMx`4PfpY7klXA^)N+|vV@8)3oZ%F{m#+^2cHN4q_>^;$+fh?!5J9b~WXyy!Xg zAG(Qq7qIuQ;&rd@m9Y`m1aUuE+3 zZT(Sv|2QHRv_HH#E$scKkj_nsb~!x|n$R@C>K)G&F$ye)7eBsws{InXFBKCFy4a42 zymy}voDtASu+rmBDUpjmwq_q>i{MX@;*tLWwy!eKdfPc$u|vfvp_S#aRL*EI>rt;Y zkZuP>22Jx2G3wHR%p0ikiH=Ba)TxyJxudakeqm}$S!hlD(j2nl9T*g?)Z*lQiu5djf`?^CFy!GJ2 zw+$WV)nk}kmg`9L6cWuxS*TSA(ErFA2h_B`c(2l2B^__@iOf6?qiw*-{{~FEB>I~D zQ*v_lyMD{}^KP3VNzD6kO*QB+G+*1OGmH!!uLO)sDv?}SjW1O(NBMb6*nQnqkM(Z^ zDU*7Zo-zTPe-PIKG;7r5Ewt;@-qqb~$aB$sR?MWGV#>xUO*|Kmmz6Jvm0|5mY{4NF zU$j@LzCFPO@;l9L@$2#4+ne@Y^K+=`^f2FFy__@>b~Qhocjw*^_SrjIf)_rHcb#-R z>@4I3|C3%1Hqb_Bst=Ft-R#uGiY^s<9PR787CH4@8+YdK_PN?rd}p-C+1KbwH!4hu z-!dy99mB6Yt`5~2D6uF!>9-=vAC(^GcxzQ#9UewjgkKd3(a?f_ob!8@sQt1u{I+^F z>?rly8)3cA`1l|gGLj4m61YhtE-}9vHBDxnc2f{pdaSvYLs2e^1_>QkJy{JZjtGI3 zHotp2sPj)2UvAt6MR37{#&1$OGt$&fP@-Q@Mtqc;#y-P#T?p>WPhFxn?UW#8)t1a` zN~w!C);*e1v|-|I$d5+fMwZ>eqOU#e%hBv8T&)!uBN?yF0rA3?FNG=0kHvM9#w)Z< z*?x`sDIwFl#P)+F%GFe6gJW=uTusDRyXFuBWL;h{XUR#*ldG&=r)V~)Q$c!VkMuSt z8zB-``-`@vCsFiIb@lCIFaOtRBs(FXm?3%lu7Ka?POX3>f1gae)?$2pA+=VN7Nh^@ z!f~q{GW&O;tFPrTvPE}6MmF)CwXb!N+}`gBgF#CUO`gWLK$D;c9{KB6Y2tlbga2`P z=%YpMtHsfPTVoy^)+hz?ue6k+!2$C{KL?)7Jm&`{VN-oBl9$O2%6#=#lPrLw{ ztB~_oYTxaYf2LEmJhy;$%x1EHpBj|WZJiDuuR5~U z6d#0_feT|3*SXvtZjwTX16kuiCWi~grdktI1wQYHo{L?U%-QlNqT`p!NWgyQ74TgE z+zK4oQm=|Yzir$MT4K$&6j`X4*#f9CwBnyy$r0yIZzcpiY(MUCX9<>{OG#Q2fq8#KVW{HV;lsNHIPb4xoN-{h;5v{SL<78Z6$+ z>~6eF6m~sbTxP1=498Fcw1&ak?ne<-(Q_<1;2LMhm8IUkCV0ErQcmGA(E%SDo2a|? zpFCO3w#v?i4S#LLZMtttaTmc+}B$Wsm$RxR747F){CAc!nk#oPkCp0;5M&`Jzj445;TBa6MG zJJSS1Tfn~rL@?w_zB7n{PL%^>#lyp>EU-)K>3hun&VQ%vy~R|Jv({XOyQ6i197r2_ z0LBnyxS+)+lVgnkluq)ih`jdZ;mD}+pc)&BD;YS>>#q5>rL&^vyJ3ybmU4rE;b_p= zRExpHUU~-q&C!8J*f9VIu%R26o0|ioxRls|nXs&?59GfpDGhkctIhQ?Go*AgEOdR0 zcu%fBKLq!HM{rJ z!t_>o#}k}_mdhRPaMkWj=0pzajMifae%nZlv}u6is#?T&VpNf+ z8AF~d1!&wNYNx#*dWo3;dx;wW9REjK@{y2B63)du5T&L433vL$bJ%5x99Qr}xj?O= zs)CS+JAS}SjWq@xIdxZ+l`qCpZO87(u)vxpcJKcF-dn$MrLv_87@6jJg?2NBW%v}M zqN|$kOH?SO4<MTN$^9waCZws77&?#eClZFl0K30{b#Og8iUE8(3SdsHse`^;P=+ zvH-7W$_Pyi7C;f3nsZi$=BZ3N=Uu%JtT^c>-(!74C}*iW?+@Cuzkcu0>TWxhY^p1( z=TmuNrJVw1sVceYUIPJpIUc}SR4x;$3f%0eE)E`Js{BsN?vFt5UZEtW?Q@2ax6Q`7 zmYc1mudjy(fMjX?vlYvI=GFc)dC5u8jE;#C>i%WU(SEJ*Wb--nsiC{oF<_zT?CIwI z@cuWQ%*%|^^St+GC8Y@qQJG%B{?TSRFD4=~paBZV(N7jHtUoQ>K5hPP?YuUiKCEBX z=?C$#$Y6ff{xoGxkSu5JI@SjD0G^%j$Q?Vc$j_Ru=N+tg@xDwsPB>(|%Wn`epg;C3 zc?b=>oX@anNm5m&`vQuB_S4f{qvEJo6*VcQ6N*uQk( zD9i<5j=8!DecpWM)J8LV9dNs`V8grEEGL<^gxZ2~z{e9j33jbpD#Hkv`o67xsOA6! zp|h{{>PFS&gb^dUMSLKcyxGA5D-!yhxCl7LJMDNW)lGk2Uj)#zlS5q5QpJxDeB-TG<4goh#vi-6$Q=wBYLJ7K?ru4g=QevWQy;pwUGOOBix34}UDxL%R@o57F^mI#S zY_n#g3e^&zx>CI^MWFXo|B7z?JdK|ASJKnx`EyRk|RG)mW>dBYlOAe;h~?rb~YevvInbR`@tKdMKEuYoK#hNxtQ*>AU}5jHGnL z7wj)VQO7~DN=M(>B+(QLaFL}!$Z{EUoF8_C0U66Dcg0=~viLdkqqIsSW58?D^NX~= z6FVro@`lyPI~2q8hiAdhn_YlSw413=ej_G&ckltW=-71H`qB~bV0iy;AaM8j zfok=7Yh1bMwOLMnZotdS)%e_X%`It}4+E+LAH`I!%Er-%^DKL9#RgSA4=>PI^%>7E(tH?m-s#02CLX4{~oEbKU3P_)#4uMNAxdZV$$7|b`rid7V& zKzkJL%4-$y38nctk7*Magih$?#EDL=OgBT46#hDD;4m^^nZ2pQWx8dH{5EI%n&Xt+ zZ$P}F3;P=_x?-4`t;VO<;7H6I4N5yAw+>a=NDz43!$6a2B*Q_em+pL*Q*eco`R+`dQa7WX6xq>7TXq;0Kf% zZj^!MOngqh7)Q$T7Pd^vuMw*J*(ZYNqU7nls`ru&@AY}b&*2Ghwf(rc!h z2(w8>t(6|+2c8`D_e^mEE;8?n!Q)YT-m0$6m~?|c5Pt!x(l8xm1g!8M6Sf`^@jrobZ7h4L3jlncfT-zE6clBG}#{p}5-9f->?@X%k7uWIui+*2kXt%sOR3@n1iWQ)yz) zj_?hlb;bcK?_mM7lUPwX8QE7l0-zM9%MEr%jSkuders0~qIExi{u}q|IP$|^9DSF}8=`~bD(tcX3 zxBi0D6nNxG84~h`yD?zTAnYA z9TkW%EXLQ@#`Pgd|cv}8)=k>e-l*ce5zmr}5jYq`Q`1<|aM8M_9hW`#wbHB9T z2A)ixtW?A1j;t)R<6&3%&pU1}k1{V$jh#;;o!$>BMqa1yotnKL(2VX^RvcgUdcozi&vmE6ms(O$W2VJ{{Aq(g_o;}_Kf;w7@|7G8Z+cKN)pyj#CgO<&$J=*nJ0DdY*@ zR*-|~>3dTqvG7@ggH0H@yKr%LgK0QYNV(i)gH@+x@#S)$E?%qU_9JQb9tthjs~R`! zM?Nkocd+N`zY=Gs`|EYLI!Ct;f!bAubNVbf!k%1+>&1Uk1%?T_XaUD^6|CG1#_HBj_c!Ox?9^*1&z^4^{s{q)7i(chf_as8x6*t*l^QI{Tt!^NU?v0qRC|B>;Z=wUUTnxHyKH@c3kj+ z-fE?gk&-?vRQvC?*zsGV4B1}iRj5LJq(BzLB7jyA&qe?%5`K~=y;bGv#0TYpR=r=zrV%TzD@g{FWy z76qOok5D`tN>&lM(0u9AS$M-dpII@`{DU>qwJo{*ot?+a-viMF7uwgab%pTE(vCQH z;(SG-kR_;#qB(b>FNyIEb{=~U#Dzo6PsHiLB_1bakPuE?jZttA?ibGf3jIJetA){L zlYnD$_T(}?t#a*O(kSeTsWVINm5184*GC)f4ih0&0T>fj(@XYWzr#KCCu&cK-uWg< z>J7kq23}e-ds2?SFy#>nqZ0}pU5`|fr{ zh8yiGw*eELlCN+6j$R!RZ2xp03VBUpz*E;wnZUA8qwdI=o;x?!VD%DgKa3-};bFkV zptT1$zn=fdY-lj2Y8$x1WP2^Z?}q?J)F#&U6SkgrIEs(m#vVm`NP=|(NTS2phB>q?aW-ric( zmFnc47;vvd^U%7ELnIyQ6KIiyuzo`<>ZkkZo0HAaZlp=K@TLSix)F4fT}j%Yt?25! zf_ZdVx)8ZSi5V%}9Lp~tvdKXKGVz{zHB|KG)IX=mnJt?V89P!TsBW1lJ>5Z^xPy?% zj7h#^8l3!B6v#Br59afl#+JOLs7S9}Cop`R_+| zZQh&+WoKtS`Ceb;zm%-C-U?suXq>Iq9{{VlLgikQm;3Bdpx3QEp6|;1i9W}85T`i< z!&i(*6-{Y$%);Ev-#b9^orxX`oft);2Q$&l(M7@4QAdmTJriqXDy=cP{=#llF3PSQl^!fW@4-R@zFMW z%de#eNxUTa0xrzwjgGh`NuiV|I)DEf61|D&fBeDeV4w*^vDN7!^tHS5$3J`|)iz6Gl&$ zV*WRwcG?Dy&DH(~0223ZmU1DJakcHPuT|8U4r%qlNUYQRx;B2@^P?T7$4aHw>fho| zO`SG#L@J_zyUU*zSe({;$F5<%f4Z}sezvK~J{_+6Idxt;@KO8dk?6iXe z9t*sL|E(A`S*Vx$Eo)Wj=8a*#I&W-hv)Fh>Az{s0OZ6aO&uKc{>az*@G?LDZAYWj0 zsH4dSb|nPpr~Ok5Y2V(>p2U0v03gB%Cr0@U8)`At2)s!858ZeyE0uDr@@-d0c-;r* zfh5u(L?*Y{2};+ofB~g}LEZi+7bw>t*JTkDBw%3Rz)IPyj}4-4(s+v!)Le(%Sg+31 zjRa?4-v)_)O*qP0YW!g(3gT%PjS3Y6VNTwe=DFm_mjrX-p@X2VY?=Rs$Ka7!ql(&W zL&yINP7d#mJj*)wG%QdE`g>pPjRB39)*h(u4txA)mdF*WQ}gegA)?4vl*4R)_D@*<-mP{HpeB z!zn^2dd2y_rE+lp`%_*B>p?U7(vT#Kg!5i33eL&$>h!+1Rh#YPrqF9g|D?|7Nlw2G zxOa|-UKhz>CbN{$WJ;sRuh4LXZd>uK)n6FB9N2+GgKmRWUS`g%#~PuvsQOW#Hk{6m z+ji5kONNW$1CI+{?s};D6I&iMyc(JsmJjOdSH)g_ZPSaa-DlBGl9{Bg<1OoRq4`PGVytf zEwB$onqu{^&h5p~y)II^1O(4_G@@%?0}i;y-^=$HJzrdorJUH3mm2~ex>1xXf45eR zL5LV}Z8|j%GG|y>C1@uUtTaf?OwFd?^Q4GfP*7^pl0I1?@9S*;PD4iGy|KK7l%e@| zP%AIeOw~%uKT);!KmKXpC{;rqt9!r;PtKSIn0s#z2uFTk6)7I*q$6 zr9F{|lQo#Nt?OaZr}QoP#k#ZWvyCe{sh@woy#`3p#?!iWo@>44=Ut)rm96G$bL7>> zBEDNh`S<1w$&{jEP*Er^4^N7GQ8#3u)?z;JU`|_(i4AH7hw{spe%4Vx{2V+b-`Bg@ zd$AoX=h=O~M3T{s4XGfB*)l0MA+SJ1I4Wv@vws&q&O9JC(fiVT}D`*$+50kDcLR#Y(8U;?2VxvPYvwe0(DBB|NG6qHN#(eZRL=BVZqv5dHssNR+~Tsd`N z0Rstr(r*313EWt4;*SZ1VWbekVQ?+|TO{~LtOZn3?qO??17UlRv?Q4v(SLqTy?N!S z7hFqq`vU+4wa&5+dHfOtq5Bg?Wd?UJAx3+$dWcqZ)2QPt)@RElhl=441ejH>y)~>#fx^YJQmXw5+dh&)GJ7W>HpB61gAjk(8v1*t#a? zZ}h6aYmjfy%2i`g{3IX9bMf2D$YZX>qVsVql)ZgkFZ-K28-}n+bg)TR0$nh=D#M$! z9evF1BH6Y8eOUs#qRDn)KOf()0Ke{Q*UbGq*j~&C-|EwWO8ya*H!vqu zN7U_Yz224QjiIFvC_ekkt8MgD=@eLJSS@=0&urKBj@xUa{csD|3dbdbSgYG;Pmrmd znLaQj8zTsa&V%YvAriFxA0=2m>Dm-EZ;E3oI>+|Oe-)3g#*FK8h#yFtDw|qr_)+o^ z9aNQk^v50}$e&Hb&k~=+`QqL}HRsdv7xIb>NiIjpg+34iIl8q)Vd4TZ2L83;r z4lDeG0^-47Pp?69?H6oK|Hc7QwYIf!JY}S|1`Ui@T?&AH{;f^T+-QK7RwT4F*D>Wf zAO#7CC|G$+C|&Jvd+^!oC!#aX@mj`qrJ!>3C#KuN+XAnt!-?Ti_}4zMQsvn z`E@#gewELs6pju|4ye_u-n;=3>t<69fxhTg3TQDPcu`bi#Ho>H$r3dNGi-$6RhrD` zo8}uqT&g&gJ|ma5!}{6O5#m#$mx1tbN}!>645H-(P)^nF)Yot*5>{)tgN{NsOqI;z_r z*Qxc7PT9IYs#vcyJ4u-N|TcpWjg08%&aJ-9vBuh z>%jRFG8(ERs`Sy%#F1q?Hl1Ag8tI~1*Xx+m%v`Gh{~Zc(BnWabla4S7%5=m}hmR(6 z9&@SbM##R3GFh#LRRSA+zJoQnVbF|8>V--JzvtEFfjs}Mv~0(gyR;^NTwVo}*9BNb$V|MPIK`9T^lcB|FTB_2Bjx@X)3dlZEn(bfh7s(v za?`M|p~}e9+2PeWU#vQqPfoE~W0$Qq?52^$XtSu3)+4aMJZkP1VeIZMoNw32`u?QQ ze#8{coxqI91fi2PINCY-jKn!`p#vOsnnovznq z|KYSy-5p6r6;GyQQ*?s*o!LN3Ij2h{D%WHM0%lA4ji(C@T57Y_j<$yhgTiruJG;hyDP8V-BCyl}3OcRt)pqfqRrxNx5`LZgmqJod~_;dy{`r+K& z`>*%q@%HKih1`m*RHDOB#Woayr%Mnt&{wzid)LEkAiDfG*D9}xBPC{G}AjIxxby~>?Kp=#=)WVQC)=f33j<2Z23woWW1VpxLfuAL=y9V1FBuX6 z*+=ys8KeaTg_4TaNrIS6le*jp%mgXpWO)ur(GyGb4~2vwwwDj`KeWy}NlA=@BBDTe zkXOdIgw!N(yXh?VQY{yebOkxtkUy}1NmS6_WI}(hqf zQiI-fVI9v{Lmap$?|I`1-BfFTfI@Si+v19(O0pq1k{p%Bl4FGWZ(($Xqi|ZVL@y^2 z_={ZC`(^QI;>q49QshW(5QhsffvW@<{+_6S6KgHDm=$%#kBv((cUGlN<*B`sFW$`;Eyp1V>G+Pnhj(L7i~P?i0kE?Qvu-N zSkGu>Y6Et9`JRo6LfA=Qe6iP?d3Wui;}-EMo;bEolX-4w?s{MBsi-bs{No5aZKa{_ zZ?po+fwP}@)E)bNVh{+0-+p9AVTx-QsyK>bvZYkW71R<}U>moK0~MJr zY*U}Ug?fB4?UzSIu29oL`8CwOp69jET5VBjg3(Xo=TQ7r*wq-nilXu>TwHyx6W(x% zJnr8`!nD5k2Uc$%RtnbE)?^TGsmO$_6nxGnkw67;Lzdi2_F7DR;X%DZvJ57QNI!Op zSs>ek$&pmHORAqcfZ6dQjFmW-Qk+LoNQ~FWz9u(=*~N{<`ciruEldIdNe~l zMo)b#9%{y`90%-{8_p(KoecG`x8%e`S1|E!4F{W=5Gl6rhR=W5J*@1HuPyNV1b$zg zo>~)gM5KH}ccyD=AHZnYAHUR%(eu2nYIg7WN+fB>*SS5qxKrqu&F%GLv?-^&v$kAp zrSb8=VL-@gY`Brd+x4m=R-0`x;IFmX9-B_n)1UCr zQs(ANH;uo46Wt0lOv)zjE^o{fp(ddxYhJ!1AFUcYTG+Fh+J0<*E_#z%wllw&EOeje zzZZU!d6nnqxBwK$?@Ev<(Nr9SYG1mh6xnXCUhdW!77W+V%S)8|V1XBtL@+AgwX zUqn3J=uq(5#iYK5k{@a5zvoXV2jvb4BJApI^QP)e zdhRk;Cw*l5&>nO}-a1LYCFPXOi{$qXRGo=8f0tizC?51j4 z);C_~9z4wCzxdDbYJ0dh<_mhbo^_+_Kis=D+pF8q?bN9EgGiH|LkV;!>;`Cy;*_e? zgVnF!v$t~1O}|!oyMQf01%^=H$3?JmATp2$5q;65MJ3!3=0B%$?;cZ+swmzHFD*~M z74K@ckQ4aCW{29(s#MHm^mAuxPDSKtHhgI4YCqEP=kEw=%=mm^2V7SDADe?UW+udM zV*3~oc$tVs(lgkEgM8-gy65$S3LY*3K}~XyG7=@%T>z~wVuk9pc~5Qqryv|}#dUm~ z8NA*8E_Bk#!M6HAbejTAa+84pp;)@uP?^1cpQgZekeLw#KuV8i50d*K-yoU95+Et* zzApvWG+A_l9N4s+B^0|427cr9fj4CUbw5U_Q7 zL!^`{pQ)+qY{;AnbT^?*kuox=(_dq30}cArMDr!X(A-)D#C>WNDah66%vu#?KN<@) zTCHfL%2%ZPS477efh&OX*x$RDG1XE~o*dQCFv^&!5cJ)h0u?KEt?ewp3l4{iUH&N$ zRA;W5FZ6-<3aBV5+KqW%HTWh*vZp7GTGV+nXj?EeG*p>Sy)dv<@H7e< zLF^n98m+s(Z9G1Iz}sqAXuNN*1<&in^x>sf%|ts=M!8waq9pO@Vxo_JnUXukM=H$W zqgPM}$!iRGfw>S$%JG3RP?5VWOey6~bERHh#No=AF@+7L89&WAf0rYNa54BSTUT<( z1uKdL5aP34pcbfnhscU^VOoEdnBx+UFhMRtr^fn%h5O|Pi_}gQD&4>^IMjSI`A7Ai zxKgAEK{76*orJ50z`1Fpq*yLTXTxm5KY95wZhh zq-CG693fmbI?xjqamm7lv^1iKuL(&!N~z>1`zq{49pkRC@09UK>d=TH&9wXjopa2u zIs;A=0!sX*x(S{Cmj$q!lW&-}wjJNUGE}&NryH){)NP0g>of_k%t;rd2_jMn20tp; z`9YzYrF?KcMo3>UpFUSH?Q2ak`6G3GOU1&OQjLHT_SWNJ(;9F@_pk8S1q0uM85Pk~ zWvj-s#o!3Xj)O|No*sa{?r`>JCnsHAV>-#w@^tL6$+Tc%BzJ7{Q+*5dbgDu10k=t_;@RI zrU?Za>*Ba6h9SjwD??%P;UFo7nAa}dL_eu$C6N+V%YV`k>VJNv5itoycJ9tJXF&#C zJ%~B@xLjGTj6I$#r5mocj8vn!SU=yVTg9Gm<6hM5%RHY9;8TjN10aQ)cB(ZoUL84| zo2rv{p2xz%e8S9e|JFrbfJ~fbzv%SJOYX}<9Zs?Za@#FG?D+Utsv!RQZRgdtQGJCb z+s5Csjr(eO*3lhxpe^$_-=v~6d$?5pkp1wIrnFzoFo3k>7wG;HF8|-z((T&I&x9m_ zf0u~05*g{on7kRC$D7+T9jH?t_F zc7WUPBv~UlS%ZYFb1w@6_OfEn#_y&a*`)F+k4hBQ0h@X(x^w6Jp3bh*YJb$oT9xeR z#LlAsbBCm}WulR_=o<%iunXlt3<#RVNDL>+Y@xz5p-JQfssvDcC`zoXYgc=bYV~##M}yw#vtc$>WD3q{WSEKSjoh4k&;JVIKMHQ?WAk1z8fzli={F-aU&i2E;b)$8)H?2ZHtJr8DM z_j2$-riD6_iX0(fM@0Y#L30G$&gZm?5}4RgdYN~Jg#e#r+52kW&3M@4GFXkGKU34w zP^F0&%HdqaD`a(3p#v39OT6moBBvt-Hp zAlUt+)K)_sAQE=nAErJkVDX-6BcC}7y~Yk;@sQFDp)re~aUDZ4C?%CeDxlkLD{U?a z=>HXt6Mvo8D8d9`P8$T{5f*7=uA99Z&pXJSTVGyUr^#f}E{1}UZ7bs`1az6_G!^gs z9nH5wcHYoQ29Yo@2$1ZL=W@HGj1-m>Gl<>Z!KfVrU$P%cikX?%3mV>1QD(2K%}nu_ ztyG;8MqSFI%)d0zwpMpwz)bg>AZv#<&#xMEzNumO^}lsqa&P zeQ%($+Od4TtRR`laah3h@8J37B)mAS4kf^aqN%AN&gkdl`4OCZJbbJO*)&KxRNOr0 z?gMKSS$^|_M&(!^t6n2O(m#ZbTFhMQdf3*E(rYtlF*AIl#@>P=BS)uAVYP7ixESNo z#F+MHn61zl6Gy1aBNwFrrL{4L<@fP_CZPVGALznV%1|&tllYshpcpg!O=W) zmI-jqoRPu_J1n`ZFu7i`gdHly0r8KcEkk24H*gLc=sVcxFr_BUd;52y?ULnp$fos)v z*+Q#967~PRLy6-+&tX6-X{)yqiXaY&RvZl@{(`y~g^U%RkO?=>u`7t<%d@jnnzQ{V zyXXC88~H=J0!b9art$+8jYlDCzxlF4%$_t;k=crekZyJl<1DynH6T)T3MwoO#xzVF=&7`o4>Y)p$5i}}-H8C~ZR`*&)ZF?wo`g zsJIn~Ui`kz2ZC|hoo#1ndQN{1Gw$*+&OTu~`aQ%^>}se8w|MR*@!HM%@68xh+$C>3 z^pkj<2;GF9J?$8EoJW5g*$dpYyZx8^EEafkg@K>{81L8d00_p+*OpWBpGvCxuKz4_ z-mM!^!FIdFME=^}iA8 zyloiMLp*O{hy~sjXY;MO-j#IvtBk)7+~cMaT=6;;dU2V+e|Z|Q)AoSvuG}K=Xd zj54wqJ70S8{WnU^R^3OkJ1*m>ZgWoo4ov6t2LJPJ_4CzQ{_|i_d3wP0Mj#|Cu2uBr z^z)IPW$*(FS!$O5E+fL`rF6<$)Rdm|?_j`6RvGQ`awUA7w zj_1mF;m1F_N7~#p1`BT_W^FwrEW2(~e-D!GD>_?fPGTlbHWs)xYgQ>nsC{PsoBNs|*7^TW!d9Ez4iqDF^xxBs)=M&T;&Mosr+ugm z1JkmGMQPd#A*RrIeGvaqzW+XFU!VAuFAGAtg|O3RPVP5W&~O8zkrWp*2ht_W*S(BY z()GJYEz9oln4WC}dUrm}h+#6MPLny<;7~GB?@%yl0=&@zWm%>!#R|D7@vDh|i|jEa zhh1AH%*XoVMtdBzcgnl+O3R+NIRYz9Xa5ExPwj1N-f`@sqi=B>=LtN_>uq$n?cb2( zJ^0aNH&C|z=C>^x4)M8~ev>j#viMDazx}#}RS!7CfPq9HMPcKRl74Ag^v07ti(B$k zj4vx`tX$ipmm#U2yXK8PL;q{g8zwY(Yop&qZIKTK;szmD<)J21mSB4jtE{Jmg!Gyb zDTnlj>S)$dW+VMKtf%`?ec$eoJALPF`vTHLWKbbJ_1CZz-Gh%K>1?_k=GN9fiWa{z zX05E{j_-sp#^5$IHd#$)N-$J6G_thT1r#%AFq${D)uMF~$2RM@35s2G>mlQv`3$fc z{k!BhTIpy{7%HXq9?`2ZYBQf2de&%=SCY5d`t|QD@TTDXJo^IZie%#DGQIOIa${p* zd1|jnxI2v1BKNRr-*NE=(1tV|-fOcMX^k9z)!ew#Xzb|e{FB&j_)WHv_dz%?+Nf{z z3Osnffp3PUD;K-=JPv%rtIZxGY3zX)BYFFT-;m(sai7C^gP>7dcgICX{I(%h`7mW& zb!?gdMAWZZedhvkZKY3`#lO0MneB1d5Ovu1Ie#WXROOV_YuN$x6zn(-T<7I@TiJII z1<6s=n&k2NhDJQxoLJKnjJUj00m>7H{Ruq4ZOoWFgxURz8aNM0`4%cB%EeqL^?_vg zzkYhA9xx;UX>%~y9*itwjN7bMT;LEfbpe#y6f4+AcoV69h8s&O3w{?duZz@soKPh` ze^Kj`KKM+eBLS)8Si(3sxN+s0qEVMa5+dMq4OXK_{=gB9j@RrAS3}KmdygPG$d<#V z9jZhl2nY9rk-_Iu(EKi0v)3r%#Hfw?4A=Rn?#KyId(lucEc1Lt+A@`1dvxlHRBG`p zNlv+p2+j}axP;Eq=upM?YC$~Pzf^O+9|vzRyk$(3e9P zW(-=@IWFUQ9CPS>R=3$Ln)xNydA=OHZ?qO^UCM#})j_)@&yI5_{B@s8p&7MAkE*K- zG*{jdHD-C zZ~rb%nixIJK~Eo@`EnX@qT6phu0tH&4;jx?n_*2reIO6zlGn*IE9hzd`FC0&D{H4} zO^B_-yRR+JzhK^xQ@6$Xx$NUu>wNXmkx+-f=gs4P?{7|5=4O*l>}&SebGW_Mzojv> zT1eLv)cK4bkGBo%jb{3Ew@gks?z@cyUYc>%l{4jAyia4#hLDc=+F!?nXB*kKT$Wvn zJ70XnQGP3QD%e)iT4ZIZ=SQ;;^W%F-fa{|^lJV59kA0>Z8fZ~TPA19Fpt@PY03h^8an*G`4*4K}z_1jD>D0o<8Jlz|{5Ax{3#spUVXX1dvj{-Is z+cg#nB!Z*TL5d6;^HXIY793q6K|vv1UUANJ4~lFo3q5T*gClp5Yt!UE+YCMbRl2Xflg6)vA;%5A0scvq|?&3 zRzFX+Y?#m0dpbHgrVx6{*~xS965An59g2v;tqr!tu$yqYC{px;a09&u%4wW3S&k4f=o0Z&13<= ztj_>jQzKF~5uAl7rh}yNo2$mi6FfjKA%c88XUzO2Aoq)q6uSZDH;uA|1WtdOFwqvW)DJXetR5V)*Q;n> ze;ls0=qN2MaMP-M>#+FKL|WnMTag0!hn^Y{{$wW`8*DPQ%b}ID5z-^_Oj|oviZc-* ztJBpEZj?kSclWX9rvQBOx;(xbGX({%1Km_JZUiqe1zg^*jZleC_8sea&*k`p>!a#1PAbd?!t zWeJ1Ado9DZ=jm(d_e|l_F5e|9XQzu4gsjFX1jYU?+f~06@?}XLX=oh(d0$q3Lj`rN zI)m>ZquqvzV`s|yT#?)W+0*4)a$OmHOzF?e>4g?p=D|kSPl5zR+?moA!*WYY?(+&3 z(0x>C%(uy0=;d*~KK{c>R^(q{hkuzioSYeA!yiww`B)8kR6xgz7x(P2r}FP#JOB2v z7ip~HpEeIL{#QgPlRZ+g|3euP zaBaDs&ra@2=7U6-tU2|%&{G~jUqK3p^o72OXQIO4oN>}UwWwygc1q%5a9s6oIlR44 z3=U>3I0`inFjLcMbb#L(dBw~Na=uN-WCQ;P_NLclRwictl@!L9M6K|R)C?6})0BYL ztXPE`Rn~d$JAs;Nl7-wPIcnD+b;$1ojwyl-=LWFinG3j?iwsGX9OXNhDUl^fu2E#h z972oAM=2aE6%s4=Dr6n=h#nR$J9;LCnRErk-0sziks#ngPfL-uk%&qx+=eJ6WfqbF zqj;1?3zrCS4o;mIID=|KmsM2Fd>n`UUY}_VFX9uJ$9^O!31vIT8dAVG*#(uU90Gr# ziRf=+srHbrnB9?z28V-l+$hT!W6C7t6aYz`{Z3bM9MOtq^r@b!qHn#_Q#55UZIy4_DtT+94uO)l*ysqOBN;y;%YM^OT zMdyf_FPgNHx=>Yi>3}W5JdKLvc6f#^=)08e+lu8R^6-@?AWD~4T zLw1G4&9mZkK!5cS3-jlq{-C8gAj0_ow#?FK918;}V5=^E*Wh#Tvmv2L07+wzF4Q2E z&0&*hab{OWPA<<*f7h}Pl5ajO}DDcBOE>BfYn#~sAvca z1&qOo@dNdEdC5wSMnD4uCYZM`b*5 z)G9Kege2VH1G6c68xahGy8p3mH^e{k-5;0y&~8dgmL0U#ijQrcMyw*zUZt~;wvF#4Gns%AjY`m)I)AJ=jaQKGrrj@a@;qQ-thb+|Aairc z-qGGPB&xo6cSPGCAf7!AcLq|T#%_J?qXC^P)n&T{0w29{KfG7>^mL$^RU^fh(l$YF zs+Nn{2Lk`6Elp=Lp5Ri9NBR*{@u0UpZfJ4I#i8>z$z?cD1h`hd>8mkYF`=-UA(iTH zb{0`7#q5%u&y`GJlD9WI%ZF>j1( ziM{mMrV=Zo;?6`vp)Mf_g9ZdeBoCR(7fl1J%~4eq+e+iRl494pRp8}_dh?cdm4jUW zk11;wy~g9-nt~3aCJ^)+4s{WlK1aWRnK;~~9~{Dn${=tH?P?2G(8VT1!tO&xL5CAw z<#3`WxG)fe9Tnf6iZxpQ&S`dYqY-~?T&9kUGL$it@tMHJETNUXqXpL2_kOumJBX8@ z3$cKoVjIY*XC5?Iyiy7JLO@U>_~{jSV#=#+HSMT3~o1tf7D+{-WY3U=oa<3S&hnx|E&~#zAsrY$l#0hjs zpU;P&^6t9Om!W9(JBS8XqOxJ0tP8s*%55BVp+AFBu0!HiD=&I<;uIDi#RhcL=DuSj z;V*eV0Z4>Z+!#(LSsXX*D<~i%B|-F+<{5p$@g4!PhSu_HI?R~pA)_iKMA?!CnMkYb z?-1Z|M94XyK`;t}p>(w9AP^Up9ta%5mnCO1>uy4r5p0vyk&(BNf!dqo{F9WLxrp#g z{&Gdu9w`vAk8{^xw;+1+M}uV`1040MH-d(MS}uW6u3Xm6jPbyiMiSi^7fo%)r?g_< z7L6IPmXho_BYhN>!p|j|HDZot3yIaw z!pvEA zS10UK(PWATAnw3i|e=$V@sGhl!+EJ~>^#b``{dJCmme ziVB%b_Uu={0!?2WSCKLyHHvqtcUUj2B51QA`PNQjW6X<1wqyi?x_YEYGZ_=j$X!YB z;AZzHG9(ZvUBB&H$&$#5R>dbfkvcs~o)4TxAj$?mj)Kx5NQ3*uW3vMq$lA$n#5rRs zMJsM|xtyN|$C;H!-hJ=5TX8;Veyfk$YFyT0W~o?TL+cmZRM{@z;JHIs1w>&0%b%`6LNPW&@O~mg8 zbNm;h|8ev?0gi}_i8r!A?+fjgQf)u#O4ulgn?Ts~eWx%)AG@W&aq$L!4s+x{nf1rV ze=4-z1G~@d;oNeUIE*c|)}W+ladyM2>~@xk1KsQv^RqpICeWwo& zo6{9Yb+wK2os9aWN?>JD(ZIk|IISx`)C{M69YNrlCub!*QZ{#J0)e0nLO@!~*QAw| z>c*9)B{NI*Z12M|ax%WB4TBVy=O+h&$!z$JL>6Pr_P@!*o;c~r@BHIA?HqodGG7}k zSTNthT)9c~oe}-tp*#d``XhDvQl5X$6Ypa83Hy79O22-^nGk)jw{ydhRF@{FMIH4n zEr@(IdXkr}T+(R2(g8dBjTXB%c9{2&4Zv))%KZ!@XpphhIcc~OGW~t8%3Gxw9zWs$ z$)z14ny?RJ<`gO*e1m;&3NJj4CeOyFD^5BI&89k&+B3W1WSm1 zxefLLBghCl;V98>|sEZY{CNCj(62r4 zzw&T?4(@kqm!s1|_#OLe-y`eI|Ca^0)_nT4vhIKRcMCv4W7;fE4A_o+XuX~64qa&b zS9Vm@ezT52_4v0$%xgt&UAA$pv z4%|%(C)h*wi0}kPfKf`kaAWJj=}l|Tv-9Msd&;-H#l^$npUtj1oLDO`6F3&-?>2UHWIcLo zMR=s+XiNfW8V_s;P^!d%Q`DB+ny@rP&`2=ux_{P%OFuo54|!@Z`?o_dtj7;{D!U}Grrd0s!SdB&?M z3*iyb$ul6m7m{MLnJR|1pRkG0`)SFLAcRmvGG-W)6)C@WHaBy$8WiFCO1?;jP)kuF zfd7fUOI^<+SSgOkoRosQSt!Q1v9XrhE(i|rYyR-f>0|r&-BR*2H0hz1W~`7>7N3P) zD%H0hjffvxcZfCY(-3>{9M!2ws?YSus8ZtKWac(v1Mf=OzYTspoeT3$$bs@o2qWT& zIh47g6^rN}@5phGm$8xaLBk1BSygig^y+wOB#20X+<@&}ZLFoamAPAsndW8#e>;vtgGyMC zOuG_u|M+t8^7CdkS^x2A{r3Yk-|%qvhmlq2r!EAEJOzwT!0jcc3m(w8W@mR|Ut_6l zYf<~CSyva@6^NdscT3VXL@OE>3nW%RoOLEw4VlKuSjT3r=4m^~$OF!2Gq(;scN z>}AFERZvxq)Vv=}J~Aj83ol0EPmk5~|MvG-vH?I1+y^E*UPVsPVYBl4y$p)*D%Wx@ zfX=FkeL$r^2X`I7#7A`7p4sSNF6PD*_mNV9&D$-(`s*J0NKLuh z^HD2HOG)pGU)Dl~WmMjhL%PfgRdBWeAr^b@+1+*8b|KFfP5dFOwx`G#&3Y&qvXAPA z5X&p5C{S=;Bpb(kgtyz zEw~;HEK)0NeR=w_G{w|Eir(NpkVk*=mex{sI$l{SjA~+!duJMP5WZ)q7>}EAWu4ym( zIz(n+h0OA*B%g*xGy5rbru@~)8TNd*W&Ru;GMZ;9>%aZdH}tR~*Ym$gSC;dmWC=cu z*sz3|+mz)AsS~m0cC)}R*$7K*Pc~kq;~jKyQ#oBtk4tvIXklSE4(<6|K1>T~@v`^G z%6kp-IJt0tu`d=Pm?8CK+@?TKu-3_CB})!BmurqGo=9&5^xeYB=k^>=%o^n_tHtv? zJO5@(U40c?^jQiU4LvxWE1Ye+O|K2?9sIA&-`g8KzRQ~WGlgBFdLp2G=bm8ricvX@ z-o+~mU-P~kFz6T(5x9qqI0}e(&s8s6_tQ+*b{?~K<==vB=0p%2?vX?R}7s~~5y4TB(&xS@vALXv)=If+#^jiPe32<_9dStfq zMDRcPmrK}%)QHR1d$-k{=g5>fO>y?aGIjha4tdY1{}MgJoLp>v@=WZV-FSyMk%}9%{Ja{BYht?o8*C9Z~@(1n>j?*ZYf#^+QCh`BW;PvgmyO+qP|j(${e(9R*Mu%5M;iJIaG#pHaaD=^w!b@Q0-H2SYPquR8672&%dKS*OeES84u<;;qrJMSU~X9T#)uw2$Yl3sHXnP6J-vA zNi#=ULb|1b$silYL&*OEX-!Y!!q!S_UJh=W6aNBA?A08y*x0DM=fY7pn`-mkRO_1 z`#5O30B4or^tuAo)i8KA+iQKj>T>9hO5=B*`41h9^XaQoV(^4|NKLb<-{fF&xRg=+ zA``A)#r?q>*OG-gN+4Zq4EcGO(BL%};tpU+EzV>_P!DLh{?)h#>B&4%v&*7{xoWto zlK@5Pu3{RX^aYkY~`&&qpIxR-XuBk1lU5YJW8e zbL$p9e{Lq-)^J)bvnv_VKhn1MIm9mPEJ}jhhCJUrM8B_jOQ=>IH z^4#kndN7_$)rBv;W@=B0R!~T^5i`DZN)$#bRLMKGW(O+K*O<1L2Kfdj_;=1Oyfd_P zbpHgsNPy_?=nVG!L64r_&q*p;X$3X8m5uLMUv(SR#^H-digzaFgC#BGsBr_74+wi?(Tx`)pWfh z`pa^nM*ETKCe1ze23EZ2|M;U&v&aYeb}JJ)AMSXqJ*jP9@8i4lU@e!s{3=J~vnw_=wacky`EZmk^$yVZne2*V7e-Wa+`9=dSzJ-xiq~;Yd)5~Jh zUNtE8eg6B;wgax3{_P(=z7oU-@r;~ ze^>lj9>;OP+0|@D6&jq=-YV=}>G-+xkH+(BM;z{_fVzSI>gx|!K$OCh`1nlA;DhV4 z`H^5)DP+Nt zxff$LfuE_;93=I#vg054-}odFeY>Xbf z*GAN~$%Y!{iLjuR2vkP>m_gJ;B4t_MAm5$wv-0yJCNlx+CN7RU&@NfV=kzmDzv85_ zUZ{lTj0zO8YPl)}C?g5}^gx1P9D1ylk-$Y4G1LtPSHok2%3Imf(i%h#u(EC=0gc3x zaq13B8zNAAx!=Veg;A#H=S-@ZfUdHH9M?Y%P?)86qk1qpLYg5lRmm<^Zb!t`HBG+< z18Q1Qj1yMfHNF8l?TKRPK_q=ju{kB0NlHmmoPEOz^$*Z zO}|s-fWs)%^7Mq6<$+i9UTHkcu1y3s1U3{aBxr54F}lp9WzMKHj3wHm3}L$m`MOI^ zfZ|D$1JUn1B7k1T!|enrn0lr|Hcn+Pk1yXqZ0Pa(#K{Vt!(t{5E+5rMP2T7fW0Y17 zy&{Cwwge8?yF9NlMoMxTp$$=T;7?}N#)Be{D?jR~K#E|AV{f_uDlcpSUe_<=>-@7- z%qxNS?~9M-%|8HNWbl4)6#x5nR~}C&hLP2nz@3CuBxOwB6izQu1C7j5Me-v6O}kVs zMr+^F?gC7lEGj82l>o>S#8m7rOsQoqMqB+SDH2&wig~cD2duizx=UQXmd9faab#N0 z;&_rm1sI4hG61MvS_kLCnn$?{{%z1|OKnSfpoC+Wf(X$2ty=T)*%bpizMTNjZndoT zsQHg=TWi(cH8fR?mBnVXAUj(w1Ok7fI9{ROQbvD|SWtol1-R@l>lX`AMfFLXCSi;# zW6~N%PKjO*zwq>teD>UIR=#oP`*ny@^NStIw>$oG&VG)Y?k#g3Eixk+qxrI%K65Y7 z92&}{ZbMS|%*q@3dX@BmJ_O2Z?}+5&S1i&$*RQ96cZY_*=-;xsl`fyS=p*83y&B+) z`o;7jY>>(F_QErK&3wW5vbm*WxG^#9@7ZM^DBa%K0tLHy`Cu&K$O-^HV|uM6naNcI zjj_g~sidrxJB$#0$ykI9z)HAA@#>aJ?>yGbh*x})x$S~;%6+D_+(6^<`paV2WrL&= z68&B3aPe&fgDdN+hX&P#X+IZ(#-5wC)z$sOv0PrqKWyJf^t?C+eHEwQKb)4OlU6wk z@&6b4C0?gc%J*7)s$r=q!Jt{eRob3Yg>EL!tMQMd$sRT$0?RfaJIhwv-fJxW_|3z%;x53 z*zQs_rWHtAjUCgR;L!JIl$)1&N{j;US9#W#GeJavRjZiBK&q+9!=NvI1%G-D)jXF$ z7p65ps{Be|=U?E_*r0#djc8%p=DJmGZsFy3_T(~Yeb&OOo+Y*%@akmxX=44k8aeHo z+MZ^n7GW1ZB5#VUG9>hJz?Ms=)83*Q_M`YK18=w>e_qgPY(EH~Y9Uk4;lPgUe@K=c zbMs>f`nR%~jb=joH%fg`XRT{)e#olHKnpBP)R`C=8fd`@rE#0P>y;X==uzxr7TdH+GLHXUCGnUAvV$C5Kd>MPXG&z5Wi()JzTuP(GnFgVd2KIUy8fLpQ8TjXg2u zeAQ0G-2xz>Z-AI3RA`kRrlj~TyO{q8f>HZ7!AR^;lBs)E8Ht=I%GrZT=}JAA4N)pi zLf4$;+s+1`q<%wi-$9Ow$`oFLa)RNZV+hoOxFFUrBy|OVkD#XIV7;3l$hw+M#qcf- z&s%v>h6@4M@2R^al5gX4;>A8=MiGDcVfI8FK~4Z@QGfgOm7m@=5gJqSJ&^WCT=Z1N z6t#!mCw?*swJh6v!msiD`M>I9;p;QN8C4OMY<&dC0aj|!w1t%Ar0WHDRcsUTs{IKegw|;yrWi_m2ycA5vFEh96d8J$mKUA=Fhp*y zl0kcQ`ZXPK%(Fl~=2eTp7h2?bFDOxxd}ygFdyYhADh&Yb)mE!I0{l|IkGB$@%9XG)5SPpr*!Whc!6g9bu;h_VGZQ6Ll9k zfG6wI?8S4}Rg5uRb9VD(d`V2nG`))Ytn;Admknw`yjPmMq_=Nb0g=}+&S+k1nChWy zOZnhYiE))CL6jb?L$w0%Moj#TSn9w7Q|5k4+4w;7hJXpNJIPk?UegQ+O1Q$T3gtz> zWvxk@$+tRo-4U>(LjO}a}D0`JPw$Iy6+rKaB>*m)Zy0uMV6u0ohvc{gj-0WgCbn{LB9uu49sCqXw zH#e|IM>na<-^*GpU|HDC77=@r3Z5%Qbp}3d>w_xLk5hE?=`O_}0d1)lLy2 zWxiEUJP>{Rt-zO}C!Po83(;ZQk*uQ}mxL94>q!~8KXctvZ51^BLH@!#;vc2e%{*NP z0hG?-)0XGW-?QZV=HR1ip|NqzJ1>fXkpcQn3Ce?f6aHrSF2a!wzq{B7by6S9SU&aq zGF9PUVoTUE<(p*rizs8)&@KDYSSBVnCt6z1_LcHBmPKr!zi_poawiQW2*yec7{(GZ*3I+n9(^ba|Xm6!6&r*R17! zJ!`Vtb~S*L3;5eJw4L$2DqHkPwP{IKc3K@>xe?rrtMSwP%{Qy?!`ZFc#SRY~x5B|_ zF4`EYe=mcRC%-4wsWwf5%V$JXX0+MT16d}f-?`+c3hNhRrr>UV;bQ1^{o*nmglNrP zT!1jjry-}Ie+w0)I>RmnTH3FkSY3#~0!?D>-YLSkN-$9>T{(9eh%IXlT;OKO@Us!4uSl zm3FV}Z#oskmi&8sHh;EVj1NrLJeu7ZUP#W9^ZDn@`Mp_3M*t+*r`OQ!O2w2J8doQ6 zv#w}9sEK{P39^jP}m zJMp=C#LF|>8mSd7o9+?srvBb3XNMTWNgDOzAhAD08v{0?s9-~Xy@t(1Cu?9t#IfR-Gg17^re^ZpgOdZiHU-1lBPZE%m>fuW(O;$d8rk55FF2p0=`})S(y~ZVt zH%~Bli%2FKBZ&R03542?TJl%xJ=-sP8LdzHaKPVX6}&6-HJO9=;3Yr^jPQZx@xPvD zc^rh@1AqS>&b|pO>^1%J2QGsag&B7x@ZfP!{i>&$vhe~mW%&S-J#)lq!(J5@RG%Ns zwIqt?w6V;Dt^Oj>?lV{5e_NmQj3d@=&y?wDmEo8e_U6K^dV*h@&&4cgJ=;mGXckp> zNFLQQTTJ$Hm(>V?2PG?|BSu1nKAI7o7UZv4))rQHGjr?1L-xpW*&WoXR)kt6-+YeB zk5BCh8BM~T#q?~WF@4T}nqf>@#iq3oE1N&S^BEHZo?>~1?kb|wKsIv&s}Ky&d};5c zxFW@mO~2fN)gXGXOziL_EA2S}I)wJnJQPX^Jl zf*3EFt{#mQ3%nnjlv5$97AuM!Dgfa?A?y3=kgBM){Ug@$SD!19wS$e6gfL#9FyGcf zdiqTeO=9|q-?A9qGpoH8-*{`NA z-nq*L$+H;M&D(`5lkaawmLi-Xw8pdjIyE(?M;gwdf93*AQY!(;*1AuhQsRYyx=*vx z*mfHTE$t)SeCbkhgsa5rCvwA(Q^3rdev%3jK_o_~dmn?h6%A^wWeJTLUe)ms*wi^> zJ6|t?KJK=Tkg2o1Hr&o$D6ZPdd$3sLZRbT|tpNYSd9Ujex}iOg?|ix8d9!}GcvRi# ze>&t-jn$u}j#Tf81=xg1-iSTi|7^%X6L~b^4QC*2-~>cB^bhVD)X-&){0>sGFX4yu z6z(oAu#n5{gH+kS6VhzpvxKCirI{y=y}R_$qF48m|30sSxhxZtDK|eEtY7un*eJ0+ zye*X}k!R3Qo_{HL%fsqwj7~RSsyvMda1x+W15c>NNK;Ok5P$JcFQ4q`ag3=!c+nV& z-0%Pj_v&ZByL4gj9he7Av85F>NDE7zH1pJw?X;68mTYTsZ>lmJ-xOGjQsgidSa8qe zp=aQ@Hn{cGwfriQ%Z@GiqvrKkRP+#Or=d@!@>CsBXggxe{FI) zSrpKf`i%YHjFjh4!^S8nm4)jcAGY(Lg$zF$Z9TUFq^{?3|&y&ifo zM;i4ZVSgmmbdT1+eU^XL5SE2rD*rHYD* z@B@p^mn-LVJ*Ea|<78$ziB6C3po5psHAEbCvAD;&vIn31c4=;pZ~eFDA<)}{#M(}f z5tYkW_~|-n4jbrw-19Vq+AbsW{;YhPfX0LFD`e?U+2D;z2PURcL}~Ua$K4FUh(AmL z;YT5SeDMlF$5l1b^R*PidT{B*u6&#>(bguaCdHH5vJ@0`rmm`O>y~O$+pA z!|nHOg|O|EeiP$NPwa_+iN#Us-u2X3$8qmmiMQcTx{YDgcF1~mK<8e>pKBdM4Jr-%laL+%mg{x%B^2Y< zgr->)X_Zn0lxO?9G$XkMy!Sdh0-i$zd^0`KWlu7F;3GAs1i#zXRT|@U&NCDY8o-swlB3spR3TMer1Q+=^Qs?X4d5927 znGFxv2R4+bVwGK?DNukQvOA2-3;vquhYm;6eKx!zYv)Xv7Hz;-X;sxAG$|AhFV4%5 zj&oTtRuXvhv5uW2@;QyFe(EnKKLQ@CQ#tgmPzWuzdm4gv>mJ){s0feUg=%uP#ilWB z0pC`=_tv>%03fe%9N0@P!(@WpI5g?lw$($9xZHxrlo z*_f=*p&&@yuPeB2-h4c}@btr^Ka1Q+&l<5--gelZGLcca*7Dv4$_tPeit1cxYzBSA$K)R^JsoQRfU_@^Y*G`?)446LeT2* z*Y%ETUG~*o{LBI=`R%*iA5K~1^Xzq5LjC<6!*35SBEr`!lW(SDpQ6KY#Voh>FC1}U zmj&3pFJVl%Xu+`aTwSY^lGksO&&={qCRQA4-y1Sg%3e(`s$Ku&F8r6jbp9jd{b1qs z&{WJXxih(DTorpr;o??a=-#RYrR=}J4^uZ+nH}j>+ZzX>GJ=wOc7^}`-h_o1*>+r< z>`gM!JWiH>BrkDV-+8{eDe6>n5^;T2h_%Mee<|gjoSIy`?7X?yFUHAge8NISV@d0T zi+xc+8LX#5`=347lu>iBMQ>5Bl~#oCf98`u|F3q|4$9l6i>5{!#J)Goc+4f;m+}8S zUGF3GX}e+Yo%71}3}(`C<@!G|!H-j0Zq-|0r~BK3Y~xl5OOyJ~fB#l9CH7eheLD)Z zvr}QZ-cIQrc1?UKCMO!Q7$noz$JNK(2ab>hLwA?3XPUhJmb}qXNpid#(Oo4?YRLW) zD4dm~F2Fqnh5R(W_1x>{Ik!%M7ckyvu3?8Ui+vA=W)G;|INCs7Qv?bP zWtt3P{BH{$7lMSA<)r+%be{g#3vGpYxeFPT!C)vrb8NZ??)39y%Bs;0H*zvOaWZ^j zZgo*X!>wEHeY~=Cv21m9UU=v2^{4xu?(U$W1gUxF;`;jXELU=Ne*Ws$2l+qfc+D_2bn_qbK`$OJYeNtAo7@(|A-tuCm!NYNIk^8=t z8%Aa!iI3EC;rFq9Ezia07kBpmea*&yn|xo|=lBqZW#u@06~xATym-EhiFxmeF}0Fy z6q1pXn{`J-<>_uYpi>vU?rK$?S^sg)uOre>d__fm0)N(gC7f)7HZNumgQ8>z-(vPhR_ zLPlW>cS~Zazu~RS5RVpfsf~nb8pjl5qhz1q1jtyClb?CqBoiXe&Tax5#od!0<@rYY z!I?M&5M9oL%260$9@I7v)yq^aVa~)G`TI3rp@M>_k(Gs|tH;X(C8S##r1;6h1#zkS zuVR!vE(7LIbre3}^Gh2RtF|B9k)!pYD9$ISB~~(@I7 z?wqGs%MeNav7tc9#dwTrsj1b{Gr_oqpU%b&uAQB{@{_Yuu9yb6A`V-JYyZYKF=VE& zP1(=I#Nmj=FlO63&K<9QkGA}fJ3(D49tbPpNs6;s!45u1G!u963zi6=v71n`dD~m} zvxe~=7`D-fo%EJx?$a-7Rm1w5!`1Yk!=nY_52_qFt6n|=51NSw!P#?4PE_2m2OAV| z?RDf7uylh}K;N6k7=S>cd%lL-4^bKrM-OWQ(8!mSt01PGgK+`4ZI6pHM18i7$DY?~hw&vI?HLJKDKlLPq$ftMRS; zQElPwv9xFBPBYVgZ8wylmtl72RD8{dn=B-u=*b@s3`hxjd5kpp zDxDo%V5s*zgoyHQjdYYbO-JF9^f_V%`i5yQ!hEr&o`#KaeiSe;a59?jAK)1L#I$wd z#6kJGb!u^Jb~^NTJ$KET8K*#;2-=vqIWH&wJn`&0B1Kp_cK6d-_0r{HM8uWgZNp;a z9pY;;|Do{Jr?-b2y9*%wCstx))~f-6LZuBk6eK4n^P#7vrrL2c+1Yme$xi75LzA1i zo*h+~`h(Xj^W_*3HO`a+ysz$XUPYq%5s3#Ah|$=XcTFPR)c6C|LR6Fp9+olna14 zimZag)A@s^)oz3KLv>y)*pue&QQ0sMnszm-%mF1~VXcBAZ)pQ~1L!+dcHvYS zqJ2^{%63$fw_FV0UenzEOOcQF18J{8{I$Nuqt)JwHJ9Vr+=tjdeer^MOQZm~b6Ay; zJ=zyfjmauQwIIY1CaA6tw`h0kb7o9W5EAuW`JCZUAIH@))HN-JdObN7`;?nyA>d-} zOg8BEw2ym(jj&?T6T#Mvslz^Tl+ErFtmEv@kc!i)x1y<$%p4Le*7CP6a@CuA=Pj3ze6#Av4YPG+eS5dH{J zQ*=~HvtDIaM%q&rV8_%5+I?3Tx~xf@EJ5gt)!a~nm_{j>x0XGd*RZP_KUCF+>Z4Po zM}_+})MBKQ#%$!7$z`^kgQ{|k#xcVar;bbnjxE~4$~HS0-#5W7pKFWldo69Pm#sUA zC)%eu*IkVh13ljJTYhN12QIClr~D6;4HlnNFO0!In7-+XO=45RkskEim;KX=GQEf~ zyXz>lZTc{^a&qT1Vba?W^WXMM^RJ|3RJD&Dg`nIMY#=7I={2qi{>_z!56o0MjuXv9 z7>Xa0?A)^qOv4BE7hTZV=Y_X_#$9smma9Yu>Faprn_0>-^&Y$rxj)y4 zOEKwOotWVGjJv!Q@3bS1t!q@TG-B;yr+O>vyIgv`t(%o#WB8&kMl7c!OU3EkKfS*K znk&{>AQT}lV1-au_M`_CUq^!kq^r%stG&6-D^%q@w>4XK}m0cVu<($7=EVSApl! z$@7Z~M3a(&4dyv(?&fDc=3KqHMnVn=^t=R@1^gVK-_gr{* zg7S&u;WC16qV?ZEYXsM(qgv77om)Mg3(_GQKZ-%ikZv1xb!0DGRAQzu;j`WYSfF_V31_}JZ1&|)lH|< z{D_t$dSl*})uYDwg-I+A^4EruVCD(eHl6W$~uOXAa zOZMNVRS(aQKLZ~j)N6WvKut5@2$iGY;qunyX$y`VdvpFhp) zI9`u9KkjsYQFGnffAbeiGR%U>(~ir9PQ;>B_-45`JmSdQYB<$9nzSnfWn*LK0Vw4< zZ)9u4pA`tiK4A{Qvw@t(3`prCqezhnNqQ;1_epxsT~q(7`A@;?HhDa&!IgCKzMPje zZsdHNTc_i%QLUxb()`(RxOHa5=I@@K0`5ZoL)k$Q+M>F)eM>&@)3tf*ep2#;Ozuu) zNu$_`ddOQR9nbp_yHQSUcDVmebetrgYo}&Kzg1nDjnvN}R4t-k2R}H)rAX+kYzG?@ zwoiz!K|dE8BObe@Vhmi!T=`BJcVAAgkYF5Qc^^rjB#h5X2+F~}Zp+C)vCZ^{)2n&+ zNTL?mODcZ6qNGZ(^-?c-MuNiEN0~)a1ni}w9^WM*K8Pwqh7jmMSHB!}QBYwK-VXhj zNosG^NySrmVbdYBAE1OlIuC2N0!G+Nk8=3+obS2J@`%`BPm8}oaSjVA~EU8pxm z8tHoDXZU?lCF~&ajcgAlrn>kZAQg%+P}a#q@c`OtqH(s}y;p{R8t#pEEA@*!Kpe&$1Be95>lAe0=xp@xcYsVkHuihCySkP(X zCoMnz7x+Gn>)4bT@{X@~Vm5Gv%<7%-YWhjK<%gxUMK2*SGrm$}dr4Lk>{L01XZyKn zD+l@=7yNkgb&(xYt~!9B?@CKIm5J$e6@{#dP^3b`N-*(j5ZQyV0#k z0vOR&&Etui+w9<@K$+@`#ao%06WI{SOD!plZ?cNiTx=u|eI-JDsubFfEfmf>_H*WF z%+%cC;%vxeYsdCzA*S@6J36kpMYXz862*!q!p_QOkDwAM%=?{}=b}5>IC*x7ji_uvc4yq~_QL$6;q)}5*{cQAAOA~I)i7MHCsaXL?D$KR#Y;Op zS+uj2Q@Z(CFO#(Geo_cW)m{x|>Y+3KfSg~kxFqsNZb9Q>F+Hvg@%GRX6v{<6nhQno z?pKdtjMu(|L5t8c{GTGnf&&N^@()@HJkL#l9bz9e`O$5q=~!@#5@5QsHdF z`IY0^%^J7~l63l$TidoW{kZ-A%Y-*~5Gx5*B3H2c2p+9&sIo|?(eh+AHHkeQqUq4u^Ztj zc6)MrGdGeydb`@Tc(B!Z9w~FPH&uAOIZ~ejQ;sXLcC6%aMp3i>ad!XMXI~QM2%X=- z2+q~7b>6JMJ>63P`%EBDtEKa#!mT!F&torEiGo>jKhbkRN=B{)bP=2|O(`7jtK>)f zqcc7{`2|b$wQY8v5#b%AylqM5b*>hlcWu5|9ldpRd~xyWsO4($vBF`J`BMGSIj+;E z-vqtnCXtH?4m<+0ZiHR=>)XmUYMO_D_s8GwGh1NwYt7eukE<{ zFe=wlS0^bU-{3LVTwGin8|x5+JvbK(ueW-WGRYJ4P!&i^%My-y=4(1)`i{PYV*4^KLH&mP@(ojyC z*Tn%0qA2!w(&b1gXR63J?3*%1Ay&=}DE$MW*5Gj&e~P@iu(kg@wY9Y;+LwYiCym@p z=JIDYXZSt& z&Fe!~v?c{FOV`%GktFrcb5XL9^Mju-ajl)laQ*sC(ediP)fo@1hyXAY@B?&}o2zsW z2dfBwWJp!f!;kwI)Ti}O!zh(Mzf1LLjV&%p5Aw5-<}T!^nBi}G%6nO$Ixk zPtiBA6pmGglhqS&7*PFmF3~C*8@15%NkWx;%uW#z`taS!)(@Yj zC_9zjSdW&~(CBR%Tw=3kIEE?P%6sIH3SWp(j{x6?8d1+sJbJ{Kl9R;?d8Lx<{7QYA z%(ZAE0j4;F%*8O;=r`*+sYqQEZ{B>zd+fg>Pfc(XZ0YtpNFezEcqb+%B;i>n=>J5f zcR?)>Gy3sI0h*OcnjHvn{;a~qY$4NobJyBevXk+7!KW_O;X4vrP@Mx8K?G)2}h8N`G z@eRpE4m@}DRP=uGJRpg5e(;4JMpQjn!aoG3qGA}L-e>)3{O(68%P8kMFCe8KFPy`J zh{>Tf(u;moX7ArmFp}#EXIqE%Ma5*{KA*|=(X;l^k0&I@0^)tku}H{Jk0zIhFsq&( zmm&wO*OeVnBCPgpI#U=FNjfe%Ez+HW2Paer;BDf@5bK=-ob6t4zpMK!J zyx!-&-LjL3xEQDDPmZ`Axx8K5x;?-}oNl&s?DPd=Pj{_Cr>?R`MsS7PO(omDlN^dh z_#B*6DbCBW)$V2*O>UcKA#PLu-F96@od5p*y*&(O!d`gDZ3i96CJ3Nv1zptH z*`k@C0XtSVv~2G6dGtB){eSweeZ-Bri<})crxTNt5UG*i3vW&D$KdBWg0Dvu@&uCeNkCTX}Au;*L67<+~5` zc)owvzDtcRrZ8~+4j8y~taW`5nQb-Sc`JCk{dD2;=HC2CVwm7|oP($Pr_H>Oi>eQ& zopo(IWP5qBaiYp1TGU$Flp-{maK}e7k8&Tmj)V|MzuZu)p163Oe0_FMUk|#Ml^PVX z(u;WpsZ-)bgxK{t%IqngVv5GhpBctde0fhsolr@>Ivrm*h~=(Djre9bB+H*pdwMLK z&Q5il{;Mxlg_3dWxSMwVIoz2$+gVT$k@fL8w0EmK|E_SYu;YLE_-w(dcB(-(8L^2V zpc1t^efq(%^N{82(c2uyrs)^SNlpIX_$YXND9#8c^mTq-E5!Rh=h4y8JTM>q*AJJO zlqkl8*|nV;at$&*4iWv}6ui(8DUCyxiObGAQ@Es&Ldl909a9}XXE)6q6)jIg@VGJy zvwNUKJrC1a9TM(-VD-KpPW554pi=)Gdr#4z(lh~<0+iu_TrBb~t%a^p@``PB!uN{r z$*Df^$E#uAsH-yM4A(opKJ658h#{|0b5(}25pm$iVc*2?=yODcIH-((I9Jr~Ftsd* zt!q7-YZ}V^f$~O*&rd}yEuHT{nGhfB;zq_jHO;u6JOD=#6i?II+E$Ir`3(wBi?rM@ zJKAB1J|W9iZ^-B82D6Yb9wU{o<48FhfWR{#(?iCUJo-fLUMVFeGCAN%&fmB&@;fi$ zFk0nlqtZ~Jyquh{w~m0=N-vG%LAB1EUIogg@wKGue|`Mu8pre@ zjnw8{sMzME5j@&A0T#*Hw@iHQTcP$2Awgc9%+86_`?LA>qt6|-vJ%lg^{6P;)QS(z zAK5fDQ>dtv8;Ukfg++zzIK+8Xgc^g<89{~NeO*!XMlgVc@S{zXv)PG{vQ%tOlc%s4 zps#BC!L?>Hs*+kOR?jGs0rG2z;cJ(D&G*QHsL#{_YOGpc z{tG^SGiOkRCYkUYkuuwEiebjUEn!P2dLeSj~&y98=tb#ejbv7P_^{yjbY@4|0uuwmmQ*z@!G`uX{} z+~t{vwC8o-2@cdd@K^N>We8d=y50#;uJ`F3P(zD{I3A3lGn2@1^&9bjK>>C!*4E!9 z{Kbp#lN^jbvZwtlvACFO0wxWJ4!TOQY3LK_D{KB??Rkeg?+6n_ElxB37gCrny&zGv zIsP=_wxw{vYqx@Gl}1;#!*S>D0Vn4AGWn`d;ruOx^Ps( z&=J40BEF$o8P(cHBfhuh!^z>tr8G1&EVuvq!F4it6=A=NWAi2dZoapc2d1znppk#?DM+CH{p3SyvckzWx@EoxptJD$ zQXzm#P9~>W$+^Q~W3mMQXwLHfP!O#>-xasG@?`RT4gM z>;B5ou6=QPBbOLlT7W~O%1rIN{3gsMrL0lyizHJXVN=|d%Syj4`AMIX^=ypqLVl3k z&?ruXSt_)B6)u3Z8w1 zQamy(FFwXwP5d7KU_qb0>2*(@oLswRP1Jb&#EDm3atV{0oVpu9nZ244A_xrC8@qPx z`td^#*XlLLJUu-P7M*kT<`5%>GSqWVxsH$5YT4+q!@Jvyo%1)J*J?CoPEG+pzbKre z%x4m0p*^n}({tiOLv=T&C)pIwmy(GgYH% zK58k+**jkpg)@-kLt=;N!%WS6`kOtXnx(D_Oww2w3{8>P7%&2`F_K3nkJ-_qCs(f; zHC!Sl-2l!247~$(R7Q!01b{4J$VQsZwbarZn+Y=@IZy!3MO7gnE1EC^D61h@K!OrU z7)tX9&Uw}li=t0VA__>TfRNk`h|XCE41`!A36wq8m;LD3L(4XvKR&v;-|aIS*Svu- z2r-0yP$NVqQKlCy1`(WPV{@RZL2D?aMA(-Z^pR$SX(x)T zpX~2HbQ*k?dk6v1c{P|lGyBrs{Q%@#R#tR1Vqyg~kaSuPI#N4ZL1G11HUtAqmwiQT z0RZp4s-(8x%*dsggmT(AAPvO3nl$Q!V2F-TH740hvQbnq3I-LI7{S0)Bz5!7xkP}Q zpKqIL$`BF^U}=Ese3prH6Q2qZ&0=z%G9@mSiHN8;mnZROQ3f}#mL)h)x~ftE#)zuo zI1N$AY%r2Rj2akF)R;*nZ8vT34w#uClZ9xir3F=Cc9^gfstNljF*>HY&n1h@j@emR zvZv7{Bj_N+eo^-8S*@1m3Q!jP5Tj>y7fsxpMLgyu)7g1%wf=Wi_*eND& z6ILJ$#%Ss>dGb?9H6Q)7%-wKamw&Omyk&WQ7pl>iHxbr{1LA_f@2Ec8Q` zJM=DNS4cTGKkuBISTY(zqC=^fh{Tkok!p4`3sN#+@~NeNHP#ww)aoOnql=3R-un>3 z)mL5J8fyL99shpx*s45g=@s4+H+O(+~%Af9hZgO&Rq0@e0-`-Wrmd~A;9~~Nc z|NDMv^{REIa%y_&2S2M|V-g6uI z{2O2U=B`~YAi<{dHvQVKfAGYKlShvn{)JoKerjsrKkoS28{T-$o34G!qmMpWlz}pa zlzIzbBHe|>F2a%}qvSXOWQHb2#E7)8*!keEfAHd0UHrnH-9O#6Yh+}U0QT+Mx8t(y z-@j+w>FLvd{P92i_#gjCkTRB0f_mp1qLGPVzt=x{G%BNJ2TEEmM;73=RW(# zAOFKEwy*r&_fKx#yyf_*sYAz({`LnyIKMb|_?1JCJ@)u{8#ccErW;3E!|#9ZZC||o zOGUTm^IDqomHnb9%j3tU2y$}So_z;buif;}BTw~wn}2?| zHQMj?f)u~^dmq`bZsoxj4_tid)_=d_8{hl>J>%nJOaMUh?fDBfum9+WKfHWwSfoEZ zJQVt2c+8)k>wobpcfIYVpL_bJ&lW|$o;T1;)sXp>!-ry7FoI`4F}~#Gg9p#doY}r( z+mlZ}d*Z~&70Z@>^UiNyaKZU2m#sWGc~T@YH%!IM%%PZoly7?D8#iuPH+f=mVPSsy z%$Ys=_JY~ciKP-3Kk$L~BGK}tqvNB)Do}L0oyB%h_NJz$`u#4mlPIQG^yf35XD&C( zoQrB&mNB)`2C5>-`=Y7<7K0!XCJrH@W0t6q9J6 zln_!2P0TE*Q7oCg$BG652C6|5YQfA@1yu=A5^P`96d5$-F9U*ONTJp-qSTNpIxhgI znV^6IDyB6HDwru(c040u0A%mnQ2o1)?tW_b)YeNc7LAi9ju*W?XFR@SV#U&>D_1TX zYPAl$^vZM3JU@44E`o$2Mu~~~-E6d)jaDcFkg}7qS8RFg*rxM0f8*=lDI)dyy@()1 zPc0L~>Dk$^XJ31voz-g-6XRlPN|Y827)i;2Gpy?V#JtxuGD%kv4AS2WfdqgVE4HI0 zTEp2jfmT9i03b3VGK)ls;~tS5A~<$21aJrnpotx9NSv-WGfl&{|6M)WFPTxr(MlZ>Yw2MnoY5sHPE0z7|VKk1to?=wy{5z%fTl+oI}zHmq{htOh_N6a^5uEX&Mfq1|>w z+6_h!OHq%@mo9gS*cL*PM<_rPK{d}=gaATF1cVxtnUOfE0wDvMDj}+%p#dU0S8C9p zj(z3PH*>%Wswf%x2qLQNTvhs{2Uryl8S!WT2CXz9^k!gW3L;_*-oVrfR%XOBQ9vX# z5HxVc#y=CKrf>xUjS7ZD3;;$j#rka$wYDfc$ff{l3s~{kvGqZ?B=ux6S>xPWR1enHt3Z_7WYKlN)ET+h2 zVra(5MJUQpiV8Y!BK=+;G|9OLP^{Wqt3<;LQx}$1>u^*Cs&G%3)oN3xPCfMFhxWa6 zpe#x=V8RoVM{obi7azF)0q6Xu|NJvx#zcSf*MHOPb~^nIlI`8Sx7+JCIP3R&a|^S> zqr({Rfv471qSO3u;{oyA*`Dgq0zvvx@pq)-PZ`Ahe+p~7v8t19###F)rpfeO;N7!sO z>iJNwEK*!cG-Jw%P%RFRw^~EB#~ywx_j$kUpPD{(-w%Fx@kJM{T)F({;lqv@Ootmo z?M`QSbQC2G0Tq#Qrl)@Lli`t(x4ii+MD)Vm7beEW9QnhCx?5j$@s90VKl#Z|-tq7M z`fI=ZE9afN(V{$VkFH*`YU|bu`@M4O)@|o)eB|iSqqSNdB&xvjiRI_4Sl;XRe*X_X zUa!|4ee9VB9(;V|>b1v@9KZjEkB%=HH?w-9b@=enH(m3_yY9NH+v(RELxMIrb-Y%q zHS0q$Mk@_Nh!VjxZ!|!aF`WzwMu2Q!CWQe5fW?G7#dgtlj5%j9L|{-0WQ67t89X(< zX##DrY}V_0cE9kND_`@*tFM0jYp(;H0{P>Z2t*L4nwNcA|{}28k^ZBDsJaz2Y5s`Sy&9^w8eeJ8?c+G2GclFh; zf8@!>KKQz;_rJJr*K;pCzxxHpJ_*-EG*?9M{bFJBc`I+c?zN@BfrE#KhKA0ZnJxO= zUeUkzNB1ooA3AaJ_=)2SrzSIICX;@zm*rUqA&RI3SI?sWnDzQyW=_M+5XNX}fY)y@OTvP9?7%@;sfkpK-%K@m}r ztOC`53eBGB1I-ELOf`6lK16+X_e;B8JXWADpy){9G6zD@z{vW&KBM!^`q1#OfW=tpP6!by z;y9Wr0;JnZMH0sC>~5&i4G}qXW*{ms_$eZyCS0CY`+KuA2~VSSRYf9V2WiwVlJ@#Z zhMiOfSlw-Qb`_-q6MQvAP<2`6z3cUYiIznmj5Vr-QV_L_qChc5Lj~qo#3;eJ>}S75 z)qaDiDJY;3G7-fP5HUGN2FX|{v_w_aRf9!jBozb&wHTB$pQS5SL>v(eVk2NcrU3w^ zRJPmT7eD}r5*;&wMir_GGKev9T49KkWzlFfRJACIw3@-6Nr?>*Ov%zEDg!o`C?KY+ z;Iki!h`20^R_&)@u;vg|GGIrh7C{LpT1=Pv*=<_-LsH==BEVEg6i6v9ra{pI1B*lj za6|wY%`BR#Dk&kMp+PmXI$O0=oWL{yGD*)4JD2Qg0B7GQvw@`$k-!p$p?V0T1|(!; zHFZ!G7YG)?*piO|A{eM4RC!X8v|~nU#*~Dz3GlB3W^6!}8b2L6Fu*QjrD3W9X8{lh z5(X0h4J_$<002dUmgL=%r4y9$-T?+SRLt@WnZ%5w8d@Qesicl9xe|(4JpIfw-ucZJ zYyyQNM~@tM>E)m9+I8Xi7xuc{2r?X+*h6CXx1O37M_l%E>4v&tw zsguK_t$xuTUoyUB^X6C<2M-)9%HZ-05t*nAk%*CqnGsne0D!2hTD5ZW*zujuKeu_~ z=2u^N#rpN@-f+!Ttr7gSU-{*`zI)H(k3V|q^wg$J=l%RGw;0%u9(Z7}y;!T&liJ9@ z)X+IMIy%aPWhhlskxWDgphd4}4UK%}FaGN08{hWU8*ljZXFjue%VtNka>c6o`L>xw zDPMo}we@=A>Z{+dbLaDOiwmQpW0w4cCbe1)Mfunx4?p1!F=pV>1CTu%z&bWr5z4M@1{k zV3-cC$m}%6`NjEO(a*fkoJZnl7NUOY&pv(Kb#Gq3VdFRNymMh;ZtB$3;Uh7cZ;2{@4)2D%&Eosh0Pn! zVV@s4QhxXDM~)w#1fx99lQtmF@-wqDmtAoMf_>o&|9s-aiCVoDLYO*za?9q;^X>U& zvu>zlHZn3iGCa~9?QGbve*gY`F@{>6M?^Dq%px+kurSvTp8b&{hbNXSA;%$z&vHVl z*X#Xm(eD?HJWFd3_T2B6B4S`J%M2*7NYoS*E9H=(DG;Y=Zo;ca;u=uesB4f20^Vn$ zQ6Z%lCW~c~qLjW}Zo1dQvA=GNMvJ5U=SLp&93?ChUA*X9BChl{R zox|W9S2IeX%?d(_h?at#(M*kyz$m>QVp18TTVT34O%;GKnn2Ppr!FzU7OJIzF*7M8 z7<39FaAbuFB6x+;3^n>Z8yg)xa$=gDQ&9|2frvPQI5jZ?=WHN5Ffc+e3;igZWebZP z5p|Te7mLPl({Ua`Sqi;;=)|e%X{K6?B|ApsC`FAu5k?6^&5>@WCo1L)z_Isb(d!jm zQOkUmXBi?z6z?-6M#WmQ?z2q60MI#?kXs1A>_oH@IzW}G0E58QRD2{6ZqhLfi27zm zXS?w9BVtZd`s#uiEDO`ok5vh3DPn|ER%GQL)3deFpajyhl9Wn!0$^q%BO_+!IZH)G zjL~~fL@|~KfNCyD@V#@M5M7K>Rcncao4Q*Chgg`3ibG%h{sW@S;MF+qg}Hha>1PBK zHQHdEgopr2gd#>nAx2191g2+84H(E5&K3bkm4dmd_9&GB1c(wN5%r6L1_z~B={WK|_2sdQ#l zSc!pB<)cGpj2e*`#D4aYAQf5F^Ix4pfHFWK4!W(uvu= z>MJ&`-|&Vvy=iv-%p;FIanC*X&L2L!MO7K*zbM#vB#hN+8tjzeE5h%WVBF}H{E#i)o-}6-7WX**?scl=>vqlb2$|M=qh;EVzw>>U`_Sv(^__3*Kd`%B^ylWf&pdq~mi7y`+)@S?z-!?Y`(xT-+SK=9(?e@H(h(}Z~o?cjvsGt-MZ=RZ-4ujzI;2P zB#E7Oh-Qsi4v1+034|Ks{QUgv>>L0%W#UvkMMzwyBjzIb5&uIHa`G={P~bB^cd=TB@zQ=o7um zJhLVvEg}Q^%mJ8)&M(Ygc;We*w``i5n{O}n$niPnEMK`|IRMNp%y$;2-+KMEjI3t8 zUT^>Yy+@85DMJ_?aou)j^{TZmzx?vt!rb{=ww#%sDf{L4_}GynN7SO2MAc(Qj=sF4 zH8NTsYSj1bJxW>bI2#&isKsult05wQh?KDafF0Yn&CV?xI(&F^bVOBSEJG-kE?x4f zi!K}*s!g3ZzI@4etJ!?=iN|ia<>zj_<>uf0$nO@Rge)fl6jY0i#?Y#@=QeBp%$!|t z;f^S=+w0_(m7(aiyG7YAiZacQqeW13oJ9#S1`{l!isy8iCP;c&lxcHKOfgn5t3XOf zF{+^yWl@Rt45CTZmY9YR3=Dyje9w9In5Vvr*^Sg2QKP7a5Ko_;o|~H|cFq_;00>Qy zP@{^W;s8*V^bH7!o1Yq>s>M&(ITT=U>QvR7%hSDUlpJ}wM`XPV^jERp4=9v>TMnwP> z%z{Z26{CL9L(l?Zp68Cza$Pc{B820|j^)lf!U$rZAXcw8Hg7(!+v&{Dp6T{`kdYR` zK)@=dS*-@(#Iz{-d94A6nHebg%p-fpJ_#>8J1{_I(Uc*rW@2iFgoC93q@4_aR^-`q zxf&v>0TNZ=3cw;_gINotOl(j@t}c>_oKb0=s%D$4B483GlS!pX9Q@;)tCXW=rdq4l zMI^>pmSsBXz4z(&6cID4*K0*A0nGsOyuR3Ot4O_`rNKtpS*9Rz=bU2_F#sa0R!=}+ zq@b8K$4rzIT8Na!3@J%bO)&x5MU9fcGiA9&O6rYdV2L)kl;}SfUa1~306@?v?AQhh z9`F6!!a~2>9T^!RW^#_q%CgL|jGZ&JsDc1#S7m9r2#O|-GXNlB1G6OM1T)nTLYC)* z=+po)(JKil6(VXP01Ao*%$PvW#B{c5BqB-dMuTd;r4WN+QskI9rXUqxB-I>BhDja{ zT;*_?CQgQe0->vL(rF4cs7jgB1%?hyAjF7hCZHCbV>2aWOqy2(WMd#gO7i=vYC#~N z)M8Wy9!oLcRNb?Xp2_ra2vs4gmL`kH1O{xV07ifSVo9^2K!}7Y0_kBULP*kP7!Y6- zk)irefGzDxlOK@NgJ%fn2$jy3gOK<~2xydCT1?(lhlj^ku37c;bIQ~?Yp4;B~);BFKc57K}>eTcVm+$!1U;5SCzjDWl zb5^|Ry6gV(FaN4FJTf=mY1D^~9zFI?U-;6#z56cPe%bi=lErp=Y<&F8?4ps+YmL`k z^@hLy+&_?WH@)pk=?k4S^3|lUQWi1-v|7WbPMtEd zp`jr$+4=m=dad!zZ{C&V^?s*=AjodGHTv*_5AWZz|K!P&wY=V_H`0k}rf3vR5daL+ z*2y#iaK8*5^U=}Kg~f$$eBc^+dNX$_$m0~(--38-i1oeN3kpbYHl&XJ|)G8MBRV#c++79^r-&E-LX4U%ZR zEJM59zW(~Rw&xe`yz|cEM^B88kLBKZqP1&QuUj+Js9kd51sCkyv$t7Wn!CIMgoJs$ zJ~pv*vFHzt47Zv?BJ#ug?_aa_ms+i1rZlVdLUFI_} zixL^ru96Hagkq@K{N-Q%m8BC)d;MM%W#<}=JkN;$oQD`d1Qr$xQjo_%)pIm_$b#a`hlCG=Jk5T7-E^5hH0kIuZXYwzgT$keHmv$HeZ zUa#L9V)6;Gzp%K_8X9({24tR zR7^}02^rG}N-IJDrluW{6)Ht&8cvv5%3uLQ0K@8&P=xeWQjBFXsU)Ruy5OxEWgUxpF_I8HV<1VDzW@2kdCbhaRWUL}ez8N=zmxNf$W1=4uK646g_PLI40D07*naR3xZ|0HSE1$w-{6iG-@= z7|2X5nvsY(s{Xf`DnXKZm@1eO8X6NJGOPX!P)n8h6G#z=B*i!Z1dD1>1k9Y0AV?~I zE0DF3rU+-O%8#UK9*oq}?%E*zXDRo?3{$)rv+2*~@YT30{jEu8l&Vw&B_rgta^`_& zPOQoYu&M;72*wJO=Fp_5fHn{Ur?)Z1z!RvZWGhtUG<6XGz%#minRszD%NMrq)b;pmMc>jBEE6V2wX0ggL!yCVrhv*umf8x@ zMAIZd!)CLdI)@B1Pd>yDV~qVWnHoS~q%|Bun4Fw+&eiL6RW(o~B=mynfGyQ|n2AIJ zQkA0Y0a}lJz0pMOhgejexL7jzsB-euwDU}8{ch22cLA+ibQ!sx*A-0^7^_KrFb!ql z$)%lc5@Sa*lWLt!Od&=Ba%MqeAC!SPL3yhwuVr~whVsnm>3Xf!@ApC=X8z&5_xC!z z8*jXR&8juKckOZPl0{{1cD~bXFI_spz{K82Tdn4DG1WJYgVqimy zW(=xPO;o-2Ne8Zgy?&?HFPcNmy3ag#BNLE9N)!RmB6h#|&F`#Rzq05nvUWP%k+HF5 z<4b*(5plb{cyjVYuisBSnrb{Xb9(!>ZO0EE>lMYqiNo{l*~NDI#eE0N;K;FKVCH-l zH6T<}u7CK#zYGtzwq3Ms>C&asbJItU9GN_Eyjid9-n)Bdb|&Fnvs$hOPygg6Z+`Pz z-uK>jA3S()ZhGd4Cm%WR;{J;+ymVn^VWigV%(Z8xW}wu!-|*InCF6hp+0V_+o>{$i zRYKeokYg;R|APm9#7Y{=_Tu6~cmAS_wyapb?8K@5Vo}DRue#s@LkvOC%sT`Gc7Cw0 zP$CvJCXTVFCf3AY5v%blK+$-!gQN)ibjF{Y_DBC444nZ&^C$See5 z29Z9YGqiTmtu==nrxV%CKpDYQ8Awb67$Knoq%KbZ65}1w5TYrQnV3UVQ9^c=T^G}F zAz%gy4x*}IWikZdN>W1xzyJx$O9;jcriz9@94lHphzX>YF&)QDYQ~-@P>>Kq(Wup~ zef?DjUV3?9e%iqMMsw+kb5^ZhH9xy}&j z&dMyycJJPYgyi$o+ImL`J%fOadNV^RHK@wTnbRU#^R*}{s%T&u#Y7OPvW1#4FlU+f zBIYm(0Hv_%D&VooZ_^}SL7?RCP5IPS`3VT1Xlg>}5HX!NY6gr|-T@^val#o@M?C!oE)RksoWA`*e1sybqTGzeipB%vgO z0JF3aLqrx0F=Tm0MutBNyFRR7K_cPP9%RopuG6uw;2C6CG7XclyplUT^aD+evX$+z!gao3HPJgRLODROg z0Du9aRMjk_NK72-#Ij2_4lxtwV2X;Cl+*+YHXu1DlS8Yb6`~5FsUb3$rob@+q6nIV zagY+gi7YW!lf)6A+7Mfc;HZ{Gs)?eDRKZI%K@$;KMG^_8!bu^dRkc7Bf0MpTR=Kj0 z_O4oc*#O?3o&i&3M57c23h1a*Y1FdG$rDC&<4rdqx$l1Wkw+eRWaEZ)cii#q4I4L? zA&icUeDkhvA3Stu>9Xbh7#c&3haY|T`WxO-g!29$KX}zuS1ruV64+vU?$DtFci&B0 zw{E}xz6bvBfBeJ2S6*7Pe)ZlLcb_~qb>XH9c0K<>uh%_v^iZ$Yn>;!B(n~LY@5TKe zc>itx?GOL((n~KneR8ts7tKaPM36W+AlBl7l~vTV_?R5 zy@m*o0=y7Zl@XZITg)LOIxrGp6&HzEN`wM9v2!pv5KXJ+JR^h{13Gd-&bgot3`9jM zN&{hPrBsPoRJjTv0!j~gT49TVf}n~iA*Ow+Vp1|BXoBW>e(dPcn{T?|+|8Tz?A~+U zx#zz8%1i6lZdhFG+h zI@3bb+z++ei$A#M{#7ei&MnNHnm#R}d7d}xO+;*WJ7p{lj0l(=BMmj17hQDm!2<^u z78Y7V&3e7@+|HekJ^nWL zcDr-V$`uC>zEYa8nRDC?XBL#AWXPNpnUDZKhJ$^unW`oPwU}v)!Gb{AiN)oZSLe@mJS{C>DEoPs-@4G*bJE}+zJw~u_+>@O^#JE3<8ieG%-U1 z12#^IM-z1pRUUrMl70je6iwg^_Rx1q`m|3g5Z%EGMp;oKD z&CVN2MV5n@*|~GAW>PCgh0$ugdt^OR=NdDe_aAenVKRo5plBb z)@r$mLkcr~qA(SP6hbwF0{X;>M#U|MKX(kLL|t!+L2jBN-Q`HM#yPD0y#R*v6y9MA!Sf0$4+oVFaZ#t z6+y?Tkr^~0ffYbzg^-)-i5v@ABh7eI01-G>NaW05!wjf^k(J}9xLF^>Asv9gSff#a z2%}s3%(!?ZR}Muivm^I|NPcQ^3vK}hk<4VX=PU&zPkZ|g9DMHCb#EOyl$z|H?*5x* ztJ!Ybf&R`rZhz;`e(}>AufP7z_uW*l)n0w|)uEw*zMkq?3m4yT(+x_IC<4M#x$>dk z`%ty3^5dWW>fwhUuU0$bcKsWFe7EnF=Fgj+HCPHGAWuH{f%o?I_MLa$3Tw?n4?p;u z-~Q%Zx4pBwyD~a*ItT*a_tP{J5hVl&j6m+`I^(2vDms9jDH9U_bk9%?n6Xte?T;cL zk^$t!8Gz2-oL6zMF@j)>0U!`jT7$DHF-!jUF*92b)b6R2&mus`)*=gNXLxd(7OO}j z5Q??dXjJv->2{JTg~ehe3_=31#+b~6en3d6%_i#8X&Ni7I!a~V_W_XEDy708*t2Kv zsnesM{M08=Xnbt+t6%%d_19m&WXTfW_dU;h<&~Ea(U?qYrIebQnmTy!;N_QIa?zR# z#PYW7uQR|Oee#b62ZpqQl`EHh;~W2CGdmL@%(tmpD-d9Sb{fC`&O0Y2CZ2fWnR2BR zx8tGV;hS!{<@x8=8)JOG!fdsoG&3yX2mZ%D_WRdgcfp^2{_csX@pdcr{Qv>{Ake-7 zfR1X#WN8}5T5AFB8yGAUiZ5+?>EPRkONB5qCW@l&-X0LFPfvqGIHTgs2pi>jnXw=g zc!5=>P$&{9L}9QDz!nNY!2r8s2p|N3f9mAvAKiD~sO*fu<`jOXO`c0&R zIdkWBbXH$^W!)2x{%W9qxZRwzRy?f`$qT%8+)hQxVHEfwa~db@+wQpY%BwGb;rSQ# z?s_9NnePQaWHL7GR3P(xJy{ae-lU zAqZq}+%i;7kY#2dvV@8e1&Opl7HeHyjDuZD&ZJT#Afgm7i*Y+?1Uf@7V|Tp(DqjIItVn8cxg^f)}LA6@G^wNv>zVY+lKD|yrF1+x< zQ{$(%y|(SL%Py-H%NsXrthbxpJzap9B^i0-);Z%7lWE*8SIU{S2v#XAY?UTZ8Zse- zB+WFCMy<34mJB$vR#CnnXUB9kK08ikeTg-Mc#5RsC+K>|b!qDFVk)R5FPyI#Ko}6R zEM;S(Fhoz;jA6zxYDLIJdpwWHEoF1xGca(Tz!Ezn3o(oD`_?HHA_Bmm6tT^Oz~OgN7NvbFmdIl(0OSdgLU7A45N4(`cPOxR*&FAa z%oo2PBnT`7fIu36-HV->fl&}7Gbtnaq5;I909X*tV?LOVDhiO16lu#MN^zC}8%-L? zDT%p#z%mmsh(c0~EY>0_Vj%(+K_q4Zca<9lwwb9~By!&=&WySF)(`VSE&%5?mVC~a zGg+zJfetg{F8~1o5{*qvBxxF_>88z_4jp_uiXyf=HrYIS?C1;YH{E{oZOfJ}9~>CE z@rG+kCAjX!>z;e=g~M+jId*K~mfLSzwQ|L_*LODKgc%MVJ~lZyH8g9u)@aRNxDbHZ zmf9_RVcUkW(UJ4dId5vBdF;gN*Is??9k<_c^3=rEty{HH9o3En^Jh&>wbwtto)BBD zmiBywd9aIE5Z!Vf9njC|phVhQ;}{X>h^_#JGbhT-j5qF3K~@ZqV+<1!c?gzRP%*o* zFVIm40BD6g5kdu;*{zRe{{AzlCMV&dQkd6EfmlLf#LOCnIsayIa%yOBaPi_r&F1vB zZQD%}M^Q8}G11lASF2AJqR^z-@?}fr%$|Gf=#i~kw^l0EYPBQ3yFJ~GTVMUkS1-Q! zqTas2-Me=+r{kSFcMc8?hGDpF-Lo4vzNoe5cpOTpD2kqV@`;hL@wu~SkB*JM@#da# zxi~s{>e#U(m2#<3ulM%$O-xSa=NtrKQKX!xha_n$E(GD(Yp;Fy*N+PdC@NK}-F=;v z&MwGIyB!CfFBSsdueaJ+oE$$o(&0gG@4)UoulqsNS*TV^C2Or1_9I=bR0SYOl3J}6 zCrM9dPqWoJdgPd|v?B$1o;Ni)6-5ytq*>}7p+w60)=d&KAfPDJ?l1--q&#;x%+gE= zYSM(@fRJMo6W3mIMNdb^_Sat1kX>-inxYTKkM1i3lhxG)7@RM z7(BiH_1fs<+}TST@$}UAl(kmtpw^h~>gjmrJ8%B!&mQ{TfBbuIcVFLNe@91os?i)C z=!?^|-E21+F@bxwV;Dss;0L-827=%zKaP_uV<6Gm&)6Eap|6}UsN9*FNGlBh#w1AE z(^??!y3)!gA_Q%-3d9l zm?cY>2t#AKz4H9?-q^c$;`C@3Md%@duo1~54E#dq6OvD43D}CS15FfXNt~pK0J0?F za@GPOtkKijS`o2XYI7ot>xltG0RpFu6Om$OQ344lAp&9)ww4%DB2ZK)Mjm>=V#GRo zngWFcq>wY?qi+=mDzJbI83BTL%FDfUfC5OQSu7i?l~&*hu>cT?0xb#*SU?b>G-(Eb z_uhBEr`>M<^k+Z0?6NB^y6~cr(UCBU>Wu~<5-NZ^_UtSOESx6nDP66U+HnE^S(Zgn zgh*Ku>mYQ7Ul9PLEKQNf_q;p}LgZfMAd*2ws5xcv2~oL$RVe_sy8$sd<4gdEQ7k8j zLg)dIJHET|$%%GK0Mr>*I3j{lU<@-0X(fhOm{+Fq5ZL;A_;WB*qwE1&oB6*%-Exfu}tN6jyy9z{KDp ze*#F(435gBk;Eb@1fK{UgH=0x02=|&KmuYBjAe!7CSF1WMMmsQ!DkK*MoXeS0~T4d z@^j3mu`2MGB@+VzN=PGF6c8XJD`MGz0HOPxqge8gGETLx6%kms44Vmox^GR`nWmkx zqD46!2+4JUAUJyzfKy@>L6&7iDpya%0Ff1|tow~3kP;DbNpfcw2S^Q*La-)ZBQgV$ z66Lm{D1^caXGTya$jvPZ9AicVk&#_zyZ}({1$H`SUJ5v~K0-1AUZ9)J*5=KxoH%{5 znZ$k+6|2>X((Bj1_~@fgq;dPmkt2ZA+cmIf&!J75CgLRR?;m*b>2(K>9RI+3-uuIQ zf3o%UZPU$GsPyQmk?A=3*)RUh_q`J*Pjz>76f33g{O3I{J|g0KJc*X#Ah z1sANj{r202hiAoU`qGOp{o?*#q{c*kkk~{aiPA}$Jo(f!B35hN+uQrvYuoql-_Ojo zS|f@I+E<_m1erOEitRZ5?bA<1VPrwHQjs4%`Pk#r%_f5+nF*C2g@rRIyPQ0re0Q&a z!dA0=aPL0tc`O`+;k>yEzW?7pPTQupulw-9gQ@_al{=*whNqr-;=o(`<2WuCI}oL> zyR)mi7m>zBMgm_4z7GiHQmI%h+SJDF*6EYS%jIGmCwW3sL=(lW7Ud&}wrm^_65R^g ztrx@qyG@y6fN1x2CP1;qx$(hrxe&hp_ujp5PS4-`e`IUxpGX=*qt7Yc-4vppfg0n*YhiG51|SImiQ{=>Gk|XQCc-@Th-gJ1kC0-%M|NR~{C@=J zvdeL2BB*jMnm7d@uNraAPXG{6r~uKjMWw{%sUZ=uBB+UtMMWqMW@-_H7*a$lj?HPA zB~95FasGo=7Wee^W^5)VC(b?ZJY!6MfB!`nuKCGNe_WrMDtQ4aqClr{!p4x&B5Xty zP*e!D)=8YONqc%ai4RajjEt~b zPvmeE5OhvTg#gwH3wS{^-HMS=ggh^>%#DfDmF|929s-16D9or7yU7D`7|0n)y3#s_ zth)gG-3kM8AE&iSDGMwp&T}p-agrgR7|DR$w+E1)5d4sc$XaGdnZ?sSAf;I> zEL!V=Ul7L3awebzGHWomxUyxFKXd?NJXLND*^$n18c0c1_8oISyw9N>6C4fw2_n*OGH*ggscbPIMIjQG~#P2zKv>bSs<Y+~H=ymrw3 z_C4QA;?svZP!rSS0ZD^_Q>t{txc0c2v8&yN;hcA*Z2K zD1^!%9UTu#sl%3L(1BKR7y$e*(7wOv<;|^D)7QFOh@vpGY3!`>GqN1#ek>OV z1gA|gp$2qIGBIEj=KfV<4I+U6Gi$8@^5hvhoyv(VZdgTRV&#)btUE#qOJ*%;4O)ZJ zxfMx-t+nF#fufP}==zKq97L?OO6iT4qA8tF!aMH5V*hy6BUi`EV(sKl`&UA3Jiis7r{XNJj-VS)bbY z(u;%r1H;3^X_okrpV?F_d%l;LRN8G{d2u^6Y_-BL2n(f3wOSFGnygKg3I&|WS_&I? zHRh-xX9PiTZ#R`k#6-K!VrvBQnqHHdYPH;$PFw9}cW2M&NbSi-pFVi>t@qygp~m!t znA8uwsgYWxQf;+b9@43Lt=_2j_4H1RjLe@mI5^ZZ-K?23VX#Ol&0R0r@A^jk~Hb+=nBJvLKyDu zBp{{K>^Z}p=XqN1KXh?j!9y9SFd#T~8?@ zAZsn*jQbz3tGio!L4CT_(cMul6_1`gv3t)OmtKB_+oK{%yV+>BrhNx!QtT-&W8lo# z9Mfrxv>RDcuQzVL^_HuzyWSX+wvxcp?JPlrcDsG(twSeH92*!M0FmM0!S1eZ7B5T4RkR zr2r5}NNX<$v_kC~1%<@|3Rw__%rc9h@B0!k3r|c009dvbxZtTI;T%zK zErH63X4X1;4bAvbW^7M66yJ>$hE1BK1X-X%SHqVYE6jf2D^C+BV{EH6-Hu~x3|phM z7X(4*`^18Zj6jy8V65k9BtikDl(jaAV{5rsj8G}VHuOVdxL%)XwVKw5)>JGPwN@s} z3SpG6nW{~(6}D{IcvNb_i~s;207*naRHRGgN~uyptg)Ck z0ol|?O-ePJ&8f*+l4YLfMNw3UPtJ@fpCMhXhEEcuaaT2G^X=9BLc2ujOA2eGnx7T#y zhy`J>Lb};#G^QIVL+A(AWX*P46LofUmZE}FEfl(}1tTg!6hTyES@M1)%$H@kq)O6^ zo1xRl^!DxBw{3r&D;$MEUr*nu zV-r2yofEaGb}KHI$|pxhs?}n-Sef11ch=IgSYYdGTaO+&;)hYA*}V6@UoKv}=!WaB zUvc)T2Ooau!3Q7is&p)vKfl`9v1`}1BuP(=k815*wdT4Fo7SVkW-FdGFuZd4Suel* zN^@$Wie(|qY;A5!&j%OD7xPZnM3=M2{Bz1fSCHSfFtep~0x)T%3>zSv@fs2XJGYtg z5J`)LEX_PG6flTtrpgkWch}eq2?&%RsJv9w-MoxwnO!R`FlRuDNGYwAcHg;Ov}ECB zmtNA_+q-4UmUgqXe#54VFS*1Dx6^F@fqjiyV`6-=vs&>y?T$L6To4Ta#IgW7x0NTD?8l;M);%nPqTe@_~bUkU*FwF!=387XR6sIOLmeVZD*v^}`U~+OY@FUOjGfu)% zp+F@903%suG$A5aij{3Ub{su+th1x4NgHF(`4laf)PQyiWDzTXB$jlb@C;eY0sv-) zwMR(cX;n{C03gCFOMR_9r4i{jPp{kb;)eeIaxp5#?Nk%=_0O7^sI}Ye!1ns#Ob)|dbM6CeMBzyA9#w>rw!+T$mVJ@@Rh zani0g8zZBqckkYfpx0b*DNVOdpEz~lg_mmICk;`d;8TznBM<^YUq}h?uJ3S z8;0gR-yhz8V6M5&b)R$Zz1Q07)BlzhMTv1sYVWK+r(~`uS%cE5KqEKvEuJEFNX_9g ze7BYPyC80c{7bLE@bq5AH~#qOQjWGq9(~+z6hQ2w@gNCExS~9HCWb5sr1*gkYd}*B z{#KgQ)NELWl2o?8^IJOx<1o&>d`c28y+lD~Y?rPDv>7^U{2Ws%yRmtepSvRt#PzeM zaLN72mqVx+R2R3E-f1=ITJgQYx5N=HVpf`UsBNV+tasa6mr<(mcsL)*2z~oLZHLuD z!_*+-H$zv?ye)yS_g&-lLnl%pw+;f?WSx8yNJ@y08<{6nUA&mf8!_Jyo4I`7_ojOL z4tQ%CO(!sqTQBN#>VJir(`EivWwI?>TzJ3C-+EbI2#_K^eJE@FMQwe5O>L8IRjMTw zG;m>2YfG6i?4_7%Hfg;4Q%GdY@-M(+!?XArGH^&9lGYPj{- z7rvlty!I>Y{E6nv1f@~qHlLGh(LPF;DE=h39bCx;e{gftk{peaS1Qk41^?m^6~v^_ zMW20AsznfgE%J#FWnACDbRV#Mxo*ostP3B%+y18QR z=hIOc{3^=IBzdUh$(9St-mdnEM4CiI{&Z++DS|@@*`wJSO)fX5W^8Qr%ko9&H5JE$ za>sXT>%B@IC*B*mVQ)T^zHF^p`BW=6XXv-3H0z5pSn3?Uh7fF7~X;ARf*cCnoF*Z%id&m?e>dn&&PgIHGoB!EW{pgRmjzTdA=?8#!CQKN^Xt`L@E&~_6=j% zv7rSDZNKU5fTSq-OMv6_m*EE^Kobi+7?EuaXxsjQY~9HMlKOTlpE~Yaph6wzumBd);C`Bb>$zA_W7aMh|H}TYzljrapM?Es zqXm(XUJ@Ita(Q`WSm(jLb9NuY8<GM2?i$dfL|M4)%`(#eE@)x#@{i`AJ`-BQhmR6@zBj0I3hS&@ zQcVYmUKkuKw-TvCZlJXXQO1GrA5GK^qger~a~;>b7Pt4$0Gi|^fEFij%u=hN&wDp+=XvPfjJ&7)-SQZ}2(+(Lo9+oAl-FBS|#=hME;Ee;Wc@3i}^ z;iJX{#-gd8!5R>&P0s^HC+&`B4-0%sA?EQxs;|Z4>k{ALJPtgsWqEpddUEQ&+xdrZ zxNmUsXaD*8F(f2Qbf$-q@xLM_#|D&6UBZPY^=pIY^^^ry>yaFB)%(>+8KqS*uM&Lp zkVm5>6NH$Eh`>0)pi-Ge)PwNv!SVhK2ZHD9-j@0bZcA7NO=TNXykVRSl0iaZF6CbZ^(g@%{!?!{f#Z;?u7!N z2JbuQ>cg%1dvJcPARN+76f1i5g!J<|33{ws{JX`jUF3W|A%626t9yj2&G2Vl6+RH? zeY;aG1|2(YbI#=3ND0Szg{%K>`_gR<6EuhguS-vgVhH+AfRFZO^tK6^)gOc9$-k%l9oQzew%|@xCL(Z)>K?{Vr01911YjL$tc1R!;&XXsf4tgkZl;MUI@;>$*?I(9Gs zt$jALHAHHMn@-Dpx{5UPJetvY{G0Q%)idoy9I7DPe!xJ}ep_@Pg7>pCCtxo&1!Cm( z%yoh}$vSk|)5F1!IB!QTXIhzR+{^_$9x&(l+zKNe9X(ZbQi{k-e9rc?vo@<6?RM%zB=r^7VHuDh9gccbL^EEz#{Xvv`~3t%#|BpHE&^Z3`5$ zqOJWobEZuEHceFyG8h_5Vv8F3ChC2prX^wSgLIx@sz83#nwzj7v^TP>Lf2(BK@a(O z(>_cohdv4JqwJM9CWjn)gm98?jPfd?p{E6e35i^^OBb6p|9sQ*?iz}__{ zk!;b1*V@7@QCsH8IDJQ!-BDbJ^VJv2uA{dDVd5VIctq4Q=+W6zD$Duzk>WR@Uw)v*L!*7SPy2|n_;Y`1c zZw0@)fR2rfY2Uqj0g8AW&2TclpVp*0x&P<)0{#Q-`vNVC^oRp>3Mm1u0X@3*PllIR z__i2fQ?i5@QaUYvN+rMf8JI8V^GPtSNf4m2kVZfl;?YS#DliR2hBx9amJWYd3vKhX zbGSWc4enpDB|0vh+o^E|cd23C&M-6^Ry-|`wO6@(L9lame0VPy|B_o0zEJBB&+_HZ zaBaFRy9&T3O3)%OuCf}*Y`QqU9fP(?%%#`eQ4tO8aQp{%`!m0L1BA*=5%F%>V=aSG z9nE?mj72MU7%U8{d6U5^mOu!Az&S@aJ zf~IB40Wqx7B@&3kwX-R%^1sL~&hd@Zx_MCID$| zL*w`FBIo{QD>d_ZA(RFsFy7X-*m>tP6A0vBB~da%<7$7p_Ix_Zo-PP`MdN=kE}8My z=@HjHa(9_~|L(TLX%-A8Nj zAo8TmGt9!IY7BIc4BeOESCo8We8=cQe63%G%KBro98?=5i}i0uJlId`>L#Zas_hoW z5zi|*h{vrK=HenDVQ6h-Dwl~6AD$x*4p(zS-F=ZPF5K#poHR5_#G(HllG z$Jw;G&R*FFQD9X{_{6yJsp*XrDgBq|_nCGueBQvxK&A)|3X75a4u6~biY(`4PPE+0 z>66FREYB7HDF!?-ufyFXP0hrvBDK?dpTQS?FFtkpLnwz=fc=z_(J^G% z<+cexksNjgJ+|+VgtX+wL%p6;OcR*P-nkWVP)^LQ(?reU7-lSEF9rFTk`nLV}Cr=Sr`ARnz# z2;sjD2)R*hI9}k}ddhl!SDapy8y;=VJBJrlO}!|u%0}rGS_X4_dU{@6UPFu_{=4yc zF)^q*rfyjm@cw#l z-y2hN?xvbMhliaO8ckLIM$m&ep0nd}5*^#evF)huxd|y3e3Z+4?&9XU^`8Lf=1a)*EF+e0VzQKS5YQx%FYRg3oR#`1Er%e$1vgg97>8?pkdn6g0GI^Fl{eAU!MfrM8whv zJ42MYt^LVTAVcpwd0Ox!UAR-LJl+@}v*5I-LL5Qrwp$>U4}+0J63c4 z3FB-TrIjx5%bDbgk?GIw=)E=yRo}73~ohB<4RlJJaOVSlryY znh_Nr)c_FvIdFx?Py?6*s>(F-)FG}Wm(5L^1Rn9HYR|d-lyLFK1y!-z%_&>LsNxBN z2$$SwkOYIC+Z(2|ctvT$>p+)>1p9`dG#;-Cl^~44vcl<49%F6r??y4GD5XFk2cWJl zc^sj2&+3cgMEMhw<{>HqDi$2aC||3WZ)x?knS~n4!wXZ!^Hw6HV6eG4SA^$4w1f z`ySs3zJ2p%1lcP0^H;V#m>fSTfxNCp;t|jD%-1IfE_umaCFA7Kg3j8SDP}oeL@eB` zd{tlj$YHu^QuENsdX^GVJ1ZqdHeK1))PD{hPJw$Q-y!Pj)=WjFIxXFxLCGnhRlA_($g! z)pwW}v;>6My8WZ{g+IaPCx=cI$*XywV3)F8kxzdhmelk*H^X8}6z*B%k=}M-U1{v* zXdXJdyri`7hj%u-886F#(mY>`BQT!k&I}x$eXZa%GYHp6ba(&UemmmSTJOG8s%e3< z9XZ7LhH|%3l^>5rtlAoR%#ZiF@nY1|3iSLKVj_C~&}Y@AS5Exq?ke&7ei!dfy?wO6 z&}+hOOH$WEst_CdmlCxY^=V|%&G=sz&KI{+O;||>zXy>Kize`UoCtc{lF;0Z-}m+P z2@4A&M`+rwQZk^;Eh^ap6TkVJe^W=xS~PmHTwZ4Wp|cQl>}QMQZ1x&il6!TlC>Mme z)um-&*MI%he$IGC9k}1>kn#Q5e|4XBR%rm{#g%`)kx4`0m8?AU71ewzyeTEyv-`$ckY^^D(hRLOR4Peb0}WQx88e?(vd z*#e;^;t$_SHO_oZSXB)(l0ghMu&;K@7V9|8BW;4^#E4=>usXekXfG43zyfkhfqbQQvkX|X3;|VKfOW?$?+fRlB`a@`DRvTk{R{h z|LkIMfK%@taFKRZR|E4-AB^5U*dAc;d+6yu(f66HX}iZ`k;$4dUkt{cgNW=byYf4& zPO5YGKe^^;gVRFWgL1p&V(fcU4SmlRJq=xa3j9y}#0A~=-Cp;PG%ifd*nav^o(=VH z+qvZux%VyA8m)2I$rc4%$YfEWQdUj)#7=ETq~n*niK=Z?W){2mWG24ObswPr)_XII zeOXo3W0&3MPBWi!9(Gfq9>>R2`-mpjxf%O0gI3cCz(Lsd?)B?K_S9~j1_uRYQX8&w zKY}yVm7f{?swzO%279*GLxlcUA;+23$79bl;_Rg=N&E9!elc`rIi?>wqiqNIG+A)d zHRcZAyQZBShCBh~8pvlhT2P@@-w&`l7zK8^yL+RiyZkW7o;{nD93v`>G<4qkd!Y>z zdv3ijUal?0mvP-5em(>iP}n3Krh^{kfK>dj#5x~x^qkwn9pKY|e7L*PV+y}1jn8EO&lI-B)iWrN0%eR+hmQ~A}Xh5;C~hs?Ppwn ztx%msc=s!x_#&wFUf&DVCIHtZUu%w%V1!ex#Dzok%0xE6=%S@1tScwQ-;@&RlUo1H^hJODErzQ@$2|g0`pt2V#NDO@5 zcu9~eWd*Y853MoR)1`ZFkgWQ0-8(z&-^ZP>PeY0aujjr8N(`*uV1ahSf+RS9R*#$m z?KqcO*emM0rvTCadbf8c8i2b`PL#yW6RFxTWzpZS0>q{B2zXug#FOzI+p4HC?77r& z58=?;!J?~iQmn)R(^BaK58XLE!f7)lZ#G5jkrvx>)Tv$|RD5(Bb#kLXOpaILS{OUHy?XoJ`)mKYE%GgrV-%YV zt%k5z*-~W+T8fwOL^2kLm{sOqhoN^)+VB7epu?dzQlrVDIk~;*WCWC<_(c&=zVme} z8XwVUBP<}O1dG|DgFW-Ru3YU7|J5J)wWvWm|1rzg3LLgs4`H`D%#xiJIx)%_Xk`wfQsSFwkF8-cwaCI1Zd zBm{oZRwR(9GjvS!x7|?MGOs3S2x7ru&=};BHpY*Mj_n)qs8$-P;sF;-kCp7ki`wEE>F8i5sa-rEx0-@lKlVyUFN z)uLrKB^iF?0vKHbbF#;z&H)(srbQ}pAeXN{B*(L$A0(AGgYv~DhtpG%1MmHs_Z%R9{ zb#hwne6=?6^WhkGD8KTx4B;+k>*%i8(Cgb#yQ^wueo?riUwZGaP)V@O&@51_wJ0Xl z%=)PBq5!=~`QORuvrGIq*V>;NgR0#AmwVO^Qh!*tjv8eo$L;!#JlNr9ky}c#va;L5 zZ%8dBJs=KsCs)@9QKHN;Du$UGdkUGKoAz%#@Jn(v(<{Lp$K}>Kax~YlJL=|uW|9}BYEv!8jme;Fljri0B0$r- zwuDvx3svs>Ml7B7URC_D_Qacdt0piaakl*57X_>%S__<8`XrT@eT~hN(etn;;YxR~o2 zm;;xS7<^k5vj5{Po~53$Y^xiHZz((Iekd)M_#*GM?oQsE18XHduZlT}1Y_;FFlFv$ z2|XIh00Gw_$R_2Bo5MrEGcxF?@lGAH1 zS1%iF`08n$v4HjQF3VUBeE0S$hYq2}c0b7vFvTQ} zuNnH8-8RMLsEK7=TIr+Y^>@ZTNz+QA(9wnkdeCCfNztKY;JqhZXf90K#4yoHKZm{x z;KHJ^IQJjVOd9IbFG%ypBV+v_+e2u}&qNaPPGQ|T+dmy2d#ejb(FXr&rM*FztRNif zfoo%8VPe#3z7B3MQ~i(&Pl=9bi-i==l3-Lo#_cLjkI51>gj{7%aH zS;}?D=%n_&>eD71CYujmTqsd)z3R)ZBZK|#Q@%k2)A2aOrjJ&P&_FXq2TSTX)-8U7 zLpd97x^#@azdSvJw$z`1A6am)Qv@-sX=`ZNa(syk?TCojPMMevo-ga1Xv6=N&p0N^ zNaHBQR~aE6wyksg-diliaEp((&z93Fz{vkW2ne`NnV6aN-u;a13qMC4L&BH!Fc)t-3CST zQzS_&?$ER9G*oU$&&ayNb+m4^=6+9TpXB>@>G;n1qL4pYL}c&kiJ;_5w}kyFhs#OM zl|=XV=Ysss4v3$O?SI{)opUXysNT`ygCUG)C7ye)737MMMu_^^Ok`{w-Zmb_yK!>s z!;9mqQQn-LTTw_KrEFoinl73jSCzJ!sfW*gw2>1zk%`|`9T3Pfy3SOrozG(C94{}y zZ_Vh8>t?5`&q?9JSgmj6tpKKn^t z^1p6&&L-cBAK2N5v%$_az0iWB!5%j)#ax5rxge z@=<)pru3N=x(4(ae(~vHfo~1zQuDJ{M@ax}D6M+dQMcm{p>EXx77w#tLQ#=k)D9DK zUI``dx_#xXJfWnhGGQWGIb5qexQSwS0Mpot&uKA^oeX2_Q@K8TcX>Qb`Y`f1yS>6C z(~=+Ic4Xwal8LPZn=d!4K9859IoLa9%Ih54>Qam67dL?MZZ{bEmrDJYou#QLGQAZn z&I3dl^P6yzPEKbE^3$T-sxic!xA~^o&D>fs3?_S-*QAwg+h1rvNOASwzUIy68FFm8 zy&I}G^mtnSHtisCIX(si-@5(-!loRXx6{QR0C3jDp=-nH-BWhE;kRi9_NB&CP{TvZCx<>%Q!)JHmcN!o%!Lze%(+@v#|K}Kd3O9 zQC8HQ=%lLX)%wysGDS$}9(tE2dtmZ(m0R6pr#>}1k`dMGOUJTETrYaRj>~UcOfG+! zK0_89+_dn!@{y%Fk^7ikgOYz`fvA#1tOwzm7D(zMcJ8PT#7 zj)RlE+chH^yP5qtqkyB`o*uvk#EGccTd>Yq@LcQcpAD$hV$<5$@$Jxcs!f3KcD2t+ zprJ7a2AaNoF)KY>PI|668r1SDxTzw=Ljx-UB`B1{29?lxTnQihXNg(_NS7~;b!&N0 z3T=460ez)O88sOETUkXG<`)$l*skFaZFV4#q+&9w*z!hE)_^6+#jK(toiljH{_*Ty zy!kPi+IsBO^mfsL{ICK(sgQ7sx*q%SZ&c3luiv>Pw$7tEgB3xIetr#Wb*YB~XjqFu z`0syEpyR%LnQJD)h$^3rj-B~34)qI+RyP#%vm)eoiw59Coj)5~1%&%^#M9BiMk4=1 z{g)29RtiTJxQ;~lCEop z}9QZwh#w<1%g97Qso)Cx^yWB9_413xKht4bF( z^0JCiPpi_Z4?~daRMeq2u!y8zvO;Zu%nz1)Voje!QAlFL_e*qKP#iHx*{P6TRhKY7 z4Ti@LGf8}cxU0jtxx;@KSMrZjO8&H@mH!0!iS?Pvcz<0$R-HCMZ)i&cJ=(TD;cl6S zo}~~am#!;~w^a92kJRp#A~m||4gh@lFU58yR5Y!2{iEEg6YqQ60S6r&&nAuk z8kD27i4s`!bjz@43Jl zS|G;11AS7SLwvj0{U@6r5v*?^XZ;sX>z9bc@FX$H=Ur&{tKuQhR)u-H;m^s zklQC>+BkY~JDIFPU(Wz1*YxDFtM5^U%;!m5g<<*32Sbk1Vik z^{S#_b(w>4@S?nqZQ7r_{i!d*&#w(2XMlB`v=YB_A!@b~Ml$#u=XLiEFS~!u{61Q| zZQ)T!kX=!=7IV3f@kDq$4&Q)F3=7zte|P&H?;*tedS_v?YmrYf+=-e(r*T{L2992H z$*IK(lPe4E9$uTd{r(hn`+iZR(JDWkBinPPa0=v;YD~E^ZvEG8+h+&$?O|6UN74%T z3JKt)nL!m%2XV-({?0Fl`{$RshMFjBTLi*Mypdn;i}BT=#_2`i1d20~Fv)QT*#a$C zI?SZwI_GIGfLDKHwS5#q3Pe$IThwQ7RQypL?4}6&-!v4nj5qr+6Q$r_S$TPpMT{NWD30R z(&k+K_OFfRVQqJJ-oWVu_k{`6IDs+x_V%sP-SfJV$+FkqzCYagnAbPYJ|qtt(S;wj53Z z$NYZqA_PB>nwzjEm_B;&*ZeU4FV{-;0_bsTeld4Hj{ND8wMl^E(#3G+k6EL}Yf&B8 zZbj?!+QdfIiqVjE`To(+(F%0LzVd`J#t_DVuZy`aqy;mzGR`bycu+xXj7n-{qjOZabS0xYQ{1H*cbgGG`uW*I zJ25okVj>?badL!2-+4KP<8L3hP9 zG!5+($T8w#JNsg1Z091hdg3fCEh4+3;`uSU(te91@^)gPdiZpRtK)8vU6>OXb@i7C z@6RlZ#?){p{vf`Q#J3qE-#88B^DBzw zXAi0(=(YQ@U>3@rM;w}#oG{cwOvZQxBi!kf5HWBzXbkE7_Fp+PSsq#j2a%sx@&mH!pKsq%Q;Ae8Ridd9rWK_{*%ozge zN%LG<2fgyj7u`h@<;jChJW8J|8A49lk7q-ycMz*^=+PoCa6*oEA=Z7g1g!X4f+oy* zTKl_=mP3U<);8B}li79LuRO|IPP@*|s--681}!{PG$)%!wj-t>H1o3XYTJ!I5+yS6 z#|#sQ!Qw}7Uy(w-E%z}CaK%{dSPvCOR)ytngY&QV&S}a4{(kZ7mBe$aSq5GZAD6 z?)-d2i;a~ynWD)A!myecB#Ho?o)2+S<&fu4t z{?G#_pAS+S^~b!5QGJtBrhRdXisI(6%?a$lE4~#M7hfvjr;1(#04V){1^*o{ul4|$ z$WgLOQ(+V-*`U$KoqneNViYqkOGtI2$I769Es#mdr}W9%TCSqQ+Sh>|{Lt&?S7@$) za(V5}nK={)QfLzt{NO)y#m`>Y*Kd^`?PGWJi1auATl0nM$jjE!?Xp7n#A|Eo2q1!= z)-vHye5h3@m008}e6O>|uA(x6gFDveY=3w-er@M>^8lv1c25~V8mQMgJ^M@9)}_-l z-p90OtEj5yt54}i2rP%{ntj-9G?lmE#s*0P-(l>?Y)F!cXB|D^rlwjRTAny+eB8z@c_b@r8rZ@1}Q zWK`)ShoPdmh>UXu>|Kn=F0O1azjO%jo~!N-6VZqm(H%#&i9%P^f*aZbu-R{B`Ev+~ zQFcp`0Av+&aWRWpVj^7J_cR_zx=qk_=|AERIDCRu%)8vKw%zMWzi02UO7Y(g!sJ|S zJ&taO{U3$EmUyenklk)Je>xiQ-FCjdqocDy;C0bPCoKBrC21_e>t(Vrzpsdn&n=N* zNak5+2)$T6>x$CkhFfEf#bnW7#A5YIrGIfa9A5S<>!qgNsu)!P3Ao*;6>8W{Q_bir zgJ01IdfRFLCh@+}-4wMrgwJ?6hYo8z!Cj@xFcM62TDz=4^0 z#jIV&-4z$Gp(EFXD#4^=m0=1&xNOY4?4C9}sGEC*n<>2G-K=jvLsew#loVO`4(ESc zYk%O@*k-y;GV1J0o@@A2w76GxN4pc;Z-T$5%hM;kB%){N5?<~_zlglYbo)y3iel!e zEbHzM`ggFo@Y%s?%d3dLUoQ+ZHW=0yL7g%Nb?`p~VD&XjxtKR2Tdo=WPLsx74+GWl z|0Ya;;i8%ABk$ZBA-8ub`UQ_Pz_PpwATz|nr9=fecL9g9E1mxf$Q{Xt1^54aQ728u;ej2 z#MLrwwYNL4s|u9gFsqe!MCv7eSR$s*ZXkP#)wE-jd41+&dsy^)&@ON|@AcKfA)uya zP11wcjesfMuMmt*iXlKOfzGKQ(ZOHXgwIG27#`vlPe=d*>wO?_S*#*yh?Okt!HWB0 zDx>(FvTkwar2V||`5fB}g_7fD$LVPf2qv=AaNWS2^Ifk%l6$FQoz?|(?bM4dP1Vg8 zynlxlYS;oBWerkkl_InX?LZ0&qIZ43r^5~jOv%Lu zQIpxlFsipa zi+#QiOHX3YuXo_ip!;=Qi!ogO^1_U`&M;3bl5p&zn>ME?CG7XB_4m5Yw;mvZu zFD(eLT=+9-axv8-2CY`ZR#Dw98|uCDWbp#X)YPl?)zd8*9v!tCGdYa`M}4t6Voj_j zkWPx&`zxSK%4L9o#YWxqd^g$x+ZP+3nj+cmj;7)# zV68r8UDJo{mr8sOwLDvYT3mkkn^-(LKYTHRdHmFgJ7+@X<3Abs+toEW<^z#lJ$vf4 z)55oY(SUFLo=+EYsv_4ztEdcKdDt814H6ZyP-=+;)oTrBNaqh-Gq?lKw3k1S8i71#k2dvpMzG zc$sBn^djtxHZNS-{@Yi2oI%mBnB7T_{vjy^8dL*m$!Y!04-C1w7_0Y=avcD|&ZhapHdhb!yux%BpPb!&slz)rOc6o1H}VN{_eLG*w2RoR{?5 zPY`w7j0`*EYk?6h-Yfjiw+DbR4sY~TX46B0GEM72J@#xxdg-V^^p>ys-n!!{Syf(T?DOZBWB>}U1xp?6T7Y@Pjwq@rhI8EGuPhle}TCT5-AYK`}_M>Z-ma~8Dg1dYxAtEOYcuQ z?zYU|f5N?GyZFOJ;^Lh2aC#q`B?_(38qR=FQ_#TqhPEO({b0Oa&FAY%El#cO*e^3F z-srdZd7Vs@GWWDo#+#j7gX*tPO;%Y0yudSQztn z+$eHqR?U7MJMrzmVzpxG1~d0F-;r`@D^ggHlWX<+A<~7>vHR``bn*ri^d8d8HlK1+2b@p+^yVJ7h zzFjYO2dk%Q<^VyV_g7>APffy39Y_CiM5pyiH(4ZRe(XkV{07m|(-k>@a@AP;pVKg7 zsRb`{p<)1X-qR3zG&3gtocGF&nBRUzdo)bW|7`g-o(>eVQM=$!m@=hN?Q`U+1lJRoIXU;G6ww7uxw^a)zVWDb;TEkoMbP69}#He%Gg5z_Ajih$mCE_tqa^cRai?g1|F^<*8BDSwY87{A|c2-5e+-o%L~eYn-Z z`(vKJYXZ5A8ql#c)Hu6!J&zMV8_JU_WsCo`DsBFvAVSK z2v|ZmbCED7|F#w))htSKN=nvES3I$swPYPfRF{e^1_w+ zZ9X1BQb0zYy5 z_v(b!+F+30yuQ6&JmG;vnyKVGC7OgR-3J^j(0|mqONE0G%- zr5cqp|Gmcu=O80C^7y-r5JOVgb4yRRdo&vCOsjYO91iUIMFNUS^d=^NJ3D-2|3&R1 zS)jqX6X}h1ndDLF5k?7RMzGnCuu5Bkh6wF?O+(b=)Q8BSH@np{Wg8mR=F!zmb$n$b z2Bsx*_9?g@9P~TPPNyU0JdSa&ZeO=(D=L3?&IFJ}GDn|dTyLtt_*S;-uh+xpgH!0Q z4lkB?)Z>Q6MrN3bUwIkFSy}ywwu308I9qMrey#M>Rs^~2UviQfuxX1Rl%}-U>8HW^ z1gMeKrKnqBe|o01ercI_A|evQQXzT;B&pc9u6m?D%;Gc$6JtgVImvh^XF)ZA3ek0X zoM0*Ol39Cajr)0KG1npGIaL)^-rrY2iNyf6dw(`@#A-^H;tiFk$K}lr<$Mw9Rl4e0{;e}J_=8XjVO(s2?(#ijoo)&GXyc6MQA z!j4C2>jTKm%}wlVmnd<=qG81ksnh<@dD(Nh-s_j@w4%?JVqeD=Zs<1yt!&%38|&7# zFzz}nI;hCW&J+;#(vaq4QwXvlt`3xUgcTFO z4qVN3=78*S2o^~GzaRNJ;(lykpJOwQ#^3}MHa?TO6ag6>pE_gEHpIOz6gIVqYtS(e__pp@V#$( z;neXtmhk9a&(6izMm@aBxU%i`&ftD^HQ*7zF!-*_a1&Xi?Dip7+?F^_;F%N_`*l8I zD(gHCAF$(#h3^e7THF7Y3we zr?m8M(?`r#J$fR-m5D5L66%v5STlNx`Dpa0J^F_J;iU55%90~D=^t_L$2IoK0nbs+fLow z9jxMEVW{9Ss!K=e!+y||;H})}Vg_7p?E6OhPNE5NsY>Q+?sGpy}m`-{$ysMb%^&BHN&m((LxgFZwrv5R6X(VC+@Ee6v)%jH}SAfrNPS*mElB#@;@>W`6z0CfrIdf}q#X~2KH!1<4 zyaOq+ehuZWr!+JKF9`^2u|QD2>eep}$CbJA(Y~qIQ6QCR!bb@wa2*@@{r_G7?MaMg zdi)Pw1-M{vLtY;)|FWCix3$jPkdPPFoNb#mEhnu|MDC;gY`I=_d6m`CzO{+habEJl zNe9yZXrnOI(cgJ#XmBpoxP9xgGr}S)wnD$UM!S+(!Qtl!dQ)Pt>Kjq#&6zn5|4jzu zs@sOUFp%F{VC6%}*|-~=tdwdGi>0AyUO!J3ZCfeE#PCz@SAE^K^TLzEq}jLsI@P}J z*1Q6tnO&WNGG4P3`mVXz#m&2={xXztc+D2`o|uk6OVMCxmJ*iyUe;SIoS`u;oP}Q* ztp8rhQHS;Wu3~2VVnSxwrPQ=>Tq2_+%A5fzn4Zsl8CwEPP0_$gVlEOT`vg8B4;n{} zeARWqKy+KDloy_iiQ=s=snM_c%JEx^ZOdiv z=4^xJ?$qdD&gh-j_GL>&t4oFc^Sqqc9X#jR(#@_5uN$b99G2>Lk~Fq_gW%JCA5rjO zmsf6y8pG>swJ6j%-*q8GLXcXE@ZDrFeI{D=6keD4=PKsR1u1%0%y&_KRBS5O{*S%D77NuZ*VoaZRoxz9(yYinVqP}$Csq6P7mev|o+4?R`DD|!Ldwnb^!QwLpXx;oF zSRy5@v;H51el2eT>^N1t*kDT_r8Xczii3(3!aUDOCJk~4wPp##n6IPC1?$pnEpvSR zLWmX)hJ;jUgFCaY=g+T?xZa5Q+T14e4tpHkUG2#I=x1Wi=UHe8I5`BU^kG+4ehzL0 zvo^H9XwaAxCK;!4v7|bTGg`K0kqg93Omg_2OVwnPq!W0O+m8#OtBc5i{Mfg8+qe2q zp%@EQXe6<9=`TxXMy44;fIORDS!}&=R|mhC;)YLI_81YVCwiF%`6=7Jj*X2*mpt7c z6&>riw6m78w$e~7r5$F7JMoqzFJQ{Z%Kp3MI(U)DBWd=YG|+0N38s#TjdosP%`!Ll$`(^2 zVt)3l!aC8Yv20;XdMaSwV?KgtXDs$cGDhCWZKCgO^zK@2ew0o{Oij-RT~PgDhXQLQ13kF8&{rN6>aFNDVu?7x`D`1dZ+T7k(1$?jJ%(Bd55zzjuM!$@uJW>nT{jl-u%ZT13;J{lLZF!bVTDl9wm| zR_inQa1=6qf{+_I&%{BAJf&lEWw;XNN1CF)x&Q8eE^}(y`@x*;+o}aw@xJFU1Gjjb zC`Ete`5kZ@ipf`TL?tAAxs1&v9j%9$16)U<-uuMfHs#cmG~QfYS)R-EOc*K99!-Ta#@Y$2U4 zKfHgyj_ug7UH5f<<8u~zUtV!!o+39t-EH@GHggQAevmdGBqO`=B!^5g4+VljunOAw zFWArPKyQ8%xS)r7zhEOhj*CX)hWD!C_$#7^em26DpI13JIrwM(i8%2@dduwc>OkqU z_x{G`=Xm7yvtCw@OD({XyQ@ZwQ2NixV%1nws+vVF7(C&=5qLa8CzAA*Tf0%yYk7|P zNsx>d=@$Qemsbd_teEKf`r2#fv?KSA@}O54qMXo;%g3xa>6W^5;eaJuGShh5ix~9b zw+!k$w&TXwh@d4U`=x%$P6KSba502NB!VcSJyo#T<)e;l1JjektEfpiB2|HEl}6pK zst!fwD(&Xl)sWwO?t_V=q7r}If%Gx{_3YvGp03MAyZc&n$Qw!TjWl%c+lMmGaJR~i zn+IS;0jI3eP~X(QMlBoT^+TIqIb~&s&3k~wg3j9Ud#iJ!8%yBqAkk8_t=SzY=m%H5 zcE3JlQ5(J$XZMkh_j3Kqbi4LiQ&!df(6IL1lsmR1#)^Ne9Mr?kWY!|JELVxkD}vK> zjpMw@CycRDWcq!#v%z`*6aW{ev1QSnBY0RZYjP4DBAKKCl9`@$0wbnK`eWbzwwdE< zY9YWS9?B2xZ0Mk548-^IAsp_Od)lpBIypKx-2d=cp?Wwul8k|cl_Bua=)I}p3IS;@_wJT#5 zw&y22t4>_7r7$txnI^HJ2#jHgM9bG0BMj`p7o2U~u1WNO-u1=?eY%ka5ehdGqbCzN z#uy@^V+L-r+YinJgi)}yPdRPi+QT4?A-_EXsSrbYCT}X^;bJ3JD6lGfw441yiDG

oco?+gGQ_XMmFcZ^S?~0%Ik1yEoQVB6c57l%h=e3J zXTkLurH`(tPeQz6r2giKZ922D#C*6n6Ru|5!X$H&x^C<8`gaj!c-|LK;KjXs3?Ji8 z>_q6_ESE`Qr4Px3zh=I0#wmt{^y6q?2V;d|$7XteTk0iYWyVF1w2my| z_DR_TAwdi*Oh9eolmQYKYi@^+65?az^RG!D2|K6V<@wrz6(xsA`k?mJ7Yn8euC%?; zH{2F8TYtYIe4~uY9X8r_9}&-QvsH0EonFZ44Npp7^w{r*n(z+q<xVQWB4ZqWcIo1F2{0)DY9%|HLV?0z znQJmcn1?!8AQD$!|E8|zA#*RVy(*`v$kJ>-J?ql@X1v?`=|Il=Dv!MRKIss>c{#T| zGckGwHVN@v8G`dpe&PrR-jt3|wC0yJsrp zWWBo_>yMoLq0R38!nk-pSC&A}dE|$w#27mCW7cgwIi0yh9BI{&6_-JQa^Avl1j9~O z&BO$UzoF(~X6C9vjpP3QMn(%(l}4N6$YL*w%w)tU7HgZ?bD(MPC|dQvUGw)Uk0(Rt zm;K<+28NF7B)h80RouH_h^!4YXpU`C9bW$qrr?XD3;g`2exLU88;tvn!=wM?EqbVD z!8nSG^rVeaycS6l+3C%J;l$)a|RT9$0*L6+F#t#3O(CAckBl)pUbMe174Zr@rt+AYffI6$FV}&>|L<;-Qtwo>&>wz@=H~f7pX5^NodK&r~z_L zBNa$Bb_=bsxeoyfhre<CqeeG5XrrgFYx?OIp@%9>(&0SmG#s_ zfCLLM2qY4IAFA;?|21r=YW}}ku}+I%0lVQAP3RWPJR_eWEWa-##6OU*asA7u4`xc!HI4(j||2O%ST6w;jq4M%`WQTq#9>zm>5=KF938jA*urIP!* z*So{2oSwAF&{&5&>b!W4skQr6EOky>Vs0oTj)ws^ob=vrHdCFSSE#aqb#i!e+DPLy zPE1E91IRvceY`)i$wKrKFC*fvqmN>@?7tK^HcsVj^=>L^K$Kq;#Wgw1siigUiggI~ z*ZxQlloE0ZMn%>YlCdzWzxeT^J%Z+7Z2p6eC6EEGx) z!eTlpz)(d<_3eaMSl9L19J2h!sb;|<>NE-16K zB~Bu1LfQzDsO?lFH)ba9+nJx291b?83vYKX3Op1zQAsG2e?x&!;MzW>|MOb4n+Bh4 znygl*#XeCso(7(#iZCD}gVbuC@GIu)!-C#ysYCd~L+2%jp+|HtabsLf&L_Vhj~xkf zVkbwq$!PDVtuc>X-~7ayo_z*%tNAu{T=cj}j5v_O#$xAK&L z;oWqv3@9|$6flpbUH_V~0>8Y_!w`Tx^aNbt?4TTYS7y{M#v7*_Z_sCuKgX zq=!rbw`R_-9>-&2s$~sGF$Sv}YLxk0?afveBlku#8b6iHOm(8e@5su^ zk@5?%^9pUC+;%KA58e97Eqm*EpW^)2^1>2&eY)gOQrc1cW@2q^ALPK>5i4Rc2^?BH zp-Iddn$eou=15WTM?ZnU;-k=AZ2PLvB&UGK%XW!U`)O~*{G}vA)hGU2^4If>79m^b zW@T4EX+p*#J32U#s;y68ZTH;noXP-~J9rf9lh!rVl?=Ly6`jR%f2;RA zTjD!qZs5SHSI)5Oza{a;`}(v!DL-^C)<^^36L&`oo?l9k5j4I&MZexARUBH%{+fkH z{(}l%&Yi6c{`Nc{AN_1SS7sU%1PICtU%q^K`MmbhxQA%CwY3wa*tUB2+J5`o8;<|B z)S@EEL}A*hUNiReQHhrJMt7~|u&Lwzd)WeWvP`IP0X*b!?DerFzx;+$=Do#?Y?@n6 z$2vb430vQ)L%ip^TE;QzlIKJhO6l{Yfzvg4hhDCaJBeM3FmdzBzoWGEf#V(R!rmX2 zZ*!?e*6)gp0z^JThCJH@O-Hlb|ILl%OBtk`{yJ`4vgzm*n*>rDbP`3s)tq%)d+{>& z1n=Urz=QjDXTbP1(NtWfE2~A_!o7Y{C!coO!e^kx9Vc;Or~jbq$Fjo z(+4y}?VrS<#z0Vi!c{s@zBAQbo07_`B14WyidUSM3XUWY=I2LGK|imWxtRRM@wFMR z!DH=KRIdidvR9L7-F4A2+3+pTW+hd@c%s^GH_%-EckBQSRBUsFATh~o)t{HGo1)P` zDvT4OU+P^AA*UCw-nnvrIw%&A9evB9g_>aE17RX)0(gsBs|suwx>*E03)%!V3q`ud zRe~|iWRJC<1W;}0`mP^7#FmYIs!84Fl8KB~5zC_0_yUl2&Y7xOwHcg+F3zakS6vK^ z9GSnyv%dBwf5mze(w{a{=6%&oZlr+(ifg=ZUF)mR6L{!9pMt-vQ$g&6iw(^+d5b!f zh{kAK9s_~XGO;jC?5Ry`WS2-{$p+Rp-~RY;_3t_|G z-#zM7%5d;SzJMSQQB7^G0*01Mwj`LsT*YRT<=<&qW@(n7gVXtD=Hi$9a&^4rNK5SXpqnwaht78WVw<4J@kGaE9= z;Ikq#DYOy&%Pwkhw>KCL+xGXsm~-SMMq7`)-(+imopA3U5$~x| zb_YQtWK&su@D!-NklX(!_@1b?#Bq&B~ManH;# zwH5!_bN?fzg^3$qd^z9e&wPBf9=(I{@I{_$rubuX0S}>i0^e}BvxvY42S*m4sN#*A z-|ciSdo;Y{kqeqtG?=S0By+?w7N7}#v$x;vAb*l7&}P7wmP!)`h_S`UnG(_kL5Q{{ z_HIW{)sxB$yBaZwQf1=PrL)AE@p}visj2S>C;+&`{k4)DW@a-ixLLC-3iPSYZ+c?l zBexpA+Y#H+)o>@YWPV__FWqb`tLhV%SOzKSH=$xKOB5as4lT>k#PA(XM0Dkof09$f zb7^96a0(|1!e5125)ZhDjAOA!MvACo|B*=cmSAXk+ zI6e4#3Bw zLGzM?yLshyJ1vzShI5%fo&I1ml3>ko3$w%h`yS8(&~tVsSi8);jfj?QZ$G>Sc2%}2 z53c-}ThSq1ahOS^Apf-0gWg>oW2mp^j;8#9;HKip+wxYc!}WoiK+k^Q=t!HA+3V%f zTfJ%sliS+*lh9>i)r)6A*~QA~b9bt5U-xHkGuyMHK+D;X39RN-0;I2`C&f!mflwK4|22{^C{$p{Xe z-}A^hJgSFXgcuQK3i7b}B0)LyB_4ARpyAMhraLjE)&VdJGTp81?FXm4g!Zbmnt&7Z zJFnA~qfi$0aja^8C&;%?vqH$@<*8If=4E%tTc@f(T5BgTY+CCv`srvd8Up90OpiOM z+NT;204#U1ybzF`kFw&<70+&CmJOz*14yA`ZSIG&>669f$(Q7wPXz=`HbZz}gYc32 z2#V0gxYS{0y*7gxMnU#8!Sn5SAoF_ZSfKc269Zbp#=REebw7Orpke+EFT?_+$~{AB zYR~5ky04jJL_}pOB#G4s*}Hp|?L~5#eCKyt(Q6);BLJ6l4`~b|Q)nXnr%tO&Y=g%{ z;Nj=z<d3H;|Em0ngVsRgP~15d)K)B{ON#3?_!((>`g<9Fze4HjKXOHuRqn90Ol0 z%Fmxc83_z05ahATkb3u!RNk`&RpQvEPGqPemRho zXvPJ&=zNvwV#<<7_P)mxev4jse;+j2dTN$t8%^{fPeaRG?B-N=SyTQGJd9Y zL+K17H9J$uZYKin_-Hl))!V>X40#06ba#?w&4MW1YLRTETu{JXA#M9>N5|`lbK4&4 z%jRdfFA-SGn$vS@JZ@M0B9>mg{Qyxk_xez^k$)jfr7SoYIbQnv`MP{8UU>uzg>jX{ zGLPPX?C|g~oN1wAo z%CW!>T9{E}35{4LDW6A78{t;EL;B-0@{RlH;Y^y^fty^&ECMo|=3!wWom@15-O(mb zrCOL|s0s7|tFJBu6=B+1m)Kf}lSF|lxzhV5F3T#y@ zsZI|3N?Y78?>kYylyTaa!SO-5G%BqBa|e!2?Z4}O{?PM&zP3(sni_3~x4~`K-yJxpTYI`` zdLZ$4jSWP;TW)q(d!9QrX|IkY$r4bjnmK8HY+n<2ZLQf2B+&im$R{I_^mK0ed2MYj z*>r{T@CNhhdFZyC?#Q|QX>u!C=)@}3`Q+Jk!VMB%?B^yA$1{dW370@l2%7JlriY@8 zzhzd@S0{D@D?Af*6ByD_rbmqZ=d z$C;+0OchBPJZXj;M-P|hV@R9zl!1QH+uOlVTqz=lx_D`nR^O~%E_)39rmyT1N5!ny zJpMXs{^>AQHbF(Q(A1V4~wzAzuS*_WxOcYuZ7Hq-)G8Zj1det<~pY4ms4iNERGF5EUAepIxl`c{9P` z%md(0`!I$RUH&`=#s zSZD-&a6Hf5b%ZcYi1s_0LL;_puh=@pq)O4u0wlI5rr~m*J`K~{*8VMeaHlkNXncr< za*l4*oP~-?WG)IUJh%D-@jK1UwjhF@xE%H@)FIQan2f;=Iq8M|flTw+6}eDz&;cnX zPFNazRcUG8yzVER65HT46LPT9xGAJGhVq-upP(6G=t4qsa9dnmt+XbtpDC;Qx^^d0 zw>a>bG-eUuByhzhfJFkytV9R(EvtK;&(G#XB>##cBj2TFZ!?DFPFQWb=AaQ`*KUjH z${Orh8GQ_+QoYe8G(^+e)({U;PedOpUnR)l;;div2L%|R$RJn{;%lOhwC@5?C{tB9 zJr^*@KSY0^KrGB?lV$+Din0((GUv!DPF@T8Y5T>E)hGmA0dZ{E+Sx|~bLKEofYst! zQ`g9F%do2T;^Jaw=<(qJFp=)(-$s)Q*mgp8#42@bne{rnWb=q?#`bo1O+<2AVj$At4HEF*KWm z;X>!>iEvW24F zfp%O^+SI8a6aiu3AE`#s5Gg3K2()7;(KR91D7b;hJ#KM53N*PH))MN>X_^(jX7UaF z4pdWLFXb)%Vx&8<5CO?|YDCD4NMetr0!7+9t!q-4n_u zt}6_*exnGtvrbT$bRQvN1iiI$-Hhd2MfUp}_ zE%B!H$5K>TRqOBm+JTZ1_tTbFKQ7D4j+bMF^!lYbcfGaOVUDr#-}=3HYT9^WC&1K_ znw2HNIj3_wYb>KCbhB^xHva9WsHzsHzk@qNS#JLp2I@>3X6IipQ zIE2i<97R=Re9RV-AjtiV|2$jBaScQ%c?$CF{8Gloc;#ok(Hey7Q>=!ki*J#Hx?;Sn zF+g=q<1Q?-&TQWB`?4VedQ&UIswYr?x1&?_W4DmZ?T%p6^}2Kh{rF8CvJd&n54EJd zK8kF$*#a3=UH1_u)|dX+_#&+6UIpb68kyv%;o&j0(ize@U397r*P8|RQ*ZtA@y&%2 zRo(3&@uV0oIte*ey-&3Uy_0mAF0HG@BO@cP-Jf5!!rseRZNC#f@r-?BOJ;L76fq?U zqSsPDeEyDE!FctAkt;16t!cplR&Nu|>w=0yzaN-`OcWB`8t}!iuN3dHZ@YbHr7##7 zMW6^hL4H|GOlVLlL_DrOB%44uszBl)HeIUfYWuUiw{d8;tilq2&XM!2$95GFo{N5X zbZpPH{d_aL@9$r&3RS&4US7NZzJ=(r^U68hW9g;^v-&*(0N%1@^~w2kG5&)i;9;+< z&827kteQIvjv~7@r~6)XEuOdXb&KYvUEh}{N|>gH2HrP2mmY*G1~waji#2A6;Bu(A z39o8RQ^rxUbmT}$;n_1Nqsp*;?0hNtr3j9pmWT@MjZY+9=n>0C$%cm)ZSLG|PIaq0 z4gTC}v&Yo(7#t+~-UNFSqkxU4q5(2$Ux6KZzk>aq~pnf`?$8Yf%f>q!}1SrSt$EuTtT;anp;=9 zSUBxpe(tutAWejytlF=$P1f!ki7PACnLV)%6HiZYaTT+166EgnI6vK3N>oS)bbpy! z*cfc6DN}haI7L>l8(J+Vb^{1*xEw_=@7Mm( zk<~WUgdf~DBF<6hw`;`r2q6_R@0GCiKh1t*GM7X=;RV61kyo?eSh9c`TaJ0c5_wB{ zW;O8@0tJ}Xg~IKg>v_nx38geL8X&BN-?_8N{qf181a%3lcFB!^jPiNChcO)D_9o!9#Ew zL6V4H%<@nJ8FBH25HTORVgf@l1&Kvbj{JMox?yG!s4Wco^0&diEl}W~65`5#^w(Ru zNG)U`6`~ud{qr%sh|ryRq}CjnMSJ;RYuECHkC6LAV;^W?V~S; z56;?-JO8#>qshoM1w8%&$eTm*GfnMZ=UuF?-D-{23lDSN*9Ss=v)Ye2dIIxn+E=Hi zPt*U5qtJitt!7o~HvC&WT>U6GXHj&Z!e7bnym_`U=iD-nO^Ir6<3;~x$!CoiZM?>U z;iu!QMTizdGQA+H66(YfwU-v4eLa4* zo@ldh6UgdmcXV|y!=wsuCexNX^a8+~p-joT9s`ywy5Tre$4IE9xc{APF5ttV)-51o&aBuP+P!d zqA(J`61)8?p=14}KXcVAwWpnz6e3-qI1s)J4JoHml^-YTMQlqbuPw|bP=P0uw%3^U z0TC*HEI!RL#;my4>G6}r!MBV7FA za#0_&8lPs=oS)acFS+#|TEsESq%iU z`D!(09~S&SKladB^Lssw6SSX2zkT}_uzpi^j(VEOpYP~^yD_=okAG(q)JDvd*~F$1 zleb%ZqnF+Rj4xlggGpz|YYO@%B5$2IrhiME@*3oUX z?k%Jq@Y}pvu{h-wMSovy&C!>g(gvk}EQM45-~xlejz>MpxIX`KscsnO{m5q#Q9+v| z_Ae5R!o<92MF)Z?6T}RjoXDg5RH@mOz_$lQln- zN&wcIl}e~I!VszPY!rB=0O{88W_mF!1oqO8K&9`XTnU4j_?O$?nXRI+=Zoa% zM!t%giJGrzYKM{O;rfLtxQTE?;a{=EzEU6BgJRO@N9;wPGl@vCvBQZCiRwEv4;_EU zp+iCuN5OyiM9vxMg>j=qd?@W1R3L`hNqCZPT6<4 z`1XE2qBocy@I_-p<9I?6#_8wj8#BZ2osyJZee;TRm)fePX6tnb*@3<{17X2>ah#D* zbSO$WMFQ$bSTTjT6d0{qzY~suFO1~6&(U(Wj0U&FG?+Pnd?oy-JIY#(Xsd>UY|I-YfcC77gx>iJvurma~n}QmrjDo(TRE?efA07l( zHigff9R@*^fqv9PU5eG^W$jT>kvoZLoc2{ue;6O&+S*w!_Z{oVUHDs zh36YhG9Q|dT4r#};_!y~N(O!m$Y2Qi$4xU-+V6+29*Bz?DNU#)vTd1)8v%zhNF$Ev z`%OP#vbnThk{;tZvM*K?h{-eQWu~VAC-cqsC1>S$TEE9ZwU>jl*#8hNMT?i{&d+yb zRYD_6O`dm+ZOAv#QJG%niE~L&7)^!AC#!90ktd#)*U5UWsXiyITWfP=4ZzZg=iNDp z(XU_H&Nk5#O&px8Pb^=rGMw8lGpdd}Scbx!${g;-YvyiFh_qXI6nQ;15h%9NqCnIB z#KK$%7uH-f?}~ab0m*u2Xm7;C;S8ptpFBrT6TnS8<>9@-+5I zuYS}0^RLqr^0ntm=asuqIj^Tw)2xoiN_V~t=1;LW**V-;WXm<4kHOZ>J2tO3=s>D% zYmYW4hychHH4%4pJU+6{l|};9zN2eF_ci;GS=N`8x#SN-UUR3dj}vrR0^D5R!H*W# z(p=&SCef12k_fQvK=|OOFqp7N7)8OKq9=mHr9zcSiW$>y2sns_5%v`0ux5Ega$H=H z9~6gHD`#>lME!U2SomZFI=yg+2;JbNUt|d%HE{@+vI<7RJ2(&uIz^yLoN_3f(VJY0 z8I+)Lv<3?V1gUI@>2iM<_QX?cu-AEPw3nliO9=Gy<6rNq2ND|r+ckLad%f3(SuF2u zCcT%*te1OJxyVefhtQ&`HmAQCS-+nrB(hQj0A+={2up-=Ixr}WhA%u^B@y) zpnTxVI@ZZ@o%>u>rt2UOU!#1VMuUJr9A+*;{)tMzVb-eP*v4zGx&bQTBKEQEZipVUX&JYva&@h`mg2NHq85_s%o^g@#wy>iYRZsI zKhzRedx}1zqoY%mQkZ@Dv+e_;IW-E|)|f1pbgi5@5U=6-FnIAbPh9V1(>p68<6&k> zj#;-g1+sKJn*;w?UN@*uf1$nYT8Z;Uhk~7=YZ)=$g5_i1_KHZizleCE>^6jpR;z@Y z1m0hXV`|0v>n9OkX+`8yC1J#mMmj8ZvxQ>cD#ADW=a>1Cl}iV4=t9x1Z=AcGxG*_+5J)tGvw|kE zG8v%l-SpJNgIqTHFpK)WGO-6r>l@ZFOBlwKa|J=rS(L$;InW~migcR>5aq3+xFV&? zjlNxXA-aTIG`{Pu)q9Y**oKTHTy7~F9xY6ma46<&&Ys7F{AcwGl#rAZ$uK|R$cEJ> zv0ilu^oIGP3j}W6mKDd2-m;gy7#BQ&lvmiG>Ry5uK-tnoMJWafius~!tMMl{C|C2x zeb`LpVtMRHts~{_ul1iJZj_u{YX{`}m$`Iu8Q?tgG+L?1UKS&#2TS# zlp6%fyHgH5i&g7`1_^~>$|A70ciT#g0`}*zlKG`eI;znci%>4~{}i zh!`!-7HZ@edYJaFAh3_vxH`VDJXKlScb@7?U!RrV)$OllAOoxZ7VM^*YY9+jOxou7R%6iuYOP^wIG4)t3TA*}ALw5~aj>OpFh1 z4r@O_zs+pr5$yGjmhT5=)UFIg^lnW)u`C*!z4?_>zoy1S+l~6P|>k?~*A=F^x0e3Txf|j@_MLg)PWoc)xAB z&4Q!B#7HTes`9=E_;b24Ln)eB;!MFJ;5UQsNLJMm#1!({;wpw_7dLsCBHYV_VrJ|;D-#qr5?520=?YZ?j!nY#RXx(-f$MRnr+i`z>@keBp z*D>JJ(|zc8xM+4QRz9o=|6-KHqV=%*(_IA{74zF^FXkmG9H@+t3dIE3zxh@pmj7_l zx@qO$1H0%bZFhH~nyy#Fl$6%-&G?z^qHZ;MhIrfJN#iBebvv6Gx^Jh{9i>e%jvIb2UQ$s~eo+5_5ge!q33}@%aVH7bTrm(OOp%aCQ3CEQI`VluH z;MF;kz?5z@aJe_|q)X)Yc(ICnY(HhG%K+Lbq?I-4&9yWC_foDs%{u)aK4tMSG8(Nm z`vaDa+ZJ^63P20_pvAtNmQg#aTv{WU!`K&-jbv!!!p5xMrb{h?NGZ`ypW82Hr(B{s z5Mw%~J6T@5Xmq~5DPU@{cI=3*$8*T2fRL?`>5AR20qZo_@XREj8q}R+wwxt4vvqPR zR4gexwoWn~_i7oI@zT@NHRS6fBi(*QYZ+~o&*CZsG&jYdH7;R zvC9NflRS=RlE-;V!mR&u+d+- zs0ab!$r#Q3!s`hz48rH{-WYDDdGtWf?bt~RR?gzv~1pTonqYBZDd^96DJ z!dC8P*B^ErWBW*5$882?^U$jZRJF``t45;Lq-%dR{-^G(=}*tduckTiPKAZ0(d3^O zbyMgNL>6r~f{?vm#*db*aK(@g8dh3%wJHv)T5fuib>9&YnVb?}Vi2;Mj;2TD?hnt; z`}!kez2gZP#_(`5*!0bMegf2rQnd&93f!|Z>ge<|!nOA6TA2?m24ga;G?HCma1gjb zQ1&+ezQ9UecH2bFQ&Sxy_$tI0H|7GJh2)h}-473}K2C@_7ndOMg-F*=Jrky{(y(+8 zkwyAhkk9MV-A1$3tiR_5`SXizfklwSgV$X=Ij>g9oTY1~=j-F=6q|;u=j$q_#D|w> zWD`@9qCJzc>po=f)7z*_9xot65gI2jv^sxV=#$Coeq#ebE^f(rT*lyU#cSM;28uq} ztOD{j(8uwrpOTFy)STkTu>PxFcO6#|E%2mYmjreF@lCf9zXF_*v9ghv%BQ{nZ0^<)7_LRAbd4E(8^Omu z1c5?`iJpO4*B8Pg;hnNCnisX-!r;(8>G?BmkkA?8$@2`GYv8CcNhwySkTfikI(uA@ zzie1W@-gc*Zr;^wJ>DJznqN1t@=VXGSH+=@Wlx)XjQ{us0Bz1yXf2%p4+;-O8==Ra zdt&>)o7z||#b)%2rVb(|{*_2eB8|VVx z8Zk;aEoFF*)Mh%&4hJE-L0ku>!X~qTqhf)FZSG8eQGpABg0VO(Xw7U4m2s7ZfQB@rwpv=CILImQa{U#o7`}Psrm52fUBY`=wZM z%Vl{uTal4QjGPBT3J49seMpNmjM;Nl3&4x@8059sTs*FqZ27Vt1HmMc8Md-|_cy6u zA0dVT&5xOQ|Im>y@D{Ak=E?L!f=mVr$jQke<*y`t zN9=02_7h+vwz~|ycfUCbWwHKkHr3N?ZoKg8T*OkRLKoQcv)4D4Asc6O+s+-L(pvl= z{l11UP@IgRNRDe3&OrSLwR{e0VLqx0lT>cil+j1Q0Oy)gia=;z+Cm`7|TmBkJ zK#5OGVfy&PwksLTFDN3{A{z_#QGLtD9ZnZq4bc~Xe8U7Qg-CJsHvpRQ!GF6p?8g^ShxLZ%1t@&IZda%6j{P|B?FDsTBk5}u0Ve-a9 zyRviNm%Q%IHeP&vdF+cM9E7=^lbhhwa(NUc&UWM7&8%Ic2$xG;A-jFTA@%tEb{|$ zW-#2^2@xo=A#gY%IrYqVA-30Z=+=&vWxe*Q!Blv$h z9A?qwthO>bnA~^|6dl~N+_%o!{pWO=ww}39Qx@9uRs+bNs_n)EZ`BPe+YJuS#y2}2 zFOp5l67O%io|ZknXYwZG2RX9$GKlo@Bm>EzOXUrjP`e_#G}JHmb1_UenZ{Iu%! zZfxYs4?YkQBITju-?7N1CG>ZT=gM(3ePr2Gi$l8f;ppR3s0alRIBGbn#b4j_vp)$; zE>{n& zqTck?cg^F3RTdXpgKAIvC{>U#U@`B^N^?u2!tO&Yz2@CApUn2ZYe49Es)<~IavYGD z@%Y5z$$%0TmiqAmoBF_DWFl~GvE$T9ZGp^KCh2EDfGl}GRL+y=TUdIpk z*a|0wsSQzqq2(VLbuXu>31KQ#W)r4X=}ckFQjDM&CTgP7UZkhQ9{mMw{F}73q@Tg{ z8X)MOn0c5PR0Rs3^X7fuheFOu9O{Hbw&FL{AaeF>xK`9KADVpSuRFLwiQ}YL#Ym9x z5L^0GVTxJ#=r_W|1A_+2cq}rNaMCpm+O}=FB;+JIO)p(MrQ0i;cRBu_!dMqP1}5JR znG~90K&eZ}$pxkIJ+FhfoOWv87xj(SYoW*1!8MP~5J~5%Ba}x*Fn}rus#fV{9$1=| zA7-jN+cYaALV*Lwj*2m)j}0w14i23ncI*P6bNb3Xd6g{>@(LFnHJI&j)MQ)&AVjo1g&2H#JmmC(=Yr7Iq=ARa*@P=(N8bIA6DGX z<-9!RjI~$~EpLuL+uI)QBxn6hNzcfoW{x#x0QvOabe7s;C5}dM%81RRgrKDK@-Wij zVe$%5R!e{acqQj5g1QwT3G%+Fku|Fv*xATvQlkB!cN8K!XIXD@=s2+Ubz-il|8y)2 z{YqExk)G^Gh_1G!;75&B5n(6}*hPbkg(bC0PM9+Z_iti2rreeq3DhyX&iHOHhLi^t zqG6NI24!EO`nTM?P~m8f`PZqzp6}7v;Gmp?Z~=SnZ{+18Dbi3FSdEMZ;$#o!IMbe! ztru$D=KzD;(|GQ%#Ywwvg{bB7C1XUhtxEOh&y2-Z^X?1dq0y*F*{|t{0a`X~KaPeE zT27mn{MwsM$Nmc4)C4Z18cJZ@bGEoV@5bhA3=B8`UTE{tCJTU{vsTfpGk+(>q{>1f z=>AY3LH22B_4l{SJ^&s5G=JXxsRSq24j(M6A>F}oLlyVFe-W1dxWEj8KS@x-u_xWY;hu^k_i~pu|IE6Ah_S#Mb z?5?(B{e!<|@c4pOoR)CJV-ZDX`M{_nJf+#$moMRtakhC<@mUWD9U&UC0`1C zCk0j8wROiNv;u80=pnK$eb@*dDJY33sWNcI!S1LaoTMrKgk>DGT%WkofKDDf5ggP! znUWw%C?$(B6_;jdI9vHANgp!|2^inUA1A=?y4h?>3}ttI?$4r zo%Z%B=!>&x`YA@?$FxADHAKe50+9NZ88OwQ`XyN^ami+@NTdQEA`JiBFAS&MUG3jJ z->zTa1q94BbNMn$A_on#ALd)M%y{TWR$gu`Du?-sNu>e zXhq{Z`ryu7VNoeX)H?IO-!^k;q<^FLYV#*k&foTVLGxyDseF2jxuYatGL8O|!i0A7UkYxew&)~`k40F|f=_S8?IPpedbcprW`xQ~KzrbL0mT@gYR0YW7h1*9>& zJ?EWsNCrqiGtV}*jYh+e>F?`ba^>*U z<4-PIy)vmJUW>3RXh?ZO06;I2cCx(NzT?i1uiJ3J=*d%Ao>!|?5h3*qsy5^X+D4!#%^mR)-J#r^%w0KRm6o_alec=Y?<|6#k;CbT7h9+Qo!Gc})f zGfTz`=b9U1ue)|zz0t_KS+m)E?!_0LefHTR^No5V&+>~e-m-V^>yJP7gfF}oUb$*z zt39`N?FCU1ogN$Q@9XO>bn>G3`9lv1%f~x?)q$mPRJu!+g6cEnyh(!>QBbJL@5XFf~z)o3176l>% zSR@ojkZ2iIu4Nn|mY#}GfF<1HZVCwNJR&QT0+JEIP%Rd+Pzg;Syu2@<7w3Gw(j};@ zh)@`M4=jNSN*FOfR8UmIyzadr6jfyX=^1n8ZA{zVmm z0f>b|h65uwL*55?1;Ql+=z^jp@U-W#eE?GRT1IDtAS-c^edXnse)Ga_I^8^WQ5?n1 zB$^o?`|h{De*EMKB0^)n^UvR|)$0X&5hj2%OMm*)yMFSMA4tKig@q(ZPL7`V{1?7} zio&@geCfsK-*{s;D}zEMszyk6-+kBpKfAw3(<09d;pF(}L-(F4l-qe$PvUC5k!Gm{ zCB)!KA*2v^3g_d#pcisoG9cmcDC>vL)5@fwuNQ)!FkoPz^f-WC;diPD&yyH~3ZdZ{ zeMrs*+4<@V)+XmB&$U|fYnHDpn0LOm^SKwFN6`HT_Y#q4o<#QS*qlXNvugR#qiJ8Q zYE;v9`_&uuhFd4j~zYYy$1-D6qc3CNkb$AOR`89>CS)4y|ft* zU=)yr35ZHu9K+chh8`$o>AxLx%Jg?6P!)t+y&(e{C{7GB^!X3JcLjvJi6ChRxFZ-u zQ3;`KRE{G`A^1Rqh=c_ctU(SuzABnfe=DTO>cK#s7Sq#ngNuiqb*=gIxtE_mdh+C( z2M_+~pZwA0&6{3-W8e3F{3D+h4?Otb`t|GIdE-0U3+-=w^IMZsvrC4DA9&#B)3bBv z?1s%3S+eOudt_uJ%{#5u9ER5%Kvg_*;e9QskRfIk5I|yP~L_1NF$l za#pT3>%(oEF+GiX+F4T5F9p1sAni!$o;F?G!$J?)jGv9y_+sY0u5J3|g|L z-R|Vx&(6Z~))ib$4aM8;TR&nW6upqDD{^E`@dy;d{E{NbPc*Gf|Dq#cu3 zv_UToKoE*%SwyfPXR}s5Ha33q%{TAbv+Ll2{W>`rMNwa~p8?uww*A^mk~n$(xfdG! zLla}2_S6+F!R;^}OE0 z&Z)9unGYAVYOKthvxtilV;um5Cc7ffZD?|UQsoy$Pyp4?Jr+(tV@RaTKtUua(dlqv zgGWFB0|v@i7a|RT(_x0k^GCAw^5Q_H#M=QBl`#BS<#Jp8GL`c$Oz#9o1Ys5cgNh&m zYRWeoa%*YXlA*ZPoR}CpeB{W10|)B0#?j-)_8r(qU?LM;apl%U19egT^lk55HnQl~ z&pdr*>`b*<{lI(QH8pv~&mMfhI%v&JE2yzhYcy@1JL^CtC-sG2SeX0B$8PaH`_-?X zt2dg>MxQD;7l}wP>lb;q-C9ufw|)H9?c2AV8XZ-@!GYmQC1EbItdrSLZtRa8I(Yc- z{w!?`4K%jC4 zY*yqssQA2aE@H&nZo93&UVG`Km(H9ybN$=i_Wt+WB&^T9@Isnr7jM3((P$nzbl5Y0 z@((`w#8Z!j=!@|a$FIM3$BLD!ckSAhbyG<*?>!eqQDke@tbXmaSFCduY*BayZ-OT* zP$OYIGHh)ezF$M6q^u>nY>YA1GIMayfGT)VB1QwChD@pX=$)ZZs^X|@#S3B-LJgJ& z(em35TCkvgz|!NU7^p`*A21=JDxrVM1ofMi7ncHn0Taq*phy2}fD%C|72~V=1=`eHs`(=P(x=1VM`9=-k=KEH4V?X1)H$pZQF+SqpM$=1>HP)oK+{ z+O64IwfgZ}e?N$wi^4O*n)ki$wp%}JlSDw1#6|`>9c^{mpkk1!wZs>>B3ZIUQHV<9 zT-NEPS;xfgLm#>Y74s}r@1K0)@t^(df#JbHV~i?zuYdtw56n(TvPA+=LLdyLZXq;* zqYTG316mBJC_=!@=le855Lx(fzSK!1C`*ENPy-Miz^W4dR1H{r2oWj8<0T^+76T=s zLZw9gC~&a?y$CKcRO;3-Xd9siRQ7l$)xKump1pg|O^zQwenQp8Q4~dyG4`Ln`ZX81 zx!JkCfx&vEGCp?p(4j-mJoVJn)O5Yx=WGvWKu;6L=N_gsK8aXqdeyCe`Mb|LI$IeDY&a-^edt8vXBI{FhZL z*QR;r#Od)Tp5B#nx1FXD8Yznu$VIWJHky6wF1Rf1rbmw*uO*GjvS!*&S=dFfi(H=P zK}O}hH<1gNa8j*;s6ir!0t&sx6^6Y>oow#a$hdRlAACwfEvYW zwE{5s{PWN4-Me>cW-^MRR(ruY=ZvYicn$ovYyEz{BFQfs!4bq&0HyeG%I_Eh~ETbk#ykuwy0p{mgsk7H^zv5jt?l^wzWV^kv zY}wLE_42o0zit1Kqi^havl6@3f{$EmqZ<2yEJjG(ZfBu2*X(Qj*`NKGAle_Od zdE!JI#{g)ZE4UD5LVx|W+itkw?Q7PqIdNjtIX5`8!Tu3z)?5+1A3E6-zz91#8yqedBej zYMcQD_Qk~5>1td#J2!!3qe`-B$@0rC-g4yV@fTm(IkIxO5aq(lmo2Z?>Uo|SbRe{3 z$&yMXUbcMX-S2+)v%h%`1^2(X@5;Aay<)|xU9as~wQ^;>R!@wrHT#n!sa9)29~b1m zK%yKR*ML+WgG4qcJ;U>X4F5k>?;YjYRo@AI!+q};D|J=pmbzPNNv)hkMj!-2NEom{ zU|W}N`9ZO-l(8)S1x0%S=f34wCXtsw5@Y=jzZP1>Vdxhs0T=<=)*KQ0ZqeMM0uVL^TQ{irCuqNi!KGyd+s!D1Z}DpiCqR zF+!FRBDhxFQN{$b6RU_%Ii4}iOi84hdVLdN=SlXSPnwR={yr(Vmn+Nj8j%51EOo5a z>wbC7l+dy~1Hf1o%vs0+nT^ylFo>#*p&Sm8s2(x_MN|Q9=1gE^S!Q|W0Wm683n2?& zYB7pP8M2TWi)b7a2EYUWC&)rdmDSZ+$W%m3>$OIn z)uNOh)7Bpr>c#eADzPjI1!d+KOB1Zu8e&ik2gIq)0+h@oFad{^)fF_N585#NYU;nko9)0||XP%QRml)66x$Cx% zf8yKU{?_z~WBq>bw|?W-M3fkR@UM3tJ%0Rs*T1LTY(DslUoeM_n>HOjbXY_JAy}fx z%&;gUfd3+>5+P|OWo&f)?u)N@^wq-)3oDO4@&BB2&beE+Y#ALJ*>&Eo@85OzYx`au zYqvIRoLF92SzTUjwcGt-SVTE%+m>5z`N*ctn_qtU14{DM(;KMitFNjq|Kl%WEOqyZ80S9(#0bY}B!_7>imhBV;ozqPR|^ zEXyq9Bh6-iFqoe|lh^C*5$lyjj4~_=%Ce&0-@9+`;?nZ1w|?lRn{FBoif5jC<~!f~ z*3Ru`fA)X)%$L9XrDKN=iOlw~nG zIyTm996NUCo$q|>=;-MDnKSh~3n7SDIUJsU{<(8=XO@?jVySN3QxgLcQv)+mWMT@Y zMj0cah%Z}jV9RBU<}oK6R2{*OsaA<7s)Q<&hM5!~7?A>b2L}OY(o}(|;+lK}(VawZ zLTd>Ua}UI9u2%-g3{aBl3K0NN5rVQ)tz;VgOrVP7W4RHas45ePBDnHE+?gausK!!Z z!%o)jA|jQbjyFde3(I zcmM0JA2@z&8o|aU$6L+XMdzOP{+m9~)i`_VbUmxrS`+{EFaGM-p~H>5me*ABf6X9k1f;$7S4 z=g;I>t_JN|qZll8`m2BN`@ehs1-nk4T<#18dtQ6}!Jj{HZ2DMe(C2>b^IO($+Q0Ah z(KolIQhjpMNf^@eMcJuw(o7<(1_#3ybq}XIhQc!s^O*zH{gA{oa3QHS*U^ zov1e(*I$17g{pglb<}q!G01Avr zn`LG$F-{n@L@+B6GaxWSc1nx5;zw9D#*&B;6){8=144-bGBr=V3;?1YJF1l~vg){~ zP|WDZ3Puo(roa>=m3AqZX3U5nQ9wlq454zyLX7TgQUEeR?`n62rGb$l5@|FPbLyJihYTlJ&f=1xld@w))_Px$PE8*!Iuq#&a z3W(%sa~1nz$@MJY<7fq|d08tOfT3FyYyjt|1aIt0<}_?iCS$!9}nXAfpO1Ez4%Y6&&Ql5v2k$G6Mz#=Xj9B!wttPvx_} z`q@nzHhtm~w{6@w^}~Dbot#{M*0$~E>^SH0OD_Ij5B=}c$B&E$8hz|0`el%8|oImR6P&jhO*4 zT<8!Geg;Z(eCYM??8l+iSen)4a-Xl zpZwIPTg}=Z{Lg<-Z!|(yM=ZOmy}$drzi+f#r{+#?T)$y*a^39AOi{)%%5tw?=P)`x zf<%qHc6{bkx4+8FwUDbR1B4KmsaKW`A=I)`K+O5`+BS)LLUSX<*8UsnW7~ zXs2L6F^#1lAu(zca8Evw+or1cW>i4{2uPxZ8FC=5a?)#Au2KZ_#KRb&0{YBM(ri)9 zLzQ3O6(>G?BLc1&l3{J0si17D<{JffdpZl7)R;srhe`&~N;k6>jFh-)_Z~U6C$h#> z1!C~@cV<9{WvL>iNN+GO)Y1yZ45g$%VrqnBTyKUgTQ({{jL{fusAW;s8}Qo-hy=WDh4dvAQt2S4~h zb=#hq)9tI>PEksuo^M#c{*HhC-b*jMymjl=vMhT=)H92FU*Gq>>)+jIH5V7=i*j)C zn@wGz-4~(=%iAXIf zC{(xJv1B3!Br{zLa}!aK64C7dgb1KW<`ws521cgj94ADKq#zPQ2rjrb6VH7GKvTfA zlNVHA6%d3biN^s1wWyXNBGgzxko*9SMkoe=$sp|NnE)YzR=j9B zSpuS%vI92GhrMy!bRCZuomXSDI&>s!4>MFd3AzQwJkiGE7d*EX5g97B6imJH3B37% z49r70K(quTr*i%LisW&N;E>l^oCbnla6e?Yq`<1USM?m#SVpZJQ)FylA_W6s2q8m6 zEPDNVqn-ye1C6Egv&;d=d14iXfMj5%8ktlD8JSZ$M;=_^rV<62RAO?vc=(Muk;mzX z1;${}fL*$dNs3_zqOK-Js4Ttc4;GqgL_|cY zMy|VZlFQO0mCW!lRzcWqQ%JZJ5d#==D2s>z)kKTfXf_~eQ$)?sSWL-)5-yI2m>jD} znx>;9izY%Mbw$hnPdf$G`dvw;p^7gOu?m|3LQcS-`3JF~_WOhPzVCgTH*fmlU;pJh z-|@~XuDIf^yYBwvr#`h|!{)#G%fH^TW%F6&{NmsJ*FXD{ryhIYz`p&z`q|HpwpxGv#lO1!w%b4Ofg1s|R?E#&k`;)E zM68N9Nes~)RDeiQ!uIXkUwvi&7ysr)dmX96nMO#o0Ti zRy&=-w4G&xVF>_v21eZN_a`PN&c1N>(@#DuF^HK~|h^AoyV_}vj5SAE63vK;B96539cP~%4ZrcN@BaMJr#ZW{>#w~&v2L9qK?oT_ zG3=h1pPye^B!pUfWP0z(R;#}2yz^rjxt4)Yp|aW^Y-_jsA_&-Q*SBxm0swD$``h>I z*^>npku0lO#2@_N-pekz^tIPt+kfC_vpur1+?kwQzr4J9&pr3N{q1l4;4L>r)O&yQ zBhjd$^;&IVe*Wus+;P!`7xj9beftm8>y2-G^P6RiS*`Z%qu=RtI$56IfB#P(edM87 zmV;h@q&4DK*##w_28PT55h+Q)$nzemgA^kA2@;GTP>2=*fQ$?jd|g##L_|hm*TR@- zrKvQB`oU5#z9uaQrrj4c#z@3O2#RV73e2?jtfy16S%oE}XL4=YKq6VAC{-}=o0Ov2 zd@(kIN?QY9NF=J{{dsG(ou)pxST&>rBoC*is5xJbD{t!BJLOTENu_A$FEB{;&M5fl zpVF~GRek1wv|ET{pgtdjw0DvaO;D>HPM^a4;1c`#* zA&o}V@2)iJ^%zT4%|dWcfjJ4`0aTN4QoWnckuXc(L6s}$ry4ZB`~JgGis$ozg8dMd z#tT9N3minO8di-%&?t~dKK~wRWHU>)XD7vd;dv7hlPK)8&1;&0{Ik%dfrxC?c8j1< z6|^XfkOOAw@D~t7C}VU^gc&V@nZ_b5pqhk&0HP*9$jHEM*pUceg<1dtVpAYsG%#Q_ z%{VK{5{ykiQrd*XVNuKTLBB5|;FG93@T+m`jW$_WL&7U)#dReWeNP0HjytXRq6&pX zOB4?gl|@Vll&TxqeE37e7^B}sNWyVj%XnN%rhp200(YDyOckLjYpe+01pXr;F{=m@ z0k~eCnA1HP4EiG@?LYj(|3xCKuJ$%>-n?PMh9{qV{PovgKR$izQ=j_8_3wUnmgP%J zi+P^?!&krhg)e-e-EJ>0E-x;u9N4?JRd3X4wZn&xKk@j}*Iaqs7g&4eLV) zu6bev1@CZ1Fz__5K;#<`#8OqxoI25NwdUr|^m@m~C&ugb);Z_xx^VY}58QYEvd-n?=BsgpB|R18X!7)&30;Ack;A8BNb6whdS z$2Y!F6vG|c&OSYTtT~n*ohr{9Q!h#ITPN%*h@bdOWKLBB1)tQ<(R^SfG#@ znE^K%ok1^_MI7eH$N_-z`MH(VmBC26b?ESsBhxce>(&j25lxT~EiBA0_4|YNNPBg4 zIDKNeRjd1rI&$=Q0oL-R2B;{CSN81r*hfEd>#grNIoJQAKmIc{-LPrnE3dq=apT62 zh5d()Ty^!;FTC{P%D9GGdAWuP$*%X-KNVbJN8{lRcp z5Yfcg*svHnI?sTH>|+2TdTFj>66Q;kMnXn6%SfauO(ZZybv2$MBKkK|GmF6F(c^>x z07PQ7{hL;2YpW(v^I#q(02C2bG*e`(B7jjP*+tAu6;vDt0`b7xBnz}Pg2#{HtZAC| zEPqAgH(68=!BoH!ys5}*5I14~Fd`K5ER8qLnAKHD!;-&Ei4*{alsv?QELQ1!(;rAD zl1e}WK1P_=To8byPPKG^H2@4q6#(S}8<-iPS@gPCaZ1EP{nH89Jm$*<2;>NwS!z@7 z_j>Kt$Zfy;%Xi-Sy&idW*Qi93Nu}f=L-FZN9dtrf zXZUUz^D}c9 zC5jA+Au}t00kWnrAt0oR6%8SXl$d%C-w;6~q8Y2Y8^i7PMw;gI>Ya6sk?ZN##Pz7E zqLL8-q$CKcjtu}X81xqwmyRDjnq}GM&D#cpVNsNa4jtNm@ZejoyEcUSOE0~A(@h_k zot>STnH?D!adXhZ^5Sc+y|ysF)bIC-QdWDbozCjY%JO|b{Yj_SjS>kdLqtF^$(Rd~ zpr~p_Y;63=r=Q>R(hKM9+Ih>ZH$VH# zV=wJ_Vfy&t^UmEVCJw$b(fs`Uh7B9O_3iJjEH3}Y|Ls3M_xy7U%S%h0)hC{KV*UD! z&DKb-D4SW>v~_E%)joFo*#3iux}Bby)$5IBYh>f5Ef<`Bei0Rb@=!Z?;PBC7(}+Ci z_KJ~_C^9=cOKKD2;|jL4xD@i7ISZjy7K+G%(Cv56-FePAJI^_E_)uQYFF60a=bw9~ z+wB6Pnq_&e-R{8y`?l}c6+$+1>g4I!Q{APd!Ei7&HQ65&r)E$8*`NH)($d_XJ$r_O zVW-oXm{>RHcJKPd&xgZORPsF6QrC@7wcDerW6oah9=l_ewmXf?m`)c6mYbS5!h&idr~w!Z5wvt8X?2K3bdKN8?4CiGRwy64 zG9dNtAp|mDODruSGFOXu)op}`La5@&E)+!>g+uUVDw(O(IbRJxY8pZaS&ISYx~s>h zkFT2;CqyfY=@Ta=CpQp>!1*IjJacA#Wqx591Fp<2v_`Gf%E=UzVyQcKZto2SQOkf? zMf0O6Wg!Sg0L4;@SPpU=$ymGPx^+_rk4$ge$Uy^PtveV@tzWlsr^Fn?Y5&bsBW1sJsi zgOQQZ<)!7$h#&Vn|Ot`E=|*`teVE{Kgw^{LY#!IL0MUDLbG>B3XQQ(?H zWwK}j3Le+t$3*hfbKj*ze9kp>Y}(u~ObDp%mq(vGDh-O04rmOhiT$iL4N!=TY#z)7 zW{{4vfM94KK4y8I8(`)7e$(1r8nU~T*3PUR#OyKwH8oLA$Uz#*A@Km@9Tke;KQI~y z05DR5Ar&c9yQ{g@r($&p06bU83|SBmklkv;Vn$44ux?^vSQO?x%J7C;3INEf%Pj#I zt{)*}a5Xcc86qPaihE@N6&MK2t6V*4+Z>S*2ySdfK?DHr!l}R#QuWF$WOEcYZF_#5 z2-uq~$<$JqlMCAGpe{|NQ5#z4qFL`NbRGf8*rTM7>_?4+c|H>s4Xvwr%fv_dBn=;>s;s zrt(_7RcqXQ(_07q-t@m5)mUEr*6VKj_{Xlg=8CeExw$z4c=5UCd)_Tiat}^Gi!V``P_-r)HV)wvT*hbYyg4eqI$d2A9 z7hZhHjvYH+dF9o6et7qHzJKTS?|tv>pSpc)bZqawz2E=A_kr-pp@Yvq`PBHtc%Idu z6peAD-6}+eW$EP|c~;LkujP4OuV<8 zb=QrLj+4Q`qlfRg`v<@L(GQDhzdtxRd-|y-pFMKq(AC#m-Dorredb5A$cz9mECxsj z2%hV>yu5VIIp@sJ&x;2li(z07(j&@>iC9yJ)LO`a;JW)gWDRw=s#G3<=3<|Od?|H^}<%KH_Eu;mXmaBx0J=C zD#vGLPA$p04eJXDS{6hMjeuyU7rUKKcUTVlz|&{uM%&|m`=u{`>2Lo2$M-!jIx#Xb zGSV4zx1V=b-mDK-I>uO92^mUMB4X#kDGcKPLlW+Fx?QvUH$MMw=I7^6o|lFPfuD)tyeEiPuerM1to_g}d)AOqrUwi@OBd_g0y4V@C$J%|+nT5{E z3LH4F@9?n$s+Q-$08}hsW(G%&91KOF2w zVi6-VD_#C6S>}b_(MR6Fpbust%WL&|)F?3)Wtr!-HJh#(iA17gmp2y!0448i?Ud9G~YJ1AwOMU}_o_d>wRd-i0}43WT73EigwULJ^moJ6uIX z;KBSv6ta-ja{^RR0~64!Vq_2@nj%rkOxN^KpdTP9_+X4^YUn_^lejT@MzC^KsDcP) z;*hqhsuPy3YbMR4&o#B`z*%A8R>^=6#34XHGc_cM;&;rWxKxeMftGYMWlX`-eqopy zRLL}o^aq2f^;5t3oBwup_T-_1hi6WmJhQOyna_Osth3J&i3blJ+_!&UZ`k|5`)}BN z;q4;wy}Rz7TbehbKqY@h6^ovfu9^^JuFHTAD($-k4lJ_3SgxyzTmTk55c}>C0d2 zEUtX$!yo?P{Xg#a`&p5+E3 z-|3w`efrw#t}BOf)zw%1;?YM$wJ3|N+s=CKo6hKVMl{IW!%?y3nLaC;uHx^M)&d&Y(p{F*in|kW0$M^5ww_)SPv9XD=9L~+1o<26+YBoE))uok{^UvFL`zLSt z%Afz?AO6|+_y6_o&AWDmkbmUnTLTc~wFYtoCE_g42$9{(VF=s?gnqvO;BLR)9hPV9 z*zqS{_|q@{?canDcJA0QJ~462hu?o{cKNc)uH3SD>(74vvlBC?oAt(_>FIq(4&Ht5 z-C3Sbv?eH{td{pzyQ|&a$XIJQ7{)>|AQ(mwBvOgpPIvR>jajXh<#i=EIeY4rS6&yD zox9HMtgf7#o!Rs9%g1Mqce}m7K`aIcs$!}EgLlH3+8b(TLi2tMGBPrH^2qTX_?f!fD z+efi1C5jmsVxHx`t(hixqby4%R#1fmb3(O$sj4WZOUP)Z47~P+n}NHg+(Rwm-;g}+ zQdQldjsQ_o2!gMQ3TP6kl6tOPB_gj05pbqaJ=08*`3nRED@e?umIi>tN$d$p$?K~b zra(6EbCkKvNC8a=X$YQ<<&bve<4ss^`s1riGLbR+>xqa7giHa0=%@=P2OO>-v0X2w8jMo5A{3a-%dCqTuICw_nYA z{*K3=c;d|b{I;!U8NdTSe<07Zi!Q!!wX^aM|M1_%v|bCNVh+PyiHY^= zr7SmY*f?|Qq^EKAI=vXRGc49kZ5SCHLnL5gqFX<7%hlIjJ#*^Bv(G#`7!JSok6$}` z=gv=m@-wGT&J2fxW}~qZ3u0VdSvs>Y_r33bfA{X)<6~`&<;1#mz0T6y?DTuz@fHx- zvu96H4D0p!#ORn5y`fXHEys3?Ql@n3RzNmE~~L#w{mj zW=&$ZHyB?xv3cv3qsOPyTd*d;Vg!`Hr2gE3nQ4}VL4QDj>)eRt3g=A3V8+Z6HI|X6 zg5Ci_2oht+f|`j)cw;RlL~*es8loEr%}l^Du8zg7mLozmGy@^zG>)iQ@=sUvr&(kq zKmr4L6HV<#V-Id&N<&F{CCo4jSjK9E@ul0}Pr(YdQAwkh)256B2E*a7R;#&(!gcA0 zSFhKQ!*aK8hLh{2j-NRBg+Kk$uYTr} zx7>Q`v6<5!_`v%vyY!0HPUrB^lLXxD^=q}-=;+w~{jUuNLnNx#>T0T5EHAHIc=09u zUUz9}b#Y~-7(TXs{e~@@w(Z})uh>$KG{?UFPu~Nw_3I~JeBtG%pL-UN%Q9k=oG8?r zlw~E9BwY3dm>SJyw^yo32uw`gC~she496!nH{10ZlMkI(+!>%*=`L@o_T?$Y_EJswN}>gP9pY@bEzo+*ARBdX_ixns<1K8WTs0fF35b zCj0liZ)87aA{ZERR?+zwGU{|Yd0xBimp^go<(C@3v(G;B#A8pKy>;8Q*S>YzS=*+k zkKOsb@6XRIuA7=DhvILt(`*cg>Lk8v5J3$DlWqbkyO8TEiAX@eAet&v9rr3JwS9bEay}PxwikT~P{2D(m2j5}G7sqUTSb6GRGxM1V@wOBAhoRsj*x zxz@8Q0$Z9Vd}=~~iu+6x3IP~0W16?jOxH$vOGUio>RKOQ*nb`bFRP2H#Euvl5kX9% zRRT*gV?jouj3mayuppTcp$j=MSZc9ObB3A{A|V78M?fKnw-k7|40tCJs5{|BiO@7c z1=0c_sfSi$Wi#&H=jPN~HgWAi ztvEi9kxQ(E&nR47_5|)aTBBw@z(J+k^|cEK6%10dI=P1i%}~@3vn)#pTyheSK?Fnq zbjgSk1aQrbD{5WCfud49pFmlrB8-IMejs12&CtZpaR>w$;0+D3>vNN#AJG6f?FiB7 zA%+x#=olD)cfVK5y-R!$z>Ek4&_sRU5>-XWhn0{=W@r1uVP4B~$YYdd-stvvPd)u)qfwuoo%yT3`tzgH z$6D=H;4puB?v6X|sMTxbU`S?+n1|5q^d5ZZ(c5nOSg+gvhyVVM-A?bh=bpRcjvxHi zZ~o>=XZ64R#a}KhEVtTiK)CjrYc9X+a#eY0&z>iqerhQ4vxgtbLpb3*98&-QAOJ~3 zK~#M3(5W+X$BrFQ8D4VnTQ1nWdoUR6zF_ymk3Cd^#G>r=`!#}q^y2d`Y~H%{BOm*y zmGOn=pY5zJPpz9c_uO-s`G)u2aCG|kusc{@U3})5r{DFCcR%#-!wgstA$FYkG!h;e*utk>-#*yQBY?Ck8`gC{P#{IaR3sXedmefsHV22y7A ztk>=5jn=srUikAz9-bH(yXuN7zxnNNjf}M^FoznLp`w zp7ut7K!|}j3)y9tU)Je#kmx<{zTw2tnY^Ag+x33G|Ca0C+8%BF?f?Dv!(mZx)KrCx z!CYZ5X|APUT`Sw*+;n9uS4$CqIRMDLU~w;?3&iEmn}VkWBOIJ|)vqgez%peTssTP%7N zkca4rqDw!$iPyEdQmHtCkKm#XCn%x`Q7|OOrTo=Y0{|vq$kh}W1Ps(SQTG-blBuc% zLF7B`5p)bJpX2G;9wu`v>L1-L2m4`i@Vj6 zzY2lhWB~(58C?Jl=w+#efKAFkr5J+#bi-OP=o+L z>R*Wxj4kCLiX=wTPj?w|45+H8>e(t77$Tr4kO5Ez=wIf)plSryCm}h+N$lDAXh^2U zO0GcHYC!X+*C9qlH8nzxhJX;ngDBLH#LVp#B1MWNEK49WG%^MQ@8Cd#Y;C4=?GQ!) zPU44!!Oky^9)(w;q|&DO;D#Ny(7x4Uxw zuJad8&$mX~3gyDW!sZQ|YI)6-ZoQS&#pTsTt8Er7mSdx1oo+|b2f!ak&{XHLVdbA(J6x>())Jo0y2PJUM&XNdsm8u*@vaSd0cmZ)Kr7(rf}Dnb!0A zXrnQ=u+Z(UHXF^A)ozwEGyn9yA0Ifluh$(cFD|x6Mh9j5=Wl%d-XGn=%Bu@!8qIpI zzfug#`+oYPCmw$!#@Oq10j$-mKl8-HfkLZ2@}nQ!<0#-W&pf?n&x_8I){uv*t4bIQ z%?L@6?HBj`WY6=@^?JQdceUMauk`x=aK|013ro#ftyc_IR#%8a0iueey}{chJT|HtVB9B`!mK<(F^RSk?uv<3ePe;(WEUYc zb!H)gA|NF=6q$ooLiA*CtVrm@sD_{*MN|YNagGXl-L9#bA#t^mxV+AT5g189Q3GZ~ zWTarmP#Hc5y`+A5d3kwh0SEwSwcnkZn%uW{|1;0O@Q!!9i!xqWS)Ms{^5DS(S6_Mc zsku|4^7gmC<>{xMI(6#w+urfE6DOyS&m7x*(FHHP^x{L0KH91`MjCBE)*$P~$JdQd z?Y{7m{rmS0q!^!AXDZAg4?(q51j;!CCWFE^6($254hteSz!H?!jDkd4ww?XT!GlLn zo{DA&RK($+>>odI0?5j8FuS~jIbMFnr3Vk~H-bFR%UB`+Adm_NHdRz(WRFrtqJX3d z8Z~OnC;%d$dP+!C<&051y3r%j4UIsR$T%aXifXmID2x7TztwIGisAUggoxaC-+gE1 z=Rfo5&t$c5;NZbMue@3givRLo{%B%i0svx+D#0^*OjM#|d4}wYQWF(bBLk%1$69AI z%Cbx`TtJARR-y|G5RoW2*6n1es|67hz2CwJF{+v=Gds~jX5z8A5@U=2%FKmFPN@l~ zBq&}hI33u}$_S-IFs!x^b<>G~iHRdCs>Z5)lg;nnf?SOZ*YC`-X@- zrQ0hf0RVjWI767AS zcmp%`K%NwcqX;UhW=#HH)XY4i4GaubqPI(f0)l$boLhmM@-b0MD;|OwLuJ%AE6o+n zPNrB#W07Nd9*IHHP)4pWpsR09x*fr*Jljew%ODN+jnkqlH6O@V;a z^bPGc8m0a(M?8%H35Z0ZmSz-)d!^ic?>$8^Y&IKAgoI{_rbiC!tJj+KS{+O&(1|0* zkihpKgp3ftqL=}YXhdLDRf&{^xw*J+|LcQZ91ezKW202hRZAo$!lEb+A3l8e@Zom5 zm1O}v5vbBjAsGAb(`ukW8A}9?8auuI#N@;+w|wy2UAvAPIkIlu#N_0<6DOucZ0__@ zp7DlFn+E;CFbXVpwVcy+bu(Cv|8YTbSbIfdRvorvJkOzqo6jcO5hDadd zCz8@bz?ds2R1J(gJ4yX4VrD=hSr*ioi6TH0>kWsOTzYw(M(JMa7p zh`7~m_Xd5=vu3+p?{wSkk+F%%Q}gr7E31kq0Hs-mLBRrr(UI|9x4(JQ#!VYHPESvF zd;NNr1qPAQUwCqY%#fWUP=hF(Mm@+O9ci{zY%K01n5o0KtP@^5ke*|3^7Hs zoI`11CUF{5u;iZ>c(rh+Ae%oz}%gYN33%y=X#8m9P zH{1|o`SYJYpdQO%r~+aoBdMvH=G17*N6}Sqq*$VfXLJ#-6?! z0wWc%Tv%GH*Xjm9h#?CIR*EJIu#*K*{5MLqr5ept(LhBCgA|isC}c6Zg$k?^=9sBb zj6#$S?f{?`UCta;q>_oCqF2))QdBP*#?lh(<>9js2+feNj8WB)3DqPDpdbc9Qt{zI zz|h+_%aq!eIA!uMdtw8Ns_w`VaVryG>dMGsr>ff7++L0Q)NUeV^aDg z#tJ}0RgF{`$q>-AP$M8FjwY!|1klJFbTI^X+%U5sKB0x{@t;AIdV#)@<%$QO@s}apWz(g2H41<$O$!xE#--0OO z6ComJ!INJAiICNgm~NSJ07g|)o@6Rd08{{~j<=v{A|(J-IZR+FJ`%yN16g1yV`--C zW`jps2$TiZSRxvtWm%451{!L$Jga3KRAP*MiG6^cDPux_2`S@{AqF)iQG=*#ja&#u zhNVZz1@QcZz=L5i91iRC8UU!2h>UA_-UbLH{?kf{07fEWonG%x|KyK%?%dq%#&^B_ zn!!K~?W+HesrQbxEW6J9R@nQb8(ye-Rj+dACYxllDU!`hks>8hqNqq)hNTfS!bncQ z7%*gy1Vfl4X(*W^$}<|1LrEkhN~A=JY{u@c>fBv9hZk=;=j^@LTK;3- z*W*7M1$0&2diR{Q*7tqC?};ZS`?DAUQIe*@S7tDq&$jN}8w^Gl^FL+%6Vf*E6|R+M=k4D5X?Y#b7YVn%nBidJ3;X zl0i`+ks%S%fSa!GV+@YS5vz$Js>;zL8}EDn`@j0NuZAvk^LD(x^6?-2*x9Gg-oA0` z;rloLqhI^Q!-v;z-ng~1z1#OKfnB?Fr7j0(xUw?#zL?JT*H+g*@v#qAULU;g)V;fR z*^wm)eGfLO>gMv5%UuW|^i^3_RQ93I5A96tLu6IS=NckTDVZuV6X9qy=-LotB*)~q z>$;-!qT;z)3bhBmE6+Zu0YHig&<+TsD&Q=c`kV?>UG6IR7Q18}qL>Px&&n(UY2GK6 zeoQd4q>N}L%IM zk-%9_HaJEyO-Y<{My3FM87)I0AYczHCgjWn3{XvpG72mw4uA;zzE6@=1=S9%ueWXc zTfg;N4?XnI+S>Ya&p*GnyE~uFpLpW&&ErS^$?yELtCugaV*ql_vv;BIG$mD4m6$L| z1i^g#@TDVU6UZ3AtbGUyG9h5ngL>FyT3$`TxdZoKcB`w#lnUo0rF>Q)TG~bJb>0S8 z24Q3#tjm;tf_1BuCbHZu@#>{BwLCAZk%z;T=6 zL2sm*8I#W*9t2fWjfx1&ECvjiP>h#NI;sXL2$UZ_m`6O~Y)Q^DXi5pqlK~JW6;yD} z0b;)OTIR=Rcf~RTwv6Sd3NR6oRnwj~{SIag+%6=9x)j5(8*KtYAjQeyA24F?rf z5)vAaNxluK5QtjgC~8zSM$W%)N-3Yj5HU#PoWmkOw3Nh%dIQIdj?}If&v4QLDV#;%F-9HhYPQs z|9?OCc|u+++Pho#x^~XwohPv@9hf13CRyU@A)2_n02m~dT&!&w&_qbYL=3Pz$6_`^ ziAan~h6ItuXkbPN#3{ytc|01ZsL^s=i766MS(as4q!=|R5di`@-rw7=t9oTP8f-TA z?rneIJ@4Dz+KTf<<+!S-w%E1n){c z$Rx7kn8X*QCSl^BA@3UiU}iasO3b6-$eBTI`9f2_L~YP=7a&H-)I2C_lrOM;$cz98l#Vwm@iOt@Q8XtHuG5_1+QV@DJ~L6+{nyuKtLB4qS{R1T_g zc=^)h&;9YA2$&=HrZ>L97v*>V`mZ-Pj|17PZM)Dh(%Sl3lyu|PEuiA?kz<7DxSCGp z>|12?&fUIu@5HH7m#=Yit}sSUtSvi{i6?@Y%P%_05MjHtMRmbouhxv(Gr9VLd1~KS?v)6&ztv zmVKWP&``-3B%+~$RaGT<=W~=&%07R9%<`g~5n#tj6qjuyD57AHEFmTYcEt14G4OQW zwrz0EfANcdT9);2IF5ZddFte^{_S7Ad*|MF>Tl;=uwBdt!-@@=I7n1Ws%Rl*d=*GS zz!b$7=sd-Qk`gfhBAe5sku4kjJdosjgDM#WjX3~&VBZENR51l0<|GLrpR&M^R20dU zjfuK616WR}WUnCrSQ5ywTJr!3DXQf*GeID5`A(6G_mdptoy`4R&OXZvKWKJc5>t!;6FGJO5M#_49mrWLK%!-(PzaG30W7F=UElYCiHJ#s z@p0EUPuDFdYCMunIp zf#gp&BV`eT=aRFeo~r?;Ac8aq;5o|es&z?RG# z0A{yb)Lyqdiy>k{eSKC=DFK3nh(>COIOoV9Pqc+&$bH^R&y5iwvy-HK-$zL*l5cgd zf6hea3!gpBj38)$jzvAQfQG)0NeDhC`d%asw`>gJIP+4%&SFFQxQ=Wk^I1k z8Xa>s*ZaZ~Bcs=pf=2JXEqy4GLy}A`2cr-%gEX1gdq)J|0hkfcd)Ew{im~&P*(`RQ zBkt!NAdFTUmxm#8oPV4})l5-|QG;+*EYlkyF8ax0cKg9o)dxTHXj2!bPoI4I+kQwC zd{w5D7#Y-}_Fw<&r|#@rT`c&IzjW^Q-Ez2gq^T;R05RSQv=cGKL5vm@fUwNXqqH(vOiIiW-!R<7;l(A(d^hL2s0fZ zhs<$lhBk>Rrn#odIaU)QQ~~cjAP^uTifIV3>$pl zRfX9BQrko*;`p#y>p) z$uWt6N}fCwP-8GtV23%xP0N;FaLeI6@CHS|5e zs4l7~$pM&}0uw?8GA?mm`L{*R%uYneqlQ_AEsF9%mNLH?RLv}9s-aOf$Ri@XUPg;c z15A!T8IU7gevJ;YnHdRy0K|+U2EbVX$0e96KY5J}1hdu9SxmZ2QyLg}=ODWt5X>NH zVr0x`^DIsyMoAg=n8W~?h)k6%?=B1k$S5iy#zohztgMVz$MZ#7R`rd$_x9%VC*JvP z0JwJbS~VDd|Jk$ed-r?ad;Iw2E0?a{xmOLEXV0B8!iV1Y@N9o};?zkXP|>EW6tGYF zPk-mP-}Htzl!HMZV(G=@g;^CGlL3h#7y|%UG5`X{tSW{;nfMOK?1;E@Wx+m)u=mW| zG}WuGy!OhAFFPhsJ-)sXV(T0-U{qz|s%V&LHd}ZH3L%94br6?x9@QAg`O3h|61mK! zqG*s*krYJLP%NPtF#{qM-c&-@J0MpSCgw{&<`n}=DfM0d@Pm)Ei^aX|?XGVfw94ZTQjLWnPF(E}TRZA&>89PRW5IS-UVyfmGBT-1HTXaR~yS{hMt7emd zW;`w}ar4V%u@6BtH#QOxOQwkcm>D^C&Sz&`I*@2p)KoSAg`YebF+6pEree(ZQrRjQ)d zaZGGzAT}D0rju#c^~@yscmNP$5RtkbY;W(3N2Ar1wUnY680u1IGYGLedgQ1iLBy`_ zR##SIN`zF^#qQ3&h(%2*k%tCs zvk`_ENg<@vjG7}G8*8hF7SowpLL|?Q*cIM0yPLOeCXq$kB@t#M1agGPO;vAh9xdzI zJMXXK$a3Dan+Qg(a2P5Ut&%z8KmXEyG|$5{Jg?ku7%2u zeOa71adK_6N@ywe-uZw1NB{cSbI+`%QZn{7w@*X&w;S|7}%e0|{fW!s_W~nGS7q-L{Vr=g_^YF@OFkeh()BTl| z(f(w2FlzR8b_294E8}GsFff2uwHSLdDvHt!*inXfi71#>bwSL8plZla74?DKYG#rR zC?37{*mhF`1|)FH3JNrK09{zrWtG}s1`a6u+H>RM((9J_^$tg)!F)0QH=q0bXf*nX zPki#u?OWe?>YIJPprn8>pH6=4lOMbP{!^d-{O8U+^K9Su!@=nA#@bK*@7%dLUo1f3neRP2-Q8bZ8UFc~{|p?jt&OI;JAnrs zhepiamvxBY-u9M5p6=h+p9eo&ZH7mY%BaDJKq7)+0td+B0(=4h03ZNKL_t&tY3cDZ zRS=Nbe2U2G3MA^fwq0~g-Z>`5=U+HmR|7yO%c5)hx*Wdp(reG1dvR@jRV3ZGaXm@u zLtNZ$5uhwfHK~fKt{V~U!$MVvv96mWmP8822G;i7GV0+n=0AVEF@ZSes=}KYmt{WA zIp;zMDH<_Ei6T%rm(f{8U3Fboxq>_zEWyfo8pr}@;e8)sl2kA|cEntiWmOf#T)N6R z*M|Uz>|9lrBEn2D_MzsZd-lrJt9@v5#g3UVVLfad@e^--+o@A0MYJd@M3R_9B&OJP z?U%p&rRjW5O&RLSv8xBQBd&`2@W!DJfAELPvSe44rORKuBtaz2rt|N9_q%P|iY7#p zq+&wMUFgo7IsKmZzK_W2vM#F|ckwo>(nTI~~ zp$`GVpdP4d(!@wz*Qx3YFTVJ#Z+^?M>qFaxI3A6dcy&1JV?4CJ_NF&K)-)A62gb}! zMU$jOyV&2|-@13NZc0gs*|D0Mf~3j4o%>Ime&qi9s;Y9{FX0rbl2Y4tSFT>#+1f6> zM=(i9>{72G#Z)X#A3O48>@Huvu(!Kg6lGqM6cRe0`q*{d z6HmO=GpR`Fn8>LLnF%6_k;<(bHwiJPuk+P#Z*T8~^4WJi`QGElH#d)NY#iA*wt3{- zSxkNK-XR*B@sbft2$Yg|GLn1yyI1Zzw)TmS|JX-A`eYxZ?ZVAFcR;~Z1&oOVBbeCI zk^qZ4TSy*J4zD!#A3O5?cfIX%UwZ2Q`Bz`u+w=9>DaB~9PkraAk}}AM5RfIO)iiet zCnj=80z!x}1ZDjcI@ zSNOa`fuV{xCU#C^GDKH6F(5!OF-0?%-(R8-qgsLikdohDw(es5uvFo1K8TS_q)IQJ7(&ftLnlP44U?*lb`?8Pd{*C^Tdgh2ypY( z?F+BH#t!SM*`D6*``-Ja@=bs!zBjWJQ$8#ZlSjssOk+W)B_%Tz^}x$o3grP7NeON!U3=(j;c&z0VJ~<)S`J5MuH`VG9#csVmhcQSmv~|pXT)u z2M~<%A&5mYcTGR?!4K_C_Agwz^5`Rv-ne<^%&Gg{_{bw$J6k(D{VT7${Lv5p=p&Cl zl2ZD!uY6^)zyHMJZ@KUOGgq!&9Sv6Mx(0xzXsP<^)VDwSp&vQ>%=a%|zAzq*JTNE-ny?{)*g@eQEJGfwY$gUviC@*gk%D+cf#q6` zk`O>a=Cc_AFd14h4Q;=**x6}Ff9}VheBgm&b?uKIKfShksI1C*Fwz*#U%I5y@7%e2 zV|(`Wi|4=notG5WhbybT8o0VlAz=~~RRAVpa&7Fp*bfJTcfR4Blj-EyQA^y z+dueDMo`rd;?~x^J9qAmN26oMAB5#C9Hz4=036yldg{zcUpPq$MrBbbNZT$Z`?D)o zt`A3p%Bt~bw7RlV*Y(8<7e(c5PrU8;=85@YQPm|ntg52$<=s2C27{r9+`V`Az;}_6 z_pWXVL^!s2d^j9Sir#xsV@C+o^~#_=hu*4FE$7?A*C$&t1ImTK?Ln zl!&mdt6Mj(-@bj@EcJa`R(>$35FCJ|l)A3FcIC>}_Vx=ey@-hG>uY`2YZ78ML=$6z z#~yp*i4&WBz<0d!iSw_%^ur(gfOGi3{inbCom^<_(qg{w~Ge9%v+>SlXu>!lZ-bA?AL7zsg(rcg07 zym{-^y?ggY!(r(wL-mChvAx|bU-;eKz2~2Qff!3)uyY91hd>Om4|i|g?)#p->)ST< zQB0YANIf&nr}MkFZZ2X!YzB2v22)393MuuMuU(!@r)OKkX3(5Je<8Hp zXgpGcs_>!jV&7|szN#;te|785t<|-)w(W>rj4_4ii*j#&@9y0@MNtfzL5v|IzX4Um z5a{b){p)kjK1)PQocfR;5uta!>$G|ggY`R#qZM(O( zD^cpE0i@8k3>Z{=QF~;U59iFo@$g&U_{N3H7u&@mf3v_$Qfiu}s%rM^i-HjuS;^F_ zVOm=s7wzoia-gdLL z-P}CpC`yP_7Wv*;Rn2HPm@j6Xz;O9PYvc(DayGDJXJSE;kvc~ua?Zz_N{IOoV@R}U z7i#Jq=Pn+|VFgqIWJ8Z`RMcV8YM;!6gGtmc&Se z*yZe@15`lEEFuxrq^jUK3Dk92Rizrl09|N{vP5JN@nvbVsq?-l3RNXwB8H++iA&5n zfB+WWhd$=JM^iV5=uk;GqfrSE1<63!k|41y3&c8%jvN!`#Gf%oQvix&dEC)u3RJx> z)G(p2Dj_*TB}<^JM25?eDhCz_FeNt1*j-ri76}!_a&Za+%0cwj zEE^I4*>KTzj$Kxhecg1knJOS5@{$#qfzo==Sqe+1i)DO+5eOy#OEJ`Sv%a>DMooG9 zO>cet{Kd=nojxroJ@wSzj91o996k2fn;+fT+5g7Z|7J4XKY8Zl0}njdw)5DvTRV5V zZlG$5`QnvVUg_K93j;`1!nT)P#jAB_-5^&Upsx?qR?Cj<-JabD#Q^V;hIoSH@Ie zN*21PB3;l$yN8S?Pu<5v4?gtRdl^6R@piI^-}=@M{^jSsyuVkM!y{!qiaKXRC1t~; zSe8xb)0^M)<_~<}gE5JMc8m7Np~FXyY#Qlgy0~%u+Sk7NwR`ur6fA{Eo zUATDh!g#zAV+^5#+)!^INzcFh%9HPSPg$0e`GnAjnGg-7owwir-qRsQcASq*2V4#4 z`hL7Je*DdEVI~zAG|jx7?@uNhhY!8@(#zMbU9C%RM!c+{0968!1mUy4|9ht&dU)&J zcGoR7HV(zUFI~Y!dGYckPlacfFnV90sivrA0@!u^SHJp~2zK`D*~5o7LQEls7y<)& zUt~J%jVsp>G8YfkmOS|Bbn?vizI)-qrFt+>)j#;ZKlAVd550Wh<=JA6=sXfQM9P(9 zM1;qV9ogC4`^=~RMb|IpeeVscszDWB`+47bE~>gNd|A6eAG$mXnt|?4pL_1Pzxu1c zN=X-!si3AVtdCcGQyN)W)NAX9ld8`Nbweg@s>-3=y?f{E+2{JcBcgfNB2it|OgJcN z=lOvLA7pl^Pe~(?Ns61k8V*N0J9~feS6|)R+XVsdix8u8t}J{}7sIu6kK`5AXWdXu zqOS|X^vbKRpuygB-!V%P6YKiLcx7d6G+rN%x$tT_s)u!5_Y(RpkeY#>JNr!6^@~N@ z_hDsa6k`yvvaD8D$E#~=!>%8%t|ZkW=7=TK^~PecxcJg*UElT6udb}7KHj-|XHZvb zt78Xt=*025^h_LMQqzv8Wm;KTLxR2io%0u7ySuepl~oKu!PZw+S60_HHa0>GD=Q;L zx3j-XM1}JL0%(JJ6#D+fmtFuuBJ8`sNTbncG#Z{bx|w^7O%=cqq4$p2#S}~D?%cie z>iP2yp(u(;*N(^Iqoa*J#HL>L>`Pzu5)~zb8Iy`iD4X%=Q>QOoyo_i`LP}xO3`Z*~ zn@2Z7pU^Ct04OW@vQ#iYb4JyuZVSA(eP^~eK~KTr7_1~zRp*_gmHAyu~M(17W;NF9*+L_^Pii{ z7blLN0_$h<`0)K_hD9YYbz~9Kk@2Cv4@FTRoA)kgN}vSFMr^2N1p+E3(~trp5IGIO z6*UkLSVU)#dp#u+Zi=!jUAd428W5rgsE9<Z9% zk&W$$*$HaM`IZqG4Zs;7G80h>3MQsT%w}MOo&eQiNEu6#osr%ZRZ)w?7$YiGMHN%; zy$fB+xC2Bis(LY>=a6<$_!N@?IL81GO@P4V>UUhCsL;TOz|vCkp^W(iRt3T=^AjOv zCTU?{0Eqw%4ul?E0_+aj7g<5j5*n)^f*>Fo1Ec1aA}~TwJ4lLxE_0+NV452`mh44D zL{?)1J8-2W5eJ}@O^LcpFC#hc$hpa6!rpmTqUKsYKyqLQ4D8%WoIQKXTmYJh0vHgp ztLk!hfA`SF;n{qi=zqWqp_=#ijO1OOf@_XL-?vtkxfMALk znToRHYuB!P?Q37#+S+>T&5ynP?LSo2_4%vkuUx)z<;v9?*KY1l_sgbK)Vn)(GY191 znBn}Zul8-1RG6J=>O)u81IKn(Dq-srFF51Ok zf9)@K_xB7zMUzP7i@|VMmF4Pqgoydhi9{KLYhr~PGr{xEK6B^xJ#zHQt7ajtt*wm@ ztqz*O%4j7e5va3Zn5%RUft`Elg%@^qw!vV3XE%jZHU$^{)Ugw5tE*ktExJxibdC|0 z80gdmU{aOmUU+#rn|bey?b@{~eYY5o$KHF!Wq*i*7OqeOhwMrk*SNjC6*cYdY=L3b z)SkE&fB4YRQBwn%D5Tie)gY;wXbj!p=mxVx)7jo`OcBTu=rqocx@IsKj0WS-hc*WC z%i}D9F=AaegF$oV)XA4$etCaBWg_RRPG_qtD{C98sup8XGcKrt($oSX6UGo6f=Q1j66|l^GJKro=_DG9L9I6v0m?`+W$Spep>4jg8gO zuE8@OWhuQ_8)dC}0N4ASTYUYOW0cV)jgT@7y`Dd8{IDNh7AZ zE|?IJs*1`AclWQa4EO)(|Nak*`0n;@-zyU_fr!(N6{Zy1a^pz`X$6eH}4;I7Hr6&>)6)DDkF*3E0j4vl{P zSO3oW%a_0Om9O@pH?z8~@7}v+2E^#twQZmJuzBKmRaeHCq9KuJ1OO&9lbbiM{+rK# z_JLzZ{-=NVf84xzqwpoDwe57Wx7*asXmuPyOl=}^IXO>+j+ZE910%P@i{y}RE+k1o z0HJb~s7MNydSaIYZr*!U6-kacqgCpvk-79in6mt0&J|3qX@-l%A`3&=0}x|)ee!Wk zoR%btY}=7+)VF0qQqh175G@)YEvd8~QD9jZn`^}LrPmIu0j5h>OHKt~rjQYmC?F*e zHpr|xSk{aHe^HYz>A?Rnn!M(9HV2XJSOk4Wg-V`lT<;+sV!zUATCWnGosjz1wem>OS+rEdUKWCq>-VtVNp ze(wFh^h^JKJ>1y3cRPj_P1wvKs%8iQdV2j6OC}0LpiT^?^RQ^Q%eweG|G~fa*c$a`L3<4J@2NU{lh=JeEDKM7?fpMkSAkD z&e+V9*`q!vA-f|wmb;dnS27~yO-D~oYVsqNZ} zS1xStY!RVj1~g}QWMgCF@ZlthkqhTj#?J#J6*Hs4kJhR~>uWEaf5m$bHB{ak!qKA} zMd=Z+sViL$IfRVFq#-Fn(=H%!(4Za+>bfophX_FudAGWDX#Mcv6hqhd zg<~daLv#qDXl4X38Z>NXF?J!u7|X(2vf9;0Hjb!>DHL2pladOftdv<<6h&Ehq^ho> zm?c3oR~DtO#=~LTE}}$4VsxmID_E7Z>tc+l9#pIACN03B{(#O9p)ZQApC?Iom ztDAateWeSnnITABR>MIvn@reoS(eNw5&>C4a%8H~&Zi>6gr#>yQB2#psg74yHr7|W zzGDDpM0QN9!~j-~JeV@5Id1Az1m3#4+x2mMb&Ux(cc(?a#LC2_*$egs2LjCIwOu`I9ex zL6dmLzI5zRV)Ug`0rpnPuAANbyZ`y$RX4nT{W5?fa1N0G`pkKA2nedtOo<58M1%`Z zM4*^bbiM$!rSz3KlqQR*-jlmO{>dM?bmQu$KlAky54?(UFqTVqP zx2+aMF0+^%{qRqH;Fmu2aR4}Ur2bcb^u@Kc!|#9Jd$#WF z?CkD(cJuk{o$q+ZV{d%J-~R{yTi5kP>6uB)@)+PA{mAKooJTVQ%t#mlQ$`AgB1Wi7BnBXu&F8c6+M%*2+SrRp;i{A(dnPn< z#0Z8+j3FijR8Szx99RTo$CScD51iRJvT0;pA8?oGGX z+}fq97k}ujZ~N5G|LpBMw_dw=VZK<9cU{-{+I6utAR^k^-zUbxk)_agi^+8F`%i!G zlRxqC`_G(t<&_tSfbw7m1{w4%28fzF?8uWsUQz_ac@KzcLI`9?CT3PJd+#+yHGz2h z^l|(3U;E9+pLkn0+r53`A{u)nMleuBCPxBbKp=*O#3ZVYb7hd4kpYU>Y|_prm*4xI zx4-uTAN*hb;qQL=FV9t@O>$g&?%HG?E9WPRT~`$3a5QMV^ADcBZ?dyH7!8P!2~!e7 zs~n}MnlzaJDj)#4`|iK*?%g}nojt1P>)Fcjx>&6f_ zHjm8qCn_2xjhgz@$&+2*BOrS+F$M^x%n@nEO67gO&a1+%v_{ zRf9p2KE;TpOiW~ey>||g5fRLy8XFK3Av)%!sTo=OzyMJKIt8&$G0N1ixJESxKl zEhRJ)3rIlh(ZtYv;mn{F84pI@m3_ZJfc@F5DGMS5Q6^&th5&{J>Wk7$1+1)`n`=|~ z@vzxAeE9awo7q+_Dg;(}7rPeBBmx3fMQLaZ;JkMR1a$Ps(b;@9+23DZ8Kas;oxaa0K>t^F}H2k_W^Syqe9_4X6Uv^S=Cit^<6(sqt(M}w{F~A%olHd>s$8k z?cUwpK6xK|Dx>sB2E>r0Z+lmvr~nE$L}W8*iu&5sYi+yW!kI$=LsdpVp!JpJ_Vt%O z{?WHT{&X?1(1)P= zv-Z#b;;XBxt3Uj{_kZQjzTk@D{s-^BbosIqPLz=9V@Ho~Z%<6I8r7D}6fuCY6=kur zy>t8KoiJ~YpFAd_`+K{e_}Gs;{?*LkkoxRhiPj}D~05gL@O368As?3}r&R~#l zV~8l4L%)y#f<;jPXp&6F;Ow<5%d!t4{~y%UdtbPsZCerX-XlU;R?fMyEO&Nx_xE?4 z&&6$2*G1R&A__~QBRT|h%VP#E#|S_Ji(r^_3j?)f>pY4^2F|5)nI)td+eK#oA5ZTY zZP|I&c|PHN-@W&VH&(7vRjH&>DOk273&}y28#6e7u?Y@9H(;X4(4@6yrs-xFrWeq? zn$<(EnSrJOgWDJz;{e7u31?fDWo4B@sdC+XPu$@R&odwPl|S9J?mb`5y65cu?&tac ze?Jfu0zw6&3CRFrlB5PzkeNUcQ33#{7-)ABg1F~5iPZcj^5RUKK0;D`WYih^XIHLsFj zOui|fcFi!BIH>U+owZ1o?gwo1oL`6xpZR#p+ZmbtM{l;&+YpMUf zzx?2*i^anx^>W9P`D|rn^}6e>`-gw{`1{`b-WzYaaiP~g`}DI#$2m(9lcpBE){+(! z)T<pVnd)%*HuyE204mP;6sEwb0FT@ObpMPMh${WZnNBEb46d5M-CpY z>Iz9A1ybMy0)Pa2;&E&hT#$l>l)U#=>H1^Wt#5A*hP@aQ#;6k8xGNI*sw5_7tQQrL z5F4^aYpv>r7$FD=0%7vr0z-r(NmD=pKuRoLydpSNwNwYcP%OA2+uq)Y5PJClRiZRR zOoSo$n1qlerIaFD14c1o(3EA|>#bh9cD0<0hl4x>k8BV?Bw#CYQ)s=~poGdxOAD7S zU+nf4_N}a3xO|CF%W}rd$fz2P$&wEM!kn|BVG5d@$-3R(>uUATApj}MavtU@vP6nP z>d-`u2+05;G1yk+qX>2~n)_LE^5jWGdG7pkqR~Y4QJKM62?3f=0}$FgV>aj--w2Rs z08B-vbNJA~jrDb7K#PJTu^|h2)Y#M&vKb5p&bV1Q7x5|Tba(8)o;Y=6HZM1~)))2- zbFxkdR3k(XNj`x=gk;DlwB`>Dbx0wcK6&hkXP%W1Edr^UgoGpr0>FT2&j}eYu_T4) zuU@?DoH>5{x}B{Zbbv-N1WtjCC00pZlSvc=gxEkr5nolcNFw4xhYnr6cyY2bTI%;z zKuHXdVS}LPqb<70*9a+yk`Sxbb+xjxkJ z*ePetbw`hub-A^@+bcTVd=(je)5tvJog!5;Rh>*DlV+Jsv7NtA-p#C`pn-F8IIS2GGih=?)kbW;4t-jn7;LO|k%<69h3WxKE-s4X|-V5hOuO&Tt|Qoci6)uv=W) zSjT9P*|0$|#A#>eQZGwC{G_?dA6z zy|XtMHg)Y&noOs6-+lKjH{UecoeUS3d_o%P&ixx3>$BjV4Jk&S!ORahQ^dfMbJf z=jB{Aow@1O^XJY_CZqmRFNLVaq@W@qDXFM2hEW?$3Rp=furO>o-E6qH)Kt}#t5^Gj zp<~2^(3+1B0V%{Jnv8YE+C~CE0>UKHwRUyiJ|BDw#V00_L_!DzsD!`_NhpD$szEGr zH|X_UmLr-Lf`&;kDLIoU1%(ts0RlFUNUfErSM)#?Ko%Dlx3;%4?IKf3i4wKn<&eZv zV;KzPE;F;TMuKiHM+0ayhSW4Zg&313h|F0Cb~+vfpArlD9p>dc>k`e|2z)u69y@*< z3G1dt>}w3<93>)0jO?ertj9Z>n}?4a>GgU$qfyiN6eF@OudI~wOH6DOGn=9KmTgFY z$e2R(u{OO92&9yXqF|%boiUl?2luU9xq7+Z%{$I9rU2?gFkq5(2$6zjS>A*yr$U=# zts&<^2vH&`prj;`K{a|GBT$FQCKPm>vE_ud_bDaY$(Qym6rE0%JMSxz5{jy^^ai)@*J6bXBszE6@QjjL%t z_LdhGx3;&~anqCrTujlhQH-jaK^}d7q^Sr1ZZxn%;t1vUDyVG*t;{ME-`K%o6Y_Bda zA=)gnYDg@+HLZfw48pAF_?~Ihi(9Euguz`=baX0D{RZf@tt1u1}X& zI!jB-<-7t!ht$?zg#aOLZEqhtcIdZ${oTLwAOFO;!)z=9f*N2ddgh6zp1$eKjR%$% zEydpL*T43@mp$_J2ie(^r%r5cZZ0hii3lyR@MyH_vTpQoG9G7HZmf$UrLPti21U^= z=jHwbt3|gnolQkrkrtNos?+HL!EAeLG9A6?O>aabXcby)vSI*ao_OkMlQ{t-Vo)T; zqMI4VH(Y=G^5wPn{MF~)`S!Q{^T$6DLoCZ_mN@_jptEvz|7-5OvVP6w?pJ@|Ck^oC zY_zYp004jd7k_u{${JaVh9I<>Srv;G7>TcJZ@uCbuRL-5x^vGwUHhtTeAn8CAN?jX zGjog{QDY1t2InjjMj}Pkgv_=D;j{siRyIONEu1wa254c;WHScPEX()&O^BArdq1Dg z^E_{RFj)CuBwAJ@w4E56T($dOmS^ETGb+B*$fdi0) z2xEwK429`9Hj4|xGpA4G&TMb3U#%NRsc!1!<)y<1R`}q7TW+}iz3=OO^WlduLBHQE z%UM}gB5I9`F{Y$hUMwu_YrLP%=2@O+S-yvEX$61+WEfN(nLSmx{i~ha?QHLW2!wz!s){6^ zQY`25&5$~I4sDK9k|Yh@1Ed(#$EMTC<60HGFY+9Oh|sXDstOhIP7xYUNR}vxAd1G+ z%ZiMNNgE8Pshby;vlwFxDJ4lMXiUL-m)W2KA~D8Zw>zGWhl`8dPIrBCgB^9}G#n}bMG2ZR8z8S+CF(z zR=r+u8%?0< z@_asKxl!DuuCienj&c9g{*U~WfruQ4I)5BLbfOwQ3!$|8s^;E zlziQU`ez#MFDDCAeMna0IRgoFsERh9)*oYP4f)o-Y zan>T@yetnAA)+BMKSr{0W`%#M9x|ea9~k&yfgN7v%R&oyt-sqLpdq(d}my8!4l)@ z;*v46wYi>U4j4x}yG=DClwQ%RtENnlQap5|zqGKpE4x568tsT^N~y^6y(%SAmSun% z%1N2c8BJ=MPSGdO%yO^WtLth$89QSoiM1vqPlSz+f-wpfwqv49Mmri+n}(cmSx2B@ zXAO~ahFd673T$%`51M?v@ydH{xc8NJY+l`zAk1Wd6A+Cn0uME z?GD1Ah$sSyQi@syZz$W|ip!2=I6b;}`Qqy8q26Hi{KbpMj-8Mc+1OUcAW?T`qoUI- zROeOQ8+6OE4k2{AJvN4!P_f_ZB7&-9E(cM>s6?*lmSydIK*SW91aWzlR#p}U-NJjH zNLzhmODoy8x|-+NY+gU`nFsEF&1=5@`@Zku+QuV~KDyi=06^U|b6*qU;loEyow`1z zREMgY6+4sha4=k6S~0`|2%-ilCXFB{(U37nSynv%!VA;sWIh@v2|y44H#Rm89y$<0 zP>~p;sx(c-%p#aM=VJ&hg2mbpLR(*HQJ6{Etz!U4#xM~nsZi z5=3K6yGsh8UBHNlOePamHP*HZZlX3_4Xvffv?ramwP^rAA*m>V!9CMeQZ;SR6CsHr z3Lr!Q1qD*0?Knh`O>D(ux;LVP7R8MQ5l9pOBd7sHq6BJakMa$O5cOL-RT4yfF}m{N zp=VG20LrZx1!0f#k1Q%t)d4y-A}Udd6cCl!7>jIL#jFB#moEm?b{vizWr_QJb!up{U7+?lTSXWF=km7L_~$OeQa05 z2%@CKmL|KK|N1Sjf9?PB#?jhE36j~i%asHWfl-pn92!ue?afgWQwT8x&!nKzDRL$_ zcxW}mWo#*sOG~5qOj42@-ZrSWFs-fl=7kz8?Q;&7&b^qTU%S= zLkJBMS>wvuhXBD75on4j`8>;j$hzE1Fia4V#0aX2QkGTj@&svCH!&s<1U0HDHr~YO zvP?+IYHo;3rx#Kx%W}}~BU4+|OG!g$RFpvwwDxn*PS(prQwYHazp}hg6h&3eGvcbM z2qgGGjI-HJQ+gsBRLXI(d1jo;axrXD6hJi2gy@->86==&HifEg$`qp{G^QK17Kq*6 z0um>IZof}#+Bh2{MimsbRBOF98*c{zv8$cTHFcOb4KP(@<(nu`yPbYW&5Mg?W=kA) zH!nOqn@ysE?d1d%pT)%pDKHUaXvWu=5 z%;$Bwe04mX=bb#uZR35X+YR1(?+cf8iX!*~eo~kXoNsOKPJLq%xWVe-g~er*6ulRL z%sDdLj&=7fE*aMy)zh8{1DIFgYBk!NHj14^i)Zq@7esthC5fuyTt=-$O$h-aNNgq+ zCX=nlyB$DX@On@VomQ8(5C>MA?2hx(&ae?}_3)^G1{#^ZaH1afbI+^Z_ctGU?%DCe;$muIx9EbBh(P<*Ct^cE6D7(WEf!5^Hg+fH z7ncr?M^~*QWOwb_=4>`^nr2~PVP4IWByBrEU@U4i-fU(U-+bTACr%z}l6&&(`lC-? zCOaU3mMq%d=Lpd_CN!CiqtWbp-}2VkbW~Lh8AeTlMl?1}ZHzm9-E9{xY`kz`vnU40 zjH+ZXq)07xSzG;e0%VEkLwNq&g&R*@-ye2-m?e=`tc@UmS?S}_P+#}$_y5UXf1>CQ zRFWcy%J%lQF$RF0b1^~inqfAt#1<-JxF}p0!=hGP@izep`2{38yjHXzXB^w(;)OIovn!-8)BtVNmA_l<= z0J1SzsFO36*?#@&4}Hh|uReX-?O*=*dS+Y7~sa6 zZZNs4s+uVa2}nUztli6qE-x+rhu{A9gmB{MF&~@pc+|_X?x45-z-rSp%!Zlf^H~f5 z2~$X*>b(a5B9pni3G<|h*fmXvDP&gLyRP?<_Kew)Pz{^5?n}5Q1MK(v?WyHO{h=VD z%d+TwYFo!`u$LeLDxfM7d`r?yMwmp^Aii;bX^+95{09)?03lRn_lWj2;BRw2B)90AdT4#*;Au zEOhz^*r<<5n7J?}CRLOBM!dvF9(m-*;loS)VfJeKr7wTsf4=v9`<7PLFTe2QlTT>! z4?Xl?IiKEp&pofZ@1FJb&7;ST{owb#!2mq*{H2G!@uk~u|F+-#_rLN(|K^vYuk+j* z5RDQwDFR`#Y7`))5USBjP9A#m>+i2d8+A}5RS*$x(141PSXUsM^XD#%r?a{W2pLia zqzDQqqsg3EH@3$oP8=8x2eogSx%rW!Y49 zmSqHJ3_?mRvQSeBegvtWm6bu9R&il*->jPS`-8#4!24!8oB5^!O|-XxGQo#b*HyI^ zMzifO&xEq>Vt;XP;e{9SPQNKSoDvWrnmT$m#yS^U4=;$8lQ`Za)()EKj5rB9Yx7JX z<+%f+0Ge^$&5OEjh6@YMy2>>NZDN40uXM1`bai*9DJ-O&V> zFr`%0JI#2@r&s(=)`BdxDBK8X(=cBTuq|Ro!pbBUR(K&}qF+pZKS?*#8C|n00 zQ)SXDhuy-#v>9wpo1)W0<)Y9!HkbqfRT2=!7&}D|fq_Dpt=sb1cfR3v$PRq$v*#{d zK4-E;SL7BUsqwxhNL5*O7P^_SOViK}@P zqF){iH`mrBsxjGUXSWRA_?`P+-v6av`MK$&UcWZ~%41jlzd!qE*9~P)e=R7&s;Fv# zi8<7D2)?X$<~xtP_b>iqXCU)N{^C7f|Hx+^D^{*IXqfjdcSXk$bBZBIN+QS#O_SwU z{_j8jNvF};qaXU4um0`VF87!A8%CQI3<#`(1u!4@z=zhhcDp7cV|}Or z#F@;oD{`0T)(3LPO_G9}@4WwIuXy$A0NjZaM}Fnket*zgs*~^bhL+KnK1Dz!1}fCn z2x1M@VY+qY-~aY6AG_|*VBz4e{nmee?RSApfqDR|zwj%6^u*ci-Y{3gDW-ZpZ=a4?Y^TV4d2Mm2ICAvJ_WD)C*163I zqmL4!zv0x)moHA9J9pLOg&NYs@!}2{H5D(JJl&VO&tv? zVyl%(L3J{p-Fxr1edY^~k9S7hPM?{BkE&Rf_4#w>Mw4AtJ#qZl6OTOcm9L#8Hdodv z1+vO4DWW2vMjS3K+;HY*V%px_T3K0HU0HtNg{z%T7a&#TtX~wZ$2TR>B&}5d4JRQ` zGE95)JCJW7HY{UO!KCVCd1YyG=`x~mY$S%+tn4i=4hDm-efevru0M9mZMQN)lLP<^ z8&%rb9k+H-7hb|Ie4+dedLN z=daG4d+vtouRnI(kW%BkfvJA=QhtG#LO1ndmlnf z5d|9`n2mF`C`^pLX(~|lApoF4WMm*zOm$OQV~L=u$}B5XTj(*QlmIBjghU|(B+NK- z#^B!iM*x7^-qqfXNfHo61!58vCXSL25t9NU0fQmcq@W0_$cYqyK-xqPN=l#v1TC=0 zAcHEPv`^~*x`$c^P}R1T@M2U&+7NErSW{3YLeTcqV-yr2gg{K%(wqTRfkhNaG$sY0 zHUr!yRg{?9Tu-Yy2q|X98qbT1OQPrjp1*jZ+Z!w{Ed0RR-qIU(zWK=dS>-WAj>-IL*t^yi1jG%^$3aYYmMgh*AJ-@LzbIzi1Y?y!z8ASz5 zDJ4b|V)OiSo0+BSZ`@yW(quf#tz%+DZlWq^jE$R&e&G9F|HRp=Po3L!#lTt{_NunI zbxxv41jjI3hM)e)AL?}S!C>M4`R^b6r+@xt-WyCNlf2l;twq5Q0vVGPxvxrS!8>t! z`$_lqxBlRz^-IPMKk+ZmKKStS)|!~YbUJMXr!hqo$g?bZPpG~rnFZtafBF4iy6Y8p zqsMi1_z?|WASzh$E#@7xnr(gT6A8E?%V@D1>cYgkV{K21j>5CePT0d0}nm$A02Bcc=Bx(u@0_kZ$tfA0^E96!#)F^0OSQt*<3%?!5YFa%bK z)2(0smG6K3cl|4X3BbuWzV+Sfle)-yP4q1cx22M|it2!|@=a)JnQs2UZ~xX^uelRc ze(YzD|EK@@SAX)CA3fMP+>R%Ez25fD79cR2_NjoZrdT>>?z;O`D~E58vVQl^yzvuX z__eibW5az!Oi}8(a(RZtUBf;E09{?(w>#ST^r!#v&EIj`4JU3reZ$f3%ui3o{{8>( z`9(Vb5@V<(#6%E6WJ^^!ZJLIy64b}8d&%PJ$;IV(?0UOdK1^9JQWBvynQW{zZ1N%# z4Z+7=w?CgxLS6piPygKNnY*A~@7m%=-+j+tee6d%2CL9O)Y^Mjm<9@Jz}B(q=KcLIc}<*N zDf&xyKsUMjGj2Mlz3eC|IhXL&P+O^@q<3IYYAN<;* z7j~w;yU>R!CP~DqF=Wp5`@N!9n@sId*(Dm#3dO-|G#~7^FSip{5ogW&l7j zfdLRsF|c*aM3^=8^o0x8PMqL>3nwSsk5W${K(+O~)Y0YCs1Xiq8xFLG7n zMJ+uOwmT{!dJ#C=LR?zHI)YM4iD3`WqHTsoq-AI!q9Ov5rU1Y#>jglQYAX|W)~1w- zPS?jI0_|T_B*a9_DR@FiQFgYs1z`XF{Qx|fOxD-eUVHzmzvp|tJ12?&b&w|>f8xsa zZol7q@aqq~|8M_pHk}gkS04P@55E1a_uTQa`FJ!*QiOsCoz0{PNwxA#Q-#G|UsXf! zXemf?S!ZWF`m;a(b5#XN#9Wr;`~UiHZaRK)vD^8PAATn@fBG|@eC4a|ef@o}3;^pp zV*ojG=9cZP(fJoHzvQ-?g2IWzM~@yp>H!v)S7Le!k%$Q>U<(w`w(Sip{=kxZ<^A`M z)-H(%QUXY*?b#7co~!7SPd~Ra3eNN_TV!n)a^C_~BOtORBt$KJefF7aH{X1CxX9zt z$R;*yLAC9i&t{WD#}D51k|R$%@q)Sz=f;Otj;%$ORr87qyS2OVmhZmnHLtu6Bm&u= z|EZt)hmZYi5+T&-WI7Gey3A!xMcGh{k(k+FRnHeX!@FPo9e2YBz@9ku@_+fU-z<84 zV+;|s;F)$a*nZ7pRAaNc+&#E&<*rxU1@kex{57w*`+Xn(!em}9EDV_`#uP$w&Kbk1 zVhzt{jj`53lIiY^*B!j=wlkP_@1*4qJ@D8UA3ED#&SQ+mIz>z(#v13W4z%Wg{524&sD ztBVKs@1KmW5I~GcG$CS4V#r7mVoD*-%QABrQIb>wgq`gxOUpMLIJiGZY6EV}9DQts z&(5{jL3Ei*O`TCH@&qu0P=ke~L1$w$*LIHxV2D-0v277Js@m&zNA;{~!t(w@5aN7y z)ZMqZv37~s0+C2m5EW4X<5~kX6EQP`fqnb;cLyuwZpkSkmb)9BJ&Fx)4t9!C1X~oU}KxBz6ut-b@rqfvf=nuQg0B*d!RfnW(B?1x}W+Zi% zK@=52(!v^M&YU}Z@TkeV;KhJ!Pe){#t*aVwMx4uaM2CDkq$t|S4`AGEfPs;#k(z5B8J9SyEmLX=$jf8n6V{?`VjJ> z7%Uuo=&R4VtZ%JTP{H=lVp?KpYlLHR3ZgBK1u+Rpiq7_C(`t7#?)CG!N-w(7K~#y1 zZ$_tYJn+aPPd@eR#VgmQj67UAy6@1b=U+JA$#YG5<=VA6bx+@VOXKIeyIYE;==Xh$ z3>H!I%+6Is!f7KxyxpRAPJQW z@nmPz&59U(ZaD-`2A!jrB!tK|5z+Q&gh&abX_}>_rNlVs<+ zUsxLSvh#A}8 zFtLajX4h-+Q+Nd%P)!i&~rC4@Hq zZGhSV-Cl)Su`O(qfGXe~BOejr#c(dQFV+`7f2~;85+zk-)D#gkwJ%U)BvHT@m5LTQ zwgg0N2S=)+*mj3hO*?R4!$f5)Lr7VcWdNnpY+j8=x>-FlU`Ipaq;np*!vn;FYhLDLcN{DAl1+ zuY<+G*S_)SbUe=U!q3Vg&&j$VaeaNw7#J>gGgsVv=1g5T5n$%yXf!g`WY#$b%v>9T zjvxrc2;$p+0wL_Vur;>DWJRLncV2Sl27o$-fJ%swfDjcGz?dw{9((lccpRK9jKv6v z0FX^9vSvx3fW{_OZ9mXNP4Z7ZdFjSehlY#8(e{|hAPT5hL(j84LH!+ZNf{%x$gh-tvlj0SZXFKo&)tSVz$$Da&2( zjS7IGB#9vo7Z&H!c?_{GXJ>9+eaW47gK-f3Y&sop@7mmAX2QH=%ovyfNey%6&=8RA zxbDOpUL64Rwc1fe%Ic=_-A>=-&ShjWmsBkfMn%Pxz!D=!tVgfD_cpc*${Et&+O^HA z8`m^zv-6ljLSsS27$d6II87nOCIem=?x%bJFtphUKz{zx<^G_Hh=?SJn55eq5D+1C zT+uX*Ay$N9xH#+`1=z2)Mi^xIATtxgcJJbz#QTPbjmeOV3g@{)g5l!ffGc1RclRBh z%$jTKvpjbMBtVLQ3JjQ<6u1#lP1?+x7*cO>zblS*77qa6x#za(hO$8}DMU#K2?(2} zOcGN{);b^q%pv(s-d$L^4)D;zk$nKmO)x|SF^Ht1)0@nu-UlEcKmc7>SWp%5fe`Y+ zD!>YKIuJT9Jinm~*5;N?&ZhKx25eMhvdHYcN0XBsUfT6r7wS}Y21oZzYZD+NV-hB3 zT;^O;hY+;o@gOrsQ3FB)$qxVwp?ebG*mzzL=4@Gs7KRJE&u;VtsUE~%Up=ykYA>>7elnJ<-b+kX6HR1gq_(;>tzw-@mD*CJ5gH(z=Xe4BL#ze6R zb=~9#Isy<<0-#=J;lXb_{_?wCR?a2V{wrU5*xL5t0W$|lQdyS6#f7$@0jeyZ8k6v) zwfXrglgVh(T}XfPzQ1Rn_Lc)NF&acp5(L`92BV@9X5GOTzIwJP|KjwC!>3jxC8NV(uf12bsuDyIz?kARfwsn|4?b9syZS40J5vZ_kN?eIbY8y`Wntt_>NgcJl64LJa4nc1e6 zXaNw}C@HihVgfWolJ@2zs;aSVG6AUJs0ookTY_-AT@XY7+^al&tLei8+SWz(N=c|1 z02n}VkLTGQhScm?l+|FHl?DbBU_hYOj{)j|m;ho6?@^INpA^PsgE&2F=#)_V#$TzP34=RsfJpU6rOc z=#6%F!@TSa1|cSGMLVis7??QYZodGCO-#ThN2+60g|exedR`#{8wP~XREx`ts|ODg z>N8KBec8)ju7*Wb0LrFO6axqW5FzX33_zr!1eg%GljndCk~d;d83Y)S6q7>qyT=dr zf8wWpw%OiRR3HJx1S*<{G_$z1v9q-^b#4I>Gyz#8A_PWcL}8n$wg4CbkSJPMC&CJJ z_1ex2C-+V4q>R2}GKVBYF*Uv}_pPp+K6Cw-zi|n%3rfat0IL)KEG=v0hkO21;RP+x8btQH;x3!LIFCK@!cFfFnl0lr#~Wh0Z`0I-On*0Ipse z9X@sJ>iSh+qgtvO5!X~fMZvX=Hie9{V72y6Fw6RnK67FJzWt)rKYsEnF*yQNias=| z=&TJfRI$>~0HUvxHBK}P7xte$JG$lc1l;h2wfO^|{lZ|dETT+m2qI8Bgh&C%{{Kw9 zS*)ztb>Fw9y}z%jPMzV7-M70*HixE$G-*oWU`bRY$B+WZu_MKZgeb6`#7Q0;Adg0Z z1V$brMQ{Wp4{>0?fJDKv>{uo#Q530xBH5gqWH+boW)Ea{-|pLYI`@oK^?l#oYskZ{ zOZhxp-~x5dsZ&*ZSZn?N|DV({k;ps=&3Eq%G>to>9sKt1{mUCiC(HeVah%jh7~9eo z;gr%ijt9HD!>0DLorJUJUOukWcm3kGfA`~ur#4&6rZOOMN3P()Sn4Dy7Up1%#560o z`{6%+@`FG9!Dqhv@}KdnPs zx9d7^aG~L3LXW=h%(YYtN11hto~j*u^X2l7|L;GYrcIXa`R~4T^`W<=MAN#=Qc993 z^UiF3%n5_aRIJu6Wt=_u%@_TD|E*7QB9d=>={q;(vjvkFM6r5$dP=!t#=h&v^(N(f zc6!>Ulpt&WL%;t2eyUbGIXZjkrB@agE`Vdp-C{}D3@*rOrltuHkg2=;+EM?%{?iYo z+?A>3uG?EIPESsVrIcD#lM@m;F?h_AjAh)}pU-#aTBbkzvoEOX^*idp_fF1oPiRaI zySuxR==^l;)sS(jl^i7F&gBcAfAYDThyVPwS6>ap)oQ)F+})IMEYo7PlQ5YY5+GqM zm7G??8kuJE{imM3{@?!(|A%veI<1EF-oZsqZ04ob`C?{n5a5#ny6QL#<>XrO2XA|Le{V-EFd%>tf&zu| zV!8kAZ+-_c5s`)wrDkVh5%<7AL?B|qg%xJ#x_owYSg%z;S5Ssb!GKa@ zh`{~5OOT-x9*e$l?<7!(z>2+bbOX-WT;I5Ja&U3)==gk`ij!Yh9BdRK==^;A z>mT^Q-~G>i5#+F-}u{O0!{xAR2KmNs^ z{|`@A)0e*dl~QzPo)3>tp7_g8l2%A_^`Rp^JsHbr`ww2ME^Y3%9#@aP`B6GLO2oBR zqNHl$diBQ5*WU4t$4*X9#&NT^x2Fp3Zf2?J&za3s)pJT#D>OC`V)F^L8;PqSQOizl zw}@8V-FFP3AV^07;R;TK*m#Wr?$$abKQJQ!Y(=^3+a3usJ8ntHMA&pR_mkh+_qw|Q zV8r$pV@tt>`_vR_u%s;oFd~S#HIBC9sryLd2!L=TaCb%k4`MQlz=i}wB9P3RI+4g! zOI6PuM+6dk1cW2g(fQc`Al-a-pUN~0cZcO-ww(2|Ud~T9!qmSnefBM6{%fIrn2JIn;G>t%`WIT0Q#cn~E2yiF1cYo6Y*6hvyge z_wT%M{o>^-2L~7K-nsprcl~ez;D`q{srU(TvL_!2^y(o|uo_~%xZ{HyiAOc2U1|r`k1#$pjFhUST zbr)j7?)-FIZ}h^2{iA!w6^#HOEFjF-YI*N_AOG~1zq_38AyP42tyTvY_SCAd%y%xm z@Y?Clg*DOi7k~N06JPk!m8+K>4Vbd@4&aUim=kxsY$h;M;clw>{43)>|Ip`dy#Bg$ z{o&!X*Uc@$5CurhBoiejrp#&WBZ}|t?u?twXTSd4@4oWN16Lk=>pLF1bfvH6h{VjR z^(q1Z`}JmXUdFeUN5^Soq}|=!F46bi7=HWrzi4WE7p~kpUY)E<&P%OTL>jWw+ydOp zM1%=cr=8tPFT8g68~^k}Kle9&=9$mE`Y(R>!_xrEo#m#~1kw7CW`<-QW~u>b8oWGs z`R4j}{`Dtry?!g44v&tmJ#_8p-q|orU5^eB7%XUNEt;AThuGR# z@q4cvogVjHW@3wAXffqQ&D@oV2D2nWvn6Hv(C>fZ4?g@kO8xCSw|4g~9UdJ65g-<; zz2pFExDZ5ebn2yyo@KeEg}L)?(Siwjtb$eI6=r=Uu#vjLE*!H z{KOMqdG>sBesb@$o6oD-X593%xv9@)9j9cqV#2QL2m>)B&BjVkee;bkeC4&%)8qBH z7Rs~vo&q&|v@j$V${>l&baI^$I`Dk=;?v)G`N^+;zo;=&0L~Y?jmDxut7#pAl!Sx> zU^bg~^E{3*n=en#);I4QhPgWe=Wae%^FSI^i+eZ(hJ!1Cg#%MC&*t;nhesdz#1~Rd z1PI_cNfYPR)3X*)&&&~S7=Y2uG66}JVW^+}^Cu00DVdh#?s7eBYPdikBDcL1fQZL& zXspWR&a!w!np+SMb@Sbm)k<64hb@%CtQr6~0p)ad?{2A6-}PPB4aEZCb6@`2v>E2J zoaVh%53|i?ElHMhv9Q(I`Oa*oMP}6?W`61A>!yZ?-Ewyv3pj#H1W+QwFtbS~b@#A@ zGF4TGs4&V3NgAd z07W>WLqOub_~;gp5~2X;WQCZ7yUlttpXXLVo4Glt$9%p#S-GjJnTIN1Rd>qksid4D ziC}Wo!{f8x`!|2|{7ct=?eG8E=f3p$uYBpLQZ2}S?r;9w$@=7<{XhTgY<0e#3L#C? zK!kf&E7B@MRJOuO{vu(0uj*7Y%CTL z2*RSK6^sawkcfA7cAk0e*|)sqktd$`-22}5fm-XAzw+f;%E8V8(IQItlxg7%W7WlC zu^EPx69`wwK1{FyG8c2*9j@M&7ioiS^2966E#Ci%P|9L3K-aSW!l5GIWPCsGxu*>TLnye5^c?U z7$OI@k(qYDx|x={yTepZ&sNMVsRIu}thJizjW=%HxPCn)e(2gmXD27O4-flC9>$ao zu3VTVxOM&Y^YhIQz4Prq`q-NN%``mn@U@?O|4%&i^`}qP8wz;mWAFHH{=q*O zHmmh|x_ zQxda40u0-N92)o+oI?aW7gji5k z$J59D=rf=AXBGKX001BWNkl3yR&d!H2>1)?-m&x2~-_1Bn-DUxJBTVfqm!<`Y z5NW+$L(%bcLWtY-oD%Qs^b~4!b$DXl|!x`lkIov!=DjKtL7%^zbCv zt$X9fiK=rVl455Dl?3-j3wN;y3`5lLz~PD41cWWwU^ z5hg5M&WNN{8QSCqEW+HFCEP5~A>3R<2r0sdbIZNBe^3}PF>tLaoDHgZGZjSym`9hB zh(v(X_7G_ibo+bzM`yEVxb_AVXA%4lG0{9dK?LJ&UqNtUEixIAk+fx8d~>ucUP;;zy4PrAp;Ta z=bdzUtVK%&LQZ048csl_p%{qZO`ZWBz#fr^iSQ#I`N+pV_D4DQPk!}luU@}?eDCD) zmCL{Q3qL#CIl$cQ?Ci~Umg|=egC);qO|d{Mh%}A`A&4mF+4=cd%S{+ZB80Bb5s1j{ zF`xH{XlCtv7ZGL#01;y0mb7N(_lb%2?{`)ryallYK&`b6RgqXKf&ekJIts(1(LP&? zWh<2>Xi+N|;1TV&HeWStO9zSo5w=DY!mXNy?(>|tRvLHOT7~fbM@O4Z=Lc<=HY!p8 zY8LLg0h^g&S)l&z4Ni3{NT?L^Vh!q)a$Qb_keyjKRr9G z!}Q1_5B>192QD5QeCOHcjnaF6`h(*HuiPxpfBz+QeeKm(zxC8NKlp(kzxKe@|MtK7 zFW>f-cYOVu-?@8q<3IiR|LAZ3@_(|ivRbbXE?mBS>+Z8Je&sLz@>3o@>t@38;)^fU zNry6Cy>j_yKKRp*KmPds?#|ia(f|05{?Ti%-hBEyPcIic?|J-ja2r;eP4Q1X@#M`r zXSLuTeDu#h`Kc%0_ult)y-dUS@WXF<=-MN@^8^4xfp@&)?W+M^dFjSD3~rS~BAWlI z#V2?t-lcfp;Rj7eaWjN)BSLf!i!OC9z4R@~Gm?(T0|StozbmE0EYNIq?korhYK90b zK;R4s6Q6F5!t<`+EmkO}f0h+y%0Ty6E@UtJS@G zN5iy25@>*mHYU>`Vi7?m5BISMr@j44fB5k~i#jfryO`Ka`>qRb#WMonY(7t2&Mcc@ zz1-Q2a3-4XE)((UGp`Xrl4Ry#DznVN)OlL;S@`bZZF35blo?nPSog9z? z7!?p9cMP0+7G$6@xIvu?d9u1rIkg;2ck8+t1e8)FVf8{#g|h>B7&?v{a{vP%4AY84 z37Nc6*(eCiqZuAut04EBTnq`+Jt927JyOau3t?hT03d|5)+lCDDr6wkrXK@nMI8Yk zQrFEiT$q{IA!dEIUT=uF`3#as+d0>pjfYirLJ-Ok7~xE8u4tHYs#9@~qodODfu>uu5CzU=^I8f-tcMLZkZu4V5HkzsK3|&6?%utNKq;l&u3FJHm~NeHVcBSDj=s$ScH=YCI--O z2yiD6Fso%Ez%DT(LgSzj2ub_9h%mOv9QRKLK{E`12oqvPl5OfRiZCL0v|(Lx4~EEH z)~X?#M95XWB483U^9bW4<7O13#ALPXFXp?udyhW)wr8GwhS4uxy!i6VuRQhCQ*VCg zkt+{8@a!|s?(QzHT)v71IVB({r7$M|UJV;z!QjxwV*&RNN$t5SB69*XEt*hFO@NaK z0V7h9JWVBcJvH<%TUd;n&0;xY;i_eKKI{4!G^mAE7Ba1fM1a&JBn0AIqB0PXfNPlL zF4y&X8m8a=o!=3WC!ToXGoSwSVzJZZS*^O z&>aX%c(a?g-%Ugi_w}_ciJwrB!khuZwIT>|w15q0aktzqI2p-30>O!>MQ{j-Isq79 zn>KMk1SQ^7Q`rrqD>L*`*`P%C@Zw27(+qdU^{@$y% zZvDi&F3!3idi-5aJ@w4t-MioV_H)BjN-g7NI$xdc?HzpoWH?)|-1+L&M?Ukp&wb*Pe*ypuEIA*ao)RE4Cy@*D-Ko^ieCCO-ef7y-`;}k4 zcxnIe=Iw)n`7i#$&sWuxljGB~<3}HP`#4N&@W{1CUVG#E%dfn8u)qJt8?Rx&#fz7Q z;m@yJyRx@C_Yzv_@%g#1tk$BU!m!`lG^w^>Nnp?n^MFH|=Ku*o_P**B4QKsqGj0q-y`HVk1gR8{F!vZnZE12l z^F07%>vXVjnjAe#((1>jC+1U3aR{efpS@OaGI!46;9&-cERqwO8Udutr$^^R$Vm?G z9l4f{d04M7^)3{Kv<2U4Eh<1`nUrGE3CE0ptCQ1k7pAG!X(&mg-8_g0gAfqRSRmZm zx8Zk?G z8Yk7VSj?trs9{D9h8U({jzW~GPUa9zw(QDG>cA}F;egaZr=2;IrWrevg+=L z%;HYA8rNn~YGp=;V59~tSe3D(6agB#KHJpQMh$r0BdTtuz5QJh0^xZ-S1pEtK%vNh z=5;eo;e>#Jfg}d4hzbCn<$e`ssu~_1ZWivY)ey02^u0uYAXzv8QXo4Jqfg^RfJzwd zp+Ou3Kvk_Efex*tLm(g`4s-(x7fEG3dITUaCQ~40Ger<2_AtPh237S&9e0abtA<+U z$wRAQgsO%^7_6p^BX-o4Y4GsszF7}B=dSCjPmF{fYFgd8$l*o==IYf5xP}1)1qpz; zQ%KYZ@{1QPA`(Op^K!W)@)V%zuf6(O-swA#U<$%osu%70j*^d4aSsizU;x09^1Pq4 zRI99p7>mA-`NENltC?-q=QP{NT^9%juBPkNMv~aZ(9zwGk53Pe?lLh+KYE~Rgdj@J zc`Or~5i#e4;fPVqfE&~!T0@i&tW=?ff+sUb9)Upw;SMN>t^W=H4J3sEsn!Y*-C4|LJM;eF(uLJ#0JnJ{hDTKKj1Zg{yfJl{ zh?*@b01~3Q0ffgk@57ADBLN^#&Yh}91POTsMCy|aiPx)jC~Q_|i&>XMYOUs&fYAdD z0i6)Skr1mDX6`%{Fbod>MkGWN8m2L{Jo1)nzx+#o=SP3!M@lVj`0~rIym9N!M?d;! zH}BpV)uySYJn#A$U{Y0pmQg~(xVd%n*2N2#=JOd5o}8Rc)A;tczb&Qo>MPfC>e^I& znk>SIfF(E4$$h)3A#xL#BY>MW>uPga{QCo(HvcKLxQBTKbh+On2{VJnK|yji2xKO8 z6C~PpM4S=Z4|75fr*I^6HwHw%e{q5)ZGjfDuWpD07%gfa+Y7es=@0}UlZMBA$aDMJ zCenqYxrGBDRk**4G^-M71Q8(6Y(5tehyaI&-}FfS_Ba0E!~gb!AN-m3zyJMjd&k?K zeEMruhiQVZe)Sti$LBA;_}tyQ$09NgV;jMa(`uTOIjz>`*RCumT0x{E|Y5!HP&4sJoh z*t#ob0YO30T*u+d#jHySw+PJ$0CgoIM5?7ur3B3o#bQFFHWz3%au(hSj0oMm9l0#x zri2j9afGhp)Lq;gM?)vszAeyh#Jju8yC>(V>zI-UqJUu)7Gf{uYy{Q-CU8U&fdF%F z2_n-p?(OZZ*Q-q#!lRb5$X%#TrkLn#IFrO)qb==lSN9a?(KI|RlCw-Ktg2I)W?j!B zwbYGit%XzWNYpnBz8MBe!psU@OD(k`Qbkyg8%FT3aTvp4;d5jHOaf3 zISM(3yHjE&a<}N1z6t z04HK#c8BWGb0#JdcCcxfz{0}01|X(dYRW={rBv{6_ZCqdKp18bYp=s*grI15 z7)Nu{ssL2oSrw7J0UE=b*b9|CKuyEjNCy!E&=JGYNm$)gjRP_>cS1!HKsBfsQ3^7Z zT2m4RIXgangGH+nGZF!}o!gMa%{FReP)tb>a%OeYA|iPwr#@|tj@%6pm>2`xoU&N3 zg}Fo`!N3Smw*VyEg3QcH&dIfUsC(!%ArXX|TNw+sIPb*NSTl%fny8_jK~-nn0x?`5p&2r--YBTkH%2uqU28bbpD5)x?YR!LJGhhbPQ zmjxUnh=>TMY3gzwh9Nv4KqTcZnN=nPL9IdPfGolQ?zOUrAi4Xn8aYugMwr%$5UQF) zrg4aHWCjl0sv98?hz!8M2~h}}oPZ+2+iMGrYu9=$fQ)Jt0fD@l3nDWIn7YXpi(?Ri zMBwZZhyh+9K#0Q}DcZj+YR5y#qpANYSVbVHiJ_JVhoMZ*Jo9Wf>n~oqgaBu&;p&wu zM@L7;N0X2UGa@0Qfst?pmkQo;T*FX}nJv8GWdabwoVINOLbBMZIa_wNtCeXYVP*+a zNwQolhiULqa-NmROK;2^rly)x&Iv8riUVsiFI9vf2S%RIM=d#W&RJb=-oE?5gO_Wu zz5V^wYJE10Z+h$7?+wKQcMmS6aWp#)iK^P33?h_iM1)!2Wl7_(+1XjV^PTT}{q@&Q zPgj>NUH;a$zqQ${7mFPcw$MP)s>}poi0EdG#vBnM+ojb`A9RR_aBF;nEm9t^=|zyJ zeL_;|q|Ioy(;5$K1O2vXd9yYL26_Y%huQs9T!6NuT9*eA01`n3r8{tUg-e!n_ zB-`yUeA`e#ba$ZpjrIFCtmY%~`x(hCB8EJiBRnL~0f4F9(JZ3YDxAl0`u2C8F^k;g z7hZVbt#5n#Yv5$Scr);4qX994;O2+q-V_4GZ*|}?6xp=wMc=nm^zUgoLY@f2J zRX0Y=lFYSFvRKY{7mM$`dZ(HSBBz}C3=s-uMM=?Y=(-Lf0x;#&vZ2}pArQT(k(+J^ zu*ZYk(=M|e}#Mel}xGC<_+dd+xMLafE>ZKs<{zzlRO!M zgERA$D_385`Pj4|6Oj-}0H-t`x9Jthr&1@)sdE4`3!th>OcAhJt=bKXMZjAoL`Ib$ zZ{9p$R5S1h!tkxy2`C!w+?$^rW3kv#Rdsg+B+7l)_p=8deCXP>2Zk~}^X&6??%WLk z#K1(0*-i;_L{35g41&a_R#YX40XS0|sD}q2nb|N7=1#;-XSIcH5}JcL#(mi)wL-vg zk!Kz-)iR9}Njr91*FMYu0SFVbSBz~+1b`b7a8(5a0(7^j)BrGZA}(6mv5G`2tX0)K z!WlUtpsgTN03;-{(m-Gox$DU-O4YWAS}&7Z##YyPco_@rGc>^jVr|1BXluLzU@1kI z47B6EldPttmN1KeahjX}2%!cE1%+7!rs}|fLQ0wB@46Ul$c1>gt_Ur5E0Bpy8Ye7V!jhqr&^Crj;$y%g{gzN2OyME2#Jx*jKbYK z!gETc6e6zX9BvUnoVyO)8B^7|nN|%0R7w@Zlrk|P0x?=UAzQ>Oky|jLs=6s5nkh0? z*YF@>tBQn3TR03Mrj(t@5tTqy8=`)(n6FnWRYMFXTJ9`Wm5D?W0;#D8meL@v6o73g zNkl|crqZmcMC246#wc#8psih6&BbCEruohs0ydkW>$-6o&9v(hvvge-fTo+UNWzu` z00XF@WU>e&6B4*-HE?vZobzJ2Xb%7&$s(5AtkkM%T|Wb4)rkm9YZ3-@Kq8U=P%X?7 z0L)ahKycM+$U8Yx+v5?dLDd+B(R6YTY+8aQ*aY9KPXx6RH8Cb427rShP`kXg*ba9@ zYdaDj?WpBN0I=_2W5fEw#ieR}`069S`fLBiwMQP#!hH|J0MC8*rGNWx{=e(jU(bEMaN%Hc ze(v6)#vDl)n&Y;e(1^GN?QP3IHIkOVN?j*C;(TW|j+2MyEUiBg5X97&#?x5KW;j1P zJ-&BbweBr<5Rr&fbu1d;jkw|r5r%+aDwNb50a|boVUpB!v&GJGaeO>LFw5-4XTN>E zS{v}e<*To~a^vLWh&ZM)6>|;fbKipZBMcE!POsm%+4b|~a`D(>?|kLe*FOLG&rj2| zv$I4DGXvyt8ki)do|vYoFmJUftxX2oL2cj`sR)QoxrmKWrs~3}B^EZc4^xshyScAw zMMP-SgFp%Z0i*~(j5Zs)uXk$9A;T7|(q46gzj^>+%cnymKqlVmI{{iOm@vE9R?`xY z0zF{c6$dmoA_5`@5kL>)W`D!2KDTv-EP$BZLu(a;iLv$kIuAiH2r)td!_ot`ps?kX^jT47pfMW|0 zNB3wwFoY(ZZp|`mAMW;c|3H`x&_e3L-5|KhKn!E6*#d9gb$|c@)pB%n)OE7}S1)s( zF;NCF3wM*;NlrQxEmj;s*tLnqAq3P-RhbExSQ1OuM5TmClu*dDY8!wtgw+UlgDezC z4Y(a1K&)y=QdNlo0?o|LBZi}U_wF6tJw88O%=VYF<#@I-MnqyvwUjzd%oGMh)Nv{_ zO`~G8+6}|K>t<$3iR-B2G>N1DQ1b?lXw>B`>Ht$Tni7dxZG7=%Kaa4YWllXSRj^r~ zgRx8%GdBWvvwOL>DJ~I-I1xf-atn=MAhpm4Ac?TiL6A}qg1gt2`sn7>l!XBz)Y_oB zx>JM@HcGlk3O99ct_mWowMt4>pjNAsf^Acs8u*1k6eEa1BPXwA-t31 z?hxVTZk7n$)j~U&8LPXaNFZ|8n_3I(b__|089Y3vo}3eA=A_}?ddB8~;3do)Fu0|% zdITbq^!<)FbKo#d{d_i`&q`JFsI`)Cg>VSsEl4HxBJQcnj;;tDq5y_^%a8;^b48); z#>k8bNx|Jlv+6!-IXgXl@ahAJlTMl?=R}M7+@0J!ESOoRk~Ka!w5vQ&j_iNy31ni){~~HKHI8 zSeOW{PJqZLfQi%m+2>w3Jvv^@m*+MGYz?8+>iPNUo8R*Ax1W7oB!Rj}QV4)x;y^Mt zY7*~O!2vQRbPaRz5RujDWN*1ljMFq_mL{%r1FKaQ9iiO1b5GLVW?I$B&DFphT&p37 zTM378v%>5<^OTUt4xjthryhOByRTfiaQ*e$4?lG6>ZQxCzxw*uzwz|h$=Uw?#b5Z3 zfBtX%oxlB?zww(_<`1w!FSGTuaWeKw{G`H%UNsvaZyL$&ueBsOY?jAq=^=}aI+4<__*Ix~!A9?&;M=yVWs)ZQG zsnp=1lrl{LSjE5EGdbvAF?oGe{$mfvX1*hARhS8$*UekVHT$N}0r4XDkW;LNG*t zE5B)6A)tGFUDbd_0?A%xP0MLpZ)ZI_YePTKR*WmB0>N+GxL->4P74WB2tt9 zpxV^$0jNA03ut^HkA_KrHs#zpyO_7Y?8}#~fEoumWgrJPcFLUA=Hoc#EX6&!0|qdS z!?5Tib52fC)CowqnjyttBO3||83B1%xI)jJn#x>qN}!IyzyyGV*`fqF8Zl<05@D{O z)rkNIEl4Q4Dz+at1(P6Q1&x3^hxe+PY8{7~Q#Onal1{p^5rqIaN;oKj=bRJvo3hdf z$q4~VDFK=glcb8Hn06SGBm@ZAO8zVYrPI1`0_u~VO^BGXcv#nU!#I?wP-4s}XCc5m zn-$lbPyoyTt5YI3XhF2(Ab>%Rh#JtP3=k0tKmrtGNYp6-V%35XxQ%uWB&@YM1Q0`n z6Id97H)fY3Xc)LN3J{uWL@;MWhCo7NM#&Ti#w;2D71$w=3_QTlQYUDHfk9AfS|WtQCC!p=`uMQcDT7xR1fj#5gBL4CGiqG0u!kio++ zAhBtH`8bZHlgQn<<+^#|#7xl%-R_a795T z-mC@<6=p7^$CBgMpE zE(UI_Q(jG5FlAV+uypbPkWagV?Awb-0bWuL!Amz zMgRaH07*naR9S}&I0$A2s#Ql(7PRW%fQS;w-4&|zvKcnQjNt2GMVv~lC^75z+!q0@n3`|Kvo}3_Dd&C|?h$bY z1cw?^7MZ8{ts6HtMRCE8zWGtJvAVWqOcE(-WzujP>ry!0^X_;4%=_Q9Apfxs{1m{> zXz;gw=^yURmtD&L;$QquqGaF(ufF%aKXze%zkxP4Wpsetck9ilWm+y~PK5yl`*9j; zEmk7+-7qRcS1?EzLjVH zMnwpW-Pz(ZfA*PgefvABdnb1f@482tcgVE&%3_}Tot!RR-YsT8xt<+<|HYHX-}RVJ z_1@vpY_S+t=Lo=@U%zqV=FOY6)>ewCnX0Cg0?ol29Crv%vj{eG5lSNCII8MwHjDQ5 zx%2%5+=lpR$0fA1HsJg2We7$Q2!&|E>$Vlf{XFJvJF00Lu$2wo(pvyq`H#fZdRs03 z9TCGl5jsFv>x(r*P>Wh=SCK$O2Jki#zRv+@y&4Gy00(yn28{c0w*W|l+mM-7_Y*b6 zA~69Ipe17LauRvR+u!=5kN?Op4d4I%%b)y{Keb|cr#Dp%CnQ7&v#RO{%mfi?#wbBL zjAM}BpKXPtG_2Nd+_<@zFPInshG9SkivSHE075}PU~?rR4<+V1ckW)eaIjgeZrr*v zo2AXLN-d-bq1NK&ppkQDW{TDVG7!PT6oZjTfe_6MajQjQCV<$ssC-)$TT~HR|Nl(A zd61^rRpxh=d+)n^TV__)zVxc@YIUm@wHCB52*I!;KryT~W*BTBOyIGGVa5)^*q&e* zW*i>CjBUoi#5iIGBLa+s1_4??K}$$2b)%Nl-PPSyU0v0+<@zn}a_>Fo_>cE1jq|UJ z$gQIC%lDppp6B^J&0=FZS!+OSvJSe7NK_r#Vo@{#0h%EyA&cgrk#y*#AwW?x6(lo| zA;vmf7QLe`B{d~5f+0>Ya-BMlV?Dd(~-qNL5)bZ2)r$F3?%1cwaXyVP~8f@lT=NJiRqJtGs5I_gtIB<~18 z1Cyx?Wf7@s2$d04Gdm(8Lm09NP1Bg!bUZpZTpT@qbVP-L1^`!94q(|dLcjtD<{Xk! z$zo_Z8k6&$K*WaVE+`-)}mOsc{2pouULFi7q}jfn&i z91jg&-jQ?OaSrUZwzpM#MNt!nWB}+qdT>-WeV5HVdqj-Vi)Ax1&0rFW!c5rFutRc4 z-WNWU1kkTm$V>n#8PS4sV&XiveV?<6h=6MBLs1x-X>v?C8sgwA0tD~?S(0;%L|{ga zS(%2iAOP>2s*s^bcF4ehYRte4rT~^5GZ6}y^E7lYc@9~6@aWkgf=I{fHhWY}&O0RV zrLW7P3eHqQHD<>}5xn!FnTUNLGaJwlHdu7osR^vMh`7!9joOBxT8rga|oja&9%>yMFD`y?5XFxxe{}!p!>soQGotOlXL5 z4ITnSvy29k4V}|0&1$!*aC>XBT`hz6qNYScnO+Fa6~z-@c!ENS3_tio-}k21-F<7> zB(bJx+WDgE8nIZo@Z57RJp0U3=Z%eINLacdNA`Lgd@F>zeLs&p!X$3m0at&O(dT zV%79uh`lfCktk9_)>fBrB26{}(GZ7IZLS)JLcDC7=*?XT-x}DmA z;5`h$7R_!AL#N@Xw-%TXb={f_0HEu6MGe-0{EGJJK zd*Q;ZvK|8r%${uEObsZgWil2ZLIN0S+1D}7Vc}xhGpXYtmrest8;9`_EhXJKI4tUF z_;NMXtb@Rbw-GyFCW;2eK#Cxe?RI{Q8DlnbM2u*LgvYnH_jY%(il_l$>|&Pei$X~h zfPe`YEDt6YFal037A0@6+mf-{Q)5&C=sd%p#fmuHaR6U1YZm`G%!#mV3$QwicE~m zCPT^!0<)Nb$N+N4XrjhMfWY4CAhQ7>llNQ|Me2Ki=p3Rd5F|iI8N`q==RB&%gltBH zz)Z|cLojW)Gz{{wm_tk|%uGmt(8o;7DdpIASkU3&LF&4)su&?z&M{8Pap625S(YRM zsDLo4>vq+sS_qy8%eEvUBoj|;vF}srV~0asE9gM9_ue_@(6OWpCJO4A!3<0gIdwg) z_rb#_AUH=N9xTU{hFN&<@PWZV<1~&rB0!R8QGEy=2o;bRM7`%OMiHq(DJaH>VnnD} zz31FVh~i5(7^0Qe9VN937&Cwol8Fu`8ANc-5r{-3VuImf2i~FNL`7NFWsDJx42C*3 z9n6JjW{{JR%Sfz*pjm7^Xo^{0H7RHD&H+$W)`NkqZQI4c;epxl<3}wbD6#Tlxu`}k zTyebfG$6?dk(rnSA(h4M&JH2YHa244g;0))GNz~sjJ|36F3NaRX2lQ+NeL0WnM=~P zZCO<*ib3`Rk{v0h1OwQ|yDWkLWmy}751SwUZ^9A8i%|k17IyBjb9%?Voz`tFK*J=Qx|@lw#j!$&B7PYWgFtjZZ)I zIOhNWy%!NiGElp{JMrElVivL6*cEhKlttS#Dd(yjYHBPG{#;R2bG@ z4S#fqKtyXNC7_vQGh;wdHX0cG3PQv-q#F^}MIyG=sK8*IE>#P_z6f30t(IMq{Jr1v z0d}04bm78_`-g|#@z6kxfFPy-f(nEI*vtehi!maCv13BaSq|rmsv5h%v5kxQBBdTZ zXAv}HWB_9xVo{1PEUy3!fze1SSB%HwMlJ52I|-u$ht-fP;!6b_>t$Iza0BjC?)`c zAS~qAiwOdmD)At=DQd<63u(aQOjV@6^R5#BIi+mQ50Er4VD`-JmCIL#WPM5=zqDVk@WEU73W2^g_s1{DPbQya?C5P*Tacf*6ufg>XCIHg4F z&=8_haE`qhFs5M`N-3EED5O?=;mEl_y6l!_!^;mnx`8vEQYNGf8O(w&n|M%1yjfr|dcwF-Tg~1T{6>{vxp#q#Vn@51tf9~y>n=QgiKUb zMNWB`&%I|RGC)%`71XTY962*k9N5GLgoG4hUzDW*)^)u&oSR}?#Xhatt|7oKrpuSF z7NM-GDg@W(C^<>aNH|0#ybmJlwT)(7wJQT>HIdy$k zdLLXt2=m1f(Jhx*#1Peam`v-O`rIS|EbGzQJ&9llQR2jpuU)^nYFFb?y~rjqNcWNr z9Tyj0e(vOn(>c~xukTjnv%^`5)VT)DAh0I`qE42aCUF`d15@#2kZH>*0- z-pymL2F+?&I`075m{*JW8{Y89`Sa($@Wn5E`*(fI=5(VXRxkqm!%uwbvxm=tp<@=4 zEQY|&J3tZNvd!_Na=$Vlr$T z1`yPc(gYmj5(7|IhF7oM;!xIOfByXWo!uP{%ppAf`o}N5^wNtLUvyj~RU%Lm6(c|p zGXzm1V1t|>GoYuS*+e7+-*&B-U!^Wd1Yqwyg6VA%uUbZOU_20qjgSCI0oW@@+qRBq zV{6ij5JNA~8Q(TC=d9*~+;z{9uReSI__2|5pqZ6pG)47T(aJdq-1jNPC@FbIUZBmx44BLl7!8tW z&bdTfX*s(`+;1XIO%Itc{o&q9e$T6nU7Y-a4P&Oo&4bhC8Sg$DSKm#J7 zqL6~aBvyuyAZLk;Lyws>eeWC&BBM#l0Y{?5U{-hqLbLG24o zQ6$IQlVQ%;NU^L53B&=aSoY3|s*w_^WCS8)Bqf0in$T>OmJVIvi$SwCGa{l8C9~0obpmDR&xG`^{0cY7V8H zC&-RVsZIl=b~Uf2TfzIS@hry9dAC@sw(mS^T}(|wpk?h)VvI{sB=mJT%RUfM1|)VV zMacgm7DDI;0ablcn8!vQ9ma+Y_#e`Ciw`Q7BE<%}AOd$2Ks;ZoGm%5@X#*^dA)iPV|yUqcc z-R8O=;NW5bGeuqJBUA`c%xoV#Xz^8OQl|0jRycmLgo zpZn^IOir_*^Mm}NYL#*6%Oah3KF#!OYr-AK^YYM&@ zkVi-$N!g*HHEjz3o}nt-i4(_s5!$w^ME-*71Au*wIKJ#3@Q%^CuFE+B0DDgeVK8o)gIPii#-lq4Y5d*rssuim-^=qu;AB!^OYwv2$FX6U%j8Z{;m=Yqu69H~juEtXBT z#O!c93DrOZk!*eEm|N2j0<4J)$rP%>cipP%4)*7Zfo@zEqpgj?7ljMdc4=4_2VbO= zi9w0Epsw${^vmVNx|;i@i&AC}EMrCaVM8SJ= z*en;jT{1l^j~+eE%+9f62Z)SB;E*U=Cc;2oA)!$(qOjbURr|Y(rddsA8vs&IwsKZ> zOpIzNivVDs`!@H1(7D2(2iI+lN<-+{bo17=vKo6IoG+M2R1qkq+{Wk#O$E^tF1y3$ zk8Vm?Bm}&E6L+t7$Isk(?fR{>IPCg zX@CFv9{6!Rbg##T?auiolE`pLg8 z>WNwQ&YKzlG)*%AY)lQXD60v8zIyGJ2(lady58L0RzNXLB7MvbeA{%7KKk$@k3Q<1 zODQjwt1tcSQyW{GS6^8o6B=kT$E-P#DIqe0BCuK@1Lzeyq-1x%clmUR4G%K;2OeUZH^rt`l=}+(O@76`wzqKnVmsLoy zS*{Mq$+W6Rqfy^=)6r;SHeD>{SyCR@C1ymfz=D~bqZrd@GDd^G>(|ff>BM`#Tr8OQ z$dPlzj)E7{zHJ?_V;eeU~5;GDv?*q)9LucvEv7aFJ?)F^BEM8l4dYK;$b(n z4u}IOsF|8V-?k@@9hpt0H=3pQfsibz8H`6`W(w>I9~dz9U2OZhtN_uHU{(WgU;~Co z3>-1D6S$4gQyElTKvTjPGYNg+3txQr(bokkR5K|WDqsd65DftzdGIw)eE!MRVd31J z!HrT*>dv{v_G0llt>+$Swo_y*0PFswQ ziY>Da)=w1`1X97SjkD?I%^Q1tFMS`4U|7s%z_JKg1OQZ|>)Wo2gDnY(e1TneIKOqJ zi?PpKl-n*8K-$OXy%858d4P9G7Ux`)tSXf+JL~$sGXr)6pkk&e_kHKR_w3716-6ni zQS$t7&P;9F7T#OxR*S0#2eP*~VuGy3oKa&+M3`b9dD9w*W^iZO%52GY51Y7(F=z6B^R&=AEC*oD90I6$+os0^E8dN4mUASSoFyE~muL^Y+XswrjD$g=v+zwaHZ zX8Fo1*RR~1@9iIq!UO;ml^HA{3smGC!E&(}jS9@%ul9~jy7#>CH7~z>;mY;K?8vHV z2P|e;cqH=9iDVJ=KBSb(A}GlG@YbBZbDkN`teWw&8r7XUjtrKt^fca07*naR5TM! z*(49d7|?7MyA{g(XMXB?D_*uMyLco1-bep(GC5k3C!&-h0;`C3MNaK)TNTHCm9_ov z|MAbf_ibD*t_2Tjx71| zD+fRJU;JEA*5mQ`%Jo}KvpRA71gMtmnIY#yL+Yt-Piz*y`G5XmIVu3)#b*zG@~400 z*pU;!_3r%e+VvZK*X5MRz%loIFPf`BklL+r{%?QoryhL#aR36SKlGu0{goFEI5=P% zx_^dqA?1u}kj1(3xfgEy!H56sCw}ZZx<#L(0HSjq)=+3kvESc`p)4ML;GQctZrr@F zv%hzdkW!8!k%*?#>Dg0TRaI_op6Hv-#E@u^_6Dn_s)b;adi-yG=Rd?~MaiOR(X0#| z0L*4%e-)qo+E+KG8)~@-iqd}e^Uqa9_0d22%bi7Y^3)v$18)SJ3-g2hzxvc?>di^h zbcj?G;o{4eVjqtjIdbXZOGE|)fe=)WZf_fts<87>5+NZtTVFnjNQvC=qL|HQX2wMG z#X@pcg|6);8ylw9b@IZCFZ{v(^ZTSgg-daM_Sl9CVK_Bchx=dt($kB@d~-B4PhWlZ z*{Uk4s@~c@b?oTT{r$b!=B%o#!VnQ9W&=YYNBr!w&m|KwOR?RY%}$>@wYR?m2zv(y zXV0E_(;MGtra31N1=Y>1ndX6Zu^t%^ap_k$FJF>stUTX=?w99ctm21K6pl_ zqLMR_5f4N}X5y54MC4G$Bt+D7$$R$TKuuB0s$8yCMBd?=t@58dD8rjWr)Z!yi0f+; zfq@dx;Gntfh$R9wMRWrT#N8(3t_Kt%9kfY8zWo8Z{S$}53ei+SiNS2xG@}jwt88W} zO3Y5w1_=gG5t&d`#AJ9GO-GY%zABg=d-Rb%|BJs+v3I=neRtn;&nvII^07bt_~GF} zRaYr?MA)`VPc#5vEF}X1rko=a7h&wY2Z70Gv{){UF-tmn?CALi?*H0z&lxB<1Tiyl zM8rJ!575LBiz?Cpxj@arOyBkG-_|s9L~>M^>QHFCwx$w}>Y4!asy)m%abr_NlVk#9 zB2OTij0*(|K9q$gWJCrP8_H}f2eL#YeLAvv{NlwctHb?jRL|!J24rBUYa>$AthSGx zdgnVwpa1-qmV4JWw~kj;$&PXsO%c8GOrQ$TOIFEq7v}e$KQ)<+_x9&76iy)l4c|_K z=fKsai&s=(xmrr@hIXgQ7j0`fcFR}4{{!!>Lv`%bUBCHTe|TeO$t58=A{sPZB$)3XZf#7dgYlP_^!9T z^^K3b^6Jj#zVz}Re*8;R6owMCB#)X@V|Jc3izjf-RpW`J9I*NJ_dR}ixOeU9E9Lau zXFmT@J(;yV8esx;fFMBLdFD~!n-wN76zP_`Cyuti{7--WD_?%~KYaM(S8wi3CPzyj z0M-NgU{udpfEW=u1O(f?b>XdVeck4C^z@U@0F9r0>4mbM0)a1ztY9JrnsOQ%6ue_I zZJRc)u72k?o_*}WcU-&HKKabS7ru0(m~L9|j7a3vC}p8S9lB7J-Hi;Unmgv^JKy`J z*WZ7R!~3r6;cxugKl#eDJ4ZJ+vc?=?I-BwCt=#pID1+5LG+k`kW@GBU?LF`Op7)<$ z?!JuE^FRFyzw`2~)n+jbRq4IYssH+ssR${hoWwiV<@x#7p84fp`uVn97Nf0S`e(oX z@jw0SMt3Z;4Ri-2BEl?!Ksl;+9#q?Ye|r*t_GkZVfK`so@BQ(of8~GucWoQ1QE6ah zS+1l7L}g3{DfOxaL~8eM{P_2M;}87s-%G2P7jg8#ANj?u=W$&DqxV5X!B7>*90CJy zUiZSL2kt-fL;u-N0PFya7j69gk3IoL!Id$|fYoW5E@hD{f&8j#oI{H7p1Y54pS^c= zaPI@DIc5hylb6!oIh9H_wYkN8vxVKef}#q z=Mpwb9y%=1y3`R78>?wjagLM8=5+S%w|ztI7mq&h+Hd(gZ@uvRg^lr%a#9<>YPqUM zTkfh?!$f{kBc!OXEhe9f;Yy&2;n_7U4Qn>1D|=~>4zRX`S@dxUAuN2IT$LfbEs7K zN;I!lZJ%W_old8-)U1Yx95OO9vv(Y_Sl4%;M(j;7gCRLURYhhzdi3n4{_2TmFI)zy z`WQpy%!rr`;Mj>{p&IYpyqViBYoEF#$v^zqdv^DBclVb}Rolrr#YdPy5%7fzFD_!s zK2#iXj&4-keb3$3uU(HZnyHE;)ts|PRzhV;T_lGJmTresR8$QBRUonVFI>E+YE@Bj zDBD#Ve1TE#x$iZrrupA~<2Q5HPdBD$mc{yZ9;(VS#cZJ{_E+s)$4)=;`fr$R9q)5| z{iAQGsE@9O&)*{AuJ6mLMx-3m*S8EzT#f1qVKv`BwteL1{=t89xW7L?n1Akx zzurGwc<1-__lT&EUFAIjVZxzpegF=EDGW_Ah%pHviAt9ePvkeB_Vc z^{)3k{>Wn=`?EhG#5>NOsml;^w`dPBDPnL!x`O$^ z*FN~MkA6&2l;9mXLL$VWZi5jAh#WaKQ_DhNd;7a@e#4{Z?!4=jS6vIH&AhQs>s!5V- zuU;Er_ai^}U8BwIhrzz>yEn4?tv~tmzno3BLQ!VIlDzk;7+1d7T+MrS?&i*|Ug9L= z?|%R5&)#=8q!#@7zyDu;=u6Mv;PHgBI9EuJtZB2DfniEX6+OBP?K18D%U}Ihr?yXg z!z1y>fB2{V@h|<#NB`vM@$s=Sp@W=^jewx*SB|(5i(T(3uZt@m`te^ldB=kQD}W>a z%m4BFzxCVyexp1=YIUd@T!j#{mjNRXQDf|5yT4(pZ~f)~5JB(0zw_W@4@1BDk>dXE z{osFfeJ=&d8oG*%E!%f!KEnx zlg2bW)*T}NG+oTf<08NF%@1rHImIZmJMaC$4}9al_}3pM+X&1EM(o?JRn4kE2BmXi zkYhu-c;`FbR9DA}A~0>d`SlO~}P1w$LJiZ7!V*^Zu{C7M80V{P#BG?*WCX)0CeH_)@b7we&Iv^~fZ+Xi{{^F^jAR3s#tf0`RWzy`p z79_DufFfFl)ibxFZ>o%C%20Li`OaT1No8{huHH{bW@ zo9)Jnc!UmCDFYa=C z=M)vaSl&9i0pNYTnVLg@f`AU@`;|IR9Q)*uM23yL0HCU6NKW&eXYT@7v1nZuAhv2U zQxF3Ha*P7Pp|IhMz@gs)n%In|XMXE%~SbG|=slM{B;y zmwlfXtNCiRkUkMGdt}4dc8k?~8IvP-{M4OMi&t;#9X+QZ6@7^+DT5Lp#avH<{LyIh7UATp85$ztw|v};?)29DGqi#W5sUkQLOya{B< z2H=2IRKSoR#th~VO)V24n>RE=bBvZWS@uN%L=I5N5CDjVNRAEolmS68L{``c4e7Qk z_V#k*wkouaQ-A$^Ff%tShz4bc$p)%6-kx$q0RR}yKuqzrA%=)WL5Dbs2@ZT}9J(Yl z!)<0WVa^692FOIJmU5cSW`X^|?!n`4eB=J^!S!p`Qc4F0`)AIcJ$w4x#f#5>>-#_W z!SDE{5?}>z<=U>PwY~k?Z~P_!y#IaQ^8AYzE?&J{&qgt}ee7o&(=hRpu9u-}O!+EK2%EKm8K|5CQ(*kN)YMci!DL@~i*+*H&#e zn@&Y!XfYrnM5kbeE~<~6{LPb3z588nsj6xzZ3Z+EGE@`K&VX0V$`|~|W3St|^is@t z{pwz`+LLAE;0U?!<>`~NBgbZ=@y2pK2T^BCNMHyCiUI&;639g<|NS3)D#=LIHSGbC zMoIgJ2MSh}1!QYhaWtM5h3#K|e)H%Q?ACNv9zT8r(25Xd8&gpr;vy9YKm+iX5DBJ} z>FG140lI^|t4!sYQzuVuZ?C#c0G7mipEaXnL>%}+1c(43z(Wt+2e6+Huen)x;K4gK zj!qVdsHnw)b=)`#pOX-?7H!}(X1}Y;1G$(Ibs?bJ!z=8 zaISdirHj|DzI^srH5-8}ZpIj^+4XTngjP}!0&?(4oO3Qq?D|#!i=sGsT-_k{1CFsrVi9VL}MA8b0Me2U3Z>|X$7#~?Y&Y=`_reltFkQ1 zLQRtP2w0YdS~d^>Km}0=1P?uM^1%nr$?EFraBq5igGj1+Qr4$#k~4sgAP=8L{)z*~}E$ZZ#T@ke!+mYF(A@diz^;_b%p~jvpIez5Z%Bt%(7E zVv3;*%nYao#zi2ejqQ!)d@gBq=JXkW4A6phdpkRTpyWJ~0fefYH_I+*(|1K#)OF1O zDR#)dtZRTaHaCiKJazUs`@l>?L6wR!yT0qqAb5`mgb;I9=kI^;Q2^RMJSa3&ljF0k zW1ScgI_Hw1sHLa?$m~)Q1x%@Tp1=7!zaL~a*}RLYvpj9WrycjCp%f2&BoWJRdz(lN%=hd3<41;9iV4W0MpWC{S=M_;2r z%oDUgK;Ss1I7sbnx9nqb9EP$u=U_J7xN?1Qb8dBYe80E-MZ;78Qc_zrt2z{Duy=6i zf)lW2*%k$(XQ1O}Uh@WkJIs}n?eQl*@x=JZNgUO$T)jS-Y}R$%^=;d%ybs<55%Gc5 zO;9$byb)NZ2s2& z_2HlY2R|;-r$rK#1i0o>4Z8tk=h)0lB|-)TA~ppgbj~~UMg|P<{}J`3!IoXuecxJZ z59gday`kUh*CQH@c_2U%00|HvL4Y$wN^~TZBu27g$xb52k`g8PLzg^#`7xt}$5E#UI3x@vnAN;8=ob`x^DRNyl1|X&oLL;f^ zb~}k{0e$y-ACBmZA%zI3uF5GHszbo}+*&h>NkqzemSqkRBJixN`m>5vCv^>4bO#4G zHHJumZdh7Nv9a0WQof`F)7exQimZR?>?I->LO_egpo!#(AO!;0x4dsW+$AN}q$(_0 zxTGw*!`-aNy1m}w(jq6R>n7B}+ss+hlFc*Y z=gn+3p8V>6`AfIldgH(P*MD%^?YDdDN5gT`#LQ=g+-yD_*5mD+?JTn`yFwBG0vX^W zduAvi)S&W6_Bw2y?=AJjGmW$%w5jChZ|Nc83cmP;VpE~WV+uq&=0Bh|2mDQz%ehzSDd#mX7ds#l6jLy9F`t3Iz zzJ6`vl^33}u9yyYwl}VK@_ag*auQc~1c{-UO@=@J^Pf6-^3<6#=emQwcc_X;d$2_% z0#O9u6s!4kv7i6m@BY&i%js<1=`NvBRVL*rb4syOIOp`_$(OBlx88bmX~7RVris~e}FF*p!oaJ_~wEy#8e(KUS2G=h#oL9r6M{j)Z`yacqvGM)yeLtnt%QF=<2KKEU zAm0JZxh|{5EHCY2pl+VoqG&=0Ax@^#*?g`B`kj6VK>?gKx7~URKCsWu_y?ZUgYMNy@M~e)FA&4j(;#`C6W3oDvab)~A$a<+Q9D z5g}uYA#3&C`yR- z#Kvb1&_L#g!`&oCnS@&bidG>!_^$g`mXAZ@67-y1I(g=z_qli8I;+-dWCSCkyTe^$ zFxI@hymV;g=&|Fbn&-vRflQad9KG?zJGM_;$_xmnHayOvjRZ*&Vn``^Z;f+3zpuM= zgobPQl=tXXh4}5 zu()#mjSHYIaF|RdSymi9d}KD8g%}k$&vTZbn3!c@Y2}p@7hXI4CxB8{i6i<>KhLw- zY>q0uZnvD*ZOZ<@fi<7y)@fbUq47_@bmjW+i<{Rsk=*Mi&n&Ml*FomxYRn$=e~9F{4gteb<==>CN`)91VOl-HH3y!5*1Y5zq)#Db5@6X zKABJF;ij8zIB@Ky2p-J9=f+#ux3aRnv17dfA^^h-^ZBGT&#$emWm%_gk}A|qlMi~Y zzWRE<*I(@Stf%>WHXM%XvJ6eVxbS0^lth~*0+4h5+#Bb?n8|D&;@B9II4vv=s=BO0 zsGC|92{A=Z%yo=a%>v+jXI4+9vl$_}Ec@6eK63uzo2O2mDe}(3@^h z{k&tWX#orB5D~~|mSvn6+Ep&J5LyDz#E}fP&SOw@WLu7^kcuj^7=sRBNkq{Iv`x>p zUu+~sPAM-shM#uPzCMB6Z;6#!>wZ>FKD(h_QcNI^+NTFVE#HAI2GAFHT{ zv|KndKBryg3ll8=kDA8hu{6318Xbm>zlp7()z|mRaVpKq~q4@?aGzQgMNQ!G`#W1q4z!f*lgCQMr+X^ z2n(o^sI>MwB4thp(^^#R7oYsWxEg)@;~yUGY)1|)vjGSVpg|N(DotJ2px~S(at3X? z;A7UN2>{@Yg0cdNq9tOEt$#bq?8?gObI+gt+P9ufxROi~jluw6Z@l?DyYh;GRAg${n=zxH*oH9dG^BW*zv==l|8$@ZqPXITegKLqnfOf3#ajD z8YMyIn`pMS#^3+m3vavQ{!TI29oZ+o^%JoRjPoorKpJC8BF_2gq=dS0-uL>w@noz* zv$?*0W^*v;FsJEg>)fT1ld*-Fo&bT}Lmq4xy>UEA86&iv8aCWj7pQn3BS()Nyee;rk*T`gN! zUS3+?+}haKND}rfE|E$UF}?jieCEvJa#2^y3s(vPP{zZ|6Fl z-5$nRr|I1iFs+?!eDWsnwOw{JPrTX zzxlKK?th1|?()@VzxAzWoGk#LfdtOXw#%w2$(Rts4abgDWwpJtn?xODPk#5s*Uw(t z+8$5Kay*`sdM2dIN#YP==IpGTqhhbWd6 zUPuikWFTi2o_+cCpS*k)DaA@%$5`)*00yXxb(2^XVpWs1tNYiQx`7x8w7+`bwTst= zpMSEBffPj~3TK&Bfu@QTHxg2;8{?cBDyzy6C<_8H<7Yqr#Jrv(KxQ*#%!@39kV1+f zNJ^n@@;qPNx8IP(%tTDHYJTowXm#Yy6j{gh`~9j8-skmnygME@Rj{>X<>7F**Xd?O z;na$;ubh1C-05>*jq|y+zSry3+tULpD_LHY(^*|L0s;vA?XAcRsD_k<&%JqR{px0W zyf9@B5_Tfh#dw6G3hxv>UMTM2f?!m$s8TX)z9tjngC?hbetOCMpz4r1!-aCBi zLiy)^^TZo(oX?9v6B|c9q{J#FVGt2TYq1VhVv!Wy@%FbLJ$l3G|MZ_#*>{WitlS)q zpL+JEPd)R(Z~fLk>vr=Kub$f68KJRgY`@o2FrjIfSykrq>D3FBRoJ(0`Ox8m47y;j zoX&svqo-I>Q50mXCU(wxXE%0cF}C?F1E`RICAzE-q+ZcEo^>`iH?wYccQO$XLq_V9 z+D0FN&pPKXT>k7AzO%Kx^^>Q6G8&Cl;qk{GU0gZv;K9S!H+CkYY1Zw`CJkV14O*mm z-M}6unIxswhGlK0Dv85^wWUt(GEc+ZEpIK5`P>)3oM+i|clYp-)%QN~eq*R^=45P9 zbeg(s3H{bv5bbn2MW+~zMlq%sqX_4e8L~d}&bjGq)}-VC8?L2|cOW20?p=zZNs4i7X^*hD!<2Mn=d_LRS-o}m1?F4|V^wwzu0UZ*6GT>Xt zS+KA-PGJJ#gwQrKTZjli+eQLFLJ<)|BI1xlSWt|#2+H=XqX5V(fWk-yiKGSb3L&=S z5fyoB$|Hz|ncHn8!k*+)02C5)L@=U~l(IYA_ib60r@Fp&{d#xMUt3xG$MrUwGs4Uw`g%O=!RwiRl+U@zF;fy8q2{rzX?Mum9SoKl4|A0|@`<)4!Yq>Z;k@ z-L>QdxDM6fgGa7!Zm+EE7fjCkfBw&Z|Kypo{a()yges~rplCrr8I2gtLP{N{gMO2_ z>HqlO{pO7~9N8Uh#U!AFsRnCXctN`Y+#6Ual0i;v$Vm&fqZYqO4DGW35(`>!qzj9y zFT8aAb6@_>#p{XOLfxb$Hl54?;PK-(KlI2W=P#chZEnB()0Y&`I=b`D+aG%Ho$Hq_ zT)Vz?@xsRS?Qzk`J6Rq?n-t4(hG-_k@#@;@Ew|o$^2BQnjc~a8uA3it;J#O0ddX(_ z#VhOE+dFDJkpluw-0LpP%W&z^8=X#``@$R7>vj5rUX0@`(}RcBT-Lk3Ilp@4y0uC~ z$~MHr232u3o9t|DKrnla7+$z2D`kDQQ4~|Bo>3C)=fwczB zcsQKS=GLi-`Ycz818;A=`DoV}m*p2Otye+13o9Gj+s4?pip`{fw>NhL(Pd_Jbu~1x zpPR_#fwlc>Ye!x`ajFWTtjj^SA7dh-UcWz@&v$pnIhhEor~{u5mKI_YQZ;}3+wa~T zZEx>v&nwP+&p0d0yHtbFMFzXmtsi96}jzYMN}2l*>pA^ z4#A=T0g6>bMeEI=-(To21`cJY^Q@c7NCwHNkcnkA91fF6WNEvI;kKI<(kmSvsFy4&rEk@g0NiKmm%yecJWVun@~uH?KgI@y7>RWdG# zFem5p#IcFN7-JD<7*2?2I-T5RuG{H$x*bJD(99MFjUewqwwgGZO|I{3 zcbrF{CPwQ_zv#@G(r2C3<)xy?=JT>s6y2;}Hzg7?$7WOTaWf>F1n#mYO22rC{K@rBvT3Uo2xM({ zuvW$XH^2Y#6JP&cRhw>6)S(26QAHU5z(%G#mRW*7k=?)e(S&b^jE+6Lq+n4ue|zdSv4s(WUUArqM!TZr*?PNlg3_e|72Dl zIeaMAm9bQR_?s*Hl4)>A9(wH@3{A;FP?bz+2`t}%$&dH zp1Y6VcyxK+;^Lscv$@$cP2TNSRs74p{;RraY>^?FrPal6|KR%v_b+xk#cVd6Rt*5G zEG-j&FvKJwresMus6gVhFc?^ZAdmyxe%q~Q&b^TmqcPO}ln9b40a_qIK%=v|&bysX z-u=>(Km3)S|JZ@m)#3Phh$#UQppr3dJzBBd7NG%AAwzBBtECSsq5`*fCL|?H&e;Ca z>Z_-&eesEBrgI-zCDkm_l=H$55Y5#qS2LgGzVm?(eYBj1Q>RX%^)J4B`jyu%SYw=p zBq{556trbT8$?w?B9l3j+57Lme>57sdG_33FnHtg_W7&-pEWMU=q&aY_s!>XYfVd< zpND!{m*jmN1E|i0XVqjLmjHlJhtrWUWm!(Lyj5C|@#M(PCzH`+GM~>CpscI&7v3BU z2J_Hd+8Cm>FQ2~L^O^7VH+ObsvobSI6lT-ebUL3-CL%GlrW-OAP1WgEZ*F%pZyX6* zRT^&XN=gnvMCP+{cQlSMu_z*#lE<^L^Z7I@R`=~&zdpXcRV4;MTo^2P=U61BbbWVs zI-SmD(^*@)Pzb&(n>x#~e$hL7VIu@aSTHt#X{(}Vq$x~!Wj z0NPmB#(A_EAQ*wkbW#*W)znqwW>ynWuiu+Y$Id%Rdg1(q?x5G}bi3WYI+J23mX|oh z`D`9SU{N(x&q^h7l|gMo2oHZQlgc6{au zQ4EtIZ!H3qv8l_Ztg3#$f6Lu>Y_6|I5i-U(Ymn-?-W`o6>;qcM@O)`Hm^9wVTDNL}4<_{hWWerRWVIG*kHJB!}?{z8{i`sVk) zJDpC(lS!86o@`mp6wwfb*r4jW-u6mfF@BD zPu7wVVQOEE6N4l{6B2iF-|2QzjEST7dE%%bbqtUg5#7STcYD@&7KtgQBsU&AHXQA4 z>|7fTcR%>p<3D}&c_1NcR6&%RrtEY&0BEfdWeWtAZS6-tdhR11`p_po{J!U3 zJF|aj`Odf9Dgq=Jnk2x4C?rCwM~~k8)U!YR`d7cPytMD(N8Z!vc8PHJ>V+?S^~uT3 za9pMjedsYnC3G7bo6o)Q!e~4Sv&jcO_>qr&{P2sf{?fXAuTA-8r1hd->s@mL61qC$YJeknyZj#7-mEHMZnIaCHvB?GDT zH>zH{wvGsi#gH-1H=$hY^#{Gq)obgG4PZ>sDNJq&>Di~Ay>?||X=SNJ9B=OopMU;^ z``&(UEj-!TRWk3q=e7s#yEDev9_mAgOyKcYb%GImRdTl9q zZ5mz07!(FpRE=cGNIsls6V3Yi#nI#o58Zd;qmR5R%gl5-XXaLnAfTp||EY+iHaP@} z2qK6=s3Ps1LotyvMc(aXoo8Nn<8%M{*{vZ|u?Do>nIgaQqserZb0lXZvZ@V1GVf895jaLpaW73F)6~AxMSzewLL82EV-pF86_U!^-gYmEl(U)jrd8Ay)^81m zyOUAk;JtSyV-4lJL}RL0S7p7rvj2{|?v615k|eI?BbOJ0rG491u8u~-!D62iTLQHi zSrmY#X)2au$Br#6EitDMLMJa~)2Wg8fXoI=eMLTKvnuJ=6H z>Gq0FXJvIsM0U2fj~+Q%j;G)I&i5wcv2hlZ$vRSl7P(2&`CM2Zc-I3r+;HRC{xt-- zc;UQrF7x@D7vDT{`qb{`PQN#hm?ScCLx@?Pb&9Udv&SBPTveUV0Ew789bXj1iPuh? zKYP9`t9eyv5dnfyUepCx%vs@&9lPnwnafwN?oKAtr=EJI6$z=Tq?FoMdlF>@ zX*m~WT+VCJJl}VDgSWo+##2vUdB;1B-F(yHjYkgUz2ziHn3Y)=jWw#0`ON$7th6Uj z4>z{ApMK`0OV_uepd_^p5oKP@dffqYGJ@Lf2AFj(^1z6i7uoYKJomzL&;Q~t{KB=X zR~Hrst?I*&W#IXE5<{>S>!uPCgMi+spu`9&h}v*sY5g@2V`^rNNGkFSz^I5Jtjfw* z)2gD3B|{WR*pfyiMA<8sXiA}7H>9R&0xLmEfm6~X(i+wP*AA}v9rxy$vo>=J3rpkS z_{zmAgXO{Q?(o{i#$C7H2@363E+Wp62!{~z+^H%mTJMyTGnkMBQ5pWv-~YG&3tRO&Xlb6nNi$I(6pqXaCce%h_Z&o1Og3Sq3El5zRaK%F4=>^{apM zr+<=CMA);EdG8XypMK^upZw^D9((^|nfKG#yxZ-}=d-hC&pq&tdkbgB4SenEKmOuZ zzFO5ymSunY#Fq?tRmgIWA_j>$Iu8T@AQsanKK@~gd%0L;R8=y2!dTkF;DRDTA~1^W z^ra2T8hOiDD6GbafL)3JA8sb`k)wj;gw9c`cyAM3g|1I5OV4RM$7$cw}EM8}7iy z_C}{$tY2F%%j(WMZd+bj-QL|X)+#~M#HgZ1S+#CzYmzk%$u6#}Do`Co6Ii27S%px~ znm|NZo^eVnLO`nO5k)nIpsX<_W1U3ULRTD$9*ecpB5fWMv1w}O=Dn?0EMAf%*9E75~QdRcP zzwq4?CogU8%mkewXHCumpxo#NYjn4Gbq(CIEb z{N6_oA3mICS?+Q|G6rIdWnIt8>b2Kj8;^Du`duK3%m?@HhXkSmgb%&0`oed-gR==Qqa=4EI|(OXk%GH6y;_dWUK*8zk%Apsks-1b>u zVc+VVcig$Kv@DV!r6iIc>ZX|X?_WD~_|WFoX3slCshhbq7Fm!0ft)w@KXAV)&FgY$ zVQ|BZ$79tjE-l@1>rJ=adds)J_3i!3%ek|SB;IqYn|`mq|L~!el@$X3#tH%{baF2o z@4oBq)qN|o$#l3oOsLB2jE^EQ#y8(QfA2l_-hS&HSFT>!+}ZBrc~RuU?cEeZr(4`| z<4vKAOG}I0ZZBvgKp<*jTwPs0e*9)cy1ub#0ITWTShFp=v+2xvcl4&?{pH12mt+Wt z3>BEfIOq))R#sPk{GIP@4tIbB0rT89l6w8Yv12zJIe6g23oq|Kd~jiL(91GJtW%0r zv$l5Nz{>uYUp}#M_3~(U=ireeB6#W2#mKQ&baI#9dh^Xy3|@?)q!d)ONoh15z5Ln< zeU(S!ArV;cO=vi!<<-S`RbSuSbUrJbFMI)+t?LRA4H0wt#<#u|Lkx95LTG~*WDv2c z=bfV4>2|MOUeBycDU{``+wE~mUXp-_ z7*_*c*{avS{p!Bw@=k7UIDT~h{*~pyz%0g|e-`W(RD2nNH@&|wLM|a(M*K)7Vz_aH{5O00mwB7(+e*?2Pk z#<#xx-19Gql6PJJl3@F{+yC>w_q)IO{&(G50<5o(Qi=Qw=b zF~03>cmLmi@~2OH<9jR1`!i>fCTGq6{M)~~va%FnO@JDioSQdQHJ!z#>GgUxb0FOI zhm7&6(py;h{eSguUV8DR#lb>=rsIl#`M>@zhYqbi_v~}0PM;eLy5sSvTl9bVmp@%M z%`30II-kv!78V|S_`zkuy6e|BN4rDe)TBm~vMeJqL_}!zukH7FCL*X{tz%`C zgk(i@JQ-E%-4bIw{9V{B0X zna`S71IytfH}t!`tW)d^cXqaSi##X9>2$KNurQs?c8A-}S_6&vY$zToq+NO_9C#Hyk^%Kmg2Qub=g@t*cj^an^cksA_6aXqoD)zyj7% zVrEcCpu$Pnk#Rso2o`|Qf^j~Jp-~lYvxX(9Fh|Q|5QC-!V&ScO1#(lTCNz1Tt7uVl z1eFktajM81tt9}8k>7ejN+L*PkknZV0L+{~lnM6cuPv<77%~cMjT7ONggJ%KG@Qf!Bzps2HkPb$A_|}}B?P0SWKdWM3;~R1 z;~1m2u3zK;LS#S*ffxi3Y|9F0srCYh7$G4jCBp!O#3>=5bre!i2126-(Hbjz`wK=@ zBqu-?#^X_poM%P1*HzVs;9CE*!S;aLzNE4y0=FlWB@$K<1rkC9AOX-;a$v1BNYE}R zsI5R+>qVe$Dq*&n%WTFR6+~4K5y7A}L?~ugV3_CqA&tx*5$b;OCp>a?sUDRD#ZpAdc8gw znoNek7F-qu2&t-SV+-R|KeX>x^Qt}VE}}Q_eA!}kmXrk z*TQc#OvtyM;~3L>ZoN`%nFMwDAaA6gU^B5F8^ zLXqeD7nfpHU%GPT(BUJ(BAlY|M?U$_j#D6DLC^w~i1~3dT|rOiadL;)np&`oz&@Rz)?6bD1J23$j>iw9SRE zqA^iZ-89VF>+iOlBiX2CPSqyT||lAOJ~3K~#%Pg{Ya!(A%~f;gF0q?ePNyA_oO% z^|(IE5K@elQ*}8#{^)x@^3jjl)GCqN<>y{k8If9EH@Ai779>Z2h{V9EKtKpcB1E)z zVgz~X*dwfr#wvh<2us^dRTYOM03u9;43-E%wcSXyRUkkxs$dL@h^m3MaVm(|hHwE| z&^aM0S``rlL_-O5u)Occ;TxWM=6P#9v>zASxehzy(NhrGu4GV96`HNh(TUg2c6z<1 zpL^-t`7?Fd3@4+<9)0xa(IcBX!^htD*qL*e&Ye5&EFL_(_Upg;t4sTO+nXDO&&Z)M zE~Q`qvyN}-N&ou!LqbXbz`mR6qzxdYwP2eo_g)IGnY=DJ)an(LTKj3P+~SdBTU2DdnE(-E2=l5;%+9%m zL4PtDUAuOTLkLYcc=%BJV{B4Ps-Q~7T4NL-##q;N454nCmOlw1+|;USozL>ZINN$z z+VVULhZsW>V~j)wP>~ft+C3u?T1U>gl#(bQ8C6jL0ulykeIz2rwy=3YMGz*^EXy^+ zDugx`8dE}p%<0tWQ%w^U6%qE_83u`Hb9W0Bi!38F1geU4QsUUYeUib^Xm>ms8ew6l+aL;1Hel%n69BI^U{K1v2Nd+@-{qE?(vk4jw!Rh=Cbe)($8c+fEcb z5+Yh_BM2r5DLP}xkhM;P+oGZF!Rg7om6HPiV~8cGfVI8xc%&M=^9zfMpc-Q|)^cL< z)>_lPq%jCHpn|6kBF2VxuS~qr{R}jI}ID37ExN+a?;wQi@E3*RHL9`O9C<@@zVtAqjI;yCFi?O zKKaex{+&BOA%@T!^pdJU%TjYn-aC^S<`kN`m|7Vj2{>mHsIdkV zA_0IJV^FaDr(=$+-0HOffE9_c%{Uf$7E_WY&Z{bxRj1#JoMMOup)Sjx{P+jw&z(7W z_G}2DC~`|A!YL&pLSPgWLS|tK2!<3|ItvlCX=K&ph{#|g0TjF;W(Gsfn)ca?M4VUw znz|7YRS2AnvjhkrAw}8KbqPdO5F!MQvx@7wGAL{XMSNz2lX2h-B@|#K6cuD;mL#08 z6%_&srIac}afWPW53Q{|^qxn?qY-Xg-(ipzDechijayp95CJL>5F>(ed!Vwz=@EeAcVwK3<4>R_>e#y$uT%~ z>~?o`w_R25$2oiNXRSF07jx}X-B(pz?>X<@&sxt~bB;0Q7-dmMIFK3H%p)V+kmc6A zV3I0XGH2;^0Zc?HnHoadwx`F(fA-J+kN^6={oOKjaqmyh&)dF#{muJv9p}e~zw>wg zqvM}P2#e@Nox_0#jacVB(@>Uz9xzDc|u*I)VW7yrrM{kz}$mG6D^{{0{S z$)CJ_{P>%H{onm}e&etG<&<=J z`{T>&%j@;SuYB<X5$LFWseCt~WXT;@t zWor@hcHAzPm#4?4-kZ#fNTt#Yh}8Mv)SG|#(=Rh)-%riG*-{Id8xqQRdOH95_rAmN z{$wwI^{;&I```QSuYT`)-~HZqK6`%GvH9LwYcb}BuRs3Z|MHLi&wug9Uwydz;%8rn zZE}l5rf#=e#56Q||MdFu@bvCK{d@n}zxh{x{g3|NKY01{;RiqX!4H1z2j|CkzxTiX z{_p&Q|K{=W>E-frJ#K}&O;qqw8j<3NXznnM2tdp%PxnU2>}4F8lQ6SJvG*1k89~Y1 zQtYi6*;*4*K+5Nw$jk^g#7Zs^p^V(Nt+yTSa~y!ojbsK=(`Zz6=9Zc3eWeKGEdRL5 zJW$P(m^C)bIRqIP5#~mkB4`GPvN>ap*>*!|z|2}}z2A49&m?WF~)_O9RZZx8DLn6Y>N)`q% zGu;hFWHfKze0-k~08jgw26LJm2@+^-(o~qS6m=k~y;dqR+?$yqvM?1%#s(oN71f}+ zi__`1>)7}1%@nI@Fgg-dE?1mReMl0SuzNj6a?V)}Y?%onLTqeoM$#~1psq{>q#BR` z(cFzp3MyzE?yZ2yRGKp(Whz*Cw-HgwR~hd%^4LgN@_PBSnejxi(ac1(b7 zZN_|hI+K=>$2`ub?KpF&_1U16wwgt8a9ClOj27%0G}&^3_Ckl^k? zOh|~9jo{SLYxJCj9>D=RUteEO=ZBn;8FP;66O0C=ne}eoETx!7MpM0;CI=w{bH;c& zKmFxbUp+ma{`PPG_I^73NB`m9e!0E!%P;>zOXg0K)y%t@m9RuA;3H_2EKs)bN<{#j zfGi0SHKCVfc2t5DB#?j!hLpQU4v8|(h}~*TI>F2=9j#@?0K7(`fnbygF98dJMNSC_ ziOK{tDT%%J%>3Pd^pF0ZfAI%1MDnzs{*7Pz!NbGTpZ@uefAVL4*0%lozxw^X_dol| zmtTD6Gb66Am-FLiUw!y`#%f8%fbdw=t{eoL8c-}ZgK-3Bwa<`FqEGIPv< z8Dq>`2oVAG?kUV;Ht;s)ZH(g>^A-U1&o+hLfBos_zxc(RbKCr1{=pyq>A(KT^W#%% zW{sQqF$dgFZHq`UM}!k%g?#fC6A}~6sTv*6e0+LpG+D%m)tsb&sg#)uS+TkH4kwG0*|u$+jN{}Ivp zmNV`jiWUDUWGTmyBp8$t-TN3Ln^CaT95-*irsJ^2wj%R%KFv8}%-*}8IcBrAOdW~V zTA{?pG2G3}qq5dxMpk88j*cSO%mIy=t-G0-Rk@dzFxL!3)m%iTdh?74Ap`;D@YXY= zF?A0q?cP#SB;3lpyFxQWgkrIjLxCx9^Cnd`7#xhq>+RZGYi$#9@0*AUKR5SM=tC6J zvQS>+n7wZ!r@@U0_lRjon8lQl)esd4vd#)JGjF%Md0;6cXwA(Gks+9Yy;;O?bC}JD zir>D?8(HEj#+Y>#<&+ycT_EJ{O~{$qnpchtL5Id1!Q9Lje;#S%%xLB$(}WDO7Ab;W zKou=Al@im8UTt;!5_<2~s94<%meIBFtR%9Y5 zcdppv_1!0Ofju*#yBkSwnHhP+%&m1Og4w+jmWplfb53jC*a$?X_cq4Jn625qcSf2e z38ys>1ZY!pMx;2WTI+I;kY}3p3610Ct!I5kf^HC$S;t84Th0*ITq?oVw>jqZxJI3( zp=P8ZGWV_Dt_Ps4_o5jH#vCxqh;859ovKfjpv9Q2x7XK~^Z8-lPai&f*!F&0kJEly z1%0K|nFaIq`ucEw%+!pzZ`<{9X}$Nhy?_6amZ#I{-Me>VCM6;to}a$?=KbU8^!oBb z_nCTn_jI|up3e^>jy&dRJH5QVxVwbb`uV(NPWL|M9LFrdQ)agAy|v?*2J`MS;_@li0oYPC%+kyl5R76)hZ8hoL`qDcxY^7gjIhr>`}}&`gxRfW z$WDI5u;YR`Z{y~@{pp|n3Bk`k|Kj!2CwHgyPnVC3>9%D=Msz>#zW@IJ_RoL(r~jHT z$XeUda_jx&dOgNriHJFF1H{ZYGRl+2jOV@`BVJ!#+>w!aOwgv{IL68Rn3}2HYX;KV zzCAvlo2hq|lX~C!F^nqK@*}iWPk%=Z=zP^xp`S>1mBgULmL=2%*j4_Pu z{Wo9zlYji*{pMf)&*^!7*fX$i=hpa7{`-GCuGgH0?VHju4w*m;G(aLVODP{QK&ZGx zHy2e&QUF6TTI2-afQCSiOx3XbaiB5TDqZ@BTQkLEPKQ-<4|8UY1QDsU5!aZiuM>dg zkV=Rp)>K+)tV(*92?AC_RWJ$3<9bz1Dj^>CwhNMQD*PDtFLrl`V%}Ar=APhy1&X9Dg z$W(eWFC@QWF9q2>f|TY4VWQCCN*K$ekccrwq^WEh0ElvTkd@hTEL%vJ+k{v>VMenC z;zqT`RNY^kx(0KzrsQkf2tA(mIffL3Uazn24r%NA%g6Wb24xB{Gjf_cq~7}V`X1oE z?=!RFa0Sje&gXMPP;9M@I5M^O9`kmL(YNih$0C3F`EuS5l7C8z?&?eOl$aU*bQCpxTo-}*R?)@<9h z*URhk^K*=mDUx$W%}k7u*Xxboh&hiivpI&DpC8Z7TVXbcF)|(> z9>*AM>*a#6xgT>}u9pN-+RXR!NkF5Cx*oUVdOhuXAqMZBpD&jSfYw@TK4(1a+r#

o_WfyNtWK8KtDRt)J#h@6FvU?J}-yYZ&N>n76HOx8o?TxVKi2#;1=TAD$k!zV+5yuhoAXBgV*mKfS(woHM#N5Ru{T zMh9)%TShqj>G`>D8&El*$IHv5?mss~2tcNup3bS*x06}(?nWx(IEH&Ovu$hpekzW# zpr+e#efjvQwGEk5;qFi8Mlm|jYn`><3_cZt&V8?mzhYM+E6;JR)=Rl< zdnd67`njJ^=ly|R`e74vjH`QtFk%`pN4T}V@3-44s5vGS&8_!SPNmWsNcDEYvZd9k zZEM$tU=xqlRRN=SOcW$?vrTEjI{=5Wt3z>u@87T^jniALycT>4#n0%jAE`K?K zTHgCuAw?>SGUcR+1Yw20E6XjnPXvo3E8Aryj8UrFNFrPH1VALRF!Hy7XJJBMX3TbDm|LiypK+W5Ee@H4cV=e+LtMg94d^?{r z=Jk55ES1RYzNKl*Wmzhc%`?M58q0yrNoA0jnJ<@{DO+n4G2kX?&OqC@vdb&Agx}+{ zNtrnbqi0lNL6H?%Lx7}3My%I?WVpGRQ|V?<5@sbeKq4|SWJfpK zZKsvLut3kUj{q`mM9fI{4Ki>}X%1HPFyv&TENM@VPv86AcYpi0|NX!DxBde+il< zkrBCXn;A&KG;Wn-5pzzZ+#BwIO-7J3L!`=$0fe_U=WJW6eFbK3+wC|cozACujCstb zr>75}-qT@Zgifb(-?on*zV5y6`(8;;uP?8yIcb?W=G?cvNG|uyX=dgdV`7fm>-CdT z+qRjR(+WlabUTjI`8A9#YIm=}nYyU1m&?=R z~tnK?Y zGvB@Y?D^rLB4DnU%jGy)YcZ$0@8|R7av3AGZC9o;o3}bQPY(~b>-DZ2Ld@A(+kDHA zG!r~;yLq{*2WXWJV&=!Kaszs?$d8Xt*X!l+;c?%$Pai()+umA#yjv?l49$Vi|TkogS`Fw7)V+=an{hP18 zc|5-x$4KSV^V7@gtEAT2F^*!wZnvA6?c1quoz%WR0-Ezyrk`%!+*7k#dw6=<_mi1A z`{i~GX4!K;J$`mvFV}HBKRlUWW|f8e^7>K`teb!K{4^s$JUu-ZH)@WUa5Hc2-sT+U z4zPsY-kXsS)=fhK*_spm!}|~B5Hzl%dEd^b=6&D0q*MyXm}`UtFuIeO(OTR09hq+4 zw|>3d3W_lU!KrjJH_wRXt=K8Dg#ysH4SF}DnKkzrk(rH_nb+I3;K#o8=1qjTx0)!L zN2F?>Z@m>@S+`8_TqUESv97aXF=`sMut{SLX_?l6E)fw+UI|$5tu&NXX=SQZl9?h4 zEO#hD_xb};QV9p-h0IFIFmHFHzw`_Um>~Cpg;tbE#&qj22PP%B7wQah&ZBxHx;Y4` znI}{ZS*4YrREaczBAEyXZYHWYP(aH(QAwjG6f}96f!cyXc-!DGo#zy+#*H^eBGNA%MCw4D{(vm5gA^HM4C{% zWE9H8HI;0V%Xb=jZ1U(_!A)7)A89aSSQ; zeZO9Ar_%|*aoo=5vv)skM>o%yW^{Lf`_}r_x2?UtzTR%fwsk@7-QbzIZC+xq!o zAGfI>lm&y7b;0HO`uy}fOPH$I&!=tQN`HAAM{9l@M?g8JQmuL4Y~RlNe!d zSyjOqNeFJuT4k&^clWmKo0%abhFhDF*4%{CY0tpzHOP(rpYxQgSE2eLs0PBIPF{J7qZmkUTU^xn_sbL*Xgxe3TfZ%$GrnKUZpL`BS#til4B z%98EK%~Of{`3@nF=1$4XX3QDkeT$4z?Quy@Sd2i-S#fIhOIqtR&m2lg@&(>NP)2%d zr6YM08rR*AB`Mci1F6Elfyi)c5^ROSWgWSRY`#T_$>4SV-LG(F3>xabDYkK8*rona z7;6YrF%yK*W)5#%F-`L3vB*)9j2U%ag~HrRZ92W_D|e0F{{mBh4frQVv+wBLwe+?L=MoZV^G4pw>K;6x_Fr1Qi*rwK0Y& z@>XoE&EtSA>y-Kyg-jsJcGZB=ld(9bDgw*z7|O|2Ub%6O+4{D~TbPyA7?q)vN>QH3 z;u%yyHg1_=^o$xHC}7Ee`p;m(+_4kejxjaT=E`YXMvnd0vR(U2*FXR+Im zq~3aD)NU)mbseX5CZwYF$>P>i-Zv>%i6BeJNaZRcW{iqFM9Jk;Ry0(mxjC(dg<0%y z&CR4r*h`XG1Dp)`5TwSgsCO!Ex+x~`*WRx`_DJCX!NPNspb z0)A4GdC98kE2N=;Rxf7(JV2K9{vvp5T(}mbRPgJaET_48OSRrZ+EB2jX2&tM)-EqsYpu1`dP}Ld6HV)x zMO+NciF;lViEot;d*|=O<_lJia;I^M)jEBd^<90ir&JZrQ zOY5!oejLL{bK7ZsZ%1U#OywMdy|;uJMUIFW!;F%3Zx4@WagH0DG@I9v#-5omN6cv3 z-dlhF@sr~C{PWLiO8uMn?=P2^&p!L^b~?{F_I`p!>n?h0Mk3}s@8^_VuOGen2pPPe z_PuwdPUr6K8R=#jk(uKNkdfK!T%%FMi?YLfY2F)7VMA+6TD62*3OFR&u6TY%FDiXQksLVjfm&K+s zlgs0>L>M&lyYV(MXGA5K%{fn}Qw@nl$@w&)Y<)xVWl<);X2uxmt;Ia5mkp>6z&e_0 z{?TPJ2ypi!k7{ldrGU!jmPsrXv?Th<%18)ugHXzovc;k(Dsvhe-D_N`YLyw&Y0Z~E zc;-rEYu;$>Zk3ig!6>o-02XvfL_t(*_OskUD$I3ecT@cvh)kB~5=DEKh`MTvs%TOY z%oDT{JsNxW5Cnt5oMXyK&FOs;fSiOyxu1i*wQAT4%T`ULfhe&74RupR)XcHuclaKw zC@cpJ6D3mt5?&X4IbV>*A{T^UQfS@^N?NmRRH?3J1l@&jn88AoU9c1=!W<*q4JlEe zm+mL#r~p7NopG70M6F#;6-Z!4C1xfXP0|c=A3(`kXQX%Llr2!fOH`pzqs(b55tx-a zL>AAijGR#Gnu>f_Di+J%UmKt|wxBBSC%m^}+yL~MjfF=+K3ZMy+CSl}eu1o>V z?Uw4TH6TS1h6KeQ|NLkEZ4|Qt=CCC;G((a4On?SYaawqm_PZpyi^l;lnGP5Y1z1%G zk#Ry!XJR7SLUgK*9)Js_s5h70Cz$E~$~8^;)fX1B{FLrThM%^x2hXT3?h+I@9op4m))DYU*}Op)r#9T&N&|*9$Mdi@$;W|>*G3(9DTQfq0Y}wm)DD# zZTk);l6~8toDq+Yk4AI%cb`3fdjFxBpHI7xG*V6@8oITNczS-O@#Vvddy6qYeEgWq zQcj#7&XkaR*iYA(#Wfh{ovGN{-n{kmo>Bbz7~{BJueZx#Qkb@F>)xE!&gYY1R<<*8 z9+PB*VCnAe&8;wGvrIvds|R?M)*m^Cxh#E{flpL0gcsxSbH7!k9o`plHH?R|y~r zWp!m#oo;KgBMWy?8XK6IQT&#W5xRGQNSS#+-K=P?n77WBw5chnc?Fu)10j^NdP!6v z9_~&lB4B3j7HZ}<4Ks_70~2M&=)DAey#jw+rc znzO*(YW*d(buge>gPI0TsL^OvW(N*VCCuhAnAx^IA)^Cua>PV6fGN5)Z=uX%6lU2I zA(?p{9idF7(HdP+HF?!@kBEYn*K|!aPpBU^rra#=CJXf>2jwC221%NL2QYJz=;nl7 z=56bJqa6{ow@73A>H$YzdtoZ_|^G)zqq%=s*l&xZ_{sRLUK*uuI$XpXtQr=+TpSHyW=CcdW~3R-r7*!nC9}ap zSwpB;H3!WN@IcNCUoTO;Z78To#*kcaD`Ecfs*w;Z97E26Oen9{0RkHgN+8WPm5G;e zq5VoHa7S?f#+;@8uHTbhu47r#F*OS7k+oH76$-y`p=v>C>Aq1aEx=Q-6(j_~$e<)O zP_!&fzD!VQHCp{M3dky!p=5FCtA_$%6B5wM=VEz^s+PZ!;d+&V8D+`?STJei1e+P8 z@{_yo8;MD&GFspE<-OKOA|V%S4HqoHs!qM3bXMKz1&&1>B)Pbd8m}v&ra}oP#f-O? z#w#%fz%mE}iAf-`xmP8bRtna1t2FxLPk#P$WO^ZL;zYJO1@2{@BsijeMogiZLyU|p zg&_@+Cj(If9V<>+GSPHees>|+UBn>pXOzZIg${$_3o|p-b#ql+kTnH^?DU_xxH4I z-g*;|5vSA1&9`lD-63>1jcJI;t+m#-mE-|Zyc{*EE+O}QH#2v4Yjeh!(~Q^a<#g)i zZgNHn#Z9trC&e(cjGS{G$IV+avwc66JS8%ZF~F=_Ve7q?IaA(z&XLU4S~D*N(VS~g zqFF;K4ae;!(8M^#v?P!zvRot2Af#yCmBI{AlQOe$J3#j4LNoKs0%Ni;R+ca}v%DW; zinQYxX6DU}OAK#j1-2KuJI3gJBRS`gkeQ{C1khT0vkk0w%8VJYUZG_Rk!5)7W=eEw z&XmyZWlACg1m%etkRfsspiwMCk7A`W6&9Mh4$BaFOO*mR59;koJ4cd$ysUfGrHLTjD@Br2xm`2E`Fxk->jOV!PYe| z600_vfU!)unDvbm67DnV6jPAHBC@xd=v@uIRg@x8H#fCnN;?=(R9R3`OsK$&dpWx7 zsZx4-O(?)t(J<%iy{{Vwm>Ir&!Dp~6ycdxUZU^0_x@Q@628i+Y(g|C!A+-yng?u`oSH4G>v6Ury! z-dB^flqRy#O3Z?lTUXsRmcqZ1)0U=veY?U*>Hw_2(aaJN$_1i;CMuFF{3RDuzyz{Z zsE$3b7(c$7Q$6a278kj7vf~9vXPYAzP4ZPPh zOSGqSvE2O3p!9n+W&oxFWq^2>&fJgKHJ%m}kW7$f=7lR)=_g}CZFw}PqM+{U&k6Oy zh1Rd6xmOg-I&tv!SRfgIpxUZ*t@e9WHh}^ai3Dh^`jfS3b0KI|Cc5)yKl_W!h`K=m zMVOoFgqMt*s^r7^8TxwNm>Ee}DQ+`+>3nKFUH7I!2{NmKN+qpS8q-%O;WABEwwF~nM$_iF#`lmv4pXfA@{EG zUSy?xQEJ|AfFz2js*Ex^A zHJ5YI5Nld#%mLW8pJGgv_<*ZMHnZi_rNwAi-m!GzO=6IQtJ)IUT{>;nxP5yi!a_hzWuSOnyVnmSwfRlf~si=YJx$SiR-EaNFItt-gPM{)QdsXU~G!Yq`LJY z`?S*k3MNdaQ;Sf&3v1SOx$K<9Dj7@hT5l=6gEN zl!lOu>hO>z8 zOx70-ao-AGn z2|7_bL{>55DROGTt;%8}N(?R<842D`uX}HjOBYt~CsIn2WwmU0>pbobi!2~PnKCa7 zhQJ^wHQE5W>SD6$sMgQasd+EO*2Ehm!K{fn6@~^S?~+V_%FrEEHZQh1S;hgdUW>bG zJ@7uSS1(8s6X`I=dhl)*gaii!Or_QETZszpb+)Z5a}ggjNXAtNE=0W?KD{WbvMMV( zKO%sN=LQr&qmi7M)hg6s5|pp+g+w}R-GEX8sp#HS4Rl7_X%4O_BQ~$;46D{3!ck{y zDx4mfMu1-ZgO>TtP_9mP(cF3O<}Hx{HEWQN$pXDmw;8JQsvn!B<`1nl2{o!fXN^~> zo;JX_ZW`7-Q!84-c=dQOHpRuB~$~q;>)}yGt z%II+qh?0|;S+t02IUrW)Uu}Qfe~+6F%}$R@Qg`P^1Ocd(V}V;Jn&`9%!Ps&s;mj>( znA;>8Xf;|(*8Z1Du>`ws$U0{d+29Ex)2#%pey?wwlxEyW;QShGp%drCl1mf>s_EVs^h z+Qjtr(pFt5%Q`NLDA8pIMq)Lsq3qOMOXlA&~UMhglo8T>*}YEMc6 zoMhyzSmt%;#H^EOU7Mwrq7`hs$}9xwN&ype%yO6@=#2m~u+U54UV`iG zoxAgVrIxR*tF#Dgg2!O_$08cs`9iddxfFRnMC|ytHu!6y0B2aR67l&pkjhi?ak?CNo78Z72g4M|8 z%6}-Ko+4$ozF*d!r=oyd5mv6y*53uV`Op9>rP#ub8T~n5~k{zT?un!ELlK(wsj{hzzd6M zgB9mex{8&e>eYQKX)y_e%|Sa=3di^_%oyB7_-|1J01Ur=!oY*k>yeHj7) zr==*!Y)XXsnyI{Z?Zy;ZA#mR|ZwNw^r$`r#D^K3BZfM*OPEKY^Q`s@GIJiiP%QT6y z_54>;biaN@bQ%!K8XhXyxSKIn9+uaLXE-zX#g^Ka2 zKS`<>>>|Mlgh4YGW56^xR5DGjGiQOLyszw9${M9HUxP@C=~L3Y0Yd>pr%@Vr1jnPA zn5>pRxWpe-C}c^ng&>6R6xq_qsQG70A{CufQi3QMI$Go)P&+voqRQsqz^FJXwDNDf zmn>j`3&;g=-Z8@Zf|Kaxd6%o!MGH4ZCXpJwX4F-95sVuRT>iX88YT&T`Lmx_Uu3Lh zXm^;muKXzMdMLqgP+&l9^)M(YvfVM&8e-2ffLoB=D$q(h$-B(EfE9N~CG=$i=Ed(6 zHu3hN7QviIr((F6U_y5PRaFv2VGVcEGjnAUMN~1Xbjyeh7DUwgVDWH9q7G1yl9`W; z)#u+q@A~Je*;^}pXkAF_#WyfYN>O_{WA9y+1aoJ~?(C!_Sqb&mWsJ94=MHDCC%4)# zL)92y9sH$X4F83+QzlE!~~3leiiAx3u;(U#m3m>KQvabV`km{rKj!RacN7CPC`VG7DO6iVW1;hAYZ88mZ@@sB(pIuv&F=B7 zhA7J5{?G!8LRfu2fl>zeeOc=YoR}t4X$Dabupp4N+P}=y*9!mAa@S52S%4IEhtSJ9 z$w3K$keL!>V0~Ye`A|Uu_h&w<$XmMP_4yZ1IE@7v7M;**9+C_uqxMZLfeSfRJoQ38 z>LH~-C*sYq`u_Zl%9%p3X_CaEwzaNp)YVsRU(>|2I_#HLakaCge_K-2BdU7Q*Z)!5 z{+B>|uB2FtDtGP|JOCibCaLz%{UGvRdj45w<{k5WV{F!*Bk4f7SVy&$yn79KKT=~A` zgL>Dp;FqRG>PzLlzO4O^UxItIgyVpVXOO_#+l#pjNcMqn1q9k zHk2iLtAXY^qNp0HMkb5KFFm`o5Omgwz$KJ<`~0gc&S~zMSeP|(p^d9J28*8}EW+p$ zrCk#5hdIe*Jad2knQvdp*5+)^EY|Bye#BzegsQ1sqXT`2PXUv<$_$ Sg58t=0000ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + uint32_t exception_handler(uint32_t cause, uint32_t epc) { /* Unhandled Trap */ uint32_t mdcause = read_csr(CSR_MDCAUSE); uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + switch (cause) { case MCAUSE_INSTR_ADDR_MISALIGNED: - rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_INSTR_ACCESS_FAULT: - rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_ILLEGAL_INSTR: - rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); switch (mdcause & 0x07) { case 0: - rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); break; case 1: - rt_kprintf("mdcause: FP disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); break; case 2: - rt_kprintf("mdcause: ACE disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_BREAKPOINT: - rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ADDR_MISALIGNED: - rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ACCESS_FAULT: - rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); break; case MCAUSE_STORE_AMO_ACCESS_FAULT: - rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; case 7: - rt_kprintf("mdcause: PMA NAMO exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; default: - rt_kprintf("Unknown exception happened, cause=%d\n", cause); + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); break; } - rt_show_stack_frame(); - while (1) - { + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { } } -void trap_entry(rt_hw_stack_frame_t *stack_frame); +void trap_entry(void); -void trap_entry(rt_hw_stack_frame_t *stack_frame) +void trap_entry(void) { uint32_t mcause = read_csr(CSR_MCAUSE); uint32_t mepc = read_csr(CSR_MEPC); uint32_t mstatus = read_csr(CSR_MSTATUS); - s_stack_frame = stack_frame; - #if SUPPORT_PFT_ARCH uint32_t mxstatus = read_csr(CSR_MXSTATUS); #endif @@ -272,25 +302,3 @@ void trap_entry(rt_hw_stack_frame_t *stack_frame) write_fcsr(fcsr); #endif } - -static void rt_show_stack_frame(void) -{ - rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); - rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); - rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); - rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); - rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); - rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); - rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); - rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); - rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); - rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); - rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); - rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); - rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); - rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); - rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); - rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); - rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); - rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); -} diff --git a/bsp/hpmicro/hpm6200evk/startup/SConscript b/bsp/hpmicro/hpm6200evk/startup/SConscript new file mode 100644 index 0000000000..de51a7c0d6 --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm6300evk/.config b/bsp/hpmicro/hpm6300evk/.config new file mode 100644 index 0000000000..20b7372e64 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/.config @@ -0,0 +1,1026 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# CONFIG_RT_USING_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6000=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDXC is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_FEMC is not set +# CONFIG_INIT_EXT_RAM_FOR_DATA is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm6300evk/Kconfig b/bsp/hpmicro/hpm6300evk/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm6300evk/README.md b/bsp/hpmicro/hpm6300evk/README.md new file mode 100644 index 0000000000..e7825a96ca --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/README.md @@ -0,0 +1,116 @@ +# HPMicro HPM6300EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM6300EVK development board. + +The document consists of the following parts: + +- HPM6300EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6300EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | Supported by RT-Thread Industry IO | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6300EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6300evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6300evk/README_zh.md b/bsp/hpmicro/hpm6300evk/README_zh.md new file mode 100644 index 0000000000..04083bd12f --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/README_zh.md @@ -0,0 +1,115 @@ +# 先楫 HPM6300EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6300EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6300EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + + HPM6300EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | 由RT-Thread Industry IO扩展板提供支持 | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6300EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6300evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6300evk/SConscript b/bsp/hpmicro/hpm6300evk/SConscript new file mode 100644 index 0000000000..014c428d0a --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm6300evk/SConstruct b/bsp/hpmicro/hpm6300evk/SConstruct new file mode 100644 index 0000000000..3dadc575c0 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript b/bsp/hpmicro/hpm6300evk/applications/SConscript similarity index 57% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript rename to bsp/hpmicro/hpm6300evk/applications/SConscript index 7c742f69d0..a65aa4d855 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript +++ b/bsp/hpmicro/hpm6300evk/applications/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') CPPDEFINES=[] CPPPATH = [cwd] -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/hpmicro/hpm6300evk/applications/main.c b/bsp/hpmicro/hpm6300evk/applications/main.c new file mode 100644 index 0000000000..0bbf637038 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/applications/main.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" +#include + +void thread_entry(void *arg); + + +int main(void) +{ + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT); + + while(1){ + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON); + rt_thread_mdelay(500); + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6300evk/board/Kconfig b/bsp/hpmicro/hpm6300evk/board/Kconfig new file mode 100644 index 0000000000..210f94058f --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/Kconfig @@ -0,0 +1,256 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6000 + bool + select SOC_SERIES_HPM6000 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_DMA_CHANNEL + int "Set UART0 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART0_TX_DMA_CHANNEL + int "Set UART0 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_DMA_CHANNEL + int "Set UART2 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART2_TX_DMA_CHANNEL + int "Set UART2 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH + if BSP_USING_ETH + choice + prompt "ETH" + config BSP_USING_ETH0 + bool "Enable ETH0" + endchoice + endif + + menuconfig BSP_USING_SDXC + bool "Enable SDXC" + default n + select RT_USING_SDIO if BSP_USING_SDXC + if BSP_USING_SDXC + config BSP_USING_SDXC0 + bool "Enable SDXC0" + default n + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + endif + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + endif + + menuconfig BSP_USING_FEMC + bool "Enable DRAM" + default y + menuconfig INIT_EXT_RAM_FOR_DATA + bool "INIT_EXT_RAM_FOR_DATA" + default y + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select PKG_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + default n + endif + + + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN if BSP_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default y + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default y + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + endif +endmenu + + + +endmenu diff --git a/bsp/hpmicro/hpm6300evk/board/SConscript b/bsp/hpmicro/hpm6300evk/board/SConscript new file mode 100644 index 0000000000..3f0a00f196 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c + eth_phy_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6360'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.c b/bsp/hpmicro/hpm6300evk/board/board.c similarity index 84% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.c rename to bsp/hpmicro/hpm6300evk/board/board.c index b0ae81048a..f176e26b88 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.c +++ b/bsp/hpmicro/hpm6300evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -10,8 +10,7 @@ #include "hpm_lcdc_drv.h" #include "hpm_i2c_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_debug_console.h" -#include "hpm_dram_drv.h" +#include "hpm_femc_drv.h" #include "pinmux.h" #include "hpm_pmp_drv.h" #include "assert.h" @@ -21,9 +20,13 @@ #include "hpm_pwm_drv.h" #include "hpm_trgm_drv.h" #include "hpm_pllctlv2_drv.h" +#include "hpm_enet_drv.h" #include "hpm_pcfg_drv.h" +#include "hpm_debug_console.h" + static board_timer_cb timer_cb; +ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag; /** * @brief FLASH configuration option definitions: @@ -88,7 +91,7 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if console_type_uart == BOARD_CONSOLE_TYPE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; /* Configure the UART clock to 24MHz */ @@ -107,8 +110,7 @@ void board_init_console(void) } } #else - while (1) { - } + while(1); #endif } @@ -123,7 +125,7 @@ void board_print_clock_freq(void) printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); printf("==============================\n"); } @@ -179,13 +181,13 @@ void board_init_sdram_pins(void) init_sdram_pins(); } -uint32_t board_init_dram_clock(void) +uint32_t board_init_femc_clock(void) { - clock_add_to_group(clock_dram, 0); - /* Configure the SDRAM to 133MHz */ - clock_set_source_divider(clock_dram, clk_src_pll0_clk1, 2U); + clock_add_to_group(clock_femc, 0); + /* Configure the SDRAM to 166MHz */ + clock_set_source_divider(clock_femc, clk_src_pll0_clk1, 2U); - return clock_get_frequency(clock_dram); + return clock_get_frequency(clock_femc); } void board_delay_us(uint32_t us) @@ -257,18 +259,6 @@ void board_init_spi_pins(SPI_Type *ptr) init_spi_pins(ptr); } -void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) -{ - init_spi_pins_with_gpio_as_cs(ptr); - gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), - GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); -} - -void board_write_spi_cs(uint32_t pin, uint8_t state) -{ - gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); -} - void board_init_led_pins(void) { init_led_pins(); @@ -338,6 +328,7 @@ void board_init_pmp(void) void board_init_clock(void) { uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + hpm_core_clock = cpu0_freq; if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { /* Configure the External OSC ramp-up time: ~9ms */ pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); @@ -352,17 +343,13 @@ void board_init_clock(void) clock_add_to_group(clock_axis, 0); clock_add_to_group(clock_mchtmr0, 0); - clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); clock_add_to_group(clock_gptmr0, 0); clock_add_to_group(clock_gptmr1, 0); clock_add_to_group(clock_gptmr2, 0); clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -410,13 +397,25 @@ void board_init_clock(void) /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Configure CPU0 to 480MHz */ + /* + * Configure CPU0 to 480MHz + * + * NOTE: The PLL2 is disabled by default, and it will be enabled automatically if + * it is required by any nodes. + * Here the PLl2 clock is enabled after switching CPU clock source to it + */ clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1); + /* Configure PLL1_CLK0 Post Divider to 1.2 */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1); + /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency =- 576MHz / 1.2 = 480MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000); clock_update_core_clock(); + + clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 46); /* config clock_aud1 for 44100*n sample rate */ } -uint32_t board_init_adc12_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr) { uint32_t freq = 0; switch ((uint32_t) ptr) { @@ -461,10 +460,6 @@ uint32_t board_init_i2s_clock(I2S_Type *ptr) return 0; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) -{ - return 0; -} uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) { @@ -472,7 +467,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) if (ptr == HPM_DAC) { if (clk_src_ahb == true) { - /* Configure the DAC clock to 133MHz */ + /* Configure the DAC clock to 160MHz */ clock_set_dac_source(clock_dac0, clk_dac_src_ahb); } else { /* Configure the DAC clock to 166MHz */ @@ -508,29 +503,57 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } -#ifdef INIT_EXT_RAM_FOR_DATA +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, 0); + clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr0); + } + else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, 0); + clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr1); + } + else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, 0); + clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr2); + } + else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, 0); + clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr3); + } + else { + /* Invalid instance */ + } +} + /* * this function will be called during startup to initialize external memory for data use */ void _init_ext_ram(void) { - uint32_t dram_clk_in_hz; + uint32_t femc_clk_in_hz; board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); + femc_clk_in_hz = board_init_femc_clock(); - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); + femc_default_config(HPM_FEMC, &config); + config.dqs = FEMC_DQS_INTERNAL; + femc_init(HPM_FEMC, &config); - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.precharge_to_act_in_ns = 18; /* Trp */ sdram_config.act_to_rw_in_ns = 18; /* Trcd */ @@ -543,7 +566,7 @@ void _init_ext_ram(void) sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ sdram_config.act_to_act_in_ns = 12; /* Trrd */ sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED; sdram_config.cs = BOARD_SDRAM_CS; sdram_config.base_address = BOARD_SDRAM_ADDRESS; @@ -554,13 +577,14 @@ void _init_ext_ram(void) sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; sdram_config.delay_cell_value = 29; - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } -#endif + void board_init_sd_pins(SDXC_Type *ptr) { init_sdxc_pins(ptr, false); + init_sdxc_card_detection_pin(ptr); } uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) @@ -612,6 +636,11 @@ void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) /* This feature is not supported */ } +void board_sd_power_switch(SDXC_Type *ptr, bool on_off) +{ + /* This feature is not supported */ +} + bool board_sd_detect_card(SDXC_Type *ptr) { return sdxc_is_card_inserted(ptr); @@ -643,6 +672,9 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) } else { return status_invalid_argument; } + + enet_rmii_enable_clock(ptr, internal); + return status_success; } @@ -658,6 +690,11 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) return status_success; } +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + return status_success; +} + void board_init_dac_pins(DAC_Type *ptr) { init_dac_pins(ptr); @@ -668,15 +705,45 @@ uint32_t board_init_uart_clock(UART_Type *ptr) uint32_t freq = 0U; if (ptr == HPM_UART0) { clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); + clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); } else { /* Not supported */ } return freq; } + +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +{ + return enet_pbl_16; +} + +hpm_stat_t board_enet_enable_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_enet_disable_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.h b/bsp/hpmicro/hpm6300evk/board/board.h similarity index 88% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.h rename to bsp/hpmicro/hpm6300evk/board/board.h index 72d774d76b..7410b1b2b1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.h +++ b/bsp/hpmicro/hpm6300evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -41,10 +41,10 @@ #define BOARD_APP_UART_CLK_NAME clock_uart0 #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if console_type_uart == BOARD_CONSOLE_TYPE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 #define BOARD_CONSOLE_BASE HPM_UART0 @@ -80,8 +80,8 @@ /* sdram section */ #define BOARD_SDRAM_ADDRESS (0x40000000UL) #define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS #define BOARD_SDRAM_REFRESH_COUNT (8192UL) #define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) @@ -149,22 +149,18 @@ #define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX #define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 -#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 -#define BOARD_SPI_CS_PIN IOC_PAD_PC18 -#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + /* Flash section */ #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) #define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* i2s section */ #define BOARD_APP_I2S_BASE HPM_I2S0 #define BOARD_APP_I2S_DATA_LINE (2U) #define BOARD_APP_I2S_CLK_NAME clock_i2s0 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 /* enet section */ #define BOARD_ENET_RMII HPM_ENET0 @@ -174,12 +170,30 @@ #define BOARD_ENET_RMII HPM_ENET0 #define BOARD_ENET_RMII_INT_REF_CLK (1U) #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) + + +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif + +#if __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + /* ADC section */ #define BOARD_APP_ADC16_NAME "ADC0" #define BOARD_APP_ADC16_BASE HPM_ADC0 #define BOARD_APP_ADC16_IRQn IRQn_ADC0 -#define BOARD_APP_ADC16_CH_1 (13U) +#define BOARD_APP_ADC16_CH (13U) +#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) +#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) +#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) #define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 #define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 #define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 @@ -208,15 +222,10 @@ #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) /* SDXC section */ -#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) -#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) -#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) -#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (0) -#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO -#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO NULL -#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX 0 -#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 0 -#endif +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_SDCARD_CDN_GPIO_CTRL (HPM_GPIO0) +#define BOARD_APP_SDCARD_CDN_GPIO_PIN (15UL) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) /* USB section */ #define BOARD_USB0_ID_PORT (HPM_GPIO0) @@ -328,13 +337,11 @@ void board_init_i2c(I2C_Type *ptr); void board_init_can(CAN_Type *ptr); -uint32_t board_init_dram_clock(void); +uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); void board_init_spi_pins(SPI_Type *ptr); -void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); -void board_write_spi_cs(uint32_t pin, uint8_t state); void board_init_led_pins(void); void board_led_write(uint8_t state); @@ -354,7 +361,7 @@ void board_init_adc16_pins(void); void board_init_dac_pins(DAC_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); - +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); @@ -363,15 +370,19 @@ void board_init_sd_pins(SDXC_Type *ptr); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); uint8_t board_get_usb_id_status(void); +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); - +hpm_stat_t board_enet_enable_irq(ENET_Type *ptr); +hpm_stat_t board_enet_disable_irq(ENET_Type *ptr); /* * @brief Initialize PMP and PMA for but not limited to the following purposes: * -- non-cacheable memory initialization diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/boards/hpm6300evk.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg rename to bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/boards/hpm6300evk.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg rename to bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/ft2232.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg rename to bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/ft2232.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/ft232.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg rename to bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/ft232.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/jlink.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg rename to bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/jlink.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg rename to bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg diff --git a/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360-csr.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360-csr.cfg new file mode 100644 index 0000000000..ea991b8e40 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360-csr.cfg @@ -0,0 +1,50 @@ +riscv expose_csrs 262 +riscv expose_csrs 800 +riscv expose_csrs 1984 +riscv expose_csrs 1985 +riscv expose_csrs 1986 +riscv expose_csrs 1987 +riscv expose_csrs 1988 +riscv expose_csrs 1989 +riscv expose_csrs 1990 +riscv expose_csrs 1991 +riscv expose_csrs 1992 +riscv expose_csrs 1993 +riscv expose_csrs 1994 +riscv expose_csrs 1995 +riscv expose_csrs 1996 +riscv expose_csrs 1997 +riscv expose_csrs 1998 +riscv expose_csrs 1999 +riscv expose_csrs 2000 +riscv expose_csrs 2001 +riscv expose_csrs 2002 +riscv expose_csrs 2003 +riscv expose_csrs 2004 +riscv expose_csrs 2005 +riscv expose_csrs 2015 +riscv expose_csrs 2016 +riscv expose_csrs 2017 +riscv expose_csrs 2048 +riscv expose_csrs 2049 +riscv expose_csrs 2057 +riscv expose_csrs 2059 +riscv expose_csrs 2060 +riscv expose_csrs 2500 +riscv expose_csrs 2501 +riscv expose_csrs 2505 +riscv expose_csrs 2509 +riscv expose_csrs 2511 +riscv expose_csrs 2513 +riscv expose_csrs 2514 +riscv expose_csrs 2515 +riscv expose_csrs 2516 +riscv expose_csrs 2528 +riscv expose_csrs 2531 +riscv expose_csrs 2532 +riscv expose_csrs 2533 +riscv expose_csrs 2534 +riscv expose_csrs 4032 +riscv expose_csrs 4033 +riscv expose_csrs 4034 +riscv expose_csrs 4035 diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg b/bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg rename to bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360.cfg diff --git a/bsp/hpmicro/hpm6300evk/board/eth_phy_port.c b/bsp/hpmicro/hpm6300evk/board/eth_phy_port.c new file mode 100644 index 0000000000..663518be09 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/eth_phy_port.c @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 hpmicro First version + */ + +#include "rtthread.h" + +#ifdef RT_USING_PHY +#include +#include +#include "hpm_enet_drv.h" +#include "eth_phy_port.h" +#include "hpm_soc.h" +#include "netif/ethernetif.h" +#include "board.h" + +typedef struct +{ + char *mdio_name; + ENET_Type *instance; + struct eth_device *eth_dev; + phy_device_t *phy_dev; + struct rt_mdio_bus *mdio_bus; +} eth_phy_handle_t; + +typedef struct +{ + uint8_t phy_handle_cnt; + eth_phy_handle_t **phy_handle; +} eth_phy_monitor_handle_t; + +#ifdef BSP_USING_ETH0 +extern struct eth_device eth0_dev; +static struct rt_mdio_bus mdio0_bus; +static phy_device_t phy0_dev; +static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; + +static eth_phy_handle_t eth0_phy_handle = +{ + .instance = HPM_ENET0, + .eth_dev = ð0_dev, + .phy_dev = &phy0_dev, + .mdio_name = "MDIO0", + .mdio_bus = &mdio0_bus, +}; +#endif + +#ifdef BSP_USING_ETH1 +extern struct eth_device eth1_dev; +static struct rt_mdio_bus mdio1_bus; +static phy_device_t phy1_dev; +static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; + +static eth_phy_handle_t eth1_phy_handle = +{ + .instance = HPM_ENET1, + .eth_dev = ð1_dev, + .phy_dev = &phy1_dev, + .mdio_name = "MDIO1", + .mdio_bus = &mdio1_bus, +}; +#endif + +static eth_phy_handle_t *s_gphys[] = +{ +#ifdef BSP_USING_ETH0 +ð0_phy_handle, +#endif + +#ifdef BSP_USING_ETH1 +ð1_phy_handle +#endif +}; + +static uint8_t *s_gphy_reg_list[] = +{ +#ifdef BSP_USING_ETH0 +phy0_reg_list, +#endif + +#ifdef BSP_USING_ETH1 +phy1_reg_list, +#endif +}; + +eth_phy_monitor_handle_t phy_monitor_handle = +{ + .phy_handle_cnt = ARRAY_SIZE(s_gphys), + .phy_handle = s_gphys +}; + +static struct rt_phy_ops phy_ops; + +static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ + return PHY_STATUS_OK; +} + +static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); + + return size; +} + +static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); + + return size; +} + +static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); + + #if PHY_AUTO_NEGO + reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + + #else + reg_status &= PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + #endif + + return PHY_STATUS_OK; +} + +static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); + + *speed = PHY_STATUS_SPEED_100M(reg_status) ? PHY_SPEED_100M : PHY_SPEED_10M; + *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; + + return PHY_STATUS_OK; +} + +static void phy_poll_status(void *parameter) +{ + int ret; + phy_info_t phy_info; + rt_bool_t status; + rt_device_t dev; + rt_phy_msg_t msg; + rt_uint32_t speed, duplex; + phy_device_t *phy_dev; + struct eth_device* eth_dev; + char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; + enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; + phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; + + phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); + + if (status) + { + phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); + + ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (ret != 0) + { + memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + } + } + + if (phy_dev->phy_link != status) + { + phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; + eth_device_linkchange(eth_dev, status); + LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); + if (status == PHY_LINK_UP) + { + LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); + LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); + enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); + } + } + } +} + +static void phy_detection(void *parameter) +{ + uint8_t detected_count = 0; + struct rt_phy_msg msg = {0, 0}; + phy_device_t *phy_dev = (phy_device_t *)parameter; + rt_uint32_t i; + + msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; + phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); + + while(phy_dev->phy.addr == 0xffff) + { + /* Search a PHY */ + for (i = 0; i <= 0x1f; i++) + { + ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; + phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); + + if (msg.value == PHY_ID1) + { + phy_dev->phy.addr = i; + LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); + return; + } + } + + phy_dev->phy.addr = 0xffff; + detected_count++; + rt_thread_mdelay(1000); + + if (detected_count > 3) + { + LOG_E("No any PHY device is detected! Please check your hardware!\n"); + return; + } + } +} + +static void phy_monitor_thread_entry(void *args) +{ + rt_timer_t phy_status_timer; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + LOG_D("Detect a PHY%d\n", i); + phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); + } + + phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + + if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) + { + LOG_E("Failed to start link change detection timer\n"); + } +} + +int phy_device_register(void) +{ + rt_err_t err = RT_ERROR; + rt_thread_t thread_phy_monitor; + + /* Set ops for PHY */ + phy_ops.init = phy_init; + phy_ops.get_link_status = phy_get_link_status; + phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) + { + /* Set PHY address */ + s_gphys[i]->phy_dev->phy.addr = 0xffff; + + /* Set MIDO bus */ + s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; + s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; + s_gphys[i]->mdio_bus->ops->read = phy_read; + s_gphys[i]->mdio_bus->ops->write = phy_write; + s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; + s_gphys[i]->phy_dev->phy.ops = &phy_ops; + + /* Set PHY register list */ + s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; + + rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); + } + + /* Start PHY monitor */ + thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2); + + if (thread_phy_monitor != RT_NULL) + { + rt_thread_startup(thread_phy_monitor); + } + else + { + err = RT_ERROR; + } + + return err; +} +INIT_PREV_EXPORT(phy_device_register); +#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/hpm6300evk/board/eth_phy_port.h b/bsp/hpmicro/hpm6300evk/board/eth_phy_port.h new file mode 100644 index 0000000000..70c24775e4 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/eth_phy_port.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef ETH_PHY_PORT_H +#define ETH_PHY_PORT_H + +#include "hpm_ioc_regs.h" +#include + +#ifndef PHY_AUTO_NEGO +#define PHY_AUTO_NEGO (1U) +#endif + +#ifndef PHY_MDIO_CSR_CLK_FREQ +#define PHY_MDIO_CSR_CLK_FREQ (200000000U) +#endif + +enum phy_link_status +{ + PHY_LINK_DOWN = 0U, + PHY_LINK_UP +}; + +typedef struct { + rt_uint32_t phy_speed; + rt_uint32_t phy_duplex; +} phy_info_t; + +typedef struct { + rt_uint32_t phy_link; + rt_phy_t phy; + phy_info_t phy_info; +} phy_device_t; + +/** @note PHY: RTL8201 */ + +#define PHY_NAME ("RTL8201") +#define PHY_ID1 (0x1CU) + +/* The PHY basic control register */ +#define PHY_BASIC_CONTROL_REG (0x00U) +#define PHY_RESET_MASK (1U << 15) +#define PHY_AUTO_NEGOTIATION_MASK (1U << 12) + +/* The PHY basic status register */ +#define PHY_BASIC_STATUS_REG (0x01U) +#define PHY_LINKED_STATUS_MASK (1U << 2) +#define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) + +/* The PHY ID one register */ +#define PHY_ID1_REG (0x02U) + +/* The PHY ID two register */ +#define PHY_ID2_REG (0x03U) + +/* The PHY auto-negotiate advertise register */ +#define PHY_AUTONEG_ADVERTISE_REG (0x04U) + +/* The PHY status register. */ +#define PHY_STATUS_REG (0x00U) +#define PHY_10M_MASK (1 << 13) +#define PHY_100M_MASK (1 << 13) +#define PHY_FULL_DUPLEX_MASK (1 << 8) +#define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_100M_MASK) ? 0: 1 +#define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) +#define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) + +/* PHY0 register list */ +#define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ + PHY_BASIC_STATUS_REG,\ + PHY_ID1_REG,\ + PHY_ID2_REG,\ + PHY_AUTONEG_ADVERTISE_REG,\ + PHY_STATUS_REG + +/* PHY0 register index */ +#define PHY_BASIC_STATUS_REG_IDX (1U) +#define PHY_ID1_REG_IDX (2U) +#define PHY_STATUS_REG_IDX (5U) + +#endif diff --git a/bsp/hpmicro/hpm6300evk/board/fal_cfg.h b/bsp/hpmicro/hpm6300evk/board/fal_cfg.h new file mode 100644 index 0000000000..e5121f56d3 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/fal_cfg.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6300evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6300evk/board/fal_flash_port.c new file mode 100644 index 0000000000..1ed9fdffd6 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/fal_flash_port.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-01-31 hpmicro Fix random crashing issue if the global interrupt is always enabled + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + + +#define FAL_ENTER_CRITICAL() do {\ + disable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_EXIT_CRITICAL() do {\ + enable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + s_flashcfg.device_info.clk_freq_for_non_read_cmd = 0U; + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld new file mode 100644 index 0000000000..4b534d16ac --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,304 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 384K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld new file mode 100644 index 0000000000..d2cfd45a7b --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld @@ -0,0 +1,297 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld new file mode 100644 index 0000000000..da0acc5499 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,259 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 64K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 64K; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 448K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x10F0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld new file mode 100644 index 0000000000..90a92d556c --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld @@ -0,0 +1,252 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c b/bsp/hpmicro/hpm6300evk/board/pinmux.c similarity index 94% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c rename to bsp/hpmicro/hpm6300evk/board/pinmux.c index 202a477985..1f1f8d772d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -28,6 +28,9 @@ void init_uart_pins(UART_Type *ptr) } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_PUART_TXD; } } @@ -135,16 +138,6 @@ void init_spi_pins(SPI_Type *ptr) } } -void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) -{ - if (ptr == HPM_SPI3) { - HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_GPIO_C_18; - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; - HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; - HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } -} - void init_pins(void) { init_uart_pins(BOARD_CONSOLE_BASE); @@ -174,8 +167,8 @@ void init_qei_trgm_pins(void) void init_butn_pins(void) { - /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */ - /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */ + // HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; + // HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; } void init_acmp_pins(void) @@ -248,6 +241,23 @@ void init_can_pins(CAN_Type *ptr) } } +void init_sdxc_power_pin(SDXC_Type *ptr) +{ + +} + +void init_sdxc_vsel_pin(SDXC_Type *ptr) +{ + +} + +void init_sdxc_card_detection_pin(SDXC_Type *ptr) +{ + /* SDXC0.CD */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) { uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); @@ -262,10 +272,6 @@ void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl; - /* SDXC0.CD */ - HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; - /* SDXC0.DATA0 */ HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl; diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h b/bsp/hpmicro/hpm6300evk/board/pinmux.h similarity index 84% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h rename to bsp/hpmicro/hpm6300evk/board/pinmux.h index 66b1413d0e..5dd98741cf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - *Copyright (c) 2022 hpmicro + *Copyright (c) 2022-2023 HPMicro * *SPDX-License-Identifier: BSD-3-Clause * @@ -16,7 +16,6 @@ void init_i2c_pins(I2C_Type *ptr); void init_sdram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); -void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); void init_gptmr_pins(GPTMR_Type *ptr); void init_hall_trgm_pins(void); @@ -29,6 +28,9 @@ void init_adc_pins(void); void init_dac_pins(DAC_Type *ptr); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); +void init_sdxc_power_pin(SDXC_Type *ptr); +void init_sdxc_vsel_pin(SDXC_Type *ptr); +void init_sdxc_card_detection_pin(SDXC_Type *ptr); void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); diff --git a/bsp/hpmicro/hpm6300evk/board/rtt_board.c b/bsp/hpmicro/hpm6300evk/board/rtt_board.c new file mode 100644 index 0000000000..b28ce90a06 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/rtt_board.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_mchtmr_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_manager.h" + +void os_tick_config(void); + +extern int rt_hw_uart_init(void); + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_manager_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void app_led_write(uint32_t index, bool state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + + +void BOARD_LED_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + + enable_mchtmr_irq(); +} + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_HOT &= ~(1UL << 31); + HPM_PPOR->RESET_COLD |= (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm6300evk/board/rtt_board.h b/bsp/hpmicro/hpm6300evk/board/rtt_board.h new file mode 100644 index 0000000000..c86742e833 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/rtt_board.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include + +/* gpio section */ +#define APP_LED0_PIN_NUM GET_PIN(A, 7) +#define APP_LED_ON (0) +#define APP_LED_OFF (1) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* CAN section */ +#define BOARD_CAN_NAME "can0" + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6300evk/figures/board.png b/bsp/hpmicro/hpm6300evk/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..e443d81f4cf62a2409eb6e3ef10c9e725421898c GIT binary patch literal 535149 zcmeGDbypnE_XP@L!QCZza6%Y7xDy~a0}R0jcLIaE%M65I!Cito!6A5XcL`2laMy>= z_xIej?u)oV4RB5^$hwEbLi3Kr1?U9%JmgHJx>I)_JMi$>(ucA#r-i;`7+*=rg~< zB7UW?{@Cd8n0}aj^fCMSGNSXIEZ_{s_`*CcVEtjO{iMnN&|w{NHS3l=awhR|QAM=| znK!0I+8z=|`z96!UOv2^c!(97b^ZT`zH>k|L;UPLi>l~lOHk7p;(!>h3p{*N7YO&*Ojn!xs7-n*Nv>kr2vb+G~CK5HG$XPZ%YB?2ui-kMIG z7ewnV%dRU=U90mBC*@)}rT2XwR-eJG)GtGw&w~wnA2Ngtb@GSq`};a?rzM`I#ac66 z|BWz8H1RI^Z*2ZcUH5)iUSC^;->R)X|D+O}8}oJJTXP)CXg*Q!5E1`Bj@|hjj~};t z{Oa)kI}Z#gEnV~4Gk(5U9c%VHn-Oud>vfZKeT+70|YP=CS6wSLe$KgyfZ$T8&BYT%;k$Z&iFS>?nFT?%WGlfZw9g zw(Q|8=eJi@W!_$_#;X0-KgEBZ9E>HuzcV%(rkMZ0d349c8if003!d&FV#Teu9~2zB zu%^$#x0T8y==H()&jpu;9dw(M^Zn|tWmj})4${?jDyQ$EoskPXLi{pUBzyn1*4{Tc zh>!qVh4-WI;aNz-=7QVc_N$j;y{AcbtC3`*#Rdfr$bNCNq>dj z1>AO{082t-ItD6ygyHkeN991{Oh{XtEjLEAw8r^ytOHFD%IhrW&JZBl z?JL-*Rfah^qv%=RBBh`XFQ)Dv;7)02j>RHRKFzhuXL4(c;gqM=r)m~iQvbzOl#LDX z(|3*$cc4wvvWAr_B5U+oC5Ge{6@oNx(f(LnTU&tT>04jcC4>f4tLm{qk@Y)O*Wvd~ zqGzt5x4#0!Oj#cCl}>DYelLT4+K)%FUMX=vr8>`Jlz2>T z8vO7$7 z)3fGi8+p8E{AufiAd7-Sm6$NP$a1SL8QV{Qzp%D8a@_1}YUx9`xq~8!PhbYETc*Xs z*LXvqXSCFC@fP?7Mi;c}4S&}vRvqog6KXV(TeFZ^)sxw00K*{0A+o;D69|b0cVyW#-=!9bhB&JXUue^5m47ae1iP zY0D=JjiBUIfHky{bIeou6>g|A4F!maxl7pRC^OPmAKg%8kV#=UW^cF7RGoIusH+8# zT>=s7d@klrS~2+Oq(Q*;&f5iJx1dZGQU7l-1j=91-dT$+UMaQ(7#vl$rik+!6*H1b zqXV|S!ZiP*lW%GP3Y}slpI7z*G^*RoKIq@^x~rYsQmmz1Uh&%$-Vk`H1~L*uiMMQa z^`G6EVfGe>W*BN7s*;3j<$GnzjA*(xDr}m_#r)@RyzaM-2 zJy1xu?nA3>7Zw*SHl4$5yB+`nUw%IfRmvbhfD%jalXRB1P)}{p>{l;9Uf$rQol`q- z9k9j!itOExRuW<0E338xUE&}cPL2j?>+p<`Ueq*q+`t+=L6OQ;kJ%1^5+Kukbk4uz z6dzu-Khz|$_}#ih?gBbi;t{UYG#u+U)=*yFz^sEPc{QyprbA9mmB#2k$B!3jvW0Mv zZk+XyuRtqG$xnKAq3PuPTcN{!9qc$J1>ly4n0W7S4+_B^&mGyzEv>Q=!hg~FQ2f9C zvotl8f{o7pkfxh}leVfNCF{+?*RdJ0T2fab|~kB^ulpNLK1KcU#=u4g{+m_gaioEPy2S<8wpHvI6$M2EI}CStih4`w9vL|8c; zmF1KQzds=J^(CZ`^nui~h($3Ass@mhYR?t~tosE35fW1O{x4GB{ue1|drC>PZ5Z7x z^R)*kKil2iw)X);hrvDN{tl*G_OX8WcmTblvTmB?>=%Tk@yU z@SfhYIRoJm&Gj`3C8g}rC?w@2t=|3zik#GG{~=Q|dJWt*CQ-f?3=u})Ld|2f)4Fzw zdN*|Pw8kQ;pn{4XELDQfE8>V-x|F;#LzmoA`WXo1Rf{GF3nWLAJ*^XIC}Usvd-_!_ z7VPLRbaB?YnxzLuzoHZ{&Y2#vFz%GN_y~m%NP^##{51cioW78(*pO({@vyzZFh1-a z#-z|WzX+kAJFE>qAgt^cCM6@Awlw*VTPeW*0ju*kk>(?`>0Cp#>uWzRN*^g_Kkr9- zBLyuiMOvHZ4H+w~taE=)7h~N88vpa>h>#A71IHAj0f(wuU2n>Yh@|)Z`NN=rtP}1Q zz4(w?p(4H2j`y9-S`G-5e{i>?n&*Qdp>(Q1v+Vhn8Y0BQF@4{lV7GdVk!AXR^=j7M zJE~-{=1q1#=OqV^{?6So^x#wdk7mUTObCi!!#;YQ7rb3+LSoHLowzOPZ1Jw`fnJ^F ztHvz8k=B|_T;?STR0Qp8)Kn@%aaIj_ZyQn{aO|B@YPp-xg^Rcb4BCD@zcYe;P8nPA z(`JZu7iH-FMe|7t#4q0ml0fA|(V+%TAApp5sFGJFqlVotjrtC1wt zddq$8E%5C%3e-$aH1ynee9J<1`|egZ`vc^G*kJ5v3sD-0sHN+`NJJ#a$JErs1zQz9 zovB1{?J*`jilv%Gcv9h=3i)3@gc?h}w07HxvHNg47NsVD*Tp-Xt0L!(OkH0szJ0H0ozfXCH{iI31?!lu&myVx>;+0bI0m6av=jgi65ol#8)J-$t8 zroB~J)?#sIVN za&^GLeVmpNss9E{TNP%(qL;LHRLOdSd53KAl!VIu20G+_9M>-C8-1!JtE$0v|e!d@L1 zj?JC-%O1gA>%n_|L$pq38KukQJazhAQB^J?14DSrk~@o9mddLEd#8AA@qe<<$;DMV ziYbQ==IPb@(r;^N6XVKN-+IiR3dP9HSk$7P*+b}{Ab7)^H1M#-F=U~}bY?E3ERjmucHeB2N5ei8%M(dX1X^Hr%gVg^}Sx@8$6O#&C5Z*!DR ziR>FC4Ifs0F2OxJ-?N4je5{&9X}=)i5J5Y?B_pc5qUtEuMEdqlmmCbWh7wAvKoJS- zvR$@dyhI4FNvR-PIcRi4ok-@ujwd3goK?`*w(!#GYMvinn!BHoW6Q~_YuvM94#_O9 z$3&1!G;rvm;}?+;+Kuo4MK}!&4C6eYqu~+4oRuFfIDg*fXTDd>_~o(dx?SW1t(mqX z5NJ|p9Y>nO?+QW9NMecSmPJ%Ebd28-YkqEispu+~Gx$IIs`x+q%A62|NCM{3X3@sk zJwnDC&F~c#oIlRuFyoe&vQ$|15{Trczr`@)fwEFQab2BaevZtg@Bf7Ea;=%4z>Hj& zVgKF2^@n}6-A!{2im~bEUho)v;Gq#a+)7VQ}-g(iKD(a`u1l7~VY!y#(Mlf-Ql5)=a})g!0NNkE-Tf^f3#% zk2~8KO#lRw@hmYtWOy55NJ7`t3Rg{?>tu`gCwU!%JdyQOv5}3p{iJ#>bYkHb%B^F{ zgLSH*T%RJkO%UA|v2xap?df_fkbC8?-;b^h)4gVaVpgdeSn)dt^q;Io-;c)m=KXCq zUvUv3k5zQib*KjI{uL^3$c(UAuJUARex*FI7aCZ&ZkY&7;%zP$Vr;z3kEm|UCTTPx zb(tX&;J$m-o98Q!WO3ygxYe z*Pn?CWGf<~^4yF^)~b(VBTe@>7(G#Q{Xfr9_CL>|ICw7J@soS$bV8;WwJugb?hBH( z+b(PR`~EF>Dn{TBPGp%i!@Qr$e_H6H(?NMed2dj_yta77W0~o9m}#ujR~IBuCfB>8 z^Nh)4UEtDJsyIk2{^JPc6AT8k9M2NipWnwY6>atC7))=B?t~51m3P`gqVNEkeP!B7~Ni(_r~xowZyL#F=E+wZ3nvkOpmuWe%WO42%ZE#Q%F;2R!?&VMKDDvC(246d(|Fg zT@EXn^a&39Pl;&V(w9XzbP>6Xkv3NPZ-12fJKq2Jk4NV(AWD7J?;Krfop(425_c&c z2E10a$Y@nwOEJ#}O)m*Ai-KUOuQY8hMzPuAFF&cWAs5-yV&3oi`ww@=+;7|0z1Da8 zF31KV;*5AZ?slv0*NTk;p5`l!g+t`WjRUT+JbeFlDEQwTcJ9jc=(e4w*G}*0rbs+2 zig-7zUdJ~V?i4=uAI6H_$bInq`@7GTC6d0n!#y5NEu(WQtw*85^JpRdeq%P`aZe)P zW?P2#al;b~wyX6x`Lh&o5!Z1na#MNaMPMcb`A4vJ^Stcup~+v?v~vFYaoP9@-WP^t zMYeX4bz?O^D?Yp4>hv?+?@&O>IICrRmue>kl2vD|;uu z@^$BM9m_SH^*Z~~v9oiA<>6P;0+*q6JZ|0V z@OE_kb&*FVcGDH#qi`LLFXVb{f2BbC&}-!f|M>M*{S02^1=&0OTYRpYQoJpT~z*Xe;b<<*=# zuKqWy-H9B3F}iT5^4#dw>h$>gc=rhW@FKiRM(VkJ%NChsR5ko3tG(?;jP_mVpo%es zxASrM1fUqFAzEXx(e7* z2)H#qpLn{t$k>yJIPrsfIPYb8)HF0pY0Yz19?fEr&F?&&w8K^?)*h3ycP@vB+U`_d zNE1jNXVlth?7|Y_M04hLN`%;24A<^CPR!w(Z?bNJ_s&8j9-kif4;^=YAMm!FCX=0h z5Aej=8_UX{KQw_AF4La&`JC)E-mHWVQ9C^gI&F`?Jbv&RKWWcats0MOKYjoif7v;@ zQ~un~m`qBhw^o<3?s;?KdUi=+bgi=9RrcDIkEbu^TcKZju{!Tbvo4OTzW)6!7tJ6; z5Y4c+_WEw#>^sqZ^v+vliSd9(wUbR(58tfroN}9{)R9RS9gb6-frXzR`4IBN&$_^m%SaA_d;eb_&yYU~h2S#&u3^-D z8Do(+V_83Iy3bX9&HZOpWhP0*bB~oLylnr~{(hZf161bx<@XCs9$}@|oFCphU(`8m z;yrILW(WslB{cbk+QmI*-^a&2*4V>1(pq+pQhAS7Tl286E_hNC4IulJ?apW4J;UnA z=I&Ajp9p=fE2}#`=FK1S>_b59&NOz=w?dxZ#2&6|>)K(_Ced8k?ORwY_nn>byjEkT z7s1^ogVv%Nj0_5KH2Iv$!XddOd7GFRW9MZrXVmz}UIAG~Ecxpv^6HB;3X4ruK zN~I;_V|6m`>m!$kan7gzWHLVbg+DvTVv*^%fV!WHsdtZCJ3nD(t*waW3U&z%tUThQ z{A(%7NW4TtCMDg~(_2H9^?zD@5fs_N7=E~BWSzsjh=~!x>hX`r6Y1SaHwTTaZ1OZc z{T=vqy(Gg)E%ZstCylxO#I;kcY1wo8-4*`m+cvHIqJ2{&Y4YP(?3SH)IV zn)(PUOaTIAX_f`e^;-sawu<(IfJxT_B1kD-+Bn{^N4zY2SG#}sG`N@L{%&hjbs+I*!M0ljWOnw#H!oDnH@n0*3M_gPU{ae=1pQC*VR##Kj z#QA`{((cmmJTT;>JKsR~Dsr*z7q`(;6FHZI)1mq1mNY5E#wPVDe$Y%ptHf*nv1R7) z@X~c54ds32G$OyqHo4QgVg94e>rabsm=ShDk+EVDC7WwhBfi@UMdrFz)1*aR1|9#2 zM*6IyYvJSbuMB3Me8RdwxNMPJS6vcy;HLDOQ0UHOn`qpXC1K|;uP0~u`W{#R*b!qL&8THmT|Z7 z28F@ex3d^>O&b%l53h4;zWiAX6`A_@!T-YbZd8?~_tif>VH z!WS8{A0FGu!2~$JLFb@ynT;BU}87|2}_cu4c+uPf#KSbKn$>t97oaagQ=AeX! zAjT-i7(lM1o>nqFhOWnOV}_N5B_uvTRwv+)pXq_*3eb2_SL_H^dq>A zeOqx)=~6>mor33rAwO75f{xClhKLMORI`m~$Zkd5gW!*`M>9VoS{!^(4-Xk9Ij70N zoYC&tEutUv^q0oLRfPnD&$}0xaj>OCR?<$fa1*rMd=gJ%RG^AA71Sj||Zs#413k>NC;xUfnarhKOY5`^f=5kv|B zCHC>c3BmaIKZm1UCygp|CWb`AE`kDu?_1i*Nv>dI5b7XSSvibjNarbsDp*^J0EXgF zhq%SVH{;3AC(a76RM`?4Ba9JcL^0KzznzHeXH_xWA~8q?*ToXrmZLXJ4V8~d7HGV) zmGnF9Us%#BruR0}g2?qPsFK-*T60n+1^(Elis}ZJL-LGrMk&exdUj{xc^YQ`d=ehU zF>*+^4^Bt7@$-Gur>*5L=1@el-sjnn(m;iR1dDA@EXf-J=0mb5+FK!Iv4KAZ-9df0 znOQqiv8Gxyy$cz2cmc_rC(Z|(ghcmn(%(KKmB&5VGJKm&H8M61z|ekkt8z5*y8e6?BqBoB*Y{zz@O~3FA9>f zr}Ura4N|U$s}ReisLs`eLip*(?TxIbX9)ArG?H>Qp|Tfe<973)yu(skV&f#Ucc_Qa zHRK_AhAkZkmRyFMe)Hz78b8F4dpgJip`J=+So^zXtYeB#oVn=1omRr9p-5Jr^( zJCq?NrGfThodlqUw)*WHt*>9jj~`S=5)bhKNwXU9>K7F+({VFWwX7wfIi6|?jY-P-j4o=F3x(wvR*8hZ`r)je6dY0~) z0et45a0n?0GI}K|f)x5RtAdcrW4-8Mk=6d=@3&Ox%SWqq<)uc_TJ(~Zk{W6FKbeVi z9EJLS|IQGAjJ}$5g=^Y{VgRadr1{ts+t=9*xnAe%qmQ^p>oSJGQ1pKEh$=t*wkOvc zB`BiYpn?1`=bDew)~}bK2o=MoR>B)^>S$5$Nfy)lVI}DB@_1%VXbwsk!?@c^mYksx zIr{nM)g~v}d_~1ADwj$_KUOpRLv+Mw$Fa#`!wMF)OiL>t1t|ZKn6spvAc5ICS!C(f zszCM*t^-^&POdRKU^3_X4~Kuw83b3H+x@X9b;18nEx>*cZI2!!0QLTfW?6)ZUeTcF9FV52a(Xkyp7YIro{^`G|67wx{eUKt6`ZXg#Zp$leY9I$SeJd_L6W z+iy1Z%Z2zP9Qb*{>G@>`YL*&o%5SnJ%s{412dGM2~X%S;22k%v8EES zPcMc;xCHN(oFIjW!0dDeB9qwI&V;(u&W%DK$!Ug-dP+a#*je1moF|D+W3`mrwbbaK zfifEzhfmN;$ro%+0R-_Zu9?-W_gN+v`TrmnMZ=?^8|RTfu`0D2wkxuUiq7tVPWv8AFTcO(f}uIr|q5{u$D6_m)Jm3UH_c zd+XQB@R7tl%OP-|leeiPd5v&_etemC(PrG}(f`P2g;wL{s1Os1i%^x2{=l0cPLIf|&;v1k+ulfg6*4f6KcRIa zi;&Gpdq29kr>}ZO-QeXFAr*04&Wv83UIDHia=)x>Qa@TA;8h^A`N#p=so)ja4F2s7 z2cHnVcPL-&mKqi5zhM+fYHQF9f35wTiqaPm*&CP*l|ARmTp`S`&;<5wfC6rn--7;~ z2JfwPNlREwjP7p}0J#NNT%!TuEpMl_(=WXjr+3N1C2j|!up~}9pSvV{Zs1J;2UaiJ zT1^3Go$f1FH*!h{9nyviqF$@5>sRS7t7?yjwD*nRfy$4K0pq;RI{SFLryWvIrc(TW z1i6b+l^v9|UhGZ_SzSE?YF{73@TxluYi>3WZLt!55S0-Qp+MNb0HjfP9Ukr1609ln z*mElZb5UlIlZ*^-O%7B>C6-dNUVKA5Uzq$Gmy*vi@52BfA1wjW{P2yh_LuOjNHcJT zfOv2XgbG^9h*V?>2uDq^AO{2FCpOO3%*y*P$pvLy(Z)2r$647`vCUlbypQMx%qdi` z?b&6&Y%!T-<|DZq%&ocQqrGv#g%NN^HbnBmJN;ycmZ+ragZl%22>j5tnONwd=oX4d zbvNm+eWxD*=ggzj0RHCdI@}KaHE6jLZ;hd|Q2xGXKBSTmENNCi+%qO*VkQYhzeB3w z)}srRoWm-&A*1E!)wiWR)A&J!JDA~oJIJpe+rQba0Qe!mOcyG&y02SOrgU9CGLY`% z&+K~Pswrrso1F6Nu+rxZZ2yvZyNDpmNmRph{X95J%ty)~`9MWbLZ)K0dMP7#JkWfKj=4Og#EI`tH*5D;0$yCdD4_*H%CV!fjL387C&m- zy#oC&Dcq~F^Jq-tt9*k5X4v094yR5Rn_Cr6^@Yii?xG6q@v$RGTN2Zo!6x{!mIOtg z4ir8H_^ZT8d^Ny5ULP(HUA=a1z7B7ys|(=|?*C+O+p>yV@^9Knh*={^advQQOt1X! zWT0xnlNc2N)b;D_DZSyBFIF~Q81$OJLUJ%S;l#q)4}y@=DK<>uOkACuzG*un8$`pQqyi3Px~|y;P9;y{%{1#wM8<-(xDq(&hlCJ>`iNA;b-^S zT{7wWL{)9^5rA3_FfWbl6(IP@e!ikO#|OWevl#Js;Cm7;jaPiDAxI-(Q<6?en~Q;n z%tt>pN-Zu>0x`i6*S@W_4HySBO3X*CZx9jdRrMtP{EGK^sNS-U%?Af7cY_pp<}+WY+Ma!k zM-4iAhNg>~?D)x*nemVp}I%Dc=zG6Y9%9$sJIABNMR zg0anbmSUe4*1+nuqS>f7@eAn8982@wANRAFwawnk_Sy7KcALk>)}J)!DRXl4HVX`~ zXl_?hJEUhRKpiH^lwcd?l$W~{>{A^l=oUo#mJaxa^I1sFIz^xwlM8G1SP#mMk|$7J_kC*j4(=m&K3KqY7n2193~5d)-0@O%x1ON5cU2>rv@)* z%=-&g&S19?EG+if*i_yp%?-t z;Rv*}Haaub&jobcG$$JZsuw-$SC~dmqg6Q)`^Zbj=(JZg=8DVd+SnwJ=2d25v)9^! znzAyh&WFKl-}B{bW1s!vfCs^~hoTQoy;nC{uR8g=mpmf-@v!sPRmID5#d;_A{9(tx zFUF&=aZiC&)hf86$#r;ToX7R1*V?t+$wop`Ky34qE_l_K>W2jdWum31lrOC1ZMsEh zEedRVm8)?dKMmD^egBf)(;gc>DuGho-~e`{?w8~y#h`(F?4RHEn!MJ0qc-yi+kp`~ zxOXAhEEKio4Ji396kod6C+^KTXFf&^j-+h0S8Nh4=wtVe+_H$7!!ml`C;V!9{PqF8 zkUHs893#39n0Yt99LX|2I|o9h&HE?|ruWWQb!b=X6lvgM-$i>UMcNS?=0oZ+Ff_ik z<)nUgPPOxqsbKo-w3MfWO|Z_l?G+>xgMmom3|a;sLUY!d#FWu(vB_YG1niGZUFOIEGue1&OWH8KdiBOW13ka7-#ph2HXz<8J<0BZ&fhJrOfb zl$ke>sY-CQX_GtVbnVH_V~1DQeKm!^I1l%S5^jbIl@CRq`l)_E`{CAeJGeTtHdPtb z4Gl8KJkqDwd%Lg37X?sqkKfB6%V-W#)vgAqg60wvqT%owK1kT`+t-%dw>vJEu{eBQ zULy?~Dlm7Mn9j^}0O_aA&&HI6meg8}XSrX>(cL4^*GDB2{Ab_X%eAFVFm>e(DVLQwWHqRNx z+mE?d8MdbSQK=d<1+#uj9&@H$Iivhzmb4cUu)mysr*c}l&9%2-M%(Z)AN4EC=hA4` zvNB@Q=sX2W9AIQ3MDD`}XOI*+j%=Kh?TpaZLv^r=SA@}ViNY7YP3!)2V!0ISr2@Lr zO|W@cx%EFx1=P7sKS{skNd~Xjn(*J~08EH=q_~MauKd#Y=Z8vss`ZW!tGKzG%NHVV zCL3-rYDl;2MeZj&?RS^5T;d!3@S?Xr3XCrez~U`6&ECwQ3&;z&%eQUsQhE02N~C0F zQeVHvy;>^68@y>hsK}t6-Ojrd`50W=Tqo1{gmp?Ld{)kon%yTPzpXVHwLB z*f4KijM&D??1X$eF*BXz8=`uG<|Tp=;pwFPAf*Y)->y0hK6gED6L9WfVfC@pH??5=v$ubPRfk zR!b5W2RA>X;aq`h3c>Y^6sk-7(e1%97zE|4FzEqI3W5_xP*yyZa_$65TwJoj5&@;L zj~QHJ3%}+POBoukNd2mFq{9Wcy(62%c{khrljH*>XMB*53mPj-X8z$3bJcHD5^RZd+?%tYVLM^rhP1aIn6x@zTovJ zSF=>c=+gaGQ88<^^3c`Z`E<~Ezg-t=+PS4zrLo zv2)GbphE5O@@^NW_vX=cHW?Rp^jnQPi}mP?X?mLT0dOenf8ZpPdG}eFKg}92*3h#$ zeMqk2^v(g_DyqZL$L0rW6_*{A0uDKj!`B>4ui^@#xLj)f680IrUOj^njT(6GCjx8s zyhg$6jbfRn8fr|kAC8tn+m#Yksxs&e&h}c%%Ro{)*aJB zxqQt`1nP9lf@gle`y2SWV?r^8(=dGyX%C;c{p5)4l?5)(FQrn=5@i%g(5#R|X9sxO zC!0dk{c#gj?$?(Zf5m*;9D!uv5Y|Fg&p$bG380Eu4`v{-8wm1tSb*_=k0G6I2zCB z`zV;HfRGsrUSWm63zy;6P0L^d9rC4lyYj+oL_6L*Ei?OJyVBacePYiO3YaqY^dv3} z<)ry|zac}&HU8l^AhM!@pc_q?!-odTw}{c5UcT1G!K=MFtcv~ID7yltGDaie@0DnF zpBk>$C^kN)Ck>rGM_15xAWACjT|BT3tNGT%-$$nhi;FEtwIP(USK#smnpNcU?wiV5 z|0{w&mD%|kavKXVd&yUPqpC)~+A%sgC`p@0mW*;xNX8wxYW`a)_BdHAF}^ew+Lr}h zYqY?siN0mv{%L1lKA36I8f~wpbl=>!B*1p`sn-Lo_ZUfqKNm?`(r>ic#YCNdyMLlL zlE}hOG&c%gZU|~RCO@Oc+;0YxE2W-GLzSZVDPyKWz`W2F=e8RpKyJXwsT@Kw=4kKY z=o38jmf6Dr-Y)rJn0z;Olv({akuQOe7e47Bx5oUK@LjzrN<~Wte$s_NFRK4dZn`m_ z*(0(hv=lY|x~6EIksuNhQdKGt#9j2>=`3i0PY>+15l^%t&ibp`J4z9x)K%Ts5k(@C z|C{P%b=hlizAdojr{`AZOQ(?kCf}Mnw=Hev8x96fT5j?BeBwWD+O_Z@vb`mZ$bL1S zvs7FW@0lNsZfM-rBGJ&mGY7V4`A2j8DOLvsqTSQpokTa4hBcp@zRB$7cW^%Y9`b^DJtOx<+QY;Q~ue%b$)!Ywq zOt+*8I)w~g|Xv?_L`Ah-I21ljdevEqGuxd4)g82*}kL&Grq zmVv?*D~5Ayb{iBi@4x5adYfkFd9l3K7sd;=caqE}7+qdd(E{>Ko2qfV;Q5?TIDow8 zJf7F;dp_>91G!DA z0X#!=D5%P^xhoYqWnVNsbb%haV}jY$Jyg3r7g@`-1E#&VA#-^*DW&?56Y+@Wjw;W>zWu1Il25&=nLmFn~fzvtuAILxeHjzw!WwCR3L2Ac-OD)1{b> zHhnFk!26n%n;1YaCX>7Qo*MdGHF&T zU(?E~6Y}Th;USgw6`c(@QKh=0W9)iPK#u-A=?6o4`j?q2ghG-z{i1}ZmAU2;*UIhQ zD6+ea2nkh?4t8lYGxPlw1VQ@qLT&E@%{qj*kk6;v<8~;qz9Y&dIGM5{*JeMF8AVE2 zCURzM=y!p!ts4mgKe~9d>7tMG8vwH}Z(qzR!D^FFnp5|Q?4SJM=t`S|G}3iG6uyR8 z1Bn0v{+X4p7aFCt+ed|E1_rcX1E~~QrSLh1=F=>E#)Kg#BbttlG=ud(wSB64R;K*7 zzXdpKhH?q}u%7VnePosC>JSENHfyD_kJWi4OUc1qd=&8&v-~|l7E>eEekO&1K|oL1 zGs!OXf4w=Bgo(TVJj18L`xS~NO)9#r-%L)B>#?#M0H=K7qp>rp6Ui!_cpbi!11>Xv zbm-okSlRI9;l-DcjZdjD*J@bp0*(V~DAzr1%i#jdycm%LyyhE{6RsiuLUIoKO`r^+ z;mvW%+d@&q1tpxAXo|V@o?oG^2CGXuaWnyGe?Z|_SQ)S7wB^g-!H$11G@D~zoVq-4 zs+w=y*B-hDysrP?E)Z7j)ZyCzW!cDyH(~hM&Urj(;(eTQ4Vp6yeI3~%pA!c=&AwZX zu%7-g(R_ECMPqYhk6A+eX(`u1YG40Tlr<-tTn6cf<~d5a-aOXw+(WUUNbE5V83JKc zpQZpuIzsZooeo0Y_gMOEL^?xR$oL^ChSDO^@*@ePbBpgx=?O3LjNTQpPR@Hc7Ug0PaT!z8 zb$r}eK#rSO3Wf`8)*m^EGncFW&O=d?1vmT#C4dkCI0_bL-LChWBs#;v@d*Md#z(h7 zCwDrIZGTCn_Y2(ANq55Q4P`!umzGf2CLppPTO)lLDQdkO+mMm9Cm_gV_~Ucjc|*`~ z)7rTe1ODg#chCPHS;uv!9L{y|nP)TNEs~I?lB3_lpH_+6h)xe@b>WU5d(#C(qp; zf9D2D#CIGzFXatl z#m|02Vn?keRrrHmzVF%R8L`huA}gCxQcL_!Za=}gX%FYypO!z72Kh2>p=@ks(d6Jz zZ#irY`FL31xtARir!2JA6T}D&DrhfQX?rKFsae8e`uRJddHofGp(IC(k^0TIs-e-4 z_4-dfD2PeFN7-vu_36HEU%)gbzRIR&2Nz#yMzY~3D(4ev657aX-r@sLICH)aTvGpv z?l86z&iq+XVQA@~JPqN5hQAg1B>}PmDshuzdmS;-T2)uSYtaDf=^H6^qd|6-`0HcI z^T}tJ!g#fTeY?BNuZ2Ap@CkzZMpG*fK?+7cG`kBWwh58IVXw-Bo4S-bhm357^pD=^+IGf#fFzbq}EY`&>rvV|Q+8%EM=xhq7 zVm_b(@#I~W>e+*M{~QoYyf{Na>)Tn3szu`ZG~ zDdU+v!ULQC*egzcHP(!F`zb*jVgT%6_zP{da?)EN3Pg7!32HU&r}#=X?jDUc%dri! zK=*-G+iK0i(o!H$NomqV&-K1)b4vl$kW6h@G0$YyA(ofG`Lx zJWMWk0WM1^$cpKG^0PE8OgjJj56eAqEMmPc_`$^vmUiVWk_qGtQ(F_|#9TpY(U!DJYjsr1?JDCy{I z1OP?lQYjE-l(UYJc}N)vy>!YOI{>mE`@O+7yJ*zt*z~CWn)kSh@1$6hY5k`H_vNn6 z$Bp9sNo`7_mzIcTPq^?{Qrj+x$5c{`!OK4HOalsTs4q?fKMGp}TYVdqsjj)i{`Yry zVTr622%6Ntg+9Ka(u$jVZO|6>kpM$bX(l~8(>R9NLgrPF%NB^8k6?7J9K6k`oRmMl z?`O(SV67i_6R#Qd!WbsY!zdq;CXQM^CzQ_y%R6&L_%!F4p3RhLVZkQh#HI|BPDcAq z2#ezr*Q9u_0&Os>mct$jip2RX)Xz#oR7NZw-IVXT&?3FiGBQX?V}g zyk>JLf!2brxhvjcKuJTTN< z=?nZ20Y2kJhe$xRfnDXvwZREzj51>|#!=SC?k4{OyN}+tsG9%Ia;IneY1J3%YJpDPMA_})+MJeLRT-u&%<-=X|v zdCOs@aDpOi)#k~|vP2hW1t3;z+QzJgoq{-R zw#8&cp@sEL?Q}G(2+Sg+R3@Z9Yu`YV()*Tmx3E`p$5|3HYQwfgXdV=zi&;EH16v>A zZwDp*{1!@~etE`(DagE7{@KWcUvuRKpdo^l3gG_7beUf-ZKtq(Gm}xSJ`o}7aJgp3 zfm1kbui{Pk-R*ngZHJ~3c650vltG0@fATKNWf{yK6Bh+LgG#~m%9S-g@foTa#@IB& zkrOIS9i;fG6N=Cn(?)+&nqq$a6R8=^B^w@QI_Gv|Z?8of8}>I6A6bQ#_j{VU()5^n zAqEz8om~nDMDDU3+xqM4{hNQKzl8_fz%faMZ<2MBr_cXpRjJhWHMO-bO})j|k1P-0`RS0v_V&zG?O^=p8FlBok%@p&{4jUAfq}c=18X z>CnjOXv;b0bz~106N|3mY~gMy+O~)fMk0d=U^$KX{T11p)THzWPG9s4%A1UA$Jzir zmx~U$*h*|YTD65V$WfV{qlEXj***f6aYJ(fyTHM8qbmfe`Kt4UVu_xVj(d$Pq1Lfk zI7YXQ{pTe)J$_m zUds-hg8O_8D=^si1(8ksq2NFUDGAoaDt)ApO0lx%}PZ@v#m!&xlCgq@UpU1SlUf}C+3`IlIKYK#tQpQ(R{#9K->H63)QxtPkib~ zOV%pLTu%rZER|cMpHN?I#l|eWzV{$7c=P`Qvp`J0mf2aQfS?Egngr86V0Heyv*Frh zd0&Vj%jyKp7mQo>nx^TQWgl2bFzb61Fen^8M)8LwY0whT^uk7aA85Tt`GCukybvNW z3aB&dJgdWs>rXvKc>WXIdSFPLZS&bPFR=gMVfHO8Vsv10Ym>q1es11B;MDmuoc-iS zS-Ai8Ohcsi@_psV1 zVcND_zIutSnX$02z;G~Nc~QohY;0cr_;faX_qmH_Kb)LBJ-v1%9K7N9tqY@tuUlRi zzGHc5|A7D^1!{L``W|aE3%cNSuX_Vef95lP&#tV#`#nGVi|76%_1B-~4o-aACJ)ULfbr0H-uYO(QwE=ZJ^ zN@)*yubiM>jSrMLYOcu9DU|_Ggc$Zv`98$Cm=mEHrHC&xiZ@qz~;j4N7UIO^ec+!%IW1?M|7r65qDqgbv+l zT9yYDJ|@<8#&mUw(}MK0t!Ee6tah4?Y14?ION;ik^TLSC^OIwOfisdgLt@+*YNv3v z;L7%dJ}Ru%jGLCq8l1IEXFD|QRO0OVj=l@{orVMVJjDJ_f09WXxaZK}#Aub3CB5$ zca}+z1|!BqRh7h;c=7oc2|>QAmDOc7wssirY@>}~w+k$Eo{ei8&^4&CCc2UyO<9(# zE-&Ggr1C6R4y<9P@fZb5gOa8f8BOIZgTgTFrNH(f?s)->(v()7!)X^-s4aD2xwbvS zCs-L2^dU0qIx6Q_svWyckB`C#TC3^3+-HR~OqyO$Nu{X^!$MiGHmtZlnXx_V`JvzZ zBVK*W5e_a5`K1qhf~PL;&=wVgUNP&utTzbiYP7I~QZywdBrZ*Mcwu9ggTs=wQOT%~ z84iE=X~4FP8q%EGku%(}qJpddx)f&dpQg{2LOb6dMo zI4Z@Y^@J3-X?cOgg(0V|Z*XnWv04er-FT1Fpqf@1w4`uaQ1Wr_>3v{jP-YoL++$&z z2z`)s)CXxKl!E;W6@_!`jA!^9qZ%?}pp?QHMdt&h(>!}=gK68bKJ)zHi3>b+{yKdh zQArc}o_h|jaPJKVdEbX0=X-zkH+bV)zY1sUo=l{)8lB}n^!Mal`xG`y1SP>=<`G_z=#D1y!OqHKV#<)`@w#50S3(xYFXBWiso;1Y1a4Cb^JS zM$_~HtVogV1+;JlpMLDaOlJ-EJp5Xe1|Nkzp0mF`r`E*mRZ~hc={l5BXd}TDT`w%k zsG7?~g~2(vIKU^xtnElK5MmPlkA@h9-PRe{>b#7nX?*6-l!6pxwo6sw^Xpr!_P(!_ z8|;{1VNg;{H`#vSX^yN^%w`j|#|>})=5OQ8Z~jt7qeZ&5;S*1MjDPprzd=zLZaloi z?)ev(UA_T#@K(I{V)a9b;TLFQWZZgmW)0`y!nhAOs~DEz^V8!^zT_((g$&$n?`&hV z=GL2U1E4I1OlP}S&YXVXd+)jD!GH6gD2vvC$A9uCf8HvnG%$Ms9kEiViT9(d%9uxD>lXkAbh zQ0=R^eC_h|x#vFfoo{&Em;Ky-{QE!54_^X)=k0&x?eG5TulUNJeDslr_TO;$CP5Zs zL>ae-1X^40EnoI}zVF}sF2!h>vg;WY1)9jr%L8q-#;HVY6l()9L;5Jjt5IR7jml_| zAb5QOlRzi=cVQi!k2oW=v`=Y|daiP!K;ZveSN$xT!qwShF&z+75Yo&phb)J;OlN8cVwCK2fl9Z%DCCGp3<+EwCCP^#B+4WtX`^{fu zw6@0UzvgWmDr}DHR6^@&u+EaE2^|uW#%#dVM5Eb=iX-!G(Nu#0NhzwqkjZ$$ul@ROtLbE-+D=k#j8W>+rK=cMptWH(k)Q=_ELA<^ zXMgrztKnck-*+jdMDRgPn@(+BUq|OGdVsPlNlA15{3U+sr~Vb!uCFVFNW!|V<@wX+ zDT-3it+`V$CHl_uPk-dcRap6U(aP-@oqz>amZ1g4QR==hvFDEYx&&8*2>H$&9}1Nk&sUK@5N4XMdi)Yw;1K zl$Kaq0z2awRbA6%!+i`MWgU+_{uEAYnzkkQfGZqjCBxlPN_5j*?m4(7&voI5uAm%_ zD5?Qn--|s`iDo{;$Rs2do!*oEw4L8WN@MKleWc0hFU}f5N)%eLIxMKH;rjM2*}5Xp zgjNeX=p@Q_adx;rV7%C@!URm7lt?mm#%KpGz~{qmpFOh6q967t_CmHZj2&m@ewUL#lUISXMr|ER;q%g z?fKQ;`w+)&ILssW-_3>1F-AkJrRnLBs7(`~^HM-{Au;oaaouYAJ)U5Hf95F1Yjogn)NL)-Z@2jNAo znGy?i$!AVq;_CTx+;IF3@q{2i$(#}GQ)1c&eAn{uEo*$m{l~bnHRiV-{|v9W<7WQo zx$|u8%osV#UwY#!DKwmV_8A^LxWJq5zL{Tt`bE5Q6h=!E7Za*bSfemm+inr`zX^%T zN&=2jISnm|jOoa+yU?Q%vspt*68~CS0SwxvM{8)k+}EYkbUr{Sdi%oay}cxoGUE|4 zLa!*S6&X;J&$Ew)>sw>C8qe~uAZb9Qy-3W)&&|35N;w6k(Ttm(5EITASr;-JfL7>~ z*uOaB%!@Db)Z>ry@SDF3>xw;qOe>X{Yx(_{*FpJpoqagMXjf%H<%A9FGjpTz1KNi` zWrQ87jb?o26ayQmssWcST<3p(=Rf4Z`ya^*ZNwE7U-HJc650vB`YXT0aA}!kv&qi& z^VlQD#O#g$f#TH=ugFp%%uzz*Q>7Bg*22mnwSk@SgxmKo^U$5QF&Zt=dr#L)GV5$` zwqiOPzi{&GXW#PRJ+FE3zf>E&;~n2~{vGf5p07P~_PO`pbmJXg5<-JgMm!mSH5G-1 zqx%=W=?8xF2mZHr{`GghYzY25j+YyNFMy-22HPZyu?4~JNDz$~ptZ(m$Ik9X^Vo+! z{59YBjep_y|4Zk2_s_ih*9Ya`xx4PT^A85MEgcN8BPv0UQfMSgTqRy}?{SVTeUKM@ zkCu>h7K)N_M%A@S%z_wxo4*`%AbiF3(J+j|P5&`Q(zAezpU(-<aXlWi0jiWVoFRIRG9p|8Q*vvjOKCpi%5rzPRLbCU}Jk-bJ%~fkHdT50G zkfl?RCcpphf1lKSZaSL6R70#QneA?4UBS-o4n`}^tY76_pZQM=ShO`oS<+1> zMBfu*plxQPl=yeQ{+^dkJU_}sN@oZ`P$Qye{mKPJQ-i^&gzy)pAc|Syl)V z0y^2*1{CL>-vC=sRs|=YeuBZ`3d%YrJ3E;CJ0w`YbP+}3{Q4Enzi{HE%c*P5Vd;DM zoOUf2^3_wbooZcMeEI?^(YTSX^B}M~^OQ zu3eeYPbZk1RX=B(cDA(trd&4 z+tYSy6!p;N<~dOp@^_;Y&T3Ywg4ynvot+s6S68u_=I?xD->BMq=Bv_SaK!w+7fL73 zE>d_|t!eX2s>&7Ak_^g1so5Mi*ug;98zTSH+up)T0l)k4Px0`*cXRxP!~D?up8!OP zxI8Fuc^FaY%-*xLI<)k;`0agUWl&QW1zU|rsWJE6a~C(=dW>N$W>wWp`Nmh>&5Z~4 zu`_9S!#&6Nz_Vxh$hmc_m2{mss;On>Fk>GnoW?m#(|c43y!MfYuskT3 zO+9xU*-z64rfti&efg_#*72cJ7b%JYXCfatagKABFEc!Fguna0{B0gPaaz_ZD+O)o zB;jaO2(z?4iP9uSSuaP064qEHnm(e*F|E$<=p(P7X+2gYLX>p3(&qKl8Wsze(Rh^y z0}5EQP!;$PnfX9r?ye}tHNny%whpMHwU6{(5Qo5#SI1Kc4gDgO?kCFNi~%(zjjKcG?A+$tKsYp2fO~<;4X) z_Qc2j@qexOpC3Q{<3Ih(@!O97xm#|&_4oI!>^CVTQuM^wqfJQ&o}w6X#|;O0_S8D7 zqh%^Xr4%zS(^+Fu6iyQ}y{+bx38T=p)@Y&1mB@F*7$>NNE3D`rv-mhBm<2%> zWgu48^IOq4rfif_TF{!(WYi(+jZ;drAyQePl~YV~F*1|YPqgPMff6R8&kctnQJOpn zHb%OB$4aw#!zg7Swb z|AstICYzjl@3S5|lfzmuYkQnd9JuXvMh?-;_a1BAUKFEI3KasrozcxE*uu%QOwpq= zFbP`}95{A2{pJtiPdXYqWx{Z7GTh(;94961Af1I$^6&dl7xkh*@7NLl^QDD)}V3 zTqu=Bi%B$*8}CG?48Qd&zr^Kh>-^d8`fh5;NyI2cX$%L412$$eHfJ4emXp~08~}Sr zYaeATn48!oWhOD{AZW|cBS%m~oCGfTa(IC%Y9|R;2@=oF| zOZU=UBZ*VFF|mf)83s<%YR%Eg(Z|HN3)If==v~LSc;zY^+grTimczW}j+=P=+%y~g_Z|)(zmwHrN#A=^QWz`iW@$x>J!f1@7L(gt{LeG~_jLC$<;Fz*?Tlhr z7<39eaMx|zb;oT4?-^w#bN>9LC^8%$6V^K3_tXmvo#N!hYrOi78`;0Kz%(R^vY_cY ze&@*(>{}eMd*w3Mw|Bu6SXb^DWmAOGfzp~T!l<^{50Nlt{<`vg7vzu$BXN@&WI$Jz zs6~ZLTh_uV&%Ah5lv1=_5`vtS&opLln4fF8l*ndKBA03QW-35RirOlctAR8TUgA`J z_Cm!VGBBk?$Di`L(0Y;TmB@g%E(GzRWo>^OBD1FD&O2{s|4p}0}`m;e0nec$zc=f3*Ozw%uN){gw01o+@_Mv)Ld z$6z?*$kCf0;N=G3^EzH`0KNbYqqUkB4GN7i72DgJXk*#jy4L-pANt{+`Fzgz{eS!W zKk&tGeEmOv-J=J-T`2|HVDthnm05~c-+KqYd;Sw7D;wJ|BjR056j}^>b7NmhiO@ET z>XJz-vXnkaLV;HE&>OvHG&EMzdyiAl0NrEPnR+G;({OpXO7=?3vYV!*8+)8J@rX3@OC{xD`9%n+ytA^Ugx;?-uqczJ_xidFNje; zcrP2TB3J%tPYShf-+uNVyc>X5+9aC1c9`N^m^EvG^~I^ zC7d;MUE-;;m-+BBV>YKPH!sx;78a%OK_V8nn_i6arA#%A0j!o(Af4ai+$bv20L@Mx znKdE}k*U#|Z4bZtp(i+YQ%xf#gUh!MF|N)j?q)&*S%^dYi1s#zXE?*n~K zoKa!#cG^R`$+y}((Pv)d&jA%h_8-O1X)+^h&w6U7S+1x_z7q|-%|MPeifJGA z;+TDmwDTcq8GR2a;iJm(QrU~jOe7&+tZ-U!<=PdjwNx4Gxq9`=d-)R_v)%E}we9$C8SBin zY0-I2R$X@juCV|1=*jHvnG%hq5}W=@cpT6wYwy(2cml^6`&<;^O<>`@Ykk z?>RsH$tQp0zPs=Hw#Cu1ZQE^9?9n-H60=BMI%Zuw=RX z_#L)SKFybW>vuD%%1ndj%`3gsR%j(j2W=2NWtyYhyyOp%DWZ~gp;e-=R)&EE8M$sU zI$3CFeIltyio!f7B?D7bhAZ`a*g!_Z$Ob{JguYBs5cw|3i22o8bkR-kDXpPPFHLVv znU?RoP@W`_JoG_KW4+8clBOX^#<4=Y0@i4T&g>znR@_{|oES~%#F#v9mO>uXV{;0I zQF8tm5>4CC_JKZtGlIPIL1r!(4c?1s*?SKtLOUh)9a>v6`p z%R-4GnF^)nkGu@SN%ZPNhqci(sDqLwM6R%TEXqmt#N1yW3`U%E)!v~z_;qu<>m`i2z8C~cWewpm!&N4>Bt!?pTARfD#N3v6#~0#o{C%4EFD!r~&srBxK7v&I-I=O6~gJG*#4W&P?IMguT*#DTT_>_2jp zYA^(2Xu6DOCNYI?UO3HkvI}XG(6{v6jM3@}3rkBFSBMNQPq`%}u3fswblMuKYnXO{K`GyNLK11LmO)fD zOIgdW&GsPVy5l_k4@memeZ?ZfZ@X-@z`Rw(J^lgLk9S zPB*B^5)(aL*U@_!*f;BY+WdJ=rVUMq#Mon^c#8Bq58W7AEeLX}Oeh#cNnSekX0)(f46bN;WSt=ek--4CepdG6{i z%E|C6mD#SC`(C8HR8ikbOp)FB>CSnFd7*woIOePEtdfzCip zeorx0_j}5|YtonPJK)O!LlS4!oHxLt3mW=sQ06o4>)KyYFMTvWAU4 z)*3f8QF5qXDzYE)U%QN=}}5j*mX} z35=`7^RcuHI!jf(04tirLR}Gj&+q-pFL3DiT^zgrLE2e^G2nFC17zy5$kC*c@pR1Y z&L&HXi;RXtLTuUCT0isoRWowD=RLpu>@Bz4_`>4S+U;5=3M2bq+cx-iMqwEINzVJH z`FObj_yRbTsZxkrIj>tf`u+RXP*_f%J+}_{&-a{v?XP|Jv)}NxKmSQkk7`qaHl)yH z#I&ct=9eY-8yp4KgjcI_wh!);t!G$bWS z9wI@Zy-@pk;kQnvL7Gen$0QOZpJb*%X*IEQdq%@KJv;S*+T>y*1%{QyYE9FL55i;w zwsdCCe5{>Fkc^g%#^w?AF4MQE_c$%O-i5j%A?DwdM0!*hVM_+11r|pOgcxc27F!j} zcD6_fZo2a>HZEPEyxP!pQ&RGD&6v@!#tmwM8;L~4_oS4EsJV*R?$Y-?5*<6w}Qx5V_v5Ilmqk&On(bW(;7@?F5HELQfMo=TmOxuh}NnR(0Ud+69 zh#f7^P8(v^(zaTL*_kRgIS!>GeeY>zGjus%urwmH9n;B_w(Vt#sx3fEib&gRP}M^! z8z@Fg)C&ucpj+P*)=1CiKa=G_hNjuYT7xSJR9T~on*QolQubjG0>1aS!V#mV@1~N$ zZVaXxu(-CL?X4Y}*;w-Yvp!ai1O$`{ka`9Siwu`m2r;sA<*IlgTz+0cpzkI~Gp1>q z9j2{kq6+HK3Lkv_5+C}f|AP94ll|MmVobj#@pLm=sgo3 z8I2YwhavHW(5@upVNHe6R7O+v8YWX_`yAulEjG8dMAp`OVa=Lt-tm@K zQ}$yD9a&gh;*U>W<#$e8Lc5_19?w3e(n_LC6=uBswfC`VJ&Pq^EB@8*e3-N6&tXE# zM^0DVbo2 zJd`r4k-U$()H;>Upjrd1V(41fmr@KtNrR-=8Sg076s%vnLVx`VgV1vB>^YW?-zltu zh7eVrunfj3Vn~9F>v@eRoq+=cnEUU!n;-j? z-)3Xx>5*Us4JacFtIT+r8=!@?2vX9^wP;IH!VW8vM4ZNXV z+{qItA2@jDJ*Xg!Lfc2WDEo^^@?=^iX<~C=M=4=@tcGbXCA-V{|9wnEf;7ll8l=`o z`jn0CO2D<0Wu#nWFI|xeChaRO6 zmygfmc)0=i0yuQ+jgR2H$O8Jl#km5bE#t}Nc~s1(ER`A;mr8ku#dkdtwq~L@|#g%Y(PHVq`RZ_7o&! zvyMRJ3`h4ZU}Mkr>CbTO!Z}bv&(`}7bLjY;q@`8PukXmj$2=S>@{-g>P+(bD?dNPH z0F{}Wr9@vjUlL{v(q?B*iAutv~Q6tiC9>PjQUxz>haAX9n! z5UC5hSKx=7Dk0Y?&5BHm6ttX__9EL*P&kRt)LP7wF^S$XCaAR-H(T#T*Bv5CYYJB| zX=n7d6eF3@EFCyR9XE--W4dz<F3<-0zNecsD6R2rMZ`_5~;s zGP|JbJS$5h4jwU* zQxxc43ZNJwZ98RW;{s;wMjm zIDGUdPe1Wl$|E-t8Y%i_Q%RzVvsN_oK^iD+G(IFQzi@$RaP)mAsXhs?d75(y1mA;N zMY|ccs+mkC(uA0TCMrTusJ*tZ%L0 z1_K~+pf1=^5L9NOGSb<3Nwd;O>}cBEWU8Qc;9h( z`&RzX_x%Rji#KrS=37`>Sw{Jezx54oX6NiFPM$l<*M8+!pj6*eDpca>wQ>mnYj6h)>yOVJu!Qw)lQdG(sP4FQpqZv;o1RqsZ6jZ}O z(psw+Jkz$LEF6QS#k4S}Q|cOJwN|sV&Q|D9k*uwjLLbP;{!8FP#y6zK%1~m5_m^q=Kgjp?}&MYo_62>kM>gu!KLo4wf1!M8r@Y{d%VLtT153;sU5YgOz z-~GJptG}F6C!gW_|H1!(?%ULMol-@`pMU!|abS6o&p!L4FkLan4r_ziL-pm_v{nRO zny{|4Cix(~5tSzuD`{}L5SX>HpXi)2mwcdChN$4C8;^4Q6|dmTr=CP<&C;>ENPVB# zF-aeC<|SEFObMR^h{;5X43$J-waC?c@AsN6g+%E_rSX#n6C-jpIUECN+$0QQUi@ct zJc;B~Y59y(OnH`x7m#cIeP`cH0)lUO_00!)`uWq`vww-#|LyPPL(gAfHk)DoANJle z+OnfO*L|vHTyf`|I!c`tTM`IKB!LhDWBWSdYx~$9PB>?{_!w-TV;>vr3&uGdC%_St zkq`(4ghHzox+S$b$K7eCwf9OhRn`4bwRYn>&KZXDi!rSEtGlJW_S$pLRaM{jz3=mS zHqF>zu+o2l?|BGqG0fG`an23Q(pWh`wLZYo;v(;U*Dv$;e|t4McJ86E+TiJ@_u&C! zle4TeniON(8J?KoLNl>G6 zW;SKgSb2_g4EavCuzmq)O?cY$#?MYS?PN5{Smc^gR!ZP|l9B!jo#QWZ`mqP-oIilC^ypM ziGnC~^(H$;q<}q%~}(d13kF zNrsdmLEJ}{YXO~L)q@G7wXpHWliWGrj_l~PEX_s~@BCOO1v;aTAmmZ$cq-er0 zqEZ{d7>~YzVFZSx-L(kRD8fkJCW%Hq3o8p2r9B#||D+wZFgqAF4dX2%9-uC3C^5~7Ve$l^M!Bx9`BM@JQQbZ@NYzHl^=URTs$ zyMw-fuF?z+4KY}aND7UJYt*Y1iXul91zM@~pekt!cc|&Qi?1w7W*6H z1%W6<0YXU8SY4yrX`{7aWv%1ng*G^iJVR)U8!l8qCrRbx+y<`QeKkd)XcT?cmqX8* z<2v>RXDI&ariWNR+#9Fi(FQ7!PpuTwN)nR7YUw@CK^NTM)M)!PMWG43-jUmyg9Fdr z-@x?NEW4UZKcJgrJo)T%tTvWNmO98VHpkCh5_`69=jh2ZEHs)721-;*A%{<$0}Xx< z(#;gH?qY-wVTiz?D~(1A0Y-o_$Uvf;*fLa<~e`iA~Tz|5S3z-Wn{YFhr%G&)8rA>gMeKz&{`9D9=XwW|1j1k*7L@A zqSyV0Olw5aVJ=ooTs6w~-Sui7J#>P7$L1;g*gh}4uD>>@!g>|}n%yqdQpCWP?JPal zM5GJ!4-QhRRasnI;nSb~3{pUUHK0@*WNEccqdv>wDumGl0*q&iODR1JRuXH{ z6pW?o+56(c%AAxqFEnXkSZ=JKwWhCHp_`^ipcMCsf#IPoz`?KmBxA1+fAYh_Ldffz zttP0PJkRm{j4&zz&~E=9_e%fMUN08_-vF18flS+p{WB6HtkKi=VegGMZ5o^&yMFoH zrLW614-iJdCIIP0_Au6Kk0Us{)Iei9{0i`dSs(kxfk*1P_I4C+JKA8epowx?VkyY9 zadfw7CDGR1&M^HvkXnGK z)iqAv`wy%wFR}UcZ{@N!r{_tF4Rys;D0{|BgTi7- z3l}>trLdF;r(xB`9p2L%PhK%oOM0oD7F`$09<9ZWx9X|GtA7S&xNxUfJ_?ZQQYM&#b zB%w1#zrZWA@TwqdGG-$alq8j7^lx)M3(#L(WZ(#2NYSF5XQq)>T4W7dYBW( zk3$%(Z{EffNZ*4ZBVAj=j|I~6iK3WpyFqhp1q|ffu6;iJ5R^@q?koAosadit0keiy z8ebaT_uIe9KmXgkeB!=G?B-qMRLdpeIAZ1e8H|}ks}xW8_JHCEHckxD80hE4Gnep; zqSNV6o}ID=K&?m%gEAIh3S7~UyXQv$p@dG7Fj1>9w`Bv5Jp34sefeJEvX#yXFLaYC zK^TPup0Jo)jmr=bL_uJg`+i{Wy`zq3ZP$w+uqe>n2y~$=#l(|@kxwZM>@zO|0^dhC z$zK=+nAH}G3rqaUFa8p7wU0+$Ji$P<%;V2IhZh70;gMx+!mx}V#CS##`aXei2;aab zRf=k*%p?2vF*i47Jl|r1j-5Hqqfb36_CNk4L8*eyQaUbC7Olu_O0_N0wYKKlEMG5% zw6eVyjh!-46r!gf6P~}`okuC0gVkx$v1&y3nE?>KZx6U>le-4$G?y-M_{1d!uHTIG zJyeoAcaGESV-Np5N|VHOd~KuOem1mbyuU(`rkp)>nxQe95S{co<&MH*yV4Ni@=@%m z)8Z`G&8My;a8n4OtQk7X3$kv9O&ezT?t5;h);}zM`Pbe@!@NW1zDyXy~%gHF8pZSR&|C#^#E5G*LU(aiPW&c;Uc+z`~F}7PLTp(8OI(K=QZeb{SK51sVhrZK6 z_UJl2>5MN0nHK9hc;9VI%I$H5Go5#kQCa=YNTMKufn-~U*^)6Kg;Y; znM$ofmT87ZM;RU-VYRWsvBNJiFfhQ5T9rdjeUW2cz~OesAVK%*Qd+x|Sp^s)p5zVFe=bIYsl zjhT(zAeHYUJPFbo+^U|>VwNDq|qcvPNi05_nzGZQ9p(zo)@szSmqr+^V3|jYX{%= zeLsfm8^-fJ8)%iZ*t&TNAu0&JLKtUMO95|v^Q(E!Z~PWJu6-5fmzsECgcO>jvB+(2 zyo<4kjaS=t36hKENub>g_~ zsuhr}EQ9Bvk(ex_Xg5$Lp^e1k9p+D;!7Eh&0V+pn#jf2uIdl3f z?M?!sj29S|msff3d;f=d*RQ@)JhtyS&RkvtAxPS7)|OV#d2Z!@L1>GtqKz*yE-tOm z?56fqR%BE?!_YuK&32Q*6^0tQt{d-3I(l+~IPi!Be6RsbeMBX%iOqkFCY8pF&^8$kL_1)Aq-0_tgM*nnOPB@J;YET2_+fAVL%%VW_uiBDfpi5x&yQp$d%iP#cUG-}C)!9O*+!z5YBn1&e*3Ztc_R%75#nHXGyUW9~Pj zjmE=DBMSo$-2X*JtM=JkTWzqg)+S53oIZA(r)n`-qIu-OhX|@eys(sT^2}*Ufrk-p z;-U>gt96aL5ccQ8fRR4AQXtGa|6XhDP}7ont;+P~%^W^X4$lJ2PY36Bv+d0UDr@#nM1JJpAT>iEh}9OgrMUJ0V!~Yc;OE5 zkYqVquHHuf^c-V@eHaI~C>-&v&^@hxZ-ine%L0&2rmCGJNJ?*g%8ckuJFIMVG!FRA z8@5yS47)ea@rg&C;OQ5S@PEJcE(Ys$URr4K$%Ciu=S=iIYIe`bjg@#ArAU*6a{n;Z z>s~>zyg+mQBw4dzf1lDL9+{>xHbrf4kW3lc-2|aE$`xof+|2HS7@ND38+!(@50A!3 z+YlZuxoahZkn>NaGs~1ea6&keN0cyicK3fzxk7&{nx#3z584DeXZx2 zhaP?Cl>_y`|0m7b7B8+9eborhE0N}!c1K}^mwv6U_wr@0mkWSzfUA=#ktE73&;?mu z*v_`sC5~#m?Vh)M$Ae#b=#L+`?}10Y*4Ny&Y3qkdQ6_hm;wZA+ z3v&e^W;KxZLoS6N%Qc?3LYFX3%3|D@G;mV@Wh`mOm$pmLqY8nYFdzkSDWYgLxbVaS z)G9IMdLPwVjW^$YH+Q|^jf{_tljS*I_~I9M|NDLiDJ56Wj&kC~FVot#n@W9@<+Zlm zpp0H`vMD=724OpoB`N4+iXL7%RR$>x)j%@US0Pg+>Y-fcN-Jfs!flJg6Bv@LKzh=R zXl;kHn`=iX(o`bPZ4L%iD985h-5*0Ivz-}X6h_#o0NP-L?baxzD3nd4lx{+R>5cs@ zdpdO+q;@DaAw7(?a;HLB_P1AxZR)EFAM36x@VZ;CXL4$cwbh33Jdf7u61vDZb^N%A z10im{`8u9_;#s@lryWYw5_@ml1K}v;fdP@GPoj-xu)oGv9=xB?sg1Y+HhvJ1tDM=n zNqkRHiX=uW@?0^uahA{D`#D~9`yIr6{oo1wASTIEM#ly@cm6Wh-Z)6?$28ZLm>H?@ z#e47NE%&^UxlOa2xx7ZDzmM+f3PaPg)cX2SMGNV9G}gLo-7vwC7Z39MfoHgJ@AZ7@ zb6;X;WQgwCD${#*vuX1N9)0L@?A^PEEbB5fP+@iP9AEhCC%E&@SM$-2-N)qYG_A%8 zrCOP_qD~n2K!WFa zcQb^L)W^n%!T>rA-uT*A@W+4n0==1z(Ft+nbNJ8;Jovef^G)A!Hy`}F&l2h!(`hn3 z(Z_1TCk#9gAp!+5!~|8->MYr(S^DHMVyJ5UGeY>pfh6`lo0yHoGa6%yZkuE*8LXCB zU0!1O(s?#c*Acp~G^$dGQnfk3&%pYz6U2oaZ;*Y3&j>pSHcx+5mRtQTjG9x{Z*WKRbYIduv|i5h@uD? zl_*y#2+w!-v!@w14pZ!{`-E&gVKV{p!UkITj!WO{CX8*^z-{0D-Hi2B=sFDMdXZr4 zCs?}1iCfMs#l|iC%Gk^kVXnxHqCk=saPaJ9Zh7^ccty(J{QbWWMj zIxxbM&mLmmzWr23rWl&tMA|yd_Uo>vs*KCXhN{sYZ7$2yjly-6DvI%CMOC)-h9_ROpK54vp@TDR0oF`XeC^F?g?gI_sw+tb*q?N_^=CKuftez zdZ5^|8(nUo7v-+p7}vv&^Lq%kr0D74ZR^XEmg!x%u7)uhj98y|_`Ws$+651Uuo9xS zqX6{`$Gto6x!obx;7Pk!D{aT9XoEJ&V(75u>0IN|DeZbzC_@ly5^?$BJTtRXraCb$Hg4X)>iijIcW&Ui z8*U^|Q-ZKWk*ADQg}Lpfy<+q9AZaA2j?XZ?eJ4WazMwk&GZ2w!BZEU$6srDLYsX^Okv{AM25{~{ZA z?&RF_&+_(fe;cp9WfytUV70NRWl)s^{r%Lc5m~azTi@~~KL5l4wqAcT%NOQpoOppE z>rjdS-2xd>3GS>gEX7R76XL>Nt;bnRNDEC$%<|NohzcM|+6%T`ZMW2|(iH>s(VON>p9 zbK=q(!gmk=aU~cr^rZ`FR1}59%L;62b}xn19{2#QsMo3t^wr67`@LAyJ!4|k~-7N}>O|8}YSY5ctKq+8# zWrX%7N+X`6i)Y_Df?_mVMq&mfRj?t$u$9nYV6ThDj}q#ohCFgg%XhGhA0f! zcEfc%`Pi4yN^}0qDY9G>MIl+Ig{s$_E?ptBll*#F0?Y9I&y%w-+3D+7FKB}A3yL>4%;o<p>|J#d?D;$@6u5spm)dzGs8fih|W{f#=!0mq~4}9c*^*WC~ z{rHZp8@7CKaA4?l+T_;qWHeIxU!@85xbN8`oa-9mSlB~@bBKA8^@DEiu$_@Ftr^o8 zY_66apZZQ7lN2_2Q)0EasoQiy-*X)#Kr1|9(P`P@1xlX4sDjbSN$z>`Js1>96&Ryw zrA^9lh3l`qnODB*HXeWcN$T|)7gx?<(hflokmb2uOmU$ut{~}kLyX(>0yj#JgbfDr zq}@=Jw1=YHK-?Sm1BJtMYV2Yc0=~R5%ngkp?R7AvMTH7!i9tzjlaP&oN+9VkhX_wn z_5>^K#2PMzz;`CC-sUHSjgHSUiYilK=KHtxKZrBaF6{+Ry$LE5cl zJlTgZiW_d&CBFBEzMuN&Mh+dnM1QT!%-k&Pb{pdrY}vAfAR0hQP15Z$I#}oIX~Ub| z@EW%7*iC9AQ!|?gsx_LI&aq?1E;h{!v9xf4djB|{#CRgt+pn6FS8d*aLQtESr93)? ze{q2wS6@ZazAVrgemG7T738^LZfZhYbL}-e{tx$28XBWIGDQ&_=BAr&Hn+d}Hqlx; z&kIj~(Ok9bRR|fV> zqYH|xO}P|t=bPTj{!FMwZxe- z^W3!edam8GgXQH0MWM*ElxC~V>C^MHS{=qlht~s}jvP6`)YK%yLxa5d!XeTuXZP-H zL~#TNR#qBxy9t8>eQ0AiJAV=3_0nX)RZ2!FBSUGYD7`?a$d|Np#rf5QN@(RU zg_9>rpqb<-W1B0st1r-LLOJy4=9+ez69*o(C?G2ojig|t5>gEU7TPJD{K}eHXyfqD zf^KH%JLS-RZIWyHB9FZr$9ee3ljNNy@A~DRWo&eu_y6Ia^Nt_;AzpalApiLB`*{0z zzKw6X>rVdkFaIZ5pfIJ7^J{I4usF?nsYJ8erJZY9sm+ophnB{bdLAm2Ja_aY=ayI5 zwQUPYmg5=2Qr8A{Z5k>wG&aSlv*!`gC(Al$A@GB6{kBh3N_f6cCrcTcoZ_k*Zs6$t zr2EjxE`^x*RtZJ530dQc9sAgp9F*RJF302saE)(vmzl>wGsWd7YgY3IjwUo4EV zlSL;%)movkUJN^lvCm8?4pC{BFF)}l@$dv&H_p&aQullqLNv!J$9 za-+e@>KZ$?ZF|+!#N@uW-u<2Lzi{TnKizW6Yt8|D&(HsSW#xfGhfbW|dF{@tH_ptxJ&NKV zF2&`N(ivHvQ52a?(Dgjxs6^mLTwY$}U-rF(tPferfJ=k*#g&9kPg>o&;EEZwXUGcV zm4#8bxk59|NtI%t9OL^Q(pUnHGJ@RAm_uLEP76W`ln`{fT}DSn3H=gErwCyw9t%s$ z)G8UHL*w-I^;6^-VO+;k0a=!z2+154&!RqU;$op~0fH2Ea#3hvUlK{X7zzU(0$tPsT&;YW40Zk!M=J@*W6zUO<`a`jIB+XwyzQR*Y{N_4{-OU+f5SDMsoHDpj` zWNd^-9zRI`;Jy6!-~9kzeC$Pvu#Bz_5E#MonJzw(APnd_orv31iH&Ro2VsEtw@97mLD z+<*TA{MLJZiIv6Ew40Xz#lq48cfa**)cg8*^2z;#m40-oPXF{~{`9Z@THJQaUh4hB z42*8{1erN<(#!%6 zk|eh{R|JT{N`bU3_IrU=J#D|84ni-*`HD!0D+{IRNerztO1K**1!ASuML9Bv;AcT%P}k6jL7$h z10R7QS2kxvN*i|8JLZNCajT3gHXP)j($~-D?!BK7SfsvoV}}<{4%^$=2PwIePE_y2zNh_9irx_jxyRcg*=3@ z`$lgnV!d%7ge1vrBS83)q$sGDB4STcC|Jqzbw7Zm@mV>OK@bN4=Pq96#F-29>42Gu zG4gJgG))+&RVaiy}7>}(M~cvtU)~VY^FhG zSby)Hu#;;oT_%sC5aqchmx6L&r%=k+iF8*%r<=0cYSUM%5r-bNz!fywtjo%LX%%l; zYwG<2eChBDeBrTYc-w3DVvHmR0^+zt7{)Z44HgzIGch_nIn?jHf4G0}y-SUSXSFIi zz8`GwuMf?*oepDi(mW$5)rq6ftvfzaz@?>&eCmO(2<1ie5B2|ta-x^7e}BDP0DJ>n zt#(VSB#MuH^3(jnPy7^>a+NgC(O$&jrFoL}Dih-q_`W6zN^IS-<5u9-c4t*@+rD!# z2*S}YuqdoTrQ}7%TBl2;RHn!*FW8e-7VyXSKE{#?h&>M}1SH@0MtaB~#Pd8ZU%res zxz!LGjlhnb*IH|g4vll>>^Y*yc0e-%{2(AOo<;TvXczX7Bc;T+MNB$`p6_&=B9QpP zBk%-eA97_8nw7wJoedXY6nJ<}`Jl0dKpc2<(|kSESh@*=kak4u{z_h0BbXmbFoI5+ z^Ww3SaQX z1aXW~HjX|sn!(vkEX^Nc@$v%W<2BQ1x5f5dd)T;T7dPB;EARQu_wm#V$C{TZRa!h-Os;$@^jQTT+Lc(fNHrPefcuK z_N(vWZ~yu)2%`#1i;LWT$L;*aop*8H7auYo{EL4S{iBnVheybTWOV0syz|$7lY0D4 zzUO=1PSUzawO-@Bzx(^5JT%EWfBko979P{nb7XOe+1=OkHy{0HLYn;2&;1xhp3v=d z_|TvH5kq6syyItng_lm9V`kUQtST7Ww1ua>^eKM*y}!!4-}%!tmM)lf<2>K;f4z3)BD5`^8T5D0N z)ToY6vwHRfmsWEwEjHM-r^4#eJWC6U_!7EF&gE`FwXY8&1S_je-t))*llT4P+eH*f zE}T1qCk)r$a3kOPZ9gDC``A-FeEb5V(=%K;`Vs?0m*4(x@8;h=`6(`*Jx7tY$nzG; zrss;0;UUVkDocxNl*=WCYGqDbUS_xyxoHp##v#6M4}Km{jqKmMNrEUewYWmN+aYcH zNSz_HB3FV)S~(0}V7qDv*In}+iYl|kfWRK=doX(A@;!tErAXEqj@HsU6uUp`qE{t= z5a?7<=q_EQ=^D+#rG%lun)TBtMWs@)rdv-kH8swqON(sXx``l)IC=au(^He=X~wBj zXX)>+QLU7joESrELz1Rwt*BJW7-P7+u*jL?ClE%U3oDv2!UJP7SB!xyPsuv&B;`JD zrY8)S9t!Q4`4+oqr0;(IULvdj(*+E|3*4&Sdp-44#euyi#!-R1Ffw_XxP<7G5`yWz zD(!Zg{YQ>b85pJ%M|KLE+Xh1DLgpeVC`HnyP6K}65lCqfyOBU^N#Q0%mB=RyLq7ZH zK90TkBGGKQ>4^tpnUR~wV z@){erZO3?m$DcXGg-gqfjt+6A$kAF82R;i6%iQ;+M|jgccQX)|5Lz+aS7v#&#neEJ zGnbdBg+6 z5H?^>Sv<4A<#HS2z!;YL*3-QAWH&}Y97UL-;Gh2N&luZvJ=<@31tv@EvjME9A7f~B zy9|yDv+MTPQTCwGY;osRV|?>XyLs@yVeUV0gzvw3H``_=_}9k|ka`|JaMztYdGrkb zdhjfsv0Zm91(7eP$013xK}m*mJWJWKA5~!w?C#0bKrM2(YatjY2kTNnDQux>Js9@? zkAxtqM3h1g-}CUK4Xl*HPT1G6scw3ug&+`yfw|56(fv3##-+~{POj+UN08_-vC#;(-A>+m`^|O1h2U9VQ#(UcC;$U^PIj~9pATOJCk(~ zq06`xf=an6!5aldS|k)2(jo_?5Ynb;3R6%m)sZsd3(p?pvoBpB>KnA&e(g+xt}|c| z4!H)>So5qWSRX0&w2YQ3WJx2r1|ux3Mi`6g)L1QKs(a=k`*X&DPdYG0I)9ijjCgAQ zGkocxFY&rpzX457;QN&0nBk#ep4|U9Pd@Pk(^C_ywz>rMD#{PZy7@XDGj<8VonxRsfLfH;onp-WuQdYmbo)oNY2$;so zK5}iy9PP;Wg_TIT0I#X3NiLROPrY6x5@wy}uZ(4u3v5$RDUETjZ8UU+cIGlW-Us{M z3zv-QI)`@Zp%lIspj1Y;NXhe*a=FClmTfd!ZTgau=yo%P$EI0n8Gh;)-^;-h^Gx0F zDya8!xv|DTU!B3t+h}((lIAJn`6Z$#6iPW^4ch4o3BRaDJwFdx@iaV z$Dd?n=@P!|(rI-W92w`IKlMfa^^>0#Ex(WP9a~vxcS-YtQr{2*vzx66vRFk5O|E@j zIC`4D{^!pzzm_q3{Vn7{$kO5>)pCXYtFGho5ANf?e9yNbM1jsTzWl^A?C=Hp*r&+g5<{?I0((r!YzQsv%fkI;PI-|(YvzM0|9Ws_*b z?1pXPFF)}`{_5cu7~FUj-b&LZ0_Td^*;!tE;Sj4!%dD&{(O-`!_l=U}1v{?YO*x7< z@W6id?$|;rv&MeklVo{L;K#&qXpQ^IQmZPSPnLB_J6(!S7nMl5trpd*Hj%X&WZkw) zE!MWsEK*EST+!+~gP;&tQ;M?1fiZSUCDx6c_Oc;JIYRpOYenGx)pq`^QpU~|Ri2Wk z7JW?CMfKZsYo!!vlA^SxQY|wyGR#V2jV#Z3>7}DwwRICyQ{xEWz=7wH(&i@^pqp4f zgwetpYo+A51BWQm6fZ7;R*ptvKo@qxDWPX@?@_wI5@3YqugjuLj~rucJ_klyQj;p| zn*<0qVMKtI0YdtswY-F0YvPX^a^G;^)I9q>^GUY7{;lk}dV@2O z+k0nq{LYLmY_^J!c0H=awn>l_2H^>t(Snr~b<&j4$qCB+eGFI27FjF6%_At60_Q!@ z)(9I&{2tjRQ$#_?D{s1i_R11kLv?U~$+?)3fqt&rvx~-R!#w@e)1oK}rsih3cH34i zy>#Bv;j)~`!5ZKDz2Ai&_#}lQjw0HbqS5Y9ivx!HsvJ3cf#C?EBH>$azm8J5%JSL? z`lEm#EaQ6~p)aXTjgw@yab;l&_AuG#WK^mZ-uT)(C`(N{wNQ#AO&Oe+!N1w(_>+$@ z<$3J6@p_)wx1X0*SE$ZxU}SC+eU%d3tiZU!C;+ytd4{Vd zN7ytrKqVZd(`>R~ph{mLSxz-d`V@tx8U>tLXt4iZ{*H;=H?Zl3TZl~IB)Prkw&w-0 zIW?9EWzDvl9EYeWj3gt|)X5a$!x=z8iAcoEt&x_N-c^#6ow1pZw52 z@kc-P?aYo3Bc)_+W(I^ub8VT+3yV~$8MR6m-}6YaoJ*H4(a97^(!t1pw9_J0hSB~q zl~59uD#Ss|!9&mS(N8}p+S(Qb*;?b}0^sYsUM>K>0j?m9!SiVcb$12w+7-#OaW;eif@2(h_!0PG22BTOWJ&pxzN5`R*tfb0~ByDFzXhT

z>t;No923LXk+GE06$cvO41r1;%7KUP`y_dW);XRKc%IKnw~MbM<}c0@1O;(rh!6b1 zpYi3FE;2N`g^9g)5R6Q*mZs=DXK{IzU|^iZZi@?NkCG|LbI+gRr{41+N|T$YZQcX* z0lEl8l7VT{@k64a8J>IQD`srCW;DKd{|Ej=T9^~%-@*`xY4shz!DRJh^DRF8(hsq$=zu_)++%(C}5XR~uZlbpwYFAGh)n*WFh|v94Q} zo{tc6onqyCo|VX$^`pK$+$x1uJ=`OpEecmiiSz=5l=y*d8dNG1ws7gD^i?a?i0Zz- z=Xqpl#>o?>nVFelXm|+U_qlN4A{#f(GBY#H;Uh;;g=S`U5?$!tGC&+fl* zp-1R@w9?#8M*Ut!hnre@g49u3w#|-VjG);`YLu&N)eVTjBMV5 z9|p9#1rmFBO_iq6%_s*sh3}Covo32bI$bKm<7~b86&&05B%U_h{+ioZUT$#g#7S0` zSJ=4c1{cz3LoIugabF4wEy%QX9tqs@ZtruC$Rs5sd4VSdH}1WjPzu^{y$fghjRKn~@yts{nV6hLN{_x;1u5bAlk;pGA7Os}95WMR)S`gpEW_rj8!NN( zeTHwni-934oy8saJ>fDe%#{K}8pL+-5sIXZV?BPB_pB45&ixBov;7&^`HBC zxd8YExO7l8nGuBjgB&||ig$hRFZs}a{Uru#Lv*?;_@0mF$4I|Iku+IYUcw+5A0DBb zJUt_Y+JSrOPtLaUQf8yKd(<7U>L zet^Ng8cT}{{Ll~m5PSFTWp-{O3kwT8_|U^ts#PY(M_FwrosQdnSyHGt(>yJTTap&{~nAvzilONTH< z;JJmgFqQ(*!}0m9vdFbXgT|p}@uvfLJpXQUF_>34E|Nq!~&p12JyIl8r-oDDrn%+mf%c_=SxyZ&nv2hBC zV>=L290J)82!T+N%|1XjC9r`VLh4R41cFKI#E!8O_io9SCCjQKjmlI_pEaw#^?A;R z=baJf+u?WkkRQkI7hBS3wAPxnp7&qw`?@=L;)N5eyy_O>wjLrZJu!_X#4##L5N@8T z*Tky_4ytCmCaa-qwyao>)4!c+EI~%ZwIYU_K_F4WAm6i+lNS#0=y$&*R&UCm)%4R0QQor`b2K(4u!@maX)UGF7EFjEa#)Hi4IIRZ?6d}x4{=?gp@j;T1Ri`Py~ zux8&)RN9tv{QM~OAf%AXAPkd8!fZWe-Ie=Lb8j&@G0WiKG@@gbxaK{#5`-c1wGb@=?poa5GOuA*gimbV^# zSiJcBi<~(02FFL{+5L`tXlZWdwR7W4IR&C1#Lar-T${e89GPqm*D~nt?;@&{P-a44 z+vGAHaS~!CAz_N=i=v3y!aOpQ)r~HCLfhD2VB|dddOKLQtdEh=i(D8UBaBiQfa?%O zx+u*6{VuHz6!iEdaEi68g~VQA!LN&~YD1H&*$0F}h#vo4kiYuBt` za(tY***RKTnvhCjJ2puaGc!5G@W>d;m-Vu3$2MlBrtp2AW&J&zICX|nxysOm5mv2U zK`z%o82DO-ASF>0YPnQPBei;%qLp>CqJdv&Q*Ibq&keYajY3hXg(w6zdKh3CCK=aU z+6D?GDHZ2%U67ZYPEu;lo93?a~7HIG6q#_l55E3Q{O<9k8 z#zmkAQd6gauJM$FIM(NsAq1TnmvR`>oXHTx5%qY{2dSZxDlI`ylh7OH+YDL!Rdj zouDpk)~{K`RJp2?bu9-a72^W~6pIUNxcqYRp2I>dOpUm@G8bsFk6}SM&;uwb6*CJJ zT3R|-wrwY)Cyvw5RN&;P0XA*k#L*L{F=dRf94y0F3cy_Yz9`bP2z`#E!I`FE;H91| zAq0N9y^W)YM5Nn;v;nj&bBVN+pd~knR5(ImC=^S!7w1J5|;P(Gct9N zU-|rZ`0M-L$DU0qkxJsZ8H9>)-5gTEd~t!nQ^#p&Xu`I1c7$IK5Y<`wdpcR(+mB^t z`2G_==F9*51EzePARj3`C}?eM_WzShv;Xqf+YP`^z$M}!HRBn0&25~V4fw4uKfrzO z*vGY7)&o9KAhVgBSyFZHt-7F~T^exxE#`v^g>~#n+!b#H*u4I=Xwv z*d`IMP>+ZuOS;cRj&WUMewJ<;i*g=IXa#_oB0o(b2vUvu;)cL8!A=t^t#sFzC|!&P z>JoypSo0~Y+d+9|lG6AonwwkjvN;aC_6D!MdVqY^roFWh$ICNU38=U&wC%hWs7rE6=2ZV+q(A_cnqQ)#G~LPdHVZ=?sjfi`t1rHgNwqBf)S zgi}BetJM0ah=eBf)FUkm5~(gHOcb`#O;i*oONcn_FVMw9lK#0;Is-r|jT;o{$SF*; zF4t0v8xB3CTTEWe*bZS5lSqkDi!t(=YaN7jx-&MTr%QrbnW@6HPh%B zlTw21u*c2q}M4oOtUYiObpC5#shPCRvpljkmy*{}z@sYQn#Nt0BwrJrjU z(coFk&Mr_j1Q#ZY1S-eE>>QZ_xK4&J3bp1siBMAEWV19jHRFac^VNv<_IAo?^O|)m ziuFj#Koaf6uuKEf^%xx;6Hy{C?JPM{5(YlGOpdY;dV3Vd2uqO9>UDIv8em2-7iX(v z+IomWACbfeq0=}G!^W^|Ol;!7r>(h#dc8(ldoyo6^*YAx)!^lk3sssL8rZUXH~(<# z3}1NUFCg^k$(g)=cOQ|dn6J+9hkyH3l58U@cI;-?j&{PTPpKZJ0eluHg=broDpj8N z>KAC+ypuJ1_aTxn%?2>Y+6GA!)7aWUBI}rzsT)iHVNk32L_x^W6X(c!4inS!)a!bB z=?4L#V&b|ku49uVF;N(j#0h>lme1*zPEY&{gD?zqF(ovP*fbzx zn*>3~!a|vzo-P1v%fd8GEK?Jawp_N6?!Io4I3VAUCzr|4-rlNAQ*id&h`8~_edP05 zDwP^x7-HBCjg5_592-X}$mO(rWO#I(APC52votg`=xu}nK^PGL`HX`^5y!ewD3!`o zN=2F*^H{koVGyTsMn&ZNH0HDP_4hM5IgMc$w6!)fd|_1EC5*-Cf5IXKNTEOX$OMH! ztRRX)T*o7}?Ij74loH1>kn&Q26)A;~dJ`+qM4-03$H??N4}IgSyz_$}qN}HeY8dJK zk;Q{NJa_vImkp(sn;pZ7YX77+c1!^-cD-$yu>suYBFJZc$oU+5Z{09Wdh-` zWAhpY$0j*^<^s8Tnz@S4o5Pb_cKPL+IwvKjZBr_)56zv~B!i zQDeisEHQ$_ui?2K!mtSDr*LhHOfE+d3k=I9@@sT86_|;L8Tb_4JeaAj=mZzp0O#duM_qT?53I8cXO7ux@6pm#q@tEU8;aSGNTiq(85=%5B z)6x$>$;H@r-E_oKZ%p*-wm4x_db40IN)0qO)HF3RHA(dn0*x3otaQaH1WGQ-htlWm zx+oN(O!VWF3fr`>EeF??j1?=CXX{jg2*0$zfq(oG`M%Zc{lL#cq>ay75Cv{7%Uq>S zacqu>g^;;YnYlNfCp$Z?xz7dsgfm8zGISvKaWNyC1OXKtSG2C?XO&mTpz{Qb4+ShL-TWFzDs}V$XT-(ON zp}(UEd#XXb{OSR*YRy_UwYREQPMr|-mVUa|Z-m$1%) zfk(e1TIOTctXWC#nl4@#o~Naw6;C9zwzYArwHq^$B*Uj^aw5)Nm|*z)5WX}hWLj}o zuVwqTt$KYg1SE-0O*IUnxK1t9+B z*N*LYWV0C+#WD42h0@%l*t}tl>TWNPX()hjXlV{qsaz956su~vBIf3bOZf(Vwao8* z{KG6;*3bX`+?N@doWu2UBuPRPMi{1vA0=sVCaBk{?AW-RpLzGMGGCnG)R`d;9zI2s zBv`gf5QKDgbuczQLA6@Pb!|$esy@(-GzEDvQy~ol6GCgsRXT79r6QNhVVe;pB~eL& zl2DB!l0Z-IGmcFX>xrxhgo#`tu!T{GuuXQ~{7w?vC5$6%%S=;)^?6iqZ7M;GAyn$k zR=Bn-v?{>s3rIOAwNPe!W}Yw%v4tW*F>w9@E1ELw=v}UAl?tOngRF1P zh|8{6ttvq*nz{>W>xxd030cPyN}(Du9>+%}#rFng$#^+xk)$>|&Bs1)Ei1Y@`0*Pj z$eD_*D|_%;v>fN-)Ha&aTA(Wo+x>1=HxpXp+@T*HfM{NB5+ zz;ztH`sAzRU5AhS%nh8qIL-6N&+^`zuOp5ko;Y@n=EepRVUTqlPM;s*=DnNQy?!;{ zeBvd3H0BFKvwER8JEUgHxl-(MV>!Oy<9}t9!N>zW^sE~(Ybsjv7KSATqjE8l6iI! zOX`^dTR;TVQw*A8=tf4Wl#iUQUk#D2?$I|-L5kiqwB#m96DSd+0V^t{3h5@uG)%%Y zIA)OqD3wkPwMEMBP6-;ZTJjF2)DF^(h`_VbU>LM!Ka3MBRtzmXE}3jgnK^tL2>s7?&QFs!~D$yPa?XO>rk&u1|zC7f8<3z^RW+c zVR)DqUffTAe;=Ryqfc{T^devS?qkenJFqO9D2#N0Hao$`KY9-aHH zkl2nx5cmj@VnQujo9M$B%Svz@3&A2oUq6N%Yc<*Z1?l_a4HwZMu89FodpR<0xWcaz>1f zUKFjZ&Fb{20r7`_@cV4sv_m}g)19L*F@%BBSU|=RNf=-%OHb*O2o?Iw&zF&1 z-S{ztQG{pf0@kvvbXzEv^!oKE!88Op$6~$~)9ATu+P0OdA5ilneV#21HlQ3vn1&#f zq|!~jiHM~Rd$eUjdFTw^{PRy>+lpho8Q%TwyLjxe@2Pj(dYd?W_zmiQ$Q8Tyh#x)i zI5*vJ3t#`o`?=%xTj=lYB97{6*XGS4Do?U*-6ke3j??{~>$&yDn|a_n-{P)&?&JCA z{*9)lR#vQ9%d^iu$$Q>?H~;qNci6mkIYAI{&pWQ>?hky3A3XdW-t+FeIeYd5voq7| zx#BwhiX+>?fDltbznd1F5iXidPHdvxah6Q zITj*`IW;&+XJ-etWl{A*+~#&J+jku@iV(JoWxLda5IY@k>F=S3ORjAoqlm|zeu0kF ztLg3OBnTso%1$=}QfgV1LT`qR6s%!cn!seob(ZICo_gaL=SRl4Y|S!`zVZUEzxV>% zwr*hM`t?Y^ifNdtxw(;yY(#|yS(VUYJ3`j#y5Ow`NW&C~Wh)_LDoBDbW-1JD3`g}_ zhL{Y&GhC!4sMUQQeeEq?IDDMnd+)WV>J-zHWo*Y~c;q4h4uwKDEvn8;J)xQiGLC~| z*_cAhR6_-oS{=^-Q%b_n$4WwO+rFODqhlm-$dhlLB1vMJGbZg_&0LtA0o&upPdvf0 z?oMvGVi&vCF6Xrq17vKImY#l|9bMq5Gf!d(K~Hld%^8bqD(M-REK-jpbqRs85q5#D zj6*ipfE5Sn7A6Ivp#3hs@4vkP_zzxhHvm5YmlBpN%sIAg62=-U7pMAM z)6i>6k?LK7lnj8nlwcUAD`kB!CaE_-7xtFml3eKD{n`|ZeY#e7=xM!zdO#Fg*zL>7 zcl2ThJ_#CMXjm4~c322wWE22erx?V^lK;RIdcq$Yg66DCqhV01``WyRpf14{imYXz z&;~Kmrhv4t){TltwUS!$gD|iSof!a{fD|Wb8m6(BJD?faZn`xH(ql&l_bQCk7ocxK ziXfItMkza;4oayLUM)kUlBV=1lafGcBbG{EcUVjj);~j?+-zV91Jg7$Vq7LXMRvnZT+?9u;EUXKybq0?eqi@A> zgkQ&;8RE;I|34@d@yKIO5Y(Z6*-Ex;*}}FhTkt>gS3L6STP$C*0@JV=IdhCJ{q6tY z%Dva{jLpnqOpnqlD_pjD9cNCSX1-X)a6GEzDtni8)6><(LqB?sjx`(T>+2;_ z;MXF;Fu*VqEZe~k!=*fnIF^`6OhtmLB*YTawTXi|K@if~tm$G>Dv%MvFi2!fA`Flc z*S1KK2t%3Jwn?1mLdUjD;wT}CVv-~wi4#oIAQFn8SfqQ;MsB$2rvZ5A;U97A#92Hi zkFxaN*Z-zAV_S|x6ouSy!}XY^ODzc1*}-!nm(P(O$qCI9ZzM?+4f&kfymd)sWTFKWO2!&fD1=5Z zXB)6GIqLJX$V4KO7$u-QKhKnkHPNXv#Y$?lKaRmtqh^}s(!^MYQ0XCqC7>Egtk@@t z<&vgfrh0TG6@H?_4Mlp!*l8-e&@CKc6tk?SgQlherijVrUE(+*#-QTIw6(P|K0b== zHjvF{Re};%U%7|k!W>P7Jk?r&AJhqg8pYx)re!iUF-jcA*tSJ!VFugFsUT6pGzErf z5(ITDH%Fxw;JRKa6$??qROc?764hFrxnfa8Q7B9l6=kx#y`7vP*s*sH2lfjNzW554 zUvnjUuDg~uUVMRbufN8M-Fq<{N0Y43Lz$MG&A^2T_P>6F9amq?nvMct0@WbKHa%P~ z3sReR7jpm>GgxGaApWoo~N%n8wylEVGA1 zD&_*8iDH@R#0)yk+|-*F$HKzIF(nP2#k`DlpdVnQUX@UZ)W>5)|5-KJ|6i`R8-SmH zEA}hWGz^S%MT;;^rFV(2hghQO8ybfuwaLpe zghnSqYJAi;SSuxUSf(~nK}mCv-rOsmPO^lMZHpG-%VGmN^x3@ zPEXR`)=g5J!zfPh&;R_7YJ6-=G&B{cmdZ>fnx+1wFMW+fDQ?+*H9tBvMpCO%JU_s1 zfBYAC`ngw_FIF&2i)B6SyyuRa7&v-}pZn0ya{6lz5!V)I>+0a_#0XdI{gAjgF~aEZ zFqvGAM;?BJk#i^b#Bcu|eZ8xA=XF=`wZ~tjy}60e@e$thOYgz544!=IDQw$icxZ$V z-t#_gxc&w{{E^?}<|}t{^1IJq_VzM&ag;UPZM3%l073u0wes7a{xsF9kHX})Kl%H7 z=;z+AK62m3#ML`C^T?Agp!`m%L6McMja<2RHz!UUC^uN@$p^-vN@1DCAQ~ONQ1~1HWFQv9W<|JGOvnt5;rr zUF35fO^pr2ro&4wzfMrE)7IKV;QLhTS`s5ni{8FojvO1nl?u;qv!bAsNIhH{Lm{QTym}UQg zm$`D+7W`V7V<%px9@IJX#w+x8HZeOh#o2SmNs>@p7(UCz$r;AS$8ju}o}Ct>V}l$$ z`WEGKg}%Oi8gdRpBWExy$%PBYnO|5C$Bv&Omva~&8|L`&*D*vy&95nh5~d;5`H?ds zj3dTJFOY9&rlF}>T$~){=)nVI*Iz{~j4@1u5QFV|b}?XCyz$BbcI@55?tS|>`26z> z9X!CwJ$n(RMG|WdO0gc$+R@HsS6xG6)}a!_BubL8bdZ{qGTprDp-Yrp;`NJkJQRd6 znT*Fxcif6f5`;>YOuzcZmUdbX|MTPUT-W->Ug-kvRnRI2p;V+bSl+DP3X%9yc>Q+)E?d)c%5 z3jX8^Ut?flo0*_m}F9#3z=6OqJ>!J~zgA$)_WqMOYEXrz_h0 zFThN<(6N9ZO6Y8EkGvB6{)azEkVuXX4zhFo zYFx{t96=yWd=#G2I9|)Ph%!0iT0LcoN=)0rwk(3sCw4r7Bn=;nqa``rqNm0Z;M#9D z0RPeJ?FQf{;3}6&n5HHiBnpIS>nRREx`K?QMvVypu4Us|E}>ME!gSh!{-7%K4dB!?_s(wtw?6e)zm0` z$u}UCSn?{=BmIIKY11RqwWLU&bH=dMc+x!$4ZLHV)brZ@#{t@!GU%%)3I`8ETP2gjHI*TG@8_ zRvH>|V!l}7sRtkDmA!3jTD@F6ZR#w8Lnv{(x&g z{G0f(qPdV~>!vmQ@ZpEpvvVVTeccqY7Cr4b;);b$Ku>d?S(OmhYBabe?X8U*JhUIj zjJfWr?Kl>k864z0-~JZA@rh3{HZct{!OrCnDqxf9U>cBX$TL!@(7kpILnDJ6KYE-^8`sg<)lRiI$KU*~zY{mz{7!->0vS@T zlr^H$vG9GL1Fs#Ry|a_9?oRTa#nB^&)v;rTM4Uiaui)4Qksl$2K_n$#{y$%*TB&jE zwR=h8gg^bW|HX=BtJt$=Hwza>aN1W>tX61i%5wQ-oA~vQ{XOF&!`yl29fV=bljqLz z#V>w|eb?N`p3Bzq%=exps@0KUz?qXLX=^Fa)z!wSv%_gZuVQX?p4VS`nYOMjM$Qhf za{DfXWs?K}B8my^9F~#b8Zl9r5c%3KM)pEK! znu(%FZv;(?Y}TWxxryn?X-3B;$mOy)j;$w~i9{+*%xY}RGdOsGnVDINWuH&}kH5tb zlCI8nR;}p8b~AdY5o_$OY1w2lE^i)wi{&ep^X&64^8FwDkjpl$7i-tsco{N*SEL7^OUAt0emze1`E=kDdvUGNKs3(8?thj3Lc3wYtl+r?pNJg}@wjmQq zCYxp5`t@{nwu4akwK|=h9k>}!EnnVGOLMb$`k5ES)qA(&xh}5jFg`s;RP%|Fn3m-m zsg_Gr1D!@}d0BlX+78mx1;0$E&m>yn=UNtiEQw{LeOW0OKq?60gq&;PSw@=Erj`Z? zVVuz5Ie@|aKX{BSo7U6U+e;K`SO7u~DqPd#?7&G*79?F=?G!5!#p46SNg^hqi_A=p zQK?0|ad1DmhDJt*E^zwfF-$kl@#DwU+~g=Hj#;9iP@r0?apKfzx;i^KH88-)$VEKI zWqPIrLa9TCkBWvu8)q+!sJYo`F)}(OG8s>0GFhH}>M2^93u5s62yuKK$1*v4dVpea zo)+6)BB|D5MI;4lc5X*lCU3oVkj&250C`>UC9@h@#`bz@cXHQrMSg&+MtQO%|Sj$zV}%^;OxdZD5> z%mO06&J8#3;o5ySFg<;NuYCQR>iOsQi`6Up`S@>qj8FaHAEyuq{h5oRI*#M$_lITS z`vGwh;W;i*oNnEcB;5=d*p^KghPbYS>pGk~J;3enxRvdzdKe#=B$tK*{_yD+$ycX% z_Qfag>s3{)EO7eFkcg~2PVagid-DucD~m7;YEeL;u?f%dE^YUfer@Ve!dxxl+{7&3 zf94h9D5A}j^yFQhzc9kHhfmSckmHT>a~QGDhB#FDyjAS z0)=fV#A3sxbg{m)dRI#OEri9Z`(LJX_+@t7{Yw;@TL=9X_J(TOwY{;zo4g7QK0*ipn`3? ztm$v3T&hqml_<>ySaAu@b=kQ2GQtO*z@MKZs8q=3GUPHYof}qj{k3~Ja`+II(?q7B zk<#o%D%E-BW@hlqWemqcNQrHLlo6l#qd(+-{_!7?@f@VzLaknK$uv-3G=-M>u!( z9LJ8H;Of2GC^TloxxqnJY}|&AMOdq28YYHNlopBzVK6yc;@FwzSiiEDxw!?-o*m$- ztFAyMIs_==I9Q2^Lb76651wl?J334pg>*N2bhTuGgi^Uo7=-#WoNpxb7iewk1Pu8_~?sMc!O*$g#51j`~< zD1b0h&w+{Qc+{#jMknV8;)JZBsX&R+uW8;i=xk{sOkyg&CO#qcHoz3=P{r2g?_$Ba zG?7jxw)H3m+oHFxAH%jO)#@7Mi}r4qhDqKtDC9Hz!#{nGj;>Cgd*Kx_j>To0*YSgA zUr`_Yz`Ml#-}(oB`i^(tIupF~;!E6h*PVRj>;J-?@4Ha%~vmTg<;>*?ZipZ^M<`qc06%+t>bbNdc;df>DuEfmE)_uR=}eD-hoolpLj z*uQ_jsw^yU_g(MiPyXTyeB$FD<&hseLPuLWzi{sdd1|N%Nz8@G8K&mTX8YU%QWk&pgA~*Y>k!&t6R1!4D#kAdvX6CiqyUMHI)xi6rA__I?s+ zY_us%j8yiiQfNb*N;%_L4~;;7Evau$2|+&NFn0DdRVnD|Uyg~wLXvfDD!xytG{f0* zgPcBdUQEv|uy5a$YQu(&B2E&5AjEZ?R8D7MSr%~|qm*J{VFA~5iH(>rjF3v|?FNE4 z{cjKiG!+{09G6%3@8|x`W*+&srwF}finFtjgye0(+(Ma!N|m|UX@ruhI6o&M!)Mv@ z4SaCl4(4OUD@O*{w_^iGrz;FsC1IT4r1=46NAi`XK`eJVshSrEurN-c6yJogwVQpQ#156 zVpG4Nl0}^lLYohlrtv9V0fkECN{f@0#m8+TmUKd9Dt|H40(fz1Wu&qoiGitLeP;_n zM>8Uk#8PV9X&U6SC{tS0BdiG~ z4k1$TtH45FSvG~nMxrQTzFKG9&MWx0ul^loCdb+>TRC^;G}UUAmcA8aTici!p281` z}s1@%e^iQvrXvjp`zUPB|9hDM50Z}KZ2{bfq!3WMPV>WM(f5b671*jm08 z*NCKr=j9Mc;xHjm2C*>6XKb8Wj4(`^nwyDypQ^7VLsF)ke-n}<#t%YF!@w{MMutcA zl-P60WL!)EK^POI!B=GC#k-La|Jo#B{c|VA~e1>oPtzt~XzniEXWQ>JUnOZ%>aUFtsjhtsunxAE% zTt~_T6-OARO*Uf^gdv0HM#Ryh$1!aOq@uZyqtMhyrCgz25AlN#!?F<~B1*=XpI;Cc zhDI408pSkCJjcNGGL*{|;zUo*P1A&wp)L#)uc5&F?2Irilctttq*RnE6)e+4#xd1O z6|12@wz&z>_6}Z`}W<$gAe|Yn{K#4?7d=-dg{q1#Jk`1 zULOAb_qq9on+WSwF*I_K?K`fZvGE_c>Bbv*>4leAzI+*Xz4v`AJ9->pWpLb$)T%X> zb+$2Esq^_~kFb8*HVh$n^T2*~TyX_^Z@ht*o_m2epLvF!Z9A|W52X^a84t&@N#cak zLWLIBz%ni7Y9X0S28rH$E~2BG@*YYmYJNy0bqcUB7E!Ju9hzy0s%M)>;K(ySCdjqm zbuPnE5$!pbFpQ|xD(d|CW8%#>-^4I1yiA5D3Pl{%FfEIu9%y-PI<%_$K5-P`Iu7}K zj#81hnwu`QdKg*sn({AEgE5jVDotBQcW;wrtwW^}X%5C6|}qI*n&X*m)bJB%Wo^RA@jZ9$jq( zH8(r`TLML`Rs=gf{MciU-Fn+?w@v?lEYJQ+UvD=6KLM9#TS6#F5`{eUmauu|i!wHN@C>ga95Ad*R%RI3Z#6aqw; zs3kd%Yw8Ks(j`(%r75UIdb%PIOX-VIatW&ky1++(jb`yL-mFNUt6KW~B}~1(=_L}| zGRfEmD#hSAhCwZsSW=U9vH}v3atT2dS2w2@gMlZe&* z-89_wVcK#YU@$DQ7<7c_@<~y+S4M@+yZtCFa7Z31%{lV|@v-kZPrD{wN1WYef zsg)}nc<}&Ne&Ak=mQE@Qb2M+<#h1VR2zS5hr?~!>TX_1J7esq&Guy7*%dUMl@R`5- z93u+}4ZQ{I)^@y=oB8zLe2tBlZRgf^+``P_OiKr3a&A_{`TG{-SqP7_c}MwNDZKYMj!x^07(EMC^Lv6 ztz^rxf+>o!Y^%nSvs5ElRkE$Ir7GFxXlR+HBuX?XF^FamGeKlFGSC1T=$yM>_lq~3 zb9R^yYv0>)ja@TU;}0wwrwXCNd+*+J_T77}|M~~EZ{5nb9(jV_{qXOTP0eH46QDHx zq|LAV=5O;)e(4wa&0qg#eC!YZh9l#4Ff1#Eg8|wkT&hZ{%Cc+cc9zbcqup+D6xsv4r69!4Z7GdnbEO zT~phd)M!!>Gm2gC!~}U~f?@4qkeWZ3zr+tVc<#B!!qWNktX;aKreMzP`b^3zs;4@-$0JD}3k| zeu=fURi1s}6~6kN$LaM3^m=`^ZeHYu8?NVt*?HdjwtJawWSlNNSM9qQjN!Q__OtKK zH*o74@8ZNu&+}8a?IJ50Y@eN^XBD5_e}I`zN>*$B<^y*Vl;#W19Oi3>&Y^ThqGhk2 zZ8uoCxXgN4F*7$u>WYhsG6TQ~EjyWYT&S6%{Vsq0Fut@jz$D)?$cef`^yhNU`D z`=5N4_rC28%Ak4h+mEnz;R0DBC!b$rZtD)}Y5+^e_~3i)=H}~fB!r3wAN&$iGn@E# zzxOd#c5(Nr001BWNklN-`C6 z5y7ssAcR0MGs}@fFY-cngQ92=@+KB|_{pb9jbdVII=u6it*U4g@_u81lIBe`UgHHa-_be_f+~U;mUjaY!KcGbWpZ0pa0r(!c`n3&$hKn7akDI-Ue$jPwmof3z zA`Mfxh|<@=qartSMAHf3GOBKa1euIHq!Sg!bQ___dpwr~z&if9I8HF;oH`#UeIVDD zk^9O8(nK>^WDIIMwgio|c}6w9LWIWhdm&Pc1kFdq!_5nY!YSeA*0Deyg{x?|oXqGw zsRC_eN&vB8LdLh=TiKwM#FJYe->g!UJ|+WeP37gc2@EuDof@olA}o$U zDW!un*9@)vJRKV?3GTV93#dXM)t*90K$MR^(^`kHl*Hv@WKSwjb<}1=64Qtlr4;=- zux>rMR%BYT0#J&sgH|Gc=egtOc>mx0Ne;g93df)PF3l}l(Mqwlx<;?8vHdQauDpu5 z-PdyT(mH3B9QW_Oo{xV1TfFD3cd+$}YdCynKl2L<96fxTr3*`Jx$#!E-To$yoIOXV zE6l_U-#&hrBfs}a-uL!5al`f3hRS+QoV~=q`0bCVr%$cZ+O>y}H`wTxOl;Xs_xx^t z;IIEJ{>G2~AaD7;cXH_H(QtZcolkz|-}2g-Wp=*dEvQD5V`nZh-ENR>+0BoA@bB|M~Mg{^B9#_S{NmVUa2b9DcQSp|^~_(l7dJ6ax2nMyvQ7uv z8

%ID$|RhQ&OQv{(eIOnJpB)%q1MJqDs^-yYtNMgW;z{J!HNsy4Ey$7FF6g?(P?+6suGY;E~8;?W|H~Yo9Xq3bh~}-d;442 zG&jYiiMvGUpI4;c(=niG>u%q`-3OOlD86fQWlNpRMYHe2l4v5gh2DF@=l)*BAF ze&0Sq2y6^WDJX+9aeB1J#J$xh0ZuZb(FhH*jvHnOkQkvky>{w6`wt$YR)%kX>f@Y! z=~=aH+aif_X=E+_)91d(gJ1YO|Lj9Q!C!yiU3}%y$JqbUA%5h& z@8+4)mpD0)g!@D*+Ihy89(@cmF~wUpFQUteFcM%zR7xpBAVk-;Kt&))Gde~NITr+c zF-eLB2Bi&2ngl{n0+0ozb%HWUbQ}se?=aCNPAf&0W%LJqx;-(F7?u^F$Kah-a#knN z;iA=SP!u_rlzO4_J-@|cDtN9a)``T%pG<5Zzb7bw@(FVythYAKjMajlJrdlv?2#vD{&k0@(svL z)J{YM(0ZDgG=ss*YjOly(bXx0K#>|!El6PL z0#?B*=hw*6gkSpKe~mx=*ni@?Pka|!$Kr3$Wq#+CyzxhWg5^O?Wir;SyyaewuXM3xiBkz@S9(luy@FL=^B=zU4B_G_m1P-c zSNoLd1PeFsfufB{6E>VoXtv$)W;Qx4{`4yk@yV|}PN9Pe1gc_^T@Tz#WAhF!ZFC97 z)3cr}x8F@MHOn7<=^_5$3lGvPa(aVO^@<5L-}7!ZZQssX<*~KJ;F;XBm#d~``1n^J z=MTQ{EmC77aa9{OU41?C*W5sjp{^~1p=ECKc5eKEzsAA+kMQHa_^V7!O~q#0Gk5#_ z%-?VeP8&9cCAN0>qRrlS{Z)=X^%x)eNB^86PstOlyiUn?-^Pu5@5D9RBFyy`KNv8# zZ5OMubrx>Bi-pxLx81ylswydU z!NQeSqoy~}4TjP|=_;CO0zuJe)XrO0$$f@Mx2uv>tnv z=ZyxoF0s~%#ciGwf+tH2N-65vk)TFgvOG8hi&_Xl)Z4VvvXX{6UUD~>C9F3pJdp0X;@N^|zY zCGsL8&r@tQq}T1zYPB#i?8!%}#)v*S=nrr%Ff}zvnkH*L*Zo#MbjzPOG}z0v|245{`R+c_3?+f;|(`4J3A96j&U~%p2^8h zbe8cn8wDzw4rrzE&NJC*69}}L#aMqZHQABrNV|#FQjktfb})&dt|nsWp}c5sJ(Hal zwidg~BuUUlGdVGVRxmZuxeV%z(&~+3W_ps1jV>21t&8@|S~8;;mX=f{Ty@ipm_+f~ zbI(Fu^6=9KxP8|mKlKCO$9E2%pf$URM_xM0clN))hJ)2X#mP^7nRU|=z%2wy>o~X8 zE~tDGBCzEZ8*Xsj{s;WuSgrkQKv3~Rr zs=AeStI41J`RCZYc@y`&?E#>xAm{EkzJaqBmwD}cj}QIuJ7_m@vLt1q-Ql@YOFZ(_ za~wQ$m>rwuSwD4>=JYgW(cs1Qh$)?y7}Ocq?ISvhq|;lxr{6-|=FlO}0UX$v0|I`LllN)a3$ zE$3*OgEnd~7_zi<9$VGa7955~Zb%c|K7Z)M9l)3W#};h=^IWet0N(>wTI5P48LE~v z&wzN|k6bN$5E{!c7NB(i?VQ+eBKv9`i+3VTM8|1?@X>vw^o$a3V>6(o=+{V)iI4Of z9}(#h@+`%wcvIJZNfVG8p$l0LrS(GhLA>*Q5bye+Mh8`3MDMpAvke7)K zgN=o~3*xt*5MmRf(MlrLt@mQr8Sjq|fkXw$aQVK)vkn_Zt`hRIM&V+KAx?1A*iuf% z>BdNNpb_M&j#G_RBJZv8V3E^*Xk(LTw2YCJ;g$1i_yG5R;1{^_{XfRp^A|+O+Gyb$ zZOYn_(q~fvGhQ0F=a);iPc3l!`+l6e-UqAeUAiu?p)xM6u9J5P()JWVOOX~-AZxd1 z&n-}Q_fX_1q4xAiNeEb_2_``SsSfBQW$v!~nY;N;>axTr5xk{SbEq_@w2tY#fyRUP zta-)!EpKMa4f|MMU86s&SjY>C>1jws?A`W)NbA_lZr!wnt=Ha2cWo8x9Y$#y6CF(6 zq~`)jfQdw0umXzNxy{V(xPo$hjnqrHOh^lgnR$9P5UQHoG@>1=EYz#N|F06dtMoRy z5)hOY=*|p7FaF%7(WcPQoS2q1hsV1R)3-ehZEUS5Z9lxmC)>(4b-rdWYQ#|$a4|hCpw~%IdxTG60s5O4@w5Zp$KXf%+1fT zxG+bn)ugx4Wq#8PXHK7I*dJn@qqoszZhnrzuo8Viqd}`#08+H)MG<#J*}sasz!<|u zw~tbqnVA^~fp)7!Q8Y*+Kp-?AL#x#yGy@wOU8<_4C~{_}C)u(%&)L&wICJ_uKm4Qb z4-Y^5s2U7POtf6wvV8|9j~+prgd|Pax_uklc5Elhi!d|Y4r{BcbS9?Bib4&nr-MvO zS5{W=Hfkbb>Tp@rtgNnM5=~_-$;=e(h0R=AIzd&IC~X9wP=Q94((QFQcJdT{aW^W0 zA|@5k#yO86&@3`4>+#Ovl%$l1LzqGZjmW(v$=rLHWF}hjUP5df@*-#H^hs7&)j)jRqoz$#b^W+Gbv|IwvgS-eY7|dA^(3#nc812*UCeIXM!&Mu z0j{~>M(V2K#b=)3$A9>}OioVlk3RBAuGzVr`|sVwfdenIeX7Z1nse&p%WSlAHj zpLiBmmAv%wA^!Bw{xhe}oTn%nSZl}Uw9;ZgYHJa+Cq`4&R>J$7#ac^}7?Lz2gg~Px zn4X%FX3GU;XQuel*Z+d$!$(Pir7kNv6I1lg9^sEa@yBdgn5K3D7F=9i4@2E#ac)5k z2kWeD4Dkz_Sy}Ir%CVPS~<7Q zURdU;tFI#jLRCu$U6vO#GK11a)zu(Y5Lzj%2+pb`Yfuk+R8=YNW-gGYDOu4VO;VIj zK%ty-1n(7Eg-9({&eg1~ZE)t?r7$_sQ7Y7AS;C$@HTJFx8HjSCULRh8Cj54UK#-%IZLt;D>9>589FK_AwR9$ zplld72U?4Va_u~+F=PFK)*2m0xhO@`$jx^_UVD~A#GZf-5)P)KTapf!-*c)N3!VYc zmjlR3FQ|TQ^!PxJa_86#$UQO&I;kGJGi3$}C1d`|N#;PJr2uNQbDR&Xl$JAx&oJFA zNawdQs2zjKQmyx7bZio^oi4&{}h z#RQE_I#7GMwWo59*@>ns)DXxLMQUWavhE;lPLWO+JPH>)1Lx7MLLrouQRAdl;KIg$ zJk3bwwvxEW4|k5b9Ln@ZkD5)P%MF}IXAQz!Gm5_z120LLJ_vQKsx3xqeDL(klDhUJ z?P*LZ1JN$P5dN^^!~O`axH<&Y#v#h{_KcqLOmx5lSl^1?EN&?Yb8CIcrH0e_6BPEmd6+@gc?$>Pn0mswg;D z1d3*ZG)vj&_BrzWQ(>_+sZJa@NE#fv5Nq4D)G)VY8#nFR%CG;;_i%cp3;lKGr>A)8 z&`IvNb|*jfSKi9f@(TUCZ{)5UZ{U6Zg@b;FwLuws$Ybo`0Uk^csV#$uIx=KcR8)D1PMv$|N+39JJ>4n{VJ9_rFW|V6nEw zIZK`wk|W?81h0b9<0+PxRsa`7kLSGuUz4N-0i~2OafQp7E&+eha9gE#Ja~uJd2G>Q ze-RJcwe^i1|DOx7{{^qt8-VYDD>Fj7QG-g*d>`oK37gv)!`e|JhoO_*SFA9Dj2?|r zQCzD?LJ)8H$PZ1m*m#Oy)(MZ)d9=}FV^m!}F5(;nQsl~}Ci!2AELG!i^a!a@O3Kq_ zB8B_N`NyDe5ye*V`;HulG^0jDC@@L1!nCoNPZN!f$-%;l4`ZRC2L@Kq6=O6iqPQa` zq!bCm(UF!!5dZvs{F+9RP=~zpy%bL>em}7?Ris)dQF)Tm zZb)#_a9FZ7s3b@xiiR^IjZGco*?K390!TV&Z5?@{SsQv9iQLmj9~JG!NC>P1eY42q z03Tu#LbMGGG>EibSIrz;lvoWlgyZKF& z+EUwqNisB+#29qez&S^7mfF_h9%eMwIr_amQ>|H&m@MtA1*56GB~4NqML}IxWLe5a zw>zfU^m;uyoi?3zi$<%7HX3IuY;9?^+GIt8!TAepn(WZ;4;fOicklJ#@S(%XT1%(h zBu!ILo_?=8PQg=!_PX4VVsFP6w+U#!ItK_O}BuC96V@h2$i9=a@^y`n6f{>g}~%Qn|HqD zE_Ktbd-?r8`5c#)jKk&%XBoo;-Y-qSfHY%P-KuGQI06(IjZG(FS==$_up=M8^g4OfzFBt&{!4 zIiX`2Jr1q3y>$lN4Yq8)n)~m4yXu#YQzuW;?G4%g%*&WG<-p-ntgWt*7$bQw0fLjJ zDJZ}@e2_Jw(v(!|nAPG*Gzy22;^=-;t<^KP82gV(7l%Zj|wVAHjGu!{>^ zS*_8~mYeq7ipyJExotDo?%vHH?eO?ZM_8Dj=504##j}S`^4P;C(XQtFQOnhL+=bSL z319IGKkydnw_VN4&pplI*A9iMcIx!mCA8LDxqGL8XQUXDq99J_#N7%;pn@1;7!9DM z5Dk)rKvIkWx)CjElkYv7z~#Nr zVn!&j4xY*@%7};#e4v?V@ve7*nu8$lTEQ@ifk(XlfY5J>h@=ml2*hmE3yeahd_Zsh%p{;m!2 zPy_d_e6(?vU_~w#|Iz8yFUK^z{>_cDiUfZapb{Ca7b-EX`-W>Qsnm= z6mwi--L3@Nk<}s&S@OJ%0X52`P%wV z$qvqW(j=9lS}BTV!SwVb+cwX0^7t|JBk%uVR#uicaptUg*Sp@q{{2rAg5$0`@8HqL z_N#@3c|w40x6e1f@oj$j7k^H@<7a-JhaUYlU-`zjn3|dlr%s$wXhV{uOiWF(vb;jo z>(lM^LPS6ODo*>7jKn197+~bBjjKhGrH0gqzf7VPwbJ;w2OFayNtwzM>awH^ zvdU`b$GIbU)OXpavsyZHmdSFBU;o)3;p~|cG@CgylP&)2kN=omSM1_<|J85u`7eKo zM;>|%TUk^~VUi@$YYfhL@;n`Xeypu=)?+e5Q558P&Tuf0f*olTLbQz?nN}!}pgHH_ z=SDOqT5GZ_V>lQJh-A!onv{hwo&xyjNGC3Jo-9ciRyEcK>Z)R4(=69qy_>_Y9_H#T zv;556ceA{Fi5sum!?z#(Zusa!FRP1H;NN`xS+ZdH)Xk~Yc~1vLr+o6?c~(T1{-FISB^Z%`q~;B8v|_Uvo>^8bjdXl`z_{PJ}^88Cjc=`ARl{H%wX~I>z zcW~Yrk{vra_sR>LJ$Ib`3$HRX1x{y7P0#R-H{D7gaQ)VKZolaU4lb>cWI4)ejM8FL zo#hNymf6`>+CCOR@I{=-?d1^~(Ad(ENymW{tPzFp9>13W`$B#Dt z9|hOz*Z6w90r(!cdS#7u9+JrI43`U|(gm_u3}xoB;{!9q!CrF#v4U7 z7W1m{2BVN7Pe!nTTt~Ws^HD?_B6=ysunU(x{1uRCDWE*^j}0Q~1+cMeA6bX~W$KW8 zM1@ajlxP67Qsgn6xc0*Rul&eKC`4OR;l|gokx7I?D1W9E1aZ|E6`jV2Qw|}-LnIc2 z(L&EUu{carbnXeG;#T2fQ52A(U5f4)6Cd{&A7E`z)5|94y1-huPp6R+;~OB3GnE$S zAm`Y0%}IZZ48_n+0@3uC{-h5M1nJjOFx-L0??mW*u_oCW&>&ZA)0(x=6D#!GHdPkE@&a-OAj;F0Q-o zIv(5q3;S{QfM z@W>;NF&qrJ|Ngi5W}~UDymFU%=BcN+=Gq%*wI{jz&G&HNl~+QRr9fa<4rzuC-ENQG z`Z`IHNK;hR*s2;&Yx|E9bSRpX8h! zvTfg;*bt(A1*~_pvkZmkq_R||RbB5`n4RRt>#t*Wc7ks`07^l%zW5!!`t?^idh`S@ zJa>S{9(fd<qJ5DZvZPCWdeslLTi2v)gvk+`LtEPowEn)X>bd z3d+?>oL^mIVsR@V&TvC3L57CF%$DtZ^~onVZokC4?tcqkdGt9hoVth)aA~7Y)$NiM z1=_`|fh0v6*^|+Um|GY_3YfU}$tF`$SC+LtWSbYbdG8Hef9o6g+EcGEICP$=JcrgK zNJaKm<*c^<*7z~ZI_KK&Qppd9ph``vfY&J+I6kAI3o>y}&Ia68X^ zcRyuSgSE7Zl;cNU<%?ha77Lr^IDPgUODkP<=G+o!Ls`{4_QW&%%m;s#+1VNTac$I9 z72fq%?pJ^1f%~x5vvlDs{r)ZtWe9m;^M`n_J6zTdi{de8-VYLOZi%9EUK&{ zx08te%81PQn8+Is{Zy-QLa*^5BK3x0uL~+LJuyMI_SChd&@xgKbXPX7%xE%W74VTa zB-J;NsX*!E=O;=D$8|(Q3W3ZhYUh|}WL*EoyQyo-R5KF_3^5oi2;%E3av!aaNyZS+ zG&4)QF}I#!btpP<394{Hh93LN(Gc2sLb!`A}OCI5#sR;buXKvr$Sd zC`#usM$t$_5bou;iFpwUAN&~M&J#rlvL;H==c1J+HvxZ$9RG)rkVGYF7nIh(id2(xpuJiY%J^t z-t{hCeeEC)&#-g~G^sMA3d-RS=RN&Fm$Izz(W)_o%i1Na6iO$kBomufF9Bk~InvZf z&Oup{MC}ELy>FIC;Mm18r>OfIEbhCDI$DS-L`XZdLfexGlK?f7je)z#RHpe#$WEF;Z@`lFP_+M2Sg z0HNR6+CosY+D-cXKK)*w5CXY}s;tTLTteH*ilQheha~}Vn6lPlj2T;ex*+F|HX2t; z4oO}Vq*+Q`TMRPMw*3KD?b^) zvoAbNdu5qT*X|)G5kWT-h4TuPro8avcUeAno;%<7*QlL{v=>^rXzD^hnS{>NG<&YQ zhHJMiaL2wIIWs$fX|y?i?i?E{%g|fFSxfCj_n;&2V||>!D}^$N&<=C~4(lM3~zKE&^sH~8+XGByzC~LaQ zs|{aVwH}F4B#B`-=woe-(g~gfof?AbLI|{4 zGgQNM^hjC$`t{$uUT*-t2d*T`28l@^349uXRX_pjV+9A^yM|i zLTMEAReCAbMvg(bhH6avh<2bZj6=c_Eya0e5*8Z?8^a1`64r+`jnvSKp;;;xq8dTb zYwK}i0Z|}Tg3_Ca>W=PF8ow@{##kQ%bb|2eOYg@BaUE$zDvWXvr0IyaWgMQYm7-h9 zp_?a)t+@eGhP55LF7+x;o@g>Hqi-9F+%$|tzCu5e16!Vlj=aWh0$mB-fzP zmx}{+S^tn}MHK>r+B4Tm>9kr@*0QqEqeP2eb6gk1=VkEtpanVCGTo_MoE*gaJF;}G z!{yMrI$U;f8f8?d*c6pco>OkbM$wK6?EsmP*Qa9Bq@#tRiL@slsX(zOATdI}8y%`* z(<&ouA4Fu`Obru_jE!N58Bd;MJuA&vHzI3WjYY;Iy-XuFqWNev`S$T;Qlr_lu*gg6 zL-v2=X|gn>Xif0U`5sOgnt2voVlDgIYorcbgDG1RIR{kAL(zKK#*7 zv2Wjvy!D=0y!R|$T16Wb-BP@I_26rK?sH${t@q!{(G%zRxxe!d3BmEBKk{C6+if?6 zB+Uulh4qatFCI8ZtJw_y{@;B>{qzTZf`f;Saq!?F9)9$3X6I(P{)X$7iv@U5P%CL5^LDnp7^x3?18z1=TpJ#RL5=RdoWa-jH zo_ygoKK=Qxv9i2IzZ{ZAnw0kvN@k*KO;N~1M{7l0SMjx^aRCNetrpHY%3(>K=NPRS z4u+!BXf$xn#vm)1_WF@HR>^bGMw6sMZ>npHa}J{n+US@}?MO1AarqF&(ib|wq1P&h=_>Tk5oU=!vKJ^Ur*ifB5%4!~@@VA1@z2 z&5^T9tZeidoIgo#Wrbl`Q`OQ4X4;^P!6}9E9&Zvz(yYRqrUvb zhd5_*+93#S2uO=2$4{SRFxXP;wvX@#9Tw(*nixRX4T^m=`c9zDvbGw12``n>u6d&K0z)%e=BUXV`h=O*Gn5^!t4pjV3luoV~56%97>PHJZ&PS(0Lm zCrdS`gjTD`@#DwPI-xT$L6SGXWK>nnaL}jKXkl$dD#C-;um8^VdIRu1a5Wo^N|^+b z3}=UASxyo?rE4c6-&Dl{%nSc{#Hk)xM-Hos&gN}QOwX`Z!=$ZAqKgTP_{y>=OF<-J zT5;?V`biQC-)5`Hg+niK;Ke7o{yje`TyX+L{3z8Ck~J!jjxF0R(}i?Iw4;1L{QR{P z-9o{LX~Td{GoF3$8!VqY%^iRBZ_vmPi^DJqHM>l~xNL7KrgvT}1Y%0ASl<~TkxD}# zkf}5zSxS)zCt8X)gZ6Gr>+oTeiNMI&j-eYFas(QQVraur4)IR zK=5NOz1C3KfKn0h4xC#o|<(BrzaNDlpN=Dbj>SqA4a?%yn8= z@5Dw|7jd!^WFac~+A!h-2Q_XCiEGCgB?X%G_&UC?5a?)+OH=Yh;Yy)x7_BK9O_bL7 zx|Vzk^fIDP62D8p+9ldybMoYAPMtohrlzLpbUHlt_>-zAGK?;`ZqHSe!wQq6;3_r- z{c#3>^0hj4;xxU%P;G2on3aTL;uC3wp ziR0?bxg}maaEP04yoPcxWOa2VQo&?nZ8QqdLJLcigsK+dxrsR>-jA$5GmJJkBQ}}Z zh+~rv;=bm+*p?>ITGb@dC<5YsWW>qI)?xxMJw46(+B$V@QPEM;y8ywB9jLM_#X3i6 zOQF716`MBA^S6Hbr&w7z&+mQY576mLeDSN_WXr-lSM0fgr;o4DXt%lZj$3)^`Byl3 z_!w`$=PnMMxyXIjUBgOm$k$&y%)9T{%k}SlEC1%BpXSIj&obW~(3qU2t}CH?rWup- zo0-4XbMnO(nHdbw+jh%29Sms%c=~09OB0GBW2s;BwS%YW4r@q61YY$9EL?RpNqd6d z{)0cG(QGkw#nm{iC`<#rxSM<-&`u1Qmb1#4jLKSul@;K~Tl&_MXDJC#Tg$?9hrDR; zN^iV!DOcy zCZ?xU`G2$bomUUFhCV9 z*H8{KW{P2$!WhGt!Ult7un~xsgb)&H6k54+tK-c%y!qsP_TDSZhqcbRj1B&*551~x z*S&AQ=j?NKe4hXF4@KdsVvII5S1w2|i>6aoKF)|(B$H^7Q)ErhAP5GHuJ3p|~m4rAoXPQ2tNbO`_2aS*7+LO`R5 z&f7F%$)GaK#y;#yN$>LFtiuX#8)#h67X*c;H4YQRuY;<_#3^Oc;A+31HTCB9g?ki= z@JM*;MJ0tt^sSpBsgp^A!xz!T#I`dO|B>{sud9l3Ts_rriBl5$H<6ji|0^q%pnHcpr2;zKrvQy%(NZkNQT^hsWthz(l#~>;7os)Nh}y!itXS&| z7^EGRD$Vw&B1@ux{`-bWg=E*VHeQH~qYOF>@2KM&tt^Rn;l-C3bvxXA&%LCPWPMms zS!l+BW*kx0I(VKFM8l3cjL0XGDHZ59CLGy`Fk49F?d5{tSK+3OWmOxJSW#R5`LrWA zw|I@lTqEO+H(qD;;zjOw=&dA4g0Y&~I)=4B_haFw2F6&NR0!eo8Km$IN5;WOTO#47 z3E;WTMYrqSZBUf8r$nf5jD0o--ik3?>^5+KExw^ltH(KW<^nQ`5Z0fgON-t< zR4GZPH=wR-v~g5*$>8)k%Ch3biL+#RN+bp8d^=43{54!w{v5H+(e3uRbom;mPMu?U zX@MwG813DCE?>S%nx;spkkU7!#kgX7`!a*!ke9#y25}sr;)vPV8ERcKJJa&nA*H`& z@;qa0eS>bd&+Lr1Or6`YpKf=XH(q;#G|On_F(!&BE}i7;(_bUOU?ZRWiZwJ^Z4Mkf zNOk5so#7CiCJ8l7hKr!l*PjvkO{x`haX{e zYE^#rAfWx;Bi9f^k{${If3zYaCGs8?@F48zxkZMuSTi z&(faT!H@sUud=yunJCK0vYeu<5l++ZtPv*-aF$wE2qbBvOUQqhPIN? zu!AveB55de=`GZ^H%Jt;CpX+T*WbF{YyiFimUT!QiVi37slW)Tz&)Ax=|e!y10|-m z{z0$sV&F827}sWsIJ$t6%HWf(3Bu1H05*Xr?Lsh^3I6)E(ZnlzxOx8}Y*hwseaIM) z6A`iqg}C><_tS{$IRV;U|9-W*j^a-p6s)IDIAdt-*hwBM3T+tG9_?;NavC~joFi2p z0e8+*qbBIM3+Q&G4chtrkOX~1ReNWkG|hP9YhPmZ*)Q4Q zx@F+dPq~)@RHQ+cFv+jDs zrzLZl#Mw#Ay+1)>CA`Cu^O_JPCF5H2%JH+Xahb&%w$JhUrTc z8VP@xJPpGLaAD%3LPI!d^SpJQ#aO>*Csdw1_^ey&sWoZjkx(Uk_t_ncXs+z#-orOh z)iq_Hrb*!g;cDwIMn5g`*K8guidrM2B#Tt=1^2eEk@7Z+-C@D`6US*U?_l470}M+& z6(Vb6N#i)2O9qEO?-2ext*v9Jo#Tw*^{+g|@(l+`TW$KC4oWKe*5O2qu1D0y2kO+L zkxv4S6e~M-GCMy{Rh{+^*;=!)u|>1t4KwmQBX4AMIz6skTc_P_a?_DR^algxXIreU zZ~G$AIe)*=2Bj3EVZmtN6M>K1aubbaPF>fGiZP}(7;9*?8Vrk)vh=CLTWcFA0kg9+ zT)A?U+ityy(Wsypm);>Jmu(Gn~ZBebD8f>vJH_P6A``B2!Ml?4^9tlpq`Vz4zX|{T(rkc(8i|&QG>U0tilWjq z8%;W$4yR9^Vs5s@2Y>(Ly!OU%UViN~&ph`sAOH9#XwS@1YEW@PWel+~q*;y$_MQSr zlN22^D1*U(apY+}CTPX9*3(cha2RVCkH-iEjb?*>Zvglyn$ZSRYsO_sd#3H(t0b(i zt$Te<6eEOxUll3PKK!b#YYc?!fS4$XX}4Qkx_pHvKJowDj?aJMi#+}O*ZGB?_#wXkn;xdF zHGlln3v85z8;%|2AH4HHQYF~j-ezg0!P=FptadlC1K2m$VArvOn6hNM(Cpo}!rI1b z{KIc~8#9d@{mkoZZ*B2&?|YPwKKBM+J#m2_c-Lc$27R9S%F{#`?%cb~p7*|;fARnP zHYc9>8VB!t04HNgQ+xWU^V7;JSJ$|C?=BAQ-NE_(2%~F$^3glkzc|modg3W=+q1wg zy!WmA_J{wH5B}AsIdsPz?78J8nvEvoevfzEcPszwXa858f9b2d_R0$^&LsT&KlyQf z?ce_w*82sfELfav@-P1BFVG)s@ys({;L7DoZhm2jkAL$dhHj_lb}lc7 zRwD^OLd@L44x%Wb-`isMzQbgVd3NsHO|Q4j=~KsPwP#u0xsT4)I{nTXd28P1Oyo_p zsoC7xCQdTCTWhTB+RvWd`)D>Ywzjq@$_i7LBw3T$c8(Ae^VT=l-?rXt0KNfM9LLTH zL8Sy%MmRU&HZ$cGE9vPi(X^O$7y&U%trc65x6RCgPx{1vKMvKonehCbN9v{X1*pQ? zH`dlS2)?-X-r$K0{^`zp9#5z%xFE(=a#}D?#Ih6g-+Q+EqEZB*YOReA`U+@z8b|Di zJe|QRK_hZt?X+n?Kq|zPBd!8+JPLM}lLAW$K_&%Gddf^1x}@58v0A>ehve9U47Fn> z^)`C~ht`fbl6b($1%#1YyU7V?C9kL)LoBb>1` zBSkBLacH6v6pcXNl0qP}lzZ>E4QqWtnncQ5uWHY|kEEPtC|D`U8;VxqeaD3mw9|mAY z9L(Q%E5_xqlEw}doQ}?2+2YI>pJc7~FgHH*2r6q( zl@(c%Qt66D9FrsoGUO##=ZKPo;pQqV&QEnNNhCRZa4(H!gYB&jmWH>gw3fxid9o~} z+v`rln;LmaRU3co%Nil!_S=t=WI3l!o+59ydGO%}sK*7vvhwz)ae_96jm>R@6dXRd zm&1o|;0sTEm8zZ`7sLRS*93n~5l$&n3 zkw&Y@k;6Ce-uJ%C>beqJn;W7mD`%=wv|24@X6M-2zDT3#1MeD*27}&!&h{2{Su)>D z*szvGua*>=vBuRdl)~RWV@K@&cpnZH~YE61(eFjvm>~?Z*ys=UumR zb?ra!=%a7r7ys!m@VPI1&i%ws{hZKsMIsZ*vL=cXF927HTI&E%T<2d_WkniNp#>tK z{Qfzyxv|B}tk)t9t=brm9(u<*uv7l@6m0f(`n;xQ- zC0u&`G)Bgp-{{azV}$fc)5W-C$I?9aJ^lzTZD0&U&N7omTsU_IFx+$JgWPlHgPgl~ zQmk)n5TQ}JLMTT)9&+)@1@`SezytR`id0hk>7RYry>{{xGM=TsdWGSInh3-0!$-(k zZK`oWJKMwezV~sy?V;OQy>^-7XU?&;)o~|IoE0y;_zKNN&h57zcGs?476h-}C+p3f^9`_sjGTxfY-PP@ z63@S`f_QOSRJ-fqR5AGzivL1ej1yCze+R)r(-)c(@vY!`en6xoQg|l@_P8@Hp zhjs}F4nkf#5XtMl@lt?NfWTY`r(h{>5kwUdFLn5P?W;|XHsh%vQU$+%grDR%jf{K|ZG}Hxv1BS-7Q)k- zw6O^1aK;zQBQvqnoH#!Ok+Zw*@$Yj4B5$GUg1A-&M7N*9~AA2#Z#BHoUPj;? z!>SHV2h;RwZA1FDk`#K9l zN*Z}etC2G7Y|@^cWiaqgGL1%xP!W;zZYBLefwhiWYZ|R4XU?2w)bG)1WGE#_vy6rL zIm)s`3PDj;zEQP~R;x*`*XQ)fQ&g3wog_($F&Y&q8c|MJ`yjZgEXm@Cay;T|UwKBx zNlZB|(Yh8@t(l*jV|KQU5ODC|ep`)4(wd4iR&;tpKaH#^l#)bIgi1WssMaAff$I}j zZ5*X`!cR>)$eAVf@83zWb_ppRm2=o$!66h`HDvR(E?rl%I;fc6xrcWgyNyeq`XVP@ ze}gQJ*?6@^Im6qJ?&Bwa>L=LRyvoH37g%3kCreX4^2EnD{@SZVN#-dTNM>edP)bcT zA13H(hNFjh z3PG0V(`_V4im}F<6exdpx5fvInc5Tigb1nS!aD?IdCvO!7T^1QKf?OP7V}Fxxar2j z+^eairV@coGbV(0 zR!S1atFTUw_`kkr2bdHdn4**jhi$*7g=zma)9FL{V0BHdjgVHm&v?S1(^+VR4Dw zdkiaX7FDJrUh$d{O^t}Q-m~;K?rPpac}WOloI{{q~gf)or7zR z4x-4)`r=bS@ZK}8S`BmI;k z?6KN-DphTKc0y^qSXl@`#dS?a6$*C~s6Dapsjw52KT-l~ML@PKvGA0WNx+sd-ZE4> zh+<#-2tsgKqP#D>4MAH%P}QDiiwf3++HWfpF&f9Ptf$CxQPy1Tk6CDDQx~3k@?L@F zgS7}bv9fdwsxYy^^U)Q4QZ&+*nbe1vB~lQ@5vH!`l!nbw&Ayooa8%(u!#OnmobY*N z{#aH9#@ZpOidad;wJ(yQ!0q?vxlfJO#(M6%66CQz*T!*9Ph|9pid0G}>8A=4OHv^P z))}%m=F4CB620}SyzM>jBa(8$MWfJ!DU1J{QJ4TJ>CayrWbt+T+F1F(w#m6a;gP$* znVtlir9p#Z9pq9@`TIIpzqS)aq$H*G4SyW$eeC4=vCeCEgdhp~WUSq^u^!Zx=KMU1 zi3DfpX~?8^Q%PlxEla9$OlMpY7els&EtHhB=jN%Znk3D^Xrf3_)`tFI#9%O>)oRgh zw`esR%*?bs#~wj3Du|PmygkeEik~0}y!Gtb<~CAF@@A8Tr3L2ZTD077%*1T_?`X|p|jA41_GW+-KBA=Nfjw6Jv5i;@nGKv^hldz5a-m3RN++M+9#yu(`3xpg&;m?iB{Z5j%J7q&+iB6iIJmo2AsXPpOqsQVa)dZf(=+ z<)}!pbN4Q8Ja&{cR!Ava6h(}Ng&6b)Zs+cuZZI6lh51>rymY`_xOj!xc`f#6N2fdB z!i7uh-nED^Fm?*56nW~1;@IC$oWCP$C(y<*zcA17*G^DgU1#Qw@8>gL{Tl06uA+OJ z{Pf@dUS9q4PqW?WQS4df{`>Cc$&dai@A{6vhq~=fE}l5f4ZBt_&eEP+VDbqx%RK(rL%jWMZ{yh)p7%vq5@U@aiWSe%d^1wub5=IxB!Ys<-MlMvSi=h9sJV2`sZwIZ}P$a`X?A;_`(;zEI#+SFL3at zTjDyZJs%Gl~xwHOj<;g(puatR_5AVzP5(e zH47_yIK8R)_22mrvokH~s${Fvr?gJ|?9cuTGt0YJ9cr$1N8k+q^83D(&%APmtJ_^} z*tJZjD4AL7a&XUXX4^BgcJAWc_Z;P&w;kp$zWM@HoFStzQL_nA?5R|Q`$zzB#&yNJ z?mkMZ(csCKj&swlogCV`o5u4ec;xomc;Lo;T)ehMR+oIwTkhuMwQWB0>RC)(6HEB( zzkZT``y0Q-qmSIr+S(>dJ9aYDYBK6oL~%qUW1KU5>|-Bxc^ZqY&XAX0euI$_#H~dP z5XT8)JZ*7s^@=wF=&TXXCa7Ht^acf2uB}m)B>+hrvA8hDt+(DuGf!Av-sPf5io5T+ zo4fD6pV4RwYrN=vX=w#rcIl3`7#2geI~~fhM5vgVRudr*m ztJNlrCEd=ffSrXG~#FVx5*2|F$)zYMrdUO5v>&*t>8(>Kl3n3KJl%AV! zJ!d(VlG0cbHO&b0%i+hD1Vj|CqnbVdnK=63IsV~=lgmI%#=0T+s~Ibb+7eA%R|M07 zRmkhb{{-<*l$cs$hB}m@u6^K@@Sp!26e&;KJPt%oh`rVQ=3f7vw@oFYfK%E8ijg&?b6D!a8H+Zjo z@Z4~m#Uh!{WA8*^E#0D~HXhlowMFB(?#qpsNJ^4Okwpq?47HLhHxgQjzpd0}5{Ttb z5*eIF9KPY3q&kO4DnA*B{66yx1TocN7~`h)njVceq&V(-_#wKL&!Q-enFhm&@Og!k zsK|epHIY-ccF-Nyw9=R=gzv->vQS`DVHy%mM0r3Q1-Bd}h$A0br~bzE7)vj-_t6d} zgnxNKu#>(?noP9-B5A$7ZxFl-DM|gD+|!f7+)Z(v?nelIi<8i#23Rl#Uj zFuyQQzuy%?jeq2ProV(tWdPtZJG$8 zG~w!%RR+TXp(5fWCd%7r?Qph2O6jE4SYrf2vbwej&Qtk}_Cn`Qcfhr^4HkFpVJ4Ao zTvnnQkE!Ysp(4t0$@<1NSPw{adjkks5)+(lobY;#!C;84YKHv|qtZ`p#zt^?b&FhB zr;Q;=V&Wumqv4P@A7Yvu{PVTnTs=ls1YCMM5wiqXhVBpf7B zOohMpjZ~yb;udEbVtM}_4(wXt?T@~V&;RvjncKC%```B-{^C=gVRc;azW2U|Z+p+X z`23fj2|oOl&o+^YE9WnAY-I-krIP0kD%I7@Y1YJ`77Lk|gnzoZ3%Nx*d=H#=*X`u4|$= zrmAX;^&JuK`vD*J!NQtQpLP{EqCWB$YAO5#L z#Q}Mv#k(GVjBdZnx4iS63xn11xZdH?R-ZGkJWoSeUVG-VjD{PSd=LH6nE5E8 zyMCDq+aq!8-bZm&L3ewbzk2p%_UzkF`{sLi=DBBS^+#Mge}O%Fc5?fD_wl6@S16u& zl}8?XlsL=zPhWbCC!RgQ=GaoYh(Gw;^CU^kOJDgSYZuP5vi}A;BIlzop5cYlmw5Tr z*SK`<9L?EzZhzoGY?9#c_x4I#MC51}T|V)|hnXEbOq^tFJpV;bbPlp{>NV8b7B8-y zXG`t@^s>hoX480&!$tEr4(d2xZhv>Z8f zfZLAU%meq`$%`+&!sov5G~G@QDFwZLpWBYzE_UxaFfBO_9lVwCc$?MLi!|Ev-hE66 z27^9Pq!#?)uMEsKzF!y%au#W@4c^eP7`Pps~E}R$~HXNZ_bK zP??n1(c~&57d!a>+e3x|&~QDUK;oTkz=t$pj89b!^qAt;?h5fYR` zfu@a_iuDpD1MSEA%a^scBlV(BJ@vYmQjx?8t+n6JmMP~P>u@48X85>yDFx0NqM*-k z&TB?ptrcSWh+>X3B#}n@W?TuM zs2nm8yhg@5PDyLf$_qUw$77NXO!&UIzz?=&Iz3U5qA{*<<1xDL{nF#gP#KNHA*~>` z1(9-GTiase+-dH54gfkjKy0=sj*7(C>a zbP)CXCKPLlk_0KGr(CMYH>uh%8jWyuiLOevHn%98;`qrEeEADc@#>2&k}LS%{^hUm z`iXP&1_i(S2Or{(|Kww+H07on_R`(%fKYVS);N6d0IMfY(ChViZn(v-|GR%ftu+@e zUSxH3l`ntc8E!bRmtX(4zsa~NMZZ5F3;~Iv7_Do6o#YLM#fZA9smpo_JWNu8$3?-g zs%f>GL{UV)KOl}{8jS|yvczaFeiva9&}cTu8VzPxHAVnly9=BY0|%~MZ(3F8F6`S1UL=G+2(*=A%F!|oRE zcQmKar>dY^efBZxvTUvTpa{`m!1AxV{>ym$&V>hh6~eH>j3S-)_Jw;kK- zs{R^#Voj-yaAm>a9c_{{#W_otA@92V27c%Vzn%a0cm5-`_o_&Q*ci?H6wIbfRPGcUr& zKf5jF<$3XdpyG|eNWO8R0n zmA+Xq_-)w0brt*#_aA&CQ)!Q``b6XKyAz~1(1NTsK6y734+4jDUJyMtP-sUZ@>G?| zI&|PbedhR>R6nMwUes^@t@bNfNO! zEEv~*>Qg$1k{lx=tcpnDm^fCRn&muSf4QA;{JCej^x7+Ad5)D41o5`=RXf&s4bH^j zMTR0DCR!AMwb~bsLg0i%hVLyxCFYzjD_x zS&XjGwZS5|`{<1<=7RH^Ypic}iLwSlmmY~58$SMt&r+5ZM%RA&RcV6tn7H1qPcCN* zG6@GWSPcjjz8erl-b&Sli#{}3BIqgz=V6{EL<)q8P%?x;VUbvf6+*@#DOM0A35kN4 zxmjeCQr9(DOPnS&@{~mRbJBZyVTR zr34N+LJl(3G%7nD5BBw+cve&7*HXR zy4E$iti4V}KwZ}~S}lI+C;vXu29!-|pQU zK754V_|4yeYRIj(-pK2(z0Q|D_Y|fonE8?KK#vP@1!l0x>h>l_4(#L9*)#6i`l{Hm zwCJu4M%;M#u$XHk9RK>$EHsj`NcV`Hr`Fl zI<)bV*(8oglQt$$z&y=M^6Ke}q28ZDLzg^EgDS_nbfZKrLnZ)h%pH50sqB zdH(+d04;+6+E~TT#d(rPA7@7+VpP@)OGB)@yNt1f;#h{F*mt5zKq5n~1tK&vhD=Gu zla#nXV{(Byq=augYYT%?BXvbF7~!<$=ACoQXNpD?apRtSq)O0CB5pghmsS>%ROI9Fy{Sn4iP+70j z5I~GWI)g=0iwGq`+IA2-7@-hS5(#f#dws6p&kcw0nG~ULcE+NZ=vgM27e1)W1r3G3 z3&zV@qic_NTW38DtFF;Tqjim|YlL+qjV5Y5;OwPU24mx0c6vjqx?+B=MV?1UnUd#= zL~)E#VtQSqaZD6>ANN=(qBNu3%3T)wYrq%x5^y3?iur|kW@l$yvylraWtjMQ%hWWE zh?5kHbV-~LMX_*FdeOcMD7-Zc2R$c*f+!NgIh2ZAoW#VDqLC${IWxZ$@MXtd{u$mV<{^XM!KYNi8F^xvfY_kEhDGZoipM!^1cUx)7`PJX#_kQ>HnO|CAII03Y)MAXG(P;RDUsL(%s}Q7FN--`lTGMDWSYKNs z%QMn6WxKOYRcq3uqO2-D@SIF7N# z(r7j?CWM7$Db6?sy*_cEB1TGi4TTV#IB|v_`QaaBSZEhDXT^W}laF!uwmW#=`*(s$ zu?xF7{FXK}+Faf2GSa@do?qV0!rUx}_N}e_nU=4$z&)=BXjn@W}#5dSho2mXu1}C_sc8lNq-9MzX2BM5&G$NCZ-SZ8$uUrzp zYb!r_=na`$n5V2NbggNn{yyL9by>Z70b_mEPovrP)XlP>+wGuzOg6%mY;SLdac|7* z%nZF=2j^;r!x2I_dYvueC}LrL0i0zt=#b?N7U$-@cB$WGX>ln$Uoubq#A6U%Z}aB* zyVjcxz&F5Z#L}aq!Ij6@$)s6O8bX5Ub?@^DEvKlh4_FEXUQBTB2}t*3DF~^+o|kXz zb&5eOJ?dH+FRrwKzTyRt9^n_xJKUHcw4LzYQzd;SKtQquOf4Q^V!!BbXpy|0jw+-t zgoW@yO%qE@ho25u_cx{&Od1N$iI&2DF6YAM#nYN<&3}YIwT z&MNKEX@{qcDg5iD^iEKd$&A43SgiACwMJ5Eug!?0KQC~WERz1*a*ok(fUp|r47+p1 z14owFzjT0uJC?X<*CJV#A+cVZsuYNXTKn)KYb`VqoU`m&ywP*^>k4T#@m+^0#uXP= z*V*b1S?iAYvuEGnLU+h(uRcrX{8=7($J@Dd`6}lxUB)RD1i(HCHH{-uDX42rB>fm) zh=7@g^Vqju{=8E-kp9-|ti67%DuoQ_J$OO56_YTg0H`}ht!tk&Th*Al^7@qE=;NHj zS?wFsa)eUSzn_fQG2dc+eUn%!E?m0CowwiYzU^Dzg|?PFO%Q>a;}D{(YLK34l{Xqw zDpH;|P?1OR8(Bu4W#Am0ZqJqFSd2#n+B#vK=cr2|8I8tnW_E^yhY!(gHW-(h%U7;3 zt}4=I!$oQ0BH^&s32O{XJ9fD=iA1C#XK{>+u^Sg&=sO-)jEYqv6(Lp3`uc`TW66b$ zZP&;%mKNv8^M)wKrQ6;fIiofG!HAie8Mm@?7gB0bR~0%luG{T09v393!#G?s&lvT+ z15%nMw%hNEs`AsMEYIBH(vmoF{DLdS6;YPE*+%Xr?l}wdbIv%#u&mvx)b%w(s^UJ}~!8yv&h}DfQHcA*2WB&ZppBBUJ78_SC@crNRkHx?F z&EMn2mygr<=12Md4}7cm@Drcp<(FUK&`q~+{^Uv0yor;FD4-^PeeN~3Pd>-u$_`YN zxJEMuJEz1&PG;tIolq880WR`^~Nkx(- zR8>WqrOeLGvbD864d;_mc#4;^M6nkbSK2qH4HY4=40^o~&}V4Pv`IoRSY7MTEJ}2( z{e;K)1mQS}J@BJ7o15DlIdp(O_>aHM`qqZ{{r~(2+;HFqZn^aiL>zJQT956qrovks zSA!0{)vN4(_gh$8Sf<@-BI_};ttQJmcF~+&q&F%t)*CcD`pARs()r8c=qvZ=8n7XLTF8=+wtPx@Srr-Pxqt<6Jo8gnPvCRC3fssrrpe$i!^d^ zFQd{R^%zkMJ)O+@ER`gQc>UBRvFoN|?*IPfUlo_mouk=ok|r_Z(gtmZAYIjP*o-CYnQpUx<8>|q zz%-o8Pdvdy)I=-6M1!h4s1^FG~0OSO`HJ$J8PsvKDQ< zfZh^gO^viQjszLUEZusH!Nw}Z`epj#k_Ya(jg_e6^%tLKVYb2Y;+$AqT6CRmR}`b6 z)7lV4{~vqr8D;5p)_eZ;yWezjoeEvmIjdVzE45@vmSoA2v$2tljT2xD12$u_xdU9_ zUc<#^hB1pUz|1vZ4A;JZjg5_sur157a?1)Wsk^1lxw^Y@)v1%;cZd0~_c^V5*9`Mv zzIe@Ouhpwo^*MFI8~@Mq{6k2R#ID=wcVw+ru_M*Wuy_lk)2PhN&eLu-g)$l&1gL&y zjnQ11TM}z0#!%YW>5Fqh28d?6$74?&V05I))qD2XKv-Js4$CJ_iDtV?wOk^SfzSlD z(dvji%SEr>rB*81$u)H$5Olj;ly>0KiQ$C^lLGULO`8@{(d-$HpFB^avC7Eks7Q+? zRIf#z_3d)ACwjfUjU!1hO>C#rLBd*yWW~;y|GKJ(0;o={Qj7X<(}> z%fv~F2n6HxF_sq=up*$_>l1|$rDBmZj-BQU$g|9K#*n}%UAySJ9K&(Yd3FZ z-@a%0=KYUwX`#uwZR@%1wp*A!cf>|gib}Zx#3XS@eY9prDzzYvq!=9?0Tio^1!iV0 z5LDK1`0N~ec3;8G*ImuG9($I(*X-fuJ-hk(!P9J;nshZ@p0juFbu2elky28tk21fo zL}1E&7>0*NLV7K;5`d)lGf_e+b*tS^l)S+7tZ9pQ)X zeJk5GtmDjui)>i8j>c*OYZZI8tYcJWj2ndvETa<>WG^0PeyIV%V02F2?<1_GK0Zm3 zmROoQPez_zsny;6Nxl*U{BNyS3V`o}C3LQ35Q6ZbG{S+oK?cA8 zd=do2VdxwnwByhV7&`UztaV_}gDZgp@y@l!dOo!SV1a*vjRP{}(x8lSuc0kS5B{yS{-zlCU@43BRF6OetOKJk#8}JvkqRSMUr7K| z3h~hWX3&|@zJnk5*Vfi)3Nr*k1cadz1ou2|S;&`ZC+uY%f-;Wo6$?l68gRvxh0tim zQztOg1C6rZw#H9Fa^q5obK@A(xwWKWKq#$GAr>^cj)&`LoGX9&GMM0?KvVDe)9Btv@3 zOaX*wav_~RdTW(X_gPzv_@O;(c-^(zxq9bLtjTG#+8n#M$afB3;MB|_3*C%M^D8WN zdl1Dmx{9uWFbtj8+xV;r84?+%;YcF4b4rn9$K)t$iV-*OSkK0KfpQ^aYGQ(In>O?M zS6$2TQ>Xdt-~A&qI&wFfsDw6#t~HESO7yY}6-Jz&nPqfrl+D*(ORL>-;KqyF1p?!b z{Xr0!2;`9R<~D*LBtQrYBJekQgEAUD;Q0%j&^2(yTGnp4!X^mmDMi8LC}S9#oZ{G1 z`)DmM5n!oSN2!jCkfaG)w{5Xg>(^nlWp1fKv(dDzUQQH;L|T)#R&A~nD@!ZFYE7n; zsFaGtX@Oq1%ksjaZFhQNZf*{1G}T&_ex`^5E7Bw)juW1H`gs;li-ACd*y8 zShZ3V##+Y5M=2K*)~=ltM~E0N zP#S0+gzfj;ww3_|j&?OZF~*iH8xTT>nM<==x;P`00h{Fl86c$du1AIx;*cN+*t>U+ z*t%sCXHK8tU+?=itL+|nmJx;_N*PS95NV1fVEWv*`Q|qs6jr$G2cvSAO%l59xAnRj z;uIN06e|_tFeC~Ca%}=P#Zf33bJqtxgs4w4+vrj(q>PjcEY8pIws(El6<%?X`@XY} z2OoP1L_lS1igom@J9j!x$DVnjd`SiXAbX-+<~kDXU+=fDduaO}tt&R<&Lt#5e) z$4;DNd3jL;0WR>q&~v@+=9~+NmyB4MQfJ;9j6gV zA*Hq2LTkh5Se;f=kY_nkMzoquN3)C~;y6O(Inq<5q^Fpbs}%sG<89FCbV<_07rurt ziAmCg+1Yty7;wYh8|il2{OdQq#lw$3jTUYKvUS&PRw;0Cxy2ou-@|GrqcS$ZHy(U~ zN1obG6h>^?yjdt~`Q-2a5%tkg-t~bo>h(HTZht+W`^;xJbAEXrp&yIs3o~52Fw5NhGQ#gO{Jlg3 z5{$xV!$`e~PAh!-;YYdc)|)u={6XgDmU#5hXGmkmg%^RO)yXi%8IH7j8Hj*V8j-{y z3o~>4)|=mGJMES@b>=*u`P>(%Rf?QBH%%JHY}>w_cB{poeeItKRS%tKbh{mj<*G=F zB}5n!2#YfAUL<1|9M@Q0V71kwQc7sHT9j%NEH7L@h=7r?Nvflh2y2KV2S@w;KJ9js za;-)$O(<7K$a_tcGR)0hB8n4gwK^hZtQTMkdLE<)GQjwgEHjP+ueBz5*)+goU>7Wfrwtnm zMmsLL@PSPJn+C#tuz`5j;)I}j==JTx(cBX+Q=p{tNzcuI&g6O1!h=}lc>2nK*E+LD}j&F^bo1UBjDhyqRmZtfyQoGrQ8@pB~@O^Jix{yWHW_Vv8Js zBEZOqFia>`s)!(bA$5cCX|5 z?Q7YwX)Rf=%N1KT@~Myid(L0H#6Lasg#Fs_)1ol3fiMuX`Z-~t$inHfY}~q)tkdDZ z^Ut}dnKIvwl(sbgF?uFTv@VSk8Zc`s6xiMZ)v5l zT0Mk;VLSnU|)5}>|Z4pN?#d3w}sG_ed-EP-UH+(=|QUsGzE<`LXHHd=qtX(_B zp~I($(jwXjOc)a+l2AqiaWpn9xNDnIAiSO?DIk&*p*7Zvh(#a?N+tS%q?=oi1p=F) z`#rji25kq^8RYcuY?{Z*8!b$;u2exF*k#IJtrV|@F; z2l&>5`_OsrT-2-+pC{f?CRYj}+;I?vA&ZMkj{9Fo9EDBFAr+`zA937$At)45dVN<+ zq{R|pm|?V`pY$cgx{R*^@eEw?>u2!LWIzPks z*cjt$#+hAgaOUDA_CNhBciw!1=-H4X$ItQPQ=dWxF10vU8k6_A@9XzNobV$b{1HC? z#ee3u*WN>U%@p?^IDssbx$TXwr!6J-A39CD(csjPqtqwIdEkX(6pJOQBO@F;dX&vq z>|%7|Hu}E1XK<<1)>>p3QaO8)qbCk>;?O*cD@}U2qA|PVEN}zqT|DyPxj8mIN~b%A zPOD5zu0_g-o!9RrId+(j{`3c^l~cQJYD&y6HTm;T|1AfPoWUr?mAiM)Tw36r?|3WM zT(^gR`tsMAn4Azw8%k-y9k;#;i{Z8#uVsF2fs@lST)H&FJ$K#8hu-^kYLyb-df*}M zyZ=#^8XecD3Lw{tKseoo$=c|wParJw3ky_gV+fNWg!D8q*9hshTC`d@QIs$?K1qFa zY#2V5Bt=x-CybyV1Q#z(J3I175*I4iyiXWN!lXnPMlOd!84#L&ul@gkzW)EcUMT>+ z4_0oiRo+2F27?Z4;6Z}J%7adH<^=+A;HV!1j(8fl4r9-E#hu4GBvK*+F-%>R!R4Kv zI~O~^T}uYId?+6FG?hUBnX<0qA7F#pQ{CweGcFPDR2$ClrpRWNuSOO5%*(?rx$b-O%dWCh}|5_m? zP7>PPE?MqqKgL^MTHoy#fpnl7cf+U^V=8Hk1)7~6D?M*3Y6nTpkVLvk#AU9;j zQV1pGI3@`MmrkD~Dij$RA7{Cfkw$^@cemC%CJNGEu%DbbFqLi_S4+puXJ(9w$qD-0~gK)1EZWYFX8tJd-M+xN0{?K&FWHV?mel80V8&4CMx zG_{~wtr8|BM%KC1*Dwg^Wx30!zz|sL3sc99wFBCXKYj;}C216R=d6%QA;s7l0?Tri z@}EBa4@{+k_x<1-xZ_pVu_Gz7IzPu)waPDl;N4==cOU1EAAFH$dXr9WAWxlFN=)^Vtfj0vo{ z?0O_!k!#K6l;q5~)Y-h>0|o(cAft%sGpFfvx^y}nCfBbgsnwXOSGgo(7FSwCN$3g< zBvG;C3*r!TPFSph(Fhr0g9u?1C};5*NZ~%e(V%jyu_UE3c^J^}X}xEsXR$J-A0$Ww zQc4IT1dayQ$qYtWjvhP9pnJ+taKEe-Yk2r z-o?gE8*Qimh)~)P#F4wO=*(>==`BNb?kr04K43}8RkVzT?q^9Hx#>j=SIaesXPSDZ}xZ1r{>6{?^+mh0f}9 z&J_5U?>vJj*GQ{1Qelacgw;j^v$Tj-Il0Pt=+S)~K751|$4{{Tndf-mfd`0uu{4-G zSuA1bY>~^QGR=02PP>hi?l_IYh&;61oK7tmneTq;!r~GK`#amgjK`pO76z5zBLneCiMW2(2`| zO!E(4xR0^%F=``qM3S&-Qx=vRG#6&svuhjY&z@uB==E$HFS7TVt9bG7Q4StHO1s!3Df+n+QJ+5i5}S7IroL`7E4`ddYZqGS zCxh<34Yf7v>Gu@D$|w`n4OH4~=lmsvqhUq~w%c@EQ_-Q`%pFhX_-+7FOzWo4F1ax{C#X?L{ zC?La#R=39^k37tt-COAPGQv<|Y`{vhX-6t$q4PeMW-by%32_{wvOaNAAdVxNjV5uS zN?It)Cn>3b8RL8-%bmk6njd^AjoRKMi{tq4&GbffOs4T%B2D!mPV`N0q>yuKh&lA?mNRG<}wU(z%syF zf_lDqW-e2C2A?I8KB3YK`0b85BXEytFD4V#I%`Sm(o_Y2@gZq`GGL9x2nR;37o{5O zLb)&oE$|=<&($_)?F6XOC$#pB1Goa$S$9C!iEq1lU|i!imSqrn#t^WDp$p)OEcBHt zD2i!J)>`G{ONZFL>k339Y4^1Y?-H)akfFO-4~oA+=(GUe{L+``&tK&F_k4&TjGV~J zCpbGH^5qaTS46tk%e1Bv#Z0d>dFfxj3L{gz=H2h16iae#2&MJSR5t<8%6hv{2W;X{ zl55L1zxoxTIOe)L?{<94ARx5veT_Br^ksU_VE&Y8hV-INu2Ah3BQocmS8d>Zcih0_ z#3VZ6S54o9AOf|XXA?N{t#?e^VteS&aipqDF`7;N45 z99V}ss*+E6@Xk;}ryXa;In)x=M=I>S`yLMOdz|0?^UrbRbqDy-AABRPy?P6Ax5sMx zBJaHGR!k7`SC74js;2Ss%(gQ5TW;JkF_j2KwZ z4~t=5R^ZCO3AK$+wNGTgVke`QDMA6c%7>IAD+0DpOwnDOM}#4{mE_BF=w6poCr=~7 zm>^1kfWT7BClFm(ZIO3cRBIyy z!qV>b(EYxn0U3jknG0X@G`2v7o*t>0om+OVDIGlsmAm55U%&>B^>fYr5AH+Q#{|}e zv{|Jwd5<8Dutp(pQ_modz$gd=LPlr=r zxeH9x>x|SYtel(Xsqa0;{K7of?!A#+yLT`%H_toneKWuKv%knU@Baq>?$;4iFmwfM7`mbu-|P_rt&LA1R;*jMhR=NZ&&gHB z7r*occJJKDu~XBCASNxAdG6#iDwtuRtB8sf@w&V2pquAJ0wy=?~vVM={r^sv^zcOW0Tx+(@i|~;&CqaU6#s6KJ;Erp1r{Q+#(Z`6Cw;C zx02%8O|0FpkqE_xO&jgRtxw)++_T_rWR%6NSDN?*dQ;K-4`x^zt_Yhn&mZ`T;QS zDC<4_8IDqiOdA2MTp@s35-|wt0)`YDWiFS=Q6Ok*MH~cnxF!w-Yc6)>PN1um4!UVhAS*_zat%OYI?6hg^(y-JqlG&?=Qz|zUJqxOUj z;P-On!qKEedF#Yb1kNQz8)Pu>lE){yIv}llM?DS$GOvyvbp5q=!4bYNP}XS;GVMFD z9xz72VgoSB(C+sfSo0mKG>%C^r%z~S%4s)nuNTL$qi-4aUn**1N9k;E#Wu~=gBj{%t&H8$B66Tvd*3{&XvkwmRYTbzJ8E8f>3wM=qLg(3LkEPWvh%Svz&PXAmmnolS?21b%2Ap>> z)TF08Pu1FDr8O(Q1L#D2um(bw#54=K|w|pK2Ma-Twt4A=U{41;fHW5MZ@(;L;kbRzyL7)rwrZ za6E0CcraH!C=WwGfWlEbv^M0c4f?y*(Qh>z*IP(*uZ!th_qx7wIiv*oLRhAWb1KR* zhDVp^xgWy@Lk|5O$PgO@?p#*NQN@zPaqU&^UO&>Cr6e5YW>O5Q;Dct%ibf!q8n? zgmV|M#t=pcvRt9xYN5K$X43kOy9-azSS-4qI~_p)+J^_Ca;yy9=kXzZ!a8C2fRAmB zWwq6DfkJ~$gs;l17s?pzFoo_aFLDY%SX8?O)(o2pD)T#iSZG?BLbLn!d#GM}3z;$4 z#tKa>DVjdN@xHfGO+(t9F6*Wy_~QMK@WQdv*uK-GEH{=}SXyS+)!X^tTVL-R4u*3# z?c%=2_p|@dQBEE_zz^JfH9zrFKhMhYB8Of&$l}5xB9MIT>-Tfy@Nrj=$dEYl0c(f> zdkUo#VH7&9zS8uv{!o0|&w7MmL~W$X($cb{^F`4x`FDAF8Lcg2r4p@nhgP#mr`@4Y zED%UZ5=SVdND3)NJ8jI%TeD#plIIz6pq;=u)fi6+ib6@6CY(Jt%?CdC6SP*Fq{R{! z_s%miKE^fI?Pm8CJ9+NZ-(%yHFWmnaU%vlQq!6eeAPfScFeJ}4LiG_+qVgOONKB!E z76BGZlBC4max{?Mc}++TpP%Kq<7deI{Uq=A*t33|-~Grhb8PwoU;NjHc-K9*a>w3l z_~S2rgVkQfd){~louwrnM)R)My_&64Ekp3Ju8q|j>_|4 zin|alvtp`RV5!w*wVOHTzRql#Ztg!cnYuUJAlcTM~;ibhmZ0ff9uyc zd*-y$I+SZ<-6oyZDrvDo5J-xp8d;XnT$x2C722yyWSu2M=q6U(ZjZ)ln>C{y3WX9q zl|c}aBniz{7h?l@{T?dUWGW^M1C-J)Cn3DD{=4-`0r35>bRIY-5Zn~NgT_G(AaGqj zV;$$(dSEdCRB?SJOI9iJlg0i&SvU7@RwL-28g*as2@o5^$QcWV> zbmbw$YAI?lzG@f zU`d7WNx{xBsg_1;xb1For74HPPYxXD&h+K!Pvi>-ybY*Qnw6DBUcJ7`N8b1ruHCws zeaBAo$*+BtXD>FeNr6J8&V+B1OAIoKS((2;nj{FFbMl4f*n87n4jezh_|_dPDCc68 zNLR=@cO<8aK?o`V%pQ3W18mx{6D6Gx(U{BU(12PdgEYfML&}*(Zi$Upy-dYVmpxdYJ zgNBi({TatKCeN|Czvf^-4QN1aJ2;mc5Za&ydYm8t>$>`vt0TWLJhjc_nF~7et~JJA zWUMc|h0rLic=a8(ap!w}jK6v8Icg%MYI{f{s1+hQ%?6+U>n}1sKFX1o4s+$U4gB#( zevEHE{3I)lMcauwEXsNDL$|(#M<4tKPd)XF-Lz$^xa)Oqp;WDM#jaf}Haa}}(n&u2 zvmYgv4$KC^aB=!Pciwpid#}HNg9o2?dY({XwCCIVH26ZPfXWpC0a)d1I3w3IDijM? z3%y<+83aU8M7QUPL8k)vVf9KKoz(jtjF3?0fbFzWdNV)^6IwOY>b`bL-7~ z^oDEDUdz&KwfX9|AHrI}t=C`0uFdP|=kAzUSZVOBr(eWI1#A@2(*~gwQ6Mm$zNM8S zjbcX21#*ACTwZOlas3qQMk}Q0R$kb0g5|kcddri1;0?F&dw=-_!tN>``|)?N@|R!W zhHdNFFj^rYr<#TssYYC`_=zTHqZld1 z+<3)S9yxN3IIwKmxPi1C^2z`854h_!cd~iQ1{UWp*_*DrSv)oK0%wnPsaFa-_Qa!% zjE=E&+fKB~#YnwQM;B>jil|hkx3WqQCZG)EYMolW&iTX7QrWhiPzJPC8?G=b6j)ha z;ryv4%iGuS&?8S03c>YzuVd4eZLBU_qEa29QmHaGH_L(jk27=b7+MS7`@xTR?|#eD z;tb7|6~eR!*3iwM8VSOrNED}Nyz4C&9$Ge0{`961(6v5*jkDOmGL z0q}3ER|Winp1N%3+0&kT=sE4iJGK-fi4cOmcB11z2(;F8bH&JO-hx2T>-C(w%*(s_ zp7P*t_l_3igUrA^rnsC;9QdEY4&aC2>~f2f)3c;ujVsqE@?3d1Y!TLd4`rbgy3Z>F zDB->1ajq)X`ov)~aNn`m++9c!PM|y3&ekUlyYMFWz2m{?*_a`JKM36@HV6d0+_0`B zdHbGCeCL4&5Efd-&|T;egaz`(JgxRAR47?lZSdZA-iuv4&tE_MIBPa;qB=6_5`23N zHjP&pukN5Ga(azrqA+ybw@#ZVO(_;q@Pg%-ftb`XmAG)TPOkm5z;%lT^eb?JYyl*= ziA4+;5nzqmK0+F&m5@%X>k^LLHp{db9!FTmSvNu=WJs3h>>RHU27wbHYvX7))*UN- zYBdn(tk03BA7ipoMCUpCzk7yj z?s`26i8dN71ObB7Q>Sv@ee5ZX$rWK3vA&uzbMiPxkDuZ%zWy*vtE=35=Z(zF&vDmH z*YMG1hrfI9St_HWBw;|VG?`Cm7J+cqwAT7yI;T|_@P0EZ==%%@p_QlmM8k>6po1I@ zDNA656U-}P=;kir))-A+8?ZcZt~zAy@a)>EF+FX zWRm*a1Vz8sNp+KwEA zvj4dMIU#!u#wIsYEj@3Wjb*WRvTjEz3G3EwLYsh@nTuR~%{BB47_CSO3D;b^o1Nn& z-gC$GbULeyj*Ve0v^u{-mSybRv4dW(jWypyWsY`=F+@>FASIo47byd>zAI>=D56v< zp^c{B>(TG^2m)8+37^Yld*A*8tTa1p+p(L)#wvgI_g`o4HCHiGPI>f+ z?~(U9G#6&r6lpRWST%QAbkd9iFCJyn*3G=*ZExe5!>4)f=qbXaKxU1zRh6Mj+V_cfR@#5f`ic-6Jn?L}|L2VaL|3 zJn`&v6f2|r;?Mm8zx!u@$^P#hV{BuJjblbPY;f8(EX6{?+EUCrZo87JHmzZ`-R0Tm z57_DHi{iq}0?k$jiAKnXMyo@=+hu1j6a6fwpXD}=6H%_zm|a+*-I(F7*S(9w2cE(x zMb^(~w^k_@%Wj&BWPEgtwd>Z??sQpLn5VTghX@2|u|%AfDWnNWlG11_Q>|4gmPW|> zPFs>D3C0>iAznUYdS(50>y-lF`(W9mD3pc37(!2>z#5_eTFUxRtp64$560v{lyKtc z0cOATC3b)C=P8Vg(aW7ytb~JRr2mIa2cQvN@V9^z+_(_3(e(c?PhIX6Uc~6hsb1x%lgfuzEQ=2mF zKCi}c`TN?EN`de<+(E4$`2j$t3`yvG((_zn1K~r^T(>)sZo3Y+;-LUxG|PQO8cHfj zNKZMtP;CsMv8?u8;8Gd}BuRk-FCFEJpZi;+?(<_m@*aNXwKwqiGY6?w3S75iEr0Qs zpXI{r0vpCEy#I~&*!SOkt9bmtQGWdo|BB!I<&SXl&JFzRC;m5fY+A>!|IAPFiO>84 zPwqd!AN|@#nH(G8mp=I?99iuW7mMW90ZHvC2#zc3C?EuGULicFafM2Fxhhi%fkBFZ zP=*MdI{+8O&KAxn2l9nGU`!wp{zhnn$n8h1ki`N!Z@ig8ZJd=>hcGan-W3qx3R8n6 z^c0sINjJ~2t!3V_eT-lF!MiaC{?nHq znLBre4ZE(U*={==$K{YNVFv^n%UCJl()0xmJa?ML>*NDE%Jx|`(Lwpa*SJU zyq>(*<87~b72kXEDV})pF-FHH&=$fZ+O2)g|Yt#hk39IDJM@~U~X;^;hn=wo};r4ufFp(rq7(`#KA+XS-*~~9WXjR&cdYydcD5m@Edns z9#WsI^@X-8zKwC97z?skW_06bOrgqBH$xW6#8Jq;LnpZKuixRS8}>4_Z95CCHvKSW z*@lddjk0#_6#w+4FNO2{Cf zSSk{RefqsVX_SyeLoBYeIDF(dpa1-q z7+t%8IFuAi1zMuOJ+Hor2OfToM<4z!B?<3*^WD7h4fpWb&;M7JXV2SL?b#+q3b1SE zP8!V)5QGH688-yhQZ1w` zHCkL+YOrq2xSwQNgb_4*IbpHP^>29#VH}eNpp@HZK@hN_B7Xjhk5Vd^P~|$G`sOoS zKRH5B+{m$1a{gP-5rqd3g)*1gIZIi%beRQ1a$OL9(mX#%EW*~hdve{h0Oe?f8EHBJr43rD8 zdtCQfSzKYY)gmoc2*ZSauS>Vnp;Ssdl`TdG(f>_SFmM@UyJ-PKA*cn4p>ydOIOGmZS*)cH zNKz@twZ;nHxg2!g1%x<3Z9$4*V3*}Gw|}q(mZ6DszWxB7O@gvMVOaPa0T0**^rK=V z*^xTi&sOFO2tUAcQU#Q)&WQ-9DMp-aU!S9DCo{6M;bE z0;3GjQ^p64Ir~CoVYCpTv>VxKV?f4i*|v?5IOm7o@dF$=dV*62o@Mj;N#61Aex8fd zXE=Llj+S2K7kK~xAOJ~3K~yqKFEm7C7wwH#ZWq^HyN5<&nX9+n%*|I_!9B0q!?v~K zY#ggHzhyHo9y!V_?|2h?_gu-Ml7w-L@nTFf*f)W5?vO#?SsDR@X!%0u@&Sx>NxZ{Q zIf1i^RN8kzK`Z5)f`l9jO$Xa}FewUgDafZzpXJa4-{iX2znS{T1npJ}AtkAB^qat1 z;?OzlC}U}M+NAv!zxlSCdBfhT`G-fIfBQ z&-wk2|0;X7ZK7OA`PmP>kBh(eC*)dTk^;4Ak$qqJM}FW#KZV+rp|qy&?NZ&b;{f#_ zkS-B8TUZ3rQ_uvUg#(l!2Bj3|&YUAqIiZxuOrdfGMiHPf1ddBD1X|}*3K3dsvMeKr zi!_@pPMw>j+ginFHyszoSsYre{KU|Kei=oWtdEEj;#%Dmi&(H4o0c#lWOd;ZQY-4! zGRL2LmhBtY@Y6r@6BN?||Hps+EY+#?6jr*dtTZsa4pFg;$ue%g_9k9Bc#zoU{K{|q z0y}r^;&(ssDcVXAkJRZ96PTR9YBHU1#~rsbbLJ%N*$aI1XMd6(egFHhS&NVV_V2K= zQetkkN0vFm-mKT>x~s2Xs#fOFV~6?7U;Yu-U4Jd3<7@cqzxi9f{MGw8ab|{UwTwp4 z$#b@B-$p0|7tfvLW54!G{M<+XN4~f32|oKbpCt?=$4^Zo!;mPB=w^O92uF)_*J`Kz zhzcoMYoaKm-{~-Oewy*EI}uR?%Af*C*BB;uUqw@d)N_r{2B8gErqLqgrkigi7K*2y z+RxePS&kfkfrUl~8x_Uue1lG}Z%?0}78lN(pt;f@t&NK$Nx5n74c!0a^IV)?WYjd- zy!kc?vE}{mf3HYNRX*{F|AlL>xsw0sSALbR{PUOjjo1@E|GIG;qg3uEJgym5E*JUeM?Xv$Mcn_u16+OORV*(rQ>%_3 zqL^<#eF&p9Q&SVX?M<(>!fNik>osEihRxJ!6{HZ{^_n}#vMw(jIc&$LHi|GULZwa? zClu=yp5ONvFYJGgH@*LZWEM1rq*P#LWr>Tkb8Ogg1*%YERmA-B{u4C&Ijy+DlP4~4 z%g#;Qa?O<-JUvZqY=RRDZJs|n$Lp@$Nm?%RPfs4f;#}sWwL_PqD2h0KVUA1l%M_}k zl+%zvl$JWlnUu zVs&K>OvcpIB$qCo;J&Z@SE|)ATek0EY3Y(PYp}}Y9OZ_K7Zw;F9idb#5QhP|GNh#u ztWl(e3PMQiYJ<+|5@8r)uq57DsMpV^rUm>k`<3;7vtB6xz7JM8mVF|L6_y~7UIgeI zZMuEsg{p2@oK+@xkAAI5N+rr8HB_FH`wN46p8K0YhkXFDl@}8$&+(7E_{msk=bBhL z!J4p+5|JC|DorXSePf7&fXGh<0^f0dIWuw4k#&^b|TzRxFlwTL}fXnl~KmluBWv$%jduNHJ;gjh;KabFr_r6J~GO4 z2M%z4dWN^XcLzNyx$3H`#eeyyZ*cVJ2}-ud!M#_ru(U+qz^UnJHcn3Pz{C4kS(9-3 z!X;)dTwtM{kwmTwj|iOWh!E&p4*&*1`Mv|SLR=SnAVQ41pf^*F$7`+e-96!{P7dS; zKpZ)7o-zik^xSOMQMTF=g~3oGvg4}V6pAID{nmZl@W!`LuCJlh?qEC!7_XIxk_4M) z96Nh~UG<3H{qcKIO7np~{UR^UtWq9d!&u^`7cvNZh?o;yW1aP@3`an+r#<p%o@@E=5Ku3Y9Wjwru41(Gzqs?X)*qd5VH}Zi!r1S0ss}!etrt zTAeLhH*w^pqsX~gWH?4F>SRihwHpXPWjU(fb8cBm5kxU@ZG^npLbXKKx4!Ak{13nIG49`YkU&UeU>(6(MpUaM`@;Ei;)mb&Lw2;9GC46W z#_HR-=QTHzR!{NeuYZ>yEfLFzu5PhzYK-X%7x>Aa`f)z^;~!yu@dEXcF@EN!Kg@|! z=Q(`rEQl&-=QLzRz{!)R_`Og5Hb4K-pTm%|b>j!P>#p1Q<3IUR&R_TnK@?)FAdDhZ zmJP3YE{sVdQN&h~XMKbYsZ~p?uC`gdc#iQ68;O#HN+D&WQbZSvs6vU0D-C*ChQUxG zT*Rh`SO>)LZOi6 zv!DJrD^{&SDaf_7vgxLq8M$ztLS>v(OE*o~6i1F7Z7$z9vR7re&juF->beMbPjGQqtPi#>~VReqv;;`XT9bn(js2OifKQ zGd)Z9qJ>ztMJh@4ot>FxcxZ@1Q!}n(Gd(qpFf0TLKk#X4Zk}%lS+;I6DWwR5AQ8WT zX;MTEL>EJ#@CWQK{89a(RNzu7w2E3Ojc06P9Ih;^bKh zDThNxjtZ$vDk9BzO)(ot(YtY$pjM?;oF%F|jH#G>&uVV$T%lGgplLUyvnzp-c6yonQ9dAmp|G;Hsvs<9KQd`2}~Ivy#lu9CE-`v zY#qfBL*vt|T-r^(r41|c2`hDCTTAE!5*2Hy7igIyD4J6awkde^#T^)#0tqqlA0)c2oaTBMPNNlNJZ zx9z$NUKuA827VA?$%uo8j`6{deikE+nVy{yuH#azR=MNOo5^h5%;igitXZ`}y}JK^ zsMUQO$5Bxj2!%;H+svlLtGLjAimCBQ?zrm>C>2mCO%sHYdKgi!*N9_@=Q@-t75p#+ zB`Fk|kuoNz6;Y-~9Ms9CQ`7^AZ3(LNfG7sfbMV7}Fc!2lH<$iDmS_LJUaxHcehpT! zQYDJD0T@8Vx`_8P#)OGqk@z%z&zF$01VN}f zkVev(50c09H4aA?=SgAgnA#ZXnnF_vlE)MC@}#TfzkvDTGL~xoYl5pt(W}!3F^@Tn zl@5VvY*rNdd84H0pQi{V!gPaV!XbXuTM$MP*D%PXY_3#8O7(!!$OLWcg82}&#yN@6 z8xu#M=^#oQnx)i*ZxCstnrjP0tTmU}ln0d(=Z_p<%^N<((Uog?=4WTv_3T&aUc7{@ zo7Sj$5Qu;J-j8T%ZpO>CaMSi}v^E#`)_1-`&x$o{=`Qg8M_$j+;2HtS}5zERizCbv-=W z2Gi6Vt0b^3k_yifNY%)i5Y!@Yl*CSw(``$WsDkAED3nI<9pAH$4cl+THaBtfnJ3x& zz#B+6buw2f)09pzJUq;q-7m7ZcO~z*`$j(fraSrZo@4yg(+82+W;(jNF;$F#)Mjn8 z%*;%Vqw&U4XwO01Fmop3ooWzK3Cpy$b+Gx~`#AB!4%V$y+_zWtoqwS$d!+@lj^mBg{M%qB+BcvZ zyrve0hDR_>3t>B$La|^$H|H*2;s-x}nvZ?(-GqV9Ll551{=+93pD82j6{=B$3_}dd z#u5gG(u5n+)G5BP)VhC>eBL9OZ0_R-fezVgOa*amD&-1;=P%IRvy32$u$0b(5SI33 z$Vfj{BxCBaM8;aW*52C6t2>^?&17-X8NBi|HEEy>1K&IA1xU&78bt4jkz;-#1N(!FpY(-%e| zmuGfr3JXE#2h3IKT$!BVYhV2ak39O2sMLIRy||Oo%nYVdsJKpSni#^sHY7s>Lm~TCoojV$x~+mgZ9?N?0WeHhKB|y zmdZ)Em!`Xz0%~=iMN515{{Q$l?zsI9uG_eYx?kg|r=Mr%?t@5W5XXuz3Xuq$bc#5N zG0>*xpjv0?(gpOcTFK1hB$n&qX7UV=j#4d^=v~}J*OH~ITd|mJ8`d)I3;yeqFB3bO zg&xL|lPCN5%%k_Sd_fC8e)2`y7A|AM%@(y-VA~cqY}?AV>o@by-~Jcs(qUWQU>jt_qDcewlZJ9%!$Gn_g1 z^?50&F!bcab{*W5m+13N!cceU4bz}FJ4;lV!ppZaGdY2bW7^vF=3kUYDCF939G5WE zz5>%Su`P>wt*&K?u}-g7QexURZ5DGFZE`TlI7=5Q75)96xl3iIEY0 z|3mNNt&hH)T_?`+)S)w^yfhzq+Z(uH)iT^vn(Zqqc#gx)Qx`cre1#|spjyHZf|~EM zWyK=yyLl^-FbMnzC1ajCGt6WFao}_NvKFrI*+9y5kw{Kn7~qzTYssZk{PQ!r=qPki zC=~eTS5C4zpXKfi%lZ1tC-9X?PZ~aO&vw4L>m;^{`OvNF$T|jJd+{hEp}=!&{3zB* z^g`dSl+ulnQl-w|#UYILn8GrpanES~Ul7IQOu^XnEHCWd%MIIZWb%c*TpDg+_0mO5 zR0F1K(@afH5%>YIY@?<5oH!zAKOv9u(pFtQV`IZG*HG!g9nREUZ z<=21c_1XsD*I*SRQ`xqIsMS%3gqonW>{;8Gr{-KOey{$niJ$>glO#>Eq;6=yM;e89 zV>L{_hM{Fd^=lBK4cw!Y+5~DOQXL~{vAc$#7GIqL#7fN{*L+dkIL==^)CBFOe&y>@ zHK-j|k4;|lOART ztQ6_Q@ax*9o)`#?YBMYsH>z=T=W{H}TU5i4q4Q_S$O?b>(f88a)y?$OG^Q{xZHFhH z+llFVMD;3LS8ro__%Z`yQ=GeWnU+G9Wg9o}SO3R17%60Uf342+>>P&<9^{LUy$9b9 zIrp{iP-tJQy$?}Lth73>m z_SgYF_tty)(CcsIkH7yEPn;Q}xnrTuFNkAJW=iB)^+@7bBEf}fV5lJ)9v34qv1_VM zoTN|32xiMQ3e6pCy!&2`?|gw?!{F9CZ{?*OyNINs=eipR;wrOMpRPhCF-dw9r)M~I z>?oVJ-N4Dihv|F%m$Y?1Xj`FuL5^+Hvw9Wp z{lF(!xw1!8%4LjHhU>Q7$nd3o*e&gNtsR8r62ftrEtTn6y_$dc>Ob-Llh4!KT%cH- z-EgeRlxBGg{e1UreI=fj-{(sGF|hz z@s_)|`PN%N2CP`Q9NS9~Nu_CArbw=b0@Jp%&qlzC4I5awq>E~~gq!l1o|vXSJj&$M z44n%)80|Ykee4qF_r&a5u#h#k-H(i7l!&n16fP0tQ&arpsTa6zbq{OTt>eLm-o((v z6tA4QjIRtLQ?UEo5WX_F?Vh{1?e?1}7mJu~ii76{7@R31ZI4Q&!j|jS^Y>r+BgV%s zGj?SVA#BFRC;0JCeoj!2C|4@FQJ}yuOoG72c630OQhKTs)niP{pjxev&ZLRrm`J!t z4C+BlCX*%KRA72~hS+fNGI^@iDz$QvTsDg#4B}WaGBS!FMoEqN^im$>;v6yxb*g#N z8ggvi+^`)RQ)y3v<2o7_8pRr|ni%wF=SuwXpM058u}EiEJGbAwjn1xxY}|YUT^;S5 zyL6dTr%!X!b({FzcmF2Oba$x1fnkK@h}aNn%jzD{fA%axL+9zv7}TSP7oLBP4BDH} zmdWy;ZdlBrLq}NDvs{giPctwzAl`Mut*SgVAf9;U1s1PZ!y6uYnDZl77&&pCxtVD; zY<(l$ZA}c1O>on?UNV-!SHJgTmMvPq16wz;xpyi1`v(YvI;{?D@9pNhdrwgh1u_oV zxVVEA&Hao_&9L|686JE1POe+p$;|l)9HAi;VG{JIg_DYU7~|SD8}ENT$}mV4_IPGd#|Q?hZ`T#4<&a!ffJrF0SiPpBg8u z2Sk=dx~U1Pkl`&i+{DU7t*TrpiybfQqExDKvacV7VCeDyeJ4(`YUK*?f%p6->o%?z zH*MR(npNv4mWo7Sol1EQ&$YQYdWm|yMihoPmO-sr!!&IcFIlcb9!-;cHp^_OPAZkr zeh1qlTWBMwmr+v779(YlcU_b)n4Fpg%foe3pj?7T`2SAn^&ft{wgLDxSOw42bQ&o^ zTm$4s8*&?Q=mKqgHDEq*)@T&IiAg{Ry$KN4RNyiCF&dJahTO#w0?#yPEo6wIh+?HW z58n{UMMfV*ax{j}L>Iu9SEWY(_oBQ}#LMJ38zE$oQuE#fV4gWHlY+t)x|mfWN%7@Z zHwZ?uK{2krG(ck$f91H7=bVWo8QY*cZ4}MylmI`H1hIi@ zi234EDoNUNal#76UwD?Le2z66dzqV_rZzjxnzgq-p%a!<=Lq+q`E5|gjY4)LGFTgbPd*jM%mCoi4Hr{9dOtE_pMT*VD#iMHf&ml zn@Ulfn56&Y3D#}e#L(a%LA{P?+9(xcnnr@NRixV5Y3W*kR1(+H9*`s}8UeTxYD#jb zubYhE{A1V^C4hq(nv$QN50nD-g`h5KK?%_e3Hm6Q<3cmtNtfo40Yt>+WS{;tDG_ zZKSoWonJowG{Q?0%+2C;EWmAUMMVLFqZ4FS^>D|-4>3JHK_-{x<~wiWRNq;`ARsDN zwIMW}#ZZb%gCq2`_VW3^_;bGX&2RJbr=I1(*WJmZk3PiHFYHZ;P~NV ztlPMe>EQv!CMJ0Oo8Cwy1^t%~p`;{I0%5zTQ0FHcI&hquZ`{O!?rvr$#>nOKELgmZ zQa$3}kv>3c{J}uQAtW2sSPAB)CK1aPP@I`%bYOre3i;6Qyp3me?B!HnKdV+O=CKdF zjcYk_uQr8=}|F!>M(!w`TxuxeCE>xrD^WH=Qe)v)1Okg zILGH7doTCixL!T++zTq#l~%bpX9VRrv3=W(^qn}uy0tx6ag~8Hr>M=8F%&$tYd;gU zfKUib+vb;hj_`wLce7woHv=V~OH(CI4_+ac$ue53aqRLH{4mBgZN}zi*?;Cd22hS9 zb2Tmdlu@Xg0ZJplZNnszidq;a;0#4Ql(gs5L`s7%8Z9$@&lHpc$-c7#+_0*L9mfwL zESt!%x$(M<>>Mg%2x!h_>1u0baI}JB3x+S9$1qKL)^B8ZXav7r*EA?hPG1@(B?94k zuFB?{IoWq!)ayPcPn=@mf;Qgun~(6(k9>@|*)b+2#)xH1wOZxak#j8U>_m8ZX6I(` zYZYp>I;Q0iN&~~N@jMIHOOZ~cn3_MjH2L=uWIf- zy=Y9QR8UV^x`M04wjsp4A+{m$fUA-omHcds?(Uv>?s2j$t+Z~qfpWDr-+`asLnQxB zSthkeM~4|g;F#Lzd2PqOu^JPBMllyBPkb$vxAFLmpY>yjXKUuRPQqng5+Xz*D-u^X z0*!Asj`5lw*T%_&`V+)jW9?ajY8X@WV{(p3)-eeq#hf40l(Mi)!Ig4=V;VF&299YY z!BL7#$|I!$j=%5>E%_`f*RJ8x`7;c!UdlwNMk?D%U;hBR_8w#R-h<+iH{8u#_fIo1 zIm7<_`<0bSi<}t{3&D?{-a)ZaADr7I!c>KEtbL z2WV<*M=6aXHH3i?MJU6j5gw+8mlbtW@L?PIE^G%!?9$$X((xea2xEXuij7c7;-HQYLX(V?!j!Sz+)9ZM23|`CKYw9D ztXqiy03ZNKL_t(9TURfoXHgensMxl7Jtv<($aENCN^Nj9ltLPY*6zj;hG8U{wRoN^ z6Gb70Wub&YtTaPjpkJ?&QS$fF{+NtoQHdgyFfa|1pkBi=1N}3mNhyqpL!VkbAgI?c z4HHwq?Cc!2lvtLDB^33#h7Z`bg_UcjIx{}c=6AAbqIy6a1jMxpPByCxHbWrmRlHn* zSVC=fhMh0I!kd5N0Ty*%$EBe$#>S`dvU$v~h#|ngGK7=QV|pH@o8r`&i>zI?fXz2< zCGzW3{fMTHh1mT=;Ch6`S)w??DzuQvIqW`ufitJS%5|GJF>rZ^(`PSmeq@}s_BKXF z#<4AX{<`L+Tt+8m7<=k@w%)Xrhu;1uaU82BfA&jJ2_j4{g#yC5ufYbMLl8@LzWgdT zZQsIsAA5`!pL&*`|MYQItXYMT&7%yHIEt}sfv_EYZM95P5HL4BM$X$x*xJna*cct{ z&0M#BIlEqdm6YdDXliEJ@?N?ZFJ$rJC91nMC$g@C5;l>Hi48#vr1J&Rjzreyh@|91 z-#Je8o#yVFxADxOQ@nEgG#`7@9UL8+H!+I(I`D z)aw<>r6R6l<9RyqcXVVF&+~}ln3i0Yk--6EP(~OgmDvg6I3kV|L8$#T%5?EES!5g& zCE;VS43P?Qxs0Ab2!kk&@N0Es6es$BO#}iluYb>GQf$BJW=sQG+nagljSq48;sw^N zS^|0Gjm(uQ+SesCpu#e>5naX+N(gE}gqbw+Dq(z$)HjjUCihC2Dew<_ z`uY0a^B9gpljrc}$G$)+oxxhRmcF@=&;F0+sR)~l=ORO&+3_o^U%rHa{xfv;uBM}- zgTV_I80bICaPbOXKXVeLlt^c?pduX8z{?e|mUgphRWIlJkI~n6iduC}2N8z8&V_L^ zOi=+!5B`8ZFu6D>9+WKoHHVwH>tiZDbv-OCvscEKT6UPtrh+AEy4#{NfY6>x* z#%m|6d6Eu;R99s^;+p5sKnX1qYV1Rl(h?iXxXRj(62zcw8U(Srnk|%UXgt%vPhLR7 ze8)A<)%g0gE08+4Osa$ql$bozwl=xiLL~kNMU$sdYPM;xxS$cI3LPls+J@F}%YY-# zKSfI>!^X|mabo{|a`@c3Z8PVm$~^bXGraBHAEr|CNu@k??m5VwcYXjjo#OPF^Wt-# z`2@YIR;aTVFNsAR?N~vDbsN`n?8p%ow&bXli`XdDnM;dhEm^m0&KFp-+G#44gP1Q)uS$z#uY~+PIP!mm|vY>U174ikkjc0Qvw-YStrCSz2~ zwyD)%(Smm7W@o9EO4Q3GzWC+8W4csBm^Q~wp5>kI`6!NQuy%b_RB{U`mTQ>lG@&07 zdoC!b)arCCT+E`D0_pZK-t~d^vv%cjo;h@iiDHFj*W}9hB&(JzIx>l_RjOPZPrc&Rj&X|iP5GD@Wq0%&b-CzH)EJ3Wn=&0;$qO2zXi&sw#n zS@wzHT_v3w%P=(!DEWF6>WP%=x>&ZYuV@W8LqedEO5(XLm&Zr=_#gfeAn^TwZ+`3F zSh;cqi@MsV#0Hmrk7}(>97pWgcR)P;^C$W6Z$HGkH7ohaPafyLe)apj{=VB;wR$Gy@^wVE3Jv~i#Tb636NE9pPN<~aJO*&f;sZ?6jeV?|D4ko9@xI8dIzNwWXM-Sus zA@zDdsa)YV-*i8pd*55xck>`-ix7{YrWkbTBYFPDgW&rR^;gL&@ID`ziXmi@$YM z4=2aVm^hpqo!pbl=Wnh~oG`v-I3SqiT zPS0q`r{_|y%)CYc`ghiA8-QPfRjE{Tp=tJM$xocu|}6&2t`va z!`)%}}Iz_&ziNLQR4TB43&mj#1W!bovg=6atRT#%0 z6H-$0S&3tbbnFB{*vRP=7>QU%V&WQ#*(;+w_sRiozy5vHDka)lnkZO;(eZH#X%E{n z36#S3eFS1Ys7@(~=G2LK&yQhQ)J&5o)H0Ju2rx}d88bIE&HXoS;*kgM=q-RG|sev5{c_fe(g-^lOwSuh6k_1s5+3apCNRge+ttlhIe!Yk9%YBem^L-{^3 z;o)N#s6?uEWok|VBIUWbo=eG>G_|yl_Vi}DqrIJ6CXHbkH0AR!7Er-LSUT<1Fb!-s zMc>6Cj`#JG&!i|A7LMamuGZ-3YU9C8y|gvwsYrv5|JIx6^du8=C6=}p2xhC)6P@JL z^c1`I>_LWA)~;K{L-*gprOQKX-S#k__{i_E| zTgX@wdMw*wLH8ovc?QBTB%Mjm%Yz)-rnRjdAw)8X(Z3f4A(^a6E|(*WLIU5%Fa#|v zEn4aoX#{A!=Ih3m(YOMO`S2?lOKe*|Cb6Vit&z*5_{VR2lYG|WU%vAlvd!&G%oJI& zbS0-RTw?fGKc4Hba&Z@T-*+#E_UuIoiy-jXyk!gD`RDuD@%%IRwHl5EciwRu-}~WD zxb^P)`Nr42&Yr!8ICAt+EX!hIYF1dLNx4$yAHVe@YC*t<-t%_uy7LW8&do6U%2{S6 zC#i=%>sPO2*Rj(aJ3q*KAH0i!u}O9vKgY|b`sr+G=K3|gTs(6T)3lgWHh=o_eMCyo z++2V#n6aM}fs;I@sV zMvw|y=-QxMtF!v9*W(Gau|1ah-h%f1IgU$5=K=;UoS~_yz`(hFT*qbEy0yf)9KZGU z``Ogf#`x3}Ed`6onF@8^XL_!}*)tbdy{wZpy`3}_@(7{d*ZFJ?!?3B>O4znTXJ;qE zu!-VG6Ti>~=UN~!OarAf7S*sUkRf1cxo}t`lTKlnHf}19AA|(;3WkuFmV?5;bv+OU zDbK+VerVNSzw5$s`F-L1631RV<;8 z+iq+kM3VBGI30|HLImL077h|D2cm$JyPl<^xxl(Dn>q5z9?WC|)Y{d}@OGgRw7uO2>1A)gi>`O+WrU;gHAxiT@s$k4Ewoh^$yZ@HCnxx^DM?B&^44)KoH z-$hqj3y$5+qRtN1tXaiRo_G%559qrv$jEGo&aMSo=PWh8R2o{VuM7i}M9Rbj9V;#G zv2}@R0kKd-fKV~Y(!okf2@I)!7YQQNn?HmiP`WEetjDk#D{5mZeFKgy3n!oF#Qs;= zx_uj+%X%oJJ$Amlmx1Xbw`|?Q$(_%0-QD-n)Uk-k*)oNUgISs8)jfNOqKJ(vm(v8y z_*IBa{A!i)u&yO3hQa#vYq*?AF)%tpHHf%);UcL_jwlKd!kGVC8-~D8dcxoF?*l;1H#1m6iqFNCBPMg*c|bk7RT!S$yO$lVfoTU>^^*q(<76#w6sy29^;k$hv;6ihzP--e)+Gt_wG9g zWz40^LsY7D{`=p3joE65AtlESyvq7DD``quY}&LQ8wq}yuI4N=fud9@l1X`Z`4%eE z<1~WE8Y$VPWoiDqlth&x!ZcA*5zNhT?``*S+ugVG!n4m}8YT}v^Z;M~#&?;Tp2Koo zOfRL+gD{Ac!Rk%dv3%)5P8~W#TXTU29)2T7jvQljbb{j4g!ZR6F2c46YgN{)>fwPm z+{g1zJdH%~!H;~9=bw0jE2CFPc@B}VG!;ui7(=1Z!o!dJ2G9TEXB10i-u8~S@baDm zoH%}pY}zA;CBA84qd-YQrRY0ximau0|0jQ6oj!eriHQm9RF+iUp)^;-Yv~{gYRH6% zZwP^O(-b2iZhhzxdbZv|Q&Ry`#ys)kA5*FMyzh73!^02U3raFNG0pcMf1XNlj;7`o zkYF3yr=d)f!tSF}tdv=}u#3O>FMrPP$axOz+0D?%B&l?Y=bqg`ZEhOFwvqBGtig61Y}=t$ zt6@71QcA)o#PM7VB{a>aUQ5z&g~sM8MHK3Zh>Rt*S`FX#$>;N=Qz@b_q+BkO&*zEb zh;p%{laU>r1Z-F)hEhaftl#UFjbWM0&CZcYrwQr-V^_v8O_Q#L3y_h19@n**n=A5( zPkxq4)yGSxxc<5gbai*r)Y8TpFU_&RNiJTv#4|7NLs<@?)!#YwaYV`mwm8HF{jat1$Q{fYp@I%Vi_9SsbbAmHVp&MvIyfq-w3&Ch@J12i>n24D7C)3VH%E=?wAW2 zMY!hX>s-&PtFbvy=wjsBg8N!+eFK8D6-N2#k50Fq%Bf$i_E;-I1YSav5yHS! zx|^$#iG?9_=#pjI$e_;YUC-0mlx5|H4V>7w4=a|$hQZ2B8}O$_d3wi-96EY}8@6mx zYuBt2`wpE{yI$TemM`t*Qy=>Swr;(Sa?Mvied0;+{EnCT@M9lk_1blG_O9g@FCE~f z>#t+^^5t}QwBe>)Vx{O^x1N7}aX&K=tlV@Rj_V;w%()3WTOshH7}F3qmJZUf&{};x zU=ajLBvKbW6;V>_w~>lKY6F=R1}f6Vbh z!X%avj@0FPgpXm}C0xfQmC8~OlK!Jd5t*FUSql=Tzm{DosgQ;VhKYz{%w(#dUyniw z6D4DehEpCrDf~&b%%A-3J9+Qzn>ca)605eY#w5Z<;+JOe7IctHr>G2_1-N#K*5$p-jE`ZP z0@JcENu*cFXILcHpjb+1%QHDU$K`<`C6ytn#UgVv(=->dG&SY%x|T9GS3+d6WV#j+ z#}UhWmauJ253AO$r=uxLEG#Zfl*z5w$jrnTQLRjbPV$c9h%MW$XUomoShRdKajfWF z*~^u>z&~~p*Re5$N)W<|NC_%6AFrdEPyg9p=x)93vgh0=O{*;&)1W1jL7EmpByot5 z^%{3>-@-fJ@(^*YDB2e-Wy7|cIMsiVY*RDs%X*obnI-MI`YLRg^KgZ;qa`L@*o$e~ z7;*^LkXY@D$trmKrGq^G>T#4(q?_9rK6i#{5VLgYVp4@BqIwn2OOeaxId%FhQP zmZ}Kb=JEYU=x%MMwW*2Y7l+yX+;gnjxPkuBDZcalpYq^aAECK9%jLNmg_O&J&MwZp zdVzO6_AwS_VQONESV7b07F9|D0NUTwk%s8y>dr6?5g)M|CA z)hdqT;5aV6?-PZgCW=K73Pl)2IF3y!<)M_KSSm3$ThwNB8B?wVNU3lf6D9T3Qc0zC z{|KTuCXQod9Fy`=%oR%v4h$1Zz0sVVE3s(tB0Sfj?ni`C#5>;hD7J0#t?&Jq6aB;N z+({_}K0}<3iV#8F1;SxtRVF`gHB#IarlN9v|rDB9>5lhAKV|6^w z!LrR{V`^YxAS^4vp9{dEscpgV|GEPEkGo#m0Q?%POxnY;Okx>hIu53x-MW5a@O2D9 zkVq-67U);Q!CX^Nj}->us@x~}-h5HPHA%VulhxqkH%JSOA8bf|R8mUEiLAs;IPtMm zNhe7cDPb%z8ir4$h-q{nL=xn6&2u(36=?Z`Op1!md|a2t3z=Fre?nXIR+Q#OihHIkM*! z9ASWEv2pVzh6e_yjg7E<^V{h=eU^*kCpdbv52YSsVsac`BJO$M zLH_b9e@jO`!^Od2E+2c9&XzotxhblZ60_AbL*tWd->{1Beg9wS>BtjebL!wB^7&kn z7^^#*B;9M3bmUBDgKCy#GEfUA%;8+mPId1RB%o+7_XNUAyeON* zu@q=2hE$L%6u5lh0{i#vBj3@1jn0UW2=cj%-Vh7@DF`*#7KOr1WNs3TMYN2hAtn_P zgUB!tiTptb14rnNoJn%-WejnZxw$!v?oMic9b3c*1?$%I(zUFY*}9$pm~lvmme1+V zzmdqAM3OqK&%Ysz`3Z+kat0YoW{V}xj85?3_y0DBjvc3GVLM9~ETQl6WtMh#v;F$( zIDYz+y8Cqxh~IeR5pLXk9dCNzUS2+O0)=4X@+DO2A&>m_yKv(wogJNG)7I6ROqnwe#R9TNvW{ZkeCXMFbT+{tvg%B^pFn1!2f zL;?AXM-&81&&;BTIM_ePrKu7jf&)`0QJp>9{^&-O?GeTj$I?dWx)gX(jhv%+;^crf zV8@abx82VQ&%+Ul$;laVo`aXoFFc5&#)35Ww0F6m*Zm8D*(kZWnC zXWd3-XJ@s4$Pj?eYp9n>OifH`d827zyDpvWtq9YiR4OxFtP<91sEHYRR`igcDRJh& zL2kI~PCD9KxtK~(tCacpZ@-yUU2W_-eTnm9GyKt8?m|T&Paf=J&F0m7_<pFb#LbRWBt5%W{_OQEjuFs03ZNKL_t(` zntUz?=^QmBsnmUZWl^iw*>P@+R|cjD~#%Pi|^vit^z*@|^mX><8N>#OY z?Rxj~JpY7YS>y|nXw-iE|Doi0bMa;a@N2R3NL&O`3pvOFVW_E;9|Vf(a7*ED>T1$G z*QiU>?~Sk_n4<$~+%i$;KTiGUmb~TnbB#hERXCUkr$d&mk#l_H-0xAFj0QATm0<`t zKRku5X(UVoFQnCILcOjP(g*xdjjN7DH5I;;l>C60p(%=y5ZJcOz}b^T0*{K78wd(c zIKg;>nl#tUaLdm@cpl~`Q*%fGLfLxSy5gVD6_RKg1it!v?gog!jzrMh5@%m|j{52f zmaSUF(bxAAGfjl1(YbaNL&Kw7@43NkOPg8Jz7RW+Wcb`g&L2O~6d;4Zu7cSxpfAQCB-?Wj1wMjnrN1vd7WP+|sJ+$YtJb3p`4j(;Eb4@wF z_gnXI`NlAZ4$WW%*teg9`ww#G zt{rF{i@AQaheP`hvE}w{*t$m7%P+9$uDgiGqD)PvXkF0Ez879lSq7#FfeKm+d|wH| zgMfL>O>Et=iJmKpuRoB>V;Y7MYHKJPN*SOd@U?Ju9{8L;bB30M?QGq&f!U&pwKD}| z@&y9V4JY*>eGOIo3!y1)t(?1|2Ka%3&{ZF+V0aN;Ou`VzAixq5H}F8}1fgI!K;3+! z(I}0L^+d{(bYJO)@>+tjN^*q~nozkkh6XidF(S6|#m_q)L0J47x`rVX4bVpkxxK(g zHv~>paA|0QCtf{F*Olw6UQk2QJk8+nIHf|K7himiWLbjaXRfko{VH~D-OLYu{8LV! zImh(O3=iCWJHF6lsZbEvOp2N5X(on;=v>yptXa-8FYRIZ>U9kF4^YVF$Q2!$SF9nT zL7?dj^bcaY4n~;vtj>u+cHlan`RIpv=-#^+pBN{bFVNk4gYQ52EG3Fqi6oJ19^Z8- zO^s1ZXSnx)?cBa%F^4W)CzUUkIf9d&u1I`Xjp;uHheC-C=)C`toQ&l~W zKnAJ^1WF}`mc}~%g;+?}d->oo`bWmO|K81PUfzM@I^;7MY(wMeqvx49-o^Rj z$Ju)Oc4VlxsV|QcGXiSM;~c&^z>%|;c;~L$DEYAOLO1uWdw{8Ifv(CVk3DcF$FBB~ zD-fu=$C*c8)O&LXd$A|8)2JTk`B?j9~)?54J+h7(6W3_@deHbZrFIgaCC+cvRy z3<2Z|1)`A%ft2`xkL#%-UP_5u^3d(jEekLW)eJbEOUZFCO_Nf|QO_B%NF?I8u8W}? zl$9kY7E7whw=DwcQ*?`=<5-Ahn>xaEF)f3}#yWoMZ4c1dxm5P_^zyBL{+_T*gIF}e z)buRBeC9a_0>&q&#gk7yjTMcFfBoT4scC4UdeK_?Pn;r^N|VkPSh4eNqR|M`E?oCb z{&nwhnz!7^)YbFEs;U{wd5q8INfkY;GK1Il9pY;LDBE{z#WZwsu0k?Eko6Sh&@gqR zt}#{eL3#vMgnxYcH7-mSNEbbox*M@c7fWDR%obhDz$IB;fgOn=khoGI+@2rO4}q8= z&~yVK)P7&`d`zjD0wGlKj!-(mAf)H{;k_;yF|l+(s^~IX^obd2uQN5ZpOwNPSv1t# z1>p@;(*(Y+h9zFO&*>r0(lV5#wBxE;q?pgpnbi5=mp+Cee3E8KzVON+F)=xfX&CI- zu~E)UOmgV(IWaXkO?`b05mSgl$s<5R*96H#49hez07OB%zH~%YGD<9Bq8qjp!WUl2 z!4L+4rel}}p7fbc&my%n(P)&)stW3BDy1I;B9-=cqPww3|5|JRyhJ3nbOa zIHo2@Cv5SS8FIsDR3{7)CM2xz}Ezp{j!AYu9q} z^?k%Ofu{+UtzNd(C*O(Xa`SSnxB+ZLD$rW-$Z5vC|_^ZGD ziW-sz0Tq_PCqDE6_8mLT)&3FE*&JIp-NskH^Ft;h22sPr^#bB$<j|9j6Vr84`J$r!AaIIBB?uN8f#WKKBv1{59=an* zKOkRn&~=r`5ClpT?E3+Jpt>v5G?<=Faq`%4cJAE9f!7al;I+Nne&Q0ufES`TdYZ0WuUx3xO^rJ{mKV!}RyvU|r`zykds7rh3Y&tMCJj z<9qkexn&zhc@2eP34tUYk8rJTfc~pJbgWy8X_&aaO73ypuz9vj@ElyvCmM@Vay_#7 zB8kd4OPlLCdbyXEUU-pvH+J%_`|cw(o1!ccr}ugmOt~lOvVuB@&Aw zg+~4S7G?(el(nd7g72f3iU8!LpyWEllNH#}I4|$r$I##at`wNl6QuJ6oaqTNsVT-M zXV_n9QJyTPZ!(Q$S;)$HG_!@GW((a97AU*oqQeFv$DaT*u2aHID+sdO64GSCFr zron=yCVq9Q2iJA!Xl>&8(^nWwXEAi0fw5_9;dB4C^(5j^8mf}CRwd}m1t1Kv=`^{K z0Tyn)i)hSZ%chN#S5)xX&wr8KyLRx&kA0F?_dd_>edLev!|%4PxfG-l!0ST8j@f8J zBb&`(+p1yJLXl`DlfjPI_^yZRx>&Z2rfCF0pi+Z1L0MS>(=>4$hmzyq3J*85_q1%A zLZLvhSVGg@XeJ~9uIr*3Iu+$fOw*vUsv6hzMAw-M1QKR*1!NFVRhi&xU;cCE)z0J9 zS6-G)b+uw}c$|*KOSv&Pz~ir-!A@3Uih#0sl(O1-%E~LL(lk~_Ogsq#le5SLOYl7h zkknU}Q9m+HrS7w^I)RppQe${nmPSL=#4>Gk(^4pS5Fmw)Y3Ky5OWd|uboX`=mPsCi ztK-AmyJj&}5re9-1g~E1$Df$ty<6APJ(*#D|1`R$snqoVimnf?gJxM+wnc3+#>i{| zfsYd?J)0@j-slAZ_yL*`8aITxzhvB^R4g%*bFm^(Y&}q6pP@;H8%Qku4M#vB-WaOs zKt)Ww_QXt|PHG)8C1OB6HQGQ6g@w*RaD_xpqh}IP6bk8OOM9Qcc4oj*Yf~zQ+Hqp zfgMgYf?EU%bH_8c+>jd?Hw_G3qvUw#f}6Pl>QLt#e*$zVNyMY*`7~$tyiDV~8kVeB z#_1zRu>ud@j<96)Dn>^}80{ONEE>T`*3iCW390F6GBZ=GUtG_}KJo#MbzS1fiEDE8 z@}*+i<}DmPe1OXNi{uAC|F>fIw)H%)VlkgQJryXlmfL+cq$sEh=%Iu7{Ip86rb!(yxbhs>;1c2}WJdLpOBgtl>*EJrtKp zN#F&_i(XgQv--S4eTJr^ONp+Bsgs6*6ly~6yIzQ(2rL1Y&t2f?;bYvfa|`+EWX*O@!z?rj`5k;4{p&>PmQa+F8xJY%OD-o_# z2ta^x-U5(9Q{rzR2){cr2ylG`*UP{~6FP>eBM^9og(f6k$zghU1Us4_kx;zp;pr5^ zeSIujvzA06!lgs6)3Id-(W-j9QV}$rp6h*#p6epkx|q(UdAPoVt|@v@ZQN$2=Mp!r zULg<~iP}0=ZMcnjRvDi3DT_y$Ol9cn=^=LeI+~l?Xb!Lcc{Sytrt%Yf?}_L5!IQtF zuC_+5U)fIk{AT9OYhm8J9AGjsGDyCV=UV@OT)%aZ7#!G#>v_~PHFM(ZMLL&u&=ie= zr?N4ovw3>DyII`PL27sinaiN-8iA%!nMm;53$JqJ>=`_vJh_`1>bUog?F70(Q&SU; zRE5AuI?wqlz3e%AjUJg`#zk3u>ITVpj35ZGO;g>Rf&ghnIezpAB}~5YZ%-3z@5GEI zune7rEsg5)k`T8I2G5=%J2A@qhI;nBzMtutG>t7S?Avz`qmV&2OstA3I=616v8s%8 zzJwD5W=nijV+(%TDOf%cBYAUzz%WkGv8mTl8> zV}O~NDF)7+=Arv{Gn*UZ(&e)Rp2N0#Kg7XfT|D#JamMf5jaw?>YEjB;8-f7WmsG^# zWC|sYU+N}eTP$yBptHG-6Ws&YhR%bV){`w3vExauTt3gS^H=eVC{i;)l&}ne?t3&h z)N=cdt<27*IdJe0*@7!4XL90O|MFvAetAEJrQvu!Lep`)08R7pJRif<(S(lfdPJj9 z;;|UIp}77?2nZ-EE2B^-VA(cyB%;!k1D_!9aZ4Va=i|D0eBZ}3O-#eUDJk^Lv@C>x zQn3^k{xZ}FDEg7-`RKY%MKVDuo#E?$|1Dg{!SyBc=GCC*nBq)&CNuc zT19i)5*999N?AuaL)m^jD~|7{@Li9;`yZbrmB~>Ea}AJ^M8slbIz_fnM3+96sZ&=h z&{45e#wun%4x=P9HegG6msO!(?o3h=6)$cI_bQMB)t&4tGEq@gNvy1b-o6ngvjytv>cBVY9-P7rVz{{+-}&xOd$z9M@Mw8;_4J)P z-_rm8QgXey!u4hY@N2L%UHGOJ3UM`|0>Ol)1UdmI(XA@z-H@6P((J<`JK*x!3mB%s zl7>YP_%|&&A+*Nhjm&^KI*}JP1cH!iaLao#LuUY82s9lWS8XPWW+SmgK-=yIF?1*t z@+KTt`#magGRNztFPCY5-e(kNJlhUd>&m#Wv2@)pg4lq5`z0G*QSVTRVDpe!nl zKsgW1p&)a;%dIPFXv9pNim0hhQp98`TfAv0s)YsM91;+Z+PK*?-TPjqVO|Z3mUnXI z$Wbic!?$dfu362**f^utZxD+{DX*&|&<)OYV_E6Eu#u8kLY@#VdI{o6m}?8R=e z`}Qs5@-CxeQ;cPNF~6>g2k*I)^~)CX58wR}*RS1xLY9$Yf}>hnxO=yQn^M2LPrZNEq%`;2>ej6IcH`02K5Jt z@j#gqYW;dn9Y4Xr14p=R z^KI0&ETI2JAIFazr>wFPUj_uekD=*ELsu!qpuF%y-li*6<6;;Frmn0Jg_PiXA&Q}B zT!yaSbOO>fos#F#I=`8b$rLA#pJL6%jr3l)puEm4179=IEDhfY2y)X%=@IA_b~K@G zLbtlGWl{CMnuQ%5lxqg(`$q7iWpwO%kiYxhQ#}3BeipUV0XjDZ2I(IjrLM7ocfap_ z{P@RDh!e+7;1=@y>bY0(fs*5M@#=MUKky(^(FSqkaz9HtI@t5XFKAz2(6)FH-Ip$5 z3uUpIFO_I$Ze(Fg6IZWXX3>%*WQKg4)HGIEIoVQ)-`c#3!Jz@VPIsXNKJR$wL84Kc zuJh+vvbYtu?DyfverjOwTY| zC{US*)7sXGFbv8os%V|x%;5Rc+;{K296fc4m-ZgP)&Ep_l+Q7HMO9e954A(phaQgU2Mj!UlS;0J0_F2f?< z^L)~?vr6;hl+blU39+TJ>xH@jVaElbDtPLg1E4 zNGb4rr4bOChEr1Li*70klV1tl{aAG*uN*K7IEF@~+R{{`?g_df#?7ESk@sJ++@3xd2;N z8Wc+xG`F`?^r0+bp-D+3bhdLt^nULCI+qzUC-rlE$Y-+@W+up$e99saHN{OUkAr=G72S#E3s|0~{~F(M>d0vir{4X>F{L#}6M9xm+II^Qfw-V%ydYa(pHyx<}K@rhUAr z4C9%iLhVe8sPOU3NNM}_JG%Z4%CFz(^=1R`Yp^^okixV;FR5xh@NQ0d{jlJkW3A|O z#rw?ySQ6DF4O{QT6B=%*bTg%QE`8U$rLvcV{{4i)qwq1hrUX-dNVid1Q;8=77087o z5;hPL#j8&kip%c?5CmQ*9EDO4C`ThXM_CGy3n?iE0oE;+V{^6poY2VBM3^=lPF-(# z-?pJ3Q2iDG^xVJAL7Td!{G?r>bN)&%lgIb6boYH!)YelhmGC6s2VwE3QU--vTD_Xtu~Eja^K!C0WZ9IfCIPD_CVXHFR&7DGa+X)1w_ z>p9pu=za-TY6PCA++6IKYA{U$0*UW=D)+$g5#jl>rAyq;Q*ujc!lx;h6^Rm@pYFLp zOIs@|+UmG^`7*~+W2{}Xip%GxIPl^#Y}~k(*19sXnJjKGg)~gGc!hE_(hSfw3|+^Q z0`Msniv;NzYAO;GOD?|DsHmt2Q4NJ6Ni^j|L#QbM6$Fz>bM4G=)~#K~^}ylSf&FaT zdK=fe`zU5J=vD;J43douQ?%p7!O-8Sd-D(sgXhVx)hF=J^eDEL_0l%U9@J*2xqC zKcB^QJ(`=Fc)@Y&Q5 zCmD|;3kEgI7tm50W2P9;T33llK*Tcf+v*ui7nssb0=LKl-QfdwtV7cTf-v+Ap`1oE zb*)Lj5->11gNEef@l!|yt(~1*zjTRYR85pmA3VhRNA6{2YJ#VK@f=P*&xb$pIVMtB zO41-THN^-1@V`@2Q%O!5=zam=mC)>nLLdVlUDqgilG%KL=6N;DWby>j1pn~#9(F8m zM>j2w4^DIC_+i?sle8{eL`!`QM-Crnayrf8jho23KAlaCG`!;x`lnMwbq!4hY7ani z@A{?u{Xaj>XkQ=N_;{Fw5a2j2IUx|5jwu2>*Hr@sUB@&`#l`k~JjV+s--NYz`yN3#h7nUbUnIDC49%jlQ5gj($+W+St_!kr4HAQ(VEM$ ze(6F^U${ylZ;$A#oFd-9=`8>21oiy zO^u=HCX+KMrYDBwZ5uX<#swW*xG{wAiZoUwn9ZcQcjs2V@x*gHcku?1@+$IfKt@^^ zrin>_hlYt7s0>X^v21=V4drFbYgx~`wyomaPxdf0HOujyK_1<)hMgTvwAEE|;o5b! zE^eXccsDV_!Vd!SuB5J}D%Af4WJ*4kCX^Fipx6VBd_#X{Y2v0f(03iG7c9hTXuFx! z;P{e~;~+ExjevYQO(YT}l1OrKaE3qm-ZLz(EfbsWdzkjoA+njQa%gjkNZ-SX#OS$t zH5BxEWDBm!YSA=`0Z8AQb6UW%O-fFYqsLB@S-wm#S)Bk5xdU%BG001BWNklvJ}sbM}8IZ{j(MhLq?U%*Aqfq1aXc1z%za_1+Aj zHlDc2i%Lb|&nwj5Rk0yOahDYe>=|$II<+A0h>sZE-)(hAXo7#C5SWz3p zw8%>XGn!yzY6eV`=GGR{`8;FUA~lN^lPE7oNQDApnCP0Wc&3FMiz*_#^X{$WG8yvuyecA0 zQwedch?-()Iziy#I4&}PXf#6M;a$i;VA?ib5RgevqZuZtR9Zgu>S1wxCXE(Nph*K6 zcxXXDA)jYKRh-A(`54PP+8Ldk;cMT2g6{EYs;Vl$3-Eo3z=t{M2C8W+WTsfTU>@)P z=p!s|U(Av28+`toKVsjZW9;0%nQND?;g%eV*$j8ASj1m_{=bD+jN}8K{|ip_3{g>D zfse#AG(`CQ5}HKUb=<%QJao`*1>J9b^N?K#^3zo z<9zdf{xN5+Tw~wkKjBLs{~aFMy@MaTc8tcFD!%a81I!d12Bvdt>|980HpPNh_fv|L z^U%G!*tD#jGuL{V^$m9KzMWz|&w_?}?!9X_t;<(1md>g~S|nA;IRE?gE~@Gp*}6T( zW?QR;^%iU;ryK%b6>^ym;U!=Pz6# zm!9JB|MjOVYFj`{b2Ft?tgtmP+~3EFjT?}r!KI^zh~2Z911~blGxT zr$~2q54l`{RJOpvMT=Otb~6PnIJNxz@B=B$0*4fGMzyO7kN361vc{Medc7*!* z3vdcKviSl#9=sb*!o}047%sYuUmsy%YYSUecChE@X(lI&=)SLPR3%KLGrWDr?cBF| z34im{9lH5#zDXf0g#N>$&}o9UR*8I#-SyqV=|| zOqCqsb_Bbk64!N^pNuk-ErRr^P9{jiqY!u$iw@abfvTFSn*ox-_mGB$=lghGfN(tu zXjrzTsDn~Xkn@ES2o2wN5J(Km#CLscVX45jz{7JrN{*{2h>k|YGLRBHUxp~K#4rpz zU!v=(z@N?L6w2+oXu2Mvk{+(B1f+d8`f*&3re&-6@^^p6@$;AX*t_3`k4`>cAd1gD z8&~1WfXV(Iwk==8@4ff885o-&a7tv-X^J94c48P0g#@4MIxfHU?eB`Ap$Vc9Q<+!< z65kIfH%+t@EUD0$oSfiok315hf67q`O(QomAy$076Cpi*`lBC^$rhPOXPFou=k4!$ z7Y$7f^mX?$HI;%`CAw`XnxCc<5dz;b!7wNhswVU>>HyHwf#3^}L znn0Qsg=~gey~N_0N(NIo;+kYpOF3tUCMf1y*48HI8k*vTqi1O~JCST%}^Zkf;64SEr zrHK>q35VP@ixw+$wW?bNwgQn+?FP!IFWC zDT13`y-pzULN5KB5B{8|f613Oiw+~?@wPGU2}|=#`zMNxe&f5CFtwY4-J1ox2yGXIz!0i& zm=h&QWcWD6QPjm7=)@cs9B#1!4dD#Om*|>Q{BhqQSy4gdj(bSjI*#MqY=q|AfzNzV{_`lMV^1*WoqWPVwxuBFJ0yPKYx}-9=HeL zd*~v-G&IhhJV||16SLVo*=&x?Op58rY0S`xL;5~`ptKRXuBJ0V=(L0sipMJ@xsr#> zOrh;u$+~4*$(IUv5`Ol=Uas}`Q5KJ?>AwUBZ6}5LT%Bx+L`yaE8-EMiY*F^KBAkv2 z4c93WjYM%hAIDR^+=ixMN20i%hv$@tMq>m>0@*^$v@mobc5mLoFJ3#qUqAj7R=f<` zG|_cIYNVepJn|v#*|LF|{45O%>-p@o`SQ_6pIuCW1|iC={|J%F1YNY@jw7 zp|`u6s;Vl^4ovDzfI4>6DjO5Q!xi9~?qA z4B9&u(R;Orn66P-QO=DU!?d<)EL*mOi)YW#xoRc8=kx5|qY7cN5=gU1(Gy%4m||dT zh7Z1f9qCM-eFvTvci)#{^zwP~eS_?}V;7eaF&b;DIp|8duMaRgbd5;F;>4*_Bx`CJ z9UP$R$UeqKM%evZkFj*2iDl{(17%Bk^4vwf{MTP*UNXX+cihgtqg})jWu#LnOj#nE z$%ts8oR56+k0?xxF;U2p%jdY-d!2J#XUI%X;0Hcc^XgdG*~!GvAf?$9lhe}#NEWWS zjZD!+iA@Hfn%rZ1F!RD2V_{4wt10uGKZRkAl;y#{x`E@?_ z*uy;ZmOGgkAEmmofyjZ4=K^X~Ti%smJ(=1`>@$Ddcj*qb8Ybkwmf#0p#;V$}7r9 z&7>)nN>tCQ;hx9di&?*bAO7o4DYJFfE@|UP{}hEnfj_u=9Sdv9$U7d-)kOK^2j9ap zukMpSdg?h*U0uP&!~1XxS$5p}R?0ipQD#8xym?}3Dn+4CKxpbXb;H26ZEVxH>8clt z>6n&*q3bufwSg3*W@d0TgX!rh7AlINE@b25!bH}nags$`Ir2#IC zrEy$^l=wi9nZ->Co&iuwkN;3yo(_G8Lw{K)7Tj1Qaekzh>+`eHo zUwiUJ^wcCo>`i0}JEOr45&lvmI8Fg{ztiYD-NlY;Ao;ISH| zITECh*lw0Tf7jhqmY4ITpS?nT!sb&C?%=@He*W&~ukz`)-^JyTX?}I+G=K8Q-F*Ao z-yu8gk)O%4YDF9CHmpUrVwAG8tX|#8m21~o+_6fE^83Uuj$Xu&0l)n5k9gN353_Rh zYF;^Wg~{|Rz8R;Y6fly?lPMNM%7YmymLbtpL*>jM{>TlQ%PRT1FMf`%fB)yaa`XZf zwl90nUHJd2B>Rn7Z#DqG2CI}wp%dV1D!j>+BBc08oFE`>=y-uDfQ(Spe=G03;H!YI zQs}83gi~NGELuQOeQs@!^^lwI1QHAFKQtM>l;l01a?2o)!A(ogIjgdpbRAt4p5m4! zBS01ZUWg9(NEOf*PFCm4JdF^FoO>?E^YNu}_?eroO5VsYm^)to7F0k8)ezabaxxMc zxSmgdn#?wqMZ#%~nzE^|F!emr53s^xktn@G5U5n+hDA#l9ULMzGEAUb)HXLz*I3V~ zLx+hPI%Xn4bK64lGm{MU_j9ASm*%E=>{y&1E3d@Dq<>_b zzM&D8tXzc*d?u#TjP(z&rlXyhA-Q<*3cvgI2f1_GMvk63LuDdHG9D%36)EN&G~GZ3 z3Z~Zt7`CbWkDUNSfRKup9(XFxz!HMlLXk{1N69TwEEe$tNhzDf&*c=SUkhX5giySA zO(9OgaVX?-c#ebb`D(hP8^j_JkUrUxOWuP-G=gPEh(t8f*;$-?fkZ5Z=le{iGgu*{ zKae`W>ck?>cq~g9tO#`86xUPq$fu*Z!(-I-oExe$l5Ll*3 zBpy`=nWkaN5~ih*o|&NM{8=8@y^~+PyodGc*Rp!$GP?G>!sfTUh5qS06Mff-MUohr zAd*NjmQhK@=gwcGzPc=Q)6z-hOVpN^vAV61`Hl5F{`@}dSR7qQs^by7LWWpX98E}S z>*{3Xj4PJ6)zY$H0Ue!7WW2mwQPWUj@KT8nZ0VpURp3`Iy+%be!kW&d z4D|IeHZ{fK&Lvzqe~Gvd)K*n6)IY?0-C)t;b_V+gscUY+Ef$EIp*smx{PQpOG1T9O z7ESV(U->3eQ!{id>*U!NUn8c&_{b2KdwS`;e2JG1Hqq3+7&kM`hraM>kOBYnFW;x@ zLN^;$FXbI?eSk|B&oG=3R3?)+em|P7+@mJO$Em5QVR3Uc)1!m5)K}3xJWbp-c>6uO zkP>o5pLNSSSh-;X#||B4Xl#;>r$m9g?{k`|o)zyWx z6Vz2zQuMD;%$2CGtYF98_i*yW39gX{!Q&c~E4~bZmbipBNXhd;oD339n zo>iYuWjPT;XEIa3)RnER%3M)@bO9ByD3ORwMbu_2?V{U)vhbQZ)jPyLJ@q1g_~`wt z+p>k(;5d8s?qloD+u3r*4vy~GNB6NKbZ**&h+2q1;&_r$=(1%;65RXX!(2Ld88m2X zZ$*o%~;a@fE)KXP@C;fAj(```YI_rB*{3=R#`)7{I*Kk-pM^O?``r+@l6o_g}} z?>_PXwq~IVL@|@bifer4;~&6tN-XGD$%z{?%ubHdzVJ@!>gq_RGbG|Mr91Gw&{RR~ zt7^vyuna{_QuiK#<9bw8RnCh}95xt74 ziX@3xoLBz#Tg;}?7@A7?_6m8r1}hlqslsy=GIP09pfEW~X=IQmj~rm6?;5iXoIH1h zu2WsSuZs|{x2DIHBMf-#+F4*+__;D|MvPRre-M!WH8~;fy<Gurouo2Z(&-dqvq`3M4ohttr%BnN8$u%>AaFf&L!%-Qr|ZNGrkoNrRSiV# zC~XVdC>}VC?fUXvn{JbTbEfbAQ!VzJw%%+2ehrotix+&}nBtqZh0rv`3l1b1SEY^G zp?|Lv7Q?p+dpyEmEyBh*9C6Dz@j&=L=FkIQzL6i`OL=oLFHqe3sG;LY872_FF}ar^ z&tDTN#6%ZbNY4qMH$c&r!UEm*-{AjSAwm&4u!n9i>SrrV@C~GDB2;J-IDxYARL`QO z|6WLKasqjCoG(OZiHa)zZB5ZN3ZAddTPUDbtZsp>={P}vE-T!6-mwM0vl2rGb<_nlKQ$!NuNwy3U>>8nw~P2%{6zG&eOe zHIqhq4i$+wy#s@+Ub&pq^c2OCgXVh}x<-3@8ynWFrc}tG5%33(-p7q=*LdaCSCN{@ zlKIsvS-gZ~B8Kk=NTCXrdp57*C(nMB^LYo`vTrtPnh0BT^u`o9>dgGx^yvzjvQs%=1m-ZeJ}6(FP~@Aip5;*8(}2v60533Hw-LI z;uiB{Q&VahYZ>^c=y^jo(PCv7(HOq(l9`z%<@=brMl=>DlTM=>8n$gAh>^4{QWK+S z6p2J4LvbEL8bUOs-F6|M7$ zC(GHmek}pu<__}U)^*g@)$!E66TE--27dX%t9`YU2^^-My0+pM9S4c$Aa~sIIDFCX?lVef8_4QfU$qgU;oh^0s9y;zsus zzVxLp$%o$h0Ka_hW%1639$?+NwLEivfVmw>0*0=mn--O2N#40*9sls!X%;qABZNlD z^RX(b86(cmj$US@7_joTjdYzj$^I8!WY@j-u>Q{79N)8tOGggVzHtk>sWVz|6@^nu zoMN6E0|V^1>n?u!{l|%l04W2Wd;V2{^!cZM{2HSpLp05A<)H`f;U_b9tNvwbc}?IRCKc43*_cEZgR(6IakOF5Slta_Q`8KJtP0 z$cpkZ(cIEZU1fp??t3f4qr(hM&C1z{VUeFrbEU7Jt3B5dny!++b(2y_87L@$a}W-x zRDo=0I#T)sQVrr9*Q2GSm6ipqeDRB4p*n6#`G2$bp3!lg=h^P{?lye@40PVB@^;v}}um&8hQTw~dBktNxZELqj+q)3XrSFi&h0T3M+ zVEXL#en0kr^v^GAowJtLIePzMQ1+0s_fzisy0JuaQ?I8k($}mRn{|h<|xCbj!?aD zIeIXPn=@~C3ME8zjluCL^7%Z){xI$H=P)uc#Y;O5GBG}Zna>jp1(7J6x!6NGmnUaQ zbigY^E|<{^QxV=$u_e$+5Fo`3zfD&S&qD z;|%7fhy^_3v8sUP^P>tEH=8D(H`%ay31Ya1H!tSsSg@GBu?a#!KjB~i+fJ+9j#PQ~ z{EyDN4Zt74aWEX)^<*vrFQLzN-2%$eLqB?tyFzf5t`=PMH*lMUAyOeFw?OSL6x1_@ zVol8OfB!)H&yDYQr7Yy5dei-xbl{mF5m}hN`^61OkL5bof1>b=vcot?Flfrv|w;fQGLdvW3 z-c#3c(KL@+tpd1C0b}QSDZx1lTuD|{sjsf2syIs5@lzP8f(Qhe+tJRYGiS&qQWy=D zq)eMsDvdyJb>J#{lcpZj!#iuQ3VAAD2jJ2t}Q_*-sE~_YON{= z;rRm$pH3hYW_VGL82EXzU&K|YhE{>m^pN77nf zjbHOfSNGn&fs|CpTavq1brKEwn3|r(b{rHT(KU^>rdfRG?oGUSu#2k7a{Ri6i$Dtm z$WM;4v9p;4^V&$|a-=QTvG)*57tQC-?!TSi#)^6F&39;;T}xwg3-9bZ$fh+bsSiSG zVu(98tmdtQXBkVI=)z%gVw@tM%LBJ8r*&=%^|jSV1mmNlTfhrh>QF3+;gR_?#+HdEN8wnc0^ex9yV7ipV6pI6@4&eJ&) z$MCaYP9wp9kIJ$bZ4Gs_HP+(Tm3-pE@8j%+Zq#rw>le1OsJ)FxpLw2hXHUx&t5=E# zKlV{kQy$}E8c8$&$`i)~sA2{^GB{!T8uDfBMM}iimD;?(}I!*RMyo zj@M+XdcklkC<=#o>h)dxyK1eFn$XP$dOhKftX!NW&MrW2U9TvE!Zt_$MvUq2~zBP1UFxBp-|k>uLoFwvq2{y>25{pbf+uHc#HUZAR~f?Ph& zcfR*+e8C96eC!ESMd3={uzdL6zbj1B;otuAM@+^OT)Q@i76|Z(&pdWo@VcL!; zuc~GH?nAuz?C%&I8fHOzGXjBSTLnC_K-Dxapioh+4^$k-x&Ca`3SU2d>?C*Ib(i?- zfB0JxBmF`Z7IT^#M9;`H)6*HwU%kde#w29uxTVGP4GyD4qSVc4BA++Os1}V8gN3b4 zyl|q2Evx6#P!i_MltnOBL}^i&I|qL<001BWNkl?Nl7uk@4CwT`f`5wxj*5F9fz1#Uqxe8IUoAc*O{1_X5AM*OgxiA;w5g&NE!X{ zyx6g%K=#~~v96gNR?;{e85-Kj?TmSK2ym#vzG}l(p zH9fBAYU~d|hVP#LgY#|!@JDc@l?^D|;2~?ujB(eSvZpK?O%a52y-+O6>pFU;P?&3l zDp@H^0HiDsgbGGm35Cg-OQ^sx2d_BS+#4hvgco$;B{WiajmP(w(#sAo9k(FE0iK*Z zU4u~wHglvzSG-9wQj#wiV;zLYLw3Bir{|>=n2uFQwY15bCZTYMlG0+%ojirE8K^-& z%^jWeo;gEyDuLhc#}|!~NTnIL(nDof;p?CM8oQ5Q;M#ParrJ_I|NgJ@^ItyBmBCSb zhJmgKRxVkSLlh5Z+ zbpyvO`~wLW>3GGva6MM6kP4QxJzs?ij&ulyqx|~Wm-zYPPZzEo48y>0_%T)8Lt9Eu zhwBOj$F}fk8rf75Uu-s-u6vXeA&8Y%5H2Yv7>c0!{FIl$XflhP%W>D;cXIOR34(@B zCY?qPxHuGyfrg*%o-2I+%yGW=&)+}`hH+hqp=@Y4QM3|;LbYA##g^gUCk^k*DM5- zIVhd&2z+e0<4*q9fBb-{sW_kd$Oll-No6M4xM~^g^A-SzbasjmCR^^($j;(S%3sv^dBT#Iencd`EF^~_(`$;r33)4t(Wf~A#Yg@Y~xvuk1;z0%9! zQ zx-L-^jd9Pt_p*3i3*YtpZH)2v>8JR1{?-oCRH{W92ZMU&> z<3^6|c$&3m)mc@_=!T}v!H;7N?SbFDubiMjCKl}NUA{2>| zh{w6u-N)GYBu_l?jF_5EqU#!ps*{+W=7pEu6c;aFrGH>R`1~PKiD?D~UlPegigY$h z&y{P`R+sbRpFD=N^F06JYg`)`qPnV_uCv{^5`O!;H<*~1WMnjknYVBpOT4oygK66w zI(U?!;c;rK%lW~NA7fj;MXaUW3zEbok;#*F1%}^`rZ|8kpg?VLn7v&+TpJr_>xy<( zuUN)Ee)q?$ShE^A9w(JCQB{qA>KT>m8ym??juIaqM>ll5R1kqsyfK)fs$N4obB}aq z7S7&w-Ly>n{s4dbS6{-=HM%ZeVRl3z7HeQ={1nALmG)K0NmkW0OMuv;3Gl`&5BkF)K)`_xfLsyrm~@hvL=JY%a;*Pq{w9RD5}ax!V*I9Qlmva$Jai#71gylcA=X! zi`tnUy+$PHC+u^{PEUxo#(L^!)iXVnLwOcJae+^ z71pv~lr&VYA#e*nU*d&1c_>oFoB9_DeqAXDa6}!dAd3tkq4&yUw5{NZT%&Dz5X7XK;>Q%B5Gx2mv|M#PItV z8XU%TB+=q9wQX%&K7Ro#?on;3X3wI!wuX_>F|6biOFLV*b;CN|*>jlQ(_NIyW>$Xr z^8i9Yy}rEp);2cZ`(A9-$GN@%j-EWjvL%aHx?(xo_Z_BnP7^n+U&HLCIrsu0W;Zkt z))1P{M@2;?4RhuYw*}#F*bC$W?0mk!sQ38&uJoEN1s9>HUbvQ&Sg8c}Z&=8p);T1T z(_{-6KLZP?7$}M&r9ddEiZpY$9$iSfQc_k{DyAmK5sHdLp*S35&eD~*R-S=NmxzRd zR2GLAxi)~N3fkv)aOT)?G({nuOncZq#~}@j4G*(n@f>1B5qyT9px?lC9Hs^bsV@(+ zX8BTr!7xRd#;ZH`^XgmM`T2ML30;Bqh6r~pY39k7-bRTQBXph7ks%(ucLTStTSYFP zC!R|2=9}Btux17Czw0)Jrzh!{+sq@+zQLM}8@X`yJc{At&f7O36qRceBZR|I0zO@s z$vEvT^?d)^-@;W?h9*Z5ipqF=id-&FRar4bp&(V2HOy_D!yDUn&^I_lG#bIm*UsT>D%)TE&`)q-bcDPfGS-a%SIZy=id<; z*M^6gN+ignGd%v=7l>6$A#72w&{2H>Lg^%TE^21->=E4NI{x)re?u;pVLan< z`eH8;vb^`+t-SH(>y+0t(w9~E+4I|oCzGsPx{&(W)%@(~XW6iziF>x(&gl3UJ^j~M zzNCXsee?k)C&ol|ZMD2<X>iAlcjC-*SWdzrb-vst&egOW&y=U#t{OXmi# z#>cqQKf#$Zm&mF?Ow&RIGLEFWybQmgq2+40aQqlWu~LTn2N)e1rexhxjvYG4(7+&n z_wWxX3g`?aOr{fgzVpbhdExaPOs8|)W?AGd8(UFvq(`<=6$M+>P!$!!=TWv)RY4bm zprI8E_})F=aU~I5p{=2YA3nd0V0ArnR zOFQP0%;xAxnwV07=^VNuNTpM>7%p>~oA~Gh_wl(e{3Xvm`3T?sm+!N9(Gup*Z{=6N z_!W;n`Unqv=u>?2@4rgVm8;~lIsWhe^$&dFlMnIuNDvTfTAE}Xy2H^2EeJoMQw@ynn6 zfS>;NFPPui$=ueteC4nHp2r@2gwOrO-;>e8D6S5+h3P^fFYxIq(s4Z&yb$0z{P2za zq;e*ju94>=0V~C#wq~}y_&m!Nw6kG;BNu%+PG26tHPf6weS(33K@U4z@K>366HU{Q zu7hwL_=D$zQou$#j@Lk|g-yY(1BWTAYhYq3$@v4vaBP>UY>xNbeHYu0pJ&h6EBx90 zw~@}}36@tdJT!`yb8vA<#N#a4x{mUaB2HZBrn~D5w=VBsPF0M_(NX^V!&_OmppC!! zx1Vt0#3@$IspL<#Y~j&24v{ym*bX{BTW;Z-{6|=IrS;N4{81KD(6aG*L%d`s5AP-?K5QIYkcAPj*Lv0lmv0^S= zzC@8BD2oJ0OsE*TM)!qtG&MK!sZV{@lRq$@&$|u4AHfOw{b-tof#R6IhZjMdy*etp~&|% z{9d803eVtc+Ag;AewW0%2?aE-S#bZrc>D*R(hR>@H_L)jcf1~(qC=Kbs3O^ z>n3QSc+-E!y+KcMB^bJbY39jhvuM5m;ed~LB831Vp&)jFCM4vIM#B{zQAbD@T`1Sz zLxDu~`KW4ar2F(K>|_$n2vFJFNG_A+?5Q)X>1e{ye4OnaFvYZx_L7XJ@|1pu3O1dFK^@E;p236wlST_lg;J%$*-OyKCy`{x7@_( zV@DVt8Dc15a{BybvU!Vu&%hR*3C(qE?{C*s1Yl(|=!%O^)3GcYDII)1AF1(CK6m?< z*tBXjrjx<4y(zS+3Or#LUW+(0)dGZ2gb;0l*O*h@KWteVH?AN&ZRK#)Xo3S+zcljy;hxcv0gZJLLj%+?pOKlZv=QYwd zJi*yhr{Ga$LO9 z%WH4^o^Hg?(-p$o`*-w=z|MIQNh43#f*Vmq6*JYE?uwT_nK)B zt165D3X+k8Nz?oqv_OQEC9tJu^vh<_#QYi+MIkO)HZQ)ujaYGnk$4K#A7StQ-CXSM z#kDOy(6NO2Scs0!c_dO9YNJ6q>MLk(Yi8ln#WXg|!gO+MZo5UCuBu`pK25BuhL*N@ z!U#sW^;(?0`;Q>aEQ=N|Vk$Asi?6=M;?7ntdmtEKOjG&77yp8?SuK3vW1qxzY;bH+ z4uo`plb6Uy8KupwIH?3xjg3^zs;4*-X6u&Q*|+ZygVP>`?B3gNXKZYo3r7#&rsB*l zt)Qg1gji{cz|{%Nyork!hKFqt4i5eQFs*-gbGTD4#@F6f%?>^^K6c%^R<=nt1 zub%Cvs;q?e<;yv%>FnF}4r^{&&xX71VAtz!a&X5EmTcHSX-SBltNn}&4pUlIMs001 zQ_>)nn8Z=QbsgI0&A~D)LO~yzCWuBuG&aqmf1sa=iZU!akFF_{l@>7-pP+SaGd-8i z6AJp67#$`xJ<0MV9Srt$vuw$HLII7dy*<=b#uytN!nO1CU+G3u1=UqC2Cwx2QclIk zMPhoIk)b{+D`K*`GA1sa??U(cab25`Ca|P8U@DLJy)Cfog#x-rvbIA@c?lhLWgNV4 zg~$dplcKdy_^b7Q2-x85g0&SWf?&g z(i0>6^|u~ob^9z@TITZjp`!#VYLSsrECgBC!AvAbT^nF>WDs5T-ZMQp!tzB6naJ8~ zJKTlg=Bcf!;QssGPgmDblF3oB<1RVVdzOU)L1xw0i%7=i^06K^-@JnPbDKalXsWB> z_Dwg_-E)P*hxh!yP@VmM`@Gu#{1F^O)xClO0n#(Wrc4X7FohRVlC!*oOi|Ff%xLIm zj60sjUyyga;@waMImb(e)jdG}^Q z6sSSmFe>LAiC?|3ArJy4GI?&UjqoSSm+{-f=Q!Nm&sR6EB$+jN;^<`@BXnKvWK%Fh zTNYZOF_4Ov4*+004zb#5`g*!Cr>9VLjnbw@vX(>lnJ#YbY+ym#9BMn3aAMb6{Ob>X zjuZ;Dvm40Rl3zUa3gJi?S2NIpA>#2k5C7=rtlPMm_NfeC`qTqR*P*4gjn=tyXsn7c znR8jZd^!F=m=fWzYV}Hb2S?Ejz2F5=Pzok#DHQVgEG-o!jE_$c&zh|4n1gUFPWB8j zRZ>RYaTysOAd}6K$>q^}K>`6UYF)}gp1@2GfL8>#5=_f0Vtu-bW!a$nSh8XnJv~>@ zHHClp(u2&3MY%RIi~veXVkrI~6B!G?>NSLh=G|T@D=N{1B$1pZ7z~kj;0KRCM|?U# zb8{0J(?-?(OiWGl`rEr1izoQ?OK-7uaR-j$U`d~e45c@9$$Ge?Q7O^5;SBXzztMY@$N5*0;-Bs)$6EKp$JAsM|tnvcd>l&VuTQ+vL;n! zF_L+UoE9LNorjD=O`0FR^IJV$K~qL``ii4Gpt7 zb@Bu+yzmMoeg!jUGB%y2ym=lScdVfI!UgK)%_psguxzjCDGlfth3%S&pkh`Njb#yX zxjdt(1nF#!d$!!o`n7Ax!AC{H#9J(V;&1v ztVGjw_U+us+6^1naMzvedi6Cv z7kARy+D1N`;G5t4IwueBXWhyLY`o<*cJJB4#`UYX)ZNX!_uR?)wX3<>KPW%;@sEmZ zBF=|Dc#qH&my&3Z2S5EF+qb_WKJ(y*X`Ee0w5W(dS7JFgHXs?(LP#)ltq>R{!Lhl2 z`8;Y$Ld-5LVqmD8MNPAK`@jKoO{MorA3uNU1%?NQc;JEe6N?pd^4JN!|M0iP*kCWO zy!I9Wzv2B%*GpV?UFl^s0E*(EDhdb>nX9TQLa3N#j*gbuWK}A=-TU!77Tb64qkC|e zs*ui}gU85?4Ny^1L@t-(wb6d!MloYK8$BqP9O$S2#1Zst0&I&^HjnGL%x!KU9UmiB z9wQQt0Fsz02xv(rhQ~=*Cc*Zl=#gS7m#=5!*g>YdjuC2@OHR5dwvFcVp(rYrX^m9f8%c{jg|8FvrqHb_M_Nkb)-=7378(4AmV2Emv8<#inNKx z$NAX{J2*F)XUc~8wUumHI+p`ydicp>zoEIVL<&U}fnWqFJsEL2o1(I^f?}y*?ma64#^(Ak+_zNsgS9(RV>lS$XQeHRBI&NXAE**;Jb`UXiROw)- zDg~b@qM+gT7XrX${ytAiRFKgWq&&j)G5}m=OvBA9&AQB&OoTrxUa`HE{S;7o%ChvCDlB2=o14KE?RtG#9V- z(>}ME)vH(W+{>?#&!pLO^E$2$jc~Dlh)^(u<2u*~P!tr`+hAmJIhMCK^U!-YQxu8t zwTFL%Yv%a!gCFMKAA6q1o_U^JE{~!bsJg_j8uX4%bG82>eqBXTjRJ#zBkAF>N{Va01ENVdqUK^7*g-y^* zV`^ol$+;5UFc_Okv-?;VGEzdU23ngNF>@IlSJKrtMs-acPOya0#1wDtJ;L&NO#}lz zZeG5Smk*s~YhIsGrwKc}WC>f{P%TPE%3cfOJf1 zB0A}84h6|{)}*MSnq@Z^V>=E_Wf8_Er!X|Z=!8Sgwwb?T1(9%=RL&$3A7}58laz%t zd@7X3idfiE&oes?v1097P98ZzOKU3)^IAE7a37s()-ktzHpz6B@nn`_%|Ou&6e$@S zpP;d}mbR7#eBok}$tm)=X?%wFiBS|C%?JY$$I2jtr*U?y42l*Y7%oE5icju0wfIgk(C+p@RphxMeLu2-2wpekID>mL`0`Ad} z)lpkrC3RI7*Sfpu>F%biw3L>{*+c>wVO`<=`|cyDhuL|mo60#Iq;h#m{F>J&s|sn$ z#-}P?Se_IF9Fv24_tAT)hdXatMkxA)YQ}v3`N+s zb2n~LDRbs`c-Umy#&sm7X`zHd%&x0NQxw8J4ac&*`<@VJc(NCdYUZITbJ;AHFP_6m z#_3$WhK{An5mK^e=Pp*STgRF$cX9OXw@HqUvg+n_j7`L8o!?F>l|mH?ngGM+@z!gq zYs8(K@8HR&pJM5fMVvo>j$|?;0--RMF86Zp)-9m^w6L3UqAgB z3j!g0fgtBE_ON!-9X$2yGt3?sWF(%E#YLuAfAa>O{@sg6Er7qMoRN_c+FP5+Wb-Up zvWng-S8-jNaI{n=6RTW+_y7PP07*naRMQldRSGo}C2v}uI$yeEO&h&HjPq!6UZ9uX z&^d7V8p1V6TP}AlX=6A(g{tWUi%U?arkR|WAe}d9Z=1`&$QWbeqjD-SBHCK#@XG6N zqpC__qvd(rr0bHm91KnM=w$K+wpvrYIiAmVJh!%;9M^c-nE`P zRxf7v*{Bc<)6V6ck0ENC&BSZKtj% zD1`~15Rh^mL_Wj4x8Fx;tQ3h$%iKBddI0{1=iLV2kKm+DOH$Aof>-=T4GqUsJY1M9J;IHma4nfZ zRRp!+Ag1FKWGtSUvp5n$RTNUGG&$ER>U^qK;CfOTulS!K1w{-UU(k;LvX!*GVP2Qo`~hWXrh%EE4{55nel5{} zK{)6qnaMGo$rpa^jb=d=o-E0uB7vdZ2t3nNm98t-STVbtcPi&Ip^ zhrjUG)D(rVY#U1tP}e+%ydLE6r9KWm{3Fuo45|?1G8udUKUyHd)xH7Z6BCRMj}WV> zqJ8CR$Ryal?=V%f8&NckbNxfOj!k_-15yeP^CmoAzjPpPITV!?kxM5zaOep2vzrix zk9}t@vi8_%lJN=J=gviFI^*NR2vs9*Iz0Z|Yn&d86NyA{guu#YJq|uzgQ#mdmhI43 zWbk*Nx{so8kVMi#^#!P$)xhynT~yDir*mE%rVC~+k7YXq41;huT-YoCigLY9lz?M9 zOs2DZ=kX_adFOuoktpxKc?Ct05SC>TjYK(k<`QooJVAL?B_ksf96oi9dp4~ll}=OU z*V(eXlha*iX=$2;?YQJ@n|Dr}P>OM|g=wZY11&of4uzuAt9)0FT(o>Vn zpWneNzki*L^BdW^`4&beCdil;MWGP7;YTV80aVgcafZjHm`tajATP^HiBA!@nJknB zLDA4OjabxACYhk?d=H9r@mV#fh7X^iAykX*{tHgJwKZHgdzKX|mT~aVQED5Th?SRe@%UlpIyRA#Qlz3_I-WF8L6Xem=o=cQq_hSj z7)94qLZJv!S~#|eW`s~RKhm|4st;B3;n;bviNr`L5&oDL-XYK4-qD$uUp}TLxFbu8^4kHk3z2_dxe4emhr>wk! zSGMm&_4x^^l3XT3ZDj>t`P`@R2?&M)l$BSYX&Sjqn$+|Zs;Ur)M!7Z`7n-3H@cHQ( z7~zxe+sgVS3rMA=xYT!zShSd?+A216HpyTxEG}FdqOq=?-CaEhy!)qG$SH{geOx+p z6eW{j{nAcuUed|_{RepF*=JFJs^S1EmM&oLj&mG$CCeAKaq;X~I+reG)w)d-HFq-K z2omxc*sgu0Z6o*rtUPkhBVb1StzX9|hM1UDvT~hx(d2jA#jG4(;Y;!v^;5dWZPL1dHc3(mOcDcs7sUXJ9Ady!zH4FPJ%! zsSHGGIMz4Khg(CPeK)^-eJ`$}a-i!8OxqT_kNAm|L>Y>w+0*skpc$g;@&L6bE;2He=D8imuw0j? z-#i9-K!m~}jtsxd>A`7A+h(IF3Xbbw6q0QfDZPojlpfJdH+cJ89|0>(Z~rxR?>o$$ zD>`}at!w$ppM8%0fkCWH62l*0<*HR&e*AG+RauUq8(ylp@W^wv?U2u#q?^0D9^n7se;?9*zm`Y{5;hUwT>{*<+)XP)b_R%qaAw>aImIhUE@9kSeckdN>s_VR{DvR-# zfBrfA0Yh%NbBox2wwHOW%@~Fcv!;Sj$j8PtYuLDEJyNE)*mIfI=0$w@t6%1F&lT*c z1g2>bixn}Q&EZC>D6VTFb>bKk$M;jcYz;CPCNO^mKIu`83{623g|uMl<(jzC14(EC zgkw=;CYasa!kJ5F$s{K^aNvNP92ya^78M~Cq|i~2)K-;>vuBUVs_F`H^z<1L=?q~_ zXDS}Y4hZV1%4nS1#yi{kQ58?duj&TlBiFDUhr0SX2q6gt{rG)4*T&)u50CP|eRuP- zXI`beEJlQ|dhY7gcRc|A!}D$f@JDcby6)i|T?a+iJO*xI(iYIXl6g9BdBh$?5Yjbr zj)S+I^mK@-W{^021d&e>TD%@RXL=J1M_wwqZ&@Xtx09TT8y|6E)97*z3m<%(K0f*d_jlom6HKY#g#6m;}w^tE71!ESu2y^{Tmk3QD4rFUfV-^OCu%W zAP9w7#R0|>lbktpnq|wDF~4IL@l+natujwpMj#TVy|Nggs!UD>@cA^tp)jLSPYW4T z9sKp>7`Q|$i_v7B>X1$-;KQ^On&vc;oEpa&?k5-O}rts#D-SVw{$AsZG&{Wl%2rE960wXeu zO4^2aCePZNZz4H1!iu(82-iYU;KYS)u8fS+v1mSM24&SX3`|Y&^7cJ!Ub~c3F2~Ia z8fmWy%S>`gsJfq_sWb+LsJNs#0X4Vgu)?I;Wb2MrNy|e#8p)CmdVLe zT?BNUNOcj1j-H^gxrN0ob=>r!yKyX=&;IQ{@x!lw0Vi6<_ue>gz0r=vO6W@K{PUwP zF+H6m;MXyH0c=|-XqOeFYXYFE2Ci#?@QjQC1?gA>LP2)yJ3&LoVx;CHna!hy{e{oC z2Lo_z=`}(HBY-Bn#$QoY6bZ5b7I1~?Nylu7t_vcO2&d2YaN=AK9ka^B)$vK5eSJH% zwN>N@VcIU;Cr;4R(LvpuRvvxo1^hmpk>MeVH*dmkyPUstneq5EK2^ccR4l2m`_ZQu zP2})LOHj-_7rT4t9~@@EoY_>yV#FfF{P3~Iv22?yo7PhvE2g5dmafZ}_~-9Ff~)9+ z{61cK^)1#fYGY|;n8Pb zexCk?m%;MLhv^fAc&AE!hs2?(|4{PM-33ItM^D_ z4T6E59>(()Rk0eh=m_I|SJ7itD4JFv#7Phemg9P1T|$t_=J@c6R@$qIh$qqn0)CG7 z4)TxBY^ScG6u-}h>MLg|K1Io;0TMY!XogSz=9%Bhqlb=)bUH;(Zx5Po;Mgv)STXUb zY0jLxjA>fvno4zLDXwD^3WX3tFg!d$V`D81jrH`7OtNiv7u{1iG*u;+PVxR_b2!~U z!qw?CA6&hFhO#KXK5`j}J5|f+NkmjbkFs98ytHd^U#S$zpP*i&D_;o32aL(9sK% zHeFS)UC22Sp9bS2!=zKw%<1&fa9!6k)anIU(2NYncHHaOOt*j)^}eoLFYpC3QXH=5 z0cd|vsQdi^Mz3Dr;!D4w?IWMZA1=XmY#dj55+kJ$+=WL9x~@V7vbHC2lHvv$RN~Ps zd&8_I++rbQ$aq&ONuQ^3rdo{7;HLQ}vHUJ9-& zL3JHe!-wlE1J&>hPOeGLauKQuLc?e1n5Ko5&tkh014p{9D_jJM;U`uUp{S^c_`+sX zRsG-Wy=RnO=UwjoyLWxs^rkY>sP`_7x@60}#HkJeC*TkuA;38hk^>2x6X3v03898V z3W-T#C#2hn9m|$1S(YVPy-TB!rb(LK=jprM_xW(|kCj4GW19~HtCvLUb)mw zW_T)YqIH9Bm^MOajWPm4zkp%b7^a1hFtwDyaBys!iBiBk+r^9CivEoo%_ssxCmb7w zAc`bmq~f$xNhqWEy4H=kh_`=U1eW76HZ;LgPko&*^w_#$)_}T}XS^EfQ`T%eA=F(M7JTn7e!pejL8kST3T{HGK55f5oNCSNQOg zzsSv7LpW74xHRtbjX(J(KKR~8nKio^!?H-5rcO4GB(5Wo}N}L2Yd<*`W~%xg2TNVad{kC}EN>l(20RB_-)F z!VC2vNXZb}aX~=FT}*H9Amamr%v!vN#-=8EZ{MV%GQ-IWSD4w{%=NZ*f>ME0buGw< zAdc?V$>*`>1Vu%{p~4X?Ub%>Y(Q$kwxH4X*&l{&$EMf|Sv0Q=X8I2T6C2Fc_#Qpc& z&$X-VJp9<1Q#!!XDnAzky6ZU ztQXtXufeRS5pDfh61OKwOBaNOU~F5pl;!hgF*b34qzc%uWIjK*)QcB}WD*WD7cJ)6 zsT0(sU6wRAkTeyy2ZrhF=;o*Uk8=_gzS588xke01hEN&4Uo!3Yv)7TYN*aCKMSgxY%kdP|CFtnFw*6g_$ zW);QKC}t!GLm$&k2pM>szi@;72VUg^kM3c?+}Zr-xu1w-%bLU+U044TE4BZ6$J-6S z&%lvNI0dA{kdb}>$1;lPX*p7nu`DWFn;??$5}&x(RwPXW6?jx^zK1A?D0v>XW#J>@ zf>}@wqdQ1V1u>srfB&>?-U;^71-`n&;h&}fO-p$ESbJ|o0Y$fh^xf~qNTlP{sQy2e zn4awG>AV2^cza>Qn*hU@4j+?ungGW%@cjTconhWXk7LUa83Z~23*8Wfv0OzPrX?v$ zH!WqU@WO!FstTTY^#sqn@Ct=ckxaV$#Sadk0-xr(YARDMQGSZ2zw`xu@Jv-)I4K?a zA~owdm2xpui04HpA+T+mRKmqD6wxGt7uQOM=U<+2!-i*0K8m*)j26eZ8+?uQ=WGymgv zshi!x=bnBR({@O?4xKl9Y3~TgWKtAzIg$zYj@+s;lhQatFTgTvOeL``fn`{lbsgzI zu`uva!X%N*AVZ%-GKE(tQdeJtW0;&hb%us*tMRYlW8(Fb=pHAB@s#| zYzl=P`3S>8>W>%eRxH3Ww9(o$Exz;IUIs_T$kf*9O_d?2sIB3dpB`XFg~_Aa*O4!K zc%Da7Vd$_p>>`l$=dpECo;by>4y5%U(b(9=6Y zPxp0h-RhxbRwLbpZYeR`yU@e7$&nCYWbtz{4m#h z2dQ#RmM>mNI$`5^WeS00?;98C=)Oto=1p8Ud!A)W7P4~XGQRNDXIM15k)vlWY1Vlv z&BW*^1J~O~nSxX*&D8iPk7*?|SKdtOECa*Cuo4;>8%dN3K$rxf zB9Y2qIxe2)<4Z+SOv~*IlrS)j*t|dODMDjsP18V{W{gXeS|1#Hj9deTM#p)0$2xxh z*FVhZitH8bKKX}# zK{A+Mt~T&Bta3s31z{ADaa4L;@42tEuAnkt5XC)DYSk_Wtx`Fl{PQ2`0wA zN$ciTKK;p0@vaXH^ZfZv28V`t=6ENG%uFt22gTUv7_-O6=~8{TqL;Nx=OdLQj3jB- zAnPRg?2lgOvyW}%Z+`9P@TK78i#N#n5r%D(F9#&+nwYs^Gj&PWwrVl6KJ(jLXuD3T zqMH7REMuWTeKyN`KkzuiV-vJA)Y7_P4M)#h)Bp$s(z59sm_(?EnTu92f5jSx`fic3 z1Rd?yNjnxYQcUGMoKT?*i^2Ab+_-q2%1nydx>{`(HiGhIK2|AAb4|#9x2qYnP&)xzAhraK(SQDw2~D45YHVpi?Z4RZb_4J;a7dw*!!oOsHw6M8i>Ka?uw^~VO=80Y85^c^AIG}~In zw3J6T0bZze`fkkjFZcm<^$n!!8wtYz8}67t<+QdxrqxW-jHVNao!G=>83v(@JqOe8 z1=AWspHM1-co#AKvjU(5fzmXVs&ta1V=<8{QVtcV;y4elnnO({g#spWMFxk4SlGOP z?dw)^t)qjk_BPh8TZ1wzA|*&A6F82A@A;Z$6ooqdIL;~XeIJ304b=iAlSCD1q>OZI zxuvIEhGAk_<}^>AX$Y!inn)Sl`MYD=SdLAhP(~?5D(PYv0^4!P zU8CrV#WK}3)tozjnU{Y20+Yidc$nPmAEvUhf~J|X2&6CNs^I;83jbX&UPSfU<}Jb=JMpSj@FVJB4)iSdV6lMWlJlzZIN(XoJ5i+ z@JYHh^IPU%oVkW&>xY9OAc{hSFbEMy<)DOxB_a}Dk=EslsH<;aDqkR1EThs@RMppG zrYf)vG)5BLG)_vFs@g`I7Prj7 z5K0?84V$W}TAn?4jOPv=mf%j2MGOVd_~AGhDN;xwP{PpnpJ^?%5XjJH>GEZqy>gW( z3i#^Z{Uyan^6JGK6xuuSy&&E~3T!*cV0RBa2u`0qM@7=%^zjocTQr}KKmIT`hemn+ z&~fhCx{-q?&arIeDq45#q~wLvRV2B5^%}e0^&#$i>@jxTeK%>xVqjv5OfpGW$TF+B znX0N9dMBq)c2Y|jWk@0nD31>#grcS*O?7Q8frJfgI=Xb7S=c)x1@;QF%w?0nfl`)(Iz2iAHuV2Tk`YLX;UsG-(DK@TNK}9;l z+7(Mk*EeE04)u+Vv|Vebx9uu*Nr!A8S-N&Lrhr%XAH;SX0^g&qxtXT9EyzgHHJRh9 zM^EzZJ=;lFWLUakGu`LTaN^)WHte~F4SV)*{=k0DzIuo?yLYi-<0io1@csjQ>ers& z(Or3OdjJ3+07*naR1ZAF#N;^jb+rr^eDa{TkY?T&4Z;6&5XDPG8>;w>vusf`FDKOK7aC!4E=8k<>Ie z8R@N5oK0ie7M(etOT)KOD4H?}>g(!Ax)PZ$@Fze29=^Em1UD{rF+4WLM}O`;42+KR z?Vr5Nie-z{`yYR|m^rh78`rO^TRk^LzFfjk0q?(eI}4g;5=hC|WS*Y!9P?*3QY@9p z<_q|qM@@AFu5IH55w%s7*tQ8~nZAiUpLy;LnyNAsJfE?0oUfr2J`j|A+?q!ECP(=4 z4`1fqt?O8^dNooR1c@=e_?7Qcld{?T!FN(y-#~TBA&4YpW#BAcL&Gk*lO zW0P^xh`}x#Lr^T2F%A9vDEpG^RF+5Y-b^}S;s-vBGn#qu;fMJ4k6z;BwcENu5(;73 zv3D!Pl6n&;r9uh=AtQoFP*GJ$|Fw%OUb>9KM~{nh7cOZeciE@Lv8bz0P#*8awr%$8 z-b^-|Z#kgP0Bmn-1~vq>N+kne5ndt9ji8lknri*$Rn~xPbr5A_^4mynNP22vPDZr)>m?)B# z)_JBZlay^RRStFJdE7)`np}AO5W+99a_3#tgjp7(1fTuz2j24TM!a$2H5}XF(7tC` zxMV3S7q>7lG)iS{4Za^DWdWZCFfdIsCN60=g^VIB%Ong#f-u4lLjB&GCMZb|C@sy3sTNTrDd!3ZA+Rh9 zH<2KjaLG<(sjjNv&;IA9xP0|8H@my|&ENS2X16S+xn+_5dJ*9`DfS(DjleKTW~wO^ z%hb9Svzi*|yV!;q1t?5}sRMPQxLJ&XkbF5{Mol#}wG9*sdE8{0FbJ8yWHDE7bRv~v z#heCes`W!Tov@h770Bia2uHL3b-J*Kae7)Ngo2=4VpiH=<sPPl>o2^<+?`uVr8A^63CabZ+e2ea<;<@4_(@O6qGSnM^aDFY*VU|7WfajAPn1#axc1ix+e1)EPEz+Q7wg=b76w zmm4EfT)5iK+SXQ{J#>oNnrd2F=F)k+gRop6op4y*RLTGP-0$<}pZgoaNRbd=7@ArG z3Ke;A!mK%ciRr>$2!vr1MII~WH8HcXj?t1wDFiE&cg*xbBnhM@fGDZcq5}jf(gTCg z(uv~A&;+SzqpVVjnyN~E@WLxBn>&MJCro-U_7RKFMX=#~D&X=4xeV$vLo!G8J;FtNxyB_3Y5AUFP z_AF*J*0cA}QA$%|{LhcPkCDkKOe6#2IX?CGU&jk0(zZn@JIVVV+|7rd_z1(JBbbDY z=RNiwKF-)^ik{wn#=VG4RW0MbWKvm(atKB&GZq37DayqX-Ti~qxDq#!WFlK+?(CV| zckey?!_zL zFIhy{^EiL4lU18GQd3<`2)NZXcoG5`5m_$Vwr}NDF{D}+NxC)*H*Dg@+0&eP^$=V3 z?56eJdpP;Z0WKXm%DSD~S-){T6H}86Webcg&=?%%qOrusU@$H%EiC8?>c!Lb}lr2^vq^%P4*N`8o&N)v>V@!@_+4rf;RB&sm#OTNfH;2YBE2`PF=N=|ThY_|z zOU8tkbdpS1<7md1Ge15dJG{#-h{I>d~|nRMLj%j2nmU$|#0ubjF>CYhk~`gM9nr)XZfjM_|+QV?;w5Fmts zo3OEk&cK>wwDRSf2qUQx-b5@dXd|q^dGQ5QdnBNvZ51OL;`-k#=p$zNEAJIs-jD$VgIIofaEfcTiJXPq|d4 z>)*b^t=<7@YwCIFz<>03y8-waILe_xq~c;w zm^gwvX20pgT!g@hjk?oQ{6Gui@guF%Gh>O3o>4)hB(^Yho}N;8u^h*V5r1B!G#WFO z)Tb9wKbMMgb|AEJj$Cex2zL?QpKl(AWfqSEOPzM~$sWSkTwsNf1b8&u(UHbcC6W z4a}R@!r-kNJo=9Jap>@Ib*q0^q+AC}X?CcLB);!snI@KH6QMc#I;0FN%R!(pO_R`6 z2qAGD3qJ_)gAmiU^@C3sxUQu&^?>h3D57{39wAH%f!1wCQK)aSx+}x;^u%3HwIB#3 znRG%EZ;C|}Fgi9t!gcu22S3cAG@WyFU2U}W+o-{bZQHhOH%XH;wr$(C-JmCIY&5oQ zCk-1ky8Hd^cmF+OWQ>z!@8?--uDRwiBe(w_g!?8{bv8i z-Q=;?+i&$Jxx@(#75)IYb@L_?1@?0BQy3%-UnVFc3{lBsW&g`z4Qj$QW&@+T+JwrH zLbDs=)Km}#WzS=R^8SmE?C|dxiWuxE>NKSy(@`k zw@EZ)Mzb6pxJEh@pv}$pN{-biI4Pf(EFFX4<(@l&q(dNM)brsv1DMf_t}VqitNbH>2z4zx+#xY#zk;>LPUkIF8_dwD zm2-=Co^hHL*AJ@!_+4g~^h3SNI2GPeDh^=*aMy$NuSy*pfqpb&ZgsJ*SaMv(qAF1} z(EcQD#kN-ZSqvZr2S;8Ee(Kf|lQ5eq;2rAxrR(OX;rph;6)KWxF0h+H zBQJ7d1I%L3!q85C;}{vCq#;b$*O)9XeSIMGO1 z5T9^2-t$-yY9!MSg`85DC<#rPe@TKEQ&Hd(Wzl^n4zW!Qn9sRQsMNm?D#z>h*6A11 z^dpm7pI15QDSk$Gf^Xy6mpY)P(!L!*TKcIy=2Ba5u+H2)cJ=Wug@D&5N}O7$(SH=; z+Y#5@0?)F;-$t)HEG2{Uy&U0JT6Z$ptDp8;H~7TG7a6?XzhapEE^}&h`3mC4kAacm zQN1*=*>+Hd4o85Ho12@!$DDsdkYQa4)>khAaG(+H_I>fd`fX{FL2t<%rA%K)=*vi|lV z-YA>O<)uHGuqtmTj{jw2!{Uf@a%D1^>}72w-{|@G-zVl~WEJ5(m-}9Pfd*@$oDAlj zZKS-TU(NQxYDr6G2r_M4c?0{vmsxls{Uv+JE&Hupsuhoq#^E1|qf_4kC8~m%11{H7DU6pk+EUTuCM<1DSGeKm@f}lW$G(g7CqdyH zr1sVmf-po$Dl27@@Cl8FkK7dgy4MTCf089TMS&vCKi=ixQVYhGd@3T6;we}9mab;J z&L=(yJZ+fh(GqN+AELN|Ofigbu)=rIWuut4875R6#%w^w^ELvMh-F7-UmV)% zJJb4zWV=LR%b4zCwZBn-Afvji+RK%`ber7!jZbrJ!jkMob)k4fKXM}m&dVtOr4maG zFu33kcZ%RB-H9hAi8avr$c|1m`we3rg?lc*x_9}7Z$UveEIB%sGPBJ|EB0A_H?2WJ z6t(sui8&3Y$2p3;mT;#(%^izTAH24{HWX8vzrVNWuBxB)o8HD)9OJaIGsjaM{(uL` z1U;oSKF&lpmE3Fihb?TEH7CfwRs!bvcuovUl@4XWLy~-4oG16Qz0s)N@-WB!YPO5ayqJ!a+ zIfj>$x9&HkBrDl{gkmL0-?Oc>)(=Cj#JcM6SaUe?LOW~nLWa>Y1 z-wC1N*PBO6=~ZN4#T3>}t!-l&@xL}Yj*7L{dd#qxaBaVj(${Ra#(T+sWtkBcIsSEC zqt_DOjBs2DE6$Y9H`G4)Q?JwZ`sXono$;wLkUKV-iTrcDd2W7Ld3XlaPIxOKRV_za zAKMJaJ0!f=!8N!fV-40%S@|@ykSvcX&k^oU=Ql=f*Bp4>K8z$q&QK>CiF~Gj5>vU; z-*tzJ3?7w@LL*oWMHPvBsYZABUsfaU>p%R9ZX4>$%Vkya5(b0rP?KS$I+J5Ar98gj z&Sw`?So_V+p(90n%d2i#eLKR{SDrQ!GTmFa(x0GGo~PUI$?;)Eu<&iP7ZUL5BQpr4 zq@hNcVq?YFc!trh3php?jvW!SG7b@;AzGEl>27bicYI_t+hTlqSaQg)L@H6 z#3fl3VrihtV8x?Ma7|rwgzg9Vy)38g`&kNKy7MM7S#y|$ItrYaqY=Z`m`hOC}qsKma15Ng)zP}db_7FQJ|HM7-FcGCpIzrbW=>L)Z1 z{HAi@;NUW*B(ScUBO!;8rUq2U!Acvl-WjzHHQZfHPtyTs_@cdE2+LXgCHZ>p$?a7j zBMMo*|J2Ldz52$~aUwWf9|kC@5m@Cw{VXF(*W6rMc~!W9 z=Y{{jfB#Op7lC}b4M|`qCXGZODTyjZH!)MO<6|1un}`auF{UoiYVng#*C;Rkx9Gtq ziYUR+_@5%p3e?yvR@t(#8Ov4f9o4z$fn1fd)kXrpza;BdYXj|qkB&FjMoh#$A(H1y z4OXHE+&(@}!xs5w>*a2lY$0!5dV(I=!cQyc7n6^-x9?hQzVAGM zu(Q$Wo1H#{&<4zoUk8K(;=cUp%8+Ed?Tb7>PT3f3uDsu)A}f^V@Y4qj5^nB}a9^(?qKBWm|zOLi;0&6+OHBVUC3wR+w$ z`7{I1d-<<6M?apIE3EPxGv7yL;Y$V%*{wH!WH7r8pji)L1eb`y&QXRJ-&CpFb7Bb+CN2e2T06M`2Rh^J_9&WN&-#(cLm!GjG5^O zisYh*uJr*H#mEwTc^BJV$YQV%WqYS>{)huJQ9Vkwc<~2Kyx(>+Vg6#umZF4;{BGv) zyWk1%d%+7=iH(cfrBcu3^+>Deeuq?52jKHYCOTMm$1NusCc?cahTo`yu292B%dJ!x z(tb>wSVgA4oM_03dv|GIx%yfBrl*MKP#gn(tdiUJ&17rq4& zb3<&1W8VYKa$4j4hQ(22WrYlS8*D-Ih3)Opw&0QF?srDmu>~$>GA){!M`q=E7XTDs zF(oA_G^!D9V!<2}3y71s+Q>|QO!+BdpI#+r3G+Lw)_;&Jq$17tN;MBPVA@ zL*;oh4zI_V8;#zqzoj#jw={;dkHOo2@0q>cEok8Js~O>`g|*Z}UE*Xf|>@dZJx& z*cv>vSw8Jv9WO}`80iz29#u4}w6ZO=T2f$POoq`ems(fE{x@&rmD#95N7g@+a(Vij zb}OC}7XnpMn@)l@s()c}JWqZIXse|B2-B@d8Suv&DuF&Ppd+Ih0b9Gv3G$rFZs#w# zL!HZuIe7bIFn6NC_*rd>$2%AC=g(Y0mvBv+rNl`kRS*Qh@T@-(WnE}-RYNlUGB|pQ zUO%_XF|DA}7h*V8gDMMU*$2jHBeg7479$n4+^p(HC?!dX>w@e3KsaHC91Wv#_HDQurCRXrM#dB0?s5Fn`Un-kk{zdTRfy?EZ{ zJ)+@aEqBD<=sBc^KbEim1V`yOR%jfbpr-}EP?bUI$c2HbV@L~A7f83i~di?+Ir zu~)s0XKj5bZsaI~`gT=wN^Dczy6#Z}>bQ35~Dm)LS2+XUH0i*?vNFaFpa$P<14GOeJ3G)|cOR?aU~i{BLo%2*8A%(dZZXt@P@?v!pF)^dbb9D6lE(1&-XTUvB>b}Z zVtJgN5U$hh4!v#nG10fHt;xy(X&%2liVm!<8~~m&w7IUE)Gh5ajg-&pn%+eXzKuJ6 zxEmz*XsiQgxBv5g=y@eaQyMY&STq1gZXx^SH__<1yk3dT^v9Z1X=qul$pg}l>>Q3c z)cH@mM=cCguw%xBS1{O22KyDle(^`o^iM5X%Fg9JiJ^84E{9@k?GDau0l}#m-j z?XbLg8buL8q8KUVslWAoj3Q04ZMQlBu;6tF%J7VlxhO>v4hhD08d@02yl+>fPjlVs z3Q%bCPNQjlb6FtRp;`1}9DKarDJ>`Pb09_2r0~&+w!5e05Q{boJHU$8Ro+=dy+}!l zGo5idE-lb$#W`-B5^I4_iY9xe&p15xuZXG&_uDsXSU~_uCgg`i`Om)?iozD*)XR0# zvVxQmhY-KCtwmeUvw>qpyiQ62=haZFzgqM^}#>$tuqV_QTQJ@Mbz$J~e{WOEk4516Fr1SWa zlAV$<5m8AR3ya)!rn3;;f8UN1aWphE$(`C(g-Ks&jD1a^qIOaW^rmG8P}Ussd1)%>3wJ? z!D;BX8T7YK;^bz|ZYOVqLRtE6a-_y_KWRx4on|X$Is=+o3i0w%b_3 zp3R@qXTGbXdfJ#2f3PURv6UY(kmX}?G$n}4OK$lhW91Rj1oo)d$ln*yjT z#$mqUx&(zf=@XPJt(7yn9={U=8GvL!KMefz;|CbxUP391G{}l{lY&h+4F1(~{Bv2c zy??Z*h^8iIGpVBKC7o%Qg<_dWA4q$SUHtj;zDb{wluU`3U+KL0>r`IP#3;8?gUut-+S(e8 zf})DfvIuQzXg%suq?tYpgfvbl8<_^5tt?4z6I@8(#R`k;JVX&JIp8@NY{|{c#zc+c z$6PkdQyLIIgwu5^$O^`16kvWh%y%|2^sZ zWrUB{Zm%j^mK+;q8dMlTz{BZwVQq_aoWg+wU7nFGU~|8o8F)IC@|G%xE$@=ZDqZz$pk*XDjbeWm?MGT0Z%FF8D(t8}K>JZF}T!=5VD{fs5Le zs2OscTG8R1R|zQ8d~LRks4AR&A6f$98d6>F6J}S12U8L@hi5eM@%05`L2-!+RB$1m zNFm|kh*7>!&@} zQ;qUu2fxQ*92kvd?(5qk6R2m}v#KhRv|WRqI|eZA4+kBQgI3SOfI;V{!ylHz`)ptA!RBThdir z#pNSKx&nmdpaiH0xqQKi2t3r=VI~kldM%v!SB`WYLZIYvJ^q8Y^!$@a>$kZwi z@-CA&^OA~8JHx&dk;NTz?b-B3v(TvC3YL!%nUw5y8n_yb_blE($lO5!+JM1fpQQ*F1K)zZci^&-lJSBAhr}5?yY{*=R z;JzS#KCr=lz{iaRE-voxyRp^{& z|$>YZ0XY?UAr^bpT729M2Okm52#osX#B*8(yDM|83b zRh?ao23wGowYfKjY^ugeb3S;bSrJE8Pghxta)b0EGh7r!g0E=K9rp9O8({7Y3!-iM z{1p}@T#_xT@WM-`@*ZZO+3j;^B?5*~q9Y-pB(d^Ku#B-x)Fsb~Ot4ClT$y&GH+q}c z_rI=9QNL`KXIFT>sBE-4L9es1Fy;hnnZM5+riO(jq8W%9u287adh>ORA|k2w7z(lH z;Elw`JH1FzS60CTq>(8NaIc{j_1Gi87{Kaz{qtqzaUOdWFxYfDdfmjiWQxsrb;VS* zfBRaaFFyNt%I_7~^EN;2cyx=&sd+oNq0^X&g9|ua^Jm4PxS2d=Hs=$FVVY`mMW9xH!TmEyqQ zBo#Lvb4}+74Bt+!TM7ptX;JceJ#oH2r4S#-?OQw@dE^7{-N_>jru^$=OMXQaIDafw zY8g*%lXW_RMnhqOZ3ZgVS*4hRb&y*4p2*$yn=}rLA@%dJg~8s;bM-cXw>|%Y0XqBPYtG# zSiw@AIHL;3h>eTi_aQo6=|}=Qm=2d~3e*|VUakHL+U=a4y|dHn*cvUCL@;U4ETry) z_oaLqQ$_+ZF93*5TN-21l<7&gYf$%k%YSJ*l$1a0EK9-laPv*D1BvycwE6z0ZUpP5 zu8x8D;^?tvF|MxL2Vx$?A>!n|XD%NKZ#Ap2SOR0BGINU=pw)>oMLp&9;6O9q_llgsx@xzr%r1A?Svu+} z;znOrz6>-U+fq!`Y`3?9mBFlER@EGz24H9|FK~-#jCb1+J-^HRuD9B32vb)b!H+OF zt_P57kjPg>Knly)_uiKLfUxE*(fBT>?A7ycSzU%iQf`7tRz|v9Z19y;Rc5x%!5fDz zbXksJHaQxarjF>ibC{f|2)wGmx&%Yo%{X*03q?VWsWpMru(VT3+K3F=laTw^pqPVW zkIOxpT^FQ4r$4P6EnqU2rPL#%WZjodqJ#n;Cb}~Gb9iJ`rBMgq75+Fz5T~IChXVU= zUke$u&>$0-}cF$)qo$CWh0?15cbY2J>P>S9e(Ii;L{H} zrGiZpr7?ye^3J3rCoHAbRA5H46zpWV9tfz zN|!04cIxBO*$JAWPhycIF%%S#zi~{86M{^95#s}Ih5}jpG6|5-WJpLwaIGjNEuGKu z^Ydre^ISH(uF|?+hFjW)+T5y@o|gnQQ)|2FG$&)*AOCD^`usHT+&(t5^i+$FO@QB2 zk?2jvaBUhl7FtZZy!5ke2xw%bkl znO3a)JtJSXp0R2?X_4Rl$u>Kz_Uc}B#svgib1Qs5t!Svf{n#J7=y~@l`}`!xBTJ3a zZKRrthGC8;uKv$fnQnpT){G7%5F4!rm$HDB zgYpn3CqJYT*ZerSNn$)z)k4RaoH8_17!}N#0om!V)xjL5l1yrLIe?(3Gfp&kr~vs3 z9H-uF~jz{np>#kG8yhi#JzUDr3f$`^Sg5`m38UE}lovsT;5!Xm&@y z;}#`dz$<5G(n!_=TLj@)RrSNh%E-zo$rA_zfShjhKj$(f6ScBqtWe4&Lyc4Wt~Gs~ zMt@;r2iPGmjZAa}H-9otl(B0_D)RC1JIu16e<7}p8+fA9P(?&f3mvF@n z5B0n%BV*(2a$G9>Gl{XzWHipGIEvpGAVd({>(PaS`^#{K@e z-KeG)B07u0WfbJm_3p+HkBrXDIJDM~j-VwagG(tvZ^N?qErwl7>S^TCCu(RPlqb-y zMyIG32>jjeeK{zA+!aqDHW1oE>iXw-mcBC9asD4A%l(JuqA!1A+jD^)*(2Da` z%zO%p({&!lUysa>Q=gfyqwuJdKDB8i+vzSlUoIg|Ff*t*>V;PvdCuD{C*>DFDh}7n zKW)_(3^g;}JF1ZAM=a}gWHI6|Co3@lgGFUR!GUUb`<=hsmqRm9ca?9zR=*D>-)T}USFhJFa@+4cSi4xfPa6)jR@FOTeDH3iNf(fNT7nM~em}#Z zXm^vSFwN*V9*(qjK7JkSoX-zT)GdI(`^WCEu-x$$|2v4BZ#JI$)emC^EC*4Pr8>R(*ps=p-d&b0_haW&?J~ zo`}wy?GHCbQ%vQWKEJhwRp$qb&hUN1gBS~$>}r?j_m8}1sq~$26lN; zWSMUM5(|#>&)MK)=I*O}!1@af%ocfJWh9r*>4g8APAO=Wvv!BEu*w(q|LE|#>bN>Y zFnH%f7JP+@%ACX&`tVp-(!3j0_KUBEEOGt$XXo7DoggBf@YqM#J2HI9{h|RcG(`$K z*tJ{6&jsNSE{EU1kFdw{!b=VOTlnK-*)%WERY=;7Y;574L8>#j=Vi=;RS}XMZGa2W z)!?ImbEr1=+yoaWtHpG}q1&0# zC*6#KnZ{+5%qBRSGGqn4hRZsCqE~bwtk29qXs$4ghl({TYOggW^Y6&F8RLA#ZZ#9f zBCXP>5nxsm+`ct8PI3)J6kP4DqPq&q-AkKWX!TE2#9#gP0c|&)bPKH8DNG5yVhch0J`giY28S zqV+$b1JcMzw7UdENsd7p3jP>?+=2T$4qJEYvBBElSH*YL+i`f{Y ztYUE;O-?h+!x}rA(i5Is9-sKrXGv>oYpWlXyV`de7RV5BpDFXxHIQ-`1NJ(C&YiJ_hk$q;NThwOz?XiOiQ0-bvj37VP zT^g~V%-D^r!O8HPn|~RF3fi}_*-j>^oW3#!WvqrFBv6lQy4s;L zUAX=D?*wHE?B^aq=jedv_mIdrI^!E2A`-DN>96zJi?d^MuMl?w11s%8%pBQ!s#0IT zb91}%t6kAS`9fGnM=YQi5jyr?NAe8%$Zw>i`C68+xH~dY_kyp*;*#pPTEC?{uj?Tt z6hh7o{JuQ<2I)~j21(D-7ISjY!7JCx`1xSFGfW+<;IwSG3eF?Qh7VI~ceKa2ykYY` zZ?NaCwnnQ{Pm|p0{OL3z4gn;QI3=3XEKuYLAKw{gve*E(tLuQslRwR}3Zgt+j)|Se zm$Wo90ryvmO~t&c}W-s@g@fkOZ)^tE3=cODo zJI%*W)>v1G!wB&&*BtE~un#JTmnGow>5QA6pJ`GQbLCf{CrCxDpejA&9xwW|+!24g zdYIlp`#+t`14@9RejL2`TxhlmWV|}bu6%m3EFLhv&CV`yFw8t}1|OcZ$-f>f1L+Y+ ze;3nyclnVM>Af-7OzsW3#jMDryadD;@HD$=6^EC4)8v@i1XPkB(q>5)4F?xE*1q9o z<|?zXvdIN}KrcCH4~NM^PB8bc5%Qn%I|cW;=rrEpCCWX_wfPHL#1oci(=_~S%vxkb z?A&e7GbJcc&yc=;8O|KXkl_<@I#tvBJ~k|TE6VgYkIYy%Gd<3V8n&}Im`o-{hGQy1 z=*b`L@K^4+prn}@;;c3$S5XGz^{iXUWKK)+R7WnKP%ynKsA5ET^YNSB^sx)F;3T3$ zJK{i-=iY&rtK#tA0Yw{>L^pw468Z5s50r7Ndf$vlOf!FHG~r)^V7r`pV^*?sS+EMI z@!LZ9hWO^bY3r!FKtX$}Bwx-zGD0eY06%-LM|3cEPxiv~ zb64R5dan%A7Ko@@?NlZs8bYLqM+R3UP6r*+s<)Jf<@!?JJB(t&XF!#n8`-EK;)&Sx z=n?C)KmD67ps=^5z{bwX&M$G(q&EBYOD|jRKw0?ZSBB0;_aGB(QD+s}WD`Jy8FI0h zc03q=Oc^hAdV~62gH=oO!@7zBD0*r6Ea#|Ibq3yZJXllQWSE!=abcvaAd0L8%cNYE zt)s&r$dA1v7dae1PODe&YF2&7VYRjO`oXs4QZNz?2(izSbmQZh#4&Y=V@__K7|V}V zHa2F?u9+l`HxRf;)4sW4M9cJvblwzr>(~2frU;VR^m0~K_P-m*fw;wotG2JU>kV1$ zYkbLM;2#m;@Ll{)XAI&dDI8o2CKPnn5D6ru6O$9M>mNRJO&{&YX)rsFI~rfVmi}_Q zB@HbPPgYZfc&!_m?C54Y3$IqCCg?dQZP~uTq$Mr3!RY#=s1?>$8AePW!V-w^l}Scz z)Jo1oRZPQhg<~WQuIDMQe-l~Q-wVC)l$l(b^M?N@@FSuznHc5!1}X&VKTzyFxu`1cmG~MmXwAofdbjkl?~hNQM=os`fn|HEt&0fx!*cbMo&CkJA|kvcNS-!COR65eLyRard2H zc?vGwc{UDieqm{GI7vD%L6O_2o9_QnGw4M4)uYzT-6|^6PTfF%NOAdUzi3+^0^EnV zzI?k({DM<26RZ1hMV=;mclPFk(mp!8?T4HdJX}PtuGj7uq-ESs;+U~Hvozo>{Pd$$hysl3Z zi7TfTL#7+mb$&+q(MwQt&M-Mi>KlQ)`DR@uXM8}IP`rSnz?ZtjjatvhF`xk*SW9)N z#_svBdc4}@hVEu}sepuNtcwLD#F=KMpsX<0V9wZH6h`$Xg2_*Ie;%rlV%R1EOVMlv zC@SS;UYWbK^TH!mXLroSq=!p+cf!u$ z=H}vN7&*8*KbW&V0*np-PD&Qv=J1(jp1^yxLBrp*HyH}46NkRX8C(2df^H2o-q7B= zh0u8ffnX6eRUIWsGu|)2)IpHHg*9*D8n9Ua2ZY&vyFCD5lG7;;^<)T2{QRsJA3yc= zo0gmNg)8&6{}b(l!x>fDr0O+gy=U(3Glx3*erkrMijMB^Pz>aOfaF$kcf?iOM!*gf z{u=%$FOiyMEES>u?Y&X?oL9ptL%0Ron+rHxYt12*Wj&Ur(W(kUx*WU+_sX<#-5!mrSAusL3K2O8EyN=axdko zJ!hZ`d-R~8^9r%W@f>XTdQlnDwEXqDkGngnstP_{p9rBWt*Ddr+7S~T!k~)rXKL~f zEPK@fQqfsAUhh2)n`Ll$TUpfVtSZyPeS`a*Ig?(SoViuhB)`X8z%7&-_sL2VqHn>& z64xz)3+UnD_8uJ}75_8)D2KH2!*&1Y_w28=ltlA1^AN?bFjVGQ`8h-I5CY4R^NbtD zSlg3@xK6$XfW=(9$6t_{fOiOey0bU#h@B@prfF3E$g856S9C@x*s%F4>}l2H)^U$XMPl|3>yM8x}h z0}@o_otMw^CMG!9N`>F3L%}}-=^#j91r{?eEFBKm16;YcyWw1}Xf)GILPi~kc+m8Uj8J&0lIzCxdcsL_VdVvk~^koAgwIQ%C> zLW7z-lm#bMt5*ar3rU{hgvCW+=ZFT!;9Gj$&^g-&mP2c#4OimWmCjvj&#y`-Dsl$A zoldKK(;xm@yOzLUyE~F(LLj_3t;oGi(_)*2sc)y~yT9EdKD|gwx28q!T7kiUsfUzz zI*`UUFkm9^?`b~wly};eikg4P9<9LpQ6DNun(OL1Uh8V#2U&P1hT5B!RS{Iw?4)K% zR`59Sp#{D2kuXh<*n8FI1dkha)iBYmWBw06n?zqlTXbAS@&`Ut(T0fPl;6Uj9`euw z@3Ph{dL_s6lymk^W>zu6B3w0J*mEd;g)TQ!ktI!N?~NJFn>e}#%surQPgE4+FqxYU z3$OjU*V=Jc5^fcLXv0Gn2)J|<8B#4Ss3H#?S!5I_XPvM2&dp$0;(EYeq2U0ZsgR(?)Pa34w?7hUjZUl)-|}kxqD-m8x8R<74c^GVSBK56K%KV0pf?2_AVwP!W_ zqiS$rKWX>YlD3odh+d%r*Z!btHZz3Ne6=aEQkmz-HBK5^^QMxL*6uJz6ttLXu$i`> z%0DfVg?+f(9#||w1?sG>?mZR?27gi8gBD^2oD&FL8P{cO zuIuShq?869hmAWgC*`67Nrm8|&+8g6ep=QC2+&0Q{zwBXk+4yyakK6A==tZ4HIHcB zSJkQZxPezGcX|>ih3Gq^B9;=M5Naf%eXZ$EnF$UQvYq{pe|}3I&9e(DBLmC?CjPXe zYg1hQJ|{fL0`CH4H#E}^dQ^CfLmqw*)9Tt1{Xz05G`K1xnp`2}?*orf(zd`fUu^r? zzrCa5hl9P5lW}a2%kjxpU4BsYKr4cL&3acvcZoC$N>i=AbmHi(195kPDP0)8$gGps zK|M8((<_EU`##sh)wVRBmPpFy%fFhSX(nI^BD{fw7IFzT?XwYiS0|p>DW5+I3m@;m zuKICiwmt={Z*XBGC>qKi)fN95Hz&Ky!W31Gj^;1hlbYiPu&;2OVOg0w?6v1bP=vln z@trDaf?=1E?sE{K7%5qJ;SNTUn(-PHW)=u7r{}W5ljl~^PemY1TqGO_PUG8w08~rzYM^B$x04=3mAa!c7D(J--d&MkK@ zx0LMPY=x`~9}!ggX0M24{AymX>C?Bv=Ra6z)zO(Pa3alu6O%#DJ^No~1`IJAc&kO^ zipxbMtuS<#adMQafgiQ0+tB#&xzrnch!{krBAIICc<^NP-S@Okzc&o-(8$MLgAjUyi8AzcPBuMp8pi@4OPcDle)Ji#mn=6Y#|9bh_ascRc@J ze$v@*m@#>D0>5|3C0lJ}Srf<`&)BvbCnf`;otT1moMt=LU#Yu;^U|wrHq@hG0v=uG zex2SQNDm)T?N!kMuO|i0x5`3&BO^4k+6to`0?0<02iO)X3mRiu zLT_+2+M#+(@@{5`AFpp;yiQKVIk>qS6UUOVA>?5xv7KY0-7YKYE@5>&u8uBdOD6^`3~f%4DA+mW(izDKrlD&!1A#MhZjbKWDzJ9gJ5 z2);ZxUa!!4BMHbGIR*XA;ZB+?9Yr#rs*+{+96GNN72cNXMoQ`5CwfBFUl+B;m48lC zmBzvn`^o4Vuy$>-&UL=zHov@_000(T1&GZ2g=D<|l$YIP=hGbPlI?~FcqdW8%rPuH zQAq!MS$#g!cxR8Y`EpCtMvI#rAqHSb?`ly542zb&mzEUCC-izanu+w!CH0HVL-o6) zxqsJ`q5olmYF>4Kn)%Ftace170N z4B`Z-AI7tf09eOx{x{-(?(D_Q%~Wn~;5-`xxJTc(?e}iWJ~QZ>oNsmI@_L85G7TGa zzqyCQe0d%V@XZ*zb^h)$V6Q{VzBll=#WY{p>%+*~>P0+4kaKjqzN@tRZ#C1Vb<5<4%j2HFp9{Hq|JLYSc7( zP8({nDKpccxVZtMt0Sed5?628WU?GFb!oXV^HD=65JirwgfZg-f*KY@Dj0fszoOzx zls1)E!p%-rb!K>wUB=B|nQSyznGCNlUenppGv3k;J&$lxJ6x&kCo2zER6dO)jx{^c z)8}#{lsIXccA}xq5PDx%`GI@L?!QSsUOQz%{+_RBsGFs8q42sT6QOZ=lQ^3{Dej<) zZ+Ixv%rw$8Ny*{J%BO7E;_RdyJ3nnl{@7K~CQfxrL#wt4HAWq8hI56S2Fg|GUCG0S zjjx5zLafu`)?#*WVKC*GTUu!sD{vH|6iUq}#+F1@>g1aDQHxx_FW>KG$wKH}TUq{i zL2OwcE5hO;ApF*8yLfi0gJ+2ZSmpZ-@w}~@>ItaI$iDZHK*3c zuOn#o6fm&&B!xxg(YgCcqi}q9HY_yxAUZhQcFNI+ZnE(h-;$_EeHeBZL#FyIj)_7u?a)$;#rKBH&F-fHQe0vkgA|bFW1`4C zWSdTMluJG*bteM9(u(cQ9h)Ci=XC55;1W#gUUfYr2unCm%3vJ$|xM&7W>`m?RPl7>l=^mtiGc0 z*Nfu>!xKJ-)_qO_!S!)rzx{|-$q0FDrh4;9Ybq>tkn*(CA75cAp>-|?U_o5K?F1(t zf2P@;(d;rG;D*7pm$UM-E9%(L68l_rVQfN-K7)eHZ)SqFo$Y<&ySOi??R5%IF*Na& zW@!!a`I^D(T#i}Km9!Akq-WULnFT}iSg83iR&t>!!}__uC6aY=weSL{6AnwG;E<^~ z6EeOVyGy9)>r9p9H`bin9~*y2;&Ig!QP8mX6-DIf$K5~V0(cNN?WdFG$-P$yEgzo~ z?ZqI}sQrUR%k1B;CoC@e;;HGW^DeJY_|10Z$0sCy7E1L$tHX8?j_Z8mhDPBw^wQ5- zqljBmWfCS9aJ=17)v-_PKhp~<%aVpOvokO;)Ol@wJ4!*wwEtX^S;W#JvcTb}`dOwp z)5zT!g1JjVbE22a(A_sXIhu}6&UUKPGw>%qH!Hhulty1!r3!D#ioJ1X-eG zcy^QgX^K)sR$i`JGD1=1Z;H!E!_~-za`i>D#l*+*O&<#`8H8g2m zZO!zLr#X4*439naG`Iy~md@ra+bDP8!ij^Fc#E>=c;fJp6TIWTcksbmw_}?YKRMFJ z@IsdN-Lwfb!H*91vb(XG*Kh0Q(1jXK42-hByNPw}Eqw3D1+qnnp$kl1SJGHVQP>Pk zr{MZHQV=n8K*I?FEDcIy5quQ&PSY)_q9O4u2+$0Rq8Bie%2HF7;JKq`>Hqc5sJi8D zHm_fU=DDg#GYnpO=@>J!^Q_&uoAQYAkIm;@9y!{lHuF-YyEj#r@Rn-Mm3LpRS~80N@Cit}fBxp@8p+ira=G22obmhhhI_!6OkT~bM+LLfAO z6F^L;ROCV+SMDhife{YMd=mff z9scfJcX90U4!-ojFS#;5!_Ll4qNB5e7Y?7oMW?f?i{X(GxpDnEv3ut(j-BY`O>ekM z^z@#Q?VVj*zwcURizm=yC2HFdtKiSy_lNxK=MNJzTDWP~Cf2X%;-%gJ3RVS=96n1S zm&b^fU{;w-3zv+iHhV}l`17T}DauzGfdAxqr2+UoIEH0`u2yjf4PQdu3n+$2vlX7a zCRAvQ{2ihW%Sbv_Bs1qu9LE~!rS|rF@C_4F*C==ahE#2X7LK(2aDol2JgyPae}qtT zH9wTyEN>;$Q8Xb%DiIWXNo_2`(2LJt1|E(3ZzZ{qQ8XYa@dAh$V&!ohKTr*Ura1Z{ ze7q7%XR%OZBoiQUF$<2`c<6$Hr*!&A#lsd-QF&ZHzz&OI-*eHWys9xBRfS6<)e z4*XKCU%yrS^rsJS_uX&iD_{KS>N0Il$E9EN{H)Eo3rDy1TcjFETv0%+K=QzVtoj z(s`z*=eTmFm%!9%>Fy$5C~&E-pGYJ^d1E8Oa|wzCEGNfeD$UNFJD3<7V}59WAAI+V zwAI$}58wYOC;G22FfzsM`>&_FV>Q3{?E#J)I6!@SCl#%$a15KZtJiS$;#D-u=G28D zPWO+9=H^Zs>#EtgXE)EjbcV^{VTL@Pqvr=Gq?5e;wtc+iwK1j^l6>LY_Y;Z4sH$&Z zF`Z)9uI=o(;d(y*t)E~=qb!bGrmnJvKYQ07qG>vx{K~gUx+>u{kUBj*=b^KKx|(X< z|D%VQ8XM;6pMHzpi&yyAKYocwG(jX$hMp)vgqrrH>2db0sppe_{vj&L%gN<(l$BTT z@NW>*6TO(weyGh^Vjd? ziKm{UukRA&B{AZf$w%J&R{rT7#uBf?`^yJ;@3{|hu7c1<4;b}xw@71 z<_7-9{XgXccf5lqA_W@TTbMq7n$~E7dv4vyH-~%plRNfv@X#T7Kh4>`iyS?6oG<>>hxwb&exA4N zU(3kE6h}{kEc0!>@>oT5w`>%eaBt&^qgX0eu16W?BR=F{}x~Q zi@)GMzVkiacE?_%^rS8jt2)~F;ZJ|T``+~?{{5TZproV>$0^WU*2sPLy@P-G>Noh> zr~exVj~s%!)m*=SAD{fkf1#$jiUqTjjoY_#;_O-4R&}yx&u)sDG`=s9LdVcFH2{$T zMbF1aS4Lz_1%WOH4XKn>O&Nv}D#R{O0!k0iWuS;lx_VD5B(Xq9pLk3VX>5Q%ZT2*j zti%ixk%jM33?wwx5{pME=2E=z=6x$UCR;k2*}G>ag+h`3t3z~lc5wavYw2FKit6%G zTI$Q0>Knv%ZIznD)h>8Rg)54jHM7r$3?g*U@DzSF*-Cv*ZTEbIoC_an$-mL z4dkXKnCL%G>)N%9j!qzam(}anFg?G>`sNB^mJW_U=oTa6(;Po_nj?o#(zRw2Qa9PU zeLM3@OB9Ml_FlVF5)_4DStLvox1gFz+ct^VB^*C>nt==bxK4rL!HYCCHnU;F7NXIZ z2m+r>Iz=pM($$e7UhXh7Jw?p$v9y2x&&A==8LtnFx}_v#pvbF(DOHFVZj(|2W<`)=Du|KKQw^g$T7QhCh; zicV!{f{f#>_`FO*$z^;gune7&ScHNfu#n1yn-`&S9s*w>rVWFf8Spgq; z^X=TYdmC$78+iQKIevR#6vv99*>TDmTWN?^k?~b}x*HCQBr5m}Kfn(>Of$mZ$Rrbk zSE+7lrmn7Dk^DjuNYV8vI7L7e|C&(mBO$;xG!n4{zLeyPMYQl<>}x`0&S)C8Wl(Ml z76%46GdaR1e^A5HQj(EAm6(42V@o`B;0QAdX}qd7zWc&O^68Z5nsAAlCYNS&eBf`s zL^_=jx?wUnK80CYO^`33AsL%qU}SQJ7*LANu$w`S{(p5|77N zNM>kltm9YD9^xAh{F=Ct2%B*o&-0io%)Qb8{3p*V4Z!cg@f?SulnBEB$5TaeAj$g@ z`*%>9%ewt#6YMexN6BE+$9TR^!A@W|ttRVBz{eI!UJ^)E$VvneLwi}$11n?;BMcN< zMu0BUf{-sy?Lqz741>EYU9AcS=Cjydo)X8$&=pJE6s-6fys%)8np)^l48NYR&{oB~ zPUq$=Dk(Pb@s@eyQsF~&UHnd@x?Gkrs;|c~nVehX@bMF@->`{%p~%eC7``yX_|z10 zvvcJ0#gL<}tD-tk$Wn<={Qe+N?EfH8$&FI36bFHnScZx3dw9OD(s{#ejSN)5UUXb_ zQ4$&$%Rw+csZ$w;sR}jKS*L3C<7CCx;gz>R)>N+~9ZfM}-;S)5qw~?r-q9JON z&lM=TE^VD{6f#*-zR#Z4X4bD;jb>_u*$aH#*DU z&?t$@YRt-d5^Y^1N)j}e$N1XM9^guZTe94P19Awj`_1tjd4Se|r53zN_ zTGB&<93A>1O{=SP}^wKcSrmM}IlMrlnwgY$Vl`nj)?5*D(omXH1Oe~`)LsiwKj6ll+ZgOU!EJl)VcoiQeEthxWbdx+ zRL2bNzU>AsUme8obKG+M^*r#CA9Lp|H!?RqLVaBgTeqy^_={CsyX#s`pE}N4@3;-K zu*mfE4EwL$%lE(YE%xu&%!S^Q;xFENAGNhLeB--6;Gh2P?|JWs|D4Z${Ez89eUjb_ zz1;c!_w&p%zvT;`{T!e9!WS62a+O=J-^&ZnJuA0v*eup|G;#9{`#632tgKAL#QWa! zNBr$)KEs;M7V6>#pM3v2!LT`X<_w$GZ(?S0kT>3WC*u>7yzS1{uxV8rO_fpZx$8|l z`S?R(Rrfl|O5*I>x`vIb*V58Z$HzbR2~M3j%=FA0-K~wRX{~45`t=-q_A&Nedo2-) zyk_@mKKzkS@>ie#0#BUpW5+eS={a?pptP(&rBs?DbI45^?<Xi|Z8Ezs&*0_DbgWy?;H676cXp!JH<212VWR&6O>5UO zIW~q@EU;z$ZOo4kF*=(fn@aJQfB!EOa(RkwK*8~N^1yN0+M1Y4ruonZ-pB2?-OA7Z z#}ByL)x?W09>R{5vSZsiOeBHtaAjbC%7%71pUjB1mPSg;>-fZf{}k6;yNB-XE?g%| zHnk*TQG?Fzjci`Ok)nSIxn&zAx+A;WT10JK1DT~IW@cwaJW;~>HC^o3u^F5^Ww9zs z$|~^YM)~nWk8`}EiGTd?yU4mey+h+HBvTY~Y3j-n%EavlI0586A6?TBx*%%kR3|L* zu8$k&WD4r{!sWOe~5p)6ui6150+ccO)IRLe9OUd(c^e~>@A{W=C`7kO@AlDT9C$Mwj& zf{KXEvA&C3ym*n;xBmebCl@(AJVhi?hG`|SOq+_BMLwHiG3`MRP?Wm5{~)mq6HU{| zrFG`VhH+=d2og4ab!{kZgRB!^yE!%_1TotrYT6WhHB8ckMm!$ld3&Oq@)Q``rxSo)Dkw4Se%8t&(QQDvGP)eC+9IVjfuHMKKJ8C z39Jb7sVo(`kIbcsSO$axwm>RhW7LfJ|C>s*|FY+m2H^ML#N%i)cmqQPX-Y zTpJ2r#(6H!z+Vpb(p2t1xK^}vpRVg(MJ|9`zOYi%3n4Ig84wgP)aMzRhHhvpt4KYR zDA}ln#tJ##%MtHFS6+l=M507($W2}0)?ClW&`qL=I44i_^0Qw)!SgS^gy(vcl$H{> z4)e2f{QD0dAr`S{Yim;9PsrK!!|zSEZ4k=nYUm!irmb{bGHeDc(?Z%dp65|0s$xDC zi{N>_n!K3Gyc@AC)wFpMLst_Q%QTQ7S;MkzwcRMHo0j9aL?YITr^2)pHNy8iMG3NP zCF@9L=~%rTw~!~ADCJj=zep@&8`jg<)j>sB z8E20kqq@3^>c$3&#UdkD2ALQcVfFfTY}>qn=UzI(;|HE+?bdCytl!93+F`K&B4~mg zd-pPJne+}#akYPdjn~%DzGWMlq0@i-1VgbXl}$~QH8xR5rkGpG(7k0dbJH`taH@~- ztAliGwrJ?=AR3Et_S9Jd*HaU%z(EVZAU0%7KlU)=H?ezN-kj<2E${cIIhe2z8+@g zW|*5>U~Fodbz{31IGc%)H?CT*O zFQuiqj`{Jcn3{u^nkKt6OT^YmCl?qQ8syCJqbx1WlUbZ0ovvkKe2nDcq9_&@NiIw? zH8n#jwIt>j7Vx|RGm|4+892xD2M^M=W(zejgTbL835eO5X@&-`lF6hQxO|zh9ngAYv-1Uo;lObsUZ# zJxXV56PL%vDTzf`y{etReBU4PizlDs^6)tCf7dO*in38@`?A|$NXZFUp{{V zVMQoNbsh7hi|z+%0xbl-(85G_(50v3BM2gzx-S&`B2D%6%ttd^y?lkP)vFmA9HPFV zj*`Y^(i0Ob3=L9NQ^%#ga~wK+j63#jVe9%exc>je-g^egb>3&bzxSlhVRA&684LzF z6Cg-1h(RPpQY1yvmPm@EB#P21uHwq_TC%;CWiPLHZEIy+S&~Idv;viw#0-ESa*l&A z7|aYN=g_%Ndhdt#4CuO5x9;6r-YS(>?*~?qY;?~wy3hHC=lMMz6^R&U&z>in%dvRz zVrnZ>7+#T*ud{XYW-MLc3r*a5+uiIte2QPcw1ZRUFHxC{6OM#sZEdZ1_^t=Ujw9Vn zXKglax{;36FL3nqMc&?j9K+DrcHPy|HNs5gJYn|^Fq13ugCG8kkhDc@btU0&h&_7` zi)_9?spw&t8WR&!)YnwuAvo9D&+v4X`o?)Y6QX$&m*&+ogICGq(sN0NW2B^okPfMI zTH3ZPGPcdOYgRHgaG5{-+keFMe80vM#sB~y07*naRK`c9Shci;+S(+B87CdFNJOKo zS=z>t&hu<)Yh-Op1G%z`?Kv0-OnlH((y<1FtPq-^5ekKHT$LpgHVrh^3m2jr0<(T0@l*xHLJ^@WLw&j6kZfuo;|g3fY8U7j z8j2z$eKbuH(NVIb$ss`SzB}K|;^qc2Gn2@MW^TUzT54)5xqfv!!xPiYg#@*g6&yWv z23G|2#r!~2XgK^H0`xz7e%}E64xCWPl!_+eA%gT+i3;wrJs(pKCjO{G-IHJk6R`Pk zFH_g>0A15mL8>W9kc-5TDlHdOL2i42K3x;)@hCZsrYZJx$@Ky>p4tMKnlk*(>-lv} zQ4ZAe0a68cS-M6_R~Kaj7$}pk9_R_R0BI+D6iyIj4%Q6Sm}E*S1xc&42f8riGe|q$pi!4m#C_#W2C2t#>NIl#wT%0Ws;F7hOVd;p6B8E zK4Zh9G}hH)S|Ki;J57CE9Y>CxV)fdUtX#g7<42Bg$IUl#;J^Ww(t-bl)R{dheW|X?AP}!^!iRKX?z1J@8&~g*-y~q$;Vi@=f)eZrDOS8>Z&XF_=n$*p$S%Wv`}4DNwK+(a5#!#SloN> zJ+!y4;?tk}7~yyY&5bqOch5ZnB&$}hqOqxo-o9S8U3V?@HMOi+vzF$@7S?XwO53vK zRHlMQ(H%UO_HtG--z^WR;*sd z<_tV|+x0Y6S1~@Dp|&!G7c_R7rcqmw=FficEZg7SOC%n}M^l3a&%N@U5kkA7ftCpH z9DGefNCBFL2n>Y6o3x|ls zVv0P$-o}OKU5h@ie1jBj9>`<8S^eeS@QnjEv)WKBl4b>*rq= z@nnVEw0@d9@4ACj%#sV68-!OXktvoKm>8#F$ugQXjjn-lH0hA8t0R%BU~o3i-mXEy z(HPB3TDfh@T9%Ga^X*snGg0)(i7?0eFVmNE+1)jSWf;ub3JUFb9*(AC+b#<_mXRzv zgoRHDiKgr7uiN)1J1#}r<{_g}w( z!{>YGpPXg;i@)aJzP&V6C%|*L`>xw$-$+?RERC9~gczM3lgBTOit(aN*SQPyPR`L# zTSH~U;BPkO}S)anFfy31BvTAau-}-Ank&}W0!4aMusRm zF7Z?v-Lh2n0fMWSwQ^#zM8tN<*#g_nV;LI1eESGLe*O&}xOE#%35~+s6oq_VP82+` zxGKtBcizPpfBZTHM|}&zx<+->WW1}B{BS=jH*6pjjdFJXJ|d|KYTH^Udf*x{GA>-~ z8zxt@RXTBYn(V24#9CKU)wUAT3KI$$NDa~<6JKiNN;Y{HY{$iw5q`D*6t}Ef%8Jcb zgBeEnl3YH6$QHT(T~|>mm8q(zpz~56qr=1W4o_T>BS@hAU>M3MjHaghp1k74RqOG2jF2Qib*jyRmsgm+JKu8~4Rs43 z(8KTB_cGUPy^-&J=kIywk;nMX_x_ph{?kub*3m{jUr`3S~wHhiGeCOxbbB&Sn`IousCwlJ<_J z4E7I_pPpf|TxR2STNxjl!kE+P@9AS3%`8sO;)VCfmgTh7Wds-O*S{j@X#QR z>#}|4ZrQPPr8s!xC}U%jTzB$6hvHwUt9hPm5b`smIU_a)lC8Q`2-^>>-oQajxqUg@R4jrCug;HqmH= z<0m^wRn{>(Gs*djy{x!Az}#$>%-j?wj-MbDO*1k!#@_vhSiO23hmN0R!@BjH?aIoN zXFA35jt;*6^w0U+XFtXM0|$vGE2*ukqpzo%Y<`Bb=P$~}#)V>Fc$Bx_-ox6BH}Lw- zLtJ;`?d&^znviLbs$I;f3zx|i<`|lop?`3gkIlztDwu4j2;aSO-4vRVEBZo5*EDn$ zPI3ifrUhHo`5Y9LOCptLNeG1RBR!X~sTnfU({%Op;Y*KnGDTfOBcqd9D(jl~``>J5 zW@-vuXk5HJ%;$de5{4OK$<`bB)u{n0qZZfRcq8R1VkA$4A*iBg$P;z&d0%8tNuDCToy@&#_c`Fg^-M#=Gc&n-7Ak`aPX$ilQNT-Ozo zlasVATFk-)o@idUm}odep;YEOPydAB;ZYv@z=K@9aSg>{5!-{F(P_T(-0Nu74G{Bi z%Yu)5_XWa{5IMs9@=QO^9_uC^kKtKSzIWgPmKnmZLKwOl2-%*`NVZI>x`s3Y-*=U^ zJ@CAlhT`)lLME%*7W4DB4)NVx$4Q1leDZn%61 zY*D=wzAf&&?H1A1+ebb#Cl@x>iJ9ps(Xy~vnpRj;)Ya3tW&`<|83rz%=Z7!6!TwX{ zInjNY=E@{<13ipfJWq91ist49%B7ORPzOn%(w7L|Ll_Dnicp&TTrLklEE=U$w((pC z+i|H`vXZg9&&^sk{y~nxZ=If*zPEnEcWucH~Vr)#1 zpT%%=Lh&R?OK0ZNS+b*pv~Ro$%MhI1zn@rjH4TmRIb8Ild zil@+N3eGEfqe5fBEjZ{rN#gZDrMU$26xHQJ@zDdR=XUI-ZL8%OLb2QYa z`Nk(7Vo_Zsp2#qr$y2hOD{?uB8jR`^9M}0bsmK0zI=^oKeg}^0*a+RgbCq*{zHoMY zN!jy>7>avs1ckM(9J)clEiiSZWu7PV$RMOk6Yt1}Tt7%x^dt@vS4wmg+RoH9%ASuS zWq|qv8G`d6=|34y7p=XX366r>CAf^7u^6}OaFnvyH&B1kCyzXb#sf`G800+DP_ zVg;K3*Hf5Gp$W8ioX6^77`%=m?aYUV38d!{jzsAnpXBt}^OPK$%a;e3o10^1W{SDO zPEK}q(SGa{LnC9v;xS5P8$;JAmdk`pQ~3fgFil_4dW5S8Awo4NuI=Fa64NpenxIrJ z2NEDnF^x5Wt{GRtyyndtzVG3>sz9-&N_q{2EbOu!Oe(?i+#p;=h>9%*^oetG}hQvy-=W?PX*R8tbcQY-pgmvKrrasYu6p_LaTtJ8**5E!S}R@KKhu zwjec)P}D+;gb|)gV{I&^{u-**q6`Px%7FI!2nsv4PiwFOF4bwG($bTELyyf?QgwJRec@p zt&2H+_&6IjZ(!x>RqWb(fa`C#mVF10F)=c#7}36u^gJ~QM&M}zQ#Y_nMY2<4Y+l*U zWB1<1iuT1!&d!ofB^el-<_rJjztcC7<&#e|@}p;8VD(j-D8(u{b?P{2GbkEE5#nK! zkY{o9#3`Qoo4=x~yN`c*`e_avI!QEQ(c9n8v(LRjO?^E(b{(K-`|Q}YgTqHop<5wd zeDO7*>n0b@pGN?*bJM)|`d*f_eUG31>{qN`cLdvUIC8QZGZN(|Km83zkJIP6@uk7Z zlgD}S#aC&rtKhlcyg*NHFRhE4IehRK$BrE1g_m~`j#qH<^f@w_9D5EO<)z}sx44}Y^H1B27)Br_F4F^T_ zk)CSw)mBb`=c;60-^Y+XLeq%GqSV&bP+eP%&FolPg&#-@YH%8q8L@10QpdlHib8wP;p~TV!b(CBm+w&S*RxInFAsy$)zI`leX=TB}1@v@vv$(yDo{JY%QxS{PJ2WgUQx}C|ft~x0 zaN~8?kg8w6tNV}ho|~@a+O1df#^G}uIDL^Vn>W$Ecp=A6p5(ThZ>GATiJb=yv+Gnh zu}DbRff?2JeKa6j9;bCdE!S^ai{ncy-5_KdOlESpj*S&FNcz4UA0H82V{`oKwYNbx ziA2KKR*Lw-6hGf_h+l2rMsuOWX{_gmukFV1UFDC{baw1M%&C)MQOpASvl=IByZ4r;fXl-j@Vm2e* z`@Z|xv~DFk_Z`6*>E)&+&1i)=T9Y~>xdASp8)ABLib%+$loiCR1w`~P^T=0UDyF{> z5VB0=SITB_iUp#kf#*8pW@hkwAK&wkLgVb7om{_lGuJ(M3qRj+kkLXGv9g)!stV?& zr`YlOD}49A{yEE+t+{ezoy|;e_G!c#MX)Ltd+F#|n(*$Yshy1<+#^a#}`2tg3~ zrFi?Gd_0DxCiR-83Q#?W7S{D3i8nxRRz@RA0wk2S#&$iXizNz%6v5?3SighM6+gCiJ19~ zm&%xHS!N&sQtzwueT1fdch6T1ktVbN1E-`{^ModWz;V3*-DzAgDr-Vuh1F}AhK}uc z@0b<=(=^Bz3K+VIbI~>JN~FE(s<`=Vq0F6k+y#J@s$<`gv*^-c+qSED;J)|a*g2%< z(sk+>`LSV2b91cRv;o8OxNzzuRwztUYa4D=B_q9kjE|17a`RQJ-?)y^(J}t{r@!Vq zPyH#Y)~=#t#2C7CiDIe5igoMQu=Q#N28QYCJWt0ejm7OtKxkY%bB_AP2AbPikm zV2H8HmkD2$Wc5`W@a!^|I?v;mOKjYFHJV}2bM^w6%p5B=Y@l-8dir|%m>L=9a^GcE ztzOB7P3t&&x|54%&J&MDS=8Lj`BP`9uB_zv@sq4vvzk>ama}{RA+~PWOy{Z7XvGo{ z%fxnkgbdz)B!%&A61vS79(_L#zV9A<0k-3ih{V`^D<4M zyB>IeL^46|(SuaP1Z#oI1^a`ofnua_A^eeE11+*)nzY4czdq8<-ybOaADK|A~ti zF7fyWA7f;Am{;F?i>JQ%7d-mt<9zZHpCXp}1#T(NeRto+pZwW3`T8G!mHz%u@WF>Z zfa{ca{`u$mv#))X$DjCw{L<$>E9##43Grx%d)|8&xtSTh`Cq=l=l|?4rMIX}=&?8> z<5R>9RqRDfoxJ0ctgNKHbulM;hl$oTl88k?`e?eL=q8#fpp@2Ijs9%}D%AjVso`rH z$*_*=snp$qZKFvUY#KGBCX}Jr2Tur0;p0mf862eV#3_VsB6W+>%p@PbV=M1};&WUW znc{n|>}G3QBX@6I$B*}%WVY<_iQBK?*+b_z-Z#w0Z{9%6GWf&4dK%A(a!toV9LHrc zZ__iKV|p%2B9+86baf2~d`~ivZfY9j${y*c#dN+%*3)QRzKWg;=UB985q0%-^mq5L zbZH02j~-?3(bIhSvHQizm$q~4WG4@O?Ms|KcY(_TLv*ya(AzgaMQt6a$~4z*yM~u{ z?4f1c?5eC|y`;V^OG^VN?&C|a5p@}1xQoPmrDVH2%X!Z0m#-$O&k^)-ek3wWcmNC8XQ zI~W=0rT54_8rEM!va*seK6%GeUNB!lTuoiWvE3j^UNv%_gotHgc)pU6YPuS{1Rgp! zxX-u}$_U=*>}AW6M()0517G{eD}3|0x7pP-NcZRzNlRxoS73eHBHlQ57FjNE-@9+* z+_^4>XVkVc5si>;Xrg2p*rtU)Ji~*xY~`lS>-f80yiV`&!~D_X_wv!l9tWWF+)=c` zB(v=cc>T2V`m z>!m$R2q^0&wk=q(VIyb;rhsh8L)bYC;UkCo`1G~y{Q1Wp22DqCy21eXev!%9EI)kl z4PM@ToNU1+oQfz!xlkKD&+{pjithhx?e)L=`F#WMJ8(=5>DpxsQ^)rueo$2E!NlM7 zeZup4=794%zwDAhAv*7Q)8@$$L6JOf($xfn5O_jKgERq#rBfA)5Vf;RUpPZ{Vi+AC zUuZ;Xn`vq3pb$$imB}k}oCq+a@4zU6*HT|ZMJNgi_&~>srXfAGk$Un? zu3~m@d#A7rx)KVxEsIIA^wzi5`EJkBf0~M8( zR8?0}Rh6bPouINZg%!4FXsja|u`n%DR#m1&BoZZEnI@Ttl8k6*u{4@tQe9nzWrb*N zsv{IKNhM>{*41H#BE(~15sieXOvUkiNgUydvSx?w7h=xP#cxx{+ znGCnwd?WRSplGZ5!S$sgs|kTXO`S`g((Bi?v{EeF$~zzgdOpL3^&M2iLoBGPWX;Ou zxOR?YD#bn5UByp!9KtZvR2IKSf%HAfu1DGR ziG@roUEp{!F#k$*{cvEqkZ0e%6Kr0+lvUeq;LO2;ENZT&s;-6$7rI!rVi}v(Ea$)d z@TXMNHL`L2I@T?3=R!{(3+ik6$o+S*sHTDwy#wgc1XbxYCocAr$d;MO7n$&*%$9vp zmDMa(Z- z&rll+bIr0AH0g88)~#H;JjmO7_i@jAZr~5^yB8_oh1cHXd;j<}H{W&xpZMsL3{6eY zf9fzb5gkKUpZnQ-U;qFh07*naRKm%r0e<=G-*E1HH+SE48#mr?BVYUaH>jwBs&oQf zD0DWi8~7Cz`KnYZVLJ|yaEMYFFijlCMfX6rtN_U^iN)gl>=(c0#v8AtI5Qz#*A<3o z;rWtiEJ?msK=8JT!c2BFLpHmQ{WI>wmE}iCn z8?csdA-(n*#&RXZyslO%mcJIP(UlFKAYoJK)&*RV&*;JAMT09I2R~TVTY=7B&f|ry ztPj+4%>Ry3D8GWPDI_QaTL(>w2()P$od>xp=;k0_nQI3MtBuCX^SzaXrem zx*)r*hY(!xa45orL9t{jEwQ1RBVVeV0MGMOn3(G_-!i#D+OH4--B1R$a5zNSwsCBm zaLA%qcGVm0I_%x`HgCT6EF)uMeDKjvfXstPlFdycg@$PuOw4Ba>t~*4B5Tui;UYpe zi6>)pEbrjVnR8?&CP^lfEbM3_S18ecp_`DQ6Gi)D)zwuTdTTeU*RLfOi*e-OVG`*i^-WD& z?(HLNg<_eBu@SD`w4Mu{=P8v+%ubB3xH7_%4?V#BcfW_ZLJrTd ziG;#j8k^;*@BDzH$4*mMU56QoVml5+yUaKK=+peSfA}W~WuLO^GF!HJ*L&|_vi~x< z{!3IwH1@plI)-#;X<5j{i#@coE+&`DGdGtdolY@6Hb!+-8ryL(tq_`~Gc%hZm57lq z*(4KD^7#T9V46CGe4fQE3+W#i2|}iPeBYz0s*N$RQ-IJT<_K@IZxBBo_gES8AJ zV??7-GIJR$Lp8#oa8#v%dN!76F*P$wWmP4a*$m-u2%&3aX6LA>t7U3p62nl}7tiyl zudSkgV3@{+YKmnS-*+2iQ$s{xaBZ$?Nb>j{*K?w0 zkiY-!KGrR$=K9r3cz*A3`lm8%Th+!$rbyrLIFH}DndYiA&mQQcbE<$N^nidC$Q`Bf ze7T;I{OQsU2yG$=ISUq`LTyE+3pS=Es7r+K;sH$!7n6Ta&**mH@8@4J)N-rkQH zvZzU?sEb%wu?S}__F~V?Qe9iic)o;-Mme7&?|9s}aWxOzdL4iK?H^Gpm59cZDm^xs zt}98TtAboW-4}EnG=utN9NjeN9~!|hbfzaJ`Rs%5p{}lmzk24y;JsI13LOxdhV3cl zz5%$dM>3tl2uBzi7-YecHfBbL86BN~a3t7t>v+;b`0DS#2<{#8;a$o=>!AnDi4XzE zA=vnuLSuYpj$1aa;M;%n33^5*_}o+f$b$MB9=-Q=zVfYqrkt7Mum9tRS-hy3C%^W8 z@aSDPao4tu>^pIWLb1f|J^KiiXXJHTHi%nqeiyU3f;_lyp9qJ-c=*x`MMSi!iC?|= zD!L}P>8e%op$Fb4UU~I-UU_XN!=sbjcIyqi``x$kfrp=+Dms&ABLf1vhiq?cqBx9I!r1NW@>VRbSh3fk&shU8Ij8uaXc5_b+K)S zWGY1{8poCfR>&k|=p|5YfkD^{rtVg7q0s)-=D-ik!nhNtgYSDpqiIZCV|+Tp#J-m(%}!E#-Fq0$Nrd#U z<}bQRlcS1$Rq+RyQq>d)<|#iy-Oxa71~h@tRUz+qfn-Q3eXb0qb*fR2IKET?TfqeH z3f04(2bC&0Q`wV5gZFA=bX3e{X4t)NuRM0*gfI+^qbJX^Ywsb15#!96v&3T&r0-*w zNSopIRcyO@6S;heqATUPHEYDLUV4Q$Uwe~B5!OUsfr z4)piax@;+P**s_()pfPZ&CQakZ{WGzM_9b*CBFOzcXMH2l&60DJnOby&&2pRsYHU3 z>oYYxLTzgs7tWk!>H0NvcU@$~(sp+5-A`j%3nRnBR3{TuH8rZ|O(y8=?xv%oojtqv zvuIfdBSS-Evw5UupyT7@a}+$E%8E2q6=_Z#JIShbtJ%2aDoz|d!QiD{bYD{2(8y5# z0F5=(ba!2(ef27eu0!X^)6`Za=^5_kOOM{qgYUhANHogi+zgRW2pf%G?>ohdhdUX~ zOVafVv4w`v4P4L15HOd`V|zY6l0+DHe)EqG23Yg#JLJ09V1SYd5_pQ@TLj_p!i zTZ?Twc%F}88n~`UOUq))woM{k2}oSWC7DX%OG#Bt6~2V1rlVC>;JPl&%?)^tgAs|6 zOlvrvPdH@axgOOuHCW~x`+xdBPn zcNmG``v{?~kx~lKH4I$@atgI2uze2=ffb67&@?U|Kg1QY$nT!`)=oC&t)_tL~&w-Ew^pKFBKT;y~M@KBmD70ck-Jz-)3r{pUUJd zq~b9Q$L8o;JBfsqmf6!xMR5}nG!tJa?4#y8S0?4UR7LW9u$iW*O>xe1nf5(ZP({NG zj|@{+Q$urG8~^;=t8}bd$)&C?GG&iUO*N(INy1fi#H#AZ*$#_bt|BUZGOpzL z-G`}bYNqJ3?JC-8j<)FyO(>pg$%*5FDb z@J{T##C8JTL;%S^2pV&F8XGH_&Sa@cM7Vv+Y9=SAsY!%czpRbkp>bZ`eTc8G?%>v| zR#6p;Fg7{Gs*WW*_sVt_x3y533~|ktjTFlTo`2y*;vtg{G@WHYn@zN>TZ&t8cXxMp z*FbS84#nM_;I74s1S#(B?p8?g;_mJz-#z#I$nWG$GBbOxS^HUmhi0d%AMIXeRg(1< z-++;{fX=2JW+g$|W_u&xEDGQ#_4I@kz1;z=PE#`T!Jnu!_JICt(B(G;E|OFQL=F=? zfi~06Gw$>_{!9}TIB~y@e8|vm#KG*`!50Ev@D`D9Tm!uxh9w8r@X7=9`&Wqg@Izq- zzHW^y+in+h8Jv&^Bim9C#jtCZyt1tzCrm_nr{bK)Y!SPWh*vsX&Cz#te`dv1Tuv^Y zp?^9(k;9l&jPq0r*p<2+3aAOwWW}`63zDbaMfyuLfJO(qkw#>RE%+pzR5hw_LzZm; ziysx3pDV<_19t!lQ6~x}KhpH;E)*yH{N6)Hy-l$%@4c_2u&>a z>vuUC!ur_*UMFuf7r!-_>gucgoCsPeQfJ9vLk=~E9Hk`WknPJ_;o-uEAibQ2srn$8 zDiMYLORWhWq$=djML_N*pXj{qe(a_)C%|hj>0i0t6GH@b8$5x% zdK9s?Q?xi4c^XUzG5m6LfE4GGCD+v6#Ft28p_yiTaINVR;(k4T-A>$DPUo!TC>vh4 zUnVu9cD>8l56j_UJmSL<_=vXSVM4n78{{037!uSv>tz4~;W6IP8RfRm>mj%XkQRA0 zCQBkFd;Mp|*y1Ys8-%Al?|Dw-x=fUI0p1Sltnxw_J(nnR47@-y!BM9c|9lKWh%F;VD-NNIk;{%^l&dyHOSz zDJU;jA3LUS9&eUpB9ShHD1DP^(5i@qS7FZq?IiIhMJKRh#R@fCC|?$4KL?*g%!Nse z|BwL9BPx?Sq8Lho-GRM#-!#7C!IoG+WEIwxS1W}Dchfq$_>*Ln(pr0c?%(8?N0M}Q zCImFqC$L}O@}(%MIRu4(&>q5&L*z&7lbarNvmp&Z)ba1jfb>lz=FHMNZ*aWX%wEtY9Ft=#Voc+NezbQz*ge8IC}+~r6rz-cjC#p zquJB($tZ3N8CRHX3L};?l|fSgw;o@#gWd(+{URz9)L;pV=4=5Y^}L2jV7nTM-yZO1F;bFz}0^f^C=0A_vRYc(n`_rxRtc`YNZK z=LOl38}%Ym*0TR8vMmlb2Tz8@`g2p5B)J<^b4~S0IEz@BZL}DAq|gk6Vq2m%FNrQE z0-SX!&YFDb9=u6C1yS40EvzdurJEmJgKmw_&6cnCkP~9rxP{|PvUace{f;X7k}c`V zEyc!;b8?4TCJwdWO~PkEgx13TKuQ_d04lLV>v`=55@l^oKI4K|^y2{cA9h&e)N|$p zhGKIM&i>#6~HC<1-RuNo*yhdgtp@xxs#D-}-;5pL;={kzz&sA2_^1~O*mKX4Sm zPwxw&C2e)-Jx{~=g}xT|XB(1jYG_p`+*rh_?~eyP*cF0$%YI&>HTIh`n$?r0n)>@1Vz;jpRJ}1#hw9t7KC7JWosq^Q=Sw_`S-n7Q=nf#7_zlkdqLK&9G{fB0;E13 zk|f7OUkik`XcBiJN*+Vp50EF>+843{z*@oAsjJ{ zP)XPEKt$oP(8P3RopI!by(K4gOu!c(5z!0DeeyH0;>6nDr`vTsY$w=Wj=$!FrwqFl zF0jc$)`f~IymZfXDIdKYd(mlZoGnj>Nol@+98H4>X{0c?{F8iw|x=LM1-3er#>g&>N7bG+FuTJnp4*uFNW?6 z6{z7B{y=>x8YlNvn+;NcJ3&a!|a1Y{wOY5e*^%DyXU zAx(`v$0nScE47d|siKNmRcY$v6=`ajzHC4;&`6gW9eaCU_!;CEEM)=Xzn&2}f~hn! zjUit`-+|h#t%mn)vy@LrLVpC%4>1=P{%p?_!*f`pP?7ao8R6XWB%d_uJAPzNi z+JKx!bnLqlY+r zAi(e=_?Fm`ldv7m9TVafo&D`PmEsG4p~mNV=>-%&$o_*s1xo@e zBJex%0TglIi1`qX%av`?ZF2t2RdOMsb*NeXziI3|a`&1Ej{GD2B4BgPrHP!D{$}fKY|G zU}Y11g~gR?>y{^|-owh0Tzrr-3bl6#)D!#-*k^ir&aTCr5d0n2TPIc7G!24I4A|bP z1cD~IF5Td44Oglz+wdvPC_i<+rpf;GI?(_5*B41QE3uURW52<;#DGP;@(;VNOctoo zwIiT=smAx`8aIIFK_IBxYfK=6tX$6Z;1`AeRf5yB<;oXAe+^&&PYgx~otm4EVJrka zaf+QxMJ=WQFR8UkyaZ70GAK5pyFA-Dpv#CJ9HPh%Jg3X|meHvGR{o8VYc*VnE*9`t z$Q>r%-G>r8%!n{`?vCza3b?SBjD^I`k7KbmBmeJo&-QesJ?*F*-v!#&<7{^xh-A0k zo<;{R*I2Mg!ygI{e#Fo5Z@jXtxHrx{NnD`8``B;@WIu1;>Zh5@!~|6Is@GJKqlNfX zg(%v3#Dz&$FF0@WNy#5r7o`>&)^KzeRp<_y4MR;7WAkU=n+e$VUeXivK2Ng zxbQ$ep+y@DIhw~f2Ut|u`yMW^trx(;bGlfko3JR zpE?$saRRCH`q)_|Pe`1$>}p96_2wn;62VB&IU0B*{hJWRM2)&{Ia0q$-Fx~%4vT7ipJM`P zL3EH1r8n@#tLXEi2wx$eM@%(z5p^bfr(;ubY241GZ(SMMbT)za0{_S}6kmFBK(uGc zRQm<@rzPgw;4%5?Jd?6wJYr%~XNTzgN5w$kDk^cog6`lrJU+b0Gj9MwIn~F}!v|+J zk9~2&n&r{!iRQT%(%D*p&2Ug5X@jeV-x_JI?Fr(ivm`NU9oF|3Az3rAvTQ(V_Z02B zm1I62k%Bnx0Yg|&ULDq#2tQqeLmeuZia44xs;%Y$&rh|D98+%(>qG0FJ)sF75rIQ9 z@2AE)`MMKk#y%k~%Lr(gq$F6f=-%gQ3Q2-r1Iw{MEjO>+4o?}hP^YL+|oc%JEny!1H#hJv*|*rbXd_+>bp4p73JS5+JzM4ZH0*Xm<(37DnT@W_rvguxA3nju zYeKmy311#I2AsOaCu9>AesJNhHbyb~dMp^(JKas{76XV{4~(eND-Iw*lD)Y3ZzN5C zUgM|Um%j}blz|T|qQjL;9BTNWhE_2LW;h2ysV1X?l_AB(4DID+D^|>Gp4#@t$=xT# zLD0|8hfPUM7T3FZ?0uS=2HOv2(u)GtG~df9I+B;OlF zdUy92?KV3i3|mNc2j?=ZSy&jdmVo7Jw;lf@0B6s6}C{rb$To3bM-;TRXzd`}!gT1V3=cv}PZgc`u5)=ZPm zm;a31mRwcTr2Y)r=P|a}t$W(GvNpkydp zn6_zzkY4WV?%>*f+?CdvH!zMrEmjqA+)&KlFQ8Go01Y7=EciY#v|kodA)l)7%e2aMO49%mYNU9V z%83OA)uyp9R6GlLI~PlE7R=D&2zg1pARJfi2>+F(TBssEa<6EDd0 zGb7adp(@GN@GIhl?@Q>K`yr0j3NduLvOdqv8j@@-AAfAv9RK1Epk7yamN7LV%(@YH zDkWAQSgfg&E!gr~3_YA&0dXalL_WD%bY{3!1}SCkgqlkJ7#|9wiaFO~jVM9uMue0zcUhfn%6V z=S??4f5o-@5arvj{?z?7zE-D2CUlX-o}(pxrWAMN1*rmiDmunMMBjXb-Sc^8WrW_H`z zrHR9&(f;n0+5K#l?BL(OGD~_foi|%8H<>g3pKS{O@JBqj2vtb!F4A$lVYTt&MZb(G z$-YE!EWtd=jWSE|HP(p=%yvJv1axj3On9}IEYPHy;t&$A*u-B!jjBB!hMuYYpBKPQ zg;g>Up2HTO39GevY5NW-gT4QHsx;rsIUorI(@f~lCo;dO-hf2V~;!B*Pb)`el!7L3AF3O2HB^6jm;h93!ksKdf4PtF^UrgU0zAb z`Yo5oj5T#ueqm-a!Xx&Op>0zxLRuczr+%1ZDvR$%3P3(`0E z{Ex1{F;bChZW8bJZ!ApAoI)H5rE}jsu3<4(TiCgKCgWX_E<_%LS~lHjr;H-5mejs=ipX9g8?mwg7X$vaS+bpM=dyEpab zy>5{pPm|hSFDmXWh9xfskF-VzKWw{HxuzP^HnwEBUo3heVUpNrsn8)*U#X3=U%u+B z-%CFS@%U>q^3DMO{DB??;3J5k)z>Sp8Azp^Br?Q%6SYjp6Wb;xOkUTk*DwSLcoxSK zKo6DM7Sn1jD-5GGGP_?jnSx2 z1qe*gccJ0;Xgq0n;q8}dbg={o$Hf>(yXn^S_A(ew;_w=KjAR6Hi5MLO(hxxK&JU@# zn7WKqnRRpqg|?O`bpSm3(S}&X3>NZOGSn{;AhB$BPkJ-)=S{_Q{y}{_wv}Z}LR&TG zQ$ikEwdUbDV83b7mll%kNf6`ddVN~k5j_E~0~-h5Cz=N#uToMpt)N9b6Zki&UhFf6 zdOM-@dG7QLl@)Rc>T7q1P`W?hhR_wO-B01mr%K*$L9u4PJ^C+ zP*wkX1QPGlY^9k=b|InNJbU`wA)aZfqSdpx^INvzWJ~-^504gy{6;zK_Hw!XC0jG( z8&_Am)i(Xcc6zXC?sv-tcp%-sl#jiy1$Di&B5yDxzNZt#y09j}%GorJnLYPldf3lM z4X)5b7(lY`+oSfC%)G69{J@{t<_md{EOU!^C;d@lpNG{sJ=Ztlub04)9=ilmQA$fo z+(baF=ZuJ;8X@|ZrY+HLd+_gqBY_Wu@2e4@&G>iYgs3QGvoBu;1W5v4-!VTfj6Y`1 zuVlVl`a2b`H}|>jSGkAO$RPl1(O2f{rpHRHP6OXk`Mk!Nt;N*kac1%h1^DE;IFvZY zW=k$`cBLAn>Brci8HyJt{&rd<78H)1vXMKXcmk0g32 zSi?`e&859jyLsZHe|6peGKxi0;AmKKZ=^aymTz=5<@YDG?#uln;TMjQ+RQP$vA!{fQgk^tvnsF89Qa$VkMn$OMnhR z{JbSr?0Q9-@C*i?*^rN{0NQOGR+p;DsGYaQ2>-kXNb=xy7J#LO6m9%S7Wne41?xxc zvrTlrmVXEiju@BtR4Jq%yzXp1(tfi0+np^ny!}WjJPveCIbCVUAd8L)Nrd2@!jHLG zx&lHBBOI;1k2;YW^lLC#PNbMA{-p?0l6Avi--Cz_k)ZU9$v zaEXLlPd7OG{ru{8NxbF>wqJ99)cUdanJZk&H*IJUHl<-g=sC{uW*&Ib>2}JudVgl| z@*bBX>idq_>+km4!@{7Hz*!ok5K!;d<46V&zMXmK-0m*9VeuF`q$Z6xfT zM|A{X9fXA2P=vX8v>3Uj9PnfG4gQUE&1a9-qkxG`Kxt^4Cp!Y={oWxqD5jcm>1VtB zLvnUx)J-;E>W9(9TyO1 zy@TmK#eE-cLzM>!2~&y@%JOT>$C$pE7hK%JJfaDmB`Z3cc(BaIyAQ4t>;x|Pqeu=7 z4wl`VtK|IDL5v_$_8VF&N(hO$?SU)z{h3$d$|@eAl!ncmQZaaZzWapB-b*{RSjq}sao zvyol6Ck>Myjn^Hu%E zJq<(%&VA&&lz&h_A0gMx;;*YLEh-};Qv`4vCAt^67MgxeHN6_SR2tJjIK0t1SaeF4UA-ZC~_LmC_yBkZ(ecY#K$k4;f z@}@MaYJo5D{pqIF!|4h=N#M0^_w%0?9U}u8Ma+P`3{eFT9)=9MI2wg??{JhdWC2ci zG+}^gtXkddqal%?5;}?%izQWhWn${^*z(6YhlPAJ6C4UAVht%?0%#(5Q+&(-qJ5vJg~bZ0KCUV4SFsI3cRwQ~<)C zB(epry%sGQRxUQ`GrFzXj@AZ=QJBkN;rdr6ki|=&C37A5_*BXq&<_F9B#4TdkaklU zpbJJD!i;K^>omLM7j7QvFv!)*TT%W~JOclJmCbZ!66OYL9PM@#fR&`HOh$)KV#IR2|k!DnY@hzj#~c{I3NY$hti9h&ei< z*UJr?()VoW?38eI&n!q{zn&}vVvfkK@#(-v3=2MY=hq=7ijOWk`k^n_b6#I26e+9l z0}j{L8jv@9bV_w>|{(-Ym2F0VlMp0gX87k@$F(3p)0R#nW@N z(Go89L!3t<&j~;sw?YW#8#YP4mtXDio9R1M7MUYiu~Tj ztoZ%RMIE1kJ^j8LZzS6ieK4oL9;X#quWdi>MHevGOO3qK)aau3FgRH1J6i|)@8tVi z#Y~(cjcO*AcWA|J8TJqX!v-BLX*NaWBhtT{KDX!6kbc}|lns;51RVIjZqEcn8h=!f zmaOaU+%@2O?VhM!-6D*ST#^ zQ%6G@B%_!@u)19v%d7iL{@ouDa50_~S}RzhH7cXYTsQjmobBW_(1AuD$ymvD^ES*x zZr$}KF=(vIvl``0B|)K0seB!jQOv?SpxVDgP*GXU!tT0505pwS5zECj@)GyEJJ~cJ znLaZx7}L?d90d*{vSKXq6C`@W0-jBR2NewJ%Mh1pVtNwgEaqe& z3U^%)fL%s^)&>^PcI%#!LQSv0Q0YP+%Md@SSCkSaroa`#|NUW0l4)uZ4ckS`FP5De0ZWb=+6KjQW7FewJ>np|KQ%S+$b)FlnhdkHJi47e zasNeeUG-D**l)zzRQ?CeeOzL$oMLT1P-r8g14=2PrBMvI1j`id-T#(@f}(`hgLi?J z=-~FdI6s5F^?LX!GK#tB6YT3Ks?>ya)m9@q5toLOL0faPMf#yWozpRD{Jt3w+i);F z_oH%F1p{INi!-2KVK#HW>J4>7$30l#S|T{z6dJ!nqJ6q8Qk^%jou5J;`0^#E%`Nl5 z$S)~vk$T0OESeIt`R`#gdDRg$eLr43R{;#PiJU3}8qNtP@+aCHFl>s|u1VNfT(+Cd z1CggM!USW5lIqmeZpuvUtlZ$^{uGw|Y^{Lc!0TQ^nM9^`Jgdv`Sj=u$d@X~7evP7=IvkPk zJpp*b9eY&ANUwPDhdQLD#3vAw*U{H6s%sA#GYnlgrh>=TsQ8+EfUjQmx6zrBEHgj9 zWL>XFuL?t&{Z21e#tf!XX8cnX_moG3UQ;+v78^sN6#^u6R!TjIEp?JrN%=LfeCC~r z)RF7cCR_y93iI%iK)(5r%+IBcpfIRLr%3F3ON=V)C4DfGDLtK>{N=x|3o)j8UDY?b zGNzX-Lc@hS@chl0w<}OXrb!dpG*81Ro4XMk4+D@eSd*%)rO*icvbZb3k8@A!I{++D zc4l1Ct%_n10X7oYDUUsivj+oQXDT(^jEoZ0Y)9xvnn`tETbRwQmtAx~Y`WahJsa5{ z*uj+AxhP`d>SFTj3MEb085l+W4nn%143-j-{~B{n&v_&}!HUpuzGg|P{M zuB!-R2xn)u}C`OBDbZtGDrZlj%Kt@J& z*?y#7B2e}?U7vcC87c4bx`+C0VEGa3uVdfpd=3@Ge)_j1UxD57$2F`5xEf+SAMTTU z;rBWbH}c=(Gxk5jSRj3&lJ&6LXYD+IYki0p{O^^ipJVCc6Yr{B?PB49j;U?KlbsWA zhrP7IXt&m!JvXP{>T-_EnF9XXZYHRIzpmiu9ZYxOG7+Ce1Urcn-IW6Nd`eqyIXDrZ^==kKx}-%)ny0CHmIn^h5RUq8llT0JC2ao z<)F(GgJDnIUG}K9U)YvBy>@k%lJt@K2k2*0lZAr%V84PQgvgisI?npWVf=iJ`P$F= zeytoA?bPQG>|)|1b3jIAa@hWl?6R6AuOolYCs);;IV`CmajJe&Us>Q;DV<-W3xK+u zwp4IFZM1~FXhI~Y5IXH|_G@WI{*!%-Sq*9tIil^x3L@SeYS= zbq$1ur64VkTkR-<+|SGMW(j*$Dv^2F7b-v-Z#r}0`Am9HT$D795an70wozJ=AW~oo zVVXgJ0-m*%8&q>wRG@4;YGFz-4v;=qgw)FKfG=1q>RthCIG!Ww@gUhhpH>g zv@U22AQ5b9g!Y$?;y&-*+jzFpRf0Z|;a7&h8$c%#!5+buOZz`Ygg&av`7jY-__31a zZz^5bV3#&{@m)msnPuF(8OLIZ`;zGujW#HuZwopuMDUcv;V0$x!w7>_MWWL4G4%tZ z1+5bEI<|9q`bBuM)ni!G0zUWs)G{9D=F(yr!BSm|tzKIFa^Cz8;8DuOD6)acZEdU0`(hd6wPYvb#hlnpr9iB++qh>ekh7QJrf zt@AyR(b7(j+Wb&q7=ju`Y+q3>OUUh!DKS;rxYsI7cEOwb!9A)V&2##9YW@~WK$*-& zof$`pL@vJPnLxchiWyUY;*jxl9Q== z#;DI7pW~<`rO-_bew}6qS9_+awZf7wrdKy3U;I_|J?4^5(WusZr2TkoiR=%0=zi$x z&&naxXn5TheR_G_BK6N=UiB2fT0s20ldU_2(uR9mvI4A@+Sr0SDf_&#uj#QVQT~sI z-HeNzMUbqiGNQLvS-s)5%rM;+5imdDUqBVxaM9r5zilEk)o&exqw;ItZ;;aE3vLah z#qkXmef>iT!6tuSYic@}F+@`pdJ;}gPtU|7{Q_-5lym@_Yem(@2wyl${%n&D8P==~ z82s%Tr-u5}G#vNHs}jq`%iH7dw0uGx8~2q{umf6GrAdo=#!zzZ2A)|5m!?<)j3pwccR5xSn72$M8Jc3c}RInzJN6IR6=@!L~0-VcV`jE$0zk(K4Y8)y6j2TLCp zk7kY^w`ZYZ&^DO_$$PMLi2nf^^z42!yx*+PkZ2nG+gzno!{vRo=y(~YtKj@KmF#0z^i;C8ypTOyBIoo$u{w zt3tlLaxmOaU7hb9K3QzhM25qH`(!!2JUD7R!~t7F2cy2kN_pzc(mDM8sJXX~38WvY zza&D~Bz`AyIX5;-P+vE4H?RnCEvcVf8we7FxK;Bm2@nUxR6h`Wy6_465L^P{M169} z-6XnFl+S8~+Mtk29#owolDL@lz%{p8qP5+o(Q}Mt95Ht&-y zy_MG_G_hoI`OfVM_1$XjWbtP_BdQ#Bt6vUbEk=<+50MW3B_nH1u1 zfeKrL^C}Pjq7VA|1Ol&@XRhvQ{Bu=G2a;AD_nsG#gdTE>kP{ru&37!TncQvAlcl6- zcPYMHJfW+$jPjIx-wXJ7p zA(vz(#cMt%%1}_OP}uX%M+0n5?I}#9nvqL^a0>fULlj*O31cZWu9uhOEHlh%@RHkX zQaekg^MBr8tFAhUg4v~Cv-TAFlnn)FKl z@*4$qJ6Ig{GXwnkJ4=}3xO24@julK^%i&?pxLEGWAWb+V!M0T7HpTCKabl87;O8(! zZVWCz`{w>Z;Eks>s}klQyS!zhw*(d}9r@8dfjYjq+o}gny7rL;e?O=Z9ao_eQmL9t zu?flC41Xi(_GcBn+3;oe9#<$DN>TNX0nZr9+D?7>x;FJE4qqS_^(Lkw7WM1(?0_RD ztH=v6eJJ99m)47)r?(#pK+}WHiX*JtAtB>490bb3&f~PFv zbM7SHpVb?)DtB?+@uGuFccSdPrLcMaLkKt5&YpRlD)gDJZ%O~iNJOR!AaQ`-b8q{R zs2X_OfVG_nR?W9^_6DM4^N`KC#Zi!MsPHvss<2WIdILf+uPlw!XhDj#ldh87n$tMb zC(vk#yQqeCHdAV+22M-TZml<*E4hviFFYmbd~PI%E1*37kH9sn`qtObkPx93ECuYm zrzIqzx5*oW{5(p|kUgMxwP738_#OkeW=4%}_;j@;f=c;FLwA7f7AAw#b|OeIqne$I zYjpN9Nbz#&&C3{Jp3Bgal|F;$tYrOsR*~cPBI3X3hd=sYeEUerJz}d)-u77QCSun5 ze5=I0tj3)j;cdF&RYik(YPE`V_9gylp^sOj-7eIQuSDNxHtahuUy-o3DNM>`k}dx* zQnTa=PR!1dnPu~E^fW5*aE*2kM6|l>GZDhUws~wp>3dw1v^7eJ53Fos>}{bViuWGh zB7bp?YCGX=y_*%cWHAos+8S;mv|DZls+1}=tecv8!B`5zT?NX@t*d_bj|h9h{(V&iW!lJAEB(V$oP`|%k0wSk)y~=S_ySExXo*eg9H9A zo5)swQ4k*3fX^OCeQ`HhRrF2wApUePc2O0De9BCd;(p(u90m$AFryqUNkV03|Y+|x(n>Q z47(wrk*;va^x)?ujW+U=Yv?#f0?Ra5p-qZHz(CkH{wi0nPA|nObLT}7UQ^7$0WmKv zRYx=zp)kZZaL3I?0#P=hK74I+A&GUk(GeAW=?KR_Tk)TL0eZ4gbz6X0^xPbJKNIa4 zQYsqP|9JsC5O$!tsKkNfJX1e~Jd>t;Jx#)Xty`nXlFMh+I+kfgs z8@dvC{Q%_oZdKkrL4O{XC__nd{LWb*H=nB3Kl&Gsnfa+}q(@qCitoAvPQKB?#yN>u zzs2eO*xkr)kFUe?Y&Rv}H`cUZ)E@3(P8oB^4cbln1#R=w{In{ydm z*yn6sdosH8!(IM1O-)JhhFmt!y}~!h&Ofj%yLso4=e6%Wo`(44i@W*!_VCaRmli>+ z5|Nv&9jk?NK%T_Ed!QIluF?_S3^8dT2PF;yW667Id;2H8619J)m;xPI^e5T^I%|9u zO`Fxw(!N`s{G8kZo<}k>K0i6kO`FDMFMJBlamY)VRN{%|vw*ycYgON0v0O{uBCsMp zDY5xY^BL9zHqOVT>*VA#C!f$@x4uK2K96Iqs_0#%-`icoxe>gX&lz?YGCY!nSS>|X z=ks-pCY(X-CAd}$4Vz6DE|`3Zt7|eyxl`+VUSA)1 zVXIWjf&?sk!Jn{#=#Nrt+rVMetIdye-uREjk&BP3z}M1*9>1*%Lu>qNm5fe-=|kog zR|}h|sGR5Qk^}I5z=G!d@+|cRIo+I!5Rv@BGUIpul(YaPQU!5#WIR+Z#*w@dKL7L| zOouf5>nah09ex74X;SOOdLy?1Am|Ewvab1 z0aHv2=aTg^P%cYtKD|xhZxFWbszPqmCwCJ3^CC!metuk!1okVkl7cj=e8U!Xq1p$vB1jH}Kt?t5Cp48z zHEQLlQAq6aS>C^8O z0b!^;wZ-nyX*|hlZUvZlRFfQynB)+yg+>BKq5Dy*r|X@BYubc>sE4it@^e17pq8GK zh@k9+X-q4XYu=Bii}`76aRc)Ji_GgwHXiWc@az<~a8Z&3pcjKoSEU`R0vqbfQ0wUR zIO34PoQ7g!HUNaMrvP-IEx>}Vq&8FlLE%M>y6RQoRGjgIf_}Dwzgs&6MJZ?h?Xu!k znkAM z9z$IO{^Q|^MRvK}!_CahwYq*r)|sk;kf{Tlqi}mXWBp$|Qx2*}k-iMgicOK%4x3h8 z)m#|VHwLS;8~`&No)=oq+{*G4GnYX zEWhr3@TQ>;CZkIz%wVu6-Rr{!i~s6G`90C2Cf>Wd%eB(lGon7ayNjhbQL*N|OQxH? zpvdh^{(T^PO2}zO7>kj*+hdynELir!henu=?eE1O{>(-y*8)6hK96Sjit_ z^mGX(_u}3?3Ssa3F$A=U$xvgnXBL%gFFlHX6fs@cop~ z!&E7xo9C{fbb@RHQ7S|0?qm!3PqzTt|L&zV^a#@01UuJFKUWmX;h^enpq&P;JFl` z%SZpAcd^ggk5hy$Ft`2{pBVi#WC05c=RMQ0F}|X=prSex4Q%sHMSSe@eEs!w*K_lA zx97vNXG}KWoiax_Fu43A<7wk&6SQuJi5o-IeuMgB5m7-WYl?eYA}OhWe14Me_?P<% zgSi|YP$yU5M-KKRD+?!2cd(B?yse8s)i+Hv03i|W1$V2{`{btYMZ)W;=nHAhQ@Y8{|*&dwd-+0B1#7+YSR zZ2jec#GVlv!=5>_&W*E+#CkEoF=@k0(7gzm_vlmd8ns*a#$I8H4aJdH4jtQuNWYFE z-QM%AB%KwAH^kJ(CKEhk{7(%}qg?Z6ZnsRH2gEi~kWmcTN+7fl>qZ~V2$?>;3)%C* z&|sJCwN_12b89qgx?$RI-Jkl!bt}Kr82A-rvecO}tSg&zj0{~xHu4CPXz106(4`A* z6k5X79g}!6-CN|A7 zg0m*ya-{mq4v!QDsU}}U*4r+X()U7=U|_e2o<-S+68Xny8jGUxfUT@CNJM11o5XE} z7;3K`_4l0sGy2u@E^DLRcy;v2GHHO(o&G5z~Nt#q^OI94Uyq{_n24=b2)8kktErV%Zq4Cep+&%i$n zZMtm)*L6jMEUdIs#}>Rf0^h*G1{Qcg6($3j`uUC8;QL*r9ArUOWXpp4xlZ@hbp7O! zO6>_xD1%dr{x|Eb-5$@vN7^={_1m~IQ<7nux*Ip z0Fr!*V!GUqMGTPX9Cx?3%3;iM8<2X$?4ep3(4Kks^chLCZ$h?bBD`v~?dJUD z@fw$OZ}KQb$!Z6zE?-)I|X=oK@*c zFoi<_9|-|lqD5<+2jN6fop|J+j_OGLT63dvJ;^w|nFjTHeXj43i#LKkQ6}iFtLGDM z#QwDaO-u)x{UwI1ZC5SfHQo|`Gj-GrMM(LZb(El@RqZXuMLoBi+98U2t z{y!9HJxR8xkBAwZ{5vB{$C0wH#8|-_$E)6LPwYHzU>pX+%+3!lONo zvw}i4UtM;j#>#QA5NGmPWKqx3C1w?T27_JL?*fX|5~oAvd`wKpx(rD-cm-qG7`7Kv ztbQ6BY;h(C4UhK=*W_Y=zqO+CeA8Z1A8qTV)Use%@@TZ;0y zY+g2Y_UW~Ljx&!8K--}g*h0E=-PGJX(WPzle*jWJt-jUC8R9~LIF9Icy7bdj!=OkQ zxDD5Z9C^#pB*j|G{NgfFN;Yra!1781qa9B=3`0ll$})DTPvr z-}%@d@NYl%37XwZl*=W%ZOgd5?a(1{eQt%PpMIIUAAT?OiE(5U@!U6`X5*GE3~m@l zNX68(N!FH@IB@t7Lz_3EwdUJTKE=Hc+|R(sFarYveDC@15tT|zY}rCkh`D@ynzLum za{rs|XJ~AMVx`72Pe049-Mbhb8zqQhE?u}xb8U^?2lmlP6UyZhFTH$>1GgSz_rY5j z9UtY|x$}@ZWLyi${LCzOJ#Zh#PoL(>wX58D=N%k-;YDI8sMqT#sd)C8XL;}k-hvi_ zmyf=}+ur&nj=pvZl9Xz>#HrKg8Jt_7R4Tjs!dR@%5!R4d)|)YF3}L7URKUd82x-2? z&wu#GDOPG+zdlK~lK_@C-G2uUKl}~~&lmaDb1yi$gU$g*5oxtrSZf#^9dT5dTsyi$ zFQL=zdfvRJ%J|?c>k;3+;5PU7A=V(IB2OJfLwTWXUz}>Jvr^o$c?16^d+!xxS$5WW z{`Nlh+VGK)k&)h3n#%INN-7y-5E2qdfFwW-LKQQ!l-?yI+lO)@lENDY1^33NKwh zUF08OayX1w)-<@%PE~MRn`vRFiGlB8!M%zYGDFM{0$WC`nDCIxw# z8K4Fb(!qCS&osbr>or2>=0BB#^z1$<$&sW8YvtKhR*0TZ+c-lh+qg<28pQ^dNr}Sf zEz&F{vrcIyQP|McgwF9?L+8+0X7p9sxZ(i#(oi%V&!<(dk)@}7SJ{Tr?%&;1 zXC(!`Bhk`Yw)#G|=H_X(ngn5p&gxbmZPtGghfbVu;mld~95}$#_3Kpo`sf=QqjqZn zFZ8VgUXCv%H!ojhe8)C~aA>Wq;rkv*yTkO^bNH1$TukObX3rtVCKd~AvJtw|Eqh>) z=87cCC>IN4?KY~_H2Z`y&q)2&GLGvK`aVgVpoPG91v)p+QV;|raYB-2Y}vV$VyVFN z^eml~HH35tiv2bLIWtT_*Q41ofstx(BTI>(f5Q%nu4H&%fOLuR^>Wh_iyCkO&=EiN;%aTDt{Ot2hVv9NH- z;|{;|?>@rjjoSd&K0d%N{oGIThoAmizVqru#s&vzcWS)nZ9l`?-~3h}p;m9Oygbj9 z=>^VRzJ`#JzTtI9-=nj%Lb2LMj;0pn^bM|Kuv%c-wk?FkB4^HDB~4;pe(5+*KJgHH z_H5UE1A}^U^1AHn?`Ldm1mT4^(uF)G*AA~9KT4+2uYbc^gy*@$Ny^H~D&>OF=(O7% zoT6`B+XUp&0hJ;!lfEQQ%$}n(m9Ru@Wgf@%DOU$kd4kG~jw0?pv#(wM)Ad>d@I!EA zSz<(ITJ%tU&!XxD*P)%|#>v74=0I08r+XBeF4q+RZP0XAIw*|bHdWekY6Y3Hub=14 zthE>^4Ip<6plrgJ(wdfZSk4qW%J3Z{Y{Vi>o-kCD%%b(ZKLS(KTR-%`mE@Tb2|EIU z(5F-gsnwfwvfCPkTx(qGG?4>H!OfXje5u*FYj@8XMM{XZ#zo*bW-`*99)PCVi5ToF zb8~8n%NH&Z)#_~CFv0l?7dUt748HF&I=YU<#UNYv|DXPM}`5DChRz-fd~V?_d9o7mx@$eUtBYSxOxqR%L9)*K{0eiwOk-> zcbJ-*q*|%4FgeNSmaRiJ=juE?#DI zlMy)FCQGB(E2%q;yA6UZnbZM6vyEZw|G zxl&>B@>SLi4KsD=GMlz-Wo>>QUka-IWtyD`5J=bKrNXgkCYP6^=P*vZcNV-Snqmm!?dLJ+sBGG(=0P~n$iJf^aF0M*fw;a?u0zrdm!?&9Tth%L3#mLp|uLUElPtpv}bu1kzXJK)LmDM^~mXT!{p6^?6 zyb;3-Vb*)8P~fGPjxs+tOTAvB+CRXi%^Nv&>O9-GZDwr4297SotmYmY*Nq?@$?9qy z@)Y41N?ohjWN>tpyjiE+Y!ZaNrQ?Bb#iJUi)f)_N*ud5;n|S5;DTE_Y(o6*%G`W^& zH$V!Dp4)q&v_>d90TMRWM49GFpvg011?vklzEuJWFpU!`ppRgApC)Ioff+Gd9I;o*I`Q1j6;q^eIESwV6cW`Unl$Hou1tbe>ZkAIEa0KnVIBi6>1ChRTg#81(m1 z>T=wQAW#ZfEOGJbHHJn;Xsk8xrDM)lS0ZI#X;2E+4a}Jt1PCOnjgFb{cOvTbRb<*B zRf@&6CNuN5P+7{_$||jPj6%_FwrC}q(cK3rjEs>WC_3P;EYfMWDLNjN(GjL=9adW% zM*56hrdEn)4;|J&|1;Y}o+oVGyo0&<8!Rs`_rQd}5BTP{zHJ)-hra3%wb~MY^N(Mo z)`}>~fUH(WdLE(UQlFbKiRW2|mpZE~Oiyz2<{X7eABE6IYDFB!Oy8Jh?bd==YqjaC z7K!47Myo@bDe^oeOU!y$sMqw9Pri+Ed63DeGtAD<<48ziNjpjq(xnw;R2+xS+Jbp+ z*PNe8c6-_ugbA%ylVabfo!~>GwnUm%D3yxHF4yn1>wmglYXE*2F6k0Qv9-sOJ;d@h z3Z!wQ;cgn_-<+ya7&Ki7@LXxRoS5&je0(V&!xa1)E3VawR2gI_7cke330&E;^~*IR zxk09@u0y1a4#A9AwT(7+aB|~d5-W|TZGx{Y46vMElNc=UeHU3@X6?cx{kspMaE!3Y zZotwWqK-7<+)d+SBzaDfSzcbl^CV#ylEg7- zl7dA%rR(8a`h}1ZmFFh0HI-=3HN0(QXdHQ#_gqbs72-jN=ecyEh&V||l9YBQqTTM$ zSFI3uE=iK0v=QsYag4}v2C7AlJpVmD`?=3?Yk7^I|G@hZuFJ^K#J^frSFT^>SAO@C zP^i*ax<#5K_@yE$iRm<&Ndn7kRYW;(UFulZenq1iFRZ%XD*&S&yIb2 zSUIi_iL)l6@niEM@|d2+t3=G&#kkD<=(i9>LU&8+6(&TxIXAbeNuB;M|21 zjEoGhurNoKXd1N|N}EtPl}5(MBFhO}L6UX2bN3d0e@&=t& zi%O-!@^X#MckN+x!?@VCeW$*7;UahK-NOC%9AshsCV8F`da!fbMo}o1n7V$J+1Y90 zG-s$cQ|Ma%7`#Dnb36zTuGK|1Hx-N5(djp6`-)kb)B^ro}s@wPIY7qq_GqYyXlekAWd^ce_z$|-fhAq+E6-jBkbymf3@st z9$=(Y;KucvJoC+GxaY3B$dzPmb%}+=MM{MN^S2gRU0p?KO}SD51aXoO27%#GcO5)1 ze*5L2KB^Kr?TD3?8ete1@ufDg^4i)x0@T(TmfB(HI!c3f4PPni7&?jLI0otTe6-TE zS{+LZ$tacztQ#G|aU9|}rqO8igp+xipu-T)^GMSKt>MzuNs=5cU%AFB$6ldO?qlPI z8W+x;BF~{*E^+zVO~?#_JUlu|Wz6IBE3dF=<3`H;eH2S2u3Wi7GwN{H9d{wov{qI) zd*(cQ@4cIWa)AjUIeFp?VWrIQrU@J&n7KK_+{`R{@41`Ma~T{O;FXtNW!KK_Y~D0Z zn&%vP{zZa3=0~1X9fNHf$eQkv}&RA-8xH7xQ)YLSWZ_aV)(iH|q z#(DYBVeWtYQ7)W2&!uzc*|cRdFTQvLzgS||?%niNs~mpe2#-Jh2-ktbFC5{)M;_$N z$#Y~;WD5d;Kq8bT@9Jh!O|ElhZ`@#f(`IhYFLLF=M&Sbk001BWNklHcSv)%a`}qzh2~E``Dt7~z%wLrv(kIQLxZGg4S8+~>u#bq0zB94g@2*J@vU%E zb6X2wDsB6HhVs|74fQ-1*LCT%J4naF_kEhpCfBdu>=o{S<;}Z2N1$Q>15Ej^juh$|X!AVv8w9nnoeFV&ZPI09bLgofOz=H2*5Lw<1}OD>LfxsIG)3%t()jChBR9-SFc=Q zadw`*{wm8$3k(hn(^*?FIW(AnxvtAn!4J52;w0Pl?&ap8`D-xu2O3Xf1Ft;2he3PW{8fguah!U8c0s;Cdz~GK*2&i4GcU)|lnuM~@E1>g(|}@yB5n{evUvx!c4P$Woizp>7mXy(!Sh0rsD+Q9v$Vw9pV-Hn z9yrLyKmRnXW)oLuv>L18%U^y9&-EGTuW<10ySekgKCb=CbA+Ctjbh#Cs6KY$RhsoR z;d>5GKl3b&7@|gpLZN^X5`=4PnT1DnV1Q>1y~0b+eTS^o!W9Ty7Z-)+nH-%BkMZ1+c>LkV`0$55ghq4f_#v~#v>;7lPMvs>EK5NKtm_ZxblS8#Fg!G51pl2D zVOXTzOlY@T3=RxYYcwbp0t%sTLNt?uECy*5Kon=aV!X$r#@LLyQj#jwqa}51QdiKP@|myT`7U?t-3@t0J4#Twq7eGzNk*q*M#L&NK|)@+Otrs{B#K#D zTBY6YkZDbx8=-HpSU>}fW{W(}sZ>hlb7mPyW}IS_%JDqw(cPs7*`M2S1clI0i*7A0 z<63|AzP>6;OUnddNdG{8&-*cxSEtc&w zqH=|FjSH2|6^`qnRNnLR&-1K@C}(Mk07}Iou4_26eBZOvZnX_91zULAqDJL;PxuS2 z6)NVo2v+y?vDJwQlX^jg7=G?RrK zGs)`m;k5?OGZY;muoFSoHU(B3s|Afli=TSmPw-2>@QWNf{sN=p6CAwjKED0T)3jS1 z%9RSO!V1q{nk7k6vQCFuy~XbRd&!kzu&+YiY7=!j_~jC=Hie_fF;Uc89X4&-!qD(A zhmRcPzJvRjyD`n;%pB|cE2MeO;O32tY@FcIm22jAE2S~i!JxysH?gtG2|IPkF{r+4 zMO#MGAt8;3S}jVIepDf((Wn!3IyioS>v?oqO#;WkEtbiIV;y@mu{Oe1FcZ_jk@&7d zlAG`@q%@YTc?K#2E%6*f`2mowi;xoX94R#D%ur7;)FrJ%uh}y#nIcY7Tp=k30nIeQ zFBZ7t&V5{)nkI@h&ki^o^ zy7Dfy)OE=;I7;JV&PZWVe~ZK62{ZK-xCmvaWq~8DyHG}kA{P!>nj=z$kTIUnMo)v$ zU>M*iBgss0T5rbarB%W(q={hm))HYD;D#YnXU;Np?gF7sh?{jrH%<^I8H-Cx6oy9G zv1cy}b2D7Me2H~Mm*T?{{NMlOcR7FZBI~#BV&iC)ty{P0<3|pQE!%eRhBv;MQ>V}H z%1cMlod&a$msnd_X7A=<(hMf27xd45;QgXpUB?SYPjLTR_woFzr*Vp9gmjEk84kr# ziT(Tc@Wwr(NS$+I>N*#$Ofh+VmX)O?gcQu&oJI;498D)`pz@e{ZJCAn8HD4J#gPFl zJeQ$?GEtO)&T)jGSO|!clr+l;0*_Y52+`6akS@qE;>sr|#d(gZ@7 zATKk$HpREXd?u~U2teAIfJI7`hM|E0JNBkG!2o(9UxD%ZcWm>66gc*)a;(dcup($} zglW zr;rqjA+F<)WM-5&x^9Gey^auqk>LS^5X>zsQ79N|%!!FHRIYG6Qyi(xG&Xbd%cxe{ zild$0q(Dk@KOIYbN|J=Y_swCMq-f6w3d^pGbbWG57xFxhD2@%nq!mBk91IZJQ+)JlfGkjg?Q7M-w63LL(1v<4l zgVg~po;=0QT|1e)e3j9WQRXJEvu@)AEwtsU!`$Q~W8>?YpSsTY`gNQ+dya|qV=P`e z#sBu9_wds{@h%32hjB!g`<^qi+~VTY4O}-Q%Z$&vCly2066@BjM>&GGKKU3Qc<0+W zdGRuT`PFZ5dTN0eo;$({e+^G2d}i+y+B#S4dD;_)XQWqRrc zr%s$=`<~sTnGsPd4Opv9iLkbmF20nER*U4y1O}A?#RCsK$Y6hk)2B{y^yOp5f4@{> zVQ~@HH&)Vi@MHww7;8ppg|o()Lfgj9we*l|q_GR*xpXmS+C*3CxrewJ=lg0U(#sCic`ZKw+n zh5={Kp5qID{RLK57MYp<7ske)X3NI)Y~Qk#zG{hj?K(TRY{m%-_zoz?Bg-{2v$KGp z6Gh~?BJ0G)S=N428y-Nm%>fEJ=uS>q!sju1%-1BpzYVVlcXaR-Ce>e;x0A{5}q!zsjLgm-x{q z9%Sd(5MMrWnuXOGzxJLV;rjd{r*F)YO5eD@Xj6GN^X!rNAY1>wA zUcFAIR^!szDuqHw7ANFNQ+7R^z%(|FOcyYT~?W00F-5F?I1Gn|AIXaa>fE z_uQuf8!wRs4!P-q!ST>G_)ee+r8atJZ9prP<;2z|x0^fRWAtW$?@*E+c@mR3pt~Sh zo+Dj}W6wXwey)t*DhbA+E?bT-5a^{-o31?);M|U0^fb%INRq|ICJ(Qi_6R8TCjd}009h?JZ5gr zh|gc0L@Uji(;qkcn9_Xo?eFB&#Y-&IT9(e3kZD0}wZ=?s9`9C((038iVQy~GG~T&F zWl$^@K)1L#J;mbuG>%^&Zr6L$N=F*HV4h{%TIry)q7?W@p{RAtBr|Z$^HT_Y0^ddG zoW9Bc%5K29(!}kUPJ#i~gr*c4YO=~p6hj|`YxmjowF$rvxL#`jeh99$mAcfzLkojO zON%IF+Kwu%y=0~|Mb|MFo7z}_y3z`Cg&F^9t;sPIA5TgWn+=fK@n+WD>~Dkg2sfE4C7y99(CAI?aXiFEcT* zjlcTrr}>GW{7F9bmw(3>{{AUOhX+jYZ;KAs^YJ~0G&RY+Q`c{@xVXgFx)Fk~K(35m zc)480^IXy-;oR8^q)Ep3_$ZZXmC4ELNNI-DVWEH&#s;!dEwQ??W_Z~)>C|;3t|MtQ zng}7-II$jO6FHZbRtbEwu{ByP!XUtL9HKa(zgp&NPd&x=4t;~qec^BTcmMX+*tuf| zu3P*}p(2FG<69baz>;M3=f zi;3@Z*L`<0Gc!x0-X!#WHtySsMsxYhIZDMMrDBnhN`>oZj`5oxdmiA`cJTtc_w45UnX_~{G5hb_&+xz?$BrK3uDcIVtXDXF z`aDI~?NM>kGzOiUB32j5XmwOXAdGd}g*CO}Hl*xVM+DnpA9V63xl+f$nNrk4c(!UQRGn+1!!n+csH%~JdC z<~2;Rv11z>WkSTDmt<{dK*Hz%v~8G#S@%jSbfzu6$AS=<@%R=!?!WOKm*%uL&q!^J z<)tN7Ys=h!*B>m>933LeD`_w-m#07#OG>l0Z}L!0W^Tpc&_1cBPDL3U<9Km zVy#hW&epA)=&M#a`tnikzxN()T$`e~xX56CnO3Vqb!a*5f=NwVBnu384YLC~$X zCRgAG9w|laZs5q}I)<>!#({^{uiT$CWtJJU>DTRF)a5Rg6QF zuxFai6`*dfYdc-jcKR)(V{L|WV^xiP#_c&E>~n53G^XKAlZ>6)Hz9>!>c%uGiTLr? zKggYT|2Y5SGk-^WsYAKHLcOuX+urd;W^T^XZq?~4hiH|FX0wgsDTJ0NxR$be5ZQ4x);TBBW`mQqXzzxLb@`8JW;6p`)YNw!Tmh+7 z;I}M#SMn?hiNLdnV{WNShO%Qjerr2OZvI~vk;*Yt027d83VE$Hp5w6AZgc&se@kWi zUPkVHge+;3DMi7KRWnOD$}s}Guux=rVTI=o9pb)w?`E~pVqtEU{=PCVy!;Z^rWZJN z@;v9xU!<=blIJ;|XA+5x6N_;tiK2x5z6yoFWoc=Zt5>H83LzsSL&iSQ^7;ecWoT>^ zrEXV%Vttb(8bz^KV0n3!TCGmdMN@^u zb8}Q~l2`>c_|0``WjWva&NG}ieTLcj6<&PlC@;NwibCMiZnv43*ub3!4)TxR{2qr+ zo~LhQj8+`u`aXO1@8zWzUS#v`U9_Tz@r@fmDQ0G7*tvckS*OkZyASfhcc16+*FQ$B z)nePu?VLP*5R^sU2u{;S{Q z;*EKB?%PY$Xs~7L7A{@A!JYTt%gkzn#?%5wUOh{@QKwyB<=_6&2l>$_9$@`YAC*#> zcmK$f6oUeP^tmtcou{AS^>2DTNQaY0j#B8Wa?btkvqInc!1@{%MAW`uNq4{4!tr zm#^ug$9_Y^QG7c<%RWQeiZ7EiGt@EHHRw0==q+8OUs?faw;(~-&w+91iR0*YXKtIt zIEoAf$2CH5&-2+dF^=cDEG{k6Zg&U^AyE|DqS_?;I^$XSLHzuOewGLByPwc6@yGx4H7b+0a2(I3 zp<68jHdjFy8iOMRNJ*lMh_+U*^YV$)JaYd%OixX-yt2w*f0a(BO?hlRn>KCW$jh&C z@W6f+7Upq)NAA0usBNY&?Kq+6Xhf$)A#jPE0xPR)wAvkn6u3cv(6%Y`ixdkXy1#_) z2mHl9ewAHYHgV71og6!TmUCApId%3tS&}h5H&5V7c5IxW)=7+;5u%q}A(ZMhXws23 zn9*pebgp{h*Ia8=H#D$GOyA#fbC7j;9lQkCO-9-)*3q0jvCD#uTpX77Rh z_$uYb#q*49-NM4vtIS@XX50QdxN!O`wJ0X=Tw0xuDWJW808Jhxgr3Xhi7}Ei=jxSf zy~!Bbh@K@H-w$xJ+yYAyAq}ToxFLlwG+>q|5w2?{*N%&hBWSJRImY5tx<1MaiP9XY zQbL(SmYV5BY!Pmrk6d-bCnZ7P(Qb9L<9cG-?p=t$Ol^gb^jAxa z`TKZs-zF->fT^1|^^1pJ5_7j!Sz5S7lBTTHTWIZ~a^s4XMkevum6~=tr{1cYkiMY6 z_((r-9I?_!afG7NTqDoQ^!N4Aj59({prr{Mi;@_v1+6F}&rLI$C~dTPxuV`|(O)eY z{=dpelE~N^zgFe`!0WYJ^FweIOJR(VXkk3U9odzaS%g6tzGuZZ8=`g$S5sJ;jzr*~ zSyv9pG%Pkc#;w2#0u>kpQg>Z?3~J;E6MU5`jRpKok)TY#mTL=_f-4zt720vRks0Ks zAf+k3l{UgQqpZS%o9NL=skL`XxrS zCXf=<)vjT360D7h`Mcv#D3>{U>=Z8?d6~cdyD#GVA;R&9qL?I3`Talm3;Krox%aNU zWVsQIxsGEtmUfFurEKp5R4NsUr6QenhvlVJCa>KfD1;P>B@&$=9fQI-GBAR?ET>oq zOdwb%Mrloy=2XfhuHTrUzrRWthD1?f1;qxz3B!P)p@Cj8<#{f(T9dW48cJz~hx%!C zA|p($R9Q%K-u%Y50TA|&@!~6I@I8k@A;foJ+xBfd@W4ZS@AOroPC}_(BbN@1W)mr0 zb{yD`!fDd$g~VRT{xTXyb51Ctl8 z5Vujrn>W$9b(7!w&0l55mJPJBn8Qbp^VM%Y&$DN5FtB9@cRjd?r5o3&EiJP) zGQ!^b?;}nVmSz{|uaB@p~wf{^$x;nl|TC8 zw>k2{5gvN<5lY1(*DhXW_Qo`uw{KgEcW0gj$3EW1!?Fux-wloZ?^D)fLlvzv}-l~`yc!<14Bc?_gtfILDLrR}~CLNGcy#Oi8|zP^faRa!M^ z%f9E)Xf}<2vWrq``(9m*j^p%v((^n=D862BiAF zk-lT~yWb}Q7G?tAdaem0v(%ql+=vW$*rd)SAXNc*~CMy!`wj(j=jiYx)WoNC}FeMj|^?I3~uYpl037)z+IFas?{>P_w8ls#x(QOvv@+Yb=wwp@7~3QGiPxI6 z*1G}4QkllmGB@*#ox66}90B8eX42ucZIUHnvBdK9B%Mx#Unr1wI=#uSwv!}dn`#dt z4M~Inw=%7nuM)UID*^EOFst$_mkN*|7$Mr7&jtOJ$j zNZ-Zt10H?kAx@t>#qfp+rmkEylQlbO$#j=tpzXxN)Citug7-|8gd&YQV*8#wOxGgL zojQ$HigL9N(kjnA`)xiwGf5t`3H(45O9iT>0zwEnX-=li6wq-UlGrq!Ch$)YD-X{L z&|09fgigCjmMhYzNhTfo2Sx}BMY1d<>a>VjG3D|AN-GLs$n3%r#bSjdlXQ{}t|J*9 zs1T)^MzcefX2h8y@Em+$sE)6hfd1g?wFcma;PS!}g4`a4CbcvFK7`QhD}p#PsE=bC z0`zUst?xQqeEN&H0*2oB9+GwkDFnIofHwQ8FcchdyLpH+qav2tpz%UmM-eHBltu_m zo+MoRhtDvu>i}a9zMlEDCRwJ<0|v$+LTNIAJ$P?_Mh8eWWOg#)T5_k|D-Akpiyw)h z8#%T^=qnb;9()sh(x4V$|o=Nxhn}%Q_001BWNkl)oMJf9@$;0evgKK?O%^wpE%=JX9-_t-sn zL6J8+`Nm!{=wSa4?M!j?d#6Z}3`e8{p2y^+OO*QusMl%;rHNZDW~ZjfgrL57i;^EQ zfB7;)>qa?q`3eQkqrI}m5|Ae;ty+yB2$(r{nvsgf$N!fPaB$C7G9=%5@i@Q!@&8IA zm4uakimOXBR|Ktv1w7Z`(y3EaMn_SN20<9I+-RE=);!0P;1o(6J9m|JgH>G&OQP9s zvQ)do0|)Nlqi%u!{D+_7=<|no_)Sl;b@xurpFT~!R%dkGNDnRUFOFJXzO?ihqqB&T z%=+bb=>f*>c5KTgT;C(PHN)HYzk$$&b>r*VzH<+M_4&`Sy0oZ2{BJ%Y4jnnn|NgQ6 zqxU|-qTIUcs}Epl1EvVJUgXlaQy?Hob9~Va*fK)ft^{6p5pnT-1+^723M(E>qm+Sx zDxE0e)~zK1-|cAx>WwDDLxa@n4Fcbz`(j;Tz3NW*wDF^NT-Rm|48@^703Xp>UhZ30xTEM3Y> zKv!4S_|;$i2>T)oa&9Dttcp z{`awYe27FzmRIYH4ODsc>_ukgZt?81&vO4ATiG){Kx=hLf9w?MD}Pnp6{X4go2Zi zW>4~mfAnXxqKIg1kzLz2GU2(*%+B%kfBp(ZPxAb8hj`*g-p1Ij1B?z-*tTwvJGV~o zMYI2;gV1n|5q}6Cq3VeLm!7miK>%cxf`CmT9SHJyT zj-S3jmZj|8zKI`u-#f@!D|+MDkhn5+(@aG$Q^UYFh7!usx6(KwjUyK37f3QiZFw2r zb8w_%EWd3^osbg8b8V2QaTd%oV=y44q);fZd(UoWj$h*V(PL~raFC!_VtMKc3p2Cq z-?NR6eB#$|f#b(daO&)NmR1|AEiK_BF`ffa9Fu1m?Kp!hryV6YLQoDgxmTo}DDq6O zQjZW$VCjbrg`%O&t~Tn{aZgfjcW6biX?C2DJc|gt0)?Q8?d{4X_Byhd>yD9&vmGj%O*yBVacNX4aU}wGQMGqF3Q|$wUCZO82Dsa zhUulP(nOov1Y8fC+ zaiE1Xt{#pLm4*HJrfZ!Ph-beR-9+8#kF-xW&PH?`E)C=IpskG*;Fa7#-p9 zg9n(Ko9F7`Z}BT1c|VUm^e~;I!KIta{LUYLhS59j=E2PyxpCzR%gbwogTvhYy4TxO zOOGp;FVl)*2m|&VJcyfT#wAH;jvx9S2X}7dqaS>)(9)rQXcXUdkkaGerV(DZe;eOC za*|^&9cBN)JGuYy$7rsskfa&Y*RCTRk60-t)(z5Zb*R;wNCDNpD&=aKL>uZvs=)Ca zvNYq_?>xu$9oul5%bW{RMu!G?<@5z^{@G`lymk%gNHM>#LcLK3ZX@|!gk3t_B3Jg% zdn_`Dw1v2~p-!&bqsf?q*iNsyR-j!DjzxC0ZO8=}G&jvqxuQ}Djle(6@Ps6e6DpOG zrO~N>g~FS>0gM;FP1bd+05-E8{GRVwG+$fwu@&>HyeB*t@^%F;9cid=S&r12EX{hh zkw&ke?Zm-8^LD}kHqXGWMS)4W?F!<%_f=UvL~iX;hX)7v>o5ErM-Cq$SBiS0&4vws z!9cajrp;RstNb{)!L09xYtF6+iO5al_e{R8xu zi<~%dg1ra!Gjnqm&-EBzH^P~dr|~2R&+RpSk#_lm&wi0Fef4X+>n(5K<x`~JGzMC6Y&-2bV zy;B@{8Lh``#%suaNw}rry4uK=k(jmB0ircWh_!+y#V` zBwFFe3DWgYT99-)2q3~tn;ncGI!h9gl@HXevrJyT#2xqEPo)r02#Q2nFmcB|UcE5M@aQO;@7T-6i9zB_as2u`{i7q?vu8Wc zotq>YnqbTQ8%;Vr-7E(IcAXhIVNQZH7TXr6ORNxESTq{U^rEw}#7bl)6n)hyhhBJ* zxy4ns@7T@uZ6~>K=^6`jvn;Osf9$-t?i>e89hVt#gx<%K04x%X!+&zh!$ zJ@1)|Bfmn(#RgHtEZ;JOy1!F;haFr753L`tGCfF#zFdZC}AM^2A& z^!RDkY}!Jmr;pX;Ws*dZ@9gH(lMnK*-&`h}ajE+u)3XaSQq*+{GFL$uiXh!kRAYl| zByqD2GKlfhVV;m7GWH?%wJb8OGdEKMLvQ3QuLv?Gi376PES+t6W|vl3DVHe}Euz>U z7Lrol!)(M<>vb#>GM-DdRws!=P&OGa`|rjNFJ8}IFE#+b0GDjkLLEqx8u!o<>yBYi zj}lGS0bKJ1`WK;ZRwJD_I;Noi+MBU#i(24g872lA^9h;;WSNGB^C(3mb+T}ppMq&< z%14s^JX+F=Ed+Vb!Ps;KZMH=_NB%jdZF z@xSG%{m-%Df0g|Q4pPYFaBPd_xIawk6;4Xq5r&DE@tB;PWo}`Kp}{_FhDs+_rtRQ2 zd=};x>Fj8ux3>#Y*~i4hRGNC2fNgT|(m1B=YK?9jYZH^H!)grEqE@XjJ~pX62Eril zLsnK+TZNWm>LSm!ZQ@u`Uaj*_|NM1Mo;<zCNbM#@Tko9;U{|=<4YuHU(X6ZG>US)XW^6 z-QASS6>@9VaO~6>@+#n^*X-mCZ+t!F`UKJtDdl~8L$oV#$Dsqrzc z*|Uq`zHUD8fp_!V(dP(+;`Ff-^z^O4b8Jc-9TYmdICts{o3?Ht?^*OYE|<<g!idhkUe>JX<;>|33I?1XJj3Qk`#LpM(O`n0)%s^z+oO=rGJm-$uDfP0?|j?aICA1NF@k)12koMU zaC+zw79gq4&#-oFKO5Gs=VKrKO>Eod!6y!aSHN(zpCnGRjP%(FR!VXUQ|Y80SePVH z%+hL|-VGbrxOFS{J^Bc+!Nw`oeHhF>X(07OB%zGZ^vIE;^vvp7AAB@6;zdnyv8w?ko~D0mLT>xa2=<2uUK zRi1g^r*!2#*7UDsd}NA9R!K1MG8qQe_N&D06ozSYVXh1(&*C`_NgOfM*P{a^k-YlG z>o6_Bu?ypD92{V89$(pip1V#?;?^pRUYzDlzx^3DuV067GIXpNB&?RX=fP*i`E%!39>0t!LoS{l zOK)v0hax>^NMh__k+$wGcJAE8ymaW^v6pE4EZ6P5l9%6fJz*oDktp@UpFS*(ogAgQ zTE%fK+VeSv*Y)wf_r04FCr+uSo_S7mb#=32-##v`#w;%{rSExy8%ONkdo|Z=>c&tp zXGbom`9(|kW{i>&*Yj8^SH=ANEKB7TP!I$Sgvb-C03joqTM{KB5C*6OJJUfD*1^gk z!&NNHO+9j&9u+5&*@Z<-m?{)8Q-rN$X;GVN35q=(WL%p>Cgd_MnS48@DR4dKMGDY= zaJ|?7`~qB3n6fzu6zK#mQHn&Vw8$5&LOzyKrxL2BmS5>u_C(2AVU8mmBIu3R7#|q5#1En*&KKN z>kq(mxcevfvs$ST#hQfSx*p&8=YONv)6L#Jy9k2-*K>*Dh%nNz@$YQu3Hre@|zq{MSiYrc-*5#dM<%)Z zCy%hErvtxH$8}8J__|lK|JXTQ6x3@d3{2C+vmJ!eL1l9@^Vr!uLP^S%Dzg_Z5-Ed* zgnSsVJQuK9U8QsF5OL5TYWU1dPO+(E^4?#6AD(SuyICH7`axA*UKZc_t3M?U>SWU- z+*~$CrS8*~&*E7o6H~K%^2^_1d1;wQ!Q{v}e)IO1@N56&&3yIi-{2K5xr(}9$1Aj9 zCW0@1<9~Dh;zj<~A9PX3xUB8(<4w1{oUh;YGr9*iQkkD;DN69=Wj5~IPSEg?alqk& zM;Tndo>*$r>gCH5OpT6G%;$)r1d$q1PoEuS^Y9>Bw{E1dG{;BY{th+_ujlOOB_yz1 zSyqmTc=tQs&Ero#uI|43N1~~V*V3AlSD&bKf-YJUej$J))W65FP)f_VwE9ICrZUlb zcwGP|X=9<~Z_P=%NGIt=s^b+1=I58_>}=N!Y^Wt56O%LAcxziN>X1wlylhsZIpe71 z15l{c$lTmMG#devB#E`LFpi&}H5h^5-o5eKru)}j~h+~$kRrc-P$!9& zYuW$obG-Vk@8RUplPoMPW4Jk@D8x)6L|EesXP%+FG{dW3ej{NNa`eO*>VbnfCe;rem6;529Wn*722WRUn1z;L_I28(kYib#4Q@$q> zEw_uMq8@9nf|U-^Y6%!gf|JVLBmysAWHFYwUI*@$om56oG8ckl308v;6$|ox8`yj0 z9_E(H)K-=;)6J7iG!ok|1cqf|Dv9U1s3>B^%raZ`S$F-**t}8GD%Yj2J>z43PLzxO_-r^Z-bTH=;lZ^H62xOu_K*hRct4ogUq ze4g^i3G$seiXGcI@#DvF9fKfJWD9M|uuM^@l#w!~ zy}b+5vnW^e6J24bIIIbkgdnwgLCOgH1_-@1O=6!gN@#Cuqma*0sYQg18ipCOSgzwb z9+H@bAL3ft+bH7*fk`G)`2Sd;{pY=2Yyf@%F3YkE8HKt)287W1Nh2*r{Wu{-Vk4zK zAY!EtN!u{>dRyoSaz(0hMj%B~`jez9;-(xx5yYC#(?liegi1YSkM;8eC1_DpYy~0E zND?f=L>Oryo)$CBKW_@XmL%O;M2X&i#_2TENVfzDn&Oi*AM|Nspm@Fs5K>{N=J%%X zn<NJi<^<)(uPR>vc-2#+5avnuCM=L{Ut2wW|FTriE==7(&npLQKW-vRmf)+E1ULtW1<)GC46x zeYrv|pT!auDvYqR8G44-(N@S(b{t&GVtCzJ44}GP!8R>A+VVt$1LPbFI}YjZ9paa+ zzn-AJ%DK@|zWLp|#TDDHWN=M4ZpP#6=mi?}ReFckb9Da!*0dK{)7{DLomcU>kAHyA zeB%eK)@zu41Je);_H^;bpZqwDz^CB{%+1d5=YRW;95`~4?oy5uXU=i;j%}=z7kTsR zZsR8pJVp}7ba%87hLV+foy7OKV)s=t^3752-Qjt2FPSRD&-1MoDe6fMeb-8 z^ew^)iqQA<^gq4NoALoj6KsV@$vpb?;}_sSb&9Xl`eoB<_9p4jv58oXQ_7Csz$qz- zq7cir^|T*B6h|+h1F19_Sz}Z6_n(fpg+7l&`ePJJY#TBekH?>QimAy-R;x9(Zrwz+ z*5F&;yN9W%X>#pdc>SA+Y>z~kU|J}23VLhBnX>P7h@j%iT~~pOS)QLGPBeR5C`F=7 zjvP9oeE@6LaO}C`v={OkKbgvt1YmnEg;I&f4nD^hzxE9*%i_LA4>G$FaQ5sd%L_B~ ztm);cXO3~;;9=rKvG~n9DfRX<)LBBx2-CF5XNuJQ0vAsn;rrjehsJ7!Fbwc(H8ys& z;d$v+#k4^s)I-HmBP6o5w}|xbt(obffPwYH+;iUptSl_B{IKu*)t|2 z2|3T<>1Uti)FThGWnDiz)^*eNsvB7;m&x_7C)3_RI5A6GcQ0#uJJ_>(7dPE}6LWrp z{bLJA+apm8EZgJGXD_0ZqEIMs-?>@tJ#m3ju?;B%pZdX*SO&O-BBn5irEYXAA&8__ zmxt-Sub_t&3wQ=Y7e#p?Sz0{}1SPnJ$%&~0T_HHiE zjPX~0{r8wcu(-5Dp;*N8T*5FS+ucdV^T=efl!|%cL~`iJY4P`8`6pg`$1S|$oxehL zwZ>|71(gJ>)&pe%|7(7vOTdoTH?|LZq~YRMH}ZE}#KFmbjLg>TJ^~ zxezV0tppqsQ2LNCfLfT~ng&_h!Z!2qp6U-;se z`G;@Z$?&=&wOWHP)ZF%5E<+GRL~%@IrHbp=bab|(ltv=PNrEsmO~G>=lv1p&t{{Yt zcee~d97Tk2Og5LpFijj+Bg(=kW^8O)djJY~jdTp-bovET)3bzO$iP4!h9PJ)0&2B7 zNJ$t*S{7m$tk&yvb#?P=@A)+zdEx;zIetO>(WgGn`VHFv7g~E1I5RQJrKx$GLIE?A zVdt)0oIQ7*xv6Qoig_H%U~+Vnp^Y0^9G@VHCDRjQY}~kkdJwTvu3#w1>fAho0|T5p zeGXg34E46Nyfja#RN~$TA7yN6mccdM1W~|+$r;}D;oryeJcc%GWOVcbmWuH#_~dVW zfH&WEJ8!%BT0Z^xFVU#25=0Sx;!|0vlJQ)GVepyH|1}epkiNb(7)tTCU%eC0c6jgG zeuY>qaLvBG-1F$O!3Eyc7Dq)o-HOur^!YOG)!#px!a*>Jyr0HpLCDukt> z1$L9*BU+7->$+H$MI0w-5T215eq{?&3W_L>Q;A?YL4AQlNz-HW`?R>Q#0Nj{8+`f? z{(uJ`e?SF6EY=MU62$?7eFIeM4eosS5Tna=4D^IHL14(FH7JM?T5f>Ab1W`hy3F#* zD%&=#r@UHY_R=_>W6|(K1~v>+>}==Iq30-MJP=CLn9`w4j4lEbVNkC}JbUaE!~MOy z_LdtM8K30*`4RG2m)hzoj%DE34&{YquHUqgKl|fP5r;kq-AIN}#9x2)o6KKu8CW~W zyWak*T%NeZ!9yqbZ@=|HIy*a%QHVrPDwa5X@e+Udg|86^2fOLJ(mkWjeUXZD7sq(b zl|#JyHSgojC!S;Q=H{D9HUI!107*naR2z81wc8nADr0$BiW!%Zt)-o|mtnTrV5Qce z9wpSnNK3)IEDxO?V{WBJlJ(g8vX^n<@N*n_{4u>XF=!S2W-762BnqJn9HEG1LZUQA zI*vlZB*AtpT*pSnG7UF0Nu)r<0j_1DEQg?0#rFd&*Cmt+LnXL|_Nidl1hp#4uY+ac zW3uDQ^}Oopt=xS54MZeJBwzT)@9^J0^*^}dt-s7q{^hGouTP91d&Z$%> z(7X%;Q;QWo^pMS*7+c&VfT4m?%D|r3u-$bGm3$qg(K6QqJPhFy3t0R(# zO`EpxzW2T#NGKEvOwL!-+}xa4e(pGawaTV#TZrR?Y$1;g4D8y%Yp&U>@)?s8C(ekY zC(m;J(j-d@ODrrb(^1TD;>2lep(u5fn3|m8!ud-$PL{!eK2DxIO_V6YP*SU`infk6 zf>`b>&_glU86rRRpJ!^mWaY3Be^Gq8o5$x>ZiBn+x_^$y}@LaHlD4=oHE zWb*&IHv7+hz1RT!0$jO#9>>c-y{-|QX(3@71~C%SfjzKpNG!luE2I}bW9Q}}~M-hGy(wocb^?afy zVyV%*C8iQ|W*yDuwgt7sWVseluyyofoQ^vU3AUwE9F=%p zYn>QEPhS$P#|@>zvurA>HO`&CKo~Z7_>o6ht@$VvCr_NBQZAFpf0ds-_%Ovn0jZi= zY_JSyG<xeg6KU}|cHY&L@-3?0l8YvX4o zkw6}E-OG&-f;MUu3Q>I#CR3Nk>Fn-dwX)2mW5+bA&vkGdhf8NhuuOwup@g9%%QN%LOwW?d zxMb~w+i!XaJ)M0_%ue#)WBchJ7-D{I4rMr~B*AgBWZJqIo0_MicK}LxY>l>)oeRA0>D|MgW`|Mxx=;2W|ZP~(}YqoRz=n0&*HT?XE z1H9&yH?yXro1V4n7`)P_x4RR=vQP+=uxLafCQ@f(7zRSd7>3Y(m{huAD@j9YQ#yu; zg(l*hdgcIMI(wYFqc=*nh&gur6ku@Yo!_I>R>Ty#m~BqWn=LVb5QcU>>e@A(x~p`P zle$%eAkEiG|9nbe5zqgmRA>{h(PVTR_(4dakf*DwgN6A;k|ZXMB|}5~G#WliO8WbI z86Te_iDOi=i%y#g(=^hlyAD-)p-joN(i{MpHVSEj+uUF@n+3zrO|W6S5KpSJ1}w{j z7Rf~qB*HM#%|w#uTmhk@stnQUbZ8=4n++9^rVVRJk&#M>dV0J0o4@%o_x|KZ%*-u` zHT`QC8tUi##VLw~JUzW#T&fyGg)Z!ji)ol7=wK%^^)pE&5tf$GC83WY6<2KC#FJa&C*sz}7!D0IQ zx~Y|y`IkozQMzI~HD$43*B-LHeNe67nV``3f^8ba!lY!_skEyZ5eYK%>BOfqmtirK zl>L}CB0AcO%+?|@mdQ|Of$^nP7V80P9N0Y2&5hUW(hPgYA&4Y*?LWqH&F97~Yq?>^ zCIY`fb+yW_jYBlTh{ul{qN}5gpkAd~o>SMn@)ZJqmG9qoFG}i3`U&1I11KS-RVcoL+3uTgb4X)W!Zw(@X^hiD6@<7){sIL#^fs z5J_#u(6TJOnU<;4$24epI28JsY#RnitUu$4RC*YcFVS`7ZdRrzF%1K6U<1DC634Oj z!U;h$;X*X!h9cd#B#Mk}@${*S?Ag#qkO=aY!NA%f{_G2X%}`%2ZEXdH*R56SH*FPd zrA1BoQ;NQ|!~E@6{+1ovwy|mBu$q{DM##YDwb$;Tt-Fgaf9*~>J327CyBMFG;KckC zPkg^7Y%@*tmHJtw5Uf@z2r+d>`w=f|7P*Xv?PjRe zYeX^zB*Mv~;s%awW04?bOvA5ZS`G$^D6C=GE>RSu=y8Q%Sj3T!DIo7T2-8BpV=rF+ z(e+{j@C$LJ$#@1JEF?OLy=gWhrD`+}3r*J0msFaWpRx7yr>O`vQoXAZ;F?Bjb+6E? z$@FEh3_&B-n}Sg4;$QGQ#xqDHiDl{nA&yW|(pSi0VGv5G@nT9(I+|)EhcYQzk@GV3-y` z5NgkbyPjh|)!EG?BOg+)X@G=>qNCz*i ztghnNE^(5uyj(^IgIq2Pz{27ZuIu1BI>;+d^fb9x%u{dpX%u@*x#5$|7+I!|QItu?#Mp zAEQvn)7I8bqh7-lHij_p+B1*@+Q5oIKA$6Rm_%_vp^#%}a4izaGlz~awNxeBvksLc zD3xH@4td8U>$((*CBj(KB{FT@1PeZMGc$B|ck+REy_p+t{3Uw3I|;*p^Owf?lmGce z=9Vh#+1SU~(Nj##&vV<$u4VsI2U#qyvanJm<9Xb$dk0^=>wc!Dr&D98i-{tLBTWZU zkhe|het^ihL_vUK*hDf$0&XTltkQt4Bq3-7m{Gu+ZrMk@JjdFhL2lT$hi`rR+l)^y z@|xT3U}9>VFMRP!#7UffCYyI)GpY9l6Za-xyE(;{x}Ya5AR(P{H#cpjfl8t18i>=J zv_DTBYAY3)n4BR=5@aH2Yby}N3A1wx$VB1?5nWv!8keY=-T~E`+MB5fx%p*_=6#u_ z^)`P}q}vh8v`Az#)Jz-y_3ziF&Sv4Sn+??pJR{X<+m4;eILuaqBX}M<(DYG2Gf`X< zj4VrMDj%)dM>F`k0xTM%L@B-@1iDA7yd{>zp1vhwC`(xN-}Y=aJ2LxTa9$$_j^$ zofXwah?Of4$8`eBCX|}q6e~sK2O761B~Khb$0z^khYW4sO{2WTQ)e$zEEZX<``mxz zEH@2i)x~3@6pJO%+g2po)lM;=;mFa`bd<7Kecfyw=z*0bPCoH4!+USQ@G=y-`>=ca zunmwR#eJrmB#musehy4x1l9RjKJtd!*tcnjpB+8NSMPtCkH7Vmgo)zLM~`s()mypY zign!k+z9{n#9==Dfwv%3!fIui2OoKiAWCQ?iVI`&WZOFV*&~m0=HL@VjT%WDapk9e zpSzzt%mar{a&?cZdh-@p^{B|A3{iAE6NTjMm8 zNkf{f)FRG}%}{Lb;g#F262;;OH(s@gkG5^I$h6dMsEcJG{$0>TbC#w6 z$1sUgjiyZV04zgGc+zp5HtVLvzfh{>ya%uh1IN$@o*|$bMf4T(nj)hVQKEI426{Cr zgdk7?%ODL*N>Ol4*@JB68-R=8(qe_EXP6{c#E&&Q-Ad&GGF_`00>VgQ+6I1V4g-CN zn!?14LoOaTM0@`r?d>J5zV;eE^{&_9x*nF}(5Tn>-oJg9rE-mDpV`l?zxN@2^wXa+ zx41-aPd8B%(x^uWQxi(!NOR*|$0Fmo4Hg!cQ|`Kj?}wNM%*`#(v!+*1 zXKYC(o1@|T2(%o?5Rk;W@C&1;MRk!$MBw{i7!(V63WXdX$mg>dh9HV!8Vx-ek0L#7 zRcOt1F`wn3M}E$O4?n_%^P{|E-!AgS5^w&Mw~@;fL?R`jAM>^E{u_V!?Vr-)I3P?s zHv{Dy+9I$2w@UQzttEDtwBS`01@i~uDnuV-(VYSy1D?x*un~R zWnzUsZLUSmb+q(D2r9KI1c6Qj6@o-*DT(EJAZ*_EtM8^!uh9r1gkf?20}t|nxBoJ? zz4FyS!llcX`5#~T26z4RL0t&x!y)S@+22ho!Ih_s+iltjqq!63(FJ=c^dVG*6yd;fANCmL{HkE$8$E7 zM=Je0R%tpxk{}FIbJoM>y$q&dk|>=5Or%n>k&R^-+ACvg>5ygW4W3Mrmf0Dl zC-6zCwMV3{o4#*Gx>XUTHfJZP0ogQlcvzuO0I5g}-J}Q#`k25(ofw1k=JD{@-49fzk@ux|Wa59W=gru=Fhv%A%j-2OJuY3iEkDX!v{zI(o zE>K=vpxW>?*g>K(lwBPZGd4z8BX0Q2EtauNgF+#P=Q<>DLRhU}!~vmU2+&6C+2vK% z@7zV7Fo@Fc%QOrO1YrJZvLJjm46NbO%mUd=hMx8k#X?qG z8maS&n{K47y@X{NESJml_4V=SlTWL<$cpj#s-9M>nCi?Vh2brf>pn@6P;fNCsClM0 zJsyUkvCy?J!m&)kIALz7%*>pJfj$Gzj?d8DR%Cp7hF|^s=lF|1{X?#}W*>eW^U&c_ z40RQG=+VbH^~{rWmoltd+s}vIa4Q$)R*1qL))p*I9(|4<{O}Quo*f}qEYjB1O=a;s zJNh?@fu0U3^Ydz1CcNjD?-0ATZ{ov8pL}(gJE|%Fm)W`14!#sNW62~r#lkq&N z^#%U%o(K8thu%T0TIWZP9^mGko4Eb@JvfFzAX1-%VNi=DjsPdc04W6+x)}%~iJjhK zmR75#h-*y;lIUfjFrN1gH9a+96cZ!p$VgnjN>Xj$7D`Cl!H?n=WyuhNf@|qO!?X!W z62;Y<*0N{gTDrTsI5Jn~kG}H&(|(47aUak8^f+sZqnNf$Ju&HAw~_k~9Ovnyr`yInh=S#BpjuwlFLk z*U{(yb8K!=a%S1=E8wyN|g{5V#+1QOC1WQW`)Dpptef#Jr6mY6@)T=AZ zEiT}8_To4mwqt7vSQxOhT;^SG`xOTJ`xI*%l zJ6^$8KKE(f`rkgy1CKt*mD{#aEEW-l!PX7Kj9>U?MlMcr-3`~$(a}zAb%loS^Wftr z*nY)UE{%>*XfJX9{XgTX-Mg?Hi)=o}^z<|rFOHG5EnPGVEfGqhkWU|a99dnar@KUN zcRM2^qkzfS#Y=eE9B~xs`zrms=#REWzY4=ZsC1g${LH3PW1XZMql8MQ+p?8_Eg>c2 zq)kIJ*;6(XT_sTzBc)&j*G*iHAc?%3vHvx|0Xo*ld&2Mc$nk1Oi z%&g6{X^OCE>U3aeZ3~<2OPomTbh?)ao5iIi#>U6kw|ghU>xcRA{SR{B$tN%~dFIU$ z*crC(-bGJe9}|;PG@@90DbOkAMw}o>P^O7#IUo#@C}5=#Fu62NrB>&fy?dFRm|}5u zp7v6SCUL+p1j^DWw?-VJ1SGK}7At)6H{QWeSCNs+Qv?{awPm^W+N&7M>87sQ2-s@7 z^mcXX^FC?52QgBa*tSEdR79W%!x(@tjLCRf&Scv<-y(_vW@l%3?!Zars&#~u(Vi=% zNQ7YR+CH{#+swTWJxPg(Kl-(|@RbJ+vb4O+a?Qta9d-`)@zj|M{M+Hn%pDx%(I=0P z%jF1SMWwRBn)So94{a2$>gwg$GvlmORr2 z+5MWEF%zFcK1WY?8#}gc;I9Tzv8wX2vEFSyw!K z=o~-z*;9P`t_Or{)F~C)D7KZDUZ{wTiB6`@Winhb*n{=-2r`>zrPjbSBt_TYop-#9 z`wt%F$mJ>C`TE`# zGa3H*;CUWDJx&dWy5sP@GmGRi9=#j45KGBOd4;GZ$=fzgcR!+#r);`pwwP@9Tq+Cm zEG;i_b}2wUd5DhQ0ls$M>gYCuZ|F~Xk0Db{3 z+qFfKV)W9K6XHasDY`1<|AU`stX;DxhICq+PX5ePci8;p=CsdD$s=JRb+D2UxM}eo zy`VV|LVE+6goiMZxTe`M<<=u@BD92VJmOTE3koBB2EJ$wvP?EvHegZ!r2sDqs zy`zmx#zrY{U57@cs+*W3qO+?5*Kt@bm+4>AgD?fcvXk?-nOj&A zk3D^qZQHL<#e9K<<%+1SR(R#hU&j1WRi`QoQ`0&yka0-XbFj?<5B%&AEYGFkH^{i| z^97^OI#ZLhK#OBc+hl%zfo+*x7`8>$%riGN#i6J7(^e{xS9O$9Y#Lh2dv3j+`NeWe zw$@h2QEY2x&sA3dij3=$$!3{fEVELrvT5BA)ARFu^wWRN$mL0bm1QnnzRaKh;UDm^ z_r8^n{m*~k*@MsW&R1MVj1I->wk6f}5}_Z^-rkPs*sNAoQH?rMDF%m!iKW1H9IC5T zdin=2ftBTD`a0S%Q+=*p!J8~D&hWXTX`PRSQiREVao!|Zhk3Iev zzwv>O5XEV+npUbZHRKtoWDcnirupwG*_PBL-Q=}&|EVTkrMmy7bT5?1S^eBnrl;opnKr-D%7^V*MQcCmp zNe2%~>IT)aEu9YAl=4C92hbi1B^61eKO0)Er%l7nYy_D|l&M;jAEgx1NDvs9hS@5J zUKniD`g7t@WPP6E{Ixt_@v%K<#Ygsq64w=3mNfI-= zutYsd^m`O1sexS}Op{VEug~4|>@^Bzi;FLTdfmsiJ+^LK&&jzO&Po+wS&%5=B%$F4 zjGa5j%)~V3CuaEjyMNBzk3ECYGemDG!}lNAPi1C?J-_oCb10GJSI*Y zp^=6%_O!S2vRiKA{OEbUbMKSLdPR5{kIv3cR!ob>PM+tPkuiEZO7!GhuG%=n46M|E@1@OvKud+1 z&qIm8Nk8v00oOGViWa~lLZD1R5ctf`&a!Fa1`HIl#dWvlSy}q53CysG>Y?{*} zW0WgZY|CJHXbs(+1$OM*$+L$~va-AYNb;p3EC)kKEc7-+m>x22Ad^trnw$cH6kH$@TrWq)u{n3)qH-J?B@o429>=i>f{>t5 zZO#;4y#9~t#RlLP;mWj!F`D@<3{9C3sWBIHDz9gm*h1sSnouhv)%&Et9U`e8z#`T5 zLmDb%=mOofbU0Woipe=vnljqd3a8TvAqdh&!x8$ml+uTuA++qsGz_EwEA<#eN*C#- z(y|>V^(ur)OM|3T|ISD(l%^U9k$&BY4ptF*KBu|&rh#Q@3X*FW)L+2qmr55EbzhP5 zJaAB(lr_wif@&vS7ci=YvpP+Yz|L1#xh-923`{W597WqW&xdbJKp zQEV$RKetG4PZyWQrfD>MoRlOK#R*9ilg(vmG<+Jqj~{3WM5EClm&@qTqadVM%oBtW zwOUOVih)m@NIcI26f3JW&X0^zuhkhG-oVKD%N#iHthoN#y|j0BQC=?dv-=-mYGIL% zt^piV5QH&OX@^H5^;ET^*oG25{G0R zOPi0E8`OQDp}}>${~fHp|j#osWO&PuRL)9sle9`V4>i zSAWOM%p6y2*+LLY?!NaSUjM3>bIsLzxO&GG98rq%7cLM64T{+;4hepv!Ni4&l)5`H zvw4>1<}sAu+^N&_4)k;G^ciF%?K0 znw8UZaVcBGE5mr+2(0@RqxEMEOPdark~(K1ZHnRqL?TlXkqJT)1|bNrEek2N6EmYAdC>mL=QpYIKr|WEdde+9qny=^Xvb}1NZ%edMLSa>jrwe@;vg`LDp^DjBtzW z*}ap};98zJbeN8wUXC9=OlQv;+B>^x)N7gvo*IY*f*>7)(A;_`i66#9QH(Ak3^Hv+ z!borXETz2{mSdA32*a2{vB>oNGS8eCAqg8)Lx~|A9((2l-~P#?*p`i9nUKU(%gfw$ z%S+gE)i!b#T%4Qdhd+LR_ELdrqk)^vV_JG+mMD->fJzdLc(q_=c7YAscCgflNjmx{ zbfietR4UbNC@u(tv2$m6{Y$Rm_uuzc&Rm}6TaO;%kKXcfj*njEL!bB)Dl2cNFZ=(n z_nuLfUFEs%Gv{1kr`o%6=&tToby5eZm4%RmBqW3oLIw#LFaiw5fU%8j@Z}sZ_QCeC z@x{hC;BW=Dj0p~8B|s7ipsZG_lRBrW?#g-Rz0#cL$6UKwjB)+r+;e|0Y^^aghFYrH zz0+Fj3-9~9E>~Z7K6`)kT`s-lb!Y@z2NfGuXSnLs+Yq%GW1<#Gt0D4^%l%f`sE!^W=R8<@(%vU>sqLHTC8?c=Yf%h5S6V zOgGqyr_YQyLL{>!}Y?Qf=#FL2KADzeH@Z)xuO#t#_Yu#us>!}Bk^$T{10 z@YdVj#87`fZ++t%xaP{sS*$e3W-|m~L;^I!kYh)V(wWb&X3a3A&K~~ufhTzU#4L&9 zll5F=zR0J)_Y~P&j#j3~XYPB3k)Ax2M6&DT0!Qw;houOFmm&YMP&<fXd`Q}fU4qG_dp{^b19s=P|_w)SW7r%}hhg@~Z4nFqYw=q3E&k108 zd5MKZZMwR;M4?b*W`3Dky+sr!v|0hpR>Y%^{+NmJ3Ho}wId+kI&h!V=xT51fmexiKV6Ch}Y zG5x*0A~AN;P^~WEx*pkliB_wX{XeYG{?i_>Gyp#fhj6TuCB4-vo!E)D610MJdY2fS zm))=A3ZcXPTzjqTrqZDxF)Mn1C&fZGW1A}MIg&_g5^eSWD~|6H?C`%GB%{hlOkmu z+iiqK;|ocmtj;mf2G4N_;)FQTNC_g66dE<$u)*(s;&<4xc^d#x67rqCY*p>^}|!L4ZL}>d5fqkDlee2Oi*|hacx1Z+kP{U47i}x|;xZMH!SDx)8wehV<6OraKXmpZTW3Y4x1bF!ZyyWdV^B-vaZ<+}X&Uw@f{Q_I}`*4s&R zLPI-bht{IHddNf(xt;+Q7MD!camD6SkbYX$8gCibC>zeGIQ&y|N+G!ZxZ}Cv1{%%LOAeYZcb79c0tU2><-$ zFJg4e9Y6mb4jwto$A0@0)@+_8XiMdwSlg!BKBfR+R>(jm{j(GTM@fP(T*({o9G5T( ziNY{_{sE5T+RbCD#fLuhem?zs|AQYs^Z+IfxZ%2M7@wTM^$TRO1@8XglYIBFU6hJN znzJ+X^$((>goVi|9M31?D}2X>4ccleK{zf5iHQ?J4X)?m_#Uq7pf#3?rDUq%c8H}( zGd3XOyX1U_nOcia|J~Q|l_rX;tf5paGQ4Ijp|$~JGA-~12M2KstQzcN+vX8Q)~@E~ zZg~TD-TgJb@%3+kpRpS6cFPww`RFG<#+z=smd76Zu{k}pAPN}|6GxO|8~$V|XoiC4 zFt~X;-K7#Af6p7)dFTWW>^p%gt-SO64QsjT+G{vIvw&2JHATf&cRk04fBD_G8JF8T z3aneR7J;NYqYy!rd^Uq4;KZ?G%vNg1d?%|58AxK9Q9_^{Dy{Rb{N?;P%U?kwVgpHPXv4(TdTnItJ!QpR;1$aZkB5+IdB zcSbT$%n=JorCLXtglcRz>fJeqi9>r?8b6Ki*^>N@#^!Ap?W?Z&zSkGtw;CIP) zh|M5GYpja%i^ZB2UXxk9g>Q!c@Cy1g5H{`ZTr{~E_D4ZzR9A%qqRJ5jS!9gV`u zW?UgrO5zDYs5Ob!DSz3bGQG68R?;T!M%sq#v;#*Jf>2uos7@#IO4^G?M%n_yv`6!R zi$Ia`oe_4@F9pj%f=D#J4vDlTHk!Jt5IV-ekSK>Rl`lC$rIG@JN*`AXi%N5(r6f4% zpQE%GandATg}_m^A#qdrlGe6RYMY-OAqas?#zz9nt-ux;$|H&rW@jhKW*kbTZiEzU zJ9j;vh&g`r2sgj}^*r?OW1Jj4Z4*wDgjS&OeLGccg%O7ipJ4T>0ZOF~;v}X}C{QTm zsnzO4VQ8}$wB?x3&Mng0*F%4Q4_X`646kNla)wqI;wT5tbqHDkp6ig!`WBt29DLWI zR&RnaIIc@yUpGMzpp-&NNf<`ypCw@sT3LWnRBKkQGcYi~mMxpjvpZiD#m*kqoU@LZ z`8kwwFh<}ylCFV4Hf-L4nXlkva|olYi9FpJg~As6tyq&p5k?qmSXRn5VHi*r!RkrS zogK`~FEKejMyXVySjaOlJWMW^C1)ba)heT>&#?Q*D8|bYx8~R~)Wd6Db2W<#3;3BV zqcgL7?(T1}lqlA2+>A~V<||bK4L!ZxWHKIJsfd#Vgh?y}&_6K9^E-dQ)YwTb+Bm|g z$vK|fdytOKZknwYCb9AI^?DsCMA|?Ks?7#fSeev27#ha<91<)cCr*R20x8&YFrh2w zv1iX7>g7eo$H&QLJm!}FiKtD)iDPJ=Gt#6q8ymqVq)p{CX(m8B1<9m0XPtU(WIFvz z(sQ&ee-Y`qB2qDYyPlV+Kfp?bj5SlI(?}siYTRAX=%mI%+isZDa}vji-5dbzG+>!- zCDN+^I*u(xsl6~aXVIQUpCt(yZ4*zeMM0-1UAtxYsm3NPWZHfJ5UHfhl53Q-0c5`C z(hfdr|C~jj+Q;?%4FC46``NW?A5tllBh9_ve@wJOL!nrtfAugw-aiW3LAP2+pjB^J zd7|qfNg&pQp*1GQ26UX@WzHI-k?qZDN*dD%%avN1bgrp69$E;9px{{FhE5V(-=$}u z-(r2!G~L9sQ_>Al&_WtXzSK$IzySGz&ud?IozcxIyI$BW?*8&DjYf;F{QFlJS-X~2 ztAU@%@!2nYk^Ou3a`@l@8cQ?Wa`Wp%?)U`K7{>PQrm8aZo-=}Wd^{zn1~Ix7k;~*6 zU#RfH(NS8hkhOi?%q~~S`X1+Bu${=j-qA_oR+X@{j!*s3Uz>I7R*8H*5Bdoj%_gVI zp~&`+;1_#vJeQ{*d6bUfb8wT8lTVJP#i~no^;+UgfysqwOt^vHx&1o+pC3HMv*UC0 zcNQ2wF-|;t2IF`bB$4B>sCAmppjeg?H%k ze#@Kq%Rl%yGjr4C;EPX)k&%sj<}-iH(PN{GY*?S7vF-OyIW9r9%;e~C_P_WnTQ+Rq zHJ4q+)XWqg|J)Z@b^YyReMy*TjI`%Tho|ryg|8${Pf!U`5Qi}ovmV+&F6(pfr2{OU zILwA?Z^8&k!BcojF#6IST1)esd+FuKOrAt1Hsivi8&#!PIU@!5Cb6l>LJ*m=c^m>( z?#&pRT@g7M;v``)Xi<#~842O!Dd_A???LIgD6k|kV*o%wzrIkglEN(!WL=M`*#(~7 z`69Qz<}%`-Nh=H}2Qj;jkCV+>0EN~X-*s_a4A2LK3{lWx^4MW+xcowz zbA3!sjPuOX&yg5GcUOseqe->VVC&}X{LfGSF0(VIIeP3Utq2o@Aq%soMaK8Yrnw3_ z4srb~ZYGECN}+W^6val#SV$=$s@Tz`mQ-p@6NdI0R>5>{!35z6tAriK#GXe9{c zr66^DVj4>!3 zf{BR@c)1Muj87wpFlog5SSw~O_Q<%7r4Z5PBil?4SK0|+oM>b!aj<>@yBUZQ+jIzH z(@Le1_>Lru?PGaLkrjquc@`ZFMC1fj)^ry#x|3V6joPiM2bJu7VT+gF&M3B)~YP^7Rhy# z=q~l}nhUq`wR;}qXe;5I?gG7CT|}{_+KM@S>>zKwayy^@^e2h15|Bv4r|kb8}Q`I~eHfWW!J|KX~dzdiw`xg)N-gA{TD|Ahn=LJ&IX1)W`Pi+o(0mAO+=G zlX`0w$M=z1lW2ib0+}{BLQ0GfBw@=IwJDxbV9-LKg|sGhKr2P1QelmrE(vm_sJ)`!zZXtpUkZOWAtq^Z0q zDs-h3IBNzr>3a|2Wd_?+N`y$|Xd>0%r^aE?E+2uXrOqy;R-qK)H3gLH6pVrgee*bIk6 zlSvXHA()?-#Lwlp_t||Ee3!RheW?g$jx#qi!=)GR;M?~;%u~C8WZ$x-bN5b>9$ugTQ|HkInVFB{btV0 zFY(~+BjkLK&O#2~b=lBY?+H0<$zi)t2 zXNeEr@p|IKaC&BmA0It~t8%zXGPAJA^b1dL`|Ur+t+(97aBqo@jKlkHxQusQa}gcI zJa4#YGdG<-LX5O%YiWIDI?=?5#*y&+scF9Y%t7ke0>xq%Yc9ExRRzJSo^GPBMSo8Z z*S+RC0IJmm9nfLvvw`3 zh6Zt+gpAR&f{=Wn1STLoHR#MZWE{y-t%*`D8fYcpD~rs|J84sGG}(?08i}OfD+*F` z^1yx?OABnd_%i%rw{1q!0g=`=dM`G%J#o@&Ptx9y8}N)qr{{*|EU>a2Ea_-XF5|QR z=n)o=ousemBeESR$9l8!uDvg6O*%lZkJaAlBLq>L;5&kM-Eaj>Bk3ySdB;uH^5Z>+ zn5ooJvP2u&C9wlGCumSvoa3S$J4nKiD2h3-cOQ4Y`6f1Xxx8xYb<9jp@XXHrX6LS# z#B#-Yz*_YNb91xo+5HrwV`GG2h)yC=t1Mzr)XI^)hkHIjEXa7Sk;;a}X|0739w^^P z6Nzlb10jt`BB6C6q~jT*9p-9P65+D6Fh^&p0MfJbhPWz(RH-!4p}VV#mexq&zLEs| z9~`eV06znVt7FhMNF$CRR;~@5ffa3hyRc7;u@{GQDu=KqtT2|slce&Rm{ckQU?9{< znwAT$kW?!b;xM4Ir-w=!KqiHqNS14LGQLk&XD3mtsZEUXk!v^eTen`zQe}~~tA?!X zKq#uU3KNslNY}^pGvu;)9y@%R4}a@fRA)EslE4vyFqJl}1eIZ%fk+!X?Bq--`)7=m zF&JUrgLbUECl%SK!SazkNMbUM%hb_*R<|Dq*9) z)oKIZmGty{SHq|$dLaMbouH#tTXv!%ULa|(~G0@+``jIunaYDY3 zqg<{62H*G7si-81Yz9H1H3Em~@*_Slg(!~kgyHn`9H08y510sjUVYo!aUI3v>>?^( zM4N{;Ih~khZUOdRUb!#Y=N;pcb zn9-%Z-=U=`RJL)@#^AUfNfM)DjZ^}Y-nrX>c2=5W9|HtN$d&EG*-gRONr8PXVnte* z)(>c%*v$lTR44!-b{gDf=_N(!EtEc2^hzMmdt`1XTOv2o4a z=K9xME#?=N#J+>4Xw+)FLA>B{+_tR;|-$wpdzRMs((wn?8dpLYC$x zSy);osnn=>c>;^)A&M=^bl;&Pw4#LVTQ=ime8MD2w{wC+Wy#kZ%0Ar}nPO&&UgCwPUDP>h%?S@&T4SaepmO4i27;Q9>u;**r6C=__ zUK+@T0o`34EL6+%j|_s4_>Q2vBSX0vQEh}Nt#9SBVP$+u5D3MQ*$OvYyq$ml;gg)M z1ne7~V#~-{hEFeXW}=SgSjdIOAe2Pvn5>DJ9iN~XghWY9p;Y48+v1M z`t|FXTPSnj&`Dg+LnEj)1D4BW(~-}J(D(5i$a@J0pD2ikO-vky6bc1gDTL!d7(1BQ zfKnm|Ly}mNLnoU?WiM|mXL2%R+XRR>yT@En13vVgYR zMxDGO0s0S)R~mqyfy38LbQBEa7_|0Bb_1>St?n?XpF<8$J~5x(=id(De`4+|%g=bBsI%+SadtBIBp zC%wo9=}lEhn==p_aFz8UxJufBE%gkz>g=S`k;3xmW4kSI9fxRfnXtCZ$Y4JMeSPQ+ z>j{?UF-CCSsx5r>zx^6g>u=)g|NcE**u9TpM}aV%Zp0~a zRci=>kdBT#s|I_}#!#(PnVOtoZf+5T#PeLjIL2`#Ylc^I=JbT6vox9nLBQ%&eT+}c z5=9YGN?g|#2fm-7Sn422G|fhXD2(iSSZhw7nWR)K;5ZKD$tqzKkMO*;LqO zlS0O2*Yi*Fz`ft*h3B5)7vKLOCQl#Znj7BwQ{SuD#9aNmcX6uHqUgCymtzh*`y}zP zy>wrHJH11zh~gM2Z1FFJ^l!)hku-QpQrCj{nHpR69p?>KT})T0$Y58IFW>dg zs53{X{N{V;$Y;25>nh%N+Z$*GEgU78UT*S%zxxI+G#t(u7~=3k6QdkPCziNzIFA&H z;r=21>{ot)FMR#mTzc`v?B9QYtKa-CZh6N$IdJGG@Bg{if{sCX?B4Yv2M?YgTk5n^ z?KHbWr#CQ#w48rw1NMYA$g~hN%1+$dDtV(pORG=5{ox1EOB3{W<+$?l3m7|firp{n z<=oL?;PnL%*y94=F8{H3S6qfj0`9*1ABbX2v3G!KX$@7k6N9jt^tPEg{Y~pvW3pBPL?Msys+;8S6p}=FP<3XtKWZ|cfIyfrVi~kU;4{G73ZIK9@(r< zWpSRqfguj>ZZS1A!J6UKIGG&J9UkY3t6VBU#6m3~8&vq*Z@iDbVvgVY!awokGrQPu z@ujGIk>#T=vAz(~UCKj};7Mb(_R7J{6_{swBHqBQGMKR;C@q!WdOf6fWg|_W{ z0{9Y?v7db_jL12Pq9ZxE|3zw*GFvaZk|)^~nnP30Rmx!iD>FmghL^(v#!9z1UH$_iZ2T`m=Z+AaI&>~;x#96hTMx#ns zS1(e6Qqa*+LOR}x&qzo~90eF7$Yk@xQ47cM@%${UX2oV9WjcxDfM$IW&vo##MOuwA z2nR2dBZ)(r%_d43qA*4%#lfS;TmK)*vi}mtD-FQUz!604C7`Xi;=~3>i9}P!(CvB_ zF$mP+7+*@HgqF6WOfSWFI!ahGkReSgl&m;xNjbxD!lq8ehi|-u(~~pw#5F#6?dv#p zrk|;$3Uy!5?K`~f(k+~sDdQ1w!zJ5!{Mnt%O;53|cO8?Hqm)Wrl*^0MYs>67f15Zx zHqP-gb3FO@Px$$fEjV`gK&TBd;9-mYC@t!9u0zIis5S#6&!!Z2dpx^-l- zIqJ0<9fe#PHA^ih=^bhp0Fu%m?{4xkZ#&w7yOL*w%E|JM( zICEwaAp}E112~SPRSzi?@-!NClyb=U9y&>=*Bb~S$QSYmDXCSfbQX&gI&v&5ED;1D z`FxHb2yLS$Y~$nk9=_+&tk;>FpTqTB%9Sen_U)w=GwEjm%d=Hm>U7_doJWHn!c(P;P|$)?MG^u+Fo7c);daNP83P@9U=F_>3)8 zc@u?5}5&)}K4ROzrX`Y*H@Qd$xCvU&?jZ_;|4v$W;>YVl5uwe_nQZ!;i z(l)c2vy*rU_)6hQV`VwoLb^>lWnU>$5i}Bw7d7~mH(beZPmU-GDCBZ{^=n_{?Qgx6 z5B$o!cpmn6}2hU68kn^dz>#ESdg(J5UT*3FK>Al9Lo3pk!OK zBvM6_l{6`3o7WTqgwbi?pUND-{+#1FC`Y9dAF(n)m$EHCN?x{Iu;rC~E!Okox-Lox zqIB}A((p55Y>M`6x82HL{Mn!K=;J>mYz1uJx}9J6`M0ocWFyU1z-RvDhsS<_iDlrq#ztS_`}h6}NnD_^G|zkA z^M0gAc^O_4bFmY-h#ok_Cec>>!2?@iP ziOFfIt$>bV2Qw3s1VKQ@z%Xn2hPZO|D$bld!PC$0=FW#6;CDaxPPWH0{M!?U=v=>* z{?)4~C{44g$i&nX8I|CB8PVIVxa5)xc;vAs@iSQ*M-fMn-4;n@;Th6OPM50z<+{U1 zKKW-1tsdgt@41t!FTIH6xk(0ld&u}6Imo$qufj+KN%)ta;uM*0blN2Kv~n zi2Vq)1#bxKASN;G{G9arn+_EcW6$^5N|nK`5@TayoOv#>bMah_&+Mp{u3XsGyp#XhYp%5jqb5RKBEZ}JAG2Ae8I+z8!{?u*jB?^*s34GWHW&HBV~V*LP)olF{IXf~S`ttQ2e0s{kmlq+>+X6I9Wv9O*9z3NOpIhc5fAV)6s2TeDR})Q~Bxn;au#?qqP8{QV4?RY` z(Zc(e2Uy$Pf$}qyL(M!Mt%X@OUV0A70WVkN3t#?Ac8$&B7mFyJq=li2CJmo*|QY5f9GoDfDaQds-EmE73B!x|H9Hiy=BlC9HBkoI;_w%y8U^I+veDt&FN z$cdz~zZ1vt*{wkO+Ko=oCRs^6)kfnu){meZmCE4k<3x$o>l-0fXjxhty1Tmg<~P2> z6F+$ZsXT^1IoN|R$mT4o6=FR?1Evtei}T?tm} zf3}zh;aJl&D<)?9ozm^^l&~utW77PRl;C3bwg%Vp7}>mm^Dnx9m-g+ab>I-&cAU>* zZJDn;bqI2+`Rw<8Or}s|V8)`9Ia-EAx2|ZTqvWmlc??ys?{pz_vQHT8?Ppp_t~~#1YUa;oy89BzyBVy zb<1WkJw0ju{;n^J?w)Se4iDkFE>cN)d%IXzsxZG;=D zO`N}F1J_@?mCb`aeD+_z&r_z<|Mv&(U{!B7i-uLcX()&c0PFjh`V`u;iLnio|uY1&W;|`m!#Q2lvseS2_2hOY!nWnu%ud6s2n=iY$h)>VXRrI)R=F!Xq-98-~YzDx#NZ__}KsTQA!_UtsVCLad-$=B-f`c3|Nm8M|GAD=8i1dH zBhXsO_IOFy^gCch2bdVk4|bF!O01N@l`o%S+DU>#D%mhLkjn<|*cGBNhOCmrnGEC0 zO@8UBZPe;@#^%d3!-(T&Cb?+S2v5IsoEtCQP9c-wuO8it7Lu+)79j?hKXr&o%TQ@V zOwFD#U_>sLXL@d#Q!`a++NY51AVyeYAQt%-rqhkA5IBya8f#AMd4Xi~2&-;-JK0u)A*HJE(zAClg(x^2BIWNgTUHy7fW)9;uzO=SzK7O%>14nv`$F0P2|mHJe2D) zF)>9HM)=t**<6n0(3m2#PCE1}VB;Ys+pTi%F4A{~cfHp9v3 z1!i9wBWzYt(yp7kq)U%fBrQw2kW!|T(X<>A)<~zVkhf&MeVWDiJPBBNZzw_EZT^BqTD?6mmH* zhS6$(sD>0X8KS9C-hcB|y#K9lA~tYxa*ElOVQ^>=BW;ytF?uS!St?9w{#QGP6 zKnY2L#bO$4qI6bRgsw&)Dzn^r!766Q&rrJj0xrMuI==j`-(YcKlxwfLn(4VYUVL$H zI{CNnnK3E0bHyBMY}P{heQ*CanQkcBaw^fTJGFiOLQ2{$HJi&}F`;L5eIiX3vL`_l zStFh6I5^7c)>~nO6gFVXXhR%F#EB-C&8*;M!D{fU)jDw$;rm`{Zcn`nsn#Fb;aqB^ zK~X}bufeo0O_oU3M#-kv9b-~AA+|Y^!Zwj{93dTr!b#1;5C#FR=dZ{l&KBdW(1ct^ zv9!F*?YG^+uYTx*Jo@;L*s*mDS6y`tFYZ6V(o&ty-d?`{!eNfj)vbI2VVe?}dOi}J zZXLwSvKOrJT?s*KY!j$tJ6lEAfH$KN7<_5H8_g)j07@Fd)I8rV(nz;SV3Uziij$*f zII#aE&fT(wtvj}JWdBPX+qai|A#XP$MxdofwORuKjf%t->g;ttZ6YOxjO$XFon!pO zDYS49VT;ftIGGHQkwij}G#ad0GfZ!HC*S?a^CbBqgfYMH$#ttPz`>VH7z^Qhl0-{RpFTytP+)Pn%+NVLjWDLx2pH~w9ox30pHc!S zv~Kb0D=ra*T#mzs4~pL2PKMX6MM}Za!Zd?}gT$UkSE+-Zt|Czw@R>jPQ}N*sy`Rl% z`uN4S|NP45zV+PgJoM}?4%8}i4zFeO*l`XXKgPC=8`-|)JpSfy{#+nEe(N_r!NEgE z*t`EA#bPPF$60Afl4yoEZQJmm)_wn@8k8t$ZQ4q>( zS-Xnm#1|K=>*cQZ-;733Z8Q;%LuVn!@!1OB*m;Dpefx-ORkmJy8A+~0D@m9?afI^e zlWaKee4M^Ps?ES=>X=^b-akrb!DFbu zg8-MPm4Gk=VL}oG6g#pwj&H{=!cwJd`<+3lJVHPe1USkN;-+Adm_`udC`ras_#PNj zpj7I$1B9SSgpcdz$@mWArzf81=<2)!{wm>>$g(z+6f`4)Bc&xIq*5lG zPEVw;@*$fJYA`Yl5lbiIQ5;i??dnm5RsP`jK1X-=;L7`Z>f~-p9o_u>KiJ7))heY@kxV8-tJPv* zsf_0;;v}&}S{fvSF)S@Dll3GI|L{J3^uv32{<)oe;8%W~YNN*bk?lYAz1n~L7^m+3 z4o%_Wcvfo}D|aQ_&4$vXIN0>N)i#LgmBO_RlmsPAiV-y&*uS4o{mJL~>?c2hBH_jx zuc6fn2%2>kYfb*}Z@+iT z{dW>Y5mO6GeCjX0geY{-TP&tVI=M1Mm&OnwX(KIViq$lvNWUa4ZqvUv)P^K%5gH&0 z5mCgd)$7@?VJoM{#(4DMhbb>E;dwr5*REl?UdQvimE>HVeoxy5>Xl->y`9sE4U{ql zV-j8-q@`cB;WEY`lC#t2bhK_|MM|OLWJM}u(&FFqefs;l(Me(x!4!mPm#D z99LRhG*YD*;P>TEp+SE>RTO0zSpknp9iU-VPXJ@LVrF zClit+wunxttV~LzfnrLg$)ziH*_G@AV@S6fa)mt9#);Z_hZ+?KSL@7G8!Xo<1WDRB8BL5tVFw}7^T5~~5hXNE+QbP+k;Q4Y zgD@*NR&A_7w5l~x9FYe1;z}p=e^~E^k%~mexaoG*An;t5k&WvS0*)R!!p3tqvvJ!t z&YTz}31S>qp_67xZ?n`AV+>(zk+zoDWKgbSoRu7n*UZk^>qi=W}r<;n5N{BE7+OWJdO=nj>pjcd*Vrud<-Q8VODiwx? z2HA1Jc_vN-I!?r<%da#OQxnh(MXg$;P$+QT_AN||Px6}|{R9_Yyn`JVUcg1?Uk<>* z!+SV2IZwE%hfFR@PnivCt`k3a z@G?-p|9Yv zT&|EP4^P>g9HR}103!uTSqWK`SRxP@Onaz+A+R?(-1LOBSv+>NC`@V|PVZMinBXZ% zYz%R#2#{@aPkJ>G0{S}&gel-5iW6jd4foUHK>>Y*4B3oNtsbyYs}Z44={YHdz$6io z)}UO31EW&wiIXQz;kpi81FQJq!%vaRW*Ht_!~9}}dmes~O`A5*H`q^tB5Bn? z2prc(%r;Zqzq0Zs9nq{-34@l+Ai_$yd?jf$TPR0z&brlZJ{EX&45*d zfjNKsxuU1Ln}x+CYK`cKl<_}&=vP1WmqLj6f3qC>FLk`q0Q?LbT5BC88q!cMMS^q` zZo6nQV5Aie1c^0dO6;mRNsU4;!+;~O#$XNPr48qDQwdN@Yur*dfBKUnM2{Unc^QuF zn?R6Z@3SZIJ)c|t>U%W9h_2otPPR0^{Kb2D@2fWRd%yh=M#tX5;=%&o`_WH0eR33p zV8_*cY#v#|;NSpPz4~&N1vDc~K5K7e2{vEAp77Qz*VEZatI$EgQ3PRv0|dst7N;r`r5PVTO=Woo&(AVCc7|3fAd|^r z3lOuC$lBI9NMWc}YUFcSq*CMxdGZ|v;xJ@sX_-p3j_3Pm9TK*htQ{UC3Ia-{BE?b% zWy8`v+Q>v z2pSD`@7>2-HRR;@4FCGAf2Y*dXGX_og;I){=}89q`}po7&+^cH4>5So#+2QjPH>H# zMCnww?#Pwfh5i0Wfk|{)7}@WrN$XNa7!slImExfvKg;#6zLeW;zKNyE61iNSW;5V3 zpZ_}^+jW%HtA{Di&99(s!#JJTJB}sigds-St&oc*3?r5+Rm!tx_|;#yl@Gr24ja5B zC4c+1@A1;nF^b(ij8D#ClnZeLShG1vf=cYQ-bjTo_Qo5h=Yul#H7a4K$1&Q=ux_Xy zu;-KVvi$g&=gAOLE-%qP*vFYu$C#a(Voj#0cL3VGiAYVxvEAUstjK8W3)5(0=`gwo_M= zCMfIF7a>I&*3?EY3xQ)|+E(%eL+~=+gA@XTBnbZ(d+!-;*>TqS{;F!Nwe!ibyHDrb z%F&W6C&`vAY#aa^48{QllZ?m1_+h{^=FTt|-@$`D4Do^)24ir<2{|d)Ru0{*mRf4H zI)~GJa@c3*6{_lfsM`COxnbab^7D+=m+t3;z1LZLt*ZC^zyHvInHlz8bu~c{a`x02 zHg4O>rY%#wjOnn8)!yKD$arKQiP;OUQJUGqIy!rJ6LBv|4N~_(XTuC`{exvuWcb&mBKy=jJYnxBuAN7#toIOUsKi8%>Tr_dHdLFh4Gt4n&G{2A z(44u%*8Nuzj!m-GiV1^&xz!p+o_vbI9s8IXAEooPlnKrt{_;l;UWPRzHtY4;v(xcOS1JMugi&YWh;BI#1z3iQ(JtX5*_Rags6G zUuLjWqGM9Nce%m+$6q7~bA;9s;BGQ!>E{-tykF${@}Z}aCinmVAOJ~3K~yW!tZQtP zrvk*<34$}9ek_b7=efD55G2N>9p|k<2uqr!2%JNS%H??M@q@(Q`=0&g{SS$iT8G-| zD!F`~AP9Nooj*#YTxQRnod^|>k-E)WYsY^M6e>=r)f)^C^*KrfmQtlcu~cGqZjpMu zL7HYLznHDIJDfRlp7DuMwr}4;u~5L`IMu~Mjx^P@+ieQPGMRSHC!KbixNgXW0l9pH z(HR058g$l{ahg)C)_Q)?NvA_1CB;I4%d?AIcg-z;Wng@gd+vRNOO(@`TZRvB-W&UGZ9z?`cn6;kq_ozLN&Ln!gbK@;n>He+4oul=B`8vxS70bV(wU#J~$kNPfcrv7tgrTE321=og z>7|;xTHLRL(xQ!`)oOG5UAOTcfBU0+>)v}gpN`R1P zYZ&S4=hzF!oM5w1B3Y}E-#A5_rWh2&BiQ$0({_6WrleFr*?!Z=Fv40yo zKKwooy>OaKOI5DD?gn;l7zOJ>8s{%xA}E%aZE6~=4x{B9S8N_a_|K*tH>8h z2$AyG6HjpH>F2oft~b%BuTd$NDMW%+eO1&}SH#H^FED-i5~E`qxc<6p*|1^EKJ&~m zVXdXnXt86*Hl99w1gz$sZ+x4%*-Kn=^DROuMQ833=NmP)6b)hAq}E*F;<=NAxju3C z8}8u2habo2j3iD;GflA&lFPX)mwLU=$A9_Mr)g6r)q-!| z`yB$&!0Lo&Ph4VQ&7zHFa&(x-zW)ICEFS08x8DSv7RqECxat58&bBcIE}uO~W9AZD zuDF_DWP(^7Q2+H+ICmcZ6G{BH_eFnJ@eUFEmvi zQPtg-1rQG50O8KjZ-_!V5vK?OA2Q=89VSi5=khcp64w0jbOL=iNvFHpRpSiJ`sflo?iqnEnZV z{bPU1YITi&@zZakP^|E8fBj$bi|<|H(_i`;-}>HT%+Jgd7D`0<0#-PRi11XGxYeTF zX|ZE+kbnKFAL7nez8on7G=^rU%}4*>Q~dQmJjld`jU))-PC_7Dk!EmiMKaCY-PH|} zk^-sSW|%9LNK+U1Mw(I_9AN+Mog8}Z1&XC2r9y$3OP5Jk7y0P#e2nqFJSWdiQ*X3c zn4d@4j8A^@&nTA4?&?T~?5iN?rQjN$Z0jf?Vts07*M-O~eb;Z$*17LEq|f>GyQadu zMt35${x#{u=vve1#9%E$!~LwTtobHMGBDWhox+?mO}*Y^WORtFTQ`v;i9?$`#U=~_ z;v}WfXu7X^Y81YRx7HWR9(BaO2S6Bw&i1rh{6lXF(F+)~ z3w)xnT^Ih-&81kMj`a2S@!7xo0{7p0FIko`&{yE{g_}8Y^hFkHG5r%$G;>49C{HFM zjL|MgP`Fpr7Le{el`#ZiW$s z2tO6d(u|Eecd~iMHjW>CmfZ*TgVC%lF4L*j5P`e4I&;ERVR6$7tKBoFo&LaSzzo7V zN@s%MNM^_viWCBgND|`Z1`Ao0E?m;;N|;qKf31Lr*jN`dbL3 zWwa7-?SbntX-rW`%H@Qxm+aT)Uwu2DJj9y^f?wUoMZdm1E`^Ks_mp_y_p$< zk&@k`0}d#Yf_mmHfBn&&gms(obuV7KzE1d}J~fu0`)!ZzNk5gde!47WH^akyU)y!+ zPo)r|qKLIt2bsET4Bf^3Em%((PLm7~M2y|^YRFPT8IWq1W}*SqY|%R(}YwT(sl>kiOH7=$XpI-G(j#R%0}$vePjJjiBA-gdzxq!V1WILU82m&zykMSs)s_?hq7bu0e=> z3aP~x+&IL_SV*iPlG3{qSQ0;y43$E7FEq|GHh^S7VpeLw%J{O<34l5c$H0dl#>=?k)qQmH_@osenGU@=D;7bq7C z%+D{dxVXy1W-njnM_%_DqWV0)@TNQ1I<<*Q zGcy>g`23f@M6J4N-}&~R6vs}SuJxL?OU3cRLEk`Vk97W^kh_a&THgd| zKfZT?cbUt>P^uSjl<5p56;Tv8x(>z(9lJbc;qp+rh+%bgh4=jIPw=t-_%ZIi_iGqy zc-8H%RG+h0jSr7&8#B1bv# zw$TO|IlEqyxx(8TgE0Qivu=_igNR552qhibsstKIsBi^K7;)*;DaN*LVe^iiy!iYJ z?A^VKf>I=@OW2lDAi62f*5$w&PqkBBT9s5-FFr6a)|f-=$+)FfJ?KBwpi*HH{bLMh6g@Pwbr1ouhN@e zy2+L0y6diCq(8^>`Ey)2`yvlM`jkC=aYi(w0kk#*fg)0tFvwxGp_R00#vQU|4Uu%{ zw3;?zU1p?)q;_|-ePrD!?^mK8?=jaHpf|l+da)liA#Tn+F{65k3uck0C zLZEfekiZC+a-3RAVnJ9zC08I0Bj+0ECs7J~7KXPs7K&yZlM6%4_I;?;er&r%%4R3@ z&otZm^1Su->zSRo%-+3wc=Fljc=ucG=E#XN9DMpYe)0{kKn04=fA47u!tlYLc?(ZI zcbrds{kvpAM8kR-WSXI+TThSyQNBP$W`xZufnRr}RD@wf&SngbmWt<|KJ-79S1%p^ zAID1#zz@TrAfL|xEkqzu!uRQJ7Dyl*a&GN9rN9_VUP@vw?u(5Ra|V9o9r&?!qBW6} zy#!&c4WV+hA}iJ>1QBk65F%-4P2`J>*jo30ToF?6uP+4T0jmuK=@t`%^E%eJg{)sW zFKmmYV=bW)uE{Viy1biKY=xk0-T63F)TL=!+#(m@1HqtY<(E^gc@aiCij;+7E=MEH zICJhaVJ_tS#Y@DUgte7f&R;msk>^kIxi5a1W5-YVgk3{saEqBSuD=igVH8p<7TCCP zlCggRP?5-Qrr)_Nr6WIwRZH6 zE&?c|n|k4Y#nDqhDM^+YE?l@wKA-dNY5e^t2?FImTPISk)#@ZkN)$y1;arfwr3-ft zYYZw3L3wVnbhH-fMXge)o_3@s1`%B}+;L)zH3&a_=u*kF(Y>!(Y|p~fT@#Hl3L$iF zJ#zy^>1j9avs6-2uJrTm?|hHtx%4fgw0LrH9-o1~gkVh0sgo7jWOR&DV za+(H>OD%TqBfPVb1~R1A-8g}zgIKyEOT5La=;^AU8}#LP=8p64Xh0b4rcxG=j)Jv8 zT4pZK5GM&!TefiW#0fTU-9lK*BXKm%C~!Z!ZoevgDB*hk2Ev_NhC&MGNR*QXX|3ac z3zs~twWYsQ;?`>q@QJ_tG%uW=VfW7MRGTfZhOL_>*tKPfR$>_KEAZ7X{=LN-@jD;= zO)g))%$Gm+XJ{kH63e^Z^=>A{$9U+mhuOMeGch?pvbea!^71k{o45J?VKG&#SRn(k zTCEZ(!=}kGO2qj`ui)q`HipV{lEA@aeN8B@$CmF2a>f~hkU-DT$rc7R1j+`F)D~ynw`OR z8ca+~ik-Xma{SCZ`9RRFRXKCy5Q7^w6HRWW7H1x97yLlaOg@mk>=Y~9o?I@3^z~J! zw>qrWTkhWRYiBnwvui^q{Ink9_S?|kf8c5WEnH(ELbv9k-8vY0y`1rYTAFF*V?#4v zq27uaDWwdDA&J-Is2`vj3E}TGV+j1_ZtOZKFmaY@d{%?tVt2M@CRm(QMb< z-)$_VqTsD>d>vo=*8SXi%gZ=h&)Bhh56_*QW_;6TZoB1XCPs$%+LJHPmka6Wj2o}J znp1Vn>AGen4QOVTfxL5{N;8eXlFQ{8&`sj=&!fT+g+S_*FbI)ZLNSR4|DOx2myZ9p z^i^SA^1+r=C(Jd1&EDt>6thLy=@E{SNJF1 z(#{ET-G-JJSKRxFpbsFiR6<1~bz}5MN;=w*_egx|`L%&@8(5sV1ldS-$KXy^kXg^| zH!kEPz&ZP9Yg{ObaPOzAYXrK8sXGtn#Nh!Fa^9=BV-1BsxJiHzNG!rSI#6ChF`s8G z2>Hs_@1=O(!}fuP9u=#LON4p;GjsO0af6K_GE!=p+HPq{kp2JD2V#`L$pE z006@qwsPd?36kXNqB|uBmEgK-uB2geY#JLSk^$BlLI7jBR~Z>ZWZru{2&8i&K{{T( z5LlD>^T}Kxn9q~qXj@8#-qFTjvXo3nw(s7>+**~N`<*}Hnr)kS?aOcE$L@LsLwz}N zQI6qa`TutBTOcLl{9K){e)n;{@!;dkFRoJPA7aPG3N{EF5^f9xAp&QQD7@vBYg)7` zuC+r^wRMykAq8=2kb!cDkq}hyVR8tnwHock1qy`%+8T!X%3PjVgg~)v`xZ9TYg{~g zmUgQ_eXWYsu8~7XOqTX2FhSsT4c0nAn{j#))8)3~ih(Y&Mz_4PINFl&jTnyZgSF_) z{caGb-p>Z1B1<)47@(9Zl#Le-hM}W~b^XDTBqg8EF+S$#2uTvVluke? zoHZ_9jN27|TkD**jQ0NiQh;$h|4es7!YpZ;lF#Mn>npRgvSfi0a z;4NGgR$9~#!nW3uX-$eCGbuav?B>O@7ofVzw!M2fb>aj?6@W3W88gOxjzao$Vndc` z!cY+^$P5UjP{K9lHp~2a?d(A@5avSCG$ZaL2r^dJYOKsmvwCqF9miapTV}Yw%!aWM zw6@ebF^@m>q;1ufg%CN~ofxe({UaN&S<|vy7sXQ1CE@0ZVr72Xmd1AqEhM>OiN3x* zo<4j?9DVLMx88o6c;d+?dFRjkH0MsALPjNW#WGQVSXrwxckl?6LV?ROGl(D*T4(eR z1cafW-RUqkJ_b@!uh-eWbrVAaed5p;zJ!?A#^Cnd)Y6!Tj~u7f?17_8$9|B-Jz;Ey|T5&323xi;QmAWUJpkESlxb>^yKa@0l3q(09MXYhU{s z-t)8n0)Uyh3w-8FU!~J(vUA@)ZhqYxXmwi5&acvH$D);4rca%qJUqhazAIRXEuAza zRFanVoxKOf;x2F^oQ5rvkR@#{JbFKJ<1WUwZlm3foePj}{*~X^g};Ra4xX3ZYSz%D zpm}|haK*kK+>vPC@LN~>8v&`-l!nG=UGpj;olp*x>)W+M`?bH^rMa zw?0K!n#PhB&IBOE5(bfD8wdd=qZCG@T2pPcX=RdDyF;;1AWl+FT)501efkT$_bqqv z`R_c$;_4bFr)Ll{M1&FZD>cd`3qib*4cXr@Xdg;7YlIC7Q&+wvC)LSfQgMEREkho+G$2UP=r!ArvTff==8V>ZgI1g zcGg9~x_;X3wWW3MrQ>N2}SUudnO_j$r%tDJqo`)0gHblnP{-L;Qj;Ak&7yfqpMQ z4M;O5noKiInrXDwesnA7wA&PmMba!|rCMWjsE>RUI9-Nusi=bkeJm`l5Co1&l%(3( zPU;M0Vt)5`f14MNA7^@YfvfzO{f<}P#;)C0p^Zjony=sYJzjj^Fs1&X9-rJ=i@_j6 zNww8sU}BtIyS71^Iu3CcsZ|P#a*5L2{lU`XB|CJ|A>yHMUkg1&E7gW}z0TJU9_QGF zIY?syA=oh7N4Z#_E1ON@gvGTc%?uWrF{||^m5GgP*s+U9DKbw(k~pzj+D(LZ=8n#` z5jTF9p3^O)LinOuVz8cv9$?-1`BYjh1Y1<#dEW+8Tju9};tsZKoZ#fyGpw%EiR*Rt z?%K+G-t}Idd-f0yKJpZ)N7@}d#Ur*^>hu8K`V#1I`>oYIDoxP!>BV^cf}>Lj4PofS z#acTNuS4s7VAT&47(z+HAoPf~aMT&Q-arFbA&7E0hK7g8k_4p${8_J&IJY*O8|aL>#@e}(<~_Y>tL7tUYc#L3f)kBu`@=_9q8 zXAd6Y@>-iHmq&yl2@;zoMAkhEu@w~hitO38g=VHXb>^H$Tmz(^BD&AZdRmfiE!=UZ><6YJtE?fw7uMDTGwS#&GiVS@!JT%fjLktMl{h+Ovnn^V6>AQ;M8$ z9PA(p=``DjKoORTUKnkNB1w?TIg4na+~*x92v5!Iv}1C)kT9|oN@dnoR{6&L5ApjS z{RpR~FY_C}`$@J=j8g9;OwTPcv26#%LXo|@HgMw5_qjAP!~EhRQVIqJhOAJNgvAE6 zW`~v4HBOv3MR{n%mL`N)YqYp>?=JT5+$!i)saDsp#_;45hxmtk?xR+#^W6u&L0>V% zWF7LQA?~{KP7IRO@)Y_97@ipAuDkCh z4hnqxkwaqs;t~_b&al=_F&&LbQyzWv39h^TW^%baho625Q~*M;l3LmX96WZC%a{KQ zBLd!W#mguSk1;q>q@Gxsos?WCNxDvSU7DO&pJZvA1+EGdEA^Div-3o`A%>>5_Bj8_ zKhxdP-*nek_(wVb;rIQ_I8zKQB|o=`GrA_ytIUY1Q{ZPLfM2I;rKtd_WED_c&P#SAvoG`>}{`{Ymd${(8l@hT6$wf zSJbA*NFNCxZ;L*U_^to&pY3<!Lu6^{IM+VuvREuqtFBThMEvG&{%_oW@8@{@;4}QvFMp7} zz5yat_(%8E1CKpUr`@7QJ;!e_N>OWf7~V2P|G)rGJoG5GlhBT1z+$EB=?<{QkBOz< zhzyRk?O(L(Vk0FIm++YRW-vhTWZXd_-H+-NVU16wcEv1KA(ZoimVvWzbXcbZ;ph<( z?{n?Z^GJY|!X>VH3X=>%e_wjhT6cOOY_C8y#=4*z>yTZy1G*H~V%p|c9=n&?$|9{! z!pOu%nzb6U(--(}pZaS?M@O9Jeh{KF?~Y_FLV8p#46(+n3uLh%yx0$VNw~s8dJZf$ z7~>pq;yA_vQ5f`!iQX>lU&CasK^W-oqh4z`pMHP+yM>1npr#BC4$!POS*@;-%Z042 z))*fjVawD8&YZbGrxO!K&R9U|^`u~HEK=H@khdGs)%{-AGE_-Lsgh@5ahWtpkV;YR z>!V(8kZG3!th3CCmxaIcj76gfWYE(As3`C{NJk6m3L(2qrnQD#KF?E6JjqAr=a`POR-cU!TGrhoG@Pq;q+NjAf*K>$mR1~ zJb#ggAAOt~ue+N0xj7c5r`fP&6N?KASPL-%D?&0UkQL?Dc_ooqMqu6a$^i!oojJ;t zQ2|OwG9d_yitGpWgUawIkG*h~cmKPOleF7362rgw_@5whMTYwOD1`y1&z(cO;%ZSG z+s$L&{ycZS;T_}xffNWSB<)T@vF~rF3=VMn%Wty%rAbkW4UJf{cd(xgixEUeqjbX6sSW=`3;P>{*UJ{~{YUY-Inw-3$!& z(`Yogc;PZ*Q6GXs3{~(28k-2J%bIUabaz!?78|2LVD$C~<_^5rJx}BdMzh4O`6bnRYO1qPwtTPo!{qkd> z$1YgQGN#G}h6~P~dbQah@j97Mx(a1DU!a;)_~z=J3Ug?FxX5 zkD_-+VhoXxzSwtRH?c9~l_E37@db_J8g|hG=wcFBv+9i5^UXC#>>Hr~%2;eXH4 z%8d77b`B@_g59|f`Nc#yZ9-xla_g5W-`Ts7f2x0AA;lF=Nf!mNZV?RpVyUg6SSV6$ z)G2S=jtoQ2&Mx!xbI;kN(?KZ3GtWFN@?pTIKK=JB&d>1QKl52mo;)oIg@O}`$`BO< zv^y~ZOR1Qn-D)#DJjm3h4P2VO#HGt~EG<_V8y}^*)*v&6D2#|AsMnilVvm3A{~c*tzKhf zY7+xPL!3N(hzN-&m$>29o4^;L2R^_fk3Y`)f91nY z;ORxK2#dAd;=F4&+9k5N0$K=XEvqx19e}$S!jZelv>^!nbJs0=J)NjKmhU3xU20F{ ztuA}ds`Aa3@jnZ+TWv;0hv~#I)>`uUfXlP41LLA+Hi)V%qHv?I2?R)mL-%Z7=8WlaF)lfqg72 zEOPPudA9A^x$Y>`yZEk|6+${;r=P}2x}NQh_9HzYW2N+Z0eZoA(n7OQr=>OJN;?vc*{jueg?_T$!>6QI``D zuAE`_-m5S=BM1uwLBN9#f1gq@Z};!pBkuXe1LDRTujMCx{73DVzw!<72Y>h%TzlP> zv>I#n;-wj8X6D3`PaWatb6Y5ticDX;M7~&L!{$vWlQJ+kXvao|#8Z!cm+Nl06@maG zEQKgyd3DuINyo=ni9>$rzum)+U$c#|N)e+1mK%bCDDbYkUdvY>ImGwxdz@mq!o@G# z$CJ-IPqcYABYUo3Y;=f&&!6Olg9o|&#w&Qm8{WX4$wB*b?|PT`+CAUk@UfHJuzwFb z1|MNb$B001{@gisZrjS#)JB@;PY@d?SXOAapczO!1y)#ki(KjvI%_Slc9z6_IMaf} z0~y9!bay9Y!mjuGx~qr5Es#>Uq+o3wIHqu)b$7kR@3E;r1!G*cMP7)Wh*ybqnonZg zWHcuvLP?g79ie6=(Z=l*m2WtGU15Q=-6G3U1`0*e`YQ9QDI!bg5R#<{g~}jdu86gU z0LgIQAljrnd1;OQas?R)zJIX>Qqey!!m}$Ko?cw0n2V4>fz$PbNEyPwkPic)>L69pcr$c)>t0wD;zkH5hQp;BWh1d2kaT*#LYEVdHI%k}go ztV1M}6yDO!y+%%~gU#9)WG0_;0Wz*OO(sq;bwp|R5jIi+hBYgF1O%W(XtKH&} zhaTqSsk0v%O;aaA_7oB!1Ul0MLCDJT3jKX$_U_xwv12dN zY_>Rm;WA;qKom-pgk~pYV4%X}jR(Wz9K-1cFW{arTWk(X*10Fbte_ z!t=UkXBQY8>?g|{%>rvF6bqzjMihp$+A%?(D3?pbM)8a9|5X4X3PS|Z^W6WyBW&I{ z4%X7?v{_rNF}qSHBBNHTx=44SNQ`Flwk-^fjPk}D(r?hX`@kMy>T;Ape#L0M1(*piA_=$;3nMNno5PuT>gOwL#%Mu zHS-pk(%T~%eB-AAlEfk9X__I0B=u7%Y4LOvPh+vJxl}ljIlbmt^iXE$J5y`HG^+gj z^T#L^OI$d2nr5p*z1~2_9Ugl43BoWUP>Ot{Xt$lKjWNbwE7nKry$0Pi+?m#NWwG5N z-?E-~tEBLOTB4^L@FZ_9u$Ep#u6jVPC6a$E6DbVyW|doK(cYXuy3bo`%a+X>AXJ<@`YijdxrXa+xsAh*KEl-p_L3RPg^QO_-C#bSM69I5 zYK@VSEYs8)4TdUZn(Yo!z-WJ&wN{74dW$Gj4D?kT{lV`Uoy-#GlviE3i!<}foSs=g zC`nwc(q3M|*0=NK+uy}+y!XdxXebVh@TQxuASjlpH|jJmUmy^ciLKj_X`7r$XA`&Mo}GJ&*80txcHA zBLvRAJP3PJwEl9Qw3273=ECmAhbjo5lNqdmVlH&Rp>dYD_0%{}2MgMGQw2$CH6a2K zM96&62l#1FPUN3cwqmUfUP}M{rynmh06z>z8YA#CJ6{C%e5`%v-sJ&yk^L?Y-`cJ| zz>S}kaM9qxf4}>Cfs{QlQMbbf*H}bdT8~HbrSRizAy}%_X_rPw2F7W(Iut|Iqm*>4 zEB+;Tp0&3o!_vxZ4;iVaF0#BW6wAk-!yJE-(YxM3kSo(kQ({jSaeo(NndedaqB7|s zp$3F>6qcY^q}^(f#xZ#bk++s(Wu7C=VZJd>85MWKpnKS1Z85v@7Vw5;en4VccDn%4Uv^p_arrEGz z+}YUyV-uq+E-f=WJjBA{DpBMRVx?qHe4aGTcI zkP?uD!h5&-rc8SzDzomMlpeWvADAFB9=#L}^$wJv+Q|^sFj>f>Js;o7$RSl2iXz1# zy?|XZSj=(y`J*(NZ8mM%K;XmidRhdnktPEvFm6VHkb&DctnO{hUA8t-dMiug0C_72 z8%w{ev##+6<&Ym9bBBgzzZ*&AoEiL=Q89r`7ZJg>qS1o zSxVaOdHSN(b>6mndEDVg{6FZ24^AYg-A<3T5K2iD2E<81zfx@7vWc151*DV|^Eq10 zmZSCr0Z|mOvQkAUNuf}5v_g*vT5Gv{c^)Yxxm@HX4iYlY$yX{shJmLnNrEUOP=TZM zX;0HZ^n|?UFV0XY7yYvl`UGt2#m#Puu{~;yb0SL8ln^&@u*M|@OF!il)(fj~)W%x9 z&g<`b4IlWWU*>xceV2iO0bcd$SKA|pkBC+)raUmf;ma!=n_ljv_Kt1d>M4Yd-XrmL ztuk=;XA(PqeHr*>%yGk!PT(trWn;U;GqY8)hYxf5{50j9Vr+bzomU({_tsjm-Y{EB z5JnV>MW*K#xOna?Lqo$n`{0Az@XFh{^_91C`0=OMFgZ$JUkU9Ux3qQWzOW#o5FsT+ zA$aSZxAXA9XL#GIZ(*=fez7(LSd37-|Ht3J zXYYHAxs_)b8?3@nJ%j(Fm^lZ3?zkxi*bgB)MVsFV{X58S|}iD9-} zc@3?lIU%jZq#btc*vy8l+c05)=T1#?@X+(LwIa5Ncy)S79Iy71hzh1ceEet{j`1vdxZJZvd z({4H-KnU^*f*|h$6D>*Far?J5NF%V)yZ%T?TLUsA-#6%7f&5w$;`4QIbXp6fSd?*u z&dMEcBN0&08P-3qLI|u*u}Q+lN|{^tOmY158E)CPol~7!56h!ci3Y;xzi(jc*dG_wSO1nKC$N?vfVP{N7hGa+c#)-Zb}hJXsN`adhVUOL?IQUmZqaEK@`Qscy) znbIHwjJ2db=`T`>T9#7q?krvYy|tDMOHMgEP-_KQ7ZJrN{e4e?#Zi9(-&ACNY#2$= zTO3m3vH-xj^au-uKoRfU4=Nxhg{LH$UeYM6YXLI921;BJB!%;sSGaT5SxPf1VKyBg z>u81o=VH=52Z^&0m3YmAZ+yDna~DgHnC^S|EP+5dx`|R~DHtCc;=q9$0H`-t80gR0 z>#w^>eDV_?=ffZVE!yqh;(>>rpi(YT$OX>7+56%LDj?OG{{B9OM}}xMTS%qI=krXC zk5F%?G&?C-<}wmG?U>QgVT#2fE2~v%YjuW4hMW(%F}-v~tuyk40%?+hg=VXTl8P+T zY}quy>dFfFTu8IgqSY8&4QUQg0gw~o?tIf8lN#5}jKTSSo7#Sbooj>(< zI_(CfQklN~0sb%c-aE>&>#pb?-U*?DPBmzR43It=0m2_Fv@1V`mAvdWqu}NT1n-1;#Ip;d?$|rNV|C zJ2<*;FPRsy^Nu@d2YH%lW|O0Z)sSenjxw#8Uz&E=>a`enq;3+PD62!sNlP^gWT!BK zwl<8-)zGy%x3BG`k_$Q8g8traT5(FP*&cZ##; zFY?^p=V{mL^mJEPw{DFc()uCBSb=Sp#sEu2vUZ8F9dx8)LmGy`QbPcCBG;h^b=n3C zTsX9((*#I&54*xRFiz$xtqA_&g%OJ+I1#Sp;Y)lcAU2NjCxoQcZW9IptybI8&M;&u zL&$(MO_n(KV9^6@G+CP3d<|uD4?5|*oe&}~u!w~LiiMnQOhtz8FXs>}Q5=+AGt!fe z$|MMbkd6ybrmPPbu8Hh4O1`u6^gN%@(J`KXVISiYlN>*Gf>Wo?2%e0EX5asyRX{9{=>()VxWhOEBg6d8guWByI9jx;Evs!IB@VVZ46R+)kQFdbz3(R92-Ft zyI4pvViA%^Nji3x`q|U0+`NshwVTMg7T9?G)x7)GYx&gQ{7Rc3bV zGAH&tMO2jZb(Kwdu*;%H+6t;CYq2m%+?b&tsLOD-gh5ge&GbqU7W)& zmT7B9gkj6Zb+j@o;7_!s5Ls);TX$`yoR9e1#}4ox?!AMaQjxa8hJA?$uSYUC*hfnV zCaQHlxAzza&W|#C<^&(S_g3C?>+2Yut`Y_-7#W}BPrmjjtsqaSr7#EynSZpg6T8T{-SJpYt2%MF)SaRmlPN-YUG(9HfGw;2fc9L@T+rDBl_ zle7HA(6WF0H7-Mb2I;4+8YjU0>Fwk~RL0w@;$CEg5#h%95eZulXP>7`f z5nnFTA%uX2^UW^}tt1;5Chz;U!4cL~Kz2l?ouYx|qTkUiEj+5Ubu+-a7AWD9C`}-3 z@i-rAE{;uM{DVCB;P;rCouhwnh_C$fcR70W7`+2u8g||6ml#qEIK~2^H^7g zG)ZZBws;G|F0``Z&Ll~YtpuH>NG$Jgd}4}XA!1=+ky^cp5rWgF&Lcfb@j*Ih-&j|n z!1wU{0MFRZRR|;6?G}};vP%h$@uZ+qE>kHl(rPE<^Eq26r5RB!VtRg&-}vyaQE#?* z@!&DO@!+GZUAu9y2A#Gsf=QjBMg1~T%JwaxAD@x zeWYHFD{pxN)0xL~wMyV7u{mE-a|KZ=(+*MUl&ylulZ?zXC`BQ~Fk~^c$ZII2vyfdD zumw^Q`T=Pc^Pk@SdWuoNoBs3Pb4h8sS6zWutk6s{W*UZzwK};d;@aUJCXOHG@}ZZx z<<2{pnVaXCR}PVnA{$XJBxuXC?@%y0?l_(G?F(DHCYcqTc6jJv$MHoP0^i4P*ZJ@N z<0$odgZYMH*N&}Bj9zARIMks<=_SNbWeO2We9sDYJ4XklXf<0)1-#PQ+Jw4uty61p zY4Zc@)W4$v=wu8SW5c>S3CW#iqH_we&6~LKy4^hR z&4+mQ2M6dM8lqk5XD; z!o=tB^DnS^`*v3J^;qGq))!*#d3o(mT)GJWnG6Q@rxylE3*7%?+BMZ31h z+O1oeo0_4%P@@sYoO<~c*6y%e|3Y^US)9_Bj|ln)sBE~BMHx~a);xA`p3Q3}`Gb%C zD!=#n2RJ)1Ppj5M%*>KiXE-}L#+mac+4J4+*@$^55xy0-`vWWJU$>dw!C}rs_R}LIu<8VKgyHTAH(z%h-+pQ@jp`ildgnWs$UGJo z7rC&1AMZMPf)Cz%J8yaJGXJLl03ZNKL_t*DF8=PZ{amPJHgm%@liFxXxg4c+>#R;A zQ%jT{t@KhDSLjKkhPqbt14J-*g&ms`+^$>Of*WppxM!+l;aW^%$0y?Ow+{3Afyx(S$D;-wIz)c4A5+~EvgX)cv6yN3O@*(I}DZ+E-ddm z416?#dNaloF=?vogjRZ7yfg+vlFNmpshyC%af&!06lP={nUw%eQcrZVTE;z(-VCBgZHt0<9aTP zO%eDZU-;7JNb0kE;uC+squ+m+pZWRUAWmY}ELvT}vSW>HEUY-sE@bH@hDzBrYp^hX zXI%@?(Y{LS9HX`K+PCn(P1yyE#t%AF6isqoh>MRmpSAdB^eef&yE zmL#^3kOFOdl**jQ*9B!cB%niy@_g${mSt8{t%bDH`lUcDtMdS8wc6Z$=Nq-{Z){qFuk9kJKqzWp=oLwI0proN$RY0?#Ph z40u+IY~0=>jUm&D#;TRfCGbc8^DE>e{KPxo%IN$e!^4C0WA#9&Kx^I(GSte;D-Tyq0juO(@g1<=3)))>|do61W^c?B2k)awr}LmKl&dTnP24a zzWv;H=S}Qbx02B_XW09Eh5z)cKgV}}@FL%N_$gu|&|ZK^+NgG$TolmvmYX?!@e=?1 z-DkMxO?M%rWa88*Moyk)_2y0V4h=9ha*2_Xr&xF8HUx&*scCj>+d`u@4{;18qrXyS zVR{Ck6`oGXyF7*Y>1lrbQ-8)s-v17M?fxI(kY=QT1RzuhPYn0dxyIR zi}^gIz5#OOE`lJSob!19{r9ow&?)}-@BfL*Bcph^9KsLmJ&YY%;nob&BU73H!8e}R zkH})m`G7s6<2*uux#b@F2x}p3#YE&K*0<#;dOGn^5SbJy5%;RI0QqnmY))3)d1> z3m3Q>yrr#RIFue^({mg>c!=No@ZZqW)q_$AN-1WmHppzSe}I{p8UEqhk21ICdH&nq ze}NCZ|9%R2&piL^lcEqpvC_-wk#VBH^5)y+9AjxyY}vet{;r7e$w@$P(~2@5f9u_7 zt;vT07iJgvz3&~QShKpK3)5Ln#Uw8Jp*c{YQ{l$^&~3(^iU+$r(nb zsx;dP-+kr#8dXbo z_H(GLjZzCp=^;I9mSK!Sr!k!kT}W%#p;dzP+Dq9qVDN%GL6E0d$cdh=(!aFAd+qrD zJzi@7eh7|ov1pVCK(wteOe-{oobQp7lGJnxYvC*y?V%8iU%Wte>SYQyz7cW-GOY-u z^@vVcE~Z-@6u^}tooTz)$~Fi>E{TQ>PIPQo@+$5KghRJ^NLT!K1i^{Y)=wO>RODoI z2BL;YdMKmZ`?d>D87qkOz*(uWRJ1Kwow{Fvl=yCv>^X6v#Iw*VHb5uIG@%C{`PH9i zU|=P_4-2(q1|j*^dpXup7q;~v1}SHYeK2{*0&$v;E}@|Id+V9yyad5iu>OB zc1p#5cg74CC#U&~uRO#^wPi!Jv_eQhGtD@7-~cKtvF65GXc;SB^nsl3ks6Dx*axsh zb-F^|J~Z5x$EUgK{@itO8`UYMbz5q5)H)1aD`gnr|)c9WPaNfrH@tzl=_wAqa)hnBb~ChMh$o(ShE}_65u%P` zPUpUGQ~AzR*ApH_X#02C(j{=ye<5s;oQEWfTm1YBPgC(Vv(+k|FPRvfpj^!JPha^K zy?wnl@mNZ{$kJERBz0Dqa;XV0of;GSW-PTt+xyDV?v!gzz)kywz{91G?hw)xZS2+uM-3Txm=DoN$mMTP;WFX zts=JJW7e|McTGpf-qd=TOGgjNbcQjSOhIpNH))nJGc!*VSzBAJH74t%iYhDccWXGx zS;~x78b1h@sXnkYbvJGTX&mjz^XzN(bocP}Z$8A6&+H*nhVGso_P_KpM~<9kZm!A| zYgW-N4N(&XjC6xUW6!x1)-xU9#FWw}5C-jRYnQVzI$9NNwJHYUc9W5p_OfBcAVJ{s zhkyEMrkaW)V+#buJkkpwZeyfpH8V+!Uno#27io-+6Z#-hYIX7e}e|_2CuDoSm9w*ELu3%J~WY{yR@`c6^$FwQCT5 zNT?KBx&!jL0F}lZ*z*K|pW|IuuHfLom+0Sd9V>%~@uNq$eCiZyw{F2-x0dmXBb+~W zf-O6@W0YcUa@q=}kxY+I5Y9{^jZKO@yZ31l&*o1Ib$4;wZMX5&XAW?7W`S#WZ>QOa z*}Y*Uy+gwcu3m?cSYflUjiiS~lSL4aBnd)UN4YOQxu3uK+?N@-c$xK^HnC#u8azLs zQZAwmOpH$ugaN+qTfJAlK$tIB!F&fT7J@)n^jrx^V{ws}j~*jeD4~?5R%?*&E8$5^ znq{mT?q|!oRh%2SY*F-lj&^&Bs*&9E`WyJIx81=sFi5>6&==efRK=H{Z?kKX`&IYgh2*d+xyVB|rUvcakp@5LgY%*!TqB`R;?J(mg=A zT%r*9;@s#shmN1-U2nRLv584ep1+7{H(3xlYsTT4dgTx}UrI8g$uKA(sm;ys-Yq@! z1%g+OpXT}vE4Y5$02j`mC(Pw}+cjI6o}FXg!8U8U3jEq#y9uO37(=bmV0@v$VlGdj zhZ*YWGUZSZOGDrx3<5tWk|qsQ*0uvc>DviE;0Lyb*KWVD2&JV}+V8XJ^Tr{0Qu-KU z-SvigdVlfhr=K3bEeF0hmQ z#8?h%oG+n=H_?n!dWsTZG@%s48X_S`j71cTR%EWo@6dO&u{`zwoP&=GPQrp}9`=27 z^aiokL>=1!v0R*Ytj(IrS}b;g!#XH}lnzOd(lr(?z0|XQ%9c8?tN~DnrS~boWf&|s zGl{l^oA24CK?#A%G%^>kSZ^>pKgarwo5<%1#7T>R!9IotR&eC-%Y6J}f57j4@)LaH z!G~BeJOEg?lPpW^Lq=KQqUVQ{%LVGqHkC?=C=993R#~Xl2m-4c2!epFN{MEzN*D&@ ziUp>orfIhm+mIyIf-!KRN}l6ucl^{X1;g^kr4S^U!V?C-3Jb=7V*ZQ8`-#0>Kb4Tc8?nVFsCD_{LO-}vVzD6Y7IM5(3e z?OdZp)HlqgtFLEX*@V_gsYtV(khEGP+K{^IYilR7q$LTQt!L+2M4t5__W#sLU0to-H;y?m^OXTyOiZ zMp%kRC*VHI3}#6nDlqet{K}hOM|UBh(WtU+(+|!RCi++1eZBw*ZU*t{qyn#RalRx6=Jx{P|#R|4xxr3>xDUw)`A$a)Z6I@uZ zOy@LB@TJ5^4{apUHF~MAYr-gna#o+d6wY?k4mLU&4q28_otx)dUeVaBjd-4RAPM&7X z_HC?Kzk$i~=Q(xwFdMgRW%HKJ=*&96$I3nlwDj?umckd<1}e(&+_QTqlq-Dwu{}I9 z(V&&9(0=x$^`!SaqA;+bO;}st&=Z(elh))Ve4~ka`Wfu$;_}4{yyvzXx%(s6kO|35 zt--e*dzNP&dWx=ciI4x{PqK35Flfc})HL6G;yE6B{soduQ!W;1HtQr>P%P#!X`97b zlOPO;iUsQP(-eK*TGtvo|YLk>YH^z1dBo+2nzh>f5fC#WpNE9X#-mN(GX zkMHO3{0yZsqFkP$Gl@WGhWfe~ompgX?FP=CJ;T_g5rJnjQf6mo7#bQz8;#9G_gPq2 z0Ifu;9UHAQ(kNC9^sxSlRXl(A6xtXvBdr-n!44H2Y+;|X#@fqjtaWpiY1R~d{;v=H z7^5@uEVg1towLX<&Je;6BZp{P=O2wAQ8p#H*^W_3!nu<w(uMJvPH}-j%3zr%X+;lixFUGfw*hwlpRdl+s9yM~K*skUIr4+A=PP}m-MD7k z{(o&9_V4j{tpWHUI8vPVHGtLxLX&!u#28}t@KweT8tW*~a*&+>!a@?#!COJ1!8RoZ=N6=vwG5rt=>&}}Pf?c}gTz1}twm{SiNlsgU?h3pPzm95tQnhG zVDF1B@rAEEKr!%GIoxj!9Xu?KA3w!Rwawup$LOwh%Vdt{${DG!`3FDrL%L7#*8*{A!ISC89Ig z^*rJ=dRt%&(B(PLTa{dT5p=IM9kDuk#|g>sdPJ#8nkl;Lc>I5SpGu{|imp88j~`{`_+j33&z+249^>q><80o&o57)e z4*Xy*g<_fOuDhD4=_%T+CL+toj99YzL`bAtkxE$pf!5mEfg0Ncb%J;lR!AIpf@HDA zBTqfYKzD`lxq0Tk_Bi7gPa||jcmI<#n|1Q}9G>TqCaFaaq|L`LS*M_NGke!?7-Ngt zG_!$Po@Z%lo@+{saF&=}=fP%?HGB`FEWcF>=`;qGN8x#vyDo)wPG&&d zPMELO=wsY>hnEu^p$Nn`K>pST?(eBUNQYnKP0jTNN} zTks@FNX9oNXR)J^TZr7{}f_Lm^AIt61W7V~7;auA@#xuA$wS@9}|JOBtmu~^`h zmtN*$zw^5^TZ_zBtCY(n8qI_)Tem?Fa&o3YQ{-uDL#A2EkC5(q*xV8u7NLzzOgGvr zop+Vl;5a-R9;SdO^x1vYdpUakGN1j@SNW??{We$a+|Kr$M_7n6g22a zDuq0aI6(s4`H;*&z0m?GxYTIyXAe9{PGpG0I^#@^PjT~gyZFF6?_*`;aeCiAcHDjk z2+7Qu(_A=qob|hQGQ4p;(-%iLf8+#}o{F8SDvc4+>d@RXLJAi`DXeBBpU)Au+f)LN zQrw`D&yjkmE7CGV+(u^^+SsYQ(T0WUEGsJ|vNWMFH$&nX()n3_^o_UDn4jVJ;lpg% zwv~_n+`GB!+ATcv=u@cX0{b3+8P6zgc>OJW_V<2`myey|kr$71xO!bd)nEPx0ALeT>udb^i2;!+0v77=;w0kZ(Wv13vx>ALNU_|7&!Y zOFVM;EHkko3_{M<+Wg8F9_HOQZl_!<@YyF{X5YvxxuCFwil&)$GZVs6Xr&Z16Gbr> zasJ$Cnr9BPeajZE80<$C1a&1r+4X{y96ol$thr*fn6J(;F+PUIqYw!KPcXO8V77@+ zS;oWP{x<#h-)$D!N?e+(a(QBgu1b-p)JGKM$g+%yu@Mfu_!8}AgEgDBBm7WEV@OrT z$iy^cu^q(3ZTdrK`8IbWb-QGTBAn@EI#Zg)RLUObrmB4MA0Fb=T#GO&pt6KWxA8sS zBJzQ4^!*@2XhnT?mS#I9)rQEVh;|FVI>udBt&-(@z}(aX-O)BXKoXr%rhC40@&b9a ztJ*S>yDYL|xgjvG`jR%}^F?|F)|&NO`nsb0(9gEpwVxfI9(!!D(fa)UBgen{f&1=z zO&t8c9IrJ1KLp40>hJ|v|p%sYZy4~SW&-K5y*Zfp#pafKi(IR+RV437-u!b0lD^b8t6x=ij7QE78uj@M_!B4mBwBJ#xa3WD4m+KA)!$hEz|yLOsfp z4?Q0K?n4wyMJ7kb(Mt2=lY2yUewK2v#GilquNhu3$j;q6QBK?_oY#7mWkf+}?H+^; z;UdfM3ps0Vs1#usQOM;;l_E`3ilq{sFG-V>I8Lb68rHu&42hG>PF40V_I&wux2`}a!m z1K;Q8f9%b?ediVIxm;s({46u4k8#&McQQFP&Z!fp*>=^{^bYiL;JJO2N=2@J-L)J) zeu{}pmx-dn60J!K;Z~{@)@4|0R~$@lv|jow9U7M>aqmUo>5RzN9C-N^`c`dV*Hu@O zwiY;X>^Nu7jW9NLi8xO1d>=pXZ9yvxDz)DBoq}Jm%V4%WuzV$iv7+*;`*hh}L;vz0J7)X)6f0={npx4Ozj=4(xoG$j{B1fgwi7wZk1 zIpImtRH2k6O{yrZ$>sA)W&y$>bwLnVq$dn*;V0!%cwMK#NRpH&vi7vKS{=_{)Z^8hVE?oH#CzY$ z&fVAX(8G^2J+nX{B||-3oNIY>6$;jI#u%F`(YY9+6TW6CM!04JVF+?o9Idj<-g8QG zX5hTj=`ZdHQkhXj5`cVUR6S);u;hv+oH#@b67 z7d$AH!U(~(HEU?M+sw@`5Cs7jPn}}hmW^DVn&H!b_Ge^q%uxCJeCAL8khzP;SsXjd z=l=E>zxeY%%^&~YpXLWIALp`k{( zGlEqcHe>Q7R{A;C^b|N#%TSr1t61WdbC>!3e|(5_-9;{sPcdd9ba?=gD!RJ5I54-! zvtQp!A|>TQfv!RUPwOQl+ISt8I=fae5P24@!wdQI-}*V;bK5nX7#U}{zn4R!GyL(_ zz7H6(B;|8o{0FYP`bx^B5}1TIPFb9*(rzu%QZTgUO1cNvuu!Y>@{u#NTbiS%F7eTi z{V}Un4pAvr$dn>ZGn%ayl|sl}_uganpP3dn^u#n3EX*#D^9;A%a2*3(6~6PrVZM8I zmZsJqJ%rXv89mE6Lf{!g==(IYgvCaaY9`1^z4$?dFMW(j$)#1+^%m)m423|NoF}+^ z@se1#YbC=yW$KA0kT5@aiMU=itNM##<*GH1#*_UGz>;lY1Xf%d=g@md4$LvV;@&C67Z@gzb*qAhj82xx0_gSF z5WCizKzd7o9?BRC(|MA}lZax`a{jP|d+J_83rqI_oA{bK%28feVNl?Bz=^TB0a=H? z3(k(z7W+kMElHOOcUYoCc*4$r6SE%0@5Sr`$S>D;$odR$w<=_YqKUO zl?udhN}MEkd0T{Ptx;MpIiLvPVYH&QSf|;FDU~dhAW0IW=Tj<|09yn}>7%lQOer!A zJ(VKge(alk?~zBjbm&QbhL%z^5=CEo zp7-8(6VuI%cmC*`2ry)6N(L;Zn)lzdo$vkrpEF*a#m&?dV6?r z-+s!KGS|QEdJY~u!s1+&zV2R214Awa=LFIUnG@gR^*7&$ND}I;R%eA<*9$4hgmcnS z%SCHgo8aC%Z{dUQc{h_YRoaQ+(#12ZST)SAeCX$R@#X!z^6S4%mZrAY18~W^IP^g* z!PG9n)jgbAtrprr<-*;+zLYi;&D}o|=ve&X#IiR0%j?_`2qDPjaxB(rq)9|~cNt@> zuzY%YmN?afzHgfy?S#V^H&OTK=_xIR5w%(^k~GEhe2mgd&3NbibR2%b;7OO->v>D- zHw;63-zS&LNE<%^001BWNklJFLo8xaEe1e|AAx0-Bk(mwP z@;pg9O_{DWSWMc4p7Ul8Bhs{uPE(47JcV2i;S#l_^ohdIx_p(2TzB2o%q=c5dFe8< zqvv?rt=IG8Z+kE6)~;r5q0Z;N_5hFUJ;cD^Fd_)i2wJTc176I3`R)HmcW*afC>6_u zQG_R;tE-Erp4-Roed!^xAkScL55^0~E zI#Ib)>BN9g&Zb$|p_A%R>e7@b46QY>HcNJ>zN5!vN|PFk5DKF~WoRK-sJA$A?6lQ5 zg#p{QY+%*;b&O5VBBLU2y!B?&nz~4LF(<|@U1sF`MYgQJf_J?2$5?FC%)XaSh$skI zwRWR;^yG7l&s6E^zLqaO@*GdUc#L1Y|1P@1fJQ53y1K~MpWesXp#iR1yOOc9vq%YA zNV@y`mG&DD^(5;DcP0$JTc=TVz1P2Ir=s|hOj(&jI;I%WxyR-zd_ zeUfb(`&iNIBU4G-j9JYBKYh;|*|1?FaiTB=_V0U&vu74qxq1a}`q6iw(csmw-ERUGF?xT&GfvYSJy%~B^HxW=P{a@b*=i!XQZvu{ClLafbN-uJkC{5WZ=P3(tE zpF2ZwXeIqCRueaBHU(8oT>h0!U#{@_FSzI`Ca zNk)=nwt#aRVX0IiZYPXQ%(%o-O&A7_reNJDz|sk{0nfL^mJh_OHqw(6@^-4>2LT32 z7>0Jka?VAKW((h!6bm_&($?-Z2uPK+mTWXymTp5z5ClYFK$4{N_H?mk?N+Y5@;n#M zoo4UzdssQt&zZBw@O=*nbzahG*W-@@Cj-_FtTS!QSEIDPCm+ji}w($&Sm{RgO2D(t%U zDh?h#Mzgv|F<*3!KbC)+c@in1nWUI7NOR;6{H!5DfiM>#v|)a3o_sFE%N1Cx*GaRC`a+eT zc;|gwbLD30tu~p~w3{t@y2>0meu~e3`!Po5=7@rTToe+9A=PS)=FW}O%LNV|K1MDo zkkqPt@)zFAPrd(x96Rv}FCN&-&h5MSqmTX~r+)GOWV+R+QYcxI1#LsMn(+dqEYH~3 z7<03;3=glQ(%nU6zRW_cYJ4e$PE%5qVWdDykIm~=aOmJsj{jf}n|5wzzL3Y%Qs%}d zxNz#UE$pKl)rBfTNcy`g2tOco`3OdUX}9RE6lli@nG$41fgcih0-2?jM&@}-R+z@E zV680*5QY&_2v!gGv32`)&Ky6^T{||i{q}o!;q+M%k52QzBTsYS;0cbOynr7>eEmBQ z@~!VaCI(lnqn#;^o<0vqR`!KgDRxz;6$*sDpoJ|a6Rj=1$5>Hu&c@c;kV#=Ftg*Ju{gUOb zd#-ufYF-u^Z64Wso*iq42_?LE`U0!F%QWKzy$3k_U`uq(2y}gusdug@WXyN1K3K-#0Yo{ocq1r9Fi#gV>93V{+ z7L%0U|J;ML8Vyzt_EPTYp(rwvAcvA3aT2@0K1qUEDz0s~ox*d&pU@%UQhLNmlU99! zWMK}k0ZG0E={q5J9*W$@L<|N8&1WT3WGW7w((+U=M)o@SuGn@Ugldf>GNfY%y;ABrO= zlrhp@niQL*rESX=rL~)$TdrQJ6gl6w-uvK+hYqD@dD^aB@otO_`2vWfz__3y<0wR_ zwjS?c2jX{)K_r%ixK;>kA!sSA4x#g&IzKOP-mr0pfVGsP zrKtoiRTgW@r#(q`E@a`*K3dZgY`OMEbP|&o&H0!1Qb=0_e#k?$3GUgsT6FjJv3K9| z=IK5AMSXFRV!2FXp~`#S_v4&6dzrqzK9sT3D&hHfD0G(L2li8F=WU+PMeaNFGIcy6p{QY0UYHqjdK?!H(@)&e*QSXv}yTB8QG*hJ7@cP?c$JrCdxpe*_ zL%n^LS|%h`o^IE)G|H}7mqKZf#FI7t=np@^?%h|BshFOgLH_pd{tl%wKK$#y$zzW_ z!q5D|he=}FjCG1x#a)ko3IXeqzf`JK2Bc0F-*D6SD902zTFo7Z;yB%s;+(jy-242nt0;rkni3o+IG-Ja%D@ zCX#9^p)1Sq2ti2NsahIL+1Za_u#_iJntGg|g&UxWWnQ|H7THLYUb6diY+YhyXxHZX zPj~O&y|=uFCXV~<^_!21$Di1P=ld)!)=e%Ki8M{Q zaB-9yZ@-JJv7tOL#Jk^mFQp*hJ3rV*cRu2(?OS;M@JSXLEw0|Oo*>Ne$o@lIv;InM z-nN-<>^sQG=>-CyRjaaQsE>PIe;sEgW)R*a?TJxFUwMJ@b$5_2_gKoESsw0mXuLrX zqJ<C8|n7cg;?AjnZJmuR*VLZgvEks#komT9!g?6cE= z5T2@4c}VhaIbH=~{D1ttL52aVR}8H9H^2D*rpIdyzz@Mu$Q6x|KAGds zwy;zFyzgT$MACVJ3qh*2v+S~y{|?-3uw4I6(XWj87vkDwVXiHzaUS)aaW;dU4G!D& zzxrP4P#FS83BYLqI?2Kk%MTY=4xwNtC!(*n zpV^stMlK$stE-C>C(aNR%T#)MNRpHwh^*6*^2p~R>h%U%Lp~RfWwD*^OKXLgW(wg; ze9ty2zT<n+%+bte?BlwwOy(oA#?+ z2$a^^W)*}sz$r}?Gjj{fPft=VMBIGSwM(gacU5?K|4UT5ySeIy>pA?&DP-J#(62?0I`^2ne+*7w-3iQc_dupCwJ1}H zoF9>>#JTlI!qDYQXhkb?8J@0L$dsbDr^4m&Hrf~}K0y$YDVzSQ(v*hQxHsG`nvSTMor$7)4^!M`BuY8>o$4@a=U7)_Wz~ImTlhgBT-n<1r zU*vq#XAvLY_s}j~*BI@B;Edz2yM0M1jB^K4&OBkZTBY3E%ck{f89#ZFGA%y+(GO9d zpC>btFtAQmGt*O?K6{S&#w<77dL5Bas4V6GW$!)X>^$o`@9%Zp?esHUGn%5_yPI%t zxSM8ULMjOlCDbJllE5ZBkJ*KVkN^fYVS{79R2#4jHtx18OSUChR_|>z8c9>n%$$Di zdOa_$`;5&eyPti^zTlJPexWi=XEb;Dm*4OEYssgW*J7%AZA6Sudz>p4`Q`TgxJQYw)YAsg4P=FzWxhfluyW-h;AH9z|GbL_$6qknWK)ll)R2Y-zaf`;c)E|>Yl z?H|OkEUvw19S^^Hlr4J?kg*MXB~X#jO_tXn3WNCnSU0(r)J?c)SVU34*AlWsSd-t5hv@EQS9_Hjb=}kzgBZ^QpDLA3tPbfv&l%x|0 zip3(e5TvPn6>g~U(rL@U4ccnBmB)&ow+PhR~xLQFFK^W-~U=#)* zO_Ts%39>1NqVF+!ZWyUTzV|QRA=BE9>qoR^Q>1e?2VXnH#w$BeXid+*o#Lz6KQ*_b zLdZAVGyb0+Z%|{#!xnviZoa*FWD;@E#P5#ZH2}X2N7yKf&~JbgF*jSEux=QUFik?# z8`$9*gNf3y_kjXG)DvmT&;~49Xo8SJ%oZA&79xoRS|c3)BlW=7o&h0nDz=)k1qs$0nhzN_AI<3{@n*p`bfT;&1cm}7)NJ?{N~6TQIE2hZYZZM% z(w(#^?Ab;zI?Re|Zp00JPHujh_JPH8t-BaEgadVtbj2rUnSB24zhh2kuK;kp8IB)6 zN=I8a-~Il5tY5#L`@a8Ejt>r#&SYrRwG0OY!cJn@Hi7R`t_B!F&gLQjvD`x6pe#$` zdD;}JV!1;Q#m$i+sn_bW)CbcrXw(~+rcQ0vxJOB~TEnqzoPSphKE?S`m#5iRf_$`j`H<~o~LLe zkwRf8K^Xsh4cWxYM#z|_thw(-T=>O>Yp8>4A_R`9sZ07a)J2+QXvvWZLtR+Kk{XGi zIC`GD-f}Z%&yH~G4cD<~(E`@3SW2bdVB4O942~4|r-z>7zMnkIvi>>z@SZPlXy`n< zU)@1I-@@7r>p8N2KkiJGbSkCOLD3p|;`G}_pbgWPUwb9TkDui1snfLNT8UJoZ*GP` zq%>j^Q_|ksMI%nEG=EusY4ay!otIwT2hAZszFWgIsmhRUAEj1Z~I; z^h7ZJ84@EBo4t_`uakY4-3~Bo5^gpQ3CGc^`#?*2R1{$tA~wy&=Ue=-!Y~N^fNE7^ zW8H>F12-lN`J@syek}V@Ld$8Yl?sW3O;?we1oZTDVVMT?cnjdVF6BxUAtg@2VQg%Y zQmLZ({Xw&x*AM=*gdkE;Oh|&j4>3(sZvuiqqe0__wuuRC z%9nyL1fdPtGM09|af?!^*0}Z7oA|@u|3kLDvWfQg7OuYLdWMFE5Qak{k>Hu#M>$yr zE0G{-a-f9XECzAW7PyT#uutLp0qt$ABpn+WOABkR%YnTI7--Al)#1c}*SK)?eAU%E zS2#{mN!6unXN@{Nyw-T-)qPy~=37-=+2ZifI4TIa`MPUG|J+`F@~dY#eCiBOy>^Jv zvP+92Np{SkY-Fg{10p101O-pf2z0~N*4ie@akHLVF(L5OWz6sAg)>kZbeSWHj%T#lVN&v?0x9Y#2b1cy!@ z|68og_1*GLEN189hIuT$pAmm1JnwE|im@cjambBcvh@Kh)1EDZn-b8OI`>Oj4}Y zDb`&~1dT{hR|-}0`R+5@d13Ei+^GU5j~!>@#!K+rI-|!9k}|<<1SGS0=FjUVVVgYi zi$^F-muTaI^BkpaV`8c9;A6uoUZ6pC%T_Of=> zN^+SL&z&6Sx=($Xix&5D(elNt=%34LV<&N1=a8B+z*M7wiXu{`Y+8);{agqPrI13= zl1Y)V6rS(J%@R7qGmLN>E}dOnYWd;;vFWL^oEbdBS+BwQ@fqf{cd&HXLN31a0y?@o zQIQ@Jc!B$GY9DFXsJIcEr3d^^r~m)s4Z&>jAAdx1=o0F@KL9*G`hUM(_;-5zt^xQh zI9w|cMR9T_5K|O%@viw9abuu#+MplDtB0XZ@3f`XayNPM_1N@BJpETnkuoHigo8k% zEi? z)ck;aDuE#-jk?R3;UQ*?l!pP=C|J1miw#el&WHULEnLHyCMIL|V zdHMzh*!0pS)o8ecenWJ%r1<3vyZOoekJ7VzH9-hoWtu4TF>`IYa97RMylwzMXElTh zym)orq*BRP$89KdGH7f{_ksXZ8gVfkOLL^bbfLga8`rR8(IUS5wQsVhZ!Z1w=kfUS zTlwjeTX<>DL27PDI+>)SrH!hQ;DsH#S=K*??fVXL)m2w=_`m_`GiCD0G+`7G2m?## zLP$vPf)E$Q_19j`;gf@m3=Y$tZJAA5mI5NF^ybDkS-XA>uG^sM>QJUA3?K+F^qPl- zOP7$d1QUfBMha6*P8I3u>QZahtq~2s9_!iBJ+Rbx&gNO(oc60Iz_!iTW3A&2TQlS< z_QB$Mu`i(ce}>-1NNEr>uMzZCq0wm2lFzYd(R?bEGGP$n`JOIjl^zPTB$8BWb^Nf7 zl!8RUp&~Rkb0`#M3E9p zxD;{oqw&R-*rudXE+M@dk3ab|x83x4F>mojgi#<+k+3XV z^)1X%cYS{K$j?!^entxwo_X?F{`_4xVOS=G!X%w(hkyCl?-N83t(gq}x@9jv-aU-3 zBvKeUU0Fy>C&g2nUgCz!*0OZzVs`G_i?l4VnG~P+$cM1g3F@v-WCs`t3lTyPLU+$x zmMmG!iIanrN+pV=3Lk#|d${_F%Xn$;clCK`TG(+;!P()nlxr?w7;y5$N#6Ii8z@!l zjFxM3baruk_&m9m94##^yyfO=IeGRxCr1k`UblgCCWjJ&{!sDYfnl~ByPwuff~i^!+qK=uH-CcB}1&L42PTF+odE^+TlZQ>^=pmp!E6Fj9&rohwi- zm+9!9!}g=6*>U15jR@>HeWd2}lS`*b)}}bMcQ?M@(D&cS*VmuaayY_(C85&lT%d;JGe7f}|<=#Jg|jSG!J9Z@6seX(45`^4Q4<&Xf*t+0p?_ zp-4M6wMIaTr8mk_YEo9H6n>~MR7Bb|$*7P+V>1}3EQl$TG!Vih6$SWGP_0+74Jno_ zU5sM{?Af-B6DQ9jrDW;yrL@oK0yDw9g$uCkn|^cZ{~KRQh~G5;@$tI`;J4tgEGHC(Nff!dev%fEV75RorNoOu zK+MLf(+mw#T4EB$^dBX(k;jBtBQQdca1s;`?}AzdYt5zjDn=lpnf|7LMi5d9AvjDk z001BWNkl~lL!U}<8rSo|N$MMW7~uFWmV8};p~3(eMOgVZL^6eqmIHZFgee8- zbei#luMrF%BX`}M*wWA&i@3RI-h7%UQ5C!Ym1B~%490iAL~Z;W>#n&-u)t~G)`}CFAEkgW%rI9guX8ZkDsDeEm1DlFieXm@U^5Q?gmsWi_?!R{cO?a z^6QwuFwmw}OX^$zA)?rNr#EYcp^I^0nz3&{bHNp0TNX2=3I`4zA)C#Ta4h{j8U~eW z9k=e{`&0O#(zz00fNfjYwnHYJBJcy9Vhvc9H7irAR;$e(1tGw8>{*$Yl&|am!ziSg z&S6MN5C%xYob|&*@f5o`y^}&rxZL*3Y#Qqiat z`Rr#u%%v-rFflVj-4AHXW!SlE51CXF->~okMT;%5=4Na3jCTxg!rC| zW4DUJ*7^2P z&cBHa8hzdAU~3<=ivcXG{!RlNA6dua%RJKy_u z_K$C3XTc+7nMkinX>5Y1Rzdk5LO>YkO&_L3(W~>3t(!>YTQRdO1c4%Q8#M3;%hN=; z6oFg8GED{s<|Cydnb}R^c#@XZ9FAjP*$%aO4aa;PWuOm*kUDid3>xu0N44Xs^51++vuzOK_21+22czjSjugeR8~hKx`2Tjt?;3#Lf+J~4W!pAF)&Nbw(P%ME zmYLma35^E@X7%$*K_mrMOb1eE=|GdlqvArp=(^PE9)YJ=>Xm4<3<{pas254w21P4} zr6Te{1xR6ebw2v$l??RH<)!1pC?s>TDHe9MXt{!v1YU!D(nccq+%I2dXVoQ@&_#q9 z7e}RfgK6OqWx5Dz4J^}|y-;ltXBo!RS`BMdIJQNrB{{$M6{=I?thoASBH!cK*5~N# zokw=%2FB|?WzPdCNgyx{f$u3y%i-kl6BwpRYpzACe)Cd}9Xrm>-FwL8^9-LmM-)aZ zTF|FyNuEa(1q6P8lT2!}uCFJgrXgdNzl^D*YIXvgOeSz$pC}BlO@koP>7ij5k+5~# zy_ANg?bx=KMi~aRY8~5l2!c37so^1{LE!n=P6Cu(uljyKB3{SW>J30kqA*RW)fyLX zSjpJo=_C?CC-7y7NwvN$055YY22;l<&Dr&CKW(Y^dojGKypBLto?m;w*?D zHg+o_JoGKrG;Bh&q$eVbHwAhN!mKZ#xk=DeiJ7T!-t)FMbJJCq@q-6OdD8{!xcfUl z;{IR1NOx~Pwrx_aRq-N4cW*c8Y?i&R?IsFCUfzF{zFdOmht4v;ZveAtCPblh6e(`Q zC6KW3vP(H~_y}juj?kLQ>M3#}N#yCxOQ1X=+hpz9RlM@rZt}T2H{Wm_wOUmNR;kz= zFC>;%ps7a#i++qQ4!ZSQ;!zUR-bl3%CY#1EUe2#BI6 zo|=Of1UQySs6xF_iTwgiUVO7b7g7?15x(nTO8xh6wiwqW4&M(c6sGVzAKNlXXEP*i zi%cqoWt%7^I5T{HmV#m1Cao=5gpf2`mwK&EwOR)eGt1+Gqxo+~k%}AP5QX-o2q{S< z60wY}u64sw5XJW)rJ`Bvs6fm5bap^6Tl6<6M^f?EJMH-lBZVUO zZQaK!$ItWD^^3`mm2g7pYM7`nRXS2+|^lBd2^fdMtzRp+v_S1BA_E0Dm_{9^C z@%(E?z{zM|M-UQ)0r_kOUnIHjXOHo=8*gCEs`Ws?^IJD@*sK_!4sQbXOwG)2>&-Xvw;%W;_8&ROkALz2mD4R88Xe>p_xv-BYL!Jx7eVAB!hk4>aQ%P) zlkPB(oU~96iOMJ-hi{ zcPm${TTWN+Tox{v$LP!?bMh$&W@vaiU0lZ7Xg^YTu`eYlwI3qa(n56YTL?oRQ^og7 z0lC&TzWl>Sm@8adX>xvalKm%!NVl{R3CU}RPf}~R1g-}PdV9J#bmRox-E+9}j<@mP zFQ1~?@NrDA+dBEq=G{E-+A#`VgjaF-)VF@f`0y~9g)8|#A9+PTH`95>UB$j<50FYH zQHd1KoEYQcqi3SYg)b$ft;e4#7(#EvnTTfv07W ztqXD#iW3YT-h-3|COXYNDotW^_2XDZoHm{XA#t1pZF2^hDb`U$XggCNq!}TEHM>;= z4U$lR5C&3eucIcW=`ErV`d*+^Q;s-W^`N(dHi2K$gNf#SCjQ-wKU~GX>hej&l3a&c ztvvewu~hqacl@pa_$@e`Oe;$12P7)QAS5&-ei&fKh&&Zf>a_-2yy04i6F`*?7qX;D z7@IK_dIc_&B4J3%3s*5OEb+?^-_B^M#_eDJA^-S?H?pdym3Q3xEM2zZM<03%4{krg z^V@cD`z0&cwR<-k%sQ2+aq>nUV?2#%m?RvFY(A@wo*oi&`WA5I^7(9k`2>Mu;RucL z)TzdhA6ST7uoNc>31UA%pfqU+;tN*k*O^V&VM_f zsng`LS)61N-}7|y5r!z!)TYKbt<Ijh;WEsIjQN^egWo1b}{2Y&t& zo_O+UKK;=@qou8r-nol^E#wg}|OLV}O zR9chnMS6PEoJJc$>%R5eTcMP|QW1vKO{*71sCtbL{lOiaD@=3SE!T5+@H{UZI?b(j zz5^NS-L*zrP_0(j_1bQ-xjbzh?HoOLm_L5|E&S}M7hmVO3yDG^!w_GEgc2^=coBz= z9q0U+bF^i1aR`zAzJ;Mpu%48xTD_W`d-jsaYqgt&I2KqX(V*f`F=)&AG4HAh2$y9>C*AMDO!$lZcE)d0= zfglKV)_|dDM@lK8Akdr1rdQ;R1HE`EYZxYmVM08q6@U>VR-;gB#A`MEa5qgwOG^ts z|M?@l@cbqkp3nSwz1(u+b$sG4|C(f`m25V}w3%l{IdpdSP-*xS3uj2!2`mYQh>(`e z7w-8E_zfJXc;wellT0PSOz`!8_zDSAvSh)4+OcDoxa_*?$hEgIbE2;Nz{fBwVc8Dp zbQ+~3?HwJQIz7zpZ~iy>R;;7!OO$0Xa()!Tke==?^(Zj@Yoc|e5aO%#RGBA6DlFFlB9BZ0%;+o!FaWf(=(60-X2uw^YPDpk-05Nb^O3S zapA=msaw}A70+#cg-0L!5m_6ad2TD8`Pp5eh?{ES_@cXQ9z zzC^uJqQ5oG)~A2Tu6@UuoGz1ZZDr}=0iuRxuQzia3_A|wi}Pp<%f>P!Zli(gy7+Oh z+|+cDdbz~*7oXw4ju+|b>*KC#*6_C5Z>6(q4)6c#FL83$YjiDI%G`AqQ3)k2R>a83 z!<1&G=xFa?qEtbKK7t5gSO}$PxD95Ob}=xq6O7rb8vuIc6qDv22H?nE5vk74KIRQP`Ba8u4?b$shd9%|R28U`UCX zNFxo6*!I0TVc-%)5kU}Lv*m17q3kT0~(Pw6*ppfkRkQ^HB(;e6I&dU zk=?K07A9DC<@I=>&(Td!FsFYZ$rYDSbOTLoNLb7?JR-Z3-ht84CWRRv!tyU+W&k=?JD%LlrG8sxU#pXCy2c-pi>S0@^ zP7L;an(N0f4kxipoeW!xjlaq?_1h3Qjx&o&Y*Z>_QVC4kB#I(Rr4m9&s?|ElgsD?i z4Fkh8$YoP_euy6gh=!J0l*(02HjxHn6B8(5QmNE=;iVm1ars6L96rWOxsDW&NLU;` zJi6XO0~q)6q@n2V^n{loCvjPms>$Sbf1-UVi=s z-hKI6mh{i%)=Ss()Q*G9?dc&xqfk9JzzaM!UV0Hnj~r!ebc~iv4nt{toQec8@Cf{X zP{4&3uVd$){iM=a7WU0$*UQ_;cXY9O?HWWFVw&3IEl`xFr+LqHe}w5*F{EI{vSmE@ z&_f(Mby|J+eIF37?0A_&N4};_z*6D|QC#5YoDGe+jITiu!j4Rj8e$cGVod3 ziur=d9Q;v=N@b4>8-ntLZ<*k|h14Rlo3_UJoUASgJKAk1<{a}PxJ>AF|x?n%-JP5gJr8#^LwpuF5Y?@XEs*Z-rsY5 zG6eV}Yj#Y|-%l;I*{6z}Sy&3y{)U??;;TWv9iHS2(uut*_&*i}s6#Xpi{wmeQDpKOb#dW?>&U8kg z(^ho+;wvp^&}VlQ_o5Wv`reof(onW9tp1o(V=0BKPjQ8$rSBX|&!E8La$cF<`iVF^`L z*ywVGFAqmsm$`%sMKoij$Wej4X0En+Yac}jOX5u4 zDv`LO2qa1|6(z!C#xLpFeRe!fz493FSu>I$y#HEh&YNB(pJ(CKKewHXpm>^X5YiI6 zB^u}W$`L0dH`#|q3}eN973~UqYrSgwPY#f5u92DBT?bT0%DRd`D$X$48HmbgG!o^S zl|esU9Xy^tfo{v9qhnPesp+g*40tEduRHcpaj-ePs&_g#b9KKYSyLX!^+o0BTN|2Z z`zKX37wO-XVieTFn(#syrFz*WzP2IGRv^#`whYWFHk?GbaVcc}t$f~EfZGw_mq1h+ zYo&L`RT|TG1K*F2$jq~i(f`Q==>$S-lvaU9Cb}@+F9vRfQhGR1gB}Ybl6#`r5*Kk4 z>LH9j;WvLTCdqHz<(C($)`3aB`a6lqP2l~svDxVqt%-Q}=gaV&`3MYMfx9HlGV4P- z3;Yliz%ygShn8332mx2q4>wUzPTJa~PDT4Oa%>)f+2JjN(_V|B)o`3?R?CnRDl8#H z$F%ZOt%fK=T_XQ7_di){Etu(4*Pl+PviG({1_Z`WU-(p^E(BY@)Y$jXr7~X5Gk9tx zi730xXHkoul4Ati_Wu+Su_4@yIp!z#?b}zSd{>W2lL@1Z;R)3+Fo+^)c_P=SAoFTR ziB4HSCSHT-=F8W5>lE^tN2OIxo>aAC$|dgYVK)+m^VY8oUv4ILf@pG-VI!TvlB`)W zm|IU+k5HRnJb<=NnkgJAC;(@pOA9xjurgdTt;^v9Q$3bbKLfU&L}$1iNf0P-XSrzb z*f#R_6jH|*NW%_uUf5IA6NWR88_bzJ3N~4AcL_9onlOB zN(&DrFqxy$T1otslAeQoW-(c)MLDs5I5rmdpTCA3@lS8ya>6gc4QF$+<J&M7j%l2Zu{=Om6n^>9s~MWeBQ$yOXQW z<)kwY$ZQ^qstEmxi9apRb(ZPm@knyoWa5GR$&tC4I-lGlav%9hFGxx4T-_TeLQA$E z{lx)-{0+1#NDP;6@sOU|Q{6U$vK@YOef=|eDLyp&UUTo3q41N!Ld4NI(8EM5y0>>r zIx~<%KrLS#a_q=2WkN*sgBa9(DiZPdf)f0n6%hf5cQVZQ7q_b^re|)hY9{UY0$rrk zrD`PkEk_Ii0+E$KV$hPFg9%Y0xq2~|4sZJ-C+O)Rd4xteo22i3FhG3<5IJA=eRlTW zaBk90HYNd{BGr6h8XZO=p70CW|>Z<)#f+g?OT+-y_y2pC{ zy7S8q8S-3nPv2;ih02{vmv(L<B~X$8d7+xal;G6l2oKXz`wb6rC<9)(LH~S|;NhqxznG3u3t!X`Kl9lc z?TPkW`!Ctw?Ad0_R5QH@Vz|4`UeLP?RKkZW=nWvx9uEyusG(}O-ripCCQV+KUbHFM zc{_3aXlSD@DJcz6SFKz)IzKAZMicPerRRk7ZUI-jt8crg5)@AMF=Q|qdJviE0d=_$s>vBjUmqT5}%{b|8_A4F>jCEBc4qa^6RF2g^qcA64QqS)Rr;q&kD5`ZKS);g62*iPvi85Cw5mY`K zQ&=!)ODGt|cG2Z@_1J~9igMXYD;>Jpde{v4E|iR; zM`cGvnN>E;MEdHx*(!W@VwgBo$I10gHk>R$-ke{Q|F1~ke~U;ZFsW!+JN5vQ_Er2u*i0?rm8Q0J+T z=UpGBVSqJVXTY1Rw{9(c@9xl()p`mb$(cEbye}~bP(HHWYyQ5K8?ZHYL_t(B+QH@@ zJe#fcNML2+26{yO;&`APND7X#ON=4-mcWq@ua@gsk^A1Y* z%IUHcTucs`13VXnwA;ODD%+YueL9|$w8~ez0-i8F5SDF0Dgjp~!mmB(tZny#$|M4k zR^CLtb@C`zKK9Bu zpx|dj>$^;4c3xCYt0*9C|E+5RJF)^TPIQb4JBNVG51ZJD3iK7B73juFlkr<*e`KmX z!9H`WHiN|tGmKbzN*fO!j4?AEwmPO~3)0jSjKKykArTsbX`zmW=x0GyrL6dRfzJBY zEMQ4!br0%=@1p+N?{MlPdjiC9QR8({-Bw8#Y4G0sLMV6Gp{LK3A=71w$9N>QLnbPw} z9mUo}z;~(B?#+VFmObiP{z+1$GpV6Jl}f4!pg1ZlR$N*OEl$X(JhNPk)rTW6TRGSi zWbr+a>)c(OwEqI$Mm2mJSWKVgi_^P+5q-$(pxnQkFt0hhdfnH@Es2tz>7m^X%oCBw z?{cy&Hs12-kTokwe3XE`M|hJc;xhcPQUo&8*hl~{r=AgyK^NEid1QVOO!#`gn3Q}QzwpicK0-u-wIg8c<3NiZ8brf|zVpenh}qn*X`K-n z>Jd^1ahQ;Bfq$gOc6=Q=o}YZ5b1#y{ERRl)DO9m`=u}i0fK~oG=IIUni|==G%s;BL zCvxrAR5=#@K`M93ENO3u|wp3x)<85riFT2%;7FtBo2Y@P zKoFu7YMuW~RH06yTCKA6pQkYk4cKDasENAXBfB3zab^76yV4A5|>@r*qS3RGiS{sJULhgM72^aJHa);A|?r)l8L-H>C=z`Fpu_N)Nue2 zWqf>?<^iGA5e&}D-2R(8UV*d?1W*^o&tdsfgiF8BYd>6FWOF)_*smfA#(%;wgUmR) zYiMrdsWqC=(q!8!qO#bb-i<*Oe@C)O(KjX@L1%-u0~N9Gi$y1F{Z1!?_9`E-BvYRu zR^3PjIIUAdd203A-8^|K4Ds19rl}b+eR+Vb)X&UhZi^)2&>5smyek3v&w&>S++Qx5 z&S)DtUy;kSDz}pio5H>~UThwGyqd4L=ycqkU0elzJj$$p$X#rg<-Jkcd>0-0xAD#~ z0+?D~P&R(#mOV6GA_70=dUS*;3EivN%rze>;X7T=S;(B zWMpQP7(CG9$?EWThE2ZCTY7m7qQ5_iT+rRZ2GM8p?04ErYE;+JthcoXT2N$`n?hAk zUbXLx_n-O*7CdqCZ-iX2Hr8k#jioW0oR-qxGm!(iX(TYma*I-}pq&M|CmPJD3=_$& z$4@wK%F##Q@XV#qTfa#p%zTiq>*j$-Rcw)TUs)lh3 zX2L|o(cd%FGO)2K^PcBp^a<<=G$hwLfeiU1gwQhR)p*7}$CJ80@KAGKl~#$fdwjEE zs&j?5q%4Kk4@JurQ0_J5Q`CMVX6|O=+^8F%lBzTn0T;*f$+JyQ9X= z)VQ+5=qAVzYt^iCXm>ahGNmzF-mFWJh;j@?kp6)BKaK#w(yz7U3&h2VNTl%EHu3Vb zYSpi$(^KNXvb{8E7AaxqFEsDkvEpgYJx)1 zIH8DpwXV~`cx>7|$0=ox?Nyxne;l71ki>sy@HV@!r zGp@73^DsuMAIYP5v#<)G>V@1|P^hzH_l9D1Zr9uDN4oxKpj-6=~#4HRO>bia^-#r2q60d!>zV=n#}Iwf0B5~ZXS{bLB~+j!7?EM&sW5k2U4@Q6)F0?MCFySF(6ct0VBW{ zM4EeJNf1oUFHamkxd4G$my}_k0}612F%5KuDC1)Ta&7s>qSK*F%{=@r750ssgaVD2 zMeNSi&txSeP;qn71Qsf?Qov}K=rZ)=2O87xyX>R-xOem&C56p@jIaC1ExRpvbmmz; z%$C~77Ok`B^rx~6rxG_*bMVsqLQBW5LPE#KCKvxDj!5A}K@l&GjZK~ohYdpzTj|nW$9QIrz?WZ`3EqHD+v|P8dmMg-uXtWH~!o}tA2WBbUrpC={EQ?{BtLA@v*DFvvGnmSD!^l|Dx&iRPwNyW^3?^9l6;ev~<9eqer4 zZ#Xu%R9m<;itawI+l>TRfbzP8`B)9@pogZmz*K#%RPhhCnYFBg(6L5Tu1JlW*0`qom0!Cn|e82TxW zzh9zkaXJApUG#t8p{5oREdcl$KEj+K8CWvw)yoc;_Ca^TJ(j=04cx?flx+c`9GwLzk?8scBsuHiEWoBhZbGHsU{4pi1!n& z#O|m(c8)V*oXuemcoF`%_ZG*YiS*OKVbHxjnLN45X$PM67>%gCJn-ZN&p}p zRA~N?{1qXtEl4stmqr!A%^ng8Ho^2xWWmWX`>t-zb)|8&mJ^quV(-){BAuaRZ?6)(BApo+8(u

|2KZ&SJr(anq>}hq=oU zPzs;mz~2hxb=Pt42_XD!?pZ;n<*x-v3Z4n;_#Y8pAseog$M3zMzw61%6SyKbljea4|`Z`yE6E9^=y>Py*o$~Pi5 z(aunxfOqzi9n3Hakd+a&-~nY$v&~1ZriM`c9U$O>ljR=G_;67fAf0*isd$%E+7XVZ%?M-3B%2urdEp8g5+!4uzV z`6{ug@&dO_J5pAWCG&PrH5_n+f8S!J|$sT6opwR6^S~YLeXSHF=TgSPd z7Jg{9>V{rwYHeCU&LzU-Ef^RbZ9@JVsM+*Z!lYB{$lAlH!*7W<_zeG)b@3L`ts&R! z`_?~}F+CP55|&OvSO9L8t~AC16<|uLmY249QDBxtobhw>@FdU=tC0QcUqs^WLr(V#X z06SDv%O)6ZA7ELOwnTd9qqSRDDY*&dy@5usJ!kF20tfA;xy+$<*&}`oD>qdYhlD zyGTL5NJWZ-y*9b`WV=@GX`d&vX_;5rPR1Sb<0os4-xxdI$2+Og1%gfKeCi+~c8s5= zF8%Zd12sV@!xq1lt)EjjE)^0(bjv~6P=llbrWKbjCR}umD11L}P=u37=Lia081AZt zk*9!jgTerN6=_&U1U#GlslLQ#p-wGz!+$^D(0>tL$%@pb?5?qe=~O1^r)Plh zaX;T1zVG<}HBSVWJzc|h24iOy#iT1#x7$7Z!gs_504*M1lbnk8S}Cit`F zZ46v=9J#FpRAICp-z@(yoD`X~qw?NkueNfzkc!h_r@R{=uE34jAKzW74yG3v{;}~Q z^m<4qHke6}U%PvC7`3|O^arEYJz^SZK>f%h;Q0Rg>@mVyT|HWGqA7cg57(WGrS{YF zkDr>v*}hv=kuLZedL60L?A;hVq%_hh(xEVXS-sq@CdSF~dgL5RH3^f;J9M6>S4ya; zaS?;LE7JAqC7e1`h&Y)5ua393JauMV?Pg~N1(KZ?H@HYW)*{0)e)!%lH~o_ILk)Q9 zQBC^MX;gP9)5%1BN(JtE=@MsT{idG+eUD~2dIL&#ML3rGm2~$sZ|TMm>C366w}V8!$`tWLXp{`!Sa97p=8sN`F)^X$Rej(IV+Ht%1SHC@* z%ztOn>ovoW%VvT3tIsjv`TJI!T94WIpOn{OGQZ>p|7*p^9xzySDoMZYh))f3gkaW1 z$8Q?oe(^8r$a5@Xd3^m$h#>`_SM>^mezq**=bOkw%(}NWL{EqDb$5lhg3fSAiilmS zEct1t(NIy2LD8-TI2djJ)$@^pSFa%uW8=;^*MHyYebY1#s`;WyZG5*l_EDR)(4RqS zhjE@p@^E2di-l<+>UX&dZzL~5dFVuAbY4pHa+Sr zWfnj<Da|+2?XBtAltq7}Ld!{1m zs{CR!s~+2E_B;xEW+voWE%TVg@rxOAp!sn&f-yllH9-lw9$e@cG#<}VTGg0cnCwPC zLXaP@@pb=iYj&`l%2fwlF1aOfox8hnLmgL!e2Z=OhW~N!E|&}=4wdf*f=Ai)VLkyd zQIU^DY0L99PxcupCQdy(Aj7JP^3h+Ogf2PKi!lYMIGH;I8O~T9b6^%N7*kNX;_KXR zUYKjbu=!dPP1?~VaQH;%+1m90aeCuV0S~_|Vxt2`y`1(L&9T~_?|S!SYyC+oBE1Pz zg9*qJ_o%ZXKB7gYUucq~n`3Dx#geO&;o|MhsA%ApO2`v1OB37ZBfk;YC}cT+mIB$f zwR;ooMzKs&IKwbbivl(%j+JOu1XrMOL1t5_A~S#t@;?^>0#+QMPo)TQ5wx_JNjS`> z){DDD8jjmb3LRJD0VdOJgwZOzjv6?=0fuaWuBysfdNpb|8?hJvMlZYD$4;zasbi6m zUIi0oVE^pzW9#Q|X_9>2o=QmSQv+&@#eB}LIIc4aaX6Y?NC+Q zCPS~?n3SyZ~;q6!zBt58YSMM)RPFHL|1Wg_*=`|r6&F`n1|)XzE zxk!C+&pRz0Y)sE-awNVg7aWh`|tn9UA9v<_VI;&&2sQQW}@gyk)Xr=*@Am zs2^mbL&Dz_7aSJLrN^pKu61;AQmW?g^R3_vGxXEEwbIG9Qqq(|{J2FO0(s%Fl1ROnO%0>% zal+jm{!h4Cyp`i4h_>RHE6G+Us_Hh}alt`vV}Ipjcc zO=mHS&a*tk8Pf|O%|tIQ%PRLf#`T9`wwVgmh`w2{y8Gi3UlYZl@#IYYfhE*@`T`n)nCqR~Xfe~Z* zcSxOtJh$^KknhvL6V~oih)Ds1c*D-7An*L}9|L4WSc*DV`m{-PhVQOR8JG}49hC=> z#e(%qLL!m@%pi4*gy;jcO1_dT3<@|-HKW74K^IczCt-y|)$)0bPBrHaEM*7j$yp_P zToAQWke!gU!rv^FE=RX1JxmaFMDFGB+J6OVji9nDYbiddV(Wri@Z3W@Ch$I!m{olyl(3dO)_5`?e+T=)?ju)~A zD$PQUCW)Mf^?N+6O6`HMjGWW8fauEiw||-Hw#(1R{_TN#p82jgrAZn}L~4>g zF0r{CAsDEO;B{^LX*=J8o`I?4JCoO{X(cp-hZdn{w~PnD8Ghb9ItcHTT*S@HFJv06by zk1_I{Wc1v+%eV)8Qu}kD!&j6tHU$X?IHHYa$OnDdBsTSY8F>3ZPGs74mw9)K7UOg| z#L@C&W!Tb%Iw^SWPm-A}%8$OW6MM_O8L!jjj^KBfgFd^9H?m}1!N;A+fG?{vtJKg+ za>3hR?ptNznbKFP*z%-Fw*{%+jf#gQP+WQ1^*x_{`Paw2V3VuQW#3#N^qI)$|H@ed z91qHc+fJyPSDp!obTh^&sa zf*o$ZBqckG#?fZS&3iMoLimn!a|Mg4dP=0s^ei8+XkoLT?1L&532GLqLTQY2O13F zSN>Xj!>*TrhhXlY`0iP{bQ0oz2OA5}8RnxKHnb_Eu(mdbChDMUg3wMLxMyCQ&F`+6 zeMH*VK#HuBmV(c0bTwn%c6N4Qv|1q|{IaXjNPdTnrDQoE>?$d@blAqPoPzsP3!4exH|Xt+wi;p{3M6*HNUYj&)F;c zz5!2nMVA~YltNu+r>sqJ_E?_#NsfSsu+S_zS%dHpW^|^5(zZ$_+`OLvZ&y)3xbnB& zkI+!xbymD6$r9&(R{$NJWN$mz%K*>+gUrIl1_FWU%4qX);PmeA6r!QBHp=)tR$CWf zn?-4e=6z9hCZR?ck`5xYCR>WIsi7YY-&G?PcwMqtaA07u*YnxdVfgye<%ieXo{iVr zF}Uqzfa&n)Y!AcVzw#1!{PnRLU%>Z~Us0>lWTQjQDvJlhCpX{n=Py3J>e$7``s*t` zAzP8@NlUWjh#WTZzJLV&^dMirI7bLMx^J{3j&gNIk%|c5pzUclO@B{dBVikksXlpIT&7cV4k;f3_&3ZeFv7fMYWHDP=R2F32$mr0fZTBl}-oIA#1UE)6&Pf+ClO)6=2CHhzcVR^m zNc@G9#Wo(2R!P>#2-XB7Ig|utGAm|r;Y7$o*qm@pm~#hf_C_E3zQ3a{&dlx}OUKNY zrMldpE!OxgetkbpBHKFg_z)tLx(Zc!7aa#v20Zh9bd6Ogcii_+UhfzR4_)|OqqM!H z5?k5ZZGr7tm)cDc=vWPUNiTev;_TODcrKk-e(abQrT6jbwCfW4vkaOld*HvgpB7Hd zO!T0nIvZVx{=rGot1%{p?d{FxcZ|OyX0vql4B0Bc;{Ds2Ob)0*B{(`V-iu~-K~998 zj-b}PgW=LVwbjNm>@>rM1V01}AlIv!V6`qF<{J;t@8gIa%y92|{EvfsbzL6CMSUZP zT*jwlMr>;Bm0CHT;Ysp8dKt{0Yvu8g(lm$NdPL}W15LSQou%Y7=nRF_68#*pW#&$d zZ#wb;tabw_M+=H7);CWiXkz)`=8%Kt+dGUce!;6n_L3m@PDH{2+3Vvc!GDL)5>^erlkm4k)VDphPWB3RfQD5{*f*&!;? z8tL=Vb+u-kgx=3SO)r)hwRV%ArgJ%}6Mw}nXw9#z)ATqZlg;PLnjUUc8SDOt9_`(0ofPUw zYK0JE0>;#XSxD$F_UL3|MC-s^xlZ3mYg7-hTV{t2e=3nd3@!&{zKxF&%R^EE+6Z6a z)xObv2z=t?t1HeR46#^+F-i=KL8re64O71ASXu177OGS@a6ltMqxafX+H8t<;ra4ox!s12t)oc>dMjns-RgLzrx&DEF8)YXU(VAYu-Ro_opCp#(eW$n!NiQmJ+tv|)u!KbrW`DByWbr4C5;e8mZE#Ty~_uv zB|^@2)sfSOdqQ0}aHqA*$=;TDxcr0Drk;QTgkC0IJX4Ot#AE@L!KF8X9 zV;)7MqdTEgC>HZL{~NLXUhtB})_(Z@VF9`SX#JnQa80O4D0%bo1s<_Hg9i;~6jNFu zsN1X92)eU3E@ry91*ymL#Na+bJ{0m{o2iNTJo6orXHrI=mMzaWi#A&0=A#a-E6NtG z_wpPhmk32Y7FU-8YSM}h;4|j`^-l&kiPh`I@U6STs))QX-{7(V4#eu=D-Cq_z(n-F9UVahyb%!)=S z^cpj#_u&ZgGbkh!D*TD7(r|I1rb#f%ELNAFb%))sG;z+Rhun{cgbgl?rOJc9678W_WFeJ>Z=+;O#&r+-iW#V5$Xi~ z+$cbAJL*lFh3=<}=%Oex*J{&MygN{3fLMvb?n_9FU=-fiG*XfRYHIK0Cgz2N$2;0 znS?VIl#UTR(PE=9wB44%_6>nGL*N_g2eeO zDbeOQQArm2IZ^c%Y12lx5hzM15Q7lK5UZ5}cb0Z<1Y~6g5DU`*=80Y|mSAGmQ1ew? z%jgce`YaiSh_qqyB)Gu_NB!@HTx!KncMPH)jO3HJ@Wr<@v+UK(N$ipA91+`y zWa?hwyevOTI__=i8Jn{eeFjn8&qRi~Ow63I zHM*qByT5;38AI`NbFPRv5k%~i-CZ2!Z8XN!^|}VPpRT_XCaZ7HHLDfM#t4aB%Vi6? zX+2gK=OS9iz{^bbv7-@1^u*OsY;eMH`mGc6NCQIisLf`QW4FA+)tF3WMGN9R3B%gr zUAe!+Tl957xE|F|=NOjoa^pj)DIHy2pF~t#%<_9`2W`09z(ds>hXO&1wK{7zU9-SB zsx>|IRa^qeEq+%2{8}m^e{lktN4LED1`E_#qZ-|!X+(OrxQ+mbg>KjHGhSgfs@#w+MPk%X43$V||)fBQ3d%5S5rIis$5mQ4FE~{lu zPQ9Yzp4Q&VN|$d(?4hb%)lX&oIB04W>@=$XPeHp(ogr?=EqQ26 zUz**NVqTnL1&0Jy5MQTm@Ds=w6W}-L)u5nRUIJ-H!nqS%{s~ii0LS@Nik2b+_ak$- zX_r%=MklVL!-e|~MFZAsmw5U_U4YdwVi)_}fPDYet*-b+(5D!X$#Bg)vq1|CDqXn~ zE_s4Nh$eslWDe=0OVF^ALpGysv-JH;^^X0VaSNJP?hvN^Kd8a&|3nAxc*;+q z$}gWogVD_+XObmuUe{4qr)Dzc8Egw;I%Rd^iHf7$!BObF?BQzMLg;8#S1B+4<0JPZ zDtB|9N4r`LWWocn)8UzpPlq1oU{2nVwsY3pe>F)5c|NHa9UpdPW;tj~_?!XndKTly zs>^G_$|Pb8h3rO;bE5OxtT=g{C+?#6^{oQ`#KL#@jR^SR;ncTE`a4rVn@ykssU9E- z#a*2&5v>G)39Y&h!i*~QDz3ahIrbF8A7ql~Bk5IbMiPpl-D`qSy!SJ@hnv}#ucm_& zBFRiU$)h{TFE2wpjn0z+uR#kHtXky;5#mPRnBdf&bn-;p%ff0$m{7ZnzK9vC-@ne5 z=HB22c|QdM2YT6ok|t)>|1|(%d+VxzD6_baF|yAVCh8ATK#D3`6fij=70F=9fu5Lw z7mT8KeTA6ljv#kWc=QRhWud`z7Ex04w$@Z3F~m%- z3PXLjsX7M-KX#c;g`A@o_5G1N*6xK!1l>|A{ddT8>KsKE4g5a)!NRt^q@H-*F0!eY ze^;v*{8Nu#?QvniylQ+E)ZA9%h0?E%qnK*gRRA0IJ0`By`HW};2M7A+_!YCLKYBUE zz9SXPtXmx<;`6}aVu4S%2t}>-Tp2?T&)u6DI3yz8$qV^$f>DoTja${ zItaoi1{05zn$ywD5TVZSK7*-yPjy?TG0-xcy?~_T<2p0!`6ri;1!vVU+$0CcGIK&| zZbVUKheCLAp5`mEdz-eohwQDxjf7gN zB5@RYABOi_H0jD#YB!hU8JrwTIx9~E>AC&C(GK5o8`47O5^)vv*<>>Yvz9yZlzOg}FA-4F!`%dH?Q=H5hF&vSYh)Mt9w>PhuF#JizdOr%RN)5uNSL(QWdGf0OwEh_>-!UKjPHKD_j zI2fdd;7&ZXG6c-HohII`Y;aTUe%BD;7?+&YBU*8i1i`-ReuPyfPdd%dxz^&O4B?4V!r8PVG64$})7#c0fJW8AWmonsjTz*!Q@vdLHgaI3(S+s>R$Xm@Kr$CXc4v;o} zWi0BzEiQSPj`+1)F4OUT^^kC<*TdfBMDo6G8J9F_&hPO|u=j5I+ejUYF9e&GfS3A{ zli<+s{H zqAd{Ih2gckMJM3A3&+(eRBcB*Ss!kqV9rUou{Ltp#D-3~Ci~qIUoow+(C^-WsN6;M z>>p|>9btuLL=QYUM{G=A3sMLQJI4L~m`{ zB)BB;o%m1)0%}8wiTDHtv)fXBoN;a#_Tj?=ZZ0MQbq{rfU$QsP)L{C%FT+H@IQJrH zXqUsByjb|$Y79mG6lzI$)_WXE?MBf5h6W-DDFR7yb&OxwAmv*bl_tAha#Mm3NbZc% zqBXGmRVK453vVfQs;QY@>B}7ygiCMMKGJH?nfaqqulL6A2}^N*V!O7nBX;AZJBb>H zXWjpa2$)j!BF*-KL29aHN&N3jXQ5nQO3{W`+5TV1i7NL>y7UIwM+DG5FpnE~!AU@&_MV>)d}1i%~* zS&=~ckR>Q#BzK#-fR?$U_1;_5>1NNYR;Mjmjzk9P;Ia5dS{Z4X`@#b*v55UDl%i}< zzqQD~)lDmVuy>91B#WXGch5IZDkZ>`X(6>>X|FK~uwTlc6!(tB^X|7ei^UOZVT zGR}zSjQ?x}^S1zuu8UH!_ceBB>gOYWDy03Be}1VC#FrWXhW3X)Ua5S<_#xaoZ9|(e z9eeNKVie9>P9Cb6!$23NKUhB=|2fop7xyf7+{!%5%6eWLbPQw!syWjThYFBB^3YgS zf_2xV6;SJ(X8Wc-Q$FeqesDLIO7WErq!1Xms(NgJmZR>m%+W3&}S9|9jPI~xCu zQK^Vcwm*pV9q-{g_70$}dGE~op5UuE{$t^DalEi+p0&7YTW)*pQRL=ntg^iW#GZ3 zSU-P@y!rZ{i}my5Z9P~0GGH5SbjJBFgeA!Qcur+DTWj8=L?(dXr@9(0XeGTu95Q_C ztp$-2=Ofo}2J_D(Qf({}!);)=9wt;mIi-n4>F^ahl(wYr-^zGqWaURA6Z!qW^vjvb z?%moXZ#!!|h26ul{{tQ=WpS`zO+R)^WAHO4kt1q%o@4u8R*IRO+>et8dxnD*Q)?~e z8TZ-rq*)M~Pq+*VDhr0pNRpiu^y1om?yF7qLT_WDo!yOo=`M{`8hC#0b#!D7HW7`I z#Nz`-`WS_b&{KA3S2VD)MzXNC4MJKKW{`u}>_{U|i$Q&d2Zbt=- zL)wL`97c?l?Q%lI2dtXXtW=qIfAhUsu_<7}rGp}j5x4m*d<#>R_gIoY)n6lSe5~i~ z@YG*jiG2vBG&Sbt)Ey+I*E4j)*^p~74ib;en=p>2cH)-g64m%O4M%_>ggXna=~P-$?(^YU}9 zfT$$qbDN!$5a}}BaXs?aM7;*sS?&x(lRrCOBKzG#7%t=aQ$rb~lC50KIs^a4st@@< z4*L4*Y6)aX3;rJf|3Co0LM#=K%{D93_C!(}*IQ3xDjIa^q=w%lWSW4K{<}(jbx|<+ zYQsQ!Q!HJs#$|qM=DLtToi!5KAZpdmDq3Jd94BX4LD&K2vQUusaAF>J=96B zW`UN}m?>6E38urfrmlBW=$l8S1%xm(BR!UiI7zr-UNdXvb@KUte*{d6Wiwis(NZF3 z3w#-H<3&rT`yq!>|pAUTGBkb6@i&CjX z#>)`LI)gz8K^#k>DA6P(Q_Hb3Sr0Rc08L<;Dqx~C0Lc)V+h6x1EOctHk%k`GmW5#& z#4<)I1IKlUWT=s^Lg08dMih}G2}&voxeQ4X<9S)?rb)RxPIFTc+cF5kh-!75?#?!D zf7knX?8*C)amYf6Xr+eu`5kPB5!`CT*Ra96E9g7s-A1Kg`*I z5w5sw9k;*zEj;wtQ~d0g_w(^P-o@U&GP}3$Bv&f2aNZoYzO2f#NJ&yu@p>(A?JE~XlZF--;Q0-sPTqh{Fs)E zMWI;4@f?N+M^Hh7pZ@q~#8MI^0?YCAc0|eZMqNt~g%Q)*0$~7hTGFG9yXUDl`e+k% zkVm;eBJ6)Ab>#37i7c@c$f>3YNrg-cP9~|3Gy)k0?-pc25JodyUR;|4h z!?4KaT#ET$aQaja*-{JH)(#T4L{w}i@dIS6r?;-_vTNH8maSTel#0gW1Q%_%jMFDh zqLP>hp_7;mOB;QKLE=~>=%BB{g2n9Gy_ey^I;NDMA_57uGri=qS*+3?7A#)Iz`y{0 zwMuj6OjOpPT&Xh9Kfub1)^gv|o9Sx=l$OrIi-wu#@1;IoL6wJD`??!Ad9IK4ws!7) zaVLf_c;_|iX(<$l8V%-mck;6rcJR-SzsxK<=F@k+6UT9=RU?+R7g;>Boj?4KCm5{7 z%*tn2(9uj+F+*))f}h_1Am90)pJhpVk%u3CjP9(-U2naS6N6*a#)ip;dzWQqGx#ymX|Ce9n zx9q&u0Q?3VVY#tN^=(S%<-cnhC{y5|r~9!|WF3=8s?_ic2vP!&AbHi`F=M7OjCA#7 zTLz94w0aK5`bT(j&oO4r>gK?)lRUMh$h$9F!B3vtj34;a8v)sjN3G$raN%O|UZhT( zJSDEa>I#|yiI?#Z(jty^sK;1&lFIlYv0&bOYDPPrW#Jj%Cz>U%(3m=zPCac?vnd3+ zxsd=e(T@hH({W8hYyB+)a-KHNHi8J(GN?rg3$P56#4wnm2s;8|!=xM=NC{{A&T-%4 z&$4CDL1Kv*9(xeNkg=M}TJRGhDWDgQ`~RVxn4S{=y|JTd;t$ z;}K)kaQZqsbnp;K6yp0nN=ky%kUV8jRT}coRMP9zhDis`8L66BPiF>)26@x#*0b)y z3pjH42yLy+T0d=ASeA)p=!VaBJyhs(+f5dhtudr=qNtQdDR~xcZLK)@0u4W8+5FiU zLNPn)X2V)bO;oF*Tq*OHU;H#V12RsArClxTI(mv(vuCqy>njvW&8%C0DLZ%XWps3m zwU?}=Uazrd=Ps_f>I(WsMj0L+VfE_O?BBhMM!il)_birncR}P6#gc_{W)n|Vc+bZ7 z(~)-(wxwEHTE%_$Kftl0$GGEvypPSVY-9hy?`S-oFqz`o3(lwdYLjou`cE5hU93+T z#+m-JVQAieM_V(VmtlBhY}!mKQyP<*251?EK^Vmh3=RW|MkAoTtp(dM=^q-=z5}Vf zCAMW@+BPytn3$N*83|EL=ZtntQ_$Nth-qpGhDdR?wqr3eGD0?!(bueDP%e*a>P;%& zNu(l?a+=?52th9EA%rnav&!YO^z`&muQ%{KPiJC;k#2^C_K_r!P6alAY&MHwS$M8P zoJgwGDnSrZ$Y-@VFx6m}%N1_E`HlR^=RVJlJ=^K-Y~{k`7tr57KqlWxkSHE`WgolG z43cq865${OIHpM@l)UibW)?1(PhBVuA3Df}b(auCiQXmxkp#y~r2?ioO)slYPO|8V z>sVnL42_IZ9-qMTG8mSLD-`=q9OHtuMV5CIcw(f7oM+Hzgd97*lhkLkuJj0Hor$`KgMGNO)c?P{B<77OS zIc+7f8Jn&94^U`oqQ5-BV0l8dSc#Z3yBpIom1)Exm&wpIG9lJo`$k$?npm@T4HwRA zrc}tXVD5Y_T)vP8ANVl~ZoG<3Pd>r$z&ZZt6L<0WrmcMaZ@!J^wN9gD8$p2U>WyX; zYp_6)Xwk~Txhib03ZNKL_t(3s7_XS-4z$Bj*b$)-t?S!{qACs90i;`H$&zJbCaeEv?PuGaf=gTOp5% zO&%{#p?c?63chG;X4=0zyPzt{~fgi+7h9Os7v7V@HF;70bgF9}z8j{oG zZ7-F(sFV+^6K@kmN}$n-J;N~dL?Vr=w***dqpxQ`GSo}#=1^{ysvk|ufFxiEgIH^(T4i=`WL!ABaUNCAo6{bFi^(S#8R84VkxJ!|58d41xb`3B@k)mwP{)W-|W3-m}NW3Er{Dl^M_+g07wMH}eGHv)th8YBh@2_zv2keNrLXNDQMnRz5;Kr3Wd7|jgQ zA`pXs20_yew6Ch}>gsY?-e;MtN^h?_CL;DjoSV(;YIddl#G~!_Qcq>&y_I?HIT7#s zfBz(B8q**N$SJ9wDD^_VTg<%!WD=@C(GFb)*3hEi6h!8ArHUhwLCR)9^KyO&|1$SH%3a9vZkr3Eh3+1 zK_>_;iM1w{U0YAsB>(?me^E7Z16R^~b5mE|HoIJ-1C(cnW=2_9z#)sbf zPM#RK#NiiSq`Rw&J$LTr`0*1=OwF=q@7+|Zi<~)miU%HeH4`&4EY8ldd*=?$96d(V zXfiM~#PFImj9(jtsEI`~qZ8tKm8SyD#{N#0=B9*_aP-&+gi{{3MAbjuZUAbD9?A>@1VSrC+xa#hc6Yp#&iX zaqR9nshr_JOZ=^kW%K6s)M_=xZjLiIH&4CMV9n}bYPC9k;JZ{{Tm$U+feR`#hC-o$ zwNS|Usx6OO-x zGx^Fu6|Kp&wIOsuXJ;qvot^Hp%^K(8w(Z=Wp66fPwSzbP&8HpJ1xL{upPJ?qpZTx6 z`>k)_7k=_#zIWg-Pai)^S5G%e2u_cjV&D2fE>BFe(2P-O%Gb3F3v@8b`@@;IOP;^!Ftz*`vTY(wnX#ryBu zK}RW15QhBQUwl7XRt|9T@+i~wmi4&)jxy>gAYiD{$|A~BjhuL{6e;;04)g0MmyEoPvY+Y;qJFc7dNMR|Fomm^K;KS1^Q zfo9lX@ zoM&Nfo|{v1ylKxS&P~<$jo<%Mw!i8=E?&6Icn+h1~qJQkNp21N|1et}MRNR=HqV~1Vp|{^p|GozZ zr64kvrm^ItAh9hzwWV$h!Wyb3;MvjJ{D=3vp2eWV$?q3*Abtu-Lf*>nSc$pUFxFoc9cJlW3{|wWy;@qXH z{Pr*ZET=Aw^6jS&Qts+TOAjjqCoW&-J^${L2rs0qt%4WF*eG&gLD}z!s0*A-0k=ADU@GpMAF4pSe+kgLU+AHnMEiO`TL`dlz zSX4$~F(wngk~sji#B4%f$-<+uYhbZiE`TMDBHG)^gn?qITBB4h;(Kbj@HfUy38cz6 z^TN8sX(=+_bU~7)&ebPPmo)={kj@TNij2SSgttkWptA&JZ43ri@E5)82(Xqk)ugf8 zdsHT}7ZOaWk)F3q;jkv<(#6Z<^94FO+K|$T8@swXSX`=6t2cfi=*hVNdA(?=Mh1iHF9Tr<*)2}9?em82mIz1d+xf6GiOgbYSQ8& zr!HQj*x3gPJYQi_OPU%M7N)2zRoQp%y*%^uvuxhFm9?8TGdnR!Ae~QI3zWcGgb1)w z5T%-Osf}W(Oruff7p>1r#pva7=GwL=^{f1UpJ5|vVk znkw+2zxXOY{f2uuGhGKi;C7Vod*439o9@`ivDt*;zSr~U>6_H8;Mt24%-0jP^tbW& zvoCVy)LDN1z3*iE`jxEj?_#!@Qt}nG_3OBCYl1C)La{!__^q2H%{p&+^BZ~a&K?GGNp68LLUgFcA{~yfF&x@;9u8|rbs!<^2nHSD-@#+{}t^i~iCPGjtm#{iH8S^i$vGFMjt|S^euD;LBh88ix)YVsUbU)hk!9Z_hT1PAFH(CQ3Awwla`}RLRE4loO42xyz5RWrrKd}^7GV%r2e7#SIMb-wpMC3n;`=Y1Ln)7$dY#1^ zw^-lbflgD(#XM1BF{&)qZQq06yF#qEwZPQC0P6<(7#`@Qr>~D!zxqB3g(87h$SMFg z{fCs}Cr0?Y$DhV;TTRvYn0yJpXN5a!W+q96&#m!kHmn+;y}d%3BqULjiAkqT8mmpx zj1pe=&_lfO9S)J^O#wv@x+0{JowEo^V`4j)BN~*A4Z5$_OoO< zCOo2Oo~=8JK$2y|l&LPx@Z|R&W%JG*tlPSkbC)hLc5RI7mo8H2?4VLC5(I`qxeYQm zDxJjWw29VEC>%wO>KOR{Krt^QN(Fd+KHEDqY1+*8RE1OlCcCfxS5%N2vke`4xWI#?-8elv4c-A zxOxqx!8NGZg~Nao*6K_&D1=MR)n3S_k6xoTU!!wyJ&#?T;Y%lP(pD-ED9LADyvo$V z67Sg5%NuuZrtg!#gNY;N7nf)&=9pPnWaaS6O!sGL&-+=C2pCP^dE8ixs747gAD{$I zTq}%2FLAUWZJpI$-MTO;g>yEN(vgFV1!+Ne0pk95P-yFANABK+@H}4l+#|f>&W(KZ$6n8|qbIm`$42~*euzgO`yR&+zeJ_2M5;Au z;;agjtk`L*R6yjYR+qrkh@+;X736YwK|s`K(m%YC`qC2BMw48jgpiIp6vq+1@+h~p zk;btr8iIgSYqWN`0L4-PKMa|jo&#Ld7AFa9r2?fwjz$z=kt9jFjO0q`^aq~rlMnOU zyK6gV$LFZlYINijzO-nm$d}6C2N(;*Qi;S^49;yv;GCgsMjKH$S0-y6s%?cpTSF)n zo|2^66>U08;8jVJN+D#+y4AdJ;w*c%u15-)X#+BHm(j%9V6DNE&Q(ZBOHP4KVyrgg ze2ED>iYrziq~K=V;K>l-L8-SwvCrMNmu`(wuPw25?HW#>J;(gg694`ef11TebNJ9p zRBJW%-FGi(y~fdFCwR^M_b@pz&dg$!EnBy6;>a;{oU(G=8u|zNIr#L`RN6b)y?Z-J z9A}87M%Rn{%1=DR#+56$c;OsTy)II%`ITS&FdzEBFL3Da0S+8E_o3WXB0w{M`+1V2OiJPm*d%<&pyz1k7Z#BdjIN zh4l5eqoiv>3*(*dc-h0Z0Yv$K<~E|{2{MrVzQ z)+tJbklk}(E(gkUQw3UH;R0Vdl&@IGQ?ECdwGMHduyO55e(hiVsyKb_ls$6nl!%%Q zHmqOA+O_LwB$^j*{tb!eAuukxLJCL??WGFUMuT&w&v4Iu_j35~OAHV8vw7oc8mS@h zeG&`S^O07&246_DF<4_69~&c|3-Jp@)~#R5%Apk;KYf8_vq|q@A3lbww{k$P-U zo=XE3Nt1nd-pRf@_wWaw`h9!wg^JJ?tkG5*BaF=>aZ-;;rEHC{)*2(M5cYp6KZUSi zA#c+-5owZ&APB7VJS&V5Su(aDjd{<%cq@;5_gOypyMIK__B)aD#5e7Xl?OTfU#~$7{?95pa^)(&dt!?*2b(* z=rBjSZ>dF#)T%}FqK}GWx_Wz1N>VC>NSSwzI;q>IrSIcKny&sq4jwznx1Kz}$3FZ4 zhCAE1IX=mir6$4;!SlE^G0px1huOMmEun9zR5~$6(`eLD$|q`8@w{N!;<%%$9~p)O z`F3Wf7MWjK!lo%vtxC0?kSiE^*Y~n*`vyEI7@wMFv2Gk4Rye_Ln%d>!{~x04v>f@2 zPBNR&tclFr=!}jLQXx@j9sl3o;QwJ6W69@p6qS5M2%N1~8h{^ymCsj{RSIomlmg#V zBv_OXRD6Y!f}H1^HBw^9a1{L#b2jT&lknnHUAL`{-3<+jOFZ#EGY*7kQJa45KQ zD}sX;ZX%Q-=Q-qBWnne3&MZm+i6vB$d2R4LA74pynqq`<2sDlsFw{{YZretbYMPn- zp%Q}FIER|V8q&;N!njQz;dw08Eg$>i|IWX7^J{rvT`%u_&2GAKA*)voa_IC$-u9k< zN&n8hJo2sYkmyYKDkakMD3?lXS-*z1N{LuoUOIA&TQ_fF;)tHkc6M&t#K^fz#Em*P zuiv0l?jn~Yq&jgDDQ)N*TtU5BqYy?|7L`FhOlsaYz4BIheChT*|MHf>xFLUQE02N}I|neXji zL9w%onVA_PZ9od7aY?jB${%!~1YDsnl|<+itia%S&wj=`SHdMRW^5EkS<;5u+%)fh z>ucGuaV;kve-@Lu{#eLtR25{YjA0O9WabTyCDw+HQh}oH5MP^7)v%EF{ACN=Oae|E zYlemfS>4;t+3U9%92#Qnihh&=l{C10;|32t^d=g$8mEqruy@}+=k_x@%a)xxIC=CK zNh4y-rVaG0Si!+3pQ5d;gROV$;MmclRBLsTD8g!kjUwLt=-0_5RRZ6mudj>6TFjTe z_;-Bf&;A^gv)Bu>;G$3|{2(AnQ<69)$Y?kQL8)A(y0l1QEy^0Q0TV3(z3=;Ityx&C za(v{hYwXe#KM33*XAH_yv@)=zaF)N#D9QwsP-`?%O5*!I#>8%KNK+>g)+uS`;uFU) zbMHsIr#jG-23VWuof{e&_}6U z=Gu+h1b#r@&=5hXmnaR8zDI(p*tv=xdpqljuVqFiZbzTRX$ zF^D8WWYovVB-upP-P^tp+#TxT)4{R zi8)?4b&#Q_2)I9XGgnYm|k2h~G0vY1>{XRPc0)REi|7+gfc}T)cXfaw#wR`?|O} zHpTe(gxIom6NN%aG@DH;r6NfULR!d*e`AbuU~@VrE2Y5meJg~(4?G+C9=`7rB`L+c zL+hW}e}Fr-u4m_(T|9E)I_uj?{K)-#85tR2YIcFtGkAW1GncNjxKyXDyBnP^k#FxL zrxX+8llWeU5I#v#XK`_cv74jBiLqtSh!Sk41sB-N2=eX}}??Uwq@|&OiTYlx;Z{f$@^ZL8O5n(J87|5@q=@n$@u=MwfF)etuxNET^0ygt?BEm@UfqJ2e;;H zT$``)XOF+gbVD1|3NiuVWSUTm_58%jh-M3XWY`V5vTiRX$zim2_`k z$>P=X9J_pp(djBtq8VH{#Ne($Ze6{K(kY=3BuRo!V;cE(_T2X%&pz=aNgOk@dIR~M zUap@#NxoDfES8y=p5@%tn_Qh*Vs@#)?92`BeAV52{i~1i-1!^K&o2-)YHZrIo20Fu zTA+xmrWtE)-&o-J%LlR6Qt9nu*zmt6i5WIHl$e- z+Dr^_5)*5KFxt^kv@>K-IIGh*6KKjXN8Xd1Jb99#fnM55MNVD0j#QF=_mK}WBMU@P z#Fa`v#`LH9oso~;v`9&GPGemeFFm=eClaBI=k4kYX|3!9Y>^4%;njz zXAj+-?JSIq@*D4d11tM`nVy@a($>!Ro_d-Kr%&>cU-$^m9N5oqeC&5J3YbO(0ZJ+A z^}3_LfTQaq2?$pN=`=+t&)H*&m#I6}m~5is<0f7P-}jd_1)j<%Y1TCZQaR7`D0aeo zG8Z4CB~hd4vI2x_(1KjJEHX~hG@BThWr|R%m`{~*cAYJkvCNh+<>mj=8oQh+psdp= zAOuMqXAPta>q?Upq`>!s%!Q0hktdKcD|kH*qYa)%Mm=k}CAs%;pMOhA;pl^Ll92a2 z=H?c7*Sp@ypM2_5ymaIM)6)~&dB>f^NzA~|T6~q~uOEAY=g*E}EL2lx)2pP!%Z1#$ zc9Y3l<20KwqZco+>yDjR+oBsfKtWiG%mUY>lB75aRkK#Z_dE)fHg4V;=i=BD;e5o} zwX0A;$o$k4&4qcodV08YYJ}3jO4?Tplb9H7EQz%)^*3v4TX`;02%^+bkdmIh9vVHp zbOn-!MSW7+wQ4-@Ep_CF>A(@z%;@{l2j`!Wan@>M+h-c1>^4CB2Rt7pMeC&}I zICS|oKenZpv1-bZYZH9#qd&!g{rf3*bkNscWN~4EeCRViwnR{yp|jA&y}P!saQhmQ z)3fxg804XSyZP#4pJI0OGJo*vKSwcN;Omb+&cuyTzWK;kn46m6J@;+l?1ihG7&%L> zP;ib=0(yJ9Fxq+T=L{wp)UFss&;y6 zR>-WI%}97oS7VL)yE|{Jvw;O6giuP^I2N+1Q-n|mfw)z>$-?}csMo3}DYw3dIut{=+}TuE8Q>W7qA(_=Kp| zo6OHwMQv#bl!xz!%+Jq*=TR=VkKr(FV@crv<=wK@wB6{KkcDSfO-GrgdnffCO8LkQ=b z_K#iGg77@b<#P8w`bGcD*DDRc55ZbYjZSgGJgYUH#CgFRwan-DvtX>&p^{36di&Ca zhb_gXMWtW)z}7$j03ZNKL_t(W`YRo$CmBz=q+;Jw=s4#2M;~F$9eZdST#ZO#8rmW- zC}HtUYZG>p0wKvl&zv&{xZ*yPf`)myuqb#QQb44QORyEnjf0g(dnsf|NBrjBJEXC_QhuiizUiyH*@3m7^9E<9jx0BpJZW{q`5$>JdPbc%;3NP!@~nij*m0EqKC!#1ynBNz%$SBQxCtLZ+zzo4n6xU z|M6e{66@am5TE$WUol&2;(5+4?Zoku-0`Y?q-nx|{V%ZNp8I)W|9*Dt-i=xGIsD>F zc=@smL$EsY<#z>>0E|enam16SE@2SN&dgD(H&}M4$qKj@SYnMqWS_fZm^eGnjO&r< zHryE2z23uD3Y{iIjRvcGI~eZor?;b>#YT)$5+zlJT)XDY8jUs@gTRv_EA(1FupxEI zW|tF@A+D)4t{}zb5V$#jAXI|DyOWM`i4&*K(d*?{XvEx{T_lbpj*OgT@2mE)xUj(D z^b8xfZR6s|DdI-N@Y>Z34iEC;v-@4~ziks|jvm3*>lh@fH*Wxw@YGY!((b`;|K~rZ zs~Fnx@!P_r5sQm;y1F{~)6aaCxrIf7ARyHi-}9(78mK5D$;97DoS=1z=X=y^uHbQK zz2m>9%a)iwfTqhV2Y^=d=|Y0WC6UWXrA~XGJdY%D^eW}~8LH`W zGIZBBSiIG7GXdaL8gt9}=sNbGudUh67EYsD~#lS#6=T3~!SgNve!#ZcdI6lLr(NR>T6XS(MCPm`F z81sMOJ0!;7OE-lXEElm@;zU!6ogGYZaON^6 zE?nlMkX$`+gq#-q+S}j7caNUs@TD7k<=_Y(c*E5TZjZ6DyKLJFp}2ol znWLvK@b_OBW!JWioIH7kw!R_W`JOIz@7PW>)XT%~{80oxuYUDDzV+xgDdjwlzI2#@ z?vNjU*PHp?69@T=zx)zmsSF6_7pf$2j3))PY87n-Vd&$Bu0d2vWWbQq{8%epU{@6L zs=eFUxVFz8K73p}{MP$zTRF$p?K{NA^&1)L@8)tGyKABi#>-*60&|NISFewYiJ2;D zp+Tb&apBT+Y-;G~?WWOeVuWkZ(FtfRtWK9F-_}~;Wv*MErx3~`O;V)iVJtM7kx1i+ z?K`&G*T3P-;=u7g=ehj{dHaK}rcf&K<>!tPh6UE&bw8n0B-Y}2f)iu2oSIl+!a#oyleaE1Ju{CV7D%F)VyTktCo$DnW2Prrm>Nef__VL=C-f!d zQl3JwK;SFZty@R2Tr$^2uge=ZVj8tNwQ7xg=+Uh#Z@+H~h4vl_l@1<1e41x2-zF>- zNlWc~;iM44-vLP!s5qpT5d0iZ1e-?kj&{2U@X z-;7Q$I?2wjR%XD2t#boL#5l7ERUFRK2cR+c9?AUh&hLn==YJ;TNpc?zy`{-Y}3SqO~P`bb{bmA-$ zEm$eQmiW%WmoUcA)6?aO$yU*4Eka4O6<~GNNSN$1g;pq)v!8WWJyV-Nt8m96!hmwA zL}U%``?nuwvDqZ&OFW@6bXzZHF`879y4eBB>g9kpX*3!^WE_<%2m?pI5nz=fiDHB{ zSmi=v;w*XB&zjAfW8=hW%C;TbiPDtYW4GCR_ub6T&$BQy&4#VpxODOq^+rVh%9RWb z4{`X}=P2ciY}~$ubEi(B>k--t)@nS-Bdm(P_%u+=9CT#$=6D%m3fe)MQ4la-4X% zd}J+$`Lz;rjSCJlnP?Z`{J&dBzQ}~YEsIdsJh;)hkOG}*l&8?zX43;l%@9($qFQTg z%Z9^gy~%)goCi1Vq0XK?VO%zW(N2#dm0WHNl#poQnv<612*?tQEg-WXGk14Hah!#a zc?7=iUXwlRGP`f1W<(J9q}rf_B#I-p?%2*l550}iYnSZ3_uR!>A9_ffJAH&WwzPMy z;NX>Uj!rf3d>;waBj<>8_4*jk?|+f)JGZiJ$7U=};G3k0YkFFHNH(PsQsGMnoVZ5V zUE7|n9@cN#K*1A4al*-?M8L92YKLAxTo_NTx0MP@=WdDy7Elk3YDi5Clrl zU3Ox}#af+3ZSa&J$$%b_Q8>vOKV#i9nHWnP$E@k^<@ogp#%E@!rEufM7|(v~5kB#W z-=eRroy0&S0}h(j>+RiBf``A0U9m#VQDQKZLmunR?49)=`pDZA7eEy^c-WwsG#_C@Lrr zTMtlF+S=U&!8$i7>-+SsUB_?y(O)Ct8ne?=B+ZCMwMw!uLlVcFI(0#mDrL7<`k`w{ zb^7vzs>LJ`cG>RO7)u&O!X!?x8WeJfVmn59Jn`aLaqjvIZCmc*@$Ws&*S`B4#f{t0 z?fuju>!$8;j8L8v^b0{yC}Wf%(J3w2szI=J%^JG9d+6^US~d?Tl?q(FdX4WLI*--{ zPp34h3;0SA3klZH-O+*3DJxbCuw(mX+h{b!)YPOXZx&Py2UjIChI0thRB7UqM2s2AM3c@ z>GJov4NywyoQH%!7=yIV+EQhLMwwXwDj`sra9IjLl7+z749y(uYNzL2KSiV21Z(h> z!m}15B%X9rjaay_AL}XN)KK;nHdVygXs;D^mSntTq##XP@gM2TYSFq)AqYcm9r`}W zh2zM#eUN;)LXyUrDA3>w=cd%&);fx_%8w95FdH#n3<>^@VAsrl!zQgQ3-{c=DP3{KStw zge`WkV(nUHrzYtv7aXs@T;ioeFR}ZcyFo~f9XZOr`|e|Dex5Xmi490$5ozLLT7+<) zjc_)r0ByxG32rKabyl*jSX4;s#Fj!z$T-_N(*U5|W~!9RC>^djEJ))%AMJ#~o^t4L zE!KqXU3BC8<2`FIX^N48#Aw$yEH^7Q^S>9%4p34G0_l*|NV`KbSZ;hR2!-?=eM8uc zvL>9kb7<>M3b~N+TerD!@glqT?PGCfn%crV8@6ua^2i8Ll(1suFulWr9C+qgdMaf$ z?b^x6$Vp_ihLn=wjT

6lujP7t+NSgPSEm$PS&%e@DVXWsbM5~oM!#Z%9o;qm9r&G$ zvB~V7cU%-RS>t(9IId$dnVgVPiDEuWPiKxu8(NJJ*YjArX^jb+3!=NH%fw+wwN?|- zEtn+Eh+NiZ*Y-6S>4~L7cf7wg9=gyytqx+BGxH)E*8oc#g@8sq; zz7JS7eGs(j6Szt;*grrsNQjXHS`$Q}y~h&0@}44OYK&l~PEn#MxSrilQZ0-@Wd6U_ ze*b@3FE#+bVg2(zfA+d#9H#;dy0(f5NjI*5~V?5&pZA6TF|1MHYCf+dV%9CI}}(J zP867Q%3!Z8N*f8w-{sI*btg!zd*PoSYrk+BphR2o|+RJBSz>S)VX64Ok|dr5$NYKQa#4yh9X5NU4xA6^sd}R_h!* zc$8c|$JF%fihZl&x(F$8UC(MFj3EwMXl*FubF`ZwBq6ae$V}FXfz#l&&T=Ok*RSS^ zD=sp{&La2U|ERe2M|bnnJAO&AkY{A|5PkhUMD3P{VnfZ#Ghb^{R4&@U`1mBRxb7-4 zNuA?|9;2_jgl<;p=qwPTIdgWJYv1&05!Dx1-J3NZeDB*t#&sF1)R>-`!Swf2T(<=w zBy(h#tJQz4pa_K^>j-32rFLWwYlnuYR_h$w^Bh^nr6HiZzn@k+e)90soM{UR$|o`kQE6fPEKw%U)R{B%3=UFl2eciZmh{kmmWGB% zICQUD&BWvc36i!pR2CM<6+7@EJB3?p1hkTrRvbt6IdrXX&K5?JIE)ydT|~z*MF-ye z`>*2-Z~Fk%T7&an^V|IS-+Y|A?th3M-uW;Z!$M?ek~Y$lqmaph@E}bqZfM0lhi2%c z&5!PRM9hqj;z)R6|ECa6hR2_HmJ470DqN)ytp-80LM#)yvo6mZKFRz4>6>ULL+{Wq zXAd2qRPH2b2h?V!D6ikf@P+-bIL)yqAESF|646+s-7FFHt)*&witTxP9T8V%s4v#2 zqo89oP2r*2E$UHBpAMKfJB7*?S%2|WwDM)*`5ET-Jw-4-!3Dc6;>1FOT4IQz0H@f& znInhr;x;JBH-300o!#9yy(26nk|eSgo2pP^!Fc@5cYeaE;bF88^!N8N)YCv!nv8^BG#L=kSehhT0JS}laBqnj0~?SR)`dj+p}*_E6;d6KZ* zrqI!WP%e(+;KTv#c8glAMi7Q{6!X0K^*8g{eS3Lo@3UlcnUxSmkr+&3K!QvXdWT1F z3ngZ!Cur6i^b8E(DwsJlN-3YA)ebSHK)I`Ik~kEu<5F+5$ma6Q&&{KxGDt4=dPwi!?)?loWkUQrpIz358SYxKLz>f1T zV#D@xI6Xd%-_ga1u?fb0b|3v4HjoH~SIlwykttiq;_%+D-GS@p(Q}i0>Wg2)Y`qjR zIb;ehEl++E1G3o3!kH5k3pp0&X8}X8Sg>`HF)ZSwd%3dbfCNbl!n*3j#!@L1f>=m2 z3LPgHtc|f}j1?9eOXn2I9$-!!p_k7eAu+}RLy3{8A;j`oU`UL!vezRNLc}Ox(Av^A zq!1+10#!+zAf!SFhq&FMn9I`L*~7xz4CU@#I&&H3j_ku-vlUV7ByP3A5r|eDGjgCq*^h*1b4V{ovIl9$P$ zOoA^XEF8_U$_)W@e@s9_T_jS<%x!kRXi&gzLD3u@tW7#*QPk(Ji5q zfG`o%S^>Ue@O{O-_dd+^*I&z<|I52gE}vy_VbMJE@ZHSKHDyhO-2K81O?PO_(2?q|H zW_D&?Hrv9?&Qvh6h;lqiIm0)<@ogU6dz?lhtoxpyCyF(~gt(a!exbm)Dl#uY3zgcc z+VfvHwjtG8V}xzdq!2XYgp87Sjzl^DH$lk0E?P$~Y5@LUtQQ-A->?>@&R!h1H+x|s z2*Ma`1hF$ zUa<-Vi?kW+H?imfD>kK3Vo(x{Nl?lG6C0zAKu8m6DSRPUC^K<81O!G3k~Fg2L=i3; zgym(rS&vZpwmH%wT~jwXq1QLh|DtJz-BXRIC>qPwSyb~|8Tpa-oD8Q-TB#+*1gN*L>v zL#*9uvtj*ea=9$IT$Td|k0F$YHr4?{IWE;&9RWQ2_#Wmfb#eIkC=WgIES~G)yMk4# zNASyoY(IY+QxBiOaXp%i7DyN2STU^QXBk=5YZj-^h@s(O^81c6IM~Y@e(zQ0^qEoG z_xuWs5a(>)glSKUBlRjl81S;oHZn6dLFjrYp>Z6Sig8K$vIwJbM0%eIK}HI8-~DsS z#Uk6*jBxInKI-!u>F?@fwo*eoK01!+?Ye|)#=}z%+RJnD>{%XoYA;t^=5f~}_whHk z-A{4VM$F7G+ES{fbX?6IT)pIL|P;m zfx!ylS`s_zcN}{kiDh36i4hRTA*GH^PM(qkF-%O)v$$BLvbaRG9&+^f8Gd&615}nO zM8*opG@wr&M2;PWkB#>;pd8XF@H0#v<9UKNOHHO|gYQtBwO`I0LscK6U| zCR8UUIj1+v*FOJOeDUAD#!nvEk6g7qiIbiH03ZNKL_t&r>1Alut85=A@zsC)TR!*2 zf8qAW4nWT;5~1+tW*EuAt)Kq{U;OGf`071-DHeNBDvzvBQm9Y!)zAHRZvW+OzVN-D z(LJyZH(MmAEYi`O;~RhZXFT%EAwKy}-$qSN(ePWitqSqXDBt|Tr`WV@8!vy;2PpRp z(Y&UwaU6x0$x@k{W!L#T zdHUJsXv|G<*{&Vz-MfcMt$|KrNJ1{V>|*nZ8-7bn&Cj!b!)69cMSk~puBI(L+(>o4 zFgR$2*Q{mt1G`1e%aP0HL>wnH8&$46Z#ysBwH=a}{@!lJ&d$NYD6*rUB$H!4&hhg{ zpXGuJFXEh?=i_-k2PfwFhua^dU;^It?su`Ot3b6{BM1T>d+s1hOBDwC`k0%Yu`WY^ zgCW<^K{Jdo0z#Dsw7mzF2Zc^MAT}v=B|S=#MC0@fQt*6qqe98g(A_^k-AGIvqlF+c z3df}W`e>WCC9J4YN8~@ z&RSy7QW6_uadRPXmd_Yt(uspjem2Is1!$4Q|j?qa(93=>%BuoTJ zlo&@r6lo_;5+Q^kY&T69#X?DKv{5LpV6={fBaKKjCXORBdh)0gAfhl5LP#R*lk>A= zJ4yuYh%iowjVVLeYQy_H#StzzTYCXs}q*q7`NQqU;Xla(LXeZ>$p^FOGq7%FP6cn z5=9Z~x^le!nv3YnX9>cX(`QE+KYNyPxxmQC2!5eNA?q`C>J&##oipwZ=3bmlxp z7iZ|}>7m{V$P_z>grwGNQj8*kC?@ZDs3fM{3aC|T6go->V{p^(E8>V!Zy$5hGmLEP zqdGT%96e0e`kgE_TF*}~;v`kE#}Gv{gNR(I$kg;S|MIn4`Q|NmP+YZ+o{480ouV`2a`}!;OjjBh zA*r?kJjY@0@zW%g8M=D9n4g=ZQC%b-H+jo7mvLlbnqNHk7)Cakog764O}zR%uefL{ z^NUsXPaMWGHtegvtAt#d;vH9?$9$vBgLm!6_Z+&ryBO{*;5HU`&BdFj8HY!Hb&{Y_ z<=C;~lrj#oI?HwEZzOVZ-233eWJJu;{0u++!Cu0tGraTdZ-QKbJAb(w-Kg-;1NYO@ z+l803x$)ASJUCHjOU7qtpqJZrKZ}#gvm`u-Wm-wPjJ6X-C+j$i6EHu?;h{~?QN|IH z`O{}%^eCB4=Moh=Q8|aD=`k9M3nXDcWnrG$mFMxqGkdvsLqBhN?TuV~?m8wX#;7-2 z#7RtF|06{#ih8pJP$wi1YWj?kuFMEFr_-bKr09^ z6O&|$9ZZj%L9NPj`L);bvxlBWM-7^8f}hQp*S_XPW@qNai4(`n>tFLK-t(?M>;A%+J%;*T?Mi6s3+%I!ig0j_*fp*g=vlpp}amUWXCR3%LC$;=gi5_RL#;DMgwW zV5B05B8=l9idid&)u0_a)o7q?Lb&Ua#o%RIh*Af!ZE}LVG;E`yr9->|$bS!Gx_UQV9~RO%Ns0b6vUnzTNcn6i85b5|*0aI^g*puIDl_ zdR&}6b=Yx~q+H74IG_x)6Gg^VwA*#SHhQkI0Avz189#kYJpI%&8?~ zv~h5qgfI$iMv$cl31PK0!gZh(XyGVHVkE9|gd<}--xEr?X&`ErLb*iJ)+{ZyXhtEm zC?<}zwSEXuG!^@W zlN)PU*tYw#tE^TER(__PDme%e!dhjStM%ggPplUkfZwnZC#$6A6SkWa^I1I4BjY;= z?c;hL#X_DqPH>dKGtwgYX>y}Q+s#Vx={j-+eXuvK73;PGlL~~>*mKA7VYNPkH5SXkKXyqVGLm_fp)j+6ZSmw9Eor#mV1p?Dl^we@bg8+r{=}U(_2c;Oi`@3(yBX>( zQZ5zQb>2BN8Z|2O8PU-Za>so?XZs~rv+tQ>jEoEuoH$76Z9!>+lgZJlPSGh2l>if4^t?X*wI(yov*!tfl`KJ$4>IWKmKo2n-MBo;?j+SjP!JH$M;(-hKqda zGk;5EsY*__xpG|}?vC{wx%UpH#>aWvJKsyS-o^{6ynM?5eQP%I_-)^%QmylvH~t|( ztBFU#w!tp?h6dSt&m9QQ&*aoJnL>drTelLLCg1tazq0e( zb0`*aDUC#M`se|EcKWzy2dGz2b6|O+qS5G}L6k(8 zR+A{uD9>YIdIq_;glRPB=_GH|^l7 z-}oA*$EQuHloxWL#ZtXVIf^(Qc#!vyg%0%k9Ttq3JOge93f+WK5h}}v&k0TI^kKT1 z3pC?4Q$a$hvkRFd?0aqx(m<=a1VT_N6mc-9blPi#4Z|{8TTM$!3r&Iu7N((4w8&@} zf@AsrR2HFCr{!g76^h89fz%PEJdh&aX&9I1uS{`m@tqz7LfS&v*swDUEPLqdD1hn$ zv|9E(&*mVT1vi6`nyhQ5s$ry&%0WjVRF~3JVjz>lWU>$i_By44Vux+gvpIWhNdUDf z=os1Ai7J+@ZY+ujqmU@k$OT`3;H z*h5aI1;4RwTBM(XWi5aJB-+gpCIKea>F4Zgvyvwultt3QI;Pbm)-gtF5}_y+io`*S zTW|j*ue$0I@})dcJ0wev$+HWz&dd@?#KD6{XvQG4Ae;5WTrQg_6g$O0Zx`-T4WmOA zTlQz?Jwp&fwwT3F^?bfc&-+B9HLTmTo_f7WyA?1wF^ksVIZ%%couy7LT|2`3LWOp# zf$xeGU^GAmL1L$L9UU|qO^gvFNk}G}1FgtKZL|pxDoYrJxH2J09KtBZa|MoaiQAea zNv!vd5=A z<<1UJ8N7ClI12EyB@!c1%1QMp5{)2}&7jgv)lqUeSOZA?o9$56ek@G7*+`N!VqF_U zw%x`_IXF6{93|RVO+lRCV+dnI7=|k-&oX6a8Q1~HWE4S=5XV;7Ydv^188`L**LGiS z1qqI_4T!yNu>uY)>l}oDAhHjnqnuwW{vD;B|6O!Ms~uWb5@RzAoRqVdMCk!1B_d8B zF*fYXXuBE3F|Kroqc(|~O{W0z*R|5=5$)r~Eb-Xm&rm27 zn4LLF7~0fY9b1*yUwB2YEcOc?y8N{LSu3Z zbDV$OHN0fkR&v=aN(yG@ra5@zB+u+SLJ%bs-IyD1dNuo|1I|p%u%;`=HRo+K_w9a| zxzH7tT@!Q3mLW4-E{Ip$@H(`vVRS+iX&!m-SNH^`uapzDrA6Ws`&cY^G;38_ON-PS z4Kj@yu5y^27)3fBjY^eW8&>nmx7@@_E;yH^YMu9g^0U-iExHC*F*`m=DVJyF^l1jy ztfjs%$Ns0EWYy}m9N)VKIX{b8yAu;7;JOx}36 zUB2-BpK?i$Lan+)*l2Uf=3y32 zHRvqniP~){wI-E%9T^0yTh&J}H%>=a4}P}I#PlLl^GlQmT5MP|%#qq6eFOaj?KZX3 z6IAPUdZLiEB_zVpV5QZ@mGYc%%nr!MV;gh4&g{?hVj)oydIOzdxQ)eM9jyk*1rA|z~1W9bE zi#>xR*&MW5G*0ZtCt!HvRz^>qCT!ISn@ytNa;9fz$VL^D+p_Z%QwEFfJ6oy6peohV@lyZR7?GFf4f+9XcM=W_U&3=3z^ z;C1yA1a0CdBAd@My40XrJ^N__a6NzY);}T9n!6u*f;*l##6q=B zuDi_3Uve=%F*~I<-)|IsU4jf>B2JgA~xA@`ir`bP# zl1*E;aB6yvvWU3uf^}SV-d65?dOtsZ_9)TZ6i#)T)~c-(9m%TxURqJinb}!PxzBICS7q&f#m;vy(zJr+fl zZL5d4>58?S9-F3E?&Ps!qwK3T=!mMk@21O`T59mkyB_3*mtMi4v(q$9L{MMibuYbu ztf#p3iNh?+j9b7XXyEu6922qV7wH*V%i^(p)GJl8zQ@?{qYSTIgDB-$8b3j9wM68) zKuLQK#xjz*CfNT|1E79c3#eb53qY_g39B!H`U}X%?|G!21E!9U_{qKri!F4SAG>$E5;wp(s(~iMT z10tabqZr@!F-TfLLe6)Qu1gRbGKqB&a!BbuCLL2_xulNoTk)&}nJW zdLDu8O3VwI9^+;##mE>m4rpO1IHa-RQrUxCI24L`TFnNn$ZmQo#Xl0|c}&kPFg`i6 zl7FC6r-~#ocp2N+#fc%4%}~f^7&|jY0_1&%TrNvCU&PI1(A5e~%4%9(kx*>dx}BM^ zGmOv7F}>8V2%Y2Eaetxn`8Q6vDIy~28CXTT+2DzN$3!NR;dM8^mQ6dhQSR=cBcDYF z0e9YUCwunpr;W>dKkyEYRt?XdI4uTLMD>=Ra`h$W(c9I<%DM+-On?}Czzd{<=L*HIDh*Fgqvk(WHpnM(>%84 z08gHnrI9-%jFaK=mt4;F%Pyg#RHSQlH;rb1>CSO_u1%<}CgkFjql!w0@~F9Z!P>~g7AD_pT_8@E5UhspU0_a8XIJO0~W z(^{x;<1Jt0+6#BE|L#5Ddn^Y8J+GV(*)X&k&r#IdA%4Ba)f-0W>Fwi-_uNToU;quN zR>4~C>9nxYNsKWr)k=-?H?L>-op0pNKJroGuxLZ3w5Ht-xN7GPHoo)Cy!Sni5J$0f z+me!cJ7TD}%$tAzX8z=3Pa;fWMfEx%2tzik>fX;lC(HZIoJpZQHY7a2!)IzKJ)sQ;pvdC-tjAPLi3mZYO_8BVv2 zgd{Nu*}g3plaP}VSv`U=hK!Q9jwBKSg(0pk^16#J<(f-(5o^PT-Za9a2afZ_AK%B! zn#dU#rtH?SRdF9en8KSE5bAk>e-$;LSI1dhF|r^!M_yx4fIN8Jm)x@m${Y z*>8|cjq>&nzJ~Q9!&KWLpZWR^*nj6^Y+2vO?_GN(^?IGn-8t5*S2|9*=30@YTVFW+_-htEuM^BaDbnbFg{?5fLoa{p0& z^ow87(K|q~&_U(YF@*1}m|tKtQrm+;hy-K3i7Yxz`l}kVqN$KZ6Dt>`6gr8~iNc8YjxdcHO4~e_jO*cvB0;N0*ovsP+6?p-5zPqUN{lCI%-5(@YB4b}|z(bwC>(o&Noj%l{qbai)AtyCCUQ)YUqN}%#6;Zkci)9eL<(2AgK@N+Jm z6A~@(Jdbw0 zMID#34WEWkwx}1%?k6di-wI09uTd6sx))kke}PeswU;%5L?<{YvCB#z1xb>iwINA! z4_;jVx%FZL@EcaCqfGxmKZQ~W&&yzv2q`6wGAK7k5GEw`7R&L}p63yU5!z@G&(%^3 zO-Q1MMBDMMlMbLmb6+T98^tDru2SC8x!#WXq6oQ_g(aKrA~8#i8ZgOCgD3jqAu% zRQ!C>u$YKpB&fI0tprglA%$6K zW?s0INvv&X+8l`GW+L58jIsPisU%7&l9itoQ?J!mGyqa5a9oVBqi5gq!6f*epK2Uj zTgYjR20YIvjx|y#JWtW*D5fT75EwkqL-`(_?-PZgbr|9W6y7Mpi)*~~#_Ra{_iiO$ z?BtSjH}k!FA7wrYkzNKF1!ym8?~Slcv)#sZ9RB*l@8Iy^Lu4~PGn3<-yJZ8-T9w(E zDZ-{<^>TmC4ASVP%P5b*}<2; z{X?F3b}w^FReAgI!Qc{M-1<7eoWVaxeD zId=Omc>nMHF6-8>=hT_gTyycoyyf6wUiaB=Gf^DG4VxIJ!Nuonr4eZY$LE3lM;Phu z5e>qi|i< zx~r^A`;t@-WW%m7wvaVi6GaJ06w*=1+7Z0Ligyt>I;7|+lE6~(Ok}4~34+*wD>cf* z)*m0pxGt{a;7HBsvtu;Q-$KE6?Bt@^fK1*#V_pWwaY&3tw_0`zAVk^_2+#>8*7SR@ zx}0O{@LCR?nPBYvoOVh803ZNKL_t*SS>AWkwY>lM8S*`Sgs~=H?&ine`JTA)!gF}r z>wbsDr3&>%g

4r5sM4I>l0>O~!M1=DEG>K6fk69XyKT`9$qDQIhbP55JSX{iBGn z3OF9I0piF42ErB;I*y3LCW~XIk$xT{t*!{=SUO`WuGMjjjzffwsm{#MuGKI=Nw-N_ z3%IUJ(-++T^nY697T+*Sxw^j7}w+E^disR zawl^OOZ?4;-@%@fWBAz;x9)zHo{j>$_Z()fS|h?E*E2*VG_39K;X`9@|F#p3uZw>`X% zJ;zQVv}WVFwRCqBIq=96T=uq)^6_`SiJ_q(Zh81Qbg`4kr5ZnZ;0bcZq{$w2!$-KzTsM2A^F9_Ptse;@fYv-J^th$zQP~A z=6Xi@I%x#~H(vKrnqkbH_wHt3WG#K&orG~fj6_OH6V-79D?pYt5D?ExfbH2JY(SV1 zsjuJi!Dy`RO2`NX5kT0vlHM+2TLcXc61c zP{*gEyPL`J*;F{Kr0WWTFrvGsha@o+Gg*>2#z+gg#YsfY%V31CdMIs^mJ>9-atY%Y zZ8TwM83D>E5YN_GGt$lYc$;?H+W*bWS1EPoIRApp%+J@URsy8-i9|@w&)_)@K@t?nNUV&a6Rf{DcjcRzlJFbKG4=O!-PzMhHk8qFXklT}DBOE%X* zS7#TCbDBmFql_R9BN{?kn`D8t@>K@yxPYbOVp7E4Slywer`a3UEbq^0vns456)(Jf zmE|j=)c=CIy}14#*NY9nZ&>^H?Pq9sn5(Y5g#G)EV2ro2fr3Ce9zhVS6o+$ji>bf9 zErgd5dDrzU5+MZ2aVQn?X$r6{K$rQMQh@6?2&GbbMNANBGM*v`BO0v$DH1{~H#C#Y z5JrYC{mZx5dG2;ze(g0>7Xuu}(skU_&_Ov4#EIpjWB)$UDWI1=J*msq${ApF0=5Cs znv^?l2;u~T!AS$pWa^=h0M}7CLW7BEwc9vpTsJ}>9S1^TQzwN)2&?W7jorvB{}*(u zF<}!mdk{0U0W-4I78oyB2C-83|KHXNngz=$GIlg9GzgW7pJV%aJ1)wxR-Kl!Z#SMK z29a2OKsyX@Trbs5*r|d@Y;b+h3Q$tAYGlYZDM^BI9DCFx#@gbkv;z}1lt?BTPg;Au zL&r|>nScIwIt!g>;j_4~fOldKI#(pzb}1N1&)^_m`j0!f<>&X)o;piDZm{dTZG85x zKaH=fW0X!3sFq9) z&t^F>SLgWD9J@BGrqOKC*WJnYfBFl)@b~|~xvK|QHPFSj^UpW)v(w_tks~w~rx_ic z;`rzcfAo<*V%_>RoE)FvEjQoDsZ*!v&iTCl6))q^p+kJ?Pu|O~o;$)%?s<@?R>#fc zxc9+F_?yrCcW%7lYRWljzW=@Nic2oNkb$-9sV9Ut_lk0uIJzkgeWu%#N=Ip)Ky6^w}FHOy~_jEEi6%r;; z$YmKA9wV18&|1t>&REzwrYELo%udtrBiwR3PA1F2ff4R~;9)|~ z=VbqBk|-pR4z^=)Vq}axyIvrOV#Y^CQ^YGFV@bwm>pZb-H(}s2Iy8hAX<{U9E=T`l zjqN)Q5ToepJ3+$>2(i$XOD%+7-oKHlscHP`3{ECP6vpHWMIzSh?^_X)oBq$Wt3E8 z^CdEF#x!G=!*pchhY5?9^zy?8o}^@1TyfTN4xSoj=i!r-o61yz*c1`cWQo|0OX62K z-G72N-+U7tU->g;>z>goV6;o-b2f;fZ7HOHM!nAHOpOg^ok?H+AkpXmwrwMoBB$Z0 z%}2TFy!G68=>{_S0tZhFaAa(lm8;e=Ju=K)_dLkN=qTNt9qhR8VWvYtOG_K42m1N> zo%gVANe{1i?fGolbC~0U!?dqhN#AsXzxdVpP0b zIO6?Z_!4!ejNR1Eo)ZK7<+pF6tECAqPB=PMN0&PguHdPoLwxK@w{XGQ734D$-2L2( zjCe-aYiv_h3X-Hr^y&Vs=MDl(GB#7??kBc!*}A19TJl%7{FL!bGrCdd=udvdlCCzU zsx=;XZZ9hr_0Y6@2`cn>;K^qYZjO;k1Dc8qRH}UE&Ii%J@BHbPS<>6fkT2N!z!n~T z=6Q<6JO_p+`Ps7vaC%pB`;$BQ>8~H+=;1ytzvvuJS3~yiJH+R{{0%PHa28=0QJtP- z$L_s!buXYkHI6rH;bgOfQ8aHs8fnlvHU*@V2n1G2&z)-kgfQ2CZW1B|DOeN(QJS-p z5Jn+kl3*(fEQJgbk}$%xCEbg97(TR@LN3GL*fir4Ra){H0xu*EBFgz3MR%65iE*TD z;rk7uFd*xe@ahq^7AOS?F~z0=m4@NuYi-_;7x*-n%Q(t5xiq0qs1pj=JdU&p9 z;nf!4zp-9z0A69u%r;oExS7an(9~3-P%L683peB7I4R}F%*M5{9APQ&8o_)~?E5~R z7gBHdkVM3BOb~|D>kR^(XdOqwYgEjQn-=JEYW66M2*MDlEK21jlhrX zD0LqcFI}JfSo7t8Z5Vbl6;AQfgyhP9hae$&3C@Fl{cNUlF$6!Cwb)l`|0dz zCki9LOeBiMGVg!)4IG^LCEtH=3pWLtk9_bZetYkIyz9aXh^B{-B4X|O^<=U+8nszA zJ-LO=+jemC%^&CSfj*Y^wDXT&{A2#*``_o;CpT)XHGlq_U-9}Y-pKg0Pa&7#XeHvr z@B{-#k1#kez`--u6FV*!oVl9GsTq=5g-`y@Cpq`r4Se&~pNfC}?rogAekJd{{t8{n zx|}#YE)E|*!P~C9jO#AHfVS2qin%NgZGM)CiAnzaGauve&D$tv9F{HZ<=F9lJU^o1 zg|xS~@%c~R%$n7!#QhI$qE`3$hwuKFBggs~sRWE`MYVY$vREPs1FFL1mPdCWq@WUM z&h6>q%(K?>H~;=1nT}3^D8|a>r94&YmP{_tbhbMV*zKfUL13e6q(G5q@RXBmquKJw1DGch&I9S=N3saU|x zWVrqD9Srz3pZ@TNDHU>j<)42<(Lqmj4j%_cVKy)uO2QmUxn}L}LgzK35 zPRE8jZo60+*Z8EnHo7{>IcryN=i?J>dSVNUdb&7rKez^farjFl${ zCONQwA7^hk7t6|!&*!PtDkO1)Y-;17r?&9DzxqQq?LNTB&@gYm>T>Siwv&NppTI3O z!RiY@nbc6*%}@?zsZ0&9({uUbZ~mB^Ya_HKNl{;=6iMI{3lrQI1OYLo!H>1%`9sI3 zdkt2sTtN^RQ-NBw%0=rh<=cPpX&SyyrCQ_I>2dz-J3r<0-~eKBn4f>|YfO%hFfcN~ z;-$Sjxosyq_a9~X;ziu@PA7sU<<-F~+Yq@ycQVO{|U;WuV{OZXaT)b`tpMC%J96o-MI7wKue2m+k+D#$n z@R_TxW^qfN?v5^g_V8vNc)pJhUULc8Uvdr;lM`s6xa*l0dFsS4{M5?sl*Z&DLPC+>>&G#Y%^)%T%>(|iLSz^DHr7M>6{Nu)JUDNl&z_I4SdgMbgDwE6Pj{a zW<8G?rfF?$F~WXFp`+A-Jc98?#KFmkp(snfy_LEj;y4*jjSnz9I7mM0uzX<~mPoLL zpb`2sY8B!np{b>b(DxBh0?H;9iikO2OuhuvnG0l^QkhaQrA%2}+5n?-!A6NDLC;&8 zCy7QY1Gt4zjFWja3HZOWUTpwgVY!ZrPC}~HDq$E?tJcY8T^e2k%d&A@7o`-rj4e7_ z96A>CYAH0fWeGRq>Ow9^rRD`pPgl|h&o+T1ZU&)a9LL4Z6b!PJnDDMSGXy8iNSb?Yz&OEKsXI`V zhAOFaqGsDbH1~|@c@c9MC4@S`k`g;(xamP;l86kL&dG{WD1`72Z#0e-9y(oBt1Ml(27<@dk(eU5l8$CDEOa?hij zcjg(4O-wRy4(*lkQEpSbb0s?(k1Ef+7N z?oWzxQ#t8Af4M3-3H{UK96oY_twEk=_ML*6Aw(Rof6pmHnXz2XE|)0hvs`_}8)$9q zqNBB)nV~VJ7PNBVd1r~m!;}2_p2u+AERSy4!F#TKBLk!3guw{ky7ebajg520+I4*W zdq3gRpZ*k{=M#q^rE(EB<5CL~loSk)j-!Rqb^Ph?{tmt$(1;~Z@7d3n?s|e+kVQH! zyC*$%O^kxp*sjY@UKr%I=YK}7sh#}dRea{(9wm@2vZdWjnnFpEDd4~63Me$g%p`AE zy$C<>`Q%q_Wy)%%tF_4a>sH~kb&*g&Sc0KMv2p(i>_sbC+<5`(&R<8o@EF?;^mFg_ zeUzG-@q5>@tnC5{s}_=XyK&?~Htst?M@utt_ez@c&Ajf~*KulUmLo0C^Rul7X+1WJ zxAGiHi&juvekLnBSF_uBmW?kQW6jECSj*NS^Bo+Ii$n{~p!;HrNB140Z+wQhV=)<( zXVHcWSyjlhJ#6LBtfqQ+0KdH#u|7++&_TAPneHpz!CgE1*ni+CZLVhVITu68htm&K6Ule*%_;5&~!72+FSzMiJBA3@y#g6v`!b?RtP~UVjlE|JaB5!95Q% z;{^x=>sKx1%(GS#2BD7PP=tPiwzhT}UVw7yWHJsbmoI^!LAF%l;B1v=_w46=m#k;g z4nyI2eAfX)HgBlIL4zb)MA#0+utNRBK3ZBk>F)00H;+7J!UcuV4@F5r5QgN7MY6@B zp;jhFzhH#U0v!fMgXOp+%0>$C>c+nI$jQOf#6eTYX2~n4DQI8ZOEKq?>FQ#l(%_u4 z&tmhld#KFLvbd`qr4$E__A@y(&9dG_6nYl3_t{;Xb=3td?(XFA&0DEAJl^v9i@AOK z5q!_%(hciazj87Ede{A2|EAZIX=>+@od*b$n2we*S;r#dIxOmFGlg!$W5co@zV_*N zqy38RS-3=8b=d`c^gDNOx{*>Pr9#ZKC z8!5Yr^Uqwx*vt&iA2`a&C5zDyZlaXWlFc}XIHI$qi8EHO;*MwbQFJWcb;YGjjGorg z&5JL5^d^q|_19UusGIKg7Pf8M%5~RV$vd(o9{tDfapM~==Ce0kK~}~3_OJZ8_|g4O z@TKqE#@~JZQ?z6S2M-_NgMa>6ZvDmG-1)#0OpFZE)Yge|(grU{jA&PDBW^|@lgJD? zlu0C(+7$dzqSNe`ggDUzsiU3|14jsLPMFZE6B6QvOQ03XQWPAeGg()}L4XvJ zdKh74Gx)(Q3L9Hkgi%Dkkf-5A1jd0#2oa&B5%#LQL(mA!R3e=i3n?gMY#Q~D8CAow z6%t8Pra&fba?FGRw9JstWyoh;YBkNtu?D_B15)5OJQj77x$uJZj1EmOU9B@bIYq4& zQph_!pwDo)K$z=iEMyfrGLv^L zC5cXm;s`5A5SGGG#ztMoG19W|qs0CHr3n1LWWCw|yuy-FCR&@WS_o6TCP_lzn;sTmEdms2f==rlzt?&D3eiTiBMsvNI%cNTJ+@n<=2ANYj7~rKa56 zf>H`0B>7y1YPCwSR0df=DaG{35z3`JNn{Q*gI__;RY)Q%C5TgQzEaFvFeh_aC>p|- zSvE_>d{VIxW>W;y6ohjD973ik#UL=eWIr;w2aaXXkGdD(TGAllQ9zO;*lrH(H6Tg7 zlreU98a+>qNutOc%$6b%5=DfvB(@b33SJiK0&`t}B*9KX0_D6y6Cg52y-Z;GX>ISW$tiHy-<;8WSaD5&IyA=Xes7Lk#TB0 zm!$u$lp zJIM;kwmmO$`Gx1P=g=_@_w})3<2LFe6Z8)Zo6pQP^bT?*sA%Mp?RW70rdLv6r4Fu2jj} ziZQKlvKfwtG5_?~Zn9+AH$2PMfB6+ny(>t{-Te5O!$>DXlr3|h0oxyV0c?kC*D`L~ zvgxh;2k3RhzkNx%@ z+zpp9(`azZBQHQxEA5@V{P3>F(L$qo79+{>H$QtAOZ#LOt>BmUZz7I-=skm=Z81OC z(U0=>WA!YfZ*M<1WhR1vLl1977R#w4fG{H8Odjp#=6QlzgS2hL$%Ay*(6(#|W0TVa zexAR)?QV|k+eabivhU!#Tx#-=k#G?weKXWs$- z=G(VnNl8yznG*v;OxHZhg%VTM3ZML=FVWrJN+F-)p^cl_xv!5>xy*Q_!5@6_YuItb znpMl_pRTiQB&4ux6+gP;9-esc0amYG&3#X7W!DdXNws|$w6ycrKfaUQd(NPxshNMd z<3XP3JB3rs^ZmOXWXrZ4bhMOd?`-GM9sBWB5tQV>@j)KkvWu?vR`K_@-OrMxy~gpa z5vA^8CWUt%b(JEW0;GGLV>42z@R7g%8W*o!fs&FtH*V$hjK`rPefZq9iWsiacppiW2Z+MICV<=%ePNIX!%ua=rk<@c5OIs5yN@O8wD7qXTn>sg!4*q{zBVkz`+|JH?zEP?}v615yjD z*aK{QA;HcNn@NgL$|52_DT~3Oan>#G#>(0RjQ}UK2@=V~$T(eXEx2|8VP#NG22u0y z5=}k<%Ql*_s2--*B{7q!Frr%X>1l6HFO@_{@WOybTcuc(c^ki_X3f3GfdS&lrZiefd(DKlye2fYBPAAPbPLu5Tau- zUI{qmyNF^FN=kI-8@*B3pkybUw{AJh+gms_-o=4~M+kzDFiOZ|GR6WlNtkK)O!|VD z9C4bTB;o*VWlh7QwK4V3+MxaO_hgzAkv0vQlqxjeyrv9-B*9V4I}JvGSNQ){{r%sy zUTpwgVc81bwIxcLn^H=F=lMvbkjkLUiB2QTqYx3-P?;i@lTY$4!m%xZQutv^r4~^t zWB?zn6M`Thn>CIdI!TBVK_b8w2~lX^`$|x!|MY2;G!~&sN{%1zr&KE9+LCO>1z~JC zm1Sd^5%b>XZ9v6Koc=kB<~h>`DN{rv)$rLC)J(mOV+*pbNd5nf^G}p=<+Yp(9W&m- zajF^)q6pi~5GTgUGmgUaHH_t_Qi@1xW8J6>s)&*#evBg^NgsMCANpSl^_hLb@XDbzX%#tR<-0=vY>FJ=mwVmHQwUu2bMu@cF`RzMsawJ))IeB6LAv9L0oy`YMviApf za&&YW+mVD$p6!FP;JT2+2vT0D5cA?tF*S-DJ4vWxgq=gob;{}ULdp*&4k4H4q1^}g z&=u#g<;P#;O@I1La!7i6Iw=(jh?$tYj%h>zR^oAHSyIRqXkT{`kL){6MLM)~_b^j$ z5KfFyq$%7-001BWNklGMIi!-v!Nb&aLg(UM&VKD#Ja%w^urh<=y1164 z%c^p0qzaZpoPZyOsM<8a*dXHgi+t{#Z|30eB=;XY&8!!g?%m07zq5ygF8)KomvbO%XRd;$ka7wQ79Yi$z3=?xogObKJg{-S(+?HZ?A=yegrc=fLhA zlsXsEy>bnQ5AUZoK2Elfr%-Mp@H{LD4J6XZ@Z=-+(w0-4bJhw@o#>;pa}hH$Rc5Qx z)azB;OoqLC_pz$HkcE!slka*ne!WUtbD726?Y!j;m-7C%m$~if=ecM55rpkh@}>xn z?4?{P(%Rk4@Ug=Pt;txDFi!AdL+5MlT0nD43&#&0APPe?nkWp(mCAH4TmW%IkQggw zmF`O*n3=8c+A~-4XTSF$EHrTxu;<7r{`wm~U~+U6zh32U|L8NUUEE0!h9uJF^tXS4 zFDw?cxA4JtT*IR7PAb(ZFC0F`3-@nfwld4I1q=E3wHLGR@DZ-O@Cwd6HO?(t4nw`h zWgFJf(_Ut9WQ_C9Ttl2I@|(>&x%PDz^3iKA!?h%S7?a6lx%G)Xh+Ki79&*pd&2)FP z;n*&BJ^3srJO#P({I+IDiRm7yUp4_q_d3f~eE99x(v^1*I^wJ|mh+R}ZerD%Rea!G zZzk)y^bL)2d|-%wzjq^x7j*H7cfW<{@iCfu`Mr5zGv7N>^>7Z;xk|4A+v_H%_ z?vS9P7#&AMLZXnwLYVYq4SpOTB2cMKHzXuTa`~LLEG0rAuq=fiCx}E~2}L9#6cWp} zX?2=tDHZYjz|d)Jh{8Ax!1WN8BneV&TGrTy3n{R5Lf!Llq)jdGXy9Qr;1*nD zn4=LTWb+a`<1$o9I6PUy&$bW?qoGhii0xG*jOJvH=Z{JK)uyNyN~Pj_j7Gq6%>UELyrniup)vOBmJs+!f)a9G z+mZy{s}!LB#(K2@c!f1RTcNYPfNiO?pw`CkU-DAav^MshSYTNe#bSw?7bB%GeE!%Y z2_TeN)7e@kh|0Dz#`Q)U)L055+>O&lBZv}gVQ4@z(=$lhC9L~2>UC^Oq4F6Tp1^jE zD~%Uwv^I&Rmh}>c|K;VZQt4TqK&N6V0=s6TBf#&v3hGr^e8lbGy)kmkUKIZ*J z!b)T0<@_|`KNB~FPSBBNMrO#YJO`^X&gl@8HNRZ++KWc;w+n85}%~ z75c=U_p-w;U31h2A?AN}`sWpvNDomlpSCHbag=fLdDHM^OK7Q3PKKnjmtChOIsC(4 z(bCn8v|SSA((nVaEp2@Fp2ykVH^{*7C^0c_dehZxIe3DH_8v#LSx#3X2B&=zzrod4 zUd{zx#IA!UIMP2zWp)~0XGp5El(SjdTbnt$e-D}U7ZBzOVtRU#IDzK&#S9M*;U^X+ zj`Sg-m_oUUd`pXt;+SGfr^uFCnVg&!jfRIGXbOd*7HHv3jS=kJ1ihk&4lv)Sh_=e|n1RZ+r*;^!b~qc>z;1vz&M43BGX0 zCZ=CFLUH0GU;Ep?;^gos)moj4*RA9q?tg~;;}P%ru&{`Foq4_1*~ zJw&rr-gC)o_{xXg&UmfLL@neK-~2h-B8AB2Ad0xK-RAWhF5&z4ZNw@xk!$YcW;ddk&+6^ZJuRA>ThO5EwYt!8fSWghV4*ejsYx;l#wu0*?$)1icLE_ZF(2&$D~>p-8y#+H2Uf^AO_`W5iL!C*S*a^3vw> z-}({B#0V`5yEtRrS_TJC^VE}1@zM9+$bq3rPLEBpZq-uWaM3vgQN-gf9;ZG&$_*Ev z%a?!eeQewPBBgRO=f3t_{_>kY;-fcR#|N){9hGX857=2g`^|r4^T}~!rhs%asEkN+ zcLXsSkvHd3q7xFGf->ozY}~41BM29gSPFt9L27fJD>n3`NHeeCkPp$YdGtvYZMdv?6=vP7ynj^U1|R2ohAzc!|aO(uETOsS|=w<24#=+4%x9L? zYFK1)S@s@0hH?b<$AE;yWb&e@c6S!TwDh^sTKY%g(Y*e6pc(qwhBd{GbgiyRN{Jj83-Bg(}* zfuE2o6sgoBDwTegtyoGNN4VKMN-AMF4z2G}F-^FN<5v$L;n4mt6 zMiK@Ae%&`0skxK0&s)PqYnJk>yT@3&b|tOF4EqMg85ustnLRyh*l@0xnyJy;d@r+& z273-3<)J_Q2eRG0xLKD%CXcV-Q(yZruivnihHw}kAIF;*$KJ4-WedC6>^f9yHR|;S z)q0hySNHPf>#pO0ZM$hN=Q(%HD*pCIzvS0D58>vDB&3rjZTP*(9G%Rvk#QBPGC_iA zaFZy4IK)yaz41&KoA!JL6OaDkaT-BPdBr-m_Iu#w5K%zf(gPwxxsd0#Pd&>Wk3P-H zg2rn+;mj9bEgN&+x9dT+QM|3wh|F$7t#lka|IdeRVAaayY}~ksVxfs_ zKF2+qp5uRf@gG^gY8l`A>fh2;F7lfPpP;v+nX4{-Ee|}sos*}Bu-!a<93gZaB&GNm%2E=> zC=KO8mLLu(X7V&bpI9fvI;Q00$XG5x5>j+>1c^z!&s#bCIHDc}1lpXZVeBK3C^Qz( z(Oe=7LMmQFR!I^ms5d-pA@I!Z$BD5DlX0HdiHR#SgfV2o1{rURPB*5jT%@a`jYL7Y zSR~dlQ;iCaw8$H3n%78>fy1QkiLhZ7F8!0ZA-~P$tb# zq>Obbu#_O5byGwq1)-&B0^$V39KYX87@2dXoU;Mdaq0-9P4h9=3?$kVMqZGlXo~qA zTw7u(fs+Pe#fiqXEee*zbuF|owq44y$=K$7Dcds5O&Fr*EH@FvGIjk40{lcHluQdU zP)S56ZC-Xfkw&?^v>*Hzm^^?Tdjz>ALOVlfxd=B;l0;-|MX{-wq525IE#QbccG*IB z9>g(87$UQU|9BYuA1tYqaeI2>)OUfPDc=hWQ3+sZ*c4F_u?i# zGfoS3#-SQneD;gqqFSwzWSh`Y!2kHn&A3W%u>Ukm7B6DgzQgn`>fxV$elL$b`#fL$ z+(-C}Z~c&CK|sA)CA(x1cKafJ`S>oThX>iQ>i{>sPck(<&4UjXs(Mu--S{qG^O@c^L@fjMSV?xKG)Z9Z9Mof%NP#HKz{*3de z`yoPRi5IPgPM^DvPVw744^fLGRky*8+kQ)=L3S->x=`dDe|rl!8APJ_;iJzHmpc&c z?Q9&JBT!wMan210k@5;>7qgU;o8@EbU#y zUwq(tzVYkFn41^sbZRH0WfHUJ_=3z?D5kmqrKn4r%)%AqG8sZ7vvJJ$Or5UKN2J9{ zoFrH}!O{>ke6+HV`6i}oK8;9H^)&mo?j@hkQ!M3q&B~=@2P%Z2&xX~@cwqBRc09V7 zi>|u@?c|WTB333xR%pWGM=2L_H23r{G0=~QBb05#$x28n^*XKHJ>;62d2!2TR`s;e zl(jk1Kg{f;U~=FX!ZG?FX*A?R4PoFJ3K4MtFmm1T-UX?U-~agd2+z+qP#3J?a2OQ9)44V*h!gaPhQ7DORhDgq~m9X3p$q*Ca} zIK=5V(w6OrY`(zs2|7`NlXJ+G@{nl8#;0g<9W)w02+3w$EvN~l6mb$6GR!<5 z73`u*9K|F-Jnzyp)2I*y5m6W-U5iM^)Pe?)jtNs|AZ1CaLBm{HEvWk*%C<qJ4_;+>M(f~($idI;i7J1d!1;! zBp}i;B7#VUR6~icEc&KG4%ZYlD@Q0Dl0*s9PcG|HESR)rG--B$5z4i+wo|E0bLhoA zbT3+h=LI;fOB8sNN<})C_oe}A7NXQbXG=5T=qYAS4-n0a!*l|t|4bj@% zOcDkpVOHG`!asd<5GYFlqsH2_7PtD-#gn|gse$4HUJVmxxW^M06 z_DuNbOqP>lqnwqGS=C)+qEaJoIh>lEM!PP}IR_mCSpF;>ZCOgnVR9lc0Z36qyYy*W z(!${QBrChySlHFUQ^zMEmnSN=@~Q9L35^QuIKTs2o@GiE5KV3K^dCKU|7$&m2AF0* zNRXgojZPv0Aqj+Jw&t7XLQ33B4x%b?oF<41fuBgCFu<0YY%asE?|+Erp4nw+l+kf) zVx*GTnLJy!?-zwqnX`J=aOCho-hAmfNWaSShmZ2*AN(6qWDrvmRL2K!g(gx>^gXwQ z!1qxCESZKU#xeQk79y{~?k6|$?yE25bD#VWU9HU=?mx{R{Q2K;cybmu7ZFF}DBA{U z5k~>*mh}?UDoj}!>ak5cKEkTD4Ck#~j*L87x~^y2Gdq|V8l>VSq@SB5I``G>BLEdxz8~MOB7ZYD~5pf)I%dhSy z9G@f%1+6sr@*jVauu4A%CxA*JNrr=O=fJxzN{ znLqsf4^qr#IC0`6o|WZS4?M{`uDX;pE0(Zn%X3`v+Ouiy?BKCIClK8WAkAf&7mI2` z$I%#b2Qf8@96XF@TR_y@ZKm})ehJ_aV!jCi(3XR$%^)X-Nt!!Jas_mf;K&eZ*+iia zC=$yB5OE?%qS(-dNOOQ9lOa$GJX}{XI514McOi!dN9bMEt+QE|!I4p*4a;%JJ2puW z8Je(dCT5Oflg$>Gnwn;|Qb8*y`E{Rdt$t za?m-_QO*eoA#x4|6HIWzIOl7xz3aG6yX*U6uitfKofd~Rju^0w!33|dF~J6rgd`9W z5<)o~og60gbaz$V57jf0ecAi^etxMhpcCfI^h{Sh&;R)cl%%TaD5c2fayYKQ=oslb zn8<49geM@<1Pv!n1HzT4FhRwdoF|!(4ze)?6%rAL34A-}1YK z{ko%U60jTO$QKKyCGU!?pBGAFj85=^JVHo1+FB?TbL8?R+FRR@j!o&3(rO2UlxZM| zAgYHLl@LY>;{;?2tyIDZCdLopdk($?gk#U;*pBJ7N{~{LC~E`S5ZdSl^#>ZZyOt4g ztl7qq((?ZUC+%4h{7e?5lGFoVP>+u}0v+$9Af-UZhFaZr>QZass74ekip8QB8mgob z>k8L*Qa&-@SYdCYc=lWm&$Vcjajm_n&>Ag|Z{+_5L_Xall<-Li5Eu?eA*0*(;CA(* zqnIE5`aZ(iG`Ws0`}dLnFvPJ!_*q0DvH1i^j1&f8Y;J&Q{(XUPMCwbNBBhQ+BV5P9 z7=dPJfKol!$ zl_vxX7A{7h*t>T(;83YlC>BfRv~w>OVORql;kht1HOF zM;O_)mA*N1$;|Adt-FhJPCJRdul_6bT7^I;PCoHO`btIaIqzgjxh$a)IF7@tz8O5a zX)9CJ&h*|uGdge` zNv&36U3WKUopK`e@-(}Kr})wjZe?U_9M|_SIz8NlKzJTX+Yz%B1cPcMQyNX`-vq*I z@>mlLNv)2qmhoHKsF$Z;@j4PCQY*!@p_ndn*1|4+@X@#Pz~<-iT*=Z|ygBxoYd__gorieEsq?w@)9>Tgk8P%q%TfqDF8urtsZ`*RFVR@irBh*BZPrT@=&89F-1^&h&Hb52^#!yBJr{j!C8|F;jb>F&p&y&KAt zeCjP1bMERTJhx{*3kPQL;4{zj&~v|qOcpUd%s*a!I(?n3>>nKFghg}tcnBhi001BW zNkl^V5Y*~*OjxE~ ztDuZRhSTJekSk9=k=1Xxk}EGc9~CDAzC*06cYV%x8827p@9CkfSYj-Ucz)+juDR?Y z-udcF+4aH>Ha@?XdpB%mQC}y^=3Pxqx*R$>MiNK(CdM_2{+>>J->0L!osmk&p@Roe z>O8K#f3We9 z2kCGUKK}8~v0zp&3kLeBRV%ET)5kz}JHP&~KXT5gC$VJSEIQjt2%}j%Zw_NaL-e$l zxb&j)nKv*Cp%Zes96jwtcI`dH_Pqyr?WGqmf1n?&4M8SDA(!Lm=mcZsDi@!+hBZs( zv3AK^JlCbYt%I?_gIsjVYED=*pCk_PT^Fvoh{baT*!uhqE<5ui&RV;anu1qdav@JY zw~dcpeE~oI^A?^OtRYg$iVePKjGa}}22@Oq@U{z2;oOr~(_YFmcVK|&YK`hUucNEI zjpg$O$mNU7sMaVI@^rTr>1@d{(99A(Wd=}51LEs0Je1}J# z*vRbeRu;_}VE(KbOih>ZrJ%(zoU-l&EvPaFpb1#EiE-ixBv<43xY7bu5<#pIf@}ug_bfG6DU@SyaH*>Z$2d5S zLlD^SSECRwjQSuk@3o*z)JCj=R7Mb_Hj3YSPIT-Rl!TxD0qqvH64j&F;9>00xM zH0(@$fg@d{bV#(#?B*q z(7xkHqBth3h1ARA>F6;%p-JzVzuMn?w*mUvZ@4K4OtTr#B+A(0UMrN+4d5>g+z@DO za2!Dt+y82<@jaWO87o^vIYN;0C9`HPk%RFOYSCu0QV^z(=LkU}um_RW7L9S-RD>x} zZh-c(P2}HFF)U}*G&YI7A)X)5)!Bt~9DcvyDSmbLeFUx~j$`I8 zT+E&w&(qUd;9Fn#C#uzurSs-cmxpPaw-~*!NTOoE`rLY84^M5<_u8g)8(}}gvhlgm zD)ozReD+-eqtQeAp&sJ2byD&25Y>;}TT&u&IW`YY^Y+hwix>AEpkgE)Gy0j9Ib6qZ zs2ua^fB6Q(gNG>B6K?G3Wtbeawz6U07;pR9PZ=B;WpMB?l-h~C97w}pta#JszRlRg zICUdwn>m-H)P;y7pZV#%6n=C&NusE^0Z~vy7F#fmLMO!gXfB!7D9~>h#f`R@%p5DLBdY}hcr03bfKdRf$SHm3%thQqGFkgPx6|9^$ zi+{Z74xW5rKmYueYxvq%Z{TP}vHs$7c;83f$X9N@i>DrYft$bfSsvTGjm^*P;Grir z)0UHTwiL`$Pi+8=vNXe)3cN`giy8z#sm|EkC^(f#8N4zCver zHzzNj&j+u2HMiY;H^2M!uPC*5QJF6D$q&Du?(Poqxjb3d=Z<^t=C<4KMI&*9;e-_{ z*tX+EMn^_@@x@*I`H{!0*@7QXEVeMayMt9LmJ`K_a;3)8yIx>?VhXBNPCM@u`g*$g z^gmxutsarfWf&f>aMjgU@bSNY5Bm=s;fr7XDy3q9e8yvPa+=jAoy;5GbS(#W@8KgK z`xKoWC6m;uqEKpK#kx~jzwQLKZ{EZ|-E%vo)>bCVH9EU`xb)mp(Zb=OhaTj2cillg zpJ#k@l*KDo^XjXwpf#W4`Y(KugL`&SDi+bgVcq)myyFw^=iuNF-}uf=jExNAc|K7T z^QJexflE$1k*99EALFOA%EmZYNSlG6Erq6-bvf_kHT>+B+c>aqAHHJ+t21WKV*c!Y zzVfXfP???tql_D5#hlp#oPWkCJiU1fTeogUX@fF?%Pu;Hj?PXVeCW^YcMDN|209i5%LKap5HkdNe_)<_!6gq7J@~)(=z%zBSGND`4sZ=M?afIW*=yaV~7;>&a z*A20<#s7498Yv{wbIv}dN%yy}hXh?7!$HE>3K$!-u zD|Kk|(>w$tC7!TTkz&R}BS@koFvfU7i1@!P@Lpcc^>PF75^LSswcL64z3kYri}+1Y)SvqAiR=g*KOhr$ z1c6UBU%+<)q$9{?0$j&%#kKEX&6+h#PmSZbf(C=7!Sip@cCa)R-_xnfPwM6E9Loxj z!qOyE5|Jb#oo@IPGCo2`;;2fc8WBdCjBhgleAn7o3S%^h<2Q8y%`rxU!`T!o z3XJR1R0%i^#`6J*%$2MFIUO77bZVd*Bjm;=(9So#mQ`xkg z6u4U11|dZ@Op>5_WevL164T=ow0HD!aPL7Xhjz2zgmrXwb@J@Srzo|w(%RO_ zV>|cZDx0Q^F+?gMQ5wf_EoBafq@9igZ5?D>ACsn8NDS@mEyS_1p9LX_ls$N*aB1!A z#u!6uAhn(Fz9*mMx8MF2-su;CHspwT+ok7#8mWqggVipV32ow6(V}F+NI9Z!aJH zw{P|86v}h5Z_@^&0yT6zA)*>U- zh=(>j#@zlsdb`?qcFPui{_|h5Y{@(pEu724k3Pwfi7L)xn|b7k&Gh%rWc!g34(SXm zSdG^^i!IxBaMMjcxm?;QQag(;GMP zliTj%BcJ#%g<^r*e|0A!oaSwBd5!t~qkj^2KkzvJ@R?6hnVjO5TW+J2@#yJp=kX`E zuzA}qmY;YM8=iQQpWO5#&O7HcmabcCKKI!#i0K{9KDT!uUbc6S`4|8Ko&? zbHqu^%|E?`s9xjR*Ij9T_~Y9|sjH7{S1;eb`A+7v23&L5x#H_L{*;+>=aFk|hN~%!_;X^SgU~%T=#D*Bl<15Rd-pF>biw3*2@0?|AyjC%O7n7n>)Z z*d+E1P4VS#ew|!C2lX)Bp|$0fO9zpj8A4gBPbFROEb?rdgS7Z;-ouS%Kp?cT;gBf> zRiN$ETg3>+y8FekONh_tWQDk1BML*Sw-b&9l3aFhaNzH}4axn7CF)NQvuvB=s2S+9|${6w}5~PBgxNiq_PXWfmk!NKR@(2kHW} z=YbLoO_cfF!%vu#mn{-~ot@N7%}!8-v{P|oNQAvM#<6vQa)Tz7$cnU6vQG2tmZ=Mg zY^GErL^F(&hGlIk7H$+ai2&E}KuBU^@B}#NSs&HPo-xJ+UTy&XhV^m-@Di(5nW8)~ zMp&z+Au)n%#v@3U88TU0I6A@*WCAkT61DOX zgs^!62Fv$%(qh_iEvFTXr5+iJHmDS7P)S<%1_2s{($?P7kv2BnMyE$eH$XZ8o@@Dz zz9(#eMvV$fTk{ zQmapc#O44PAy7_`ioPsr^JwYlN)mJ5xr0+{1zW(E+Fuv%%NQ=$Ua-QLQ>Pd&>Q?|hh{B*Az-qEg08O@SLgM|X42utq=@I8c$I zt&ruSQ`fR(?_uh(V%M(StXj2-UvGS#$#RXU>1n!4Ia>2svcAij<%?LbU=9Ow=b|*^ zsIqAJ0>(y07#bYpvJ1~*-lE04;SJaDjcBgql1yL3Bs_>HLpCA6IL!WKlu4w!l_p{ z{ftxbB*f)O3i&K=di|B=j8oQ$H@)k_%xKAR)m4{q#rbFAxE{L)$N20o{=oj}5UDl2 z-95B)_HfGj6S(M{Q^ZvlpM|d@PFlT!`)3c3FP4}$(9hy|vsk)#KDoeW*@AiWbav9w zGlRKvXL0KKHD<%p&x^jUP6lSoptZG)l9|CJ=bypSB}>e{f4)I1m_3VPA&>O4EL$*> z3(q}W2$gWhA2-s~)D9myz1h! z#bbZ^6Ro)n?Zup>ZW(zj=Rqs*0!SiDY19gmgvA4Wbheeq1RY#;*##o5Rru56&oXad zfI=?Is-<(d^5Qdiarb^+JUq^<{+YD4wQ|t~XL9+4r;2UQZO4-ivu6&_)7Q`Zh4ams zC#~RtKRzsq#S*hUkJgqFD_1OG<%-4Psg0W`6$-Sqw9!AKm-Ek9OKWF0dtTg&;|4g6 z%YylHx#E&@>FH?UyFb0#Qf5;MsgcsEc0`(_n>qmd! zbsGxj={i!T)|9GFwot_L1187E0qc0DVuh|*K7UJl3%CFBZpLacvuE{-dOblINhZjm zl%gC~DT$KRDoDq2>1z?On^4NW;~3BeUplvH9t?8-SNso1fXtDeKqry4PRJ z>HZoc3-s1Z{(s2k}E9`Zhlz*Ori=O8R&-XcYc^gE7#)n;ErMT$_9F_j8 z0AiF*z$kQ5L#qUn7Jn8|wFRf^Xe!f##Pv!#E<1+&TPHtF94BaPg|?nhcz%v33IT;9 zt*F=-g;p`XpG5;nR7;(S1aUpGsC-hv^;`nqC5r508Y5E2pwu2zBp9uzhc+5Llg*)2 zg6rC#nb@&0^it3mPmuLJ7S0=B&(u!q4k8^q9f2_%5QuOPsfg1EVI7==bqO%qAk#n-gmqd{7z+T?5IgI%Aav|Ca3tDTzLbk~nZU8O zNdikVF)3vPrE%RXS|>Qd;7RLtV2r>O7EK~;Zkob1bh?pBbO=hj_}0tJjy+TN1JCi0 z!l3;Op0HCUhXmJwSV2oMOIJr9`**!SxaT?I-X8L~EQNfI_L&Q~_x>k1I2zJgvgx?B zuufDD0Z4R1bncTRmJb}oAyKu=j_0<8b8A ze&)?zKrM=?Rm&8MMWpMXl(KR2I7r7OkrJIG%{#!v%3fa~5m<_s{r^scF*ZxXG`OJl zs+Bqu+)NfvCnUoX3pbUczdPL&M_;*TYmQoN~fE7S5c(EzfM@#gURGk%hp)hkL#gTnjYIYQ;orOC1G80 z>pj1xtGx}OH9Z||RO5tEeaW*r?);&y;^2Qcdt3~l+(psci(T042_E2`wmf_nq<%Jy^M_v z6W1d#dtg4RSFd7ZWYh+{8N-7cw=$!zpZT3F>_0G!?|Y1uYaAIGqmaun&^N$&XRJ4y zcODdjM~*;{qdZ+Elg~4M&H`4gT*l;dnL|S(B*rj2HbGpAS-WbDIQxusW_WB|B-$`J zIYCh=9LHzj{JCP*KtJVbh@UMmUad1eKEbU1SzL0-C2V~DAhk+`iZl#QSSO*C%TC~( z?|eJoyZKHgsu5wL86TUVr@fu!iO zw(c6lNWtXP6a`O;SDbr3A9~+j#wt~Ue2!Ray1To@d1su#RhL~vJ*uOUgt%H}@%-81 zgw-p#;H;CGt{dV+F*!EI{JHbQ(#4B;WaAFX)f(kUH4`ljfFD@;ql*8E-P5>lE!fla zn-}tbFZTax86nAr69}VF!cI+GUqd9B93LaB*|Rc83s4ExB`A=%NZQ-mx$oWwX)oo> zbfrcVCBk*>nHz->j+V3+TBs&9q>#j6oyo}xQ9Z&h_+)%P)hrog)jLQ={XQ1JvvL4ZLSZ9&N(OQ;OnU))1|Y62l7B_}3R z^w0^^!#XoM+nCwgi{nX*v3mka+rep+FcQ1$3bPy`OC-~2LVA9ap3N9z(f#IgO(!o# z9iwgmf`(YpX@Y9a_e?2#VQ9KQ0g=)~%1(Bq6v7zue_&R;ypCTlU#OQ@-}v{>eqiz9 z#a~~tcmY#WlXP_TQ7E*av_cqgQWqbs4MJGTk2bawwaLNK@{X0pU_(NTa8h4;2PrgK zX{4~|r`@9@I2n|25lNXw6Km2NSPGHWE&@k_>$xO}u{R4e?LPH!jdY?Q@C8a~8%83r z2fA$7k2(kxLi!k^iDE?(D}3L&`2dJ?Vj!f0J~mLE9%t~#0Y*nh z`Q0BLDu(mSW;c%MlC{fuHIa5a4+}nM^?50ihyB#>dI| zKCP`SOx8l;Sdq!)@mvq(_(Vclrie-1VPqr5<(LzYZ!}&~qqUIZg=sr^kkUrdTY8eg zm(uc$4XMqUrMScfjAJ>Zi3W_NF)1NXLRxWDN>h<3s^th!ScF|BFKV#{##q4@+J0gh~8XmTKhQw0XX3w3)xtCtfL%;t6yLaxQ z(AGv0MN}py$z^=z%$-MfZ#QFg&FWLnWdF!02cFwPuC0qHB^Wz$n8hnsuy5Z1`U*ZP z<_++`mhIG}kDtj9R;mc$k<_bbt${iE^yNoB)yp$ z)F9EI4LQeD_00y(I_4BqNPi)~I4+UWj8#J>6N&IM1hol@!scDLu1jLzXySr&$m<&I zuDzE@6cY)IY6pZ%iwRlN*Mf9hyiAs{a+QsPQy3(^Q3NWa-IIjcaI|i~x1mtFU%fmn~pByLf8r4&HvwDq`vLvxhcu>cW05TD5@tpW4b3Pdv%RC#|5py`3vB zI)_i+@Ldia9VQzDOdFR>CP%z?8**}(QZd75CFUPK_8~?N9pE>&{hZF00=2Nt+(k?I z^!3;C^pTHFFm&rlX}mKI3!uFK?%RMhEle46yIWDD}2kv~>4UtyTc^KnuTUFBQm_TG%>V z;ZP*$$~w$xFR{4bau8fJUYo(Ic8w~e5RCO*S2je9q6L7lx1*iii-9K+Iy)@ zjx%)R5DPl9^mMc_7HX!7{dCNl!=W8pnRs> z5=vd&?BBS7!t@}s`#bQ03}fX4T6^$Zha?P%Mh?=~*+Sy@Y#U3MvuX`OD>mM9Cu`>S zuzJ}-jtq^kxtgQgzl4!W-F|Exx4EYpl~_t+T3q>YjT3uI?0b3x9NER9IeoOYcQ80K zLRj4^o9L1~Te zdMKq(M&o5XbfgfDz?BZd*zhpdbuB$S0uJ+ett_BHN;@mj2*jj;!1tf3-2 z%jq|b8IGl})W$}+@|2aVUAmBu|L`sfogL^zA%sb-CIt?PEQY{hbTz=|m=FI5k zyZ1auPgfV~7R=(%_%x3`vx5_6_wcVDcq>2n)m{94(@y3O^wCkw+eU11l2@O(j$EO@ z6Wd>8<*Y8wJNZQ3{MoM)5ANlOU;iifZ{5o~Kk<3qckQb<|Fm_y<}bZtPF z5fX$8Lf|Y({PHyaV#$utG7X^W20_k5Uy?Rv?bjhdpxkVea4RL zsa9!jB#w&+{9{k8@mx}Uk?l9r`BKC3OY4;Cq?*nr24HFe$CJ2dk|aTSIYf|2Uw^8q zG&Jq`P|A)G8<#^Vh+|tkYK6#VFq5N@$sxP|Gc^i(wlaIk3c^~A@k4v*?CIt^pZzGp zX!agFLN=S_mZx^|$7lC3vo+xQSD!k>@z3l}KZhM9!dv~L?AxRV;|EEuK=_@ZrVAy@& zFn9dw4(_=17CUKj1F~~g^19bwLtndXy0-1v&ux!yqnc|+CkX|S&^5RNJ+zr#7o1G3YaY^bFw(KKAEi{OXLIuZC%vM)3{NU+VljD=M!l`kT0N< z1ShFc4{PL#Ehs08lgUu4R!FADNun6PSh5ar`4ZJAA{$Opt=5Rz`Y{VvQ}J8U;>9+< za(ob!LbY}yk~)7;+Pu^~-2fB*TX(s%fiQ+#br_i>M0Ev31W}!f&OL*zcmJHIR z#I=;~FEsT~QHc~8SJK#;Fu2mSpe2UD z^Kqm@HV6pvC5$o*kB;!-3p=S)D@a5$!$u_u+CVN}WM*$Kf$O4#Mn?*yz|Z+aGGOmm z$XMbrR+kLnp126*RG=%4kY0WYHlxP(FPUCY(^ZQM$pW`-N5-mPsD2a$* zXg|u!U@&A{Nyd@HwJK}6{R6-G{*6n75HCjp{|)P93eZa|DTS%kV{BN5CJgJev^vB| zLM{l10Y8VXf0?uTuOmTeaYk4{w^3)WK(u^iv9~B znzo*i`GPrv?PLM%i=|d(J?=~n* zE;cyLNLxG`d}>B8S({@0;sHMKrmOhe_kPaN7j`h~>@}=gv5@cn$X1Oh2dlUG?ahLP!MuDtks{^^77;I@1I!0xTjaLGsB%2c_+u4lLM zTpaQGGd@mxKEwCF@gH3EiNEK?J$snlH-oJ={eoq^EnIQdIsC_W-^a2=^LXp4FXe0B z`w2Jy_$O?Vjdp!h=S-@Jwg{5ZP1mGjh(E`K!GB#O zG{)6&WXIRdjvec1tyAH1YA4w&ye(%9Njiek8k1Vy*}^&{03K&$Xmsl8BvQ-LLN0w8 z4TQkzOhmdT7{^WjR@yu@Qo>D=HX05_C(T;Mz7&HgwORx*O#~E;P$-kW=Hm;dl&%Nq zXWB`viyJ6~u#R4|blTV8xcIp|PBx1pAg;#*?cGclyLjg}Z>7Jd3mwO}LNi!RP@d1B zO2Sv}euTI($)c`S)-9XQ&u_n%u8vN6+FRMSV>gRduHe(3{R|6c53q6bv;5urKFH#^ z19X;h?Ad>W)`biCz&oyG#hgBV|KOka=ilDViK|x7RtR`*`wO(Tw)3N({M_1FMvBKC z*}%FJmQ&1Ud2ZVa%Ui4?g}|EVGiS17?K(C-wVA^&9%1#Wl}wJ0 z^6ZX%%x)>LaQRX;-1l2l60>g23JeY#x9?$Pe<$4ovw7&QXX%iF6-yRStyI}{bdvKf zx`aT&J-@k|{-V#~`Lh`son&}?nANA8Mx|2Y*=G*3q`!~Owl;R|+=b`GB;7@JO-0CD z(V9~@X~P-Un=WQXx@1Jm`O9Xp@xEth$ro6$cpgz$}@6Q3PvWT>7O%)1j)hOd+2S=lkt42 zQN+we3z#Zb3CmL~nlqDpCSd>2IBmT%7@DkLrl-hevq+sVK0QWBXd*PRNz-$UK}=5| zRg7utK|4M|9j5_pH0H-GVeGl^-!}jaKtK{_S_!5Ht>azX$ilER7%8OHo5hi}#>Nnp zLvp1Yz9Yy5E`vvp8l*2=$4w`lcK;|A^Gr=unV6cg`9gtDY!b3w7T?ztfyt>V`wku^ z>jxCFSqix<89zV@Num{X72EJk>5&+XpDkd}h&aUavN+PgcO6_mL%BLlWvar#!^4aW z4>MVw#t%G#Y{qH{j7BGlY_33Cu|!*EE57ejuh&sEg>WTa)@7;=&yCeMQuhe8!FVoF zkO!ksT2S{h)@Y<5=1uq66t6sXg+*#;kxpz(V~;t0&oOEEV7fmF*99G;{fzw`0|q;B zPmD$i$NEaVy#A*3as%*^%hUBRq*|*mRj!cF7dSF_m`o;%)7FVAZE-9R6-EP632-_XxykmEMuZl4?%sBWbgoH zYMhfVJ(mX`eVlSVVOCEkwOG?OdmbQC%p4M9W7v~)+|WxbFcv z+gg~hat*_wX7BJg11r{I+I!Q?1=pgnsi@d@Y~F%&TpAq4>i95~#4tEnrep2t6xzD1 z-J1bHLZqP06HFY~!^n|?EL^slVyR%!VIc@riY!YP;W}1TpcS5DH$+d8Y8srTC92lO zqPhqY;ZU8Nrlk%yHL7G`@H25pA!YHV(p(m?Uj9MB{0hzkFO$8@-frW%RLd9Rbb4zS(Rw ze198a-}JEr*xz;BRMT=C|5hH`DC~5^jx@D4RvY0;B#KCb&b2dLk2$(;)NWb^2m++% zl4!}6qZLTNFvU56$I-!~y!S(I<74l84?np17M|MjJoT{7h9{r0_pj@4$t%v~;&V^s z?%zGca1|bZ{7G88^#qQfRLF7hE6(Ml6BhG}U;c*ud-qZg>l{9Ckjt;Uio0*Sjn94j zz2?fxuMnU6(pSl}&0y2EoqYO+AFycNY_7QA4311pLs(%&*DS6)b3G5=_G9MHpT!$q za}D=B^e9Khs=Vu6Z{rOkJEf4*XOkW@W@b~Yf)Yi@o-@TdBFF2cy&JLcu=hrM>wusMt z=0jAfRlf4AA9LMnFC&-B@%ST;aPFxq`P7Hs%d=ab<0rTOp3i>l-8}KclYIPlw{qb{ zSMaVkzLwj5bvvVVpZwDG{L7E-M22N_zRgl*RBYcvH%NhQLyNBP?pK_`Cm#JH1;^t{ zpZf%@r5rbW>n7Hnb0M3b-o)CKi}~>T-^|Wkd(H13dQ!aly6bq~`?v7QS6;|_uDgN< z9(t6$qji?8TFtgiPxIC{zm^kMF6F1U{f3zfmr@Sv{OmvflaGAt?>J@cD!%&7@6$PB zra3Y;B{n>8KmYRS4|4h`C-d(&-ehE3pSbV7`>6)-@%LXxM{9}y_gg<>^#!N#qeq`( zDAeHkpb}L7e5;q!>aRq=$KTV(-BUuO2k8HKrFr2P>EL*p#JHHqq>qtu|5Kr`(qO{G z(lZfcGI<==rCg~IMiplFwUWf4b=7qx^>n(M)MHu-d8Dt=Dnr4`Fq|bo>mt zQUMj!twWFy6bpH}y1NMi9}QE_bo zvT#ztc@lweQjzxYu09Pw#x(i=(n+npg|IG8hLp0F?k(y5qvATAX-oy|J||5B^fbma z?8;tV|DWsS2H+)DA(z8(Y|uteSC{qMu7|X>lrR|TiAJXAts{lq0JKgK_;i#nkJSor ztaeZ-`WYu0*O6&cAPC%4IAcuePGf)Gb!gTRN*j!BbiJnOWav8LFX+jZ;%w~Kwbd+0 zX|;<=)0{MDZJLxJkph(_odgI>Q%@zO#B;5#!AoC=4MmekVMvU|X$tlYTE#d*;ADK- zB?wtSn1s=xqht#ugd>qULAicfkQfpr`Csh4SAb|*ghC+;M#z}QKgr>lCIp6QnIg|NI7ehO`XN$g8G{EOf|a< z5A?BiaEQl`o<`OOna&Kkm1wQWteeg#n~__GB3NsY#yGc#;;;}VBj_0RA3ep+=UoXV zr=4aj>#wuWZZj|2D1{3z(Jm4`kj_HQO6df?fX#E##vB9N&gaVWHqrRzJ)F&)jazSe zTK7HTscGg<9%J36&7@h*;lqbeqA0R#FL_m9jaY&{rLV}-4674Lr4pX!(_UC0^qi(5 z%QXmv7x>Iij5B%Zb|%i8#&i}rb-2M_{?()W$$xt%*Icxns1#5QLbk12!`R7_EH=*P z!fjjV#yOLxj?MX41%zv$QEW0QQx`3Cbe`5+fMQS zdDs`lxpkB)p*%NTf~A5SEH=x|J*;{|ao4dpk!;V2#8@|(f^#|nrwr$u@V}^)mncYX zqIK@|oLlx;uT=<9oE-)syrOX`P{yK}Ialb5qLJv)7ka;A@q3x#wJsI+_8ijU`A$ID zd!Ot4+zTp1>DB@|cMXXYU<<_18u!32(qu)^ux8q6q;iWxZ~_TRpDVjp^s4> zu{A6k9%S9RHGKMWH}Tl6$2mPV&dT+h*!A>5zH!Sf{MOt53o5Gc?H}CFZ9lk&6Q`$n z^$oA3JHN=ke);QM|B`DELh_Yw-NBb`zJ>XP7QgZ9+j#vOUdMrF_TpD6l*(oP^6x$> zKL3@kvuoE=yz|}f#uqSDi#T%p1UKEGNv&)2o81KEDTYUex#fHJaL11xWO{ai8(w<@ zNt#fKBCJ&W%ja(9-uoY5_x=-HdhLtQ+R)e6M>om%tBuMDOL^lv+v+>Zv5Tl(V9HvQEK)k>KMAKS~{ z{^Q4)o|vSiJ!G;-UnOMuiWPkKj(a$Ce6xjE)RZsaCo9+jnqq|1%soc$C4F>sY&XEkP;b*6-iN0}ua% z-Mjbki(9sdVHF_4Dxdz!t=#+Qll=I{4~aLt*GdxHn8#b(6a*lLp(PfzDl)1GgUV<}Z5e9vdFT&Eeg=w@9qt%>{+f$)h% z!s^jcf*_!=xInwrq22DVxHw0aq!=^qzN-?*Ai`4t%Ja$dggoiE3>LqH@I#cfU^8r< zA%!9;SE={a34Nc?^RdFBJ1N2|&XUaFS0beE^3jh@cNxz@nh0_w(P5uMM!XQA6akPS zmRy&tP(7%3=^QH#Hh0EK=dvfPcA`bkA&N#86G@B9<)Ik5O z*gOqkF$CKG!A*W{73;YM;NMtD+{{WrnYF9eprjy9a+Fl`68U6rkXJxZ+7^6f>wLHc zqCi}1dH2=-tBJtjS+?N7IRwCcpPo?Hm?f>e6Zitwio%~5 zjFAXw34)%OQZ3PwERJrVwX>S^{i49J0%x`BC@)?hollW~u%y5`yR&MwjaX1T|kxh@2B?;w`RfOe` z2OoKy=k0hSK^XG%o&zv21dDAzIas?0Ldb*2bu-0e!GN1W7#BQdbxiCrkou+$@0}}umdX`LLuFK(nUI_lsG86IZHi{S+{;2V<%5CbNVD}SFL1v zp@Yp+Ru0xka%i@@Y+F4_P3HXb``*K$(^LG;U;QKR`-?x|f~}kQ`j0=tGy4yb&FFF&}K#qntdA|I2q$QEZ2^K;l}5ZmcM zDS$k~E>40_FffSib|B5LzK;mQCAimQ8MM35S91X|tu~YmIt)?9Fmw7ibACXje~2WG zk;64i>RhV?ZptN>1T6a8+uKj(_Ws8r;c2nRvL9q1-d ztz)ZIm~XfSwtwIp)GrG3Ez_iF?gk^ihwddVD|xQIvUZ7%VvPk~l4nhf){HD0VOndB zO}AN`TVUgk3R^d>=Avzz811ic$t4$Y_{cG8wF*(Wf**Qp+OnS3e4Wkf*Ru24=kesz z&k*?~q)NH+ipvpYe1efj1Y0XdDwA&GL z?F6rqGycRrV&Ra!?!qjUQb3~>b7Z`MNxMiStvDfSH__H|w$Ws9VF6DnmT%ZZJI(0C zF_n5hdv_nFF}DCFXWf>qAU$U0n~cvc;`u(!1E)DVHqP^2uE@JB{HR2>ej6sLW0P)S z0h-fGTgA9RPpS=>)+}}t#^yR4JTk@R^GdWkZAiPEooTR`Ss2ae9w&0RBTtP}l; zVxS-jTW#AD`N9&)DhhvpTQmta%Zq0~ff5Sg?wdS!k2L}hQ=F})uu_*OrAV`^1hN00 z+~nt0vBZD=CIA0hpZwA%FFCY(_ml7Vt>0k%x^;Au#JQN*XFZUMXRd)F3f#eYz2e;z zZa`9bSd$fwKe#u0?+hwZVtX*VMLO=U=oQ{Y7hQDHLP{spvIa~cIxIe?lmOusjfufn zg|-$|xCHgYma^A*BMQEqDy%LY4I|49RwqSMQE=$#F*SO=?T+i;OaB!@&}z4sou1WGp5gl*UE^Gmk~Ag2Qt$6WSj))pAV*G}p@iWDS6#wAk37L* zl2H$Rtj?HR>@qz)M;b%~qpL`w8cCc&nnJA(L5R{BBkdWcpL&EFUimWK`D<_B?Vq}h zsksGy>6%OU(!=|R+bw?Yx+_RDeB$;;*m=Pw-hTbHyzdLQawPVUQH0f+;cS76R}b;f zSc7hy@{$cBoN0DBIG1t3P{39{;n?&7N5{_4Unx^wx0PAHkC}FI?)tk;=HTOA!`XwK zEeNGB-45%5l($@WEnj|MH%BKHxpLET_BUc$%?>+PS6N*z@%24tAgZxFjPWXU_RS_v zm9G@G+k&|3=m?cMEKK8hid+Tm=e8Cgs-XgpdUuYdk>p{OvPn>ROsqne04xN;^IUV{ z2gPfJrA-Luv(gbT(i8d#%p$7%Dsn9araY)`OTMK#nj{k-+cTKwr`ocp2o5w zFodTMuxw}$>v`-RpC@0ly$6BzrYEiuQpycYq;q_#%#ZW0@A?(`Y87&0X}8*RS_|yF z^aAD@GlWsZ`CGPdWb7~g}e9FG$!tGnxd+;#JmkqOH{c4V$nc(R|C#aUov|26J zj1D>!(Bupc4bzxkU}km}jYRoAD~1QDlmZqy32Roa;HK~0&4=%Pnu%u0mWtt1@A*yA zZU+r?Ix(FzVX&`{v56@*tXj_0f^LG#k!~SC@9M3%IQYwX9d-W9@I&z%3MuSebLvAG_gMI8cZyP_p|6zhK#ORzn z&)BefC2Q8MW7iYA34(xTvq^Jdfvc{(5-;$1p}A8{_;~bfYbYUc*l2x7ZH@4m^Fk&`w*~^Lj&oFlA zAeU`h!;Te$WD?>eLm;TtB4iNJXf!x_`i$MUVXgSy?LV^5zwBbMal=Y#IJc zL|!qJkP2fo27^uvK{X)HGlD`!Bq%*Z;%KH{bFH z>o#tn+l}$0L@9~z!X<88o)`Yf3jDyg(hGzX!lk}iOSd^syBj;Vol=0dmfYa1+_ZHQ zX&iq)D3!=^i#8UcQ}QGs%eC{^S58c0gbU}gdFIFkI!9}RAC}1ToGeYzd1j?j!c!jF z7<54q$Z}1Ry5c8IVkblbY{84q@*L#_nA{~BCz(cIttW*rR@f}hgw~D*kQ+;$8yAvR z6tHQQ6USY=Fd{{9YHR}ODN6M|u%Lp1_8|nB3NXqmAVPsL5}P}!k|?HxmY}FzBw9nd zI8Ut{;YDR$`}5a<%~@=BUBOdW7N%*AFC@c*17zAbp>pmTC951YC$TPMN|Vwp_mL^Z z;$n=plH3I3b6qlH@T5RmM=$biju4I~of$z|qydY<9&(tN8+KmG>8V-1y>9|kd1)Fd z3y4}+L*RQX$`T8iCGN&cKGyEKutc$7VSyLE_!8!3X86+&ew-i-85tdAzTIN~?%llW zzx*0c@7YVG-jA;nax19U>fH0t<4m_xD*ZL~96W-smP)yVkS?~~lafF=YKFvMbk0T$ zAAav|)5$b%|BDZC>E-A1>p%Y@hN>0*>|L=nxi^K4qRjCcI%>-f=wyI5$pSyK&p>x(br%XdA(w&6amzv2Q)o@Cd7qnw?X zU~N6*U9Wio@A~W=*h&REd6rl2+{{OR|1EsrYd_%T@7~F${_s5VU`Ws)zj~;s(+c&~z?tTLL`iq_1BfR%6Zt;e9t8{f|Fe&QCM96QcCZ+scgzw83W-uDR}d2}!DfB$bYpXA*5iSHst zS7R6Ec*TY~?|sAT`KvE{n+NwF;FEvwW_E1ez%TvX=g5){|MQ)%<0E%G#N5OLKl;aa z^Z4;`e&c_Bn!kVB>$%~oi}>|__#E1gn3$So?fR8Gd2*78SQm~!y}?0YMGBxKy=)99 z__o$M^gzlYw65?(m%bDD2(hGRa7t_oC|GRpTW`IN^Ea(!adDA@Cr#5CiRo6Yc6S@A~v@jF>j*{49RCM!GP|TiT)Jr5HE0qy1jZ@=*^Tz&C*EVdJNA3n*q?%Bm{_dQN23dq_` zOlyH0$kPO+Jo=)L!1u|8WIoO)^$)UP-5RVh_(6bIu8>IuQN)pMm)HIE$5~zW5v_T2 zo;z2YxJx@u*|=^sQ5X`HLUQdiI_-9w$*CzZG(1ARR&|bQL4Z;oGu@Phc868&O9*TISfvP+LP^ULH+>5!1l39f z%mlfCYOTuM4?jV@8X-L&W1tjRGh8XC1~?Ys|_m_%=gy7SP=o zFDemt%iMOy-3*Nk5hoe3tddvzdHU2WD@O+D3k8+PX@;x-X)_|Xt%;))A4vvK(lQlv znCs@WL`dxW;0KN_=0)TPa;xx?F3l7BFr(`b%hnb&M4nar_pbA^tUe2;vU4Kf9^FBL z@{w`dxjF@2Nhti~f}vDG2TG+51It3}-HlBEe_W2fvx4?QO4=bPllk|YUfnjtZ0W6@eW2(M84 zdByZu3Q3Ma+ad`s&oS1J#EF=hZ!J+uP(@mldiGS5r3su9GZvido;R;5xRpk`AKJ4v z>V*vC`8i63wM$0(DhRNmiBgK7RC3KqPY|RvIxLe1B}@^u?#N9NL57q?TCOzMEJGBw zgGRe+28OUyrmw$`@!5Gk{P~+P<*M^w79J`HFw%1to61KjMUKE%%28^RU+4f7zUN~x zq!zSLco;n8(M{8WzTq(Oo;STLiY?Fc@RdYccVBXCob$u<8P*K-(;o#(oa&x-wo3^6hf%^^gLa(KjuY~pqfZg2Wu5c3GYGzWE0J@}r+-``Q(J{fGC{Y%K6gFS?Xh zT(N_XedGJA8K`h#YKAX-<2EW}-1opk-0=L%IXixq>z{uWFMZ9mJo?NLx|wET-$|&| z&hh&Fpg{hN%f7IH=Y&QstjiV;PtQ?28k2;fkMb1Vh13alg$vAc&^cgo#Nq^b;sOUp z2Krbrcp?At)o-z8`7$=IUrm2GVCQ*Tx#Ql4SZvIqe4okb20G0M1k|F?ohm|L{Sw%e z$*E~Bzi0=SAo$R+FM#N!kb{s#Q`56PwS|77K-WZ2Vp`RR8>dl=U50`xi>c)!U-%Y% zrSFpFhD-=YV^jf=?=hK5{>M$XGyKCxvBn_7fW%mIWeDR7lEy4C9+h&1cG5svMZ1;Z z2Ldk)m`x#5Lp*bAzThK+F;fslsL;a%B^pUWJIkqba>6_(iafe;Mj!-7j-RH}?Gje1 z1cA>&V-_o1(Bk;)B2syjD^(Vn3zS!^XVR~N@R^7^bWa{4Dn)d<9g=b#23HXq15=YY ztrbL`kDqs8W{$pch1Qu_%2Ac}?n5Xg$3Nhr+E0lX;yy%)s3W_3>!Ww6q2|sx7Nyg_>f-rKFo2ZO2hEp>w&fNVIRu9+Nwq-4wM+fPv zR_P=OvLcaqq)Ci4Ia#7np>il1hM*jhCmGsWtblS@BJCz*1uCIDOWf>$0$=!aI~g|e zd1`EdXJ#@IFT$_*g$?*I4B^+I3tY@M&QPCzWAD)dv&(f@ze^;`q+ zAFRDkKKZo!Xo6FR4*h#ycHc)n{*n8R9X8?6U!8^n{%^qkUJFfjzY+2iy}fQ<^Jrs zm{_~?`K6DI!5TMF^rO%uRS`yHG6&lkojJ3VAav7ySAet?utdIx6oS;ablFm= zLZAYq5+n#RV=4R2;YSHKMMw-Nz_Z3_E^y2Rcik)&!$P}-FgZDrPC9^99yt__s6IAJ zabzs_&~&;^iKoP~s6Wr*rQ;l%Jl`j4H#q+E<9z1t{)B6ucNJf}`P-}$)JXhv2vaUn=F$Dg^aFA?L>F zoI1$H^LB7@dY+f;?BnhK?RU8M;3+01Cg`hG7?LT64;|nwFT9Y=tCsQE+wS7^uY5jv znjme#i!X}9ILlcvx|~mb|C>xLEC4V+KhG80H*xcK??g$DAPmWp4kyRX@QN#T@aTc# z1--`>g(ij9G)r{19_-wEUnfaMt_>Hi8R6-vCJSdKn3$ZT-R&^bSYW=B5ClGRjXAch zTScoIvts#Z(HuHDOQ+RjU}%{1OoPVUJW@ywPcO2N3Lbd+01rN~fvsznv*($El&f`A zsX}w=4EN29vHO>Pkwz!x*u)I)+Il@Qa&naNsCyn!xq@yr36w$`jTZ)3sj#Mt3QGttz*maQ zSjQ>0mZZ~hbgU>s8cps6M8cwi0Nn*Y2q{@h=nJUUsZ{Hvoi@r-_?~ooMEUg9>vZyz zyw;B-#7KqqG?j9RfqFm6YA9D(EcZduU7BpFAi$3*l+zZ;>>0|{8cCj#XYmph(Mn0V zR!3SxH|`PyA?2t-H|{_XE)~`kv`@6VAFgpL=%8NUkdH865DycD4D|Q0uqa5R!V46B z;NvF=qr=OXo14KGmQo@976Ni@@JnU-M^`X2GlkJPz84ZzDhSV`5(G{Yhb1qX5MwMh ztgvFsDyGhife@6HB1uvP`v$3$%S_KsktHcg3KFfUmP#xxEHEG>>sPMi#F?|$v&X5d z*hD9YusXwL2_vE4Wf!jJ;UMMBFT9k|{u&>;>3h^8pWlAV8~Dl(ALPN)3)pfE;roas zy-SapB8sQ3a{&rMgU)jjzz+f}B}c{87E!7qmU$eXI8FNWajx9HhT;AidA9=?WDudk zh(J3%&UB;0L%a8Ly3xjuN(d?OL*F6tMiWFOthJ0aJDhs-0FRV>R*&?dJVhsQlY5iK zY+g0Q*0n1TX^ILIBsqDW;70*|Ze0kcfhek?MVnf=gf^B;W(0vpDJ(Ow7_;}lID5}7 zVk!gFYZcPMVJxSxGM66cjNA|D`W2@^6cP`M7u9Ljhml!Q&5p$`Q6IH7Xi+p5N_p0npVI*RjO)1u;D5vV zz2E-5Z&+);^`i&weEl8Y|G{q@I&}1|14o#ioI&{k!t=;8XL05QAv(*P?Po6r z9k9Y9GnP{)#{hwn66q=OI6;*{td%ZQDswhvE{IGctwnmC%RI<4{4gv;#y!@AgF>b6 z_LTG#(sN$mQc855V{=DW5K>}_k5w4Bj|=*e6$0Z0Jo_N9!ox9_4c25Bt;jQ$AZ7;{ z;--s*SGhGgz8^T%f83!|F3~X_N(ek9P@-^UvX*k-;VFeN2Hy*uOB3#)nQKE7c=&#i zdR$l}20kcLG&~5x0x9oJyOZ1nghfF>oM<$X)CzJ0f#-u?a)+LD&N4bnk)Ds%330ni zD3s%lr_NebSc}jpMkquO63kDqIf(i2pZ+09lCblV^SNNtT5O(Dsn&VlyWdVX?$Yga z8SN|c?zg^)n}7HK$6Jr{)rX(Kgf$ZFpjN4z=d|<`64wA#!+`j}Z+PX^Yk|RtWs4g1<0{KE9Xro3;~Yng<_x zls|mab@t=$eW$qfv8OpPHqI}<>}u8y*SY_ReOz_X`Se#KPS4D<^OEyfyKIQJfAG^- z3=KX`OEkL=#ZTVMNgtXq44x;1QBJ<3(r zzmN}p_8YWX9qxMQF;=c#jY4CLhCHKIt#IVjS>_g7SSeX(b%;!Y3JhT>q%k$kYhQc~ zlP6Em>AF|~0 z_Z`RA35~f$s+EYb@w2@A`B(9}mpqTZ`RFG(a%!B$*)x3QV;|)7#3XNf&tEgxSECjG zfJdG>z}YjWdF`M4K1h$xeEqxJ{=hEQtX#qB(PgmbKIk+c7kDeya_2)&aP-tTT7@oP z$QX?8^gp8K?OmXQ#R=x#Uj=s70~?KjR2#}t68OHe475(4q&q8_P%a?=rCeTv zO=9wLL~0c^n_=>lEYIk=QJY(gmQO3`l zMR1hrs?D_Vuv!yI!wa^rbG^uVuVB$8EcgQtj_YU{K0Og)!1w zge*f_Lo3b6=tB)hcv%M_B$*$P2PKD&>zp8MQyLtCEF;Tv4$XAjJ~D3DXRPJ)o|7CJ zo8_X-E7-JlB_k^a$aI(7g6~J{J$90PCnrf$S3eB)S6Q}V1*OQLb&bUZPAz22=m3_j zC6tD4k1{J28i^JHPe=#?Oi)3i2!tS%sxUsu5yo?SuE(OXx)5SJYLy%M^=5v?J_7OL#{AsQcB>Oj&oubjH*V$gU%Z)Gt;Xo`<*Z+~hWbFi z-LrSU2s{sCV6w4*l#)%GHlVd;aiIyh^Xbj4C26-H%Ms-=e&~35Zu;(can`z`8*l}< z@1wIES=bczTtu9UkUVGcC(nrmMIjQi#U@o@=pb8TkY0#XUO`Q8sDcc9mwqc<7q3&d z`BmT&dXb9E3kxBTK$;9Ay(I@Eivm?H8WV~!Gq^)R7SOCah^w_aLMhVS58_qplrFxS za=E|oG&cp+1LxY5r;us_B`M`i@}%qF+Q0{?Xe~Ce$|tPUKtiH5O`!;-6HujE6WAOt z3_$tVJR#2vEw4v#VT@&Nb_QlnW7R6~LwsxTj3L!Po^a{aS27_hq)9=c zQ64&pK`4CRqtA4hKC*|)U%r#O9(;_CedMF88mcif)1cN@W5f3C^bPb;ipm%R4?O$? z|MgwJ%{>RtaCr6@438kCAU94-jZn_9!WxuP_)5}=W8yeNb=#P@gQ(QF{m2YDOA*6s zc=zXTr)*=UQ-LW}9K>I6%^gL|7K22KSB~(TGqjHHXXA#=U=33z4l%lBHGRX&#Xo)N z%iMea!}t;&yZu`Xu3itd5kB#yuVano=;S*%&x zyytKK38@sd;bna1-bcy19Xdubx?(x+`{Y;o@sEB?+Xj5^-p7!GLo75~yzebH@X|}q z=X<;M^0gm7!Yz*B#5QM%f;t>*sL}~5pP_=QWLE&4kjGHw} zFTm*7?KSC&^=7Ay=L<9zBMi=K#nC%Tz9O|wPv$Fy&T_PJ)B3>km^prgX!Ujymt9`i z)E0Z$51pV?O6RNIZK2zXWGmK^X_ubvDM5xsR_jEzMN_Bbxof23JSP&8P)SUlf`q=P z#9VV8VGM%<1I#vN9a|fESk7v}GG75AMa9jDeM#n2lR3wwicBiP@=1c5Yk4qfb4< zeY>9G4X?PCH0ffECW=ZRtP8;kD^5&oa))SH@VfITlaWcE)Qj+S>Iz{5c@n!vmG2{w z=%nMGZ{;eK$~2{q6w)=8rI0Ms9(3Y^29TA;)v?tAf0B@72t(P z%UXTT{G(t*=5g$}a-MRI2uc-BHU*ctDCYAdJvVwQJk)iX0v0cH4-B29j&t7=9Trx9 zh;tMmn`=y-;{^d$DSVxhdOj*{!OR4*)(`a|=S%EYkTOL|2z(!5Ex9QihPoX$eXs_T z=ggiS<106P6RLHGj?6c(i}Qs;K*4(#&}}&z%4)sO)+56b_zLL-h#=r_oWl4S-gL!AUU=oj{L@!%<)W<{xb}i=EMGCg4{!eg*Ij)v zN5;Q!rqycGZO+qQukp_Je-zIPm~J%q;e8J?KQqnA6DP>)BYfh{$IyO_yPi1(UclYQ z_kpL7r4WO}lbWq-SMoRi`c)p>Hx4r4@UatIebMx=jkM7<_D>o<^kwzYO?>S66 z&6w?G_(4b~*9?_Pv=$OD77s|2Pv9#|Ax8C7327nCb27(LbH#y>5Qfe&SPDvhu#}C0 zb;btTg3yjv>j5^009mU6iQ)jF+( zdHRQjNjfc(xJ%@_K)FmCk~F6;3hBfxgn(tk%V^BcQS0v~Z3|kh7GdC%3V}ou7K4{^ zrA(`}2(pi5%a$?In8j*MB`h&N*C31{!g7tY(`L%E6utvXXS8Y`|34;F=(Az?N>yz8*_T0#gT;! zBNVlIi5&2xpe$Vz(i=!7v5{wvPdr!G{*3Fn3-y0^MIt%@d=~huwKll#;kz$bm~T8! zN%6c+r+azpjj!H3IW-;3H@nuC%54;D2m%jJ35>BKOLH(8B_9U+Yn*r9b`GDM;Lrd1 zBP=XVv17wJ0zY7CZjq@*lcb#z)M`$cl@~!lJ#kHMGGFlatua3pk|aG3le>goAskHz zKm`HP^O2r%t^#RRQ2hi(=jXWBOT0;zPzR^?6@{oxkVO?XtQckI%U{knKmP?{JxShL zgd}lLpC3ALZI*H2HCN%OE_>(3$>-1V?mzrJ4j((ocaI;SR2!g5LYC(Eg-@`^4W8#= zs{vtoh-zWqR;vxNX4MMY?j|COJJvKCV)aNLC7ZHxpv>ywI--DbZ5E@^4EF^rE;d;- zF~axhuY?%gU^21=`-E4ckh3Ap67S{wq2+!f%Y1Hv54h(=rl!ZO|xEO5J!k4 z!ZMoBE~2uG*IaQ9B^&0~d&FVL3$D0=-CH;Ddw=^0Zn^wMo_O>j#wMm%>krvEHO6CS zme@GGfo~i>4b=vgWm6t@2u?lD=1tRRAvty8BwP3HqhDwet(_rB6~%Ie>CKzC_WZ3} zx_>XuFXXkU&4tKC)soEes*oym_MvUPW7~VtEezQR>!d&i(k3@CZ1kcBux{} z+qso0H!;SjnlETvJ~_vRP#NdKQlN*jdbAXJ9E zIuFSZRjH#&H4xzVJ}T|Ab<;FEx6SaDU-@N@KJ^sGPn_n`9hZnWP1(4q!JA(B0%Bv3 zIs=(c$&72~nr6?&>34YZ9WUhU$~u#!0&l(J7D~QLstkYdfn|2@*uph0yOs7wzr+(+ zkw7^4zq44*AKb1pnv&)BYNiGAD{H*?n#&M{W2`JK^WT2u6@2F3{+)$D@x#MMdDk0% ziBh>hy*a_`;tH2scp>vEZQ?ZJoFSw3G8Ghs4^Stn;>-eWXeJ8Jc`ycV} z@_@`OARM3XA7A79N9LeVqHbk`{T^!zbHte<3?qtT>)2L4IZd++7mZb}GCcYSW^oqw zU-h%epD@H}gboJuJ2t~XpUx=0QA&wX=_nFe5D$8!X^iN#v15fTAhAFPL#(wqbkQXl zbW#02X}?1>>=8R2naW6mfXMeSaY{IUlFW9|Dn&Ui$*0GINgUG6 z62dHJ~*Qv8W;>| zoYEQ$(HL5-b^KD9g6k3nAqprsE|$n)ma9u=>GgVeu1nhMa^Sx2bLF1xeD(fESzhb% zPhYy54V$;JWoCvuzxyM0Y~Cd9`r)I5g8&?Z9u8sQ>3rBRxoxx&H(0Gg;p71nxKuuMqrie3_5LuQOI%wQ?6ptD34-JRbFh%JWb1XJrDxvm+`7KoI(+$ zvS;bVqjf!wv=ByNJ3hj3P?m-3xOl?B8hP}T&bLm!lf&Ds(PA}NUt>at)Ejl?d+Vfb z5$Tt6P#PwO6xz=a>_^OzXNbT_gq4PzQ-X`PmCaRqH!;(!V3Fb%il$Po2&I+qT!((B zIJ?&4%=&;sPt9`Z_yV0M!k2lX-!reN(gX_9SzKOq|NpGv{!c!?XaN2bj}RgO9v%IB z*cc-ZJ^9GhfAS}Pb?=WJKI#^04W!Aiguz0f(+Fu4=btk}!LiAr1e=5-2M%%G#TW8R zw_U^G$BuE)CFj%c4@t9(O0mGBM^5ng$z{UG;5gPucW0iZqUMEvhUMf`S)G|@76s_h zgZ3HNm=FTX&vEf8iP6e>)}%-AaJNuD{P&pLKfkZ8Q<3QRu_%7ebJgbiK`>BL=(m_exaC? zl5IhIX@Mw;Dfm7r37I>3nji?s`T@h$HMU)FE+2gVyZDE{`v;yn+QnLXk_(=*!(4Fj z^;~t;4MGT+N4z=?!h$oia~yf%2%Bd%kQken{nmR>X+*ZZgcXO(oU@nXhYu3(-+{CW zoH}`mZ**5lQf-bNeNtqZ=DXi}h%nAL9eaqyE;kDB!!Eyj%Vk`6-nsnMr@zVzZ@iRV z5Rq!bfkTIR$J<^*7RUVMH}2!9xgIkWk2k;gdNh(xeEoY=T${aHH*m{Um-5B0f16j| za4CV2oIH7&KX~VxxbyCN>4*Z~ICu(d2TMYrqgcG93MkE1wQnTpTyg=hZ}CXX+$&5Ny8|G z7QPe&y)Hlg)4xU9F2(v7TW6+l3O+rjK&jAR zX!ZH)fBh2w?X@qa;z{Oa=h!^fee3{{l!W%R}q7jZi zl6mBc2dOolx*V+y+6ZjNCUgAJHK3n0S|S8-IDq&fEX$%=^a;ZVtu?MtXpsXC)ks2O zk05iyD8@qLdAY89h>hiX6g-bCONoX9FZM~fjj?xs{^Qn{yNDQ4;8=m_^9Sxg!ZNv8IYNgLx9@VuO+t3@7oAhkj; zk<-hyA`Sw=_WDS|<6%24j^pNWulA^^9~rdMI6y(< zH@KVJ2WLdi@Ud+Nq4UUEA#E(9&}kmVV8sb0C&S?j8)dS5lcjUtlQb|G2HdcFD{p(n zZA^~USZww9i%)!oC%QvSv6@GZ*e()-))~ff@`0gB5J8{KPQuOmCd?JPC(VYjG8?AG zWv3sI#D*{m(ONUJVTw4481~kvdy?@jMRVzni&*YmDE{IjpQ781C^RO?M*(@;;Rprp zFY5pQ==nth@N+yu2>q>ZeRY1Z8`)8@NuX@Bw$MpTT@N^C^Eg*szMn1A4bGmKr`H`I zWDfH<_~4`1w!<}-okti9iF#e)Xu#&iHZHkv4_mfu;@I(7j-EP;w7pT1=cq7}GFSOz z*~mYTPXlsqWd6XBR&EqiY2GNPB*h*O@*64L%)buNmI*;{al%Qj|Xvafa zHc~63E$DT-^w$=Ri9@k_>$JJ?IeRFS>Y`LCqq5jEn-ij3D)aDxgJyZHMSp#Xu(QfT z5BB)xJ@>KF4)9zTFi4?stqM-TC+u~QmP87RqHCejgrwi$$)g>TG!t5Bv{v}8O%z7> z#a!pEO%5vw`dy+RAPEALkZ5i4Sk}?!HXKH5oF3zicig~zKYD}@{MiSvlRmdyw@bb5 z^{-`leJI^ZS@@oh=M(^q)+ya?hjOvNwb$K06hF`2;S1k6GC(y!TVywYr(c?8Qd>(h-_hY&%%iOSk7Z>f` z%r_r8!lMsA%H7}j9>4keJJ>SWnjM?2L1ziuH%_y@-r};o zJ9+x-Dog9@q-o4=z5b=V_Y-$L3(={X3@eMUi$z*%t2osv{?tZh7nex;JqjwMR4m{Z zeEKWP-1)U{^Z75`B~+FngyGX){5I988SKezSaF=MZ@nUYQ14q*>RCG6X} zfs6O;rtaJ9+O&lq9y>ulHEi9uf!f4a-egr91a1NGjMj7%1Dea->^$lZgO(P$I-cKu zjysCN)p=3pI?T_`(JMIo)d&BPR=3O2@*0mEI)PVjGQ^{E^dz_6dNT#rc_!g*l;bXN z9hX|A%%|_Xo8S4>SFvx)1{UV#0BE(^oV#s?i!MBur;eY(wXOWGkG60^{!EG|$Wxa@ zp$x9i!IgP#|HHo}w0*MF@ajML2W-z{XcZZD6tDdAeJ)iIW7mdDtjamLh@{LI?_e zfr6Je0)^%ngMJTbVB5xNbQWO=fs+i$v_MG*L0$|;@qkjTj-45dZL?+T7VIpcRxRPW zE+QV1XoD>UN*fZLOT!wCW41d&uNzd`X&5^^MAX zWw!X4f!z{$)UzRHu%ua*heHT~ZRJ}4+qRH8H^ms=mt1#UJ}XK>jz8T&8ikS?->-m5(XPQHnkWiUsRAQtl&geMM86ZE(v-_C*u~b3 zlic&egQU{Ib>+yElZ$lJ=wbY9rOt?K?7E~$j8Qo(N@rP~h7smdDV645k}Aud&F~h& zpr6gk6r)_;9Au+}zzhc{Ig&So0hJwF*|KXl!gA>Mx+0AuqfO5|dF*MCq#4tbHIpd8 z>e&S`d*TGzD9WV*%1E|v*+?&(Bg;~fFdz;CRJM>$k%vQ?)6*a^xGZ6B+Uzo(ff&&p;+`umBF_KJ2n)!b0EKjKH!j%9RSo=a*SpT4LAcjbJ-S$Hf=9p-^QBwgrLhu$)Sw)kVzg69f~RNK?)4 zzWp~DFZ~{In(^SFBP3Z$tz1N<8L3+$(=b&pli5B|oI<6Hsy6e7g|rYTu6^#+%&oS$ zZ?;Wf7x?qf-No5qU3awH8iBGb@&eShbCbB0 zr^*ZmU2eGTRy^nT**-nV;`|&>ojlFH%PQ2W4LWf`qtU=G6u5ZbZa)9O69^|SIP%V! zTo#w5{MsvDj_0{_Q#igF@b8C@aQOHc3ckx5Uiord*JWX~lk38DJ_R&tq!E55k6bI{ zQ;+5`cw6?+?X=*`DR3-80kk?Gp;w!NauZ7!k}v>aAQ#V$#Jl4iIH|L6U$WY zr<0mseT9+*{UBoClrfD>tgWs=lu#RM5DACB|F<8Zq9Jej>~FcK91E{q<8i-JNE8nn3=|&BNWsJ^< zQYEkq2cGn8Ww!tTAOJ~3K~y}+00&bjf>)%H1*|;zI5W)}Tc(@TYGsO+A&4{9TP=E> z4lC;&WTA>%tP*zCXs;|WRNg{O6W2{5^TpMNi&ugSFpSS{a}DC@-1`{1k7yRitpN(EJZ7Y zhg&|yBq+aw8j*Cu{(RbL0ek(0-iX=u5X^kr-Ss0MT zA*F(gE%P+LX2mB80^WV#5tLs;+s@CRepyNqhq$(+V9Pu$r8%L7T3-AyyEKJj5n%8 zNi1B~$5_S$QQrhY5=H|Y3q04NGl;}Qqe6XbTu3R&!VaZ!4NF?=-L;YT{m=iKzyAAA z@x6m5D2;Ex9;LnwlK-UQ?f-!Diw5B5d^T>I^a{>sQj}y&xhcQ;@>@-{pvBqKi^Oq) zZReCpFAa$zjcvKuR!piQgze(F9;I02(}+anIQlFh>-X5bc>;O;C4A@p1Ei_IwsU~f zGur-Qxs2m_7^9I=BCK3aVT>6WYM+7l7?3##D+6qkPirheo|r(sJy2TVxeldDg*3}Z zoScLl=cGj6vk8Nc zB+c^7amPj2POeW*QZ(S&xdE!+=JKY@h*4x9EUmOS^7t`sf5FAs<_!(2H%KYh$2oT7 z5a0XYUz^LXem-%UFy0&&SUy1%v1`{JY}@9p_MvhOwf9uOc!d*uHBgCr_TD(i~^&?mZkmvw$zbWFr8a5Ga*TjodVPhl))`)W-FX~-;z_!lHWQQMxKa?si_EPp zQ{AwcOU~O3+7Jf~R$6Ur*UR6hfJ(K3Cj>=X62&R4iciV0Fw&+}tx~C!(GpzOr`755 z&JTVZl8{|hm*a;I(CrPFbPMd|NQQ$Irl+P&zugc^?E$svCR%5VRg2Ubbq2jQCQC^rAZ;uOuIn*Y@(5Eyxm;o% z1KN;=0sVFd9Y-Bs8(@YKTo`iL!vmq_1)ZHD;&le6#z1v95O2<_F9Kde@L-8&dS^@LAOJ_;7~11 zW4j)%Bk_G7OBmuP;p{MDZ4i-_ONcCEX>AQVi*SmXv9W2YQ+1?K2*)RkW7Y>T{Wv2m zcu2oUcm534poL#ul(G*>eU^ry)_#AZy>cu9_u_j|< zW1M;V7x{Aqo1Z;tevq)(~Bqfn_jfy&~EtSott-FM4DIBkauuBASMz?pC zOg3NVrY)RB@v2F7- zFTC+GzVY1$!K>gE3k*9Q&b{zLrnhcqVPPrP;rc$d?~_C^8bhU&%VWYY#IbE$-=o`V zlPFE2IgW?I5h?Yl8SFxtR=dm2Ez=}v#(Jku&4vpv+|Qw7CrE^a5*8|sxOCT6PMx0T zTVKD6TBE_PbM~@h*FKIOJt7=w*fcY4ykdpkaE%~Z&n6nRKqy_T6@}~;T;gzu&QdfM zzMoIabe0jPDX#0Vw6wx-7!nQ!Y~Q+p^DjS_!62eo@^Nj8_R1;~dp0sYJwvHn;<2Nr z`TUo^NpX|_R2=1r=j3LM=Q=rbDpmPZQ7Ih9Cr!0wNhRWFh~sV$N1ixtmKN9L-06d+ zRG%@uVI+hIDEKaCW=}FPKE)siSzcN+^|5)8rYYrW9mjR)t}oG?-o#+g!ER2Hm78=# zK-llm>@4zsz4S(U{XSp2>)W)RJV5Kn1H_p^I38QJZsF~3{Ud^5zzeUwn7unUb7rk& zF4(hO{Lyc|j%L~A-EVt6*F5+bMhK!LL8uJRad^o!myl?9{M0Njz4kI*bNkKw@!$Om zGd{fYrPos}6`3kXdV>Ksz3Lh^O-=E{;yVB9pAS(k6>*D2LZ!%3g(;NKCywyTmu%w? zf9uyd@YoUNT77H@7wp+d&9!;WTYej(GH!p-3+N1E@QYk}{<&Osd66)T5Guo9;fx{( zg?NS>na9TYjzuyYu(C3N<5+b2L+=0neZ1y5=kVs2ypr)|llg^tJkMitdWQRc@(_1E z^aNl0-ovo{JWR2YYb%VwBnkFYkMQYtzm033^Blha!yjNU?A^6f%xu`mqX!P~+FyMu z7hk`~WmjB5oMaSyk1d-wbNeNGnR@Cp)p|YG^@<$KcmC#SCTj(>u<&e)VHoFeiYQ9n zZT#echxyR|{t$ol{`c{M>z|7pfvRjY$4@-TeFvZ9JBQEk)A?1h&3n+6i#hTzuYTbb zeCUtgMW#~*K|sN?@f;7ZdEn3i{_rpUmP_h;asb|@Nj!fmrGjT1*AeqeYy9-550Ygm z&FM+D?bu4`!tGQ_1>z*ZcO5L51Bgn#!(un$!5{p9|NiDz@f)vsC18lNh*M`yG3>Xw z^rCCH|B*+z`FGw&I<*s9D^4%0^2x8>#Wfe6ORKfU-0T_Fjvb^bGi(Iyv$OPUiztjo z@<9c9G<1*-?X^YXRM9AU)Ejly=1#LZH!D<@=EXDl#z{Q(gs>bJOV|w0o<>*>byqN4 znxmUUqjZsML<-F#Kc!{iHzsH;&Z2?=Q_U(R*JAF}sga~nVT=|6gDoZfVMw_$hB6WT zRM7A>1B^gPYf{-|#M`8=QOUt-Ap;9T+T3)75EKw}@ z1aZV*Fc>jiG+Ijh#sIHWqogBnU^p0J(uA>HTiCK;lI7(Ul4QuB-(eUg2rPz{iwQ$Y zPToWW{UJl4s8v}}N5S6B6+TiwDI8->>?~)`5 zQ52CxF}C9%EE{3jWZgAfoiJJPvEn|P zU7WDX`TNdiarO*@G$Tb|jKI${o&E}6`_dP9)5~t+mg}x%z1_yx9`F3nC;8sVHH`G~ zBq^Q4{#2H5MLFZP3%8kxT7g7K<2WwL2+%Q$OC3`wmnitI07ZSgiRBbT64n7Ba&hx$er#xS?9(^Y{J~s^d9aB?yR(#n!1N)s5ST&YtAl^Y*i0YMKWge28Hf z5huzt#vCzz&R*v2%vxGkzR|WNM26@4d9J%-luL9W2Ws)rKq_^84?2 zE3bR~t65uHr(7;^;KBR&_q*>hSKn|WJNI5Frlw}N=X*cq&b#i#FBGYi9MUXfy)&R* z$z>}2Ru9*8C=`pigh^{$+ciolWeiS|YE+h)X0xOk;}dduu`f0jjaXk_rPEnw5X96Q z6BNpIHf<8jojHZ)xd_W9><$>3jER}t%$lYtu3NyB662If7Y^{JZ@Ysxz2OZ2T(N(v zL8apIOD?5RpW;V9y`T5}^+&k#-@b{CBYel==ws^)`+ecL4yn?7_}~GgF}SYJFi7xR zi53>!OtE5euuPU^XqBOqqO^XJ7rx|qyzQ;O{_J&nYVJvN8nbi91q{PJpZ&sD8TNZr z>SOs-UF$qCB@21`n_tKNJ$pF!oUOFmYq*|ErPKs0KJeam@vis0pKlDiXlWyDn;;V; zMnDpdBsICw&KBf)R;`hCZdjMnA_zlT3$ys85|)%~XjHlNf{k2o!NmZ~Y}~+^xfAqz zOT6l(x3hcy`F!sF!&tp_EHqiMmj90SDtkAK@v_@r2*CB%K8NA3N3~pItTE2>pZ9$J zpLf2E_kZwXoIZ98%XTnmT)#+|DuNUeV}VNX$nd4%$5P_B7M|ne`dVcThP@t^ zZFBXd`?%tqDfVpJGWv8Ao;dO_C13IGxBoh&f4!3*fA~)9#(2&u&>1hf{y6}2+sgz& zkB-V{G$tq(E9}`k#)h)w&))NHHf)&2aU2q5a6MN5q}cS=*G6W-9I=rkDfWm|>v?V- zxhn+aQUU3DoZG1I^5qrc}hTY~m=+3mp`h(h$cv zH$!DPgfUG?;+W~FainxX+9+*MN?}xnrBae$fRF;)tB(FW#c_(%DmBtLCXACj^+s!y z*7Vlb&{|O}7V=a!qfl8!ty-pB7|RC?D=iY4;W`dUcOBJU#q&IDzeG3;h@zNow@;&9 zr`a6i%-mTNBd}wd5Uj6ZTp!nUu*k@Qki<&af5{#;-E^h-)MvjgmRotFVN^)GdKQ(Y zc-Dv(n<)l^fZ9Y2>AU!a0`q5A^6YvoNCth-3Rh^fC2@--2E8t0%?8az1xAp`APm7M zEGbFCAxWI%`g{pSDdH&iPgRN@sVcFuvW8MB*Pmx8y`_1gH0PkWr2;`GWvtnxP_KY0 zva-BFmMMfZNIf81=;F8@wzNQJWTT;1wdhkQRB5$)thKrrottvaU=>S4O-Ph-$c8b> zve+;^!C1A#U^rxPX`LvF@|fx*X4qZDk`|t00~Wy`pi=T^)=G$KfljAK7)2U_UD;1fB#95 zM1l0Y$}czo|H1Q%2H@v>%6{3hjA8%o&D{R{YdAAEhf^FgSd!&dOITSiPtYtE@ohu9 zA09q)w);q!Btd2n^=fhJShaNF#;x^DN*jV{{b` zKGGhNB-&)k2#i6v9>ZRr%dfeLm*4R+{_=ev;OyKy_GlgKxfWSw&{`7&L;AfQn2a=2 zroFl-nvF`XJslbPdcz3EvH7)Me^)~2PdxrpPS4GV0Lza zJ3se1hEYs=Z4KWRx&J}rg^^RLlBOBMUW+J7Fw&t?DPgG;V>HD|18upqJ6%?n7J0|- zyoGLioiBa{ei?}(PBpIOBS*4;a}@nWjg3YIO+SglTwDc09p zLS-tq+L<)Z2^Ruwd--_KvM^c3c&)_dO&j_A7w*KQ5w%K*3(nia^3np|zxQjjyKOwr zW!v`coISh7onQJK4?OY|SPt&6jgk&=lJdic9>f4arqvtJs8`vxd73oUNC{bz7~9*ARvBp+BBh1nc|u5uWlL&BA8lZ9d6mOQPLQdL zUTclde&$o$a?1@o_|pe?{P5%4@`4v|_0>1>*-w9rPu}yWh=w+}HS}P>O_y%t*Is-x zvnNk*@c2B)O%w~cu`*K{r8Ggm&&2c;GD!%MEKd-U5-oC5q%)cx8NsR_!=khF_OClZHLwGJKiBVblEX7pX zHlF8TYX^k{nMWP_Qc$#YK6wrU1~!Xz~=c;b1^eEwE|h z6j7KrLA^nUCa18+aYEH{kWylsltf5|gMi7g+Ov?#WHBbmGL+I_ITWk8)JSI;X_}!8 zluIRC&qJj7b}oq0QG9hqu~ekU2n8Z@0M}p`;`uJ6g3rvx4XmuLp^ZeV4C8di?Vu7$7DwQ(QvWeoDD9+8fLP%`S&*fTLgAk-iLTkOvSfxn4mTw#97nTu15JX9y z8l-b?os>3NmJ)=9EKQl3Y$Bz_^2!>Sig8^VC2Z0-fg~IOJ`F*yOH}l!SL-xf52X!j zL5OYTeuHAA#wNe;>~$_=E_p4D)u|LqxQ{g6BGjD9QsUgvFqIbOMh{WPkrUz_~wI;Gqq_m1ItAya{rRaqeBZ(m)mwV%)ZTI zXtaoegkd-|w&M^*D`pTRqEsv}4C3z?oqR&4>Y)=)&d zs~N2o*Ij)Hwr!z|O*CkUxs&Vkh7o&qZ)Re=$^87;!-Ht>&Odw4hwu6SzQ(!N|8n_7 zS8sXIhUu|C-hcl2yN?}xl5(|dYV`(jtc2Dnu5FpIu_m3&6JLDrIL2tUY~I44*Jo_J z$u;}WVb_KU&Mqt<4E)o-ewH`9@}(q6!oPg>E4=n)FJkxJz5MvlF?w;zN(z@>aT#Cy z`rTY`?mlKNx{{SBrdcafs5H>E4OoQ&yEboNqER6f2G2lWNW4NR2mIMSo@3|6#6p2< zuf38|sbpNw7u`;mFMs7OjvRT4z1z32aCRuBCZ}=N=g?Uqgo?TOmK)8B@3=#Bx;-W) zr`Wr9AE!^8h zdIg{P#HU$ZUg0-?`)$H0lzIPq--i$azhE&j-NY_VxWmk4YU2$3ek7iri|sqvUaJoBO!!@ki;gC5RI`hSjIMO({3+qy2Ih|*wfLTF}7*U4mO(%M#d}>2+)G0 z(ymgKN~PK>Ys-DPx!nESd-iYsIBBAz#}SQ*i6CM|-`|-hmvisA@ArPc_j&mI7r!9q zr>2CSE^bI1C9zOY;t-k2@s0bxC9=_Nyzl+LEzX=f$)n%@F1vSZW7pn&l;ERD zw_TyxbSM;i5TSz?B=|-Igno$7RI=GTiV_h=$p)_Dx)_Fu ze)K!o1fJJswNgWdQ6fn+H2feUow6vE zy2+*tydYv}sZ1;(@B`Xz1#N?bl(KDfO(BXJl(q~fBpQ)mPhHm~2xHc(W#m#BfK1v( z$e486CJaNC78YqWn-mK91j}d&re_zDO^pQ8(8y*|M5qK|M8Qf>oKi-#ofe)S&~9|_ zgW#u#$aF4^s;GEgKq_S=PL??FC^(LTL?H?TY5+k&zP|Mq5em7CMH~i6G*Q<-a&jnHw4gN?{Y zL~=jk2wh8xXRqC&V`{{Hf`pC2kRVnFy(F3z$%J)J93x}|!e_a>g4apj&!(Z%aXJVo ziDO9^b`YwHrX}-jp|9YyT1?H%lh0+aEECHzXgV&YogxeZ1mdUEFF}m&x|COIXj(G+ zQR*%*H@~=n>kc56D4LF8TN@VOm`2M%#v#3>BDSd~9txQZ{D;1erkj{{I&lJM3ZCn+ zwq8fb4Bf>XxlEe1T5|fNn?^z}iXuR4{M`!mMw4PbO@Chxsv>Y*k1%Fqvu@xyO-i{Q zDzVDU+!}$APG&b^AE{~xVtUkwox=sXGg5@Y!V(&dR#h}RQsz@a*y(%_1i^3L^R8d{ z^8Z}d9653%ICA93954s`^OwK+>5r6p`#)o6Ogi-yg21AX6*#RJ*K_G9rs>UDoIZIh z{r`5I_W#xO+6Lekyn2eZ*gn$3_?BTbRS-rASG&7A$N0o{_Fr)&ljknHc;<|E`&Yj5 zx6Oa;8mFKBcI))h{L=?N_|8ZA`ul%yVtLnDr3q3Z@WUYX@b7b+~Y z0){vBGrzb#9U_HFWe-}xTj_{x34t=HHz zG|265e;al>g$zTyNHANG;`?9xv6x+0p;YQZ)ih?^OI&{09tJjVqgWb{y*)jm`_OwKGzArvl^8{*72ze_8GYQ2GoeI|D7;KgHSIq>)as^@3XM|L2s3~IZ|si_5S z-9OIQ*aR;;^&@nAZhPB1IXAmPCYQl!)#A87?jQP~3Kg}C%x>25b^@s>PhppR2nY}p9vrj%rt65`x^%9QL z;mqlCB34x}EK~(hbt0ia6r!psQ&aN^j!$(l6c06y*t}(gk>P&!?ik^Z|K!hET3*6) zU23%k6I(VRVu=??P((uKQ4~zwKnR)O_Cyl4Xt@E)JZ_flrUOLFa z;w*!kN1+{Ks5%g0mi((g0Wq=yTgi4l32z;T_V_Aej2RoHcq7|7ef!`vXPBVFN zhJ!C1aG?*T4%Rs?9cD%S|^>&arWXo&%bblzWzR3Rps#~4-$tSRysr4wy;f&X4@6EWs@)D z@H%bU^$ML3+HSN=#jqwOXC2saX-B(sDX<6?4>U4cv~8VVDRJ(`>c5{nj@y zx^;^@b^08&dP9^~s(7A{DnPR|8Vv{AvS_;jity1ijo009tz2Iz3!;FdCngCaNf3sV zx(h5Wtl$R`nRJS{)j_aAI-4bmB2-o2x-N#DB8Xzr=`>!)qtS3MEEC5`Vm#SwhGITT zCT-E_c${0EBaD*Qd@h?}X?>AwK8vO)w3-g>w$H@&ei{u2P1mW{o4B5b6bji)ij|dh zTFn+I+urE%*12rY1iSX^vcTOr@OmA;Q5qS z*XiyqB80#XTU074TShk{k$9fZ;?x3B6p_p2&~=SwvxTPGc)rB_?}NJA(gUOSuSH|vgER9 zOkG8YI{WtSWO%5L^=gA>pF5oV3@NcKop#&9^L%vEOiqw}k2s7Nz3wW~%{tAdLv_7I zqtOHVp)mThz4;@k#KTOt%et=1%;&wx-d42@38!m>>!#>X&qont4?;(9(o7-JYZPCJQI z+P00NYUrv!5RuLm5_GZKrc!I52o<5K8@N^X?X+aLLjd;jDA zqxk>V)`#x>-OqmU@Bdb8pV;mThmyvuyNKS`H5ni4lrR0%EpI~Nch6^i_uI?^~LzjfCuJnJhRdPcUeQdM~AfoCaXGo&+V(eZpREn>~U)N~A05wX{1 z?(09m4<&tDcW~Lhyl6C^ z`Dn3^ok}4z8?eabyU678Sg9=OY@S0$PH^D)rQM0BI}xX+*V(yajL;3}v|G4t zl6MY*4w@oK*(N9|{r&x%n>~xF*#r?}az)OapT_e;R3lBhRj1Td#3^1#_304%L{Ut(SfpNu?otn=_yOgBUHjQS7<>giKxeSJ7VVVl5lufN(XT93QPDSWTWjxm-j$_KJ6-qrlluCW{ z_Ybf%UnWLleQg!r^GK%*8igXN?;sj$XsI-rj6uhXs8rkZZQ2aFj&4~Prq1H>D#wnU zW?)l4<&{-T!$=4rZI4XeKv7kyjSjx=QLi;nRe_-@pj%{8CW;Zl@(P-!q3Rm07tm-r zc%=fuNE5c|cv4|%dY&@) zhlD}M@nff0U0D^)MjgXSVd#k;H4!MOXln93eh?vq#<_D-h$sYsNT*Zu5A-uNvyfO! zwPdJNMiGi4uuX$jtIZF7_!wKaZ56Al>y%2}tglswv?OL^8hR2h@&j~TM^OZa4us!CsP57Qez!!WIcdZQ&>R$bN5&16tHm$n(`FHtNudG5tm2s|IXP((&Cjw1CQa7rq5=1dkB+)dTw$tI@!6Srm%<$j=!;=S|=WTb~jGeL> z-!e=#o8|P`ON229T|-p_*^GtL36N1lqgE#jLv~DzQ|jqPH7w4byGX0mq_3}psdXho z*nnYZl-KGw&M9{6-A!L6iIDWp#}pOkRglN~*Oc=Ppb$IyTDS z&>)s&vADRx%^#%$ZXiHDy%#Mj#`PR}f08wQU&eUJwpei9jlqzr>k{QW=RI30Ek z6lqn~m~vWNHP%bYQ25HXzQW31L37FTM?ppwwo zv1cc_LV=~(8GiV{gS_R=xADQ>`VfPIgPfb3 zc3s+DKxT9Yg@OJAY3asUnN@{Z-s}(~a`kZ#^eu6yW80 zh|COxAu@_777G082j0ek$9~9&^A`FtMFa|xpu-7;BPT1B_hJp00{oV&Qp ziBsnYe4p~Czld!aM6uw;H(bv{=PN`)M|E37GUA3CZsPb8KjZ@+_)WTd`)EZ9pZN4w z>FVxcakY-nG^S=2nAoumMOB$wC?jMSX^3T`}k&3R+10D{<{7A z=tobW3KEZll32j=#Ug8~F+muyw786_DrD0(mtVe{M(btjtu|eS974u~VPa-AEE6GP z*4C?(SE~$d>cMdwcJA29iwBRQC;~+RRVMKckf@rD=S95w>M0COp_tEd`TjjPZI}6l zGPY$VK9>z~qoM$&$?U=^M~|Oj@9ypF-nE@#sfX`=`}?@8wEBA5b)%zJ(TxM!|fljAGB$N20t|dtCM$6%uClAoo)y2rj z5L?HF*|KGbnVAI^7FY1vE@{h7P_n9m*Xgjf(q?XciILF}_UzoswbxwE!qN(J3uPuR zEfQsC(MEO?#R68?<0eUJ+XSH$v&r>ta&oBN(v6#KJ z)H8st>NFcpB3g?*R872A)czaRYyYcX@M>09qcHGLH+HZ+U3q#-T|&`JE=?~4ufB5h zXF4AHA6Kc^^X;bN{+TLJ<2Vpu7_wSk#C0-qM>;1;X`M(yr`6&QKX^BH-}-vOFu<}* zy7D=mIC6$x|BwHLfB4k@$s4b}jI-18WNZUd(`b4DQQ*^)NrX|3>yx%^q>KrJfI>Ef zP&C@N-hgeH+_YyadE4TeiBWZ){ku$|c^oJxX8pmj=LZpffZF+<%G*DDDGf~p3LL-n0tCc2_ zBx(}I5(tQK3H$)p^)T%eQ`7S-EiQ8?2(eQ(eZ4)*IZc8vq2>rxrM)~ytGq-x@Y#9o zb&U3Oaq5-BIAh{mr)!2N56tt53+L8;aqrTlvF3`I|&`X4|Z;u9NXX zW@qNuzi&HX7$6mcl$}B)!nRFx(_nPV7(p0w`0!CySJ%lG^Tbii^5PP)Q0cfX*IYeJ zBm{HIWuAZOn6xdO{NNU`*os+MuXFe25w>mHM%=6=_X?0vfGQ-Bm8By!Zn^C?4!`(< zIDPaO#jY;2T#3207A@}rn}&zTp1#1DQCKyGv=ok+0KZsTS* z$!u4j(88F=vWUzqLXb#$ObgVQ!HFvvoS7qZJ1DtjTE67WQj>J9z+3LPnFk+ynCa+k&C%tgo*V1|gC}GWRbl$(0AxY95p4rci{!j-BHO8DSI#q+=As z;I92h0bvwUv$EWN^NmzOgYQ58aiX1<1A_SMF^e)mP7;s0uO)={?xvdP;N^3o_r+FG@XKthHlmUW~93*Fdal2vzy1 z04N4RnQT54MG!_25<$J`(D8h>j*p@#Q0nQDGqcMg3Ih}^>4acer`AY+6KH}d}> zk(8K*LEyVI8cq89OEek|<68!)tyhRQ%-p7KY-Fi@I)R5_Su8KFP|RnsY>Rw0#dX*0 zX1mE!z`8Dtc3`Q^LWI<}ej{L)>VKYJe6OP+;7BskR|2(eQZuIqF9 z^m+E}-GPilZoBn*E?$`7;470!k?sfRs)8aUx~dYHIi{xPi6l&H-^!NFo7lT=FHaqK zmJ`R%uz6&VT&_U1S|f^M^7#xc$K}|or`f%8jGmruuDSYhf-vU!=MU3pw2%^XRS?D! z)7Fueoq}^`Q)m2Q`Q?bNOr7&%q)%6CCA2`U49b@d+zJ-0ew{!aRB+tKi z4998H-Id2MHC$I>rSmv$#OcW?$}4N^*|UQ??|d_X7sw|LydaJqJ4?rflx?C2Fl~!4 zl1xp_F*`lO&RyHN;rgq2$J=k0XD`g~;7b?8#YP3v*$wbSfT;>BMPQm1jiw`dyHXIf z$>lN-xkOSDw5CTPO~Ea*H?LM!D}0U zU-(*DU6Miw6g`vdx;0(cmYHPunziF!``Z2I|E<@2_q%`j;(=#=G#4vkGz>#Ix_MYs zYYl4kMuH?05}_(sw#D~;@*H1(=yAHb3RE4BST$IfpQo?CkH7r#xB1*ZKZ1|}tq^oo zWm7SQVHi|uP1YQr*z16qCeRJ)m3998oi{VTTH%pb&SJSuMoT%C8XZ~~NKL2R?(o+A z+ZfzDMBuwDPoL%2ZoP^tcJD-}0$tNtUoF#U)aAh7kl3|%F9MYd=T7tR6Hm&a;mu<6 zU>~3U?3amSncy6yB$hF{VPF|L&1MT-cR?sn+@L$L%c7&-40guVnYG9sKuCe1^||>J+(rj)JB#H(O?WVua6p{QuzZzw{3* zl;_B+Sw4F2+u62tE4RGy4rbnzm zzVZD>_`scaaQU_^5IjXBC1ksyQRm{^5^vadv$*2U_fxK{6KOU}OREfKRd(-O=Fs6+ zSzK6TbYzh2+s9~D)(8=lXJ=7$6FZ$j#vw~98#nRFW*IsiKcir_4 zR+ble^zoN4j91BKQfP+BHCOK8$B#ZuPcg$)SL~wGaZ!X|$Ifk7=`?3wp2X^?kj~*c z9==r3v^3`*Iw8W~2(b)_vfasWnv}>OKuKqrU0mngfA}$ShGcYfgz}n6t=WP&re}SP z9XXw$fgT($AdV!xr5>`G6#0CPm2w%|w(05VmWn{ERq8aFZG7LycRLIZ4Nz-HCU$H? zhRMKV%F-zHZQ@7I91&`10Abj)y@((TLAQAL_&l-iqYjKD;<7j<_S)7YTLw4`p#WmMl z&E&a@96oZK<)uYj*XN4;J4vTgEU#3^rY%N?2NHX?Og{Xl7gl(7auH86@zo_1MHPx+ z;k!PuB2WgmB6I~}Nf=9nW)lP}NrX++@q~sMOQJYNATbS{^-7Jog=NM@24vr0FZEho z2vsEv60(O-6tXE}qv%wKqKF`hSzIi0>n%5M^%eVh`q>wF{+WXb!=1!JE~O-!%c80Z z)oKOH)CoP8H^1>Z;wXSP8^ii-m<{Vl=9iDqBYfnHV3HaU6>a z=ckh4N&&G1(=zGmF5iK;Cd0JE(m;&S6(^E>uh5M@VvOU*Coyf%Hsp}L>*IPMnyTUXAxDp$;qrYG?Af)G z@hw|fT3)C8%4yTe0?rZ=G>z3t zlU&9|)8N$EOYDjxdV5QxQYo&wVlS1-vv__;+BWby0h*8mQA|FcrCzV|>ajCif8Bm^ zo-4L*9hT*#G3FLmlV*`3h-E^h(p80gE=zf}ij?OQs!+jW@8x@ly$8}b z*`TV_s&z7%6oKclvRr0mX_2!#K5GgcT zj?3XgM>&6finqPxX72sqd*uG3M|t4;j|->clFQiSG8R!76POxa5OV3#9CLF^TzmCp z;-)uT7k~JkQ67Bi74g#AGD>$p8BN6r0|;F5wu-JBvFA%+TZoR+kO(0J9)3*w=c$>V zewy$-_e6*NFdB2b#22G!M$&`|T$b0G#?N!z|39wRHUPii)k@qo2qJVN#mv+N*=jb# zWqWrKOOF0L*AzkoPd)R8Yr+>%;Pdvwc4?fCY{q7&oT`chazq$`6 zaQWCrKFA+`{b6Pzi%9heQK`2*mYN~I@unO2_jkRShn_vepMUomlzbm?)TCo%ktpaw zqJ%EL^6t0F8*jLIgH03Aa;jv~1p&$X*!3JQ3z)?54m8znmstG4Nj*~&+d_Kny9(;)JJ@63s-utWQ zZ@8Yn`S_>#r*D3XY$nmGD>7o|mM&7J;Mpf1kwwiDgJa$D%By!UGOtYzO2 zpFMDb&p+}4rm7{BpU9=*`fN+Xl|5a&@uuqtJRenq$+PF#vv;RFdh~>N!;LpGKCvAc zdH8Zt3Skfshd%Fo*W1`Ov7KtI`O`eJrW*-@P&a7= zF-vQ8sQDl)5GD{IbOCl6Wq1oxw~_)^)evET6dEE|pj=&}tiZX0$3fFkj18iSkPK&2 zyzX^Z$)}%sPV^2BB4tc2o1t2%vTNrA!z06TdS;%*`2{MqZ0R%T(~sHz@`D( zPK&f{F|mCMr%s$?blW&G-DYm314sc%2ri zl2A=TH%1bpWKDK$8{qW%ESef&^mRjD7rJ4vy1dM_*Iq%fyTm6x`9-EKO(7Kn)3Q-i zg#%B&OiynK*Nq56my~VM-&3SoZxV(PPAq7e1%zoQ2u?Faq^QJQHj1GkH4}*fA|{Bz z>>ENZ&k)wuNe%X6sEIL25lOyZY;3q|wK}RI#Q4@xdGh2L8AYLxGBH8Nfk(SzfJkB? zmZ8ycJr)yyi?1hGUY3LP&**8}Ef=lSpl-^E+*coXZN z_!0-6ehHO`cE?9m1t~LmU02rv0!=}LAr~gk^C$o1!>lYXac=S)iYk)dE0SoMO0dDZ zcYR4ZWwKmeC-8m#^rL^wV~;;3AAjO`ArTv$|0J@fDuPZJ;kXJywV0imW6zGQ{P7?B z9*tImpFH{$Ezcv9GAS0jX*60i8%<(GK~of3?WEv**PZVql}_=(3or80ORpl3jE)Qu zMKLE%Umy%)bVJ9oZI)No>9pJY&WG;djyv8=wc6y-$DgOGE6>2dCfXg3>8V+2^(K~W zW9TZ&yl6SMef=VQ8490SFEpc%EN*?>o45&lrPQ_|ao8(rk6G3=Ksj zvnpZWqp2!Z%BI8ebLzw?<&8I9&Aqo=LH~(Gelp*tV`dXsn@CP6EK?J%>xe@4C_!8oQRt%UI_Y%J z&n@hVrFuzKH4IInDKVYMK-CR0S({F$^;%u~Gp^VEQNQ5TZZ{NFk*Fd>3I(Ycv^tUO z_@Pks)cDVPUCU6Lnnv>QRRzOCgCdAG_{g@6OTw%UBy8WjiSl}d-J=6szi%5`h6lOt zyASc6x7-Xe=5yct9&fsKKc$`$-}uRM^p;ATTC6Z$O0%iEfUZImC9FAB#ssR4Oc!|h z^aY;n%}~e{Pz;M$CI(ERC=rfGiJ>bjmzO#C(&I=}R##V8T$th3+up(WmYr1A7P;>$ zpO%G;CMHJvD6dqxaQYTN+^$@2e3*_4Z@&FD`iA$hR;jU6o}sUI5E+M@ICX+3ickotRoCb$^5NNJKrC%`mK zUVizQxa+RB<2Y>|eBdGCD4^3x(1ydCdbs}jtK^|WN5#OVeson}7#2ztu)bDdWNQK4 zvgqj=CTg{bP>GB*p_ztsj@U3M8X6*~p;$IytA)^2gaU*hT2-{>I&#xigk=)@0VpbI z(?pwHM^TdkuvV*b*`6INuhp4fDC0-)<@@eO*OTsVd8JA|pU9C4g(46B;4!RJntHuX zKAR$)PLa#&G#hnHJH${`ynGL8Hjk77;+WX5A(JIGQbekrL}L^cwYCCwhDf&vi~WdV z4@41)lt`gK;6voo<5!Sghx0R&LMX|MiD?=v%r7#wb&FIqooAmtC_FzTolaq;(ntyI zc4q?%s8cSlQ0nf&?R2PC>sWS*>FEVh#Xi*7LDh8-8t4X5u@CGts@sOSiztdpY^IQQ z8kx!zr(arqzff{-%pBh zMJ0@3dM+7G&SY%zxeTr!;QKzY6vRk`5J^O#(34nDt7SydBDAuIC}bl>kBB2Yp`!E- zqL>zjh#~aIW;5u9PN&^LXbOg|ClL-5bi)$Gu5M`>8ciS!f@H&>fUYTcfh33|p6e1D zI_tG2K@gEnXA@+hj0j>tC`3|FE^l;sRfT4=g^U7Te)X(OXVStlbp#Oj;fBynFf+4& z?}uobiXTOIZ5KObVH&#FIkBB$)}~Ue6G?%FAn<&gRvXVxo-tmmU@DT83iKV7*riXsp~O)!u#wA(JNMg!9@ ziDF2nQ+Po_jM;qIZoc#2llVb|W@v=5M1~Ovk<2Ig5gj)qlS#9_TIR*)e?qfS6X{ff zG4=caL)Vh1j${LinmlKuqSIT-apCmK#F~kr38Gez;6bZZqBurXlekI{fo+?tRq8zO z;CJ|?e|I-MJ>5xsDU{64Ez)tljXb>Am_JZSr%c+dI-0JM&E@Fr=|)o|uIsX}uuKqy z$Zgvq> zOByDIt`k@`7tUQ^?;rjLuD<$8f=F`Y)k&&rt7w{Jr7k?5URm)d5vx3WBmHP@1^SpPsk(x_?(yuBNPOY zl0yU8dB9%p=ug&$9>HN z{4=iCHUPiiRm>IIGhRR(tLUnNW~9+YK&u@f<9P2!Kl;(^U;p)A|1SwZ|MPOZus^UDb`vpisgcu;1w6kD`-+e7((cys7iu!^n7}|itN}v&b|Nr>%?a9ry?7%k;g>S zQ8othrf25m@e{|W)>`7$TW&+j@_m9ZpsA?Ik+<(70pIfp0w07Rowl)48G;}{RTbXoC+M>C(EHnmkQxr^pqGEHAGjH1q#v@4bU9yXrgN&k8%7 zee%t>vs$fI7Dy-%1c)H)AsGieU%p2A}snFsb`>~R3>0W5+EMxcOD zMp&f07LzQ5l$@bx?Hb=+cv zOHdqhox6iXl$`;S(^D)huX4#H`&nJzq8E5Xet;H^&OwnQ${eW-Mhi@}4p^)gP>2$l zX9yEur2r)nLSmCXGK;aEN2wHLwGDDWq#!+e1aH(siYl#klb65z2DWdX<1hc})1+BR zzdu4sNf@cIeXDbH$@3hcG+|ib?Aax{y*|O--9%N%(&93v$eG)=&E3>Zi7X35y+NiU z%CLqN3Q=T8oGwDdBh=$}VyCuaF1g-$ZCl43wE|3*P*ISdJ3*xxK$(+dCDYTBZ1n~V z21B$IY;ASK+S&%zTGAvX%X9K9!}C0ZQjRhb`1E>xMsY&DqFG&8r5c57o1bBEtpJ~Rvc9YsMjNU{jqq@f-W;eno#BmV$_4E zg=PF+t%V|`kQ%E(RINo?8uB8?tGGh08ig3^eC4ev`O>X-bN{!VKuRe*KR~MyMQJEX zOHmk@+am@wX;cPPt1D zXBp{9K~$@f7p_>%^O93%mig$%KF#a@&1>ilMkx6|)Hp&C1)9OIbmCwMLP?g_d;I-B z+=m|oC?&xZ7%RvMH#sRvr<<}?VoF1&+vll+$9d}yyp7>#z+jjlq#BE1OG;z0?kgW# zaF!IMrdGeVf+yRbLWk?pm-#fs>t4_Dq=l}TVA8_q;*ITJP5&F*f!q-kWGiR?HB?a@_ccHaMk#x~2Kq^glFml#? zp0mUYeGgv=nzbqmXBT)JU%H)L^D}(zBOm0Urw?=J#1dD%b~o+NgEXcw z(ctP!FJiiOA8htP2&C3X1PnU7{pL3jg#q*Pb1ZG-PJCIGC;?cD@->Ai0U;)*Cauz* zxb%{XxaOK`Ieg?f`_#AY71J$cLw{(N7f)M?fo!)XL^X7i4A*wHa<{{rdHYFbr5+?eX}d2hg5Jy&CYjTfV^OzVHu@TA)4t zTEf!eGWB{L0Yttc84W0stu!yud2XrIv^jbFWckFSkNcg$-`Qq+N?iVemk`w^saBgL zaZGb^5E4Gp64RS65krS=guJF zWrPvs^RIzymQX@=>Eer5`JRvZP$EYNIS{Lo6yYw8} zw$0-EK7%8tD2-(_8lguCwWz|%(h7dy;|b{kiAuw;H>BRE;dvfeZpg9})vP&=Z=I=Sr7g*=K_Kyj>&7cj6ZaE5EgfY?`^2M|lifbnTD%}YN$28& z5EzRCGg5$cT7X6^qCbrJ%58U}lp+WNvOGuF5-F`KdWAsy3OlA9Aq0;EvkU1CQ$GEL z+g(^xy#Ywl%+VYMu`B$A6nI+WX+f4N?tAC}x8L<3mC&cvZi9-+OYntz-om)oOG|^b zP$K!lt@rZj&)&)+;zYh zFgeiUxb{Lyin1gKe2kQA^C-S9qRxUeK?VAW8GFqYh}TkXnMZ#A(i#|KU#Vy6b-8IKfIa2F8#U z4q%xveJt=j(j=o&t8@F^k8|YY2e1|qh84W9!shyh3p_I=7E9#&%uG+PeSV5pz2bVl z{MEZSa^kF5SzSYo_mV9OMuQ=~R$vOsvP2;8!+>6I#61r^$H8Mu^m}~*-=i>qbyFH^ z!IO{_VywZCoL=1Ib6@%<4?libY;E7}gp5{}=0l%8(T zsZAk-j};K3*c#<*tgq5)R;dO;4AauCb_xUu6BE@pJo@OPyRN*j!R%86uip|8}15U-SA70Qe_fk3D^$Ow*jG;-hTNa5$h*ubdzK z6=n8Ie47AZYjy4YwQ3l~{Vjya07Wk@Q4)4d)H(RAQy8o9uoy4kTZd2a{jYr)pTF-h z?mDwYypPY#3L{T!z3jh#@G^s5ccY;uMxvIBTt7MJ$B6Yx?9Zc z*p6p5SzkGuD=C#!0_}N}Nf%S5^oKF2cEw|w7HoF=H0u=vf?jV#vbo8-e(_zr`$xW? zh0~|0x29M)d5HV&yo(pT_{CiLqU&k2Civp5_wtKB_Zw6vCa6|Cx|k~6#V{3)^-Iv;fM~`yq$+ccRtnysYnddsyA{miB_bB0oHNwEBJElT4 zn{|5KE+~&QNsyk84ns_mQe-)S)}&d^(&7@}5-&$_M(9h1E9>}S0Ln*=Z{l7UVXSqQ zc&5O5Au>(qpIuyY`!eVL@*wSK=6!Uw=ycLO%0+WL%G8!hOIQ<-E*k#wg{cNqT(KMDItZ?}7 zF{Jh|c}7+k^1P%w7!fs_lvzp=#~@u7QY%S38sUvanl3O(yWpoZ!8Z-IHa0PtzyuMp zyM{6#!wNELk_Qpi53zZQ^#eqiW7f}M)|No~6edT6AvR7~PdkXq<`5>u*UpkvU?{Di zG@!=Gu6__umafyMv_3yA6VeH7h0-7t)>wS4==KH(BS<#aN%}p|0Yr6hm>b<}K8U*;wT4C{$^dGd0nq zD01iQ1vHyAf-nGMS=;E4=LMy)C~F;+F0~HGl_e5Dx{$PbHDVaY9L_lv)Mv>n&EJWv2M~JrNG#di}vp&OB^)~>*zhrc8gB8PiDsZ0$dOk zmPWmT^4!!`Dn+l`qbN&!&m*c03ZNKL_t)wR03zf;A@HUe58`} zdqboUB#E1rrMW@doX}TfX^K_?D+Fo`D#1=+T7njkmBw}6OGAzp{f#KsrD!6T18MNyR0>s2NuT1choce`VajRqm8 z1OeSVCd)Fqy#c3BEHF9UqEV|Lr9vvmiju%nPIQd}ai+9b37zhc=Z>7_*oiYtPEQfl z8!i>vB(AHUW_Zeh?Ah%*5Un|~I3o=`lF~Z6Yw7lFCl{>s21q$)SGQ8?k)kLKwa8~> zZJkD=TI~*2J_Nk|A6wge@r$=y^@1xe`oJ^K9-!H7;3-L#L}W!NtoG^k|B@ZpWQ&?R&1% zH;zXK*D=YBMFPe;+L0g!EOA`OTCE~|JusVnA(O(0bBjyH4PmuR6z?ET)csW(C_xxxpN13UNRUAiC32>)>c7D zD%Co|uONiQ2#Ax6;EETM@3;(+Cyrn1SMa69KKBrfY>3Qa2AvJ2t0C3tS-OWG!{#x1 zqRxqpHTr{?X3GUBJ@0Dsy!(n#9uh&3Ia+|$iokc&2lsECGfSEz*fM7}^eIjpr&*NP z^%EEa0nXEXkhrip|LRwgOzlROIriX#w0bMN;w9IQU2D#9@af0dxBnt`%=h(giODj&K;mhM#1%JEI*Le9W|X<%`uQ3Y6D{y7 zbbEb@(hx|?iIb19v3LUgf}1G8b(Dn!HP#nMON{L7){{sj+uI&eE_f z$@0QY7liAW=2^ke4v3-(%JUJvM>b5zOE7TW)y7!2=cTX=`h64*JlMibiClf{{#~9s zV68nL&zB5GF%{pL0T^q^)0B!Q=?zozvUKmSERaFqv;cxJSa9w;S_#rIAbj5cy(~*N z)e^#Ku(ZTeprt0xOQZl}ozHrb=BUB}D5nz=Jdd(`Em2C5WCc<}Q5r{c$#Mta#_w4w z;pj}bKNCP{3gXO7JA9xhN-WOt%pqREU@)ZOD=JY)JdDp%u(XsQHO9I#LTgQyyJ@1p z(Tj$$qm>w(55LqBPdU1f0Ft!8_cZN^=J}w;WHiE9gZ2~<5O|s_O%O69%S#7*q;%K5 zYgH4Cbq@WZp%QAWu?(}Ede!aY(mMK&u%MKi`k1kElmwz`NHB=U5XPN%SrQXP&cGl| zGnYev+f$51yT0dy=t3AQf=07Wk*1W!FrpyKbD}6D$uhLk_*HjyJ^%X3uP{A5!{*u= zd6qfACfq(8C2kt-RU)EVozWC<^joOl`riwz^KQA2S@C!dOeK(Li|~{b5S8 z<&SeM#5j>$BebR{j63tg3Q~szfyRt!X4|&UGa3wulb9mQ9Y9l(xHRrF^L#wtrxv=& zs8k^~%aGc~Sc5O!o-DJJLAQ(X`>flLkp$yl+xgp=@D!)E`jlRTkDEvXG$TnM8+K!} zD=M|t+n##np(kH(#SI_&pVc-$^yA;R`-U5?`P^{W3zKAoHww|p!w*7+qcv8~E`jhq z{AYjm-uxd^D}85u2LSw&uOGbm=I$^5^gHg)lK3sk3$UgTbMxB?J;i3fAk7lq{}b=~ zgKhJ(SM9Zgx{c^<>8 z;Kf&6G9D3XR2cEz5Bw*RUYGy+%kLtK2js>bet}ke@Yn$-Iy9C>t-`*27jfHdw`1~* z(I{t_Si<@=X_}XnC=zQMn@UOzR&m9Zm-EUSucuzE@QIIqimR@?lvd>1CmuT>it(5- zNps@Ch+e;s7dSuTvVdNmeDai7YTI9QfU1_2~<11_} z3Jg{#EdpANrW~e9<{}Wa*(shrc!V434Y~i~ORW%svdEd)zYnQ|*t2UVtLq(5?vSM{ z|Llvp7sp1hYU{XXyh(YLd*w!)#qhuE?G<-GZO-pqaXe$(D_&%L72o~I}Zw6xS~ zRr+y$UI?wVyMY_e!;k93{SMmqNwdOrn{0s_M)$;sxAx`&VeUn@Ayf_Q11PA;^*h6FQq%V;oPsG+=B-R0&Col4KOq z?+=k$yRo!{fA@|b;DHAp;rOYuyz1rG@ZNX73n5C59zSa1%&>dcPVwSvuH%D$_)$J} z_v47^T^K)tG{%||Z}S}a!EbTP=l_OF_Fv4YGbh=$eI6|>)v!vO=DhXazMV76TeK%9 z=ybXSfsYcPv`YdONEc*QTBqUB!Pst4l2c;GUiI-Pc0zRl>&uIL=(m4`H@)#KJpR-p zoH%}%M!m+1uD+haXnydW{~J%7I)a_K5UJXX-dl6i88Y^As(e@ zt?@i>%sZE4an3}u%AL1=h0u?9_=yLsQbKfleO`6rP5k92Z{gkl{tr-{6==?YPzX~% zX9F!~P@acSnzBr>#*VEtEi>&ljaGwr6w~SUiPM}kFUPi@Zu%o|(qNQMSfr<^Mis&+V$|!=>klc$oo~imd@<&9E9rhL&f+tPWAZF# zl$GR#gZJ*ZbD9qAX?*3TCarcG-}i|J14h}9VjM0N1kUWh(U2t46Jz15B#vVWE656a z-mS=DDROuH>v8crR=zsAlyusNi zNC)6bg9S#J`+T!Bg<9wWs$6Ge%&N;ly6Y0*fEB{MFW*;KQzC>N3(_US;Rs>#^V3R~ zPa!Ds5-G+sJ}F4E(j`V)h~tcYXUk1!#tw8+Dm=}34Tc=Qwh)5OR);~qPgsd4i-I(X zF~&H+D52S`vbp8LGo@hMm;xnT296YB{J88qjno+H?5?ZcdHvmJ=mPY#6bLOzb3;}b z2fD|5&6LI^29HLLmS>%=!d;o1pD-nZK1DQQ)M$~YfKo^|sl{NeK==V?`ieUrJIZUW z+(DeWJr?E#VN@s2bGy2{EW#lC-Nz3+xN~8-|2uDa-Rle(hI2@W&VI-t)@8`J2D`;2n27^63Bg@K1j7KR0f? z@%29yXT#qtl1*=OYd~IFy2A`5VK7Vxf`DEo_;2?e#% zro^{7DylIm47r6ud4#rbG!UWAcN){YAP2{VEL?}t@s!;S+*nI$EWMG!hTD1duYUv; z_wl7Q`=MVse7F{m@&<4Q%y?Zq$yW)0Ab7c>X5uDQZ!LdaXutqHUw7 zA{wm*jYbu$CCgKkuHw4=mLzqye77YGLrCJxI75G|G3q6KOMz_=D-0~`EAuzrgd()fqR0_aNMdAS_ z8SqQL`hMQ|L+@m1b%9e0C)u-eJM**qxa_iv#W%n44YE-m7S zN+XqWpVydTP-K}))GS@V5oL}p)3K{c$*vuVze{^!ib@!8-HUEw z6n7COBa7w`R$___?FVEgBS-VbH{8r?Ui(_koPHXwQl&Q-an)7(x$=rjx#yc-;hCqO zK}k>alalS*=UHCapf`+}Z#0n@vdrLl8dH||)d)YVu(jD`G>VBrkGa`tsuiD)fATX( zDcQAWH-S9MuK6Y>7tXT2d``UZg;&w2Db`j`bJ>-bWB%bDSUL^uIq(B23W72xtXH|@ zqCHHsBb1sa&odsl?;fgAgNrY{f;|`PJJ#z-O zR`6>TMp)YQ3Z3o>o13fDYE80XSA62H|J=Uj6|dldhaW|2k7U?G3+VR;%*{-)xU|Y( zm{95Uh-x(ik|IrArxODxvNU5jiV4F2?YX^TjKTLbCeQi3-~CSv;*kwQk1MXYj7Gi2 zpM2zxx#RAK3AG^VuQJ3^HYO=fAA!@)qOabER+2PMuoXdRN{Yfzuh+QlhN~G4hHPza zp*=@6a)p*43^aWy#zJTdQZP3=#q``9y>p6)4R%rq)$Z|_Hir9bg zJ_h|h)6CUV?H-uG>m%ijh?A*DXEK7O(@uzv}nIl*$u*MJs z-gr{xTxOEeGCe)X)bu2_$kEcW)#;9lc!BRJv=R&pH_+JVmXd8TBnnJKB(xlG)iAF5I&NYYoe*>pb<$ajbPsjWG1_eNB>ES40*D zp)}uh^G#g3f46<^&@u6iyB{7;B*2WdCEyB9?P~&G({8uevu8V6N*2y7bL{v6MV7ni z1>?+U>w4$LSPBEXcFhw8KFwB>C!RXY%F4Pc4xQTBb%%|?3X4>ldb3Fsg_K3X#ya!| zL$a|EgZ4B^NThIp$pBLmEoSFtDAR-@&sf{&vboiFK&A{_FqgGtV>(a0R$*$gO`}mG zOH)?Ywn*|mc~Kz7HnhUJX@Z-gSSl5dT|2fRu&i%vvDqDv#EEl}D;@ZG9?XEFKvios z0g+OuVd@5|(m_jO?O5|?$qPde zhBO*AN8c2%*&R5rV+>L&@+?PG-D9k^lzB!_tr8Cglx0qmIfpwKYhbWgoIWD(1X@Xw zI7TTqttpGrnFHhwR0diy9->fMND6~CmRhZb?`g6$rr#ToX0CY+1A?*AAj~s zWg0)Yuz2=ZyWTFh?cA}e;)ic2%i?Wos|!5&)KdhWpe!=-%-H^*BZMv3T3JA8{hRyu z?@#}~FVOzwuI~VVe+KLKKKhAUfBq-m{>`bG>6@ac%~p3{o6VL8rNCDe4nOx4y>6Fx zzVk=l^2(cD`<8BR^PWoJf2~z-ccOap8Vmo%_x1K?o_&&DKcU%b6AU&`N+WeZy453z z6Ye{HlCK|Hg2p7)_gU*_tex$Fr`#+a38NmIcnan(go$l{0X^_n8pZ|;Ivezs&Wc^zCwcbFkU^5s?QC%3$YD;LJk7h`^W&U8cAQ&2 z^92!jicxm}wq&z2bb@1Hv8Lq2$um6p>`7#OS}d-m96r9p;pdKmfp}|+v=Py$MP$~X zwIWV4JmvHlc_A4NV@AW0uik%995{GN`Sm8b)C~FqCMGASJ#d1?fi=>2NN+e|Fc?y1 znH#;2fl2B4j0!=&(jpIPPT)JH{Q&31zakmn)$2U`$fI1oe+SPTI>I21dH8_`2t1Eb zW+?I$DJoE=lu60V)FkH?*Ps?TetVHoZMBh7JNG3e8ICg2qQp~z>8U2YUWXz#sHjDn z!9Cx&TlD(_Zu!h-xc9z?xar30#2dcn&0KWdOL_RA+xY73_p`Ox<2~PZBafXr$D{or zra3{PBtbReMyc) z&rY6r<`^r>tIW<$QLWWT(~PiMr9=`B1`G#%gs|+~xq~3^5mFA(97fBfOUVE;vz@{V`Dk-vZVS)N$zVxtO0Sui^@!()#< zNT3ZbeZ|du_EVqc_S^13D9w)DJIS+@smTcj{XWJR^1NVfZib^rPXL06cHI>jLLikw zC@AyXCB`Nh6YU1AR)h7mb>cW<6mKvyGeMe+_{!%$&qk+*$gdTzea%fYTNC{CU;Gyi zJozMVd(-#wvNwD;zyHb4(N&U9-SSx$&m7`^|CwK8;nZQidB<&>URV+3XvFE$3zW&w zxs)jD99=pcF1z$X9(wd3>uVd#08&XjKR}ui;du=D13KM4N?0b^Q^>IkNt~wSS%D`M z&8nu%g?Q}22Qi}ozxg|VKsC6F|NN();AJnkil6(HU*QXPKf)(&yO-DAa21b;j9f@3 zW)+a7uKA#pqTe5I;J_iSzwU(yoTJW>qfY;)wW1RGj)pfbJgtG_$4^tO)@V<(kU|g! zKBHuSu$IvGpe)W$5S4PC@fYsh&AtnFGaALLF0Zh;)uGHwe65H=O}Asm^{VS2A3S(u z-1U`c<$jVh!}Ao?dYz4puKRwaB#9IH{Q(p0Ce22jDD=s*oFm5;&`RTZ3ay>vk<(Zx z2K@o6t847tyNhABN2?K0i$eNwHr5vfD9`CHjD^e^)>qe=o@g*J(IW5zrl;C0Ev+D= zq*AS+I(=-KxUROfY;A6G?C5cJY?~567_f8qc8(o8jgST4Qi7$@D5=g*O28QwZnM)9?1s6K$kaOi#7wbh^Yza=r`g#KDf6pXCKx zTU{zqg_-Fou#gu8Nmk^{8mgh&leJovOD@{&vRlN$crxQADMjgu)#vF| z!#F1xjJV|D3#nED5XVT9*d?$FJI=iD#?%xS0GDMsg@sqV^jc1wT;R~rQ>?G9IXYPA zQI6A$tua`fHUOYKHR*t)=aDV1<7tg>t)~AznZc5!8J<=&8k+g}8MKlNlZ-T3B_G># zmX6uz8fC_b*gfB;*{l=JPO-VwWjJz)xp|or%D@Tjm87(G?3Uy)HPPhi*W74F!-06< z!6#T*+ayaZ#22t7*UK363L zm8gRDG<)~#pgB3gbI%@Pd1-~bDCzcxL`|Rfz47Jj-m{0tpLvciJp3G4YnEJk;|vhk zl0NqyTA~^47GaqHC0Slt&nrcOM0+8pjvpqfw3`3+4bh=$m zoH)q(*zIg%bDcOf1VKO)wdt;$VPm8F;BS8Dum9%%=Thxo-1-gx_-C@RAwTi-V+S6; z`eiSzlm<>5Kf<={I|(aQ>XA>czsWuK-ob?z?B$BfuXu%${wo~!yvyOk2U%WSqsVh+ zXQoNwkqfTTf;3HOHYcdGrn%+wU&jU!C{2{~*dC_z(}FeChP2CshK|jUyY``kWww&h zQ58CgWu~U6*pjt4LDi>-*OuAa(D>B`3%wDS?`*Nv8?w^rVKSJmh77ZUjWR-b+6mgU zM_C$nHzR)V<{SCqT@O;*cLlee>xk;|GFAulJ3T59W5+{DP?=+pB&1;oQxVIn>qO_y zFd^X6AO9r68iFw3KmNuC84gD@n^k7!w^477DAEaTyX$@q9zN>aLX^khBPWSd*tqv8 zn#~imn>BI+mtXS&kP1&L`djO0?YOtrKq)NJlxQhQ&}i-P$l+y}zmRks@^badFDJ2z z`_>c6wH_ewM2He0t?g6fS&kHf+!*?!n1L`P%E$T@XYn}hc=CMLO#pd@Ok?i6>uxUF zzk~O^@8|ieKl>2(-gP@a@~-!?y47=CK+i{eA%!vcN)h^+jkR^AXQrG-`q)~pC<@Z7 zAjwkFB;~^0bJPQg&>?wdDYJs@GZhBCEv|my<-GSN-pdWweuIbay_=fvF*7~K`qD`r z`PR3%`sx?({*a_gc*tKl8Wjn4f0*jtkkbV;gyv@}}>41@CzMD-lxj z#DDubX<<+nG9x(n%mH5e>YIq7h~+aUx$f$H{N&I6G7mlcC_nXczsdB>92Z@@&)#$Q z0|G!x*tKgLCr_TCC|m}Bkd7!JrC=}|cLudYYel=&pizr3z~b2@$}Hv0Z+I2gUH@Y4 z_}bT4JbRjpFTRwCsd;Yw>g^Q9a?{Iiu&=)MGV$3v?qMO%F+!8YDYa^qCajM#I*9<-9oOf*A2a_ZCqo|X&;112Y0Oi$D~v$*C2-pUCE z%FZ$pZBCsMltKFt4>p6 z3MMDpv^V>lIlDxwQK2jgio8Hc?WiH8!5BDr@Tgc@+raY!w(Xeb+}UN~yuc4a=h#)` zXzigebo(O?K6i}mJGPOeIn7p+;b6ep`j(?C3g_s9DX>yf2?LHEJIUhmD)m~GFpAhV zKf|$Or(GeY6nUCLy^7KvMNyI@IS)Ph3`@)FRO@wG%?9x(VYAc23oGYA(YTS0L2zbi zo$fGUFc{+dK0CM15RYQ#pjL}mUS2`Th67jQZu#2EDsyu)OifSHY&Ahh&YfEZT=APE zDZU?)WCkfpjvhV1+UgqnF5C@3trm^HGsS3_AcR4CnzAsYNyfsNMHUyAx#H4&)M_=_ z6K#a@*xKqkdQ@4sGgS&oqZq|Gk34#SGpEn8d)GYGD8x=pk`*P@s6v(%&hFRqDT|WA z!0Cl0jvqb2^vpCf+vb_yHiukUXV4!IhW`1ZyDSY-X^bg3esY23l?`_8+D@}k!_F71 ztZq`PMR*e}j1>rLP)br5%hJ*cOXrrDm}oIKKg0H&+gV;(qTh$GT1Sahq;yVNo)UCB zUDj4sSy@>Vd-v{P+qPMh)~v5@;0GZxE1i|Az|qdErQ7M!>-K22noLc$nVFt&+M_|@ z8W=cNz_Gy_c@nd>x(X$cpXt&zbn=SHW z;OKZdM2eEN&7M`#6Sb|Z<2T;-P8QcTdDowQf#n>eKjv&& z*i;e!<*WD6ZZ%2UGxUQ=MtOoRGwf`YEx+pg#Q`G~)^8#_A6g^6>ov37w6o6t`Fp=h z6#8UYL7b#WN+#OQrn6Ryn4X=cNE7;T%rl1YRt(sK(!i>s{l_|F|`IFipU0i-t@Yg`1Eb}v07-nT9v$XU40=X z-BeH{1xQU^mXux{D*pL`!Vy%*zl?!^Fb1Q2l<(sypFm55P|VJ>dGU4o`R+Hqme2g{ z-yv|08hL+2t=S;-Jucb5o5M#=vA(uJwO%J4C8SAAo|hz9f$u4H&Ni5zs31L$;V5P_ z93d$g#0gSb2Ax$l*3QswR+yLwX*R2r<&gHo1ifybB3~oVGgf;8j8GsICLPkKS9$1> z1KjlTmw=K~YYjZ@69f`bZrVnBQk3R2XU;B>ra9A76IAO}8nuwCuH4VUnPo$In4jcNT&{=tk`uYX~x+%EUwiQ=~{Go%mAwEG@5Mtr4QkNODK* zXiv0x!Bv-Vc5#(nw~Oz)sh3u+Q(3D;W5K0ib7KR>T;bAK`h%Dvi!o)!w)qB|O9e_Q zz$2(cB&Fb|qzvI4xCm7}h4?p$nc~_Wb6ham|F1l2h zBpYvS3C2(fed5u8?c3*ASX={R==FwFtC5@7DK)0N2wLqn#%_Xent)EX!B(e-k``SF z$;VU|N`uxO;Ici6!UX|dbkPOGS?-*KJdawf3S&{QDV@MJj3Rt3F&1WKn)C+=Nt%(S z36+XJ=DQ1mz$1xcvci&Q8ATdX6eT;i&oCMdNwW+;2=TN!e>Rt;MLcgXfU{x^e4lD9 zqQAUGlBP83HH36Ra47{@I@T|ZMucHVk|az`wuwh0hTSa!Uy=FR3H`0(To=}f{@bkv zNs`j2M{Jv$aNKkOwR(iLB}FctKXTAo(d!SWL?KFRrl#7&qZp}_%Yx_)DDoUF1x4;` zJ%{~1%~}OJ7F$nFHc2xla;-)ciZZ7xT{ei6g6Y|5`u#r5MvZ2(MVzEmt07W*=ezm7 zFUhhJ1ZXdy(;aZ=&~dhJpQX`kkS446I-u}1rpU=Nmy4m4#Pe!cYk2CJqg=fI0-DVx zrExAq);e%l6pljld@e&&iP+feFp6Vlrzfa4>UdfM0wD!inmDfe`1fHLQb<@?+r)x9 zx2hF-y*^2jkc|eUzUTHYb{zUuWf*51J#vEGyXI)rYYayTVc;=}6Uws0SVNhY<8VGr zQRXZytWv1B1Dne*=$%<&b7Pb3J9kozBFq@LSYR+psZ;`dEg8irrLionZn3oT5IeWeFgrWN z{QNA{YK6FfFbw#MPko;CeoWW+R2xl3(&==p5EN+oQIq@6beXJ$;&m_BZakSwYYIFq zg^(eX$vDSB+rZN{&tlQ*N$S-qSur3TZXk6)r4r%?5mF!)P9CA?cbJ^n@hk8DnGYQJ zUsI|5%Ua(70RN2EpMBz%zxnBR{oB2V4m|N&FM7$#i0Vz0pR&2t`M=t`vmiUq`p)Cu z=Y8Jw?C11yy45YU_T3V;Ft*uuLtx^`Rwf}#z>`1{APbeuAS|2=QxbNAiP9j|>Yn;w0NO_SpceV?0W#(DbrQ#|;@VSe=| z-p=-!X>wtY|MZccW@W9(voE|zyRZ1&d%wij|KL}+dDj*e+XH6nRSLFbqF}PrN>EOg zz#uF^GcmaLyJxeSch^O@9;s;&0GL*mVv{E8sSF8%^@I^6sJa$=HqSB~jqp4dDFvpL zB|4ZgyO0fnkT8lcr9|2emg|Aa>KUapNl*xprOb@{0ddyfMtgOIB#y}!D_KO{utz?Z z!_5~kU6+2h%U~4J^Fs_nW~ESB1PR13hBR>V1#mo&X12gk&`%RYuJX$DxFNF|Ns*@6 zLw$WH+RIg&B27_AjA=VrUxgq$%?CEjZsWw!XK6PYc=-a&W{ZjXIHhul(`PQQVMCqi z`WSn5ZRN(|GHZ?YdWwidO38G+N;zjy&bvq_&%%vW(j;PLW&>-D7HjPhQb{K3(^>z7 zP}DbUAWlMh-3}=R?|9F<`TSSD&4)kvd9Di&YhngZ3dSu#e>lXNs$#n?{caB-VycrH zX!m1MSr&$2a^>3XoxshHVOth`zs1R8N0^+LWHj=b-8jR}9b3rfbDTPL zmf>)Ol#*gGPkp?~z;j6AZ1|34+eBfOEFw*l#@ZT{N`Wm~wh%_y&v)Amilqw8wPpIl z0H-|8v(J5xO`EnbHeOZJv$NuB4?n@<^9{mLNGdJ%@7u*|?zn~X=T4HuDdW>y)P)OI z#AJOVyLRs45^>;DC^*c`*0aPb zLz0A9S&JWp7&!F0J%+;}GaKq$ym*N;il~(G2m!V6aY~gMy>6RsvxzLHGwVl2xb zO`zRs!TN2?_}CbxZG4Q$dYyj1 zPrK2?$z`YYN(fxnAwuDgS`2z!X6iM91e{zx3n1wC==KK)&*9YBi|pUM4cpG%=c}u$ zSf*s-#tkHC%IwA&0EUAB0!1f^*C)yWc6NrBBLgPtlc*#n3VcREL==sH zY>jB!Cf#-mLny{-MWp3$;J|MDFeZ)?2K_FB{t(MDDHL*~>(ALizmMyh_=5rU>1j4> zlv%@X6yp0Kopu+;wh6<8LeU|Nvv^nO3JN)oJ^S}C91Mx$guyV27C?Dv_Sox*WFFa${u&}p^kk9=yC5{{Rn)9Ew2ahiU&$0!Ifq{;r9_7bf(f&0TD zo!$t?HkqoAWxXYKmN1k?0j8Af+PxKoBp3||f{;-VV@N@%n8P$pd_SOADl$6O0Cf^;;tYf4x!Jva*uUb~C$?D3^*@j!k3L z#(|PfGKI*R zzG6W2TBtN-|G@)TZb3cv=-0*BlP6JTkt5Ijfb*BGF^XcO;EF&nn+#ph8jU7knfOPIpMA|^^=n#)VP{Ublca-+$^fAoh82P68!h~p=| z&5LKQa_P!7Ca3Bgyya$sL63+3;XACZtg&;)RxHaRjzW5!2DjXN0EI!npCwV03l5F; zfa}+;F*QAvMyDO$vh%7Z#Rz>C{CYe&RVu68tdYiSK`gnN6Ds!U&}V=Pz8L+wD;( zmKgL07%HJuEYNQEsFqyv#R*EKB3G|2;*Ulsl`Y;9ilom#)Z>YXf7>d1Vb1O@yZiiyxvuxzV~-T6vq^b6*1}$ z_{sy{CRU2;i>usp(;j;LA&%>?dFxhgT%Bj*#tm3fu(Z5Jv$2L_I~az-a$HO)A@GT@ zxbV_>+*}SsmXlt{=UHA}c>9H*;CK(Yya-| zIdgd>YaUHga;}X+VcT|=PLre*3VHVL-Kk!4=zutL{;K-hZ~dcaclw0!B|O(c8j_rw z#Z3-IKGkx8n_sn$En7Cx>2!JW$-^|eBd%Uw##)a~%(*V6Ws;^TYmGLwa)I~W`37d{ z6ZHLvKmGIjIr-vQEK4$3p8z2l4zp5;z|U^ggi3kOd)}e;?U)hg7uNXnyBC3K7jl?p zR^AbY5pkRl2GRO(!~|0)c5Ry}M)`$N9-^mAF7%X-6ToFrKvOq@-T_I)4EvAAi^ zRtzaQb><=~jqB8^B>jljm7mS;_MAlawGz zKna2{CSNcJl8BY16(%NXOxB7xj?K9X3#_d*$ma`L!jw{3;!oZspU=@)Ymm>mR4YZy zGz0|KRy!Ed!m%WSQIvh27?SacF`_VJb$Nwyxyb%~JE@jROiq@0?gyv2zPOgn^%w;p zB$E>*3WWmw-he@`%fSPCc>7!Lpx^KF%(Fk>!li3jUj|u|ZX8LbrpHO*kd@UYg+d<3 zwyBizs5m5zBQPYUX+oG}L)|=+`qU&O37u{i%d)6d%k14bN6vHbgOElmOV9#vJ(qkT zhhv#UVMrJR3IwTQsl>M5DX|Q?I6#Y({RKaSi zPl)$Qk3y|dWMXm~t!9I6w@l29U!6NrbjRu;H= z`6AMg?7I2(``-Jb_x!>?>jLdx7`*}bA@rwz`SsuW_y>Qy^UULqee&w1i)@^mqfo9A z#tIc>HPfJoghHfQ44$DBu@XpWVmlryYaRaT{_pXf`8G~{2C+7em1dJf)3p`;&BuO@ zx4(KHC(oSa{0m1oylH~p{QA_E;ze?mYW6Tl zA(ir#(er^Yk?ZxfhLIpyKOtA^!*|vnq^2PeNkTH{U~jn{+#-FmfTaX!WZ~cvblVKV z1QjQwVHQ0Y#R(W$$pNNZj|@?-G&F{}7`zmFY7_=T+h>)+;jtW2+V*Sb*j3mM6 zw^61AhKZ8~80{63MjOj@NrizaBt;>z>8)yggJxvuB5@S0N7I2yvN~fa4J=b)kZqQt zV1yw8R+d-!KzqQKis-2!rLNWmcOV)>?zC5j#qloSbB4cAAyt)hsVNiZLyl`5R57fT-VR zIPxJ)={^2^LSeIO*JiAOjWiUAO0moUXSzt3-^At1m+(p@Hf-8RtKH?w1!?Aw2wXlYe^d2uDdpnr83s;V2{# zl4j4RTrQIMu#o`WGJ3X^ub#mLV} zFrI(mMS{TRU3b1wyzQ;8BTSwag}jI3c~~+VBG>KpX|_5zjzbtkEU&CFIZGK(me7fBMP8?yGMm7n#UuCjZVEdLT?OsBym?w!-a-M^R88+_!~FL5fts%ygAaGgGu%9URvs2xA(JY|-bsHoZ=lMytR?t;mnv^=@8u zU=LsZ+BZ3Q`lT$LNJ?7m4pEpbx`iQFSzcvgqQ-_Tlic;*w_=)-Z$J7pm*=k|EeFF8 zw3^MV+)Ee)L4Y9ymZ5ml8*b&$EeCk<>=n+QyF{Y0TMK_UpfmIlhQu_p1)A$vG}c!6 z$j|=_ANlaFbM)wAoH})et2fpVGCQ%B>kZlhksWx15uxw%@n8NBx8C|HKKuE<;?Mu$ z%S1ttHL$Ae7A&7HFdF(4b1tRz6s*tQ_dh8XtNh}}KE|U@JVWFMbo$xNn(J901Yr>1 zI5xx4h^<>T@`+D;gz;*Ldq004-+K5v^twG12GW#BBkSuhEel5}{6U{L-tj7a;e&T0 z(uj}#`hVo=QX4-?v#3>-MOsH;h-2GG!=T$6aL4Qv|K&gb0c(vVe)dBjqup$QVPV@A zrBXIKCyv5w>bgHY~`aa|?mLhZl~Y&SGN`)2sw3R%D53D&^bHUlQ||=6UsjUF2PfW1A$y z0hS7Y6vxV@bDQhE6{ckp_(PVLTL`nz*t+kgPrmm@@6jj!|BuA~?-!u`pZ(GYfAa2J z-u_%ZXH|q!2w`UF3gM7g7^o;hrGhYyP=?J2kJVP6Q4rJeQ`)Ib>g17R+1`d>VhV*! zBc>~PCJG)4ODi;nA=RA2bgjho>E(OZShPk{v zaLY(SQWQ!V7)I7mm?j~cXQrrBsyzRL7bxcQh%_M%eB^o#GDh}i5r^3ciO6z^4PhYM z9EOp_p{Y2^Qcob;B#_+zWRam+qt(kP9)`@~?F>?4ArYnxM)qN&3==!{spM@M!}UnW z^#zz^TObUSAe+LN#3WIOk|vfk5JI6W7hyVJTF794@CVt4zh!6t38E3hL60a1Ayw*XdBJ6xld4LF|th4oAG>-FI^4>;=x8JOHG=1k9;4G6qS7pi^w2E_sgw(Z{)mwuQYsaZmW7l8 zOG?5prrYahi@Px7(#0zjig^}qEHOS_W6PE~Ql+R=DkN#Pu`5+7*;RbIi{*KkwnfnE zVLLX3QdaXCM_E&}Q0kS}SE-a48yln5X_F=q&pvyc%a`Y|Z5wGw9M`5)%x5vNen6_! z`o_(~wk_(@b^M`^?+5hz1L7!RI2;g0$t$;X8)m0CaA0pXNGwh9T$kEdEgKvb1te(# zA_bM@m&d{)3=)Pxgo?9T`s}76q*^VL^E@tHxyE;&`aYiH;CLQ!;FBxls8%XC=K4UZ zG{uk7tPH`niToj^TO=hr5q{x?lMDs{dh)~K5# z)M^!S`8-LQ^&k1M!nF*-L65a&3)`~D7d*~iSYTyo1!))z{eZjv)!W!QSEpF2^4NEt zBaQ%Z*1SO z+4%AIzEu_77?A48@0|=&!@xA85Qagg+vmi|vnrb-V2Gg~uzm9e^&@w_76ED$Bh}$COg2G*P}E#6SDfcQHLRj_XLVxY`n@PF+Y{$2CpM6pdz^ zQ)e%xz8}PvX^1!on5a*1$D#ea=9WD|fqdcE>G0ZG*Kl1A+qOA+GND)Toz6)m!wIGZ3;n}ikaytF+N^ZhhDXhndvcg^o27R(o!ppc6#`G&zdI6 zu)Um8X|_;Ll2nb4kE=t6_K}2fGFEcaR9b4``l>kb;%Rx~# z2lmUO&!6I34?ddf^+(clJjz86PzaT(N~L;ztX5LncW$#^eQ>+V*}}cL*pc7()?FsX{|NMdyd$= zWs?%7K@!B`(Z>!O$}m;IF|l1sp&*VTF;SmTUcNAT>7|$4*WZ3ieCOM46N6q~oH%z? zeDO=)5aVN29Lrvh2{u#|rN-RcOv@0Wefrdy(l6ZeGvOzG<(J$q{^g&g&m6xvxVkn{ zrdJRcL{YC73Y18YBx!;$varBJ7)0#`oo*{Bcn+JUCYZ=sk!`3%7)l63qzEYFb3@ZH z6M<50F5g{R%HybY000LQNkl?0Dj2*+YfwT&(4xV;RkSAs=-+gT`n$S_xw{%#|m5ffCV;8_ObyB13uwT(5vy^#~9NouJ;g<*o7-9D&dwKx!Al7?w0 za(2#8N~vKul1q!L#nnN_Glfu-)v?jshI%`SA{C~oh{9BeG!-}|rkhWD-JX+wRIC)0?Fz9x}BsC1-nh^MjQLI+2yyF-UlPi@t@xqDpt6%*)KVL43@k)X1 z+qYA2K}sq77+(MSo8_g22G_1!5w7bdQaWk7y@qQ-p)!u|`#kp8VSL|bYHF4{?|hwH zU0scHxtsuq;~3(YLZz}^FY6P>aW;5t{l`<|72HCBD_5=&`#zW^Ca|7#hv~Wy$E>yc zjE$Ak*pGSWp+}7I@p1O=-_7jiS(dIXLEOi53rtT>C!J2m0BAP5!ZgY1T+8Kj-@aYq z;fMcG96tOkTXyVFcfIG%mg*E>EwPK-&vy#{eiO!j-2FTb`JVq$_I zQBulR{;sa;a^S$u$C>2Yz+kJ!4NFaoo+^~Vx$_*}FoX@@&mc`WO*>r4bOm({>h$C`VPI{gR z5hRA8+Jkn=dYvwSNz7<8%9<1{3mGaQr4)mggUW$YsYs{M5Jw*WzTpMIpRAXafREw^-c6CX3wHgp( zVuA^NkSN<0iYP1bh~goZnaeKGloVz*83bS0Drdd?>MT6ZqgX7Zj%%n(3yZSbXiyrP zB8no$N*)n0@hD5d3B!RnxN~nXRvL@KFyy7>%g$P>ZQi!;fL|_`lO##RQ_mf7`u)C8 z(iEFF)O+uI%bWc{e_#%WLp2B^=b7h@c!&1xeEZ*^Uv!ax!-#${)XvPkf+zH@4suOo_@OI^{y*LJGZ?3 z{bS$!z58qC15XLtntEE!Yw4s{>((5Z>*s!?aLum7@UWQcA8e*yJ8}GLjGDUoReRg- z{twsw{s!#NM!x&TYitC(XC2m0Q`gGr}!o};KJ$rV=_WPa1=jK>0K6QKB(tiaSvrHt98_4bWFPQn|_iNp=u_^0k zZ)@Bb&A)P`FZ<=&-`;j7PTRgGbGAkCo5G(n@Bi$%`nF8aNyAFk>ZwtQ6+_LdeZLRg z|8am_NRegp=FLfoiH*D8@4H`xz?LGh%O@4xYmR1fH&bF6*2UngG8qm+b%m literal 0 HcmV?d00001 diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.h b/bsp/hpmicro/hpm6300evk/rtconfig.h new file mode 100644 index 0000000000..9983edcfa4 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/rtconfig.h @@ -0,0 +1,242 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50001 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_RTC + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers Config */ + +#define SOC_HPM6000 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 + +#endif diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.py b/bsp/hpmicro/hpm6300evk/rtconfig.py new file mode 100644 index 0000000000..149fa5ff5f --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/rtconfig.py @@ -0,0 +1,108 @@ +# Copyright 2021-2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +CHIP_NAME='HPM6360' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + CFLAGS = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript b/bsp/hpmicro/hpm6300evk/startup/HPM6360/SConscript similarity index 86% rename from bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript rename to bsp/hpmicro/hpm6300evk/startup/HPM6360/SConscript index 18c366ba28..3e8dd931d3 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/SConscript @@ -12,6 +12,7 @@ src = Split(''' if rtconfig.PLATFORM == 'gcc': src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] CPPPATH = [cwd] CPPDEFINES=['D45', rtconfig.CHIP_NAME] diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c b/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c similarity index 80% rename from bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c rename to bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c index 5d6123bd09..b0bab335d5 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * */ @@ -43,11 +43,19 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __etext[]; extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; extern uint8_t __data_start__[], __data_end__[]; extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,22 +68,28 @@ __attribute__((weak)) void c_startup(void) *(__noncacheable_bss_start__ + i) = 0; } + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); } /* noncacheable init section LMA: etext + data length + ramfunc length */ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); } } diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S new file mode 100644 index 0000000000..2708b48e45 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S similarity index 95% rename from bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S rename to bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S index 4be119768b..6c8798ab1a 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -16,6 +16,7 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer .option pop #ifdef INIT_EXT_RAM_FOR_DATA @@ -44,7 +45,6 @@ _start: #endif /* Disable Vector mode */ csrci CSR_MMISC_CTL, 2 - /* Initialize trap_entry base */ la t0, SW_handler csrw mtvec, t0 diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/vectors.S similarity index 99% rename from bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S rename to bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/vectors.S index d84de492f4..8f10ab7bdd 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/vectors.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c b/bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c similarity index 58% rename from bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c rename to bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c index cb31a6e131..b87eaee524 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -36,12 +36,16 @@ #define IRQ_COP 12 #define IRQ_HOST 13 +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + typedef void (*isr_func_t)(void); static volatile rt_hw_stack_frame_t *s_stack_frame; -static void rt_show_stack_frame(void); - __attribute((weak)) void mchtmr_isr(void) { } @@ -54,141 +58,167 @@ __attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, { } +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + uint32_t exception_handler(uint32_t cause, uint32_t epc) { /* Unhandled Trap */ uint32_t mdcause = read_csr(CSR_MDCAUSE); uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + switch (cause) { case MCAUSE_INSTR_ADDR_MISALIGNED: - rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_INSTR_ACCESS_FAULT: - rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_ILLEGAL_INSTR: - rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); switch (mdcause & 0x07) { case 0: - rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); break; case 1: - rt_kprintf("mdcause: FP disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); break; case 2: - rt_kprintf("mdcause: ACE disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_BREAKPOINT: - rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ADDR_MISALIGNED: - rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ACCESS_FAULT: - rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); break; case MCAUSE_STORE_AMO_ACCESS_FAULT: - rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; case 7: - rt_kprintf("mdcause: PMA NAMO exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; default: - rt_kprintf("Unknown exception happened, cause=%d\n", cause); + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); break; } - rt_show_stack_frame(); - while (1) - { + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { } } -void trap_entry(rt_hw_stack_frame_t *stack_frame); +void trap_entry(void); -void trap_entry(rt_hw_stack_frame_t *stack_frame) +void trap_entry(void) { uint32_t mcause = read_csr(CSR_MCAUSE); uint32_t mepc = read_csr(CSR_MEPC); uint32_t mstatus = read_csr(CSR_MSTATUS); - s_stack_frame = stack_frame; - #if SUPPORT_PFT_ARCH uint32_t mxstatus = read_csr(CSR_MXSTATUS); #endif @@ -272,25 +302,3 @@ void trap_entry(rt_hw_stack_frame_t *stack_frame) write_fcsr(fcsr); #endif } - -static void rt_show_stack_frame(void) -{ - rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); - rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); - rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); - rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); - rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); - rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); - rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); - rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); - rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); - rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); - rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); - rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); - rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); - rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); - rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); - rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); - rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); - rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); -} diff --git a/bsp/hpmicro/hpm6300evk/startup/SConscript b/bsp/hpmicro/hpm6300evk/startup/SConscript new file mode 100644 index 0000000000..de51a7c0d6 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/.config b/bsp/hpmicro/hpm6750evk/.config index 83577b9679..7161a7a80b 100644 --- a/bsp/hpmicro/hpm6750evk/.config +++ b/bsp/hpmicro/hpm6750evk/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=8 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -32,7 +33,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -# CONFIG_RT_DEBUG is not set +# CONFIG_RT_USING_DEBUG is not set # # Inter-Thread communication @@ -42,12 +43,12 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -71,10 +72,10 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set # CONFIG_RT_USING_CACHE is not set -CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_RT_USING_HW_ATOMIC is not set # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -102,6 +103,10 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# # CONFIG_RT_USING_DFS is not set # CONFIG_RT_USING_FAL is not set @@ -159,7 +164,19 @@ CONFIG_RT_USING_RTC=y # # C/C++ and POSIX layer # -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # POSIX (Portable Operating System Interface) layer @@ -198,9 +215,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases @@ -225,7 +244,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -243,6 +261,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # CONFIG_PKG_USING_WLAN_WICED is not set # CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -350,7 +373,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # LVGL: powerful and easy-to-use embedded GUI library # # CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set @@ -425,6 +447,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set # # system packages @@ -461,6 +484,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_PARTITION is not set @@ -496,6 +521,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set # # peripheral libraries and drivers @@ -560,6 +588,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_BALANCE is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_ADT74XX is not set # CONFIG_PKG_USING_MAX17048 is not set @@ -580,6 +609,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -592,7 +622,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -650,14 +679,18 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -676,7 +709,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set # # miscellaneous packages @@ -723,7 +760,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -748,8 +784,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -896,14 +933,21 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -937,7 +981,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # # Signal IO @@ -970,16 +1013,17 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_UART13 is not set # CONFIG_BSP_USING_UART14 is not set # CONFIG_BSP_USING_SPI is not set -CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_SDXC is not set # CONFIG_BSP_USING_TOUCH is not set # CONFIG_BSP_USING_LCD is not set # CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_PDMA is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set -CONFIG_BSP_USING_DRAM=y -CONFIG_INIT_EXT_RAM_FOR_DATA=y +# CONFIG_BSP_USING_FEMC is not set +# CONFIG_INIT_EXT_RAM_FOR_DATA is not set # CONFIG_BSP_USING_XPI_FLASH is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_DAO is not set @@ -988,3 +1032,4 @@ CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_WDG is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm6750evk/README.md b/bsp/hpmicro/hpm6750evk/README.md new file mode 100644 index 0000000000..c5d789a8a6 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/README.md @@ -0,0 +1,116 @@ +# HPMicro HPM6750EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provide brief introduction of the BSP (board support package) for the HPM6750EVK development board. + +The document consists of the following parts: + +- HPM6750EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6750EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Display, Audio, motor control, etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | Dual Ethernet Ports | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6750EVKMINI RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6750evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/README_zh.md b/bsp/hpmicro/hpm6750evk/README_zh.md new file mode 100644 index 0000000000..f58ebf295a --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/README_zh.md @@ -0,0 +1,115 @@ +# 先楫 HPM6750EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6750EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6750EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM6750EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于显示、音频和电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | 双以太网端口 | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6750EVKMINI RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6750evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/board/Kconfig b/bsp/hpmicro/hpm6750evk/board/Kconfig index a04a99388e..651d2de16a 100644 --- a/bsp/hpmicro/hpm6750evk/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk/board/Kconfig @@ -5,7 +5,6 @@ config SOC_HPM6000 select SOC_SERIES_HPM6000 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN - select RT_USING_HW_ATOMIC default y menu "On-chip Peripheral Drivers" @@ -247,6 +246,11 @@ menu "On-chip Peripheral Drivers" bool "Enable LVGL" default n select PKG_USING_LVGL if BSP_USING_LVGL + select BSP_USING_PDMA if BSP_USING_LVGL + + menuconfig BSP_USING_PDMA + bool "Enable PDMA Driver" + default n menuconfig BSP_USING_GPTMR bool "Enable GPTMR" @@ -286,7 +290,7 @@ menu "On-chip Peripheral Drivers" default y endif - menuconfig BSP_USING_DRAM + menuconfig BSP_USING_FEMC bool "Enable DRAM" default y menuconfig INIT_EXT_RAM_FOR_DATA @@ -373,6 +377,36 @@ menu "On-chip Peripheral Drivers" bool "Enable CAN3" default n endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif + endmenu diff --git a/bsp/hpmicro/hpm6750evk/board/SConscript b/bsp/hpmicro/hpm6750evk/board/SConscript index 9837cef2fc..b0557f0945 100644 --- a/bsp/hpmicro/hpm6750evk/board/SConscript +++ b/bsp/hpmicro/hpm6750evk/board/SConscript @@ -10,7 +10,6 @@ src = Split(""" eth_phy_port.c fal_flash_port.c hpm_sgtl5000.c - trap_gcc.S """) CPPPATH = [cwd] diff --git a/bsp/hpmicro/hpm6750evk/board/board.c b/bsp/hpmicro/hpm6750evk/board/board.c index 8b0de6ffd8..1a67040346 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.c +++ b/bsp/hpmicro/hpm6750evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -11,7 +11,7 @@ #include "hpm_i2c_drv.h" #include "hpm_gpio_drv.h" #include "hpm_debug_console.h" -#include "hpm_dram_drv.h" +#include "hpm_femc_drv.h" #include "pinmux.h" #include "hpm_pmp_drv.h" #include "assert.h" @@ -21,6 +21,8 @@ #include "hpm_pwm_drv.h" #include "hpm_trgm_drv.h" #include "hpm_pllctl_drv.h" +#include "hpm_enet_drv.h" +#include "hpm_pcfg_drv.h" static board_timer_cb timer_cb; @@ -87,7 +89,7 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; /* Configure the UART clock to 24MHz */ @@ -115,28 +117,29 @@ void board_print_clock_freq(void) printf("==============================\n"); printf(" %s clock summary\n", BOARD_NAME); printf("==============================\n"); - printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); - printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1)); - printf("axi0:\t\t %dHz\n", clock_get_frequency(clock_axi0)); - printf("axi1:\t\t %dHz\n", clock_get_frequency(clock_axi1)); - printf("axi2:\t\t %dHz\n", clock_get_frequency(clock_axi2)); - printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb)); - printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); - printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1)); - printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); - printf("xpi1:\t\t %dHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %dHz\n", clock_get_frequency(clock_dram)); - printf("display:\t %dHz\n", clock_get_frequency(clock_display)); - printf("cam0:\t\t %dHz\n", clock_get_frequency(clock_camera0)); - printf("cam1:\t\t %dHz\n", clock_get_frequency(clock_camera1)); - printf("jpeg:\t\t %dHz\n", clock_get_frequency(clock_jpeg)); - printf("pdma:\t\t %dHz\n", clock_get_frequency(clock_pdma)); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); + printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0)); + printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1)); + printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); + printf("display:\t %luHz\n", clock_get_frequency(clock_display)); + printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); + printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); + printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); + printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); printf("==============================\n"); } void board_init_uart(UART_Type *ptr) { init_uart_pins(ptr); + board_init_uart_clock(ptr); } void board_init_ahb(void) @@ -198,12 +201,12 @@ void board_init_sdram_pins(void) init_sdram_pins(); } -uint32_t board_init_dram_clock(void) +uint32_t board_init_femc_clock(void) { - clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ - /* clock_set_source_divider(clock_dram, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ + /* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ - return clock_get_frequency(clock_dram); + return clock_get_frequency(clock_femc); } void board_power_cycle_lcd(void) @@ -233,6 +236,28 @@ void board_init_lcd(void) board_power_cycle_lcd(); } +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + + config->resolution_x = BOARD_LCD_WIDTH; + config->resolution_y = BOARD_LCD_HEIGHT; + + config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; + config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; + config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; + + config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; + config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; + config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; + + config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; + config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; + config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; + config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; + config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; +} + void board_delay_ms(uint32_t ms) { clock_cpu_delay_ms(ms); @@ -325,22 +350,52 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_uart_clock(UART_Type *ptr) { - uint32_t freq = 0U; + uint32_t freq = 0; + clock_name_t clock_name = clock_uart0; + bool need_init_clock = true; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart0); + clock_name = clock_uart0; + } else if (ptr == HPM_UART1) { + clock_name = clock_uart1; + } else if (ptr == HPM_UART2) { + clock_name = clock_uart2; + } else if (ptr == HPM_UART3) { + clock_name = clock_uart3; + } else if (ptr == HPM_UART4) { + clock_name = clock_uart4; + } else if (ptr == HPM_UART5) { + clock_name = clock_uart5; } else if (ptr == HPM_UART6) { - clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart6); + clock_name = clock_uart6; + } else if (ptr == HPM_UART7) { + clock_name = clock_uart7; + } else if (ptr == HPM_UART8) { + clock_name = clock_uart8; + } else if (ptr == HPM_UART9) { + clock_name = clock_uart9; + } else if (ptr == HPM_UART10) { + clock_name = clock_uart10; + } else if (ptr == HPM_UART11) { + clock_name = clock_uart11; + } else if (ptr == HPM_UART12) { + clock_name = clock_uart12; } else if (ptr == HPM_UART13) { - clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart13); + clock_name = clock_uart13; } else if (ptr == HPM_UART14) { - clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart14); + clock_name = clock_uart14; + } else if (ptr == HPM_UART15) { + clock_name = clock_uart15; } else { - /* Not supported */ + /* Unsupported instance */ + need_init_clock = false; } + + if (need_init_clock) { + clock_set_source_divider(clock_name, clk_src_osc24m, 1); + clock_add_to_group(clock_name, 0); + freq = clock_get_frequency(clock_name); + } + return freq; } @@ -482,7 +537,7 @@ void board_init_clock(void) clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); clock_add_to_group(clock_gptmr0, 0); @@ -494,10 +549,6 @@ void board_init_clock(void) clock_add_to_group(clock_gptmr6, 0); clock_add_to_group(clock_gptmr7, 0); clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); - clock_add_to_group(clock_uart13, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -543,6 +594,7 @@ void board_init_clock(void) clock_add_to_group(clock_msyn, 0); clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_lmm1, 0); + clock_add_to_group(clock_pdm, 0); clock_add_to_group(clock_adc0, 0); clock_add_to_group(clock_adc1, 0); @@ -553,23 +605,30 @@ void board_init_clock(void) clock_add_to_group(clock_i2s1, 0); clock_add_to_group(clock_i2s2, 0); clock_add_to_group(clock_i2s3, 0); + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); /* Add the CPU1 clock to Group1 */ clock_add_to_group(clock_mchtmr1, 1); clock_add_to_group(clock_mbx1, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); - /* Connect Group0 to CPU0 */ - clock_connect_group_to_cpu(0, 0); + /* Bump up DCDC voltage to 1200mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1200); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); - while(1); + while (1) { + } } clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); /* Connect Group1 to CPU1 */ clock_connect_group_to_cpu(1, 1); + + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ } uint32_t board_init_cam_clock(CAM_Type *ptr) @@ -760,23 +819,24 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) */ void _init_ext_ram(void) { - uint32_t dram_clk_in_hz; + uint32_t femc_clk_in_hz; + clock_add_to_group(clock_femc, 0); board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); + femc_clk_in_hz = board_init_femc_clock(); - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); + femc_default_config(HPM_FEMC, &config); + config.dqs = FEMC_DQS_INTERNAL; + femc_init(HPM_FEMC, &config); - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.precharge_to_act_in_ns = 18; /* Trp */ sdram_config.act_to_rw_in_ns = 18; /* Trcd */ @@ -789,7 +849,7 @@ void _init_ext_ram(void) sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ sdram_config.act_to_act_in_ns = 12; /* Trrd */ sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED; sdram_config.cs = BOARD_SDRAM_CS; sdram_config.base_address = BOARD_SDRAM_ADDRESS; @@ -800,13 +860,19 @@ void _init_ext_ram(void) sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; sdram_config.delay_cell_value = 29; - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } void board_init_sd_pins(SDXC_Type *ptr) { init_sdxc_pins(ptr, false); + init_sdxc_card_detection_pin(ptr); +} + +void board_sd_power_switch(SDXC_Type *ptr, bool on_off) +{ + /* This feature is not supported on current board */ } @@ -818,6 +884,7 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) break; } clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + sdxc_enable_inverse_clock(ptr, false); sdxc_enable_sd_clock(ptr, false); /* Configure the clock below 400KHz for the identification state */ if (freq <= 400000UL) { @@ -843,6 +910,7 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) else { clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); } + sdxc_enable_inverse_clock(ptr, true); sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk); } while (false); @@ -1012,11 +1080,11 @@ hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) { if (ptr == HPM_ENET0) { gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); - board_delay_ms(1); + board_delay_ms(BOARD_ENET0_PHY_RST_TIME); gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 1); } else if (ptr == HPM_ENET1) { gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); - board_delay_ms(1); + board_delay_ms(BOARD_ENET1_PHY_RST_TIME); gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); } else { return status_invalid_argument; @@ -1024,3 +1092,8 @@ hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) return status_success; } + +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +{ + return enet_pbl_32; +} diff --git a/bsp/hpmicro/hpm6750evk/board/board.h b/bsp/hpmicro/hpm6750evk/board/board.h index fefeb8352f..9827edf155 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.h +++ b/bsp/hpmicro/hpm6750evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,6 +13,7 @@ #include "hpm_soc.h" #include "hpm_soc_feature.h" #include "pinmux.h" +#include "hpm_lcdc_drv.h" #define BOARD_NAME "hpm6750evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) @@ -50,10 +51,10 @@ #define BOARD_APP_UART_CLK_NAME clock_uart0 #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 #define BOARD_CONSOLE_BASE HPM_UART0 @@ -74,8 +75,8 @@ /* sdram section */ #define BOARD_SDRAM_ADDRESS (0x40000000UL) #define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS #define BOARD_SDRAM_REFRESH_COUNT (8192UL) #define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) @@ -201,11 +202,58 @@ #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* lcd section */ + +/* + * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} + * + * HSPW: Horizontal Synchronization Pulse width + * HBP: Horizontal Back Porch + * HFP: Horizontal Front Porch + * VSPW: Vertical Synchronization Pulse width + * VBP: Vertical Back Porch + * VFP: Vertical Front Porch + * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active + * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active + * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active + * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active + * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active + */ +#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 +#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 +#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 +#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 +#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 +#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 +#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 +#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 +#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 +#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 +#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 + +#if defined(PANEL_TM070RDH13) + #ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH (800) +#define BOARD_LCD_WIDTH 800 #endif #ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT (480) +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + +#else + +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH 800 +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + #endif /* pdma section */ @@ -222,19 +270,33 @@ #define BOARD_ENET0_RST_GPIO HPM_GPIO0 #define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF #define BOARD_ENET0_RST_GPIO_PIN (0U) -#define BOARD_ENET0_INF enet_inf_rgmii -#define BOARD_ENET0 HPM_ENET0 -#define BOARD_ENET0_TX_DLY (0U) -#define BOARD_ENET0_RX_DLY (21U) -#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (21U) +#endif +#if __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif #define BOARD_ENET1_RST_GPIO HPM_GPIO0 #define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE #define BOARD_ENET1_RST_GPIO_PIN (26U) -#define BOARD_ENET1_INF enet_inf_rmii -#define BOARD_ENET1 HPM_ENET1 + +#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ #define BOARD_ENET1_INT_REF_CLK (1U) +#define BOARD_ENET1_PHY_RST_TIME (30) + +#if BOARD_ENET1_INF +#define BOARD_ENET1_TX_DLY (0U) +#define BOARD_ENET1_RX_DLY (0U) +#endif + +#if __USE_ENET_PTP #define BOARD_ENET1_PTP_CLOCK (clock_ptp1) +#endif /* ADC section */ #define BOARD_APP_ADC12_NAME "ADC0" @@ -429,10 +491,10 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); - +void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); -uint32_t board_init_dram_clock(void); +uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); @@ -478,6 +540,7 @@ void board_init_sd_pins(SDXC_Type *ptr); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); void board_init_adc12_pins(void); void board_init_adc16_pins(void); @@ -485,8 +548,10 @@ void board_init_adc16_pins(void); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg index c053c1d16d..abaeb2f373 100644 --- a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg @@ -1 +1,50 @@ -riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534 +riscv expose_csrs 262=scounteren +riscv expose_csrs 800=mcountinhibit +riscv expose_csrs 1984=milmb +riscv expose_csrs 1985=mdlmb +riscv expose_csrs 1986=mecc_code +riscv expose_csrs 1987=mnvec +riscv expose_csrs 1988=mxstatus +riscv expose_csrs 1989=mpft_ctl +riscv expose_csrs 1990=mhsp_ctl +riscv expose_csrs 1991=msp_bound +riscv expose_csrs 1992=msp_base +riscv expose_csrs 1993=mdcause +riscv expose_csrs 1994=mcache_ctl +riscv expose_csrs 1995=mcctlbeginaddr +riscv expose_csrs 1996=mcctlcommand +riscv expose_csrs 1997=mcctldata +riscv expose_csrs 1998=mcounterwen +riscv expose_csrs 1999=mcounterinten +riscv expose_csrs 2000=mmisc_ctl +riscv expose_csrs 2001=mcountermask_m +riscv expose_csrs 2002=mcountermask_s +riscv expose_csrs 2003=mcountermask_u +riscv expose_csrs 2004=mcounterovf +riscv expose_csrs 2005=mslideleg +riscv expose_csrs 2015=mclk_ctl +riscv expose_csrs 2016=dexc2dbg +riscv expose_csrs 2017=ddcause +riscv expose_csrs 2048=uitb +riscv expose_csrs 2049=ucode +riscv expose_csrs 2057=udcause +riscv expose_csrs 2059=ucctlbeginaddr +riscv expose_csrs 2060=ucctlcommand +riscv expose_csrs 2500=slie +riscv expose_csrs 2501=slip +riscv expose_csrs 2505=sdcause +riscv expose_csrs 2509=scctldata +riscv expose_csrs 2511=scounterinten +riscv expose_csrs 2513=scountermask_m +riscv expose_csrs 2514=scountermask_s +riscv expose_csrs 2515=scountermask_u +riscv expose_csrs 2516=scounterovf +riscv expose_csrs 2528=scountinhibit +riscv expose_csrs 2531=shpmevent3 +riscv expose_csrs 2532=shpmevent4 +riscv expose_csrs 2533=shpmevent5 +riscv expose_csrs 2534=shpmevent6 +riscv expose_csrs 4032=micm_cfg +riscv expose_csrs 4033=mdcm_cfg +riscv expose_csrs 4034=mmsc_cfg +riscv expose_csrs 4035=mmsc_cfg2 diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg index 3a0460204f..601b680951 100644 --- a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -1,5 +1,7 @@ # Copyright 2021 hpmicro # SPDX-License-Identifier: BSD-3-Clause +# + set _CHIP hpm6750 set _CPUTAPID 0x1000563D @@ -12,27 +14,48 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -set _TARGET1 $_CHIP.cpu1 -target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +proc dmi_write {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc dmi_read {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc dmi_write_memory {addr value} { + dmi_write 0x39 ${addr} + dmi_write 0x3C ${value} +} + +proc dmi_read_memory {addr} { + set sbcs [expr 0x100000 | [dmi_read 0x38]] + dmi_write 0x38 ${sbcs} + dmi_write 0x39 ${addr} + set value [dmi_read 0x3C] + return ${value} +} proc release_core1 {} { # set start point for core1 - $::_TARGET0 riscv dmi_write 0x39 0xF4002C08 - $::_TARGET0 riscv dmi_write 0x3C 0x20016284 + dmi_write_memory 0xF4002C08 0x20016284 # set boot flag for core1 - $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C - $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9 + dmi_write_memory 0xF4002C0C 0xC1BEF1A9 # release core1 - $::_TARGET0 riscv dmi_write 0x39 0xF4002C00 - $::_TARGET0 riscv dmi_write 0x3C 0x1000 + dmi_write_memory 0xF4002C00 0x1000 } -$_TARGET1 configure -event reset-deassert-pre release_core1 -$_TARGET1 configure -event examine-start release_core1 -$_TARGET1 configure -event examine-end { - $::_TARGET1 arp_examine +$_TARGET0 configure -event examine-end { + release_core1 +} + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET1 arp_poll + release_core1 } -$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0 diff --git a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c index 6a096ddef5..6df7441742 100644 --- a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c +++ b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c @@ -101,14 +101,14 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr return PHY_STATUS_OK; } -static rt_ssize_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) { *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); return size; } -static rt_ssize_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) { enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); @@ -170,13 +170,14 @@ static void phy_poll_status(void *parameter) { int ret; phy_info_t phy_info; - rt_uint32_t status; + rt_bool_t status; rt_device_t dev; rt_phy_msg_t msg; rt_uint32_t speed, duplex; phy_device_t *phy_dev; struct eth_device* eth_dev; char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; + enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; @@ -207,6 +208,8 @@ static void phy_poll_status(void *parameter) { LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); + enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); } } } @@ -272,7 +275,7 @@ static void phy_monitor_thread_entry(void *args) int phy_device_register(void) { - rt_err_t err = -RT_ERROR; + rt_err_t err = RT_ERROR; rt_thread_t thread_phy_monitor; /* Set ops for PHY */ @@ -308,7 +311,7 @@ int phy_device_register(void) } else { - err = -RT_ERROR; + err = RT_ERROR; } return err; diff --git a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h index ae756ff551..8632952660 100644 --- a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h +++ b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h @@ -156,6 +156,3 @@ typedef struct { #endif #endif - - - diff --git a/bsp/hpmicro/hpm6750evk/board/fal_cfg.h b/bsp/hpmicro/hpm6750evk/board/fal_cfg.h index 80818b24e7..b315dd87c3 100644 --- a/bsp/hpmicro/hpm6750evk/board/fal_cfg.h +++ b/bsp/hpmicro/hpm6750evk/board/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -32,7 +32,8 @@ extern struct fal_flash_dev nor_flash0; { \ {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 9*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c index a664b13fa8..12d5b3daa4 100644 --- a/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c +++ b/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -20,18 +20,19 @@ #if defined(FLASH_XIP) && (FLASH_XIP == 1) +static rt_base_t s_interrupt_level; #define FAL_ENTER_CRITICAL() do {\ rt_enter_critical();\ - disable_irq_from_intc();\ fencei();\ - }while(0) + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) #define FAL_EXIT_CRITICAL() do {\ ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ fencei();\ rt_exit_critical();\ - enable_irq_from_intc();\ - }while(0) + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) #define FAL_RAMFUNC __attribute__((section(".isr_vector"))) diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld index 256c8eddd9..0d29b2257e 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld @@ -1,24 +1,26 @@ /* - * Copyright 2021 - 2022 hpmicro + * Copyright 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0, LENGTH = 256K DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -57,29 +59,33 @@ SECTIONS __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + .fast : AT(etext + __data_end__ - __tdata_start__) { . = ALIGN(8); __ramfunc_start__ = .; *(.fast) /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*cpuport.o (.text .text* .rodata .rodata*)) - KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) KEEP(*irq.o (.text .text* .rodata .rodata*)) KEEP(*clock.o (.text .text* .rodata .rodata*)) KEEP(*kservice.o (.text .text* .rodata .rodata*)) KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) KEEP(*idle.o (.text .text* .rodata .rodata*)) KEEP(*ipc.o (.text .text* .rodata .rodata*)) KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) KEEP(*timer.o (.text .text* .rodata .rodata*)) KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + . = ALIGN(8); __ramfunc_end__ = .; } > AXI_SRAM @@ -145,7 +151,46 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); - .data : AT(etext) { + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -153,8 +198,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -181,10 +224,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -196,61 +241,64 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > SDRAM - __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; - - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .bss : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.tbss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.tcommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; - .heap : { + .heap(NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; __heap_end__ = .; - } > SDRAM + } > AXI_SRAM .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); - } > SDRAM + } > AXI_SRAM - .stack : { + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; . = ALIGN(8); PROVIDE (_stack = .); - PROVIDE( __rt_rvstack = . ); PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld index 915330acb9..e98a75c121 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld @@ -1,24 +1,26 @@ /* - * Copyright 2021 - 2022 hpmicro + * Copyright 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0, LENGTH = 256K DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -57,34 +59,59 @@ SECTIONS __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + .fast : AT(etext + __data_end__ - __tdata_start__) { . = ALIGN(8); __ramfunc_start__ = .; *(.fast) /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*cpuport.o (.text .text* .rodata .rodata*)) - KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) KEEP(*irq.o (.text .text* .rodata .rodata*)) KEEP(*clock.o (.text .text* .rodata .rodata*)) KEEP(*kservice.o (.text .text* .rodata .rodata*)) KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) KEEP(*idle.o (.text .text* .rodata .rodata*)) KEEP(*ipc.o (.text .text* .rodata .rodata*)) KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) KEEP(*timer.o (.text .text* .rodata .rodata*)) KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*ip*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + . = ALIGN(8); __ramfunc_end__ = .; } > AXI_SRAM + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { . = ALIGN(8); *(.text) @@ -146,7 +173,42 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); - .data : AT(etext) { + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -154,8 +216,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -182,10 +242,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -197,60 +259,64 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > SDRAM - __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; - - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .bss : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.tbss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.tcommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; - .heap : { + .heap(NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; __heap_end__ = .; - } > SDRAM + } > AXI_SRAM .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); - } > SDRAM + } > AXI_SRAM - .stack : { + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld similarity index 75% rename from bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld rename to bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld index 915330acb9..ed0fce209d 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021 - 2022 hpmicro + * Copyright 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,16 +9,18 @@ STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0, LENGTH = 256K DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -57,29 +59,32 @@ SECTIONS __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + .fast : AT(etext + __data_end__ - __tdata_start__) { . = ALIGN(8); __ramfunc_start__ = .; *(.fast) /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*cpuport.o (.text .text* .rodata .rodata*)) - KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) KEEP(*irq.o (.text .text* .rodata .rodata*)) KEEP(*clock.o (.text .text* .rodata .rodata*)) KEEP(*kservice.o (.text .text* .rodata .rodata*)) KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) KEEP(*idle.o (.text .text* .rodata .rodata*)) KEEP(*ipc.o (.text .text* .rodata .rodata*)) KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) KEEP(*timer.o (.text .text* .rodata .rodata*)) KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) - KEEP(*drv_*.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) . = ALIGN(8); __ramfunc_end__ = .; @@ -146,7 +151,45 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); - .data : AT(etext) { + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -154,8 +197,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -182,10 +223,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -197,39 +240,36 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > SDRAM - __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .bss : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.tbss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.tcommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM - .heap : { + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + + .heap(NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; @@ -242,15 +282,16 @@ SECTIONS . = ALIGN(8); } > SDRAM - .stack : { + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); } diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld index 4b63b46ca6..c3c0f2cf4e 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld @@ -1,30 +1,33 @@ /* - * Copyright 2021 - 2022 hpmicro + * Copyright 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; MEMORY { ILM (wx) : ORIGIN = 0, LENGTH = 256K DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - /* It's alias address of core0 ILM+DLM, but accessing via system bus */ - CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K - /* It's alias address of core1 ILM+DLM, but accessing via system bus */ - CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } SECTIONS { + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) @@ -32,11 +35,6 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > AXI_SRAM - .text : { . = ALIGN(8); *(.text) @@ -98,8 +96,46 @@ SECTIONS KEEP(*(.rel*)) } > AXI_SRAM + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM - .data : AT(etext) { + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -107,15 +143,13 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) KEEP(*(.got*)) KEEP(*(.got)) - KEEP(*(.gcc_execpt_table)) - KEEP(*(.gcc_execpt_table.*)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) . = ALIGN(8); PROVIDE(__preinit_array_start = .); @@ -135,10 +169,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -153,62 +189,71 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __data_start__) { + .fast : AT(etext + __data_end__ - __tdata_start__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > NONCACHEABLE - __noncacheable_start__ = ORIGIN(NONCACHEABLE); - __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE); + } > NONCACHEABLE_RAM - .bss : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.tbss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.tcommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) } > DLM - .stack : { + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); } > DLM .framebuffer (NOLOAD) : { KEEP(*(.framebuffer)) - } > SDRAM + } > AXI_SRAM - .heap : { + .heap (NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; __heap_end__ = .; + } > AXI_SRAM + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld new file mode 100644 index 0000000000..dedb377ad3 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld @@ -0,0 +1,252 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.c b/bsp/hpmicro/hpm6750evk/board/pinmux.c index 0ad35b7570..67ff6a39b3 100644 --- a/bsp/hpmicro/hpm6750evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.c @@ -1,10 +1,18 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ + #include "board.h" void init_uart_pins(UART_Type *ptr) @@ -12,14 +20,16 @@ void init_uart_pins(UART_Type *ptr) if (ptr == HPM_UART0) { HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; } else if (ptr == HPM_UART13) { HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; + /* PZ port IO needs to configure BIOC as well */ HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; } @@ -83,11 +93,13 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) if (ptr == HPM_I2C0) { /* I2C0 */ HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_GPIO_Z_11; - HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_GPIO_Z_10; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; } else { - while(1); + while (1) { + } } } @@ -98,12 +110,14 @@ void init_i2c_pins(I2C_Type *ptr) | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + /* PZ port IO needs to configure BIOC as well */ HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - while(1); + while (1) { + } } } @@ -239,16 +253,18 @@ void init_i2s_pins(I2S_Type *ptr) void init_dao_pins(void) { HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P; - HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08; HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08; HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09; } void init_pdm_pins(void) { HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; } @@ -260,10 +276,10 @@ void init_vad_pins(void) void init_cam_pins(void) { -#ifdef CAMREA_RESET_PWDN_CONFIGURABLE - HPM_IOC->PAD[IOC_PAD_PX08].FUNC_CTL = IOC_PX08_FUNC_CTL_GPIO_X_08; - HPM_IOC->PAD[IOC_PAD_PX09].FUNC_CTL = IOC_PX09_FUNC_CTL_GPIO_X_09; -#endif + /* configure rst pin function */ + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_PY_05; HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; @@ -401,9 +417,9 @@ void init_can_pins(CAN_Type *ptr) } } -void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8) +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) { - uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);; + uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); @@ -435,10 +451,27 @@ void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8) HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl; HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN; - } } +void init_sdxc_power_pin(SDXC_Type *ptr) +{ + /* Not supported by current board */ +} +void init_sdxc_vsel_pin(SDXC_Type *ptr) +{ + /* Not suppored by current board */ +} + +void init_sdxc_card_detection_pin(SDXC_Type *ptr) +{ + /* CDN */ + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; + HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN; +} + void init_clk_obs_pins(void) { HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.h b/bsp/hpmicro/hpm6750evk/board/pinmux.h index faa0a72c1d..52c97a9b9a 100644 --- a/bsp/hpmicro/hpm6750evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -35,6 +35,9 @@ void init_adc12_pins(void); void init_adc16_pins(void); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); +void init_sdxc_power_pin(SDXC_Type *ptr); +void init_sdxc_vsel_pin(SDXC_Type *ptr); +void init_sdxc_card_detection_pin(SDXC_Type *ptr); void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.c b/bsp/hpmicro/hpm6750evk/board/rtt_board.c index f16cd34489..2fa9cf7aab 100644 --- a/bsp/hpmicro/hpm6750evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.c @@ -107,6 +107,11 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) rt_interrupt_leave(); } +void rt_hw_us_delay(rt_uint32_t us) +{ + clock_cpu_delay_us(us); +} + void rt_hw_cpu_reset(void) { HPM_PPOR->RESET_ENABLE = (1UL << 31); diff --git a/bsp/hpmicro/hpm6750evk/board/trap_gcc.S b/bsp/hpmicro/hpm6750evk/board/trap_gcc.S deleted file mode 100644 index 40de7b31c5..0000000000 --- a/bsp/hpmicro/hpm6750evk/board/trap_gcc.S +++ /dev/null @@ -1,12 +0,0 @@ -#include "cpuport.h" - - .globl rt_hw_do_after_save_above - .type rt_hw_do_after_save_above,@function -rt_hw_do_after_save_above: - addi sp, sp, -4 - STORE ra, 0 * REGBYTES(sp) - csrr a0, mscratch - call trap_entry - LOAD ra, 0 * REGBYTES(sp) - addi sp, sp, 4 - ret \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/figures/board.png b/bsp/hpmicro/hpm6750evk/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..f3884496b1b48e836f6abb802a61440f92c79f62 GIT binary patch literal 69601 zcmV*#KsvvPP)T1LHfkbA$coFf;z5n~a_uVJiwk^1-NJsz(n!f&#FOnoReHKDA zdTixi5E4zFuezeCe!YJs0c&0%HQ%RoTvqNUHMd{CzgX|?*BM{Y+kuPN}HX>O0}&gf!{X$_+8RT z-yH$SIxPA1tm1Xq@KrXoxR%L#{q`EQTA#C}-=*uY=q;?gkk)(4Yxl$I-`7DpH#~kV zHhQaVzslAZH;8=JK^kxS`M&S4=#5olZ6GDCUayjL)5gD9Zk8W8jW5J%8~=yLGFr!m zT*WGjHIcx&`k}>-z1nXr-H@%m9;@C!3gX5@`YK$qj%Hu=-mB`1Ya*RhdR4kH%_?2j z_LitFkVn;QRSxmkV`76032^}lZs%sT$% zb?dET3|+@&7jIM2uF_O>az(JF?Jfz{Q`OC%#SIGjRo_e3vP>&FNc{EmTq}FMo%HhYLHO5W!PgBK zxZdwv$A%VfcYvC0d|6zxzgzDkR{g&A_v`I}5Ms^YzeXH@_yJwmEs=ZD+Cy_wb^rXkr{kL>y>x9hykVnDygku>o!=X_rC8g~z3MvY+6aVoxCbHL z)?=-zD4eSMNe+77J1q@e8^THJZJTR_N)k7QK-P==Z24JSCq!?xS3#^vF04dgN;j}9 z-T}h-zBl@t@%~MX{{vVoV{zTzY^!iXZP@1WcihI!@`I}K1**8Njr#p5$6EKRxB7LZ zRhnbH_F7o!b!@#>(^^{3D{#HN@B-PhtJXpKZ$vBlScL{bZv&=Tk%32_~&Zt#BBi+@B7u7$n5-oE$NP;Y7N z_Qbj|^ez5h@3VY^HuU-#YSs&mm)AD!TL;R~SALi3&C4LW*9*&XEBf3P9NR)^h<1T+ z9AsbIZRcw3T-T(+K~kbPR{p9dl@X59_7|wj5#MtpEWV4iR+pO^{|AY#5o?<%*P0RHI=0>_!$#cH_CMT{NCK&8 zTW*VOEZ)24T1%p@b~>~~fXQo1_SKrb1xd7ME_q$+Nm|?XYk5G?vOiy1$4|a0@@y4C zsELvE^ZwWf5CR$f=~ttl+T^=$Ko|Gc$7 zu06k`_2L{_`dJohn(|jsDb4*VU2kuI)QW^yXZ%|bObgfXJzqBO1gMLf8vh5#Hj~#F z;cL4fn{EB|Hy+%um(i7s^HcTr!>oiz>PZP-QbatHj=QR}uj_um8 zima@SqrH!oZ8v?bDoTrHmYP2|B(U4QVHj&af6I&d{r;xwtGa93n}$g-zks1-iKarB zhJjICKv5#7ff6-s39D8n(k5ZlG^*t}!f}D)2=vMVitNK5N}`u$T`C}4!8A8{lXrb&#rlS(dtUah9P&n<-eKLSSxEX#63 zSrrK(9IxFKv1B_=)BS|wVA+=Yj^b+BAiU>ukN{Pc85!Qh&Ru&6ha=xN^Xwfg{CCFw zo2JS1^dy(Y&r{W_*g_zLgK1jcfZI(ST%QQ_0T+&gEX#mIrJ`e0^{X_#KoaiX^?|AH zKoE}8koZD?(-=TELvB3*kr3{EOxs$K>|$l=NOdG(yYH^bZhfulGUrI(AW&5m5EzDq zW0~0AL`9O2goEYX-!|0^!Im@Tgp=^RInw9 z{kQMr<=2h_uzkw_)6?@*DsF%5+Bw9rV`s5Y*u7(vQzyp(2u1yj40Utz>=XcdcMNm( z!ey$KLnIVnbRf;qGgk;>u;;d2oH}!fO4TBriqq4T;?y~}oth=;l!rG=auXLJtL`6` zA+Cws6z_Ujk@5Q_VgUt&K&zTqLgtR!_VFKo@juhsH}Kvffp@;}-+s}wGXMOQzvYFO zUPjY2RH+7zLrE7HLPnBR7aU1-sOTN7GL0tk)3NNP&q8vj=-Mj6)i4|s<@)2@-#5(S{4}-dN*gCnoTF5- zDeF3r!7^=1Ws`8s&r9Ea6G?Ri$c3{L*p5I}-Tpjw>};cr6Q?gBdp)UZCdUq+Me(%g zTZc~(iNye@=rs-{OXpIKZP1 zJjfsYIma_#}(lb`5d-*a=jh#wR~=A5T5~62(%9&P0&5c#xxq zkDzwRJaG3mzWAlDlP~1iz2iZa7PGv0q(FC92k*cCUjE?pDT-Q+pa0p%CBum z@GHOhGKY^GVrF)d(UEQMB})uQ@4m*bXeAE4^*Y@Nh5z&)-bXy-g_c?=w%wBCKmT$E zzw)d9%*BNpC;prpprc1OZDKLIK(UbjuDr*5W**ZrDV2&OlZmF^HgDR@jvWC{;5aSh z&Q+$7_X3y4$NAeY{o@VY*BA72_r3ek^K%?Hc$!oy$;UqaVgB)-p8|^9e&;>_&W}$q zIMm07KJz86rxsxMR13*5JVgwF0B%5xe-_aVzs ztSY2BgM9G)yZP^5Ji4Yv7FV<6j%Ul;c4N3Bu_*C)g3N5D!6k$vAwKen&+yzgpXSuD zqn<`mdHf?EWoTrCfBfseqFiz}qWFD248uT@71V$aY=L1Km^HHr;ha5tj@(k7=bn9r zPkrhWgu`KvjSn@|TfLwB>c}t2^~Vc=BOFx8#IaosC+hA8?>~jQZCRz1Un1;NF--#@ zY*bkg@~dutNDi{(_KPeD{HnmV3{*uy5;kE~#;;092pq>jm1R^#!ZJ;4%R*6HPQt2c z1XP89Pr{GE9fLleSr(|O#J*d$arE>!oA=zoD=)p!^j?zp+>;ZRn4GwTBuU(U*L~de zzJ~!=oS#RLWI`S!U&<{IjVB04BP?VxMB)k0dr_mNX@sLu0E&5c6H$9t5BXdc+p-9R zA|OeWiv@hDJ9Ukkfh`;qRV5q_qm@e3Y83*Zs7JC{1cMQ(dc_r_K0lpZom8tDQ&X2v zEfrZ&8{Qys6-zI!A`=^^7P~zB5!kZ2aYis4OkabL!Y}RMl;xw|{`2{`dbIANll;@yXAAo?rasU*qS0@&DkK zTkl-wAtb7L^%^d%8xgls6I8yjO9aW7pS?Rb(w2zh_bYtxvHR%nYRB(a*|TeuJ-2Kj z7L5>(hxyFM9-+N0NzkY8=}&%;(V-0_<6%aIH}J`ie~@G%K_ndF(;t679qkDMewBOo z-^T5?Zl|*&Mc60UHW(ouix3J1iFfrevT+l={rxxeyocU6z~xJ0jE;^nKR3n23#UmW z<1FRpnVp$L!e;O7x0A_S=KSenY}vL2pCXvKatVM6pz6%(EHFI!Ln8 zMCiVEX#acQ&XW}%vZ7F}x!PO_#&8fg$f)Fy&{@uv!LFkC!w4iC$95&Dr{N_GJtIE&*^k?xaAyl72wW?tlCZSNM zB|xBs91zX+$^Alk%)rPXJ9h7(QZ8YcCUf&;vdb0H z?S2;L7kTZ_NlGRZmkXRZJ;~H`mUJq`_{C{neDyd&_A@;-!_(jV7Ugo0!g7V9M^E$m z!6PJ-Nyg5cS$8c7gL}PIF;m2E`ZV%-KnvIcXpiKNA-&aq!I}ym|aA$Ip!6 z^QqXjjjXs+Cm0T+YdT00ju6ORzd5#`yQdeQPbJ{@lWI?+>t(XDv-nh%YPp0YWc;ea zhW-JjCNAOg2l1&gw&M^Cxrj^Gx_Bl zlC08^?qB67@_}<0 zwt~yPN;icL|S4vz5bGtcqT3o@l*iSEGxhWiJR zZJBIlp&@~bC3m;m+|&f|Xq1{>Vf_4A67evo@fEj+&&S4*P1N)nAkot|z;n;P$frN` zv3J}jisaBPXK7EY&+e9s72bID6#{-gmun07Bn#8FS;`mrli&M8uFSh==IO6JK`vjy z7J{*h6MX$2zf8?E5R$`}{_0Cy$rS-OdgKW6lkWZU`8;3whc8ns8OXqEuN)v25cvIm zmU0UmdG&cZ5(*RZCeJ_hRZL$L%W>%KXlG<(lt?UwVbl-;e11Q#9(Wm_;+ia_a@if9 zR083cB-`4^1G&XnQmGUl|MX`#cls3Rc2rP@1aZ%;M)VQyxIYSn$t zU?_wn%Se*z0qN=KZ$R$+a*l;;7FCvA7(X$ABcvwNOG2hvt8(eWg{u&!J0Gr0%`i4L zfg(X77N=OMU^zCq#pSE!^7?#&<4Anvn@1SzPjTOV@TnQFi)fVsPds&oZyuOr-`>&h zn{Ds!T9(~Pxq@jLIChP{{oCK?@Uclg{OArIdwd_Ea1bE`g{2Z-{-@`8;-&Mv|6`va zl}h3FyJSvJZx5kxl(VN#5{X1meLgCs3eSA~U&t-x*s*;lK~W|W4x=b4namt>i+TLf z6tm-Fn3ltGu|PbL^aO{Wa41ZvtP_ugDQj*VfIk?eGu@6PY!(*_^mVs0HJ71SEP9Jn z@c;ckzsmVDr+NS5AE3LtkLRC#f=3>GbWKuf6=~C$ETWcxLhy)ZyMh7@`VTQhrFk43l$mTUvyTWZ<29a2h|Nf23 zM8g3deBgdAPR+CDuKQ6vP2V>#K&eoqv$u!p(i}ok(6thUF(?23xE2D$cjofJBw+U^z`(zm|MiqHG2Dp0GPTw;dPtc=-1A!E`p&jlN0W{ zZP~tqvu94z6u42}#p%U=s2TRqL%0Eu{SVHgW=6PiMI8! zRMvU%`R5wrXBrl&>I%4Ot>$?PR8K+39%m%8Z%02nH>JqTml+$M=G^51jwEy6otycu zzwrkIBi*Z!;i~=r-**8#*Dt!J^Iv}DS2=U$6p}1aDi_i93c1AvUVq~PLxUYymdUvb z(@ZaF9;7Q14n?U|4P;58n2$8s#q*h2qLBoKQKMKW^4ftH85!y!7!0FpWtNtTT%MX` z+wMKciUiimpaAsswDa(T5Ac<*J;P&<+{^gnEJshArd%p;&mBA1vUxLK{Of<5ReCqL0Ua|}X4bLq zWzS2og-mtOozczPshgYecpJU_17y!!L=8oWw{xw5O0HDCBZXO^h=$GecD?uy4;T^bd|OFgVJq2M%!Hz{_mky@%!bIcl{knr0A; z20h8Fkcft;R9s2jH#oqq+wUQ_xWu7X4-irRr}&S*^nVkK zM)}lF{0#Y}JYV?JKk_uZvqm5R*ha01MQ+3`)Y)Y(bj%(q zsa48ox<C z`tCaS|GxeWJpRaibofoQ>}dpoaJ&mSG0eHCMQVny*s z5=tBi`Psj-n_{_!VL2$0ARcq);R6re%kDcrg)fwH``F_|BuRWP75=-R@vjOruP^#~ z$yaKO&lYhUXC<&kl8`05@K70D)3I$E!!$T~^a#^aSLh!aq<3HgJw3f>nubv`5Vpkp z{5<7~&at-+lFygi34WC*wH*@(qE&Pf@hCHy1(LBim8!;4zQ8xX@pbAmD7&~sG!i72 zFQA5_j9(n1Qr1@xLtj7l+w-8rB(6^0H38Y;gI~89Gu4N=1z`$4}Eg*ypx?WrjQV-vdBMlv$Xc zV|ZjE0O4?qc-(!SSiFtl;Sm;>mRMd|!ZfOkT^M6|DMwY;@CW=13=GiL?#6)}eB<>S zdjGN|`06(fQ>)den9eFwtXkDMcWIW(m&Q1I_B0(GX|`_nF+3Ebs8{*cv)?2X4D#8J ze}G^7`JY6U|80}0;Mf*!M6~QV$y`UEqR1$U(m)ihU&@UN)rvFt3>WD}+J=8H{rIc0 z+#+F`CKXL{H)A-W39{xq|7=}SOP*$uTTiZ$B($kXYBht?$B%RJ$Wfy4I4O_#864{8 zmTiMXJa#>sU1EGDi>gT2Mj1sCgaR^~w{GJ2u~S$=X2-5weEfqC@#U{RLuO%#idMli zO*+~;*?Zes9QX68MAr)Rqb{BDGwaJ-P-6-v4?yXu$7hWOOSdn?_vn>hcv{ zd*yXXo(U5UhUo0-X7}DbJpBF-@%k&@=DgLYSASPyM}jjW$JQ+q+PMu@eqpPA)OUl|C!^N z#(J;MN5z|W(^saMzA}x^=O+}2bI1OB=#I;z+k@ycIzGRjV8GArJ$H~wZ@}^PR5(_> zpX_E1M>s24du$7z;stI=?miRY?I*D;6It;gyhzYSto8RGA%=KYG`?s(dg7gz_Vzdr z-nWk@p87VKOpbD~NVQg_x3`x>vW=deev0{Aqy9)=Cz{&E=wLTflVfb%vXxBHAR155 z-qArMmf-cb&Y%VY?78h$WJ%$~vE!stN#e;A7bfNy8W~|=Sa9Lo1#^yC$udE!Y7+i+2qQr^coMemmsL~?N7yT8#YwIdYy)K$N&o;L z07*naR79*b{O1nQXozjwHgW0V6jr5x?buWuf$f+K4iA#A$rKDXW;>pCgG){xJiuhTT8{jfrH#?93d6QW=o2EEB&fp(u(A@r8rW z=f5h)U5mxknoYLezGyjfPZlKGQf%3_lYBnUGf#Y@S%UyV$W3R=Ik+2;ve_(u^%sA} zzx!YR0}np@C@+2M`K#{h2`9r9P7B!#JzYCVq&kR3gG86|EG!s=!(n{3LCtWmY?)fs z#58O4_YZ*LBNT5Z81Ug+EMhJd2rD%^zd^KC~^vdpD~|lgDFTWMwdbEGy)_&~4k>_1K!}r*4&=J$0Pg zU1^k{%*^F+Qp0Ak1ig0D7NxRY*5>an)_+%6{kmjqO-B%mConuWh$9?iNp5WO)T))H zHiE$rvZT`A)63^S`9AWy6iT^yo;tqFj0TI#MLN8?9qpYM-o%WC0?cP-IClIT1N~iW z-nNb5p;5+89C9UYK96lXM3e47r3N>0_~0SJa+PAaf=>xDzpy}m{{{e(sWkJm85Bic zw--k@ZQ}Kpo?>X@&Q-r|-MWRhUVD-4Tei4i8&{zQNs_2kv^96yz1@;*OEEOMnKLI( zP%0PSHfdbcDm?YX6MXzLpW@9oUZ+yg)~q)%InK7Nn^`VbDCreYRKOr#$Wtko>D#=6 z^x!6J+oZ6(NXjESmx^Vyifd-Hr8~)ICdn>oly!sNo?hD8QdCMyWV0DAPfnAWynta# z`28xOXo3qD&eGX8471Z-zi#E+xpV7#mh>vO-+2#1n?^|{l6?JZUnZNGzp-^uHy^xS zbQPF#e2fBFeHYEYrmA3%EPffQ9TL zj8dYX%RbKt}tGw^dt?YhaFV*GC9GrZUD=P zyD{`-0>KE$jtxBj(i_MKdb_$9kIyl%p%-BZ4!rmR@o0!tI!-VcC6`;Iq8pS-8iqYi zG#+JR-vG0jIW}z?ArKBgAjxvENJnQkmSr^}1VL#Q#loSdyN6GF_GebvQ2_lLHqifL z|JJqbaPtjhv-7StlVvZXj=n~|d8vt{mR6nKTaWE`zmF$UoH%;e%V!|1+g|IbyNzFE znNw#^@@e0X)7jn4m5u_O_2Az9g2qlEKO@@;x`Vw#Hpiifg~v9U7_RD z<0QPKef2;wMRmE1!HrueT5(E-MKaxsZJC&+jq3NiWVKi)CzRK%v1puhdxCta!vFhU ze}kak-3QQ>PSe@dK|J0@BH7N+U?&4ZJJ_^sR})f^q<2rzzsr97^>vM2DN!@6mCh3@ z5LWe8yxRc|syCsZdiF)k>`^{+|0s!w`<+p(a`4-)@aD@egA9riz!8G>t{zIo3S;Ll z;8SH@U0x&E?l0Yvop<5XAr28FXb8T z@5a^^Q4JrR?L%a9WvaSPwW@RM$YHkb*hMH51~hi>yPfjlG=?Q%sX^vur%9)~IeFqJ zx8A;=7oPhjn>KCc{)ZmofBgBMt$Lq&3bPw6;aGy_Upqo}KFi3)jhs1koPbYdw730+ zuD@mPZT!(6{5I8U6;0D9cx1L=nmCSyt{GUCNp`_SAN7U*eQ)DmFJHYRNmTXb!yoE4 zqE^*c=R5ZrG!>)CFIsn(gn|-Na}s~|)nk0{z78r?foyA-w%?P~GPa{**)j`@3vLD& zMPl2I%}h+r;R{CDf9qY$&(AY)=_1)|7Dotv{D1l>-a2%MNI1qs{t`QH*+ZpLW~o%8 zr*DY6@4cU6M~^ab?i3QP9h^?5X-}t{#ao>%_Tc)8W|o>@W4(mJVK#2r%+a$K$;`~~ z+RHDKU(R0@4%(8tubv4;kx6%^S(I%!*q3Y@c5$-6OOkb+Xn4jePm{4S(+Iqv$(|e+aDy=-hu5{M53;(U90Mp z3T37yXE19uLV+NfrZ=b%)Aao79@4DOSDy-|?KF1z-Fx4C2)o8yW{zki%Jy4sr+07@ z16yw618m)~o4@(OpVQgh!yWtYXJUMka5&^G5Er^X`SpKA zkrm>}I7JU013dlGDP&opzo(yCtwJQ3rfzYB0F^n$2O?w2Kj{rj$SRxuv5)G-}8~pu!&FZ)2lb4#=<(gqMvaFWN#YXPDMk*_hB&!-V zFV(w*BFhaVVL7(Dx4Z$aWh6Zc=qMjDHh8NZQMqFxj!5qI3n3}gESs99;W(m!%vPQ3 zQ}_6Y>m>Ydn0zL_VA~o4-a;KnH+stNdv4>y=*AI#_1FF{zV?lO;?$XQOig81)roqE z859rND?Sy+u^Rz1m2zo4%5;5ZJDEV(4ujokB1(u*M?Y5lq*(Q_Jnd#$0ulSPceS!EalpbGsXU3fIIKG zkAttg=6OA$2uUIo4)U3w_ywZT7{amf`$HUh<4x{;-~D{~@BfBRfA%N%p4lZ zwej)`&rz$@2nIv6ceHWl^chTBqFC0bRGQ~WA{t}Yju02lU-AOJa%|nQ3CEFHSSm7e z#Z5n+Ex7Y;q3ocKPvQtcZmCSEBm7-g`R^HkxG{I0w5DHCYR#4INv3*C^<$5Hh<&%- z#-IMh@AJg7uhQ0@Mz3g?rs<|Mw(EK4y~Gv*LVlGGJa#|vWCxCA^Ob-4SAC+XOYw`!1BvU%FmXTv$XAj+7J%SR5D9BD&BVAYNZUeNh!BLDCj31 zj}eK4NG22Xba%3l%QL@FYj8!1qPVdlih_bdXS$vFY>rf0l4v+YxuOvY28bu(_#~5P z#7`;}C)E}u7>%RrHG)AOirjjXNvq#oYO?vox@VZxy$KP7ZLr=czf#L7zY^=5_4mDU z=e?cMp6=#-k9>fce2s-{4$CqdQEEojz%;BzsIH7eB53jWgDHv?lTuFSQ}_21Q*;hq zHpw~d6bnV-$u`mlx4> z9eG*i@4xt0%+F=`%HRDx)6>)B7Uz+Wn7DX}bEnT@ng&mP{i~cjew+*EP9aGWfBhGK zNg=&l#DW+9qmkAzT#@=g=`~o@@h~xGT6i7Ql4U| zLOd2}ctC?eKP63TxR=|KF*Xl&Fh4U*x+8^AauG`;-ic4P3H*?qK%w3^I%t+`t){+M z0~jpT3S?6nJs;mh@{-4fC)`}+Gc!|+9Xd;SszksEqM8bl5+NE+am$tfh1?Pk-f=JG zvc;i4JcuYt#3BhIU9L?Zj>ZXv69fWYa*2vXy1Sp5nHfS|qjdH5<6q9RVR$nKUU-3> zd+y?umtSV$qPvhI(J0x1PN}fWU=e1g=PBgoQT=`#8#G<#j{W!W=%Wu3^!vyaG~&q= z`9c9nl6n4{Pr3rkLoT~FkFYqu$YM6raMcONAsh9dpG;{-@}t%|0;%QaPHihRVNSG zhIih9X(AyJ4u?==mA<}SQf+MnLm_P2COdlt#n$i(gG#A@s8!g|-ND8!TPW)$wV`1u zTA8`235o@is<-3%XD){SCmG$ik`R6ZU9hw?=Z8ob0pf@(R6c7*X$3M#&4MH%@KO7 zr_ipSaB@WwRh=5;Qi+bG7@z;dPjd3&1Zqs-f-`}Q%X&KkYJM4~S7P??9Ko{6bVhE( zq`LypZk&!*lq=4NQQU$HM=96{gMs{AONubNJL?j$0 z-POaTv2mV#!p#>jJ2S&8FMbQdu&9(Oy!^s*=z5K^R_4_M-==?HkjaS&4!?Pbu?v@2 z%r3Bb%NBn8Cx3=#pM09bZ@u26aT;D2@4k+Aq}8E=uQSl!M@Ls0fuN(Solq!@Bix;E z!f{BorBGxQNs{UA?4(pEAcVru@G#|4g=BjhR<+1tX2uf&P^!3#JLF+%+Y59`hU4hf z8YnWcaG2TY%iOl-7K-H(hmM~{R{Vs*AtI3o?HwsfWetiFp^)DlPgQmK15KyBElOs- zjAIGf+oA-6A(XO?EK9`WaeO`rpQ@k+L$r6MaU6@u@i8R8ABehr(l}|y%Z}_=tKwSR zC{5uW?ovOFOSngM+1AR*QL5@ABdRE2z@jA>cl(GIhUrm-#E!CQw8GJa`{`Wa!D z#xA-$@Px#-o_hv_`xf7N?pc?6l>|>e`2;?{kGt-^i}!!WQf(=sQV9|2BA!TLloyGFLn|Aku2Ghkmw5WAXVLYl zdv>80Qe4wKa(7Vc)D?w(%$&F4qHPc;5@j)NCh?FL(;`c=pP6iLCc9cC(75DU?bKZ`{Oz=bz*9#6)8l>~)5v9v88g%`!AN%*Bfrz5b~m z8rf?5U6mL`l1X=U@_~U%A|J!+LwNQqS}6;132dYKChy z3D~xMCy8W&<>e(zU8h!DAe2nv*cOqXim4Y+WEkDNg=*EHTB~yQ#8Hr(#=HsE`^T^d zhy2vML?JcDqE;%iyqHIpi}Va`q-Ss=wrw&wafzwP%jmj+Pm;)F=1^o6RZ&PKqm)V- z%gYr^+aXt2CRbQ)oLFQSHil8gupA7-!n7QwCa0LmquRD;k6*}>!fRV z+q?PRHH}}teaEar`fe@ zmq#W>kc8t3tx%9;dnfr^7QL)ft>`#!GeG0g*cf-;dmoZdVeIVr>qq`|b#cdCcd_q| zyEu9L1i$y+ev?u$Pb?aLTlWoz0&M8(Ar^P9i-beW%}h~Pb|-SsbLZ-Yi4UmMOk!uF z0>oo3%YV=Qy*Q3QtGS4w9(AedIe-_`T$kVejOah0I)I z0+x#f^l}B$G6@C4UI?wRN=P-254?Wh0Q>L1kBuMM#D%lxSXfw~s_7sJ6h$SLh||;C z%Z^>Q(AC|`#S8yGcW)LXOMadA{c@|S%*x7IdtdLq&vIwM0D~D|01zNZkOU<%KuZc) zj<7A-e({4}9CFxxQP>QdAq7cW7EQ|xlcFgalu2;GN(?ZA!EAT#zV}^v@2c+FE4Rwk z51C!}cHetvKv@t>|6gWmx~DoTEC2s<&Ue1^eM|ha-~0`>>-EGeRFueOlSnIv$>+7w zp_Wl?zuR{n^~GZx%fT`S$@dEw#WICL0VSj0yDqIw8(CH;lq3A1%b?#&ETsWI2+?(& zjG9gS6VjSiQ_~tZ{kZv@hGmCjB#}6dF$c+Y*=84p9fkvwv091cyAhRg8Qmx_IW@s{ zqlNEB)VDiGvOq+Hq=?A7(|aVD(Zs|!M$y1@Tvj*hsA`tHmLsc31aW#jLX2aXL{XIV z@+J9!=3%t!(HHF5FJoil967Xr?Rfm7|LPwhL=jOGVx-!S#Zrm!@kyqpr#W%rBxhfE ziA+v^G*s_0Vq+f57kG3?@UIv0e{2zdKc%tNYas|R`I7d~wLZAWAc$}VHqDJ~YBS>; zK68|QcYx^$yzt!fymIPu40?68?p@{R)34C)_4uv(x3Km{45NhI?~e5HR@b%=MKPVy zis^I*dp6VJ;p0rs%%JHyrCJTtBE%w>FP$eALe75Tv*ZgU29`A{Wfl(}AeYscKX?!U zsMKnRzKLmv6iTHB7Rw0a)Eus}7q7^wDsF1gRVd^co0vq-$moT_$Ugf=U2nblCiy~v zQ>V{x^u)zq#8T0q+e^}2Gi7ByG^j{-FiZ@B;|M`yG$#>yd+*2O^ek_D?+s!^ zv_eu&*w%pM`!@!jC!g0JwDF#>PMkQyKl$}v!}GjkFwII+ec!|LhIpP& z5ClX~h$J{aF%F;npk~;|7!savg6#LU`-lv{3p}pBcaur0L=X#T&*;R}h#(9JqL86G z01-j%z8sxkiX!7!HbZ-eJ#dgEne{7e?!N!8`Kt8iY1%iSQ2ZukL#J!nBSMXph6+td zPS%{7Ma$*bY4(_&t`SEe0`T@b7l?w8D7Br=WhFd!fFJ}&Ld3Q67b%v@eC(62q9`&~ zKRC}PUVec=&mo9?1R>_ig)1CAd4jF22Ai83C>a^c^~e{?3|$#j%@c$P2VW6D(Q?RY zhFng?>bJ=n23EgEsaz(fX~YCP_v|y&re|rVvbDe(5z7MYBK>o`;^WqJdPtQS(5k#Ss);n2f&T$){zOeRYd1(>#rpk%035)H*t z*+_*}lZ_?IGC>d!OIcoe_F3-Sxy$DII$;#!c_E?{;`u{N+r@SQ^n9M3<{Cs&!Xat* z38E;`-izXq^3Lv!+-Wwcl&cJf9)a&8Niuiu+-JMl#&$dkhQV}kE>T|AiU?9BRf|e> z_Tm(=e@I_qgjZyIo-&OT>zI$@gn7K+J( zQr~Wp(=>F$!0h)Qtrc^*w6<2sW)<$<-J+1!_G~7AT6RdM+2N@dpJl7jV*bD^y{^UU zU;lGXoq38whYnIv`fOO6JbU(e?%cjZb*w~fVv6zc3U+sbsksC6TiY}?*NFWTG#uLO zDwkVk7i@`k6jCe}=(aW!hnYbKknmlfR<{qVBPu_d;;!fWEF3(GpoX}9rQi>fYxoFj?^DwA`pudNctF@N=~Z~V2t<6^nU;=zNM zrb)S6#xVyFdW6Fe$8pHYu+>XOiRTv<2!epgsVVAPbxg}9^nD;=;5gW}gD8k7S!HCT z5hJm(zKM{&ZZ+zB?lYglv<6(daR~ku4B*O2N4vAAlIPzjX zcJeuvHtQT&m|Tr$vb`Nu>%gWLbP)R76!Eq4gR#OS0_%rjkZxUsZ^q8fB_ z2G+nNjw3wR8@+!%9jR@l>3JcS=ks6q=}}if3DN_mG{$$n{Vi&hDp3?OF*Ah|Wgv{{ zv^(5gYhVv!*3(&ta@w^yd}xuPmZ4nIM}!)rEQMV9Ib{`rm>>)Rk$%5Np;Tqi?_x|Y z5)MpGW=fn2+!2o=pVt|BF&T4+n|1}7?S6Xyq&=B!xo9LceKtpbVDj$!@27yEgl+p= zy>yTL*?SVYaE+9!MIVt4jno{Z_m}feDo|=x=W*x-G^6wwZT)*KSk)l#_}q9A>`?^ z&$D#n7Rz^U6Gia|cuIQQE>Q&E`Q8uHv{4|Ag2XsN6h;p&K&3Xu#y}ufn&Q%mkD^bZ zY6h1s-{kJy6)I(eY`(?)U8bf$%Re+%o<@n8#d-9CftuI(#$SHt!|(57n136cAzD$xiWFA2`w(UL z&IhZMs*?#SO=9l&*8NrFoDOz?*X`i@9S877riA8xAR!iuAf&I*nDz6Z431NUfMhR&|Ds$!lllxwzCM zNDrQJ3exWC|A%%&ZG0R-lqru*;HCF0uW5Y!&;Ep+MjhL-n4X;ZXfA@;#flXItT(tqKu)d^g0-;vb@4heG5N|nVw&OOopLtBT6aSTGZ&7K7RUO%b6^`A5a)yOb(1t zL{nATU6cEp4F(>xT?JhhF+CCFJh!f2XS>nhJKy>ynx^r=xpx@49=fIx#Q{+yAcz8! zQ)6Tm5iNU|tY*;a^wF{kYQbPSn?=cF7!GZ=HX7W%bpxx{}=Q}DYErHa8* zPd|sIB?rX$3m>rEXzU3LTa8WZq0MkOMB0VJ#Z6qt9a(`VzrIdh*Xj3qBZi=&WC(qa z+E^Xeb?^fpcj%2;VY`YohNdyFZ6rlOFBFJ;AFH*287a)_MYLj>Og2Lt$1EN`L=c1t zc9HTaBuPTe=Mg2Da!TkB+U8k(9#5=A=w zKG}gnty)7AMFdGElg$x?A(^a75DS>j5JVZ%aWDsiB;$<25hk&V9S}#ziiE7>(q}Ze zZ@ZxCZntN*92DY+OCOxW9wfm^$*Mf_{5+x*(r(>m=(>b*jRW&zbWMwudpksGjq=nK zFP)jCS}Kg%+5t@lVK5bp!ig&z&w|FPEiyVq*Wl(`(; zAs#&Bpz}~C(<#RIU6E?7%GP>9v~ewKWOKBCxwiFC%Tz$u3+S3oEB(-$t1EjVJHWt$ ziJ2KX%_f#@V>=F-s#2Sn;Dh(x;koCZr@OPw7r(f`_I8HTPk)+RHb-+O;T%MQ%=+pY zK@gD3shETQ=!-e9xIo!ZP_+V*T7uB!wHIe8mdm_z{w}^$q1|e6U%#^zt7NhQ%u1F zlJ*rN6O%acazLU*BY7s`n1~oP-Iy!g9(qy7en_!KRaH#O+WU+}0*>vly1a}%7~rLt z%Uo8)8xAQHi->{*gy?yFgxT!!>}O_XIQQ=RY;SE+8*AXYL%N*~va*G$s$>+2AdGPD zZ!j1P*zS60s)8g6?6e0=jwQ0x-Azh;;t+sNdkfAvD4T_S9Q#R&H6^2|Mhq8vA)*f`sL*jx(smO_z7P8 z#3vXG23)^(B?YBGku$hMpW5tGDFwL?vB>N1t|PEQp*qIx>sKI7P~3j6M;ynQ)J8W(NtyRMc3&kv)`jglb(yRBq50swqx?l)6bwA2G5>-fp2{M>#VP?Bt{&7 zYYq6_-~M0F)I9dkNic^PvT6?7w)x=P2T5s{*J-z!gmFyKFxc5i=*>$@x2dnLaPr6^ z8~1M#q~O-QJIkCpahTQBjSzwvAQ_CNb=W{*Eh zYiEPIOIPq6m#UHD^Pm4bZ@lp)ilPvP0mGrqaF{3;M^VJu%1Wwqltd#*5Ga%?oIG)Y zFpg1Gm2R)Y^1WrEC_)xRGAX~I-yNVRBDzsXc?}VlFTRH)f|k#qojawTOv;^3)hcis*s^ztjod$=Lz-+!NMF3Z~5`e?FG5+bH1C;9B> zzkuu5?Cf;8dE*+TYMFMo#|tlhj8?13n{T|1=Xr=}OQHM^fUugMQF;F1T* z$Sd?MpOT)c7%MW}f%iz(D2WmalU0gEZDhk0MbYS6(sT`pDB-LFYWn`WegmubZjsGp z34#F2a!|4=SFcnEc6wdjaJA6+!&O zNdMtK-(P|V2!wG&b8DN!>MXCm^cnz%BA+*{i`0d6;ut)~XVB>24Tt1)jj7TM?qJBJ z4=yq}H^tL0K8NpmTzvO^PMkPGsZ^xCc8|H)DPDZ`Da34^(6yPFs?llB(QoY_$s)Gx z?Y6sGpk!)e0w0pJsY?4y%(e>!c{;+{Ig5dGCj# z+BYl1i_aXxwjBmuvZ0#mOPC!MEtBEnue^#VWhfU*y#B3kAqa5r;2}Q!`Jd+Qm3L_m zY&^$7*K}6zFA@4488O4uWR3RD4u>WS(COmz1WunilLC=7O64j+w~pOwQ18cFxNs?v z>l0!;KSGNcMYi28fa}F%6!}3P8;}G6MN2X%*Yy#^sf|yjjI|nBsFk|H}kn z$k+e!&$)Z&9zQ$tC0_fPzr}Fq^41&Q^wSi=AV$sQu@*hxo`dc06FdNi*7)p_e2UM% z_HlmWpZ^{=msT*{Kj-wRlXz(fIW;xIx$nQpts6JdRF#+*F9->Pgv=z0F|AgIC=Ah5 zjsCzUibamiS2#FbVk$QUu|TF&;?~VucuvHN&pt(ctIoTD$J1w@XLDtRPrmYL<_{cY z=$L!JLgAtDTZj`}YS%(aNdF~{h{Gf+)Kg!A{}0so!oKrk-*ngGW#0Ep;qCo_u#ZA( z(AhDOg&0N2P#<=10xS9T7zAs`oH52`+)3+o2~Ex6xi*3jQD45x{OknUR1LQuaeK2) zyS2lcZ=a`GuM1MFP_G71L{2q({_0InJF?-hI4niX@nkU zZgG*r$BwhKbcH)GVPNAj?@c>kZfrp_hBToFosrc@cov!ZQhvdIIL!UT~2!aSz zhFT#*oGT$K8KN-2Psd6<&p{v}OgG%_RNAg|nk>p7g6AigK+m-3ce~tMYfu}jF*jb~ zxvPZ!FM>6gGmOJs|1N>tmzku*# zMD=$O{jx!w9^bzI2IX>%jcA8{JQxA7*@}*diDc&}*DCb3npmbuKGjEaOq1315AVEHXm$LRCw1>X8Cou2U^^ag2 zwnrEV2*QJn|KLWXDXEr25kkyfliBG*d+yQb{qri14h%njl?$o4q@3f>ks}zz63vE% zUV^e3VVX_W?%m{PzW60{!@w{M-u(XeIDX;;`Fx&6qt4RJB_dHKYg9NjF~hm{-=k2F zc=4r|xOVjlb2GCn9z00FFxcK|aPY`sip3Ide*b$MK5`U*<0nrt==YHn8AVq3z5nBP zxp?s+8=E!E!GQG?-9LCRLRD23h8}Tzd^AVUYPJyLfTgSN@YLC}qxR~P*1dao_;3F4 z|9~h;{OAAaf55`Qd4xD5n^n<`5*amBmsav9ne0y_+Q-6Un0pTn9O1EyzDH{O_zB!% z0V3DOY_#w_pKIYQ=-wm_V+106r-wUqkTNn#K}GZv<(h#tNV)-L8d0maOn<~JET(5Dc7oq(U7T1o>sfbouzxD{y*tI4=p5VxF1W%qJZyM z=xP>GO;WkMQKT|a!|I!yd+#kKCMP+1`f1wtE|XOhZrtc_;o?;?TCzc|+`L0Z$#C#c zCLP`>(r&fU4V{RH@v(`dJF1b^-FGGTr9RsLK+@B5^AE5$}2f z0J&T`WhY6@%q=o8HOuLz&LDawrfDN*O|~4+G#$(G=xtr+8(&+ZTASe5k$JxR7m1Gl zfddC9y!J9>HRheyzX`dHrCf@H=7Jy7fF$cgAmKMSYKPEzPU-O)naBY z$yC->R~ZZj#BofeT){Cdc3Mrgn>%|lqK(a@jeKbKV?=V1Q0P&vlyF@KC96Rk5e7a{ z^!USdL_fDJAmQLIE-rHP=pmdz7eSKI3MG_m9!bf7m_-ybkM5&=DYURJhR6H4`ul7B zc%LSw@R&>>j(>a+Uqm2p3fy`765Gu#X5UO}ymaa+2myg03=tFowW`x=cR9IulC|aK zJ@0kn?j|BJpLq4-NTSb{qEISVffmP49AmPYN0Kw#Uf$&B;lpfg)p?g><8SS>Qs!BJ z5QCb_W4X@A@kNNBnAa%gHEhSnwq3@Am~OX6x4DiGgX;w!I-R_GNIF6e87NfCM1DlO z(M+9dg$EW+zJqHGIQ!hwY;SFG;Lt(B2;6?+J#cSjomXC(;)Cm#(2O!#L1Sh49`F6| zZ4d?YypHcBLpZMEpyvw+2cVU2Nd&bWn`h2G&)Vt= zW8-7!Mgg-wpqP$D4~IiamGXyb9p>{o(_=;c^|#)m)#(un8LnNv!raUlx>5QN$K(e~ z)l|x*0)5NoH~;5Lx(sPxVyYeztO9W}uj)mltbXskU zLIEk0V`_4eQn}3J+&sQJq}^)Ms;{uVwM90oCM8HZ_F6MC7)66_f5_C_BGJ%BGjybk zPF7P9Vu4P(iKgYbaPEE1JpB}hkDuiB)r$$GwOnOmbAv;N4<}uLtu?e_k)_-BIJ}tW z?yAH1%p8IcbM4BNQG05apWvmw@MD#+l)&RY^fkn(KAezjbTQ%f@22k$d%#7+Xqw8( z#u@|5Mb~wTg~Et{(@6~`=H}+;wc8AR58HNm;l<~9;l+5`ghRvBCge@P{`A$ukp|S@C{1kA_cvGuIAX-ZlY)f@)m7M5jUTNa-06Gw5=DRUJKFc;b6qxq5?Br;f33T>pCC)s17RR;-;&_yf?$&Oan&Zyx+sSaqE(Nw;r`_pL z9jno9_1LLzAp!>u9ww93h~pR`hGFQVW%C?9dXP&OF4AhXAPN~cKHdI32HoE1#^=&0 z!Oe|LOw*y!*y8xf;~YA9n%ev#0s@0(ow0=@)W*ixY7hACTbCh@Sy^9CH{eGrzhv`T zYDtzp7Q24#yZ;aqL5mR;J0;){2IP0^afC-1qv={%UPh8-N=AWCzVa$#W8*}=N2{^P z%+w@jo_?A?{QckOeyVf-u;tUx57B{KzCtW2G`F`$V5^>b;mL&5sufn3uJOv*W884N zgkp{`hIlx@c}T1$BMUf=i{(1RVa&$nCPkw_schhx4n;o!-$bh|xX(satzF;?!~Wo&Yc8<($f_0ol1%xt6`x7}#4 z-Dn_)0_Wa+kGrXrld9(#n7t7?-s^NxWa(6W{P+L>AOJ~3K~#aua1iY|%}3gMDb_Hs zEna--!gaKg;ZOftW_z!f@ z;&@b=luHJtX%VDtm@tZX`IT20x(=K7ZjjAnFse1Crf2Dz7Ev6N$>qrAvUu&7YNd*r zRfxkOQ4CQqq*SgE1UJ#M3PI>&l&ffiK0+L07zXv8Lnz2Zag3Ie2x0}JSi-jYl#MLS zc7mkKf=Cei*n{EnVX+yU|CE~Oc7NB+S@JG*VpNF zzK-h;3B!RfgZOAkYyH2Dx^1>j%9aQ5X`%5w>k(4lM4hZxi?dfBb*{1*#&_ z?pu@%onaWWzPU}K*@HNyHZei1TA`fFQyiaTX=R1YlmmezLlp7J+9X=upfb6@2UqX! zQ8lWR3cT{dGqi1w#hDt*fMf4fJt|cVXr&Q(yvDI3iO1pVZzkFh?RJl~`**l}<1V>- z8yq=um=pPFg2hJI8$4{y$KH}urUAqn`Q5>Oa8il-06vx!J zlg)bKRaoSOGV113e)3LxQ>N@fTSqA_|nTLjJ_1xY2pHY-#lf(jwB#)-=uhYckYt&P6H;>HRCq(-){UFo zxqX{3Omy}|S!D6RK`Jw|eE)|(;L4>d1VKm?#!QUYxPSjXr%s(DlTnCcSh{(Qe&1xX zu}x0XSy-5-*GYD5p*q36dk+Lw)og~0lHvUM^E6vKOidp^&1T3d3YKM$4#2FUFfp0T z^SiFg?WG$S1%p`3V%lzE3{n}xc0Dp`fw@B`Fm0PKj*yjH8o`B!vtAw>Brzx-t~a)=;^ z{9k|aZSLH;gCxn6D^(tVHoNKG$1iTd-T z+JFC1lM>2%)5^l;t7sy?>Qu7Y-em*4t!SzV_$Ffn@r1VO?Zdf28-yVE9$A~LCS&#tnJoW6eG&YIS;DQFf(5waw4=hjV1 zRvG0G)&>Z^E;gAm8GnmZ_>jGj*!%J$ z!QL9$HG4!sfENYmg%YO@FYw*(eitpT5(hp4BDUl5!*}0Fz|@S&aOmTurA*1t_LMKX zZNkk)gUv>R(Dx{o4Tjzj-%r}iaRkkNK*h1~BNxvbBE5RMx z1OM^+DBf>u5r1e4Ievsb6Z2uz+c-{2?;l^pe>m5OA74L?dbYkdQeFjk=K1GYzITUi zyM>z9c2{ zB5{;V#Ce|oZ~PTRQN*Fchm)=YP%M?vidE(o7Z{i(VHAAmoW;!iJfHok&vR$#76%U< zqTlZ`*x8_<=TVI+!$FU{mZMxQBTF)QO(XJLiiW}1SQS~8sitC@<#LfcGL3qJO0~-3 z;v&O-`=h%;n#Sp8p5fa0x4FN(%pd;IpD;aMqO51>^c*_vRL^gIfz{O&o)EnryCx~ zblQDpOU2}Li$VfF#4;V$RyQdZ$`rH=11ZEdeZKXb?~utV6rwC&_{=A1bdu}H%Mr3M z!FaXA#_AG-L7%~(Pq8?TBnl7<$eAoV%{DPH-A)^$s3S;FR(#rKi=D2Ya0sFpH7h3f zN=_-A8Hvg95_i@bNRmXa+eK4zOwZ0R3_P~Y9*!R(NTBAjXoWmVMnaYqqBurRi7B~E z7CVaBH4n_BeQw7|`^I6g2VGXu)Hm=0I_(ZW`2P24Hd~{gYpFo#_RbFWaQMi9EFdBX z0`72#ZJVszzn559udSnL8es(8zJ(V{Oz3?ir_Rd#EKv-KtRM;zk_e6MCbhZ4Sgyxl zVA1IgSYF>`(CgFO-XV5OGD?QwsNI%C&YYY^`XD71xh_!{qR1Hv1)Wk!=fvR!1WCa0 z;LrZ@+i3}DGhVGAN-};ZfGFTP&VzaNI7XJ_k#WoPFm9dT%p9)c8k})_kDiu=e|S?+`M^{x88o2>eLK#M^BJ19^VUf>gsEyB3&@!mS8f&WwDEF0L z`X&C=R}&iO@Bh)C^5RRMWMXQDq31%f)IxGql&D>QU#-^qZf+Yx^xLq z67h3mOihc#*#TCsi*A(Cnp0$RYx_YT-5G#dAn-%fF&#ah=hm$o{P7=uAG2+thzi|- zh35tIO_z47owhL@L{WNdhV<82SFcKhxJ zIB|kTqfYE}5Yocp_rCfAsY&hW;Y?;r{=d*FfZ+{VTx?dA?M^M@ZiYpOaTZq>Kj zdk)T9OZO?Jip@!9z~JP8aazX?q3aq|Eo7`(A(pc=H&@83+GEU3{w7BJQ6GOlsxLhL zB-w`!e&kUkByFFZ9C73J3W_MPFgwM<{4`1?$K?0~5EHl-S1+H#iy>FY6Ne$&TMd?O z-lR4$hA1Y~R7ntd;pLav*ho0lTfG3!kC2TqCX_0Jeh=66u!a$I*0^=;T8cso808wp zY7NW1kLUZ?mPsa?V`H;HUQ;=A>^NcMvvOydoFd~#Fe6; zj)^plv08=LU!Yph)7o30*SA0j(Q_jCl8zH)P;wapKLjM|+dZ;3*4f(HB9}|J42xqb z*{n#}DBxHYi-(UOO9J^qo=&GVI?00+rOsuuMDYVFrd@{Ou6yq;F~;#cq>PeAl$apxVA;UP)1QQXj*~F*cha8O*gM!Ck$i4Fe0BV)xpjxo za~W6zWLd_4sO&D)#;H!t(%f#~`-#U~>~;tOnNn$t`Kbx6TzsEU5GWK1WHR{?Ef&B| zr}NZ&()X3)kgQgqxxLMm_ugUp*eN>oEvkhhNq@dGz_wjhR}&$R_`0SD~)mfz58T0Em}J*R6S39V*|^!=yV>fgKf)ZdTxg4*#$Q4Ck{D# z>f&7Xi5QcX%VN7jYDFV?JQ8Lvg+c+?#Py<-43*r2sp)C9(g79#*Kx`1vh5U+@v#~U z2M#bueejfBIdB3j(os>&R@PZ`n|W`eUG7QGcz;)BR!huE?gav%xaY)j%{OZ&I&sBV~0u-7az_ z$GzK2BcFRo5-Ao-7$dDS0mmIuNOjq*ev8>kmRncv61q^UmeEUNj2SAHFG3^`g+pe> zi+txhuOrDB6iLQ$90r1fn#ofhPrigmkcgsyV!^<)hkW@LzQpA#=je6@Wb##>dG1+q z8JXt&yF?<0s?Pku!#M7cPN&P#y;auhP2xnBfw_fwY}ZB*1iGCLgKnQpE=w+#Wqxsy z+1YtK*TJZiSX*Ajw))&#zW;#1)oMOag%t$!yf#vcjiU%v&C%Xz;#dx9His&U$YR1d z55wqT?Mc*(vNxj>WAa*tIHeYfDWyylL~>arnW+x~WI-g8%i#w;wed0ZbWC_>Bb5$Q zL=;&@mSh4ypxM}=R4zg2U>G_^!9Z4Ia;ioqn?)1^q&Of9Lt3pSzB{C#=10sr&kOM5 z#C})Js-wuZzP7?w|KR`Ri$DDuYA(mW_xJw+&7ExoL1en`Qr}M6lplNHc{VrJL6GPU z926jqbL4Ugap)qX`h0mU%h0i(3|>E! zstkuif-u65LdxYb6XRukCsF-Xb%Si)KvHrbWDup?L+ZGXx5FLr2KHfSk1%J251;1S z6N`V`5kHY9Vnk8wcG~oN9qRQh#K>p6(d-t$Cmx?WL>FxLF1PVjfWomYT<0(Jj#F0h%mdEnFWxCxSLFjYx*a0fz)8s29 z482UTSmDmCYrOJPKa1@+TzL0A&b|Kwe(~pjj#7DoqA|g0eVfV28EmVEs^uA`{b4~? zC>JYiHJT`jf|`27Wo3z<`_j*2o5{4@?R#~uT)LQ~tjqTqm=?OG6ZjsPY%-R)v9|gV zC$#WT#8yZ3xno->vHx!`JA1g!e?rR8>-G@@$mj{CvD0eNXf&`Lo3Zg4aR{weo8izW zV^rw%2K0IZOv`4ou`>cA&6MC}=qk49Fg`JbWm^n~dpix=sgcUATJP-}H|U!KqBt4} zc>>9%|A>a#{#8$P{s1cF3eTOKL(jn0);5Qxi>Q?n1*1&t?qFmhq#r>YSI_5}o*ZLf zx%~RC|0b1^P8|AVa~VqIGPSV@YPB(pQia+1gB(0`^xu8Nf0(lS$TZI*{lbsvQ$EI1 zFOFk^I6{;pPMki)YcD^`)I^O^$skHaF<0*0tHlOL<18Aa?tOyoysIc)?eg@L_r{z$uK`PLC+oHnkHEy zJT-@^WjOct_b3z$=4U6lyEH+g(`R$1N2k+da%K*shUe(-=zk=9;O7>+~& zN51qaw|cj>v>a;`S&GF9QZ|ca4n~KAnkwta(r)d%mrE{f)|8-5r|42K>?qrkyK2kE6YX4!0&z;n@c4FQ;&og(mDDwPt2N|iyc zPb>&ry?T{Gp@=thSl`*8G%*c9OtGkO@xq0~fyQwtl`AY9dy00uNp)<3>Dd|n=%4-* zEYl(T{}A_{L6+U=dEf7(n{)T=IGtyDa>fiYcEJtA269P|T#}MVTasnDRQ_Opv!yDP zLzQJwRJrUTY1tNKCCU;v?_w9g0$2b8U@!rgJkx2WbG&`?y(it1{NbFwJ>4@6kSc*V zRVYk%-`joe|NO)IKJW8BPbk#xvUNR?!o~`zbPlWKU9w@lJhxAQ(tQ_-4D!pb)K>Iz}J zNQQ7a%R9Gb=^i{lQge_cn_SNzn`$5Z?l@HAu^8Eo4kD2#qW+DT3bEL{XGL3j3iv zcLzoEF$c6K{HJ_e?TJ&XR+yiCfQLY(UZ+!S(rD<&vV;`&Q;Ug!{b$=2j_c8p$>P{8 z1VJFzRm3)RHaAOD)c2X3nMOeH`yT{>@sU1qoq0xwdU@fizrx(y97m2F<8S}|e})=> zW9Obc$jjgUHdo*MIi<}FY%$7-qet;vmukJq!u&k3NR;mGJU!hVG@2Te$~3i4cD3C< zHryuPNTSE(E53!+$2X@DMHy3wGt%%lbNW>KJ(4817yc(*ot+)NM&g!+`NJJFL6@lC zo%i{013U!eUAEhM=J;(ie~;XLJ0}r#5J+6xrPVUAZHv42rl_hmo%y71a3F{%sV+=M zB9lqux;~gQJUUEYK81kHW~D(%6%ax)#r1V^of6qhC$V^%p#!I}TMl#gXK+0wIci(1m;x79}#+kTx7X%T*G||NlHVX}M_6pHxm}n}G=Xy-fEu)#f zk)tdt%+Ed`9EngXmpOdo08Tgrl7eoTEKc3y?v*PH9zB6!n$%5?bheYJr3aik{UnN0 zMS1o-UL-}mQuaYY0eX6SId%AT$89xPs(DOKO`@9y7v8@_ zxm4spK(I0cgjWkxceg?V-SF@4wYRR)k?TO$e0%K+rS~72zb03%T;|9QQ9zcZcEp?L z7<(+k4jx}L<5P0@y}I?hhcE)+GgaAb&!2!;5=c08W@0>b{_OTHDk}^Q4N}$o2i@5% z(m$||?npqn?CSEr-#f^guf5K|z9EK2#@JY0qPV$9B~aLr1DoM|SDw2!Z(`XkR9!_5 zi}c5%?R$zP5~Q*jLQ05aI?K|+JkNaLdCHq5-hcO9v}S`3-gyT+0oQY>1Lh^48mZs($f^$o6E`~W-; zB@||Dc^S(x(G3IB(0s6M_gK2#qp8%^g54Dg)Kv%1^V(&k-7~4FIrzGHk2?|F9TTY8 zR4EpGtm47UG`+oj5502d?^T;B@kE?>Jc_F7pE^G@UFY_FKgZrIH%ataB$7!qU2Avz z0i-f%bVKLTM|ZFthw(#)P{lNv-eFRq?Qy*~J%ivuPrv@DdW!(1a*cAi-bVKKx*p6g zkVvH&>B;ct|Kb0mzbj4Oz9AM@)_ComOO%Tho*#>IYTO^2TrSS#$qJ4jlI!Xs6pjQ{ zmY}@osvH;{CY4Szbo7PKt(-4Ex|0aI>i0Wy3(@-&itbi-P~c+Xxh|q8AxSiYGX0If^{`zRPwn!8dok|!gW_sn~gRs zYuOf+tThL^XtljuXEr8b$u@wf6MX^1h;)+ zZatQ8pgOFZPMe{(<3#bmbv&$=jT8zIQDk4iCkRI)(U`B>;km?O5p>%n9G1~6E1-dj z=(vB-N@r!aIKMV7fS^#fE*^PPtclUOu@ z>%ru`309VtnVVlgmL>KL4N@o;5oLvDt$`Z|NNoicw&#(`cVp-pk|d*q6dcFFFbo7i zK#?WpXYV5l5=u0I)iM!e2_XRMY}qp52skqFglmEPXo_V3DfcM%SUv1}W|&`D)7gcXH)tqy{K-YDR?9;)t< zO@|Q$kRv|6p(qNKN|}LSp9i4T>bst*KYq!C1W3ff3ZCcT1RJnre|m(LOeGl|Kg`P7 zDu$*Z0P#c|wW*THWCF@>gjh6+9Z-g&K{WN-zxzA9{_5+z^!0CG+cuq@os=tOdVBhK z|NRSm{p;W0wV%Dp=`*L9o1a5Ms`wo`v@S&IG@K6rLsd3@@68Gjd=*p#d>4mc-lCgk->`|F>*9ieu=y zN@sT$LrsoNxQk3$Ev*`9g3CY>UYv1=?$}EQ9CK zvP@)2CK8R{xgPf?rzmZ1&}tKaq8vDQkluX*q;ehHxqgjQI)f~U?UO|@?o+Qdxp-}r zGbj25_@%-^5JLufk&Ic-fo|NmR+z-`_3 zAe`Uo=6l#BIU0#`=*ST&)hc?U33xP}Ra9JCw}f*N5+Jy{H}38bpmBF=+}+*XA$WiQ z!7aFZaCdiicZa+Ghx^!rmmZtZd#zbj^D6+qwzCE2mOmqTjDRpuQ{9W43u-Kb5|70v zNgb*7dnHa*iq|S1-`pgAxj!>9cK+4XC8Sl3DFtL!5rFm(GkkvE(F;C!>f76UWb3Wqw+ackUzs(Uz zt_3dA`GmdO^oKkYl%x=*N#Q)(`xTP+Pi1!cUHkBL?{p+P#)MJlx-yyu6Q;#PFml1Y zs#prw%V;b{*pyeW2>ETl_p)SJZF_`kOW&~gC=o03|fR3 zvonFnfWM|OPeZXIphFs~0tzIjrIqgV%-RUR@Y4E`3!?no7=`3$VK>ao6Qx+Wq*hqBNlWO1g)v3X)08nAk$CH z?nbkE*fQ>Qq5CHWPIXo(Nz9ICdf zO?_K=VZaD(%^+Q^(QBE;mLXdKX&xqe%l7LQe0=%f?|jnU*w_0Q@#|~sxTCMoYrQJT z9+*S`q9Z8CgdUhs8JaYNWQmbG+z!8!0@0PKx~ahvCho@38g%1>i`W@`vhyE(EcKRs z>fFm?c9Yg1A#*E2ImYB)kXMvk5Q&t)zf>vkWBbP29ls00N2Js1z`_^7Gh@Hol~!#3 zz|Di0rmmx-4=xbxf7*1#%F^Efa=ikVFw5D&4Zuj9g9qN%jnk6AH>XW;;Ew{ch*so% zQT)aYLP<5QNrMly$SW}^O{U2@AsPCfOS+?lnR}2OoTCu#^F_pYmxqZxCJ1_9r6h=u zsTL%;IT^o0EQK8k%vaVGl}?9;4nS#Rsp;fG1{oTgyLIN@gw1J|bQL^$(}13^xP-I8 zDNd%*pd;#a-<`XAW2?0C29=u>!&t$e!Wmx(5k<`{Wzk2vs%{%j&Qd(9=W2kK2=`cN zF8ppFQK|YWx*iX!Xs5-df+y>Q^3{s61&^=a9(1eVdPoWrc=6XrbJj}Ll!CHk?)XeX zNU7UAG$uFrKP3K1P4|SZWg7m~YkYzZdl0Z~!?Mz~06u-?8_Lz4fQB zaN2#Ptn1`vJClH^BO#I=35=CBt>aX%D-J_2Ge;?g&!Lob{aew&;*SH!+ zZnOWo*SiH@4i&$1m~Ai;`1Oyr^IHWWCBOc5eSce)_YF5`;BvoYvXnJ)_6}a}5Fm{J z?KiJS`1Jlaqc9{^CN6N^vcBauVvh(} zzLCj1hcjYKTuno-AetfKsab@eTaR#?GL0UDW ziQ~q=iP?Yk>if_PJ#%OoW6t*$PCEJT-zPw-(|0lo0@6V5U!WyG%HGaTs6gBF*5i;e z+uXNQ!M0v$y${?*yY*b95@3yrAd>)?4_MgvdLKF;bh5Y}pn7`Vzd7t48km}yJ*{E+ zhMi{-f;GiZ$>p;7$Gk3dHpdox-v^5Z_jtkwcFvymJXVb6EbGm``FxEr4a)Ak;>i6J zV@e=96Cccz#!fH-M03zr-i^B{53kH-sC|#5^@Ne3D)e4{O^ZZ#uWdH^Uvg*PwZibN z6LQv>;SZ{BzNV=- zNQf4nvcaN8FHlm(IlL$;AW!?#~!~6DW{k>27-5uv!1USKs zwDSitm?KKm_pyg49v(AyUL~!`2U=$#9NY~MAIb#ZtFse&^E6WWwomaJm57wf=ZZNq zfWNf!qH)Cr{iSM(jUk3f8ri#t#}JJG(+SfgZ)a@0e$$XGG~HKJt>;f9o8o$TZf$CkrXN<&!9SSHZmCLCL0Ko>6eUClcUKBtK*{p9zGZEcAO;d(1BFJ45D7Csl zFGB$FjsND3+3^_64c4MXjth0@gW>n#ciwL$TGwmL&8dmK^IFk6do96p(znK_-Y9&iqe&Mx%z!P_xAG1I5{O5d1_iwW)V}SDn5k6ju z0_C#F%L}z!a{vV__U)O=X&=Awe9T}4G1QdF;RZ98uG;T|DRk*1?>1}Xdir}t2y##l zVHi?utu9qn6Vt}~uaGfW&zI++eaGF_)}aD4^!bIO)6?BdxAh`5dZ+8hc>gf{APN06 z0y2lNWS& zM?*p$Xt)5=mzd8=-5t*~-?M3Qc|yx>C9dODW{HeI)lk04FZDB{L5riNn3$9_vYTT> z#aUBNduL8vck6O0Z?)Bhm3STduq75p!_-4)*>r_t%yVr6EUFhHfezx~sqrNWJTN@` zW?37t<8fFjm8VFFFZYQd;#a4E%~(sy(VtS9&>X|1_rsWIc%xRt1Y#xijN&_r1kkgy z!ODHwACj-4YW80s;xjheiXl>KAfm`Gq*7G9XlC+>5+)8hcsOCkq}|5}5f<1$dKWmb z9Cim4hfiqP$m2{!$TMV}fEv?(q6rvK6MGq*_jt|^&R;DXKVSW6qZWXepuFCZM3NrK zJd6j~a~io$%&xucCi)`XX7d*}XD>x;^rI5yNglxRjz}ac)vtwGX3)!w{lPC@?04eM zy`mb&oa%F#O#e2Nk2U+Gx?K%*6D3MP(K%78_xM>pOJF!o@9nErf&VD^Vmn|IOjMA(=H8I0zc&naPU^-xp2u+CyY*9z!RjIk!VqU*n~KrS9aHX z(MdbVllLB>evVh*KaImnfrM!?b4@}u()Ct@+UG&|vx!C#*o9|y=s@2`eV+#hCdu#N ztJN!?zp0jWb>9NDMavf66HOwg%&~Pii4>o!>7a9&_;`l>-ZowvU&{c58sD#U@CUj; z?^ND^`+1a}v8QK3R+a!NFnUkp0{Uga9qL83gy5dHxqrf5q6>>A>=2{we7?MQZ%-32&hk1Jx<0AJeZuD z=_#RXB_dyV#ZbR?ldwCBK|Nnj7tj=c-D2clK-vIuVa}h$(m}SGkx(i>B8(ZN>$LLJ zDi!H5fVtX4e>PR&Si)>dHmWOLk*z+0G!#a3d-q0@L9Y}AK|H)KFIX7X@rp3XKD^7v z=X8Yfs)psRMNA`Jp`M~dB{F{soGi+xNlX}nd~q(^!r6L8bKG@QD~}u*ylfG%-N4l@ z*fV?l8IUTZ3PvY8YznL)}@nOT7>Vp@)D>B$P-YznuUU9{Prv;ym zePeOt$v>mFgcxB&&|aRx#;u@a_nc81oR3wINufBekzvH;29t%?1QNplywh1zG-hPQ zTf%4j&%!Ue8#K3J1u&sG22gYVX(pkF3JN2Co$?d-0Zu_CkI?%Vvjd8``YQciR$eOs z!#%jcM5X%f@$;xD9KSkyOh_}g^+;C@U1>RHM&I}N@ZtBXAbcLzz`kb9^_R^rY&w*g zM<7&KGFV>f!9sdwZtfV1jKvg@yc|cfZGq(UuAnDXhK*nP78Vfzg{EAW3>DE}2@y>h zNkN+<43S`al~wOg?Mjh1BRw6!gmeGM1MM)Ia$X1vW|=QQf|R zfsV`WV@V$jlpbNb{Cs6^e8V z8oC~BCzD%bJI=2Aleh@)V-LRLR+SyGxxs0A5aT?B{JEN+Ca@!xC~>w<=alEN|7+DL znK3&$Jts|*0e1J@FV^7BLONcCcUy+`S~a!xg0wlgydME>`tL0izc0QY!!|Nz2Yl-^ zdo~uh=k8gBa^hyOTFrykr#i=0a8wa=McJMK6KIPYq`5=ggxo!3yu)Od?>p=dgt2(m zE4B*^CR$zjH+LHi(z>6AG!hI;V(F-jYcm(Mf+DrZG2;{#=m=M{`|Rif#=1Sd5;|V3 zHoz%RzSluSPG*jnH}`CMZ_5kZUhdIz1>7>nO3! zr_SIbp{|aV7AprxLO^Lr{&YzL$8Ti$oMQ^JtZO_@Q=(CT*xD1J@taY=Db&#*r282c zx*w^gP4Q1vo0Relm-jVS!%h{`!3oZ(puN8YTj&lCfEYIV`V3Vf6TANIGg#BRd`y$< zi1OcmBQ?lSMBzY`fG}8vr{{mZoibYD>t*YPfr&?iXI=z)Ldk;V8NYmrE5{dvxR@Hd zjZY0mPP>bWw_*q`J}DA(u@z-9^78R=h2bH={%**5CX0hp|BTr{xwss%^+Usv18>l^ zizzWwFt7b~ZKKc6xFS74bmg{_)}`iJiKcl&y=%Px6>tgZ=@A*d5&VccQTK`ZYgs>h zwKGu6nGTQ{cRUy>b{g29JX@UT#>bgD{C*l2qV;6`0qSI(S!7fkhCtJNH{0sV^E##@ z#984}mi1NT^9_h#`)jx+uyK5^fL={GYX+i(=&_OXT6flol^esw8A|HKR_qIx^=9q; z_zhpG%DkE55z<@^(YOQOM4lF{5jJk%A!&&5e5$m>f26C{4OIlK^mNrO5edD0(&{iF zWL#PQ2JIPN29SuU07z@gps~>p#?bkE)6~f4E^FxEbYk4tvxSb%&2U8 z&9KIl2B9&pdz{b@_X#tlZNtYzCmaLGYdxIp@p{_0)d{juZdDO>lZ2L-xtdG+qr=19 z%?Px7R-EoFn7%vJ$PDR4jzvU#uWiY?Kec0M`u4`Zwzd=zqhl0eo4{J^{o-NEeq<<7 zQ%iHAbXocawy|3EG8CydA#%t~E;rxe{k8C;29AjEf1rz|q@-%-ZNP-n?;BlwG#}{w znKE}g*++m(0GZ`0Uca{o^Cgat)3|qYap$TRRPuP!c1ed?FdwPY?j=ktocj5AZW(T7 z8lBD)1O7;E4ofe9vr#v}P~6@Rg3?mS_Z;iclWIf>EiXQ+hIa6X9bB_FgL6hOU<> zGD28lt#roS-NQ-`-zXwT`;Sis!BC zn=DK{F%XUv=F7@g1J?a|qTFGO zXDmElu5X01(uTf-1$$r2{?U>}*i>1uzIdV`d#(t+!q{-aND0hcp~tU@Ga9sAy_wUDM)D zsgg#HcB`N$B2y=q4c2roivgaAiGzrSWaYUz;`^JdH^K> zOH@FlXWE!W;7e`O(TXtvpYt!JW-t~0RtQ$dV1ab%p+uO+{Zi3mt>1@_>G=d2tmJO% zb-pkIDMN}yopj@wr79J;qzY)~*yKjUOQw(l4W->2xEFg|GlMuU7<)2&X4{w12uHU3 zf@@wh&w2X$~_a9yh1A@&=C1E((hLep(icK6m>(x3Xvi=!3->0_La;T6`iOmw)_)}Rgah}30g;fu`|Zf$JKjii+&N`N?9?Rguaq!Q6v&XI|1;k zvi0^(p4%e_T^X_ID zl9QjMsdm(PPVFF@vsU3c;?94N5NuIboT{Fdk(L7~Pn0X*`Y^UE+eJm5z1K2tE%EVE-5|_< zf%7W8e)bc2|C<=G1{E}4u{!Bu&8Aaef(LkgfPZMALJR4^Y^|*NOrp>#$CvuAPl`e`(3dFf^L>4HcZan z;VBUjchX(HL4SLE+$odU$hPAh|12{xdMWtP;}?#v|0TuZTj`gTnSmQ`^0k|TiJMcb z&cV1&fT{QJ;G6w%hV=f)Y3315Hm-`4nQb!43eftQAuC1d+9`~`oBg=r44P+6{!@ff zWe4n+!$=GP{c#91~5E4VDVQfX*j1*MhvbdKcbNgRb9V349EZ{8b8;f z^jX)pnC=!vo*>47v*r%`bSqxq>E%-)$10aCH2c}5?*M?fGY{=`kGMa+>y(ZUL`!L| z(jol2CpJs;A665hy)c-1vkTcslXep*3Sb;jrNgC#iOU@L$jwc2Uya$@S9_ZDp+J=$ zG?4W`7X}1O9SRcX`Z&cYz55@Axc3S&pQ8RNtr<%}z7d0}#j6zu8@I381~EELxg-T} z4FKQ~JYE^C_1}u0L(kj4_Hy+MA-}VGt{^PUbXhynR_W!KVh*q(<&)oCwzxRbOO>_K z$&A&RZh8i*p_Ci#E^lWhF1wPgW>47pCbp6yySe{A3veBFff7X--iLPUdVqs_H4;&J zWKi#{l_FVYIX&%yKTxP;#Z>cw91|*4t7c&T!G-2#tIU8A5sGo^iBYdhnyU1ZJicoS z<@yO~2YR4ckXyC@LV}N|NR5e2biAkD>5MC~AlcjFyw7rb_fmY*M@v*)RrN!82H06R zyI&sr;VF&u+Y?=Ab!vhP=5qoFHKP9~Mge`$SqlTq=XeRWAGI!EMG*RTGbjAv6XqwE&9xE$~AD{M^8 z2-2*-ns~d8YwQ@N(=I6RqktJpCyBmZkNZ_YeBUV2 z%Zw~5v20*v}$8$GRG zCI-G)Y9quIpuj}I?spOKCa)U`E7}vTiat++GiDj#kJ#sD=*c^ZWUY1^ClECYRIwjN z;(waCx+Mvt##8Lc@9(~dM7Tgf(I2e}`-gRStjMoGlsR+m==|uLkZ>%;&+bfMjV@k- zJfiT%+kOxC6JW%!O=%=)(8Tylv^Q1nyz{U!N6y*Iga&N(YW>d0Q~R4R;>P5u&u5OT zIO!52tzKDO-4RL^Nrw*ad5=Kq&OmQSr3g2J@w7f6NQxQ5(pkYWEY^yqq$*3u*Mwvk z=}tGC+Ig+o@p9lNSFg6S`UC)^PO$^2u6u~Qvy}{Xt|l}v0d*NBSE3%$Z=L4s?7B&^ z4F&m_idTf<1H9CriO;7IyR_?(wo)4-6 z;Pf*yO-?8j4R%|`cdYw%JlCh%&!WCPL5*o43|yP^#Ab61O)3c1Yh|XDL^SX%J>AGp zs$|H>^OtsAj@~fZU$w)XRWkZKlDKU5qx5S+`%HA*)M6g2fs4}TLM7YMWOHz?QG zUhjq4vn2Lo=nog`3Em+k^Wnyv$HR{OL3Pjyr%Vg#e0#PyyHIziQB-_ya!v1Uag_qrNx3JbX0|@0gZBkP40Th}Bc#?mWHT6f`m< zU_6%3=;fi7iL(bNnBMvcrb7`;*|xU+iv}yfz|ZdkQl>s%YYsBwRT=gjF{Vid)-Kq} zxBTvZ@T@pmPY*$rNlOQlIY5E58iI7Rib|i_uEg3ycerlv@2~qR+j>t&*&5EaKOGrI zl2OV{tFR;D;~vx#y@z+b868>%fq6vDQjyX_?5pZ{l=Q__%SxyM89UENkiUnOs0{xK zjm3!qN;+jfI&{I3xs{C>b0!;p<2Cp-1Qxh46bV%J7xy~Po%aY7jJgK;=0B@*bWyLU zD$G#gs0X*8(hJcLU>9Sfh`EA=Np{`wMN&d5=s{>=L*Sb19~MfH&u9x+Pw+%0qG z8?{n3NSSrOi6}>i8R83i{>Jh>65YPyDx)pi)cQLi&&v^S4Mju>urCDZKVQ3#;-!wGr^8Pf>WtC7ua2sO6}@nlk4 zEe&aLCjXZk`1D)mYFGK7njoyz?c8B!9r6i%-eWI0I{`*Q$MnyBYdv4q%QO~n8P9`g zkP#vL0E zTKxQ_r{@+CUf-NvEk&Kn`<5%m{}5>NZN9%k816&h2uh?XEIy2lu25x`iHaSkdkB(! z`?nJa*h0T33Z+sX0!pU5sNv z$f5QJ6}qjmYR?qaJ|bbOc&%EVi8gln_}&AfQ45F}by2sM=_tiC1s?Eh<%0M>|i2=4w`1{;GTF%kB*| zUu%eGRanFjtmRzhctZkl0_69r^B~e$%U3oj}x`*d7%tI>|{QOKqD_^hGn_sK-e5lk%k|N2$ zo98kS)j>Od?a&X8j`nX$W>z0BZGdE~6}PPcop>C+p`oWK^n$UYVM0M)vkmP@ScL}P z@YzbEgU%wAn(OOdl~r&#Ep}+g+4CNR4@olN@a$q|a;pdZhJY#|dZ(oqjhSQr;@?5U zv6t_63b@u|ztfy9%G2ptG=UhS(*T>sOZ#{bEMswxc=r^&O^}Uk?FlLI+b3bl@RK(Pl?>!RYBz$+@ zx_9XMI4h*Z6?&jLt@Xp-nMO3PWI7Grh?^m#8+S=2bS%b2_jMZUEj00+?~@gtiSEl5 z(xBSDwLH@ zdL7^XR{Xs=j`Nc-$os)ZXkzjHUufZ!RBt%>w)fMCo*8f!MyWH@wlSR;(MMpPU}QG; zxr__mz*A1}1+1-tk~aqaT{1n@q0&`RxQF1ydmco*Z<$V`c4JmHQ7c5&52aHSt$=?=vN(gwksZ>}M8ch7J#XEfJEF zv)=>p7AlpgQ{A^CoPY#YAq7QR`mf!BRNdUh%2daaXkw{FLb_2w{XC8S8iK$75~Mll zlN6$kBB^N{$5Kkp2 z(%IEzdTpks_pda^+6`6Fp@X?2ov`R!6(rT3Yqaw1-Y%z<=jGe8W_r84Fv{ZJMh#s} z1K@TNWCX3T_BUbpu}Hh5A@OK_V?(xHiwt9(Vbs~>&amD&7xsgHd7n?IEpa?J%)+c> z-m-?eYwpl8T9JgQi^m4Bc=ufQa5i44EFCwW{;0#L}Y+(@wd{BiIrWXeG29hC-uVjpw+m>Vt(QE z@S?o&b;4Kw6)H?MUa15o@JFRl9@Td{NL!bi5=jVNqit=~uU>c><_MiYN%cza z@Uw4Ye2g7~hwsd#$t)iW*{@ewH>W*OM4O8o381HY9nxMS1K%5MJ)p(#wLzk;4eN{i z;?220IiC5;LlaWt?y}gwOH|i+9389~mUxpi6&lHrD);MEZt#NOe{{@pbXoZ&o=vt< z#h?JV9Eo3B)y$9)Qc|2BQRm~fGHb-RvWhU#91Z7`1lC(5qB&J<-IFCds}E`l-HOvW zK!7fHjs`m`Ybh^T9Owxn56v!e7R*_>)sHD;3Foo+|vP zU$w)_V!?gQ(7;%haD}YPCSH*jb;m{@*+2<3s{3o|Lg z8$-8tuA51VD>jB|$e5?KT8koOi4-O3+N$%~CE*IDvhxWukXW%a1*oQjelXL}(fy9= z^@=ce55=JK>c3Y&4s4~6Zp`(~f-{3pw(Dfr*!A0%fFaj-z)0SV<<;$D^TO$2Ue+-3 zlg4j;pWj4phXe3Pw@mDBpX8H#HiG_W9(0|a#vYMKbwnhdcyJYpQeNXakFe*!~#{c1&!1(FTX$Jm!C0ju5G29wgHP z4}ekv#GqbxUp9)A$_%yD^dCv;hB%GLM9u`BONL<4HSOkiuCx}uSy10Bc@H-8N z!eW?YK@cXv5t#v+DZBb>yG1iQ3D zy{W5q}7n zk@0p;)95~c2@e!+SIg0AK(V%q_o<9Gi?Yn95B%2Ws)K#l}qN(CJ~{}q?EoFyACa)c=1 zEVxi}!UJen2kS;3BJG9RiOzr3XanvS-7669i=Os8efiy+wl;mYpZs=69931RNDn(N z-b7@>VP{qz7i{-~IO2StSx)fOeUJlHt+oiuR17E9{^E@*n>BFaZFN zLNpR0mETskUw3d%%COx5S?v>DT?=ashdVnqEKohQ97=Xi;*FH6BZl!OhDA1QJF&PJ zc`3b3dmyPT8@olGlmaE|`KO;B4-W$fWS@-#pY;PxT^+K-F(tci=M53=2~zbUm2<+^ zeAgic+qr{jwPwQO?!QB~NU3l-oGdbD4*CyUP}szCr|g#)?5e99hG#B3Lg)5Gy_q8q zxXl$~Y%61SxDMAC0+AQ>$t)Cn|f zf^mn_MY#*EL*f$1TtbzaTU_l}qFMorUjpZJTFq;rV<~D&mU)PA;>NfvGM|P$6k@V~3 ziy#P<<)DoTmBv8N>)--04&LduS8_UyZB8o0yx8IJNnp(uYoL12Ou6mm3fg05*hWoV zo!jkQ_)pm85;m}@pHwU(&k1a`X~gz$cD&#H>A%2(Q8GrVW$LA|#+#Y6XwHt+)Fa@uNy4)~XkWl7mCC5G&v* z=1pk1u4EzoQ8+2|EPfnRoOFH}Q|Zlpo1Tb+gG-SME>6M%VlTRlvh_+v=H|bK(lmL- zSOjQ9zG~=dmQ z?|4dPRANZIBtTkli8n^kL)OsJgrge2X2_^e!0xyBiWXI9Ky0D8f3d!OU%rxG=#;fMx!)e>N2X zKl`mQrVJxQ77X%q#V_tI$vmtRS;2!ROJd;TKEiK za8c*Oqo3ddH?V(@bzp@3qUsA7AV~}lIGL1F!4%C4Mg1SjeNCId%Q{XLY=zfp)Q6Ojx4!A%&Zmm-Ho>MeWk$AQUE!bmA zgMNZx+0h*(dnpu1Q6S)5iQub*Fqh=vH^E7~AMgC;4M~M4sbq|8;_q zdv#(P@JZ}hU>S04nw?v9I2IyT-yi&BRAwG8#RdA~S&hTZYM|&RG(4}#L1CR;WkW}dikV9AJ^(=k>p7Z)Ng|A=e#unbXy)2}bRP51n;MWX? z3rJ{pG%e9t+az`ze`|0m&->oVPnIu!yLy1g#LFnzP4Es>sngOwhu3(8&*{7yFmo`@ z>Sav&XJ3jX7X)0B1F1+O18A#>BOkNE4w@yD*d9+CtE#cNlwiZG4AzxrUS6teb*N>w zvK~H+UGCn9I5%s>J9QEyD2&`Yq$^kY+30O`+9NH}f}G`3@_I2MvZi_-5IdECt_!6S zi99uNJP zjKphn<#Zt%;>33MlGM{3+H(u^JO&fG$oX9d7yh=ugBmxnsC#)CKiNCzl%>hs9+jD_ z4@Z(U2yJ&)1Q@GtxIk5(6l$MiaxD^n&@%k!8?2pQ!(eUN?E;E zg>s1!WxP~gahFR+eU&UVzUCUYV>2Dm2W58ed@GoDL`GINek}hB_3`CBNcrfpgKY_- znX_=Q;a1XH$Ho74nJtbHBGo>kg3G|?o@L4`1Y(yfsR=bX%YHd*LYb`yIf+s^(Mf8w z?{2@`6ovAx8NwDX6mP!GV|lZUO5QV}prqjP+DDI(3kwG+l>hHCo0DT8qk|MJ8Q=_% zw2v6BR5*-PLz8wSlCYC`zT#swv6?BOM!)1Y33x`;2L2fy15VYeWu zFLwIL8uA8w`kIARJoS017#?OZXFtONHz|spZlwQC-_#qGo#v}ZW=EGqaoW5K{!dn} z28`o*ac)oR6cwI<=V6v=jc5sw6ip_mlzK2HPliFAm@ulkxkId0tpI~Tg1pcm4HJvV z1NsPpxZtw1t|5YWR=__o;6zZmhkD`j0bS*sIsfb;W=522B`!Mn%>cP&2T-K@e#I&Uc&C5&!Ge^b7dF0DBcklu_7nq8Q9}H3Pshu z#cCsCCtjy>6OIK==y-wf4qP+&?9I%$--TKw_Q$ud6{}kN%~*OlmCz05ybwD{WDSUJ zPUc9$scw;K*%vG9LLsnRm8Qj%C3{3);$rAf8%!?#mQsOK`xGG;8jgWYXDtpm_q%-O z%h3h1zs&dCH#-=oCNf2-wqkoH>&Jgbpa zRf6x-20sqg(hOw|LXYm?w;hsq4hZ{C8@tYpaNCLDIvW4${0KljPgS^>_ypxAi0P&` zdj9VuyW4r)p!of~Q?jP_QXxR9oLgT`(rej&Of5);XQU*Iu6w3I2o9Y$qTxA*=yY_oo7geOF!?|b6ji2jobxzsp%mjN;hsa!91Fee?P|!EPt=M zAueM1^0kB`HSBD13&fgiJu7LDea~5qNBzvnFz1QTUTKt$*>PdOjj7fcl238z9Y12% zF%Ixxv}E8YT3Q@JS!g~Bj8*l=Nuk`Tp>dZQYWoy+%WQ=)@(~5n(Y)E>ZE#9bCKlI- zlcpJ4_%c|Zxa0G)h|nbW-hhLdu4xr9CV~JAwbBtCZJAX*t0urt3pV-YX{9`)+^gh4 z*A5pOvng$UrSV6C7UowA(71N!X{Q$g1dDR1(BjFOI>f=URZVOY+tYlp?Ys-NIGEaa z838&?7F8WBG8{Q5+>Ypqmq!mgFu72H!3SUUbEtkW;E)wb%H*Sy_E5(fs}>G?|7&es zU0p5OxY7)5=R%j!_tbjWB2>Auv%EKAZDYF~lHo{PJZ0$N5kFTzj;^^)_R;6{w5;AK z)w!|fGtrR>;TXAs4s=*d-XjN`SMea|Jz%Q~lojrDc8no#y&k2}5QeX)sg-_k8WJ{G zsDc_oy}xfab5_^&FiFbNc^hv=jS=P5|JQ9La>zJPt9|@%kcyU;7Sifs)p_tQt9;3o z-!yKV__2%l=O!&UkES`E*^$i1S{0AY&psl)TGDX|pDc0aFl9`-5>hb7deqQruJsvg zPb!(K`1L=y+J)t?^WXHK<$$u;vcR~Gz;(B zUTybDqa>11w9GfJBbYvdueZbzk_@sV9A;Cl<6@={KQ5PpUYUjVbx+3>SIn*B(V5lo zv=4|T5agRE(4uB#;UH}5T-scl5E$8h{T$V3H*MP(F-)pRA5e49BPxV{`Czk>+g4wn zac;@1HHO&}QvLJu$l2kL}q7 zK-7t(JVY0JGQ?;Ra3Y{{AglDzPe1Ta8sM+*^WpgGV}orsK%xCZB{v%Jz(I#e zCRIf$f5BFPwqnxuL1CMvv{b1=ErJ3SB$_roPvK^__5+X(b4ln<++4Bw;$oj!3&sekkc*x5IdWLb41e{SOoID;_C%*aY zUP&(R$wF8)epEX%T*hJSwB4@W6gzws3Rbd+%E?ije)=p-!SIK2VSFge{#8ri_USPg84^j%(pG-N}?`xmwJwiiW!a-eII(t>S51omvt zaw&SKMZO8LWI1Jql*?rV2xTk?4rI?I7%%i`)ih*ep;3djaq_N}QSbf#vj74>`vDxZ zrC69a_828L&hX9d5cT&Z_{t7nj~~vOI=aR#9w>^jq1gxLtrNU7wZURZg$B%=jsLDK zKNVAK=M z6svC%?VK@j=Nj4YeS50%B5c_T^_xIgi*zfc*a)lMLV;MtxK8|lxAI(o8x?_!?8?7C z#!VXHp2^uU74q@&MqRWt!JSCd$dnZ%4n}a2NMqFrWZgI)X3qu@29(Q$0klnOZvTWwssm=7IK=8zJ@^&@))C z*>XgJX;RF*tiyKR&t%|ksue5F$rpZ^5%Ao0(8m0WPsjZpqv0_{14f-LA&|wLej=Gp z19|F+N0n;C3QaH-+m+{t<@Sal7}~<+?bUX)4J|2Ce)`o}>vzwiP4#mca8 z{twu)aRsLQo-mqZZ1Rz5UoGgY{wsPV(K_FjjqdX1YqV*`XfM?-OiA|1-<_UjurpVR z>@mU|;t&KVK{u94!}2IwPZ@dmn?;q_;CsZ5w{6-lSWAB4PtlFX(1IWBscEeqA=V_t zXFF*mVw6Q+)Ye194_$S)^ExjDhWA+9&c{D8Cw68!uN{^%88$wqOgN%)eudlSQlm%} zut>2DUIzZ1Ey9swB@}e{4WL!T#0Q?*{hl*cn;gFSBl&Hv{iS29w)dik%nWrMHro6m z(Qo|#;&FDnFf-z&C29>0p0ewKhP%G&tjIQ>Y!ymCR47bkRd zcGrR*m7Ve=*3~R1tf8-e=NQaywAp+vIR1+~H>J~Ho zPW%bgFp-$BN%jbFmIXm3Y2h{9<-ATLgQ#^8rS&{UGvelRmc0cG1uYTl7m6iGLwjN7 zvt`aL1dh$0V|+6R-lNw}ejGk)mnU5XSPRHEW9OfxLDJRQg-J7t{ttvfd%jrPW@1c2 zR<&S0UXXBihF<&~4-s3M!RK1zqpq`Q8BR^X^Hh0)KVS_i=p}K@?eD z-e7E~Kyht_yDJ-rlFVp2PBxQ43m2yn4Zcv{2$_Gi7C071rza@LJ{KQ6%d4-xG3dUy z{*Qlh)v$)OY=@YtlFejEBop|)i)%Z0o=d0G1xLWO?ZMyG;&FcUH-C%S6UWi}eau#k zOe%(tPsb9`+f~5F)w{T1`Y%fI0KN8n56|<%5!i6xOY(PrzLOC+Hoh0A7P|v5O~4I* zZ*+Wui=*S1mPvVQjiWO`8JA4Nu=Nf{rpEZ@x4y~ko7d3$CflobNoR+dIevmmQD)??L|C-Ful|<#LTqC;0af zqfNE#g6j`-_x2vmc8~7uJFF}O{dNZzqi<5Ll!?d^YFx!MY-CA7KtPmA0YK?`^g6A< zC2!ViTzm8N!5o4li+DanBQl~Wu~~k7pHj>Hj*XR7it;ASMja4{Mx*2_ZF;>fqUdwT zX!yN%GW_4+LY8*D%;t89LMR;;izgV)XXx|{Y@>&+dt}lXVwy%jOmFXO6p2J+W~L{| zWYbhDHSW$Wyydy4(iyCfUH9;X3w-+1pW^X%JQfUDnI`k|3;g+?|0OTH^a6&_N8i&0 zG4wu{UVoLXdhhU?jgh=bB68xNMO5-K-| zLTLW!xs)3_65+~#N8oxsni3y$CM?UM-|KPg#BolZJdJ4?e6L<6u0-jX7N*`q3jw)G zwTa$0sWsXdmd%-Do`)WO7{_&)pSwl9R^{^R8+1xr_*YTkiVlT>#?}@KOC_$~oFkh{@e9v9!f-h9>$?6v;6;`r18}ljsc?5`o13@pAW0%W z|IT+%7|tWg(SeNfplv0Hc#a36K(F6racP^Iw{9Yc67PKU0nVN}5|lc6aPv*u30Pi& z6tv0&0n0qa-24i+Z_ndLYJF+k0uqQvx(86JP)F+Tg5KjX9i>9bTTCGf*( zKU?6^kAB1x?|u)@yzc`D0>tAnWUI}s+qa2lhxqJg|C9@-Pm)Wjv|HWaUhZh)g+eYn z+?^d2D_IhVL#*jI?B_V=GBG~# z%z3W==oN~U>OkBv8m85i^ou-Nix|OQ4Xa;o6FFs-#bkw3L^i*zxr2v>^DEjmZy^xM1Jv+2ayq}J38xDhtq0) z-+O-hcYcGFUBz?9a~>F>F>#+dWOwkeExHsm>$D1 zbyl~lw5!|9uWixm>G*iWeSuQB#wDKzNJ3y>O6Y9Hu!+G^jDJ-MGuO8+W;Q{uCD@EOZ8xCFywb%e(fp?3o8gfED=YJM9?&qvGF|FTnfDN zG+SLZi&Y%Q#`8TQ5s|q&^St`<8~6kk*XcyC!w(JT86GQ87|Nsf`)qFq?{h4Rh$K?0 z)_DF~-$RS5#1k>1QJJ`=kVqvNn;c?da*|jwhizH7jx!i*w#&<56(munkXHwhdGhE46QePnd*L?C zW}V}?1e>D;9LvCusUS+|hDF~nNhK0I_4E^Ldx1WF+cD8)hlCVG_Z%{kO405O)=59& za#GFksZaefH}BkGZ7Ud>azhWqXe3H1lSb1tnvDiX4w*!p_2L$e3lUkuHZ4rk!1V$= zBgm{mF%oGf(nH^N(M@mPIy7`0UGHO=29b!2i-^(dkQ<+2d}bEU^H{h$$IIV)nTVob zg&B?@2HC~x+B&Oi>jN*r<@K#SYhA>&OuqcZFAZiGd>>rT!!#Z8g&e>B@lTP-W@t6) z2)@VIX_<67O|!HZ;AID%CtvvSHT^C#?*P-*7w(fd{P=S7r-JJ5J$~-JPviSyNU89N zL^Y*mb*w zk|YXfF@<;{MmiPWaRwuuiIYwzNv0CJ^2>+#s3&7l{`ddo_lPPYmF0Er-V|}2I9nS5 zf#mkw7R8Rh$3OloGqW>9L{U`Y6p>i%K>4%ul{+ zmZ*9P@R0In_`}bBk+rpr0ShiIDYRS@ai;|Eq3#%@r2V}3;fRKaz}d6sn4TEr%_|4) zSvZxM3%ev(74&YCWI7$vx&wQ)!9(#Dut`D{=^EZWwDTQB+e{|OP9Agj&K-a-?^R81qQrK!~ohDSo?UHDl823B}| z9ot|yYce`H%juJ2yyLy^VPj#Dn^*6KsCJFvBq&i4B_d+zJq*L5Rd*0%g-jN*X&Fz5 z1dcj5OivDx&AXW0Hd!-=kiw((UzdT%XNi16xWUOA@~8 zB8eei!1ECVcVDdXyq(Qk7_0*=A`GfmS(Z?gXyDu=2(+6G+N}=R;Zbtg1d^;0iADx3 z<9mG}{C(KZJ*n-E+OQ;|Mx&TvS?hVw>vs9uuY8F_JQjk*L3SyLFqTygMC1F-+5111 z*mp1Hc0eEFFbADIKlzEH`a5hX$=!>zyStiuu6t;X(C!+f5-Rzj0-0Qfh^mrECdd^= zsPECFHw}xeVvSrb$;4=y;hch-E|82zNM#GO>cIq>W#}Yg%C19<<58(KNT)PLhf|D? zXEAz^N-1Ot6KrpmaLphhsA_Z&p#)K+T&<%hGGoITj?7Nc?^H;{Wm1`88jUvnc5{%1 zMwDGlqF8A#GLvL#JjcjT7AYd5L~_Iu84O#dz7=#F+z`MNg!|Z;?THwI7$^_#i$s>h z&~Sz$CugwrKJ>Op_icJ+pUt99Zgdz)6vzz~@En_sjS{L7MejPy-CjhADMX?QL$Wg1 zAbsEE-~QphV|`Rd$c2p{c5Vjo+blrU0thj_G(bad?Qr|RawVK!==sJ{+F_w~P>V0$vW{-^z*5-he z^bdGkzkCJTwg;}t@i2>d_PtLWn#ujN>wNis6d}QXE0q86Hwt@*Lym1@8o@jTD(`!Al3u@0 zCJw2I87$L8Qw5IAjv@%qYt?w@!V$jx+B}&|iekgy|M}zpkKg_91#k`?Wau^%M-Y5QhaNyt zBFGVlr_((7)H_&QT*c`31_Y6A-{F7!pZ0i*RSwj|I7c9Pks7V=(rYXStBY2=T~?3i)h@qagA2bq}Mk<*ySZu zD^+aUp;RiPcRJ+9l0>6XqJ9*^FwiuWSX@JC$(Xu6*m%o*BjhEB`)3T?!DIuPrjSmh zkR%aF5V(7Hj!vtA09fHha(C`dfFIa45m{n5snF3a+9A(jP|6%EyACkocJ{bLBE`i= z9_7Zh%hYNOJOrdj6d~-&=waFC4Oox&=jI*Ge>z-=XTYrW{l616=qDEO50)`;B}OEc zK$P~!_Z{;}C8Cmyr>WPQJo)Ztuw9o{tI73CZ;(|Ll8Qj5YXB;aV-L{qGbg9{wO{@K zLn(>;_!R4lw?m>xQ0M2zr%|;Sq9}9o=5CLAYP`TlfALv{(=x*|$Ea+s;rreIam|ke z9Qt@N#r(pqnolem<Plr_)HHj2_PI?{FXXDim6d&*Dahk4ehTs;c4pE{3k7su}|Rz#{D6as0#yPMtZ$!u;*GkqrMMsPVan zb1xj)F617@-ocu~zo)jaEDJa6@VdB2o{t!|?F0lwQN%QC`ntgrPd!BUyK<{>F)!HP}0-0>Ep~Q<7blt@0 zbtx7*xN?Ga-@!K>UViNsqvIpAn;is1DEEm*9aK$4sW%ZM1=DIVf2)QsYBahgf+z5U z*KV*l77o|w9?&6~N}xnlqOBfULO|~|xN~y_PmEBnH$fEn)=QV!ZUl=;Z#PLKlc;JC zA>(n8cq)o*8Z>JaHcKr^r52v+5m8jEu!a;o4^fox5vjF0WaD{y^&U*4{Vui;Zf1KNQmzkem#PeJ> z*H`(_hd;uZ*98yj@i@6z6b>Tgx57`j0N zm0GpDZ!fAeJAC(*n?$4Yfq{qX@zi^M4&TorN&>p2u)I{{jURq51bu?9Tx<6D@^fz@ ziUH2>p7(!{SRzHg*(0JyQB{##*xpU>;qj-RCO0&~>UJAV z5lAE>$X$=Q8w=dHd~Gna0dVcs3fJ$f;rpN}D)0NqFCken{a%-7U&dUo@%%Twiffrf z6q#Pn7_^giX^eZAi_JF2$MdXi_Zb;W;5r`i0cDrfl{J32xk^`e8ObIYo(gyXy-t_4 zQt;4Ej}_Ri)Ts6J!|A!|L6;y{TA1hML;}Nhc>Li9Is3qAve^uVu5)=|fp2{4+uWI7 z;MO53#{gF@U1o7<2}M!K=W~n<57TV5pjgAUY-CNL-R|I6CW%Ch_dW9-biIGi_^I#v zXt5Zbc87Q(M!i<&hp)Yk?~9nWyH6+Ye#h12D*xMOUZdSJX?69mT_})_h0~idSe*(F zUcAU~xZ%I>+_#yX8N=;ubN(&rqvuBSs>)mWvikVESf&TlhY5L?#wbB8nm-qZ1*$ zI53d3YzI+_hV)E-KrQt=7uR+1mEfwmo{KC8=(Fd!*dd|DG@a1sVy6ulqS=Cr6bZE5 z+I<7p^{6)cB-Ab-(Kmzd=SmKlxP~aoOidlb2&r!EW-yFmS~jV;!uU{{R=dUPi(4$O zYz$^Lq%cC;zK>y=gX<-P(bei$&Jg*Lm&I6;wsVu`RZ?HdtI-U~X;>&vD4- zvIDeP440f~yO@fxh{@v?o*&%T1AY6q zYKz}5zzg@I=-mf1_{rD!VI7mn7icxA`|9qPrr>)nf*_F1XDAG12MbG!DQL+wt&T`4 znPPNQv^p1}%lXtQ3&b!}8F77{lMI_+KNSv0CpEmz+1d|&&) z_XDf1oeeE)uD0p0>kQu`Fp`tsi6l?T){lWC)+dYcg+mwr6C!5dn&|~kw^IY!Syg{k7 zwQs}vyB>p1g&@-Ebb0v)uV6bieOvcrs3c7Xf~R> z@WP9H@)I8mnT91&LsKXr2GMHO!1qb3B6F8t8*D6EGMEvFL>2VDF|b>2wsm5f%84^4 zIseWXq_>fY{B$DzeQNdHo#o&Zp8w-%JH9}rQet%>n9KHMk-ljliXw(-qedn01P6=+Vpx|BuU1$%zNgUqY;^Z`a8cxsZ`|ZmCLMcSFucM@V$3PG&{hOZgDH=P4J<7^cCo6DO#Js=l>K1y$1+pPURd-Rn)Jj!d(< zv=j({`1@uccy5J8G4AjtdHkt|F6@~3~5<)sCF@bXJM{jT?L;`B*A`|tk)0KfCk ze~+8juki8G+P~vUVngWE3uu@L?9Bn5$|-V z+%RK^hFzf@ZNl-1Nggf8LRfPx7KETZzw@N3KXvFt8FElXhD2Vpi05Pc$1nR2N#sQFb*3&bGW zEt>T@ilPkW;T^{tfMJInfk6qo?IEDJx=2?y*sL}%aU#^nRPQwT&=q-OY^5J?+-Peebo=;=y`fx%opX8|&zX&CwIH zKVt=+w|ww-Y761;9p`@i`#qdu&#`fL=InhrkVzbfO$0Jq^;(%$y+*xSr`BpPf`B(B z6HkxQX!hvq2Ccr097|E{m{_(&v(YA>OkkTjU0p|26`D@CgL@*TW#Kp$5hY5wT){B( zU6mo9+pJ0Pog z@hrX&C7y`kiW(7F!B>L0@tvA-2a{_xn=H-G(`mPP==@1)eV24fbR2B6#mVDSfda14Vs`d8 zOG^tF`u%n2dp(^OpL-79_wju%0Gb>J&+`#QfpV$LbY}+1`6q=?`tF>q}J7h*&&R#f+<2aOx>j?M*qR)Re z!Q~%c#6LXM74GMbdrwoq$961SXICxO2}Kfh!$ehrowD6&)2i3;U5{)kjVy^|#!t}h z_mKe?NRQ3Zu_COOIvkxnK_Z?YqAFx_c`n~x;q>{*fz{LM;sTlc5M#$r00O3AAYQ*Y zP(6_)k<#`y%S+3A_3Ph33(;g}N7S)Y3{!E1jnzd`p+!?v(HI%ZQEllYV(OsHRyPE| z8l>i>%?(`7#V|}_sWhEdhgPY<_UZ~pW~RyHQpCLumltb@qQFot&162wdSwfc@qHmM z1r4dbk{sE0{dea7cfODBd7-P1voADw;R0*6yZa)o?fXR4ILQ!b-5o#*wetnV>3J;T}a4^rCLVq$EZ zGiT1w>vXt%?JAEw{wN{>b2qLd0S`ZXflF^(BAdGgVi>{s5+v56cjXJ)v0XOkx$JN zN$`m!GxRzzHI+b%B@i)bnF8@t@OL|v4xZ0H+C!FPa-jyk>v^=BtslGi_Wo%4$T4io zAelm6?1mfT_Dww38<>o`*x}+62K<4Y$Sxu=J#z%d zwwXP4j9ei%F!oTC2>JXdJ-tu0UZ+wjW4kU_FTJ_{e(w+bgN#CpsfeD&!Erv%%aE&&vz4U6ZDP+?4p1}J*_(5)7djmld zIdOcJsbgo^+S~$sZe71ZDxGI$B*A(^#CLbR2Ym!lz%q0su}inM%{RWdgdKj*)2EIF zS``Otb^maM3*nyG82=w+>-Y)w@eet*upTlDeNex3yFI$0ubL(uIXh6;J22m029gun9(dE~y)Ns^%V-jmYHjMR9=c)C zYPLvavW(_bKK^TuQtGtWE-GY)Mo={kRa5D8`xG}fxOVB);JSp8GgtZy19Ip zdU=zfvB>~~&>YIOBDwr97an?qTD450-q`ct|M)}Kd#o+qB9_RreCPTgtM}i6#96CX z`TS@91n|jZvP@4OVQ#%dIyV-Og*=_M?vu*o5G0A4i#3R5DC9E;i))OGjUh)On6|@E zJOLr-*f&hl=`_V+k$%5NAyo+ey|3eVKKY?xsFbPJ3?gyJI-`ZWH;f6dvcZ*`F zh9oP&1}jMPx@|h`CW7yih{uVkS)w6Wx4OJYvtHx>Z|}^b=n6TLd zFc^dkNPq+wNgxTdwWMyfy1RO-uKm^a-km?*t5;R8>UB#XAu;s*r={+yx88ey+xPeV z?tAqlx#>9NQW-^2@LSn_MKPtu3>1W_+5ob#GZPewWulkT+@F_Bws3IjiN-$uCLL}G zxqOadp+q%At(-}$?1E1f|@>OdH_6|~>OW>7Rq@1K; zNb*I6qVVDgg{Wu+iun?Sd>+4**UQZ%F|ui{P*e(91+P~SjfDwCBPgmuM`t^oT|LA{ zMu(vXAdQv=1o_`j)L`Z1gl9k3zXrB%8^S%jQ4|yDo1SIzFEd6MAmg57wi4P*pD@ z6KUd!*FdNQ!bQeT57XV-OVRRRvbiLP`qo`xmr8{y=n~$(hpsF4UhR(9? zPNdJr{CtA8wl*@^tW!q8#=mc}dqqM}oicodbV9{&mL?d^1RcXMWZ4^QuS ziq7tC^oqgJ@BAI*a+$8~ZVnwCWn%nZ`j;&y5DIa8^xr6G1uFqO&MTIfsL$&sm(5@p z2Jv{D(X(?53=UG%VeN)1czypq9(wpO3V97p)0jyYn3{-_nornOj<(KD-hAx{g=7+4 zH{*K0x7?7#Q!G-@QpLdM^U%>Ds5In5TBqe}4uEjP_-{W<5b~nd@f$~HXFK6YhkY-G zt}``q7?0AJ6iTN|mo%Tr;tNMe%*}J(kDo^IMQvmrK*6EDI-e~vdNxJ8IEnC?DmCq0 znoZf&+0}zD7(vst1)1bkvKDb(=P^Y4c`VwI`QJtgFyrR%U2SgIO~`T&9KzjnHe6s_Xo@+W-+9JQb+n~GaVT<1m*1142hXp z#?OwS`2pWHWOnGjK)08|$WPMGtN5u}d1?%ky&eW$T@&iG{b0w69n$VyG}UxQd%^{1BZT zF{05h@yRhFkr*Qr2}-((fl4?Muw7N%&{?@=h{WtHKEIF2=_I{<0o#H=4gOo@Yp)nO zx)jW3O9TQch9Rj`D(ICmLI}Egd+>*%7*aQ5eG5oa(aQ}Mu9`JhJYI?=9goigQrg&c zy<8!kOp&p~F@lj0nwCSaNOIX6zJMQ92~#PT%#JW=DzrMe(yGiaRj6@wDJ!Z%dsmkY z74`@G=+d<8W~E!2uC+rhybA0q>t$xAXKW-{$%5`y&*!B6u5!*-Rf4M+cGb%6f8zE} z^4P!sJIneu*vZoPWSsfgS-Lv92(*Q{YTH#*$`!^&NBH8Gzr+Lg-piSh({@(3pcPT7 zee;H?S=hgAbbf4jH8+&#=hm?ku;88$Gn_m2U z$K1>ek3V$33CFboPv(Z_^Z6+jwRhAyyt3zcn^Q0`6(?x%)pvE6%sIJa%1lsNvG3j& zo@LfzuQfNWFm16Ix*;iPSt8LWL4S~hQqYQoDnYW@92+-nM3*|5WC}&~U`R=^SYpM>6(&&1=VjlEPq*}dF55c3 z)A9=k379idDHT%`b8{4|Hpi+-Dp_^Tyv3?p#lq{lYQ?w$pVvdFSR|j#nJyEcTUha` zY;`ruZ104IL0hyPziL=nZb2jxG3(vZ!0-1_EaVXg6P!_XPz>qVVJ*v9DG>~XQPjp5 z`kuRgksEK=&Scz-^+v|W*|1?P?VVlreWp`sUf%mELBEH|u?}wh$hCyRQFiWpk*9XQ zYAuKWk+7dX{o_A0LzPsTY{8&V)L6HEof-Q}9Ry5IO_7>UaQ4h7-5oL3tm-GHmHGbv zeTea?Im?pkTyynSzWUX#F?#w4XGTU?w|oVPQ9&z|ZH_uaN`e6o`FxH8M~3O_?_|x; z5N9W5x$nV8Nmw8n-GJZx@|U=N`(`@Z+Ii@aogCCO3I&ZjZo7%Db{_}!AK;CXN!p@q zbcR*#`i)zd*L0S*UynwV!J&18!ZBj8Hi~5(P0JGug*mwI=bSq93I`6pVfO}9J+P|S zgq=GQq9uZ@3Y@7zWvkye>MUq3o3rPO;Q-E5%e5ZsdsPg-$A&J8hWRuV0~DHgWfgqH_G`8w3JoP9$I@pM;`v;>a6>LqT*yr;aE2qx1Tn-|wfbqmxKm2VTD)SuWudh8q;#bxg%)SiVxTY=9t> zN)e64nkK-4k4!Xc*+rva=4NLAl}IGQvrn1ipSOH`fQhqb>FVxcEScrmoiFgw4{ae( z$&j0$CY4N~m(q3nr$I0fpsS~!xtTbfu?|w1DV}`nNxu1Ke`NME0O4?i{ja>nzL)l} zWlcBB+d5G4XNY*aXb<}suRG$}HLF;;yqE5d2-jY79p&+13iFc;+;W>a*`(=ePak@P zT(Zc}tskIm#cIm=H09}WVi7;}l=|6hiv4?cbL%a)vhAuZ030~5kL%vIo;8D=P)RdB zcZ$thuANG2hgvlzV!*>FVtxk(g&{ z{4B9(h+nz;6Fk1-WfG~J&ApaRWh{$r?%dhL6usdRYu2se)GYL@TFn)kw{d9yA>w1F z`10@k9svLPkAF{ccFK-*?VaC3$i?HPn;HuF35EkGc2}8sUY~_o&t=kl^JxM>FZcZN-KMF|NL1F9&6@fo130udTN?{ zP9qi#QLgAVFRzx*w|pk`dSt~?k@S3$(bK0$rxTP7otO9QMgW5=ma%oy6+E~5*>fm+ zh?aEzS6;mxLz<|(ZC72v*MIw;NzR-1kh zqL@puV&yWry4(5vum2&F@fidP)A8M`SiYP)fAKRsv*Stg9GZdGrAW|bl_~YIBoK{a zjGSTRo}c5l%7CTk_HY)cba#-=X{0h5>0HsG@)jtnk7y)@#9+m;UfSDMvtek6so6By zyhdBZPcRfA81#|PWifP!$EQ(^A_FT{p!gD03_tlLq#s*5o$47t? z9P(Rc5^W&^=geY%X z)y2$QieSLc=JhLyPtPzhlOY%kaKrYEJhj^-`X5@^MJVXw=ZDN>-}A0rxTNA)UHGUbL?zuGsS&KH?Y$Pd&ARc?;3z3;~2gpv1^ZLl;Drj1sN~ws~ za`CWvGh{=Z7b$6L3o}>9pr|UNBWIYMowq#-A>8i7j1*1(GjL1khb-wG38RE=S)=R+EN?Bll(iALBk(8~w5Z=%0{ zfR|r8#q-ba=IEi<`HOG;0h!s8?0xxlUV43&!GQr}W|Ck3%;(8w;yk|lFlo<9`j!o_ zcKt@mr3(IF5M4KjwYT%wgZDEtdIUvLY^mvLZF^*59>wEDQ52?U<}K^)!|x05+Oa9S zX)2M@NTkjZ4x2q1PrvYb!(-iZ@C>TQL!ne*-y0*goSUG;GkXr%y%5JorW$evyI(y8 zDENIfPfsW+KEIb(EXK{B{1l-`6d_bXp%7l5m*jkcryhTV^xQ1J^O=p@b8{aaUl6Ib z(-BGYpTFp5S(lgZ{$$*0R~OB7dsj>U7TfO@j$tn*=bm|?TQ_y#^>|5TgQ)F;=(#zH zl`cx;JXOoDf=?NF6gxFcd_~x6W+)0%3Z3I!R}n zv+1!&nBV%^SLy2MC6~>ks<30n)908NX&i67et<$=<6|GbhEO=jx^-*Wzkk2|_uk%i zVzCZaUi|toIWf-6bevGo$!;DIpf4sO8birIvTR``MicU{}D)cfO->$0u$f+R;xsm7-WGvUA4{jB=LIiCGef zc@FG<6~D|=$j5nX=ZhGMpMecl(^Gtkj*fQHnLMFT0FOsy-qJ->6va+DzTFWDhD;#P zMHq%*fNEan(E1_zmaR19u;%9p1Ouc~N%riHvNBTP_7C>pkFG@YeG=jC1U*M({9*3C zsmz|&5_OCC5@z<_noPC}(#Ww>l}ZIBr)KC1OOO?$^dJN%RjDP#ZU0&%wBwmK z5!oVXtxPsP!O-ee-1dFn&};rk!vjyrEb2$kXC<1Am+!(E@hiwEz22%kq`d4C_9uUN&<+O@p!!U2X)o6I!A za$~=6&*$jt@8sx_V@yuOdGpQV{Kjv7nFsHGm~1x9_3yuyHEV}Buzx=RpO?XbKCa%j z5#8|c-19$2E7aPEySuu$^UgaN8yzN>n4^@-p!au>+`5&}>xU2mCe{qW`XN*;hoUHK zT(^?#+pp#5@F<7hI8M1-VLp*SRTWYxvmN%yXI@}g-wKMw3X{{b{LOdnH^DJNK`08# z^UE;wB2T}tmqMumC``@0%&U7}#vcfwP-kS9JURghHmaz{hX+1s?jz zE_7XI)xdIA_IL5h{x=cA;Ip@VkVl_yrirH>^?Ut)JK75Lq`3mi^ zHm<*VE06Dd1;5Y373&5_XEU4_nI;+uaLwi+o_oop!5-{4jmqhX6ro^{Z5x(zd?aqm zaY+mespC;hrrzg&wv*289=tw3<#LIlB^N$7JInT~qeOxVp6=`L#0D&ntQ+b7B<11n zvw0|D@ha43_1_+o&Se+lXR}H6AKb@^4uwzMRv;8Dqvg+l=)~{O;PXs!?8qcD$;KFO zIuQhdzzoUR1mi-dRN6=`lP8nYFbvCC5`uhQt0Cf~L3_AbifI;?KXrP9zxkj4h$1Dq ztj1MWZ?+SKrj_nw z;^)!z5;xv(13RC6kp~}on7{h#KjGuI-bkrj#_RR)Pv7}hhL0ZR!`oJK*R8)wz^|hO zx;c6DD96VVw)^(EyFSYozVOQw@_9;y0`UXSqvw*W|CP^E{Pb;R3>plO-1j1CF~v8( z@q6^I-AE~);l<~l=j_-xGjlaG+i!j4KXB!y^{iewz>`1Q!=XcOQmJTs<=5}QW8^q; z^c4HwFsaXm`r7&2&9_qaMmc!&G|#?h@f+kER@k!e)wW`-P#_oxkjtAM&O<-hWq)*Z zY=Vgi(-qI;a{Ty-J>>JImlB_uXKucBtuO6=lTx{Ys(47I(mc24pdD5n86G2VLC5FQ zc@DgB+WuaAE^oul^P0x-kvKW6WK)F!WKua&$qYrUz`mDWK{skiY*kS$q0I`qZt+dj z=`;#escUmHI5RefUMZq_0`ImMU!Idg5Dd1_9_!}yy^Upu{36m2h-FBf^YOv%5D^XG@ zm)Z4Z7VnwUR<>I<+~CTUE4btK+j!)W$JwxcBWuVaOmdb`-M;~5mytT;%c!u))kKq$zoC#HDe z^CBUeDUN##vp)JGKE!bbz!ZDP!x(K>$qx7c_*3CY=BNx*tD8ZoX=P~2O)D_RQV)IrHY9J z6e>b7Z0R>C1X4G79*&HpNu_fH=3c=QS&0btBa2g1;?I)H<~eja$I09a{L-&}ji^P) zBHar37rC5w(JX#27~x|#eVpOpf8d|)JI%2Zb6mfDIUbMT@ZmU5{%nL3W2Hp{SD`3G zJNxW~Umaiie@t=ikT-MzH6nY@7Q z%RA^@eFbm6ae{n4Pr%=r)9%n=GjUf1bzJ+wkB~DUvnz8<>P0OiNbdDc*kz=Rg z=!QD@rKP()Q#iUo~gu}C!BhL+DGLY=JG;^W~5?n8(; zv5pSD_-kLKy|W7;gavmtH`(t$@Ka_c&N3OFC7sFe>tFi@f(pfQ#muKjNu?6ykv-s# z^%3mf!kwSH9*;MGrWJVn;fI=H%$!z0RXrCh#=qF3QZ5h-h1ve04>LDA#etviZ~DxM zi5w67Y>NN*89$=(zfnUS7^M_?KFPz+PI6?t$Zb~-5(u_m(t8oDy7S)lzEk(bn?Lqx z5{YSk{O}_@x@(3j~O)8bZ=ZO%Cgps;VZ%>rbc#?uvvMpPwTtNWy$t3^!FaJPCXD2t`coTZ1 zgb*ck!{CXhUm_f8Ls6qV@S{fwgu(>-dpWZIp#7w5nkL(FNb5SwR*V|LkUI0J1l`>| zsH)1Dkx{bw9H5ZS7BCE1htv`^fRK<#30kqp;Of<6G8q)bgrg3uUS%c8;-pGYES5k> zQWYJ9iTRfG&E1BHN%yDdcs zrBo~;g+!4GimEa`F^9+Fv*(+q%JBi63S#xAR;8`1`gqk7@Ko#Fz6MKK^(>^#JY>EP zzc*@mevLgC)#Dj@rD4L_2u@plx7^^ik6QSOvC(0Y^C^2CR1HqGD)PhK(@dwzeCCE; z`a7pdX3ISJ(hNV{mn0Yt^V!edWf?p9j>Ph+k$0(ZtD3=S+KJ)fk#vztTDI1SaYfflsWzeNnO0t}xbTZBK)RcKI zs>;yXA^gFhMWk7y`kI-Z;>0nFF59a&0H3VKhsR^kzhVU|2L}Lw>QT)NT}ocryVs&F zuTCtp2SLkK?D?iU7QSIYxZmo+H!8X%xn-Wx=L?+I!nc1~3*YNi?NGETxn2+as+I!- z0gFZ1r{ec0=!T@ILvL>f|LN<$%P-#bs|_35rSNwIoDXvEV#grP<2TZZR+B+vV`mW< zbazC_xCSJDDV?0dK0YTh-Dg5-I-p8~=@CCyvqC(ZQQX&Ft>bKo@zf z#JB$ZFS+{K>j?%U6tpacG#ZE|YT9MO#oaL%b}$$=Lyo$vt!ayE_gPaXG8aNa&$VR~ zOk9m(Z4k1q%va`*3*mh;ThMaUPaFY|Dfn%_)N@f^_N$)1HNlDG0)$`D>@#^-5 zAg%8jjkpWz+$L*OhFmVyuwmHOVSm>YR}qRrM|%fbuiDPC6>Bb`e_wmG;$p`57i+9q zJ!s!as13UNS2pGrEY;fTO_m+C>fYWSmMvSxk)uai)PjAiUb~K9u-YOTp`i;&T8qK- z&fOpwb=ML>a5*rnz1xRLn^|@Y{(<@#Cmi@I>Hd(H##@;oj%nafjkVi$tJb@IBDBQEG;&5ZPM12Z zhnDY4G$A;l9$POg4@}nOTO1QZUh>u6@F?DXlgecA5FVltZysPTMcNN`yy9;}vnnJ5L<=9b$kPDtjp5v7W>Gnl8y#N=B;Wi=M z*1M1w=E1&e*ReRS{jiCNrokDnf1c+y6P>*E&dYH}#tX;kWJ}LfxXsJU_I;b)iNexY z8cX9n=T9}e`sZ%4FN`ZI#DXSM2xsi?aP7poUY(0ZnZqM!)+?7SO@-TrE*6tl?FPx!S>r|}M!n?j;xv*#A^c*jr z+)j&?P^;)Jjis?P-YY}OOOV_<_kBvVj+unRVmb{$Q}VBo1-Oa--x=deXKrROOWc}* z$SoJ(9_pTB(#h>(E}q5W7TT%W+WNYLTTa6T*U)USotNX_Y!vdGasbX@IEfQnExd5~ zyQ4c!Iy?}hOOEGl%GJJO_PyD`mU7ABFO8+~9y9mm509Irz0@&^okeZRp0=E7IXWNtaZPV}3Yu59jNeTr3lQ zo*5x~-Yso`OJixg_lAdaju9`d<#%%WN!RSV%ho4gvFNx}E})vdH5{f`u`Q8YIEHPN zS#h_&O$sUkx9qfVq!=7I1}R))yjG^v_JD+F6@oYA7-})O8(?LTnB4_ngHtbFoS&r= zZl7?>n;P)PS?zJld0ZHk+PCVOU!afK_q=5Bm&Vd~&&B!j{ImL(Pn}Y>~n>`>G7f6Z)V{_N?fpmNRt&=3O33=B# zJ1)-^7Oj#IyW@9dOCwFO8+~9vVWLo8x6$$A8;f;$nu& zr8&W-mv_YaI6R$Z1J(NPuAYZ$y?C)Le$h&;i$k&4@m(a57VVyDokVcUdOI=ma?#i8 zmWy$5klg$iho>T3EV>X2dvcfWIyk>(nMDPAYgR&PY$)wJjwh)=mN;!eJ0PwUde@=cn1t|^$h&n;#3m&Vd~j~ag6&@XI( z@%6Ra~A6X zaPbIaBR)bdGQFHt16L349iEn#8p+>Og%e^a#$Oss<2^U38|uZ*>R&FsOXr$}Z;n~r z(!35!=FEmGZs(OQF|V7Y7cSp(TGZCn2j|X@OU|Q-vB<>|yPs#_>s++R&~zD&>v8

3O;$JOBS+K00R{!?~=xr5Jx{ERFYIe1BdR|1yu=FLX@QY!O{7(jo{tH_kv;&tlPj zdRHHA5ewmFv0Hm0?iNNY`1z*hKDWD)=N5~)As^4z0>1lf`vtlq(VAJv!_rt9OXEFd z?Hd-pt4{YK>CnaXy)Vz0-`#FXmz~n-@i=XrTU}Tz7~8v9=4M;wg54Kl;TYNl87Q4y zf?|<3CKtg!G))(`+=a7me&L|sE!Xf?s|%OAZ*abjbyM!cxn5lkv=rknjivFPGy7Gn ze!V`CQ}n6cB(&N+Eagw(y186fS)ubgTB}`NED}e*RZCJAD?6l_tY6tz((F?Wuv4mv{z#+LR9UdsL6ea`cJ#@-Ah|ANZL*`DmvS4*}9_fra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + uint32_t exception_handler(uint32_t cause, uint32_t epc) { /* Unhandled Trap */ uint32_t mdcause = read_csr(CSR_MDCAUSE); uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + switch (cause) { case MCAUSE_INSTR_ADDR_MISALIGNED: - rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_INSTR_ACCESS_FAULT: - rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_ILLEGAL_INSTR: - rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); switch (mdcause & 0x07) { case 0: - rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); break; case 1: - rt_kprintf("mdcause: FP disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); break; case 2: - rt_kprintf("mdcause: ACE disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_BREAKPOINT: - rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ADDR_MISALIGNED: - rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ACCESS_FAULT: - rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); break; case MCAUSE_STORE_AMO_ACCESS_FAULT: - rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; case 7: - rt_kprintf("mdcause: PMA NAMO exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; default: - rt_kprintf("Unknown exception happened, cause=%d\n", cause); + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); break; } - rt_show_stack_frame(); - while (1) - { + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { } } -void trap_entry(rt_hw_stack_frame_t *stack_frame); +void trap_entry(void); -void trap_entry(rt_hw_stack_frame_t *stack_frame) +void trap_entry(void) { uint32_t mcause = read_csr(CSR_MCAUSE); uint32_t mepc = read_csr(CSR_MEPC); uint32_t mstatus = read_csr(CSR_MSTATUS); - s_stack_frame = stack_frame; - #if SUPPORT_PFT_ARCH uint32_t mxstatus = read_csr(CSR_MXSTATUS); #endif @@ -272,25 +302,3 @@ void trap_entry(rt_hw_stack_frame_t *stack_frame) write_fcsr(fcsr); #endif } - -static void rt_show_stack_frame(void) -{ - rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); - rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); - rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); - rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); - rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); - rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); - rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); - rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); - rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); - rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); - rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); - rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); - rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); - rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); - rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); - rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); - rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); - rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); -} diff --git a/bsp/hpmicro/hpm6750evk2/.config b/bsp/hpmicro/hpm6750evk2/.config new file mode 100644 index 0000000000..15a8df56d1 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/.config @@ -0,0 +1,1036 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# CONFIG_RT_USING_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6000=y +# CONFIG_BSP_USING_ENET_PHY_RTL8201 is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART13 is not set +# CONFIG_BSP_USING_UART14 is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDXC is not set +# CONFIG_BSP_USING_TOUCH is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_PDMA is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_FEMC is not set +# CONFIG_INIT_EXT_RAM_FOR_DATA is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm6750evk2/Kconfig b/bsp/hpmicro/hpm6750evk2/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm6750evk2/README.md b/bsp/hpmicro/hpm6750evk2/README.md new file mode 100644 index 0000000000..5f0624b48c --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/README.md @@ -0,0 +1,116 @@ +# HPMicro HPM6750EVK2 BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provide brief introduction of the BSP (board support package) for the HPM6750EVK2 development board. + +The document consists of the following parts: + +- HPM6750EVK2 Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6750EVK2 is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Display, Audio, motor control, etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | Dual Ethernet Ports | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| On-Board Debugger | x | 10-Pin JTAG port | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the Off-board debugger to 10-PIN JTAG port + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6750EVKMINI RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6750evk2) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk2/README_zh.md b/bsp/hpmicro/hpm6750evk2/README_zh.md new file mode 100644 index 0000000000..35e712a630 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/README_zh.md @@ -0,0 +1,115 @@ +# 先楫 HPM6750EVK2 BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6750EVK2 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6750EVK2 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM6750EVK2 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于显示、音频和电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | 双以太网端口 | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| 板载调试器 | x | 10-PIN JTAG 接口 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk2.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6750EVKMINI RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6750evk2) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk2/SConscript b/bsp/hpmicro/hpm6750evk2/SConscript new file mode 100644 index 0000000000..014c428d0a --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm6750evk2/SConstruct b/bsp/hpmicro/hpm6750evk2/SConstruct new file mode 100644 index 0000000000..3dadc575c0 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/SConscript b/bsp/hpmicro/hpm6750evk2/applications/SConscript similarity index 57% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/SConscript rename to bsp/hpmicro/hpm6750evk2/applications/SConscript index 7c742f69d0..a65aa4d855 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/SConscript +++ b/bsp/hpmicro/hpm6750evk2/applications/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') CPPDEFINES=[] CPPPATH = [cwd] -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/hpmicro/hpm6750evk2/applications/main.c b/bsp/hpmicro/hpm6750evk2/applications/main.c new file mode 100644 index 0000000000..b766dd547e --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/applications/main.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" + +void thread_entry(void *arg); + + + +int main(void) +{ + + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + while(1){ + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6750evk2/board/Kconfig b/bsp/hpmicro/hpm6750evk2/board/Kconfig new file mode 100644 index 0000000000..676f155d77 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/Kconfig @@ -0,0 +1,419 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6000 + bool + select SOC_SERIES_HPM6000 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BSP_USING_ENET_PHY_RTL8201 + bool + default n + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_DMA_CHANNEL + int "Set UART0 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART0_TX_DMA_CHANNEL + int "Set UART0 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_DMA_CHANNEL + int "Set UART6 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART6_TX_DMA_CHANNEL + int "Set UART6 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART13 + bool "Enable UART13" + default n + if BSP_USING_UART13 + config BSP_UART13_RX_USING_DMA + bool "Enable UART13 RX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + + config BSP_UART13_TX_USING_DMA + bool "Enable UART13 TX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + + config BSP_UART13_RX_DMA_CHANNEL + int "Set UART13 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART13_TX_DMA_CHANNEL + int "Set UART13 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART13_RX_BUFSIZE + int "Set UART13 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART13_TX_BUFSIZE + int "Set UART13 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART14 + bool "Enable UART14" + default n + if BSP_USING_UART14 + config BSP_UART14_RX_USING_DMA + bool "Enable UART14 RX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + + config BSP_UART14_TX_USING_DMA + bool "Enable UART14 TX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + + config BSP_UART14_RX_DMA_CHANNEL + int "Set UART14 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART14_TX_DMA_CHANNEL + int "Set UART14 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART14_RX_BUFSIZE + int "Set UART14 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART14_TX_BUFSIZE + int "Set UART14 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default y + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH + if BSP_USING_ETH + choice + prompt "ETH" + default BSP_USING_ETH1 + + config BSP_USING_ETH0 + bool "Enable ETH0" + + config BSP_USING_ETH1 + bool "Enable ETH1" + select BSP_USING_ENET_PHY_RTL8201 + endchoice + endif + + menuconfig BSP_USING_SDXC + bool "Enable SDXC" + default n + select RT_USING_SDIO if BSP_USING_SDXC + if BSP_USING_SDXC + config BSP_USING_SDXC0 + bool "Enable SDXC0" + default n + + config BSP_USING_SDXC1 + bool "Enable SDXC1" + default y + endif + + menuconfig BSP_USING_TOUCH + bool "Enable touch" + default n + if BSP_USING_TOUCH + config BSP_USING_TOUCH_GT911 + bool "Enable GT911" + default y + + config BSP_USING_TOUCH_FT5406 + bool "Enable FT5406" + default n + endif + + menuconfig BSP_USING_LCD + bool "Enable LCD" + default n + + menuconfig BSP_USING_LVGL + bool "Enable LVGL" + default n + select PKG_USING_LVGL if BSP_USING_LVGL + select BSP_USING_PDMA if BSP_USING_LVGL + + menuconfig BSP_USING_PDMA + bool "Enable PDMA Driver" + default n + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + config BSP_USING_GPTMR4 + bool "Enable GPTMR4" + default n + config BSP_USING_GPTMR5 + bool "Enable GPTMR5" + default n + config BSP_USING_GPTMR6 + bool "Enable GPTMR6" + default n + config BSP_USING_GPTMR7 + bool "Enable GPTMR7" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + endif + + menuconfig BSP_USING_FEMC + bool "Enable DRAM" + default y + menuconfig INIT_EXT_RAM_FOR_DATA + bool "INIT_EXT_RAM_FOR_DATA" + default y + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select PKG_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + + menuconfig BSP_USING_DAO + bool "Enable Audio DAO play" + default n + select RT_USING_AUDIO if BSP_USING_DAO + + menuconfig BSP_USING_PDM + bool "Enable Audio PDM record" + default n + select RT_USING_AUDIO if BSP_USING_PDM + + menuconfig BSP_USING_I2S + bool "Enable Audio I2S device" + default n + select RT_USING_AUDIO if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S0 + bool "Enable I2S0" + default y + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB Host" + default n + endif + + + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + config BSP_USING_WDG2 + bool "Enable WDG2" + default n + config BSP_USING_WDG3 + bool "Enable WDG3" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN if BSP_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + config BSP_USING_CAN2 + bool "Enable CAN2" + default n + config BSP_USING_CAN3 + bool "Enable CAN3" + default n + endif + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif +endmenu + + + +endmenu diff --git a/bsp/hpmicro/hpm6750evk2/board/SConscript b/bsp/hpmicro/hpm6750evk2/board/SConscript new file mode 100644 index 0000000000..2225377386 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/SConscript @@ -0,0 +1,20 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + eth_phy_port.c + fal_flash_port.c + hpm_wm8960.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6750'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.c b/bsp/hpmicro/hpm6750evk2/board/board.c similarity index 78% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.c rename to bsp/hpmicro/hpm6750evk2/board/board.c index ed65ffc382..624bcbcd13 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.c +++ b/bsp/hpmicro/hpm6750evk2/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -11,7 +11,7 @@ #include "hpm_i2c_drv.h" #include "hpm_gpio_drv.h" #include "hpm_debug_console.h" -#include "hpm_dram_drv.h" +#include "hpm_femc_drv.h" #include "pinmux.h" #include "hpm_pmp_drv.h" #include "assert.h" @@ -22,6 +22,7 @@ #include "hpm_trgm_drv.h" #include "hpm_pllctl_drv.h" #include "hpm_enet_drv.h" +#include "hpm_pcfg_drv.h" static board_timer_cb timer_cb; @@ -88,7 +89,7 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; /* Configure the UART clock to 24MHz */ @@ -126,7 +127,7 @@ void board_print_clock_freq(void) printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); printf("display:\t %luHz\n", clock_get_frequency(clock_display)); printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); @@ -138,6 +139,7 @@ void board_print_clock_freq(void) void board_init_uart(UART_Type *ptr) { init_uart_pins(ptr); + board_init_uart_clock(ptr); } void board_init_ahb(void) @@ -199,12 +201,12 @@ void board_init_sdram_pins(void) init_sdram_pins(); } -uint32_t board_init_dram_clock(void) +uint32_t board_init_femc_clock(void) { - clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ - /* clock_set_source_divider(clock_dram, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ + /* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ - return clock_get_frequency(clock_dram); + return clock_get_frequency(clock_femc); } void board_power_cycle_lcd(void) @@ -213,17 +215,19 @@ void board_power_cycle_lcd(void) gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); + gpio_set_pin_output(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN); + gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 0); + gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 1); board_delay_ms(150); /* power recycle */ - gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); + gpio_set_pin_output(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN); + gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, 0); board_delay_ms(150); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); + gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, 1); board_delay_ms(150); /* turn on backlight */ gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); - } void board_init_lcd(void) @@ -234,6 +238,28 @@ void board_init_lcd(void) board_power_cycle_lcd(); } +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + + config->resolution_x = BOARD_LCD_WIDTH; + config->resolution_y = BOARD_LCD_HEIGHT; + + config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; + config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; + config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; + + config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; + config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; + config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; + + config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; + config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; + config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; + config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; + config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; +} + void board_delay_ms(uint32_t ms) { clock_cpu_delay_ms(ms); @@ -319,29 +345,59 @@ void board_init_i2c(I2C_Type *ptr) freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%lx\n", (uint32_t)BOARD_CAP_I2C_BASE); + printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE); while (1) {} } } uint32_t board_init_uart_clock(UART_Type *ptr) { - uint32_t freq = 0U; + uint32_t freq = 0; + clock_name_t clock_name = clock_uart0; + bool need_init_clock = true; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart0); + clock_name = clock_uart0; + } else if (ptr == HPM_UART1) { + clock_name = clock_uart1; + } else if (ptr == HPM_UART2) { + clock_name = clock_uart2; + } else if (ptr == HPM_UART3) { + clock_name = clock_uart3; + } else if (ptr == HPM_UART4) { + clock_name = clock_uart4; + } else if (ptr == HPM_UART5) { + clock_name = clock_uart5; } else if (ptr == HPM_UART6) { - clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart6); + clock_name = clock_uart6; + } else if (ptr == HPM_UART7) { + clock_name = clock_uart7; + } else if (ptr == HPM_UART8) { + clock_name = clock_uart8; + } else if (ptr == HPM_UART9) { + clock_name = clock_uart9; + } else if (ptr == HPM_UART10) { + clock_name = clock_uart10; + } else if (ptr == HPM_UART11) { + clock_name = clock_uart11; + } else if (ptr == HPM_UART12) { + clock_name = clock_uart12; } else if (ptr == HPM_UART13) { - clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart13); + clock_name = clock_uart13; } else if (ptr == HPM_UART14) { - clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart14); + clock_name = clock_uart14; + } else if (ptr == HPM_UART15) { + clock_name = clock_uart15; } else { - /* Not supported */ + /* Unsupported instance */ + need_init_clock = false; } + + if (need_init_clock) { + clock_set_source_divider(clock_name, clk_src_osc24m, 1); + clock_add_to_group(clock_name, 0); + freq = clock_get_frequency(clock_name); + } + return freq; } @@ -364,11 +420,12 @@ void board_init_cap_touch(void) gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); board_delay_ms(1); - gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); - board_delay_ms(10); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + board_delay_ms(1); gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); + board_delay_ms(6); + gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); - gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); board_init_i2c(BOARD_CAP_I2C_BASE); } @@ -382,18 +439,6 @@ void board_init_spi_pins(SPI_Type *ptr) init_spi_pins(ptr); } -void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) -{ - init_spi_pins_with_gpio_as_cs(ptr); - gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), - GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); -} - -void board_write_spi_cs(uint32_t pin, uint8_t state) -{ - gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); -} - void board_init_led_pins(void) { init_led_pins_as_gpio(); @@ -479,6 +524,7 @@ void board_init_pmp(void) void board_init_clock(void) { uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + hpm_core_clock = cpu0_freq; if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { /* Configure the External OSC ramp-up time: ~9ms */ pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); @@ -494,7 +540,7 @@ void board_init_clock(void) clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); clock_add_to_group(clock_gptmr0, 0); @@ -505,11 +551,6 @@ void board_init_clock(void) clock_add_to_group(clock_gptmr5, 0); clock_add_to_group(clock_gptmr6, 0); clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); - clock_add_to_group(clock_uart13, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -555,6 +596,7 @@ void board_init_clock(void) clock_add_to_group(clock_msyn, 0); clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_lmm1, 0); + clock_add_to_group(clock_pdm, 0); clock_add_to_group(clock_adc0, 0); clock_add_to_group(clock_adc1, 0); @@ -565,17 +607,22 @@ void board_init_clock(void) clock_add_to_group(clock_i2s1, 0); clock_add_to_group(clock_i2s2, 0); clock_add_to_group(clock_i2s3, 0); + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); /* Add the CPU1 clock to Group1 */ clock_add_to_group(clock_mchtmr1, 1); clock_add_to_group(clock_mbx1, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); - /* Connect Group0 to CPU0 */ - clock_connect_group_to_cpu(0, 0); + /* Bump up DCDC voltage to 1200mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1200); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); - while(1); + while (1) { + } } clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); @@ -583,7 +630,7 @@ void board_init_clock(void) /* Connect Group1 to CPU1 */ clock_connect_group_to_cpu(1, 1); - clock_update_core_clock(); + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ } uint32_t board_init_cam_clock(CAM_Type *ptr) @@ -608,7 +655,7 @@ uint32_t board_init_lcd_clock(void) uint32_t freq; clock_add_to_group(clock_display, 0); /* Configure LCDC clock to 29.7MHz */ - clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + clock_set_source_divider(clock_display, clock_source_pll4_clk0, 10U); freq = clock_get_frequency(clock_display); return freq; } @@ -668,7 +715,7 @@ uint32_t board_init_i2s_clock(I2S_Type *ptr) if (ptr == HPM_I2S0) { clock_add_to_group(clock_i2s0, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, BOARD_APP_AUDIO_CLK_SRC, 25); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); return clock_get_frequency(clock_i2s0); @@ -719,29 +766,79 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } -#ifdef INIT_EXT_RAM_FOR_DATA +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, 0); + clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr0); + } + else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, 0); + clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr1); + } + else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, 0); + clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr2); + } + else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, 0); + clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr3); + } + else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, 0); + clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr4); + } + else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, 0); + clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr5); + } + else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, 0); + clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr6); + } + else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, 0); + clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr7); + } + else { + /* Invalid instance */ + } +} + + /* * this function will be called during startup to initialize external memory for data use */ void _init_ext_ram(void) { - uint32_t dram_clk_in_hz; + uint32_t femc_clk_in_hz; + clock_add_to_group(clock_femc, 0); board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); + femc_clk_in_hz = board_init_femc_clock(); - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); + femc_default_config(HPM_FEMC, &config); + config.dqs = FEMC_DQS_INTERNAL; + femc_init(HPM_FEMC, &config); - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.precharge_to_act_in_ns = 18; /* Trp */ sdram_config.act_to_rw_in_ns = 18; /* Trcd */ @@ -754,7 +851,7 @@ void _init_ext_ram(void) sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ sdram_config.act_to_act_in_ns = 12; /* Trrd */ sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED; sdram_config.cs = BOARD_SDRAM_CS; sdram_config.base_address = BOARD_SDRAM_ADDRESS; @@ -765,13 +862,22 @@ void _init_ext_ram(void) sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; sdram_config.delay_cell_value = 29; - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } -#endif + void board_init_sd_pins(SDXC_Type *ptr) { init_sdxc_pins(ptr, false); + init_sdxc_card_detection_pin(ptr); +} + +void board_sd_power_switch(SDXC_Type *ptr, bool on_off) +{ + if (ptr == HPM_SDXC1) { + init_sdxc_power_pin(ptr); + gpio_set_pin_output_with_initial(BOARD_APP_SDCARD_POWER_EN_GPIO_BASE, BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX, BOARD_APP_SDCARD_POWER_EN_GPIO_PIN, on_off); + } } @@ -950,17 +1056,9 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) } else { return status_invalid_argument; } - - enet_rmii_enable_clock(ptr, internal); - return status_success; } -hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) -{ - return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); -} - void board_init_adc12_pins(void) { init_adc12_pins(); @@ -976,16 +1074,34 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) init_enet_pins(ptr); if (ptr == HPM_ENET0) { - gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); - board_delay_ms(1); - gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); - } else if (ptr == HPM_ENET1) { - gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); - board_delay_ms(1); - gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); + gpio_set_pin_output_with_initial(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); + } else if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); } else { return status_invalid_argument; } return status_success; } + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); + board_delay_ms(BOARD_ENET0_PHY_RST_TIME); + gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 1); + } else if (ptr == HPM_ENET1) { + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + board_delay_ms(BOARD_ENET1_PHY_RST_TIME); + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +{ + return enet_pbl_32; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.h b/bsp/hpmicro/hpm6750evk2/board/board.h similarity index 79% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.h rename to bsp/hpmicro/hpm6750evk2/board/board.h index 9f7d3250df..1c282cd89e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.h +++ b/bsp/hpmicro/hpm6750evk2/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,6 +13,7 @@ #include "hpm_soc.h" #include "hpm_soc_feature.h" #include "pinmux.h" +#include "hpm_lcdc_drv.h" #define BOARD_NAME "hpm6750evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) @@ -50,10 +51,10 @@ #define BOARD_APP_UART_CLK_NAME clock_uart0 #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 #define BOARD_CONSOLE_BASE HPM_UART0 @@ -74,8 +75,8 @@ /* sdram section */ #define BOARD_SDRAM_ADDRESS (0x40000000UL) #define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS #define BOARD_SDRAM_REFRESH_COUNT (8192UL) #define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) @@ -86,12 +87,15 @@ /* lcd section */ #define BOARD_LCD_BASE HPM_LCDC #define BOARD_LCD_IRQ IRQn_LCDC_D0 -#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_POWER_GPIO_PIN 16 +#define BOARD_LCD_RESET_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_RESET_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_RESET_GPIO_PIN 16 #define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB #define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 +#define BOARD_LCD_POWER_EN_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOZ +#define BOARD_LCD_POWER_EN_GPIO_PIN 00 /* i2c section */ #define BOARD_APP_I2C_BASE HPM_I2C0 @@ -192,9 +196,7 @@ #define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX #define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 -#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 -#define BOARD_SPI_CS_PIN IOC_PAD_PE31 -#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + /* Flash section */ #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) @@ -203,11 +205,58 @@ #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* lcd section */ + +/* + * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} + * + * HSPW: Horizontal Synchronization Pulse width + * HBP: Horizontal Back Porch + * HFP: Horizontal Front Porch + * VSPW: Vertical Synchronization Pulse width + * VBP: Vertical Back Porch + * VFP: Vertical Front Porch + * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active + * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active + * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active + * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active + * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active + */ +#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 +#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 +#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 +#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 +#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 +#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 +#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 +#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 +#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 +#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 +#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 + +#if defined(PANEL_TM070RDH13) + #ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH (800) +#define BOARD_LCD_WIDTH 800 #endif #ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT (480) +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + +#else + +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH 800 +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + #endif /* pdma section */ @@ -221,38 +270,52 @@ #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 /* enet section */ -#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 -#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF -#define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) -#define BOARD_ENET_RGMII HPM_ENET0 -#define BOARD_ENET_RGMII_TX_DLY (22U) -#define BOARD_ENET_RGMII_RX_DLY (19U) +#define BOARD_ENET0_RST_GPIO HPM_GPIO0 +#define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF +#define BOARD_ENET0_RST_GPIO_PIN (0U) +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (7U) +#endif +#if __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif -#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET1_RST_GPIO HPM_GPIO0 +#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET1_RST_GPIO_PIN (26U) +#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET1_INT_REF_CLK (1U) +#define BOARD_ENET1_PHY_RST_TIME (30) -#define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 -#define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE -#define BOARD_ENET_RMII_RST_GPIO_PIN (26U) -#define BOARD_ENET_RMII HPM_ENET1 -#define BOARD_ENET_RMII_INT_REF_CLK (1U) +#if BOARD_ENET1_INF +#define BOARD_ENET1_TX_DLY (0U) +#define BOARD_ENET1_RX_DLY (0U) +#endif -#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) +#if __USE_ENET_PTP +#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) +#endif /* ADC section */ #define BOARD_APP_ADC12_NAME "ADC0" #define BOARD_APP_ADC12_BASE HPM_ADC0 #define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC12_CH_1 (11U) -#define BOARD_APP_ADC12_CH_2 (10U) -#define BOARD_APP_ADC12_CH_3 (7U) +#define BOARD_APP_ADC12_CH (11U) #define BOARD_APP_ADC16_NAME "ADC3" #define BOARD_APP_ADC16_BASE HPM_ADC3 #define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC16_CH_1 (2U) - +#define BOARD_APP_ADC16_CH (2U) +#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) +#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) +#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) #define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 #define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 #define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 @@ -286,7 +349,9 @@ #define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX GPIO_DI_GPIOD #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 15 #endif - +#define BOARD_APP_SDCARD_POWER_EN_GPIO_BASE HPM_GPIO0 +#define BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOC +#define BOARD_APP_SDCARD_POWER_EN_GPIO_PIN 20 /* USB section */ #define BOARD_USB0_ID_PORT (HPM_GPIO0) @@ -360,6 +425,7 @@ #define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP #define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ #define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD +#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A /*adc*/ #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 @@ -436,16 +502,14 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); - +void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); -uint32_t board_init_dram_clock(void); +uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); void board_init_spi_pins(SPI_Type *ptr); -void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); -void board_write_spi_cs(uint32_t pin, uint8_t state); void board_init_led_pins(void); /* cap touch */ @@ -478,7 +542,7 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr); uint32_t board_init_adc16_clock(ADC16_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); - +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); @@ -486,6 +550,7 @@ uint32_t board_init_dao_clock(void); void board_init_sd_pins(SDXC_Type *ptr); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); bool board_sd_detect_card(SDXC_Type *ptr); void board_init_adc12_pins(void); @@ -494,9 +559,12 @@ void board_init_adc16_pins(void); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); -hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); + hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); /* @@ -518,6 +586,7 @@ void board_disable_output_rgb_led(uint8_t color); */ void board_ungate_mchtmr_at_lp_mode(void); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg rename to bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg similarity index 82% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg rename to bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg index 686495c1a9..4af46a3ebb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/boards/hpm6750evk2.cfg @@ -1,8 +1,8 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause -# + # openocd flash driver argument: -# - ARG7: +# - option0: # [31:28] Flash probe type # 0 - SFDP SDR / 1 - SFDP DDR # 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) @@ -30,7 +30,7 @@ # 3 - External DQS # [3:0] Frequency option # 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz -# - ARG8: +# - option1: # [31:20] Reserved # [19:16] IO voltage # 0 - 3V / 1 - 1.8V @@ -45,9 +45,9 @@ # - flash driver: hpm_xpi # - flash ctrl index: 0xF3040000 # - base address: 0x80000000 -# - flash size: 0x1000000 +# - flash size: 0x2000000 # - flash option0: 0x7 -flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7 proc init_clock {} { $::_TARGET0 riscv dmi_write 0x39 0xF4002000 @@ -71,13 +71,61 @@ proc init_clock {} { } proc init_sdram { } { -# configure dram frequency +# configure femc frequency # 133Mhz pll1_clk0: 266Mhz divide by 2 #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x201 + #$::_TARGET0 riscv dmi_write 0x3C 0x201 # 166Mhz pll2_clk0: 333Mhz divide by 2 $::_TARGET0 riscv dmi_write 0x39 0xF4001820 $::_TARGET0 riscv dmi_write 0x3C 0x401 + # PC01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040208 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040200 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB31 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB30 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB29 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB28 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB27 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB26 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB25 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB24 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB23 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB22 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB21 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB20 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040198 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040190 + $::_TARGET0 riscv dmi_write 0x3C 0xC # PD13 $::_TARGET0 riscv dmi_write 0x39 0xF4040368 @@ -176,7 +224,7 @@ proc init_sdram { } { $::_TARGET0 riscv dmi_write 0x3C 0xC # PC16 # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 - $::_TARGET0 riscv dmi_write 0x3C 0x1000C + #$::_TARGET0 riscv dmi_write 0x3C 0x1000C # PC26 $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 $::_TARGET0 riscv dmi_write 0x3C 0xC @@ -208,7 +256,7 @@ proc init_sdram { } { $::_TARGET0 riscv dmi_write 0x39 0xF4040218 $::_TARGET0 riscv dmi_write 0x3C 0xC - # dramc configuration + # femc configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050000 $::_TARGET0 riscv dmi_write 0x3C 0x1 sleep 10 @@ -221,18 +269,16 @@ proc init_sdram { } { $::_TARGET0 riscv dmi_write 0x39 0xF3050000 $::_TARGET0 riscv dmi_write 0x3C 0x10000000 - # 16MB $::_TARGET0 riscv dmi_write 0x39 0xF3050010 - $::_TARGET0 riscv dmi_write 0x3C 0x40000019 + $::_TARGET0 riscv dmi_write 0x3C 0x4000001b $::_TARGET0 riscv dmi_write 0x39 0xF3050014 $::_TARGET0 riscv dmi_write 0x3C 0 - # 16-bit $::_TARGET0 riscv dmi_write 0x39 0xF3050040 - $::_TARGET0 riscv dmi_write 0x3C 0xf31 + $::_TARGET0 riscv dmi_write 0x3C 0xf32 # 133Mhz configuration #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + #$::_TARGET0 riscv dmi_write 0x3C 0x884e22 # 166Mhz configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050044 $::_TARGET0 riscv dmi_write 0x3C 0x884e33 diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 0000000000..b9ae112104 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 0000000000..580d98ef85 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 0000000000..4fb0fba2e7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 0000000000..fd8f04428c --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 0000000000..e9d6e6d698 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-csr.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-csr.cfg similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-csr.cfg rename to bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-csr.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg similarity index 78% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg rename to bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg index 601b680951..32b87da2cf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # @@ -36,8 +36,15 @@ proc dmi_read_memory {addr} { } proc release_core1 {} { - # set start point for core1 - dmi_write_memory 0xF4002C08 0x20016284 + + set chip_rev [dmi_read_memory 0x2001FF00] + + if {$chip_rev != 0x56010100 } { + # set start point for core1 + dmi_write_memory 0xF4002C08 0x20016284 + } else { + dmi_write_memory 0xF4002C08 0x2001660c + } # set boot flag for core1 dmi_write_memory 0xF4002C0C 0xC1BEF1A9 @@ -46,16 +53,15 @@ proc release_core1 {} { dmi_write_memory 0xF4002C00 0x1000 } -$_TARGET0 configure -event examine-end { - release_core1 -} - set _TARGET1 $_CHIP.cpu1 target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 $_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 -$_TARGET1 configure -event reset-deassert-pre { - $::_TARGET1 arp_poll +$_TARGET1 configure -event examine-start { release_core1 } +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET0 arp_poll + release_core1 +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg similarity index 92% rename from bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg rename to bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg index 8e2bbe5f19..f873527fb7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg +++ b/bsp/hpmicro/hpm6750evk2/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause set _CHIP hpm6750 diff --git a/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.c b/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.c new file mode 100644 index 0000000000..10074b1a4d --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.c @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2023 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 hpmicro First version + */ + +#include "rtthread.h" + +#ifdef RT_USING_PHY +#include +#include +#include "hpm_enet_drv.h" +#include "eth_phy_port.h" +#include "hpm_soc.h" +#include "netif/ethernetif.h" +#include "board.h" + +typedef struct +{ + char *mdio_name; + ENET_Type *instance; + struct eth_device *eth_dev; + phy_device_t *phy_dev; + struct rt_mdio_bus *mdio_bus; +} eth_phy_handle_t; + +typedef struct +{ + uint8_t phy_handle_cnt; + eth_phy_handle_t **phy_handle; +} eth_phy_monitor_handle_t; + +#ifdef BSP_USING_ETH0 +extern struct eth_device eth0_dev; +static struct rt_mdio_bus mdio0_bus; +static phy_device_t phy0_dev; +static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; + +static eth_phy_handle_t eth0_phy_handle = +{ + .instance = HPM_ENET0, + .eth_dev = ð0_dev, + .phy_dev = &phy0_dev, + .mdio_name = "MDIO0", + .mdio_bus = &mdio0_bus, +}; +#endif + +#ifdef BSP_USING_ETH1 +extern struct eth_device eth1_dev; +static struct rt_mdio_bus mdio1_bus; +static phy_device_t phy1_dev; +static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; + +static eth_phy_handle_t eth1_phy_handle = +{ + .instance = HPM_ENET1, + .eth_dev = ð1_dev, + .phy_dev = &phy1_dev, + .mdio_name = "MDIO1", + .mdio_bus = &mdio1_bus, +}; +#endif + +static eth_phy_handle_t *s_gphys[] = +{ +#ifdef BSP_USING_ETH0 +ð0_phy_handle, +#endif + +#ifdef BSP_USING_ETH1 +ð1_phy_handle +#endif +}; + +static uint8_t *s_gphy_reg_list[] = +{ +#ifdef BSP_USING_ETH0 +phy0_reg_list, +#endif + +#ifdef BSP_USING_ETH1 +phy1_reg_list, +#endif +}; + +eth_phy_monitor_handle_t phy_monitor_handle = +{ + .phy_handle_cnt = ARRAY_SIZE(s_gphys), + .phy_handle = s_gphys +}; + +static struct rt_phy_ops phy_ops; + +static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ +#ifdef BSP_USING_ETH0 + return PHY_STATUS_OK; +#endif + +#ifdef BSP_USING_ETH1 + rtl8201_config_t phy_config; + + rtl8201_reset((ENET_Type *)object); + rtl8201_basic_mode_default_config((ENET_Type *)object, &phy_config); + if (rtl8201_basic_mode_init((ENET_Type *)object, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } +#endif +} + +static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); + + return size; +} + +static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); + + return size; +} + +static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); + + #if PHY_AUTO_NEGO + reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + + #else + reg_status &= PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + #endif + + return PHY_STATUS_OK; +} + +static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); +#if RGMII + if (PHY_STATUS_SPEED_1000M(reg_status)) + { + *speed = PHY_SPEED_1000M; + } + else if (PHY_STATUS_SPEED_100M(reg_status)) + { + *speed = PHY_SPEED_100M; + } + else + { + *speed = PHY_SPEED_10M; + } +#else + if (PHY_STATUS_SPEED_100M(reg_status)) + { + *speed = PHY_SPEED_100M; + } + else + { + *speed = PHY_SPEED_10M; + } +#endif + *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; + + return PHY_STATUS_OK; +} + +static void phy_poll_status(void *parameter) +{ + int ret; + phy_info_t phy_info; + rt_bool_t status; + rt_device_t dev; + rt_phy_msg_t msg; + rt_uint32_t speed, duplex; + phy_device_t *phy_dev; + struct eth_device* eth_dev; + char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; + enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; + phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; + + phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); + + if (status) + { + phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); + + ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (ret != 0) + { + memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + } + } + + if (phy_dev->phy_link != status) + { + phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; + eth_device_linkchange(eth_dev, status); + LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); + if (status == PHY_LINK_UP) + { + LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); + LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); + enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); + } + } + } +} + +static void phy_detection(void *parameter) +{ + uint8_t detected_count = 0; + struct rt_phy_msg msg = {0, 0}; + phy_device_t *phy_dev = (phy_device_t *)parameter; + rt_uint32_t i; + + msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; + while(phy_dev->phy.addr == 0xffff) + { + /* Search a PHY */ + for (i = 0; i <= 0x1f; i++) + { + ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; + phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); + if (msg.value == PHY_ID1) + { + phy_dev->phy.addr = i; + LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); + phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); + return; + } + } + + phy_dev->phy.addr = 0xffff; + detected_count++; + rt_thread_mdelay(1000); + + if (detected_count > 3) + { + LOG_E("No any PHY device is detected! Please check your hardware!\n"); + return; + } + } +} + +static void phy_monitor_thread_entry(void *args) +{ + rt_timer_t phy_status_timer; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + LOG_D("Detect a PHY%d\n", i); + phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); + } + + phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + + if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) + { + LOG_E("Failed to start link change detection timer\n"); + } +} + +int phy_device_register(void) +{ + rt_err_t err = RT_ERROR; + rt_thread_t thread_phy_monitor; + + /* Set ops for PHY */ + phy_ops.init = phy_init; + phy_ops.get_link_status = phy_get_link_status; + phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) + { + /* Set PHY address */ + s_gphys[i]->phy_dev->phy.addr = 0xffff; + + /* Set MIDO bus */ + s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; + s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; + s_gphys[i]->mdio_bus->ops->read = phy_read; + s_gphys[i]->mdio_bus->ops->write = phy_write; + s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; + s_gphys[i]->phy_dev->phy.ops = &phy_ops; + + /* Set PHY register list */ + s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; + + rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); + } + + /* Start PHY monitor */ + thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2); + + if (thread_phy_monitor != RT_NULL) + { + rt_thread_startup(thread_phy_monitor); + } + else + { + err = RT_ERROR; + } + + return err; +} +INIT_PREV_EXPORT(phy_device_register); +#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.h new file mode 100644 index 0000000000..cde420add9 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/eth_phy_port.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2023 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * +*/ + +#ifndef ETH_PHY_PORT_H +#define ETH_PHY_PORT_H + +#include "hpm_ioc_regs.h" +#include + +#ifndef PHY_AUTO_NEGO +#define PHY_AUTO_NEGO (1U) +#endif + +#ifndef PHY_MDIO_CSR_CLK_FREQ +#define PHY_MDIO_CSR_CLK_FREQ (200000000U) +#endif + +enum phy_link_status +{ + PHY_LINK_DOWN = 0U, + PHY_LINK_UP +}; + +typedef struct { + rt_uint32_t phy_speed; + rt_uint32_t phy_duplex; +} phy_info_t; + +typedef struct { + rt_uint32_t phy_link; + rt_phy_t phy; + phy_info_t phy_info; +} phy_device_t; + +#ifdef BSP_USING_ETH0 + + #define RGMII (1U) + + /* RTL8211 name and ID */ + #define PHY_NAME ("RTL8211") + #define PHY_ID1 (0x001CU) + #define PHY_ID2 (0x32U) + + /* PHY_RTL8211 basic control register */ + #define PHY_BASIC_CONTROL_REG (0x00U) + #define PHY_RESET_MASK (1U << 15) + #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) + + /* PHY_RTL8211 basic status register */ + #define PHY_BASIC_STATUS_REG (0x01U) + #define PHY_LINKED_STATUS_MASK (1U << 2) + #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) + + /* PHY_RTL8211 ID one register */ + #define PHY_ID1_REG (0x02U) + + /* PHY_RTL8211 ID two register */ + #define PHY_ID2_REG (0x03U) + + /* PHY_RTL8211 auto-negotiate advertise register */ + #define PHY_AUTONEG_ADVERTISE_REG (0x04U) + + /* PHY_RTL8211 status register */ + #define PHY_STATUS_REG (0x11U) + #define PHY_100M_MASK (1UL << 14) + #define PHY_1000M_MASK (1UL << 15) + #define PHY_FULL_DUPLEX_MASK (1UL << 13) + #define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) + #define PHY_STATUS_SPEED_1000M(SR) ((SR) & PHY_1000M_MASK) + #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) + #define PHY_SPEED_SEL_SHIFT (14U) + /* PHY_RTL8211 interrupt control register */ + #define PHY_INTERTUPT_CTRL_REG (0x12U) + + /* PHY_RTL8211 interrupt status register */ + #define PHY_INTERRUPT_STATUS_REG (0x13U) + + /* PHY register index */ + typedef enum { + PHY_BASIC_CONTROL_REG_IDX = 0, + PHY_BASIC_STATUS_REG_IDX, + PHY_ID1_REG_IDX, + PHY_ID2_REG_IDX, + PHY_AUTONEG_ADVERTISE_REG_IDX, + PHY_STATUS_REG_IDX, + PHY_INTERRUPT_FLAG_REG_IDX, + PHY_INTERRUPT_MASK_REG_IDX + } phy_reg_idx_t; + + /* ETH0 PHY register list */ + #define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ + PHY_BASIC_STATUS_REG,\ + PHY_ID1_REG,\ + PHY_ID2_REG,\ + PHY_AUTONEG_ADVERTISE_REG,\ + PHY_STATUS_REG,\ + PHY_INTERTUPT_CTRL_REG,\ + PHY_INTERRUPT_STATUS_REG + +#else + #include "hpm_rtl8201.h" + + #define RMII (1U) + + /* RTL8201 name and ID */ + #define PHY_NAME ("RTL8201") + #define PHY_ID1 (0x001CU) + #define PHY_ID2 (0x32U) + + /* RTL8201 basic control register */ + #define PHY_BASIC_CONTROL_REG (0x00U) + #define PHY_RESET_MASK (1U << 15) + #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) + + /* RTL8201 basic status register */ + #define PHY_BASIC_STATUS_REG (0x01U) + #define PHY_LINKED_STATUS_MASK (1U << 2) + #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) + + /* RTL8201 ID one register */ + #define PHY_ID1_REG (0x02U) + + /* RTL8201 ID two register */ + #define PHY_ID2_REG (0x03U) + + /* RTL8201 auto-negotiate advertise register */ + #define PHY_AUTONEG_ADVERTISE_REG (0x04U) + + /* RTL8201 status register */ + #define PHY_STATUS_REG (0x00U) + #define PHY_100M_MASK (1UL << 13) + #define PHY_FULL_DUPLEX_MASK (1UL << 8) + #define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) + #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) + + /* RTL8201 mode setting register */ + #define PHY_RMSR_P7 (0x10) + #define PHY_RMSR_P7_RG_RMII_CLKDIR_MASK (0x1000U) + + /* RTL8201 page select register */ + #define PHY_PAGESEL (0x1f) + + /* PHY register index */ + typedef enum { + PHY_BASIC_CONTROL_REG_IDX = 0, + PHY_BASIC_STATUS_REG_IDX, + PHY_ID1_REG_IDX, + PHY_ID2_REG_IDX, + PHY_AUTONEG_ADVERTISE_REG_IDX, + PHY_STATUS_REG_IDX, + PHY_RMSR_P7_IDX, + PHY_PAGE_SEL_IDX + } phy_reg_idx_t; + + /* ETH0 PHY register list */ + #define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\ + PHY_BASIC_STATUS_REG,\ + PHY_ID1_REG,\ + PHY_ID2_REG,\ + PHY_AUTONEG_ADVERTISE_REG,\ + PHY_STATUS_REG,\ + PHY_RMSR_P7_IDX,\ + PHY_PAGE_SEL_IDX + +#endif +#endif diff --git a/bsp/hpmicro/hpm6750evk2/board/fal_cfg.h b/bsp/hpmicro/hpm6750evk2/board/fal_cfg.h new file mode 100644 index 0000000000..b315dd87c3 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/fal_cfg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6750evk2/board/fal_flash_port.c b/bsp/hpmicro/hpm6750evk2/board/fal_flash_port.c new file mode 100644 index 0000000000..5f21019b86 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/fal_flash_port.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +static rt_base_t s_interrupt_level; +#define FAL_ENTER_CRITICAL() do {\ + rt_exit_critical();\ + fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() rt_enter_critical() + +#define FAL_EXIT_CRITICAL() rt_exit_critical() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.c b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.c new file mode 100644 index 0000000000..30e262cf65 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_wm8960.h" + +/* wm8960 register default value */ +static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +/* store reg value */ +static uint16_t wm8960_reg_val[WM8960_REG_NUM]; + +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) +{ + assert(control != NULL); + assert(config != NULL); + + hpm_stat_t stat = status_success; + + (void)memcpy(wm8960_reg_val, wm8960_default_reg_val, sizeof(wm8960_default_reg_val)); + + /* Reset */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RESET, 0x00)); + + /* Power on input modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0xFE)); + /* Power on output modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x1F8)); + /* Power on PGA and mixer */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + + /* ADC and DAC uses same clock */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_IFACE2, 0x40)); + + /* set data protocol */ + HPM_CHECK_RET(wm8960_set_protocol(control, config->bus)); + + /* set wm8960 as slave */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); + + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); + + /* ADC volume, 8dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3)); + + /* Digital DAC volume, 0dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, 0x1E0)); + + /* Headphone volume, LOUT1 and ROUT1, 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, 0x17F)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, 0x17F)); + + /* speaker volume 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, 0x1ff)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, 0x1ff)); + /* enable class D output */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xf7)); + + /* Unmute DAC. */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_DACCTL1, 0x0000)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + + HPM_CHECK_RET(wm8960_set_data_format(control, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width)); + + /* set data route */ + HPM_CHECK_RET(wm8960_set_data_route(control, config)); + + return status_success; +} + +hpm_stat_t wm8960_deinit(wm8960_control_t *control) +{ + hpm_stat_t stat = status_success; + + /* power off all modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x00U)); + + return status_success; +} + +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol) +{ + return wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, (uint16_t)protocol); +} + +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable) +{ + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCR_SHIFT))); + break; + case wm8960_module_dac: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACL_MASK, + ((uint16_t)enable << WM8960_POWER2_DACL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACR_MASK, + ((uint16_t)enable << WM8960_POWER2_DACR_SHIFT))); + break; + case wm8960_module_vref: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_VREF_MASK, + ((uint16_t)enable << WM8960_POWER1_VREF_SHIFT))); + break; + case wm8960_module_ana_in: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINL_MASK, + ((uint16_t)enable << WM8960_POWER1_AINL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINR_MASK, + ((uint16_t)enable << WM8960_POWER1_AINR_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_LMIC_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_RMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_RMIC_SHIFT))); + break; + case wm8960_module_lineout: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_LOUT1_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_ROUT1_SHIFT))); + break; + case wm8960_module_micbais: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_MICB_MASK, + ((uint16_t)enable << WM8960_POWER1_MICB_SHIFT))); + break; + case wm8960_module_speaker: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKR_SHIFT))); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xF7)); + break; + case wm8960_module_output_mixer: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LOMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_LOMIX_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_ROMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_ROMIX_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config) +{ + hpm_stat_t stat = status_success; + + /* select left input */ + HPM_CHECK_RET(wm8960_set_left_input(control, config->left_input)); + /* select right input */ + HPM_CHECK_RET(wm8960_set_right_input(control, config->right_input)); + /* select source to output mixer */ + HPM_CHECK_RET(wm8960_config_input_to_output_mixer(control, config->play_source)); + + switch (config->route) { + case wm8960_route_bypass: + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback: + /* I2S_IN-> DAC-> HP */ + /* Set power for DAC */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x0C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback_and_record: + /* Set power */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_record: + /* ANA_IN->ADC->I2S_OUT */ + /* Power up ADC and AIN */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x30)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + /* Update volume */ + vol = (uint16_t)(0x100U | volume); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + } + break; + case wm8960_module_dac: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + } + break; + case wm8960_module_headphone: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + } + break; + case wm8960_module_ana_in: + if (volume > 0x3FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + } + break; + case wm8960_module_speaker: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + } + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) +{ + hpm_stat_t stat = status_success; + uint32_t divider = 0; + uint16_t val = 0; + + /* Compute sample rate divider and SYSCLK Pre-divider, dac and adc are the same sample rate */ + divider = sysclk / sample_rate; + + if (divider >= 512) { + divider = divider / 2; /* SYSCLK Pre-divider */ + val |= WM8960_CLOCK1_SYSCLKDIV_SET(2U); + } + + if (divider < 256U) { + return status_invalid_argument; + } else if (divider == 256U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); + } else { + val |= (((divider / 256U) << WM8960_CLOCK1_ADCDIV_SHIFT) | ((divider / 256U) << WM8960_CLOCK1_DACDIV_SHIFT)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); + } + + /* set sample bit */ + switch (bits) { + case 16: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(0U)); + break; + case 20: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(1U)); + break; + case 24: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(2U)); + break; + case 32: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(3U)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source) +{ + hpm_stat_t stat = status_success; + + if ((play_source & (uint32_t)wm8960_play_source_input_mixer) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_dac) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x100U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x100U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_input3) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x80U)); + } + + return stat; +} + + +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val) +{ + /* The first 7 bits (B15 to B9) are address bits that select which control register */ + /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ + rt_size_t size; + rt_uint8_t data[2]; + data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); + data[1] = (uint8_t)(val & 0xFFU); + + size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U); + if (size != 2) { + return status_fail; + } + + wm8960_reg_val[reg] = val; + return status_success; +} + +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val) +{ + if (reg >= WM8960_REG_NUM) { + return status_invalid_argument; + } + *val = wm8960_reg_val[reg]; + + return status_success; +} + +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val) +{ + hpm_stat_t stat = 0; + uint16_t reg_val; + + /* Read the register value out */ + stat = wm8960_read_reg(reg, ®_val); + if (stat != status_success) { + return status_fail; + } + + /* Modify the value */ + reg_val &= (uint16_t)~mask; + reg_val |= val; + + /* Write the data to register */ + stat = wm8960_write_reg(control, reg, reg_val); + if (stat != status_success) { + return status_fail; + } + + return status_success; +} diff --git a/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.h b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.h new file mode 100644 index 0000000000..a288b08db9 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_H_ +#define _HPM_WM8960_H_ + +//#include "hpm_i2c_drv.h" +//#include "hpm_common.h" +#include +#include +#include "rtt_board.h" +#include "drivers/i2c.h" +#include "hpm_wm8960_regs.h" + +#define WM8960_I2C_ADDR 0x1A + +typedef enum wm8960_module { + wm8960_module_adc = 0, /* ADC module in WM8960 */ + wm8960_module_dac = 1, /* DAC module in WM8960 */ + wm8960_module_vref = 2, /* VREF module */ + wm8960_module_headphone = 3, /* Headphone */ + wm8960_module_micbais = 4, /* Mic bias */ + wm8960_module_ana_in = 6, /* Analog in PGA */ + wm8960_module_lineout = 7, /* Line out module */ + wm8960_module_speaker = 8, /* Speaker module */ + wm8960_module_output_mixer = 9, /* Output mixer */ +} wm8960_module_t; + +/* wm8960 play source for output mixer */ +typedef enum wm8960_play_source { + wm8960_play_source_input_mixer = 1, /* Input Boost Mixer to Output Mixer */ + wm8960_play_source_input3 = 2, /* L/RINPUT3 to Output Mixer */ + wm8960_play_source_dac = 4, /* DAC to Output Mixer */ +} wm8960_play_source_t; + +/* WM8960 data route */ +typedef enum wm8960_route { + wm8960_route_bypass = 0, /* ANA_IN->Headphone. */ + wm8960_route_playback = 1, /* I2SIN->DAC->Headphone. */ + wm8960_route_playback_and_record = 2, /* I2SIN->DAC->Headphone, ANA_IN->ADC->I2SOUT. */ + wm8960_route_record = 5 /* ANA_IN->ADC->I2SOUT. */ +} wm8960_route_t; + +/* The audio data transfer protocol choice */ +typedef enum wm8960_protocol { + wm8960_bus_i2s = 2, /* I2S type */ + wm8960_bus_left_justified = 1, /* Left justified mode */ + wm8960_bus_right_justified = 0, /* Right justified mode */ + wm8960_bus_pcma = 3, /* PCM A mode */ + wm8960_bus_pcmb = 3 | (1 << 4) /* PCM B mode */ +} wm8960_protocol_t; + +/* wm8960 input source */ +typedef enum wm8960_input { + wm8960_input_closed = 0, /* Input device is closed */ + wm8960_input_single_ended_mic = 1, /* Input as single ended mic, only use L/RINPUT1 */ + wm8960_input_differential_mic_input2 = 2, /* Input as differential mic, use L/RINPUT1 and L/RINPUT2 */ + wm8960_input_differential_mic_input3 = 3, /* Input as differential mic, use L/RINPUT1 and L/RINPUT3*/ + wm8960_input_line_input2 = 4, /* Input as line input, only use L/RINPUT2 */ + wm8960_input_line_input3 = 5 /* Input as line input, only use L/RINPUT3 */ +} wm8960_input_t; + +/* wm8960 audio format */ +typedef struct wm8960_audio_format { + uint32_t mclk_hz; /* master clock frequency */ + uint32_t sample_rate; /* sample rate */ + uint32_t bit_width; /* bit width */ +} wm8960_audio_format_t; + +/* configure structure of WM8960 */ +typedef struct wm8960_config { + wm8960_route_t route; /* Audio data route.*/ + wm8960_protocol_t bus; /* Audio transfer protocol */ + bool enable_speaker; /* True means enable class D speaker as output, false means no */ + wm8960_input_t left_input; /* Left input source for WM8960 */ + wm8960_input_t right_input; /* Right input source for wm8960 */ + wm8960_play_source_t play_source; /* play source */ + wm8960_audio_format_t format; /* Audio format */ +} wm8960_config_t; + +typedef struct { + struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */ + uint8_t slave_address; /* code device address */ +} wm8960_control_t; + + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief WM8960 initialize function. + * + * @param control WM8960 control structure. + * @param config WM8960 configuration structure. + */ +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Deinit the WM8960 codec. + * + * This function close all modules in WM8960 to save power. + * + * @param control WM8960 control structure pointer. + */ +hpm_stat_t wm8960_deinit(wm8960_control_t *control); + +/** + * @brief Set audio data route in WM8960. + * + * This function would set the data route according to route. + * + * @param control WM8960 control structure. + * @param config Audio configure structure in WM8960. + */ +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Set left audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set right audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set the audio transfer protocol. + * + * @param control WM8960 control structure. + * @param protocol Audio data transfer protocol. + */ +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol); + +/** + * @brief Set the volume of different modules in WM8960. + * + * This function would set the volume of WM8960 modules. Uses need to appoint the module. + * The function assume that left channel and right channel has the same volume. + * + * Module:wm8960_module_adc, volume range value: 0 is mute, 1-255 is -97db to 30db + * Module:wm8960_module_dac, volume range value: 0 is mute, 1-255 is -127db to 0db + * Module:wm8960_module_headphone, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * Module:wm8960_module_ana_in, volume range value: 0 - 0x3F is -17.25db to 30db + * Module:wm8960_module_speaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * + * + * @param control WM8960 control structure. + * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. + * @param volume Volume value need to be set. + */ +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume); + +/** + * @brief Enable/disable expected module. + * + * @param control WM8960 control structure. + * @param module Module expected to enable. + * @param enable Enable or disable moudles. + */ +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable); + +/** + * @brief SET the WM8960 play source. + * + * @param control WM8960 control structure. + * @param play_source play source + * + * @return kStatus_WM8904_Success if successful, different code otherwise.. + */ +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source); + +/** + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * + * @param control WM8960 control structure pointer. + * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. + * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); + + +/** + * @brief Write register to WM8960 using I2C. + * + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val); + +/** + * @brief Read register from WM8960 using I2C. + * @param reg The register address in WM8960. + * @param val Value written to. + */ +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val); + +/** + * @brief Modify some bits in the register using I2C. + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val); + + +#endif /* _HPM_WM8960_H_ */ diff --git a/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960_regs.h b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960_regs.h new file mode 100644 index 0000000000..a484f2937c --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/hpm_wm8960_regs.h @@ -0,0 +1,2139 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_REG_H_ +#define _HPM_WM8960_REG_H_ + +/* WM8960 register number */ +#define WM8960_REG_NUM 56U + +/* Define the register address of WM8960 */ +#define WM8960_LINVOL 0x0U /* Left Input Volume */ +#define WM8960_RINVOL 0x1U /* Right Input Volume */ +#define WM8960_LOUT1 0x2U /* LOUT1 Volume */ +#define WM8960_ROUT1 0x3U /* ROUT1 Volume */ +#define WM8960_CLOCK1 0x4U /* Clocking(1) */ +#define WM8960_DACCTL1 0x5U /* ADC and DAC Control (1) */ +#define WM8960_DACCTL2 0x6U /* ADC and DAC Control (2) */ +#define WM8960_IFACE1 0x7U /* Audio Interface */ +#define WM8960_CLOCK2 0x8U /* Clocking(2) */ +#define WM8960_IFACE2 0x9U /* Audio Interface */ +#define WM8960_LDAC 0xaU /* Left DAC */ +#define WM8960_RDAC 0xbU /* Right DAC Volume */ +#define WM8960_RESET 0xfU /* RESET */ +#define WM8960_3D 0x10U /* 3D Control */ +#define WM8960_ALC1 0x11U /* ALC (1) */ +#define WM8960_ALC2 0x12U /* ALC (2) */ +#define WM8960_ALC3 0x13U /* ALC (3) */ +#define WM8960_NOISEG 0x14U /* Noise Gate */ +#define WM8960_LADC 0x15U /* Left ADC Volume */ +#define WM8960_RADC 0x16U /* Right ADC Volume */ +#define WM8960_ADDCTL1 0x17U /* Additional Control (1) */ +#define WM8960_ADDCTL2 0x18U /* Additional Control (2) */ +#define WM8960_POWER1 0x19U /* Power Mgmt (1) */ +#define WM8960_POWER2 0x1aU /* Power Mgmt (2) */ +#define WM8960_ADDCTL3 0x1bU /* Additional Control (3) */ +#define WM8960_APOP1 0x1cU /* Anti-Pop 1 */ +#define WM8960_APOP2 0x1dU /* Anti-pop 2 */ +#define WM8960_LINPATH 0x20U /* ADCL Signal Path */ +#define WM8960_RINPATH 0x21U /* ADCR Signal Path */ +#define WM8960_LOUTMIX 0x22U /* Left Out Mix */ +#define WM8960_ROUTMIX 0x25U /* Right Out Mix */ +#define WM8960_MONOMIX1 0x26U /* Mono Out Mix (1) */ +#define WM8960_MONOMIX2 0x27U /* Mono Out Mix (2) */ +#define WM8960_LOUT2 0x28U /* Left Speaker Volume */ +#define WM8960_ROUT2 0x29U /* Right Speaker Volume */ +#define WM8960_MONO 0x2aU /* OUT3 Volume */ +#define WM8960_INBMIX1 0x2bU /* Left Input Boost Mixer */ +#define WM8960_INBMIX2 0x2cU /* Right Input Boost Mixer */ +#define WM8960_BYPASS1 0x2dU /* Left Bypass */ +#define WM8960_BYPASS2 0x2eU /* Right Bypass */ +#define WM8960_POWER3 0x2fU /* Power Mgmt (3) */ +#define WM8960_ADDCTL4 0x30U /* Additional Control (4) */ +#define WM8960_CLASSD1 0x31U /* Class D Control (1) */ +#define WM8960_CLASSD3 0x33U /* Class D Control (2) */ +#define WM8960_PLL1 0x34U /* PLL (1) */ +#define WM8960_PLL2 0x35U /* PLL (2) */ +#define WM8960_PLL3 0x36U /* PLL (3) */ +#define WM8960_PLL4 0x37U /* PLL (4) */ + +/* Bitfield definition for register: LINVO */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_LINVO_IPVU_MASK (0x100U) +#define WM8960_LINVO_IPVU_SHIFT (8U) +#define WM8960_LINVO_IPVU_SET(x) (((uint16_t)(x) << WM8960_LINVO_IPVU_SHIFT) & WM8960_LINVO_IPVU_MASK) +#define WM8960_LINVO_IPVU_GET(x) (((uint16_t)(x) & WM8960_LINVO_IPVU_MASK) >> WM8960_LINVO_IPVU_SHIFT) + +/* + * LINMUTE (RW) + * + * Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. + */ +#define WM8960_LINVO_LINMUTE_MASK (0x80U) +#define WM8960_LINVO_LINMUTE_SHIFT (7U) +#define WM8960_LINVO_LINMUTE_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINMUTE_SHIFT) & WM8960_LINVO_LINMUTE_MASK) +#define WM8960_LINVO_LINMUTE_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINMUTE_MASK) >> WM8960_LINVO_LINMUTE_SHIFT) + +/* + * LIZC (RW) + * + * Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately + */ +#define WM8960_LINVO_LIZC_MASK (0x40U) +#define WM8960_LINVO_LIZC_SHIFT (6U) +#define WM8960_LINVO_LIZC_SET(x) (((uint16_t)(x) << WM8960_LINVO_LIZC_SHIFT) & WM8960_LINVO_LIZC_MASK) +#define WM8960_LINVO_LIZC_GET(x) (((uint16_t)(x) & WM8960_LINVO_LIZC_MASK) >> WM8960_LINVO_LIZC_SHIFT) + +/* + * LINVOL (RW) + * + * Left Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_LINVO_LINVOL_MASK (0x3FU) +#define WM8960_LINVO_LINVOL_SHIFT (0U) +#define WM8960_LINVO_LINVOL_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINVOL_SHIFT) & WM8960_LINVO_LINVOL_MASK) +#define WM8960_LINVO_LINVOL_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINVOL_MASK) >> WM8960_LINVO_LINVOL_SHIFT) + +/* Bitfield definition for register: RINVOL */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right + * input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_RINVOL_IPVU_MASK (0x100U) +#define WM8960_RINVOL_IPVU_SHIFT (8U) +#define WM8960_RINVOL_IPVU_SET(x) (((uint16_t)(x) << WM8960_RINVOL_IPVU_SHIFT) & WM8960_RINVOL_IPVU_MASK) +#define WM8960_RINVOL_IPVU_GET(x) (((uint16_t)(x) & WM8960_RINVOL_IPVU_MASK) >> WM8960_RINVOL_IPVU_SHIFT) + +/* + * RINMUTE (RW) + * + * Right Input PGA Analogue Mute + * 1 = Enable Mute + * 0 = Disable Mute + * Note: IPVU must be set to un-mute. + */ +#define WM8960_RINVOL_RINMUTE_MASK (0x80U) +#define WM8960_RINVOL_RINMUTE_SHIFT (7U) +#define WM8960_RINVOL_RINMUTE_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINMUTE_SHIFT) & WM8960_RINVOL_RINMUTE_MASK) +#define WM8960_RINVOL_RINMUTE_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINMUTE_MASK) >> WM8960_RINVOL_RINMUTE_SHIFT) + +/* + * RIZC (RW) + * + * Right Input PGA Zero Cross Detector + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_RINVOL_RIZC_MASK (0x40U) +#define WM8960_RINVOL_RIZC_SHIFT (6U) +#define WM8960_RINVOL_RIZC_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RIZC_SHIFT) & WM8960_RINVOL_RIZC_MASK) +#define WM8960_RINVOL_RIZC_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RIZC_MASK) >> WM8960_RINVOL_RIZC_SHIFT) + +/* + * RINVOL (RW) + * + * Right Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_RINVOL_RINVOL_MASK (0x3FU) +#define WM8960_RINVOL_RINVOL_SHIFT (0U) +#define WM8960_RINVOL_RINVOL_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINVOL_SHIFT) & WM8960_RINVOL_RINVOL_MASK) +#define WM8960_RINVOL_RINVOL_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINVOL_MASK) >> WM8960_RINVOL_RINVOL_SHIFT) + +/* Bitfield definition for register: LOUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_LOUT1_OUT1VU_MASK (0x100U) +#define WM8960_LOUT1_OUT1VU_SHIFT (8U) +#define WM8960_LOUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_LOUT1_OUT1VU_SHIFT) & WM8960_LOUT1_OUT1VU_MASK) +#define WM8960_LOUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_LOUT1_OUT1VU_MASK) >> WM8960_LOUT1_OUT1VU_SHIFT) + +/* + * LO1ZC (RW) + * + * Left Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_LOUT1_LO1ZC_MASK (0x80U) +#define WM8960_LOUT1_LO1ZC_SHIFT (7U) +#define WM8960_LOUT1_LO1ZC_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LO1ZC_SHIFT) & WM8960_LOUT1_LO1ZC_MASK) +#define WM8960_LOUT1_LO1ZC_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LO1ZC_MASK) >> WM8960_LOUT1_LO1ZC_SHIFT) + +/* + * LOUT1VOL (RW) + * + * LOUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT1_LOUT1VOL_MASK (0x7FU) +#define WM8960_LOUT1_LOUT1VOL_SHIFT (0U) +#define WM8960_LOUT1_LOUT1VOL_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LOUT1VOL_SHIFT) & WM8960_LOUT1_LOUT1VOL_MASK) +#define WM8960_LOUT1_LOUT1VOL_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LOUT1VOL_MASK) >> WM8960_LOUT1_LOUT1VOL_SHIFT) + +/* Bitfield definition for register: ROUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_ROUT1_OUT1VU_MASK (0x100U) +#define WM8960_ROUT1_OUT1VU_SHIFT (8U) +#define WM8960_ROUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_ROUT1_OUT1VU_SHIFT) & WM8960_ROUT1_OUT1VU_MASK) +#define WM8960_ROUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_ROUT1_OUT1VU_MASK) >> WM8960_ROUT1_OUT1VU_SHIFT) + +/* + * RO1ZC (RW) + * + * Right Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_ROUT1_RO1ZC_MASK (0x80U) +#define WM8960_ROUT1_RO1ZC_SHIFT (7U) +#define WM8960_ROUT1_RO1ZC_SET(x) (((uint16_t)(x) << WM8960_ROUT1_RO1ZC_SHIFT) & WM8960_ROUT1_RO1ZC_MASK) +#define WM8960_ROUT1_RO1ZC_GET(x) (((uint16_t)(x) & WM8960_ROUT1_RO1ZC_MASK) >> WM8960_ROUT1_RO1ZC_SHIFT) + +/* + * ROUT1VOL (RW) + * + * ROUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT1_ROUT1VOL_MASK (0x7FU) +#define WM8960_ROUT1_ROUT1VOL_SHIFT (0U) +#define WM8960_ROUT1_ROUT1VOL_SET(x) (((uint16_t)(x) << WM8960_ROUT1_ROUT1VOL_SHIFT) & WM8960_ROUT1_ROUT1VOL_MASK) +#define WM8960_ROUT1_ROUT1VOL_GET(x) (((uint16_t)(x) & WM8960_ROUT1_ROUT1VOL_MASK) >> WM8960_ROUT1_ROUT1VOL_SHIFT) + +/* Bitfield definition for register: CLOCK1 */ +/* + * ADCDIV (RW) + * + * ADC Sample rate divider (Also determines + * ADCLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_ADCDIV_MASK (0x1C0U) +#define WM8960_CLOCK1_ADCDIV_SHIFT (6U) +#define WM8960_CLOCK1_ADCDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_ADCDIV_SHIFT) & WM8960_CLOCK1_ADCDIV_MASK) +#define WM8960_CLOCK1_ADCDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_ADCDIV_MASK) >> WM8960_CLOCK1_ADCDIV_SHIFT) + +/* + * DACDIV (RW) + * + * DAC Sample rate divider (Also determines + * DACLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_DACDIV_MASK (0x38U) +#define WM8960_CLOCK1_DACDIV_SHIFT (3U) +#define WM8960_CLOCK1_DACDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_DACDIV_SHIFT) & WM8960_CLOCK1_DACDIV_MASK) +#define WM8960_CLOCK1_DACDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_DACDIV_MASK) >> WM8960_CLOCK1_DACDIV_SHIFT) + +/* + * SYSCLKDIV (RW) + * + * SYSCLK Pre-divider. Clock source (MCLK or + * PLL output) will be divided by this value to + * generate SYSCLK. + * 00 = Divide SYSCLK by 1 + * 01 = Reserved + * 10 = Divide SYSCLK by 2 + * 11 = Reserved + */ +#define WM8960_CLOCK1_SYSCLKDIV_MASK (0x6U) +#define WM8960_CLOCK1_SYSCLKDIV_SHIFT (1U) +#define WM8960_CLOCK1_SYSCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_SYSCLKDIV_SHIFT) & WM8960_CLOCK1_SYSCLKDIV_MASK) +#define WM8960_CLOCK1_SYSCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_SYSCLKDIV_MASK) >> WM8960_CLOCK1_SYSCLKDIV_SHIFT) + +/* + * CLKSEL (RW) + * + * SYSCLK Selection + * 0 = SYSCLK derived from MCLK + * 1 = SYSCLK derived from PLL output + */ +#define WM8960_CLOCK1_CLKSEL_MASK (0x1U) +#define WM8960_CLOCK1_CLKSEL_SHIFT (0U) +#define WM8960_CLOCK1_CLKSEL_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_CLKSEL_SHIFT) & WM8960_CLOCK1_CLKSEL_MASK) +#define WM8960_CLOCK1_CLKSEL_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_CLKSEL_MASK) >> WM8960_CLOCK1_CLKSEL_SHIFT) + +/* Bitfield definition for register: DACCTL1 */ +/* + * DACDIV2 (RW) + * + * DAC 6dB Attenuate Enable + * 0 = Disabled (0dB) + * 1 = -6dB Enabled + */ +#define WM8960_DACCTL1_DACDIV2_MASK (0x80U) +#define WM8960_DACCTL1_DACDIV2_SHIFT (7U) +#define WM8960_DACCTL1_DACDIV2_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACDIV2_SHIFT) & WM8960_DACCTL1_DACDIV2_MASK) +#define WM8960_DACCTL1_DACDIV2_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACDIV2_MASK) >> WM8960_DACCTL1_DACDIV2_SHIFT) + +/* + * ADCPOL (RW) + * + * ADC polarity control: + * 00 = Polarity not inverted + * 01 = ADC L inverted + * 10 = ADC R inverted + * 11 = ADC L and R inverted + */ +#define WM8960_DACCTL1_ADCPOL_MASK (0x60U) +#define WM8960_DACCTL1_ADCPOL_SHIFT (5U) +#define WM8960_DACCTL1_ADCPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCPOL_SHIFT) & WM8960_DACCTL1_ADCPOL_MASK) +#define WM8960_DACCTL1_ADCPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCPOL_MASK) >> WM8960_DACCTL1_ADCPOL_SHIFT) + +/* + * DACMU (RW) + * + * DAC Digital Soft Mute + * 1 = Mute + * 0 = No mute (signal active) + */ +#define WM8960_DACCTL1_DACMU_MASK (0x8U) +#define WM8960_DACCTL1_DACMU_SHIFT (3U) +#define WM8960_DACCTL1_DACMU_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACMU_SHIFT) & WM8960_DACCTL1_DACMU_MASK) +#define WM8960_DACCTL1_DACMU_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACMU_MASK) >> WM8960_DACCTL1_DACMU_SHIFT) + +/* + * DEEMPH (RW) + * + * De-emphasis Control + * 11 = 48kHz sample rate + * 10 = 44.1kHz sample rate + * 01 = 32kHz sample rate + * 00 = No de-emphasis + */ +#define WM8960_DACCTL1_DEEMPH_MASK (0x6U) +#define WM8960_DACCTL1_DEEMPH_SHIFT (1U) +#define WM8960_DACCTL1_DEEMPH_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DEEMPH_SHIFT) & WM8960_DACCTL1_DEEMPH_MASK) +#define WM8960_DACCTL1_DEEMPH_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DEEMPH_MASK) >> WM8960_DACCTL1_DEEMPH_SHIFT) + +/* + * ADCHPD (RW) + * + * ADC High Pass Filter Disable + * 0 = Enable high pass filter on left and right channels + * 1 = Disable high pass filter on left and right channels + */ +#define WM8960_DACCTL1_ADCHPD_MASK (0x1U) +#define WM8960_DACCTL1_ADCHPD_SHIFT (0U) +#define WM8960_DACCTL1_ADCHPD_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCHPD_SHIFT) & WM8960_DACCTL1_ADCHPD_MASK) +#define WM8960_DACCTL1_ADCHPD_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCHPD_MASK) >> WM8960_DACCTL1_ADCHPD_SHIFT) + +/* Bitfield definition for register: DACCTL2 */ +/* + * DACPOL (RW) + * + * DAC polarity control: + * 00 = Polarity not inverted + * 01 = DAC L inverted + * 10 = DAC R inverted + * 11 = DAC L and R inverted + */ +#define WM8960_DACCTL2_DACPOL_MASK (0x60U) +#define WM8960_DACCTL2_DACPOL_SHIFT (5U) +#define WM8960_DACCTL2_DACPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACPOL_SHIFT) & WM8960_DACCTL2_DACPOL_MASK) +#define WM8960_DACCTL2_DACPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACPOL_MASK) >> WM8960_DACCTL2_DACPOL_SHIFT) + +/* + * DACSMM (RW) + * + * DAC Soft Mute Mode + * 0 = Disabling soft-mute (DACMU=0) will cause + * the volume to change immediately to the + * LDACVOL / RDACVOL settings + * 1 = Disabling soft-mute (DACMU=0) will cause + * the volume to ramp up gradually to the + * LDACVOL / RDACVOL settings + */ +#define WM8960_DACCTL2_DACSMM_MASK (0x8U) +#define WM8960_DACCTL2_DACSMM_SHIFT (3U) +#define WM8960_DACCTL2_DACSMM_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSMM_SHIFT) & WM8960_DACCTL2_DACSMM_MASK) +#define WM8960_DACCTL2_DACSMM_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSMM_MASK) >> WM8960_DACCTL2_DACSMM_SHIFT) + +/* + * DACMR (RW) + * + * DAC Soft Mute Ramp Rate + * 0 = Fast ramp (24kHz at fs=48k, providing + * maximum delay of 10.7ms) + * 1 = Slow ramp (1.5kHz at fs=48k, providing + * maximum delay of 171ms) + */ +#define WM8960_DACCTL2_DACMR_MASK (0x4U) +#define WM8960_DACCTL2_DACMR_SHIFT (2U) +#define WM8960_DACCTL2_DACMR_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACMR_SHIFT) & WM8960_DACCTL2_DACMR_MASK) +#define WM8960_DACCTL2_DACMR_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACMR_MASK) >> WM8960_DACCTL2_DACMR_SHIFT) + +/* + * DACSLOPE (RW) + * + * Selects DAC filter characteristics + * 0 = Normal mode + * 1 = Sloping stopband + */ +#define WM8960_DACCTL2_DACSLOPE_MASK (0x2U) +#define WM8960_DACCTL2_DACSLOPE_SHIFT (1U) +#define WM8960_DACCTL2_DACSLOPE_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSLOPE_SHIFT) & WM8960_DACCTL2_DACSLOPE_MASK) +#define WM8960_DACCTL2_DACSLOPE_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSLOPE_MASK) >> WM8960_DACCTL2_DACSLOPE_SHIFT) + +/* Bitfield definition for register: IFACE1 */ +/* + * ALRSWAP (RW) + * + * Left/Right ADC Channel Swap + * 1 = Swap left and right ADC data in audio + * interface + * 0 = Output left and right data as normal + */ +#define WM8960_IFACE1_ALRSWAP_MASK (0x100U) +#define WM8960_IFACE1_ALRSWAP_SHIFT (8U) +#define WM8960_IFACE1_ALRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) +#define WM8960_IFACE1_ALRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_ALRSWAP_MASK) >> WM8960_IFACE1_ALRSWAP_SHIFT) + +/* + * BCLKINV (RW) + * + * BCLK invert bit (for master and slave modes) + * 0 = BCLK not inverted + * 1 = BCLK inverted + */ +#define WM8960_IFACE1_BCLKINV_MASK (0x80U) +#define WM8960_IFACE1_BCLKINV_SHIFT (7U) +#define WM8960_IFACE1_BCLKINV_SET(x) (((uint16_t)(x) << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) +#define WM8960_IFACE1_BCLKINV_GET(x) (((uint16_t)(x) & WM8960_IFACE1_BCLKINV_MASK) >> WM8960_IFACE1_BCLKINV_SHIFT) + +/* + * MS (RW) + * + * Master / Slave Mode Control + * 0 = Enable slave mode + * 1 = Enable master mode + */ +#define WM8960_IFACE1_MS_MASK (0x40U) +#define WM8960_IFACE1_MS_SHIFT (6U) +#define WM8960_IFACE1_MS_SET(x) (((uint16_t)(x) << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) +#define WM8960_IFACE1_MS_GET(x) (((uint16_t)(x) & WM8960_IFACE1_MS_MASK) >> WM8960_IFACE1_MS_SHIFT) + +/* + * DLRSWAP (RW) + * + * Left/Right DAC Channel Swap + * 0 = Output left and right data as normal + * 1 = Swap left and right DAC data in audio interface + */ +#define WM8960_IFACE1_DLRSWAP_MASK (0x20U) +#define WM8960_IFACE1_DLRSWAP_SHIFT (5U) +#define WM8960_IFACE1_DLRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) +#define WM8960_IFACE1_DLRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_DLRSWAP_MASK) >> WM8960_IFACE1_DLRSWAP_SHIFT) + +/* + * LRP (RW) + * + * Right, left and I2S modes – LRCLK polarity + * 0 = normal LRCLK polarity + * 1 = invert LRCLK polarity + * DSP Mode – mode A/B select + * 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) + * 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) + */ +#define WM8960_IFACE1_LRP_MASK (0x10U) +#define WM8960_IFACE1_LRP_SHIFT (4U) +#define WM8960_IFACE1_LRP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) +#define WM8960_IFACE1_LRP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_LRP_MASK) >> WM8960_IFACE1_LRP_SHIFT) + +/* + * WL (RW) + * + * Audio Data Word Length + * 00 = 16 bits + * 01 = 20 bits + * 10 = 24 bits + * 11 = 32 bits (see Note) + */ +#define WM8960_IFACE1_WL_MASK (0xCU) +#define WM8960_IFACE1_WL_SHIFT (2U) +#define WM8960_IFACE1_WL_SET(x) (((uint16_t)(x) << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) +#define WM8960_IFACE1_WL_GET(x) (((uint16_t)(x) & WM8960_IFACE1_WL_MASK) >> WM8960_IFACE1_WL_SHIFT) + +/* + * FORMAT (RW) + * + * 00 = Right justified + * 01 = Left justified + * 10 = I2S Format + * 11 = DSP Mode + */ +#define WM8960_IFACE1_FORMAT_MASK (0x3U) +#define WM8960_IFACE1_FORMAT_SHIFT (0U) +#define WM8960_IFACE1_FORMAT_SET(x) (((uint16_t)(x) << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) +#define WM8960_IFACE1_FORMAT_GET(x) (((uint16_t)(x) & WM8960_IFACE1_FORMAT_MASK) >> WM8960_IFACE1_FORMAT_SHIFT) + +/* Bitfield definition for register: CLOCK2 */ +/* + * DCLKDIV (RW) + * + * Class D switching clock divider. + * 000 = SYSCLK / 1.5 (Not recommended) + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 6 + * 101 = SYSCLK / 8 + * 110 = SYSCLK / 12 + * 111 = SYSCLK / 16 + */ +#define WM8960_CLOCK2_DCLKDIV_MASK (0x1C0U) +#define WM8960_CLOCK2_DCLKDIV_SHIFT (6U) +#define WM8960_CLOCK2_DCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_DCLKDIV_SHIFT) & WM8960_CLOCK2_DCLKDIV_MASK) +#define WM8960_CLOCK2_DCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_DCLKDIV_MASK) >> WM8960_CLOCK2_DCLKDIV_SHIFT) + +/* + * BCLKDIV (RW) + * + * BCLK Frequency (Master Mode) + * 0000 = SYSCLK + * 0001 = SYSCLK / 1.5 + * 0010 = SYSCLK / 2 + * 0011 = SYSCLK / 3 + * 0100 = SYSCLK / 4 + * 0101 = SYSCLK / 5.5 + * 0110 = SYSCLK / 6 + * 0111 = SYSCLK / 8 + * 1000 = SYSCLK / 11 + * 1001 = SYSCLK / 12 + * 1010 = SYSCLK / 16 + * 1011 = SYSCLK / 22 + * 1100 = SYSCLK / 24 + * 1101 to 1111 = SYSCLK / 32 + */ +#define WM8960_CLOCK2_BCLKDIV_MASK (0xFU) +#define WM8960_CLOCK2_BCLKDIV_SHIFT (0U) +#define WM8960_CLOCK2_BCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_BCLKDIV_SHIFT) & WM8960_CLOCK2_BCLKDIV_MASK) +#define WM8960_CLOCK2_BCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_BCLKDIV_MASK) >> WM8960_CLOCK2_BCLKDIV_SHIFT) + +/* Bitfield definition for register: IFACE2 */ +/* + * ALRCGPIO (RW) + * + * ADCLRC/GPIO1 Pin Function Select + * 0 = ADCLRC frame clock for ADC + * 1 = GPIO pin + */ +#define WM8960_IFACE2_ALRCGPIO_MASK (0x40U) +#define WM8960_IFACE2_ALRCGPIO_SHIFT (6U) +#define WM8960_IFACE2_ALRCGPIO_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ALRCGPIO_SHIFT) & WM8960_IFACE2_ALRCGPIO_MASK) +#define WM8960_IFACE2_ALRCGPIO_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ALRCGPIO_MASK) >> WM8960_IFACE2_ALRCGPIO_SHIFT) + +/* + * WL8 (RW) + * + * 8-Bit Word Length Select (Used with + * companding) + * 0 = Off + * 1 = Device operates in 8-bit mode. + */ +#define WM8960_IFACE2_WL8_MASK (0x20U) +#define WM8960_IFACE2_WL8_SHIFT (5U) +#define WM8960_IFACE2_WL8_SET(x) (((uint16_t)(x) << WM8960_IFACE2_WL8_SHIFT) & WM8960_IFACE2_WL8_MASK) +#define WM8960_IFACE2_WL8_GET(x) (((uint16_t)(x) & WM8960_IFACE2_WL8_MASK) >> WM8960_IFACE2_WL8_SHIFT) + +/* + * DACCOMP (RW) + * + * DAC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_DACCOMP_MASK (0x18U) +#define WM8960_IFACE2_DACCOMP_SHIFT (3U) +#define WM8960_IFACE2_DACCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_DACCOMP_SHIFT) & WM8960_IFACE2_DACCOMP_MASK) +#define WM8960_IFACE2_DACCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_DACCOMP_MASK) >> WM8960_IFACE2_DACCOMP_SHIFT) + +/* + * ADCCOMP (RW) + * + * ADC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_ADCCOMP_MASK (0x6U) +#define WM8960_IFACE2_ADCCOMP_SHIFT (1U) +#define WM8960_IFACE2_ADCCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ADCCOMP_SHIFT) & WM8960_IFACE2_ADCCOMP_MASK) +#define WM8960_IFACE2_ADCCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ADCCOMP_MASK) >> WM8960_IFACE2_ADCCOMP_SHIFT) + +/* + * LOOPBACK (RW) + * + * Digital Loopback Function + * 0 = No loopback. + * 1 = Loopback enabled, ADC data output is fed + * directly into DAC data input + */ +#define WM8960_IFACE2_LOOPBACK_MASK (0x1U) +#define WM8960_IFACE2_LOOPBACK_SHIFT (0U) +#define WM8960_IFACE2_LOOPBACK_SET(x) (((uint16_t)(x) << WM8960_IFACE2_LOOPBACK_SHIFT) & WM8960_IFACE2_LOOPBACK_MASK) +#define WM8960_IFACE2_LOOPBACK_GET(x) (((uint16_t)(x) & WM8960_IFACE2_LOOPBACK_MASK) >> WM8960_IFACE2_LOOPBACK_SHIFT) + +/* Bitfield definition for register: LDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_LDAC_DACVU_MASK (0x100U) +#define WM8960_LDAC_DACVU_SHIFT (8U) +#define WM8960_LDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_LDAC_DACVU_SHIFT) & WM8960_LDAC_DACVU_MASK) +#define WM8960_LDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_LDAC_DACVU_MASK) >> WM8960_LDAC_DACVU_SHIFT) + +/* + * LDACVOL (RW) + * + * Left DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_LDAC_LDACVOL_MASK (0xFFU) +#define WM8960_LDAC_LDACVOL_SHIFT (0U) +#define WM8960_LDAC_LDACVOL_SET(x) (((uint16_t)(x) << WM8960_LDAC_LDACVOL_SHIFT) & WM8960_LDAC_LDACVOL_MASK) +#define WM8960_LDAC_LDACVOL_GET(x) (((uint16_t)(x) & WM8960_LDAC_LDACVOL_MASK) >> WM8960_LDAC_LDACVOL_SHIFT) + +/* Bitfield definition for register: RDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_RDAC_DACVU_MASK (0x100U) +#define WM8960_RDAC_DACVU_SHIFT (8U) +#define WM8960_RDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_RDAC_DACVU_SHIFT) & WM8960_RDAC_DACVU_MASK) +#define WM8960_RDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_RDAC_DACVU_MASK) >> WM8960_RDAC_DACVU_SHIFT) + +/* + * RDACVOL (RW) + * + * Right DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_RDAC_RDACVOL_MASK (0xFFU) +#define WM8960_RDAC_RDACVOL_SHIFT (0U) +#define WM8960_RDAC_RDACVOL_SET(x) (((uint16_t)(x) << WM8960_RDAC_RDACVOL_SHIFT) & WM8960_RDAC_RDACVOL_MASK) +#define WM8960_RDAC_RDACVOL_GET(x) (((uint16_t)(x) & WM8960_RDAC_RDACVOL_MASK) >> WM8960_RDAC_RDACVOL_SHIFT) + +/* Bitfield definition for register: RESET */ +/* + * RESET (RW) + * + * Writing to this register resets all registers to their default state. + */ +#define WM8960_RESET_RESET_MASK (0x1FFU) +#define WM8960_RESET_RESET_SHIFT (0U) +#define WM8960_RESET_RESET_SET(x) (((uint16_t)(x) << WM8960_RESET_RESET_SHIFT) & WM8960_RESET_RESET_MASK) +#define WM8960_RESET_RESET_GET(x) (((uint16_t)(x) & WM8960_RESET_RESET_MASK) >> WM8960_RESET_RESET_SHIFT) + +/* Bitfield definition for register: 3D */ +/* + * 3DUC (RW) + * + * 3D Enhance Filter Upper Cut-Off Frequency + * 0 = High (Recommended for fs>=32kHz) + * 1 = Low (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DUC_MASK (0x40U) +#define WM8960_3D_3DUC_SHIFT (6U) +#define WM8960_3D_3DUC_SET(x) (((uint16_t)(x) << WM8960_3D_3DUC_SHIFT) & WM8960_3D_3DUC_MASK) +#define WM8960_3D_3DUC_GET(x) (((uint16_t)(x) & WM8960_3D_3DUC_MASK) >> WM8960_3D_3DUC_SHIFT) + +/* + * 3DLC (RW) + * + * 3D Enhance Filter Lower Cut-Off Frequency + * 0 = Low (Recommended for fs>=32kHz) + * 1 = High (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DLC_MASK (0x20U) +#define WM8960_3D_3DLC_SHIFT (5U) +#define WM8960_3D_3DLC_SET(x) (((uint16_t)(x) << WM8960_3D_3DLC_SHIFT) & WM8960_3D_3DLC_MASK) +#define WM8960_3D_3DLC_GET(x) (((uint16_t)(x) & WM8960_3D_3DLC_MASK) >> WM8960_3D_3DLC_SHIFT) + +/* + * 3DDEPTH (RW) + * + * 3D Stereo Depth + * 0000 = 0% (minimum 3D effect) + * 0001 = 6.67% + * .... + * 1110 = 93.3% + * 1111 = 100% (maximum 3D effect) + */ +#define WM8960_3D_3DDEPTH_MASK (0x1EU) +#define WM8960_3D_3DDEPTH_SHIFT (1U) +#define WM8960_3D_3DDEPTH_SET(x) (((uint16_t)(x) << WM8960_3D_3DDEPTH_SHIFT) & WM8960_3D_3DDEPTH_MASK) +#define WM8960_3D_3DDEPTH_GET(x) (((uint16_t)(x) & WM8960_3D_3DDEPTH_MASK) >> WM8960_3D_3DDEPTH_SHIFT) + +/* + * 3DEN (RW) + * + * 3D Stereo Enhancement Enable + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_3D_3DEN_MASK (0x1U) +#define WM8960_3D_3DEN_SHIFT (0U) +#define WM8960_3D_3DEN_SET(x) (((uint16_t)(x) << WM8960_3D_3DEN_SHIFT) & WM8960_3D_3DEN_MASK) +#define WM8960_3D_3DEN_GET(x) (((uint16_t)(x) & WM8960_3D_3DEN_MASK) >> WM8960_3D_3DEN_SHIFT) + +/* Bitfield definition for register: ALC1 */ +/* + * ALCSEL (RW) + * + * ALC Function Select + * 00 = ALC off (PGA gain set by register) + * 01 = Right channel only + * 10 = Left channel only + * 11 = Stereo (PGA registers unused) Note: + * ensure that LINVOL and RINVOL settings + * (reg. 0 and 1) are the same before entering this mode. + */ +#define WM8960_ALC1_ALCSEL_MASK (0x180U) +#define WM8960_ALC1_ALCSEL_SHIFT (7U) +#define WM8960_ALC1_ALCSEL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCSEL_SHIFT) & WM8960_ALC1_ALCSEL_MASK) +#define WM8960_ALC1_ALCSEL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCSEL_MASK) >> WM8960_ALC1_ALCSEL_SHIFT) + +/* + * MAXGAIN (RW) + * + * Set Maximum Gain of PGA (During ALC + * operation) + * 111 : +30dB + * 110 : +24dB + * ….(-6dB steps) + * 001 : -6dB + * 000 : -12dB + */ +#define WM8960_ALC1_MAXGAIN_MASK (0x70U) +#define WM8960_ALC1_MAXGAIN_SHIFT (4U) +#define WM8960_ALC1_MAXGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC1_MAXGAIN_SHIFT) & WM8960_ALC1_MAXGAIN_MASK) +#define WM8960_ALC1_MAXGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC1_MAXGAIN_MASK) >> WM8960_ALC1_MAXGAIN_SHIFT) + +/* + * ALCL (RW) + * + * ALC Target (Sets signal level at ADC input) + * 0000 = -22.5dB FS + * 0001 = -21.0dB FS + * … (1.5dB steps) + * 1101 = -3.0dB FS + * 1110 = -1.5dB FS + * 1111 = -1.5dB FS + */ +#define WM8960_ALC1_ALCL_MASK (0xFU) +#define WM8960_ALC1_ALCL_SHIFT (0U) +#define WM8960_ALC1_ALCL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCL_SHIFT) & WM8960_ALC1_ALCL_MASK) +#define WM8960_ALC1_ALCL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCL_MASK) >> WM8960_ALC1_ALCL_SHIFT) + +/* Bitfield definition for register: ALC2 */ +/* + * MINGAIN (RW) + * + * Set Minimum Gain of PGA (During ALC + * operation) + * 000 = -17.25dB + * 001 = -11.25dB + * 010 = -5.25dB + * 011 = +0.75dB + * 100 = +6.75dB + * 101 = +12.75dB + * 110 = +18.75dB + * 111 = +24.75dB + */ +#define WM8960_ALC2_MINGAIN_MASK (0x70U) +#define WM8960_ALC2_MINGAIN_SHIFT (4U) +#define WM8960_ALC2_MINGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC2_MINGAIN_SHIFT) & WM8960_ALC2_MINGAIN_MASK) +#define WM8960_ALC2_MINGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC2_MINGAIN_MASK) >> WM8960_ALC2_MINGAIN_SHIFT) + +/* + * HLD (RW) + * + * ALC hold time before gain is increased. + * 0000 = 0ms + * 0001 = 2.67ms + * 0010 = 5.33ms + * … (time doubles with every step) + * 1111 = 43.691s + */ +#define WM8960_ALC2_HLD_MASK (0xFU) +#define WM8960_ALC2_HLD_SHIFT (0U) +#define WM8960_ALC2_HLD_SET(x) (((uint16_t)(x) << WM8960_ALC2_HLD_SHIFT) & WM8960_ALC2_HLD_MASK) +#define WM8960_ALC2_HLD_GET(x) (((uint16_t)(x) & WM8960_ALC2_HLD_MASK) >> WM8960_ALC2_HLD_SHIFT) + +/* Bitfield definition for register: ALC3 */ +/* + * ALCMODE (RW) + * + * Determines the ALC mode of operation: + * 0 = ALC mode + * 1 = Limiter mode + */ +#define WM8960_ALC3_ALCMODE_MASK (0x100U) +#define WM8960_ALC3_ALCMODE_SHIFT (8U) +#define WM8960_ALC3_ALCMODE_SET(x) (((uint16_t)(x) << WM8960_ALC3_ALCMODE_SHIFT) & WM8960_ALC3_ALCMODE_MASK) +#define WM8960_ALC3_ALCMODE_GET(x) (((uint16_t)(x) & WM8960_ALC3_ALCMODE_MASK) >> WM8960_ALC3_ALCMODE_SHIFT) + +/* + * DCY (RW) + * + * ALC decay (gain ramp-up) time + * 0000 = 24ms + * 0001 = 48ms + * 0010 = 96ms + * … (time doubles with every step) + * 1010 or higher = 24.58s + */ +#define WM8960_ALC3_DCY_MASK (0xF0U) +#define WM8960_ALC3_DCY_SHIFT (4U) +#define WM8960_ALC3_DCY_SET(x) (((uint16_t)(x) << WM8960_ALC3_DCY_SHIFT) & WM8960_ALC3_DCY_MASK) +#define WM8960_ALC3_DCY_GET(x) (((uint16_t)(x) & WM8960_ALC3_DCY_MASK) >> WM8960_ALC3_DCY_SHIFT) + +/* + * ATK (RW) + * + * ALC attack (gain ramp-down) time + * 0000 = 6ms + * 0001 = 12ms + * 0010 = 24ms + * … (time doubles with every step) + * 1010 or higher = 6.14s + */ +#define WM8960_ALC3_ATK_MASK (0xFU) +#define WM8960_ALC3_ATK_SHIFT (0U) +#define WM8960_ALC3_ATK_SET(x) (((uint16_t)(x) << WM8960_ALC3_ATK_SHIFT) & WM8960_ALC3_ATK_MASK) +#define WM8960_ALC3_ATK_GET(x) (((uint16_t)(x) & WM8960_ALC3_ATK_MASK) >> WM8960_ALC3_ATK_SHIFT) + +/* Bitfield definition for register: NOISEG */ +/* + * NGTH (RW) + * + * Noise gate threshold + * 00000 -76.5dBfs + * 00001 -75dBfs + * … 1.5 dB steps + * 11110 -31.5dBfs + * 11111 -30dBfs + */ +#define WM8960_NOISEG_NGTH_MASK (0xF8U) +#define WM8960_NOISEG_NGTH_SHIFT (3U) +#define WM8960_NOISEG_NGTH_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGTH_SHIFT) & WM8960_NOISEG_NGTH_MASK) +#define WM8960_NOISEG_NGTH_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGTH_MASK) >> WM8960_NOISEG_NGTH_SHIFT) + +/* + * NGAT (RW) + * + * Noise gate function enable + * 0 = disable + * 1 = enable + */ +#define WM8960_NOISEG_NGAT_MASK (0x1U) +#define WM8960_NOISEG_NGAT_SHIFT (0U) +#define WM8960_NOISEG_NGAT_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGAT_SHIFT) & WM8960_NOISEG_NGAT_MASK) +#define WM8960_NOISEG_NGAT_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGAT_MASK) >> WM8960_NOISEG_NGAT_SHIFT) + +/* Bitfield definition for register: LADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and + * RADCVOL) + */ +#define WM8960_LADC_ADCVU_MASK (0x100U) +#define WM8960_LADC_ADCVU_SHIFT (8U) +#define WM8960_LADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_LADC_ADCVU_SHIFT) & WM8960_LADC_ADCVU_MASK) +#define WM8960_LADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_LADC_ADCVU_MASK) >> WM8960_LADC_ADCVU_SHIFT) + +/* + * LADCVOL (RW) + * + * Left ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_LADC_LADCVOL_MASK (0xFFU) +#define WM8960_LADC_LADCVOL_SHIFT (0U) +#define WM8960_LADC_LADCVOL_SET(x) (((uint16_t)(x) << WM8960_LADC_LADCVOL_SHIFT) & WM8960_LADC_LADCVOL_MASK) +#define WM8960_LADC_LADCVOL_GET(x) (((uint16_t)(x) & WM8960_LADC_LADCVOL_MASK) >> WM8960_LADC_LADCVOL_SHIFT) + +/* Bitfield definition for register: RADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and RADCVOL) + */ +#define WM8960_RADC_ADCVU_MASK (0x100U) +#define WM8960_RADC_ADCVU_SHIFT (8U) +#define WM8960_RADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_RADC_ADCVU_SHIFT) & WM8960_RADC_ADCVU_MASK) +#define WM8960_RADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_RADC_ADCVU_MASK) >> WM8960_RADC_ADCVU_SHIFT) + +/* + * RADCVOL (RW) + * + * Right ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_RADC_RADCVOL_MASK (0xFFU) +#define WM8960_RADC_RADCVOL_SHIFT (0U) +#define WM8960_RADC_RADCVOL_SET(x) (((uint16_t)(x) << WM8960_RADC_RADCVOL_SHIFT) & WM8960_RADC_RADCVOL_MASK) +#define WM8960_RADC_RADCVOL_GET(x) (((uint16_t)(x) & WM8960_RADC_RADCVOL_MASK) >> WM8960_RADC_RADCVOL_SHIFT) + +/* Bitfield definition for register: ADDCTL1 */ +/* + * TSDEN (RW) + * + * Thermal Shutdown Enable + * 0 = Thermal shutdown disabled + * 1 = Thermal shutdown enabled + * (TSENSEN must be enabled for this function to work) + */ +#define WM8960_ADDCTL1_TSDEN_MASK (0x100U) +#define WM8960_ADDCTL1_TSDEN_SHIFT (8U) +#define WM8960_ADDCTL1_TSDEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TSDEN_SHIFT) & WM8960_ADDCTL1_TSDEN_MASK) +#define WM8960_ADDCTL1_TSDEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TSDEN_MASK) >> WM8960_ADDCTL1_TSDEN_SHIFT) + +/* + * VSEL (RW) + * + * Analogue Bias Optimisation + * 00 = Reserved + * 01 = Increased bias current optimized for + * AVDD=2.7V + * 1X = Lowest bias current, optimized for + * AVDD=3.3V + */ +#define WM8960_ADDCTL1_VSEL_MASK (0xC0U) +#define WM8960_ADDCTL1_VSEL_SHIFT (6U) +#define WM8960_ADDCTL1_VSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_VSEL_SHIFT) & WM8960_ADDCTL1_VSEL_MASK) +#define WM8960_ADDCTL1_VSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_VSEL_MASK) >> WM8960_ADDCTL1_VSEL_SHIFT) + +/* + * DMONOMIX (RW) + * + * DAC Mono Mix + * 0 = Stereo + * 1 = Mono (Mono MIX output on enabled DACs + */ +#define WM8960_ADDCTL1_DMONOMIX_MASK (0x10U) +#define WM8960_ADDCTL1_DMONOMIX_SHIFT (4U) +#define WM8960_ADDCTL1_DMONOMIX_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DMONOMIX_SHIFT) & WM8960_ADDCTL1_DMONOMIX_MASK) +#define WM8960_ADDCTL1_DMONOMIX_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DMONOMIX_MASK) >> WM8960_ADDCTL1_DMONOMIX_SHIFT) + +/* + * DATSEL (RW) + * + * ADC Data Output Select + * 00: left data = left ADC; right data =right ADC + * 01: left data = left ADC; right data = left ADC + * 10: left data = right ADC; right data =right ADC + * 11: left data = right ADC; right data = left ADC + */ +#define WM8960_ADDCTL1_DATSEL_MASK (0xCU) +#define WM8960_ADDCTL1_DATSEL_SHIFT (2U) +#define WM8960_ADDCTL1_DATSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DATSEL_SHIFT) & WM8960_ADDCTL1_DATSEL_MASK) +#define WM8960_ADDCTL1_DATSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DATSEL_MASK) >> WM8960_ADDCTL1_DATSEL_SHIFT) + +/* + * TOCLKSEL (RW) + * + * Slow Clock Select (Used for volume update + * timeouts and for jack detect debounce) + * 0 = SYSCLK / 221 (Slower Response) + * 1 = SYSCLK / 219 (Faster Response) + */ +#define WM8960_ADDCTL1_TOCLKSEL_MASK (0x2U) +#define WM8960_ADDCTL1_TOCLKSEL_SHIFT (1U) +#define WM8960_ADDCTL1_TOCLKSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOCLKSEL_SHIFT) & WM8960_ADDCTL1_TOCLKSEL_MASK) +#define WM8960_ADDCTL1_TOCLKSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOCLKSEL_MASK) >> WM8960_ADDCTL1_TOCLKSEL_SHIFT) + +/* + * TOEN (RW) + * + * Enables Slow Clock for Volume Update Timeout + * and Jack Detect Debounce + * 0 = Slow clock disabled + * 1 = Slow clock enabled + */ +#define WM8960_ADDCTL1_TOEN_MASK (0x1U) +#define WM8960_ADDCTL1_TOEN_SHIFT (0U) +#define WM8960_ADDCTL1_TOEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOEN_SHIFT) & WM8960_ADDCTL1_TOEN_MASK) +#define WM8960_ADDCTL1_TOEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOEN_MASK) >> WM8960_ADDCTL1_TOEN_SHIFT) + +/* Bitfield definition for register: ADDCTL2 */ +/* + * HPSWEN (RW) + * + * Headphone Switch Enable + * 0 = Headphone switch disabled + * 1 = Headphone switch enabled + */ +#define WM8960_ADDCTL2_HPSWEN_MASK (0x40U) +#define WM8960_ADDCTL2_HPSWEN_SHIFT (6U) +#define WM8960_ADDCTL2_HPSWEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWEN_SHIFT) & WM8960_ADDCTL2_HPSWEN_MASK) +#define WM8960_ADDCTL2_HPSWEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWEN_MASK) >> WM8960_ADDCTL2_HPSWEN_SHIFT) + +/* + * HPSWPOL (RW) + * + * Headphone Switch Polarity + * 0 = HPDETECT high = headphone + * 1 = HPDETECT high = speaker + */ +#define WM8960_ADDCTL2_HPSWPOL_MASK (0x20U) +#define WM8960_ADDCTL2_HPSWPOL_SHIFT (5U) +#define WM8960_ADDCTL2_HPSWPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWPOL_SHIFT) & WM8960_ADDCTL2_HPSWPOL_MASK) +#define WM8960_ADDCTL2_HPSWPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWPOL_MASK) >> WM8960_ADDCTL2_HPSWPOL_SHIFT) + +/* + * TRIS (RW) + * + * Tristates ADCDAT and switches ADCLRC, + * DACLRC and BCLK to inputs. + * 0 = ADCDAT is an output; ADCLRC, DACLRC + * and BCLK are inputs (slave mode) or outputs + * (master mode) + * 1 = ADCDAT is tristated; DACLRC and BCLK + * are inputs; ADCLRC is an input (when not + * configured as a GPIO) + */ +#define WM8960_ADDCTL2_TRIS_MASK (0x8U) +#define WM8960_ADDCTL2_TRIS_SHIFT (3U) +#define WM8960_ADDCTL2_TRIS_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_TRIS_SHIFT) & WM8960_ADDCTL2_TRIS_MASK) +#define WM8960_ADDCTL2_TRIS_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_TRIS_MASK) >> WM8960_ADDCTL2_TRIS_SHIFT) + +/* + * LRCM (RW) + * + * Selects disable mode for ADCLRC and DACLRC + * (Master mode) + * 0 = ADCLRC disabled when ADC (Left and + * Right) disabled; DACLRC disabled when + * DAC (Left and Right) disabled. + * 1 = ADCLRC and DACLRC disabled only when + * ADC (Left and Right) and DAC (Left and Right) + * are disabled. + */ +#define WM8960_ADDCTL2_LRCM_MASK (0x4U) +#define WM8960_ADDCTL2_LRCM_SHIFT (2U) +#define WM8960_ADDCTL2_LRCM_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_LRCM_SHIFT) & WM8960_ADDCTL2_LRCM_MASK) +#define WM8960_ADDCTL2_LRCM_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_LRCM_MASK) >> WM8960_ADDCTL2_LRCM_SHIFT) + +/* Bitfield definition for register: POWER1 */ +/* + * VMIDSEL (RW) + * + * Vmid Divider Enable and Select + * 00 = Vmid disabled (for OFF mode) + * 01 = 2 x 50k divider enabled (for playback / + * record) + * 10 = 2 x 250k divider enabled (for low-power + * standby) + * 11 = 2 x 5k divider enabled (for fast start-up) + */ +#define WM8960_POWER1_VMIDSEL_MASK (0x180U) +#define WM8960_POWER1_VMIDSEL_SHIFT (7U) +#define WM8960_POWER1_VMIDSEL_SET(x) (((uint16_t)(x) << WM8960_POWER1_VMIDSEL_SHIFT) & WM8960_POWER1_VMIDSEL_MASK) +#define WM8960_POWER1_VMIDSEL_GET(x) (((uint16_t)(x) & WM8960_POWER1_VMIDSEL_MASK) >> WM8960_POWER1_VMIDSEL_SHIFT) + +/* + * VREF (RW) + * + * VREF (necessary for all other functions) + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_VREF_MASK (0x40U) +#define WM8960_POWER1_VREF_SHIFT (6U) +#define WM8960_POWER1_VREF_SET(x) (((uint16_t)(x) << WM8960_POWER1_VREF_SHIFT) & WM8960_POWER1_VREF_MASK) +#define WM8960_POWER1_VREF_GET(x) (((uint16_t)(x) & WM8960_POWER1_VREF_MASK) >> WM8960_POWER1_VREF_SHIFT) + +/* + * AINL (RW) + * + * Analogue in PGA Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINL_MASK (0x20U) +#define WM8960_POWER1_AINL_SHIFT (5U) +#define WM8960_POWER1_AINL_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINL_SHIFT) & WM8960_POWER1_AINL_MASK) +#define WM8960_POWER1_AINL_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINL_MASK) >> WM8960_POWER1_AINL_SHIFT) + +/* + * AINR (RW) + * + * Analogue in PGA Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINR_MASK (0x10U) +#define WM8960_POWER1_AINR_SHIFT (4U) +#define WM8960_POWER1_AINR_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINR_SHIFT) & WM8960_POWER1_AINR_MASK) +#define WM8960_POWER1_AINR_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINR_MASK) >> WM8960_POWER1_AINR_SHIFT) + +/* + * ADCL (RW) + * + * ADC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCL_MASK (0x8U) +#define WM8960_POWER1_ADCL_SHIFT (3U) +#define WM8960_POWER1_ADCL_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCL_SHIFT) & WM8960_POWER1_ADCL_MASK) +#define WM8960_POWER1_ADCL_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCL_MASK) >> WM8960_POWER1_ADCL_SHIFT) + +/* + * ADCR (RW) + * + * ADC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCR_MASK (0x4U) +#define WM8960_POWER1_ADCR_SHIFT (2U) +#define WM8960_POWER1_ADCR_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCR_SHIFT) & WM8960_POWER1_ADCR_MASK) +#define WM8960_POWER1_ADCR_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCR_MASK) >> WM8960_POWER1_ADCR_SHIFT) + +/* + * MICB (RW) + * + * MICBIAS + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_MICB_MASK (0x2U) +#define WM8960_POWER1_MICB_SHIFT (1U) +#define WM8960_POWER1_MICB_SET(x) (((uint16_t)(x) << WM8960_POWER1_MICB_SHIFT) & WM8960_POWER1_MICB_MASK) +#define WM8960_POWER1_MICB_GET(x) (((uint16_t)(x) & WM8960_POWER1_MICB_MASK) >> WM8960_POWER1_MICB_SHIFT) + +/* + * DIGENB (RW) + * + * Master Clock Disable + * 0 = Master clock enabled + * 1 = Master clock disabled + */ +#define WM8960_POWER1_DIGENB_MASK (0x1U) +#define WM8960_POWER1_DIGENB_SHIFT (0U) +#define WM8960_POWER1_DIGENB_SET(x) (((uint16_t)(x) << WM8960_POWER1_DIGENB_SHIFT) & WM8960_POWER1_DIGENB_MASK) +#define WM8960_POWER1_DIGENB_GET(x) (((uint16_t)(x) & WM8960_POWER1_DIGENB_MASK) >> WM8960_POWER1_DIGENB_SHIFT) + +/* Bitfield definition for register: POWER2 */ +/* + * DACL (RW) + * + * DAC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACL_MASK (0x100U) +#define WM8960_POWER2_DACL_SHIFT (8U) +#define WM8960_POWER2_DACL_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACL_SHIFT) & WM8960_POWER2_DACL_MASK) +#define WM8960_POWER2_DACL_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACL_MASK) >> WM8960_POWER2_DACL_SHIFT) + +/* + * DACR (RW) + * + * DAC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACR_MASK (0x80U) +#define WM8960_POWER2_DACR_SHIFT (7U) +#define WM8960_POWER2_DACR_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACR_SHIFT) & WM8960_POWER2_DACR_MASK) +#define WM8960_POWER2_DACR_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACR_MASK) >> WM8960_POWER2_DACR_SHIFT) + +/* + * LOUT1 (RW) + * + * LOUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_LOUT1_MASK (0x40U) +#define WM8960_POWER2_LOUT1_SHIFT (6U) +#define WM8960_POWER2_LOUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_LOUT1_SHIFT) & WM8960_POWER2_LOUT1_MASK) +#define WM8960_POWER2_LOUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_LOUT1_MASK) >> WM8960_POWER2_LOUT1_SHIFT) + +/* + * ROUT1 (RW) + * + * ROUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_ROUT1_MASK (0x20U) +#define WM8960_POWER2_ROUT1_SHIFT (5U) +#define WM8960_POWER2_ROUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_ROUT1_SHIFT) & WM8960_POWER2_ROUT1_MASK) +#define WM8960_POWER2_ROUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_ROUT1_MASK) >> WM8960_POWER2_ROUT1_SHIFT) + +/* + * SPKL (RW) + * + * SPK_LP/SPK_LN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKL_MASK (0x10U) +#define WM8960_POWER2_SPKL_SHIFT (4U) +#define WM8960_POWER2_SPKL_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKL_SHIFT) & WM8960_POWER2_SPKL_MASK) +#define WM8960_POWER2_SPKL_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKL_MASK) >> WM8960_POWER2_SPKL_SHIFT) + +/* + * SPKR (RW) + * + * SPK_RP/SPK_RN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKR_MASK (0x8U) +#define WM8960_POWER2_SPKR_SHIFT (3U) +#define WM8960_POWER2_SPKR_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKR_SHIFT) & WM8960_POWER2_SPKR_MASK) +#define WM8960_POWER2_SPKR_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKR_MASK) >> WM8960_POWER2_SPKR_SHIFT) + +/* + * OUT3 (RW) + * + * OUT3 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_OUT3_MASK (0x2U) +#define WM8960_POWER2_OUT3_SHIFT (1U) +#define WM8960_POWER2_OUT3_SET(x) (((uint16_t)(x) << WM8960_POWER2_OUT3_SHIFT) & WM8960_POWER2_OUT3_MASK) +#define WM8960_POWER2_OUT3_GET(x) (((uint16_t)(x) & WM8960_POWER2_OUT3_MASK) >> WM8960_POWER2_OUT3_SHIFT) + +/* + * PLL_EN (RW) + * + * PLL Enable + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_PLL_EN_MASK (0x1U) +#define WM8960_POWER2_PLL_EN_SHIFT (0U) +#define WM8960_POWER2_PLL_EN_SET(x) (((uint16_t)(x) << WM8960_POWER2_PLL_EN_SHIFT) & WM8960_POWER2_PLL_EN_MASK) +#define WM8960_POWER2_PLL_EN_GET(x) (((uint16_t)(x) & WM8960_POWER2_PLL_EN_MASK) >> WM8960_POWER2_PLL_EN_SHIFT) + +/* Bitfield definition for register: ADDCTL3 */ +/* + * VROI (RW) + * + * VREF to Analogue Output Resistance (Disabled + * Outputs) + * 0 = 500 VMID to output + * 1 = 20k VMID to output + */ +#define WM8960_ADDCTL3_VROI_MASK (0x40U) +#define WM8960_ADDCTL3_VROI_SHIFT (6U) +#define WM8960_ADDCTL3_VROI_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_VROI_SHIFT) & WM8960_ADDCTL3_VROI_MASK) +#define WM8960_ADDCTL3_VROI_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_VROI_MASK) >> WM8960_ADDCTL3_VROI_SHIFT) + +/* + * OUT3CAP (RW) + * + * Capless Mode Headphone Switch Enable + * 0 = OUT3 unaffected by jack detect events + * 1 = OUT3 enabled and disabled together with + * HP_L and HP_R in response to jack detect + * events + */ +#define WM8960_ADDCTL3_OUT3CAP_MASK (0x8U) +#define WM8960_ADDCTL3_OUT3CAP_SHIFT (3U) +#define WM8960_ADDCTL3_OUT3CAP_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_OUT3CAP_SHIFT) & WM8960_ADDCTL3_OUT3CAP_MASK) +#define WM8960_ADDCTL3_OUT3CAP_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_OUT3CAP_MASK) >> WM8960_ADDCTL3_OUT3CAP_SHIFT) + +/* + * ADC_ALC_SR (RW) + * + * ALC Sample Rate + * 000 = 44.1k / 48k + * 001 = 32k + * 010 = 22.05k / 24k + * 011 = 16k + * 100 = 11.25k / 12k + * 101 = 8k + * 110 and 111 = Reserved + */ +#define WM8960_ADDCTL3_ADC_ALC_SR_MASK (0x7U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SHIFT (0U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) +#define WM8960_ADDCTL3_ADC_ALC_SR_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) >> WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) + +/* Bitfield definition for register: APOP1 */ +/* + * POBCTRL (RW) + * + * Selects the bias current source for output + * amplifiers and VMID buffer + * 0 = VMID / R bias + * 1 = VGS / R bias + */ +#define WM8960_APOP1_POBCTRL_MASK (0x80U) +#define WM8960_APOP1_POBCTRL_SHIFT (7U) +#define WM8960_APOP1_POBCTRL_SET(x) (((uint16_t)(x) << WM8960_APOP1_POBCTRL_SHIFT) & WM8960_APOP1_POBCTRL_MASK) +#define WM8960_APOP1_POBCTRL_GET(x) (((uint16_t)(x) & WM8960_APOP1_POBCTRL_MASK) >> WM8960_APOP1_POBCTRL_SHIFT) + +/* + * BUFDCOPEN (RW) + * + * Enables the VGS / R current generator + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFDCOPEN_MASK (0x10U) +#define WM8960_APOP1_BUFDCOPEN_SHIFT (4U) +#define WM8960_APOP1_BUFDCOPEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFDCOPEN_SHIFT) & WM8960_APOP1_BUFDCOPEN_MASK) +#define WM8960_APOP1_BUFDCOPEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFDCOPEN_MASK) >> WM8960_APOP1_BUFDCOPEN_SHIFT) + +/* + * BUFIOEN (RW) + * + * Enables the VGS / R current generator and the + * analogue input and output bias + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFIOEN_MASK (0x8U) +#define WM8960_APOP1_BUFIOEN_SHIFT (3U) +#define WM8960_APOP1_BUFIOEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFIOEN_SHIFT) & WM8960_APOP1_BUFIOEN_MASK) +#define WM8960_APOP1_BUFIOEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFIOEN_MASK) >> WM8960_APOP1_BUFIOEN_SHIFT) + +/* + * SOFT_ST (RW) + * + * Enables VMID soft start + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_SOFT_ST_MASK (0x4U) +#define WM8960_APOP1_SOFT_ST_SHIFT (2U) +#define WM8960_APOP1_SOFT_ST_SET(x) (((uint16_t)(x) << WM8960_APOP1_SOFT_ST_SHIFT) & WM8960_APOP1_SOFT_ST_MASK) +#define WM8960_APOP1_SOFT_ST_GET(x) (((uint16_t)(x) & WM8960_APOP1_SOFT_ST_MASK) >> WM8960_APOP1_SOFT_ST_SHIFT) + +/* + * HPSTBY (RW) + * + * Headphone Amplifier Standby + * 0 = Standby mode disabled (Normal operation) + * 1 = Standby mode enabled + */ +#define WM8960_APOP1_HPSTBY_MASK (0x1U) +#define WM8960_APOP1_HPSTBY_SHIFT (0U) +#define WM8960_APOP1_HPSTBY_SET(x) (((uint16_t)(x) << WM8960_APOP1_HPSTBY_SHIFT) & WM8960_APOP1_HPSTBY_MASK) +#define WM8960_APOP1_HPSTBY_GET(x) (((uint16_t)(x) & WM8960_APOP1_HPSTBY_MASK) >> WM8960_APOP1_HPSTBY_SHIFT) + +/* Bitfield definition for register: APOP2 */ +/* + * DISOP (RW) + * + * Discharges the DC-blocking headphone + * capacitors on HP_L and HP_R + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP2_DISOP_MASK (0x40U) +#define WM8960_APOP2_DISOP_SHIFT (6U) +#define WM8960_APOP2_DISOP_SET(x) (((uint16_t)(x) << WM8960_APOP2_DISOP_SHIFT) & WM8960_APOP2_DISOP_MASK) +#define WM8960_APOP2_DISOP_GET(x) (((uint16_t)(x) & WM8960_APOP2_DISOP_MASK) >> WM8960_APOP2_DISOP_SHIFT) + +/* + * DRES (RW) + * + * DRES determines the value of the resistors used + * to discharge the DC-blocking headphone + * capacitors when DISOP=1 + * DRES[1:0] Resistance (Ohms) + * 0 0 400 + * 0 1 200 + * 1 0 600 + * 1 1 150 + */ +#define WM8960_APOP2_DRES_MASK (0x30U) +#define WM8960_APOP2_DRES_SHIFT (4U) +#define WM8960_APOP2_DRES_SET(x) (((uint16_t)(x) << WM8960_APOP2_DRES_SHIFT) & WM8960_APOP2_DRES_MASK) +#define WM8960_APOP2_DRES_GET(x) (((uint16_t)(x) & WM8960_APOP2_DRES_MASK) >> WM8960_APOP2_DRES_SHIFT) + +/* Bitfield definition for register: LINPATH */ +/* + * LMN1 (RW) + * + * Connect LINPUT1 to inverting input of Left Input + * PGA + * 0 = LINPUT1 not connected to PGA + * 1 = LINPUT1 connected to PGA + */ +#define WM8960_LINPATH_LMN1_MASK (0x100U) +#define WM8960_LINPATH_LMN1_SHIFT (8U) +#define WM8960_LINPATH_LMN1_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMN1_SHIFT) & WM8960_LINPATH_LMN1_MASK) +#define WM8960_LINPATH_LMN1_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMN1_MASK) >> WM8960_LINPATH_LMN1_SHIFT) + +/* + * LMP3 (RW) + * + * Connect LINPUT3 to non-inverting input of Left + * Input PGA + * 0 = LINPUT3 not connected to PGA + * 1 = LINPUT3 connected to PGA (Constant input + * impedance) + */ +#define WM8960_LINPATH_LMP3_MASK (0x80U) +#define WM8960_LINPATH_LMP3_SHIFT (7U) +#define WM8960_LINPATH_LMP3_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP3_SHIFT) & WM8960_LINPATH_LMP3_MASK) +#define WM8960_LINPATH_LMP3_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP3_MASK) >> WM8960_LINPATH_LMP3_SHIFT) + +/* + * LMP2 (RW) + * + * Connect LINPUT2 to non-inverting input of Left + * Input PGA + * 0 = LINPUT2 not connected to PGA + * 1 = LINPUT2 connected to PGA (Constant input impedance) + */ +#define WM8960_LINPATH_LMP2_MASK (0x40U) +#define WM8960_LINPATH_LMP2_SHIFT (6U) +#define WM8960_LINPATH_LMP2_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP2_SHIFT) & WM8960_LINPATH_LMP2_MASK) +#define WM8960_LINPATH_LMP2_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP2_MASK) >> WM8960_LINPATH_LMP2_SHIFT) + +/* + * LMICBOOST (RW) + * + * Left Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_LINPATH_LMICBOOST_MASK (0x30U) +#define WM8960_LINPATH_LMICBOOST_SHIFT (4U) +#define WM8960_LINPATH_LMICBOOST_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMICBOOST_SHIFT) & WM8960_LINPATH_LMICBOOST_MASK) +#define WM8960_LINPATH_LMICBOOST_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMICBOOST_MASK) >> WM8960_LINPATH_LMICBOOST_SHIFT) + +/* + * LMIC2B (RW) + * + * Connect Left Input PGA to Left Input Boost Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_LINPATH_LMIC2B_MASK (0x8U) +#define WM8960_LINPATH_LMIC2B_SHIFT (3U) +#define WM8960_LINPATH_LMIC2B_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMIC2B_SHIFT) & WM8960_LINPATH_LMIC2B_MASK) +#define WM8960_LINPATH_LMIC2B_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMIC2B_MASK) >> WM8960_LINPATH_LMIC2B_SHIFT) + +/* Bitfield definition for register: RINPATH */ +/* + * RMN1 (RW) + * + * Connect RINPUT1 to inverting input of Right + * Input PGA + * 0 = RINPUT1 not connected to PGA + * 1 = RINPUT1 connected to PGA + */ +#define WM8960_RINPATH_RMN1_MASK (0x100U) +#define WM8960_RINPATH_RMN1_SHIFT (8U) +#define WM8960_RINPATH_RMN1_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMN1_SHIFT) & WM8960_RINPATH_RMN1_MASK) +#define WM8960_RINPATH_RMN1_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMN1_MASK) >> WM8960_RINPATH_RMN1_SHIFT) + +/* + * RMP3 (RW) + * + * Connect RINPUT3 to non-inverting input of Right + * Input PGA + * 0 = RINPUT3 not connected to PGA + * 1 = RINPUT3 connected to PGA (Constant input impedance) + */ +#define WM8960_RINPATH_RMP3_MASK (0x80U) +#define WM8960_RINPATH_RMP3_SHIFT (7U) +#define WM8960_RINPATH_RMP3_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP3_SHIFT) & WM8960_RINPATH_RMP3_MASK) +#define WM8960_RINPATH_RMP3_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP3_MASK) >> WM8960_RINPATH_RMP3_SHIFT) + +/* + * RMP2 (RW) + * + * Connect RINPUT2 to non-inverting input of Right + * Input PGA + * 0 = RINPUT2 not connected to PGA + * 1 = RINPUT2 connected to PGA (Constant input + * impedance) + */ +#define WM8960_RINPATH_RMP2_MASK (0x40U) +#define WM8960_RINPATH_RMP2_SHIFT (6U) +#define WM8960_RINPATH_RMP2_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP2_SHIFT) & WM8960_RINPATH_RMP2_MASK) +#define WM8960_RINPATH_RMP2_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP2_MASK) >> WM8960_RINPATH_RMP2_SHIFT) + +/* + * RMICBOOST (RW) + * + * Right Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_RINPATH_RMICBOOST_MASK (0x30U) +#define WM8960_RINPATH_RMICBOOST_SHIFT (4U) +#define WM8960_RINPATH_RMICBOOST_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMICBOOST_SHIFT) & WM8960_RINPATH_RMICBOOST_MASK) +#define WM8960_RINPATH_RMICBOOST_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMICBOOST_MASK) >> WM8960_RINPATH_RMICBOOST_SHIFT) + +/* + * RMIC2B (RW) + * + * Connect Right Input PGA to Right Input Boost + * Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_RINPATH_RMIC2B_MASK (0x8U) +#define WM8960_RINPATH_RMIC2B_SHIFT (3U) +#define WM8960_RINPATH_RMIC2B_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMIC2B_SHIFT) & WM8960_RINPATH_RMIC2B_MASK) +#define WM8960_RINPATH_RMIC2B_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMIC2B_MASK) >> WM8960_RINPATH_RMIC2B_SHIFT) + +/* Bitfield definition for register: LOUTMIX */ +/* + * LD2LO (RW) + * + * Left DAC to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LD2LO_MASK (0x100U) +#define WM8960_LOUTMIX_LD2LO_SHIFT (8U) +#define WM8960_LOUTMIX_LD2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LD2LO_SHIFT) & WM8960_LOUTMIX_LD2LO_MASK) +#define WM8960_LOUTMIX_LD2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LD2LO_MASK) >> WM8960_LOUTMIX_LD2LO_SHIFT) + +/* + * LI2LO (RW) + * + * LINPUT3 to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LI2LO_MASK (0x80U) +#define WM8960_LOUTMIX_LI2LO_SHIFT (7U) +#define WM8960_LOUTMIX_LI2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LO_SHIFT) & WM8960_LOUTMIX_LI2LO_MASK) +#define WM8960_LOUTMIX_LI2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LO_MASK) >> WM8960_LOUTMIX_LI2LO_SHIFT) + +/* + * LI2LOVOL (RW) + * + * LINPUT3 to Left Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_LOUTMIX_LI2LOVOL_MASK (0x70U) +#define WM8960_LOUTMIX_LI2LOVOL_SHIFT (4U) +#define WM8960_LOUTMIX_LI2LOVOL_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LOVOL_SHIFT) & WM8960_LOUTMIX_LI2LOVOL_MASK) +#define WM8960_LOUTMIX_LI2LOVOL_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LOVOL_MASK) >> WM8960_LOUTMIX_LI2LOVOL_SHIFT) + +/* Bitfield definition for register: ROUTMIX */ +/* + * RD2RO (RW) + * + * Right DAC to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RD2RO_MASK (0x100U) +#define WM8960_ROUTMIX_RD2RO_SHIFT (8U) +#define WM8960_ROUTMIX_RD2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RD2RO_SHIFT) & WM8960_ROUTMIX_RD2RO_MASK) +#define WM8960_ROUTMIX_RD2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RD2RO_MASK) >> WM8960_ROUTMIX_RD2RO_SHIFT) + +/* + * RI2RO (RW) + * + * RINPUT3 to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RI2RO_MASK (0x80U) +#define WM8960_ROUTMIX_RI2RO_SHIFT (7U) +#define WM8960_ROUTMIX_RI2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2RO_SHIFT) & WM8960_ROUTMIX_RI2RO_MASK) +#define WM8960_ROUTMIX_RI2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2RO_MASK) >> WM8960_ROUTMIX_RI2RO_SHIFT) + +/* + * RI2ROVOL (RW) + * + * RINPUT3 to Right Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_ROUTMIX_RI2ROVOL_MASK (0x70U) +#define WM8960_ROUTMIX_RI2ROVOL_SHIFT (4U) +#define WM8960_ROUTMIX_RI2ROVOL_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2ROVOL_SHIFT) & WM8960_ROUTMIX_RI2ROVOL_MASK) +#define WM8960_ROUTMIX_RI2ROVOL_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2ROVOL_MASK) >> WM8960_ROUTMIX_RI2ROVOL_SHIFT) + +/* Bitfield definition for register: MONOMIX1 */ +/* + * L2MO (RW) + * + * Left Output Mixer to Mono Output Mixer Control + * 0 = Left channel mix disabled + * 1 = Left channel mix enabled + */ +#define WM8960_MONOMIX1_L2MO_MASK (0x80U) +#define WM8960_MONOMIX1_L2MO_SHIFT (7U) +#define WM8960_MONOMIX1_L2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX1_L2MO_SHIFT) & WM8960_MONOMIX1_L2MO_MASK) +#define WM8960_MONOMIX1_L2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX1_L2MO_MASK) >> WM8960_MONOMIX1_L2MO_SHIFT) + +/* Bitfield definition for register: MONOMIX2 */ +/* + * R2MO (RW) + * + * Right Output Mixer to Mono Output Mixer Control + * 0 = Right channel mix disabled + * 1 = Right channel mix enabled + */ +#define WM8960_MONOMIX2_R2MO_MASK (0x80U) +#define WM8960_MONOMIX2_R2MO_SHIFT (7U) +#define WM8960_MONOMIX2_R2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX2_R2MO_SHIFT) & WM8960_MONOMIX2_R2MO_MASK) +#define WM8960_MONOMIX2_R2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX2_R2MO_MASK) >> WM8960_MONOMIX2_R2MO_SHIFT) + +/* Bitfield definition for register: LOUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_LOUT2_SPKVU_MASK (0x100U) +#define WM8960_LOUT2_SPKVU_SHIFT (8U) +#define WM8960_LOUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKVU_SHIFT) & WM8960_LOUT2_SPKVU_MASK) +#define WM8960_LOUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKVU_MASK) >> WM8960_LOUT2_SPKVU_SHIFT) + +/* + * SPKLZC (RW) + * + * Left Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_LOUT2_SPKLZC_MASK (0x80U) +#define WM8960_LOUT2_SPKLZC_SHIFT (7U) +#define WM8960_LOUT2_SPKLZC_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLZC_SHIFT) & WM8960_LOUT2_SPKLZC_MASK) +#define WM8960_LOUT2_SPKLZC_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLZC_MASK) >> WM8960_LOUT2_SPKLZC_SHIFT) + +/* + * SPKLVOL (RW) + * + * SPK_LP/SPK_LN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT2_SPKLVOL_MASK (0x7FU) +#define WM8960_LOUT2_SPKLVOL_SHIFT (0U) +#define WM8960_LOUT2_SPKLVOL_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLVOL_SHIFT) & WM8960_LOUT2_SPKLVOL_MASK) +#define WM8960_LOUT2_SPKLVOL_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLVOL_MASK) >> WM8960_LOUT2_SPKLVOL_SHIFT) + +/* Bitfield definition for register: ROUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right + * speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_ROUT2_SPKVU_MASK (0x100U) +#define WM8960_ROUT2_SPKVU_SHIFT (8U) +#define WM8960_ROUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKVU_SHIFT) & WM8960_ROUT2_SPKVU_MASK) +#define WM8960_ROUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKVU_MASK) >> WM8960_ROUT2_SPKVU_SHIFT) + +/* + * SPKRZC (RW) + * + * Right Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_ROUT2_SPKRZC_MASK (0x80U) +#define WM8960_ROUT2_SPKRZC_SHIFT (7U) +#define WM8960_ROUT2_SPKRZC_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRZC_SHIFT) & WM8960_ROUT2_SPKRZC_MASK) +#define WM8960_ROUT2_SPKRZC_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRZC_MASK) >> WM8960_ROUT2_SPKRZC_SHIFT) + +/* + * SPKRVOL (RW) + * + * SPK_RP/SPK_RN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT2_SPKRVOL_MASK (0x7FU) +#define WM8960_ROUT2_SPKRVOL_SHIFT (0U) +#define WM8960_ROUT2_SPKRVOL_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRVOL_SHIFT) & WM8960_ROUT2_SPKRVOL_MASK) +#define WM8960_ROUT2_SPKRVOL_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRVOL_MASK) >> WM8960_ROUT2_SPKRVOL_SHIFT) + +/* Bitfield definition for register: MONO */ +/* + * MOUTVOL (RW) + * + * Mono Output Mixer Volume Control + * 0 = 0dB + * 1 = -6dB + */ +#define WM8960_MONO_MOUTVOL_MASK (0x40U) +#define WM8960_MONO_MOUTVOL_SHIFT (6U) +#define WM8960_MONO_MOUTVOL_SET(x) (((uint16_t)(x) << WM8960_MONO_MOUTVOL_SHIFT) & WM8960_MONO_MOUTVOL_MASK) +#define WM8960_MONO_MOUTVOL_GET(x) (((uint16_t)(x) & WM8960_MONO_MOUTVOL_MASK) >> WM8960_MONO_MOUTVOL_SHIFT) + +/* Bitfield definition for register: INBMIX1 */ +/* + * LIN3BOOST (RW) + * + * LINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX1_LIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX1_LIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN3BOOST_SHIFT) & WM8960_INBMIX1_LIN3BOOST_MASK) +#define WM8960_INBMIX1_LIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN3BOOST_MASK) >> WM8960_INBMIX1_LIN3BOOST_SHIFT) + +/* + * LIN2BOOST (RW) + * + * LINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX1_LIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX1_LIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN2BOOST_SHIFT) & WM8960_INBMIX1_LIN2BOOST_MASK) +#define WM8960_INBMIX1_LIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN2BOOST_MASK) >> WM8960_INBMIX1_LIN2BOOST_SHIFT) + +/* Bitfield definition for register: INBMIX2 */ +/* + * RIN3BOOST (RW) + * + * RINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX2_RIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX2_RIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN3BOOST_SHIFT) & WM8960_INBMIX2_RIN3BOOST_MASK) +#define WM8960_INBMIX2_RIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN3BOOST_MASK) >> WM8960_INBMIX2_RIN3BOOST_SHIFT) + +/* + * RIN2BOOST (RW) + * + * RINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX2_RIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX2_RIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN2BOOST_SHIFT) & WM8960_INBMIX2_RIN2BOOST_MASK) +#define WM8960_INBMIX2_RIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN2BOOST_MASK) >> WM8960_INBMIX2_RIN2BOOST_SHIFT) + +/* Bitfield definition for register: BYPASS1 */ +/* + * LB2LO (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS1_LB2LO_MASK (0x80U) +#define WM8960_BYPASS1_LB2LO_SHIFT (7U) +#define WM8960_BYPASS1_LB2LO_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LO_SHIFT) & WM8960_BYPASS1_LB2LO_MASK) +#define WM8960_BYPASS1_LB2LO_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LO_MASK) >> WM8960_BYPASS1_LB2LO_SHIFT) + +/* + * LB2LOVOL (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS1_LB2LOVOL_MASK (0x70U) +#define WM8960_BYPASS1_LB2LOVOL_SHIFT (4U) +#define WM8960_BYPASS1_LB2LOVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LOVOL_SHIFT) & WM8960_BYPASS1_LB2LOVOL_MASK) +#define WM8960_BYPASS1_LB2LOVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LOVOL_MASK) >> WM8960_BYPASS1_LB2LOVOL_SHIFT) + +/* Bitfield definition for register: BYPASS2 */ +/* + * RB2RO (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS2_RB2RO_MASK (0x80U) +#define WM8960_BYPASS2_RB2RO_SHIFT (7U) +#define WM8960_BYPASS2_RB2RO_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2RO_SHIFT) & WM8960_BYPASS2_RB2RO_MASK) +#define WM8960_BYPASS2_RB2RO_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2RO_MASK) >> WM8960_BYPASS2_RB2RO_SHIFT) + +/* + * RB2ROVOL (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS2_RB2ROVOL_MASK (0x70U) +#define WM8960_BYPASS2_RB2ROVOL_SHIFT (4U) +#define WM8960_BYPASS2_RB2ROVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2ROVOL_SHIFT) & WM8960_BYPASS2_RB2ROVOL_MASK) +#define WM8960_BYPASS2_RB2ROVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2ROVOL_MASK) >> WM8960_BYPASS2_RB2ROVOL_SHIFT) + +/* Bitfield definition for register: POWER3 */ +/* + * LMIC (RW) + * + * Left Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINL = 1) + */ +#define WM8960_POWER3_LMIC_MASK (0x20U) +#define WM8960_POWER3_LMIC_SHIFT (5U) +#define WM8960_POWER3_LMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_LMIC_SHIFT) & WM8960_POWER3_LMIC_MASK) +#define WM8960_POWER3_LMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_LMIC_MASK) >> WM8960_POWER3_LMIC_SHIFT) + +/* + * RMIC (RW) + * + * Right Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINR = 1) + */ +#define WM8960_POWER3_RMIC_MASK (0x10U) +#define WM8960_POWER3_RMIC_SHIFT (4U) +#define WM8960_POWER3_RMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_RMIC_SHIFT) & WM8960_POWER3_RMIC_MASK) +#define WM8960_POWER3_RMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_RMIC_MASK) >> WM8960_POWER3_RMIC_SHIFT) + +/* + * LOMIX (RW) + * + * Left Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_LOMIX_MASK (0x8U) +#define WM8960_POWER3_LOMIX_SHIFT (3U) +#define WM8960_POWER3_LOMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_LOMIX_SHIFT) & WM8960_POWER3_LOMIX_MASK) +#define WM8960_POWER3_LOMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_LOMIX_MASK) >> WM8960_POWER3_LOMIX_SHIFT) + +/* + * ROMIX (RW) + * + * Right Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_ROMIX_MASK (0x4U) +#define WM8960_POWER3_ROMIX_SHIFT (2U) +#define WM8960_POWER3_ROMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_ROMIX_SHIFT) & WM8960_POWER3_ROMIX_MASK) +#define WM8960_POWER3_ROMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_ROMIX_MASK) >> WM8960_POWER3_ROMIX_SHIFT) + +/* Bitfield definition for register: ADDCTL4 */ +/* + * GPIOPOL (RW) + * + * GPIO Polarity Invert + * 0 = Non inverted + * 1 = Inverted + */ +#define WM8960_ADDCTL4_GPIOPOL_MASK (0x80U) +#define WM8960_ADDCTL4_GPIOPOL_SHIFT (7U) +#define WM8960_ADDCTL4_GPIOPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOPOL_SHIFT) & WM8960_ADDCTL4_GPIOPOL_MASK) +#define WM8960_ADDCTL4_GPIOPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOPOL_MASK) >> WM8960_ADDCTL4_GPIOPOL_SHIFT) + +/* + * GPIOSEL (RW) + * + * ADCLRC/GPIO1 GPIO Function Select: + * 000 = Jack detect input + * 001 = Reserved + * 010 = Temperature ok + * 011 = Debounced jack detect output + * 100 = SYSCLK output + * 101 = PLL lock + * 110 = Logic 0 + * 111 = Logic 1 + */ +#define WM8960_ADDCTL4_GPIOSEL_MASK (0x70U) +#define WM8960_ADDCTL4_GPIOSEL_SHIFT (4U) +#define WM8960_ADDCTL4_GPIOSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOSEL_SHIFT) & WM8960_ADDCTL4_GPIOSEL_MASK) +#define WM8960_ADDCTL4_GPIOSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOSEL_MASK) >> WM8960_ADDCTL4_GPIOSEL_SHIFT) + +/* + * HPSEL (RW) + * + * Headphone Switch Input Select + * 0X = GPIO1 used for jack detect input (Requires + * ADCLRC pin to be configured as a GPIO) + * 10 = JD2 used for jack detect input + * 11 = JD3 used for jack detect input + */ +#define WM8960_ADDCTL4_HPSEL_MASK (0xCU) +#define WM8960_ADDCTL4_HPSEL_SHIFT (2U) +#define WM8960_ADDCTL4_HPSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_HPSEL_SHIFT) & WM8960_ADDCTL4_HPSEL_MASK) +#define WM8960_ADDCTL4_HPSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_HPSEL_MASK) >> WM8960_ADDCTL4_HPSEL_SHIFT) + +/* + * TSENSEN (RW) + * + * Temperature Sensor Enable + * 0 = Temperature sensor disabled + * 1 = Temperature sensor enabled + */ +#define WM8960_ADDCTL4_TSENSEN_MASK (0x2U) +#define WM8960_ADDCTL4_TSENSEN_SHIFT (1U) +#define WM8960_ADDCTL4_TSENSEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_TSENSEN_SHIFT) & WM8960_ADDCTL4_TSENSEN_MASK) +#define WM8960_ADDCTL4_TSENSEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_TSENSEN_MASK) >> WM8960_ADDCTL4_TSENSEN_SHIFT) + +/* + * MBSEL (RW) + * + * Microphone Bias Voltage Control + * 0 = 0.9 * AVDD + * 1 = 0.65 * AVDD + */ +#define WM8960_ADDCTL4_MBSEL_MASK (0x1U) +#define WM8960_ADDCTL4_MBSEL_SHIFT (0U) +#define WM8960_ADDCTL4_MBSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_MBSEL_SHIFT) & WM8960_ADDCTL4_MBSEL_MASK) +#define WM8960_ADDCTL4_MBSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_MBSEL_MASK) >> WM8960_ADDCTL4_MBSEL_SHIFT) + +/* Bitfield definition for register: CLASSD1 */ +/* + * SPK_OP_EN (RW) + * + * Enable Class D Speaker Outputs + * 00 = Off + * 01 = Left speaker only + * 10 = Right speaker only + * 11 = Left and right speakers enabled + */ +#define WM8960_CLASSD1_SPK_OP_EN_MASK (0xC0U) +#define WM8960_CLASSD1_SPK_OP_EN_SHIFT (6U) +#define WM8960_CLASSD1_SPK_OP_EN_SET(x) (((uint16_t)(x) << WM8960_CLASSD1_SPK_OP_EN_SHIFT) & WM8960_CLASSD1_SPK_OP_EN_MASK) +#define WM8960_CLASSD1_SPK_OP_EN_GET(x) (((uint16_t)(x) & WM8960_CLASSD1_SPK_OP_EN_MASK) >> WM8960_CLASSD1_SPK_OP_EN_SHIFT) + +/* Bitfield definition for register: CLASSD3 */ +/* + * DCGAIN (RW) + * + * DC Speaker Boost (Boosts speaker DC output + * level by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_DCGAIN_MASK (0x38U) +#define WM8960_CLASSD3_DCGAIN_SHIFT (3U) +#define WM8960_CLASSD3_DCGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_DCGAIN_SHIFT) & WM8960_CLASSD3_DCGAIN_MASK) +#define WM8960_CLASSD3_DCGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_DCGAIN_MASK) >> WM8960_CLASSD3_DCGAIN_SHIFT) + +/* + * ACGAIN (RW) + * + * AC Speaker Boost (Boosts speaker AC output + * signal by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_ACGAIN_MASK (0x7U) +#define WM8960_CLASSD3_ACGAIN_SHIFT (0U) +#define WM8960_CLASSD3_ACGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_ACGAIN_SHIFT) & WM8960_CLASSD3_ACGAIN_MASK) +#define WM8960_CLASSD3_ACGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_ACGAIN_MASK) >> WM8960_CLASSD3_ACGAIN_SHIFT) + +/* Bitfield definition for register: PLL1 */ +/* + * OPCLKDIV (RW) + * + * SYSCLK Output to GPIO Clock Division ratio + * 000 = SYSCLK + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 5.5 + * 101 = SYSCLK / 6 + */ +#define WM8960_PLL1_OPCLKDIV_MASK (0x1C0U) +#define WM8960_PLL1_OPCLKDIV_SHIFT (6U) +#define WM8960_PLL1_OPCLKDIV_SET(x) (((uint16_t)(x) << WM8960_PLL1_OPCLKDIV_SHIFT) & WM8960_PLL1_OPCLKDIV_MASK) +#define WM8960_PLL1_OPCLKDIV_GET(x) (((uint16_t)(x) & WM8960_PLL1_OPCLKDIV_MASK) >> WM8960_PLL1_OPCLKDIV_SHIFT) + +/* + * SDM (RW) + * + * Enable Integer Mode + * 0 = Integer mode + * 1 = Fractional mode + */ +#define WM8960_PLL1_SDM_MASK (0x20U) +#define WM8960_PLL1_SDM_SHIFT (5U) +#define WM8960_PLL1_SDM_SET(x) (((uint16_t)(x) << WM8960_PLL1_SDM_SHIFT) & WM8960_PLL1_SDM_MASK) +#define WM8960_PLL1_SDM_GET(x) (((uint16_t)(x) & WM8960_PLL1_SDM_MASK) >> WM8960_PLL1_SDM_SHIFT) + +/* + * PLLPRESCALE (RW) + * + * Divide MCLK by 2 before input to PLL + * 0 = Divide by 1 + * 1 = Divide by 2 + */ +#define WM8960_PLL1_PLLPRESCALE_MASK (0x10U) +#define WM8960_PLL1_PLLPRESCALE_SHIFT (4U) +#define WM8960_PLL1_PLLPRESCALE_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLPRESCALE_SHIFT) & WM8960_PLL1_PLLPRESCALE_MASK) +#define WM8960_PLL1_PLLPRESCALE_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLPRESCALE_MASK) >> WM8960_PLL1_PLLPRESCALE_SHIFT) + +/* + * PLLN (RW) + * + * Integer (N) part of PLL input/output frequency + * ratio. Use values greater than 5 and less than 13 + */ +#define WM8960_PLL1_PLLN_MASK (0xFU) +#define WM8960_PLL1_PLLN_SHIFT (0U) +#define WM8960_PLL1_PLLN_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLN_SHIFT) & WM8960_PLL1_PLLN_MASK) +#define WM8960_PLL1_PLLN_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLN_MASK) >> WM8960_PLL1_PLLN_SHIFT) + +/* Bitfield definition for register: PLL2 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL2_PLLK_MASK (0xFFU) +#define WM8960_PLL2_PLLK_SHIFT (0U) +#define WM8960_PLL2_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL2_PLLK_SHIFT) & WM8960_PLL2_PLLK_MASK) +#define WM8960_PLL2_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL2_PLLK_MASK) >> WM8960_PLL2_PLLK_SHIFT) + +/* Bitfield definition for register: PLL3 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL3_PLLK_MASK (0xFFU) +#define WM8960_PLL3_PLLK_SHIFT (0U) +#define WM8960_PLL3_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL3_PLLK_SHIFT) & WM8960_PLL3_PLLK_MASK) +#define WM8960_PLL3_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL3_PLLK_MASK) >> WM8960_PLL3_PLLK_SHIFT) + +/* Bitfield definition for register: PLL4 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL4_PLLK_MASK (0xFFU) +#define WM8960_PLL4_PLLK_SHIFT (0U) +#define WM8960_PLL4_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL4_PLLK_SHIFT) & WM8960_PLL4_PLLK_MASK) +#define WM8960_PLL4_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL4_PLLK_MASK) >> WM8960_PLL4_PLLK_SHIFT) + + +#endif /* _HPM_WM8960_REG_H_ */ diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld new file mode 100644 index 0000000000..0d29b2257e --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,304 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld new file mode 100644 index 0000000000..e98a75c121 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld @@ -0,0 +1,322 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*ip*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld new file mode 100644 index 0000000000..ed0fce209d --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld @@ -0,0 +1,297 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld new file mode 100644 index 0000000000..c3c0f2cf4e --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,259 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld new file mode 100644 index 0000000000..dedb377ad3 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld @@ -0,0 +1,252 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c b/bsp/hpmicro/hpm6750evk2/board/pinmux.c similarity index 95% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c rename to bsp/hpmicro/hpm6750evk2/board/pinmux.c index 44fdc7cce8..c008f1dcd0 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -21,8 +21,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; @@ -98,7 +98,8 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; } else { - while(1); + while (1) { + } } } @@ -115,7 +116,8 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - while(1); + while (1) { + } } } @@ -192,7 +194,6 @@ void init_gpio_pins(void) #ifdef USING_GPIO0_FOR_GPIOZ HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; - /* PZ port IO needs to configure BIOC as well */ HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; #endif } @@ -207,16 +208,6 @@ void init_spi_pins(SPI_Type *ptr) } } -void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) -{ - if (ptr == HPM_SPI2) { - HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_GPIO_E_31; - HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; - HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; - HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } -} - void init_pins(void) { init_uart_pins(BOARD_CONSOLE_BASE); @@ -426,9 +417,9 @@ void init_can_pins(CAN_Type *ptr) } } -void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8) +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) { - uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);; + uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); @@ -455,15 +446,30 @@ void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8) /* DATA3 */ HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; - - /* CDN */ - HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; - HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl; - HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX; - } } +void init_sdxc_power_pin(SDXC_Type *ptr) +{ + /* Power */ + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_GPIO_C_20; + HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_sdxc_vsel_pin(SDXC_Type *ptr) +{ + +} + +void init_sdxc_card_detection_pin(SDXC_Type *ptr) +{ + /* CDN */ + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; + HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX; +} + void init_clk_obs_pins(void) { HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h b/bsp/hpmicro/hpm6750evk2/board/pinmux.h similarity index 87% rename from bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h rename to bsp/hpmicro/hpm6750evk2/board/pinmux.h index 11d6a0df91..52c97a9b9a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,7 +18,6 @@ void init_cap_pins(void); void init_sdram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); -void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); void init_gptmr_pins(GPTMR_Type *ptr); void init_hall_trgm_pins(void); @@ -36,6 +35,9 @@ void init_adc12_pins(void); void init_adc16_pins(void); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); +void init_sdxc_power_pin(SDXC_Type *ptr); +void init_sdxc_vsel_pin(SDXC_Type *ptr); +void init_sdxc_card_detection_pin(SDXC_Type *ptr); void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); diff --git a/bsp/hpmicro/hpm6750evk2/board/rtt_board.c b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c new file mode 100644 index 0000000000..0fef780fd3 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_mchtmr_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_manager.h" + +void os_tick_config(void); + +extern int rt_hw_uart_init(void); + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_manager_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); + gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); + + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + case 1: + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state); + break; + case 2: + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + + enable_mchtmr_irq(); +} + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_HOT &= ~(1UL << 31); + HPM_PPOR->RESET_COLD |= (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm6750evk2/board/rtt_board.h b/bsp/hpmicro/hpm6750evk2/board/rtt_board.h new file mode 100644 index 0000000000..8a05e027d0 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/rtt_board.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" + +/* gpio section */ +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED0_GPIO_PIN 11 +#define APP_LED1_GPIO_CTRL HPM_GPIO0 +#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED1_GPIO_PIN 12 +#define APP_LED2_GPIO_CTRL HPM_GPIO0 +#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED2_GPIO_PIN 13 +#define APP_LED_ON (1) +#define APP_LED_OFF (0) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* SPI WIFI section */ +#define RW007_RST_PIN (IOC_PAD_PE02) +#define RW007_INT_BUSY_PIN (IOC_PAD_PE01) +#define RW007_CS_PIN (IOC_PAD_PE03) +#define RW007_CS_GPIO (HPM_GPIO0) +#define RW007_SPI_BUS_NAME "spi1" + + +/* CAN section */ +#define BOARD_CAN_NAME "can0" + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6750evk2/figures/board.png b/bsp/hpmicro/hpm6750evk2/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..4c149804b04621d75de620f5823e0eb3d672afeb GIT binary patch literal 654298 zcmd?R^-~;C*DXA_WN??@9!PL^cb&mqgOlLy4#C|W26uN2?yd>$?sD_I?{ll}_cwf1 z-PKk7Q}5nuueHzFt4_GGq7(`;Au<2}K#`FaR|NoI$N&InZbbNhZ{h=@8U8(x9Hg}z z0f0|f|GA+6>6!Qd02x3=TmF3Ec2# z+_fvy*;rV(>vFyjI5_QGe65|TOs=fLgyMRRT`};jIIrS$K3>0B_N;7t;6Vt>r;GUi z`*mm!-MLJJE}?R3KnX5#ef=ZE2TI$qk)!RtoD+Js9rI-J{Xh`n{&jZdHT%*?`Zhz# zq;I(KnsD*llRxWX{eJmpPUzisi*wo0;0zwkgWBDXYXyD6XxgU_JRws0C za$(6>IAMRGD8F@gyZ40@_Avnw`fdHYR@O^VxPNFP|mn?gIl3)R>p0 zK=&WcccT|j-1Td9C5lPOPaivY zzE?1S#p>2vhRze1Zl9@#?spyi_NLaS71H+|(s$p@m(7RsG}F!ljgO}+OE&Mj|{ z?}MF-pZ`Vg{WJ(m6_J0)E3KkvN>zPG^BlqdS1$n#@L0c4QlGNRway{5`LsW=c{$hf zmILcjz1v*e{(?5?vPlLI_|e;ZukE^Km)&wSoku!3YjaiqXVNeRcDMG9@ngR=O^wZD zgDbPO=JqQf#waE(Hr(!Ew|6C+RCi_h{n5ewg{wvm`nu8njdtR9La4s0snNcacJyt( zujrW)wC1X9=hlmw5TE1j^lgkw#*?*>=l-jb;RS3E-Y{P^f0yr7=){{&~RDKGr59IFC-wx(yFhUb`c?!HysBz2~c zkP;pl1ZdzGH27_?0bCS>Q7>|=x!m}4Ru6@q4}se$K(d_)i|xj9bJ}}%hW4yzNZX{1JkzxTn)X5W;fO5;^?_r^ z-R^v3qWR2v3vv6D123}`=Pg=DcIj*V##gF1inW(s%01u0F}XL>AM$bX6Y8nnq0sHL zWO7s4zpI@VS?x$hRud*ntHDBd1C;y9tFlAIXqFMd0$e6Xf9k!;cx>bw8831KlFu7$ zxa6)IBbC@sHAAk#B@pPK+Sh@;TW|a0Y2Am4%RC^kRhycLr=8>f8w0vM;%4AHk9z$9 z;>gn*f`i)%Qi4@^9A5+4Sz3)#eS`fxT6Aq>g%hR22dUmkb{qi!xq32b)P`l#>MYAI z%Db1!yerNWm#mz-_93Ar0wRx-ZHOq7e%4xHV$$J;Yf$#kFVI{dQ?+4v%^f$Jduv{8 z_S@3{SK!Aa*_cjHXZE)9eU0<^j-`fO&va%3Ay&syTfsl^IiaK>`wwo!pmM>8D*F!} z{7itTHA{a)U}Ac!d++c_6xz`$q`wkdcv6E;sl2CnAhG^5nC_<;_?ZG+Z64Y1`> z`5i&Wk+0I_yR}eT%4{ME0lHsOBTir^38~k41)vJspf{Y-V(yXd`QJz4iToGUj4(Zg zGVz6Hg-I8kw=C!cIP}XnYq-@Ol$X=zavEX{;5Z#?-Si(&{7z@Np76QxVX27n96O#JmUAz^Wb7imfY@;1P+cR1D7 z1=h0a`tFf8(cR=Vu(hf)YX$VcN>Z>G)v1rh^gC|C?xh_5NSw z4Ysz%gqE}GC!0Y>*He|EKUMPb9-<=AF0|4#%rV0}z-wEK={+*=Bwdos0)gYEig0AJ zvouEz)pzGPf`{Rx1PriR#<*XwLu;gE;FbZDm^i zH6E7)l6YcSwIIebaWh1n2wgw#9pT&n0Q5*wVO)r@jJ(e`%gcG5Fs< ziI7vcm|F2Oi70u{uzK`W{bKHSK%$-ruXOy-C-prXMe#fe>Tv(w@PeSZDPOBaH^;zu z{WK~Wyv^Ns!g>q8E?!e32TSiZ`oF1J%2Yri4dKU!%zx&w)4Oz@L+M}6< zqyr=dyO;yZF5l|AY@rX@+=R$=8|OTmaJ5x76|%Z=3RU*&p<4c{Z~utwgNMXpJN+S` zhOP|YPFZG7IOkc#wIhgCyYCJoIEHtyx_qbA|FAwguB|W`)ws&Ol1)j7_d$VkqgtSk z{Rc_|_lhL;|3#;jbu1{HO=eYmRr(<_JF&41BBQFlnQ?aag`Om1jSWe~oFaf>q-B&g z)l%Q_t&3O{4AuoxuO_UFgBH97iF_X|gr0RS-j1xdl>9Yv>2l^FjQ*LueV*`#nNA_5 z)An2$8)-;_KW#p&Zh$rJm1dtV20m$QLIoO6|LZ9e-7kALwpQ}UIEM1$%(W=xTt0`d zG^Z-Y+9^aRNvrH}7r~>=ax8hi*rpI3m&=U#VG=BD3y@wB{S$XRQWmK2e7ZJNzQgk~ zL=cFFm$jx_*6;elBwDVzJ&DtwVh^8(%~Kr+8E`80Gd!84_#|^TsG}DIL+hs z=bngeHqC=&*k-cxnhsohL!z#nPp2Hoo=u&H_MLw^F)_*vnGemfA$n3K$x8^xtPluu z#or0W4A}Dn>rN9`fOs%=vP2jNEbsf^>R%YnnIN9fcNeKYb%YX`PzFH_&lb{-yW{-b z$5l7p7xzo+ankNYpqpnMU$I@`O1QfFjMQTr+v}~+%0&PD;ivOp@P2~1FvCkvc@NkV_<{QK=Wl02SzFlnTbo8`Rp?< zPP3Lp?pD~7JYk#>J1(s!-k5mRw++~=L&e|s&8+m_wmtQFfWg}b-N<{9Ho&IVtq0DDc6_vJ{t0==f)~zh) z4h}Px9w6seDy$V-?78JhK2G%~js}U<+Prt1i9AA{Hb3FiK4BUxzvWv&}!lG-cQ zaxaI$RmF{lK?`m0beeqi)z_^V=YOb2;lFW=qWr{>fl?)3;e*nG0w5_J<5++C(JttM z3jnhDYt}PLQ5FTa*4CakCf~41dx0D0p~4lIXD01=n(U8Z{XTAs#~z*JU8ViWx-9dnz4)Mtcy|$fvSNs=cfP z1Gi$w-QI^z`=ukpK?h;5mT0uxvhmW}k13Q6?oGQ1TFzcsUujx%BDCVcK*v@l7z?KXWWLNgH?t)a!H0+S(Gc)fIvI5&OhLKbYp;oN8UfJ1 zjbP1X6IyS0Kg40xm-ycpw4GY{`b|VrgZ6+eS)BC_fB9jia!dw`yM<)x>4S|e_v+l; z&bF&=Y6y{P`|4CtJ1*sR{-b zF&9dhG%YQyw<=@&*1%&mrBWuM+o#haG{Q9^O=x%%eJv{jy z8q@KiM^rGVt)`Yvr6WrPAPB>2AY6HU6+h5<-#kHmTM_cc|M<~hGb0yH%Ory0j>e6~ ze&e)t^;ZA!_VM%hgm%$$O@}CjE5-LPtNYa+s=^d^Q$0Ms7X61b7N6@bJChzr4*?6)ARMjes9c1-2aQSb_z z21$&!;XkI0B;)Lw+0ye1BGca-Z#Hoe$Ahg zb=q*w&Hv)qeW&ERe^vtZoqA0@QxgN4PGZl$4%6xSwJL>#?^X=!;&t%JLVZc_J>$Y> zd&Pp2t$KRCoC6sK1KR(4N7k12!xfBF9$kw1qR_*?e7wQ=B`qXHt7lt5ME#%_DY8iH zw=#?G_iJ7LmVY`(-@3YYeIK=dU014v^840YB0fYU3r|5ZG0(W}{P(?i-NA6byR)U^ z{j%WVvDFuKyG-rDx76G9;A)9c{vH+6kFnO=yy7XI4~=Q_iL@%tFDjZNvsYMsiEA-O z%hJGoqr9XZLFnE+_?WYc3aM5<7zz1veno^+<@leB>3_wj5BrZ|-WUJVgm@i_k$NPj zhbEhwXMbQe(Rr{WZ5F6j@tP#O;MRw?|M>In8#9NddsACIW+5avHh7QGpWWdq4V?I_ zm-%}B(tQ#w)iJ$4y1y^w|KJPj2fd?kILQ`{9#Z6&cy{V`@XI{;vwSr1NAJtWlIzNiek@BIAgIrV{KLAQ}R&z`xjal)@{1&nPOoi-CUR z2DmlB-seLuDVXJ>|FN?i-UKYKmd8sjF+b9FS>?}i76FzYHE|kRdknjf)N>a*ULU~L z$FvYYD{86!_9A@r_;W;l}YNs$~A*@J@$1ffB4J38XB#P zjPrrv%YUrhiD(Rs`Bn*5s%;s1LCQZIw5azQk!j;#;q+NvUOcPz)U&?c${s4RX7Z#v zA)Tzul&&Zmbw~Gat9-o=zq--^53E_-g>ZG8k!HW0xqgge0eUiH@hDW#F0eq8P~wM8 zM1Mo^%nb}c*SpIa-otF#>XBMje4BX6^m*t2WD3#rlIT{+zi!6ku0C5_A6YK-3+dW6 z8V0q3WSBU2n{jx;U}k*W($rqlV)LQZ>b58A&FkOhp7NN-T1~K5&=>vQH2wJjjqoOw z`{6{WlfE4H-LF#)?^rObmZXWiCRmU0Dj;YA+?ul71$nf|n3x>cOJ5ZA%s=qE`Y81> zxqwtUozzpGej)>BuI@ig2JfzNMEx<{AO6kyP=1M+{S~~MS#lO;r@N#=uftDiX{|Bd zAI+WT?)IJs=9U9r0#!kxgTs^hE%$#t{zobp{&$HhlFf+>NXic&KVp>UboEZ#>}?&2 zD%yutLB7Dz$CiifA23CkifT4^X>8uQ9%uU4P4TsuE3!zL%xWr>pzng6_cPqd8g^h7 zrfkgWzfr6HIJ)q#6`Zjm8O2;Nz{Tm%kQPu;5m&xNAfsp?JVI$E7P!O}o7CQ_7cfUd zjI?s&qrg^m2VF{6Se|BNx&7UGSxhOr+H;!CZL-3*P{t7^P<7{4F%AE`B{cVTpY!(n zVuio+mWlL8&kLfLSQLs3f}@ClI5}+g*W_K<-ISky1V8v%7-MD=kJ(SUWq_a#V2f@J z*>w=s&b;l@v+-Y^X>(dH1-A#jL6wX#{zhAIvRPMaYHVsfL!D6E^t`=XXWzVTvhcmp z=yGciZyZ_4%_@pWzK*8ldx}Pb%IWg45cyAU&Gg^)A(^WwenmYAy@Xk2laVt57eL&0 z(e?T(rOU+puo+O$-Mdp8686$iGqan6h{2}?$K`C;1d^!tK8Vf z`xTp;6Em?*BpM~*&Ijxr33Be5&AQLY3=9_+W7&1`?20O5 zZfRcUsoC+ene$Xcs?)wsl+DL4^q!uKI+UXRwUViNXI;*|z0&!nH`qSSrui{B!}ktt zX^}JgZSdo0O8}mKcU4_`!=)erKXk?Az>I5xYZH-}4<(cSon|VUF5+Ii=PgLB1W8F? z5TBTuo#u8=O8soU)}*!dbR$&gM^lT5LGo@rmif`ExqDU0lUOs(zNTlMSx7LhR`Y2~ zZoR+z;r%`G&Hv+r?tifEE8+XlenGnA z(%s6k(eXMBgVxgAeRB{)Q|Xn%!PMn+Uc1!tNogFd=~I*fHG;hm`yGnVW6UO77x!AL ziBG;`br`nm`|FEf+nHsJZ`I4fSh?kXXOOTyM!<~+Hng~OeZ$=N4XW706}=-Uve#4# z2mLpC`t{7)A~HoPKMPGgGD}c|%%BDpNR*>2A($8G2WsG%Z5YR;MEJX5t{R~1aDmFG z!5l-{?OMG&jhgOLPdNZN%q_@5bzuw=5MH_<{XnXd>a!;oGa;1p=cwsR$gzTq+vM90 z1X*37?aYfs4)~fID%uHvC$Cm1MT8gwXhciWK6n2u4*W<3A(*TY4L@wn zj>k*%d+koYuIu2Mn|IrmH@`i8yk?&xkhb5ph1&Bo`&>9#+YY%0)~e46GADFBlfJ#` ze9Yl}HSn_WY^n8*`~LPT!`>xE;H6?RTd)#sF$S~iV#3~zYh3d$+Ga)-0PXZSJMM#3 zw&mlqhU*24Mz`bfyrqYgalpULX-&;bH2wq67E*5K=iA9C0S=a4DLmY+N0*ejotVle zaGiuv(V@xIkQ^RF1C9(?$w2dKhMX0 zBeE3B@!9+YvPmxg5&{dj(W**K9}2qHaZgXZvF_|@PLrx0XK1DmcW6x8Tdhp_nC)&J z*8N$tW*c9h)~Igjx$OJ8?vPt=YEPJBg$7koRefu^J=SGr#}NV>W#aAq88B_fNw)!s zKO^|D469v{ri3Ni-b7f1oz8v(3%K@CMT!5SZAA&?$Ee_XZ=?=}1xUnyuU`>wU)i>r zZYJK8zyd=3Cg0SOt$6t&FiuvR9O0AXb+ojiiR0^>6&X3_*U~Zf9ko-T;n21z&YV?< zQ(eEMBb`w`CWS_#3}z?k-Nm|7$c7p~n07{*mUFyTSV@iiZ)PG}?*Q)GOjvu;%g!Xs zpwmpP_CZB(8ctvRt@B%QCgpv!`3cj|Y~*%l7&F1vlaj$SW2v>&Il2SZG7$T2BQfMJHIXgUtLiVHOJmK+&#RgjSC z)`uoA=eq11I{~iUTKPp0r!D8KDHJ;Q!6JjJ+Fhdo0m<(yLQO;hS`wM~1oEbVbiQwc zWlP?B{l4$FlsT`_IWMi&UE&;Vf`71t^AA_?HRQ&o-c}oujSj_QZI;%Lx#>Vy}!DA&u{Uma+k(ozkZcXob{J1!M z@p$qfzKB`?W_xpRZBAxwJOryB(&kilSZV6@`Y7ty!M3R27(XVqrK2ODVT|*AN^v!) z&!^e4cx(-?e9w6H%yBAJ@dWVWiyWqXU4hiW;rb|qf32NAv*_37i~XAkMuU+GTioES zj+U;s-O;BTA_TN?QXaSOSJ4}iK8Hs|W8Lj-di>5?dd(f~F2;ZKGm75-sO4llP5C~a zs8#z+csp$ml;6psr8I@^h42d5rWJ>4bsSR{Xmhf1`95QHXKgw3lQR-~!+op915hi2 z-AE;|qF4YJnAYn@O5Oup2yTQk&rrJabHU!Qw%;0mK|W5j z0!i;4M`*-PW&$@PnQ#^$1$-W)>8lV6UGpTTUB{hSQ!Hxb1I~~sI+9vl7`_d@dv@<= zvYo+Ghq-&?^|^@l8I(;Qr{_23q1+iON+qUJ?ZM|FsfM4MT(mI{oX_cn?)6E<^r?)` z5_!SH1i|`N(}p6RN}n4*g=~?-EQz&e6SLW$u?MeL)h|wq#>#W(3v~l&>C0tDA>F#T z>s!st&i0fFXu8^KkIRO12Nidpxy>~F!hdV`Q(R|SPmwiBX9f%w7^*jpbJj`&av_>o z>Xy(6Jwa}pWokc<75Wyb79n+TfJ%s{xLiJZ2K6Goxj7h2w_L87&y4n!C5oNp@FDc~ zkh##<9B6oGwJfZmBgHukb+HLS;YX1zhxXpG<{VNi`tp3gUXq5z9Mzbk8Xg^iA0h)n z^?(gZMXk$$HVEU`_8zN=@yz@@QZ`ZK_c+M4o1@s-%=^SrMaX9NsfGJMq6ier3_w%8 zkWd?w#M#C9THD04X?fN>r05>@Ep#w=;_NJPXn9|}#2LnL`s5*p7!_VXF@8Wh77`x@ zK{O0YldfPH0_)S)Hd!;#GWgU(GMhP%n6biLGlH==LfHCk$ZZmW`o~!FOofl3@Hy94 zN5%gc1pe0xAU%g2D-ZQWJQ)@#T;0kP@lRrJnIkeq8BpyFm5_o~I;}^%ped*ClOPfR zOF9W;2)49vVqIS=^$Rf-&P_ky0a^zdz9k3}3kRJM96` zbs+XRo5(N;u#<9IRkfELx9LYdKuiQU+r~%^5hp9EiH5C(r^-K;0R2WUqm#}Z5FbUa zL@+!_kob)y9h|4gGlex(K|sVHQ+B<15H6CY`88CL@J}OBfXYHvU)V2XQdxN;c6Fq} zNsTlX8UzBgD=|(Rncp5))F1{{Q>GsYsSBP4bf8oy6?icuLtH4WF?nV9xGSrgS|0w7 z)6v{}~M#z*h_0C73*{JJwk1*nG|GzV7fQv}0`K zWt*9(I1Fm0D~!Dx>%LS)Fmdu$bXclGE>c@ z^4eh}squMTkxb=hK$n|UA<$tb6EBz@GlObV)u_UL&#Io$HYq~H-m%qm*ML|V4Qkh* z?rQ0I)j&fqWWZK!FOyyecD>VU?Px+$AN$l{F^EvJio1d`4N<86%VTy!hoNK>g|K z_+L_%mgFfFX6(46J8~-+Wafy)ArN9-;sBOQWt87=^^JwIs;Zyz{3Af}ivbG|y>W8XQlxSS+I0?1p25AGb~DVsCn*X=SbL0Vs?`d3KtbArUk} zXf75KvRO`!0VM`P((ee9F3Fl`sJl0|XV&~T^T7nw*Q$HAt&F0Ta5hTt=&lmmd;=%B zX7Ojp&e=o>gLt@3Q9|SbcN`MZZq(VVcP%;N2Zb$DTPJ4_dnZ0eq`O-DwTvwkiv z9BJiqhN-eiG|Zq-V8c)7(}YoE#m97L{dFf-vg1|e_+n2ZWs+Nn(uBl7Yo_%?{S6FN zqprXGWl6(X!uYh8YK$+bd=kScTH2A05mB71-xNt+83WS*gQ#Et2u+s1(}5RYgaV^0 zK1yaR#%LwlE(sySbh8gyMh{BN-39j)tE#dhs|S!n(@T?!%ES7{YXp-+W0iYMiEhs` z0~E1M^H^^;J!#`h=`1Y&2$KQe3xWRVaW~5F^6|`H;zZeXlZ2%OCE)yGS;7Ibe}X$6 z#9_@$0AMg!Y?{S5!R>%ce1X9FCmpsj0=h7OE%-qn8ibH7E8I8KU>h%*qzo>?GO#U= zSD0-u3sVL!G{q(>*NuZ>FhgvCyUq)i))n}IYp`JDdanh2_w21>AO;AJs**OB9;Hz^Y-x0%J6;MklPKH!#UZm)4$@~f zWY(CpkL2C5V)s%}*HxcH{}iT`O}f1R#v=bl1{Y5Lr>zE>W49kItdCGkd>ws3Rs0L} zJUFH8%CQd_rk`SGDfN;^Q*>cJQV|cHY^OXRYr@0si5FX$TYjpvSxqXV0-4oWtyokR zJDn3HrpXv=%l>mqzH*HOH6v+G9$-#kOc89=B9)RRGF}LQr8bFz63M#RjO@dAFlG`L zrqCD9Q#Ruqkgr(lHyRyJ*Zd1mh3Brd0kFbe6KabQJ;NG5%Cd_kU&igwW-Km@$WSd)(ny` z_{sKp&9zfbLOp99oM7GydL!uiMn4Sz$$^R2Bk3@{c3tf<+1V7bw~^KkxT>kQ94`@m-v;NXkTXPVui)M5opkXat`8U42OjJXLG zI@x3yK;Xj5GK!qS6qy}Uj6eO3iXkbihGQs-hK9~>6p7&=F$|Hgm}-Tp_j(jw@V43q z>tIU2e*hmS8xwuUkws{qxAOh423!5EJuXq~&saPI?vyFfuXG8|I@= zpP*^-5Mz*yxe7<}TKLjUsG+WYc@!!H7eY3caftTJuzpD5VR=(Kkfq{HLECeO3NFbJ43#2r$Ci&!XPYx_iI&Xnp+UKQrVdN}rxVLi%f z@h4OX;3D+B=zc8q{-u*{CzQtw>ci@j_WsNWm4uLqsae>CSAzPhBNP%vGvY5oh77f( zNCZK~KqE~j0wCiNHY@Y{Dhi(uQc|ITwiv|8P?&y(A(&aT<$T}xMGiZM?s~_zpazrm z0KkY+5XNl6K^&XEG2hmMyI`ncF-*vP4N1%s)JkVRg@ft~EU=|9p_E;<-!2^yy@1r#~P zw)uQj%>5&V+=uvJwJ;p;JBU*iCm-58VCleX@p+jSLpqDjUFGo^pV{*8TYsKk3a?Co z$FYg`SCNyy63BPZ6U z{>m4h*_xP>o6u}5n3fstE@W|fP_vVh4J^dSx2(FvnK0yL$29^o6H(aNxWrGCtjotd zXYoZBW2i_nM-N-IM1*%$5S=VQ<$5YN7G34h!~3>B%-S1g+=b2SOzzk0XQ}-fdmrct z{^956p`^WqBq5L6Pg7pov>)#eKG?o*X~;7i1F*Z*+oZ3jA1*gnVxOv4x!9a9G@HHc z+v7f)na4lFE0cjbz4SKx7(j4Qu`!18Y4b^N7hmu>^CDOwztF|NCn4c|gE|KMrF;P% za0M?)V#9&c1k;NB#DssRYo_rOS`iJZziqc28*;N7=fQjeConhjfzU*2Wn2XhN>`ok zybXeQWf4HV#1O2>7{b^#3PcHMpy*$L)p+Hd9pw!bD4DR8lNI>8XKcl)><(30b{oH$ z1W)GU#}i^^*lFal2YSiR9CV=MTdRk23G&Hca1Bxt?hig8tb5PzUMd>!uAIg18wC>p z46oEJR8AmNXvxRp^p2CN+Fo>s4CYwD-%>&bnF0gKyKWSf$3`;lgBc=V?abOx4I&?< z+?+BCyFK=1EV;$Ab$aljPXuq zb-8(7d=aE((JyT$6HNr%DJ3dOSOuUEV+a@p8&-9fscQ5#WLFvHnVvW@XNu<|8^hp8 zfKiN6MMJ+pgV7AOmd9=S8iSrm;81e-Kzs_`1sv$SGEfT(Li0F62e4r987zl5$Te)I zRs zj#XYx1Yk>#PG-;6uV<;5VY!HT!oGa5*3|C` zIM>88F-dT4P0Mrk>#ptkW#s!QGV+GZTvxjd=nxQo^+PiwAWaGm1{i^9#?s?oz-4lL zd3Gr+%!!2L&jKJQ4Y@I5m&Z^f{|tAGZAA;DAfiZ`b~ALU|4;-Vtdvcwe}%0{CKd<7 z6;Dp%Fz8Dp0g0Gd61f{}oxe~YC+SM~tsu?zIV+-ze*ccc;2cjJ;JR8Sjs=iXmXkjg z0C}a(NWe1#zvagEBZ4|r^)UYJRN9F4d?g7&XMf=h|D!_mCkcdPdi+IOm^}7w)Tq#3 zvbOPEn@&>(OQ+%?pJnLJzXp>x&I$*q#p+OeKJYkF&zB zo6Y(fgruwr+B}*!O-ThVsxOIUAci2HMVUUfRhK-og*1lLqL;l;ul)XIS+YSAjL43B zdIA))yp2(&BEG9F7_g>ooZ~eNo#)x6dq;QJII?`}j#XBbhKL)5pHPbDs_?5d=cyW? z<&9~Cq5Vc6>S~MTLmNl5Wp`Yjj4fPPlk2G08_-y@pb06vAjLvPI{3ad^L;E$cu^P} zTennZE-Ph0^cZ1M@Ai}>HS=3dx5Mp8tt5x%;oRUo+V^UQ&G!=FN(9HioCWIXo5NNa zSM%0oTlIUp)Wd}D%dPmq-cYgHRF&OMoK#L98{RjQwP=WXX~M4=X6w(Iwp=O+W!q1Oe2Xn>ZgLh2Vo8l5k0XYQj;#mZc{T`Ed$Kb<)ZrHRT4e%E+_G}A}(MF zqlYLh#MA-HzW5-@AoBCee=hY1L*tvr4B@k=!6#3a|~duO)q z@kySODu4zG5#1mpq*9T)&`vpzFr*FK|D%i#X=Xa`6QbzdGac-Ch(Bd0F3YC;B}el` ze-_tg5f$}2muTM6w*E4{;qq|(EOmyOm2VEurxN_n<2bFeL{?g1KQJNQ?&%aVm>|I@ z{WzmkUS-7SCjB!f30FvgDyiIjx2se2^>@B7cUpfZeKKgxF=q!f(58u}azI`U4Q%lw z_)@VGy(9jbP7EuyjwR8YiPA7rz?UHDMz+GR66=RZRxDB9Bs-Kp9sL5%UuG0&Kp$&< zegoT%zx1&zaTy)EI5)*k=AYQ4MJ#Q}gJU`*$dvu;!G1b}9par?m~2Pj7kF;B??TUC zluY)nlzOd#CF}jEWL*9znFr4DRa93NFv@Ws2qV`trV?IID9l~5cJo5XMhzaXGK2&Q zMm3^e2-{2_HO$y>=0T%J7uzw145DXrGJzzJ%mW&c%gL30QEQ}$VdOD%y zvQ)`CCjo=Ex9qcp+4uH+3TK-<6;)OFj2n~AjGK9LN4YaLqM$fUtYSIg+RlyPp&@u6 zjE!i($dIv>6|_up@L5&D`;J4{UXcYkgq#J!Unlu1JY1&GGGH{=kiQlQ1oyAEGg;n} zjMqfO-{gyO9%dF?Y$ddTA~UIJ>iRV?F~J*wy70_6#UdyO)vr-9C```Bu3 z%FJN8%?@SrxfDHcC4deJxMa(mJH8WNn!(9ILp64HC#swBEaQsIo_CvPSSPG!i*{xu zpsI_fD}7=ZDK)1hs>6{^sRWsBYZ1<411zY;HGJ)wF7>26#ZK)DYY?T^HQ3pz!#WKX z{xMJEz#XE0;+TIvCEk}vP!>3Spsz$6fm}DI6wUi}-nKw=e#sVi5rrE}G5!6v6qQQq z%>gR=kjznft;kzH|kaqN$wvF~x&d|&{RFH(&b(7ln(wC#Q z51K!19eDRu4&QuDa9mBSL<&TIG42{~4Sg@@O`O8lT?;iw> zO0Rhm6eM;~#rH#2j}9``5~~`LLy7VOhy?@Mnlg7QnZ}v?XtT$F!ZJk3`}xnSV#@vp zi*WYYtN6Ly8C6Wfgo-elYUX>;{xQ!e2#+Q0*p19dD(QiaU&K4u?)b+;9+KBfx!oXB z=z)WgsxQ(c5o@3Y)za);QWo#ae$JaRC-taD@J zNydP9o@^m@z<8EA{?3$xBkckup>vPCd5K5v-J$#;F(O&n0b{6aa)id6(I)GHqf~!7 z!DwDH7RqOeh3L1^ykWXUstv7=QuCjUVuO>1@X>7t&lXb6(HK|*OHgilodjT37sxGk z*S9;184oRpl&7-BS=z}FoHDv70)!!tLK4K4de=n(Bdv8102^Fc?q$Rkxs>(Gcb*uM zuc+$gl-ajL4g2tic!)5lfQ$3T4>Od0S#}x5==~iE;`1yMnmP?&+oeonv9(f&r3w%WTXk;AQ(-+KT&>=F>9PIe0Ge=Q7Lw~vc%+yg8{)KzN~%yyp~4z%g#hrJai++F5j> zl9a+zS(KH2L1`L*eouei9&prAnq@_@bqk|#ABeWQM^UL7sHSlMWE;`uKFGz4NBstU zAl4I`$~^nMB6#8_J|u^Iu)uwNhxfDIL4%_JI;M5cVh@jh8QSJ|rvTuRj9d$k?!rH_ ze(9y`+lrA(1OMM#Q#bO`s4(I2!{kE2 zgrmLcw!`AAbLy#>54@2c38sn^Q%RJbn4ixdYBJLiXiwlq`L}>0dN-qldfj4AbVAI^r)Ht7BQoO7X!4}C_H$rH?@VR>j=s6P8IQ8^(Azr)oEdc@D z`DD|c`|qlC=SBPG-fbF-p{{>;Ts|H7!l=CIeYqSg&Va_gYLsE6n!0KmysK6Ks-9?w zeqbL`82K%a_Gv;bY8(f (|R{Bp-Q@|BxqtRpto$C*pB*DFd$s)*R;`8gR0`q9@ka<`*7q)-l|Z<-1?PcSW}4|<6VcyyzT3Fk z{>^*g+u|F-45%tv{GN#>OS(5Jx3rwvK>K_2xQcR{oE+0Z@UJtkBW5%_y`t-H?K22)3AZGLC*J88pjs3@>P}j5TduaDN z%I4;Kxvf1Onb3y0;LW9{&-s8&nhmbtM|RU~GIGiHtM>9RKa+e9@lyZ(ORVuTHZv z2E4oC*z{BsEM`t9H4&zbkhq5ocwT{2wt9^|ZE&r5OTbP*}8~J;ik~~O|SuVM&5dHcN5r|O3XT7|& znkROb@;j)b2px$9FJlaHJ)P_j;$&sQSP~QU)DvjYQZICHdRkufWJ;!495~VS1~j?CU`)!U~~b zrK{wg!@;5G@2hQZPw9H!y&3nS-g6sA*Bc4Y9KAxXtx}p-1qP{S0QK@-@`vX)bfy=X z${;`bluBI4n11O9S&Zd6({E zwKe?Ov~bz73AjSR0s+4`i*P5*sB`zTWti#R!NM?(Y2;RS{SRW$Zq<@O5WcoCDhquB zqJ*Mi`@sTbu`)Ye!o_fE0`8HC#FAsKv+iMnE#+!xEUR+95!Eg$yFojCSQm8~H2KaN zu08O#Cmq`jJ;CD$3wTuJ=U*_rsWAI$JDKqvfeUppj(Dj;GCcRdh=6R)H7YSbmf)ze{5TZyQvr zRKCe`G|O_;S4y)9-{GPC8^(afRVEUz5&H$tZqIk;uc%|o8Bo2{SZNvYVk5xzq3%*V zc?9PO!-9K4X<6x|mgL(s+=Af9MqF!P*WIeCNV9B!coJV*AB8?t$T@x;3WAox+J(+& zZJG6g%KfJSgsAxTryGz6PAyjBcn5a9P}mE?^9X)@0A7EEl5@ zLxAqOlEF?FSvX@a{953v$LqS}gH2xhG-`|N6U@&gW|9s7za>B=D`PcC2!- z*25`l;dgA?)q0mn+F7J-Tjw_E$NdAA$(Oy+J7D*b$= znEA8B*ZtzY`8)+V+wVEAk=yd;m@{|z^)55Jm7hq`5h$yA9{p@72XvPQ{4fH!=jsLQ z6(HZa`$J$dR(@v^dW4q5u*xN>sv1ob&)>*MtB~R} zFmPDx)U-4rE3+ni2@V@0>g3rV2pjsQlU_lOjUWnNameXsNup9I{sK_$Yn3XZy!{4E zaF3f~w6Ug@Dj`^V9}ng355StS;0{SulS-1xO*$JJ)A{>y4g#*Nyz|`d0OkEsvyiV} zy`7d@*lqR6SM{YE0JB5i)8F!S$Dg06DD_#muJ?A8Mpz-4X>wI|?S+kE#Qu9$t9aqx zP0T|T5A?G#EvCh~HrCYSX*4$U1Xpb7Lv}M2UJy)fZg0HGBl-WY7vS4Z+XKJF=10I; zK20mRxtRpsWoF@kp(U>4D#VDHfCWE!l{9HeAq>f&5fq6_kB}&lR>Tl)s%ju#G%o+$ zQ(Efd-%H;<$u`yNWAe z%l2aFSeqR*?_u_tSE_`x&Ay=ozHMkekzFQv_h+5?i{l)Jf$LV1F{tEgN`iYER;;(& zjUxmeH94Qru^ZoTK9p{-O1bdcPwXPJe+Ls__-})0=sXk}0Z>#sVq^^-6JE0+tBDkX z^Y}nJ=6U0ab~{9R+I#f4LIH}(hXGFI#B{ggf@5+^|JA!Kf{dc7tTn6Ik}swp!6*2D zVeZf`iDmLCkpYbhd}A#qkw}ApJ@K^~Dw+>1`p0GWh9>5AkVL^jRd^*Lt~!{fSQh2ctk-zu?WG{<;(u zfa$|aW=d1m{)@VZ5psVVk{OOpPLmS8t7Q5>lKPO7QdfW|%ZPN~5X&`Bx;{sZxkB!t zFp97Tl7bcawOWK{79EwnMX#{{R}gbCt^kwvY8tD(588;obj8A`{6~n{ttl64W?3+j z^!{)~ffJa|=G=91gOexLc=pm3i`wHH42-UMg|YaMNR1~sgUJ%k5Y*+#M3uJHJ`e!! zJKh>3X(PT55mzRCMv{<~`8lr}k7vMW^DO(70*6Ti9}+eO3TyLP8<{U^+PcZii?YMM zX;^GsGz)E@kh_e-Di$)^2ABTqj3gSgb?)k+1{J-;;UEr`qP*B!`H8}wZB3r zCk)GixH2Y*;f?(R`Db7HK{|0{)tx(a;*$^G_pVRziBJ41zWUW}jLO^Ff5G;40rDqo zfAfF-t&{J0=)T|Fuj5Dm*_WQ?JD2WYY>BajB4VyUtf6TdnC-I4g8SEmd+(lb;>ZT4 zk8dz63*NkWi(6aU+`PTRYjX5jYk0AFx)KyJ8uT=AFb0HA3la`30m?=Rtv`G;c<&i7eD;aYohpwqN^d&EE;@W6Jm)BM~E9}(Hc4jHgdA2$$~x;`FZK~mxL`G<=O;O zx*nzP5>!YKa&g_sVUqNp8`?m9FvH@pW=$KBlgY2~nIVY8RGnULrc>zI_m&>jN)4$~p=Hao$H z%H<*&@Vnwc=YSYG!vTOcL~KeFrOk;~C-I4dn9oIq)RQQR8sj1SJ9TJxSMVQVKk|P= zOc--WHkXTsRuw4@5j)Byl^$E`Tk3g* zH3fso0BbcC=e(BC9dFQk%U5%X$%+C*$z&$ZGZ{L3Y?#icn9y?H*$r;q*x}aB44WCg z=!42tTA$^2s=Wu%$rch-<{M)MF#;(hhQks-QS5xb`Zg@xoHDvyl%<}pT&Sd!bZtT? z21UL%Lk6ufO(!`X`j#+1z!U{CoG8m`AZ8g&Y?YBNih^V`*|Z#Dx1@U(5}|Hr<_m`F zYZ#jiT!Po6)aL%M1g?~WYGtv?LKO!gGhHDB_NO%=MA{J4a3ljV^EOfKH@!(n-XT)XCt{4u z>p(zVy}GzRnOMfdg586f)(3ps;$#WF#Ae25c9TE%=yCr0&wYq@UN|9>A^2uWw1Kvr zk#JxJhzO(6kn<~J&Yd~V2OqhQKX~c|{_QuO;fZSpOwAgD$(Z%BAOSDln#sTZ=F9xX zXCFTQ(1p7`|2IDQXTJWwfAy~?u$Hh&oPdzkFd_*vK+&Q;{+d=FKS-9dYkV& z^(x)lAGUD)LankM zi?I&Pg%aKN1qdKeSJ>uyDxpq&KOLmRUymjV!~OA8LkjBQhfM$jlj{(6=n8ulD?AaT2_Ve2F(aGBmU4O|JGXY{8F-4lTMs@4jj}RaiXIc;lhNf-wd>X+S zi(j;a*7xj3$VH`bdMsTMonq4cwysB8=@>n_m>^J$N!BVT5ffr9rpS`E)PW3oF6ge4 z0K|-b8?{t6uD|!XJ}V)h9n_f=BN3?g}mBz@8+A{eJGaKX2T7<{XYyGmWPzbB-G&p=G_ zExvBBCKvFD3?L=^q9%Edku{8!ybc((0M396DH44{y>%T^4jG+3uTnyUs#5t+sB0}c zR#!=0k2CZSgk2UOaao*(uuPH_`H%VadXBws=^iSHrgxO0W6)zFSgTx!5Bhz^WRM`? zy)p%aKxmqLzX`bsE;okLIey`s)j~3}spRLh4Ju_alGOk{sBsKIC!?6$H<+|{N=ogO z+Sxte%&83=0fMJ(4YP$>f48mgV-o#(7*!gaR6g4F4N%fEQ=PJ*YCL_EHK~_s3#ddf zGmaw4cy~$(XBD6zgMe-58tnBv*KMQED>*=56d*_m-{xzPpR;bwjgia}%b|Fo&uQK0 zI;)I{?NuOFBF$pX+U!k!^H05#U;o8Va`fmr&0?Rb-dDEM?`hn_;>uOTO^C6j^&nzd zTU+C^k3YtJ=TGp@f9Ko$_A}co8i#R~;b=frw|xBvSNYgG&zX0eT>rq?&Et;%Zx z)=~^deG{9vF4uFjjS_ z9HQ{Mn4~O8x27nHs2$GwU7GYS*^jQ+5?R^}=UwXG*JJkYy*`?^DFsuAw+< zxpQ#uw9e(Qpev}kRg7^gvz^o{ z5Du3j{XYEIf?;`VKk79Sp=sHP}_krY=i(vQh%f&S} z78h2%^|MYsK`)i)jQ%Jd=KHYgJ?fpcqI&greHeLoTz;%1YrwNde(RDb*Souk zS|7Ku^UF^?JCX~%T+%K_GIv(VDZ8eLb$vnKOJ#C{cL;$tbj)bh&d0&B!0M$|`W(5U zB=}loDOURF>@i;_5fsSiVpd97>f=bR)9UHHu8qXxLSJVa)YZIi2=5rD*fm$D?s>K9 zrq?$5dpF4OA(3+N--Rmg8%8S|Y@WH7-93Yef;dfZ)IluA2%}7g-d9F#)047vF2T9j^GSLpYJ{MDJ==Bv6DdyM3q8XQOS17eJqghK?@dxlzdfQ_0{WOh?J3A9QW7j>PP%-pGJ4b5V~ zWdC*k#?L>>um94gD9eJyY)T@46krP^)({$HpXz`mBI3X*pZ=Zdk1c9%Z~woxw+oP; zu-$v=)O~w3AN$N zv-uFRzB-T1krpwA3-_Mnubufc7w>+WfASxm;nG%xJ$6sF2h{M;#d)zpIT|bzs;KfI z&5^RqCDD6=cdMHzY(GOp&=;xtK!ZfPeS`GI_c_tL%9@=MY4P5t!XmC15dG`yzHyzZ zKA^nkBQ$PEmf7~mv+eGpu4?Lw3h0Hyd526cD2N=gc0tcnwkYgfv$Ed0voGW@!rmdX z%Xcr4seDd48$!uQU00xl7_tstGMa4OvdbNc)VX*e+GmiYJBQ?;FMX1lGCFQdhal%< z6S8b98xd%>OlTX*qU6~ZFY(ILU*q`ZCZGFrzsUN=Ce~S=f9_fS$v^o&`T3v!1s;F= z6V!FnA8D89rEcMnv}_LTPfj20^SN0zJO8L+;HTQ&^4>$=@h24@hhL96dx?moWKv8? zoO85IMcXu)J?LCq^gW$VeN2&Q)%LvvS~x5vHr*Zw^uz8PyVvUZFrpq>Dsiqj2$sV5`oU)PVzKM% zo$C8!K*HnnR3C=QGmIbz+;4`9foi7)`jW z#iT$|&v&tgWRjKO1(%H^)JZGr=c5N=AEUY=7zAreqV1%snbk^~#93ptUnZm8Wiim_ zPBIMCR)n_F7~8FeMw_t3I*gRKL7@&q=2vIG_!f` zKkOICe8U@tlND?^P+8VuK{eggUN8;DI@?9Pkr|Ix#TH|13MAh!KiDSWA!>4zlHLn3 zl59DYm6Z*QwRrET_O~F^Dsk;tmux~K#<8(>99#jhrQYAhFBbYtB<=ZB8M7gZ;9%z#2ix12)M8@bUj-JJgR`JR9E}t<5 z42Bp|HgC|MJCh3$L9Du5s)>oldC06Wxp)FhGCgP`qQ$h`xx#OJ_9B1r7e9fdifXX{ zDKNzt#6fHTk1#-NRC5(tk{#2{KSMMI$LKkEVw1o4bC0t({T;sg+HKm&DWq^L=2M=3 z{We>>XUD6f(fN0*HLI_~+Xcvf;r4a`@?*AN{g?mJ2FwF5zp-=t^6eQ>48>r86a$*J z#ooEhuRc29um86nXFPW7A8hx@fi~!Qv^lsN{NR9L~dH8Cm=MZKGX>;27j$ua8&<5?rShfdrEeu`Oledml$gD(< zW_Jl;-p`yF<#W{GGSaOlnt;Y`m^XQWlYDwoUks=zjp-?P4O}@Crmn#-2h!Ae?C1T@ z?1;!xm;V+wA<6%dE|sG%l2UfC>Jr&L7thD0av_y8XrGAE@MljQp(v;Pi+}M&&YV2T z`ycxmHjkaaSj(O59lrjp@A8g!KEmUVf8tO{*L(R9a`^wH^*&i^)kUo+iFweWqGBC7$6Jm`=%jRM$x@LQ(tg&AzNZ^7 z*d_D2Z%b-F9r^-^^ykTRG+VyT@4D|8k6buL)3m(v-c2sOvBT-3L)MDG6W{$qcDJt+ z+ZGda_DSnKomXR+029>5GvR zJ(h%Tvb-@fCDvMEav8a_Sfl8E46$culC}M3OO}~fSEy_xC87_sZHpB!6xvf^EUs|G zw$2Uu1O4o_!3S;l)gg6V49L%q(fJw17?lyGrS996X88 z*RNh-Hmflbb7HRShni?9vJ;w`l~KvZ9($0LQOVAYH+lI7FEZQT)iX$qomO~E_trM{0z6Qy@tW( zXC)U9#$byf=O1{O(dKC+MYdjlnX8vy(jFWU@48R>Mdo|#yzv?b zJ6puiVocG;dmjR;o2NN{|9e`phh21-svCidtNFVwbq688fr|;#+ z@p~~urgv_!y?+T}%VcE@=PZlG0$M}eG-AgaoIdpq>|nsb&KFJ^pUW)g$=n9=r8rd^?8}u*NYQO!Pd3KDJP`Y+D1R)4{ZZ z9Q)M%SHLJ>XMtg1u+CC7oo+w@j$xs%M^u7Y-MPxoKCr@H`IVn#G+tp*RXU0QEl{u{ zBt)8O%4~m!s-CAoSyGOV%6NSR>&ip!dYVhr^@1~Zo#VgzQy<{g|MMkY3>B$Zp>&R& zgE^OP>=o}iGg#TQ@^tG~zMD5UW-CW7zI^4*xNce!7OcvLZU<|&Pfqw=^jFU?OTxQ zKB-@3gG>2EW))(#J=81!Jw$WpTy*l4lx+;V-v#H#M`^^1wZ(()#L(jK-sM58BFoPb7$5dZb989PHwK_(>`rTOzW1x>MCJSv9(uo=HyY1o;iV; z)>%!zj5#TIIuna(HfQt5kd-oV`KfO)zx67zx5c2Y5rMW<_n;6H)>sy9!R5tmDi3k7 zjoI5}(AHQYg>yRh0l~&dTsYpC-=sDx*iaE?TNKqS%a3d}RVkFE@{Zdt?$Vl}vNhEn zlV+i8O*SI1Nu`ldgz0N@_OHH7>jT3y!^VcPX-OnTqY23h0ZXzD_OI~9A6%nuqp~U0 zKBLfJV}WxHTMS61AQAA38CRbC0*wcYr-&6Rp~AH)v9i_?#o!T4FzjCXF4vzE+O}ol z8cGS6;Ifp?Q4GeIVL?;Zv^QSh(&Zn}w4U{mVdONV4kDD46h%Z#LF)=;^V_`k{Vy`F z8YV+aNlWw%&N{|pwS+a+60p=w!>t#;!@+dUz!_GC1r{ZU26n*2l~^~x=bopXYcI(4 z=f8`Io--#;us#|yZyQ?U84O2^MkDGPnu%j}<1*FBGmK=Dd5X$tk??KI4qVz`UJeRY zCM9hfs3qb<_xP%@$7JX@x;CI{BGgvl3u78))TxHGGq@WhN z))|bgIH>lx@yabi`#9$8!+B_@O4CRxaZ54bL^ytAL}7*PgNEH{CrgWr3&Y)K)))>f z*KW<(-mf7goFfmmg(yN>%{e98{KhZ*IgTGY!lJ4$rZ}|x7@EZ{cW%7I&Fil-+ux5> zJx^`j5MwJRPMqZ42i_-}XCD%z$V`YKQP76O!|!~APrc_7uYCD++TmT4g$_!+wO z$jNob14zWz3#R+GldosdSi^99#7tI?igktB=A|wv%af%AKK#K)xPI#n|JRpaU~jNO zaznc2x=vQ12>Vj|oS>&JJ9^bf*RKHG;I&SnlTa#?wjv!|XLAzSJhCdsPoLwnfBN(3 zp^NX78+W!z#`3Gb@(bK`?mWNyZ~r-qbR=^4001BWNkld_jJdqM!MK{8WWU_xasthY+F|Bj)gT9V#qRe|>-C2Oavy4;4RYSu|>KmmBR( z!Us=0m|=%wOj*(|iMcRnD^I(q8LkYGQW5$@=Li*Pn-;&Q7!Fp*6Z|ssN6(aXy+)}U zpq8X(u{vo|0!n8ojBsnOVtbx=sjo0f?GX7X`z`O(D=yN^XG`w$I{M? zH)SF-KK9sqxcQos_rCYtjGuayD>rr-Pu6JKmZq)|lgDp1Gah~TK8B{2kALLRbnC$I zjqg5<6k|jTi}`FRA(WbPcb(?KT}L^0YK?ci>)pKc@@uJOBE!*$wy9}-LyCc>t~s*4 z#=9T6$nLGz`NhwFoPYJ(-{$hwJFKj&Ly9bBGn%Ht`#|Z0M<2eQix*C&PkriVfo>uKu1eHYI2SAXr#usU&a{pN1^?jOE@4-1Bq0g?tR<_lWy zX_}fN>k~fxGw)B2z3+a;t0%a6^`<=Y>`Sa}Y~qHFs#?%CHQv{ZhnA0j^aJvd54@AL zwW0jKzx_3yca%TtmzG_gv)9e)faB>yd}$+2^nD)U(eMqGd1~ zE2EUln z?9XwT9qVkHB?eOR1mDoirqnX#@(Vk>{@fD`sWQves>_*mTzKF?){h)vez4Ep?lyPc zc#+-RJ;tLEgTYW^YnH#BKXaD#&EwQf!}V)#a(nAdW(QM-!;cRierpS+73Tes!XOE2)|mFEe*<;anB zoGa-1p4z73gO7cHcYol+Os5OJ^5rk`!gJ4ZFr9Mr$Pq@PA(%YqF$B(@-bg?5@yBK3 z$RVk6Mc<-Z+@Zf_N+1=aY3t#w8Y~6fa0g59> zh++voU}Iu1usnF*c|QE%57E{OzViFO&-cFnbauEpL81gnEao%j(J9loHeF0oEA)^k+ZCd*A;7p8TVy_?_SWZDzNxlExEC zIYL4~6Kfr_=^hV1^bjBX&_@9H(ieY+Z@u=C7BHJf^m*`&S}Lc=s5E^3bD!bjgAee; zlYhi(+n&XA#=H^M)*Pd;!ELM%BV5~>a`)+Vf*2k27bDInJJW5(C=0*4J7X{&V$E`J zAep&nGgE4fq1n1hdGn7rCvP&51!4^6@4b)Hr;erF-CbUP?G16Z#a7q3dgbfLWSz8m zj&3-ks@{aEQPoFbg~Gz1w4~JJ`#Un26s%1K7)h*;9XtCKAtvf35Nragb9?;W4LU57+`P3-n?^);R-~}Tj#~U|mzQ3?6kmJw#qj=*e8%2$ z@o^DbE&;|YiGA$R2l(2PFQzAF3vq)XbyHEdULx^m-PWU@YC(N_`-$7z1;|g>p1*R# z9aODEGr*Q5AlQRzeD0%1dHBI|%&R#ay4zWF246GX+e&Y~ewmv$_hS;5%E2Iw#@lSH z-;m?SPsq{ZrzMHWjt(j*3BJXZB|rP|_wxLuYkcYY8<^u4X=Cae3S;aV$`sMk;$kWJ zIRy41Bx0)`|HfGzoYfCe5`5cWntjGYZ8W?0zWX_S>P()UrURDNCnG-mfp_!uuY3U? z5(5*d+Zj$0F*jv;pJ=NFW7OqJo5*rcN|v>B$ah<{gb*o*C3avA<*13yougZT>RE*` z!f<7*Qm^ddVyr#HOe{72zOJdawunbJaYdoU(V^axK7&3~yd+XCTpDc~_!YXCsBS*>1yP(&Nn$A1*0Re9y&WbPeA80TYvv0$n9T_>V6D@c7P%pQ zcXyAfX%R6grF6)Rs!RSmd)q%QgObbv=|8(;T^@V)^PjkNuCHAI^TQIWuK4^>1&%0_ zBDx(aq%%XNMQXAp3*Mp!YjMSp)zwuzmfl}17b^OU!EjJ892R+kcSO`|JjT zamkyvX1#Q$D=t(*+xQ;tV8ZD3d!KKcH;xpsTTnPX#C?U>K} zsgGiZBcA!eC9Yn6jnvM0=82oEj}yd(c~dCT>Vyjy&ZWspK}tc|G++^QaGCc$UvHfu zky4_xk_sDBVU46DG_6A<=pf1Hu@r;^u5gTpWhyPC7}TdfS!k2G>x2doLr6MYb2uni zTN$x3nNSoZNlKbvROaLZ2}d%PqBI;ow#n*bNa^%^SnG&pNE0HlX|%E1l!!~5I=RV_ zHJgTI#95NF4k^YGqR}CMqOS$d@y&HkZmu#eLmCuGSv@x-no_NaqktI@fz_1>cbz@W z+S-WKiAlp@fpr6kc8$7iNo@pMl0;q8P8>VJ+RA{{$snz)t%)thASHD~=OdVcghede zci}t_K6no+D>j8#igBgXcE}UY-=GdRbbnog*gAt1`pmSbbDc{2LKd7x+NR=_=PRy{ zhP18cnddHX_3BL~;|Z_6_%i!@2OLaiOouJ6-Pvd7$`+miPnMOkw6ZmLQoEo%*kR6) znG6{f35%tvvaM;;G8_n>`@{$NrC-OOP^nW=04Mr}V@KBb&0qUv%5uQp|E+(>o3Fi!C188| zVx5~3gC{gI9=`u>e&aX(DzCos3jfpp^1pJWnd5TLNbp|G1yW>xZ<~`xCj6B@|2f`x z;|;#|wf{u$4Wm*WquN$q=bM_QZCM*xKJ>18_~_3(&c8@|eC7APK%{SlR```Q$SB;@?-2hHCZ}7nMV3+M%tNhIS|1u{|9OH$jzJs#~ zE0(s&W)Hq4v<+2N;i!1`#WQ^J6Q5$Xb(wE`*)u2#g7*YhkU~(|Wz*0$3yvR|@GF1z zaVBQQ7yf-kQK*D3MC}9BUbl+r!9M3stn&F!eUQ;;$g@v;1(TcY_jb1#3p1-m~ zSvq`^RT;S_B&Nio35*9iOfY7}LKoLVh*%3^4Y6*BTd%Pht}`@qiqRx}{+E7EKK5WoDpUzU^_**Lhy&h=-o8>cZ+^gW!7S0joxL=LLJXkgi&wf*{G zj2dlh@6L%av9n+4RP`(;Yoiw5$+xVt&!<257~}Dns;-yIjxqRZpEq88k~eSerQ}Xz z(5XlXldK)FGFX*z^_1DV@<%-J%`b$(XvLnn_c2i|fk15W^@6i^o#O)+&&bP9PN~W@ zLP+@5Gc1bo!MjiWM0LR1+fTQ>U4ZDMtf! zXGvL-loD1Fp_;K+SO#T@E3)P_1_q_m2FMuL-QFg~fGav#k|CLtcHh>J12`- z?nR8t08+JtsDrw?qAI7b%LGoO=Q656&e}n|+ zFoGYGHbEL4ZrJUMTJp*v3ER?s(^^9@9Au`+&`Hadg(wu8C$vz^)u0cGriP#s(Zv}| zsZ?)gLFlw=Srf;Y*xlP>zNmZQok(X(pxk&*N_0iVk6;}1&$&c7^!Fb}TIhYeWIL?d z#T;TT-YVt#Nv>Mm`R@zM{LT8>m?Sr2mt{e04PN=XfiIG}1uOxu7*`zo*`F^ondtTocHMy?z(wX4uJ z5Nb_W?Eoo+m2p9eH9i;+E2bDo7_L$qNX-tCd=C_CtWDBrSWs17WZ;##auXW60dXHm zO@CufCM&G1uHk)4(^$Rx2NTk0owlBn;zE-O>lirU*ycJ$3{BJOjFHhgF^maqi*QHp zTQtErvU!xjV2H1G!4<5GC%A!ul_Ly`0YM591;&+FSLS$z0tB|38KQ^P?B3*v@vPf9 zp_)@57$11_!ZFs?R@k|E8Q(Uz7`gKN9zGfh9OdR|f-Th6H3n_C&+~44J*V{nB;cHO z`K74LYunbeZOhO_)=ST+^#QL-z*iNx`tvOO0PBWABQR zm~_}+jA}CAThEm%uQT1b$3aYUViZfp8LTc^5(Vc+`e_Qj~m{%AkZ`oObY@ z`NbDyF`FT%y>ng7bw){3lVYN-D=xkCJWqcAyS#q+Rqouros1QUA<{H8pmQ=}@XQwr zu3x{wlTSX0lfb2yUrr<>#6VTe_4DhRx?T{x=lb=EZ++vNOooojmtIIQMnO=+3^Byu z`*SG37ryv=3{B1Juf3jTv$+^!@WIp66){HYs?u{=*Ia((6~6ep{|@gxPe1)k2C6)> z>6FD{!D2qw`C=p%i#gx=<~Nv>@Wl7NO;xR8%_`O;Cc_eEgxh!aDaRv1+p@hk!}~~E zw}b?VeD5A|FRN;=Jrzi{!Hv+(y-Gqt=fn8h@|%oG!TXw{ zM>k~SFZ=}-`@8A)zw%vKDI$COZ$Nc`SvjUoZqZ}2)prPyTibI)1ZM^31fsf*RgLGh zYdgd!V3(4rlotRILo+|%o}-S3?>k2)ch74VgqAxuFR^v!faH#oOhJfV;}#}`1U^bK z#ZXS)`#!nx${(0#pZr!ja_k-%ubm=zWjP~`;mQgZFWk+sA3VV>IxxCv1I`Z9gQxC( zs}0=S+ke*fb^-DeHsAP^M3Ms64m;iAgAYzPb83^iX^}&TUW|d=JGasc&pnqaIVDH# zx=&nDyj8AJj3tIOu5H~$?5o^${(@RLW-H8;6e)S=!E;6)XLQ;E$Ixfi2;@`z639gYyEj7Eo>TY+R9-j0~hA%>Xd2Yce18cLTRGD*WhDX(3= z%+=Q}F(@nx9F$|CG3u|Kz*=EA8EMZ$XRVhYS?L{0x@5H&l{mn-&anhQFm@?{5fsH3 zjE9F@Zk8-iO7zWg%YG4XWq~b=rF5zYO+?84x;u^Nxo<)=@8G( zR#$+c(0+@yY8Vd-Ha14=9<&+o>lhh5gkm&cxH8aYY#*3b!b9he;$q;%OVjY|F(qOwF{w?dbEPsyp+drf zSl75BP!^J6Qi*H~$}SBiD>zBa{R|r`hJ|4^3y@;+%_5bqkixn2vG<)zjP}eQ-k!qh zF+#FvOe)m|EG4yDwYI;#mAMc`1H&)B_g+5ojuT9)igL7pwFN7ytE{e!sj8Zg%T<2yi(gzW+fSBCR>`tlcDWp?B$Y*rGOa?HrbtjE5oQ1o zVSoW9-w8KO-_-e}9oJfZSo@sr5kNpR^*HNc=7zrK?6c3_dwt*cPk;M=BrkH_xwC_F zZWSo!U5RaKYU@aol>Ngg|HJ?Ezauzaf9n>~YIvNrR1|pUR}<$>*5UOx-{x=p&A-L& z!~6dJ-l1q6vT&NFLhuw-FjvSrU9R7}&wusb{2k_tg8Tc&0l97*o(5|zMOjhT4M`Fa zb$a~M-}wr^{l(|l-8;bR81I@;__zCH)dZ{S!EnUQyZijtf8*~`6eWlAN;r~UQ&ne1E!g;XN_3}6h>c*19Fq?{nksK7a3j`%R2CQaK&y*o_T=gw9b`A=9Tn7?8V|zwqy0ssMUJ8sOB)7Lu>g8Z?MIlx#9bAFYf_D<^hpUp98gCoM+napubDxte(G>X< zyrZdW);G50W1sqz|KmUYp3lohBD)BpdkF>=3LhNe77dMOl>yQ;OB0JWWkgyhWug6j zIN;#_682zU0+d+hD)Q87Tr8P<945FFxFyOBD)x7K-4M%Kt*9-y zyraj2r!JiZwY0E2p}ACL>EFHijw}5@*3Lg3ibiKq0+A6K7m~!4PH^cq_xAS5I(w{d zZmk*+2pJ-ywJ}dz9QhaakL1{$!?hmnX}`C!%T(f9kMrepIvhvn^xNZ)BD4-Z-m=QN zXyN`i!}rco6z`DdxqSOuU!y-7^4ZV*0&x`6)HUD#-go$|fBX-8e!R;d)l#Y z;j^EV!yzJK>7cP}I9lxq%jRu$(%MiXR<^0(_*#TVPI;9t3x83;dU1&cEYTHCoV7e* zvbU}a{@p+K2p_uC!}*4)YItzm_-S5qW|(mM#tmt#qpBL}y73|+RaH@xHN){bAS?3# zP94J%PNzj?R=Ju{l?^J8X=) z9LRdOdO|-HY+ay;7!FcC`oW9rzHmU{J<7xo z8C=tFW}vvZkx`d9&N+3`R#3Li_zMhN9`gjwAPw>?o!4Vs<)_Utik~pE; zNx%j1sptrz7+>Uwc#QTe7BfbJbyU=m$V5<1F{1EMOrsNAz2Hn=ad9)l)>V7cE3RF+ zz_X8T@#?(=ad(~kFbdkOroo0uzu=*6YKgq_k6ydLQQha2y*&!2SIxC^7MthTx*=T~ zAtq#gNJ}m1B$|(Y@KK8STYTfWmsuMP{RcntN!i#OvA(`R6h|%nCm?H0T}l?guYUGP zo`3ZL-@9|4BN^cuOOqFv$Pgt#0qt!Q+=;Cv&-3uz)FsXar>dgyeC>tTiIN+qbX2~z zW)G?;>%uT2Nm3?x!*^f185)hcSy6DrJG@sxq~1~_i`w$N*KZIRLsJI|UfoXN@vV^x zpp~XG7;wC3_`|P#m&s%zT1O}yGD3nsBPeCjT1b)%i(>aErzlGr=Ue(=b!w0lGN9r( z!Hed2Q3o`lsDog;35~Vr;39|jL`g!Fq*RS3uPXBS0uv=v^>XSSEM7&xL=l~C2c;Bc zBQ(UAG)65-d?PEn*MN9wI-L%kULU6vyOV+_jtOCU;d!dsJPfTBX_k>D8CkDOS(bR` zh*M27Z-Rk=Hq@?0X+>lVagvdALdH{7l^7{-i=5@K%sY!#ny3@g9}MYa9hBD0$`Y+3 zP;nS8Anfey@z%~Eo11GS2Xmsxu(v-)#Z4&My$e>jElXmV%YqHxWe|Gk)nL=N*FzY} zsnu|%aUo2z+sy(};NQD1#7P`zr6L%yG_=;lK3tFUyrOR0%0$KnA~~+5#%fs_GqlZ5 zdu{{ayhYrtLpKE%x6YBJY1>F!a24W9iek!qQGgm?loIDGqO=#kig{}PBUmpk?v9j1 zeR+8QE*Gy>;e0g}D1}oU`ol3BgADU9IPR8BKthreAEEcxpJBb> zRB?7|+}>90!%D&pzL*^N$*hsV){|=a00BrMA&rE_L0Lo9-hft*I5;jCt<~=tSUcxQ zlZf+MYb0(5S6jR?CswZb7Wrrc`h?&C??D;0D%6~HZPuWyUf289f84nc^fx+3KEK3q z`6fqiyv40s|0^%P@Pa>o;Q~j;Q(k-J6@TyDTO@HRGaFHku3OL4RGuH5&4F-RQ$Q^ZKX%R=Nw>M>}MogYV; zYOm!V)x4ZKJFAl+%inpwM5Epd%g7RIJN4SjV+$yhEK#TFbSk3Y1CL#hwA07v;7Vem zJ*n#jrLrj8DkXf`&)8-eR&|n*5ya@hfC1eiUu{7Y$APw3Rko#GwN1?OdTbj} zNNmX{)ja?DE|bQPMo`XjcIui3#|3BB2Pk!yrY(wW=~0V)e&*S;eCWxuEb@ZsyuzDA zx*7hLKl_yY;rAb~v+wX;Lp9~e%LAUiyy3BxOlLWHk^8N<@qhJ~e@db+zrnYzAL0l( z3Fn3ppL*uJ@5G)_KlVusM%Df=fBqvbN#D_5`1&nbNCXnoODvy!<}%&P;9c&GR(>&` z@!==7+^>KBL+ZDlyQTJO4HAdXYa6`t*t#H&2clXu$<_;!W`T-FSg(<$=E-XttoMw+ zd-vgzyDwVR{$Kz6$K9lUNq_Hd0Xo5#GhAJ=G48R}@5?;*Qsy%sMcQv|j3tReK%7?w zRInZ%Z=T`ul}G&a_*m?E7s$xc#HW!+Kh;#G&++jCI;!E5AK2pXaN_q4j`2SCWm%}L z&9VDyzxLDo_y5Q9>dk`!A9e7#p=v6;wcNVB!)!jM-%q^tn%CcYAm4fUK2C400?<}2 zX~qO+9i{O;6hGj@V98e4D&m{3-}hO4EFXPxAP2`YvTmPFw?ygSUS_SuIw&ef?GzWc z$NtfK@5+rkM@(E7K|_?Z!G}vDj^GG}ig031?lEQ1?R9ISh_$sbi^YOGUxa%LkCGtH zHYWT#V>D45v9YmEo-a5&I0$=zbFBkegl_4i+QcZO=yki8IOh21DBL?P6opC$S1@f% z+dPCBO|L(sYIRM)sKXN{;h7vs*n^@dB25zd!y(QIG8ibONbI~-k)&e;he}AesJ>$FA}W2TeFyDK8W)kXP3=`KS9^q;9WdKN=RZ& zQG+uPUTKULjt&pFdE;$=<;q2IHduO_D8kmIf9;i*S>&a7?`VkeDhW-vb2#gQmaTo; zz}{|A>b7253i^GkHwqm?2yOMMwe+=?ZeqB2Zks5ID61T?Io>yTWde%T4(yhOJjx@k zZFbsm;Sy9qltxDhb#1*@9nnz&HlVhsgw5?ocYv5sJJgW=>`WP0*o0M0Tpa4p=r?zaKyfGm00J{ z=Dl^F$FZ?Kl#aO*LZY+@W+JOMK52eV9Bf+$A6S_mdFv6i!dO?6^8iCyRCh=@ev*TO zf{oNsmouJ!?zxt?YEh!-rYQ}ES^o*Dt!HVJ4jb{Z-dqj5m+ujfho##PoD}u%sUBGh z%GeVGQkyt?K0yN3u4r zS1w<}dduO#1knjrr){I(HmawNQItOYR_|%9 zme)zsgpf5^q9dG8{DkFo8LquxO&PvZEuL~QWimTvHod@4fBZ4ZZ(is2TenEkgh!vc z!letFy#CGuyeO285T$9VlCvGplUKLc*w`eAJhS~r3#&i7tW7tXHxPk-Qy{MJ`* zU{y?};Hk^&zLN;vJ73o|-g|%R_Kw%h#QyvzAJebhcwUa0ut7h1=?qU?9JB!LYlqQVrn7}# z>uLMBk3Fhhxp!T172#b&Y%~|nond`E3X^YduuYA#jZcgcoy06kk0rt+9nNfRb9Vcz zIOoap0&gv864C8;iIl@+2?tiQIqLYwFOBS1?;nV3oNBzKt_#2a;Evy3i`*wZ`m}oc zkKVzmggB0gRKX+LXE92c&T_`<>!OtM`-d~`JUD{!r9iWC4v|ol=*-}Kdk-&j=6rCo zn;ahV%JDsPUCWtKAMYC8dFxH~_x4yHuaP7fRaJ)DKx^?WjqLDfDsR1gn?)XBx{5|c z#HK~G2|lSxYpk_s6BDN$ntG1bN&CzRu7`0HQ@0lGQ4|N4CliI|pbu&E0-;dX5lvl( zseBY8D4MuIYlEPOOhBfM)+AAkiDSHTBx#DODw;G6O_!2Zh#w)Mh)m$<7eyYLhPLTZ z67+-4d$f+)=V53>%A#nUyc9{A1`V7J*2Yn6P)dlRm^euht9wHwD%=R z9AV6mI7#r%1^SQ)Sv^q{5kvf4wH)@>R&p$T&q2Q*$-)Q(Bv&`E+XDbN>$cO=f%lZOc)Xg4rPng^W5tM zk#4)K$1Ce{1hfvcE1U!aNl_m0D>r@tuSKgs*O1_N*HRe5o?cVW_I#|o^t%blyH%#j z`|HoX-fuvD%o0GieY4Vr(OM8No+JpjdI2SrRU;;f5z#2|USTCRZQ-M0K%uoIZF%R; z1)Egw1uYJDs_J#lb9Q^1^BXt0F>L~p;ZF)Z-=Ymm`bns>SJmn1|1C?daHFcF&1k5p zmC>+%fvK}_tQm5TI9lLcO%w^D6$>)v-7A#apPa2*j|)xHU>k>tOsjWcg;qH4QOm*= zSSF-)dn_q`OT@5!?`8AZ((YExkZ?i)AUOBd^C{JI zO4RA`+{+L6nGY#`@gwKCb+$*=?=oKNap&G4FTe8;F)`jZI0^KOL8^&-fyQ&`;sqYQ z^P-;|?Qw3i%P{j0^}P|KRuL+Sh@+S@n*%OhKF`~49Q#;n8iA@>*zxGBB$3gSL5w^a z_WWRN#C%cEO(Uk0sW|I=-IQ*SbyPP^5Gg@L#9DE7qwmM#K1JCezVf|Zmq;fvom#q` zG+gh1GBKOu9-sQ;PqDq#^H~cdgf|_C?7>}q~nxM z+&I@aZf(>+R4|(Fzv#ygsT~}&4nR(F>S$~bZnE??dPRPrGo448PT5-J#+57X}ev>L4UJTmnB@~19x zc5B4J(Sp3F@U{T21NGKAIX*gIHk;AZ6|dab<(=b{MZAfXP;f6121n4bNEG9BpcrYI zRv7G8({y73Wwlu3Xst2Y5XbTA`VZzP!LcjQbS<;l9PlkASMWZ?y0CXB36x0HPS=Y( zUlm}wr3^V2&VseBZCb+XEQ@p9HUmZ*v~JKkCTNC2{)0j&%L=75dA?|A$4dlRBebq` z?Ve&=(fbm$_w9QHt)Xt83th z+f>9!N@PrU53Mo5I~GsKpwMwbIh`?^&4}Y<)o=w8s&D61sV^ML)L=pn! zEKW6I1lzdP;B2`s4>~bAQY?ywva;d&(<)R6?c=&}gsdy&kvO9sT;jOcp{oksc;z+u zZ~x}s@t^(aPx=cN&dWP*zUiO;+P9>fmm&fa25{zSeA~zdrba;Zy!XULb8)**FEi{P z6+Ae|aY$Pxc!u4W^+7^o12bT@DBB#fz!oTK&x3~#0}V{atjO}BNV{Xw>>g!)ve!9p zz4PMRs3`B8!`nu*F&RGn>_!3BIaSOp5LrUz~DSC>JMA0-hi>u?WCx!clBs$Nty zbwivbs93Ewo6wlF=!Oz(!nUaDCPy#A}1U4NU{{1 z3yJf~iMlsy1(D=lA5tKF}G!hx(&5}Z9E!Nfy1_S=1zy9y@aCeVC`s$Z? z>>vJp{`!CLAJXXzsOu^;p{J06Rm1aR=u;={*Pmv2ymwwHEvH{!mPJ$hcBh*XrPR`7 zZG{j8tK`s(y7on!3n*OFes=GXW$Nzk?n5*MuAHI>(0fxil#2yAis=fUm~b>nm)72rgRt zIyCexi*u!!Te8xF_qoUUFj-Fe1Fmk3_{0D{@u72AwExC8zQyaW-zLdYN#caG)8qWv z5szQpbXT^|iPx#zId)WRvT%LS23fvgJAe`u;Y~)=2?hnnlbpn8v;os<3K4ML;%!@S zBTNfRK3k9^F=-aBo{>r!Xoof42R8kzuuNwKMj-2^7!xRF)(g@s%|$e|6Q;Q^oz#de z>GXSKX$OVFdPnfd4#!{-W(&*VQHiZfx;;&|6Y?Cefdc6~l(nU{!n{&UrjBw^lO>K` zuM;RoTBF1T3uzQ6A+J3LbH#iH5jDNOAxjgC3FaYb8Wh2`b=2N)m^V!35n>ngI*Lv= zBTYMGNpLo65NhivYsBF-z+q7I3+qFCx7y$JnYLe(@B&T}Hg2n}bqo#a=Q zrBbWuX4r>mpR4VV#ygK_L9cCdym*RuRhl=9TgOyWq`zHk*K8fR<3;p#cW z5y!{J?9P=GWRz8oR))&f+1q#Srhm%K^!@cC*82^}k69jqgR z_hHjWvrPQF4BqE~_ypFY6d1ouZ$6z`?T8{1613Y%-?ETYB0PM!>-T20G^xhbO%N-V zCE7%oG+50x_GIcCCUpSqL!(6n^5ZEIMP$8BXhfFHRO4Dy!H1lX(HUHSoq1UzG_A-k z!kdT&Xle^0nB~I|5UsF{rI;+x#-L-<3fE3GM!u!Ocu$eH#eQTkZL;V|XkkESbc<-1 zZV%l;{L9bi8cQ)-AXXURm0*54iS#V>t>Zl}Xv`73{wZhzpL#;)+7Kl#d) zQ|E43kNo&1rTqt-@YI%#&GI$d^WyjuU*|NPt(|0gIq4q}Q6i$yI-EUGN?fS?ytPh5 z1QSI>CPO8Mcz?7y&(3*hEY3TO7?!UZ(3iGoY@19aEo!x-9ugYmYLOEq32_#3B=7-u z)B@FPMlqR^4*HmGhmNv*?wJex^Vy7dr!_n8OmKBgJ)MQ#Gz~Nmr$S(6l&0*?Qg-Kx z$G3ZaF+IlM84P1T>|bJ9h`e(19dV|MigL;-?Yna+oKeqy@T!0Fjq3>bUT>hZ^vnw{e@%`UViJdoXFQmc>@S>p z@~KPq&b^6D7o}?I+V@9i^q0QbVn9-<=X?e^`ufD;BGku1c_k!baGWU(? zDK$8YEd(9MREvx^cjoe`4?m)}&vqR+U)Q+|2W#@$tM~OcU)zJ>MO1T_Mt7*Z!r-VH zN1o^H@IxVSSK{F|(`lR4q7ByfnO6k|vx1^(NMb{zg{qj*8=s?!Ml6nx&?aIs&*b~p zkIaAk*FNHg8)y0BuYFr=<9w2h)i=KTU0&L$VQ?Nhn-ifpcW#R`>oQ(nr`zpPR+et2 z{m=j0$Jl!3NdD2+9$?j&I7z9kTcLUZCG#hlOYI=ZBr#hX8KWd2%QEsZh}`!N53u{* zIopUf5w1SZGf!;zi<`jqW6$Ml*p4-Z`kBNQEWi>bT0t!8c;{O}B}no}o+{&DsuE$R#^>)_8m&i+G9Iq5Kp?vt3AC?6VxnbYk1G5O{*_(wj9 zHwoAVN3-H!gwG*VWzFq(4@uLA$*c%2er;W$1P&)TMP;e#hO%yJk+ysA-b2*k&AU77 z9vpIIIARq;=pD+$tc|zW+dp7lEW`)Cy9hA~E6#dc(+D6!q>ds~+)$yY9eOdZ-y`u#lM`RRaSzF8nF`=y;-Hu^A=u%XcgGqt3;d<7FiAATMt!!**KLdnkSz;8M z_}-gvqSr-tL6hL=?3}l+f8&CyorU5f;UXu-!Hm!NEN+v@Sv{yco;oiA6raW{Wdqu1RExMISpsRqdnWuMtuCOgU#)NRBoq<}*`T+g zf-R|K%ZZUvp@3F8SPSM(*vqwC?rbwYbBV!V2uFS;m~U(&wyANoP*o+NzVIv-3$8qJ zf&c73{ZIJY|J~o?3%~RGT)KRjpZmF=Cp5BZdBvRiKc{~0f9TJDV)L>5(oU{yPUnLB z(2}KTzI*}BMxsNllm8;5g&$G*0Lbf&}>-Wj06Xuf{ z+=0OHPYEe%6pi! z!|mgO-~7E-M4MD_8XarfSm(d={EPAj-+d^)a}85Gz?z7|s>g4Cb654p7vf&llO&0} zb;9>v*^z(xl^asUmx%0wMr&%pY6J=Q+j&VFLE!x^?NUI{isVk==)L`LB}*iRLU{03d*t++f<+$BpHyd zZIB<$!CAyapcIx42lE4tC%IJR)L}bh-GMN;#F0%Q$xvG3(lx&RRxWE_d`*A;=Q=*g zQXgr>i!Z&&Z+z({$DK#p8AxzNi^Y*I7F>UG!q$3^^>L40s^!dD$GiMCqmJRR4_;=i zpE1cxuHQQ3;Aj?{hO&ec!i9h`s8(REqZA!wbagHN_OJg6zxd}r;}`R}cyH-;hpde^ z7_F_T{%|Z!qv^)i5nF*oE$ZuADo!vCv8|~`X+7IluJKd7HS*~MqgxA5+u&W`(HkA^ zzj5R6*5R9wG12Y!h~g;h2Q7lD+9t5F!Huz#rJ;z{!uH09QRaEDbBpnKjT%EO8OM3U zqNuTT(<0lRjq!lZu4ez?4x8f-z@7~?T+J-bz zto2gzvL;{5naoRuqak7oCbN=wun}C~>R^%W+da-&OO|CAtr&F^YOiQSL7XsN8#1pf zi`t^&I2g-_v_OYKbjbKvu4Unm4|KS^Y{(lQw4Ckm#yQuTwWyQ5LS!Y45O2|)6npM* zroD9*^9Mxv9@+((Tpf?7N0-s#b9ilVZJtKUAzAGw+5{cPEU%c(OOy({5TQkSL{T|Q zF!x;yYDPAS3X>-+h1cy;jTc{dA zNx>lXjMoMT0h~HH+FdTsq;MZ=oZR*4v*)EF}(0bL!Bso>C=yp7bQw*?(WU` z#>@Ap%BC&wWW@(zo6TXuQ&%?l`b+mXnwLEG$Of0T`h4q^ z`xK2uw>$x@;8RbX;qmhWc6O)WJm)vM+m?>!f7j~J&Rza@&z>T?*D$j5|qG$0)gsEd-t!6E&%lv!o@ z!S(yx-JJyu#PU-rMPAz0#U&64@D7v2-1TSpC*Pj(?_@nTyFGchcjUkHgNgj^%MJ1H zEU}qU=QB*2k?V{6&a0Mqup^I;7Rto2|Nbkt`05)4Q%3l5ic%o4!mBagxTT4od&uWM z++kyV==b)f^3|6PWY2BjrqkfQCxXg)yfy9ee}46@{K5xEh@?E&E9AvHQ@K~JVf_MM zFHkDjX}f4dZu*qc!KjL|s3b}UqPt@jvtXr*gy!AG8$5T@kd0>Qk&9av-?-~idB23*|@{1oHk|vRVcsOGgox#U_$dAz`qM*YczrKe` zN;b!RKJ-ip^|6~wBKiCO_w(|No5Dvw_w#heJzjkI1|Rsq70O1qfBz^LiKGdlRu>)G z#1xI=`!C<%{G$aAcIRGb5D~iF0h^oW==Dc3p9hz_{exqUju#xy951|lll|t=Fkx-K zt0hW@2c;w8{*Z-teD~D{q=~{e5q8nKOnFbFg{HAV52X~|3pjTT2&WX{Dn_Fr`*-i~fisR@ z`<0*NjkoXc$FJXGw;poi)~u?H)19>kvR^Yu0)xn*;Fk+x#29 z_UC!*%6We0cYlxX-+RE#cO4J*j>0fRgznBE&t4s)4&UP6`sF{zCqDjBzW()Z@Z2l6 zx%)8X`t9BDY&Q`&%hOlSlFn}NtDk<9zxWsaHQs*nb-wu3Z~6NNxm>^bFlb|p0dMi% z(b2)e_5M-L;$RnaLbB$AZSfMtZJ$d`)vz%hvbD9&t^I;~`%}b3c+qsaQ@qj?l{>M( zZ!gbQwz5LkftAjO=PTcOiJ$rO z$AVGAsXb1qh^_P2@W8t}I~-3dY~#ZF31BM{v86FIc$15GW-{OhH}?5_Q=!@$a%tt- z=?-Oc+xxoSVNx7XNhesm>DE7JSD?amy$N5O(81@o2JBsJN^#;R1#wR~~l{nJu-rMEL^L;*WWs|!*4|x1+ zkL^*)b1&TFd#~>hrwP--^60rWrn3cK`Q{s>O8B|YJjuK38E@P|FkH-1%fNqn$l`$a* zj^J+|8DSV(UoZCL)^5e|(U4v*6QxEd5wbM#CW@pf0~EciN1S(viUQ@!XtFd5qQ^Gx zp#25!K{|d!gYn~QNLYWu-!C_XmNUHabZj>*PF%-Y;>wSF54UuNQHp!--r&ps z{0nStpJVIXMe@bMmy085Pkd_vaME~$&*oP2Dv)r$wj19G<*WS{B1CbZ{w)m*#6vTk zP)?_0!#>GyNV6!J?d=gI3Ej0ZM~j-b?oQd8mc(&{_0ZG~r8IFQ80Ai6CM_bT(=Lm& zOB0RgcIVSB)4VMCP8beAGu_`~CgcomVR9p-!Q;+hgMfDOrSQt2q73P8QYKxhdgjYw;v#ca#c_mlr5E1_N<%g#$DjvWr03T0 zI`VZs_d4B>h1p_0-r~)D$D>Kk_V$>`Ea$=AF`a$~9T`+BHV#*~3(p|Y>=rS<_3a1z z(Q99qSXu9z2Jmd2+2qW|mcM=b9Txcl>l9uhDoJIp?joDrpg${0u$H*jTQzs#aTJCo z_l`=8@`$%MTay^!i7VS=NyLML3AcCl1KJ%#VXfRXINXe zdS-)G!uIBXVK2iZ348a3y!&uMg~2J>XMYgbH%-mj`j97|dIW8P#;1%@b{1rMgkV_J(wimh6-z36G&sYTU%Sp< zeDNiI=BIxeYm3$P7c@)}=Pq2MKicGAZ&&8?1x;0Afh>s`4Tp@+oF~nC|3W^N$3!W0 zG3WW`pXbflNb=4QYa5E905Zh+&TLk^A4T}DV7=df{DkFDI0=52)fW60+|dWFrk4jY4n z$Y{>4_fQCX`%|p*lql+|6?I7vpdHN`Y*{ib8bW|!1K!}=GBtd8OrE;&L32VV_#Ph3 z`0&*+ue`laUDts}?>*u?qC-)hMT*HRXI51F%BQapN1AWG{4VznbIz}K=yy_*PhVr_ zV8M6a*yYWgV}9mC=jnGM2HluA(%ia#+}hAC-}zMIz^P1(c8YV_s`b4hnz%Rp+d=Sp9^%IUJImgqSUN>cH*bBVXY008!&?dMqEvY|= z@@({lo|*WXxzzI+PWQR{)-7MxV5^yEr77C1lh~M$;lgsd3BL7)*E-1c-b<}oZbIz_ zBJb5~EZ6A(!R3_gCm|v~sd+)9Z9Y86a`eWEnswrUC8yrktqyHz8#x>fD5o*UdpGFC z1&g%sRauLoK}6A%6~$~u)JaLZofDMm)N93Aj7g&QHQPh-rwkX`@!PVgG)7ZTg5W$G z^+`tq>bzjKyGInqWNSkvwc=~9++#TC@Uf@Qlco`M<2X3Zxp8mG;dBvFr5hXQW};h5 zUInfpNh6+o`e`{nJ`(rFL*j0qa?(=k zGoOGDE?afokk2O!MpxAO#=6|!n~QUfvdqc4eX8kRC<1ht7B~5V^JmZT(QBXeX@6aw zfBPM(sw7P^;y9(qYs7@a@!;2Aa^=x$GFV%~HPv7V&}utbK!<3iEJ9k_3H6VpbhwpLROYp#CGN-Xku!!}` z0g4Jq_tueh64u5Ujsu#iq^=SU_a69e7D<+Mh>`*m2a0N(X!_$JR15w;_TKBsvLny$ z`();E*H_goU)8=F4KzF&z!=UBcV~mkr3rC^6cq|>NMtY=k|Ow|(7&KZy-E?17#m9? zi9u3Ja=5dcbz?CD%q&a;Xot4t?e+HDb53UJAeXruAM z03oC>#-f6Nxy35S-3CX;CoC=2?DozsVW}oO&spa>S1}O2qA)+tAlu{N!-u?d<1($r z5n)uaN_s*~ujM?&yHqGpDzEco?})jw<@P6^+D@!U{4!R=cwy-FWGN6zad_N9m>OUI z+Ev804Swf`w`ufJJf*N|Y9QkVmKz&OoZnpJ*4=H+tuOG}bL*V8AA@jtA=bIrxM7P0 zsRT+YlFXjXhh%;xS}?-qIU^FG4MyksOJ<$G8ImHVNf~;kZ;az~w%I6ZVO07e;-5{AH1c9bh@~PKXS(sl$D8XRZ1*`LEt-DDB&u8b!4nO+zh;DeD zs!)_8pN-WyqR8jsYK?S~FiJB{I%A?z0j&*(CtVb9{n9c*2##9=u3cCr)doMw`0A^h zl&VE;-9O|sPB2tld%JCSV?L84D}}Rc1j}2`uMkPga4_H-uWc}hQ}$2$Bx#p8$+)~R$3l67cR$@{ zl4e|3DN_hM2IC2hUXs_=ZljnMkWNRFk4kU|)pX4!_xV9F`!~ms&0kmU&^4VJSwl8S zbBd1BaJb=++j!VjqjfIk;J4pHVj~;SqrNCES*`zaw5z^yFcaC{_+{5?I($L4& zW3QEoa|;>cII(s#rq}C>Ugrb>!k98a7&7ShI6XOHJnCVEBugiteNqj>;fTR-%p^(k z;`YpmZMOcSrc3;>h{*Jy`SY#3!7#=eYg~i)Y|~>u|NLg3#}w8V!a?cM9YS%E+1*Ag z3Z)v|Bg%QwmoMICR9>=uZ9Sjn+t{Q@coc15xHnoVAC;iSUVHt9c=)76vvEq~&tY|j3L?aKgb)&w3>h6ABjc-_yYP~ThfRBWd|-8!37d>j zDnu$DD?GF@==L6_8&WF1C_LX2CrA5M>r{ZF5h~@Qv0yWFXP54<0s5+#Tf8EU9_-U@ z9AncW(hJ>tAr%&Z88oruJ>`#yJYU;G}#cd48uwQ|?HHJWOz%+(9aq?u;_u*vRGpCmOomCWe`JRdrvghVZ| zJ&O6q|LS|xOFr9;vFNZ)x8HCsiC&0B5SxtS*dvHm_^03e5$9JvW$&cRu{tLXIwQiM zhzbI<@#UHaXYX#1P&c2b1$QGS3>9!SkWW608li+tzPU3MEk zpwk=Bw98_5Aem@2qqYW~<)}Gi^~w?-pR{QG>vvcvYEl!*JG(u4r#*s&HH-?7LeZO8 zx~9lpQsw{o-S^q77sTD|#O}vSwm0qyFD&2*2@<$FQr3?J?-~W`w_wEsfA&0|2 zJbw5HrK+e>#Wh&Qu(Q3(#!DCZ_D>%3{rCRJcKRdw;YIQAc!cy_Qh6Q&gSCc@^Bdf_ zw!t9QJbAoBr!zo>73Z{QrbZeP&syS1#>J&7SHJNxrDDkUKG?!)iwYz*N86o&OP&-y zJ>MiQWKh5~&)146V<6w7#dK_UhJ09<4f8>Fv^H2P z92>&s=!n4C*IQRROoy#*xCTbJ=0ox`h9~(s=8g{Mm_=@xj!lu375;Fm&E^01-|#>E z5C0uuX^u(knviKul+oI`hFXmm7Lh7&|NhMIYPzKIh@yzQx8CKS{nqb``^hH#Vg+jq zo)ARE5DiSMk%^gnQ9J(ytS{cgpR=Y4qnXs#8l=@ErB%Lp>o#w^aGS4x{Y!LuBQouv zcYzamg@qDp#S+WQ%cN<7K;wIYFf5~m#Aez#Oy$8sLP~t!r`>Gw&EI{O+np-9S|^#r z6hp-uSC`n{gL|LtFicWjd-;l^fN2*lC8T8Uw8!#%g`I;Y$IU)pyLp9sj}94)q0x`I z_u!CmoaK}mgUK?+g8|jm1@1lV(C)`9%$Iro(lV7|z;SEH!<`n!8l-RnVLfXC+yvwO zy9d1W@&#VFus}S?rnNrcHkQn~#MsdHc<+NpoV5D<+AqI?uOz#tV?KD?KuI|5Px$hS z8wg2oz4M4_xd7HsixfMDZQl8Kk1xM`j$e9poz^>J`r{NY zKO{yr0;YS}cNisAZ z4<2n%tQvxA^#VEt$RHK!&SCoB=xXe)3!anDmUx?}$Jj}GW~ zON14RAC=L$Oat_+&|RE84U55Qa>~S%Y5-}!Pu%WMs8uP> zRmtL*{%H#pMuhY8Sm_YYD3pBZg;k#HwRq=~eUjY#;NgCUUwPZ(_3JAfoOVf+M0g5q z1j#tYA0F`HreNIKQ4keyw|%4hGt;YT_ibnK<|in@GwEbcdt z5XBWYokha1#V@>2^Xj!ZeY$s7A7CAkGlLNZMkuIk%PvNc;bpbV?|ylO{dci zt#!tI60FbmQHNqw=jH1gER+lU_`|1pUWw<15{`$16dv6{LbE&I#^qJk7AmxR4{3JB zj-n++u2YjF*7E6YpBv{^X>|sKeT(+ixxLe5qy@^496BWx;PG&O2KIt<%yG>FIzEe)>M0_83((cu{~V zmQhM_ynDbqKlzjkn@cP%uZaOZ4<5HU=_NVhWKhawtmss;Fjr-H!P(ibZLBg#B|E1> zm;d7Bh`w+GuvT}>fB4ZoUbwVGAqu$r^c1U9jxLF_3@$0aNT*q38Zdaa6Mv3rl_Lov z&*_;Bit@eF?W4JV(crW{Lc>(!Xe`E%H&i)=HXrD?CPotYo=c)PCJ!lagCDCkf$yGw zmYG>Nq5C-jR$zsl88d*RflHA$G1d*OEa0mtVq-~bSNLb|+@@Omm;C+z=D(y|TVNbd zcs8pID-bFG;qsJb)Q;I{0-onm?C;}QfWS9zr*h`>>v&;&t9JnY$j_pR@We}Ah_f9_R`NfFj^(iw8=lP7F#ACYK7 zwN~b)fJ>cm0P%Ck6ZJtM4hrD=cmBDb#?(PZUTUY4!hWKH?L3_+++ieP^B06)$ z`eA#(J0Csa#&Z*{Y%X$tyNS*WlX!xUW-^XZIRcbgO`191bgi=-R+cpT2_HW^;@5xm z6}C@DWX9&TY31;`VE-EQK-zs!t^1Wq3k70+m$I@e=> zYb}!`qY!!ol?tEicF_}yUkGXTQ`*Cf@88~sX^4nrXY*~qJ#?xOahEsGDSqj-bsC3T93PE1Jn7<_ z2`?;{c{Ci;Ox-~!ttPZXDoa%g#Uicdsp*X}*=+TMNk-VXg;$!JjvJ9Wrdm`ePtj;J zD0@ZGX!l7cF~*$W*EdO}kF{fbJ)-2r=+TgqW}9xSX^)SOiN|APBC&dm3L-}*O1iv$ zt;9lP?Eb-#*xsr!>UYFkt#1F`-@0l3kN@ujxs#?KeRMqH)is~L`PEIEjT^RkvZp8U z#8$(i{}2D}SG?q3{J_3{FcH%85J`$iIuruKT(u}h{f6EjHSNi9Pt8{&TAd7yb|HXT zQ&Ta&^!f&CHDgD;hUs@B+U=Ho{gvxtWi#WSeCLoj2pA_r!fe2=etFsc(w8pKY#i8h z)XTcB&IQ+a(g4 z%$EX6VI8AHw z=cq$-Y*0agX|SG@&JxyY!~N|p%L_$nl^Ts+LWx=>LYJ2@ z#TFtSk&K6k!WchqT)^__C-+$`ODwF1 z?#!Cv2m+kuLs+bIVY_LXVYF+Il$2z-b-(XRH_$WI<--_DlDXgGONo**qLv$=OleWt z5C)R<LA!v1D2L0GQJ_0$NA6fUBiUprqHDWkQ81%WNCs$10KupT449EN1A2SDg|nlh(ZvW)r*_Y3P-+J zf5!Di1M+j0+tv+6XBbkHE#y2#gI}%lUSq)j`kTMU|NQqdd*!+3#c-UsLel2pPd3YA zKRiUvNS<-hHGn|oX}jIlDgW-9zstY;(J8IUt5`3BG(n)qw4pc7FhPN$uZUC2{fGO! zapM9}=u@keNG20*-PvY+xyE3W(CQ9&yx-)c+2i6yotLkzInk!_*gb3_tu_LeWdHym z07*naRCakA%47Gi%X633Sg)7ZKI-xDXO7FQJW1fYoQ>s$GS|;7(CCi2^Y|EJER!@N z)s}}lEw=ZX%+FVuDKhc`&Qp@fB;~Nx<1gL3!p%v_ay8;!&rM7ljlm#hKgIRR1xx5JU)sak(Mm!4Rn=QMrW5 zi%XLuAjV`k8rGDe<<=~{HU9_Clib_susI*`E3dBd!ufgL{qz8xZ@#|gk!nL{FrixT zuvx}9o?ws^$`MKl7jk3-R%?o($JKLHPPPXOhOv#4%n^!&;^ef=cfa#p+9POn6A(^2 zBuqw{CiydbX3Rfbvu??LzTtSb5t;tv&o(E2iYDb*(f>?y^10`d^LP=Tdzw->%iZbs zm}xF8RwyO$q|Dt>T-J;c7V`9B_f+NVA*bEPO#hQVAB&yQ4rUsaDby|??Yrh9tduFt zRY)f({gWoj4=66yv3Y@ItwjmTC{B5L(BaJ&*62EAizfk7N<$1=|#|u3M(gQsr3Ita#UZxUY_l~+!d5T0UQD0o76Ket=COW`c%}Q0U zQmzt3i}Z(m`Qs0_X>>DDuP;!RWttgedE;I$2MFhaM;vAeLInst;nI4@bDL#za&pMgQC}wJL`H>>7niSyl{IaD z@bQ5?9a=HemW_JI*WSEnKm72P{mFZu$m`cGgriX`t^m(KFuz43`_^W~e(Cy(*!`$y zC!Q~a$ylgFJa=x5P9|J&}VD!gu~-DFW)%N!`&vzQ+U4H$E0#DQ3x>$ zF|~3^1$EbwF&1MT_U^)84ULWwKbOKBO2`iuRgzy=PR}kI(VK-RCiGl7Of5E*XMZq z#SKCwX$@nl!~Z_TXDJx@7(jdreS zS2k8zs1`_#VP&qwhxZRSZuF6!!bOPYTb7c%c4L$4n+v3AMrSa`Xc)8g;4u<|)lNUA zge7hs;p>#w-*}rsxx!z*yvptE7Qgr72NKehF>UR0Of_;zPCe~q^MFE z^Z0;fYk>4iuFkM#rc=zcVR@lQx#&{~1b_9-%NPUie6sI^*@)c6-8CP^8jKN`T!&$$ zbm6EubvnzY^k_?(X{Rw+C~|SF%3*s*XOwY%sSL*QXurwQT#41i689eLVJy6KZ53-> z6o!?>5|wg+D2N#iC;5?PuvjXkkZL)kKQKE|GNokEV%Lw8L17T6p5`{h{ z9U-wqp|bTt@e2gxFJOJqfcz(xF&RiVS+e=fW{k#GH~8LBM)Hq;SN!*XyU!apUn7bl z(o7?)K^xaR_zr(W*bIxp;L^f_T&TVM_#yx5-~W*R@Nr*sOD|&m3TT&jJBd^7JUnEQ zWcWD;R$;mG^n`Shuv)LsI398D=?Q~z!nfajNPjRUHj+Ph?;*osOsX}Pl9;7XW2L4a z!AY~vAKl&|GlJG2;fEh?F&H_mg{RbvhGY$B>ueu)4_gdI35CGtxD(U8wL`Z(K!yc= z=cn7$Y9-QHkRV9w+%qc0fFFL?Vi+6B#gO+tyNeZ)@i^h)T9s;~_`@G;@#thiST2%T z$-jAb3vC5fDpbz#m)0fjdV%jmn)xJes^xgL06*i78g!arw8UiELDzY6B$T5S%-pk{ zEpBD56mj-tcv3J(48Q&UKFd{~ue`L*S8gn0uw>4>^DJ26JnxU<|{4AE`%pzR#K6?a!>dF_@tM zKhscrUWdWw8~z#AJg$LA63qDl+YX++pLIkGS0-tduC$T=OwFZ6W-CXmKIu zVdoA(xu(k)c(mVRb7hWS|HgHC!-T+71fgK>q{m@%=y=l-wC5o_#p-;-#Z^BW47viL zd}KwGsy?q@zm6vix3^k&N};`wWOPbY3AlRo63v4xwoj#sLdENE+$1Q?@uLs#Gf?39 zKH1n%D0;l`+-3A+AddHU(feZ=mY4YI*RJ!^4?bp;#rVM-Qu$O$ii_uKJpcT2eDc9h z*=-D^^g_P!l~?Ia1mFMU5N&(}l0p=)yt=~cZ+%(Zz5OXC%@d+1VsU;!wEG#=xkaJW z5aIbmR#7enLGflbC^|z9ZIMDbeT8uQMw;(O=QkGkpTp;(A` zxYuTNd4acHI?s4CL0e}Zkr~TIy+S#3nMZgIF&5JcI^W8Kupp-<;ot`WOUnz~-)(WO zUgGllJdX~095n|yn?%kEX$vgRmw0Y-jvsvZl%=IP=I6`oHikKcC#R-POG#-c6xIJUZW5?>Y9+#$kVA{8GKJtjyx7h0g28ih8|NJbce#YGr&kk_j-EN<^I+w^?DWI zIrK$ha;H3p5?cYnXx8c_>LtZtvyU%JE{M)bQPlp7a zKx=~^c+6KKnw=4~Qo#AuIku0xTwAZPS{5uv9<_3bdck9N|Ac5RrW&Ob;wI}CeQFDf zHr86mAmZp)aU3To`LpI8u9+N-Ca#glG~>|(m4Dsy6!9dRH5#q<*nQ^K&YZmT^c+VJ zC_%v&91SL9+I`M)ihPY?Iz6A^C?QTVw@;@NM-QF9%=b@P-2W%<@z!_V=NE5Y;guJk zr(U0@SSnE}&7*Zfuiv5HAF{iRHrwL=?o_nqL2*3 zWH2H#H8M+ET9OqmDdTx^+w>|cM<463B+fVtc zUw@6wjde=pGO6*9+TaPuGK;5#b78TDESYe)f5absaGT%x;T`U@YmDdL#Cl;qeRmsk zl4We|HWAn}J+*auuRGgK?(eknq*EvQ+&$-CZVgdN@%VVi)1zJvz2{Aoh5o3M zJ8oFEb{cL2_RlCtu2!{pLUPm`@~x8r0+%*!tfd{t;01U=$nijP(CeXmZw93*Dd-H` zhV;gZ=ef7j=43QxVZOqJl`22@WS@8LH&DjVZ}(7PL?9(bDYj3?2$fG6bF^Z5P!+1q z!tzW;=iV;tGa8Y+&X!71s8s-Rzx1=@a$#`?|1%)K^oOTTQqu!c2*GMSVi>19JRNba zG2+U4nItic#u}{+FJD=tRt|ah?lGRPC{&8ryhxG4O)}lnb2JMn1##TB#`yfhzyIIb zpimN-^Abbrj7qgaA@oU-l>Ng7=#-n!pZlCh?>~2a&SLRr5t2Xo2WRZ2KQ0$Ui2MM2 z<_q?j|D5S|ezswn=B-#^j6o?yAqt?UbDEk%A04%LigKCH>42u6&D8NqCn-sI@@=LTgyBmw0})%<4jkgJz$- zlRk$h6GoXOP?E`Tj2AgK9~FdT1W2J|ud!tVrCB+*$@=-rT)6rIgZ3ex9o_~n!z)Nk zQf4sj^JM>&)ur>)Hm_R&Vl+-@^+u#xVpM>NDyS?2PtfTOs1`lyE9*p2fz&{=-9>ml zL7_~leS{ZLC~o=*cd6(lZxU1N-VLFCj#UhmZFdr69thC9H^qgw(6i z*CVu7CI};9?P1~+=>@2;j4Tu}S;lT-j1@kGYUm6MU}j+|eGf12NGB;z_S)RMzRD!k z^oJA9t82b{{0i~Z@1|7$27;5c5jUD2YJqr z$%{Ifp9z*Hdu_h*@+N=hmtW@oZi9o|?P3PIp8nWW4*F38bq%SmfM=#`0zMIIe=X?DkM z@6HiVm%HOALr?eHEL9^etyV}fO?Qw7JPN1L!D!NP;*1$G=*5~V^%{-#fJS#rqNne> zdoQf9D5;nv8FwBXvou#k2|;h1poPM#EP#cib%2nP)L260;a6(JD!}&(6iX$FzF;(1 zC({N!b+}X#q(_!%5)EbFS%TXnZ>p5j@d&{41iit8tDCFn%n(~RXb#ZY;ss8SPmYvX zoZk25sGStJLi8)>@uyH}E{gIL_P|Buw7>T1Ml9r@PIW*3*?6?hFuE zf@+;cR^!`yZGN=Bn6V-GNxQ)zFuZL z9HX;bl&?Hg?tqGb^|eJxg$SKm@kRIX7qh--K>ma!5JJv`h&i8AYpiiFrZpCdOFYdg z{Gaa}@cSQrip^Dkj5 zb+i>Ioj5q%x@KoeVTZhUeMSVX^68j!uE<@wJdyJ#bI3Kfoz)0(V~l(wcN?$CGUDMF zS9ukk#iX24o^m81-xQ>9h=f6cw1maN4B~agx_h3kSagj`XPEHLtzF){zQXGlYmT0# zB=@(Pboz;NSP_ECQs`cbQaKORaiU$t3o`$M!8H|by6s-86w?IQGh12rC4o?m9wl>X zj);IKKw^F6#!IPZ1q9-moyySuiGHpKBnM1I-);#c0FR4j^_ZLP>%o2J$O%a<|6 zrG0Cy&!}d9Oe690taGPm!Jle9^Zh@IfLLp7nx?{7Ykl883mdfgfslV5*8VZ*NxqCR zHcc(sXp$r)O|4KthH}YSOa#R$JxVy7#3bU2Y$HGMNCcx z3c@*Ld5yF)!WQNk8O_>ajqSq*X;A&@#d=DNYm1?I&IFcmCR&q*~hVfB!wspSvP%e)$)~CwI2RPam`} z(KTU|hnicVHQ49wqXWBCFNxP*f0It9MXS|em}b~$0aaN-=PqBqikv-c9+W3@7quBo zDg-L8)y8%2ivU9g%m@Nmo6_d(UvC%9X@<; z>i}*=~w1z^t1WM8z zq%?X7o)UE8ah@mS=i5tue+rRrOO|UF>MWEaP8waT)|^|L=l*spM~R&sy*1V$I7>C^ zwGy4)fGpKqT&=Nl)FVlAE9%^wNoR&~DP&`@#Oho`z3Nk+ukwSB_K0H*1~k&?T(HcS zB3`?`M$uO^yF*G*$WePtZy4td&@|Z2iIZQtvP`?(=h4$cu3lPYX}(PR@B}Gjo>o2` z{=m}mJkMX<;MToed{1!w;vxs91BP*$=X~YDYHJ95#al0)M=8N@9CN8y;71>AGZ?2R z&%^V53dIVe;TRcKsVpw@)mJVs7>pQ=W1>QVgOf68oMD7S=4eE1uFR$Nc@|d|X*WCE zdvu5m3Nw^zn#$@~$x&m#t;l#-Z}-UQMyH94W8#we)>(=N%d zZ3mrGuCHGdKl$vCESmrU&z|$z7_6D1Uc%J})*_74r968kIj4E&SUIIRPc=FsACMU= zNop8Rw7ZU&1}L7P-qzr#XwyNV1%u1pA`b+mRHvus7}|_S{RD5I`RSldvpr&*t_kV+ z1VMoIJhYWyHQiP}XFa&j3n7rou`e>MX}9~Vl|06A>>UidU)0Wj0qcu5@#n0>%XDUp z(MDr%-tr(_n4s1e!z`3eD37#yp1b2ZcRy@Y4_@tw#-#QB1uW@$N@E+<$Vy=Gq*_NU{vR z^U(o&r$dDA<&C4;Xs6G`+9{f1n9352*63s`vLvw+<;^BJFl`h$^Jssj8L(z*yZE2C z{xk{be~QNw)>58N*V=@>c zgd)fh4gjIll=@B(N&L{CT`NjJHs~{IHV7+aO7nAAZRnpgke)|zX%Q=O!8y}rCx1>> zki-e&-hkK-XdB5-w>oUri~Nl*U*;EIJRCetvxeoKb7NNRs8rtpNG8~nX#m@L{Oc_lQ0~g^5LgUgDj-5 zew9fgm>5M+n#b4x?S&jRTcX$h7*8phoxT{Pf?)9?qts`j1yOy2?Lm`|b`svcw#MO6 zlTPm#6_t3rH{d9(;T7f?_WP*n0{yhW4;~Epn_ph0TIi9a9lN}`B*w!b-@dggw$lrY zCK)O!A;JRhZS8UXktc6neoic|PE4^D*-ob=zV+iB`=Gxd#FxYOe4 z&JhdsZ6574MI$S-aQ+7UVa!Ae!umRmL4$XmN*RO&*5@+T7te_x2>3VO{B8T&w}zr4 zmdVV7pt?em&hu~oXq!UuzWDmvuZXXI?Jev1MSl9xWAPi`y33J&8CjgerU|ODOlC4p zdmW^JtXAc;lW^LaF!C0V>(`K_IZS3SVj4V~+oR`GX*YeJHU?+3q4ys)czoD%pG9ws zwG!pUAYFjr?cE;t_bh>@C`N52nWi^N9h#sdnYCn@A+R8YeFlxq4L$M(0Vz0Yjp+3E zDMgC@C?(Z4&kwOVuqv=pqLjcFc>t~i?`-ap_fKbyhrwkI4aONi{&bJtV8peHi}}yG z^TN!2*4>k%RC90Zl*uIJ<_qhzdlNG4-ZLrOKwyf3WZJpLot|{L`TQ!?P&pSQp`4Rr zz7b0-skYqTZL@#a#`7dsE-dGPb$Nb8zKsZ+wD`C=U}e6*lIPJIru5?s=_y3!oSvj7 zz`8;>As zs+&juRH^RT7;u4)QHM%QSDje4fiIWk#cvW=Oh}0^d`Ng~am&C#@bTKjR94N2w5S)aHj z;CqT<juR#C}5SOllhE2k4zf8EasfoVs$>`K~vJSRVJA;d(c_N(qb9u1)Q`8&Vn}#iCYbZ zol|sL*PT{#N|O0v{W;bb4am<~lgXr5DHns&jwf7(fJSSH)*6#pvb^w7QiIlxmKFFA zY|z)Mbds3QT4Pi*MTrinEo0>zGVqa+kF`!8ar2c+RHA@MlJel`2~T%VFf%6}m$+=S zK_?01c70Q%U|JxH*+F$?N9yc(KTnqt7_7+L&5i&mP@#vh9u`QmJjGN>M;Dvbkxnxq zOomcWpD!^SO-PNw^E|9D4sj59F^8LESnKEm+CrRjT!rN9(B!NOa>;)7&zv=IGpfg*vmvq8S|Nl`N}-f{rJ2@N2!TWiW?_jlrN@8t zd#$z8J_f9|I!&!KnUL1t*)+FqbiryAJUm%;(?^@-z@9-`SM+G%>`TQnhqIoHo#4Fe znh%p^^iG>d&m*eWom+ zau*qlMM#TZEOVz-<)8mVh{de0#ISFz%tW_1&xfrAhMC5C60cT8nG_+`C@pR>Il0fL zw;$kp9<>WEQmbB~-5tA$?9v88cuaaJakNf033zb-LqeIca{elF*Ir=1=aWpvc=M}x z#VT>C`RF9URLYF^pAvT)*zzi3@g+n{GaU4gl?8%Q4I2-6ItuyTUX`eKLJ%K_QnA6P zaE?y~=V^~JyePu2&Ow&Y8&>(=PLX>DO%Ze-sJTi+TD!_8{d3}EFhmPQxVVO}mi~B5 zAzY{AH~H+=4@Bv(!G)K;O09l_r(63Xjy2)ZCSF)%k|pfK9)Gyw$;ppDU@3Y)ZE1yW z`G$CsW{l$=(ZUkKFCa3_Q5^8UfA^3d-2a5PU%e`JkGFX5VV6#D1#f;Hbc!T!grkLv zG{$XleA2+|G+hW};W@(P^QeVI2QF)#Nr=wThiTC?y;SpSMQ3?ZwCB?vYAgn+0<1A4 znVs3)8teA8Nn+{7F+zYpZE&o`4+4DOcg~1*dapiX>mZ!{ZyHaK!V(iQPBN4fjt(Ov zz5*qR`CjE5odnb5>*)}S*)YT%7A{~B6v`8Hh8fLHOmCP{>!qZcXWY4P0kcveEo7Ms z$KBd*Gn#0Y7Aknk(V}L+q{y9_kc=jpo#u%Chr7J|+^QQ6Us7!Vc$^f+-vZE6v|AT^f7YQ)ve1rC~hI{gVz=o179$tc4sl<75(81L+nS%L5Z z&aKY#rI*g}*>025&X~>RD!1E)foD3KY z$DCiCqtTC9L@~Fp%*x6NKltb|_jV64NJ_;O{HTo4nh$P$OmC18L{)mj37&F##%UJQ z^qiXxJDq;dI7hc!BWI1BHOkZLZ+0e_85hAdF9MXD+Vh?b@wCb7fP8Q{{kwBfo8F|Z z4l>rDaE*=43~35!98;7Nv~@$BPOryHwTu^Ey~cN*q})9*WJo5Hn59~s+QJ;CEk}I| z!hmkSW82w*2-WkxDOcC7{_3w+FTJ>`fB*gWCw%|=U$CbS4kSW-O=wqW>xq7ZnqtPZ#^P5jdCpI%FX=;#4p@g41m`GF(X4t&g zpIQT2>o}V3fOMYhB2U$xj@YJr+UYpMX+vBf7`culA5~zrA=4Ub;Q1?c-n_BK)_$Ab zIHOXEc>mr}o)M5Uai(XS%|{o;5)a2nrSJ!RFPdYs@ zmi5INNoF`|j!82Y)MoPcN=iu(1t?F=pk%jM<{A;4qnFKV=|ZJM7Wk+jaPM!80FL<>hl>XQzYnF6zPm2 z^`~e)eonI@q&sSyYs-`>CYU00XH>Y)H&CC`aJcT+S}Z!7h(V`K*4G#$-Ut1YEv$ zfeV*g%*`Qp-nvO9TiDgt`1jx1;e%~OytIrIlCqd{VSS04H!gGXaF17R+$B;P)xT=1 z?S}ZuyW2$V7DZWM3Qeok=GN`&RQov>yKAiUVq3P?g>m!P(mr9U1r}5oa_hzxD-BEBxx>%Ay2?B+ISDRtP)vES zn-H|yRAqrc5_Xr#8%um+R`A_#2&`I0bhn7&$bmP)Q;w_znLyG;w6~zFP%0p7HVESg zt1I6FaQ&f<4s}W2v+yo6V8n)cBMO!i=wGRPziKhr~&=K(uY;C`T%+ z1vF~zyj`rV-@u@b^lIR+QLfV^-ijj&Ey z*BIDZX>xP3LlQbvduzGH`%h08yC~aN@eO63b785&XYOpU(oM*Uio2JWDND`a@q`fP zl_aFZSVJQU`1sXjM&k*+PLta!ZQlK0hrOyqc!_oC6QIf{+KrgCUdr+5jN4aNiQuxC*~e4$P`eC>LOy z6kzJ}$SeYW*S8`Vj^=1>DYYRA6nn#i#q<5MZ#?tIh2Z|vW2~-N?KjvynGyFAd*{ZM zm}Ld&`b~7X%=&VdZUj1M+ZThmc=ypu*6+MUG@WC|Q><{p9v-Rj$AmxoWL>?l_fii; zE)Kc6E^cbfhcnNP+S3akv#^LKgpapeRnlN>=_q-A@3%f7v({iuwMbO7wTs^iM9Ffs z!{x4E$FB2a(BsPwp7K9j9`R3q<|@DUH{0CXuaMF}KIOH|i=6BwJl!5pjWU$22r20` z;>%lW{r~l!|L$-7>NL-Gf8pBQXY+sZn-BK&Ws3Y|!*GI3PBp|@& z{@FiEe)AW<@ZVjzu<<+1Msn3uMci&S)LcJZyLC--@zN%FRxlXP(YQnc4P*1qiR zdMB*$=23og0PhO!X;D$=C3>x)l}3;kC@h!O+BBOn^H(;|9uczER|||`GRZ(fGl@Vz zAe||YF@`|az>vjiO;KrdRiP_Q6iQz@cMG+w3}sbebO}NdL=nAilRyP%Lfhg8S!-YlwW-F65oD*kA62L!t&+sK4kGoe__~WlWWA`L;{9sRuveuvi zCkg4?+r9XJsdqoIK*pWKU_=;43se;AwAbqdLTgJg8X=4(?sf=5S9OurP~~&7>5yPO zB}y8|ut^vOLJD8~@RyLa=Lfz#eTEo`bHU0FyZl`*{vTt0WFN*4T<4RHAM*OHaAB$!PKh7da1qw`P*2!n_qiX4rquA2EJW-REUqAGKgY!HMFdUwgKTT#~dKlO5{f5W6$+ zdlBc77)z~@<-RspbX8HzX2h))#=z-h&drN`urMzQ9`BAgOJ{s?rUXU{4v)vYdTp82 zev_gy>>p1kDi`#dvcv#M5F-SfjOVn{6@K=$O-{#iCgY4*R=Cdv_^ts8T`?NZk;3wG zuWoQMnls6qfPs>NDlZ6<#5LL@DJ#v}5B4}d851`WqChb@9iuCa6q2eeQMlek8HD7e z<=w{z499c2&4gw%rL5d1ER99R0SJgy!2a=!?>;_8S0&ZKj8-FNJ}*4zA&8nSqE^d2 zqDu2*=LF%;g)e>Ui5my0NJ8fMUgm#>qKo^s=2k1J~(p6;FqLrA=ShZno2zA;#>i9<=6q|9eIMOh+* zb`=v9a8g8En!e<}c(u)6k}@ps@Snc-oG%21-~IVbo}H97uOyKY;#Pmi-Osk!Inb0E z^8AMAHbT~y;#RW}f4-Mq_^h^!=DD8aS`V_Uc=*=V^)G+8yYt2W=P$qWc>gc{_4My` z5dIinKS@A9RPxnHN4aX)>gdpQn_GV8&^RQ zxT=HJ?qEb9ZHblEEmG@T&82`ia7tSXs#v{AX~VS4nN26|p!BG3Sym3MP;T>@qzP#p zqf|&<6g5e?ZgqL^@HvlP>~s6(1)6cl(Qw9hKis1h5Ij5laHV^2 z=)aUCou+@!^8uy78cmiJ6s1ebUcb`gm8~w%_Q%X-InVY_na*+!PG@{#WsR+s)`D`T zgh%C!VWk<7_hT+DuXBC9#r=nZ!SRF(y_kdj6COQHS?V;H&P!jdz@z43fk(QgHT#4|?kFxSpEtgGK+g>+ew^sc9*8af22iq&R!m`c}kQV(|S{ z8euV3n@|NJjv|pX8aC-VGq1SaaTFfTKS z$SR;JHA*Rxpkg*YrkGEejOWD3RX^TdX4QQXw1HSwOi%Zz%8J=+4uSIHXOV$8qa6uJ zs5E7MN*o4Er*njGl~;m@s4209dwq-{X*P+XScE}jr;`aq(GqbKdud|n1ufiik8?N%@-a6 zNz!b%fbe|f!h#9{8r}9nX4KIV9gyUVir##PBVm3NSpz0C>%JXgym$Mvojd8wbJ4{AMEkrixW%` z5`=-T4oD1!xY?i*irvAKMkM**#W8O`I;7BoKnCalWa#KTXxFH0gyfSSyTZ$Z5r6fq zCuGORq>Yp)j+u_9RP)To^v=Izz2D--+zJbZS*EamK-wF~m{8 z>Qa;0ykIn%yNZQJ@f4P3+x7QNr-h4U76K41F_*?rR3%Xqu(r~o%uC9Aj`a=WTDzpJ z*J%;OA=zw>smcY@!)VD+t?`we1KQ~me)ChG=Gm;n-gd^9zWE+M{px{z^X4V1E5mp? zv(uN)MW|wNy_qr`j;x5KSn97ZJ9>;sQyPs{oW{v&ui08vVdq+2^47*u_w!dTZ~f-a zz47|J-QW4uzxl?yAN@ zHB`o;wdLN|G-stmaJ#wh6_Ddn%v?b#0uBA9SG@>Qx^a`&FKn% zreiTE&Kj|`uAHisazQNKu&CC?4#NOzEqR_}v?hvU@IO<+QN50i2mXL`5~o5cYGW;} zHAPXNq$Ew9B1fhbRr46tyF`_&FqzJI?e-Oftyu0RTw3Yy^7%eT;H3cVxuZ^C&W)|x zC_T-kb|d$w4uI8~@g(D&2fL(6L|$mV`~EJ?R!XZ8vD$C&aC^vLQX;~Dhr4440w;B8 z3^EWHZ5U1Fj+&&M{RY+f+s`8BK(Ge;LX{@Y57*b3}l$r0N7Iu+*)K!_93w&-c zfAl1-t0UBh!`T@B=UzXGLgl~rk+iF>WBjlj=e+Mo?MM%x0*MrsvdBdeCqiI2Jw6n( zBM`}qVl;AUI>HCLLY^IZ{+&$y`nGP?S6Cw)I%nO_v;`G6NS1oe{Ea$*bHQcUaI)87 z98uHTEVx9(tBr-RB&?r5KKZJt1y$Xi>w2Q;PYVAPf;njJATT&;%=+{PCCH<&{fqW>pMJH#vM>kryRl z6np7Q!_L8wYoEN%Hy=M`Gjj|{t+q&7$0X8B#hJr@$bLB!{wJ1Pxhva8aKr5xLiC7v|*l=j3ybY zTWkEguRi4V^FzwAveV?Mc)D+xWfk};LzU;edTp6zr1<=d7<0*j> zG?x?S+u_=jT!5kiRGcEiU@?Uql@o*!C~1*th_xYsvnZKxd&-x^Ep9EydcEU&FK|5} z@?5rLVIkDu_9)lq5(GHdOG)8T|`7nj%_=A4{PP$Hw2SrOJ^OHH@g zWNW#}aFVmN(c{^{l-=E9gm4u@<|QVKu__>mLteYOOrvC&JZfS>)u6{bbS{?Wwyx_AJ}gMPhM%1S$8I4$_}-3th7c)D}q5)NYs zqtF=?YX|x@VnriXltsxWUs*#6c=%+W+2oYT(LQN+iT2tC<$TU)Zx<28v{u&~%~TtN z*JCt>k5)bWd5@=L)xgL?Sj8Ab;DER|kZde9X+)CsZp1i%I1b6?A-!fmsGxJB%iSwo zj!q*6$72d@xVGA6GdMv{X5#&)?;}s2v32nxo69W@PmY*NMTHYIm<;wv`YXsr+w~7w zw-eWDnDsiSsZe;p&RFLSa{1yC8>>xDPUmFPIrH3ADyvenw%n%I2xv579=zKF=t%B+d+j;}MdAG)-tVo3uMU*1F5< z8!OA})69H+xzqmj_0{DszV+I_`Qxv>``%yv>woz#4u0T}{4u|Nl7Ilm<9YS(zW62c z`2IZ<8iYd1kT7&jU}uH#dZTg)NZqVDolF=VAH#Hvln&*TVT1}oTCEmI=nR5P<(kTa zP*D~I#%e+(!5U0eQ53ErPAauPV4V@4_9|FTzEubTQn~=#c#43K2;~~Hq=ZTvjBr6; z7)EGaQRAXQD6FXfiWk}3DfBmt1AMWQ|qv>bb^314)87K zel*W0I5mIM-FS_|*W>3lm@o)OERemAAnZgBO=IyMY=c{E+zkFFDsnkJ!L z8Qcx6JVWlO6~tTsQlp^m`*zVYB5K)K>vYTGG(uX}ucPyf>CphC0vanzR6-J9iKKN@ zIO-&(9=|h%kn>la9Mwth`Gmv`?e{5TovVcWu&Zt+|Nig)U2Ls$35qyN2Nrk1*^2T1 ze~#9rRKW9RPx$cucj$FeaX2_-?>KW+qA*0p4T7}k6siQC3oX3^wOcDvcxh%o*Njid zt)Ig+Wi1LrRFe1v#-8z(JzAGEobQc1m*mw|n>z7ZRBk+-azP!jb(PO6t@%$K1d6A- zN8C8hSZ;3d2k$bfOpr1_SjjZE+<&ygr#^O>d!rTJA7&)&%VK-n;Ngos^4Xl+%xJGIV@1IINBefE zf0J=|TReL@qqnlgylU~m%Uz@l5mq`7Q^veJ81ejI#@6a}{$}r(PAj2|`r=#9Pbg*J z5PTufQZbqoeDLIeyVutE_F+IA1%yi%#M_TfnUo5loUe+KidhBs9_{hzk6mVxwRrN} z&|1C8{oR7S(H|!7z~E)xhq8y zhh$ksRhAs@CG^vP%4jw_0S7_FFwzZ94wo0M*_%zn^V5Obm!&&DtqN%_uVCYdmwTtQ62){{u-r}Q_B#v?PMiaL z5>b{VNfHyNl<{cHvuC@c%@ov_b`r4fRh`fh8Mr+^5Q2ljgm*sNBM@*r7@=^Lj+#QN_?%Y-grjy+5 zcle5%k2U7=+$HluVYOL+pvKEJmqm&4=E0#7G~`kZdhCIXane zI2e&>OBy+x<;CHcozopIwgov6m1)K#Z@GHbw68A zuvCTS*|UAO?uya_PR3{2mczpn_x_cp_H|mEN2Wpq5u?^k{_We_JQ+Qq-|H|OO>ChN zx+tV6D~#3FScpSKw|!!l8kXf0dc7uBE_cPsY6m40l@-i0&F;~VXD^S4)cbaQeN8Ma zuW@O0{qkzR{ZH4r-JiX%y8P$A{ONytUsE1F+dX*l2Y++_-u>VIKPNwUy8d`w|1gO3 zAKCR=|I0uB#jk(yum2VE@#~$I=jYa}1dn#=N`sJRPT$hGa9dmgvcJFYc*nk}RVhUn zMKoJ2qR0h0b>M1+rO0wz??H$$t`cHA>gptFJ+@_q&&F#Q>wI8e2f*?iy`@HKS@aQ< zc}|^d)E}y5RnD@UEH4p0AdaFCZ7i7ysT!M@<^?t`ZgK1O4c`6WC8bepZLZMkcPNZt z_c$jjEvUeQNM3?hxNX#Y1S~&yi?y?twU|=#%WqwxAxmC9eMVq1UJhoQj0-OILptq* zO2*u}d7VdxId6Zs@64F2bI`tZd6hd?mKmN5$+CjoQN{i+=gLaNg>HzI0ZS`OJlvh} z;maXNi4mTlU;$&uvy5ysB}ihDX6onx#tqm$%xN?`Z^ze_>fzD_}~8L|C%U@C=2a^7*TJy;v>O(z1c5<;&b1x z6RAbjqoxs^zs|qb5BvJ>d7ZD2ID7#Eih@yyp^LzgkXDQ~~O!}k7|C<;+=NGL&OW9BDEBvHirYKu>N`eUdl=A8$7JbW=k2<3fA z92%M*?a@jkp{=-j<1(G4CH9UdygZzd6`FjWVYQ*vZBh;Qi6sbAu(7pHdu^T3ykdVa zqtxyL3+t+~i+~gDKP8D;8Nz7zoNNgV70Ls8F_G^V(%p(&S)N zF`O0)aR(tl>5}63fH)2jretGlgQVTzbY5{d%oa(WHI_hG^1&e?nlhWSd0~~_<^_(Y z6@zi^6aKod&VsGD(2KZzd5MqT*dSJt-}{dr^7LSa43r-;ywHRTc7?3>Z9KS8@2h9% ztv0n9ky{#4o~^5TCTUNPQ4%lXDo_fF>fF4NE?HK!w6o{>E6(O-y39l%K=eF46@I;*4g9 z^{Og<%&qg?aC@Q)=;TM1`I%^kM1pa_rS|Dq7`QXR7>|(Gdsr<~SOYzH%BbZ`+`=0m z0tizvKR%|+3c4%Hh&aYSN*FM!UqrS^}joN@0<{x!(AF$EBp&7>ucqSVAcf*_7$=0kYAexv~b8X0pGH zl_Aa53!nn${Oz~!x)S7i-hATdfh}#^C@!Sv&jbd2Z-=C+G>t%T`}!JXo;#nA%5d${ zGGBT737`M;4H}{3$@UQ!H@i-2c`vgG(k+Q6{Lq@Zb zNp2REJ7F||w6t0YRb?DY!ONam>l8*Y#(`0onpR9cpV?|YLs%h%v^Gv7;$~0erB7mv z@nSsn96D>17t%3N0wvJKpbZ3J=qwg0voJcuIJSz?6XfiW&DFO3jbD62yn1n9ZuKm~ybg3xO4Nx%o;;IKLVNDo{jm z3wD5ds3Gd;ppFoWd@Gp<1imZOCUwkh|>J-~LRl zQ7wd%rjtQ{HHJ8Hw5<9cIN-u9yw>U#>B@DsAH2(C|DkiVwHljEQArnFmgp?QRwbs$ z>Gt|;t@oIhh6^ig`b%BDb#E6b4Yf3|kTw6)D>i}Opqw0`^AZt@Lo5uPs>c5A0gYnB zN|dqx^4pv|e8T0Azs8ld*BKTtKRKo)BC4Z(2t$l@{wy1JR;h*q?tS&^Z1!X9ctW;) z$WEeAmo8F@7`85Od3BTb2743+;${ogYB>`k;bjHuK+~h{ixlJ>?MeV;RxqE;Nm?mV z#YijtVd-fO9+}srt9(eMXs#@SfXV(o4WS9bfXXq(eC6d_;;@)^AFXmg4RC&6(r_-> zSOnYWlZ5)~ANE@Rz$E1St5|D*r{hsJAuhQxES?c#}m4-s= z3W4xu=mwN@GRg~cHjk#+dYs&65*~RKxOrv;AEluQpCIC5KI?#G-ddlVXF8e11qj`x6{C#^gksxH2!Om&PgW-TI*93tgN)*!XDM|?ntB|2$X=#}$ zA-g+Ms!F>mfHy|7MlALm6$n<=HmHo{FtZ#DGo%bb80I5~?#f;pq@=WhZl{Y-5|gxe zIV_lEhTyzOC=P@W2%<)dQfo4maCBNaKD$y2jR&a&NT>`fcbjb9y2zx0Cxbcjydn+* zH^jy|vo;F|NtRb6QNZye=erLN*gMVrUUK$ag%1>K`d+;s2?Sb*1)}V8XkW>6y?bs_ zICR+>!z-7TI2p}pHX@pFK);>vy+?;^EH}A%xzD?g2Rz`8J?m*v zQh{~Ki1;<>sy{9%j2Il7n=`YOlz&j<8(qd*)rh|P{qd~f~g2{6x2YX1VXe_UxeIJ_J9_<3u zLO4nrb;Y+nH(ic{$2y>{j?}UO{#lmV^6>dFWmyn}0cjjED-W5Mmal$qo1%0L{ky}G z$-LlbIOFXH2i)4~Bg2^eY02|hOcky&tYV63g-H86*cr2ZFeGYq5kgR&46tS4DdgR6Kn0l!t>UQ{6%fA8%g=R2x1Ux`k$Nt&kY@9q%wk)57&s2*E5XiIWf^BzaLS(7CLr2+*uFG zCVO04{Uo1#b%REKgL{YY?I%N;jf5bH+`VZ-WnePT`PlU}K6!nKum1HHdH4RGbM^Jt z`IS%oEGq4Dm?`!qa{}ws%ktwxM41tE`&1}`IHbAcHrcwQZ9QUFiwZ0PeSt%T!9O+O zS!G^PO8{lg^zaCzq`9($RFdh@5jxLlURWWBBcu|39+~rx(kG#3spf)u#o5o#|Ezxg zod3BvcfUX4`iB}6+B*6dNQY<&Kedf;<#?y4Fb2z2mvZky!q-SHrBeFOmot9 zm#^R7WiXth0>?cs=W~ccj1YY6`Z_=T={uB_;c$}k-t!S3z8qq$15l)Oy%1VkHrKj* z;d6IswHusF3m)yw`09K64lNgT<-q+n4i#VcnOpSwEs`YUn-7op`u)8{kckB=T`xo$ zhy2tVSJ_x@(djhVnUws=SD!J-ss+GPKejSA^wztqEVa3|+GeBQKZX6Vs|DeD~fnWDroKC9kY6Gu$zJ_GX`_FOFz718%H0c>I3Jvz;BH zP%RAI&d_`74Bfm|xWZtCM0+qs8sm+sty@O8W@q>B&sP`ydNOB)ZCwX&9>9|x2&nfR zSItysXIXtRTDOkeld0*I?krMqLUVbEX20uX-#wMmc#y6J;G8E^fQl2O?IW!ww62Fh zdOs{oMLrp$i-N}TGBR*Ut~s~N0jipo>py=@!>T9a8O9-yWx;HCL=Y!5R#q{2&S-BB z5d_4`8;{&iJ(~vD(v1YvBPQKp4>Ovqo_Uz-;c+=Zd^y zGB4R1ObEk(X9pvcQb-l@;m#PWB@83pdokj@=R=naBM6ivh*Iu7+M^ha2wQDbr%Sh; zu-r^JIZ=$YrW_waHDi9bOT4s>YP5XvB&n*38`qb)wAw(Lk~crbyPkX`;3(OFhwPw}|72Gzr<>-XojM2?IBWgc4Rtr?nNxfV#D-(gtlT zaU7vUWgE(ftIN=|Q=~C;(g4v~#@H1m;}d%{9x$5hiDnvdadnf;&5Pn-=b1e?d<5YO zE=FyPOt2OrrJ~+)XTwl1wI!$U^JU(;DyC)~IRB4skm2(@#5*OgP$>9s-{NkB0^wg@T0q)k=i zobEnmWAifo#zl5UxtAsmP-)C~G$NIfpxvXC4rQ#5KC91-@A(r6XC4+r-aL%6s)M!G zp?+n->}UW&&{|t@N@E8{R9Q}Ibp@F^^&N@vuC5LXJ)eV|zdrJ;|Bku*18P}+p9;s{ z@;g7QPecf()3b>DZH;Uy;hcIG{IQR|mj6o%B`gwcEP)DWw_3~sX@#u>_5AiUD}XXD z$i~hyBkiG6H@PJf7Zis{yEm@+qp6QzMn0Uk$N3_F7lc8 z$r%Q4eoe-4$o~E@fBYXt+`e;-QEqv5I74;1Byr%Brv!*Fz~+L=S{}bRjI)x!o6}k8W=Fe~@bMcPOpA*9kM`NxTp?7Fxxe=_dY&N)6>G~aj*d>*Kb`Wa zjV031QH&IVsw~N;Q!puEpy;$x-uvJgyT?7X+s#5CVRfm&>2N}~qxj^FK1vFbt9`zDZwG4(SymDWgRM&T4o+zGx?m~>!wI*q zEYl1NM46FKbHX?xYBUxSsR9>F1-=KVC`zibB8)e9@kr_+zj9ZsCn4C_z z-CJTft9UkXy#D+J;DYd zmBk~~9$l&DuXISiz`(G*Xw$hGWXyHLEWWG5}*-FP+8Fhd4)F#<`q3;!=G! z$OWpsKzM8oAk-;`dmb*S&{$FXGQoVF6BZ?{UXv(I2$I+*cODR^WoP|!)mCCF*DHhc zRhW8v6qX=~nI0Z6Iou~*UPS~UQk%tcw|Y^cLHl{_#>@e9DhM1^3X7dhn9s(jI3n#X zVX~a!_<;4*E@j$tb3wRqIv9+QQnIny;dC@5&nqvJUsKau@}Z<~ROSU1=&Bt~$xnh8 z>af25=xj}Ss*-dvxnZb$pPTcus;jzE39NNAu6hr1{h-cyJqQ$0pt!KsB@6?~yd-b6 zKva~c11NLyqdn54HDubvN{h6H!{ZUfW}DNK89Uqi1m%PcyJM56&7F_kV5#2`VW5bG zw-S*8REU(4*!NT^U(E^vK_HwIuLFN7VoKh)w#3y7ead3S$>0Gtk5Cnl;ZpRpNfvU<87@{yhs))|*SFtx<5!i}2j<7;8pU)T^?Xy>wsJI=hFLhIX zOs}6LAVAVcM$+0T_(fP5T${4r%+8_A));hEEgF@xJag0oDJhGBEOXuhHNV`&Exu6; z=Tl&7#N%A@QKNL=4uTpLUjVPtZR*BrYWrVw0gA1KL4EMNpgRQ!At}qkIk;PcE=#O2 zR8@hAL&oC~t=WvV&CBe(e2%V4fL99!ks%2g|-lPOQ1?4YZXx8A%(x0Ukc z@9m&OfK;Kodmm};?wv5$Y`aax!0zEGcdzuAOmmVTLP?KQT0N@!+B$0!AjZkIWNfg!NS{DPT03 z@N)Nym@x5Z_PMEz+b63E^1NhgqsP;oV;bF@c~*jORna0VFjYm|h!@Y^ z7(-c>NMW5JDt-+MLlgvj?)6RHzW0pjcuF>(d!#a?$}&oA**iGq?zLs+(>aHOA=j_0 zF`A4y9iB26PPzYRpYdo$mK9FwTm>KlR3I0g2+I4|Xl<#A(mS9#bIo2mVXYMr=0iH> z1g(dpag)YUlkSyUOdEZk9PRV`Xv(cy7x|@bhYL$7%dLn_E6GM<%;_lzx0bB2 zAIXjCd$U#L=!Ur9xTcB8G$mc?(_CF|(PZ~fF8eDA?7>#I$A?G#}xyD#>*dToQZK5>=* z@TGfXWrbDNJBCB8bZM*tPh++?Q4NWuvKFmNkOqR#QFyKQ)=+0_s^06g0c)HWhLFA* z=g+SNRS~=**qKDP&gPJ&9G^^CS!y{TQd`1C7Z8-gA?TcJuuI%uhejJE1-nNh{^GBX ztey--cCydsZa2Ao)riYCH~EF1f6FxD040S8>OMQ)nV6Z+_tm@xwp;)0`i(>n8~a z5KvZ0V42s{3*Q4Gr9_32vUHUNB_$$oL5;Ca(aIRNo~00!+G)DGvZ=0Xv+lArXTAQ? zcy4XIYc6myYI7`E3;KH?X3_ZWzdl#FUX;UYV9BWkNtAN(iDji1n<}QH?k$;2rxe=Q zTX$a-58i*5(eb_;0HCdMCi#FoYqGbyPgPZDTk?GOgmN~g+isznZO6OyWnAgY=Y`Q+ zy4WL)10Fm(;`X(5;zo+rn&D_loP>nZQ2>M#y#4NTF7#agiE6A;R0g9o;aV3XEE8k+ z-isM8Pv*#`L&5Xo15BQiSFRCr{mNC!tu4x-Mjp(#xRh{pEx`ywdwH4X2NQyo4bo1* z?BIZ=&1m;Jj89GhL)7b2Saq)AB&hY)sgXOkoh&>}78C*NNA=H8wU55u;&uL(Bt?jt zZ1$0A$Vcu}N-3;$0gdpJ*3;3fSWvOf5&;#s!=}=%@@0%O&UBn_N3pWPC*4vI#1V0~ z<7q8!?bKoiE&=zyuOx9ZK}7*!96H|*To6+yAGO|9UEL^)5`-X#!o?xyPYkTJ=)&Eb z3e-oGm1<6WKABO?Ga5@hRFpa|1_VK%xVYA4R5=Qt1V>--IIj_SuCqfftFq+F-+aWa zYwK)nEc1B(1;#ow+T~+{PN%_zl@3BG8gYQBDxy#^&n<4uYiVt0^!r@BvIa&o9hWF; z=rlv}p=;<4!;mO(Ab`y!w{BeE+NBkqzC1z+Na6@XhOn+zpvG0LwOrm>rkREe#syFI zCTy%P6Dr}1&V+Pw!~%@bT)eQvXWqC@bX|xUR9_dbbS**7=?t9@}g{-AW~F8%Duga z`AI!2`iS?J9IC{bQ4L`XmJ10Axo<>HkO+_cs5|rZxS{dy#4Tq@4Xz83QIE* zymotwd(ThN*4OhFp%#lXDR`q z9|{(Ux)g#y30HOSK{eF9K_ETFS9%8}v3MpvX!iG~@qKziBCCwi(SWL`2pg%Zs$fC7 z=jf#CjoX{8cI!uK59ay)$|@%xonWkX=77sRM?!O>eS^;YbRY)9%OsAQXZ7=O& zkG0yO0*Mfoe0)MS91x}{NxO?E3Nafx+54ok1lE$zW=P%S_;7%f0c*XKPriDQRvgf6 zrJSBlFuDTcq??7Yq)CF&hN`U4#t;OGZmZ3Fnqjb%zB%2R$_2K5&&9Y#`nn2fEC}Np zzJ>FoK}y#_Qu}gw;8IwNPy&&p=3zR#GV}QBZ`Cc=WxA@Xy#dhR7!Jpfpu`|ULn_2z(CA4oe4rxqs0jTDjF4WW zCsLu1VT>3dLyE+3W-!nYKw}y`-P5kxlsC7ocgN>Rv-j4+-kIlCqcKD3kw8WORdxH^ zbMj>7UVE)?ee3&Ibin?0pYQz5zs$FP`B#bJ$eOYc(kUfm zD9l5eql5_O?SV-p0!`AoAkHH~VOA+iqsk@q!oeoA*vxlEm6vwe+dC1m_k+bC=oV~!qaFdtszUN zm?(xorJ5tJKJ}=(DFHgF+n)GEGVgi>UaPB=Ond@U0p>wOLD<0F=rd)&Ua&E5MuG}qP;NsBad7#(qt!DuH(2*;<} zdrZ<2BNQ@e(p+C>y1z?HWGpQ881@I?K!uqQ0l@^xC-9Y=UromfH$dRf0$es@a(E0% z(pg_aAQ&AUQ_eEli;L)}fh((7k}!-a!PpXO%%7=zd%BzO)q7sQ#=nqiUg+6};?FpK z2K_2@Hbh0^gCIxjaO#u+f(R9~s0m~O@Esu=HWBJG_kSoUh@zM{ZV*K=LP!Rqk*5Px z-yu*2lvJoh5k(P%SsY&=hVP5N2i4CTjfki_?`S($T|ZlIpy914@`ChagtL~`+7fXR zpSr(({S|r6Y?Kl;Vp_d6T8p_KPZ=lx03ZNKL_t&vjtE6)r0e7f=g>+pouu4;xXZ=o z&XXC(M|TgHW@VtNP_Iv|C8J5o{mnzx*A_r3?raU&JDJu4)z$VGMUrWn@pR{yH(tI- zuh-$}@e?3NI7g9}lv#$2|+eVQ4$*6mM_+nW_xeI;mL?^zxq6bsqxaJrv`#6w6!b?cJ>E6+&tvw3l~^g z>hh;|4sij2bXCD8yy@R$nsevj9_KEsaqZ$V4|d16FmP)_LLwqbBi0n9;gg3)Xss|N zFgbiaMUr?VQ&h22K%^B~#Xk3T7U89j0x;u~iFPxhkto`-;L{)eK7-vSbcLuG`RqLv z>~9}19nN_0Gy!J>Hs^4>L8Fl%%N*@WFN_c+T)K9HR7E^G&WYO{wARFpgw**VDivrU zomlbmn=kOEw-lT^M>ZRiaH*Yuvc7#NEe-eEQ{6Y?+6B)!#=U9C~y@ zdVD}Sn+AvSMY6*^vV%>c-U=>JxYB?vk)>Bts+936*K#u(k)0fnG&>~SF1DC4JJ|=R zY4(;VvJ{(7dE@4JrfJG}H008y3k>%6nC@@0sMk2x6YM?B$&JI{nHSOt);e8A;|ZfQ z^<5ZKFdhy7Fh%K~UsnPe9aQp!)ZseVkTm-|MG8?DA08+Qiy{ava7w<}mWHI$MV2}F z$v(^`q-Boots;^}NZ=i13A)+BnPsN?J1lk_zwzcJGGlq~o!eq|azvwG+X5`;*@|0&w^`JWnIam&jW7Qg@i-| zbKr_bB?5Zuw>=+3OaKd%k~mk{9fbX<@&-DU8`Pg2;@Y!2wZPiq)V>rt>o^@Lxlly1 z!O!9Givk1?Dk@OIIOi9x2-3C!LE#4&P)eb6RJGL*!s}gIQ*loH(`~FnR=VYN@_e*|pBro42DHe65DNtIZ<(cQsGwobwz>R~H`v*>E1!s*+p3c?cZdF;^+c zLa$4!(Zr(Aoh9t?J_^CPGb=16nS1%>c~1I6@yDBc=+$ff%!NQ`1wtdVrlR``XX*ke z(u!LT4*25k7EJmKyD_Fn+1fhd=wOXUoBK=)PX(DxCR|>Lxpw&skG2juIvP^UQe>-# zQV=CELV8}Rl8}#voJ|btZ(if5KV@%oo8^la(d`ZgCo`58nzUOnhy5v9ORRy(vg=;uHIuCWSya|NPiGv*y{DRlWLDf$+2Hls|9S{HNxI{+z<(t8*XW zcj|eNN;YABR?h}o|J!O_WpaXKSXnr#+KeAlbj1;=~uC>Lg> zf;!DJYfX7IDc|jyBVkp+*K9X&?G{QaPXlp=A}_ggag8@`Uf{t_pY_!)Z@+Yg?|<-= z)HsxI!Q4(#I%qbV+_-Xv!6f6bKjy-@H5R%FyC>7S10s}WXK%>8CkL!7cZuSNr$crfA7qg{+{l1);Yy$(^3@>djw!6; z(awNzTKIVdU-{s|IZGkA`)Hq~r4CEW3*?32!B(Hr7-SrZ3g@s^;!tFzWA|vtorin$ zGspECAzhI3xJc-pmPocwCfwaTc<>+yrmGyNN&Ywft7NeOVH}PvI=FhS$I&q5Pj4U4YDgBEnvIn>UmmrM|0z4W1=9g!P^q9+M8r ziLO%U5-8=MEEpa4eXi^blY;|HUeH}%Lqth1!L>ng(NS8!uOIUHcd3&^NJVrR^zBW!j^8FwiIuwu#_DQt*Apqv9? zDW@YE&XMRY_V5rhn;`Ryq}@Xdj>*fMFMs@y^XJd9wY}>lX6-H~4k(D~P2_7}cm_BB4VCURBJ` zhE{72EY2%fhIQkdMJR>tEn>=&qQ8$UGm8EmdSMk*6beuWPN0$&qS>O^kmRFd_VDqgNFsb&kiW;s^Q6@0>n_Q1u==-%ldIdD<59*`^XJ z`8hp)QGfu;>x)G@ie@Kazm2uVNQ)^9#u}vX{sl@Y@*+q`RwhPxHH!*q)zZ&{)WnnU z>{qg`)!GdnJ~#()pnqg}MkRCTP423}bAyyRRNkj%Q>YN}ssNZ*;SNwygjUL{c{#kl z2*Gqucoh2V>N1O+riitq(dmUMrQo%jmswfBC3LUJ zj4!%`2=cm8ky}Xn1HSXhS^kT^^%t3@DZl$~KjL?O_XAE&rbw;*5;hrs>+k#ufBP@L z#r@qr|MCw%_h9?D(Wd%{Ma_u8$Ogq!|;%8bOtC z*55K9#-XqhKJhH9qcDz0DHgg-meYcTRzkPaCXO|eX^ukrWEz1rjwn)eIt`rm;rQHA zgH9vDT0s;{3#~CME_AqYF~V1=iVxlS7$Ng9#ln=fuqOhyck z4p}*~&cafc-F`t)SafNTkw93BR+=|oy1>rifbD}Z7cQ=I?Oc!D<0%%0iZtM9Hl;OO z-dN)NT941~Z6TwGm8BNq;V~vJQPJGDqO@@4>=HMxo~1B?T*NGO5*m?WFfBY?DqKx# zEsF~sUU}g>N-HM0VY!`f(kj>+%mTG@j(XN|*_9eyc%H2QQC(XVk_7AHQ&E&YX%0iT zFI`;V%u)l1BRvE?*=2OJ%isU2zrpgti~N(lPkHy+T8+AFJ7LL@FA`BfL8 z;+s2XG1l_yzw|Bs_TT*n{K<#6_{n?kyN&bbL}oSL_~t7J8S&44_dRYu++sRjCbN#! z2c-@#45?P)_aoVB|`fd83A7DO29Oo zK@`zQV$^U{D@7GqMyuDY=Phdk(JH<Nr^EfO86d_44o9e*9Q=zzlX5at2zmR>+jW` zMF%I2{W~_)t%^T=@Nqp$bJF*qlu{BYq2cD9Aot0nV%;nhN0PY(%(u0zrm{*ch<{}}VDZGzIdv%?$vlJ%>P|TPe?GkmD5J>_~ zP?p~RNW~3Q>^M0-W;h&qx;Ks@FPtq)^1=vD0kgewNA}if!pZB`Lf)svq9>z>mY#YZXrKj{+%eozKk+m9K(q)m}%vM}6Hs zSiMH;(9yAiMv{=J95)(Nok;g{+5X@c1qc9_msau*8jWG~kSXC6U5xOEgI3y`)Y#Iy zwuT2*N>7onMUHhg=vyn#jja*5(>YjZe^$sGezP>jFW5>;yF$^bqQQ4VWEj4x@PcZ1 zFyw(^-bSrZTpbb`A*nUJgs7Z!ePN}PMk)oiWVzQNTU}**xXCP?&}pBc)lA&_LgqRN zVq8sVJBP)iK{`lV0ysh7RLdG6j+LUrnDr#3wcKIv#Y=qe;~gflg^aZSj%LPWnj-TN zFRW^Mj9qMVVV(2lRMIPV$dKe^*_8hNCadvFM5{4hoJrgt-5ZGM?wFfb&vN(4A-(68 zSZ^!JH0A6S65MuBn(rE+9a={ z_FzvTEY6-PC#$FBD@8)p#Rz}@spD(98xCsPKpkpNzt6wtak?uagb>bE7H{>>=BHnu zwgX4qIkC>sTUcayWu3#r15a@*OB&4vh+!B)7j?j&Z$1H?16s|9W~_MO(h?x}`2GQd zQI0c)o!w*FjffX7^oXTFD@RhcxPN3Aj>agw$_scDJ&I*bTdSVgs;aKe!zV~$etW__ zovYN%(KwTPfr`zi$MEJAUb}vlTle>Q_sav)(xNMeb$n+>X~}3ZV>HQl>Bc$kZyxi# z_a3l+k`rrDQ^K6JtgS6_@$3>i`+edh;_OnBhL#M4M?;gu&lOnfXf_m=*SkF2oZ(c= znbjVvOMQ-KDN(bH($Xh_(wo?2S;=pG`vs?FCT{=jgWbW5qJ-J32mno0zj_MEbUZ~_%dday zdG-fWvcfS=bAR`3Rr6MJBS9WjhR#@c=B;ocF%5zp;m(%UF`Ld1Kzp%6EFEuOTjV!h zTI14cmy_cSSI#ElNALVwUcK1j%{SlV-5*@z-FM%?*^)-orrBuX2NQW~Plusm0VJM9wZpAef*$EFy+~3@1|9DwkSWLL}=zzPAcEOaGJf#)G zixU~?IiE49)=B%@NLv~~QmCd7jf z4lA0Er}Vn|vq04H#1(b1x+elo(T!vsV@hLi)?lQdEc^>au&{H*1UK42me;YOfz+xt ze-yzm5D}EXoS_+t>MSoj9n<+|q{wqFpYPFbCp|~$D!Xm^i%B;X- z8Me$QVojD84}H(lb;d1y!e0D4%Nu8RrTO7F08~^-kc=siKF8`Om5}OR2y*IkiVu z>&c(C3sKWkE&a@&H>ge;F@r(B-g|ytk6#oZz^u_K^V)jQYk!+ysHbY`kEAq}R(BYR zI>nDyQlNw;N@8C$grHLohXej$uNc?<-%iX`tCaEyxf9QF7loK7kusnfFfT%+lBm#n ztP)ir{rrkCCMZG#6^u|6iK3v#w}RJMX?vUSx=76HEz0P~LkZ9FG}{Q-snyIZFNP)v1llI&j9)YsEB^h`SH=kWs|uVagZaGq~}Fe=#}O!<{>-{kJYJ^tX2KIV8Tkj;hK08|BVW0;oQeR|AmH_oxY)Zv3q z9<%vmpGJELt0RvSI#1OsZNa_Adwl!#=h#0P^P^8T*&SDf&zv?Ym6z;%ynV#4ymgIV zdh2<<_x>ZEoD`JScPC5Zh@2NBz`@bsko}_}7tXJ6=gBdT_oqyYpmr7#F%c5INt&^_ zbIi(0mz~`cK7MdW>SBcQ-Cw_c0!CaF(biICCB_(Z9C;(vQ1DAz6_@^d%BWI;@@c_% zRxp{Q47BAZAABTkefkOa@7?9|JC9iT7vJTFKlS#<)_@f|Cm`R#Pc^^8;5CE=Tn~lVGX0zE6&KdHP16-Mt_m9vWgOCwYDNJ5s@)GA7LFviII2GuR z);bgttrTS$%z~h%-POH?I)AAfbHVleR1OuYlWHAT0leOO!q2R;!3&7sHRAIq9mV1I zf()^BIBbY@CWyj>LZ%wt4>^c6hP*5=Wm&7B6-AD54(FsdI4laRHRSm$C^8Z}to(f~ ziy5=YfOfm|Go+oRi$4aA<4GcjL~?+Y*xCxgG1i?(f=z3lL*~j@r&QVY;r)}ehz1T$$fd} zzBoMG6Smd!0l<`gs4@=@wo2lr$INDuX_|9MF!r5iEHXm|vL6fH` z{lSEb=axC_Px<1(Avc$VxOjGv4?ex^4)zaGopabc#Yus-1x4u?q(*#xZ_EAgkN<=; zZ4xiSt5=t~y3ys)rA5-ba`7i@Zl4lJlw?;CGC|JRI`CC3(C?L zXoOAKXrPEPkJe)_0~qk+?Ot2r0%Yv@^Dece~PDB>#}x_{3?L<%Wg zy%W^u85%D&#wEPYdiV#9q9_;)N3>f_dfhh8S;qY%T`RI~;L& zz0H?*wuzF6=E5R4Ux-^%a{umQrj4mM+}k8pj*C}bpm+5QaiqvbBQTO^aVdabvfdo3 z?xCwbEUZ7Owdbdo{kN#3=tNlC;d<&u1CvhZc3WY6DK0IwdGYcxcb*P|8dJCy!EDD_ zLz!i$IA*!m;MEs4`0(~VX<>Z#FT{YAl^#+`o<7|tD=km<#}q=*Xm;zhSkV_c4bA#e zo2R?SSOZ&!Bc^FVt5?Y!`&eP6M8z@Jubkn@ZlA2QI24mKCDKvlMH(I-i*=F<8!Jqw z8I!D_(M(7W3X)cWj=YPp2<;b4Ll3&-#-boHtQ@xX(DSWY>6#15DCteAQa9xj8j2{&#Qw;seLC>`=Z{@1^MqE zMT(vM5yyj+vh=j2sJnz9UYKoIdP;Zt)tWHxrL=w zfl$P8#Bu+G(P+YGFu)k=q>hBv39VKW5j7}_jPzuW!Qr;}*4y9Y8{hs*)(M$qy7)x_ z^7DGUd1I~o-DYz<(h8Wno!5x61(ZMv<>^@hEEeH>P$@DIT5=IuMWG_EHf@KK6|<9i z_|gZHP@Du`2oZSi0QQ$M+Tb{|gp?!Wq%;!pncQ%?5Bw6DLw zARW{0G*CsK{Re+aqCqIogFX7H!}~vZhtIya$KKP2{NP{xALyh-f0WYdEwgg%EuIbp zUpzPfXPNCi=J0&ZczlVyttVo%c?Z34>PZp>2Zx8^(UT{*#wFG|lJhG~ ze)92SUcR=@gQpX+Ny=Y*>oVt7I_&gQ(!rQ4&FGz3M>d)@qBrdi5K7VNc96>Fv?gpS z)_FxDtLn1yXSYAX;rGU8gYJCao6~jbqT?%_5dX)|=#Gd#=i}?$;n}W<2=8N^b3#fX zJvHm6e%%4q8fTp%Nn)Y2_l#LsSRl&_j*m~kbbPBkC?v^K31`(VcfcgG91b&*R)hXH zLw7vCJ1^llh4=p8U0yn$u(H@Bn-2K?``=~x>K@O%^=mX1mKgQN#N8f3X^;E)lk@VS zb#V}q0E8F#GpIcP03ZNKL_t)Eao{StBO=f$-24)UE~Qoy-Avd&p76aNedz}t8!bqh zK8Xr|gtZp!N^}%49A|w0ozH2mu2HJkJC0X#DgI=FYMt+F&T_-$wKi|Oc%Bcw^dbtC z45zD$8bLbEkT$2&jCl3N2JcSuI%%p~|IRy18zkjyO0U`A+c(!a>ObTpFA-5xgAN`w zj3`lLvy?~I%9w?vF9)*RY+DPS=u z%A|*GE<)Uf?vm51XT`K|WJO7%5u=49YBf<>Q;f%y`HbU1#@12Fm5a+raa6*m+VUao}vx;V?$A$A}`Q{62Y(L%R$;k=V&t9g{UF6Qzkd3t-SI#Z6 zvC?95JLcf&4#t5NmE@|Rq5%s8P7+KMmA^*9J7+s%DKblGN^F@UgrzhEyW87fix9U! zh&U9?0l*0Hxk_NGB-jDMI?5vV6eckzpIU2i#syj8`7phdf>}EAGbGBNe;mhkx7C#M z*|sVkn;=hZD~}0R6*#W$7U29$n2r>2BcUuxoWm=SNd=}rXj69&iXumbXIBVO`=NM5 z-Xs2%e7>`I?;)i~vl3&=&R`$oH#`QDQBF>frUSObTJLS+f)s9~N`$aTQE>C> zS&nw@^Sj^ufB5Tv^FO1R#HTuueow6CYMiz8jEoKUK%Qb*Aq67PF;BAsPG3h4ylSi~ zLq|i`!BhD`wp#k7i*mxr!(@x35y^KMoLBLStAyS6_RGF>pBaoI4Kzw zZ6Q^Mg;pD>6wS4D(OX%;I_H!WbfQIMH>1%TlVua6ki?Oq5o?@`oRT0`mdGw#6ssGT za6(xpoJ*%awPpTX9KR?)fNX8ewVRQV;o&|#JfxJunm~~f(r<2rfiuaR+b2DOBExEt z+7}hpcn9zr4GDp(O5#-bplWldkZ7fp7v&3ym)~!zgoIkbWFqc8##^t^X*WfhPF!jtR@OJf3opKoRZZUe z;0{7sq%v5m$kQ1@D|8YCUbID&GtB6S^(7d_@Vy_ri&h%rpc6@8hyeLO2EWn@Qx*_A zws*GpUw-Ei`7CGo;&s|B&Ed(APFK_BfMNd&nho#lnh3|<_6h&wpZ?E)qT6hc_78E+ zAgpCL+-G^?IihHt{%FR<<%CQe^T&Vq0lRnJXKVL>)^v!NZB~hlh@E9J)%??c`cIgp zQ_}u~Yj1y>oRTunS?so0TWqtpcg%1w{N$?(|-@Q{B-By)bUI=1D*-S&&+$A>V$krXjXFj@i9lk8OO&nO5LKfu)z6?XP6ES`QYORJRaX+t8oJtx6pd( z6J-$`$q@mSKedrPlNeBI_j(yis3f~#E@>*Hm#)P z8XDa$hlfLKdzq-y#o0g;l>(t7w)PMC*FX4zJTEY<9-_VIm4CFr1=6b@_7!BMfQ5g8}VshtV{nz19uJYSiexe`bA>*XlG7I7+CgXwLXGF{i)=sw;k$00*5|qgxVF z6wHps6ytrA8S?VAOO)&1;K4^D#z$LN=Yqtm^hsV>f&is8iBin6j6BPHQ5ku!4}niY zSJuz+Ti^O+w)c*>b^CLA@*=BU!-cEQbI_l0fAbI($6Q%nr8s`d$?eZsS!hyh?J;?} z59$R{&bz%V5!ar-!nx%ZiGoB6vRTT(;gI!SgQbS#+(N>`y%Ecu2ve4Nr5dr;8gn; z;guHCG$YUR006=)%Sh9dcDqd+$6+5fVNaH!kab|nn#JI$-h$G4iV#8upD;^VdRkQ! z$DyDBTNccw6I`i~u5d`n#q%4&I>FZ7k<)QYh`8k?k$tbg7g%A&Q~=URKW`H{4c2-p znzIg-v@nevJ2{3Tr7Sa?P>5CsgkUzyz!peyT$ZC8T)A|f$-!fO_``Sj&VT$j=(JkC z14QW9hIL!n5O`3iy5{u+V7DP>^yv_tT>%17F4f+Ze zbEbT z^Z?;06khty%cq%8p(`yZOH1KQK-x4~Yn1j}Xy3Y@CuIKFdsc1DC%-Nvg;m=Xs)05g zMNpP?0a3x^QqGa#D!A1TxSJ1WY84@b^W4yI)F_R$7-LD(8G1c(jYdN>8wn>z`|f}G zAOE>{_njZ|cmLksb9)DUaes4%ymX9?576ypub=Nip&S@L85i7LoSsf&qF}P?<-O}kEmo*oQZL^L^(^O0{tzt$HRDrkQA9u6Ci7!aDf!-ecdYj+!)M&ECnBL4U$u zeDxfY;fON}4Vv9HKl<j z_8ADL(q?}K)%jWUsITjGglDDdiU=WUzXkU*-s{h*J-+TUzfRisnIh*aZ&%R{gcOWM z6O4sOM>rg_S&k5qO`1(Vt%t?AuP75bFIQb!xW7AQbKe)6zxw87HV+R#LZcBuVHxEm zMV2!dr;JB4W`&{AO=z_nq{FfvQmkgQs=}haKw|z~PHWMNAl>Wggn@8BD*}|iccrmt z?O0jt&|Y0-W(Cu{#JG7^!+Yff`W4Vw=(4ohMZ^i?X~}q+1-6$BN_YuAY$^ThpFwm7YtN}F%#LNrwT5fU8mdY^0Z%&of^J%&Y^;b(Kt7>TWv00SV1-t22;a9 zKLrAc911$+1i5jvyFD(gcjz=D4u?4hS@0w|^@vs6?C`kZgk+jkCSrkaU%%43qi2&0 ziKWqQBQbpI#u6`Yw79mh%4{+wpY*x&#V!8QFMpGpFTB7%{>PSo_P_nFRDvT?$>0s( zX*SJf3l;oQCZjPricw0F7a7L-LGAzauYZUC>L2|>{`kH3-AA8&$<@nO#W>B}+uwLi z=(xdu{onp`-n+HQtiQtGu+LJ%@mt?~p7-U1dmns{*MIXGH(yv1k4KtGEIG<7(`m+j z;ZgP1Z=PrOaL90!q9RQ*R_q?lSYPg-v|^Oz;h~l__*8>d;d)BoxieiZEnMN=&Vc*7 z6OKnSrn7W&3wIzUP2bQYLRQ)b5_v`G>DEtWeSmd>1Gp$+>|qmq_)y{6hv=flRH z@e`EXoDDU)MCmvvVEV3sbzXA65<74q_?yBoo6QhH(Cv1SN};u;S(fBk#&kMG2tl00 z^{iAG%ub~gel${g1I?=FQbJ;+f1)dp(>eU?Q=qIGW4O4n#^twe^5D@HJC7fVm6c`Q zymSL070YrWZf~A|jzD;NWfd=+HGWP?2tN~2nh+xd7$2vEwYbuOZsOt=qywaxxw0sP z>}s58F&XxeZiXboWmA-j5l%8nOY(e9X;am;79gqCm8}}Bp}_lTT7Z}4t>%8htgaCC zJno#j>tnQ5s*V+tG;=C$J1w<19;OUNDbwkcEX%N_^z$7>K}%b%U0mbh#SIph*Tr)e zFZo%QAp7j)w*9fAr1L2i3DnlE8R2yg5d@CgM znOERx6{iNeLbg-;dz8k6MXKtgR|o#f{Q>t*9-xy0go;qk7iB^?Y!soQIB4ZNCP&9)M@O{V zO^6ynGFAE@R-wj0Wu)4mymExZDCrTPVg^EEttHEiS8|a)aks{J3Y_$`jMM0-&p<4u z%$G*`8;14<*c7bXty532_idF|*l> zPd@pC)zxKMt+tR#qO=AbiCPUtKKs`7Gc912TdrMRLQBW2DA_z1Q|1}H7F@a5;-mX* zmX~`(qNLr7dHLpbWbZuJZmjYB4>p;Y%Ft8bN<*GzfFo+eR6-5@t9eR9dNM=`Xf7`x z)SM3>g`hB&BAubMCT=!xLQ>`hFW$JojZ2HjVocmf*qS!@$=zd$K-2NVGm<l#lr!-|8UGC zGc~|r9bgTwzHpxF%g|*;x3kLb7=Czf!qKGg!?Oa)K=HVIewkl+>k5;jZG;=qyKtWO zpD4cE8sXKzJg41Q$Ld0ZUwXbrk{!`)M5v_4$NP>CAB`vr>jzuKT!E}|K9^NzS)LX{ z@c-umWhKuGq_xCNPuW{;!kM_>m#=gARG1z&)bhSe^9s2u>s1f+m7^H;B zWXf!og=fWLokQ#B8AKf%qmx4(Ke)^GllvkmM{Y66Ik(i|{DMX+$8u~a^AhI-C4$Ll zLVCPQF&$xu=#MjEX*s(P^TY_!-0)y~z<8W;{mL0u76fOOI_&pT?rjg~HDey^4rzDV ze0cYmQCfHzQhx*I7(rN>#yA?WDT9va6(^C<_F#jsbqSJmT7O8{FF&a@e0BrenVG(p45ZJ!Ve| zCX*jzxRFae0hi8{*AxEFTed3m#$plCqMonf50&}UwNH-ckl52pS*{yq=2hRfPouN&TuvMhaZZXLh!%~$wG|K;D|ou7QbcYm+ot=C@Uul?1( zLbKW8lh5z*-~4yK!->gpG^uFX&R80WrqgYb&dM+Y>(9xS1&xNH)mUJ7)c2}p&LESP zpRY;#!j(BLn;_f*`D}u-If<4?=jFiL?H0XmkHeEOrt(qa^q%LhH3-za*Wu~ozR}>< zHLi9R7xj!@H9vd0R1x+6q>5_r2;u3O<4NX~7aL71k~nEF84nl@`pl*y)-RuBW4((O zGn_3wpj6#kW5RrHfi=cuxslc~e{fvsfzW>kW&MgJVgLMB{s(*fq5uJ4kEGMfg^mhq zX0g(uMvHtxSyGlIWnLnbH`pplUwG7NIMN3xt^EUE1}*HWU8t1u3%0BZmbrvm-C}fJ zt;K~(yVBS5g@wg?fGDJp0fmuRX@a`W+)>mIg!zRcl_ZK2X0sgUjIZ9^TtZR`A(WKP zIj;{Wft8gNvAcJ`tuOAdys}0s29u|VMEfM&SZq-uL{7UAv#{91>4-efDbp$4L~!QX zRqq2*rlh$ITH}P4s0-Jp2r{5P&=L{_V+~GegwQoAWvuf-TSwjzz6#9J;bs{iJk7%t zl*Xd86nM(EfH7X>tw@M_3{0Zfua-h~0<#n8MOr zTx3#GBj)oOC`eA?=F*4w7PFBKA%iiO6qH2~zB}_Gsye==yKuT_cxEuY`fguSSbXhp z`qvZ}KXshyXq6JvL+?gmYnOwT-sP*?|8~&I3hhbB$r*5udnjk|H)tB8|Nd6=>V-I|Iu%C z`FwlKEtB7}DVw;T$SjM8z_wUioWetqbjWSr;wU_jW*8l*|SrR2-q>7$YOj zo?GXQtBbVqea^L0oO3KR7Z_da@zJAU4M13-ICE~DH?JI#;E34dl zx<$FRz~M0FV3;A5Pqrc@dF8nt?s$_cO9g-7)hlf793e9}S#5E9do)iisxF&*7WJ&> zRs6po2!JT9X|x+2P1hRZEGHAkq||)(-8;PV-bZ})*==!ra?DEa3ljT(@#y|--(e2P zyD@VGE>q-~!pq2d@$nExjKx?VceT^}-{1XxzW>J`GMMB@6^o6HPgq@F7Z=X1W6O*W z?+l1n&O)B^j4%2q{!4LL7;5Rw+VtJ4pVFxKe z3`!Jf5|k(bBna|?yz|`iRNd8G^N@4qnfBg(*!yJFg-H4j08T{5z1>xnnU#6=-ru*@ z`qrXejp+0;o;}+TX)aito?Uslc*@M%w{&>nLTz?nLPlSMC=@P8bC?oYWXQqoM3Rsf&VYt;%RPvMizS(9ZSJ zGQ_sYGHwkW-`C2{ce?x!>4xFU83&vpLMU>4HH6U~N6+uG-Sn7m{33B2k@k;Bhiyb< z35-EvXG{u}Gu^5)GhJtYzfW)M95ano6wJ;vnQd0NeQ;#=O;`BKxMAP7@yOi^_D`i! zA(lR2Bq;I}tqZDgfbZMJ!^Rxo?wpf#)(;ZUR;Fy6p@b*BV^-7H&&%`Oe5+%NCZO)b zWlz|Kr38+pC!{Ahv$9C7-ejB>bUTOa?L22R=rQbfs79-%*=UF?&+$EpI9@>3{mk-a z7*kj`qEfx03W`EuKf3>aL4l=1G@d!}1V3cgj~WmlYBaR($$>FCE3^(hJc7VdXt~nl z#n{$aCGw%v#Oqsn_K$VBDu-oDZD@%kIN6gb-C2%pKTT=tXv(0YV`+;j6lLg@aB~AT ziq%q!<)$N?2Rg~LDY-!n>Sl+q$eQtGujzVDOg1yLBX zwm41RKd{J`H>OgJk)Gtjm9q?nDbvk}mp-$?`m=qCToMH>W*06HMiIMvZTfp#WVIHX z+s_E20If5MG^JXLnVz1eeQed}bDw>2*5{x@|iQ zk4t)03NHv*TU#Sb6Snrc#LYQ^B1U8*f-olc0>P?{+Z=noG-gVZ^A@rASliv-5~BWH=ZhJdZGrY*1ZUA_>89aI( zH=7j6A;uuWD5P*w8rzF%%ER%my~<7Yulc?oltWp{UH|3Z{8v54Bjb@WD40&?*F=?)N?fOeRc(=nyYm0h;-T2F3DoU$L!9h3U&+qKeOAC^$ zpcoF3Qc|6sqFSrb^n4Bux9J=m;s+k*&(+Ort11o$22W^Fx2#O3KR@oAgJTKlyNv^Q{*5L!Uuv z^}$96PMulCjJnMD2Ymgd6@>J7^VSg~6SLR|c|1yxUTA~*>LFn>dvAd=D@1Y1TuQY8v%?kDvYODoe8k`*p$AM_XK+JJ0&2bnC_^szj{K z))*Z=<`-XEmFq3zhcWGg0|ul_ zS0y{W!iJz}&HVBLIvY@vdwk`E&zfqjf+$9!voT_+S!2JeF|OsTReb8QAV%?x&z~`K zQ-ZpT#Mbr(Yt0Kh+&NijxINa`!E#Iq;y6@T6c+V10j@u1Cz5BCtp z&>hz3d*_H2&ajgl(0=?jUXl}ft`P+)LEtRGU8t)s34+ksa#|QkX-ybLR@NajqjARJ zVNPZK67lpJ8=l8{Kje*`K!})ldI>2*qFRlg|Ker#Uph~(+vS5N9rV_im#)oo@pKC* zpjvMbM}00Xw@^axaJ$b`>@(GfXw@s6UTX4ezsKfYpUAK4BP;js|o(hNJGtjB-R6`n>txN6hLiUU}tJ%RVcGz~D(^ z-J$fc)VJIR?95os&6^+dPL@}nV1H^rEUI~zwlUEgPEp~-aJrzqve z=Gd}UX-N<_NX8?Qv1P1Vv1iVoTIT!jeImjSZ}WWfIk!Ifh=&g!&}`KC_`Nm8$(YUk zHcy|d^YrP4c(%1mDLydTSXHsRw^UIu9t|-F;yA|l{fV2JF{O;rHFRzsPL)H`@i7<*$X_w(}K%U!K(;)Pm(T8&v1rX)1znCzW6HeV7X-eCB zOPbP(+niuI%m13m8D!VCq-4@d02pH?vprL-2Gx2Kq)$`{DAe)1PM)N6dp$86^zfq^ zllk2f=bf#u>k|mDQfd-fWUw@+cKIT>P0DuhuEEfyweQIRD_ej~ zYT7dR&=>+ga09Jsg2sYCDuvb-g)@cK&0GDwO(N9}iBU?E7dgHDKxA2Jq9`(>;gIIk z6ytGfMx%jfHEJxid`uXcim${l?Q`|QXPKIt!D`xRrcsZPxy zf(pV&rsh`}j3FyD^@UZuFl2PpCQCAEGuCQ1O>)w4h8Oq*QDA9a?4ANAHY-sgCeFIm zfFF27)ha3*(&_c+9_=w0j@)Nd;Q0ad<_uB>lpE~H>r+g}U(+D`AVX4qU2AR1!STQH z`b!!cXK^_B*&l2=e(=&p8&BGn!V($wAl=;AL+tL8z^!i%ZmNvDnz!=c9*v%wK!O zqHjpc!1$8P7;3FLPQhJrkuK-P+G1Dh@dU*^InyPCv?=M+jfqa(%FH};qKHFDo{kX) zq_nKdMEi_$o^jw;CG^oMx3<&T26_o96L&Hx3{n>; z8I?)}WeSGlgdo@SM)vih#ng6Sf&MC{>UvgRczj z?odqC8noLTlB_@(IU(EZ2jE%9%YOJ&cfqaSfFhboMui znlntVoI+Gv^ad$f`ZkM2!JBWs&(?!m%r-0RJldhN(`BfIvZ1MR53bZ)ax+!!g&@Pg&C?*z@0mrw5kE8=j+_6M0k+}1BG!; zRT4xT6VA?|vlLHhjB1NflA1sK-rGFgcuv3DB^h?f#y!HlLmobS#NPfsvn%Js_Qo#H zpKl|5kEjwmVDWelD~f_auLlD1yg(HNQ`6Iwb8OP{Cb?VIp5NWaC+;yTqY`9U>R5g| zOBP1qq!F=4yzLI9lrF7XQxwGn$+s#C+h~*x(D5A4@!W$k8ZQXAd-oo{{{Q?s{ZYd7 z!Wv^8@SQjB(5lB|T9OeV-Ti7Mat7fUk}PL*)Ss}=(#kgQJdbgj(B1CZgmg}@+qU1p ziyO!w1tWwi3bJ&B$TLR6F)|2Ala&5Zk0i;_#!4-q zwtMIV5Snx?C9ozCQiJp+fP@hsy+8z&3WYZGhY6Lq=AP5T^8-9TB&^oiJ?QfE=_Y3{ zTm|7db0O(+y~=2W!XPkG3Y4=bE!V+c*-w<4*M#N)t&RAR1nWna8H~qTn_Nk>weT~? z_H@#h4rwpv4vy{ijJD1dS}F1(BhRCWTw^jYWdsIgou}L&uF}dP+}eP1Y!Tp)awdmb z$(Cq$xZx5@wf5W~xusyGo7mFY`d8cVBr$0~ju{YTUypmdLTRIv5 zGCs)J-0rhG@-cD-f4OBhNl)S@nyJ)uBHN^Be)WQoC_?9^;3Z&@JOTqU7ZoKw+-r2}VO-NXc+3BSey$Wjn20HYK zLXX0GiVFHvt1+#ac|$xS%mMp&ycI_i*(5^8g^$VyD14Z@d1 z^%x%^6vhaG^od@tx}4?DCOpZ9kvcrl1^d%!T5z0ZWYF(&>Eb#5 zn_v5HIeq3Vd6rL5FykKYB+Fnh=47_)r~d5(sxCe(!=Z8we;e#X)Dpsl^%IUEkoaCm4-W z@?e_7QNSo0PMlq|7VI1ixp2P4#$dqfH+u*Hhgr-hnBkz;u~`#BV1%SS%E@GlJ`Mi$ zyIp4Egi)#))h@ENF`P7a1{kI}JAK9J)-r$i?gmQ@O?|$KYMkQ1yLTAx^{LD*;6*Xo z_-q^ud39xl@85aOlWhblV-%m^{+>@-fbi}6P!yVvZ$4q^)ioY>b9&$3B$Bxp2QzG^ zF}-oObV)^eKKtzv#lkcrxyHBN+F`!cC85HRXt8xPa0j;C)<$W;(MWT;HOKG0vBjC$ zUDB*zP`}9IM+uY#s9Ra3#KOu|nJ~XX2pfpz9~VkxW|LBC;$n7YHe_Ym&Zr%2_sPYG z{=qh1_}mL(@n>)F-9Pvj+`s*i{oH}9P;QpZ?)h;oLJEr-=Y`FoFbKEr+d}-s>(}_X zU;JAF+XT)MV`@Mih;+xOY)<|KnUcc1T3^vAq>agO%ZfcsD1J2%mBl$eeze2tOpQ1YOvM57Q!$m$XXknMICsVvl(EJm zo)D9q8?a7}d+jlQ_R$vYLCVp%U_8#aIO9`^Ypic<@~{7Gm&f}V(foNv!!hHEn#?Fp zhT2`DXN08WS3fNYl~kMarm^e`-I!-wTVcIz7>OFy)(rhY!kL8{zw}dAsD>U7Huedc zO}sE zPOnF;-k??wTm$0HbznRm~W|KTG81#EK@Gl4_XK9(IWu2>RmWtg5ZKI)zV&Zfq zq{MT3w$_^Qc!bsp&#R!c#t(e!vgS#bdE?kAPogu8QDEe;yr^s*%fDM&Z+q@M-aO#u z_Ir3i9ZwqkNU~aQkTS#Lr_V@CNa&EwQvNL*yDTSqFO60?R;ucx-M&QR?o4y44SUYn zj2;nGFc^v~Lj@MDFo4vGywGI1rf{tBzXzt3XN|jG%7zV%ReGE_*GhY1d-uBcp=3`c z`?Vt#OxaF}3HViwA~F*aRBHrLgvu3Br9!pdAkR}gKVXn1+`RXM+SC$_sTnXXtIIg> zSSX}4!jqoxrNC1HZ3L(Sj{t+BP{&8!du8j^K?1);Aq$q?bMDL zDH#@pO|;cfi8Z99|f+zW$tru*da_ zmwEZcYogoh^61GX-+%p2>DDd~)n-VN9N|33kpjQkqCPdt%v6)lUcbi8=kJ4GLHHGW zfY}bqu1)FDoSxy;8)vzE;hcHC*A?;2LkO!DmDL8ws5fT0e(f^X&aH4X)I9&qH#piU z(1e)4r>F;@a*QV_0w2@J@M{%n&1rGrVq~UoZP5>=@xv(whev4TQ(auftJN8_yJW*L z)!7-m*di!khXvzWJlXiH)WCj*B_d`~S-WA@V~^8I6;_%7qftid>@s=U5>IY_fF7l$ z)9s6FJm94(XSs0YhN;9=F`28Fl=Y59IdQp0!T`b{HTJJ!@>8F>jIk|>C%oe-% zX5-8ZGb^j~M=86x!k2=|^fbcL+C#l~ibD4HQ`&T?E-#**eM;j@AZkIknS+#*7L4Q zueSS+1oqkqZ`|JHOD~_LuUaBa63`89KOa(PoGFAYY!YpF_t6nAot+_zrp0D2qdzu$ z^6Zd)CXqql${~Rkf=`}xQL9Z>TjzP86?qtO_t}u0_833#${TW$XEK3N-90L##FK)! zQFXaWo|A3ZFu|lhLZunCW|gnMaEhOKVV-&=pg%ZkiY(!sci$C1{^|>S{&Sy4b~m_l z^Fzx@8mLsP3(|NzK4y`%CRc?+MNc&1ZvXzNAOA7_hrj=~dHcQh`0@*D=JKVBjFL=T zzHpY=>1hTB+x*tIKZ5ZB^;%3bnxf{VNHxL}8kKbLvL3a-P>p=L-63y3-l3o5Tt2^q zR0VM*K&4T0AQ||+9Z`at}#15PrtoQZ~qBPOA9CsMV7k7>|U=f zLjr9>;<*_Bx1XYwrcf5J@O__BMy*OYmFE$JA!(X`5X6<(HG7uLP1A(IU_h-_vkHbn z;d#C-T8jd!T(k{yk>-vK5tuwDtc0MCou7oT?u`m<10wU3bLTGbm7n`h%=(ij;?@Um zbNSk5xOC+@)n=1ct-|-;xrxzQ2%L+hJEtZtezub*3Y*-$fayi*A2 zTWOdBS3D`GL=h5AmS?0{iV)Vj%9nz|IM`|e=rC~<#Io#;84?qv2;c%R?Hyg#N7kxX zI-@t?_GVkyi&A-D9BVBFVN|EqXi|wIgx07$V{UPUFo;N!FRY!3E&joW}Nc%c!K zyacEDJYlUn$x_g^IZ?_?<_B=EWrDyMgLVhLHk#ZyZdeAyA`W?)d@8d614#NpdBMJmK`&^CAdqjJh3@AM`}LHp6Q-USV!_hKCQI@^sjz5E*xF zet<~!84QLz+Sp}hdy6Yy{SqHONf`Bq1aSr5_sG(WrKJVF@wG3rFctHYpS#8zA3fnw zlHtb<(2x#CB*OufMib-tEY8&Vxv#v$%KQ|22VG{SpK$2VPpxc|cV=;li>q_g18rp8 z7tN{<(wYVc13{&NFcFvn;S0iQl`nts5?}q&Yi2Occ>DeV@2-y-w|ju3wR#E}h71mm z$i^A9`2}Rvh71~apg4?YazNPw$jyP2d#O9LrkfE}#{9&EX@2!*Ut&1U=#F!8rFr|^ zWu9;CaO>ey`t2kB$N%a-;`1-Pz-TnKnFBx2N0gL%`Tr-s=n8-F*X?OiNTJ=1E`$)S zA(^~lDJJl!FpeMgr00G{7*}ab|ge{wU?o-&&_oApO$B z!4Osg>T~mqq@-5}Uc7XU!8qgJyt&TqASVoL(zSNYxRf64MDfP`BNnErpcU=*klk)d zwbgWb@Y06cGCjNfjC!@f#nTHsKN#|OZx8KkH_h>lXNy8Ra4^{yjmvit&eGI=h{t`l z1xD??8u}8W3qoLcxFeozJmvA-j~KOgxqtrw@4x@mJ4o^7#x z5D{GZI=4D?Hvjk*k9Ws>?reqUJ4bwcZ<|W1$)nfr(U_hho@&t^W<1#0AoM+QZMglU zJ+VbEy*~v^-1;1v1z?9}jp4?HS(;U!sanYXew)fvix*$MPWz|>Mb5RUCPEKcTbSYc z>4pWf%HLafpW3G6r`C-_fhC+jy+TL#XlDgkp?JKX(k=o9!-TxhJbkv$y-`AaX@PpP z#`vhisMDo6H-pYHdWT1ZaZFULApy^5l75Hzis7e!>{b5e*Ir{~zD1Ix{PF8=nf0d| z;^O)9y!OfsR+ks}ci;ZD`EC>Oxz}DXpWM7HzWtr=y3g1FN5amijYdPd?G8#Qx1R(P z6@gX?DQkysj3$n&lVN=!1$maaTEhZ^+U0zx!p(#@ zvy7s!N$jQNtn`i>An8epaly4qXZfH0{x69SKe@#}?yd96^%efJzxy*Z8a4jp`%`@K z$!*5QW~2(K;OAu9SOkSX}1f3v1HZ4~b z#|PzPmc&`;xdo3qQcFtLAZ#|kNr{0&AOuX3O$7p@iiwuIH1`2R;T~FPjW(HGoNgB7 zq|`>ag??~&z}EJ*7^gW#dJKkR#>treFvSllOwY^{MOsvc$!xtG~H z>fyyz3Nju(dc^qXIeAvF*G&kcfQ9KgJm`|8DPAQ8KXBgWn$E#4j~|U0=?c|)9g|>( zZH2anneajSNYAI&J>uS-dyEDv;=P;q$qI#EjTol|NXE!gR-4 zcx8mDuyY^A2!!#ip5FJkuslQ6OGP1a>Y>M|-@~uX&{$o@3o8r{j>v`ywYfR`s+Cpcut80%%sMoSF|Aj1!t)_zarsqCZS{|NZx< zg?4W}rm7wKRPMUi!miA7`1dYhXD=|${ucXp%TpW=@|H}6n+K8F7$c?7+8Ci!Aut%> zg1EFUtm?|j53Pva5%TtMaI}yp6T~$_O5yvyF~$g0D74lZv?&TLd<<*zE&k3gevQkg z=UHEWOc?mgwiDno#=chP48sh6Q z>EIAO&Zt&v)L&R7XtvPO=j}Ic(Wq6}>1Dim|30l&ol4}97G;xvoX7L2<^$Z?Jo!Eg z8|k8t0Sd4O*=mvpQ3yH_Vv1G|Ol>=F!6~ zLf^xyHPD{tX3sP;jga$;4dRN=a4;fC3erSTsd=smF^E7QwC2StODxY;+1@$g(&Q*IIuHj<`_Uxz;rF*OV^iBN|7r~cwvF>eXz;Mz2{{vOO`2S>mgsgv4$@UAK%$z zb*aVtOpWIUBfK)@-M#nX#JZbk>SgJyW1rvslMPYxJgQBL{7VUcdTXDJt$jkBbNl`y zHl93zA|t&2l;O@FGj2b(*+UcCRRgGrhTlqSKnZK}X*KB}gV0KAwC00PZt>2oCyZ#| z*QWU1`a|OC4vm>@A*E!m58>)X`X=Dixif^VX^bjJy9MKpBAySKstP`Tqe8P0bMw|? zUb}IIt5?tP&h6(2Kjg(rOMLj~5RB%+>J&F0?Qvms8V$U4YnQZ8_MVagFODV+fzno1 zq7l4vcbBWDrioB0eL;Rp>v!Sp} z+9Vglom~b90w0y8jC%*h_hRw%aKyV059tpJo*X3h9#2vz3T77Pk(CNbx69zDLu-Bp zFeJSmvFDL?+o)a#ghraoI+D%Ss6`%2&5*fzM7J1lX{9b0MTp@RyN@)^t(rs0=jgCG{#uRw75#)WK?C=R=NL{z+<6uht&I%dCW4GBM3s^*t8-+5;2xEjcb{O0fp6%gXvsJ4_6h)ao#0dbzfvC#nf%u-I z6|g2N%7qJho`=dabe59mIYvsC0ACJt+jVUB+LGOH4WMh5%iVOsTukJp#vZCJT(D%5 zZ3tvp}A+sj;~=#>~%73278bwPIutn!uAn3yF~)D$B@n zB?=8j7wDp(*=!KkYP4ESK;Q{T3&qxchxt~OMy*PJI1)*kF-lXAHNwbaEQCOW$V$a* z@9c@*;0dqJt{%^5{SaP1YCr%Xg#N~V{@*JjG?OFFaJ(>t#8A3%D4V_EiQ{`4>%X67 zxkE)fn|a~TIOC{ARU(vbRh6uxF(_blGnc4T0!G7qBmGbW z%_&w^=9yVq;qCYDGfp$+7nc}r9-spsJRf{*vl1Mo9oDP(V}tfQ3anQ2U=Z^U|JD0M zLeZF6WV@4MYEviyN=S62N)W{u-^2Gkb`B)}^RK_o(&{3QpYD)X=kSCb`u5@)K^Smn zzuCzG40yNgOEHfUz_3z&1@y0Xu4?4Ve^BG}0Pi1itDisF% zM`XhhwYgc0A2J?{@uC3f2e!C&RnBAxZnCkuTZZGW1-`^6MKT-{hZaqaf&eKzio9T^ zS))>kFxs&9tZ9lo7p126FB?8DDQF?ez`h?;Pkm}5Huif>>_!tC~thD z6&fuf8FKE_GX2gzd6t=6X`!?xOLL5tc+QqrYs08NqDV8UtvZ#sLO4B*-)tdFK~%5O zPy>GA<((b3cb$g31zp#oB zlD)&>gjKWmk(J#^A?OZLZf$gUzSE-;N?yDaqKuP|n6mk`f7b>MdkK+*gYJmKK}ZqC zROaTa%S~Lh_PPiH0XLtt$?}4~@#7cS?~K^n>w;2vQ9u;Lc8|i!%+|NMoLQ=&rQ~}b zKBJpB)Y9eolq{|kg26cBusdR$q--9HnQB#$VSp#~@$ZP0W_0^0>$^SXn-QCbV}iIs zk`>2ucavNEIBan8uj2Ug(yDYa6Sl!|`AIe{-mam$J0tFF=ZHd~)C{T>QTGhp&H?Sw zIx&*anFJ`KFsYgB%d!Nb-1AuPe{0KIXywpt&?00YXArGZROVNqT1T{I*h(~@@#kZN zAMp4vp^zcS7%enKkVB9%G9hh3WDZArLpuG8%jXsegyz!eIqq(>De{ynD>c^U8yxn= zEYu`t7i)xp&%Gym?6!-E3`hv4&R2?B=;L`F!%Wdn3f{Z7XXhW26lDxgJBsyQ&(0>G zQO2<1OTswjpgrJV<9&Mj>n4h)k)BVMXJRx;%Vykop6`aHA@l@?d(Rl_I^OE%F~*Q- zpH$e-9Spj#4XYLsl`GP520=hnuhZK0QnDnm1+fHUN_JNd001BWNklWf?&bO&V{@(u8!nT^`)KYYz6dM6Fh1I3Dp&{>eY)?5R~Y zJ2|OyvnsA4=5W$(V@T5ssZ$1n zfm4F`_VFBnQ9fk3KBZ?J^K>Z*Lww5Y!@eKKyK;FpPR>|PxUNllqOzg0@+%F5e!!WP zMOGJQF^&V$+P>Z_%dt=h2qA?whQiI(Xl+Py3w{MQD9(m8A_zP|;CUj`kmbe1UOveS zb`RR7-|Nw6HpRm1l$}4rAf(5Iv!^lXz}k2#^MeQY56$(X2Bf@fl8?RdPqyA=BO*a7 z>)zn`Vqyu3L%6|iAX%Q_DThduk}6}10__kXuyS*Y7MaPwRmplx&^(wF6z&zdf7fW& zz?2Ts6BNEIf*gk#_yH;hr3)*g5LQoa3=~<;;Zd92y#okhqPWg*obtvWeTV(+XZ*_F z`9-RJZk|5fWdEoKVw%O3Ws5W|v=Cv8!9yL@n4S$;SZXjDrwmjVxp#=?3xX(Qb;a8G zA_avO?Ce+R95t9~g*2yX%&ZxLYLzGLgiHz6&dxZAnxQ)`*i~~-#K@UhF3qk|Z8q8M z6>RPGsfINWlA#bh7}z(_6B4NvNw0?tLxNh>F+=WsR0h8>!-rc#9{1a%qak|WF?DW^ zBC68g-A4_2G!_;isxoK~NX7|qt3kElJMzkXW+#}XV;bJN8yNvY+ry~P8X-Mu)e3>{ z69yqd`uIVFFgB3RI48Bh_lQDk%d1pwz!PQT;d!3<_>)h>z1tu0)vx^r%+4)R6uEnT z?F#7$MqIuo%U75(ZB`;Yf!10`VdXjogeQ&BDwEo1dw7B{rm%dDL8v^l_pDMv$WltA zh4if8Lg!j2m4i_t2qHF~@9>ZQ*MG#dtC#tE|HXevC9a5~C@`+cP$+~kw2zKR#)*5u zE?-9o3hmeetw9n>eo_;mAOPOfEfTnLw}rv2s1##<1CJ`Xm#9QDQ+ z3`L>Q!Ztd}{SGC}rs48 zG0V$S>~~VjwwV$jF=!!B7y?hy9~3;^8L%|pB=jYzGI$QbHSYI|Bac=sWO2I6ekUai zB$dc#lx6mJGuDU~hj12!CJucX)qr+yOdR=`US`XK@-xvIVR ztu#>-bM@3J{iNX8gEyI3KE-V78jWg|-ngLC86hiGu3TSXt?BXn=?3VWgPjgR8qkQE z#0HcWTs*hNspfgA6`$!^#P;EkM(mTM1<$tIEVe38WSn1ak`6}z?m!X05Ct?Vk{y+! zjgv{0HmEA+#^rgmki30w&stEsbHtDAaQ#dxrcn#&4pO?q1nCJXwFV#Dd&c+oAG7uN z7E`qlP+UB-%-+GF(LqhDojT3>`UXA)%Zqaal{#6TlN-d<>*tZ3ghG2%Dn7Zf4sZxC z;S3{VC8v$4D)owBI7rCx2%1f@yGnyjn@%HWK8OXm5C%SKoDt}hFs@G+p|XJ0>Nr?fJLb&Zp2rSH!pVJnKfriC z#?6hC3r|W(p63)re&S3PkfxtP_=SKltem)a!Sj5IqOh)bK&4WloGSa{kDj_gX=DUg-=^dU#=E_hVHM2oJ9s+LNN9uFTq@w6@iRRlkj zO~{WL5O;Y(8tM6|GU?>sLjtV&(jJ=$c!@~~k{R5=u@xrS&*m%B&FX8gV(|qp6RmNGt z!>4=f>j#W;tCziUdY+ZJ8V~M1L}nxOZU@!w(u`-A6?2Tzg3p}0K}Wv#yiGh)XId!^4%#f#&T#qKWqz+cWRxlEf*}N+?;&w0XKo8toC{2)5=;=& zqR?n9Y0WP%RrSe|gnU>>1Qi-_Ks;4r6h~00BRoMAhcp`@eiV`#Ll}6dLfHXKm=tE8 zLTk$G7Ng0F0^#{YwHo786IWw=XQMpTta5O$N9g-_VL+axY;PU0v@pwXG)4$RC9XP= ztszMjzx}(v&tJU$UFy}4mv6jCmL+a*(NXz8o@S(J20{=9fiM`xNrF;}!1wSxPiU>l zvYc^}A%q|bJfVt$B+aZmL+Ht%WTq5(riJfY_ASp9xufp{N|eK!N@*Je>3OU_-Q?|$ z?lH&&&ENYL2fJG$&oU}e$oY#`NOHx^kKX6p`AfX`@@wqwACROO&1Q>ATxXCc`0mj6 zq$I9YF;zoc38+@BHD?%jj1z0H(5Oael@p4LD`%Q~=3I+$GN#B4AK!b%_Er}^JdYSF zLSIs^_)OIzD!!zzb1YRRKDB!g{IMv48|CviR)Foz^BlL3rj6Ndv=P$ z&XDD~I-3V0zWd%YRGw3*MEFq%K&}+4b5+jG*XZ=eTst!ZLU8-e4¹QT&;zd~!x z>{OMD%MCjH5wBgIBaT9L+he+eoG|bvWSj=7f#k|s6H}z@9`-r4*y2%OIPB#_u`MzY zIC-hz^4b)O&5#ct?C|;PYkcP7BJbQk#PdBngz6*?y3nl6*9n9s&kDZw${D(&jQg8? z+eEv=RtU&*L$ew(*9hqi6Tb24DU=a>`-4r3_?|fImDW@$K6A~Gc4xrl)6-1VW8S{M zZ>5dFu{^Ha0|h4v6?43UmW-9fYqWJxnt(c1yMO&ujf=Ap3o{MIy*^oImZuMI@l#)X zmCs(k!f*V>uk-uA^DphNs}NwE#K^^oj7Fo0aKsM19?u3TrO0!|H@^1c{CB_hU-Qw; zTm0!?yk$^TzAfPi$7!QZ2G_miE z@R31iXA+8nJRMW7S3xNX1D+=d0-r)^uCBDWuu?}UO%%0w@BSWJ2SX}eonBF4y+4aw z_(>{r4RNsXfM<8xMDZNWR+FlkWv}Ro!`*G3jTM()zKl0N!|HsKekd7?a-vGe&%Cq@ z0(K7jNa+#BAOQOdoiIl}W8Ckgddi|WiY1(E_=?B(5p2Rm(a zQ9=4GDtL(D9^KtOx`^I&sL zK$%*uPZrVIWqSyL=h^%a-?v5%lY-g(++_a2H9J-sr`%)O*Onw>T$O7X18Er*tqMFZ zvadVO?bhX2sLY<_=%~Zd_AY*<&hoj->}4stM>$6L5);SSO8=-F*wC5xQ)w6sR1eL~DT*hByu=@`PkOCM&XHFdiKYN4*h0 zgx8N65O;;ON*`oulSl>Dpvp{|2g_KN(1k1LOElCWpcb)^2+zm3{Eom`#$~!}C~$|Z zEsTY*h<$;c1UQuk?8%PXp0DL#JkCneebIb+d6btiOeohfPNZCz#$baAwc!h|+@L#F z+`apdqk{vCkOZN1+}Phc6osq{Aq1Y$)ay06M~AFGe9qkJDq6u|C*{LW?lJ1@lPS<% z%$L9T8V?3Fl5`(s;OVnHo__KUUwQEqqu~Rd-}wN)_A;l>{}^r0CrvU)bIfQ=o@*$^ zoM{Q7;eb!>f0y{$6)v@w2}X)yG&K2mBtlOx#^8B2BSDlXg%L;(>eCI1Tyb%^&a0Q^ z81(w2MaGkz5s$Wdtj%~_IXz91haYp+2qS#{xZ#}S>Afx3%~FSN?*GfP=bJ38p62I&`9CJh760sae~WIn!}V(yxN!Y*9CdsA&UfD9 z@BPXpu7Bn#57wWtwckbtq49!9C{>^l_?|@@!%9G2C{E4S`09;i`ojc2@OZl2Woxg) z!J%T%?=#h`i^xwY(zdBIe5#FQ@o;lQXRyamj=8=%!~ zPdm<%l8GEEAE&4+Cx|1wFqlXOgt3QBK29-O5ycfe-{xZX1_{01h-92`XZ?WvZbp$6 z6r(YokOXmPC5nN^-qDC#PmV~koQtPsIqallNGkOh&zF;RD+P3hDIYx8W7HqAy3oX% z_DGWgDUP!pgs`@@nKHa}XBTY@QRtIo9iDCMqN2ueQSJ(NAq0=Mx`bYfi>GGU-0!h< zV1o^h2?o3Qgudj-PM^q^1kzxHX6v9&niUo;o-}PXYo#~J`QY&p+k0KkFSnR#)fkPl zV_?KMUd|Jwh2rkBF75V!IP!Vn!UDZfZryKAY;vDwp-ya)<^EjeES>ziESm#^K=IkN z1}`rPzVhN4qa@|vpvj+myIecfbmKE3s#Lgg;T(;6oj>{hd)&OcPBI!%2|d30g%|kjsTywrC*_^{hvY&~X&-TCv(Nv>-kZfrnw)2PPelA%E+;e3e(Ids ztE;NJx|`i3ySZs74YiCc1GY!r4cJ!$!(-Th0UNLZUkxxYV8E6Q0|NsF#xsUB*38J3 zESnlrq(o8_mu8dQtm>|=u6?hwZ@K5cMT9RR{>;-Y`NFqD{y?FsPG#ltXT%rZ_kQp9 zzO9<%wF@g?4Aztk2SaML2%|NN&4BrfZImtnR*&Om$<^0h=0LOo!IeuL7UB{yZtdZ&X*V&1*+kzHv7G?JP)fBp=^NzUf|d%S$y@(AcvToJWpCDKFP-G-csTNl#KZjYrI#>7i5I!qfVc z3Q@|fGixd#20Nv2edQ}}@gM$2|1sC!{|UeUPk*1&mtNu5e&aV;S(@j^KY5>j_0=n?bJl{zc0)e9HmK*DoFHKP($}tovuJjMauPP{NwRYHttSe&F~x$jvhH5HR^V1~w6fi1l$FrO?GtL-kV@Euu~f4NSVD?YW)MNa6)yLwf- z;wH~Z@*-z6ndF;$-S0ozIrzr6{{DY|%>VqCQn-KauU`}({tAUkr4$C~Jsqr*#XH%y zs5&CEbbrRZuCTXCEyWcU9x1x1TIF%o5EN0q0salh>_3V(?YKG*m zDn0z;JSF23t(Q+eg7G+|*Y8mpNx$DG&kKS;F-}W9y#18LFJ6$DHDWN%pa%6sk*qE< z$_&j$LJ(P2UVnp28`M1XY_QJ$+K%YPE zkM8q-|Jje|wC1>U^>se`**Dlc%y{svAM?t!Rlf996s{w?A)>x&v|g(lu&FUB3Ej zzsg&0y-jfI0rMMIdDaj3v!6b6henw2^zMNO)DeSH@SOM>K86JGeGOvn0}*KV=2>|Y&b#&3Kd7wgdO1$?6_5jimKuFYhD_xQk-6GaXc>A z>}EtsNDwrgX{A4g1%gSgiQ|w~BVsttIU40e^~4n);zYa=f}(UouID!9$L<4@D177;R`Z6E3bb$nui@xIo4YS5&yg>brIB0B+So9&H|SG{{(N*J(8qcKZVl zrugoMt$Mz&FqaTfG8#@O^d~z-)@?(Ku{7%uK^UNAz=NG3uhwFcIG~^E3NdhWEd%u= zV6G97rZIzI%FfY1ZWaf{l)8lw2x&n>TDUoc8+V@Z z;oZl4@bN>QK7GuC-IVXXf1f}8#&?mzVst?|8BvuM)%?zs*){z(arepp*^~ue|N7T? z@bDpfhkXwFnK*m?1J0g4#Y^YbF}mdXjVIJv^VC`$`UfeK!tmhfHa8#c60W|&)E9veZh_h(w!4eOj zhde(R(=3lzwTc(}3H_i>pi|B-NCty_ws($MZY^T9CJF=UwS;t>Q5p?sB$=ZPNyDkN zdH#cc>ubDpW`*&1%-ffnY;El@*R0uBu3QqQH`eXPw@xviWL&xW3V-p=``o{K*C(D% zbxNp;X65Io{Lrm1glNSYC9qcG_mgUD{o%n{JAp(#n}EI zfB651bYi{XV3o}%Uk03*v#L})E4>jR!Ou@o{jv@e1-wF-AqWJGdJJWbi2{n;Da}ct z+?Yt!wxq%X#5A6$3fK_>=~W45)N=P)&ev?F0I7}k_bQyGIqvJT{<%F{oLn{HBD_={Aaun~nq^1h(Hji-iy!?| zgtaz@hewoUiIS3GT5$K-f%xL*U*XoHeU8QgQ4`#|`;b>(z06y0y~^&9b2dJ6d7TLv zr!QQw>qe8Bke@x+74>?DC{#qDARwmfT;luphuk@oh~;bC+A7%p`nwc1eAqXSX{NSKf@c^7#u$v%}=@0Gnkrn~6($yrZfw z&(KmKEM$eDktlxs?aS2i1AG4`H^i08U*cc<$_088xb>n>kxpp0=O{wKYCC4N6B7%| zmGurmsJQuHkH;^%Y^=0MqF`3wRkya{gjOUNA*SX|QYuPgdFSbf_wH|TZmG`M)fP!F zqs%k96C+qW%S#K+7eQyK8^rbrPvxdzon#SJAQw2X0c#v8wzsoGt<~hrrB}$Zf~AFd zR?l6gF&MCM?t)!doEMj_yvpqdTLen8@zTrG>P@@6x+<2}&$GI+#M;`LU0GaU_0)!F zEN<}9%dfGxyh0eqtgN47ab<^VFJHEE%^F!=aOTW8+KcO4y!smL&LaK6koLkUmPeM) zyzz!jGtE(dOqkSZHjI7sm6sW3g)qRz+4D?-IsWXtIZq#dgfM-nqx(T#ci-d47ER1O7d&2%;L+%sGy_R88_RTH)V&6iQw_zrev!pWUMYUwrK>`@Mqu zJA>&wg{;yLYglN;oI2BHQW(Nev3)plNly@hz)=(=l!fN>QkzyY?|r<_M-K%>k+Xl$4#$daJwn-rc4NtpyyWj;e#>5i6V$s*?N%j-s7i;AH8tNPSPP> zUq#fLT)O%a{ce~2yiR)R3nVLbMoTe!f#%I$y~rysUto9WD5ug`B2jRvnQ&%fjrV_Y zo$j*-oIbP0%EBDw#IU^7VrgXo>oQpCNsRIU+qrI^o&945hdUfRdq&h~qlgf;L=XUq z<6*|Zan5|J&M6sj=h-m?0f7{}w9(?lL5d0jwvQ*gckez@1$J|PBy!u}2iG66J%s(N z##*v~3M9%JS~BJGN}aV+bG-AcOA-Vm`61?Tz_1&mmM_r^3TpWQB?d`ORvNwz8SN(^$a^cpx^89=n@Y8)`n?jZ34+j>2Wm5&BgwOj3dOHxH(b%` zhR>B$s4$%R*i^JHE5uCY(693fskhb{a!R45=EmU6Sbui?2LI%r{$sYcxB2MS9d`E) z`0jVUW!F}g#l445gf#_HwJ<6MA)N=ZRBkPbsvqII3j!?Ct6{kU3S~hACt{=qQ-E-D z70y)A&GDsahAzE;h7^?6+g>pJsMEPvA#ikbpCs7|Nx{uvV70d%aEg6u`j}6B4^u@g z4{R7i>F_i|N0+B*Z zyEIsfDGOv6Vzn6yrMCQk{JFe-QGoa>ijy%?j=e0YAB1)PRw?9wFGM7MNY^bv<^CAAN}M*8mkvL9uz?C07*naR3t~;0YCoX zd$iWhFvtWOs|y4w;_ktSJ3C|1s3)XlPP5%+d^BO0S&G7N?#u$UDYQA8Mp(}EXky?=wIOf$4L1W7~?C}bEg7)@xX5$DdG z1L@p+7Z#SW8djDTL>wpl>MwtVpWL{Ol9GSpU;o#rH=1H;agj!|gSC>?l_jBswQs!o zGN;d7;`GJ_tILZh0oSfv;Jfc!XR*^1r&gCq^ODnRD`GO4u(7hh!hA!Wbw^Cb6OvG}xVXSxy~FV+v!}~aWLZj}0x~mUR0^Ba>LRp~ zaVdDPdCawot3281a`kM7 zoLOyh@!T@KiDvs?g!G7KB_C^Whi-4+W_>>Q`f0j@jK|x3wDz02g4%rtb(9uN@{+gS zJjd?AkSE)HrxK-RsJ{^wt1X$a9CgQh=JG0=`!%)>hV&-6+zc6#jW4`yA4Y2a}H$!>Sd>uQm=UO&tB{(y&1kNw=xta=mDNdX@ZGB>}{uJd%e z&(^_+{>ag)TnEO-Nhz76IsN{KmpA6vJ{a(HXTZVnm?RJgqY+hW#i2o;DhQb(s3+fZ zl{n5mgG&Z_x!^dpU;<=qiMfqMY*}!uGd};hOI)~mmA&mfgfWz*OM-$xdcM3wTi2m7 zMGjUFgrP%1wMGg{oYc5_yX02NB3V)W+|7?uCTV&;mpPw66@5Hu+zD( zdM#i)DJZq!()qJ|=GChl9d+&9hc85tXP||X9ZrwtTZ^k z5HQ$z#;c2UF3vYtTWHf%FO$qK(@Ui2#{dw34EsEOvEx*Yg2;C* zW`0i9oQ9|n?P{HRQ(<>T&HzYjLF>X5>ZVe&a)^6iw8tA=Qe24?R30@>e9(BMt7^uC z>3TLsQ{*{Q3nl?lDA!f7<+KB1e4;%Vj=6dJA(Kf)*jVB?Rs64i@GTLBku?Z0C={~2 zY}MSdKnj$nJvoJW;R+BHc~J|CC~`zP!W0vjjIr4SbneD6jH5ETZh}SxAtH##@)D^e zliUGlMg>%=UQ^!?zb}oaVTHbf>prtLgY*m%TgmlS9R*)dxZ;8t3&nqLRY6#Fv4oIb zqSwb#{O=xJwpHA!x+36;2Je3&RMo-o_o(uTlM0OXd6}ooR|V|}`dF1nR!Uw1B22{OJ2Xpx5iO+bjA0(}<;}WO;c7ox^MA&apG; z@ND~-*eZ@59P;AXCV85(u+U~W7?PKUq+WM-*tct~($j8Lr#(lJEc0i#y5y{oy!2~4 zH96nBIl#)0(-$u>DI_-^>~gfdPuv)g$8$XD9+CtwS5L4)GR!UC{a~A{w8T+(BC$DH zh&Y9@EX#;$2`Y}fx|&OB10{LB+hcRDH#LoO1KfJrwoUs(CfzP!y-vM7H{-NdlFr&N zIqIVGjAUV+xKTqXMWz)^6|&rEaQVzK!>pt|*C3mW*;rd*xzivCPjPCwgGTb^%NGfh zTb+$Ylf`y}jZ>?H67iX9mw4&wW#&6=mOCwkfR`_9&}q%F*q);qD?+qAyRjk`7Z*6Y zzQTOF&f@$WFJFDh{^%z+#K!VGYl}@bmgl*6;T$(V`jD0RITkx}EVSw@EzI*59~@yv zEu@r$aY&JCP|6)%*y&+yj3rQ#y+O{O-`wIWubrYl&KPDI1Dso5U~sffZ=8~5Im7M| zajni!L`01aE6Va@Y>{EegY5yAHWv8mYisB{=cn)9CNCt76dgwXmHg%koKtYbh~XeEl<4+q?S)*}c52R|67 z6nCue6bLCuLd9U1@zdM8h%oXUe=|e<{cBj^L>0nu_OY$_smL*XXaxk>UlMMIn2~V{Sg$r&bI3YnMC3hj;m<*DrDI>=~}#yhV4EaWJ%G zTJYpWm;HexY^*RbHSRt-pfz8jcQVG4oX?zXQKl(cTe38TqC}Yl8P^GuCMs$&$t{!I zl8FE-BL+jwC@ir;p=vdPS`Dj9Oz9Is3_+4$(l+0|vBP9=%w%L(UQP(rJcHvyK7P2( zcr?PAfU~PhOvYpO_V-C@37vLyB7tX`(4WW~U1wm5te+ejcS*lg5^L3z|F43;#cQv8 zSQQuu>4v{0#Gz9;G`@mSo=)YcTVB#y%v86m_r35Zjho>z2C3X@N$LEly8R)4{JrbM z^)|Iy2O||d(V^8jEuKDmP8KM_T1$wehETyYZY6<>x6W6@lTd|YaTr}XxoKGlqX2|0TXfj?)f@6??5hbp=9L+w6hIJftTVrxA}RT;2-5_p-u zMDi>2qvu?=neqWDq#CPYBXU&Tel)Vq;ViI(gRu1Qw;- zL7L{8DyHNEu$Z5*Of8i6*hgp^*wBWTn~lxvL}=@e9uib}6p1Q52` zh@wQr308&}DY0QfBW^-DVSi_naaKS%wn3=GXgJ{5_SxG%Ae)RSWWu8d_vo}5cCVL- z!a!21v$OdOMUF~32&p(aI%0q48A63@?jBMQvwPU*(c?!*lZ)ZV(rGp5b-Qdoxr>y7 zqr(Fc#R*%RFKC7tpg7pyL8yc$&o^n*BMy%T?Cu{C#C2>OPFwyemdq_WmuwY;Q-s_K z&}G4yO!47%c;i! zuU=eWbZ?(5cU@IiO!_TrV1BMfqy%MNa_#&gJKc=#D0lQR-+lGVj9MH}4;6#{m@8-I z**Z?yI-2l_Gt7HaB(Y+pQ)4pDxU$}+KQ>%{c;sjhC&QEf^Fq5uo|mk&6Tb49(|qT~ z7NgwE4prZAFvdyi#-Riwc>9%Ax~XQrJ3&>3d_In8V~ImaBMvau@VP5140FrV-J!n+ zmMKlj7<7>lS&c1AuAN&XD>b(t?vr)9L_m>GFoPc9;xfAW%qI&D`>DU5`0l1kW>r#A zJzhAlrpQY-Yf!KAcz4L-t)4Fe9dc{R0#g<)!3;tKX3Cs#%_@PJ49Jgn357*^+KRA# zegFxct6pXWGRRR%5!CAB2tr?Ux?3Wg@SPA|2G+Cmg+tf_C3(7agfIn(k`z{xrelQc zAS4u}As-FMvk7UIv$!yi(V9VTM6=mMml?f*yB~R8P~;^>N0_`I2m)T(=&;(UvAR&_ zJJ+96k3+=pfHQM~U;n~YYV{h7m-*ID?=u`Nar5pDQPu-p64dJK9gWD#A!=ucQ85dx z1be!HAw;W$ahfw3jVQI{t6zSL*I&8Jt%sY~mL*tUOu zAV(@N=?I-?L~(?)1(~*lafA8AWsE5~+B%?jFeC`utexJVIoBa>#CF`<6Z4C!L{U(| zc6>5_boX3JiK#jof$M-eN|px*jdK*o3Xkr)LZYJSXK!ac6kg(WUrxIlY( zohT4|aO(k97no8bt)o3E0c$IZbo*oa{>*Y+2JQAk5MspyCki}^2cJlpJq;KkDXk#H z-7{NSv;l)cYwPckBrwva{bEXQv)W9VAhYJL_+;)fd%+pdXfm`U}y$9@vr`=kUcSRb35s*IEM^X)&+K}ATsH8=o8R?yqqa*4E* zC@I}AyZ~uSq?pms+#7Jopa>PAtf7)RDt7#0ckkT$z)FmjRI~_d4MK%L0Jgwn8A1r^ z?G|fw?AzDY#rM9MGA_GZUT@l~rxH4A=ft1f*dohH;y{ueA7Rs!&U}YaZ%An^&DB*1 z0(4Q5jVDZoW5QZOtzJjSfCoDRp6(7k<-?FqCZxkL54C3VIHfE~279~IIvv8f7S^iQ*)ucda5Swy*MK6_Yp{z<{|H9 z>>V^14aS_=SRl(v`a?qqm?>H{+oZNSV5XFw6JUY>>!h=gf#S(-A7Sb^b$3Ct7BR_F z7f&krX5skwJI5)HxBEm2j0$PgLykvw=L{jtez$c2o6TdqEwHo%HB{bL*Xr%wIQc1#k;yyzd zc*=$F{v?iSBEtZv&CpHZcH)d4BM6dJL=a)RdnjwLCIcxj2!wPUu#*GpDpZaSZv0TL zoh4jVkqVYP%_;MOxRxLTiAHk$;UVd0#MzYwr<5fMoQ$mXMs4@*-DNcBQ5FR%h-tUm z?C$Ncx3|k@-+qf)7&95CWO+`l$dM*SXBncN(5%JeWyx}IuMO3|!^?(7pGVJ)F7a#S2Kx3a{r+hfw}kt{Z;H|I!$CV%|h_X*7ev3Qw0YOoZB zOojvYcK3;xV}7B-^4e+c-n&O6OIABI0*M2}{5sI-n91G_=#tDD7TXb@fAb=L^H<*F z-1-9Bdq@1~x4+N9!2#E=Qgtxg{DAf7zMM)?S6&}RYqTz% z7f9tx<`Y<@6h-C+(k<3Y#=6c$Q55{@7e2?|`8)q5KfC?`|K0!4Woc!F|Lkx5%bYuN znsHeJ3s{E#~KBvOEd5{WEnF2PP zmV4RL%r{a7_2JF`7ba zDvgxKMi^3r%f~g#(`wUK9 zshW3lECw;%pw?=rT8&-_Lm0<#wn`y`2pM@tR^gK8d^Dyg3gX5bB6N=BQL{-J9(3$d6tp!tYj&X;B z0E$V$xHlkdG>K~sw?334uob1py*;HQWpkAuKi%PWe<=FLhW5%8v<&&~y-jZHjTsK= z)Rxa-gM<&ZpYi1V1IFW2)E3S$Naont+v3K}jN1MPlhqh!b^hd5imDG7PHN1ZI>X0Z zDc*lE#2QQ7tc$pPjx>+?#@zyepj7MB&o1%!V2|xPhCEXQbC-zcmw2|n%kD=5Cq+Gf zj;L0n=pIrW?1L_xVVVfh0tA)YyFYle=ILEQ-J~q)obHPukDlz(nQzdHU}-L9(#u4V zX9PirP$9zPVtsXibLT^ze>|dAi!o`&!)M3TlaTMfdyn125mBQ&JyS48=qmU?}2vkMk zkXShrB1m(?Pahn){ii|rj>9a$u40HQ*see6al;zW8Y?AADn}Xd?U(9^lv40)f6UX} zAqeYu=9LG6HAv(qItZgobK}v`G+7IzoJ#guYus?V7w#xZ%kAgg={*c&B}F=;E>x<2 zL9NEtQ1krh07m-+!V*eH1F7KhdJ|tdQ#RLguS4ufRci+*(9vhDANhWpodT%aEOCxVkDFzXtgP_Au`JxZAB61CHx$b3=lE^D-i@3>r@ScKyiGy&$A~_ zXm>iywdWZQhQvusXMUb^GND;(&}cN#g~pU6frLO9;#x!y2>PQ8X-b}NbzK*4FYQ@x`&k7 z64V<+NklpvqGZ6_!V-hyV@9JPkuCTae(80V+6}t>0f`;)^yyR9R~I<9oN#VA=Admk z?8L0JLzFFM-Ali&r|YqjY8BF%Y8s37GZ&S&2RI|U${5eNz6*-7^f`l>eTP1OaF3Y{ zC|7eQK@d=Sm8+^4$@9$ZV{6^8dFCj^R+r9UU8<=$q8mgP^p5s6=Pp5C{;!)+nU z5vrU}Qw8KhOp$wISLb082!Tbjzkf`i6iR>;8eyI2gaxumN|~idTT%85;OS#%jMaW7 zPE%wltw!L7#65kglFY>krWj+<#!whNE$n9dwb~Otid9`^KO1RJd{4&CW@E5F{aT(#tp)T zMa|74gd}Q?kZ~QAOH|T?I3{X#P_=~E2B;`OHX9`QBKcs9j2lj|L&b=s4RMo5mdH59 zq?#-(!5WfI=#yGS+-#tW94iBYxh8=}z^n*SNrZ|M!lX{5gg=Z7wtGNv+$9hS9ViU$ zkQPdM4gShd<p~o6QRssC^X+2>-F;fECXL1%)>zvcSz$}V zrSnUiJHO837e~k>!=O+}gZff~u-Wn`_pD20#fd|3n%Gy{sOli*3RL!cKNVbG^9CtTdt!5IH9vrD8hbs`!`uGrqftLe!9p6vP$H^1uhp>cUFq1K_ z5)4mWsUBC|*LbdlXtyDqP#*3Pm<(eTwMGIeU@{y-nv(DD60fXbr5oU#f;&|2Q%paG z|IpKpav+_bNh1mAjdJo*bAEM>v&#)Ef;-QSI5_OlRGQ1zP7y~T$Eo4zZlB@)A*#&1 z*o7de*BJK)SRqJSa|i*tv{)@Dv>>k62$LAJCLO0}<2|3Wc67PIV1)9CPSq7M(?Y~p z2%>;E4nazE=>UtO&}8G3yrD2POKz;A)F{PxG$D)=k|g2i@Q9))IJLGy7zE697HQ6P zkOCUDh#-nkN|BGc6cdPR39IvUu$J5oojGAQ%w#`QD`{7 z-XS?qoLQS=d$YyzQk!~E^6J%9Lb=YX7naD!6TbFKpY?G%<h;9=lH?^9UafKY z{5mTOZT5R3+8ZyierkoAcQ@(p9nxww2z5+ZhRijaG+K3*SLS(Iju{^v5(kz){nKxf zNX_Q+08TJR5k?~jP%fbO^;H=qQ>CZ*^ek?GQb zW5!ZQFRoG1kA$1y(s@Rijj;I$Q;b2E2%|kPXR$?&2?VArDe{aF8Iqhb8&PB#SvtWq znp1$Ux*P*sPAN>n?@@iCaGS=eO2i|TF#rG{07*naRQ9$)Y++XT`2lfP2u;JK4?Qjp zxwF&*h}Qb=&(o@WqEyjiK}-kSZPkIQ3L;;GeVT%6OjR^hZyLb3oXMV`t$7d^Aqm33 z{Jf{&Ki{AJ#P!?%%HP;~|J#55jl6&OIj!xQGYG;b0X|W}PI;&~uB#zzHN;oAKpuo> z?+EPzjY}ZoIB|n$RTo6~4TYE@m{$0O?+uRJrWC|UOc;c&-D$0JYYmhu1bmRPQWAwB zO3peiS{p|nvkvWW#2trFI(|0O3f@{*>jy&knGr$KT4Ff#?=c9FDg+8wd>D(Oa7lep zASe-9fs)iBNuXjR1tNEnbV4{90zzQ239Fri<+Wvga(j!scML|O+RIF$7@0^0(lFZG zg?vJuF49X4?WF}K!;u?SU06VC!+J~7HUmDseG`%Q$R{JurwzPxu|bN`C12V&S5it$ z>Esoo$ZY|mEyqd`%%34{E^zVc6}EzcbW#u`iAUjQm$fc9MUf(CBna&iz#yuDlmu8N zg8@aF0~(PHG3gLJJS0wch-8T<3v7`S)Ej6a8Rrt(XHiK55yTMHF)Aib5~3tQMai_t zv%WJUg#cqIbI0oywFqIH)Su4Am~2FmrIbiak&=%~bTL8aO%Mv5j>yR=CMhb3F+~gG zxw;5XHN+xyhDj~Dbln>vC1EXbrfy1+_KvaH2pL(@(SUGa6x&8SwS&L0gJ6U+2HChs*p}w?Y$G76#UPohwn-BtZHe&bXd4j*qSatF+Ce+ z#my&ZBfeyE_C|PVeT12HcPk0cSz&PU=f3zdOifsA^`@)G`dCwaR%;!~I~{PA-d}(d z_rTq$>CdJy(YnHBnk3Zfgv+aBd%MUWCoc+;xh9bc$od1!WJ0>TL$tJt4ypn8PhBTI z6F{jAEA5!KuP(FLjKCW1JnQmgcfhZ_zDg|N^iq>{P4MUM_4wT7^XNQh*dOu6)zb_I zV{D^F5VcVP$|5K2_P~QX#XzvIvWT7UpwpD3NYFBbKw-_q3kZbBFeGj?5OEEgM3k9! z9S&oh0D+&Qu@)BQoMUxwloLwHd^@B+%xEVut;J<1a=>6v&O{AKniuqXeRSdII&qS4 zaCA(s*X8ont7Q3@BuX5@uUrx?Oi9)s5+-#9qmGF=`#gU57+DqwDfr;J^P?~_ zz^WJ_B_DoxpRfM%TfB7PG#}o1L3c2r)vEEi&t2i%#ym<&o*j%if9f;Ft z^(8RVbqlW8(B24eIut%F+MRr@@p*#9cx1ey=|WK!WLfHf#4yDABC#yI?}*=n&h*eu z5&s}?QoxZ?#7RP)yScC+2>i^+?EMJgemChvczHugJ3#v?vC%u^TSc(r_@Ui8jBNx9o2UP zt_YdU=m`(7RPo_N(SYloxVUPkXU(*t5!G{6#Y8m+1ZM3g zi0wa@*DneXe|_!3h4jDv{onuHZ~ehHclVw@{Wk|Yn}4IoCaubo!|2LjZnnr=(QCaV zFDPe&?6|7J4ax}wK@d`}Hwohy;U!_GN*e(CKm@8fU~~ zN|*F#jgpEmim}>|Q#$3DvP4_=ds*aYYf({+L|SZF5XLcaQnN`YMI&}Y>RWqVb`N?e zUub9)g?8^H3?u4|1~MEYBMaGte9(jO#Id=ga+N-whJkdPXCY=_3ivq^K|bp98-M)@ z|Ng)8*V*n)c=x9t^S^)RBTC&wgf5YIvD@Qo7drgyfAz~mNn*eB#ECFY*5UT?Sea zBu$Der^s_u7*?V`XdoSqDANoXETYm89W~&!(`)wbgT5GN1B`6YiAr8M*XG{69g0bW z2_qKcl+RyX=GMm#=uQ;D!a7zel3L^rBq`8(!fPAzc7A@2@85VR6dNQ-j8bz*F?kkY9dng{`d}w#Ef> z=g*Ldm_%3x-64}vM$&4c;>2yz3gz})L|24av{d9GU_Uqf;m>wOHdYjN18EheZ@70q z6G^R3+*l&-PB?#RiLbtWk*E7(o<2XO7?0haXw|3kv{lhiWI2=W5FsV?g%(PlI9!C2 zRE%mdC`Ayesr+Vjo$Q!Q`Tr;Wy^@GUh$*6XvS`uTIByMq@HvFrbuXEA9A<|c)xNW{ z`4l@v;ATVZv&w~OF<0dw)q(Glsj6_0Q>w!>K2=xsLetkazWX3fJjBfI8}1C&);MQl z-!XDLYw3(NEg(u%R70(-p$~RYI-|%-;>9IO6uRGoA}1g82^W^9Qkk>Ynb9In-p{pm z%(c@kl(jtC?lRwuxc9tZ_i(^m5-=EL9Q7th5pX=nSzoLd?f`8JwJ>1kaKO9QA2AwESX`*{n_qjA+`#cL1r^X< z=43;#@=*%zj(v_F#_j^Q9Oc(|XhGR+tS(Y&w^^pR?ARvrf2T6u8NnBvdk{b^X z=%<>Z^s81{f-qo`<_wO;6q7Ma%OMBdA)C8LOh#kYmYS@#8(>N%!!d)=gj=_tG9Hb% zaB6`^k6-ZUd6#+|5hy`k6lmkRZjh2&*f?{Ft-~=#4|b_H5|-v0TsX7D)r*>+T)%^~ zhF3S%*xNtkn;+dlD8*-AyGRnp+0Ez;_HYR9Mlm`q) z6AY5(oG*v9-x5MhlY6(Xs^NdfU~uMy#yMXj2*Q9cbRr>TsnOcaUb@vM{CO(TO8LQd zMOi6bNj3HSQb9ndLdyS_y*GQ3ExXS9etVxWr<$woTz9_ReY+dY1{y;P07ndTP>?lP zl=LDiWctC5Fzv8kEI;Vg4$C2$cGy_#b+t`TNd+R$cx<0V2F|; zCaZG3P@0`SLL@n|7^Ae}L~V|_`YgSJA%YM!>XPO;Mo2^u6NC{(IzbnyHP{7LfcSP` zUD~dzQa)gTHXHx!eB%_XQK-Ctz_&CdjiZVQ1XeLm8)d;!Q}!sQa`m|Xp3c^~w=IEI zArYRaXrso(jxt_b%G5N5PT!Pi{BzISICW8u#WMSEwt(bV+_p41_eNDgVweU@K`9P{ z6jjbvddDHk850NmIBKgr9z%aZub&nm$FBeUSAVq!eDxpvFTeYpKl+{D{8sfsv%5( zSGNj9I5h|1NrWHTcBm|q5T_|_VaafYWKj7=y~fhSPLAdE&D zMNGowl{!)2i)Rn^kokc6(m5uR31?b{zxh``k5A6V(+B2;+7&yS6QZc@x;fe*s?#C( z<0vdH*o1*k82CufC(9E)_S`C0ufIwVMO?dlk(&=T`TZX}#hX8k_B>RQ+OCEtIWZe? zVJYU({T-_pZ`agMVHzPnY?vF@^BkGF_)Ekl0 zNe3AOghKHA#YGMuZINx>Vdm5TzrV(-*H-ZwbsoL_jO(*Ld&v_P&d$&}9q?%D87o?H zuXC4~xvRWfsW_!9y;*@FM=g42MSpp1*X0L8r&f z`&*d3K8@BX^x<7zxPFy1_IU5zC!CKAo#6qGJ8fQg{WXHQCFH2dtv~uIwSI$qf1UZ+ zOT2t_i91_EuAg7z&38w14ih^!6glc1RGm72bT}p(j)-TPJl+;;1`@*zo;M4gTW86s|mYp3i0&=CHCfuOFq6ujCk4Ogzu`*=FBb;9(D{{zEPz6$e z5+6-YK7vZRClUC9wY>p7_3r+4n+#(D-R!_}wu>OR#r|YbqKf`u!z|!e6)B;0S z<;>64i9^ZTZ~PF?6J*Jl7hisX<9M=p#`Ap!%BOqujI)b% z((#xiRjjXnh%yG>^SFHR6i=T#<6w7-3#VpSnw=qtT0{}7Klp(8nHiqDdXi-2vXq^zb%Jn8+$)vGEbRwMQ({VUKI16U(xaqnmFrEoSqE^+S;Dgt zv?{NVeZ&+5uoAJhc+rJIAt~~lBuT3MXef<|v4j4~#-eh6326t!rH~}aglku?@bCPc zzsJ_*hWWj({_kRLVTCV#`E{0-R@gl_;;Uc#GdledB5WaQE$SyuBc))tw}mNkl#$>E zXgtfv2x@3$z|-Ih=Ny=WGyB&@q>pH+wNo7~$Nb9C*v;_-((yyNuApalNfBEnIt%I+> zyZz7p;Xn8fFZXwM|9%koLOZUxDhjeJ0jUY9!&N&pR-i-#K?J^E4VD)g(ov2Wxi;=c zk^gk4FK6yf1{rHyzL4zO&jOPi0FvPe@$qziC zwINr=NDy)8vA?&&pM2x%Y;EsgbRo{pDm^!|YL-vV8 z&fK|kO9)-y2}7oGJY!vR4-Sqv><$~X&4q0kl zudb*J71?L5@t@v)J>m!l;G(Mt)z944kLnwv8W|h%2!HB zW2S+JVRgAq{&d3Q_73m7dnh`+0iO+qv}z%5Z`|XLjvmtP_Bem(yjjS0#JIi9xBhIC zz5O;P8>d;F3waX4{7lTmXl4V${jAH~TkGP%U60W~5EXqIjgVdk7Ha~3To9QNw{LyO z#*^E01}XKlO@tvoc*r;YpS!3$#RRjo%$S*GK&LaLySKrc+a0pJU?rSkRwmS?VzCu5 zztH3;(FBn{<=ZkvC~e|y>4-)dGA&3`+a1u_i9Tp|{J74WJp+8+eSCz&tO#o%(w}wy z3Lh;{0fNY96?&<^D@+Dr=;;f_}Wm64Z)?d*HF1HDXq zD)bIln3S^{<>Bn!A7L;?BDAikY*ViscZ*sR2a-rCu3wnr&0AZflL<4S$DCL2^B-U3 zpf@4Qa>Br4ex^=)$!9Q5XtnAzXJ`50{XKRLu_RembJ%E*xB6R(wR99505z5 z+o7>?0Vxblw2p_5*C@I>giDga!4Y9|1}~6EX&|QADnDYI@8|7nbM`2fT3M z1f7ErA!20IAT1QL%_hTMPEBUC4-a_d!V1O@5rN0`GfSl7lu=hR9^@=61}H7TtFf`R zPS{$av9v^*Df*owRwR7<`YPSC^E_)OY}(kpmlk>H>Pi07fA?2do}Z`F@AK_9mg#i+T)1$a>(?%F`O-zc{hjadgYQZ{^~u+G z_vSr*`*)sIoky)fnCUvV3>kM;8wJ9Ony5lm;wD-tDD2vkC3PByn&XDYjiqXp1IN=2 zrJ-;`>{39U=M+Uj9K~p3eW6NvmaB%4<&21&sv=_S(0rj3S1w)R@BWQn=EL{j5#Rsz zA2K`N;8*|h7kJ^htK56=fIs{0pK~zKctM?+6KC)|Nq=t>o#h|`XwDMUXE2@zo@YB6 z$rzIi(c=*!8G^Dhz^R3XOkrJu&$K|OI?WZ*Gkx}=?7EZz-B8h6jZxK)Aw?DY%AY9# z6=lG8U~zd5()quXg-&^EYSgq|S`1M5hNCf9}}Hx@yVWh+p+Hm&F6^6ap&bQB8DllZ=+FZsTQCoP8;&nFB# z*SgfiVZfviJih%Q7tTg}=}Rx0G%d{b_9HK&0SJ-hxkW7yq9`(#fEmV~2KJ1<0L_w)igTkE7fX{gPCmS`b` z8XPfH1KRDj+1=Ztb95+_3aqX^lF6XQ_uu#ygVBgDe(A4p<>EPR-??)vFuA!JC*5e2 z#t7Ro$5{TUQi{SEcNicH0~Y6+;_S)-f7IURt+x(XK7ENO3>Z23PZ$Q6Rukz_-Hg?==0Xw z@A0SKdV{Fe9x`qcL>b*~U(}i-TCFBg07u;+c~PL0=F-_EE}WXD-coed z_mM(UZ?q6n5F{z-B;icmXW_~c7f;Nvqb7L1hac7PBM)y}FzEMKICqj(tBy7!L{P&Z z$kLR0=#lxhSoOUa;cL<)BNB?&uC4IGnK=SaGATCbj&q0b>uTt?4BKJdde3;COWJHaKupUp*c;F*i)?%7CbL=%`GB1U&YgR*=74!xpo;$Zhp6AR&0-a{$I;eyu zN+mVnN)lc91UOXC6&|JkmXK~nL|~r>(sfVlK&^1yN?cdLQpHR)V}g^b6gWOMmSIv6tP_qqN41J2CH?2c2y%jdbg z(jo|3)S6BDqYR4Fei$K820~%g|FqVYEN03%CTpf9gq0Q724-pjudL2<^YJblha*;& z=GfRBvbNnJ%N3KXKn6LJRPpYE18NdxLfCEh8BG#S&-whd&p*dtlJn-nBU0nspj~HM z=!EmjF)v?QB$PQlogvFkl2)J#PA}DXWwmK~t%A^6(q*!23l$H~3kZUMLOInZHzTEVnaEqlK&gJ|`#!$sljV8kFH(9? z+2)Bw?DH&l@yF7Wf*|72qX+yCzxj`Nw)TXrjZON!K93*VB$hdEegAE`-7d1WNNeR3 zzEJdcHc?4p*$k~&!nqYIm0xuRGOM7MWf+-)9|8qPV;K&*0AceDBYdRqSB8Dc`H*FK z!EiVx&ok$vB0iF!8yt&7e00vT`mE(%#ugBz$zUb-e|*!p_xn*AR!O(A?_)b!l^@V? ztfEA098g*63s(EPocX}bU%JDfk_vWbm5>t8^D%C2rJP-{AJe1ia{q*1KP^Ch%+)`9 z8prj8MzC;^;o+fepGtx8HFz2&3}bu*zCDb+0#kR1xLe5O5UBQoN)@K0g@8m9!s^&p zn;}OfBk%*fpoaYcEB&VtWW=;)TU@?+RrY#awhy10M^D$p)6GNn_S-CjkFEGHxtJiq$>Sgod^_THTg-D-?W?eHLD~ycUZcoJ4WX&38`60sd&^?F3+s_!a zC&KIR8iR9x$i|EpBHsA+H+izQ$;Ok1L>HFHv_*{e+a2D|y3Ehb(QMSH*J7)8QS!h= z8L)7DY@0ILKw!1gb&2Y_%+eTTwcCX?2b`oSGg)T5AQ0MEZl@OpNZ+>2`>Eo+wH`;C zUGBX3CP|u6yZmzucPG?NU*KRz@b&lC@Vx;>)DdT1C-1G36-P*+Tsz-((UejwET5ur zYL@O$Gpe8C&_6>q6XB_pi)ZFoU5UB(;2A}pplS^+URh=5AY$im;F2s*g|a4t>4an= zDU@O~p3s`}P=-nlI?oG)uqsnl!AOxMDavRrpIhL$GxMBG3x2rklWS{M7KA>aQAJKG z6kI#K%!$P&UN)vE>~r-UH9;FUuyr>J{T6ij+UWE2wAB4pqrj6sX?@Tkr#%Ej`d zM?!gj8y1HO#jw-_x+8%n9G^YI}6%Zip@HGhHD6~a%sh?lokg)4p zYhBUMaHg2kg2oDNm`aN&8NUDkAOJ~3K~$wiV6;LNIZ{gEC_rU7h1L#;vD6;lvs`!+ z)yS0O$>tGPPA+h5b%Afczd;a3%r;{lKRZB%5#uCB4GvkEmDJQ2F>Z4AVV8T4xB2B? zdX0lra4^Vix64|b;iE_<6I5Q{#SwO{VEX-)35=AI2U~rLqCgnKg|kbn?+uvbmI}Kx z7jbH-$=zp1q=n+rLLGzkPVs$@-J#^k=03mi8~>Q7wM_lW&ypo6((@>Q2RkD=ea-I9 z9n_@D(IBHAj!0D#Ukdj3x+KFM8~5+=-`)PMSXf+ybFb6W8RcA4*{!i=Y95dFMm*T+ zIYmLqH{abxYE3p8^5N}uu3S99wdEFF8PFLR?mc`=I_fjq+$FsKgfuG$fi=G8qg26Y zG(;=IAg}TK`8n#%CIvk@{V^v`%oCb~gNHXToed&=#O?QffGILIpEz^6Fd#1q!Z1b% z!z4**)Egwpm>>wrazzjZpbD}qC5mg-px5`9Bq?!yixv~sKlnCrx<`HPDswAK^v5}W z`0d;Ddn3FcL!~1^GM>9K#u(Vz>yo88V3=Q=VfDf}+Wirkf>3Jy#lQS2SvsQA8?bxO zq1Wv&Tlbla2CQ#xk>rNSc*qBLo}wK++Dxl>z!^UpL!lH_xn+tvOgn833~|HfN@+(g zw9@UyRr;lhRY{#PQ2B~g-N9q?Q9?+H!qTmUGepi^A>w({1ieJr0X*Ng-B~Gk`1lF$ z-gpNY)Cr;*B8GqRzy2=CWCUT8v5sjjoF+ok+ufqb5`+lw8*|K_IE|12X_jMjfiRv^ z@k&`)Xt8j9iKh=9qLoB=A^mQjGQ$_fiu7o07*A3{AI6gjMkzdBQmcjdzI_(jlrv{j zkCSPa(#1ecrBXF5x$NASHrCm^9O|}?@DgFHs%PnAQc54&=QWM&#+~(2`qlS39T0bO zhR0r8hEXe(ZDV2Cm9g)ytMkFm{@N~;u1qUU)#cKa!Qo#xeSRXZpB5lL=9-HlH5rWu zI*5yS`9e@Ag(?bEIzc64j2D3PZJSmYFbZ^rprBOjF?s6LPdry>xCJh(8rDbGU#UnR zgO-TAL=?-GF6elc`x|ZA?Gb0st%ytQzJBm{Pbj58N}8=%UV8C53-faXfyeCZtPw(r z!XXd6!HB_N$kM_BQW_zPA&uCo`+RWoq1hNkqG+DPcrjC%PKgl#vgSL9UDs+3d~h8e zN)s{}R1;;Ds)aTPQ%qffwPw~A40i-?zw;h9-oGh4FQhI7jJKuVy* zGDOtmbTeS5e~3sX#7hxruFZIo3#)o%H@I-7bA!iK?Lo@M=05k|yMdP+ zL1T%9<$0H-h`7;03!gMiDGEgphR7ghl4`OfB}oe!o>ekg z+c+RLiirVbBu08lKd_++cJlN>c?~m}jxY{R0YTf0-T8uZ-u-~F7 z2aRp0*Com&Y_b{7G;QHg9%jPMO;iVrTW_NJ)9%w_tl!Fz%y!m9^}EXARUj~~BM{aj zgy#{)LG{|Hpu}{yOOCxy`5BHEMZ&s>zyIifFz`4UDZYPmi-m^ArPXDgn@w21_db3; zMmai!(ZNbc_*_Tv@7UEecs!ULws3hJ%6K=bld#1lIgaDLi45B$QQG zveYo!35ny7@n{GRwaxO3Y%;+QB7(UYvO$j`FVN0d&`3$)d1QW_+VTZH{@N!Q^|~Ci zdwlrB4)8`%$gQVsM!8{SzJ-)97ZqGN(W2KKb2!@P(sQ5UFfp`8IgObn7f-f$)IGwu z?uQ!mnY24r-nLdJT3kf0I<|CQ)fKTtRIZXi0P&UI<%^YgR!PJ zOh{C~&cq{&C1E0&Dp(JYz`GzB3e+L{ZG3+a?f#bda#S zvqN0JNEn8s;}K_IgwcNq@)%+JkmY4sE;F#Pc5`wY5An{5Jt?-&e?*$oKwP3RFoF=_LKFk)-sUAs<%W zJx%O$MTp9*(D!|!D4K!-!pGE4AnUV)wTR{O=ZRNNvb(;^V5rCgj}XP+=ztfFcWNxlSmKWqIC(oSs4|dk(%Ei-!QsL`Wl*;M%Ms(V30%^~GiLl~3Mq`vl1`$Rn zd?}cz*Qv!pC6OxxmD#d3(`P8FIO)LJYU56UnU54JuK2(e4rQS@?RMB?zbX{W6zl@0 zU|QM+l!u70GaA~IL;ocJ<;s$>OM+7ib@bG-V`Qm(#}raM4>yADI{9VxF$KYXlCPf@ zAV22Hi^vozD=-2t2=L?BHYpYs<aTF&EXe`oQAqU2)o8XWdg+opaC{4F}2yicne_IwL*WXOb0g=^R4TL|$Zgo=2lu7o|ISd1tu!9HgwqEy_zN8?co#k;5gQo-o8= zNDxMhj{4vQL{Wq%O4&gh@U+o1GfueLH}zw6=$p5G3P1jJCP7;`7-T&#<)EWKuvY_R+nRkc3yy_`G)Y zCEj^-fJlc3;|?jC9TSBCabuQ3)(GnJ=#gRZ!6cpkUzZ&Bn0W8*RB2grC9m1QiRT%ofy#EV<(9`-ou3|L;6rJrfy#tdR^ zndRkKjvjB~HCNCwB2$vZxj77iK@s6KT69yx&})h2$||cXH8!@}h{hr!u5oj14IR{Y z_-L1IC!uxvECpV5sOUmf^E*{WUncH9@~0p8c(V;kO4IQ*AcbAYrJQCu$v_*TT7>jv z)zr{RGZ~ICN)tEhc!8aDvJTu1VHeYt6@~#}7*vO7iHwyk_;QDo#Z1{P60QqUA*{kM zPIBIUa9}+@v?d$&h;@R<#%#R%9X9X$fMz5r^sds>7vTFLs>oeuZz|&p7BN*?qY6h0 z5S9w69c@B5vomALq()TlQx#REF2BPIrRTBldCuU^?hi|O1K|aP^;wQ?-J_U{=(We} zO#*iJPGYnn&kZt+09dRC6q$fx0x5)Mf+#ZP8v$Q_{dt7+*zS&5Zu&en1fxu;OP-*p*b~Qqo3pmB+vFI zd|&Kyak_M@B3h=k@$9c?s$Z_li!FG=#*UVpfnLy_pY;GY>ED+b~ET33r`>>DpBz`0a zJV81fu(!TJtrn9^67~;A(nRhf-BbrnI9j4rzB(r5Z$Nss@GfO&wV~>67>AY%0Y+&w z!Vas45m}lzNpP#m>G@UxvpmnVveeu2FTcv(ew)M1hdj+DXkdP6iL^apc+^GbyW}PS z84%7c5zQ^3B@9Nkdu5-8&1XC*F+$Pn_ZW7%h$3Ni^%U*>J)|i>*si$7&dB+`2PStJ zy+EmgBu!CyXgfcuG+Zv96P0a%Dfg(b>t3s}GX!PFNlIzgzENdZa`aho6JZKw*E((B0HzwbaT#T0b@ z$-RDBfc%)tn-2>iJT1K`8sZB{5o+*!OpzjVhNWF-Ysyd_&PHKmgz-bSDI~&ZFa?Nk z+JGzfjI=d!#c3=Z$IGE8BnZzY74sMQ*Eb%LB)@O|$`?My%P(9)`Ze?3gF|uDPkHm5 zyX3`9j4lWRYhY;S9^m9si#YJmleU%sV%qitl`I$d>;C%$!DOTeT~EjIf7I zCAp0&4&+CbfGlF{Hou^vl{ld2Sk-So=Xf+iCJA+?CQ@}qjX|tIzRw|N7_6)7_r<`mH`U*N2R9!QmjGkRh2U2o}!r>E~YID_{Ie z{L63N;n^TWZx8W&pJ#_7I^6`Kd4A~^FY(#euAATb`Um1bETF~{=FVT|FMshB7Uo)f z^^GU2^&|~F!1L=|{nXF%H$HQYcOUKZohJz&Y-i}!G9&HV*_`o+w7rMFxPlN?E>tYc zPE9Y^B9C^B30M8>LMeZ=gq zOiVbok10_zsx3pBmspvrn}<&(VrH?9Cr2o)sn>m078{6Bi)-gs*myb;1C`N=teRlZi1EYH zsLnn|Z47gf&!?^|@Mvw1LGO^d$Ph)rsCUF5>2v3ap;@mns{~8)8leJa7UvmGJZ|6K zB=RL%_~^KSOccGr5aY$R5N*}?rB{EJ#pcWW*8lbgtS&V<+qlN=#v@cda&Xw*^tF@sTp$|ij5`Ey*qdX`qJ$==}+_iw((k(ltQ z*FM2#U;i{`&z(igtKVQ0X9^_#!NVQ+$oBmCAp z;oJiFmi{>yCP(WOP8vGn0Gi!j;&8^^C{vLRhzpeofY;iy!m>Qo4qN0q=H zf{MXFnWs2`0o&m!!P3%asl2)AT^t9CtN9=IJ(TZXmQd33tjVrYR6Ydd&*DIxAMq9Y zNxgnrfc*bmLKzR=6rz-t^tJS~G$zMLAER>+1{nz3)>B{?tt~c$v1WJnhdn@7e`hzK zSDyQJ18Vy+t03i5K`)L9rH#V(L(KAv{Ql#8@!dx^%!#H%3y=M7K`s_pSUEv=d!IDR znXNVH9Ca%S$)kfYHy;0xW-N&#PfQ9;-?W68`2=3Qg%Hj}On7MHp@p<O3v2EqtNmZ1X=R6k zBIWdagTMKUe~It@`S0%8gZ%=7#=IvvYHsn_C&HcZO&}j>ZKa|I8;zvI)A|VP{v; z?X;OclOymM_bipBRttHscEGT&SZXctV81YG;i9;Cf0yKNm&L{$5B78Xl}loGt;4N% zo-r5C@`DFGL9K4GS}1O944@F)d$>cqv_w9cpu-juUFY`3fMVtp?cNx2N$7`s`{oWs zdmpI+o^}l8{t^C(OFU_3O!j)r%$(v;TXH6d2o}%r_#i>HGlWsB)SGT`7U>7*(NW6O(_I% zBepaM&nvMxms|*Ht=O(D-?v+_+yKX#9PTW&N$#;i`uKhQMW2c(Qg(c3I!|*hti*ir zg&FDrynO8f(hGRHvCjv$ZnMw~*xhLH^{;&mgFC>*@c~s2aqI?-+sDTJ+Ns;JOPI>d zj2qsp4A$(PlRr{qRLV7F=fyo(OLMcRo|Ily%qXRhI^)-W?Qb(l3%>XEyZp+RzrfW? z7g$`HXKU{WjAE~o@=w2chtzoFL=00yf0&asB3`(1j&~m)@UQ;(dwlWpFR@gQxIY{d z1wPss>a#7a>yII0oUB9xkK zqCm1d7ZG?cR}a`e?2(y(j&5;xb7&r}b?6l}TD3Z1t4T2&0+Qiaabs(n?kE?x?(g&J z=dR-)>+WW`V!xZRc93y@w}9r1MYAIx&vh7VE@i(HX$+pWw3mLT$BG=X92dND{VF$Z z9I&;vOQ>PKxyY-Ze%(CT*cOksjtD&%CLU31o?fR}N!Qs zgner!J3eAA)?7Zbz@#&#vsExLqMA1dqX;2zrh1YvvgUZ`!m80BaH32Ux%H$9!;qrL zNnJO@^E?Vw&NYINK9k{qV%X;F@)$b)}C!}_RJYR`O1r2y?BPn z?oGsag-^craZ`&taqHGiyGJn7`6;81brVap+c-qtbxpx38VN_)0qJ{{Cs_IY6|OkY zZhtFnFp^41D-aoH=xR#n%9>0Sk>*PGLG&6Luz_U9XMKuf07bl)^1Atr(3 z%ISIY`p2$_&7FN_>K?m&P1sr>o?mpbu;o0WaLIW=(mgj8pj_0RC#G#c309KV{(L!*XfW1A_rxXo`KoBA zi7k8@hF7nj=lTm5S>M=UIGixIxWJ#k@d4vB$MZv!A25`Xkra4=M-Ya>_kGgIm|~O= z)@tB;Abo@pZf@SWjC!^xsC2W9rCsG|jxKV7dX4fEL3P`B28@vy8K5&o((AL(tig$M z>_6?1rwSno+pd=$e&CZQW4G}=43hE%nG7dL*(7SUY?3G?lTm^}(jE!EakC@*#U(NsVq~56AmvX!*dth2AXN2yB-i7e2w_GMUzhbc~*iQR6YPIb&7L z%yjN!s_U*%hL0ElR_ZZgI$SO*M9lub0js57kEiR_(ed0r5=NnG-n zX^s^k)ggN99*!3x*3}NGqey%E2vMHIqDodu zR8ULl+WZ1h2{K5^Zjr7AG|jPHYY;|O2fr+(FtIYIr8kMzC9j%_c_5w6{`5XdbssAg zT4WjDf8#soBEi!Vl?+Ta?ug#rm}1a3X)JJTjNsizhb#sK<93^wR*jcmzJgLOu`wD5xp;wB&YYyL0;0twv{s}^#wT8T zg(quU1amXIwsM*I`4&cP0+6IR=gzDk(Cnlh&2!f{ckVO~4wdyS5>sbvt*t1AC^Urx zRL(EHbP|1VWQxgHeERw-ak|4hlO4ji$;I=h`P?U7V9?$*!-f!7&aXgifww+<%COVr zg{x8;?K~WZLz)E;ra86Y#$Bz>c4pdSxi`(o1t6G;tMRYt?at8lqu)< zT@@y!(v#H2t2YhMHPy?P>d!CMdsrP!OX%E+gp3YJ`9d_ING|$)3r6;zwrTU>znMKSZ43Z z2TVpoZr{7d!O?)5AKnz5-oVWz$SK{&#WgTh@_2lYlr$i1${=Fbyyg1;$bK&qVBz7r zaN@hpT;UbfcU%-yv@2BEi40=O~QroRu`GLYw1Z z*Un^?)GO@$PH9!u8&w@^UB+mpajOJ+OQ2Q?4`T{SGvjhj)7GKditgCJ=;YSRd$P)l z6^*O3RMOfN=W-gVDa{xQev+@B79c<7nvH5o7**&ZGl>$y4?T>^geg*rEGJJV=wgh> zGpj_SHHea?P)gX@ASE19P||`dA}jHHI|wY0Hqq0Ls~nV+AxCu*qLOYy$VyQvh&hQRId=RSddAd?P?cq@$dAOEEa= z5&2d&F-=oY1`~+t>lMeSaYlM%M&JiATKZ0{$tI{C5{*RTF&U1D!Wv;zBN-0K^8%zK zpXAgvXy3O7y#cgU&XGYt==-+bHU_NmCetN_q~r_ZTyV=oyL$bxSTTK%>E3YXQw1>` zFEq;ET^23&JxYm22!!EaZ=a3vL=0<^Z@lpy-NA_acW?3N&U-w4^Z>05vkOa(UU{6y z?so36gI<(3E~b*frE0b|Kl+R`QusDeC=tBrjWgw_3l|znFhW;em?cI$XW}65+~K@vZmP*x%kH^0a6~f}NgbH=E(-FP~$7ah^_ILn*~PG4I`4quuUt zef1=V?E&xKTBjC81c6m!>K%44PK-kfgFr)(fhrJrM%w97u_Rad6A?F z#yQ+r>$%wk@O=+Iklf#!z_1IQ0|E&>9a4{cx`$(A5Hj2vu-zVF3Qet6=fRUbCTRvh zb~GVRGH%{or$0=IqmbSGE^mLhMlBA>b%FFl4%Y^3_6z6f@KFiTA}y@>X{}C@7c4ZJ zQkk|JWry{^EJ^EM-)9gbEJ!w;A@jsLFKH?zt?_EJ);gU<6r~61a|`6j--xmk4{F zXVn*r!mepgQWQC!6x3@GX;x4uTd*jt8TNaGtufjNKD_;ec0Z>vJ4;tbWcbWAd{m)G zv|yBEbOs09d3FTakmf$3K0~KFN%$*-piEJsEI;9GE()xxdr2vBzZryxDrq?E@0tkY@qW`{UaY;XL z$-l<;yo$1HSqMI1WKDj{gxS}jn-dXeRiL$XrZ?{AjB5)V9UXDw#tnoQp@LaNRO8*d zo7`RdzwyF4?V-Y7nlnZUp^gD5Qh;w1>Cqv@po8y~)N4teY2Nwa2l!+ZSxTO3vNWyE z3b2d=>vRrTmZ61WlBTFMVK^E&#mT7=U`eB$3Vetu_#>th@zf|) z;gy=gc$gz5THF$-E7de*yY*baZvyo0;dFJbUf6zVBP#Du5N6iWQ&1 zL?Vwl;bexH064}OMhNK`9%JkTd(Rf$2w@Q77rGJT(*or0ITGC)XW6KK{qm`NY2`wg z8szc8J|gXtjK@~Ts&Z5|M&&75<#@i2=lNt=iVfPv&6;qAv_j(BYy_nY2c15h-T*Cp zgz>>dma6l8Chk%NeQ30;@U^xIFW1N?P}Z(rN*-<;5c(D=I_f9nIT&dOeA~pWjdHZ2 zZDQ)F9}M4V@B+C35-)u*+r)Xn1cTFd`h#6 zbn=v>qY?2cYIey6A8(EM#Rgyh+E?iH`s{rFUChjLsJI12(3c*)p1_YPL~)&?QHejl zcf_gr5=kO?tWM#dUL+g#P+8`X2xWt$=Oet(7H`hhRbVGF8^8-fjP&q*pO25nJbV9$ z*FJxS^(W6b%tGYM3L+{IFRn1&-C?}DL%g^^>c#9G4_Uo9OYD2RdvBMOg^00|7<_Ku zUE|x|{vMClxA^`Kf6VdzmUScRb^!@P$JhW_uK3>fe!#9MptM-+t!Kg27=^gQdB68Hfgno_gD zAeI~)^+}W5PPui-xx#+`+F0x7+}V$wIW>phtYiED-}C4V5)RrUbf!>QP8da;Uzw#` zEg>rg34Cs$?n&pt7T0%r6g!Jh26Q1pK7HrPJ+Kma=Lp5oI5?si!Yoe z?bgV$jG$5_kpT}kjybc`V7Xbw_XMqa%#Q#BLHoYm+vI2`Cy0EPFP&f~#FSOkj{2G? zwhJbOVl%UUZ(TXXr1+Tr#4U$UyoTwf$>bwXNStsz2q$2>6Y?tx2^21|5gzD_+Br$5C~e$8n^F1CuM2RT$m~Dg%1}RzyqR84h&(vZD5fO!N5mnfei-2U*8V#TeX5lb%?nq=Uq5=n8*luSdmrE7(UTpF z&e-2?BZDfXIG{E&!`tuO5~nV|z^k9R#^R|(^1*;=t&CE;Z11yWh9rPHDo6NKt)M|?3^))_N+a@3Oz(B3;qtX#srio=Sty)bAZRr>er4&jTmm?O} zq%9Dli^95C19p@1Jc;x@x5o-=aN=Y~ApXQxo=*-x8D~(z5EG1Jp1PXM97gva?HH^+MZbG^# z80R86Hph1#tMj+Xr}E>1hkVMi-W;iT#C$EoX8k)$vIgQlT(3dR(%y9j;- zlWvT%Y7=J@Twqbs^BlG_?dvc<7ZWE67Kdt0PNQIHihtd!RsJah^6Bw+9CvQ7%h_@e z{?o6$;D7DQU*hQKh;I7;)Cg_t@GBcwwaJu5D)bfoq_VQWPj2rJgdwG+Wkx$& z>_3Zn>p`1`|MT}q(wxI%K{lSjjC+*o7g=6vF&>S{vJ~GJM5QX5J00G57C~6$gF(*s zAFtv2l1?7-xeGN`7piETlhx-bhcGi!=gIMryEcQ89!pCz{Q4Iz(QbFh#{)9e$Pi9__5xm1Wz;@qe`gm|hjO(^ z>Ff%B*&CB375q4~$*$Whr0?O!5zn8WqnUSjyt_^m1@sS|^2%$U<>=TWP&p<`*f~r% z>>mB;lMW zIG8djlXr6HSHUdWbz)9zSXSShDQz99vXo1wX87&@>@y}HK3!KfVJ zNir>1ZIwB5ZjPB+L>x-mgOt1LZJs+fOF8stRs*_&jCb$t^6HgEvT=jQYaWB)n9o1I zOxoU~Z-&S)X0;`mxqg=K{Ny&HexEaE&v5<1Ja4>pi|W!GFTQjcDLwwv_upe@BV%@^ z#%niLd9uDs(raU+Fitq*p1 zv;q6u4aS2Z<+9@T@rV58H-3#yPx8@bk8W^46=+0)k*ts;8L5V~XU9}Rc=y(0k~C*| zp~c?b5z95f{!yF$@u6)f_5;95@Pv>kqsVh**V>6$O7?qpV2V~qAP79mhRDJkL6Ivf zJ+abL@B`%dh_Vn=_PW%n6(SuW!ZON>xqAHu z4{jfmjk?6XHDH*XU&Ie$+6Qasq|fa961Dne%8^exIOJ$|laUxBec!Q=#iA|FtC+9h zO&f`ewJPjjOKl1y-xeRm^FFa)6~Y-KVC~D34VT>{s z6p+%`o*3gHq>t;Ku=hi2lyS^(5mDSTAskp!s7QP*QCK#_lXjr9&MgB}6pJytsYUe-myT2Q}`$vD2@e6o-T7djL$HKX@i;Hdlyd3V!Y}iKV0kv3RwAJk^4O&a2 zKq!NwK^59kA2v7(J512SU`&qE21J0A9&zZg+zg4uhw8je+_-?wfOa4tUd`${; znj)lctyhIWV3TO+c}_p<7NGF({Qxa&p;RfwTsk{Pw>M&Wp}|2n;r4@_3HqrulVE9t z$E2ZE*xnVyly0=@7q8$tC>EeGU<%}6n#-Wk;3P4&>DnfC#uEtPVT2~nHF3GjwJR5C z)GAy!f0m^)7kRd$2&9MbgcY(FO)=onSV)4kXUC|##_81sa-|rLGX&NRC-OZ4PclyJ z91tn2wV&@SE>)h}3G|+a$`!3&O|kJ#Aj@ZyzaDv`(jQ6CY;q<+BmNP+~vHG|9&@}!R-Bb=K-k5Xio+kz+z zhy#TTXONX9eh~1=bIXi#_~79#&-$8r)1%Z{ppywQt$6rohy9~;GF9CRLS~oB?C+}8@%|!Rqoxq$@!%kd%Fjy_9EZ-2fxOXJGW@>Y?4UD`D@p?x-`$m znnt_gQV6KUlE)98@WC5DqZQ|TeAuU4E>kPbKoH_rs+2>Y?Tu%=_4-?!TPX4D**3K} z*8AS0(yAlEfTxcikhS+Yb$-RX zckhwdURk6RHreW=jFjQrQiH=@!Z0($u7_i?k-0yg^o!TI!nlEaMM7Ov3R-Janj<`c zANV$zm{9#i)9KVSpg<4{=B98}Gs4N(PSh_G0D+TepIdJZElWlT$zViSiixDha6IDS z+GEP05dHR{2}$_)-UHrv{T=cwV?6BJnBf<$dbZbNN>migg+5U*OcV5?IMEK`6T-@7 zibl<1VAzE1`NZoj)M_1Fg!}BNtIM=6$6l@HNwO^EfBJ(zKxK(&&Cav4z0HNQOU%x+ zXm>^!;c@H1CQ3=Rj>Z_7QESzaUSWys6E<4}&87ug1js-V%|d#xLnsAN9Fpf2Tqy>f z86y!|VRUXy45E-)y}~OOXUKEK>o+%f?%W(@&k#$^tLNr8?2Tx5M^qw@M#*QVJ>v3e z6CnjhN5_2h;XS_e%4M{XtnVBUH|E^*c$-vjZXK{PSLgFDta5O)OQqh#GdV#Z2|UTO ztzDjNJmc5Dbe(70dwg{BCap^^VbY8wQ$*F$r2j@rfi{vvX@W2$Y__<6l+rkVgBMTT z;Or(FbetT&J)U|h=cuOayN{0JXSn> zv`Z)zvL2f#3WVRRQ>|7>#^Wi{jhvwPS74g!`H+b=d=U82s;XnTApK$ww zH|h3A91RrR-oQT2T3cpRoIthRvu#{offRP2rY%Z@lUvz=tHs1?gfns}lFT5$_kHrr z=9dN2VzjlX&N77|cRil&^W1Ayp5umoyBI0(0)yuVlXEN*U84+Hu6XIjb^hh={WI>~ zyUXUSA98Ti=C{87MZWPHzsi%1XZ-%Z`~&u#EK^8{bj*k9cWto)Xl3xq4WgN4av{*^ z&~4_*CeT_l9*ymZ$p{#O5ahW+r5SN80+ZwUG13S-7QlV?^2F>EJqd_z?uM`u(82|) zm^yC@tP`?NmtYkA8^$>Kl>@8S7A&DIQH7g|vlfN?rd>xFN$AI&nor(Xb|wo{v@m zDjQQOm1xaX@%$1&TqdkF@q!q<2pNQUVdyOQtR1M39)1`h!+@YvB25)rJ4a+$ZVQnU z(5v))!m@3symfz@jm<;C&`0>8LqBZrD%>xmaPCt$9KqQR+U)%VvT6jzMiYuj&qkZ6 zjh&-TE2V%+Dd3=&FisV|Z_$-7lEi_e+fNB&ACTl@pQP92(fxZo+3hjTG}4dJ?tG-M z3=-O)1de5~TJC52eL_#*nVc7|E-~AxaQERejxxoK%d7OZj}Su8Y}L5?aFhMxAxO!1 zlyiQi$(LU_&&E!Nc4xqwZ``IlGe_=ujFe=kJn}3jZyykP5>c*!A5vOeX0Wx%;pP@s z&dhV^%p$YZ5?k#NL$87k6LOVXr!-@A&cfu@@>O^YbOIZnZ{|!>tEf)Z#L&dWnFDG*`TLdxJY4Z&F)c!mmYWWiZl1$$-JI&6P7VeCGNq z=FXi5V$|NH+n%RYl3ZG8;U^ukQHRItTRgb`fYsR&M~7|heDpC(FShKxl>$64o^M&A zWXLbwILqg*pEGaWd?=Ff5G5Mmd4$a-VXFqJ%`ZK-#B&!{%PDc}jP)LDJ6-j?Y5C-_JfjHBeN|!)ajcsR!*5KgRj9ag{*Dt@y-1;QHvqT5xHMtZ|{Kh z$A{$oePUlR(`q7ZwoRdxo=7sx2?rOYKOqGudJT#-E4`^5ww>^!i}=EOCf zxCs;V7jWhZ=ES8Ma;-TWNroej?eUmnZ;MCAFgK^!+G|saLxy9C^2&rk=;kFc`JTXm z8O6C6P-whTgdf?-?$RY8+Cbc>ll1yXouTs-Pe?qi31i8@@qq8VvBrF}#Oh*$rw0SJ zj}zLX1B^CYKR?T1H({@v^7g}hc6W|AQ};=FJuaMXapmkXzw@it>2|vOyYKBVG74F# z5=SuzNxd5I+RK;t;*GQB&wlu>I5<2cPsbRc31bf_;KeJ;{F5(T=A)Zq9^LPg=eg~( z7>x)^5ynk&FN%;v34ZwD7R`#!Xwc_#SC_c3*r3|!qDz3zh@~+?A^M|ZT8(+;W^24F zCD*Q9#PfZ2wsx6s)!E){Q!4pfxqO;uTW!u?Y~TsQ`r1>n@j#^GG07-pG)^Z>oh^3l zOp9Dugm(huC_7KaIyfmisCJ^Uw`jVM5{Y!uqKpCr&@K@TOEqzM^&$@rY)lt^jPLn0 z%aO^IFAfh6#Aq}m%@m#f5P}Laup|}_cN+mqvt|6@ zHexuY7N&SQrCAP;VVPdf4%L)}<-I9Dg#tYgXg{Hf~yW(yp}vz_9}Z4|kvO z`d@#WCmWmeyGLZ>5xyR>SPw}WA*Dc&j|HBP1Zc*`2V}iAz8kifDuY*QP?}r8_&#bp z1`3N=7vB)z#YL83|1FppPY?xmPFN--xnooiTyI9FYI;P$5LgD)e;i1TEEm5$> zjzIvdjXvOe1$$*E`Y3TyIb5<|gxf+sXFU+)iNeDEzO_hqHvU3dz_aL~a}bm$s4^GS zgkTyUh39fS7iHc2kixKM!aTe8M_4AL97jQ;T6$%^QGS6>3y@C_fJ^`2_oA=Abn$mq zW}E+g+4q)0ZvpbbWCt#+^pvyY%axi0Euoc@GgwPPZ45@+hQw)ulR_I!;sy$p;u2*A zA_#5cnaJ!EYt=`30e)0Ml&Z)uaE)OaUnU4;@U_pGvr8zYdAhl8>EPlJHh6iyV3gz> z9QCQ!%H#&ZC?waK(KvSt#Og}J$Tlx)mpm8)!kZ?DUKkKWk&8LP)hg2kIYFHzq)Eo} zmuIy?`9ycHE@yeAs@?4W^&Bc`lkGHzaG)qLG&l_)a_}72-E~jP#`nhE2)hSmi zRBAD^jS`355$Bg0eDvsmC<-{gQs>^;^3&y`O}L$c(TiIl<<|$ zUFPt3z<8YU$_wZCt2gdbDwmm`3t3sH;`tsgU0or|a(1?l7oBop#&tF;L z`RC5EzIDuvOBYx=wZu<<`XN$6+BqinL%e#E|M1;gq`79KB^Q<(oL#JOeAGi_DT~b# zcfiuyy0C^6j50&&DXMhw+YgD;eSE*kQFlbcAJG(TD)h<9izMSQFPyINjW0cKe)hp# zasMEj=yQeZH4;M5PYp2&(cNZmt%FE1v^+zS+v3|u$xwSlqcN5KF2n6Ue%2vTf}PIT z(q{c##(PJ|e9S1-Wa=bEE}XX75D0-6`0N}djGuLR@8-8KX@_9tRkE{^c0MAIhFa{i ze>@;A#f-)|5<@ml9g;6yF+BC>x3-}UnZyqGnr>2dBQcg!q~JWJZY_{y&dXn$$p$K5 zB9E}I0&(Kc#;prSbyzcpA`DEkY7h{`w#hUsmoRCUR=vVkKYyKiq|MUm8LD%qM5oi^ zr$2q2g=UHN{ubZ)_Fs_ab{cX~U=+-T%H4)5rq?o+4NRp86Prl){{zuuO%|zD<~fa4dvUD5VL4fZzZ9-=k7*@z(pd`0AHlv#kb4-62un@y5G% z`B#7bF6C-OF6{LBiBzq)XT~^IzTI{K1|TN13WcmVQ$2o$GdE=KcSxOvQU+z!@f{?it?(A zf?2L!z07mxmN=c{Jbb*%*`)?IUO3O6fA@X9{7Y9@S#I&u;cZ@fah2ntW_^7J=n+LB zI`uGWj8?YCP-~4Z+z>UR@q{-4oa`2&CL<4&vHcBFduWtflRi4L$)i$g(oih~NF!+< z9#E<@@$vz_lk4J#eE8r{h;+=sUXP7ljPye8wPR)%=czAfN~M_Lpohsul*2jx>PJ80 z{deEt=wOex-@hfcx3{=(W|?vCm}gs?Z0{X18jkF6+0X%fP6k#K2-0&sA8x3&;wXLq z03ZNKL_t*MB$iCv;iM}96xvPy_B=C5NR5*R6$Ohjw)wnpzzTv8A*{UBNZWL7S;CAk z3|vFHnYdz3dbHf2M5PKlSUqvG6H?-Ng0;s_`O)id(QbEm`eYL?i1^mGzr)S<-XSbk z7>!0qX^5~5=c;>bdp--3enNZzQFS=RcKNDLT+GO5O#F5 zR<`1HzS6F2wrfKOe(7_cVfEZ4(;1{_Vfzw}JAEE+Y>WOdHNubRjdC7tY>8eXA*whe zMk2g`zz?a_>y%0X27MyinKlDzqwyuYd})!znJVr6kV?JIn;&h`9kdDk&`P?bB+G3Q zFHgo6ZLRb2G{p#kAC?dl{UJresS72tNWcWBoKhe$dCr-+5@m0mSFSE{`|&;>t?hAU zw#=(n=GZ;#({A^8{<(Af&B$>6+%m77nIYANwap_gpPHc@1-x@-i`TBsbJQ7f{rnsY zGi9DU-oa#>Txw zLU4Am!L>`vtamcHqc%cH-d{VwYzzrz7f@=O;m#KE!YZO%!-O$%c9rkFbDz!KHrHQ$ zi6^@~@>Bs5S#1({wx`C@?l~gOh-YW;!vGojhcb0chtQsS=cG z6&`PQY1JZ{rI1n-@Z&chP-@ihOM$cVv-2Q!k4KC#?7ef3Z~fnIiu&SN&VA`3s@-M# z-TQp^Km4Cm8#A2w;y-0mcX;&P9d7^aUx-|UG++D%{ceVtG?7X|0Z*PCb6gGBe&-H@ zjrTmbJTRQQR3cBNWn8n}^cw^Q`U=co($P%*z0^JJ?_Y6dLT7HC!@zVy-=HV%gL$0<73 zj5=Msz^7cVI%$G!n6*n!Ode^Yr;XpmqwWQk`4IBNW;lrof>B~EwxvAL?J!B|%_MWQ8)zA z6wR*_j>R_NO3zx9<4{~gkz5|!^CNaSVSW2A0dtHX~~PJJ;r?E z4jLy>IVlZO3WU~p1yWtyTcaq3LmCW7+XRi$oUMBdk`eEHw8`_Amq|OvM9URaD!BRN zmuLkjrWN6)ypRN=k%*Vx`oc>m@Tg!Gwz{<9qKrzpU$RN33>v9s4@cx0!o zzi^{ME{+%s6UwC$d;4A5y@YI>^4|N8DOE}=TwCJcV2l?81O+Ror@ci}J82jX$9N`3 z2#@ot^L$~|BOJzDJ3GhyJMR;gN@h$`{PgxVC7H4^Tj5{-@ekf;beuqw{L!;Fq6PiJ9 zOb{xX&FI7$wdZc1e^-nM3pyCBky!auajnI=w?%Ep@TZ*WE1I2K7O zNR`Hy8l7cm=S1lh$cr$JdA84YA#+8D6M57$F4=l#YOQPIxCKqLn=WtTm;?HRPr*JF z&lpVI%uYZ<6IR-?BXaV&#l3f8-ASAmo&$J_A;J?D#lFrqsoM$nMk^5Zna`C|e@Gvg z&RT;pd9KKEXPfs6czjxb{M=EQiDzaSm1eaP5lDwN6bTvj!7CSV|73H3Vo@5cC;G(6 zfHYIs#7!I702bzbp1_44C5qVw zzVDG2Y>YlZ@fFsX&g~{oa~?g}rPCdfYi2}a-$^|xd z+swDBR7)YZAMK$GEG;y6>%*rE2N}=y25jzjdF9FiUwr8_y?(++Ydietr+4t0v(`CF z`gDf59X#j@qS-~phkGOkyOb6rBCb%Xmbv`eXBZ#s^5oeO*UrrH{=Gf+cDqO^snjb3 zaWQC0Vtk*E*V_!nDRa#-8@pXL_6PXY1~P~lAMD|$BZkLqWE2w{L4Mq)a;8kP9HEmD z!_k=K`8vDD+nCV+uTryK{Z59WjbVQI49j(ovGy2d3Kf8iYRsN_4kLZqL(Tr7Vymqg z+|0xt__uPi6}74EuG=qVx18se4&T}ivk)0wQ@k1!NT$>{JAQL zEK?~3#LbxPZOQrPULy7tdAUwl^64keh7yaE`vt{rYyx{_waReh@zSq+g*XaXJ5-!n zt@32!h`e*e)f>y4T4-?h=`oqIG8HfI-6misWET(RL=#Mrdl#Eifil~o+lvBmyFU<^9f40{7~mQ!uj3FFYNE8*C}6Kf17Ehubl3;N#nWqBO6yS($( zyM!dX`Q}?fX?V81&7=Ew>9_YW2I@0&*1}Wk$u$+m5yd~+>5dDux@Z_K)~UfE*oEVZ zLvU@pv*3d{5w{BW8oN=uLQc5J(eCq$Qct^$+VecJO!2?{oBxMo&}Ct1nVS!{&8gF8 zMYA=>{@ymF&|{~ap!G6FNUI$;(*bLkY2sp$Wb=vp4`Pxy6yJ~a-gn=k5D2C51oTHK zZ{OY^@+GfaS>m9V@NjLLYB{FSs`Ki#Wrj)4?(u+kKHjEM3YlMM(91OS`8kp-<@%Ks zgi>s@hs@PIc6*9c2~J-;OR}jMgo+!_eU{moI^%K5J0Ctq_=Z-s!t!F1t*u>NdEu8y z$0K%oJ*xG9t**8Sn=T66>Aq6@S$GnOZO+e=ggk(?$Gd#+(LIiLHz}7w8jI&SIP7pL z%@Mv&qZ%;3G)K8qqFM^6MuJCAcZf?NXHPG%vvWu!q2Xn0A0KdBju`d2&do_qo-fa{ zjG|KJ6VuUsFTj(Kr71#5eCgXh1)WW%cdI;e-;K0Mr%T+l*5oFqKNt{?Qp~9}H zt{|#1*Eq#EeZsigofNavqTM3mI@go+V1#qUa_WXc^Ka#bg%N}6)zQvX^+bH}yuvEi z_0cFZDXekDgA}&kObSVsrX=I!6VHAD2028KBH=%28|+CdE%JkqRKy&26Ub6}y)M0R z&g!{K?BBZ2ILU~5N2FH1||3^>77O!KWNdoElqQZOo0nW$rC zi@ZiyM={)HN26YXQ#>gK0d+8D)<-b__P4|xnnp;tWCF+#<( zCj`Q?c5c>aX6l4v0Ht#BJUhWE3XDoc$y1afPsFi-isbBEOwAv&HRutPTSz}bdzR8u z+D=;)6B-$Ch{yycwEl-gm6*9|naVI@|L%^p{`00xrM*;xk+#5*UV*@Q7MXL+>6511 zq7cJk2exIzE@D3n*zcvR?`+X(R@gu2(0Fpl@?4FJOLdNV3HLURIK3=6RcrFoTU+Et zlH`WBKi*=Pq#U=09PD>lTxwA&$J8n@N*f+-wYhO=2@!-y&v${uGM+ad9kaPVVtxCF zP{M4h!p^>R_jtJ3WqqS<8wn90L-xBlA3oe?W4BA>3lc3UOOL{8(kRV%*ux;GHfx0Q z%OnST4EJ`3XJ@Iz4ZiTgX~v^D+U*|I7(PPb`Mzz+7fweitd7)ZSe~zO<#dx?f6Ud@ z7Uz~{_`&@=kv>VTxuYdlxxOwLu?JN|k*5G#MESJ9g&)MAB zqa(*G%#~T|bR5#J(HKrI)rnP`b6>u}S3i4=AHR8%JwIYydGtoMk@W0BlS;Y5xihbs z&s@L2Uwr>f(O8a{J=fyx!!rN)w|?8qR73vuojW2~sLCkK;Ze3Qlo0ushrv$+Gl#2(M`~{ zlZ)1|2c}r-t~crv== zg7zRKU1;K$X3@rw`6a65bCgCgt(7i19nm@3b-TWO=R%uaT>Uh6ci#ENZoImXOSu9_ zzzO!rOl>BMf~&X(Mf@syNKR~*Q$&zSqEH-K%h64v{Wlk$UPNSV$>^w8>hLhY5Gu#>F|I1V#vQ2Av z`0Xz-7!LWvfA?1eRXFTJrZqFwnDW_KUb%3MfB2Of{MFyS!%$cG_`xoR$0^lv$l`37 z%c~dp7yretaR1>NfAXy#L)~Y)pW+;iKaq~uqEI6|LAhQ^@S}ix?VNt|1=^-f z>GE|3=}44jXE{3q&4mTt```|%b7iW{8V84cR5E7$;bV?>x4Crr4Bb)AYp+~kclUsg zKfHyf#+0sHVXl6fz3oi~gT8Apx5b>4wsCr#XXJT~m*?a`FkuCSD?IH0LMQDFZ4%Yp%sWU7ruhQ=x@zL8q zK<8)C+OV~?<&sLbcN%Aho8=RhloRX27U075JWqSRivA~D-0=Kq;V~(Ur9ca3&7Wl_ zk_P^T+@D|3an{ zu3b9E)hm~I`Pw=D?Vo;=PUiqGt|FwJi6Tp7qSicK6tOVhU^p1l?G5c*53QZEr64Yq z>GhA9%oZx5nKQe<*ccP}65n_I4+;cw(yNkYR@PM*QF$(BDejfM*J29tIM_(=NmgT$ zOS#}Ar8l`xz@%`|#=40X?`LC_2a~4uqW?!a>{d>SD;x8*`yJ^DO8Xu@Rw7!&%IORw zC)4sRbL6F&Fvj5fz6e7f-}CVNfXF$S1%V&=zFhvyKl%=*CQj?HD1fbCQ!s7$Laxw2jIQVsC_28nZv<{?>pO&W@>7V+I-g zB_p}qo7b~*^pM;OEKV2`k62*NUf2ay-BwQcLLP4`n9o%lIPhWoF|xqDHvdjc(+k}ay9<^?@s^+mk66FP%WjPTrUGtSGgi7Hz#s> zi9wA9m^{aeVvrtrrWo~y_+da`60R-J@?U=A3zQ7lil099#fXI%-c7?11_#V`!Irdca-c+eq9GiGP17^5k9lDVqS z=K2=%jS|VuQ?lb-=1!gFfBbL%ACE)B+Xo3U5ZLlS7^uyQyWAj zvLriEAltFG_G8keK%ZmJ|h}G6PYvKR| zMp?#Gc)$q>m9g`QirFB>SOXmCg*ILmmb}852RW(R1ZWZlv^9n>c}8wDTG{?srE=?P zCT!o6R*F1N$+Mg+OGz`!Vr6M6q%VY&cFvXO+g>QUmJH=mgfyvFt(6)}r)MJI(*ood z{bOb_i6a9k2BibNi_NjvmaN{~#ERmb2?0(ueQJl|(9=(6?n zAwd`ugg(tmNHq>HYHS$_mDz@OWg8o{($lv9!Z;+$az>NGAyc8#<+h?hsC2TO_H)Kq=3&)M=Kbj;$z)8jFsUn{^BhB?FK?<%J~% zySs!c<@{oeQXG<>pX2VMebkc!@}qr9i%TdOPb>zD&l`+$_PQhDMit?CtnUuUG*c~g zR3==oiL7uNPooiWu@#f$hSqF}uoQDVhSAXxzA|Ko`^ZL%K-8F>o8$4rb-s7&fG2H_ zvo}uBnr+cmCEni1*dI5zG~~V3y)t$)vB6lS89KMUPxaOuH}5^> zAn!3OEpcgine82o(E?*^;W@uB&x6BbesaHS+QEXjFnEQ+-P1g3=ZG*ydLE%kS*+Ko_?qTyh42jD9)Jhq~y&-v)Q*Ks~GMpd-#%)NpsGbm?6Xsz0U)=gF ztRbgWeX*e#teKqZ_sEV9K`ZjOL_E6)23rIn@I&h?^K^Zkik}PBJ1}{ki1qb#K6w3I zR6e5L?O^f@&+{p?;<$5|$~B4$Es$D`c8--3z4Zh)k(1d5g$zrG!qtvxLhKTtA}$u; zt7t;Ex6LxJ#m_x2Aj@+8=nwx8pOk8Ifnf?~Ru@@pMf5udbcdP`9v%uKVvxR_PCU8S zCoTo1jx?^K_b`)Q1v^^^JTaAmVT^04x5ZGkT4VXt3hmUOjt49(%`zb1`tzr0HA?iy zIm-)m_WCJ}T8VzD+3O_C%~V-zmFPC+`L}#c|6x#r>vuQIO0j7PgD13?r{>_m&}FF+P6 ziS>A}GvfZU9&@#TE2mm$1fi6Sb4{KkRN|0vs`<=kUnVoKeKckvideh5My}edT)M(| zG-mz5V<=1JPn|~|>{E?XmKSEohew3IPe0Ev#-E_nLIhw8VHlF<`2;CeN|9xmZSJ1* zI=H<_SP2tYgkK6Lu`v#*20~v@Da9rTBatY>aFnnx*CdpJ-e80u%(1n7#Hr;OuAEyW z84g%IwaD#z>uf#SMQDvLG2=m7jAG5<_Aa~Y56$C`Z;Jl@I@@a>aqG>{+`IRXci;O! zc!5u9BH%=SMe!`VL^RihM6_s}x6`E}bBX@l<()VqVpcF-~q;bWmR=Iso zm0P<8S4?=WPpZfzr1U^2Csz}n$TM(#T^88%(9RNAL=g|}-Q~~z>_75sV}pke9uUT5 zZr=P*_!92if5KptA*7Eo9>4t1gxZSf4_t8d((3lMF9o@KC#}`LJOOSLl0WVGaf`l^0&FP& zCn>B+fDr{ik^WjzW?`y}#S#cQ+!3|F|q-jPzPVwUq>3PgGBCami**NGEc#F-DJ;QRXx<0m6cgJ=gm8vJDz!u5q^l+`I%#{r{r<%yqu<%Wu#hO}MhSiPv2v!RM7Pev$rQ!sX>nWV}GD)8^9k z=ec`ch|FK*^5qNkQbB11g*FV1Z9~G`#9VpiBHNd?I6E7%eci*0WBTI*>&zNBJQ?xg z<_0gk@*-K5i&wU(Kc*f<87QyPpx`gMW{VBb^MxA6VwId#!A2A+GNQNWAP6riu)k>=8g$?-UpZEOx zE<06aD-3hxRI|(n#?*mG9aPL41^F~L!k*N*j%FTJvy!;^WCBv*`yP2wqVpU-ifFW( zNYBF;1rPRi`G3Coh?ogNAiUN(PxgB3+<(I4bO+C*EH5uwOv^$503ZNKL_t)#P1pr) zc6Y7~Q$<2IPDsM8kEiRL5tY@dRII9(#Z%3+M17u$`!XNsJ-w!?KkH7>*tPTIbV8az zJ1dyn>ha0B$MQmx)8jtMlpLSueACe|h{@(xg4;Y>u zQE0=x`;W!r-F?=UyO?~;$x)B~Xi8pK@do9GEUv8K`JPj9oh!L?fK|0tsvaFxRzm>B zWi|{3q36nf93fpAn^`SQX#qnw9|aZv3Q&QQICiqKR0QnOB`9Z^0o!rjxFEoB=5(dH zWbNAiL61NF_V+;soF|feGUb2z`~Q?U{yJI&jLHCng1AGpx{Yzw6Uqhfh1TRriBc6u z!>xaWQ~xXxN>G~%DKK~lZ11E}YX*Z6k#9(|3|*Auu3S%u3ea)3*H8!56$moVU6ZQH zxY-nO^(h6>l|P>69Sw(ApP<1(fuNRvKKndW|bruF&mv z#ArAqOA>Th;Kvzqx}>#suvSNf97}h)M<~ymaW3Wp0|A6_i064$ z+LXCvJU2guQ{mED&NQIuJL{Z4=uV2F#nc3c2XJh-C7>`rF|K0Bq$&BgngztU(Pi%Ra=UGQx z%mNYXG}(Z?n!k0^GGnNuAgda6>H7EBrDJcR)#;E-C**nYR4O72LmG`12n)1K$0O1t zamcNl*(!$w7+s<~$$#=U|05PRw)ycpAMndx`63rCUS@Hj#nI`I*n``59`Seo@Ix|F zf>3kW74ww&t?>oy8ZV7NRWAxF7GjkMtJf+89~*?ENy>CMqNxm1ozn6RXM>!_2Sd88 zkn@r4S}g@mW?j{C(?7j;3R!|V@1aY9x3WPI#;%ORa5&2O7eC#F(?i5$K$%X-vl1aa zg1{$94d3|AO_V4J8cj?PAy&62{03eaQb|+mQah=0S%9Hp zBUZXiCRxtb)vH`sG@Pobvy<4;Q(*zDvMA~vAVMglazUvh=Srza(iACe`A&uGSI(+( zT!4By8B0`-0-sJZq}}j1p1`{wJz_kVP#DAN#wvgCof{1L6FxY9%4*(MC4~x1a2i3{Jpk(d{f!W>c%0CcRoV8(}lh#?=UE zCqb*V!3bA&i}2#im6neu!Mfw z>!RY3;Pwb*OQ40Asc6kP-vB>(_an-15!G5_z0;=MZL_lg?m!X0d(0?F2%{D{Y7;N7 zLlD$`HJs(BN%581pROE#VVwt|JOqUW7pt`;6e86~N`%qmd4>{LyJ4&np+?nQ5+x-i zg)673{GS<6FhgbS|79(*A#5?UbluNgd6xb7T!-@-0kK&Wp)E(Ye}2y0`wuxDLm6)p zM@`}=LTfFwE;#P>tjb$6ps6J7c7sl5QFIoUXf#^{en6>9d?k?5C(ARFXDMK;t0Zl6 zbx%nm-)VC#S}^psWNn0aOcqxNDmF`C3iPtum^bQ&K zj)+&+kiJd%55_sS9-m^gCdo9Tq;z$~)Tpl?2AH;0X2QVp7Z=$-8uFw!WOKDmLm3_& zj>(Zk-6cZLXLN8t7$_PZJbbv%*4iTN$U|Z{KJK&gq({3MvbNme@!mPN9vzVvIZI0& z8ga4dP|A?~yoo}F72vjV>T&I6VkKA|V*_0ADpfoQbQrJ>dG`N|9H42Dyb z&X^2FJl;Fuh378NAEw;gIpd|PE2IVVPRBH-84H17r6D;VWneVzZi{d+Cx~s6OsSOP z8QEk))s)JX(~FXJHJ!@1zmkl&-TJVvZzV z&+S=FGT7^zCuYt|x16D?UdN*RI?wT1Ekxi`A)ht_rdjGXxw5rHLuv8l*Pb<7 z%NU1 z2*GGPW-^|zxUhgRwoIngZWH)Ey@P#bGMaXzjj;{tN@Jij3{Uomn9?qeSym%9ygnUS z;0Hs(sKvcvYKkNg+S6#)`(P#=Y=aHV(_A0xkbudJMWm}fHnLJKoCPpO8-l>+_@vJ_ zzVklqee&GOoG&bN=qxN?0w1kBg5?EiW znA2}YR5PdQj$Y;^S(=fJr%c8v7Z*KVe_@$;G^R<;?emb;)ehU&*GO*cAhR&tXoF~h-xsTF<@g0M{oLEr_ptSBoBqA0T77EX4z z>Qf2zY!=?KOrB0bX#3W?udAYR>I;`yBK zALBb4th7KEg0u6K!NkyB3NSiH8$m9b1PdLeWx;qf#Y{#N#wTj85r&F|me26)2uljD z9DGYu)=sIi>f&y*-PR%2Lf3moMI6`0fKqr;Qk0b>td;RC%W@W+xPBr+*m*^zkSSzM z@HYlZonbH(S#HNHuya3263a1?l1ALX3xc`5&AHz~Vkn7QEk5_^SJ*oqa{K0ocsgNg zV}%PBFELIfCue5_t*#*mg|14P3a5Alv;HO8f+|&}s>;62_Fd-(2mxh+$)+fQ+oc^Z zRtijE#dwrblw~QZ28u8fw=nhEo;C9`;O3qUJF5Gw2Tt!%OFlTz_l zrfJ5bojneZ&cT}!#}mv#7s{N2!yb3*xa(JqlIfU zX-c3pg+`}Yra+*}jAS|ySys9Rw+7p#D4^Obs?2eng*FC1P*CPGlHJeI@mT=!XB@x# z-~6p7EC0j){QDbA&9B9w|Ee*rizm(@SAdWRTo+AKk)KShwn7cqSB`OID6qff(1TAO zLW(*aTkDTY$=1diFTWHK#9h3wNo#3^cwrgg`Bqs(+GXoYcyN+4E#MbkyG(zS@L+#P zia>g@R_oBUdu>pDK(ye4vG-Hsy>2nPGG1q3pmLLqa2W4=If|%1guC&&TuK0^0V>+HCm5)Mrk_4BrKd&tXb7SZKME1Ts?MDDr@VY+iEcZh(+YWX zV2HXcq^~Ho!0#;3Foyo|0UzJq;mXA|zW(tIhGUyjK06=q@L><5H9-_m8b$AXOx$ks z@slAJS2TnEh~%_SF;0k9mRQ`rKwkv(Mg=>kDZ^n(D}XFX(di+L6;N@T;UwpiC+7@? z2|Ev;&`<_c#GOZ{{N}Yy!Z={}XvE>^gt!?arQrKNzRSbiQ@YCw9F9s(h8dm3)-01z zfrO%Zo}vyesx-I|0zdR?X9hDv?`sgP`lnihbHQ-^nd>cZ@>MHY5N85zw;9UUvY47z`eVl z&_CKINmGL65}qG8N6vLjc4(n7R%NepmS#5~kVq%NX;JlA`IK=RHcrmjk}8uVvCe3b zgD_-yY5@{YkY@>5mNS#1a>jxxyQoo0QWToM`@8=K*<{3p%U8Jd=zt&y=(HCZjYe#3 zY?#CIshCWBCT4;NBm6j+1&W`_uFf)^!Z}B?vMs3WuKS!3bEeh;3!|x~NJ<7%gDebw z07U`){uEQ>v=%#fQNZyaBOOnWQqb(g{QB$btb_%RcSfi%pwsptYV*za4;W{fi>nQO z<%K1BPZBUK0)LTiJLdaue#EUi`*hk7zy8ZF5(J9g*^pMZO&ItLXz<++C&ZpaDv!kY z1inw$@GXB$Sink3fzAtbtT2la&34G?WWwW}V}i*E!`>4p7g47vjlEAeNqsKJoWJm! z*SU0UoA=-Ugtl++TOp5k4_Ig@lG7u`(~OQ-=IEfuqU_p|5pADe7zUOT<{ZL2FObsJ z>ld~h$n$)_mTD;_>#p==VFTS+M;;fH>$0|gQYo}XjHWr0Bu5ILC=O7OkBlrZ?E4B? zTBJXnOeu|FVPzGgbH=Afpi^FYcAek)m4AiR)g{K`32*)IO&;FA&nvIK#50#Ju-J)t zc=raq{e7}5=aYL6+1o#GB~@j;j@Zdopc0+XjyqASA(_%; zjRb-3TUlZkkZ5f=BcA8kaj3}Js>ByQ%JV2)qfsGzwBwcdZcS9r!!CuAEK7O$`pf)R zf9pSE=gA)bCldgRQ5NeC3S~Ej8?fDtCG@{@YyBo{0rxg zRC-f(gLS~43reioRJGnK8}9ap8d#Y#!a~@++8OAIN1_cJot*MyuZQxRv|5pEmYA39 z?;mh-)FYXW$dV~veB~LI7TSa!c*4Sw7>&^dWnp_lm1QcjT+6(4n}(jE^OSrRW6kdj zPyKDzvZgExsY@fK z3bwZ|h|LSzZ4}1Kb|LZND^ottVFw%C5*4m(rKudx0 z{8`Xs47!e#oa5&F3L$Lyr}gV+To2(4M`bA77i%P0I3jqV4Xx1Q+3iJ62MJkGva#G` z_h`)SX~JqZL`+g1?+<8pT0~7%JDXKkQDM77S@g}-fmJB3%~Dipeqo~~;|x~~&bqNS z22msD)IpU&*eMv>5d#7_9_B=%JCEPYX7dTbzw^c2B0Z#K6pn8yHh16`u+!M4g?m z2wv&R9;73)SAldbzi4#*BNc8~ue~ZT!OoM4ggRTFGa1ZkrOszX=6he%>zJ8h|ECqS z%v|4&YC7tJ^v4Ndh-j#D(!FDn;Sj083;jx4q7DY@$K?iD;52%) zb#aB1R{mOBr?66?Ls*Z+V1Wmz6sQ2{c?ezDfUGKE6BXcU%WulE1mWTPJ|3EP-hPM4 z=@C)G=Y9^a|H`is`jSyvvd{=Pda}n`-+PnG+bitt9q{EZeU45uqRcbmpn)e1KYsfi z7TN*Xsn5yzkn3OkDz9JZa%Hp2bdsR+j8c~waVD~qxdN_n<7QB^`!iIdcGPa9{q-JEoQmqqn0 zfIVMj00wNFMX8M|Nve1h4z+hZdS+Qv@I4~(rU+KX~~$>DXm!rK`9lTI0RiH%7}C_ za7t*l*`moa%w&Lcd{^5iMG-|IiUO%4^4w)JavOk@t}0~y9;$4B60>Hh)jlqSv~s}i z^;&?U0t+hxYK(i+@me)Ad+YWSr6gtPY-E{}XOhuy#5Bn{KR;tS88aS_$tHce?G_8m zOSTsdy0(3GzT~*xC&r+K(`2@Gw1!OntfNN4+_M!JjL7m_PNqNOEB}%op9LU4nyKq5Ja&(V#DUPccn%?%!+@h7tXdRqyenq19}#vT=d#!XnqN zUFGVvXIN=Sdw)RiU5?KW@LSiJ9XIM9n zsy*SkY)YPGWRocv@S}ieZHx5ifN5`^<~o?Lh4vKjx(z}`hX*v))**-~OH<1~YB6)F zq!6x`i$lyMWEwtr)UW4>=gHX^3*!(hV1Fmj%X$FdeqdwiH zC4UQ}**iGn#Ve~Uv?Kn-H-5@AN%0(s)Ch^E1m}Y>qfyEmuUKh8=SU^_{PP>!zJG*jwJ~|d#qD*LRu(uMOr29GEYizt zebi38m^BQnNg;Dt3xg~DD68KQwXAIA{8yVb%r>SfvthKJ)m2yTR~bv{)6`CB?O?di z8TWTpa`C4!Ct_}WP+jlSAcUP-b_|NN;L>uNU;5Hzv()hT$`@Y|tLvK_o%Z?tuW!+5 z#!QB1{G)&P51hpCEW;t>jNdhHgX+LYR(uF%fp^uxTFz~r#>#syEv+Jq)=DWc9FD|b zG^X2KAZ|1<#)<P75${C@0tS%$#)~}EPX$mJ*UJY{f{B6y; z%|J`{dzR8AJw@EMfmJ1K?0Ft>r)7a5AvqgP2t>h`zIcU&hR54C9x_c5Y^eoI(}J_K z&*z@s2E9v$(R#xYy@+ zGUb`e>s-CO&fT384o)Y0{*^17^iEk>S!8o#nWK|)wl|mYOv>@$J~|(h=NVSv${;=G z>}rDwY=*ula)eYUVKd5BhF4Jkmos%cMm9|Rf^K! z`O1odcz2`M={A0veWCCidhI-lCf z&UQO7)5!>Jr0oU{m@Gw4`VRQC=1uxm!d@HOEHue8iX@=|aBPsGXSTGu17qqeg>++} zu?-5VrlU3b8 z#0n_5b6ae}^=%g(#$*^>3gyBRO(ovLpL0CzKOlq`g?=lN<}(h+XUFXDL{K)HjohY| zZDbvUP1Y}T*}N2z=Y^S0Mk3ErS}m(jUgRlBnu8Sho{v;M!Zo<5Yp|a}R{!*&OHCZN zc=46bb8@`LCwCqZw-!8hI)3!x*DWiaY~T;s-vfYwJu#BeT1I z$m+(H(8dsYk~d!3qPx(*7{PL<$y*;h;w!ISB#u0KXA?g31b3eFk%3>U0#!br0HkZI zV-;rV0Nyz}=1<*FWjyUa_RX@?bQ>Xyt&ksm_=L^X4xTg|oeX&K@(M3*FR;*!Xm=tS zEh|B+D@U+GQ=Qi#ge03Lr2PRwr;Sv~#Rj5!T(#p`b%55o(*CZ9vYN6e$&wtY1d*yZ z2LjNLs`71HMswwt!QDYjfIT3shS(u@v!#H$9`Xrq-+yt+<$bjbAZ zfadx-B52^mZJz4(Y6skA(yIDcAq2iqGvfub9xQGnQvxQb=KTk!T-)l9WF=XS~p;^9dkTP zdHCd%NdY2mBHLZ0?{jyrPZWBz8=?Ko{uI+%=5{aP<*SQ?o@D1}%+1{q(aI{O)I97L zh(?a*DQ@rdIXF+9BW>r(e91;Vwd$b5%mwlGIeV^_TDaP5-_;A2Xtml*(~Kw%8IJ~}SxU3fpxbFP8jo#er)pB@#@J3} z+d266{?R|A5lRua7YLMMZDmPxS~1g6AJ6l+aeEIh^yw@uQdS&}xol4Ld@5T|Ki0~D zlmeZV=q#tiszpg0v9$`0D*lUz-1=e$s0e`<_%$MHaSvH{w6~>10$rw<;jU>$ZMv}# zd1*y4D(UXh7*6(|aQ~wWRZK{dkTmm9$~HJ1j}yvt%-PPz_$D=tC>9w$CM_`Ol&@T0 zWVF}gOD{jm!QL+4{^K9hG&w=g<}d#0uTjd->>dxralwE0 z_x>3>5APu5IaWh_%2~ z3+P&XswgyCmyTp_19&UbJL6FlMNU~-rAowX-d5(v7>$xP*wtEFLb$O~(Pe4Nhy5UM zS;`r2paL|ZLiTORlk}_rz}xTM5R+U|gbSpy#XtGxJ0xjF7&jRe5i0Vj_@_Y_lBGG? zxY9Z0KraU{4#x@S=Y7&-YJ<=MD5mJ~8A6xN0dNYHUVzquEJ+c8B$+0ZE<3H1%Z`1BG2*T5MurJK zXJAdZmE3*wXorI*kJ-AgJ!hjGz~j{SEY4*xW=5j_*`A%9!A~8=;47tCalE~~xx55C z`2YCwzm&&k0m#odp1HWO-fV>HHf>kf6rmJ&o+Jo72$hIKTVL&aiY!YoCI&R7EJ&s! zv^GRxOwedhk(&R!LjXmQF-@jS$76I+&~8OM_v}^5bU=4;g)7fIivcz_FL2%;nA6iU zJc;mp#m3qiQVMZ!cx)`HZ`fFF(rSe~-Z|pcYa47YH~8H18?>7tH}33lKA3WGeUXRz z11AYMN7}Us0f%Thr%AX(z#Pgv?_14{@r7jaWT$V+LP5paO059z(*=+Q`S@tC9aNDxZW!+gHc23Gugkg(4=XO zCnZ7bniUD_v{*wY?EuL6?$A}Oys<>lz;~ODt?NZ9{FN=r;~taVG3^bBh?;0m5v|!E zWb85_CTiN?rn-KZNg{vRmbud#D&&1u7G{Z$hIZ)jxoay7#$$9@^7^x@ynFkQm#;2U z<~f-W{K6YA^45<8o14o_`h6bU>T%`TC0em!=qo%=lAfNC6h~aWw#nu~%!8d{x}BKK zwFO$6TjW@kr7X+YUTyKrW`~dO_ej%>b}K~q9xq&8q8%x2JvipsOG|W`A^ZK5DDe5h z^Xp8;38(#pH=bML&0B};o+g$I?rygBtCOOyy(4Aq7ziPt)S#?WRFrcFI&)jZ z+yt+(E%R%zn#9KWto7?v@H3aufT}^(+ygU^mzIne_@3K9XKSRo8sXMXp5{!46a2uV z9eeDb4Ed8E9EjCs$v4mxGGecH#_f+jVtTfZFACN-)^JLA2xFr7^4w7aBfR!fi8V^?Kd+*&L!+}=56 zJWUB3eU9bFW_5F0#L94bc!2LIdLvCLS5cn#RM1$90nGh9TMz~*ZHbSlGFC!3r@)oN z)bgHl563x;_SS_9Kq}iZtKl~S@-%afWx&ndA!TpE2jBX-2t7^v`CrEiQj#2k&}Z*F z<#b%q`}jV0Kl~Bhl?|q9kyNb`HCjv(&5z%^M{@drAAS8zd}YLiul!r&#gON(ggn32 zqsU4Yx-nNTZjfXpCYzX*rEOZF61vFoMPUL`5s(uoNw*oX z*bGsoK$#q03SwUo1_94s-N5rCtE*ie_XhNnoQ>@bB=GSkkND=hkI0Vhk)0l}&}!NY zhp+&WsYE(zZjo`of$iq4od|%c`j`lTF(qZ;REi7)L4Ym`@}eM6ic|}J@WBpm-tLnS zBm4$sX_s+nDtl-pVoPoCankCZ?=r>UwK{zKYOv|wuq`cs16$3KB(J46}~kj3a&ykIw>-KjZl8|K)#w{rcsNzuawg zE*g{9k?&+OCYcN^xl@4AneEq*O--IA6h(nXlI50{QKVzGE?pNde(tMvZTg>gDBou| z81VKFzQgJ134YjQG#c>HyKgfZ4Y_jlSsRM7VXcYL3$C|FwA z;Mz0K8;??C(=ik|7gpOmb77Iw!I(TrS?jKHVXcc$9-~QykjCxlb|FgXdSaOQ`fHai z))oH)rygYLRd2vLg?8X7ydEh9lT7p8-6MYKu9~*hX=7&NX54*;E32f(g7IOGcy$HQ=%7_aOh07UJEXm~hKO3A#mwn)235Fm ze98f1c28o?*cxq>%$kA6)^f~XG67>)?}l94Y_Yi*^Y9==YuH$6vwdZY3tNly`vbg2 zlM8DdZr$~mj8g*N2GQt(wOG*%6orr|&trYDK^O(3(;Q_i^3;tz);bY`l{T$rfKrOk zGc2`yE494VVQZz$V5<4}$pDPy0X4mt(35N~Ml?cY)kS>uRIpGXilz!Sgs4OL`Fi0x z3*myXtTf0-Q)w4IoSjP;TA(;#&=%R#f zlOPW3@&e4P^sbt(Qi{67P#aCV8S#ZTUSy%$Bno_*?Ji}O^S$qUhgg+}e8gKn{2oP7 z;Q1aig&sAV^KLFy5@;S?x$$!Y7rO&0pZWKOoO@p_GR)n#nXl8^d|OZ-aZ~ zF&d8@@mM*#P&q`^DU4G_68w$7@z>efzHHw6@TT~}=RYsDFJEDy8PPjFHA+cw=fN)j z`!_yjqHROQI_v44tF0VyZk(JEfib358mb%=oEp)*_=kN)_C0L`(rDZ3$vHz6eXS~q zF~(-3lW_uNiN9jyrZarJ?lxg$ovT2CGCBD;fv`cArYtNja(R85qJ-llz|bJcGn5cS zaX=9@S=hKrr`tt_El{AsfI?>kzDF4NW;z{;$!Lf$C7uM6CzSbwBq@Y0bD~CQ!Z6~> zwM%^ay9eU#AKzk}D6)l@c{22Q>-Ij!WgG1a#--wuj~Y*H{Z5x(y;9UfEa9Ft{Mm8lvZC7o)bjm&4=q^&f35QG$YZo73$*U(m% z1k&2*(in25tTxRPvT%iX;{^s2Lz-m7afd9K5;a1E@`-|g)Cktr7s+$OFe@=-Nq&A# zHX0GP8kEV9rp$Qu+6DZ0i6ooS+r2|EJm=!YO;%T4r`hQc$3DHsHyIDk!9X&d)B(5@ zRshBVQ}%wPl6480@;%q}+LmUOMM;qtGr^-ZROGoHV?#f3{3 zSy^cDjUU`#Sfqr)?&VpY+knFu*HpGrx3W12DM5M42K3VjPt2t-z4Nf=wt83guaF)Mix_o(i2^ENhNWl4guXlR;Xf1AY#V&jOH7 z9l!A({O8RtT;2Y+w^o*ZCyxA}OcTHw2diMA$ok1?MoGhK1 z$z&?x&IT1h?f=(dY&YG-#RZm@7Fk?bB`*cv{q}b`IzHy;bj)}%AqqV%T-d@7TL!No zCTYraG+=XMg%_WDo~5N_(QXFBqlED|;pAbDXP>#icRtu*?`X(qoY0>XEOZ-8GtI4s zCm5sZ=7gB4)XEy#GR;w;=Zqk827;QGSLWK5&bUQqjcOG%I3A2r?4PInv$q~O!zYNs z0cl>6mmW8ECobz!u}`bgiK>L9Dy5<}@YcXslvh^z|Hgf;9@d%DHFMDHwMGrAHbqvc zd>DsV3oC!*O#9#Tnu zc=LeWhbtCIo?1 zgQ=X$Y6NOBH#1WCd={e``T6hEjWXw-|EGe7>bp;`zqw>U^}j?oGk3L8jQ4f=#|C88EJsICg($~yXkA%d#J$!@Y)mRgij zd1P7Ue#hQRSr!e2})CC zZmJ;@?%JxgJU5O)Q2_&BYNBi9=(w3<=S3wrhp8K_83V>;I_scwR-J|y_!wNEVlU3$4{7cW8zTqhfE)LYF}fsf zOo;yIyKHY?+V*xOn9P&F%t9z_)jIdG6UQHr5vS(T7jiKRhEJ^l3&u$>0o~40!HRi~sgN z{i|$mZ!(!CeEWxQ^WMAf^Xd!Nc>VR4Sz21*CvSe6{hgS!RNTJvfFJ$j9qY6TS*zh| zM?|;#k9x}XR2h#-NJ6+wP~{(hsBKt9X4jS7C`}DqDOK^>s`)JHb0bK}z$43Z`e!|gJhS2fg_UWxTV|EDtc~Z)Qkv>2T)sf6x~QTOx3m(x)WC^x z`*S5(ZOxnwL^|yj>+5UW-8rHtHBuRpNlKCDNIxQOEl`#=IP{_>)3W4;A3Val@c>UE zjJAP;5H_H;6%q#D6DVl|4y$wqfv1R~&;&ss!YCpPeHu}NMkAsTheV;r+WI}e zXIpx5M$DZ-n3%F88I1`=DwJD_&3>hWXdq}Z?94Md2lGzUP|>2hPJtytx-X(KSwBTaHA zcRtHJ2=Vkr;k>)2iN$y8IBTsDe*#|N2eM0 zdsCZIMxeYV;c~}CjRsn6jt+J?{&=6T)x%f%B}(IMmsJw@9x+R?F;P)DFZwo zo}4A@o=#b4g>+jXopwa3r{tyP(MiICqlqo=fV%$JICV$iGH|BepsjzPM+1s1MFtTv zZq!b|d}+>X4x6XtTbV=DT(Dvt=ZX|wDQ{Kt&N=XPIoxb>{Irr)HUFx8R0u)bj?raU zmpW7}d8&*_J!ga!8c?CFuNNlZs6XKk{@{;U@~4DRKzDVM)8ixF`{_@3c<&R^EG1|z z;s>+lb>gXeHFa~i+5DdiMCzcVDhZ$tu&T{m2!Zc=wkN=x+~wNp8c`Hd6eU6`27>|P z@t7Ic#0B8>xLA>e-~IdlCwY>H&f+rP_`wHUx_pJrjdjkBPw;|(lm3)6>)5$oQmc{8 z_&M_>R<4ZFy`x=r#8i$GmN+VG z*%QZyeOA|=Ck`ajAm;6dW3DY;6#Z<-uGeI=?vbY{YITVlr#XEwHg}Fb5~pd%^RK?d zAO7(>oS%1O_a)3^H`>e07n9*b;7M9leqaWSp>I*OP`YYEVYEsL8n6;M{KQixwg?}|6t6OWuNo4 z7*9_*e0+!FC--^(owqpL-DR2^j{6g5XYJG|N-K*i#jL!n>hdlyn9^n-(keUQ9A#?)q+7Ek#*_qMMBw{Y0m?Nntb>)g`EN`W2-*3X zOa?rD@QL~9n?Driy~niLZL(pHbZ|g6I3ys$lU6#UD)p^w+44#oLrH%ybtPDqjINV0 z#n~aU%+U^*KzPX33LCtMD#dJXpQ%&M?3So)i>deEdHW8IKUiZu)^E@l+U+*K^&4Lk?Zs7g_fIGa zjZhv*nwn%f6_f1=d6tvqIoio1XL&}NW|SI|G$#x^q<}QF4G5EILQ+^FzEUtYkY@!V z7l?5#gh}x{?aKI1QA*-_5{iTuF0b-e{@rV=t*opM(!&*g4v)_QkWU?P)M$5`!9pu` z4P=4}iL;A7ZnWGdEy=7hLNHqgl?sM2rOg;HL*qZ~w73`RKMk{zAt5YcqRX6vvoRkY z7`??>!ElzcQeKm-kjnZ`&DUj@khDPRBi7Ft_px=;ZL5h_rmg+=9+k{BV;(ssEu zj#OCr_ja+nMJx=S?-6#|c)pyIgq&OW&QVjI2TDG5k2O*ZwZmr#do%KERi0)|ikbUq z=M5U$*?6Yf<9=Jtq0sfY=7&`}+ct9`=dbOl(jEIQWmz&Ej*zm-lDKQruJNKYwG!4- z==!`7oI~cTvYdEjmFclybaX@ugKBlHI@a1c>B$kJgF~bj)ZCBC>D8{MNu~ZI%q$;J zb>KFRAa4OX$;!qu-A)S(bXyTS`^Q}0?(o91n|%MBhhQ{OGvuJ3u(`TOH}=uS@WF#K zrnxOk0T6K$v9iI6SMr;`c%Ab}#^JwqI z30Bsi(RgZJ)pNlZvZ>`J_)&=RRQ;^yo!GL}lv$2YmTX(aAHpH{Rfef*?;~rtZZ7_< zg0U*2;oh?{rE0Dfjo|-f@4bR-%g+10-&$+O6FYa`eCOUtn83jR1PO>#uw0Z%wk4ak z%W^5W><7L0%`bZNlgm}sgUYt5@csYa|NDPUCeN;12jC@(%_x)aiKK6^W#;W?SF(YA%$ZgBnea7J4mo*HDlx{_b9feanW6GoKU!Z&GDmsnPc8h*5W-UF( z&gK~1WN_Sb(!RjdvQl{75CBHE7UaS%os3+9(|BT`HA!`I3O8>|aOB#znEsQ&+EH zE(FQmRid>Hn>!n1^C@pV9#Kp+y|t^P-43VcGd6}@PNx~?r;vzrG4Vk zlJxuJM$(A`E??TgikQ>$bMo2{4L5}?0TmPPK80Mn%-wUt`Q(I3Ls1#DllQ2&i>;gA4nUnY!CQ@-~SrFd33~s$44BW9CLVdOdJIW zQ*l0?qD91HJVsX~NvBJj*^~lhmCu+t0!9dd@+LCP{Hg2Ojl)%EMA0_dBMd`VtnJsA zrn5NK$+H?jVSEpdMlxwEUVR`50w<*mqX??fO9F%Ce&T_-v8L@KBBde-B92ea`0ao7 zyS({y34ir3|EE0v{IjC2 z3#(KlYVCRidHS>6x*PMDWxdF;O6z~T)BLOd6v6o zu(+&KQPmVhL0*&|(+G;Pq$mqpR$3Ts0coW~lyyZ}yBeLmD99=>K6_eeCskEKB27tM z6=YfF=2?^g&apF;l4q~2v$3diglro){(l?}0U(uQc2y8l8!$+$im@W079kT8la(=n>Y)6B zS7EU-LTl@jmLW=pE@(0i?OSBa{58N~$s{(cHZ8MYtxFfDo#;u-(Xgg2!azz$23>cS z6}>AoOyiT9Zu^;ly_L%d(P~m#9<}+Ge+R-x8Lc!1|5t59$P?e+x?zdcV%>&aS!ze| ze(P1fKw=4#1Stb*W65RI~t4zDKn5HH~2xccEdVuQoF+vb; z?NFvYY?&i0Eu$}*Mc4N?5MuSgLnv07H{s+r!f0N(z0LDaZS(MG%-&|7NY-o*6Y}Yl zS8i`I=*GPL?ma%g+vN+dTxOn?%<__=)co|$nFBuvtkw{w40k%Dq2vNj-GTX(FJ02Rg5mBy4MVW)#`#*?+aDBZD&#Vn_s&*^Th5%jz5SXgyeDi#^p zWJVZA1Zz&B*7maTlccE!ar1$d+JaSpZI^7ESOO97eJWO`cnh|l_+k6AvMRZ;-Q&Od zkAIn+VaIN7?})s1#hu^ycPGk5001BWNkl8VKtPKHYg65@kG@5Qd>EO0KmlDsJXL^NhrDKQ%^R zP0g?Wg+Id!FTKpSfA9vs`jube*3BEFNyId(=)@u4`{7%>e(xJ(w#E|BW*Eitc{g(l ziR&*S9B}iv72ypgtXMWbZEA*u?`G{}Z?tQ3V+3HWZTkv1Q0GiX>|#oOdV;NM7Dde$ zzW5@Ck53U;Zlx*X!XVZ+h`N&FdCeEQeZKrBzruKyv10|DUWfVkjA&znG7uciYWA*Q z=j41t^niXR;$U3y=DiC97rc05ji;}#^Wptd7W0BmYWd*qF<*M|2J7oe|UjEYyW2i~`5Pdlo!SUB>Iq zamLY1(^n;8vf!;^CPt4>S>LExEJ_y9CP#-;rjtwvT~n5t{qZ4rB?x1~B3lrJihE;4 z5G96fxaVxF zbymOaxb}OU1zpu%2GnHm-CCw~Mbm3Xst~N3ukO{l^Mpab{=o_V=(oNuMBF3VyoHE+ z?B_#H4&h>SNN!^o#26_EqyStk1lF?1T=3oauGnfpetLkcD^Uwa#2OJGIs-)9Md%8> z7!xXm1kxm?GZ>KPQ?j~783{^IYi$dy#9(9Fsvr_|RS1nUtq4?;)9@K+3)-5ta38-m z;Yq+IGcH8aOx48-Qm&AV4H+jS2JL0LPEM_HS>d%o2ingn;d&P>_wyB5t1#AQQ-eS> z>mrS{vhP*WtRJpFjrP{d);n)i2&J5aPD#=vC5aPsUGU*YA2OPpoK5E0jGw{d=K$n0 zM_Cr4@K%B?8x1)8Y?lm~5H6T+0uf_;`<_1Pp?$I(d??8kDCq* zFh4z`4~R||EkfdcAH?8^tctKr(?_?VsRlLL<-N(~o|;=Vns*-0xi`uf^kN>K=iDEa zoMeEhdEu!|F7;E6&t@zpGoHG-MVL6N$LS(pfS?}f4x@KMn zgzM{AVQC6rpcJiZkG|~qC4G;|C5Jbmi=6JGxr1@MBD3mXb z6k=IyzARprt!}#kw7RY-vI1)$=_aks^AqD-F2|T%`MF#L*m7k}@PW49Inh>-EoOEh zGcmS>RZ@t<#}7FC@CPjBGqNnB*3~lmip!K)y9zp%W4p=XAwBT(0jHD_YnJXhSm$Zq ze7*rK(%+-S(jN>N34U2xYrQ#EWg_~vZ}?HhSYD|}aZJiIb1;A08KTt>_5 z#C;zGV=dA*Pi)8;>3iUq`GoA`)PWQka51mwbrNbM_a2_GxwXc-kLQ>mA+VZhRxzGt zymV`eP8xDH$@%)*2b|_EK+Q|dor4MK^>wy(HrN`b{Na!8@^G}EmLXgHm@C@@-udK& zy9X1VzrIcWeZyzIc zfz=_BfI43w<`p6yk}oVtXA7$(ha*F$8!?_n&Kg@6ltqNhE$Lp2NK=B)(2WH1TvBVp zo9{j#i6s}~1zT4HhjY!*<1@|N+bU@&zuB+#8nGLI5=0Zp> zxis2k3+u|cH6aM2kT{AEfoe00E*avAz-16%$^vWaR!LD+rHcc6fqxV!>e70tku#N$ zQc~3=o&FlX_$&Xuz5no$_~gyk3FDgUx1J_WI-H%)(X}A3uD^wIj?=EsixjSHmaq<> z77OO1BV<(yE1kiBk+G0z4-t2vE~)1iC@D}Pq?%6&qmb@kNTn+l^9i9;M8=?u3(@Pc z_B4|LykQ1S4V&@1xoX$SmTXuddz6ojTFZUm`wW3I*bua?X|QVN>!UcMecz`5i@~Mw zYZ?H!+!^pB;!3@Vu4vAR|9&AAtz^tNbA&(&gbEQt5JrkLQteu6bd5A6rZP;%V;1vy zo#pxcgQJ5peg==91CT%R5Vi??m&rlfkn%K^kJf_{@Cy}7jq#Jms_)Jpf3#X|U+{^w z=(@t%h>c;N>$~eVhZ(Enk{}8>9gP`XObEBGEdwv% zV|L+50Nf-~!pn@B$<=-Wn)HWQ(d7W|KoGzC7;Ob(EZN^DG99aP8dfqK&Cfi`FK8EU zi&+L6)&|D-pEISBq4}ncOAm}`zt}z zO)<40h@GVF2?o4*N-Ou?rhRS0zIq@c1o7r3g_KN2=k$do>&p&q6C+=dhBj=SnoJCb6yyFotUfJJ=PMzc$$$8*Eu>q=e>s)T)wnM zKZ!Uw&#-`64frt3^NP#2xA_w<|4HH~;O?EreC-==Q)dfQ7*J`8u$t?)pXb$En*@R6 ztq%`)`^O)0?bvTw?d(d0)atwBQz3~cIfQx zQDp@xiBX?%E^JtE>m7DFgAUpxNa4r!Vn#WeA;XAZFvKc}iUPW8eJ2H21t_wq?^(%a z2qzV*D@`%W!5YFiBub*?IBT+Cmi99(;P+#_9WNdzNF4AfvcfgPi$V@Z3;ywMe@8@m zh6)0)y}QfZyLWl;$p;)i`~)cld%N32QAq6z-A$9ZSsj0P2y9o36B?e-_>RXuTVR_4 z9B2z*o3Y-^bs+@ZPKU*Oh82RnOIN6>f{TkYSiQ@J!4!Utl!~|S9kY1%0o}nmCw7ZJ zeB&`UuI_MlG9pPLavPy_%zUz-G|*k^62#Fm1`$hOwalOj4XYqunLD`8XSl;auocUO_yb6K<*PwOR5#%LGpdcdyh%CD8QvQjH7^SL9n zBj4%0swx(+Qzy9xjiOuaD&PJc-AN;eg^6318&}UQvrCe_tPk6aK z&)7O!2x&D^LRAAYAnL7SRfH~c>e;y~ypAG@`2^`}(ZV30I~X#ZO&s82r9fYJNtF>+ z%2nGI|G1@Sdx0PY+BAEt11d^Nf)y#I^%6@ZmTM0FJ=qoGAF=YMwl>rQI*XyHU2E%X zXzE*=_1`_~#wytw?UqRy`p)Rq^^5U;Rzcup%$7#Zx-{v~lvRZgP?aTlk=LgemZ`!j#{Wwk?^ddXteuFMtSv#G!l^J(X7f|@DsJoka+N*q(qq7 z>0=w&Kud9ZvrOw5Q6Jd2McCbgFz($*1+}&-A7+J}UD~j^&w*$bt7d`m?{^hDrJdLZ zX?B^pY3^|qjI07HpVnW3F?SyzNY>ZMtz~v{PL#|sGIaN2eOkF;e#HulZ45>@PN#YH z4Jx*P(KSfJQ_sD~tIzK6JAd#KF6|EKS7SCrk5{f;=4;=4n@c-uY;N?iO7RQN?2)D+ zCuehzE14+I)LY?--5(uIxV@dSJ?QZI#e%Y^iIkx(EB9{dk`LbefbGO`^Qp^x`q5ox zrz7N6%Jre(&ixY(PbXa7+oU=>MQv=m%}g(wQVG1ha~Kj0`c%eml7lsxY-7;r5Og{% zSf_b5I83Q0V;3|^Nwl#^*y*|lSQZqcQq*u8Orv(xkqYzM#f)PW60*; zxe6p<;w>2iwd`i!jAegKZ7-K*s5f8Gj1><)kWLP>xR{|rMKDO{#St&R@(jaXLL4RZ z`dyxX`SZN>#v9a&F{WJb_D^1;s>@c6fSE8znPFyHFY7fB^!({bZP5f z{Md3ymgU&bvIRj9FdB_q!&Tpd1}swfz{nb;bdGtIt})i|SO3ai<;qjf^2Qr)@apGZ z;nKBR?5=k>K0Re;t;fUt6aI&P@?Es)IwJ|QTrCB@G{d9J#;?l-5WXzSx@*B&z=J}h93fCMoP!8xQC3!en@Gri1m%sSso1C1EIlOzHBuy|{ zb38ewyp-^3uU_Teqf-JZuCDj__`Q$Vf7~Sq6rbGN=jq$m$%=}LhxcHbBjc1RuUK0j zGT4r>wIuC!DCeilj!(I88@+_y zjXg#uBdj$XJU(E0F(oT&u0Q=WMNu+eRMeGZV`tMzo5o`VFuj=2?IxHaW0o%vK-@{4 zyiW$L#Mt<;83;>Jl?ba*B7h*EsNf{@ky;%uAnphPU7Q zlz;i#zk{BSJV_y`gz~aew@f1OEis4O`?qvSzg+@HpD_>z2&j>6S(Q+1+;O9Pp4vxaq)o^u9Zeprzix0 z456uov<}SC?6n@|SpRR=7fE2PGk0l;nI@j0$!s{HQpymlLEFlK6VEKUHNFC02Wh?A zo|68Zn7X|eR^z0`1c%muKxIW?X2tr-2Yz;rp97FT>JSpkGAKcarL;ygg~3gL?RCbj z(^aE^_J5{f!B;24A1}vpDA{l^nGh;TQI^y;;^^@{r=yVogOUofI1wg4BanhLiG1T8 zi3%dpPKV*z23x~z_BJ}mD&zKc#8bDf^5Msi$%~SmYg^=%W}a(mZF%PUI`7^+Wil%r z%g{_JYZ1z2V}zpzT1X`~zGmS`w$jOpmO*}d`1*!=Hl-Smz!;Lj0NER& zy*}4HQ{O8=E{jc@*Rm|OwJQ_d`giBvQxl}M@)WQ0wa~gBHTz1FeQAro{r9#1h?TmQ z=H9J!zrQkWn&Sze;#M}&^$m(Jpw4oH6=-nvG(vbF(&X8ik9vm{>w-neQkn)9R7hzJ z-+SkXPmgmR9%Y=DinGy-dq+8sFAVz!Q;tV-3K1}=6~F((d%XJeChvWE$i+A(?)BRO zz$VZWO7iaG1t%AGdHL2BkLQ+PZIeb8(A?$6(}I)N9`eFT#VEJ*_Ac>g2LJL~pHP%F zQ5bUe$uZ?@PM{6p)-I^f_nLVUtcATUL7F(At3uyPV)+bL$CZ0c()BBtOopLi$ z+7%^wz4$5(Vf{FiN)jZIbET^_yK6oE{4YPp-g;^`hCLC70Yy=;ZjP~Bp`4HT@Xha& z)z%ksigu6+q-XxYSWTM5T)w<#t+gB-pNK5W+rYbFd>cN}6|W2bE|yMm&F~gNFdmQF zqW6>Iqt=1PjYwJx(uPq)2+)@8Ejr+b7^$Z4m;#@ZU$`4O=w>GZqQ z(zy*SrEsF{wbDK}v1AsT>uG*weQk(rGB5(K$M?@kxZ-r@c4b}0OSk~An9WhRfVnDb zI-Q6xkenQzl5P&zTHj!A*SSHRoK3N1L47u-JR8yPM05vzZasICtCu%9n-;F81a1#e zQgU^#L!boXNybJm=Gs=5yLS&sLd8X0^9TRtO)g*BWHwu1fusEs4j-NH2a^R+7;t)W z#{CCpop_omHdJ%(8k2)K3ajG~yIpOr-2jcYpeLFjO!2Y|C zXH)UfC-*r#cubl^Xqixyg{!IXGuTao<$hyvGDH<9OzmWjQZ7v%R1hFl+>R%Kb4W7A zvbMJ70C-&z$rx)aosM(vySTWZ)-_Qad3lzz0XB8*zjtX|BYho;!UJmSyRJ(I9GZrA zLcnBl!FwNkWWWE~55+rgzrpouH~8S4cgW5U**`jS`%9P*#3@>ZGz^#UeLo_r!PW>} zBSb)DBi#$|+jKw^pK-r9K`ZBT-}7Abz^8Yy_LL&(~nwOapE6yXszk5ZScY` ze2I(mQyx6nr?NHMyO&sG8A;mZ(&ei}X$LJLv{j%bqOP&FVlC-0TV$M`-LXlUihde$ zb*Ia-mj@g^I^^Q`lwW-D8ee$j8i!{y;yC91;g~PIaEXV<6V4~O_jb1}<7@q5tNo;P z*;M6hMOT8r73B4AKh1_s0fbTrt=mk36auuS7>@~!Mp($l6QVdpM6SDhv*0unzNu4b zekzQ>co5h&d7_Cm1n`;bYJzsV{2SRg{#cel=SsGtxsT<-xvUEi&}K-49}2CPkZ4Qe zmiJ*C%N`BZpx?+<{Qa3_0bX;l%M^J7c%^6Nn{>2Ax%HK`?Jn!aI#R^5Z zx$QwnquFm{fEE$>279Yng_W#R(`2gMTpDR#10XDI&kL2r)B+ZhDHcmOSZjmuCIi$%JJP+tdyZXR7FA3Nl3cs6QD_~{B95`dc&U66jvFe@q%xC z@27TqppaO~`Goz0N4)*sN1UG?W6C*&kpw}oTxFWg8`C<(HTv%Leo7REVm6;KpJ!gy z*JLG^Ygt>Q?SuMOe$@n!e*8Y+>i3zTV40C}XH`NXf{?%ekA8!4G2!aXr+Ijqk%nJq zXLCrA&FJ=ey!+{hO7!UTJCuGs)xJo)d8ez-u6Z@h_ceVLWCJ#&bgVMVcMQG-n4PZ4dd$PaYE4oSii0 zy_1j04j!`k(k>gxHunyW>2^|{fA%^OxVV_|%IB{0C%^I{lgWgap5Eive)UEE&9~p; zqfhp^eSMoM&zaArgtp=5NB@?h~geFWk6^lB;edM& zPrbw8lP-|U=^==y$SzJPPDjL2psN}ghFHJ$n8kuPjmVXtuH0fBBr$njQPnOh9;980 zy5{tJ!r%J4|IkurLLj(*?=G{f5`$is+1UX{M~4vhP*PClbA$?s;sh0XP}IzGFV&Mm zp_FQ~8d3_Z*3??l^r*2~yLHDCHenDrXDa22`>RSjg+c8IZetBm91$lmRb90`vzGIB znMrLJ`C8Y`PFmZR;TK|=wQ%6h)mj}K9r2HUd<+KQdbgq}GSTH+30qg3};U>63S3LXdZGQ2k8)QYrt=l)z z2);AgcNtZsKwGvpH`(0i^XUE^vf`X7pD{TMcLRhO*B!utZBb_$SuRnf0rP;^v znagIKS;kMoXN;OT?5ou<*7!p8kfz2&2nE7;(9tw(H8j_Nbym3z2yH?cVe2QG)d~+T ztg9FE8$V6+#w8KjfI7cVcsW_96hRpA`0!-*>7&Qr{OG}>?~f*nZ~x+RU(UYD&))HK z0P;s1W@V>q2O>?=uO{epo2$euN%4j_rU?pH0JgAL`^VLYtQ>ywByo(CilWF#I$b{Z z{B0s>NIP9#c=2Uq5D)|rY1$>vrxbYxwq|p4mo)8gaCn5SYdh$q;>NW-kcywY`-n6N zxOH=fG*YZ}V@hp!_4X!7;1{%I809Vpz!;1W6nRBmX(tVfBzh(Iv!4BLH}VF+G-qm9 zW*;cpCvMtrO4ed^a~_FmgZR~8Ts-ml)}g3jKJ9W5XyhfZYA9gapwtEPwsmrXWiao+ z01Z*&rCuH+crehS6@0D8%9we=wWnp)TH?oDi*Kmtvf;}B&iL<>G}q`QF*q%`*a^6{k#Og5j7|fTfFzb&-AeiN(K#mW5p+_X8NdtAY?0T7y^S6}e(OH3 zzq?OoX9pu(*Ig+jMr(#K#F6CV#~Dc+w$E4!i4m@2bgT@4kQ`qu5K1x0oS8!$N=D;3 z7o}#3 zv`?jnL4Z+$tjvkxh%olfO+GMkV6*X|rww?U@zZ2qmL%8;AYJ*r2K?g3x~VmFR#Asx zJ7ydAuLj&Sy#S;Sn8Pq+bTH<-KYS#1)*~vTn3XVH)Eu2hR11YDENSB8cny$gTzZ-% z#@Yt(8gyL=qd@pR1K4n7DSA@x+&ufw{=XM$(F6^vbx^Bg-fhULT~DNNl8FA+6@<7! z9(Fh>J1E=1+AWS|=L~EJ{T_0Xp_IYY(y{6u5H`=N)rhZrchk#&wy0IKM1hM9g?GJb z$O6|WG4NL71{Z|+GIWyRfC7Uob0T4!1D=ifoqAO+cHP8&}rY9R#d**6DxcIl8ju#*NEtU*6+%H0HI}-^XapU^rkro%7CH z@3FhtC9Fz*_#SEA_W%GO07*naRQ(^&9Sq3Nj~FoJop(M${nD3R|ElVMZkkXORXc~J z^+BQ^b@}*$Vl*OAlBy^`x*au+V~_#)WXhnIVr%V)841HR2Xw}xGX`txq?=omMaD-* z`@HkXxv1)jUbjOpxz4OO;)8n+C?@A%G<#Q4q}1e~j&mA{5!^qbo2|$~+7fo4Kgq~P&dw}(w#(C1wiDg%H*Na2~%e8J9 zEPGXewIoTvbe8ee?|wks-6ZW@X5-3bdRL!en$>*z$sHz@Alw{cg4hvmxa^XY7E#Vw zOfIn6U`0qW+#*@upvV@C4<8}wnof5>F`se&!6C=zQ@-%ZbDWQ7uF&2XbX`+cHM*{u zP7K*%LZqOWPxz<5@eiqrj9+-=WkHglNRdiWH*BJx&u(q0z3eJ*5;dv3W0sSsYg0KZ zVL+*3xA2w{EDw<5#x%V%?lHmY<;x(!nVAR39vO619E1<8|uBnSe| zN5{PT=9`?IonfsdiWAO`5A4Ooh1k1vi8yp!u7fZl2weKOHX5UA&PL~iQ9@PK;@b6F z%w}`$e0twLH{21w_NQJTPC^bZGTy&;!k>8MCU3lTpUpwaFTQw2N#s3 zMoDKy*)aG`ci7gYvE^}_z@6otP>6TPRksH?T{-L8C7M7dwsOlREs%5 zocbwim(#O3lYhlV>vo*UmG67fQOg63+Bim2EuC7TZj4llD2uBc(`8W~bkklqCQ4e279sl5t5n!EB=*@b5>sm%h?Ga7pkq*(ZS~ z3amw2cOSBmfgzAIfg{d<0^x%aFC~-$VL*h6!OkW!o3c1QLDw#TR2%E0>l^)>Up^Pf0on zkH7OVL6u>t&_#_>l0XIoWr;3YnfY?Q;rAo~wWu-0g1XE&J3V7Q+2;PIpK|cw1?wF_ zp+nN)Ht&COpV4^1-Te!a?Q4jz%kO^oM{MtIGo3DY@279^-1E=y#v5;Q{mK?wS8uVs zvq5MR)`op9#&gnM2cs*7NyV-8nn2XN`)E#$U=Ue8cXOL;c80ABgzP%@zvGH_gD^n( z-ZL1B@N*=eEeNGVSCumbkdnI8bO&y|FN>1#=#;8(j&HiIs6~kof;dU2suD3dqskY= z!Vq@{AX5kfit2)*s2C2{2zPc7Dq+}D6tfX|X^FkN(`r3py9Nj+ufl>6E?BMWdS$I~ z4Pm8JPC_ZAcf-=Cz%?ZdDp$j{nqsuRW4Y0WZm;L>sdf!$5m=>K0NwNqX~2F{oQ>ZP zglF8PuVvD8O~2pc%YW`K+F4$UAAj>}Jow~8u3g!)m$r9Bwbw@5=O@^*#41HN+$P!C!`3B>(-VX-q@4lt@reE7ilg~GioD?CJ4Ynl4%Ya7Ibnb( zY9{9=ge7($rXnw9?4MSQ&(10I|AjJBu3uTRX(ttFnz}@cCr_jbg*7$SR0tJ=2rydP zD2g%F9IZ=?m0~f!u=9&!(;IGxPH$6|Rc@7ZJ<^=zZ7gQ9nVrq1*t%f2wkEP#YaB@q3Ra@1FegzdLhl=-=UI_4qje`OLB1>xxbs zODUX&*=d;@cF_7DRJ07?(pi5gSpwSnC%3pc)a-&4;Xehd%>ENF#8{waW3A7|))rN5 z`Talm24`pI+&n+y{rBHzePe^Y%hzofCBh=8>zbmhSR0Pm*}cNf_NE>7QxS)fS*65J zKOJ%H>JHhsWPdbgJ}(%};rL=sQC{%z;heQzg3(UyGoQ{0!+>rtY1!R030n}>a#+?` z!6ID8VFPVsU|0Uz)PCSufws0mxZIL4g0SBwNE4*ds4zr(cBeU~waX{fJUJJCv=E_X zmRgyNbt%|3W!|vq;5DAULv;hPjG-!OS6m#rLcC^kTCFp2P3{a)8X*H;Fz;WVZFKZP zQf4J}U6FJWf>q|LeI9NjDT|t_C3YQWX_eYobo#Ed6|N+4gC$hBy%1 z-s^IyCwb|{Ro=dL#=ZTLSD(Jj&D|caKE1<_-h0IR?;rEb%^hytSm#+OIbW2#HO=Yn z?XoyNKpgFp?Cg;l!QLR|OV4Z*g_2GZ@r@tfXED#A0l&3j*a`UJ)0=bx=-%Gs+i&kv z6(zT?Z}7~e4#PC&Xj1U|Ke)^3$(T+rbvow77_yA=(_@Ws){RmUM8Ok5 zzgQV(t5DtoB92ijbr}L&!$EJfV65=cbO$O7#s#LI8B?Y<6!RRdHE|~)j6=szHi5bS zU1JRSqM(>Ah&nNyVb23fK@>+safDo%;j2_vBQXPf5bSI|lO(3!jY(By*TjXevqK&q zo-yBlm$JyI%M5gh5W!N4=CgjRtVII6WD=~d=yg*z*ZM57l1lr6NW0qmqdAxBUM+wy z45@uhM+Dn3FyO%gWKC!2|5|8%J zJa7_CuTLLz`EO~i(P#S_1{$%;ift1){E~@&(oT z2vby86%cK1p$2QrN=ugIJbh`4|w5hqkd!K{Qqze5^I9v@FoNrVFO z(_^a11!X^BJj?in8@t?pbjra;A7aJ}Y9U=ixi~^tORXz}at>=+*B;ykASD47VKlk4 z=qg9pisOSL0`VMMySse+@tjEOd zIO8Zw_~i9R3_lu?Bnh2vhpINLZLD*0_?SC)BIf58eCxe$l0=H#&;JDqney&WzsI_o zlE!@=9gP?jIiag&cJ5dC3>^-9e+=O=#=-@^wH0UtB8ovk+>JQ9n4+w~>Y98}5Coy? zD6Rs^+R*L9^oD&dPS043PU&|7p1!uhU;m4Lnrm0DFrF{?)_1?pCm%(;`rwBgiW4lZ5WC58F6MKzF({?Hv

  • e_NkmS{A)sH>@R4ft#bs zcUbqUmbI{0WPJXWXZTxx^S=;>=QI9JIAK1S@HhV2f5?rSH+b*EJN$Ql`|t7S>=>#N zWZ*ec<(!?2>s%fTwn#Vk(8e-8I6_)WZ*7g~`3R#T23uQPyShgr1#u*?Qu4<4_Zjp% z9L&b#iwWJx@Z}e;@!V6t%*Xdnn9k;Q(C>T+Sbz0|I6?UE+S3N&%t zmG|!4;mvpNiq3F{t*tHA1_N<6p4cD!;0Fv+>|goI{{eSCzH7eu&F_isV4WyREErpq zm8~i*e)U(r#0xJx&yQbw&Dd~FCUGSC=cQd+?}O2(Fz_)+jjl^8q!eR4u_{n*NeDus zz#3z$h?A};^U_|7?s0K;iq$p!jXja}_e5RSDCIKSS(Z5?AQ8Ikl(kfgQw|@zPj|RJ zo>cMMpPom5Z>+xfyT9>2{nr=#`~ZFqK>n>`x+oV#RnMIb9!vUrg>^F?j5I8?>tbvh zdc5`37mXW3%Lz6CR9m%;OZ*%EGq?D}Ny3dAHwgnpZ_uZ<0de;Yu{b>E$;vsN+%SqfrrmWB8Wjq>Z)XMK1M|m z-Ob@LMPZk97fn{g1(JRoc$b(qt#33cNhsr#d_G4-F(U2xq3C2jjrg#s0}vhrRaK2C zE220=%E$vo(Wd+xX4+-)Y^(JZVp)42L^H#EQLCRX1`r-78Er7NV~V3VX8-Vl|MQ>y z-(ss%5t5VXfJdW@Pu_o@$;kr*6jC1S=Kc#wNjV4U1r2)_nhiL(WHI zjFjXuB;H;_M2WADQ#?A)`Of=C+}Q0?SV<^hete9XO_4I7(1Ld!jw#gvv+@V(dG;qtXzY&2vvTTsa% z1&XtA$;&V9u`2`zCl`#44|wk8E}J_;vc;H1u6X*!25}Pe^>4n;=xjn+jEK^dn@`_D z={YrUwlK`b84ut70D_p8uGbW*;^RB}q^jiVv#;>+!wEWcz}09sSA(QOT^m#+z5Af> zM1b2HJHs{by@-;vE&3al>inE)Iwgo=f-qn)Td=l1q^dRZ>6EZ6scVZRAc|9ZvE=6~>C(+( z(e!c9EnBFc$jCX<25T*07}DwX$g>QDAdVBlFr=z#7K=Gqo|C4@GV>p(7C_f}MZU9g zPB%`Kn-A6%_AhI+EO@)yKnbdR!Q(scA&Lv0xv^)Tzp*QBUfX1Rvd`L}&;I#@s;XTt zvBrb}*DN<0Zjo&5g4Ik99wY0VPOr;+e1-@j!hRnSM%=uzfz&y=Dw$5k7;OpDK5058 zj8l4pUGAP)Q709uv&+U%h+e3%Xny+MJx4f6B&nec|`vgK;>{Pt*)_s2T z!7*#w3ENu%{a(r8=~VpTw;uE2juwCYKUem{Pag2?AKelC!BBL&DRB^pMV{O7_(EL1 zblKi|>M8sBkKdt=cf{?dpT!)_L|LDZ7de5HzP87RvMgCGTRc+Y2REy7l;j+~xA&O!LUS*#+PDPOR$rlSIXD8XC`}6VP{l!na z+Z(@gWP0EJ$A9a;eZO6te|`Wz2O$5}@%H1xJ71Vw{?>Fc_|jTGU6-n135|0l5||wCfmrsHz5?V?Q0T-0gXe9j6z>~;j@YmsiM_WMWP9B7cxSJ3}LCYYwp|BM#Gb%&l+?3jJ(>Tn4Qi96B z_ufCD8#$L5BNUZYy#C1laBw;&7ZI|~S&SB>yO-heH5P~a zgl8vQs7=25!v{zy$nuiuLc45^e=mVjEGonA|Ku@o;C%cm?Si+vM+;6a3c%HqEK198 zZ_|M;V+l95D6ue`AhHG3=@IeH9$H3dDTz8MGEnWfvVM#?K)F(?zf6KXk*R9Oic}=q z+t}fnGePhUODnlce;)rC0YMm$bQ4Szx_%Tin(t-(MgzE;OqdE(6Xv?#e_|ZA7w7|* zWuTug3W|9~lEy^6h)77T+_=rgdY3>2^w!pRUR&0-USn}_L?kpHzyB6mm)?SVWsLf9 zAw1Ju8;b#U%lXR}Pq78zNVugo+-7%G$>uZX2fR@1Wu zni?)Vc=1`z#<5KsjM4l@zy9l7z4vpGkGg(dv5O7-Ow98>!*N=hu0d8P2svt;lPdtV}yxjByQgaMDFg zjh;%sPe z4Fdu!$ncY(2SYIQB1n)#*a9Vrq9lu!#W5*JA~}KV$=%cW=2*E-K0B_p{IJ$Or|yV^ zCB3>gFw^%|)jhSt+IxTBKYi_le329O*HFDR2NUUsPPR3E}DeN7R)@ z29cX{g&{d|}NHJL8a8srml<&-n1+8A3{5WTu2I#ob3Iw0aMD{pL3R z{eSW^+`0dVzx$8B#(N)p%rE@>&yd%G_wPJmeQk?Y8Ze$@1WM9wcZidOZofmhSa9Xy zCU;Kn^XeCWhThs5(Z)KNjo7k>)JUyi(;G4hqeV*KT zpQnc>eEqE-i2eQNY;SE6C2gMX?{lz!z|qkWckbTj?t{l5XFJ>URW39 zYK1eful!{G73UifTk9pj;6N<*UOqiN}1+B$!W036&)N+VaF&mp(B90>r%1*OdoRteJg}{i=rme&pYsHTq zjKs6ta8Pez>H;ky;v_{_&0;=fkynhS6Co_Db-O4fh}&&O<0)mHiz_eRrq^FXjteoH zD)yhjbUNd6k>yM64I4xWL6k}<6=4{lq@^tD>7p#&do-N<^P@a@EBW-#eAIgLzkT?3 zepdYdGG_PxYx|@D`LXR=zxcmSKl{>O`IYr<`%||9@n>5}95%Vz;NE3T6za;~(KH+m z^>Gzj6a)38I?-bJ@IDWoD#`b6n~AZ}4* z3yjtz?H*Q!pdzokaMMAh71-LN9LCK9k%3y8m@zDi{HCaKvA$|K30X7);+nn+JiEXu zJ;*<>rFBJrF<(&37sTx@Njvs~rdCYC%3tHP!QO~n*M?$IprVigI3(QICf(kp*nh_2=$LA2 zmr6$HS|K7u=%%*$<`j$-j0*#~XAX_^`Tde%;h^w_2MnTss;K>}21&fJO(`U1GDPMX z)$sx0)*e9;Bg0^M`fbx#@*;}>=Xoc5vDw_O=OkKEV$YM9C(oDIWO(?`BQ)7OKkOHyVglW z9K{%2u@g+FsvDT9XP|D? z4MaZS&dGv6DI|irD4CDO6!R&INliW(vfjJF^_Oq+#n&&}Gz!Gi89X{!u=ka(^5*Lo z`JJzSgX`CCAV(=rv{|hKAB!%q=MoJ4JHQ$y;|W$q$aWhU22_=kn<^!l&oc6?rZx~n z3AK!g2V2C={ViP~fA9H-zx3CB)z*ulDC-)dQo5ZM51!qj%w`-N9+P%^7_FHOPdOV+ zh-1fUI#ajzbO^_0O8*XBCQTs-d_&wY7D~wmmqID!7%XdD^s3R1Qor z#$eAem337ujm$w5d*-8B&OULUX^_eTX8vAu?5BI4MN!DpXZ!rszwvj3jC+)=E1YH( z|KPXpA+TJ!utg@i$hAG9{)UggmtG#~Ws6obJ$#NbHNEvU#={{*DaqP8x^~wpP>NcY zRHHFiLD=e0E@piE;E>0|nmCHU*4Qe?)FoDHgwbf@SW~%_xYZc5Kz?|FK%I%=K08Q_u-NFxu5-tefNiNo8I0lvb%YedyfxACkEox=#&GdUhl63k$=>PcW(UZ5nJ3e^tqhI{R zse9V|cYLz_{@W)F$nUfLwZHH`-re{sf9;>FCE=HMH@K-y4LBrE>v~Cx8jpNnH3E(C z6}iBr;Ya~d(jjiGi6-&ryz#SnQQM|qfEO7S+{*{+C$!c%LT6wVR3Ydt)YVceYl;jj zD-h)>hEoNos09SnMMb`t6Ls3e$`^Ll7cA$dkK+*-tUHdfDBWPUNV(!&3eZgyT~lwZ zW~0>pg=xGt-I$uXaz9ubCw}0C$XrchRu5E26i9R{q1M(7NR(=c7z^prV46-y`T}Fw zgqZV1kS{!po13AlX6C`FfWhL6nAQ0Y0<}bu-OI%;e;+t$mki{KO^$!K;`gB$BG^Fo z=ee(@acXq)tJEHkTw8p$nn%zZ1G-X89knc?n^h!z<7KTSkP=i=*ox)(QGr~ZkLLHe z!qKq_L4S<|$WITj+7fJRBlj+n9quDek4U%osFTQ}fUEN-9O#V#YOR+I4gMSiKE%D5 zG$!n{QT<@aOe`5H-yDeZpK*?Td9gHJ_8-nua1OC=?t01U`eWVS z<1{9WLU%k>!O3jQw|?(?cCTwh5=vWCMm&1_gde=~BgUsklx4weUJ(Sr3sQ{cKBLMj zU;qFh07*naRB8Th{8|ix(5f(ImW{-dr~6LdpC+V9#9F^Yn#Mv1NgM@EukL50)LOI1 z3fip}LP}<{nLA!Tc&k}}4t*5oZaIH{N;i)~gduIQ!LjysC)p?N^?`N}MjWYoU0m<4Li>jikDxzK&;us|b)#wy6Jmp?K0TmMVdXz}C1*=1Oac4JCildf-|jHNs~LtR4sq*!YQzy$8OpvxMo4MmnCY|Z-S8ltx7yh4^Gi+GKXhBg1w z|Mn{^&W>25TlD)~e(`VqEuQ?`PjUaG;@vw(C@Dzdgxp$6U2^Z^I|vn$N{CurqK$}I zDa7+PvB~84v%G#A*2_MIf<$UbxaxRCLooelvuODx|gjwPyxEGF-8*x3ZW#{STD=+p%`K{UbA6XrF1~$Jg+&KcZrj$h*pB^2L633 zd7w2?g~%wS))j$>2m(o6YXSk%)J%@u0M7nko$>Gt9VD~{n@(;<=|DtNQ;ko+XySH< zd^*MkDYCasAq15c)LLLl1+`jUBLKAY$1E^fVYES^u)1(ytOilJMn|a-gj&`XBJMC+ zboixz^qc(UzwlqlKl2~|Y4hHP_ql#+*M9ZOpJhHBve~Y!5?1_^uYJp&lpSHy!~t|l zGB0XAxci9FWXAUHE_LlvJtxySS?!b*Po6$wo|Pa%zW?3tbLG+nwl~)}7z}ufVKJM4 zt_Y|^HJ|Cz$@JmLXnH47`tHf1{Pn-|=l}da$K^(Rvi%!upEMwU!1mzb;r=UEw~x9l zbyIo2M^!9rQ4}J}rrso`ooTx+u+_xYb!LmoimK99*9c(?d+Ek)aqZ>LyN85mN*-7i z$go5zo%z;cbmga>g0(e*fH({oB!Vaftt&!NkjTPC|HYQD6Cfe6pf+YcrB^4aAC7U zl1NU@=9FbZD-u=X62(iB2X{qE1-vZxeI6UnjwJI~gL zb46jZKduTE%cA;x1A+k243cY5M6p^gmX!&*`CjuPT#+`uk@e@cu4+tOxoa2(OGK|} z9vkVK>U4>$Av--Hkq~e0(7Jeq?D=EN(LSx63s|AhzPVhsK*Ca$6^qdn5rnk*PCE1g zd*L@J1=1yrptVL91u_bV2V0Z~^mL3`%&4>>*xW$|kq-(0VW2K5veA^Now|a(dB6SG zId7V)733;b4cxi&Cj&(gCj?=*V!h6>T8&qrVKrRyaZZ|ee&C+}owiwf{%4v-vH80* zzppl>z=!5|m*)#y zys8_jwq#+1YmcopsP;OjgsD}W)?LPBo4DNIFo!6R*j9`UW(d!mS<^@-Em0_0Z^tYO zmqZjO$t0_3B>{OTsY-{g8w8 zlbPlI{hapRF44&|n2d;$h?7ZyZVw37*71W{pmq##kj4&?x1f!|N`dkWLakktYmges zS&lAhtOgmygh{}nnjvGw@my2b0NCVAE5g=A%;JEjKX`{Lw{CM(w0ZP=M60{zu7Q-a z+HH!erYuU5G-YFBoy#}6Ji7aUlbIAR-Pq>B-WFefYs9^w<=PuxVdugH4&Hz2*bU)| zW-N3DU4k&dh!T-i?hu>Db)2Bu9gMZqvnj=JOskc+=by2p+dJqmp|%bvYlfvZ*ntzL_iKZ)%}L zgB?0go)XKr+-88MF)q8zF&+kOT|_yi0hjRXhLd+m*~~mLly$XCS#s!-`)n!QTpa70 zIqlyK#&|%;xXJP9+BQLd(@QVC>Ox3@P%I;UBNec{y+)uU*`i=JnlL*(Mp{jGeT~uC zDK>7=+1&F19t9SQv^C}M7+Y1uogT$(%&nW3x%TSol%+-p%Ln(KVT|GRmo6fOrLJp^ zPKG>tengU_OvV$cO4I4KNaBd2{X_OH?C{F1t32O7<>AA9N?m|dXl+T7i1qb8!_kzg zy~Wo*e#YPYdtbAE?mzpJ@}*Z^XEq(1eou+;$_1W1eac_`8^6pqKAekm;}vec{4&;R z9^SvtWI97v8Wnd~TU+Puy@x!0aF5G-o7}vzNw%1>Sj@S8aSx>;&Q1>b!CPPF({Fs1 z*Y*U1*Ef)+#n1l46)vu6F_{+Qhey>v`kfCR{?gkgkM2GFhyO6+lkMMX`=kN+1GYjV z>sot#j&vx#b{USwXsl^+xD9m;y0jE|E=n!PDk-f6s}Xsjmk7lR)wla#|6l7+0>x5x zRb&O&m?(lM3i+9z`VwFGa$sAn7Ij^-KG+n4!8%eYs;VXqm6L%eLEP$4Xi20b-~7SH z{Nn%pU2ea$L6juCcmJ4vw?$rRR4AFu3U)Wz1cBnw!IX`)l;g9RM|a%*#AyOF34o2n zqsikogvvR}>q^s06`#8`pce~HP6Y3M_jkFrm2%_KE_Iz-Ycxtq5Pr0fH&jX)u*fQL zfAoy}_z|yu{wDzOKn}lI-!NRQ)|94-gjI3rub8pkeCxsax-79c-+=TlmPQAE4i=^?D*&Q6TouXZ zq4ec$SnAR-Z$TI=QGU}ztDa-bIQQ~vUN9Dxj0`}P7c9=kMBNUZ^`4g*teTs;*5tD} zLIt#YeNw5&j`xuWqOBd$J?9CTA3h`5+{38QNmb6tW2~{525nx}@xI|c*PIC<5P`c6 zy3)*s6T&ni*jOXp*rGsSrbEaxs?t4*xtzce#p zfU>N)yw&5s{!>54V7+UDAQDNdg%py1`LBMPy3FW=mS6e%zs!8GKn8ME95s#VG8s!! zRy8N5Lu%c#Wv!7a5Y2foR#4Q2tjrkCGn5(&Yu%(}2?WY}#)Jm^OoWE9YnmNb`g@Yf zGpWtJfgAo+*ERq7fAlB$;+KDt-}?Huc=OGl;MLooqLYR^KR9N+-{r~E1K$7ZUt`e# zG8S*%w|wc=CY!yG`}-4KzrIPXEnoY+2mJKyZ5~BAKX`9S=$Dxi5Xi*05cU*>bZ*^2rEM1fk+<-~Nba?;r80KlW#M z^YdTk@u((R-{X7Vze8DRl1`s%H?A-oPI&g{IhC>8eX!5xKHDY;W410`qa@(N`v>&b zH#s^QqQZa=AD;63XiOLeH2tda_oA*B)U}g^N*p6@tsgq*87^Iw1k$p$*5T}Ugcb@N zMAUZm%tHA17Hj=`Ns|pnthHlo9WpvSqq`*ugAf_D(WQ$G7h#GfMu@<@yLIKx?ee+l zAtvd3D#mF4eD!m{aB?jv++1>t!Pa zN>SG}!Ws_{)=L(pVVfm@e~wB24z`{>sda_c0ZJ;g70amd75L%*UrM4-(d#7Sivnd0 zlapi6C2NBX#={XNXw%(vsf4C39q3mZiqRQX*TmgE*>p@41-$mgZMxlrY(Ax^3=|ng zYv$u2H?QteYeP1lbN%uzYnubU`|WqBDB0a!V|QmjK+PMky+oep+`PVrl(2s|bR!AQ zhV1QZu(P|x$?+L+9P!nk`ICG!dLaJizx=oPbN|JE$dzk1C8pxpvwQZJ|KV@&okt4Y zxh~##{nMB#BhO22zI2m!fAl_=E?(r;t*abA{+L@kF+cV4ZQlI!b#`_(DYGG1==L@N z!F)DG1(LP?fG`Y^U)>^(0^+nq6eY}a8%L4e+g#tPpZ@i~@=5dY@34K+fcycQRJDnM zpjv)GxOmK3TZ9PRq+GxnL8&#RiA6!*QLM^RmQDs0Mr~hMI3&<*P4TlTbR6;PinFRR zoDPS?QB18hwVAUR9a0-1W;0y+(rlmnB*hp@tKG(kkXj2=7_zgq!PP65*%)l{VLRZp z>jN%yE$@ANhtvf8(J#Kjqk{=+otV=}#(F>H@^+tZe|ShMjrdn*vn8T0r65V2_SijG z-3whCOFmmTbf}vW`N^UR!DKw)GcOHzvm?1WHeA2dVq-%ftP;({c#A+vC9JK{+Bz!O zw0YP{xYZf(>SuR|2N!tj!>8C1Co!v?k-JgF2q~Q3#LIrXiDo%FqDdWEvJSo&sfvoa ztbN*)!iomfwM%48GzCfRB}JhxYFV|7`0J%>&0;*qSVP+H61SprkiT8B9931bm@GW# z+9ry8$<#DXviTi?yr`Lvrbs1;+b!ZG@=_8wM6%ZA9I zkcw8n?dBLL)tn$-ireL%&sX#g-Hniei<7OTA{uN^T7jO8kokh*# z9Wi%K%5|P?1C+4Xs&cIaIk}!5q@=S-<8wcxmVPvn4D@ z>m)$c@YG3Dgg~p9WP2OgidPa)W0zBsRUlE;P@JApPbY4wbgNBocZ>Pyka9dlN|=_= zy?BXG3H10B6-W-o1-iRQAQdLhoD>IFs7iky8Eue}lYR;*JWB7@OAxu>2Wu@N2#I@c z=0<4+c~(2$4u-%~eEL$KKl0fN^gAh!?taXZvgD8d>7S?DPWj=T_u1OpqrWquJUpe< z?~qlHw%a6WM42!6ov(kFosAB+Z(g9(hJ(W)!=mQ;m2J+>Ce$k7U|2BAYXap4upvNL zK|Wi!H4`X;Bw;!lp^bZ|SS9^?1ytIim`yp{Kc%*UV6cvr&ZJEfsoo$^=k6yf1g17% zoO(bDfkC0#9qQUZ;XMUbVo?|skd-Bfiokm!-Mi#mBk$9t8Xrf~TsQ25G48&WQZ88% z2R6EAjf+nX5JFc%%D$W(l@g+****%evBa zf~0RXQZxg78$d*QSsK=omlX$xXM{p>^z137F6pnYF*+N83h8ZaIe$}KyF<~2a&(HV zO5%2xaxn!d>1^&WDKzhV{1JhG(pbie5@QYDdG7&QD(XtJzkkf`&HxD%wWidDAdJ`; ztkHVoQ=A;1^47P1#I2VuaqHGKq>5ZrF@{SQcQ`p6Q5Gd>8d794qV68Q@s02Cy}$T3 zdGpQBAceFay#F4x4dvxmzkoWPpaQ|WKm35aD0%HOuXEwTHhX(J+`o5+$M60wfAPQh zvwZ$DFZ089-sAn}_v~k0yUEGfjAw^ao*tYqoh=B%NNjHHLXhz6=@Z)@48->K4xhRG zGAihH(x~`cJJmOU5BX&Kx86Q!K>mPjZ+oNFPUEifl&bJA=`czdY+fWQN{YO|T5Jzc zN(kv_QLBxnE=v(8%jV{$^DvxaJDO7E1w*=URH-(GZhwPoFWu(s_9gH_hepMVwDhMg$6ByiCh3%NbU(9rrteKsjT*|2C#6 z{_q8$qwCW+fL4T3lI_hli%L^!OA-ZSMMdLUvBIHqRZ(HBAa0pu5|hFEO{^u1BiaMC zWM`V=b%mKB2o>pC-w)Aq5;N85l48hCjsQWlxkKy1WfuESDUJ?FcXpj-+4!PfDZ)Ul zOor!}rlpayX-IrgC__biz30x81&l#ULA1F+r7ZP$gvjUQM+d|k+lU|n1Xfz#xVZwm ziH4T2^aHu3&d2p~&Km*C>(XpXsoOaQX@wlJY#=$kriUG$SBIfYtQBK+^pCQXXx&2*_N9P$18CtT`9Y5n&rS%XWl|c{)&-Q5Ub3aB^97U@LN_A_4M;(iNAB6- zfrv)->W95MoxZkCLg)8QX^k=&RkdKyzr=jH;8*_XZ?V-0$nuiz_GNzb!2_nlLr$iW zUf5%De1^^!jPp6krHk$!vzB(JOI|E^>#et0>&EQuZSnp`k6G)rd3f(JPaizwmCwGx zJg*pPH<&YO)`c(XHP(AB4Amk-L@6dp33@K(*cyWkW0I{sbe_2h*sa!*>2RU-{#osr zEsOJf#A_RjPEVk&h}JeBZDWfP5rhP-7TVUN?H(Pq%e^~yAW4y}0h#spvQi)`tf_rd z=?4+kg=;+IxuL?I3A7UT)UhiM$#PDO6bNbkj1h~mdih|Hq6y~rGf}W88G4CT(|{YO z76c~8)Ebejp=Ai#F)643WQd9b41%(TbngvJy75B1ylfKeuq$?03KsL6`ROTE7YsHB zOhyxI5U{bciwr}uqV&&A%lzyJTP$d`TV%5dMo7Z`CWQ$JqJ(QVukq-~AxB3;tO^|% z841EDqSiSF$ER2<*RNgTGq2vHDl&Gr2MB8@%94}QF;XZ-qd8?&lVuCW;~8uH7HJ&w z{MivgDYCrgqkB)eeq{%hbU7>xPx3C4(VV--Decg(p$*$x1E!NXrM6Vskms4**xD8{ z3>od;=c}(>=Gx^8{Py?m^Nnx*ke~kir^GuS9r5+IpAc@p!ow#8les1gEw{sUDnh>h zP9`qxO!<8KntjQ(McZ0i)b{aoUhMP9_V2WP(t!Lv+t2?G|I6T&YnOkz(@Jj$vC8+4 zq6ig6gi%1d+oP^)wALbt6RI*to0>p{!h)at>b3c%@g%LR$bZmgts!Z(Xtz5^A=p1W zX0W--%dgz#qYvJv-EQ%zPruGAtJv7s5}i(mJl&Ee6ZD6$#-Zj1SR z#?DrsU-+uaV3YO*ZnlAnLTBpsmEy|p;Ze|KQRXX2?YfGlI9j6B#(7g(y|zQOgGS;dmepue z+=WqqQYlDZFtGyhtS`W8ZP?pL`Qq&zCexhZbiq&D+Tm!N^W=EOwcQ?fo{st8$(TS% zmuM9!+WihfIhj$T6>o~bW-dw`s%4Qc9R08?)+42elGvk+ICRcfWOt2JD)Qq)w6&xg z+jRCWGC$ZSJ9tKGXBWc6>5*;Iqppf|NhP>&?H27gAP5z`jctree{sjGv zEjHJ>WR*+%S&WDL@Bi%E6jmdw#Ar9@?cu?Mo7XbFe0zuSETc9N0fM*Rf5@#HdsyWo zr#(>A$f@uik4A#ktTTyN%EhE$d9PM^$!uPbBoPKhmX`=ofmDP^LS5-)<7FMx?Pd*W zO@4YpJsE+Js3f7gwZ(KaWpQ%i7>y{QJ=kP?Iz~^1NL_MLTB6;{^g0pKCy%KYZkSm$ zbI7>Fnb3_f%X>ENblms+y>IazGS4~&Qlj$`l)zMlV?wn?)fJI02!-a?zw;Pd7kuRl zukxigKgIWdbO%$l`0P*I;(PBOQrCtgNu4~Xtg%KDx7q~CrGlNz4d3{|1AaE`(C&8m z@ZkYzC|T%;=f_jV^NLbiP!Tn9Ddlx$Vhd8Cf(UIiHjL=)?jYiXvh=aM2#8~%G;!}< z>k9tH=XKsshX5-i+E~JNn;=e{B*_o#lNKmaRN|K7xDZ^s^fI@;7-3B9rJEpxn~ILD zU22mQL`h<$RHDi=H)K#r0zb6R=XrsEC=9Vi(`hGERYhLZV2vME2s@i=%oaJbEVo7* zkwlKkH`e(;sX5H{V66kgCX;74Up6srok10e*olM!g zbb~AxeEY4p>1)O|O&k;Nc<1r(@O!eI6byIG7%?$n}d_^>eZl zjYCsh$Wg=QG#YA9VL%W@Oy-%WtAa2LXr*n6OjDE-!oU(pgYzK!Y3im%;3mxq;|$Vy zUa-h>YOUE_PdFLP`PSRdxW3(Hs}pj4Z=HO$Kw&vLnKGNZgbr6!G;EEZ0m4c~BZMGM zW1=K-FLD1elRjOmiC1>4K}dVO>r8^mV_&|gYH01I$PA-kRh%{;tZodj?i?cU+TjL4 zcbey>>CxH{D#2%OY%rND_`%0Vlx59&JEql&c>H|G_3aKXU+nSGlaY^#6etuyTR~l7 zrz0#);*>uwAuzTHqj3e<(sR(HyjY8hBSg}2jDnwZt&K%>`ozHE=n(L-JDmUkAOJ~3 zK~%IR+1jPGdx6FCCoB%1)84&=P_awwIlpGSY(X@1kM9AOO$RHMVOjL!UYrupD1!A( zr)QpwkVQdud`P^tgA8InS7qh>IloSuTP^g4`=;Q0!MxAPyx#1GZLXF7dh_QdBmrJb zwpy;MbI0vVlNAHvnI_!~4D?+=6aHYeGdwpPT9p^PwAtoA{o`MuTukit#u_ib{E}EK za(?YM5*G6r?ZEQa|JE-uo6U)$VENmuM`xRc2_Z4Mrmky@Q5Zj9ubl+6(jJ?GK6zd+ zTjWgV8H=o-u3gb70i$cIbcm+5zEKoS1J;~_rhiq%o0Hy#3*GKD@V2Nq|%V z^Y1(+P?CPXO{>4n5AL1v@v|W!?YKr#KxQPM2-gzoGDj-OANs;8eD3ut)Oo?nFYS@E zVs2jBWpmKwWH{&UlOw)UTk0&wmTpds^GzCpBqm4_%34Dh(p~RUEHZ3SB9qoKeGw1F z2v!nCmlm}$VK2iL1TKLM7bqb`;CvPagbGkmL=6Ng;_y% zX*6B%-S;1G|H%$dse{f7iW=zK(Vd&FdA)=^B(}cXJ#Knu-1j?eU zt5Kpfbpthp6KU7Rm|7N}q+b0yZl5$DKem1L4_~{wxz_n(o4xd?hwBan(tyHA|>$-UNPTwA1XJQ`HqoC90!x&NLkiiBW38L|KD0ouUc?iRIy zfBqX^vsspln>TNA_wIedFeXk@!YHzf`9kPgqoR;byT!)F2AiAPZ0~H_S$Ql76FxdI z=+PJzSEwjqep>MKq`;bhckZ3hJ}gja$|%o$%Etg*|bAEnrsOq&;Yv!ANb{GU6%C2OKq%|#T2 zu5fP9WrX*PGyv;Ly3)u#jAs#KBWLkN#Ht{*%i;~hG7=WyGX2|ez{%N+aaPlcL!u~P z|9D1O8y1V43tK&sKrkycfeZ)~h-^kN9Ac}=T^}z#Iqz9;v9ONSvVdCV(EDylyWJt(aB?gwj!3q5XY zG_zCgC!%RIUp$XOteTnghjYHUS;hCVjH7L&XS+dRPxce>_`zKcoC^R?Ww9Jz-b#ZERz%_8u+^+DoR4 zwS+-P(oN`fVhjVayyn59$IPpO@pvMtszgai6vxcwb6@;A=0o`VqVbV5DMD_o`Kir* zo$kY|5u@>~eHGVm!&4i??J#1T6g@&H8X_-=+Nt*+|YTG7Px7 z(dLhTVv(<-TuZl{PTjt(aNH|Vgt z+2b_V7~uxig`uLX4N6$P@aap`))mov>n*ZUqXZnCPPl&a632B!e(L-OLO>vuOA`wN zm!fBDTCI>o7-m?qvch1j(UmY&;h1a;NgOhs&1rX9l({0G&rnfJkfu~sO=TsW^#QZ9 z5xT6Ytsvd>6X&gyCz(cpCh$zO5A~2Q-ji0lcts-=7UO^)8V{gLqEdc_iZ+Jax`NUQ zi&3D2qAn&7#26VkaK;EisjzkJ(wJzPPl=0$wW|(9TSV;}Un^G(p!ZW5Z4e?_9gJ^M znsh#4B-To(o91?v04J1!D0FuBxPC}XIl(nUQ>5`L9>6&?IC=N#y!&7vb(_33-J{h4^NZjvZlw7i)RzMtw zblWXjNkpVva#gKeQ=gaG1929meDHwAfl4T9Z8$nP+Ec8(C+pajpiI29P_D9zszfId`fI?tTE3D9^HS;_LsJK z<&~QVEMb)L?Ad)fQH{vX81%aAZgeS*pK$BSF8d!H^NnwQ8*LT0UwaK9EbqSk9_>yC z5JXWxyOpxF(Pe9E9b;;$I-d>4R&6C8XUO63yskvY08ZoH;JQ!wLzcC zMtt<(xj4S}kdGc65k(2tu3h88#s+b_!>l|btL9J&R1%?yD9f66fAk~q(W4VenGz0m ziGm30k)CF%swJeQLRX+jm(i^oNyRydNh9rO&|)K{&w01r)G7P`MnPUybh~{K>|A6% zIkf#wfUV~ulnZN(!J3>}FRMbUgh2|8spnQ_XEqR8T)A{nBuT<(ION{*DP?%Z)<&P_ zR&eL}ly~l*BC%Y*FmO{yg`Y9f42H6eh>REVS0T=Mu4?F#rmh+}(1Q0K4SD_gI-PdJ z{bxhUN^^8JWlQW+c?-SX|Ioa_sGKdJbE~10brGDYkfVA;b-i06x0HfW^ zVYwRO2vAOESk5=TBK2 zJ}2GYg&;~iKMQFSGb0x)FH5JCA>`gSr4|5@vqBGdz^z4kg9~^Ra@Ccy` zHU@p-C}J7Ie2!6TO!Y!I3FZF55$FN!PD+#RBZOqOSfI<2cBf6!iU>LZaTGIS0oE1U zLMbbynQN9QDNj*D0}lpe93l#(nHgn3D@zd$R+Sv6-d z9I_}1h*D$_F*-h>s-b7P49~{A|Lz^)#WSw1CzSaUj*gG%Y+Pitn3GkK@Zt_}6k=@V zb0}86h^8>N#<(KZpDW`N+nl@yUn~lG-I#e^@h`srgh^=$q}zX^HLW;cV=ciu;*eEN zc6Q>@tc)aCmqdYJa&$;pR1{j$+R#{ClZ{3M3TmrpZw3gFF+Y4tH;ovNbIP<&f6(XT z$uk1s?hXU*G1A{%O<0(=pf~ZYVR>&|SOhRg1Q&?zUxa8P^x@Pa6?ir$_Z@!dr4T!PJ;ggLyTnOpzZ_kzn%KI^`m!k@aAR-J?7pP$^ zqLH6UQI|E1S8g#LVv7aq8|zGmBPt~6U=wW(x+?vlNQ&B!7d2o0%nfc_+Qig` z5AW~u;Mp-!39`IES0zeCARlWN6c;aF;P~*6`*$Bv*P4$$_=xK_t`ew# z58nTX>11ISl*HMw`1gP60;*H<)<+{gduxaP@{fI66~ z7R6xe|7Gt@V{E(9^So!RwZ}78ojNtwok`wHve}%v$sW{`BcUY=j^arE5dlV^!~y~b z38ElD93*j)AAym;2_hH{0t>c*C~)LR30i5jdQi7|WRu-wb7&5icOGj#RcAhDPiy7J zTKiOy5)%IxH*oL8t>K(~)?UN+eee6dZ-*pFNoG@vj+p|G-r0?f=YDf(`9J@{Gavi* zkKeiRl|T7k{=qRHUH{70M+wM>E-97ql`w)bi2zPm=JRGa0hl7E&}D+Ap}Rmgg5WakiL)b3*Okd&&F9rrP>g?`^V%) zBak3xcwWy2${401WaclSr1R`>ULCHiL;(oj!xuKqD(`(>&7C6yF355Lo-u}82owS- z3{q<{G!uix37*?T=DL2Kz1%q!TK6Ewn_vsvY) zEVI(JwkiCi5^A(|UIYSN$7HS>WE@h%763>cR>-OSt*&eX610 z;^XJYWk3`NYLQQ`KVp0LkXo(A`7Nc&-gsx?@xhCF*|ks=@R z*(a7UMzFEE$nSsWI+NTG)EX!une1D#DAMTAZssy5z$K z@8y`BpcV2I8U@(INGVHwbMvq;;4ievg`ntl5otI}}5T_CY!)!Pu8I1|+HR5_@e(0C?cKSZc4C&N#ng_P?pE-4vv@Wd;v*Cmy%Zch0 z0;gm)|2YFPisk`wiLj+v&iS(&{Nj}>nDH?ew$^y`kxTT4BYyb(a~vLaX~v3g{OMO2 zk4F}TEol~ZL>=`=+X|`>9QDUcrZd)-7g=gI@O_`GC!gvoSDd!fm6Iw8wb+KUSaG}UUA;b3TKnMykJw?s#91qwl$Cj8pp{0*Le z;RRlQ<4r#K{BvBm@CXa_P;?IuO@ETG&}xc*_y<4Y$M>V;9hu*$_xU!XS_aqZ@P!l)qA@C%=RitgbtH}36FYbfGM zjmJL!ICmfJasS~ijk?AQ0v`Fqr7tgIytH%8J z^;^7k^<94Tm!Id0zx*_>zH^V=hx?fE#J)BH?PSi&9=0scXs)f(+1g+{p76w(RhCzl zMYR$l(fFPquGBf~-JmEmz3#xuzDA)vFAGC`Z3|IvkPZhF7zW3EJS9le8QI=8+BI!U ztf+?p+l1{BM*|qCNP!|t@q++Wts{d7`w;grTaA0ez_qA;L^?bFdtej0glCd`E|OlfF)au(R!r_8EOqpTJcbw6ThnPmb} zzGhIT@TMH>?~`W*BB-LgkV3<7Z;z-Ds9N)+NNQ|SI?D{TYK^2Y6uDv6>)C==7&4n? z_@0k0j7yF*?}v{3id=6OZxte*0JWKfd+~w{}NVDh)2b_!yp&Tw3wjSg+7X zTGZp%X}uWi4x%h$i2@X_`EdwrCEeCW#a zDf$Eg0B7)46sIeC7D3Rb9Lu%V){x5B@1KNNHo&vZz*Yrg&bz047xBUWYpkZYu#JX7 zKyG|SY6(AHLiiy`P$QYviDZqe(wHlQXoQ0|q&rlV?N2av^D&NcAdGe}U5ynSbvH%5JP|Dh))gJZF_EHPOkvMifdw4?yv z56~jP=qYJtxOsOhrjvxX4}XFVtDJrEdAeNzYHIb*rLq+qb7Hbo-ZO5*Z6I1wMZ_HW zC<9c0BG-)jBZQPxn^ipDa}L+claw;)^1{%LQ|T)JbDj5jaSK~XRh}Yl)-3uEc=Mkv z)66+($DF7_`IQ(I1kN?u@Z|Y6S(fwO!(%3sgyU9ByB-k70gs(sW|A3FGvV2-m!*DAOV2_O&>v6T+_yossMLs;SD5VWQ2=pgh059{Bq?$;i6<`0WmbA5*xXJI`{m zS%wM&0{fyLTw!h=lvUDlwHmAhE27LX&HNrq6vUKn+PJTMXibzzN;%((ydY0=tJm+I z|A{)=NhN!}V+b%>vrvz@xY;2{e4e>-&U9L#*wI~9Dj6b9Q9@Xb%6zV#%rS%wcnppr zC9MPXEGxLTeZY7!Wo>ndC0{!nc1b=lrMvNpcb%8pB=gztOIl7v~Bg0M}q zN?^9uS4Dp`BG&~{sSi}D=i_Q@LWvL@Zr|qin>qUU5HnbXfd`_7pACiX_vlZn6w@K# zAxwd<0-E)ht7*W)?SlJvUO}3iNmdXK_VF4Wf_zAIvF-Tw<+?iAQ|I!+=49;|A?6|z zC(qtiEtE5rJ84jN$e}cZQuF$&Z^CGwGn=d2yxwEA{w!DDzRtnk4o^M)2=CwB;W(E3 z{Ec@hW<#RR0{6x_PoHUV{ms|u9~~e%3+#0VJhAc1T)T6R-g6h(-djZEIY$RaoLgzK+^%!;_!tocRub1!_ss0M8gj(YTtheS;)n_JTVlmL_G%w{vBACe3Pwr?$t2|BBc`+dlARG}#bJ&T}9 zX{ClmSr7wV7(8Ec<iW3@^ zJIiI6*px_T*}q~H%(O5ckO?pM!7>>tVUn_Nkh=s^mdFkgf(p96%s3e#0)ebG!5A8{ zV11>{BsXM1WRn1$v%S}2p%JstsE}kK<|t1gCFDiH!Qmm*O2l!0M3x)t;2vO=7z;y|W=2Y1NM#Kj zmFJTewmrkrCJlwog$^3La_fMVrEC1!m!9Fl-dV&4x@SGs37tWg)&&yL{o_Utd{x@z?dI@0x%6-#b1U4X%In zXFvYl_x|xe9`VujmtG$wARoGX&yxn}feq5 zz7U*FPCjszu&&V*c}8k9Q6)$E5yA^mVTcSPgbeY57_CA!HdinRZrnM*_Y|IzPA*Vj zgoi<%=!*+0-RSP}XZJ|}6B4k6~x((Z?H9uo^8i0ZNZ+{zs~?&r(HQM>mL z0+jNID(VC=(kH>DI5m$>{5gd4?yz5vJjvPRI`7;(;I-=q)GIz0)^jA9UwQF77q^zU zcR1w1!H~Q6ce&UOd314+AXqcw!Lhji{w?AP$WZa+&wrY!mc&uS+L^Qb*;_kQ7F&ph zRgJ-b=PRV|Gdn(Fe6Y_!Rq*)MWBl4*f00_CxW9W$=j=MZC(%iUb~GUs*Qu;XCI@?< zcZfU7RM%FS?Cdhx-J!CwO76!PEo`vt5{VB__tR=v9OvQU?*l6h;!&E2z+)H=u)~nw9fG2*PTF7X|pfH=pw*W#L3hSA5_;OK*#^ zseL{T-1p08C>)aEDMh7TA&+wWD3~`&i}`E2{~4^jwXv0r&{rJp9rE&zwyB8;-Gi`h;DC)1V*DFo)RYT1C-~9<6a+a3PL|*G?|KImKq@?K@f^8pJGhGNy2|> z)fv0izxnO&@rVCcpJr=;x9<z*xz)UyDjG#C2sXVvIvrn95 zrxl?4>*R&OLy{|nA6KX^v;e_mnxcfn2t9Y2KGi}17&k2TA!$dAlg@ua2#1WiUKvVc zr2K7TgT*3Cd31A$rypCVchsfd>oXqqIM)eza#iQ&-OMifn9M2+Ni_Xg!L99M;wa+v@4SW1 zGgdkcyfEago4cf0j_`bHtrk-Gb7^WVCBCO9JZ%AB&qqZeiz^*6B{>{vmRCI*?KUQ; zkZOVOJaU~{g{s_1wF@7qJo4d)bed7!SjVq7@T+z5$(Zc;2%()>AJ*eZ7|>;}T9)(3 zV{1JA_*rh>JD{~t=f$Tl@XbGegG(C=eCl$CAHAKj(u!Gb#zZ3L2M1j`%_fVDkXFTG z+U;_7rOJ4Jm#wqweD3*6G$W5{9CGgL3Oh$b`lIAj(ZM3?CYzEBjxcFv9p+mLNIyav zeS&aHffQxekn0nYV5!&!V=SU${Wy#@IaH3)<<@Ia6jUmT&O(j;C}BEFS!~xCj%H+O z&g$|yN4*J+T9szA%1(F4$1g5%VbNna7!brUS(>o7e@sxzSZaFI!U6TAs)^!QcwUH# z&+@JBzs~kqQ~W@8qYI*bPc(gNzsD;NVsS{g4~&!kd%7-@TGgl`LK zhrNLs@OY++7W1#2U~NP*1}B+7%M{*c4tAyNpGAD{&Yqw%E2s6VE6 zJVZ&2ANV9w#WYDpBnkpyNQ^edXm@@qgwUtNbj)0|LkNN2O!1YlA@}X9!D66}tD)I9VRNj>f!cSL$ z=ZJtg(GoA?C#}m$v82$NpWZy8n2mYz(h673FLUF@J#OE*iAP4&m*^}*n}Q(lZL?=; zSYKIU^UPV|MxC&;iSz>A+fC8i`$$irf&gR0yqQ+JAi`IWj>e=(O4O_o#<2^2><(vR zjuN$Sfupg(ShZER38bT2S&EsHfpk?HAzdq@3tZ+>o_`@JvyZx@pPU4koVae6L9iRQ z@_mrZgWt5!Y9@%o!TXKNuwDM>0kW<|mHu!jmmY73T96)v_Z3d8L?d(Q&#ofRhgd&urS6__r3%6?TqB6e^~=_6X74Z5CICEN>`|4i4vI z`oWx7&M~F37pBu*Ftthu7@>;{io&@&3xx8>3r(dGa%OXdG|T7@MijYW|DaoP*G>@N zqCjgyYP9u(E^>>sAWn^)8w#oX#r`P^6t-m%53```Xfc>++_+R z_iwzzTSb@QSP{l+2r208+$K)x3XIN4 z(*n=;NF-c6$f<-0nU1J88oYXcNPE^}G#Vo?BvBK!S_NZJhIwEtJc%u587^Nr!}?N< z$1be$=Jh=`wmddB+BE7BgHg&WS9ge4R`JSyNNsy4XS;jUnibLvhNBsImRnjY;8m-5 zm5N0i$~CJw>FWTb)~uXa=GyL0#=$46d4%D zPDpcR(<$R=iZnT~G#qyaEVXI`o?>tRm@_Lac6NGhP1z!(L@*mp2$e)N8cfF%OqQbp zL16?+`j%3R0O{F+pLW%KgFTa_aqIFF%~^rxKEFjd3_90bI=9Y+ttEQH8GA z1X-5TZdJK?cb{AvK6Yu1g`Jq;WWqvkP$EYNNJe8~J>-jD z_zW*Rb&-ZQHa8y}h;M%9C3E|ri&x!18!htUq%XYmqLN5FrA($e;=5PJeDB>KBP2o- zkmpm3>0@PqrO-vr@@m1kb4~h(J5=SwJoD%(|Jvt2L#--^R6ra`d_B^}45Ze0QUz3M zO&ZJXEA9Hqf3e)Ge);nH<`0j4;}>7Qai{y*Kl$%|=Of<`cYTzAeCT@f`u6P?o<8^8 z;duI~cB8UbTA|P5Bg33(WwUK@>igxwbcgjEa&<1Xlu1h|)Om6V_u_d`5XCjlo_`EK zh)8BruHD^cJWEl^!%8&yXgrh<rB99B}3mgm*(p=MS#@yK%u(DLA7JJ;@?vY4| zaHdi7kE7%~_%WxbazfxdI1I{TZe(S1fwG2NqEUA6UO z-pnKGc~Vr)r_#y7Zq0%>Zyxf=M?1v6U@%U&vpZz(Xv%9hy8Qg%h`h*|4M&9S2Gv@P z!9X$|9*cA~wh64sD3TG=VOJb=hwSg|FdFtz<-KTY!iKTIq|6MtPz3EIj1c_%-P;V4 zoJwsV3)A73PFXe zuyjW$KiD8XhoH)d3v-Gb^XESQmJ1+G^+1)carzmSf1OHPpzH;~tw~4gQHEkRWp;Rg zaQ-@zbc(7rNpt(zQqOR{DfzA6_!3(iD<~oGe4jke__{ZuKX`=2g%kB8g-+KLLeYb zbB>N}<2lAKo6U&Ah(@!;EZMh>?M`5!+z(ICtAb~rxWF&{;%E5I4-}6-@i@;t`*9W; z6^4@;v9Gv!?|`p-_brmJg7IQR5Oa5bpZD+H#E$}sG)EN$eyxgV!eo*n^ORWSNUbrR ztv+j`Q5ZZa=6l(^7*y_sE`ZXdaiI%#i^5h-rIO^@604s0Q(@_` zU*O)I8T&gEcE0-qzW?os*m&}@T;maTwnrSi`~zA+LFb7tVuF;esSqx8<~h+1y&;I1Y&7fFe!l4`-ZR zUEuxuM`XDnGlF~DJv?KnrwfgkGiO$rrUiRPLkx<+bj)HiCQCCk_W4^JL!gB1%QOg- z0J}g$zcfxIQ6iN`T=7Y!DTv@y!3vC%G6#+C`Q%ArD}bJ2p8L8uz=+b}-GC^lMn3I& z1y4$D-P>c}D>l|U0Nl8;s4zSg%h^XZn85qD_Q70&x~e8cdK*!2b2Hw@Bi-q{@?#M4*>Y>-}e9EV}H&2o!|Le zi4fwioQl>*3CM@8m;dm8nm+&W^MB+^c~)#K{bntW7Cx-5R%+juR2?bGlC}+QP6A9b zZ^XpdtX?TGM^0?ee~RwpvIjp1i7OQXKfoaAPYPz4HM|p2Av_<1vJG;^picaLZ6Ix| zb~{d?!``zKdnu)X-KH_8iMby#;Ho$7bC#9=Qx$6rPHoD}f8QSTwjv_k=DdGA;rXpP zAKM5?9w@%>>%WB03_(tjCnU3!-o$W!f5ewwe2O1m-Q%6N_Yq!zLEtONGmoyYPzy1- zV121drxDVwDw0{sCm&y-;wyeK$?+?ZbE4Ih&4Oj1X)D7{A&Zl$c9{%V=USIslsp;t zJm%YNNhvXYqN9vMLH#Ty<_1T}1Qd+a+LR)?;mW~F-27cPGyijGK5i%UZ zMyJ8XQiY9njovtAb+O93@83ga3DriOy?%zCW#(Id{(W(9*yYak_mKt)>G8^Y+jN$e zc;t~s+3hFfLg2Yzwzjlrk3Xl9h15ta5;7Yd@nkdQKm2z-g%*n6`-4B@D?i&IsxH`h ztPO=jG%^E0TqRyvXR`AU_V$RDSE#Pq9+C0>K9%JagkM2hMFn(GkWQwgvlOJX3CMhI zIn+X)AWYJ68c$HCQprdVwiZcU65?kWvx9xYr4C*Yxup1m2}O}xU7r$~FV`}s@{;m8 zeQ=eD(42c!91v8w#f&q;(NtO%a5-!j4I3A8{AmUKnJj;oq2*1dYN|L0RP4Z8TmctR< z|EweO|NWJ(^7XHOjZAx7zuV=Fx399?ZgRN4ha{(;_>3kAMOC1S0wJKXyo?w4*3b`w z2t)jO6A?#5(#Ka-)TBo-Osj zL5?CX$kNm%VTDb^(5{MXU^1TZ?(G96)0ELHXK|qlTC-I3x%u#j`+EUntxy7IYHAVh zysXX}0aEeu^)9j7H-u6oY0kaF3Bnl0{V{R9iVQrPd=!S#+ca!1kp&@z5%`U|T?_8H zNNGh}N;Anqn|b55aKWcRaQ#7#G|8xkf?;nAt2LGut28Peo9!CM2gig;u)EtOOEaE) zY?DeYCdqRQhUIph>+ijf^n5lpH|Z?YIT|Gl4ik0`M{FMqk)DSTcHFc!6h`CM7f7^V zI2++r8hEuPLVC8L+VgM>ELX>K=ZUmNgh(s2f|IMZdxhI?gtP@iSFjY0W}FumtvS2e zWU1Zc-Rt)`v)N&xUZolZtaVzXxxw@7GpbiY+RcjD4wTSFv(ReMY%LN;A+yOC<#|R( zL6&9=CJD;(@UnvO!4CO&NNZ_{$!J2F6*M{>L>Q9K`#_l&GNNjo@nlM#W%J%MDV)@B z>5F5;JY+KSr~oKz;W0NkS(dv!+!k`F_CAAH4JyM9N`63zNbTYvEjFPgvicmJ0B2mk0_h#%hEC-<6`>V}z* zt#ClGaY8ss`PRr(+kUFK`j9JHq|+(WiBA~%OebR|vka}Zsm77;{74`m2V+bw#>oJm znP}EL!l+QVpOzxdpf>e4^@y|2W+uhCpNo*o_l*Z<@1eFr$= zuh{ib0`iw!|LDK`4{mq=lmGU2wSFRg;#~XRsziRA7f$VBPQS4cr`>o?s2RpUp$jX6 zDuruaFOOnD?v7^b)++Hm&vB0Jrj<$vd`0Mc1c8s|Sw6f_6^t~fAhM=q%F#T;2`W*l z2^A>UXnE3@nG0bdQX}!CrJ59{Hu$o4f|4d>d7`sxMe>)yT3Pq>RY4pc(rtHX^?9@?DZ7=j=+I z$dg=Jsqx1z-Q!Dv*?khOhy?^CbZ0P0co_bo3tS=qmGQ)Dh)e zLqM5$m2k2#&Opw&i34->6Tnr!1V{%}3#@ao`+nd{Dpgzg4}FE_Ne;SW(mZ3e6|&Nd zs0ETF%P3|u9@%Q+c@2(_hJ50&WnPz>jWcV!^WXvdw|fNf0!L}gwy>_rcr_jz`8?g( z;9Tnh?{`zeICAq6g1~nb;9{<-qn-Cg*r;)Md_+^Fgw-mO(a;{QQV>)kR2102*BwAb zp^~=UB>){ z1Oj8wSnmm=HH8rP3k&2Dirx_-OPKBN5-u%4RI_J^d){f1F&mCiflpkIZ3PeJiOq*{ zN%wXqYoMgxIZlqtMGTkL>Z~tSxq83HXq>UWQs;P>u+gs49ZnJ2@WSN|N4+7*bc~Er z{FcXLJVi!6Dr!-0)EFn4AHMuP$v9^xnexAV^~bcs8HGk@FJv${X7}D*hTR<$Iqk&- zf|6<`PVU-PCr?TKVlYMvj!bbV0w@b4h$DNTFQZ@08F47%3Pea4@wL(zPi}_fl>h57^lo6Umf% zqeal_FmmKOwC&?i%@!5ukxwVcD28ekBLse=P!fs>C()m=s8TtfEcz+t2(vCxk2&IH zAFqRzF@4fUI zd(Lk12L(@ms>v$Mug`hi5n5CLlJ>>k>64Oj`usyVue@7P**u+|uEsV;dADJg9 zGFQ?Pf;7=gM-$8}A(hY1W_1}O;a)@F zpNHl|)z1LZDO*Y3cT2Re=zy35Z%#7Zo)OY`^u{SK|NIV-=W%|sO{Z03u~lbxzt4rO zWp3O*WO=bpXQ9el*LLv2iWp84Jg+XAiydauiP=3Ih+NeOCI!<>qJk=oX3XBfp*T3! zRBH?DUA;v%9@1)e7`x=7v$;V~jhW0cCl~Ar8`@BB#&nk3JbZY-px>VhT+Gka!tTqh zdX028V>}sK)QAF;j8WvQb{0`GCYw!=LL#JsqM+4^QBpCTN@lZ!N+mS9$b~KpD=Qrn zgdU?|C=P;Se)WY<^Tih*(GTxmEh-D={U=|1QXmvMo$z3Pm|r@-!r%GLFXR95&&@zA zVK6A^2`>mO?W@Q@7bXrp5&4R0y-6jGm`x{UFdT^4EHP3lG7V{(iZD>7)oh6%2#wY$ zkDgs4@W2-ZN@gg}w-We%1u0vM23^zb?TF4&olBRW5xxF^2M=zVM!hH6tLIi8JG1;- z>z&q@r4d3XuX<~z`?c@C@zziHC;|ECDzAU>Km1qMpZK5u*Oyis-mmFK7+ZRRaaInN zJ8dD!0?+epWxFVxf{NvQDk)vS>P|9O;V=e@JY{$L0lWKMW=W2eioytz+#)KKY7Ng1 z=?#WF>}5JL2Nj6636(Fl9Ac%q!4f%TdNTn@cCgei9^| z1en56d$bXhDyH`EaFrY3sA|rASYS>$VV8fzyvk$1%>m|(hozDj4t6h!g0*_Ym!I2W zGPBOE<0Rv|2R%$tATg{pBJQObz21lmTOD5h`F(^jeEQ>C_)77U_xHGQ?Exa6QC+(r zn#~&VXv}iENj@9lM-hb#*&C<)(M#9)%(IVB6fnzj5T2_DTlr*);^Y~V;UPHe^|*8Y zp=mERMLIel@T*{~mK^bC~m}JS(_nV7k2#VuFRGN}>4+z^JqB;fk zcZ zLdjuIF&@nr_xil~+PlQ*0n1TBKH4YGa&)}HP_-sLUmKpdLr!XcUh=cs8%9; z-vuOUfN{>H!lZ}6$levy}6d6`c>{V|?-?m4QJnEl>}$!N%OtH$sC(NE0R zu8#yk46Yh(G^lD7uU>P{iVy5pC5mNx2jpCO)uL!8p{?~3a42V~f~B#@ildh(QHoNS zd4Z?Q?>uSgX<8RN*xBdCogF^^$Wv58pZ)F;x9>jW*1cWMKYgAk2=V-o-Mub%Zr|g= z<)_HAf7 znd|?v18RhrkBJp}ck;gir02N#N{~$xbYTcQNs(nXd2vRMCNF6^PL#tTHl=XKJV_Mg z+SVX(NQ5}GuiE*b0-sP>lhST~!e}s|HaldYkq}Q3+C`Tz%X#P4fP8wHo3cQU`{vwY zEDon*4zezJo?`mTT)%S@6V_R|@*Hs-xgG#pNE4ny89`CbLqK?*?OW3zgrfAEv3rqC z4DAF|cK%Y<7Pa%8k@JL02!q0%NlrRj1U~onhSu;C!-Jz4wRoRdk};g5+&h>sO>*w- z4+%ZNILUb8!V33$Gx{%GWpk-&-oCrfE-UmW3xuJM3@Y3`E;yPcTz_zAIv1{p?)^T~ zUYF(d4JMNrNmkHUS*1`u1_i>#HnulPB9&q|n&SICbdgiIGebC^G-E8P*jlWyzT6@m zbUDtCm?kONbi$%PGTC5PeC*2eeC{)!GWBYN?|XQqJhCxDDT$KGXam(sOi>g@8-(v! z`vPN(F~u*4&6Ng*v1qJ5?YF~*P+o)(ilQheiqtDq#2A)KIjvqH_bK4Y(^OP#F0%P<$T_{Qkf|nf}&i_!mv?DOE^wkcBMk0yULO$k0jESt&6bS#ybqLd=S0WwnQAoS_Aj*btXIO^aXruxqBW~Z_=3o9l-{IEI6#N(!R`4o| zpp=t|^wC1%Ra@jGB}G%vV%cbBbmkC>~sABb=M^c`+p zyN<6s);3mo^ztP>_3X!Z>CKzGb9;x)%}wrK?V^NWnr6Ixv&)t9ZL&OP?{L5mr!(&F zj#%x~**Tu_{@or1F{kOwE7p!iX8$-sh>Ir5z8G+nQ@3%r4{LwJoq8oV)M!JVr1s!c zHsLE#p_85wd)OrX0oiy=)NbQPp+nd0?;yYvhT$aT)vG&<#xst(BW7vJDAD*~h!ODG z^U{Pn+(ZjdmQZC5#xT92RGj%m*+tG zcEp52coC=&iDEWO821Kvflq6xMP+$~$=)tzcb9l&m3U>9@!lTOZkNiEN8yJcENWGv zYlf0Bc&ZY5dNCS9HcQFV1V4`OeE%ewERm4r0thIMx~N=}9v%=b0a4xhh=d-ZSwnf! zRVm$jxnOo4(0*tiC#p| z^#+^XjHl16a_8DHajk>j*x>!`F=;Cx*M_KGBS5m;Y4GHQ6~x3h3yqq%u(iTq&}Zjb zKtHI^s0Bz0w6UsBVvd3^f3|i@kZ7Yh>W%65$AqCrC5mV^D%7emp7QWKL9G(eZdIAg zavtvN)9Vjt)LO(*fDn>dl2ENg3`Hu27aRrLY?$~luhBI zqiqiF{0uR?j~=xVqg4V~XIZ7}XNPnhb|$R=03ZNKL_t({6tlqr0U>#jSz705p$~14 zWs|F!GbC)1@6c)El0#V{&E?7#*tP5SYRd0PE77ZscIc-$c|S@nyWIyu-=ns?%0jUV9F|+ZE+F}ijb(+`nUH~UY@2E76(a2C zvD4WhR>}i3d0`QT&wXr-;IPMnC#VOCQ8i(RDzsS{QZ9!^vAar(=1ctETvj+;0J-_ zN&|2*`O28rZj2?ofBO2s7B;UO)LU(qHqJ9^_^7x^P-#%9w?KIqq41=#)t)HC4?+xr zXM3ZTlm-oh~*(%N|csT#IkJkETxXHiI(f`#)K8V@y<3T&qSrZ z$-)!MoLhYwPe8R^rSE%u|Hc$03OZ-b@n9%1LLohc)Pe{5BX*A_WJyLkncxKhDvY>) zoLDr$SO|NbZP)=m8FlHJ80QI;YZiAun@y)^Z3v?f;hjj9y0#tMheR9A_^5~U74c%r z(%DWwT{j+DYw{!^8;%HCEvIZ|g9EYzUF1N)peT5C{}3f5>3GWYxQ7=AlrMPom3@R4 zB7=y9SfZvwGA%Gsjjz3QjlG>C`o}~3#v-~Fb2v;`3zBA z8DkaGjbd(JJ!Ej$BWyMaD$EBb1E5} zkE45rWl~_=d`l)%(*6*!B=G}F;VbEMw)x)RH(F>T$d3>4^PIGMfWHVTs)6t0d8J>4 zeNzd}f!s|Ub5hYfkz95a=2J9`54>6Ydt%VZG-WObAl51O(IW;ZacuMw;Cp>pyjaGYs zSyHf?Y3L4SJn^y1T&p(ml;o+EGaL?P z_?0SK=gu%1j5z<)8po+eT=hBg$Yo|p&Xx6Z406TsC_yTV?ntFTSP5};iV9dtE*DzQ zkznl%A^|3u=A8#4`#Q>cI_&g^T-%#q3M+P7xCZ<=jp!5tZd{?O7{W?4e-7Fh@~j{mPYB`&KMdw)QiNA!&GhTUb zmz}*s;^i9WFIItM?$IS&{|rK)oQ$mX&(YWC0%V*s*KH=lr4@7(8A|h$=&U?2g^O9C? ziF`U`rY)`2vxtz}%<1A`w{-LPTe-^Pj9+_7u(7rX*0T9%lh{sqc=Kb1gE1$EN3PXs zh$xPj402rD;!pnU&v@y@mxVQ2YU6};1|cDG)qF;kJGnWSC=8Xcq9jlytAfMLso~Xo z1fo{SEQ&I8Lc`}(#m6b?c||MrGe#jd@Kgod>86AW%mxvFo$#}&%j!?30zJYEXbnt; zb2X;E*NT*OyFquckUZM$=EbzZZ{hJ-0rDG;jit62Z%*RFgG14d9dXut!tcW`lP3#{ zYWY+{=kCS;^O5Sm)A8n}6}Q@6(Db|Iyd4 z^5YM7_}A||V6D^PE6=R*{dXU;KlGb><$NB>f1I&Tb{c}-c@4l?hZP{BnEQKUv~|o1 z$zI>kJ08=p1y)Pq#RbMf@nHLi!<|E(dgdakEO~S=^}$dGK!bqNItp!>PD@f1(}-ly z`1hMbrPKn{fr^m$3n%>SMSbzBl-3su`EZObO4P~olL@yT_bCjt&&DiXy-b=W z;w;t;`|HT@q1%@tq{=96$Kk+kikt5iJIYa)gwE$#~3?xy;EVV|PC% zP7y6d(fP%opJ* ziNpGuYsooZ{b7Y5>GmjuqdYo9m4@KhHm)JT!M8r#&*$6ky z5v>*%SJucfpS-5s1t!OjI6j&YwIPzitzCLrthLwZJ>JDxOPa(?CqoF5mepqZgu0rm zmuH<&FE97V(#-829*N;_%5XF#5|AFA&}z5owA*NHoRCrs#}j6G0XS6T?=a3W9go=C zu_DP@6uM+GnfldO-8<*J5>Dl*Ap~Vv^3=00arVL$9&c^3e(?(Hm!2Y7+@R2Kb|a&6 zZpuf0{W`fGf>h*3ha^!yO`1&pH&8e);@m=li(uzqz}q)>xqfMl)ox0&k#aPg z@%O*D%L`XlIltN=jU?au=|_BjbeBK+{g>#^EZe)s3`ZlTM$lbbqeYG$4pHq6?`=+b z=~55p93S1>rqgS&*+1l@ki@a{#kIC51*Wu!NTTzCEQ{y+jh8{AnC3XGX|}zG6h;tb zF;1$$*Y~fV=t?XF6s}f|^FAQHFsp=1q{Aoa)_97mj64VxM_66$4gPxC(6#WF+@iJi zlp_d9pqpoMp&L+9>Z)0=s#sJqC_ZX~i^J?1mW^J9Ei`HN9Lp!oi(~^p;atT<6T{bym)-lcOlLuI01qxiA?aFrgqZKNcy>SkiHL%Xk9pddAVui{x#{vF(Xyavfzwq2up1rcd>SBl2 z-%NP);1T0-pEOOmaOu2QU0-oWheu*~a)gjE%|?qzDRNy3oDDOnRs8=Ip`TyRn*1wl zCEDTxnuI6j-RAF~7a8*yPW`iA_d0``_TXC~xSBd2uEweQh^hlt9aX33)aO0<9jec& zC|tgnvBqMZ6Gg&r+4Izl`Exl09|hDsgklrHcthIZ7Q|PQzzj*_~1<6Vz8iMDnC3#ybDv#>_J+-_LK;FcYi-r_@JBr$ z@8+%Z%F`ifHBpH{MzZdd)aZqOv&V6jBx^SSQE$)?3YE&RG6bDCONc{&Gscpn5o;~S z?>&E!&p&?=qf6IoWn!Vz(5y*1V==O_Vj6jYiZBp*qQepZ4863A7=WIUv7%}{X+N#f151e8Lsai+t6 z_UB*b(wQZ`^OJYD`RxzgKr7)TPi%P${OAAf7hO!j znYBfpy7m;>I=*)%W^4CztSv3_KmRZPf}_Jd(j=`n)Eear*FjKG5-jI7R^5d&E6nne zqoYFvj>W|V+N}o8S^9$!N5_5tjiv8?b$eZ;fWyN>(QGtb9LJ(43Wk%35Yt=;8P)5r zE+ng%5N6Aqa};I4mtTFEf9p^Ggzx?E$9(D4FYxLYzCap#>D*KawhspU?T;#V{6Ngg_;VVw@v{!{Ugg z#Dzf-p9uJMY)Z{+>U|?>F}!fot#z~-F;~wo@XPl zvLs@m*J5d*3C6I#+T!`=F7oN_#3#~1^W0PG>|ssHKmGaF0J_Q==^i(LZ{McM?11? zEVQ|QZ<`dFh2o<*_cszi=x$k4#pf{N8445^x*w^4_2o9gY7P#L=r&^_VVRZ%X&TXK zXG}&zF&>TmKIjWj=bRO|AO&uv-*7_w2m{U;q>O!aTXCY@ zX{U4#O-{y^(nzBA8gVy9wU$wF1J!7G9;%9P+9486)M%lCT9$Y2_Q_UJ@q_|z)L~iZ zH0ZWc-uvJorOL>%j8c2$pmWPTc1|Wd-XCyjqswqS<<8bIjo9;OU;A(qV=W4h&f-kE$4 z!^nj19Yrd*$W}=C+~nwVq4cZqp>C_zr&*mVo(>=-5?RZpx>KzyKYZ!`QWqZ8mp+x1 z)+u!8Bv-UGV+~m(IkOP)xob;&<@pOJDYvHFhL53XUQ3kj`}R98DIUzOAPlOaOc(s zoL}nlwJ-f+?r$IS;LdF#u}ZVu3X?o-7RIs?+(}BS)B899ut(aoO48t z7R{`KY_xo9UI?O6bCeIbdHbG=$|3K({kE7+5h96d!%CdrxRr=7)ulewP8U?2i6_;t zB%+p{K3%j_H};9`$%1OMaKiz$3Yw50%&B5jP_^x=cUF$+u6mX^g_yzIQnV^ktR)UJ zLDlA^!iJ-Sf=F>PbNuYafgj)%Af-cCix3hg720@unVIE2Nprs2d318ZMq6>P{XpoW zyYBFKBp%$^;@=2EZA*|lYn#1W(M6r)R4R~EQ< z{tQY=oHeX0Ewa6LCI?kL;Rk+iJvwIn+zLtx9`6kpObicq2NeAy zMpMo1$Z|NCF)a*E!MA>L1DQ53Lh$SCrH1`dqYmBy%-%hryxq2>~?#$xe%Sgi(M ztM@sS^4$?{&KY9Avwm1VQU1MB5XXuVe~p~+h_elVl!{bcG&uYmqD=fe385ISggbCz zu0ZA-vd9@9>|9q|SNn`bEBSb%Fo=M}N)RKl=yPmRp#z zAfFX%e(-a$Ea7-K!Fb(sbWxBku5;~+f5iUrgooQFn7$-l0*MR*$>FS}@M>d9hJ8+8 zN!D*fs~TtqZ4+vcTp-r#Rsim788RQo~oVO1ef0a8@~DeL{ey1%E35LekD2*Rvb^?U}f=@d}*YmJTYZ`GWs z7bn2a0-qMX2-$3?iBO~N>(^qk+Y8WBL+YJ2soDE6qbb!4$3RstKPv=@8CY3!3ZBY5iULQuwXJax9m z*6s;7c=sQ&sS}9dLfrfSLh0mx1)BHNjQJ2thaV|LgT9Qa|xVIyYAAd-*5pnnCO}_NvRfI}# z0(2;1Z-4kU*Djo)$a8iNju9%QEDgnMg0+$VrUJ+(l(Q*Eg<;Y4-5)%EfnS!};%`5A zi*J785BU8rKI7aQAB#u3Ckz{{@LWPL@<2*Ql0-~}q$oh-Il|;98eTyK0g5OjQMTRU1{G`)f}3r~XYaSIw%LlrZf%WeciQ~U%U_~DnlhRe0SNG5 zh71U+F&2bFM%DbCr)25E`(4CIMAFI-HYM&f$V;D9TIc3|NFnL-3XcA|7;Sy0D5z~o zWvMPx)$vflSzPNt)AAg)8nt!-)QF`ZcK);S5GP%jRq<#w_`BeF`H>WqlL?V7SX}MV zKN(S;9MNf}5JyZ84#>(WX%;a!*yh0pN5lthw(sAfmpPU?Db^*S5ONr;eNr6eWV9)m z6jKJ9w`sT6NLQCxT3x2Mw!|m*j~H8mEO_W_D1nG7imxMTwV2JulzHjZ1XTjUg0KiH zLMRJ@8Uch0PmfQYodZ*VGh~ext)zhyUKLB??{DIDdHML(Hb$4Unklz#KPHM327@VY zzH8SSNdA#xe?&|%Z`v22@PnFNi ze9hMZz51P^>ZXU^slxpW9sa6Nm$K^CRC`vHQ-BcBya1`XD&bd3Au*;zDTR<-hQlG9 zM!IqN%(*VVg~w+F$Zt9>d+O%Hej;v<1me*YM1eCJT^5u@jx9?c(5=Ba@9;q|`cqNt z6Y*+AyJ~p=LV4v3O5%1K)oS@4ONCU4=hzBgYiO&v#f`w+n+F}C)Y#vQfH@Erv=PohHHD$&94U6iu2Z#ti zD`o}7WJc1=e3zqAg{ry(;m=i~7t#?Q_(CD$DNh!imz1SNB@qN9y^{Hrp%AH7cO5U> z=^?LEM}4jRQK8m#dsUpeCsgQr^;%bNAg(Sf{J943F1)t-Uh|~3`qk7w_dIiq#aWGr z71{}xPseONyd!@8!*99a;E0jU^`PUcAm;rls5)@T!@DcVjveQR`#-G2;vjB}oLWOc!; zoPl{>bh--^vnhLbeu`|b;l@K|Cr#qzOUQ+bl&*yp%DdJ>-65%FsOIjv)tw60sJd^} zznn(z2+yAjUA$@+zix2=03ZNKL_t(`pt?1c`6ix!JLj7}32ar!q!1#s*Tt!#HTWy| zYP?Qrt4|5Ol0NCt8fPpjC<>W;h8_$_1(-ai7@W{pUB%31nDK--Qsl!SEj#6RzWHSq zdJWo*21`pzoQ!jB-uRfo-XoSeF|YmPhfGEjqFB|^(EfS^V>jn16G@~AyvtrFK2L!s))6HUSt})pqZ(ZB|Kw5ORy*S9^NTFE5{?EF zdYuMKBJw>|K48&0EVInQ5MV6Q*p@&1SxE-bLx zi8(&%vt});ndYhW23ODYc(CI*o@lf-80}r=W$cITm6Bn-_<~7ENm=BmNck?MbHr&v z5_^hVsU1StAU{kfE<%x7`4ma%J$(XNtdzuR-vw||`i^|$lR~Yl0-L(y?VK;%r3&Di zHeM1~I)n~|Oz66pfQDC{X=}W>sl}^G<-TiL)mkINET~s_avr=gA;u&bV102yECgQOHi;t| zNsJOEcn?|PIC4rUA*J%e=Mv_V_@O8cS22jV)g6jZZxhCw{5yoKX-wYUpz2~&U8gGF z3KGuYe=3TIBgJXTmS+S6`dKg}oOc^7g*8r>8e^=`T8Eh#Ls8^G$imC_8smaYu|^w% zu@h zEz($`vcQ(5Pll{-uU3`3kOCp2QyGot{ncoQRM=TgIV-U$MW`&GYYHa=g0Dj2ZhcFy z<}QZAC%~SLRXMRsr8pTE93Bt(+RJA-o|L3f#HBMG7Fscf!x=w*_W|R{jDPg`i#&gM zjly^ntB)TX^TOp7UbwslPK1_mNcI9kQ+FZ&qb+4odKc?Bf)J!@q&l=gt2wR;6{<3` zY7PMF$j1|=g{9GL6UA{*135*3plZ9iQ?dON0wSu9oqx8JGH{YBT8e+a(I&`wR?@-q z#8L=qIYetcnh4(e!ihP>CVbHvd8|+o2k6o#;z|kc1A^n)dWUq<=jdRUL|zbIe)Sa| z-u*zl@%lcq$B$W9zeuB%prXj-lc|W5q>&|TZte1Tb4SE!lb4=83$74Re$18i%WNG^ zF_S5=6daBWR^=4&3P1Yjmawxas{IsO)0Dk;4{5HZJe?LyMpNu~h7&1yu1T92MkE}K zEvx6Q^5_5bYi|E|$lrYTH6fBV<+P908n6`O6Tb55S9$ddukhF3`Y!h#AK;RbPBUV5 zu#a#hR%@j3#)d!phwrm}?_(a`dY^pnfJog&3dpr#Eh}iAKgXxTf@ZgaagI_OT3N!h z&^78+725t1&wUx@reyQI-WtnnG{KgdtkXnhl>(GRIuq6>H9}?z&2%^dA!u~kL~&Fn z&Zqgnb0w_#qgFkSrvSV8x(v^tbY5O`I?B;SL9^2&YGq*z#-Y*}s|{9H#gLh!XwK2j z1Yi5yMYq&VXe0^OuU-&EKI1!Xo6Yuwm8BlvSTN#RucX&1ND`RkIpxTZs7zRqc=I}=S!ku0vf%x_g!k_}q8Cjm z3n=d$A-XMkm#@&3ic%Z?@axZWG@LQbOM0!0M8eaTR=M@*4oW3ZmNnnLO2V87K#TKT z&m@jR@g}P4RzHV>ami~RZF7DhA&w)qPI7imat^0Ee7fED*GULAmRdYM+U3!~h<4@^ zj!q-yr#B9`w=*J1Vv@)|*Kgk5XGImXm1S$^gw5Oc_(d^dd+QwCg&vPia!y7C!dRc+ zh>Gs#llQu4cOWC_eR`Cv6MXPVQ5<=ngb=2QV@c_#X~NY&RvdX(Yhyx;46)dct=-uNWH7O9~A&+Yf!==Fy53= zD1?y2-DQ$i2jR>d01Nw}b0Aby7l}@K>0`u`lu;j(d`HZQKwY*Lq(TAh$TKH~rKO*j zNF`}xDL9zT3Pc5N2DQ2isqzNzc(WF&pUBIiK>sO3sMeJ6A>1U?v_ zqH9!~OBE{;;fK%buPdvKWR5IX-4jlACydsVxp(l6V*fbH%1o@fK7lW7v}HUPjSjM;2PyVW9P!nscDj)#SK zeE&X|&b`Qm)fNwLZ}S)b=sHh5^Ay@z*n2>K@p*pd3(w-LaUb7)Ao_zo|H*&&ZlUt^H#bK0ahTwK&yuRkSy%BhFuWiZ6cY zRc<^U@bJg)AY_Y9BgUpFt}w_fC5jVFS#bBxZSLN>fr=s)J8h(rOePZ?hD4Oaw&2QY zk1xJ-mZMS5aH=`8++;j6{Pd$83gc=~2dY&Ro}JUrf7PL}&QeTs0O~*$zsz)sN@Aic ztzS`fImD^L)f!8go7x<$O4RFQ=vRx6y2~~1kkv&=l`T{Y#zAHJ>09)3I#-mWm?UL1 zoXu@PRC5j?us=@bu^0ruMNlN3TIfwmYe)-Gy+1q}EEhbnQk)#2< zsMlV7vFda6j0uM^CaC;)RVyV0Iy}oNQYckz2Oh=CS}j&qmeFN_!?~i=V$ko?$Pzam z4#^q~;y6N^f{JrpEsAQ*R{ZR&(ct?(dW~;=`#WUK7O%Z`hvkj8IJ3UabZ|f{EQ2y( zb8CuY2}^+$&}k$*|KbI1?+kc+l=IDJ7Fl0xadUIP+Ycsuv)kp_^Go8Fx3@UAu}Cq^ z+1)zf3(uY7M?e0MjinYZJbRuGKDy6noX=yzDOA+qDUuM-ePg|nU!V&4Yv>aWgXC~x zNFqn8nK0R#&}l2a^z0dogEUgyetb-;k?`!rWnv}Bl89T6PRP=PXD%(HLR`4Lc|w1x z(ZZ4D6S|!?i)*WBk#T>2N}4McyDhq{nB#%1&C;q^TNO%D`q>XpJ2LgWp>v*6C6%Yl zR>g!4V3@6jti#hOLpR;42ioAnAm*Eo@UpYUIaH-70Rf(dGQ`86O3QdsPz=Y2*@(+e zpJ#cc%Rzs_@u&nLD5o>Z>5Qz`35JRwqKI^5m2`0tS zO$Orrqir5M+7a)({RUQ-C^=u7RiCs1pag|C%bM2XDS!lmV|Kx

    cr~qbF0GSIE0x2UT-e9ky7y0$# zH!DHtjz|@XWuH$7S-I3ZkP2OTkW8xTe5*~HCsgR#&6Efa^hA*i^B7@$DnT4Yjts_E3f-C1%_|D&co85zB{`o)uuY4z< z-gg~U7en|<9?Sr%$Ug@kO}OS#1u0%xh1_{DQlV0nC_uI5m5SKjddR>0fB$dZ``}}& z6O^T23);eXJgRAP#s+z4<9*YFiiC<{q>SrJ949GK3X&|M)evM2hmejaPC)b!nIp-X z2&rh;k~ESu+MW*AYh|L7DY|Rt5GodDR+m1T0r~8B@{mYuqK=iRY98!ywTe?c{Q4`p?ABFiNTsypH_|9l3}%kM zf8!DBi%pDk91e429AS{CI3|uG9vl{Izy1&bl-4`wZXK6wzq5%{!P(u;UCl*EB&xz9 zilb9#shxi>D(OYvQuo)yo(k9oXEhiNVQ??)v{43coM;Uwg$)vY73GQQ+5((P_=;)H zP!uZhXwAn(5N4o*mu zMnKI=&YW52h3nUN_UZ-x$v3~ohg$`MNr9a{_M3>cSbWzhN@Ai$j0l7MxiCazPnAg)8N8Vn|w0i>_W#Ic~w35`Q5Kk`Fh8%P&0fombM$%MoN?=RMuAh zE_n{Ptv|`%+eWvA5PrzAKC0rTx}VjLIaOd+=Tu<};hC(S3T+H!>DO?Sr8pIVRLqJX zTCuo-Y->akW0RC=VL`;CYwI|py&2qWz}Cr-!-GCj3YO1bW!&sBi?*0?h>9CXSwc8yEjHg31B%I7yRIj+w4EQ%h_bY;K6+cH%~CC#g%N0orm}NxE-^y)aBjx z@3D6{;+bn_Nt1|Ksd@j#V=kOq;mlf(t=+!AR>39Q1z@R4poH@?Je4QIX$l7dA}M(K zY>#$iIT}n6u_6+VYpYF`I|=*8V;YT^gNESwi(RHg$*d?@>?G{$IbOQZAumcMxu%;* zA}rU>bm=uCb{}gxv3JJ4c439M(_(j+(`m(|NraGP=&TE@akc+a6p7&1VlaiqXg`k# zp5tE_L!3m2DDnlpwKxl;*3R?20bfCQb`s!DMjVG_+-xz^%lb0{P*+Jno1SQAdK_WYG*rde&ASzmK;YQOgegjFp;rFi8@+YV_3NH>4~ zsr|kVLZ=Q9<{97r-~)d6+Pe&MiBeIx2bQudnN174LY4o`7tU>P>GBn~ym4NvtZtAt z8b}qBD&Zm}g^*q?PD$x}EhJD%ib}Rw;E++|*%;qe}6*5H$m-lxC2&y5?OaP7(!ck9j_q4Wq- z=9r}A?~%1+X~xS>pJSmZ-T9T4xN>fldykGurSA$mXX$ntJbmd5!j?RHahdbWE#BVQ zr5S0g)*e}l1^H}7r2Nn|P9p<-$J00@L=hs6QOXfXOBBZ}FSI=kFE4rRai3{nd~tiK z7^o-!e$C8_^QyQMLeOYt^}qRqCNN90PR%xaf~rA|$eQBwNH()pPbAykMH{@nA@aL~^wog*(atEZESE!)IlanDyma@FKfOF0Z9cWM4(52?^;IKx4<2bKu8I^R?go694{R`~^Sw@lSZ}nd^M@%de8flEafeMNzV{xWGjJ#O>S|37e!u zR#V8BLKv=|Ti_el)>({3Y~H)U^7=X>xx%h(kw%g%iTL?1?~_J?Kl#SXD*2m-5h*04Hr(DirjthO_Gc`1Eyg(b9}*zcDNiXo$!FG@v-iAd>H5v5PM90C75A+U0;hE-YCu?nbX5n`apuZ7%GXs1b%m^h7nvEY379qI44r({*#6fZC!q+~iP$#szY zu8cN=5t4J3$z+O(VxJ$>-IK5YoWq&Y`@R_ML62H?*mp##;#gE>nL*vJ)CQSYR+kr9 zT3$qlcqo+&1L0v$wLu7`YEK3<*M<1+02QclE);&XPe+J)6?@@y*TV%cMhIW1ANNNX zBC zlEQBeLex^dAuJPKSWD!(vcOG`u;VfLAjb8Nu}Ms1S0GzNM=g*Fi^L*`k_4w>AG$*a zrTT6jiE-WpFG)fm48bsTE#`x`zHAXfkfe#f9K*kACocMu6 zYjDXiPk-?iqiN3TZ@xo9#QI{3M}vS23I#6WlUw&;vM+KYh*}H8y;XER@k69Y zW`*PKqdhhc`ix4+U^u4KhPc(BFoxM|hSG{SY+?Z$JXJJAXeay(j&m3haqGbWU;pBD z;yB{ggE0%eCaWUl@t|LOxzqqzc$WN!x%xglp#W7CCgJ8tIp4so^J+6rNM%CHyVs18d*$xWzluAgoB+;HXq$*>-Jk>^Zr8) z9wbah{a|KR6+x9U*QtWZ`P657_kb)(SXx>LfQ6(#9C2{mXLWUj^|eI?qbY;&gxPc! z5-=G$D1KM(_Iiv*L-KrvwNA{tw(}y*hJ>veL?(bENu2WL8*j4n@E(KyA%pEt*?aH_ z=PzD#wit<>?JaVfa_7cS=s_2aLJJV*nqVx$GUlC|+ce7qj!z~;yW6-HsI_HWx1`;3 z{O(turz~>rZ69%N-BY!iFJB}}6nlF!=BbNEmQ^)W>jEO}0PB51yx4&Yol}AquYr1{Ix|ES}8AIUE!UZJ1llGUbwi(Qa7bA@T2!0({0AQaA}dH zZiY6F*FV{zmBl=FX^~zd=K0IZ{OtWlthO`&~4YIS&S!wiUu zf@z$Ro&^;JN!XA#*5H`%T{+=E1+!Ht{D3)1AmeKOA#`+=FK7KQd*JX}uMH&;thN&x zi9+ER%}T!e-WG=^Q`+qYTYCeJ`ZJsqEG@Os#`50XJ-+eEdH(qKp615A13rCpNF)_k z&-A#u(WcW%xxYK&{dJ zih?Zc6V_;=FazidF-eppG}mI^ z&#&!DHETM{k0tE?+L?fM-AFt$H^Sq=iN?h1yJ#04b z$oLPDwYY$D4l0_S@$1?WLQ#+ncJ==00R(5Ym%7ekhW#m&+IP8y@BTPzu|jK@=~&b`2Z(Lu%KRQz@o$vWg4RWVn^+W@$py21z{0=3Hxg{@8&%r zms`d3Kue60hKtio6xw-{$)K2M&4jYZF~y9snDETiSGjiO97!aR!U-3;zb;Vvtn@o9CQR)h6jYeW?8mn2duYi7+JzlFzV1<1eQkiu)l2@%!k zk-$HA08vztjXV-+ES?Xm6jBJ1c7k)%$!%p;Q)Rk!p&vA7XU5I0h=U1Z$_5Mjo{ z`Gh>QkzJjpJE{R#5Ap;0^2D<{aa1olTBw3fv!U~0x%*qti zS)vT*?%T7XE+#lNKc??aMbYB%PR{Y`53$x_jA6OcU}EQnXoR(6tByp~y$A?E zwU5_HKuwwP34omcbzZo_6Y5$O!dBmN>5KfjQzEKD#8b!8MDmRnH)v;yH*f5aiikh` z%4KdnK4x{XNvhz3o7)^64>;P{=h~SjdUVW8j=6jLBl7V8Ov%#n8W%2KWiUGC;e#EP zIvMNjbKDYMeQ58|Hh=%!Efx|ZdYvXR&A4~>HoFgQ^2rCkWHuSIvbIi|HK3-0P}5DS z?u~Q4^&drw-Ti&~g8^|8lNW}Q{(!R7eiq0f%A(}BKlFpRr{=o6=Z++aV@B4{YPDEj zU1dDYF~*SR1*6d*&{8b2I9DOhPIWRd60OB}I;)pkld z^*%FMB(bR?OC(t&h?KuGjWni}DjE^YtYeyMvPjTLeZekqh$v!lb&*~tBhPcPM&^@2 zV?BjR$XY_TdVsyLpz)SI7F?JYB7h|hFHT~Nmsj_q0&?#4V0~x00=oQDZ?VR)w$fqs z@-kWquAE)qs6Pc``1*?*l%=LWExEThrqf8cu-d^GO)HlCWc%L#&)%E;T6SdVeZPp< z(;4qPZ)RmEDpsalT0$_yz_X*J;mUMh<(mwx4PkHS8agI;ody=oV_Drt@W*M zeIMmCr`L{&vy4mYJ%*#4`;Yh7Sn9HnNlx>cS1$L7gk^IfX1Tq<*1?Fax{ z=uHkk@8_KJG+imV^JL6N&xYVEYfFo4Y_@s0bx2VeF0FMrIvIl!oZnn#dvCyGTwq5z zE>g%S_Gok{*jxY>n+NW!_NtUp&O3aKFoA0#ZJ_Ihvc)yAC=>(MSd8}fQZw(QTWft+ z#yOmj80Q5BgpyvuUr4ID4k*6|@1%%m%rShtw}DpFP{rownU`AkidPmfquu#?>47r; zlpT?h)U_|N8|wh9r`ah1tt^$&*Y9%2_@?Uq3FpTDp;bzb(!XFZH#{3e2vgG`{i4w$V0`M6bT?i|@DI^*d zl;*G(P3ItR8siAr@A&rzxS&N(Kv!nY=XiRRE-Re1#7TrwX9gX0g)OHDozqJNk&wt( zQWlQorA1!*`d8?!oab}TU*_huOMLR=nE&Bl{g8uNBjePACyj1+1M&zjk!r0Ex~4YN zb&ZNt7%>53~C=GaEXCMEPNP=6@e54T*1OH=U1$x^On}g;0c9FgQMVe8SVc0i)5_ zBc?YtsK+JNcu7ixZ{4@Dgg0J&$&Dss@oa04o7XQh8Bck2(2ppU1t8Qg=4V)F@;R&{y5G%{+(H+6Pf3bdWFdE*=pFD>(Mcg(Nc>T|HWOQal+_bYaXyR0v4a$&v4iIZ%uFK}*s zkq3`#xT?$Oz}!B@WVt1K<_xxbf_w=PnuJ`Rb9BxXEh^?aMJf8%vtdF>1Q@RL*C z+10qL$JWp%6G}uJ9Fzzl1BHta;^x7oDHdeYQnz-d%Xn55YZlBzQ^3#Xmzr*eJM;X` z7933wJX_Q>Ac1w3)ow}_NxuD~hm^+hx4wFf%d2gwJZGUBlSGpJr8Z@m^R3Tcrf*M> zs~ujr`8oG*|6o@f?&YW`Pv@Hl?N5HMwMf3Ub@DG&1K>^ zMrIk8uRX`zpRcmGv_^knk@w#DDdl81L$&<}6bL8g=&XLkx@&lq#9MNgDiIwnbcL7N^dCt-CF{9Cls;-HGhz2wCxY-!Z zesh#n#n->_HNN?+-{771?r`hob)LWdGV7~Lj3*PU(@2@}-~7`*M$iX!*RuTf4)r?`=Qm7!g4y+eEaP!x{1Idm}<-Eq+*EFHWzuPolq6!47YBjiX`?XvXPRs6F450JlQ?v zmFw#~IT*8joHH#9QVLX*_!-2RL~B@1E+m)|WTs|oPM0OOpIhU`W{++s;r_EDUc7mZ z@igc7bjs^5oae)K%FpgRL0gNInNR4OJ#W2Ogs!{-RHF#hP>c{FWc^LzX`96z-kDcy zn|uG5SptnSoLlR$zOu;n!GOuMBvLV>N#UPP6O)}oI!CYDrOIn68+_KKK*&Ic3ine= zuc&2;98AsiE1RsZEm4&vCxbD&ha-|!!o>@#2%$&>45uaAheM3EOeeXQ&IjtEB+U|x zHt1>Ya|&Y+fxZ-tD zXM^p8e4(MgVJ+6_!0fOz-7)LV6j32c(6qE@3aQUT7$1vd3|7;0bv%vDAcS=0-!oJ5 zi*Wt20Qsvff8x2h!ix`DO35H4=n(+{H0@L;&mgg`$?HS0;Vm$FdTXj&%|Gl&Zi%0U56vS~7W?TGgzVzZv{)_+c8_t+YTsgnV zxy@yip12N$ICS1<4eM}WcIK=*M02=U>!_-lVv>`#QsOwCpH?mm3Z9{y34~V=X^KJo zfj2{M-Mnxy&Pzs&e4=ic1|oHYm`i6iB8 z#mj=}WGGs3Os^%`SXp9MduqXM^#psxa2cPnf|MCCG zWHKRZWk?*q`+NUdNEM^CVR3ntKmFd1`O#ZHXLs*_rHzX`e)y0(cRwW(hV5s&=;v>< z_QF>fOcSQZhZK8HS!hY>{ZA$mv!b{mFBh1Z1Y*T5MuUve?AxBliz6u_v=C;Bw3;lAXvYpIj8FpFt(aOVYU77cYol4{r+o8E zFK}V4>msS>v=ZT*alLw1obSWN>I(NidY8$-&j)zvP#fmU1j5b%1BCJvlsFQ-UdIW9 z==XYVd3lN9XvAPR6rS?thw-hc5yE%m>bRt?p&AZCp&^3uout?AlO!>9r5Ox{pF#a* z{wYEPH)%ntEUQ_?T3fT;m0Vwo>9s407-}sTOr}KjF(SF(6U``QXHf8Pcgxd7g}{_0 z+2RVdN~mj1uP$-p0j@G6X-ZvG{^vy!5k>yqRKBYvrKi$jfyf1-XOk*eWYd`r?>~(6 zdJstnDkr$RmxqGadNssI@#v(Q&8W$6|4*jnJn0Dq^@D?aUPMcY6p|-LC5S+vkrEYW zoQ|eUPbbKz_Va+T0%JVD4sivNG-Bs;O7=|BYQ;P`obq^oOeQQhkEfhlYGYH${Ri88@ZN+MKKDEe-5zg! zyh~xBx4w!>63WW(=7)P+TWfJ?G3DcjyXRjznb8A@XC%pLFDo01Btesn;-A?%N zyPta5=FkZcLSnRLJer0WWM(R3v5N7-(RJ`>krd-Gll?6=`YA7OUghNAA$ELBw=Bp` zhb*tGuvSb^k)qXJF6OBWgpMpT$?@6RI9tKk`FY>WNi||QN_tvxWo=Ltmc&Vl3c@V9 zHavN<&8shs$a;%2^Fp6DiFx7Z47l3gD$%@)MhWfD#SiB}0w;!g_lN5yItaLMx&MLht?oUQydV5;=>w`94OHoFrjc#-efRNV&41NTm1Kj+aM!0 z&Ryi{)#unfDH)FoL}!)hXaYdeX%jdN!2r^~&*l(Qkt9xIZ)n(bY|hea!tcF4ydxh^ zaMsc4b%@g-3y7E-6NW@s2tlna)8hf&WO50m!fZ*PaM)lxcx9u@`Q?nNtcV2M{bUX5{!88V-wF_$i1ar-;l!s?o`syIG9rPu3n;oJrv-Mf#Jg1W4z>k<`dtToXP^Fe8S*pmzS@tFpYC2gCoSW zq^vbbH{tag>+alA%Ay*Hd+&XZmChpH`oc9wYncPv6MLhIq}#`38RV9mSI_gc&%eZQ zIO5yizr(X*;Ri?qhdha6p1-oe=2F-7+lkm%>XJmKVIBH_-wbQ}ClC@?W2m%Oj*0?e zH{-Q8MZ0L!WafNZ+pIC$B$SROn)|qUrt8=I%rl*j=GiwAmQ7%clw|+3;L+ZQS8uNI zXlKChfA0Y|E-oUKq@6{KCnbj`Q*Ldx$s$Q>c}a|p_ZSUNsj3nw9Y$9a(&D8(=r{NcC1%SK;`RvKfiWB=fg4?cLGy{#wYMM0^(hmSQ5Av&DRJ(sWXtb7Wb@n{WP*@BGOhlV)u;Zan5+{_%TU+E}C- zouHBygFDkW##X+mP8WHb0JW@n934NrZ3)*~SjXZY*R z1qxNu(erazQ5yRq!&ncRIzOZ=q6oCc)EaFSDo}Z%#4GIx<)zGV&UU17#Pyw;JxCS;;*g{aU4cG{bAySLl{37q2dTL9sBQbUcg0HHBYyWNaBQ}!xNNn zDAhq2gLNhVU@FXNz+~(T$>ub&#*ihEpH~uICRuAkd3wxJx5c>&>ztgN^5E0^ym+z4 z#jaxSW&fqhB{{lqMF`+LD(wMmVb43%NKX zGD?tfigS)iTRyz^h*w|U=Elu70uyM9E)4q%Vj=v@rt?zRsWmi|GC!)TLT=_)mzZz* z=BD9=NI=)Mv9%t}zxa!D{jvc0OD-X9`ZQby3&D`!Nab6CMw=k*XJ^F;xEVcYo&Xa% z7Y$-H7YIFzp8KRpf(z6DLck2gK=bD&pPng93IF@ECHGmy9ypVPhh+IooSdtB1%yX9 zW{O=R(6nY9lBP(S6;(|*_W?ap0@Y~)78S|aO{jB&D@T~|36b%Gd2#IhRjgG!-8m~uKH zR+1!%X(Upe2(-DNrS8IEEtR6O+EWEgL0jZp=tI2}F;2ZFgp!gP$xq&YEc%?dt=)Z0 zvchSZ@b1SuV(migrm-SvEfV+o8Gp3q;r$lhs1JJKYr6zqg3N*IlE-un3ts~wFK zj(Fh;rz0&MZIz6UEQxevfq6BXQ4+Hch!FF63{PDoB%*V$&{`uRC4`EUvpBKPZ#io+ zw62*JC0Wbs+z$pr`u!eRmXhZ=bzRf#_E0KfduN-;B=?Cykk$O``ylK!Lw9+d*1`tU zydYaTPiOTS%a=CD$0MYW^hCsm`=3xApHkQ%x~fULJ+gj}aqW}yY+(VBCRpc9)263G zB3sc)ypg0ouEfl&Qp`_E?_S)Xq9G@lfe3PLn(Ebu{M8K7$C08oA*q=GL6WAs?3%UP z(BFhVDatYQg%)XoV92JNuo$1MJH7}J1v-;45(_2j3Pe1 zzsswyUFZErhm;0Jg`Sy>HruZ`pJ%`W?z1X~A^+SRl-#<|=kB8e>RNMUW06mv9n2*PXsdVUiIV9c&pf(!m zDtb}LxrGi&=TueA)%70ZX~}{0?=w<@P8M7iF_Ja-W(1>b-75lJhd-|v$i7eva( zW}nC#L{(y9jk5|XBZRWyeR;7I4|vG%Z)BKh0)d7=X`JR2rdeCFW82Liq!0+yEbKOl zXnsF_HlOkPa_(&20Jt*%#?I%48gU=Lo}8awJAVn8v>E3mlku3vejj5r+uP5mifNFq zF8Rs(4;ht~gOe$n8;@zXyw8~RF7g6JK|rSwK^3l{c6!>M z5RzKg)4ZyV|H6m-1-O1$fc#aLCGa|ZJ5&*Zj1ridz@3#dmt_yc&bNflD+CZ{i60CU zjna|}8(85m^F&@KthNXl2HBkpLz45vh#;$|wIyvO$k;oj&g4hkd^p$CH4Qxq{AW3f z>I=k7cbyq>DMGR}o5-H$c)}572`#l0*iAkpC@;T7Q5dYLNs!Pm@yqgLF$9&igud&`)>;VmZ z&doB@8C^(7#-(9o4Z>QqjaYAIWbHQ2>Y!;7V{OG`n)A;4cl}zi7Rm`yB~+&5?kA6l zBuHJ*Zwcb_=ULu3kG75vp5{2`==D3KS%w*&V2zz6SIs)Hu0do8f6uIlUSIArWr!)p z^xGNP@*-0SM%S#ZZ}N2UJkL%dane~vUfHB`ZkfZ@MUDokSY1ho5fs|t6sWkxPe0z} zfBAzSVuWJrRMTBtrcjF2g%)WP5edtkoe9sLZMox7!M#%Gvf<}g3R>ILo;7uj3td6d~|2D&0I*0~m6Vb2}&^6~~#DQEPK zPAd6Z-~5JKSxCiVzvo_g`DLMN&G)|hU7qaha{bZ<|LZ^h=j`n4lEo@~tY)<~pCQlz z{O4&Hl;NBR!?VU>tr5-`Os$0oa}ff^WHLoXFL`&+A$t5Fx>Dr;^`# z{XDH$P*fUY1#fkvEV(8jQ~knx+ZpAUo9@ZP5pKYV|S%}&N&|H2iPyD`TT z%^&~lDNCK0-}=%O?|C5y5^1UA4481n3lcO5zO^AoYEC)p&FK&d zXDoZiQ(n2UL@Whc2V+i-M@(zW@nC_KUWO5p!_yIYEtu})OvX945LCv_5b7ip<&)Bo z#0itUW_S0Pay(^o?JBWwTwUw3H^_M~>%uKWI8<7Nbj?$#HdwE(_mDodKhM(`a4e7E+w9 z(7L3mGU}?Nu4`|0YAsQuT$U&?Q_!5nO&@HVv&jVs|Jey*<(y63EY}7_IkOg;InB9o zvcOnRoAzQnid#3YGt4#P(z?;K5=TeJv|1TTNmiB@JT+1&PL5A7y5hlJ!QBUM(`_eo z+b!z4#%ROC`yaU?AJcBNL>&8$PMoz!l7vogf%E4t(&=`{^8%$5))}OOb}J!CQ?jhZ z(n6P|0}1CXOXCm@BDBP+JjrydGL@hNX<2&qtWb z&lp6hubO>M=p%q{DXIW)c*M|@71d}++UxlPT!a^Dx(q^MfU2q~rv*q!e8w-Kk>HgA z>b#;HPl!7ml6D$4u9yX$266Gfa{+0ZCuU79-sq{%4htMIbT0^+-@Cs;oIA_ zbzEBQ@^`*?f&Hy*iXx{fa!g*5#1dWCR8`GjTo5M-X{$wE8ie%i)RmP!w{D#0-fqOX zl`e(0Jl-8~ajk=tlAqk&=f;ITQVQ-q9)MsrnBORYH4@B1g$_`lw46Qrf001BW zNkl1Td}dajIQgz@ee3$5IGPb&78}k&XYlOzJE_KzoAy0p&T;gIECm%sn_o~JgRmLYV7GsZ=c z5=sj9rB|P0b+Ie{=8HYVWl44TfaAfK)7?*)?(g#?Kb(06`De`x zS!<-Iac7WZ&nKOEM;NcW?;A4~EVPDu|MZB1~JJ)PGbXtDuZNsK+Q#?o-?2CB6zWQI+ow} z*3{l5#5%f(;%~ljkwh5oZy(WL=+ez1PRAvsw(K3}Xya!0xHb;sd=hW1=fBLgWy!_lcU%kD~-pQ0vp;1zh#(vIBR~pqyePY{yDpsN^-+|SY!Db0b z8ik@n`jXrDLE%@fEfblVbBk?sQF7;QbstY#!HM#ET#5q!f1`DDv~Ut5f>m7BDQ%g%d9x}UohYd zRu_Ek#cNzx>oOeD9UN6=YX;@5uj*Vy0LWjGu% zJe(565$#J$q)AL$2udS)_v0;2h6U@Zi|n0D+1|g$)9q8nbwq6}IWg_Ube6mmI+t3P zv_uzEN0PT*iZ*pR8$uIB3lQqlOMAL%!3f zdd+er97@PDa_RGB&~#fHu%(e)7U9e?jVfIDM;A6X$@82?Pj^Kkj7#W=$~daZxFk}- zXpIoi&SL6XQtH}i)e&QxxWj{jvX}}X1a<4YnAStK_m2_O#Bog8N{D04demaHHD)q; zhEOpoN|=r(NC9!8P%2@4W6dqKw#CNs4xNi5OUe1;-UQ!f!1$ZN?^wF?XUp z9+0+{k^Qy6-?j*6>7cjl8wz3UVHT= zmpLJBKmQ7YX~oa)eoETuae1}F`eKGqisR!E)A5vF`P?OnqU7r@pXc%3h`WzZLSXXA zN`tyN!K~}ic(ybiD$O-dh-af^C@DD{6ch%oUpde18yEQ-zwvec_uu_CKX~)|C_81E zj}TKxTP>_Hl*N=zyG5lPODoHK?d#uQb?qDk5Y;O%s%qXssyra|6H4*e9HdGgq4*=j<=q$_4FC%7bA*?cRAkO=cIa- z`1}=4bw(V;tgkL`<=g^stmtMjC!?HKo?Bt}XiBX$mp2y4%bLdrIdSAU?MW2P=qh4< zvp-XO{Dn*S*{boCppYX(ctJipHtGY!z^&c1YTRQFxBl}^l;Z?98p!~RLm zYuDHK=|@|f45wUP@3LzRx~j>?W8QlA6PWCgngO=X1xT{~3RbmPJ%16MM-&HpC}%MF z3BUVqeGL0yb!^%ihZ#?RmW3B%n-Oopedu5Zxk^=6=fJ45}kGunX&t$uLU5J}7^c%Holb|PMPIZJha-|W#%M!b)d)Am%f4MCTf4~V$p~jOQL9DL>&>2t zR}=N;pcG!-*D2-A*P4RUIc%8gXr7q}57Yk|l9gc6<|R$RYE3?^7)(p5vf`zyt7MVj z4}SEFque0Gm`Hh*wxZCC%i1SP!b`69v&bjyk!1fkrz$HBh9#dK7L-<^EOisc zrS}jr&e15qS!2CAmUCF+pP`U~I8hg`G0hRWJzjTI^lObhQBeO2$)bO)+A8>xX zN1UbTBBvY-vE3D-D55BG%HfdK@*;6Cnf(iwoBt}MoShSA2iS4*{cN?R&I_U>ovl$1 z#z_zsCA`$Hiu^2=bH4aBb%C-a(iFV+;}1F7d5qIJu`9^z1mO(UnloTeP;CkxT#Tj& z15QR*1(+Ho1Uv6PLAXZR);riYrocJ?nf`VBDppa1L7}rvqDyaJ(=L_P{N%kyEcIJp z9i{0qREpR+_NUS%g~bA=+uP!Jr0Mk+Y4!T-ADl9tmPCuIJRAA$SJq$jv~uC8*WM$k zrY!55HR~icV4X1CI@ZF`S%^C~H3xV~lY^DiJ3sbzPB9r%08$ye!b#xG2d2kSpmg zEV^DMR7y^5bgWFG{(VdQ|L@l?3y{C$x^m@$)1_shn~5*pyhS%vRCz&B`NG3!jjn65 zEG5elo^BnmH=c6!`HL8#FvbuygNZ_fw!dSLYaZ>6(X~Z|C1>%&>LQ7Wl0MBaxsYd^ z$?=;|3P=;>=|oLZbtV~Z0;)HgQQ`O8(djf(i1*XzW2V+zmlXWtLh(f2r z^T}re>7k9%m=$lV{?e{OV_BR+S1MWk8AZ~pqLlrH7JJ2|4LDzc^=erTFq&_@vPmaXjM_1sL@_L_ z51s+1X&h*sQ=hq!ZYHE3ZoG4|LF&*^Mn;NhS@ZGMkcHj?tE)@A_}nG_!GH7{6jj9s zckYm68MZ2jlbE`yDD#}fg$1r%Jjc>P%<1U?yN3hb{qPe^+;=x#`=Zz#*3>Fv`RZ-T zZOf(eOO(?I4<9`M;M%q8bhiU_Nja*t?Axbjhw8OJc@6hir@Zghs z=xRU|C(WG+zXp0@pdND~jE+XwszkP0sBUi#5`@sqqN^xba%e|cu$GPFTa|^65wK+V^dAv8Gl_|b_YmM)|zr+5p zLF1&t#Dzrixh%M;f>xJ3En7H#Bq=oRuOfr zgYjq(%`l#W9xF#0N%GPg&()QuvPuCzySLA)7du4d1Q{jVx_*ICY1lfC|UI9L!fwx05k#K zfH9Jd@D*6i<@1Y71_O2ug(HgNP|$kw$AwOY zP_d88kqY-;W9k~`0ubVSm)8bA8mS`x972%{zMHM933Yvd%ty|;L`Wq$I-Rg{I0$NM zk}QiTrvrZe^nr+E8zn})=Qwv$afTs^ToO@8R!yS zSTmV({5?SU{o2T5`=1d& zmFAHPhq1m$vesg;L^3*ah6f-iuo!IcC9@uxAwm)>NgOND%$F>7VuA3K?Qje>V1^*P zVic(+oXp~n&(R14s1-uWpjPSqK8&?On;?@N$4DtrO3`ljBsiWud(2PYdAF6R;ukU( z|AqX}|6eX4Zo1lPb8)ln{?UK%I#*Zwl(n99EWlz-847}g5AN^qPyWw8p(9I(TUaMh z;b8IAvL%icm!Df^GOc*DHzAV>B^vb@H=C>QLDZ|GK!d)A=~2#5RGar2er-0h!@sBs zgHKJ~971%%rkW$ZGsN;tQWp@1Cec2tCgrT1w`s$VFhQ!Y*KKidG9i+JYu7IGqo3a4 zJKuX3aJVw1YZa|v0M)3_WLZLQsY|rdLlKc>hDkYK|6od?EqS_$-ON~7TVR?O93Jem z*iYDcvdiJYDX)F;%Z#TLPpA6`tH~!rHy#c}yT3}LBo#2JG;iO1ic*s6=lZl-DNhf^ zJli>8sh85}w1fMszZa(RU4tA*Xz@1Io^2fd9Gf&PL!=6Ye!)eQ7aQ= zZFurzm#Y`oc5oo(*k`xF(Yym0%rJGZ$Z9zS`)mcd9pL$WH4p1 zoe-r7+WKNmsE7wo4jCm=j<%k#bE*-GSGm7eiS&b~3`LL5<|QH}nG_X8RkPU5xOriL zhfj~Ver1IhvK8LCx6g1|&1ryV*7#?NfY6Bo(6y!*PKe@&wBPk~EB}qyP%KMpaAk?? zc+)AP%`EAdJ-_g8&d!3&LAf)UEzSEtfOI6WWHhN5Pc%E#3BUJ$5BTO+UtnXc&jH=3TU*LcGXWQ&-oy_)fvrolrxi(ZI$je%EYCq(=*y~_%R7D9w zvb?mwG|$mG47dt!Zd%nf$H&K%MG?GqysA}Mm6+Nv&2x&Pq}A?XteJgX%x+tA0Qtmz zb+PR}cVnI5;Uk{Eyuep)Z;(YGRg3*YL+xU|e@9_u zyswpY#H|<^^@%zub#44CT<9dISYowCDZ%rXmO0$1$)^P^H|4@ckI%oj#*g3mh|zFN zV&U?Ib-L2<*1c_{O4#hTSY2vU)`sG6$nKM;+<4^@{YDVHoFhsTfBqO> z;5JFFw=I&MS%C6#)_7`|3*BpLOeiGIuo0TLjKd`Ye-uO(^_DRA(jR+ zIC9l+AR-X~8k1MP;Kp}G%b}!UZa4SFI^UtN(%++?sp-X2bdAv!wwhw90#kVp6AS*n zJMW5a$^x9vb#z??u@#LqDs*H;=#2R;hjX6pBxyWfn$0mUJ_KQiTuP*KK9{ltvrRW+ za2V?)%%xO8P{(IGQg}IS53E?UwK$`F+;Sr1QS-UjCbMedjIkyR+6#0QsPIzFilPSi z@<5qD_%3reUyK)_h$5s?La7*sK`B8i5tKy~+H^f;RWD)(KKm1SsbBs{#()n{DZFTtJoyYvnAO4I7r-rz{h)NPFZRmAcT)upn{k?6T z?H%(cfA#~Ctiy0L=5YHFx36DBqQvrIpJ7p;wI+@t?(YnF^6Z3SJfYRj*gU^Np#_J- zf;cHiqA{iMsx?L%^3eocYr4w|L_uz-L5ux)Hm9OBDXFP7#b}C15-$fFBsQ&-s5rq{ zL!M6n$&1fj;J^K^{!8wD@+trNU;Q84dHY8qR=70F#KlV&`TAe`78fpGCof8N_Yb&n z^)e+X_qLwk>YB(oa21cXwpmg+wKnw6U1M?mf*X}ibS5QNZ+#A(t{{>gTRZziS)bjZ zVSi9?;mSn@;}RnTOKZy%RgE>4Np3iv)))itJUnG^aKxpx7S1|iCE4BDM`}&Bw8G=P z3C=l|7CMOab3EHW;OXgr)8)^zy7^6twKg9WDN(D-Wf^mHa>CYeNm&`zmfG~&3DctD z&Zh_5yt2m1Vu$wblwoc_1tp&*fe`Z|xG5HJpi50X9AeXyxZ6U?xm>SQ3LR9(^l(5L z#k4v-gjykr&j=5kS>Usu6KDu$>UU_6wPvdsc)B~}_3Nwr`j;;w!ur@do^Udp@cQj@ z+E!NCCn$I;P%I8NrYDK|@}XP+n7FtT@W!gQL`ZD(}b8EKXUx~F7$ zd65O(@nQxRq*Bfygp`U_tIg6v-_^CItST{{Oqq-($S9)Q?UE!hRb99v#)I>$wA4tEN&WDTn%dN9CF$HYlQSr~-$ zDs=N_<7S->InP*d$e9Y334C&#AM$mx1K9;WSLmMk32x#vC5a=9wLCie&(=xKckUc8s=Q3A3Vigl1JxpcPM_`! z`2GjmoaBZ{VYt58;j6b-*jQ}wbZ^X!OAB0B>v1y9d3HGFPk#1<(n)G7=hT^KE`KhB zByB0m((i2*$Nn4xvNT247K5ayOhDf~b+9-Y!)>3hfb3J@Wg`1PYRWu143va|S#O&di+V ztFrJu6#h^nOH*dPN7f6X$Vg&q9p<~3{d?;i&NQ6|@2RD$lBnH5)CQb(dOSd%9tt58 zE>4hX+b8D2zwKCoGZnhlL~)D~0Z)h-N z5+PlZf$`BClk;_UHqmMRt@TAKO)T)w(a)AN&#?i-LMGsvBDMj!1j;$DqGvTiC~umo zYlf5Q?fv4$&L`jN-rko!{xKEiJCZ&crI9XHqyK zDHsh;84ONAM8vH=QJRvbkST*HC%AS7%oS~fl1Sx;DE<6^@CMFuerWo5=v(qaG;<#W znw6Xl$u%^C<^bhPV%E^3KEscnA-SQOVS|pnWnRdHVK*T}Xc33*NP{%_7eh!%HOZ;V zil~*6W+?*S@}882@4mN%s&cj-JtNB!o(*eCE$A#RA&jOhMwG@;6$LJdFvd_-1=G%SU6I_+^hu{7)c27#4?VPZ=c#)!Vlul8Jl&X?c2L*AK5N9dYSaR)V2`>VoEJa3< zN23I15*232)vTBcZrf23lm5T#z1fdt*_Gb++rt^|9CJj@nKcirVin2a*zAEV2@=$R z)iPumvir&Ki~kTk8HND^24p=LZM1Dcw%m}~-Rf4eNj96!B3V^r%|q6ZV`Ro0apMkW z+{JV0hfMBcdf412HPTWfvapy%0nRAb~MN-9*`W#~s?cV0v zr3?InzxPdQ>)h>wTs-mQQ~cg{zU*Qx*}im#N%^Yy{eSd#c=Fms_r0IICH~D1-sdlV zzKcPVpPl+SA?L`en)7+d<(&cXxa8*jF*hI1ps?J(cbnmZ45ViK@SNSb#_d*EA&7+I zzoK4QffuAwnlllM`Q}h<3r*NL9aKWZi3Ko2$WEr!1Y?KiKLQgZ8H&NSOY3z+34gI>yHR+8r>tHYF|@tiL|(c#Gp1E!B(quyS_ zPM>BVrBF#1p(EDgl;KL3J9qZTj*f_w;^cVDk7oB-87NUyg4In+Vc??&6-RdtFy%R` z!#=%k7o5OJNrUGJ8YeD-W(5?bAurB3Ih)c+V|ty0LBC6{*9BMm!Dyv1Eh~l}WUi{3 zP7*O1jhJN_lj)2!P1)Sq^!o+D(eX(eL`ms2b{xKUx@C+LAd(TPw?ryu#_UL}Ips3wzkP|w8HuL zjPvoB+SERwkbZt+&>td&ptd!}I!{GjRg`7f+87b^v5eQUMM9vpNzSE`?l+L60yFv62#>s*3@p)ae~vMuuzqEfX<@R z)T2?_5!o$dQ@(e0fhaV8YKIkIThXN^>hS}CIE$%$yN`;LM_PihYBxp*iaiR}aKeiq zQne^sHwYY#5U4C6OO3G)yxz@VbzN0dS%He9wruGUBRD^wGuhuG(lL5^Hb)N zQ!phIW8$>O^n6TxK5dQ5>+gKR?Y%#u*G!hSaxbM6o7H;vkL` z5-l6b4CDtp^gqkd>d%`y5ZsIaGgz+KEsfpdC_g+{S;**}$SA)2JgOBoD@A zI5)vjmJun5Pzm?P6vb6nJVoT|KYxx7KKOvEJFEQLKmKD54)#gnq=jyswSn!aamvB* zYK22%jUOPMWhEzP6QWqtOA~s%4xKb1NxRM=gms?MI^0kHW_BUKP*)W?jsq|w7u8h) zdK^&ZX20Zl!EgTdH~549`VaX255C8>OPAcYe)G3PuagK_@YAq_spi~p$VSy#NK8>-BF_S) zlo!+c_pjgMi`Q59;*Av!Pp7>0=?PYP8tQlNoiQ(KuMuJmKYnkI7p||eHB2z3Vw#og zAJ2I1%80BqSO;(3I$=65gBo+tnW$<`$2m9eo%zHdTvII+-+%oMU%oNo%EpjSAD;92 zM|*6n_UZM5{kISW;XCIXQS4jCR3Q4m`pUNGN{V?AT!|;9kO5Kl)ge!vYmIALgGvjN z3hv*z#rOW?V^(&qQy9gAan7wf_r!|X(~9%GJEYexqGk`sk2mPVF~hYH zlcPiS?o`y%b3SJt*DEKm;9NT6QNfY)AUbo6RgtZiT26c`qC+_}7$6}BO*7};m(=l~X z;37$;3KA-uN^n-v?RrYpB#r6zden8z_ zZ1CB#O{k>sbEi^Bv~cv}icYU|C#R=kUJ5EBg`1qAU5(KxYPf|GHFYtk$}?Ox$K`(T9_!FlxH_Y<2Ay=h9EkGZ zU2P4vwkY9+I;E0mt)1|UI7>S?1m(+tPz#aNUrai(F{JA8gy{4r%ur;&!tUf$BySaOQ z{wrDifL|vd?eWR(?o;3X;?w`lmF<;RN@He9Nj00!)=$>EMR+otLig#FYZwT|w*AQ*KH~(-f_Qt7#LI|p|B0rxHb-E9&@1AhvBJR&pe)g{C>{gu(Mu}i%H8&reGrDjQHaC${p{SXT&p}AyUKc48 zRhcuLOc}1Nk#;VDR-{S7o&A{?>(a_|^y32-Tq6+V2mGX5GBhD6vn`@di-IpBF6}T* zV>H7(_2|AM5paF0$82V~{LC|S6UCkVG4FkPjE;OGu07u;O(Wdu6~^;9Hn$|BRVtwn z)(2J=iA)rNh}a2M`ze{(;Lm>W0Y7@@HU>?pI*gAL|MD+BAdQ7Mo0go)b^gVlyv=ZB z!2SDs@V1B~?R76I){;6e zDaKPG72}k~(1;EAf1_@PxYt`G5n`#j(IQ}r+t^kdn)V77_q?HP1X?k|Wvr=5L>K!EqYY_G zE2aJ0YaV&pUKwUaECQ5fcT%(W_92m$el|)7bR@|t$D6m#e4uD7rm9h+gxiO6^3rfg z2u?D~ci-LjB8dT{s9i%T?E@EQ{o3C@IOBAZ(HZnW`F0yAB@-9(-SaSlRLTcYtth7xgf)n|pyx_@iQwVh zC*u9X1GKEr^%)|YGVFFKYeP8&ohT#;S}TmRWZ4`YDTLH55aL_oJazv5{vOUbwze*S zfU}chKRek3{VF7b0o;&k0k$-?O=}GK^o;t`H*o8lqMDX`?Mq+bnde^MPyh0V+&ip@ zN88BGz|ZIf20T&bvM@`52Mds?v9?Q@6v zW<2a+8|GAfYnAeIE5@`;Y@grrZTHBsA!iAI4N;F1zLinR1s(q*HmEsw$1e}%elF=~ zY;pT}&S8u#&!@B5>A3o3!}cq3{5k;%$FwS<_uhSL$DZ`ogtKdd^-Zo_zrl^2jx+TM zMcrh(kr)nAtgA7V!BjK9?PM&TyPDXiE-KMo*%ooyLkOG_LMSbX<3t>u75v|SbCb!L zbIwJ=g$hU$$GTAFYyg^Ok1U7;y>U=cMBD|X^)DqUi?Sg!tG_8Z8e>~@$fGI?huk2g zO__R;;afkr7|u^>g^G03{NRzss$_O_i~xo^8z2<3!z0T1oZr=m6w+B-T~VK(QJ$aB8I8PiJ$>l1 zqX(kfAJALBi0!SBxtJP7?KHYcKEkbRT0=~rPIS)UOhD${qqN1#1Nf%4zCop-F!RNx zwwgoxyoBe3H#P6yIiW5KdWq!vg)Q!$TcTAjP+4agDm&$=$1X9KDMw~XZoA0g8tBNk zriW+SXw670Z+x_magO7aXW2J~ekA$buUzBZPxiPwg|EMO4K*#ecWU_Aol}xiO?F(7 z_IgMm(6K_tin_Lx#<4btdEv&oS8bL&(jww7Du_V^O#y@#gTpzB+01KWL=nb1YGZwc zubFRR(eK`t$(#EX7TxD*aGMq1R43Z?jbEEBC;ZYOS;_}pXrHoPZCH1DsI6^^!vnOf zsgCxEoJI9Uer-01ISVZiv9vKhpNO==pNK`m6t2};LpjedWku3Wi4u(z5|ehQ$`WM_ zWl__+a1q%bc!wH>C{0}xYenX|{GWgJGj@j3>)tpxJU!?3o!cBg+{NXmtgWxp?e%>R zHWtDFvJLOGKoJ{-@&$23gLn!QNPpkTswOYb5rEd3x~@4oI$9u+ZHt>n*p0EwXVdmc ziQu&bA$hmW{qrdOyC2@-hp)a(r$1u-(u^P9wd`zfGd_I4AO#^~?i?$0)WfL669xoI zSWj_E2%f{<44;FLZQ{5bS2U{2?M4mv#D;T1%9gCxIf#>pwBJQY=?AE5M-()lvOI|7 z2@9rKkA6*7SwS{F=gLs=rRT5XtmE~YdmKz^kdmydf)K4grzR){Z@O#iC~AW<4ryGN z;|qv!5>Zz*6=BYywh#$wV-Zp#wWKcUR-?*VZ_|vm6nQ~8$*8AO(#u;UNrVZlFgo%G zwF?(7n&m|^I+ z1cH2i#y|PbzRhoc>t*--AHFKe%JR|s?{c>HDNjA|I4?Z^jN5y7U+mt$#|Jk*3FHil zvd9>Z&yYHzDhskKYX_yBb96dgHn+A>QX!Q>OX#FKjK@<>s-xD&yAbHg2CWBbW2x)9 zRa{S#n0$W9H(&fZSFSzA#qCv|e&RB({uu7(YsjPv7_WmOB{rLq9qmJ1fz+t}3h{6i zlq8KbCND9wX82uVjHdt|3_Hy8g2`;|H8mPxQzv}Il`uOhBT$|!K?;e|5mHB<8e95( zTh$Fin+Z7GvV|uAr!Jgx*c&bknTPFaLQl993zn=!5@4}-`=mmZ+$VQSMUp1KaXbRV zF1r$E4K65@gIKWnEqzYY`rahLGPE+bnrVc~dL;Q-u&v2Z{nScDNtE#^M=<(|W zBpj|%v!CC5y{wLgL`t){bEdh((&3y8Pve8G{-Uvw{JcF05m>wRY zgrK**i9<3!IHJrmhU=>c6;o9P7f`=R;rnu{ykvTGf=*M?)fM7SC!h<)56l@$o@E$o z>GU*798*^{b~>ReDynSm`Q)<+_TVn{@hxHUDUrBDk?pbbL=%X79;Ndo zSjD>^A5axJNgDIv{V6pdV})^!s?7O2UwVxH?w|fPpY4sgdHVtX{)g{!ROJXAfwR6> zSAf7%9oGgvd^q<(LZ?S6Ar^*SCkA6lBgN&dA!TvIrJWV-on$y2fsU!|B6tJPQgU!s z@U!>!xO!oTvGB7G56KEo$>?f{LqThJ19BTME2ShV($q7H%`2SL#8NLMdCQw@iCK!J zO48Ez4SKmuJ?)&u7~1F3qM%|CeE2OAXn5PTE84YOOGni05p8Z!9_$m@it6wHWesYu zhP9r$vq|_x(3Po^~?;UPPl+EDB+3qQL;s>$fu}<=Gka z*@;(Ik0PX*bLrv^*S7{3>s;JlWm;=4+`c6~e*Z0ospR3kPqD?hPudBrHLh;aS0R_E zYMX0n_IvZSSe~mP1a6`Ko2B^;{4lK_1Z|jX8qy38de{&k`TG@^%tHG}S(ZHeg)j2e zZ~YFp?(eg6=@L&r^E^B2L-NY&SL9j2M}PR2RP&Og+s9-%WtNk!ES$eF7L(UrBPNO3 zb!7v1V~oZ5Pz2fv3^deJ0^$4o!gVinI{nOw6|g!;`PwsE98XIk6~tznYi%ENcuVUj zii#>SgP?2w~Y(bC^d^R&p%jmKQ8d*_T z4-V1pPZ@lxiepp~d5x}SeJh8pOR6m6(#0L>s^W0>oNL=dzWn$mo5{=W@f$b9_kOs; z2OnN`Pu;jIp15{_ySF5F)-?|w>~eHAr#1$hAj{?yyZ2B^v=6zVg01U{@!2U-N{T$E z*XyB_Vm6z!`=_c(Ux5<>Q(I8sBA18@w2u6Iq3!U}i_fvOvBuHyA)noO$myg;cl)hf z#5qJZqdMA$y2OZxXt+T*XbeaK2Jf&ZTWjmuYbJm?K1mK$A=z+KErD0f zZ-+#nu4|vbs0F)a1Bk!^u%L;91TMU;10in$FCERa9CYh;grp7gh*1RS;gCLeSol~(6RO{L2-f;S~%kn z&ak()i_($U+F0k-$M1{bFqO}L;aQ}xNLvIxZ7HmEn5uF`J{Q(hnA!?kl@0a=!ucLa z0R|cRFh6&Q_Amc!+iF5<=$b!`2wAMvQXuV6LU`2AdV}daVV39dwhdanw9yE`rZtPQ zc7rtHz|_nS4^ht2-Pr-HnI0ZdXF0v~bqs>Z(FrO^>GV1X7DItfXk^+4tvpwE;NKV4 zwN$D)?Lb|7aWf@xS;n^?@A2RM{%>$H%X#g?yL|ZG2Ym9z8-bnoE#kUgU@D6tijcW z`FILK(jWHFkw=I+NrVeVHjWj>Iu6Gf-+tvu&Sp6u-aeq$>o6D&81~K(X@ctaJ-uZw zMM|&5GMna1Co|qYIOWd4452lZ^+C=8O?Iddgo+?=)?BRx;^7Ee8%$Lb_4=TrM`>;e z?j#s!*&tC(6+tYmYiQS+kMA7$G^3j3#Qlz+Bl%qNu|T#$WEbAAu02Jstqq;gz$fEr zk7RR;@^BwzDyrjSBB9Xz5w#V8S~VmeOFM4i62sdsB~xtz6!sYo;%+mS(fq$dXiaxx zqg@{jXdtY?Wb@FIFDZ(GzApH?UwxcsAG<)e+m$OLFB0~XH+sBvQS$ipYy2<&@_*&d z?Gu!WXePC610)DR<6nOnj`NnoEwz6v#0;D2A1%VySOP!q7FNVk)m2K>22srr=TcgU zb6!~O;^qp!`}L>!+n-Fher?FNzPQb>-*cT#EXuNA?|8-^b`5(IOEsB+bM%J;l<`OVnA$o&Q>S8Ti?3`6g|qm6^oHW7Nl={$>gvADPzo4NOWwbG z%1Sq)A9+^1=1NSc=rqI>KEV`pqL{i9ffP*h8t0%BE!uFJ022I?P)keRS`djqDX(bX zEGFSB#WeG}Q%X^ml}}cTZQJ8;22)#fq(X2fxI4=@p4F7rk@iv#mUI)WRMfR;+rR3n zMz(|_elWe6qe#*SJNLA|iB_D}hP%6ae0*n*WbHDeUW$=1?|u4E^!fugmje-xR;Xr@ z_xDcu?EZw+$1A78fQiE=NJ2&AHsbA1_qn$}WpMQxbuM`S&H?v#_c*RPTz^a=g~POo z^5^!LW5Lq2y#Jd3Fnn)}4a`^$(asHskkC1#a$#;#fQ~pj8DmX}txHZ%PZ*ybiBCU# zo1gvYd%XSLP2PUzUGcM(9_woZvHx(FqK4CnMTn>c>YTASVNog$w8y@ZV2tsMn9c$o zU{F!w*)y|@q9}0AcO?iQjw9lvi;g1lJR_TXnsHyv_>-WqLWR6dOn%AYscFz<6{H|as_zfKlw}lKRkY&fP}*;C4`hxh7C6@Eb}@?ONE@*bYe+ol!A-^1Fq)q zEXR>E7;SPgo^$c)4RQ6!FCkrqq;TFK3apE8A`y9ZKvfpt6wX$yBSd(^)CTu0I4PE* zpx`)#SQrr7Y|JJzZvv2opiXnNZyTIq(_iW5N@Z|FHUts=y&Ck!wsQc4&+uxq+1WW% z75$xUoQ}y34=5)S`kPx2cPVCbjFYI4^ekFvKx$1o9E4$QNnJURp3y}sPj9Cpg;YIi zQ)BVegF7S1*Pq+Ln2P5wM(+NzBmU>3_rzOo?UCph>nySMGwlPxH-|w`S zB9$OXV}ET8hj~>YtCG)d-{<}J-)CcW#Npu~|M**1>936WS3i9~WtA6=lA6l;GxOaX z4rAcy%R{d33^+WSV~k9mR9C5hTj)~%Ak*t9a(%U;D7GJjCH#ods ztZf=4npN+Uh<2k|3$8(w@ph`s!WPe}RbF3CWSS&fIFdBswb$R^tzW!`b#U?e(|rF& zukrLV&x*)p$Z|~OG}Y{o)zKv`UD_c|6q8v-RvodvwMMU-(oreGc9>)(b0YeKF4s1; zxpixwPwyS@((_k2n;Y(&@DxOI8xYojvCQ(CSKoO+ z+(|=w*P_ZLn(JyRoz4eDVY#(-xP9co5G<6>LlROOs>uu?CCRWy(?BGJKq_#dB4G(L zNlKDWy%q}rZB7!6a+Yj5N2f`k*!A-_I`)IxD%Nz<7^Nkq^2oE4f+*G=yr?|wtFN#u zg0i{_6%*lDTO0DAx4~=o_Q}c>o?qQzV{4r{8S&wXrJrl}^m9*fRmI}tdut4O9p=5e ztZeQGckg4It9(nCFyyv2QNE4kv)ecH5-iboJ{k0>ltu{ORhUE89VoFIgxv$Dkxe)=v4`@7t~caKj# z`IN)MBWCAkXkn4USIu;s(CMTM2Z>MQSpl07*naQ~-P~4{AHJu$vO1IA%Vd zEdue@2#7Y3x3BzJ+sVG8+Nc4E>ynv;5iX{6 znu~tyMj^f3@Y4A_3fjTm#sDc1P>3aiU}~>W?GSX6h^>_lhxLqfy~AK*gIk~6qnb?E zxVX)5WrZ7;Rv3?G+__UB>nYcFM&W%MoTE8Auvi2Vtszbv`$tD)S;5-ICYLU*QHq40 ze0V^C;QrnbfAQVF=E2@BM|=0gY?g6+v`-v3?uGEJ2vHJ|4*Qfu$VhsY6Y0^Yx+>Wi zrF{9hOH8IYrqUn62UUc1VUz{ADG8_!Je>~&*Q%`Vty+{4T z1+HISVOm^BJQNH zba&g|6aF48qeg8|8=hyJ#t0>elPJu!FVN3s{Wgw&85z})CLQ*Df*9%c&1-8>y*|nI z4&~uK(o|HZ$0QQuU=7opM4NLj%|Ead)3D@JSW5B{?O(U7c6c=eM9^q5f?h`R%d%5e8~#rWYl_4Jta)dBr}w{^Hcm=iML#2W@Y*F2VR z3l>!mKZn+!f=%n24@eqa13w?t02|HBOXy{8624|fi*W7ECtK~XsB@IWl%h*nRitKs zokpyVYgd(qa&APVD&{UF=|+6z#mn5g_W+fh=4lHNx<mFST%R#Zf-B#{#V`3}Nvwt3$$_!?Sr zq*j>RkoG&&#?p-(=Hvu5ofE4yDj~5-lO~$FwkRctw4|zRKyF>QMvKyZ*xs57i?3ic z!M-sLr92(`WM1;g{*1M&*HOa_wiFCjQhxE_E*lpvAv+^B*M<_QuyxMnYM)-GL+6<% zIG@ZpKA9k-LORF2`-fbZoi47Jqv9bS9-i{{tvkqS zOr6I#y^2m9buq!_IWmp`jU&tzhDzq@+PbfTosWs)gthe{lk+jSoTA9NfB!DFt`S1g z9}KY8FrCfA=~7rEqE;3ucnd{)*Z(CWg!gCTKc^nE{Azz(}KYh z7_fEIs_k%2D6O28LfFdTqyt-_rNg>KMNx`IN##+4E5xITfs~6~)U<9%(b!Yl4#Ky# zIymAcu4z~STR+|y!!S!GWne%H_PcFoZ_mU3N~0a(=i!my28o{&Sz8NOptUtL}||tft!+i zHX+aEI9nm9An1lPhX)c%mrsrvKm1IL@12vIROsx48&5vX#^tNL^YO0N0Z~n0Vo^~7 zQR)MtKq)Cj)5Grq^X7tTQUt5A7$6V9zB6I)JWvJ$(uo#{UxE_a6P7~y_XO&)B0Ha; z;+VCSKEL_GHiK00q0D*g(kd6WR{1v%?lIcA#FxJGB)fZOJh2fWSNlBEO*#DR176tN zVYTnY2W{Z(Zz%HGfo>UbdS3I^*~jEo^VRFuD9Negh(TnTqxr>d$)|txW6sad8ILDa zXZKl)X7m#6&zqn?UuKl2_sR1kTz3QF9!e{cexKP~@cyk6oDh6)>yVv|A)|i62e(hX z)ACUY&5*PUNTdSnY|8xP6eWEL)mYaWxJJwhsc8DXjq`|^aHeI@u+~spLq|F6^q7MO z1!rg5ZanC6a6IO_-}`HJo!I%3y8IKl_a*`Rda<{M$dD zvbR_A&U^c;#Ey;a4V22}t-}ol~;U^#S+DG?@(hko(vBA?Koyu169E2cacr2~`rF)h#<66ZgBQByKem+QcIS zXv^qvQ#lY)_`)C%r4dmlS|D^`tv1dRSg=&t`?B;BM%$eJZCgr6}|-9FKVqdGc3 z*_z_yh!}|+j26`xv1oN{Kd(W_md>GBD`M$uubESj^m^zdZk_5fa@QnGPDSYT4PxPY z`a9j2FF$#Oetp8zPd(|bT)QD0g7@Bem$%=1gVj-=AN}BaoE+?;;v}?GxIjG{5(CjN zUfD(4Tl0LD6OHDcg@2nFo8=_4`L{s>mwjek*I|ahf3_3?D_mga^7kss=X~w!-{8Oe zXMf;+^y;fzzj9f8{Ttt4Yi%S-V>viFb}QXT@W(&lhj$BZ?oYV3(qY}gZ$9-LMK!69~g9W50( z0sU=E9j8p&^RyjYPVx6NjivG?;M1SD-o2i+f zo{*iM`6ND$5lXeb3<0X!MfHXl^a53O4lNvcmZ72;rM>dD*S!jNH7~GLMbhmqq0&CM zEheW_rw7DZF)uTozj4J~x$vBL{k2y)IJ6jH$m^2T)m654u5f;SN|Bx8a2Qjeb%H<; zCkg$2pOwLYX_nFJ^)S{@7CDiQ=ybd7-dfw-@-**92TZ3EoU`aCB1seW_jVCNva+%Y z0<07C`UB?kDaIJIfce=z_wS}i)!{e4{spc)_6+~;_g)iuc8;y)q904fr9<>q(JPzO z2&A(Cpa}cd`9#+Rpu#q5vDx2Jfvsuv%%mcUqc#v<#O4yD#yFrhzQsyN;e>S7I$@o4 z)>@&2U3duR!PchR!UH0Hmv~#Y5FKpns}KwDwbA(yA~0_STiPThtsc;FyO$u$3;BK8 z5dMgej5I*Wayw}wG}?X!gceNU8BmuJxz;0!C5N%xO&?yg=&leb&s)r|>hbFYBpgwq zOl@Rc8?YurOHGwena$5hyCc+Km9i|!aik7ZUZHh_BqL2FFTV6LkKMS8aFr8csXsiF z2Fv*&U3uuPbkBHcGZUpPnb$K0GtH(LB93>N&dRpz?{Fxc(pld`b$d$zt^*WKSfmYE zG=VuHR5(1xeAwz$Np?1-&U199Lw94-Gt4yo=Pe2f#tRyuB8}F5khl@)62f!DZwwPw zdJ*6M>1WI*=Y0989X9%!7oWMr>RO-8VamH7jF}`gzyFQLIp`ixZ#~KOTGvtTI%kYP z3X~GmmBX4EA-tfGOd_~;MXYrMcOM?`_^M-Y@dp3{N$syEDo;$<7PAF$0wwNKAqJOLPyjMq8hXha19b_(Q<*HIO~wsbMBa6q~rM^vwI)2 z_wWGvKn1^;KRW$XM3LrnJmKWzjO6ekYWosGBuKaDZ=Hk4~dSwE|ivLG!cE zB{R!kG}VVkk#@o!X{sL{S!y(E?2JRJ_hyE}w@x}^7S41j0cl$lliB2iUU$SdUw(!f=|1@2Bhj_m?e89n z;l>W%{?_xH&q_|`72Qt4sFyNLW3FA=;KNV%7@v$$D)RGO*82EVdQe71nob%B6q<4- zv`jqBbMutlVPy$g;l;(w*rE!zm{(d_|56giaw+jx;Jpq!fDw}TX5XtgLMw@_D#Uz- zt>)ka+nWP6MjgJ~iNSiErl+=heEML_1|_VYuMr`@ z6O!p+(&;Q|X@WU_d z5O+rW^rx@#+0765#w#!Ll`p-_yYIfu{@w$A__wdJe{f2qBZT$?{j;fOh3j^D7~`49 zz=Ku8{s18*aTHV4hO#Uf4F}{!MqO5Dp-@uctYtQzqP3*k8?*^jb1Z$`U7}h$4-s3$lC+#-MEpwxX(P>cA~s zTd1sey2Gw?FFyYyD;qn))^jJQ9;tpbS+uD$H=WI#vpHAReB0Kfl;XA9xB2K{No6#v zy&ju8JM;#9q!4^~^FI0h15bM^9A#Ni)eaZtP|`+;7l~KG4gK08%y_gF22B)cs`(5% zOVO(-#)+1NqCqzE*_=8r{lKnL{_F$wZfDf@ZD9D}usBV)vUQP8qWN_9lxH8`25U$n zNm=IDQV><=nE5d~TN`w`G1L8fw#=qd>W+{dh15-qViD33$C}Q{3RkWe9v&R<(R*+5 zd(S*aKT%|p8Cl^-2ScJb#?&>++JKS-HXCcfI;y(nn=e1lKmITND~vVn<>#K@sT-HY zzy9;rdFNmJ6_pi8rBPZ?+c4AM9u15eVK4B5sAL(l<5N1r9^H*KOjS{w9JlQ*0udU? zeCv?4P>B${g^G_85@9N|$#Heg?C2I&Zz2S54gGHW^9F%$UfUp8Dgi9NqY+d2acR%9Y_dnw9?c1CkACmTl^acaK?*YO&Hpw8N+US{$7PAR00akF( za;Y`J*ZCHLUkxhx$WsqhlCm;XWfiD37kUR$h9IVK-p&!nF>k&1F+cw4&(TrL^=Bsh z>8qcyy}f}nbJECHXFqsYlhvDygryg+a2`cW$0zg>iK}z425Sncd`#sM;>7={%9^*{ zz0I|2I}~}&>mNMe!D@$(Klp^zLCW6#G0xc~m1ch-&6*HGphB`;&S#YK8E8#B93fTI zGJq|&o;1~~BFm|=oTT3+>BNim`DkgQWz%Zb0k9-i=7Sq01odo!ElX6lgY5P^0g41w z%sG4bkZLv~UFo5-0K5mkncW6#j#jBk%BON{YJ-?L9$q2KK?&kCG?2lpOQ z6$Mu|I_ORhjAc5{c;@N~y-v)VpB}T)PZ)M1ZttD*!eeWsk>&?KzsJ$Z9EroqFq;DO~r(&_dQQX#A(Nfc#LV(lq; zmQ$5Av2w_IPA`Hu(YPw3%rbP8P{$*Z;Ra6lp?*KQC0bf{2*Az~p-4MG?HYRvPAZVT z`dwMS);*7k@F3<=2~P@dysQ({*19l1*!FA+=@Ui~;uIHlpbOQ~MH(JnFGQPUET%C0 zch)vT`wQE&m^*9qNt$_%_D#aqOZ&5_?k;(UP!DYZwdQBw?VfGb-ycEc+Ih!iyT&Ox zmV-APX+#YBXE_h{&-mu^+ngO8addD%sd~Kj`bV4|pK<-MOB^0en2!{n-TI7TI-z_0 zDndGhj6CuZ;!UNSHn31BmoZV&V|~+?BtN@zmwR{bI;y##Hk4UKlvYUPgH)`+)ZTbE zRbizRk=7jUe#S>X{d4-ggrm-wODhuPa;MEqfT2*ndf`zD|EI`Gs(DV_?~-)=5UN%Z zJDV~6|JZx8XIZZ6%HfO`QD06~f*I7l4Cmee72tJMy>)e-Iv+hK z7aY{B%FN2z!}`|xzHc2J6EtI*%M0i{XLN9cNmG=su(*Z1Y_VG}(AFAMDGFR{1zg@- z;PK8erzcZ{NhxxTDfe~Kr5f-RzeF)b&m+j_s@^-dGKJ3AsJ6e`vbyelh$&VK(3OXoFH{U*6ZP0P@Tov z{ivSL<(!^tD}?|j6fO$FR*do#Q5?DNB5?t1Sy`wkXmv$p{=7IV+;nh;4h>TpoMj=& zB*0sJmZhg+&ZZuV>(@9xJ;In2<+(FdSi#z|vMC(D-?mn9ruWD>2Z}9N^yIjA1RlM-R zi=@&Q-Nh~+Jl^5qk8UHqfX3Py+lTv@enRhL!25T$=qxOh?ryFEE0uIrWGo6xK*6xr zC+QFILmx98Go6fRZERAgpmd;e8CF|XMZk?+t*eY^wZ6^tFSF)l6+m`5{rWWnwxrh< z;}Pl65lUE!(ZIQ;c|J-S#s`N4Rui_H|#g0-@daMGC@Lk&IKPh4MXu$S0j-bx`F8PROei#J;4D!3zUC-$P4}-pPQLPI&tI z8V|Pi*;rfWq}ONj;xcDbOA#*8?k>>l4Om)iaj<{L=Gq3s;eeaBp5gHL9AhPgg}aBR z_)!ayrxg8DY@RY4=ZGNS;)P|t_2N2%<9&{cb4Jsg$ET0kys*xTs}{q6IPj415;6>s zLh{1Z4hyZ2^@SG4r$at@+~YIXRzMi%rYNhNxWE>!QXRCr6jCrq$H*Y!lLuS;_-Ai( z_rv$OfA16Sd~}bU-F;qb#k3oNJs*rjQYaEF2%;Dv9c68y+ja9@cd%HRjRt}5F&+*G z0>#?u2FeqR#}kkq?M|08nXJYZt?-fEwYlW<(Vbx_Sx_4ELb^A;O0A^rBmh-FX zG30bwdM+{GVza9FBFZ)2RVXW}Q&o+a?Gwh%8V=UqOTbJhUoZRhzgJ*w-Zivd%;)c& zS#_nNcUEt6tAOTL_4qXaDG$|T5(<$^G+rQSwmW1+L7rPeKfv?6(pk!aaV6?pKoG=2 zDrL1U$_)6Eh_(uPlv3j2#S8W;UpP0%XSon66jKw6;iH0r08c2!qlDL9e}~6AM|}3P z&k%Tk&PbD-R=dF;eCuU|6r3C%^N(J6ik}3QH-B*(t19GOjeLo)1}i;BGs!X#5-)BM zwptWrra+XLOo0v7|EOW&$z#P&dJs`&4x$3vcc|dpL8(f zX!sZvD8j(ALJE=PMVb8)Se+PS3Ph0$ql8dO30qoYy2YnJ>l9t&E@Njc+E}5B3_tQ| zs3yYmNiu^nIYJlZBH`{*h|&}w@Okg!$Nb{X9___tarJw*dEuqoB;mS9vI5;d!(Uz_ zwXR2l6b?J&X+}D6B11ne`QMWXj4_7kSsx)4t&5jj!zCrLH~>G3O^(61Nyh1-PuWE^@3Xa82Y4#;Urvfj|() z0oHnWfzO$h{QK7*^UUKBkIy3RZcBQjRUY2k5~GuSqQHumo@>EUY7Hmihqu2Y-u>W1 zu0Qu84e7CWGR68n2#XyQnEeE$TsCz7ctnpZOuUfd>FmSnvnRFP4fp5P(y+Fdl1R*W<8ID)zZxz?IwGC?N^D)jMu*NCffd960r zU!rd@t6J1Sfw43K#XtLV zUcKQmw}DsAZ$ip42q=Z|IBGy0AkSs!YJRe)fSmK~s=_uGTvy!a(zKy2tCX9$abbvS zq~^BSB+IyQWt0E$U;iOLeEp|fSYPAYU;hf7R)gG1_K(l-ZOWhjt)?#|PhDK*xZmSM zE^}{sfl(SEHZMA=RNUrc6nAv0|vbbN=F=z zrX-VN;dzQM^zl7~A4I5flArcY$nzZ6uf|ogtB&?U2$C!#FlDv2q|0SRfzfUbDNiw- zjFCXAv*0TII>%FrEKL~>hZt?}J)hRf6?C}5yB}}y<6qonnkgp6BWy1aEUcrIKg+O} zb2AJ>q*NqHiZ)K1Z82pBaZ&e8s_xef$M$q3rZ6RMof-j1@v# z@T9O=VZ=1aFvbW`+TKM30Er9wTk9!C|} zFg2xjhEU4$nkTO<=lY_}07jWG5_7;qRIsaBKke+THApKf<)!|{jYS8Zo;0lg)jEC+ zK+2=7*3+K!5>eI+b&=u$vF{^HN}eTneuOm{aTvNLLRNF$KPOFdA%q83TEwT&tabKt z+FM#i}Q}`KJkGl_dxpCtPw{Bhop}2c*+lly$;qt|Gmby*; z-GBT$wjS^D&;Q9+c>3xlZ@&d;mJP>3M(P-@V$sm!>8Mb7@VEaJLsWw zhET2#hO~y9oGi;}E?pp8`V2#VncLFi{Ws2tf)UN`BBy5~5Q2DRl~gE<5l9R{93wp+ zKlJg0#ZHEdPEHA04H_#e=saU`bb|7H;4#TvA&?HjG6}Nuf2D7b8vv6W;jb zm}j0^A&3L~R1z(h^2nwW)}Q|}o7XO|dzLv`it=inDyq~GNCCbNC1==_ z?la}ErlR`H3zpq)S(d+HE<^4x7-1VR$F z8rV2;;G^99^qe@m4m9VfJkH zyW99)>4`5vSXp<8t}I)tgvqC?Q?<3Mn29|d2vTJLrIAX_Xm|6}Hz>c8helI-g_i)w zQ&q4~LPZNv6msYN_xRub*Z+mlc*4aiPjTnnpL6ThEwnbAoVa<_KR;ut+APP{xq0(B zKG`~Aab=m6$XXvQgclHm0aNR9ni$@>e~2=gRx{xFo0qu#$sV1>F5W_uY%EyYY;(MK z$nL}aIeMO{K~e?i$CC-Ul{8j2F)Cm*7}D?q;*E<;_jj1??-FfnLez9lH+F`gm8a%< zd$_=+?!jKI$>sZzFnH)dlT#fkoYp3)c-{H0IBy8Wk$B(85^m-=*K|mD6 z?Ck9`J$cB%_7<;yZ_1;sJ^sR+v9rC+!qO@SCj*+(5z&#R-~x3A_8JtS`4ol8gaPUl@go!6Zi; zfl@p{y%Nf$(xtW7G)0%dJTC-~_f8oPha|%cVSV!C9IF#Y#}kswNIYhs(i(%1ibm{F z=mIGfVHlF-Icb`d%ebo?>Y@Ot(AqE_4pB;AjI1l9qtVb&C#Asi1F|&XC z9+OOlZ13)Ke0ak0`X9 zN}kM3oSIr{OWvq4m7$2O*IqeSPMJ}GD_x*VfYfe;bCmPhm1dQnd7VdXeo(J@C4eXa z7<^Ako#zxUq;SB4}W| z2!SLk48BkZYY9AIh4LN0cn*A2-qqC@RZ5A=7dPxzzj(`@oFy0|MImF}+!mx-VNiVj zI>cA}{#;&tK(#`X`^`(Qc2AA0N;^f0^(9_5Z`i@4w~5klJ+)Z-x=^ z;xbc~P*D@vT_HKyM@};qR~9+%ouaVBs~b$qx>XSS1aW|p0wzO}lOBGfNn?2#Q{;>f z4xNB>aRIA5j43nm)-A43Wkp<;(-VT--k2Y}v(2ri7P)qLg**2Sxv&uNuYd0)j&^tX z&Y#`q?C~~Mx-QaEx@K>AI;F@nL|hIiQB@n3%<8*U_f`wgtACS{sf_uXpWUa;RA?+wBc?x2xO=xp|L}x-^byO8E!yoy zUCF3+w(7Z7Vsu-z@D?R?u>vOLW5&)z>a_(W<>p^kO57zXYh)<|Vcu!m4SQ-4aY7%+|#jt=&iPR?0eTw)-W7>o)IPA7bLcZaR*9XfJM zoS%qczYktS&|N2MUa(i6xgkbbfzArnR$815#$3I!%GbX53?J_FIXuj`eyPLrmlyd@ z`^Q*al+liu16Bst{aMg#cgT&!3QcRVi}XFLr)XZd%y@sB>ES-j3zsk|aPvTjIj}ve z4$XepdI_egm^|?utEW`9fdcS59k2qOr}%zAkxa?+g4|fb(l)TMU)t)gK)p1RVV24Wy8qoDNXRL+jjW2c_hw zcZQIXlXvc*l;Vd!d7EaV#a{0*d79ExlJU-mNV&l2fg)%nc%3D}Fhu7mOY0jvy7z#; z`|&&UkG5IZyhgOT!QJg+dLvC|^%4fjTOS{CbUx+bae^o^$TJ4h0>9bBO3!8PtxKdy zAsNUG`RCZ(J7h2% za@y;;HL%no#Bod`3Mq8%Fn`(A-e`lB;CVi}a5|6Sc+BGBGObpNBF{?gltgQ{#wOD- z$441iR*>g;+4Ry;s-id|&xSm`agA^N<{xl%qf299h5ze69;1989}iok=)6FB0oH&K z&c?sfipVQ}y1IE|sd^}@u)Z%Tw5^-TI`E(o*0R2~40#JF3}G0u^LUpmEx-z*FeLJv zj!8&o27?A`9PQip6=lAzo*%|qtgvN8WzHVBT#rQw1}f8>iau(~#GEPDY*qeS-CwD$ z%9jRLwymDF(SakUrJqW;;kTmQeW zDrUp4=J9I)QXX0E6al83Jbvg(_C{-vK2j%fLrYI;%7n7jTBwSi$aB@f+h`S5qTC*7BNI&4CM@O{6 zMf=`|TjKqDQz3=+Jr9%;1|+&L6~(j^v%>L7pVRY%)y>QJ?R8%N#cjGvmxxY12Gc2* zyPmyyu_G3I&E;0YhaVsEQ|Sx=9N=>ciq$z-mu)e|qJo&l`enw)C+KlP)b4P8a!QzK z)bcups=F%W!y(h7Bf?gjaCw;|El7_K5Y`Z{ZBVF?B6EJENd#B{dn4-waEVL^h8-sHOGda>Y8kVt6B(DujM`Lte5VxCz zk&e=wsH!Mb?-#XZ>z9xE9;?pYxSj%D6ccv4 z79A#Z z+6`_!{WNFejE9f5c<;UU>Bb&Ed;NQy9BdQEag}Iy^SAuIwR4jYnJ}C|@o%xb<%4c7Ek^lC;`ycGv zAAHDCw=KT>#m}*_vT75JI5_RoZAAQ^fAub}eRxFJY@qvNE-VGyXck;pxXkur&BDqB zGSy&fEJa}izVETnig>is zM@mWZJSUJ)OcM}IWDsGcPvgQR#(TR=_jZUkFJQdL(OXNfSyhlMGyPX3(5;*VXS;)_ zFt8iz74P0!tQ7c*uEV>~1?KdO>1d3In#jc^2m?ax0HrXNIFNK>kMp4*P?E!wbBuLV z;G0*LIUOG|8cfO3f@UDOdU27jd}fpJU_d_~6O0ZyKN!$nT;c*vvXcox6mj#J=h(i# zP49e6+bd|OgzR*W-gt{v>>-47nSKe+$a5#+_moGj3p}Mt zL3U1V4eidN4g6IxN-e%9NKOw))tDE){0a|0T;dmRJwRj=o_q0mf-vOgcaIns5x@J@ zFR|EZ(TPvFe(4eiry~Xf=^P5DBVN9`iXV7<^yq|JSC*J&IUn3RD)%{w&U2>y0T5^hI90wrZD`m&D)v?ceZ=pDpsz3(xbdZ+wII-g}q5!xR4Bzx_T3 zhbMTRN1o*j2LrTjk|YUIN}?!aJQ}*W;wg$EV{mrL`uZx1%S#l6APljk{}viQoQyST`7GU5FElxC}mE<#>;={jF|tQVquMY9nz&W98TQRzbjSgVbgr$x=20m~}FJYt8s%3`oo6w<1RU%g&h z`-EYMv6Wk2S*;M%z{P!}To`LGFkAa(Iknk7BZLDwRRTelPGvRRm|IIlwE>jpnNR45 z5-?RcAO#q!KefUAY8}4@AmuSlrdSM>m#UPMy$A$G1{e!PHpUN|Ga)(?emKlvQK6rG-!Re6o)h;`SXPgZ+ zezS|#ntlS`|M`8+PR}U{gEd8IbLfHe8Ba5$7gE#{&DMdE(FR?(NosXYnr3d(En^8| zoEThK(B&jovdj`m$dWPP+9m`|#)Fh(IL2=^5T1wMUBVZF!O0OZ0>9P9Z%7tbm-(dE zXEf4G#7&B9B*x<@+6g(Owl2`C?hye>NeWVm7EI(aYz$`1%v*3kVPH!dv`-&kWj zN{AMk;D?U-q6>{5)jK&$g{)8-Zy<+^(cNu&m z>p-&+`FNg0cER@t97-mrZF#HrSMROL=hf@;!T#L2 zD*!_^{+NLYaLa&F)zf$LV-{T6+4ZTib@S(P-#u)`_;FY|FWI_H%q&k~Ynt7B)k15F zkZ^5tk;~1t?L;0|*Q6MaH7mwP3|cHLEb!r5K8JNhrrPmb1c*!f)Xf8J{>X^nshWEYqU{KpT$m-VGzJnlO{P=F0SxfuLv%# zwHXa3EX0c6`s@_~1%LD1hh?&(q`pb%);m!K4^oon1=;z4u+gL#jL4=5G92J-ZeW83 zsDSo`i%j=+81L^BZ(hWz5MyRZj*8A!HG!?3Q&qjI0E#Hr=lYkhl`~cez-wxjB3xM^ zT3*7q?r=^B4_GS@O0m~Z*?)73#dd?`PKYfmTib^y-(%~r!<|PxXWKna$rHG=&|!aX zpOd{kZa%fn)pp2RfBlyl(@ z^;dtz-TMzqO=MYJoBO)PXs3fK$CBr{z7bNpo(!&IwRJrvq(DeTp>w|R`Dgj+*T2bs z_?tI)`@>yw4Mo%A!GkT9qk^x$e1)a9N0yA3jLulP&|s^tI6CcfvCzD5eU;ny4(XjG zT)(_TyA{KOBUTpzvNY!_FKi%<1{JV(6tZ_bs{1)e<&z~jl(sB+mU4Qs&+zE3*u6jE zqj!JC$G1PgOwUQq_w1vG_cvwq&Y%HNKuLDAP8HoL|ffM-7yX- zFTA?EX@wK)Rc==nD#5Ae1Pw?)8-vcKkfx+Z2ZU=Iu6dQQc%|3B1*iYWHG|_*nj0}E z*5~^_`H*HK<|Ok(AOz2BZm_m2IXxdS8jWa#KAmPnInzN{#^Z?{kEddNbB#RgaR1?WHsXEHj+^8|j}p}Ts4t)T)vCxF(L zLU>%gd6h5S>~g$+$UrBgCwGtv@+1LcSy+Dx*;!#@V}-P^PQS6N+O=l6g6^Zetly~yTrhxOJs+1uYop?Ustm!I9<;bc^>hhVAc(}@JnY_{3& zJF7`+EtpCxROuHg8%I~}Hl`$%Q~?)d;BE~%*QDbq)`AxX&aJA>9(@XY2vKJ6%d8c% z;Cw!KpBK2h4Asn)#FPQ=6VqT0bX4@4*)~N@mzb|eXaiP*@JjGro%d7sRGp(J3ev>s zvHUPVDVKdT^Y5+hp$10oW~#2e0=MybLU4RCpeq8gb$G_B?>^+?yAQa3{{d-MAau&{ z_BNsCIkSTD3pv*tRT>yn6*=lgg|ov^kLt#j6)>@S_8dyly%VKcOkqoErY$q@0xM?p zE4THFQgdTV`l|bWo)p~v_&)Fd@BaqtwT1N?eD~dBR+bk8#h7-pg_S=0BgIl^NwWWZo z8y&W`jw;MVMGZ4Tm19K^MiE9Ra;?FO=v-bQ9rPLR?GmqVLfk|vpJ?+E;{rRII~Bli!+iFe&&KlXZ(E`jDV%V*(gsy;DvV|SEM>9b zvHj=_Z8U8KAAhvX+H#Yjjo3MvaACED?@4w~CL9bk>kXeTfA$7nxZdULXb)A45Yuy> zztZKwCn5JAkC-H>vz-qE$YA%;U5ehvoE#n0RUIYWdY9#S3Ccw|jw*_ZCC@V|M>d3; zQg7Fq$le!|%>;l=9_zVvA}BLd~9oL0DsO}x z|HTIgJ7s@whd1APm+hT>hJ$l<4to6Et3MM-lDUS5e#FAka@kPV^~DLJh$!&TT9*bC zu9;9#

    `!DyDh9QRv-Qy`A|~HOn!MAkf9b#lqS?+qOEXtiha9qyr*N6=hkbo(K9sY1zAzw z;qSC;izNm(I(4(;v&*!77t7L9=Wi&|7=GVnOH2$Y ze_z{Vx=jrzhdSomx$kzJHV^K!%3~x=zelIC`tGcBA&EgN6MLvX3_oQp>CcOR1kG06 z!v{{8?@Wym?KEXw_Fb&aGUHGZceWkYn!TBi&+s7)7`*jmma`2eT^HW^Ud-4%q{d;) zat4G6m35!uBj!e=sgFxG^!;tFUNp61avpw431S1uP`Vra5gb4sF=9W_CLDA41rHs~ zO&5gh7P=j&Q}?Hw2q>+Nx?WC6n>rHpX_ClXx9N+K$Zz51*;Q!@uv0TUG6n^-_Pvet z*<c$IZNr&gwgen2A_A~3(`5)^gh%k9p=6R#~tsZO7(N>CZK?;b{ zrr7agDOwiBda`BuaSJBE~{bRrdirBJ;+Lvu8~_2MJ1{vi}s zZR2(qB$ii(ON|3q$(Cg)Y5{~qL~7=8-WVK(dsJ?rSd_*=$P zwBJGNU)%cZGY#}0a&)*+#W0srwcpf2rYHz+kvMuC!`DrDJMRuitdtv9vPXyS@~h!R24KRIEpA}|Btsm}ka?w~jmT|VNUbr{F#3!38qz-1-N=a;Jr zh(M{mJv4ce>izjP|DwuvM(frr0t>sq%uK*oEZ^Hv4W_ywl0;{~ z7+d&S-22Ub;4$U6?(hHRBjc=TvDG{f$8CARpC#nSn8P{3RW#IyU_%KfN}Ts%YQP)Btc6sHyz4x7vgG4Af>w&hTAe-QdsxL`A4IBi=G2ZXP{b-nLWocj(ReS+Sd z6`^5Kf@8|d^G}G21QDmpAo8jl#n2T#9R@*;V=&uzOCpKBgb+ZKVxl8WLl9*uAT*0X z0Syu^lwrh}C}8#GuRKEEfN>;Ky~Qso8t6dlvs7VW@`Q)BcSlX<9W(H3JbCi+6>+rx*^9G`8= zrKjXdA2QKBq$z=uAED3@Wz~6y$K4p=L{I(24nM1R_9R{aaCJ9s>#! z=&`ReiQ`)R`$i+=Or9rC|61m}y2DyfE~SYM@YBVoWGJqnF%*?gnvd64{`kFOk67Sy zG{9o0q%WMH(`mkeu5CEC=5;!9n$D@v2b*aW_c4LAvt#%FvHshQ3U+_9TjQ@cK||BeX))jUtRZQaFwa3lO>x z%;Z(HF4+($A}alc6>CjoC7lfw?VEuZ*B$yc2d6?Fmdz1@Dt`|82#@}arDA;%wZnN2 z3?Il9-JV$!y?edb&^7#;(|D09Txk7oX!B7|Rx%~*GTo`NDd4yuUX*#Lw*wAtH$1*d zr=6dC;#B*N%w`4s2$AQrEe~Hbkt-kN6DN|`@;LEc-Q$EzbyB{0rBIt z@*-t7laUbcU#oqC&&`;!xb3R>4X0GyrX+sqRFfDrx1aTzzAJsCcUDb_S$~PZ>0x!V z>uQyN$kSY%ER$>#AYnR#>cdpUuo~B#jfFfz=>J@l1{3r#^dq@1DFAsoF>)J<%!dIl zQ>?zfVPs990a<;&a$kp>l17Rk-sba%xh=CD_Z|199Azf1BEYzTr;knKl6mb1%QgL} z&+I>jfUO-1c_)Krdb%35WV9X$Jc%z`xd8$Gyd1wzob{FO;lPBZ?gy3h0HMeVD)8$; zVsA-wS+x0^pfmhd`!=3fy4rGTfmldMVM9T)m#gA}*;L1$;~l#7*LApcr0>Xx_1}$g zkfo%alo4OVZ4?*XwTzaW>q_P*FHej<_a)rN$HIZ-RDrGG1cGF%t7F$yb<@a!S;PVu zfKcqs_%DS$46uckAR)Fy^dGS%7Jx3@$E0|O7B;LCXpZ)T7-lYc$OISUOl{-E4_B+g zKR}GO6Nl+}w)%#R#Y*_cTjOb9X>A_wpd z5Bbr6^#46GCEaD_=bRqtrHlaG|2cy}5bc_)?l}M4;5pNEM-QBQL;o>t7)o-oTAkDP znmQs;zN>c;R*29uf8z?ob06 z`KoQjQTv7*_a^~+dbS!A4qo2W8L{yxt+-!U`pO_&Vq+_1 zf!1xZ1NU8rmsq)^@lAt}0}(kmVHeF>OwR0s1SRsv)%FOW`zDOre3F9Mv^Zg5j3CfG z9|?GBYdfLmfmoy0=mn_ix^P%kybd*~e~ot=t^6TOh2gZTUUOjyzrf8VMcTEWgRWl8 z%>aD*+T!g$RaXDW9$eb|x~JmRJo&TQhBOVAuVF2=t{0%hi)n9s6#24;ESZTx3<6i) zYE0Gfq#@)xZhGgnTbf8t?B(?=y8cJVlT7R&)m*~874L<4|4hyOA8HhR#fmLLkc8l8 zyG7_4>^XP4L<0X-BKkP8Y#oO+l3S*xaas#I-E)Puqw-~~Tvsn_*zP9UR{0_*2cw^amOVltP{OjhmSK zgfBxu&7G7gm_HZ>MvBnH7&!=5j1V_dM2-ng0n1duDt(u*0NG@)jutK1PB9D=e2M@9 z#E@ZnS*5w9g0MivHbhx%+itk;M3`Z&;4h!?l4lc_EFc_a*FyTApPDHGn){EM1UhsD zB4IzPKgiz57MgQ=4pl8JE+{Ekw^Y5&o{#{>8;Q{dnu_x5pCSj77K-RB8vW-^DnQ#$ z(*E+6eC!aujuUgIrP@BX!-@8t;|jgCIJAf0e$#PtLi0k3^?;e|AN7ns7$D!wjGV-v zTSMi0M4CCE^SuJ-B^U;yoS%=MR(q>0_u~dta*U>uIHQzbsFg@U34r3Y{=05)om%E%jlt$aW>B zDX}asip7DWNsLErnB2a)>*w5!R;V|l02VF4(pn_al`Gcl>szDc-E>_l+4 zi_RX@9#$wbZ0~j8#AAe?5^{~!jIw3SRM&o)K&8pGT zOx4oDv(q>Py*b}cdhyzSJFG%)AsXwNZ>Z!yEq0e1B*g0J4pRGoOfwE6l^DmZS*wTE zTFHqH1qtG6maxian|9kg;bMxkJI{!PED$QeZv+O)C$zb5%npddz2Y}|e0Sbk)IX0J z$Y+w>;qS5M{gyrX%Aogs=NjkU!Km{rb|P!tbL=m|4R1#a$2}s-5H@UUoB#%ppWyEA zq58KJ2HY~ndm5dFM?#~j3r~9;TzCXEvIZIJP3{Ch!-n02pne`i0JbDrMtMvSz)H+I zq_#Szq_`?^O(Bi>&`n5LyjS!OitO1%2^?F};`&9%^oF82s^ENrgv5;~h?p1g@ek`B zwC0jrw{!huO-p!xi=lYRFPrSX1k#HvVl01eDB7R^7XiYgFhYXr{;k&ZHrF8y2xfMSIO8_279!jU_ z@dmLlkVVFji3AKERi#)Iav>bqN@kFN`}zR@-UgztgLbT~-_l%QNPl%&7q|9?O%&x7y*OKixII_h)=2yYKH25&KXI)@|zrzdgNB zyzjGAcfh#Nk0;%4tYo7+!{oKJ5CH*CbGh&THZC;g7d^I;}Z01~}#8npAGoW$tij5O%``)RNLkP>M9?fQhsr0KcU_~SsKPi?IM|LTo|q1PJ0 znRonEkPphj{8Rz@hU%k95vfBuij(<~Zs-3jr1HxCBlU12*%;NAl@y8gxkkx23L6}; zu)x3h$Of%$#8$9>g%+LKc@l1hiN_9w^CKVRYdU*M1GJ1bU!U(7)au&iALnvkUz{-C z_s^Xap@nb#4%-3D^H&#LNv6G`b2MSZpr%Rkex1!NmCgU0Y4_N#_@NlP&)Z~K<4|p8 zGr1^Y3;<3rJiXoTtuZko1qNSjIF!4i2Ii~~C!}U*pZp`|az42Syv*C|(zxIQbyZI) z5dJ++Vkr4OC88)eK@|W;b^ZBM+LT$6EJlRpySp@qE<29L{NqbU?*mLEe61P0FnDmN=; zSBKO-#-T)}RfZk!u1h%<8+FQ!7f_7GfK!`IPIEhb)+6h+hRC&1ym2VubQ)iKz|laO zz}ez2|KDYqXW%OS55s`T>jxa}KxiLYL3P;FfER zxV?g`+4B6_o@s=Dgf*L5{>l++ST0Us@;I66WTM7xV;#9-h17bNwbtW0k!K7zV6p=6 zgq-TQt+Z}#dKq1)Y=XVm7Z~(73?9-yTb*kz8E6|V7!x31;KpE?5rcs4#szd;Mk&>~ z85!&6aG~6%u>yi{m$P#D>Nd->ikc4JTQi5gzF0YWe8# zY+a+>qP@?B$or*4hBa#nzx(fj?wb`|lmYXS?+-YMOW&lL1}WriDAYHi25FP|&F(;O zKOjr}R%b$hx!V$>kpiEU-kiwhTlI)3Dx$Bxr<4DAu9H6q#{>=L3t?^8Q(a)oZn1pL zA9S<3f14EEr;lDrq8ILLyB8Um0R#5f7LlHzdvV%&r@TVQ1TaC?Ejb{(xKw^tz?d`h_;_@_dIlwB_a!ogO^$Q* zEZ;f~eh4OrA+NAVg0t9`AD?)!s1zDqM8t#xBfA?a$z!t;0-OLMA}bD2J~*S=BnB#h z(Gr{aUC{4f-XdcBdnIXx5Gd57yQnyD4B>neV=(P48|9Hu(aYstL-;(W*g0PPkn=JQKK<2p3k3}F1Nuk zdZmLUAgh{C&IP7rPrV<`r4U&7W_o_Tzn&vf^htq{WNpmx)fZs#+FKBP{8!c(Kpd>O?p-oIl z_6M}OKioYJ6R{+BXR97JYl(Pl3S`yLy}Okr$s_Iof#0yi1|{9MO< zEZBnja)Vf4a(|wa5krhFol#Ann4u$v1cVG28l1Cv z3P^lGlloaPXvcgl1t$*v{!#J&R{K)Hg-e0mFLwHNOLan>dU|T9^%sXkD}M|W<+NFi z4ysBy^~ROr3mW{c{qNsLDNw6*I$XCC7v7A8@vgPCy_-*0n>|i*(sNdCgJfqeDlNvgcQ zdiSinnB-6W(tD2x#Z!3L;-~TvS2n3=;_lvM{*kw@k?+*7 zf7k2nrL$=2Ak5?)Qb9uZ^78jMv+x5pBXmGQe8s!6snzu{_>qY2=Cod!!OW$iyQB8a z$wP6%flWHSSoHosaURLyWyVB}AJP$&ayK?)`2TIZhHF)RC5n;qMI8L5teB_yPx!~f zfKr<^XUrq@p+ecm>EG9**T0MlFU*~Ie@KATKY?X)K$f0@r;w<|3T^2f4jw@{YU2N?y>sM-W7nXU11{6#Qpo z^d~y+jGu8$Fb3!di31*24%-9;DZV}YDiqV~j+l8x!a(euNjl5vLs{S4RIL5l9sT*J zlFoc1zs2bJItRZ9Km8Kd?-_NxP5r>L<^6UecR{QDVW;BV?@l)$= zbs)+RO%(Nou=BJ9uR*Qp#Gk;z#=xIc5RlDL<&S5KiyN)^L0k@0sUo_CHLtF&gIV^M zt<5l4nm*vNKKH$}`debLonBMpSPPhPLtw+y`~R~5#z4?y4+mQo;kdHYX7_Z~g@c#= zpC9VPoEZ|-#7Yv0;rC~|Sfhwi*ts=-Pf8hCGWeWqSc!eF8`E3^%MwOnlQJ2Wx)S90 z6d~?2bqEyg&jF5+QoWH9y|#@I56m~282RihjwAe*KeSd~W@7STgYplOxv|9*MB6?H z;w43$7CTEY1FXo?XNuM4+3h$H@E{lZ9~j3*$v4lj+%6uw|jfF9m_(e-vr zlKQodGbyS(YBKALcwyfBr<%yl2?^P0Ynmej78af`iL(=s3Vxci@5E(Av-OSk@AvKL#s&qFAO*EwMSIV2#eFj3GoO{As*Z zJ5YUGE6z5=Mt}=AQZ7GW2^H0eoUFtGfU%Ebb~Q)%h;`G7cBNj6>4IF+!qpz`6f!*EY+>=3 z*7<@Dfb$WXGzBk;dGYDI`ujBsr@Omnu#S#$OT=#)1QHDxO^*!)zv?5}9Hh z>SL0#{{H_BD+P(is2S%CC$5_&(#g)@&7|X^0YMe1?4APAi(lPmhMm1AiCWZZ3=m@}g?tAgFh~F`#lSt!}5=tRj?h-K2Sh{f>Cy3A+ zVEoSt3uXm=L)Y?xDE?qml$e|>htp>jx;Gz(m|35lq^W1(DW;Py$}d&@3vZ^~VKVFN zwVq7$adKLPN$!#1wi|RWh6!5VhNsR%BPh4c{$9W=%aSMstt7&KN~#%P`Q7y)aVB(1 zq@D5FGUNxfEvMeBT>fjfkRCnFYIN+PfUr|u%yFhz*(Zy{?8sqmJgo@$?nG`4bl(Se*MUvv-Z;2HPfgG`i;@uXKgfBUFZ5 zVsx&!AlEP&GrU+QN56$rXEyy7N| z9MnIPj)wvF&9BU~lOhbr9gbALzlLwJ>opvEVgB7*;r%kZS!?l(FnRajT}N45yuW#L zE)p(=LUiqj8_tkeT7sFuOzQkYj~N{ckWe2van$+v52@gL@(gVzsaDBcqv>1rxj2%$ z4|TMV+hmNxny8$`q~p32G6xDRIv9IYtol;{&#&T7ey>|E_1x@+Z-+yWw7DZ@Cl_(U zMknaKv|zKWBy<~5X#HXq7z3R_);jY?SuSihL4}h1`CzG2^{d`ahhJ=YS^n@y z)F7?`R;Gq%nVEH02F*yl>4tR-a;Bs-gxX5aY+g040M|ldACjNYjiBq3Qi{e1IMWM7 zOA@`}8G>MQJ3pWrekQ%EUq+tkxsp+IL&rw&B>&TtUv2=(3~--nex-WflA**Wh6_5H zvx4pRx@fPjC~@1I6nSD0`$Uih1)mwY>1LF`nkBOs{|R!T6c|JnER?izStQ$l5+{oMZ=mxT&(g;8I>p;dnyBC=JGs5UU0T=6 z_M}kPFnrvwc@Ir{zSGPRe3@>4I2vW(iY+tlZ>Qaye;m>^m3 zNp9eF_-4ytcjWGm?0P8^b4Knnv(sZ0XHw|+zIVl)+k$w{m;3F%kM~T8m6pjda_dS- zV>Ypa7U7BwYvaFUIPqjfUU%%afBu{7Olm*kNfY|mdp+ztvTw(3)HZtN%$m*fc6UWnA3U70n z&Da~}%bgi`VRZB0AB*J{H)i&k7LhSO>bDvitt9>+S3ZP&wg8mrdL?v!JC z^EU_ZY(%2B`}wtYxad`D0>S$}7u>anVWR6S7myWeE_dvYzQ4i+N-4)0ZC2#N`k2Zhx4HT;NeG#)_Rm zE47KPw2n%oijf^L&sh+5IGCS!e+kEtuhD5LY_IfthKPuZcW%CJ!^~{M55fQgU=K1X zS{5G%>TLOVp`7!)Kpk~=c$o!m^7KJh%D&kZH+gwEltr)8mu_=V;jC;$n9NbnLdnYw5r^5-m`pst}UoVl~uVZCcpZ*K1TDo}? zVn+tR9)?R9`Ts$wv9djUBM7*UOZ_le+yz%-UVdrD#BqbR>x=kH8>F#PLoXr}4ja81 zx_HPV7k}xZKVs7wc|Ly3!ElmgT3Yqtq^Z!QjBw6gw;4#L0yDA6@>EY7vLvx<{oa#T zcHUq-VTJ?RCejl;Qi9oW(Ea})eEw@%uRBiQ>*DgG!~5%NOjOyDPQhm*W$nY^=~~q; zK|xlx)Y;j=gR2ck{tnAa==f~~-CodXu;5lgxv{ymVK1o=^#eOol1vn-k)hsqNtX?D zH*5lk?mHfR#4dly078xRV$aM6{ zYEREkXPy5(odtL zx`1@iC5jU%bh_w$NveiU-4kTIlK8`@?Q9bJeL0^F6-)YnErai*jwiu+uRDuGUQRg7 zBHE6HM7XCJFm7mm_uYK@o*XB787``v+h(pN?&jc7Fk$I$`HK1|(2tP*V1J>O00dq7 z@fOy$L{s;WCcW~#KiYl8Q?I?+AG4$}eZ8%DufNnLPou+9;$6@_a}d#&ng=_Ni++U; z?1)6ms_)xZ*H)nbGbosmflMsa(`>Xufo=NO2US8hpT`y?!}x5{ozo-kkZ> zbGKVHgs01M@S|=_m>!r*2+=>uDjrHSVJ!4)$gXA=2f)~U3MC)oazW%Feo~~Q@eKHi zaZ)cU-QDMmut3F_p{S4LjeS=2@R7SP_dKRmQP^kb4#T8XGhym}CiqdEY(Pm?&W~Cv z=b0&8p*;h0ASC@~nh~^VaSjg@AHnynT{svtc}s%Gm1&bavkJV7e^(3lm2S)l_4dT| zBy1}%&k2E`NUCDXG;=+(nB6I@$%#QOg?t_eQh%wataKE!72n!xy|6NvkhGPty zG)GIB31(!mXwE7Bg94}cJ&p?xA)5yJx(1X@%HyOx7Wn&!NkXe9@`qzym-~2#s41vZ!f5X2+9pbRNhx{YlQZU9#i%Xg1(KMYd%4903 z`hhF+|4rWW!TeC6jY2SQB*thUHFbHPgv;6B)aOr(D54g^Z1VDIf(u%AbZ%w4fCi(W z0YJahX*2@KTZ6qK9cB|gePv%EiKT?{5Xe;c0PdG}oj;BK%KjcSfC>;kM;N=;{=N39 zb~aH>a>RbQK~mF(7i-shGRTJrAXK%Oux*9`3um^2Pp~nICYe)U0nNpQ7-mBLo?(VW z)rtWQ&h#;T9o8nWbGCE)f<4soHT-}3kc60Q+~1QmOR#+BTid+RJ;zsg%CtMzU2wR) zt!P0RXOgXd%ZfQ6IPCZj71htCw3&X}MTez`HBhUd*_T{A;`%l@2gL1Hb%!Jd<@F}F zv5#6cEEPu6hoVK11By2t#3ueIdY>(Npse%eGXY~BXF=pDvun)v8=v|}IAEwUw7HHs z|BI6{1FW$^eL4bbQhj3nzD1J`h*Z`bJfRDtf$Z@e2%0dN^N0eO1_g13V!;IiG~ggC zxDQ}xQ3M%lC_V1lUJ}A0GdJCiJ@Uv-A1z+enk>ic^M?{A$-^+0C-As>J-pxzRDMaB zd=gQ)hc5||BHbPw9MWdZtaqKbb#n5vFt?XT;Yx8_Gj`hCXGu-b;t_p*>Fc~w4FRiB zH%06ejwCrf?P#CakrZ#PsQiZcK^zS0mzA$a+G&^A)!`o>J&^?E?U)RWobZq5%qsAo;s)-S`GzLpkQ9RF*{ z?!k+YtaMdS61VXw8je;LzVf5Q(`&iTKTzpEF|ao;IPOY8d4*Ipgx-B|@}Xtud_AVHGc$WGm)pwP?gIWx98xNP8lZ?ra#jD%md+Vxp zC zqP^w>jf^lNtc~Uu>JnIUQ<&5mbOm`%UGH6bq?0 z_53DMjfopbA}PXg%B^zS*l4ml^BSJhRoy~P$y2(ZZAG;#3mPC1BD?rwS*zsX)tBaK_^vR=szxPG@-MPB)(zrxCJ+Bff8eoCd z=hmp~yPI|A`zsnxFO&rv*6bVZ6h9-pI6k}=&R&x*{iH)&VrtvQ^P;DW)qlEmZw1jN zl15hrpY`u@#Q?#AALa9N%kaoRVq}A3o=6FXr$=sSrm*~^6CxdM^nl}Ew5Npn>YfVP3`vZpMKC@vtFVMZw2-LToCYh!57Xq4NrIRRD@RO-;qh<-N9NFOjrWpqWtIghV8bFBh8&z zDtjN_A7?eS4FoH$`%X2_gJS370c* z1xXXRlCu}pkG5)g!}}K3=-_POfG{`oEd1i)@1{`CsR?leEeck`^LQ0$kIH{dchEF@ zWkTkS-sRnHi5!_@$%%SHb6r&_KF|8X+@VX_vhYjmNhe`+NxZxJ_sl;BgIQ{nyc5~l z+G>dl`F6IpJFJrm%$nQ0hF%kV&5nU5MIV=@AUtOW6*VNp#4DQtctAtL zei0h8arJU8_$bz-_GZ}D!5d-m{(WwtPu^-AVyISAo*vLM3Su~{s?^cYNCvzaur*#h zwA58z{(-@HA=d5Tg~)C56|+d)=Eo7V_eX{7e1vcG$L|dN@4Lx`P~RToq(@h|(p=Kb zLHnoxD&Fu12^7!@C%^ITiMu@oiM?3}+~ANgNeGScbC4phEG#V*70Ujf)s%+SY%42< z!y^Na!0~Z8M*f_T+~>dHPdsgNTyusCuZtfyE?zknD{x6BqHFB1? zqCR^_M-r#mP!%N7{W-~hXH}J@-rFnN8p58|L(jM+N*Tg#VT|ASsy7p4%+*HbFO7{f z4RL{v+XMY@DMYXKW{aCa^bQe!B3&N0m?MpV9|+$mPB9d-`MENXVZe^G7L7tML1w?d z|9gAOi`>V0>@M;@V=-!oV&%z9V@nqyj(xrJ3S`_80@A&u3Z5`KeK)t+NKy@a;7me` zE#EsZ-v|K(di%z79KgR;2k}M;C@^0mW)0j~b{NsbqXrDgcjU_m_EE21!?^h%zpaiN=`-)YCdN2V4FzbCNpaK=QufpY zUZqdi3f6jADYp22Z48m&fN;&LkrFTo0HBpI6wQ?OOi~h5IeE zqfHGRek4wmCHAH(Wd4e)AQ`RWCLi@!I|IOsF#XF0seXE2jIlz|6cvZm0i7k+Pc;-u zC%YkXm9$dEh4$^Of4?p9MDv~6YBDaMQSaXXl*wC>CPY%kU~RPZX&z&NFqKf-Sr4)Au-uDFe*@MIQB`*t6NUnyDY!PZ9rFaQf3uI0peQOm>&94@mF8SjyL4BrkH$LOU4gd6u)tYc= z`cCTSd9*ajzH*5dAbtVUt#<>2RFDBgsl@7v%wHrLTCjb6FhCwF5*kU|z`9Vt=pC5wE*>wL+I5@;Vt$E^Qp__BiB!}8s2?eqNO zi)}N19cuJ)Xn=>O|AiJuD^*xGnWj=jkg&78y2k+)d5R9m41hHM%Q>y6x#OGHq&Q*> zd)rS;_m!T)a*pe0+qltRzt!9aR76L@nLNLhgSYV=Da_)JTDdNxq)V*Yyd>jDV`iQPlddc3pq(N7mpyL`u2X5O_id+=YagGh z5Pup?M|NPZ9;N>F!d+Km|8Hjp(wS$PF%O%*r>+tYX=)N@IOu0{v!hP!OO&@@u1u(7 z>-lkrw7!Sp9M`s@e)Gdbu`^?Dy#g!gdWY4=8O`rp;!OVTj=S?9=;}9U?^$-W_3&PQ zWnf-NgEuLcxaW3>;P(#x+Mp5ZaP3lg zj!wcEh(QT6K_jChx;Z9O+>e@4-se9K%U`r0AHCzSq*QJaH5-&5yeYT}eKg;B#S`D=k}kd40RXBZiy#xxn9- z57tW{KxO0K9>u%4%L;E-bH(L3Dto8eHbJh>`9N)LuDpZ zTrn6;Jq6vDCY{@`8=t5sZF2GB6bB*n95A~{z?$KfDBdLdV2~{<7h(>3o2wJ`f8m9U z!J512X^rSu(2n`^{Aqf%7^u*K&uWG@LBy z4I!kbRzT+o*G=7KYyS^E6rHC)9%Yf16D#t&+aeSki*x?py!MCl*6N z1Oc$G(nRB-V%VWF4wCB+C2=e$-%V<8%k}pDQ&V6033*m8zEN5$0pj?$-sAcrq&)xkui}O(hNmGnxb8<{%&#~NQf#~~6 z>U|SQ*spz8(WjblDC;*h6?aI~|BwxB4DA+^I_AF>x=v($L&)LVU+nnUA{-*kCG@-q z*kGy{qQmc{3;Uo92cR3fJg13eCEF5k>=0z_iCoe1DWwA z2@}YY*#GdhE@pl@i^l z6S#Q^W5Ne0tNy1!#B0JtzWPovh5V58RE!Vf*koW{^-^pR61s_ z2=VXycC+|YLcPoK$!H!oVo+^GWNjmx$00vIpuCd9kdbQ}t#la#^ArDK9T^p94cMfHh@a?qDj}$ittwzL0?@uy?uIQ7QOq zvB}tz462chX(01V(f;2IR=2hb4siN4w<13kKUBkh+MH>O-ojW%g06ywVYMSM83}8a zCM1j*E@(v^mqeK8;sOAQ`eX1MOj$EeDP$RL${9f)zk)nUtt1j}b+}6ixpRunp`wF4 zgHM=1#223sBw%p*3Ypdw zImi`FGL}A#2#TQOZOCYs4-q?TOvE>OBCqbR?Xkx;NUsWY?xIongG1ayCjV)Mnw zwm-2KSspSdd|+Jq9L5ovLhSxPN!X`Qacw@bC13 zGbajAtrkKRW+JJyCGZInu{WnXV>@&6f${?$t*$gU@(ah14e@$cNlLOQzwi)%1`RRD z8G(x6fTDqwVJjZM`=TSK;#!{AQ>ly2?mZZ)s%oy3~^wXF$jrC#2S_t zuDe9kUmAo19kimyrUV%2jgmSFH96mr%Edso-|Y2Zf>w#&@4KG6!A^iW!3{Nl1tc*J zmyiGU-c6n0Nzu%0Jv<+%wHYy05xO4^oOEhLX?>}a7G$1Tb7qHm ze~Q1-FRgL$f=E#Y@JF_?h%5XowCHS>xc*!DyOLLJ1uK+E(tjEuK>( zo||0`EC{JsV6gQtR+Vkr+um)>I7Ozi%yQ>l*EP;t001U$O>VS16HftvA{oK3w10m$ zMu<>gFk%EIo-ukNxwJ;h9sEe-Xe?Irl&8;_&{%7=+blZKPESh1Y1S_xBpeKRT#oB+ zx`V+C#t1VEm)jJ}!8O;eSuk$~1w`dsbyfZNTny;BYTl|+Jx{cNo-W91S^&ok#h~O2 zrQ)zAw-^ZrU;wztRE~hU8KF`5z*1sr06?n}2Y`#swdarKor(bD5@}-4GlDt>F@^{G zPybIomy`0j){~t*orkKbYf{;4E}x5@*k0*Coo(9^$#}D25d48$|Jd*d02J^YO5Krq zheDijULXiYQyVsI_j>(Xw{0yi^CcqTWy_WvJ=Q&;xgi>h?c2VCGJqMzZnFWvWh+(# zK<_|5)wPkq?!^md_YZ}p&z;hClh z@Y*LnbGO4`ed>3=jSi2U?;2PJ2Zn;ztzP-;%g=p&-MY4p<3oMJE|;y$ZrihC&&n%S zzqWCM-E~=E7e2ivNl}#M#^xJtzisC9>5`HMmW+l+cWiuP>EflTt^mO2?!2L;?P%fP zd2<$cQGWM(uO^e(BPUL-z45lHT5mWQ1OUTO0RU6P{;Nb9m%~E zM%TajrpT}jO$~pe@l#RNOQ&zX{Vpqt7SVj&jW-8|i;~beRjTw?jD}+Xz<}Z_tM2L_ zoi=$Q0v1zURr0~;STdB34h~37>iJg1a%s$o`sH*bTR+sCtWcRq`bi`sYM+f^^yT|5p2xfEl(YA`JYCvo{765>{ zS@Y6?zP0O`*6>cz;RVJdlvMQ04lhP5z)1i|k99Xps;Kab7MDMpNUGTwWyNSTpLoAV zRP?)VUHrl;`v4%C)eAImtJ%yU22LfTigu90Q8Y6(-53oJMn1@_Jxf|dCy-5@BCw_t`Mh5uRL|$+pZ@q^1B{eJ zF1hNeJv$BviT;7UF#x9y20T2ekd3yDk1kNO4kJTh#M$u{e zvE!FtzIyw6@6BB}r_AfG^jar3Ri_gf0N@$Z#j97<*4J;{ylHq~I6OA`*4yg=;FXtK zSPoMiKKbcSE}pk|?wmy@kMF*A@uJbOJ}I5B*v*s}PKRmUw3)qq#~l?D`ue&GW_UrE z#7Kq;zJ>Nb2-HlTGpDm{XFLrz-EmKKO{L8$@+LD-qO19IGSt_xx2NM|BAF4b)Q24=XJitc@4dxcdCC)N4&ewVYDEu1;oK67&2_%;Io z6tgqulmS3a0YH2tZm_IR%0Y&$43DH@t)XNpI~L2Q^ZmAGch^`UATd><;kD3-&A!Si z5nN``?j4EJ_~__cdqNG6Yybd*SgW7|K%o^a0AP(`1T4cKN(n`c)23a#>gwu>8ccCVXZO1sH^s;L zkwJptFwi1_#fwb_C38$(KWjRi8=EXRtVjsxX{*k$fa$n!5G938?|>4g7;0E61yI3= z=#ow)0H|ZkCQbx^X4Yw?w1TtfK+k^O3SXB@Mq}Y<0oDt>v>1%XyK9Ms?U14A61&Ny z5spI`5Kjqaxs(c$Ok_hr2&W|t6BQw9;uwPvLQipaH6SbiBU+|RneFqqqmgK5PnVWW zQ_!`NbxCvs5Kx0+OfkZgQj>}A?H}B^^JpM6`l(NTyu7w<%lo@;z5e=yC0l-{|H)Q}}C{V7{%D{b%vwKadmr{080?d@*`uhoo&Yit0S+=CX3f5T5>t5x~yvdp|(A(Cyuud zUA1}!#|w6k^AjJx(I%RlcKY~#JxLAN{MJ?gAb9Xk;VC1fS1>WV=KAjDgJ0ALarL(>J0OXoD3wM3{d1xv?+OH!$W z<2ZMoG6Vpqp�He&dB#0N@+<)mrSHzq3^k^28rrGdnCUukD8GZ;6DX z0N`}H-dX>qZm7Tg+0OuBUSJ8(eOq6(+RS&{ao6Gn^B2sYr|Bw74NccMmNknOUJ&2f zzC&P`{J1q*=2~^twT#KLbLXCHydw~o%RK+|HQJnRPBc|jl>q?5AWhY?$=t~B2!w+G zkjRmdh{B3?uz0dj3INfJYtalB09eaiC43?O(hiE^DM=T_CVXClMb-4HZdkKo<+WSh z+qi%GW}n-=aPguCzW?o?|LTu}?YsN?do^9=I12zw5?t-s^aK_PYHKplF@pX1&?0jg zK8p@f$yu)9d~U%uo<;SrmJrPWz@U-$adrS`5?y0j;*IR!Le@E%KewaS*V7$~6|;68 zzq7l0m=b!1hpnHbYQpm@0Mz@;U%dYhf*}6*k?&GM8YkA*%v&PaPxiG8^9+Md%h^(d z=Pg|L*}LzihNjAr*W*_W{OE6=Jh*q;Y5W=BFy%O^=`6vNQq({P$>{m}A z%*?)U?vOBWf(R&cXVxUKk_2KazEQA9fSVv^MQb$LK5{kf}%JPere0JTs)|1D+`jwX6 z&i?DJU)wyX`LUloT<-O;z<>3-_W&V(ex{x13}Q$)nmpr~F%Xl>Wj}rU?Fi#JQ>SW% zcHOF#3>d4fxP(%4^%Ymd6S=EaR|9~m(p*M5-qkauskZB6$JsX%0s;US>8Z$op=7Gx%cXY za@&@7zVY>M9P8+)&e4QC3rLHi?F+FS}^j;loEF(XiL!@9sQt&6?}2 zHs{_wdjTMuNw^)(d@jH2ipw@`ek&3lV-3FTNQ-vc%{Arz`|rOOBL-<)+3;=-5$5R>tO5MFVn zZ@=qKyVcI}oJwHnMXN5k{91$D*%RwssnGxcuOuW-=zyA80`g(diPFGEJ-KKY51e1Be zvgHqNd3W_ik*hAg@aV~tGbYq`jtsl){LF@G!^bVGLZ0fW1Bv87-%vi2viqyTL;d56 zZ!!x@FTJ9&Zt`C@y?LVbs7#ezU7xyaq=~onv*!j-pLPZ#6S*jSoFxh;} z>T+ijalvk8fHP#76Ier44NYYbG23nVyi5rNolpuaW({3UWU{-C4;&ka&huBXtYC4v z06;7CQyuTmdHM1sdsGH4L}gwQc=>Uoh{X>2nt!+q3x(fBxf7XUr?w z=4R(DY{LmP$syJR%w&_zThvM;=yB!J8x?{xUZqMM&R&;i)QJ%-Z#*_;^GTCI*xV?_AHq{ z=ULvo^zutAR9ZZB8UQ@{_@nDS_f^aYW-UGWLAog_AHn@ z(}xbc^!7XVfBkDi!NF7{{G~76WwTfxc;JWEty<=Gi(a>%< z7#Qm9?73jh%;C}SMN2O1>TXMoMHxf`LxYb!@^CmfP|8cIXJjjM!vFw>)9Ue7AXTAM zfbn86Kn|CUf&7zC{POVLBLHBOJjL<0Axl?WD%fr92M=3KyxnHwOuT`BWm&6Pqy+pP z--^}O{?TKJMe{%bBdP=JJlHzYKRjnjTX$b)C>}=!C6rxD$x38TggrzK1h(Reb z3_z5%nQ~HcsJq>5cIH#*Y))5|3;_6@_EfIuOOGelacQH-(vo^JN29U$J8!+w&^YM~sl3O2iy4k4ZFTGih`hi6WIq0f4};t1ezu zUe@&DpMEbO#aT1)P=Bap&&hGiWZXnA-Ga1InoGlSBA%p=6hQsA7lzoN+vEfiSp2@{Z(jrzKJZ>uh$R$XvWAa0uY{srV*^(__^Ynz{c0v|oYErRni~oms-NMfoFnN`g;$yA&emI9F zR3Z_6<@MKfrFdjTjXxev;PcFUG@Q8ohHGXtx&@B!{LL#T`-g#rKR^3Y*@mrx)f|n- zshU5sdne|_Og5Ly$abfd(xQs5U=j>!NI9j-XU!#Le}x4AOd_ApWOQP1qWSRAme)3H zSaIDN04Oi7iKR0Wrc4zr{DQgjkIX+&UtY7N?O-fCq$zSdmNX3Gz_F8dv$d{vA^`9< zHvn8XZ?Vg6&#T&@Bgf`9OauT#AutxKude*wcfbDYr~j15WUpJZ_R7mH*|ckG%lrG6 zUU9Ktvi1i8`wtziZJrDOPM0s0mrkDSy!0Z^(bhu>A%+2q7tEF9^t&Z1{%?%M^QQ%a zgZ(38<2EryMn$zd5FCa4c|Rp(^8-DDqR0U`JIw=_(%$|703d{@n(XtIO_+5F05Hx* z^;k>Gt^<_Nz*t6AHK6S5MRR;*WlpEx*9?`lH5%0mtw^GQ;K0Fy$#lkS;sAi7=wCCf z6VVLP!C7vLM-wapyT=ud1ap~$p=t$DHUOZds&%Rvv0Oq|RbCK3g7^>ldML379015# zarTv5o);Ki5VMN>l`nnKX|tUJ-%EFal$Q}JN_kmV)Ng-bowue|Com8gxbUJ2PxN-~ z*}dQ8cEywGap|bt>fFBmg^H@0?OV5|#)j5hab+eHuA9>Y0F_hcw6wIAi3|Yv?bfEI zy8iU=c*hw`nH}4=R#w-QmsbYUNkdaP76WDgnKWEnj#GV(N{%EhrJE>241l}=k|d9g z$N->72JGzu05y}FG^u)7wSVr~o6hjBC(T5gBaww}L(s^Q#f|wU?=0ETg zEEKmR19%qaaw-5|fi2uCW>EkDU@*Z*qdEXkb-cxS@eDgVPp-W5;`g@f8X8PqvSJDV zghn&GO{}SHdU^e3UDq)nj^{RP-g=^|>$Y2NojYf-z*_)epg^cjiEbDMP|EQl1q_s; z5+0~P-HbqhhV`tUwG@7}$cQMVXBY9_ZF($%jML&Y#mRjA)fdyLysqg|P5}T0K{lJm z7-h40rlhnZmHIU!1bg@G-@6Zpl8q*E9D@PjTh`q+d+s8R$C-@${qH@v?3(M!JeBXi zzvseb3!nJuF98@?)d3(Jjj|LP8XE)M$CfT>92`yqKroiAZD;@r@o1#?WY_Yg3ujMg z8tw0{UOX+GO;4$<95{AN1%2hxnUf|qY=4j8MKi~n^I45$u#-m|DCJfLK$+244xkQp z91U>X!bQunsl3(d1_FRNpUatyhQcHLw_UfAW%(+nB^K96c&!RsrsQSBC?l$%<|70AT16)^$qtbfo|J=l)`~SSc7~KF8co-D$G8hzRBbZ@A)xBO5X~Uja75skEY9fEkQt6a zAZc=;F$g5fuUc2%t4Cv|SpARJ>wSEUxP-kb) z!1fLG<@EqiQB~g6d!oQuI4wI$M~4FduxIDK3s$W*iyVWDasJQ$WXKu;0F!WzL?}j> zxA*~ID60T~%WjS(vj6fAF$~7cd9C=3n>H_8yyX9U`E$?x>DkWqAcw(I=3TYsw)U>B z{$s7DAK5=JeDD1~sPeieHq|>EP5{WH(`mU#clpkJ4?5iCr*qb)ip9OTi0|i&=P=?; zO!WleOc~9Vw%xC--AUW_@4g4O90-_9tS)P2!L<6?HT&BR z#$!>8C@`p_t8Llrxfap%BH>*- zcbtAXUK^jzDjvHzmOf>lf9o4xdVRzClf9#r6@G)}JK8(H@cGZ|cjtvj{y^hgvIy{zp{grnxAiL9l`I^gz zMt3ZkKVhhUu(&!pX=^>&cA}&ASVwVhmJMKtPV_RL2T8KB|5z+MR8ixqsBw8k-c{x* zuWDeq5?!^#ZKWl$tX2x8>QeC<^^#mRDN!xQS-e1iP{SZZ)8tG%nNDXSsf;9pVJIKP z;y?7EoL_q=naF(Uo_kyt$KSW>yLN9L?H$u?Ri|hC0D$Pm&9~gnSsZy; zLo9<$EN`&H_+LoW5KI9;Q_jJL#4G~<{juQxR>lML^X^HRbnfwA{^GNrz2|2?{n1Dy z5sSp8Oss3~KKaZao<2tijgW9SHWrEk1p|=+S5mZcq9A_v+xLF|M-SVa{&9i83A}^S z0@voe(=}D}07YkzafU{^9)0vN0MK>4kT4WXTsDiv{_w{~9{SNQe*Vy#Z@oLv z-)~~zW4GMk_qp!-&izzl3`96qum~K0BAOh>+qz=O-0)Dp*NP`M)#yO1ZpXe|Zvy}; z2nNPpzsqH@4rdZwy~79$k!L(+zP!v00RF0~gNNTOgcbpyuFmK6SlN`ydbFA{r(xvF z>|$gf0|1j}EU2q%`0Fb#^>vNx-oA6@v8+(V_t{K@Gx*&J4Ex>7`fK-m>nI62v1y zDME%$%@!L*IG>XMz-MQ{piZBws=nFosbE+hAq;>Kr3e8<2q++gD8dK`0uB%mYEWtb z5TK>#B{dLYP(k^W0#HOt&2w~3Ql)GnI50HO3#XNQe+2O#X1W!SfdBy1Qiy|=x*C;x zeJ{Q8N;)3<{tq6s*?b=e(2Re)^eIlXKJ>)T2!O?6T6)p)o%{ZR7z6+YQ7>JxWQUs0 z>v}FYV3|0a(uz!ix7Z83_w7sNtVDYBA#c{c|*xdfRWk610e_j#tcOi01+J{ROm_x2oO*} zJVSxXvI-Q-nx+{FEoEzIDe{9TtKt+e*ivd5B`JbVC?x~~!T<<^0Tc*A6luB+gqo~; zPF8i5aDWkm2_=HS89)&MhO!0$s#7?vN()nJw_5-}WvsEJ_Rvp$IcZXLO+^g=?AZEh z=kb%o(AknCWHys1eG2QvO{4JL6d}lGRgPhYgQ1`N*AM^mKfmd8Rbk8mAfN;l7Y(1W zxTl^iN&yNju!?UD475M|(2s+GF~cAnhtrZiaZ*iSBw}@#Wm#buTu{A0zyL#7e5zSk zeN*!bFR#C7@vQ1HKgEb5v~c>&3qQSd@4-Ejni?JMvbC45LYPgYV;%h?1QQNXrlfh2 zPNwhs*0*lI^<#HjUnDiPojCs3V?UR3Sr!w(MA4P3q`vyv^ETd;&g4}|+jOv{&StcA z3{IW5Ldh#F!BLh$qR0!JFdT|++Wbl;ky0d$peH{Rz(Ilo24=3USX+bo3JZ{cn zJ$m?fm!YNuL&-?|WN53+?`OReZ4NQ7Yk}5XOl~Zll@-m94W+&7xL|W3UZ6ymRSW=> z;A3rl9g6ULV@z}+*qUt4X%y?h)S6|wk*9ea}mZCQ{toOQ297l4pN`R=PY)4F2 zPPCoq>qL>HVyF}WaO`;JETgHR3M=_=II89|foPgFo05^tzC*_wtI7lf06Hhy0Ko0A zB_n-WE(Qql$rw?x&TCS6wu zF)+pm5C9>dBS3&~5%f_3q7fkkfFi^IXaE!e0|+Q3g+L;u6ag*1z?flJju&LcV)xbq z0LyV7LHvh44E?;m(qLfZp3i*FZ*!IK{cl>ty8PA8-Cj{$4+1OYvku?NpZ)sR0B~gQ z-hq)20KC6-Q-60+d^H{Dukx2qnX^0?94(vVDX(xuPo8L;yR53bvblLe$H*3!nU_za z8NB({n*d;_+E9N#tICuhq8qDMES)=Vnr7&RlF=0@o{j?mFIsciBmgiak8&Kj*phPA zc%Qk^!0=#uJ1?;3wz~l|tOLND3m3D3D3zMr(vpiRtMm-GB&D}Fp@>{QcNqZ8m^Sfj zc6|ZgPaho}gC{%skik-eAY^8FhWx|vs8lNNbXt$McYpg^-~Q@Xzuee76J!2gC=hQw zy8CCpcx+^Nte8ZN<)=)q8x2Gg>FmS_b+_JmdrsDKiZ)~F7Fl%B)qN-X0bu6x`p%YvqOJPq z$$?zn2Nqv22f`TR*QF&FFBMJv?i_z?>#>X~Hq4j@puW24n77QiYQ>}j$BMTx!@<)} z|Ei^B|8swNq2yzocfx=FyGI^+_>sfFqqz09ue! zJ@XNx&^wywE``e!je30cimJ-C6FsLN7Kw~GZSL)Rk39X?_3UsDD`0nqOKD6zqUdLp z@1>I&8PSOi6P$L_$Vg{_=`IAQ2iHa(m2)Osco5Jv=%X85^ys zxU4G>^<;7+I$|*~06@=GN=gl5EI5V?iZI>$-lqD=(^b8AGZCd&l2^d@e|(4xi_TRs zR0ty?h64bn!)|vvG($%KloAaH3lsn`z#s$^F%*Es48vdpC}KE@D598S7?$N3o?}@~ z2d%U9?y7wtUX+ThU;pw;ue_1T6v?3RM80`qc_bK3C9*D;wao94RL$>pzy8MC zc190|V+-fa?dhs4K)jh_*L~^}h6jGKyzIc$Kv79@B*R%fSwuyfS!()a*rDTW=?2QDRlJons~Opx(XqPCUO8wC^S5& z(Iw0BK<5B_LTauXjCTvlvb5_0U(}=);k*JO=$#xXf7`+s+D8w8|y-$gw1Bg zr9x#@LEpaj1FOT3^OitA^zb7CLs3;lh@n79Ffj7#pZ;R{wEB=j4+fII<)#A3TJ8%8uZ8zP0_x=NWvyz$3 z0h>=ZOqleQ?|tiqm!CiT#5Bxz^|pQED|hwwjS)?+omg33Uam;$XgD(5*ZIcw{Szis zR91SjIk~lca4?wUSVRCJN+}SALuO83FoO`$G@=_|wy?aJ6AW5r7tLnD?y$PN<+)5> z*Wie%5d;VUio~U?{`90tO+WwnpLx?qjG7O5sG7_cC4q`A;dr~UuHJz!eDXsX>Y-pUQAp`*a+J+xJ{KLXqQ6_JD(E_%Vs4RI&4UdK9U2thS z8w(CbD(ZY`!#*<5-@0cv6bXo@gv`bbSr#y0@KjZ#leuIxN)3|F$g}28wm7N~HUI+4^<@tPao+`MVQw8`;!}qb)W#il)_fy&B4dB5#ztE z>4ua~xxJRIfne9bi<`FWxN+^(i!QiGw7L<)W5fVZt(2SPMF&ty0a2poGVwjTw!QGz zSBFQ&px8wm;_*yFL%F6I(P-9c27t{OL>FnyJn1CSxfYoAo z>Gi+da?Op0k019rZ2&N-w&7TR2LOx&Lzi8!#BAoxf~BML#Dr?!tSR$8{g)R2;D(Er zdmQGM`g;@6Xfz#LyK=3rYY#v2quI0OGkWfV`429=k;r|@#v3#`O7tH zZaNSfoxl9!sdQxL&fl)R?Jg{*smts!!ntUmZsL?Y1s(X#zD}#aJ1xTWDKp=BYyG?L zynESY7u7qbhq~I@4iJvR1@{PZ)a|d&B%`ucL}884a3li&SYSM65mO+fSb|`)`zaH* zT5wh_h$1tIwB8d)uW6j%Y_6ALQ8}k@e37W6mR30_Nt{_oB(g}S0KjovUY86V#v)m# z-D?tE7qyD-&0C@L>H?F#TWh$N;uW`-fidNCi zox2yzpA+cpa+_J+Bxod-mx;hLO|{~Lis`+{NLYhFR}27nhj(&$P4UJ)MIRV#LMTEmzz3u!h1X4 z1Ay;LpZ537VW;iYceX0(CX?Az-_(?doY`14D@);Iy3*^jTJ5qFq?9I8NyQ~Z$=Cnw2uLj4`|R@|9UdiD&<58c#f$b9<}+FgQB)=o3$Q|NQdo8B>-n zxv;vf$>sDgyil^)gUNVwaA^Mt7lNj$>Br>Fhi+P*ntVgbq$ldMgss4OQk3iVP~?5 zOganz!;!>TXoy8#0Kk+a;z*H}h0rAp|U<1i)gkWTg}Uq>_0}kw&9q70q=3@Fm6KnqP%%9uZN5=o7gOQA9N5@95UVBwCla#VqNzNf+ zXsRw4MA3;xsll^URi#8K9ZkuKIyNwNir}Cd05BGfrc%-wKRtW?tk+(DyYG14+=bJt z7F4hl&As4atHtVa+WXHs&zGKkz2oSyX;YiWJz#{2JRG;(URz(qG7Lf(Ft8LM7Bd`! z02ly-Fl7We*OS3aV|f{iG9zP&SSJ6;&)fn#-?-#_v#ayEDU>dSnUHG*gcfXapm5B}(Z@pqf+ zCln9U)X_j6V`wIm001v;*xb|JUsmNlexhHK6^p|H02J{CJ@;7+#ZmxJh@K;$K!~nW z0O;uMsA=>Y_-`qNxvQ!GfZ+sM>Y z?RL&Sy-c6cNTXgXtGdX&VQfP%*v2M6Fd@18azk!zNFfb=X_s&la!I8oHed$=HW&l$ z-I6R>)#{q6=`*MIb9P(n_s2Q=j5Hd_#$f+^d9)rskLS_Zb*;6(^{w}NzxR`6iQA%P zm_A)mH8m3P;o^(lY$C`Th=TBXU2HoN3jg@=C*FO-jQ}UyQ6-skQK%FqrYAIi^i5nj zpQ!{RUI4bm6RG@DFYJ2!*_{$WIOy{Sbi$}@JGo4uR5MJ+p)wOThv27+cduT%WNJK- zOcYMP?6D&QfBA=hB`6$9B>F%-oZHMlV4Q1;s%T-#Xe<(IbkmK)V^f*r>>vE` z9~?b)`y-1BvdfL0X+Bo_FHbgVP<-QTLvY}0xMRFhX(tX zboJDC7U^v5nMa@bX63&oQ(4Cp_kHUjK}Ei5Tyg82sdRSc)Nufo=}>_eUfJ{9voBCC zsKZMR|IBCp6hPi|I1$5xgR_$Zr9vu^%*+13qxU^&8#P%N#av#0b)f2yKwIa^^&5CG z{oRKi{?Q|kPE97pXVciXCzqdsthAbTlVV_)wLkf*FGl^eNS`{>YINY`zN+1X87 zE?>L$5;^P~JaqEX%^SOxv=#E%O&c%Xzh{B^>W2;w9XdP&;cx*WK&X%aTCWlUE+}OV zI5-g?lyHE8H~@tp0vrG#j8H-Z7lHr^rCf-~Wbx?nab1&ZHCq6m``kZ*2udj1oW@_MWzZ{^J8UzG3Snn1_0tg)?_*EDWH^qj z%8_UsK*a?sUV7m%=hAJ8qVC`M?8%`~kC|7P3~sNv zYaiu|>8jS+*>lCVONT~=zx$1Ej-HwvJvAvY3ee06VRKFU=OR5?c>Kz^aJR+ z7!o6rBzrt+q$TD!s8og57cw2YRxv}t;IDlAe~yh$X3`Ds*rx{<_4Ecq{(#TBDcC?#Y^9H+s*mXtZmz=*`i@oO`~R8rr<<^bM&<%`AlAtRaIB&rKB7#gu@--2q7^> zJ$|JlKu0r%uxo-)0)fnj7aNGyr;IsXgUw_$)&uxEg&(RZW`;MPHq0q(? zTJG#+WNt<=0uXRPD1@#D>Q7oK7W@HUzE}d_)jclGQxSr20>9o!`?B1(7ThL)22jET zpn7EPf|HJE)Jwz)A?D=EFPQkZ7O25FJ>O%82k-sJuSP?WH*}p!}9dTwgM zuX{4Hr~0}gCyy5vJSCgW|MNfmqhZ;1f9L~)3d)0h5U@p>rW(Nx3jAJeh|{-9Z_6^g~TXBvbeLA70(8k#tCaG0<+ssA^0a(L+E z@LXOo=(Eo}KQP!IkH!X0j5tQ|pT78|>#n_~mcxVJeo1D6J4B*@pg;WHcVZn~01mwd z;dX-0P3U~=$b7FTQLcYg5w+i$*ZQOBY`|NQ4a`J4YeSE_b*hBS{)R|ZcU{ph{_ZFXjAQ`f5d9{#VGFZhX%e=uLIR%+&>kNsrB#`Tx4TQ@j1^jp9A z$u}haKtGV0EF7QlG*u*W1ZbC;kX`dUr{V% z`&P(LKl1q2D>i3J`E;_dva5A!YNU`U-t)0rds;$=_8%xzE!!|T7q-JCi3NS$SUltl zg>s49-d7KI_qGd%YhL-<>u;1bwN|rKnQ`v)wQSKm?4oNgz5Uv)Hn*<7a^08z_3P8g z!s|>1w>EuaAp8Lc9`yTA=PLsMyt>~Ogi(&4WtYoT52X&c4Iu<~1TM&sz4eWryO+0J zy0L%YIDoB}U;g_2qH6mN9pAn0uoeme$mR0qIXD^){5;Rh1Q8I9Z9{;nnsA(0JQN7| zxezChpE@UFq+BuFqVJ_#krS>+Kd%VV71v$0fB*4tP`c??-aC~pJ^7yx{tPooVgP0) zCd$Q%8%hNPY{9APVVw)GdLu0m_WL5C+{|2X!WZ)U7`04c+YX2$GZxT2HQN~-@Ps8~N5IVFAA0yvK}jIs@9JI!U~Fu#y{+@uiJ6IK zUnRt1lsZC41Wbs!M4l};A!ON_<&?@GVyOR!SM~q3roN@Ip^hMDpSs;ANbb&zx6wxzW$mU`noy_)pEI7dElG>lFH>JBKcMI zd*AssC(`9xw*t7~hIcRSXaisiZdWUL$0=1TiL&X*iE^&=&2QYd@$WvL$X9yX$)fhy z_;C)PP)I)VgP%GU7u+G73s5*9jB`#vgdl`bI6_czTvfeic?ROt$Z&VhqS?u*zReqa zKE0)-ZD3@4-KxI+I!T6#SV$ip9t7Z2jbt(lplUb(CIGE}ym_hdQ_}!Es`R7pKOBez zD#fZ%t#$Xb)EtL8;HFh5SF`z&Z8<@|=XKNhKK`k@m$$cveF3Xx*p6dy$FNM!d97Bh z)vBgr+aS&0s_yYIS@x)EzFedNgusRnAPOZCQW(By^B^X zD_5(RY`xSZ>@Pq6R}G8oQgoX1+N#muy_n`4UNj#DnX53>#4e%uV@^5cK-9^%%T}$r z<*pBxD%E304y;?Za@XM#0(%=brDp*nfXAa8IevV0CQIdppz!IiI2Ni=U^Vd>a)xOJ z(6^@d@*A#71a6bX001BWNklOTRCl3L0^%$sVE~PH(#@)11 zN=n7b=}&l?h@cC(G<#$23Fk&`{=c~I!v%sN{e$;@U~qU8>y`rW>w48TpLyuHYNfH9 zG?UAlgq-Ge*jzS~o2AucTe+{};xyn=bGVwvG!cMC-jxLk;xIz$bU-3RXK(ktzxL6^ zJcDWeW*JoTczwQ~KKsPQ>o&|LW?S1kE?&36cHlUrk@2B$ zG&VM!O>>hHsZe!n?p%MvyE{7DcD%epP#ivbaOKLSMkPNsL!$9`CXqUI>Ub#D(%(N6 zZ;h{8vo2e#hWx=-51rh0#pdUqdC@KvC{-y1acZa!s}Oa8_hxZh;%3u{W)(B)ZXY>< zp>R)U&(O%QswkSOg;h^LRYjBB*eLZ91t`KASDqIbF>>se(H-WOvt9D3aM! z3B!qcqT9$sy6MC;2ToR1!ntKT%|M9V%pf5YKqTxBsEQ^_tCy~zM1T-Ln3aadM%{bW zY^fP$2jKTbE18kWY^hW(Rx35zcJjr%U8!*aP+G23jatn%Ek#o|Y~8kI`O?(bEE5uN zK`;Jo@Z#N0)}yKp0J5kys?x1px3pSGpQ@yR>tFXedN4GZP7S{_MJai4$95(wzwk#@ z{4oGbk2$4e1Bwm!Qn|d><4NSpyWGs|^S6V$4?6r8<2#I;9Gx5<1`vw1{NM-AT@AFf z#ivic6T&MFfTw=+w4z9BH?I@2`q0;Yc-x)VhFikbQPR}GJMgi>EfBed8ul5D>Yi_)KY-|=lUpVyH zzx!f)$D$uU`dDUm0zf*G?LT&Wc07IgRhxJ1c`Xu;9z1xctFtYW&g6=v)ytNjIC>zR zOJA~e(=*RJEm8cOA{zNz_Tn{binYp`)vGe4?7GW0rmBUWrHfPP;-cP8!8wtIVH;CZ ziBvLID4M^h&UXYjA?Mn_N`%@}sR!wdTGn0lUndQvK6x1QyqH?e_3ul4ub)Dk{TV)s0)R7fpd)GF&S zMU^kR^omz@ZU6Ce&;4Q_H5Sy`7OgmPXik|+qH-pgcUZzxV~8R~;Ce@Oq^` z{G-44o!|bQRf{?STyfc!#~=Msp_tvZw;)Sw(b7fte)Lx<#K7qA*48x-fB&IhzwtM! zcK)7Q-*;kU=udwCj|8~jba-G&F!A)W+Zm){ejJ314o`qMAbe&#L8wFF965B1aEXEF zfk>f{e$$=$NYFoBr+L|hB9(nEZu6u90xuqj8eB{`Kx$t5V z3VH}7Dq-n-`3>H*tF2|*)-5|;-BZYA6GdymNS7wl=AJM&b<#9zR8b`+6DCnAQA#Oc zAYfDxlv2vzi36w<)6MDU{vkDYz71Wpu1At`H<}23o z=KGc}wuM$HXPau2vg&J|=0XE5N7(O6Td0i=nU(SrFFhCb2h}F4WX>OR*=C06I8bCF z5z!O(_jR?z<3YwG?ucZrFg7(ank-p@*_`{lo+g#$6TkI4Q@NbKy<^8u9x{rhnq^JS zOrIK`m>wJ7di7T(;Pf-rCg za6lx&D5U_A7!{mT3IT^ZTnKJ+kEU`6!384(ln@XOas0^9>6!F1k3D(WwbxFJ3?)V< zC?yi5j8VwcaRe-94tFAiP%ug)#yH_zP|5}8giyz+t05Cwm-i3?vLY!mF$_m=a3Me` z1n0c*^nl=;2?EXqs1Sm40T57^Y}d84_r15@luQ@<*7S}Jp1SU~ODnZXYC7q0dGVH; zTw}Uwz^c~xNpc5HFvUgX$UKmWqgg!N1;hlK_l28AW4HqW2B2Kb3)g-4{XhIe0G(Z} zhYsy}-|e>;rt`!zk8$EqN`#>E5HmYyZCr@aRmeJvH2nisz?JVzI^2Ae5Klj+v?L8g0+E7w- z{@iM`(x`X3YFfS1JzstGRn;vL1#`NX>3lZtwWtUQPIq?;%C_43K9!Jb`)5Y=(^co| z!%f*q*VB5QO4&@f8GI$<79Fv$=_mvDHUekHddjX-o92Ao3Mn9u^!>!*WBa(aqwh!G zfC@(zQy9OFq4jl|Zgncg`@xZ6ovmaljXR_&raT$IX{CI^Q!AQLXP!p+^btx0q`k&s zvqqzC#a92UR)7zGT(^oNB5v8T!_xJrDdf;sym{J5R-Z%Hyquu6k~eDlvA4FxsLmh? zV-zz&m?s3|Fq%@XywZFtz5un=pp=3_I#wqpLN1-eK{-}O&sNM5$r{N*%OcYaW5!y9 z24fV0B8vAZ9YuH=XsKCY7C!54+Hjvf*sG47A02lGkjL;{wH&$D?7@e9 z73>-sDqiCw1=J1j3mh4sz!k98S8vU}R$Fs6y7a?FpxC`Y&j3u>2C&`meNPrX>TEf{ z+O7mW3}4G90Q`cVw(hBtIu+Ftccr($X`3gR(Xs#lImPAG~H zB~t2U#BU+AA@CYmJGodaB_=;?!A5aNdTB}k7&*|gl^Qay;4EM&j9jIt5esU|ISfC-0z;`dxi8g=e$vbJRyyLZ&16UOT>T3R1h=d#vpp)+q> z?KZV;tixL_1s^`TElv4KdFd;`02^bsKnGS|PVZ~!Q0{*Yc@4J;Y0bm{pW zG+E^3Y&QB%Ei&Nw_`QSD-C%~-F%tZtfyclb7bnh}qR-n<|Bt1b!{}7sHiM3-it?zV zv^6`wr*NTAhOg*XaBSbVxR1jtKdUvfbfKsBD+rJ00fLK*DzycFXp0ConUMue1NU23 zO$B)*1NT0}ywA2S(9t9xr$OCKJ{={#`Y%nrE87_XS_tN3+W2DHWY00>VNW!rUXo9B zO+()a4ow2j3p3F_F0?CHw|6eCKVW)b&FaY6B#M6O!U$9HKoDa*kgFbe3;8U0Z~9BV z_fi>nUmgc)COy*!Hl(=Cc(p606L5jmIRk z3YVEJsA<|#<|&LrJZ5o(W(?{jlY$h2cX=UWwY!Y_7QA2p=1Gw+%m0C6d9o3F7gn^N znm2{mJ_ND{i2DloEmgfPa&Nt z&F}pXPWG|3RsY;dxAaBQack#YUj~GcCN_?}61HERB}Ul4ud27XbtUBBxOd1};T4}J z${w8B6hn3&*`wf)W`YNR8Eo{KS$a71Vu1@=_t%V~0d(ZKbr6L0ut9nS33LD$NZgX4 z4y?eR2`x-wI6NFc$cl8v8Rj8K6M9{lQvSLN1SnskkLmF2 zHts?-l;2Wy0MeNN^1WO>L6m=I?i=qPo8r;dO$6}Js?TpnA1_Ri@{lB9W@s>y%P4Dc$wB|0omlksue8FmHRn3*9 z_u^<^obfr6X)l(A-gESiOzRpXg5yjAm%d2qtR-pKTH2!oB@Khp2`Ea6W9phs^!lAa zw^pSc7d@|6iV73p3FM?9mbzxrGhj+aknbYuUnmVkAn?!tPS{#^EGl)Zquj#DNrse? z1T8=u6-}K@&?3fbw1o0oc`?cQM5e@PS!iiAjPx5e3Pu&izqo+P@tG({GH~qvkgc%C z#Pf0^Q)f^+oqg4-FMwUTcB2x6{)4QlYQ{CInjbOGl3iXkdH_5?k3_dB4Mb+8{zKJN z+FafJByD{Z8j0Ka{A{WJs^c;2<%RU;QiqBR?lkpMB^wYUNb~wVLjaY*AYM*htU( zb_a!CpgO5x_v7m_xh4$QS5njs{b$^vhDIpx+T(|uA+_1-&OWfN*J5&%SzoX(ZX3jj z4+ZWW^jmCI@VR9+A%X`e;o*|6j1?Eo6Y%7+1W|+(;KA?W@aaGXSH*>MFuoy29hEYr z@z}+Sg){;PLM5mU!gC%I93SV@J5S4)5+BFAvV*6>htE6CgYhs0eB^J^zba9!xwtpS zDwH^bSOZ#WcD}R2@?g%b*WLdXs3BCLhMHd3NTk^ZTW_&_S0nX2J}#r6d!a05TQQx* zi}IqdTBMD;=q@_&h+|?l&Mq^gU2`CB%$7L>Y(*TuoIGp&&=Q z!>%Z%v=k+cetltF^%&T#o)+>uv2WIQ?%2TzwRyYr7Mx#e_Bmn`dg@ryw9`X{Ag;KN z|ADqn8iL|LS)c1>I8`-f*IIejGo;YzL3)(90k_mRcq~UzSFBt=aef`B8KQdg5+oRZ z4ZVsXgo@IXI{ki8kYJVR;`1vZvx$@rq^B)GP_}pQh5;DF@RyAyVgS4i4Rr{{kBG>V z;YQnS)HzOs-P_J+jMW*g-J%tRWUM%`m|!}`X*bA^l`fXfZQGC3iII;~coIW)$Lau` zjdAQ)>@=xltPUNxW0ljY!a6kc7QPQLteaT zr{XD5p8kK7Vf!&qj);G8E$z6lCemP*iqVguX0yVZ3L@k5A1>9z`tKKB*w|C4Tm&0FkEX9v(|KN=ye=mB|?<(QDco4mMQFJLEX zwRRxUp3ujudQ}?r;(JyBixMAGCyH!uF2OAN2})TFP!d;F+VI;Mw$p)Vb&NCmjztL@ zKy8rT!U&%X$e-75E~s1eO+n>58J6-b(205b9e60snHoBvdZ0poNOw5)0;GA}+hYSI z0Y|V%kA^*#Z%+$Mn`~AmcNeGopHhsR2Zxafx0IP+1$>-JZI?(~g?>gGZoW@>8#ZEg@(Q zc0#XrvP@UM<_UMw5Q#BnWkYeBL1rm>Y5nUVDVU%HCa9oJ-r?`j&F3r6qniTXIPF&) z_Bb?)WY+iZc1lhkaceP&03v@RC^#6GWN~5G18_z0--6aJ%zNkoF)VOyJ^ft=u|Gvv z^cx0^F*osXqy?#9>l~e|WvO@JuJ42BWUAre;gDcZ7w5VvwEI&~D^0FBHMpj_>sK%vu_#V} zjl}L5m8S3fF#~T$fiP>UqK)OS#CddQRioPZr)SF()zwd)NxeZN7jGrajZjvNT#C8Y zv1jt@pA*@er!^W=?vKNsY^%FQ`j)Jhu;3&_fFX7;Q)kS9!iK?jZuw)EkAZi>Jh#po zdud5_Pdj62%?f{0UMkrm{MESS-lXs^eNq?BR04iC1Y)G|ogP10*u(AABR8Kz6FgBr zt%tKL4-y-hl?lzeo~A2*7Dq}!yU(t?&vLP^#hH|t`_Xe>YhJM>Sz0cGBA6+K^pCdy zQ^)o0_`b4uu~8lqZnRaw;ENazBBU<>cil|pwn(LnU-NtK-vQy?Y{vO6LsjE`^UB0cF;zTiSg`PK^s(E*9vJFE?QU?JNaXAlpJo z3lxoHGt~@&%BbS9%B-zrvDhcy2O4VXrM#)1l6`Yw;n)BE(J}CDvN;H!>D8S#4 zQ5e8l-FLDM+nK*xUziV7@^dzx9VU2PFL-M>jKy5$K$<1NC6Vm-;i-XHPJS=J(9vU) zxM(Ka;IcK(qyseHoa-|+JaK?lr?5@b9X-z0@WsS&W6^{|MP;jCKnr~^_t=lq9sGe-0O}44! zWadQ-0Kp0Xe^-^sknig+Eg5h;Pj5REFKTIKat;=jIp&=zr>ZRA;>t41L_Zrl3y#(` z@E42k5)NSVxcpNi(aorDx^H6xxjR-=mldg)+4w*U7pqlB>d~r8CjIKZYHO%*rL_MO zU8Kx4jPao4P?A97fmzi^QTYu6ZdHgKHvcd#Zucei=7D(T7p?kVIrspxf?t^{dZBPI zB&G7J5O>MV439D#^>8b(IJ#nFtRu8c|V?cEJI34PO#~sKn>?NNiTkd5rtT@+U5!B&~ApH0{}8 zrue|({JrEg`~`74ruT2B5=Qra#ti5fA-<)p#B8tb=_8OFV4THe*H-GK{3^8d=-}0= zQmIq!7Y4t$f!p$Y%E6`@Ib^_3Y08sF2l>Mp$=pzJ-}h=2X0lnR%lpb2qA0U(o-H89 z>|*oteyOY8|FN3McdyL%NAj&ZCY<&HUZ>C4>{1-U#Z}(8Je8w{c5qfx)$z%(kKb$V zkFTk$C&CQveqn@m277h|+S$DsIk^azG%r?}u$eV~O|9^%1|9e^@jnd5H^rwpQ5X($ zT?No_(ko|h3uflwzTS!9Z$*Tz6MzZkBafwGurW6}lB z&z_+8cPs9J5y}{C#kKANES}A2LrRZ^=RO>3>(gg20F>=(8;_|$zIEP@>9)4|Ie zm|`z0_TP;$8bJQE;%#Im_^EzWjOhsAbH`F$Dc0=+%Mg_cVU^;tk8p3882Wzt;7chP z8KSljPupI(KI=ruDEYK;b;`%-y03QV+VaDs-jf1LsINNj;~8TLr?E`TZ&AN0Yk*9C zt{k{{nNy?Z{k|~MNGCI}e);u&eDnMx2!@o&W)#v<_{gtLuCMlMSCPuZc5>7hB9`Dz zX_@qq1oVjhk!S{(iPHeIPT|Fc5kvY1N9l-$tYM!NAkmHhY(#v$@;~Q)kqWG=Y$63% zA~NibaWV0{w>!B}=4F50TLmiJUa496X&Tl!YNJzK{IW!p#sp-;NdrHN8k>JD890x$ zx(aZNDVW1e0wrjHBloW1n)GooY1&ohxAiK_Ee_PpE|d;pOa^nFd#+i0 zWbAy&WejR#7in}$Hu~T9Q+;@KUGPa2UehQBb#&e}^+9gZZB(gJ-;cB;$y5p)&qDcg z)~aL>W!u5&f*VKru!cn){NG2;hiChCQ)QO)tjR2k zJf!WU`;D>H`?4L&S`@o_GuPLRE+@~dCFwthSssHp0k&tYTs5{MlQC0rOh0!yfbCZs zYmC~cTdt-E!qv?FsaCMV*fsid=yRn4kJoM!;KEShe{~_=G7+mR40+6sVabTS58ooA zisUHpc~E#R-nF<-yNqm~VtouUw@az`+j+iLVhr-cQQzCZE8o43Z-idQlJ)2`(#FI` z?Zk!qcjYUoq7*#3qZZboHkiV+x*l`I63F6;@C0VmCi&Qq2%9gI@L&@E24-t~kI`3t zr%EYWerO34m6er)l^BdftI9x;?6V7?gZ&w8G%4K6x!537M}~U$emLK#x48O(Y#MiW z$7~Fsh+&O2N6!}TV4Bfr+|QjD^{GW~xT3hcHtdBRZ%F6r7-S)cM`EXJMs|@X=Ts2G zh=(N66@Bb2)Mn^N21c;6fCTsWleJ<8ANB(LJitVD@pLl)=GX(5b| zqf<-0qY_1%B~RPMJ63y$uIm<^iPmz2IP9*csjadU`jInuuOmHR@#W!%Ntxbm;)xBA z1};EmVBR-(F5c7ZQCfemJ}w-+;`wLNS^5Huuk9l$$_#FTxeOK{o(@I-XrRd4S@O{? zk2`gJ$&e0c?wiqJ2dR$!_FVE9;=+ikN{I%U0z$xr74B49`UDCn@$(3-jW?^Poif^Eq_MEFtH>kF%M}j(p^V!YUmG=#^3L;Z&tOW8RtK;G z&stlb6l#@l1ph^qds^Yw>He8#mg}p=)3Z5+_vClG%^?uMFXBtC^7M_xtWZha*7{JY zBotIMogs81K{bo)xD!s=86)KY+EkoV_r7<^7Ky3~b1L-ewto&y%CgPdiu+VU~dU7KoCoeA4$?I3j6Wn=2FH^!#IeK6E!8+`EnU^lE*QEIu%id+9ny! zh;Ms4TX~H%T5*jIj|07Tpy)r=z^72$+mGKlSq4QsZCG5b;N6JDx z{gS#T3y;QNh@^4JM#LJ;0WdkCzX8jR|6H?kK4?mmcr1>cT7N0zX(sRA1hXOfve#XQ zv|oj?077Sbdlu56W!hfibB$Y6~3Lo4o?|*-V?Gp0%fJKQtjqV$j zT7=9WcA5BR2Ef=gA4!wpvO5RebhwB77NClc`Ga1>_2_89nkv=ry+3@jvy-Uw$9qIS zy3Kg!^WNeMz)i(=Bf_j6}qY?3BY?|!-K9@POyz>(mX^J_UN$rE*?9HtqkgdFQASl4r4S1<$l8M4qg29O{Qstwi%8i zo;O_Uo9~O-4EZ*$nLY!p0-NFjm$0ggdJxOichmBLjh;jsG-2!I$1B4RI0_X|3WwD~ z?adxAvMZ4`xxAAW$y#cg z66;glV50b0+apJR886ljpe#YlVGtmCKAzZmdi1}g{>Q*&P^IyWQ@?!{TNmVU;N`%V zPVm05^?A0E9m;Fr#K@!%_?e`~bpyCl(q!Icp|#wxB})ae`LIemMF3Fj&PsVA#7R%y zzURf)0Aaw%>pYbrr{T*K?S0Yln=F^GZQuq?t$NX#P*5@}gM^hPZL6ut@&Caww%9s5 ztT~=XLFB8r;=1T)R*)gCw*?vYoh&7uodk!GU{N3 zJX~-fMeO?&T{4a78S7@(`JCMi*Hd(CN5RAO-U=*{L-vb}X{zz*oa+-Hv#|f&d|Ri& zkayI1gu(uynW-lFSaK-1u~+=Wd+1YjXdbgT_lLGEXIjp4ZXMf3MuKZg)CeO+6vC)l zuPSSHvjN%f@lrlA>yRjJyS%u(WB@fw_kp$q&~BjNitz}mD0u=V>_)yq1@_ZIor$I` z5p!bTG7|_n5p+0GCr=F+T{kJs>ehC#?x9OkBgzYq4Y|0CK~^*)-d2yK7kTi&6i^w9 zx9+(FHVkCI3EzHO2X4dJgIcHKw1e@F4wMfSX0((zNFc5qs8TZ{AcI9F_Ui}?+jud@ zmn^_YLU4hPo32-@(ThUw<7{8_xd(fpCx$|m5zGpteo4Rk;48nY*HbQT&!?3URVtZb zNK-@h?VINmoduX@UqCNIqTy?7yaLrwkEN0_YyqvSX|5G~?d0O3sM~q}umLG<(I|NU z%Ww)^%nA~>O>u3&=IJCa0J?=l8qP-~JMB9}uX?v*X%5l1ZNSb0lDiBwz*L@%7V!qT z(72qLDFU{OV8ZQ3Alh`Di#GFS@~EjE-#KLo=mgWXr|l;BM|+y@UUNR<$0kBGv-USD z4AI*mzpw?EKRP?MwSOriFPOUc1qGwwFGRiDR-?btHq&V&paAiNP5_e4QW0V`FnT9k zRPi)i>x|JqGL5DA(9d$hgO0+bzlZCe&rcgG3^$tHeU8<-&$1vz{S;~SX%1O~G-2-n z*QK}sL+V`!pH8;*qoyO5767aKpXjW)>a4LVl0 zjU7BZEETCp&VPR1+(*Bnf%stzZY1OE4TU+}VH+_W+D`xQ2eJ(%j_>DK)gH%t=xeD$ zpunaWXtwKVs>pv%vc|ZS&91HSW{p!MYfI91H)?^LP9o8RvCn5hAK-0j)0Aivb=NTo zfx{}3@>yUR-wAG^{Go$UZkHIg^b(r1al+Z8k;Nnx2=M(bQt$R{{#0>nYht;I?MCzR z*q@6SEZ@v7%4fBCdl~Sxl$_*%ZO5rTX2Y2ED9H+@1Gew;z|shXoc^(OJ-#+=r_9J| zFzlsk0OTfc=71?I*J`9D5X6^u!Du?dl47f}Oz zDQZL;K7GNSHYRZdx!WAKxminwD~%#(aeFXhrTCj&pZZ*z)Iay(pw!jpfWLRu<=f2X zqa-M(Ao14@<^GB5(iA0mjW@OY{+qdy!8t*Cu2vl9@K5}#%K(Q!K@H47bgA;3Q^a-> z3??c<1)@EvSVqka0cKzZ6FXED;!>&gcEy)~{U`&kz;Y3)oK9=CQO?-I`>*T0@7A+& zt7)hXFC(>lCqb3KtS?O4*<2UW@KVEpQP^c!v;7OThxG&z;18 z%Wo)1&~?wE9RaW92LwZ}B|65P^)$2hi)c3#tViVJ4H7~1K%b4yybAHRT)A4WP6+T# zIinp!Y1!edVReUs_pL1%kdJR@HEay|=*%&`HZfL%>hn@9g2BR0>Yx4CEW3%iz)0|X zFlzXh`8W{?5IxHfR+DX*??0{I9=rQ2{tl#hOoC5D$QaR$_OU|5W0eNNEVwtXu2a>T zj}+z#KyyU!87b<`nJ1|Vv$jG$@b1cqZ}Lea4f4d~mfXq{`-mbD#N1xS)d)7KHF+vf z0hSq2N;~gRF2qn!#5978(g0I+N^FlC`yXf8t#Gc>q3}#QvR-LjE>EVs0*#gnnE`}a zvm4OFhP2^tfp_C-hFheQBenIvA{>Qu{huXBt;DVe==k#doob55C6yoUj<&e65F0rw zL4*itx6i+G7!a%s3NRv{B%w>edTTGL>Lz|)pLdCHWIkSV~XHUGr9ZON`nltRv|{A;jj6B7kCjXU>|U$D-9 z%hl=(W2Lg8|1u$=P-h2Ig9j!3$!(<5G!q9ZU~jefGVPCf{WJom`0!Fy93|I`9E=?$ zDR`ghR2XKt)}J1wU3i3)tDH7e&e#;l9YCq===2$MRgP~A)==ap_gBw zs(mgQkSNQX_I5M>K>x;V+#YvCdP27oa0*j`z(rxeB`mp5gc9PZr{sc@v;=0Sq4QO*;2P}6!S%S~Oq`9JE0PqEx}?z+1)|VQ>qMcxp~Mf;Ja=vN zb43#;yC3F4F1K9%{>h#sD@P|x%QM%;K1+Cl){#?eqTk*W@7!sAU@SUNC!Q;w;|N59 z-A~n*t}2sMRtIPm4^-jb9tTl3DN`UNmXfb$&+^-5l;jDz?f)QZ%SDk!mj2p5CZLQE zm8n;0j5!HY6nkO7V(?hWJMNmF!N3LyzU^Vd>8Y|0RGeOPY&37R8)Q6eeayK7GQ!AC za3N?pRLg&Nka-;(R=aPx9FQS@K7E@~cxe3gt>m^b?>})! zn>OG|%O+oigT*oab9!qD_bE1BFHy!^@Y6mX`wUJMAq}2}TIBumOv7fa$@6G(gAYlr zi(9bpd6=JkN0q2U^!EAV(EgK6(@_Cg2#^4r#U$>!pP?I6koS8I4=*;C9rG?^`>vXp zN?EfPccy8-(Q?kW<@*l^@g-m&6=ul=HX-hJHFUY6$C%c2S9P%mDzEm!kT1hYo7!_E zA$}1Oblclmirf60Bg1c?AYMz;&6Z6AYyT`iSTd~Nsn~kjnKYppI+%J|r}#^C{=OgH zw2CBni>%0gO`2Z3YeWmC;r4RbX*(APK}G0cC+f%+JSwg_w{YN_qiN`9$;lG8yRVqb z$DGzQUJijB`44m&e+6oQ?^bj}D3+NJ-H(MGiR@s%Y`Z;-RzQdmXmCz|FDt8Bp%-0g zrf%Why&%e}!l49+C(3KCFEh~)fo@j|0ux0k+0y7!#w2Ebx#>f2MM#}zHaY^f{2XCo zPqC{7aRCt=8#8HIFx@kSWE9w>(N8I2E2t#Qs}WXIWJGf)n1@U}M3xaM&YpZkV{zWgzty!Cnc zDBzSle&n>Fmp#XBBLWGP_=jz<*wi{+sQv6TYY{K(emB`0ObzSz4*|9e!}_b?fvm-; z=sJ&m?TtAHQ37W{@?GYOr$n-;3p_S%0k7lk-_?`rcPR%p567K|6}-u1vvN&3zmmWy zpoKL%I2)q5?EP%Hxwr)kSCoIvZzr_x=++qA&tb}l7=FBwliM+@whf9PUx%bndBG6JAy2DaCO!yAj9ypI}|J0h=(H}=7$g?WMLxW>INo3EhHF5|>e`XusJm5x% zqmX*I-7>IY+q?6XnU01K9<+M8(6LI_Czc4GI=G7)D=~Y55HLZf!?@P)@0*adf;}<3URqlm`i?)DI-vgulHOQuz_Ic#NHLeRvGT<3FF0eY2S@ zCD!1~R`MPSR=jepJ8>%WF{alpUzPW3Aa?Pfzc<-F_+b)~EM^I|I8hdPzV$wa9OUOe zp+yYFn#ut7G&1)JrnG?kXEH=p=781HYG|e~cuu11VRff$6?mr3sR?=AjcjPCdC}7g ze#bIaOLdznnd{S7#qhE#D{1j>VQ!_z^|kZLlr?b;$S@v{vR`LbsHckye=f*E#sU{W z3#Xu(P(wA463We*!pzW7(rhv{LnA_wT}JMFtX5764K_>&b?B4*$12$uf=0OYm)UCp zy7Tujpc9Wa^{K&v9vYssv*J-w?&e6~PKxzz5l{`QySeM}T=KHDvx8xFqgm@KPM7fu z>#=mr9niFyTl=fMqeF;=Dp!zI5F$TUN840cm2T*F;LQq%eXrH`8%mTr=JthlGe2jB z;sNfIP}cB#$LRaeAd~(U9^7$`?Tji2LvJOf_)q8VVROb zEJWyD5`k2yuIf7sY-S#)1R6}5f|LM2NKyb(!bDN*+Z`ShGYo_hojHKIIw}97QcwAHngdCTIBoQFEd1IcH(oz^p*?TWQAo5bbQm5S}FE1*tchZusHb) z4(o|Q3P6l;Us(Ai#`q!ao(bqd!=AZxq_#A5lKo5xT?QdsG5!Ds)z=qQqNq5cX+Ma0 zuKwg?#8@_ZaT84?xIl+dQg2`F<~e%g{8|dv!OKh3sYO7J_QdCVz_~4Cy~^Cl%8HYB zG#AF=XV=3eyF^_@E5sAeV`tIB>1p+5`px*=xQ9*rghvnO-ZIjrR5uPET!@b}MyMj{ zXt>QTd}0I!g-9ffs1$0Xk`yVvC?FXJqmrZ!(S$9g#Nx41fUQH(U300k{qa(Oim2Ss zlb;hhDFA!&O0`0APXE39)bMe``w|2U4Adwx_SU6#g#$27F#c`a<7)y4^KMFFg%r%< z;>a*)8EP>od{umVNhn1p!a3ssIG7a`r{r!50suKJQek_N%a)DlX?P}uK+|5TA7bbI z6f7IxlMW7|5Pw<83U$-zM|lx!1}V6hHS+MM5XLN#6ne3pH0z4tjj)ivrBVmI*`)!+fKPW5wjCVSd|;U~Z5DdVfTMs%v5k2W_qJ=qkh z)$V|9NDN#&Z7U9WqwX&`lrb#twIQ#Zb2OlyQkg;=Hhxu*xy6^}xOTI4RmtrN-_`os z&#UVm_#A3#`^tk`P)yv%apXwV9;{fYMz2qg^Sej7w2yjW=_5{6qXNz}_Q!j_^AR}U z7zYuM_x@&)ws;0|vGe)Mla<$fa*l}!s22#woofm6-p@_y-`A)~r#y~?#=%u-5l&}sUyvN1teo3Bhc@LQ=z747xdb37x#ysEb zg{H2W+hNt!#5^92gwoE$ucfrlhE4gs?{_ATDe`;0P9HOq0rb_~D)a!5E}H4pKJO<) z?JmWTH-Dz>{m=J;LwlMy;OY1nBqievwFLQ`Cy=kQ)|=d&*6z6!7Bt7|u?;z-XK9uO zn-qHx^Hur=g4#M;o>qrAc?EcQ1z-Ue3RGH55Y9E%(_)-LD&xqA4ZH@$OsHv#^!j`s z403WdL#O2SdG;W7w|^Q>?>TOPv2@{nQR&8&mRtt2?l@(1XZUZ)lWUxwwYzX_ zx!Rg|&Af!9!RLO0TNc^emol?DEoQeS zfxmjS>#6Gx)XJ)_SA^sZAEtCXow5mtcEI8yZ(IfRw`9QI7LD7z-zvuDA?AG{BKjbBS_!iJA&KyzN@Kg}m1$xIVA@#|nQG8orGm;U28^J#O%D3bNnM z#w<=&>+=bIQ04iKh3)XM?SgH;BMWZkU3~5e`T04T-CMl3(K5W=B`&}`mbTK7*2k?90tc!#(o`T6K}t2?SEyU;7=zuZt&LSH-O@~*i`WIa23hx zu~32OV5@YunxBt%{nKeTsIj@Cbzz5!+0X&`AkV@CBHWhC;xqU4Tv7?Kud>-57rnhY zBO%4;;sEAGYh6bl{8Um0n|Wd_elc zwX+2qfB!9EMj>{Wz4yWZ9ZORcc&5CVRojMs8!5{R4?g?0mEY0baVkY)&I^qT5>-V6 zm@LmS@^bcynBjQ5gMlm_%@Lf#!Z!JrjI=?)AZZy{HS{X(qGoi93Ot4ff|eG25!EJ z+5smIk|6fN@cZNT%GtL3YrW6%8~O%cVC|jE=J0hs#M;MV!4F*U3BIRZ2{yQI&$JDe7yae_ zNA?Kwe!aY^nX7M5Zt&X6celIq;~O$*f<%#CI2kl0I!_qG508b7CL$c9;Az>G_vd{p z*V`T24d<~ONTV0FP5W;F$Lz?+8AYGF$E{K6r%CG{ zVK+80&QsoBveUjxnq41L-;n&6U{)4$m9+N>2{1h*i}|g- z5g5P0O}7(-P=D4A%v60USNXpR=|Avs=7vR+j#*rWdGxDy{_Z)3W2#^6_rw7BC&< zeU(pl z09wwZGn&V0qa%TSLyr+aAU&y9r-+`Q|0J~-B(z%TYjG2G!?18br|8h!LF01-CJQLe zEjdz*_T&MXR_q%XrZ#ES>LM|>45;NkE$0^vxyEqyUW-8x#&bYSOgH+RZWRZXFwM|H zcZBxT9OGBs+6OutQ=X8kot2k+(ZW-A;gu|vYRSik+}gBixCSyl-9|^7!`fu;yclV+ zIP?^>$gjJ>FaZ`_uaBn}&_efL<8Ff;kc9VwDGi!)4UeF+ti3{Re>1o8Ssb1n_e(E4 zl2ZqP=Wx|D@efzuMh#uvR(3fs_r0@vZJ4biDc}z6l@GoS8*C+0hfWZ%MOPjETlG@{SyLFvz=m|WgL)9kdQ1&L zzRs^Noz4O$OUr}dNcWD{uTpbyMXJ7?H9t(~6U7g>C#M~5RP$c$p61;mpSUKDuluij z&*O>w@5r|Jt~ctB;+E(Rx*-?C5Jn{uYqOq><+2Gn%#Chx1P1i^xO1Z|2>elr99Q@h z%bRIx-QV0v8EwxGFsM{w@9!4}2ag0F(?fWZ@3=T|_n?^I*fvrF5a)~;;H+AVDOLZ-O>xS#y0d!dQMcVf#NRxyPfX&;)=7A~bl zIsHW^wn$DuK~2a={EnK4n(!S~iv<8-DPasLPL^VZ1^|3hl@=3Gi-^ciA5BBS9z*CJ zmMTR}*~>SR-EcF2%YX?4Ya_~zh=Fu*tw%SGE=>r;Q36A87aB$Rj*`ehLc+|(_ISW$ zVS?*u>qnX1a;SJo5P=5%@oeb-@|0Nb3nAX(Vd>}U>-5Lt;auCLvF0yE#wWLq*UOXF ztSW@`1!y?`R9^LLIUw*mrnNYJo%)NvHcf<#;b*lwR243+gt^4eX+PGl)%xSod+YY1 zq%%i~T8#2u<{42}!R)0WD_el;u`~QCoM@w+OLzE7VT26N`a-5?wp{z`>4$N9-`14F z=Rc^$!9BfIit&2uJJ4zTc`ZB-n=8aTmo9s?;XDU)rfMAn9L&yom9eVOU#@#?uzfzS zf6IMRhx!#HY+Z!k=sq>6=(o$%q;Ta|5%0BSG*%^Kg_s76q-XnX(nm_LV2AB-N59aZiP7mycI&X= zv%#BFi6X-T!r&kL8X~Fqf$lKhBrKO9g^9u4kKeyB&70$8XryJ?yugUQl0OG&jt5-{ zGb5rlBG$P{`>iQiAx>Uyy*O3ZUZV;YRti-YU;=I)+RsSq#Lg^Xg#MMZ+(=nBu5&UB znO3QSlt>{9b8J0DixAwcKAMF1dpO}9e`^_rI|_lODkhRWK&2Xt*u-~wHgL49~uDh+E}^<6gdlQ&LE}-}+l|N%Li=<>SDLZ2b|V z;PrOLnXN9bQ2o_pV&Lxfcp06u^VwRnJ)z@V<-%IdPp7qvlJ~J&O#pFGrBp4DS07z(vVP#;_POoZJaOha~pjn3o$RWT){FD!g z;Dl4Av1TCsYaF_o5rII00!B(qtQD1@Orm2Nr^Pdx1P0!>&yAE=J4nn7p-WnPITN-l zFpAb_EITNMko6hYAApNt^;2my69zG$kQ5G;c&ByPR$K}$BegJfM~aPwTKK2=KzBE^ z7F{e%EHP`?iqdcza3m;FG*+&_EC6QNwL{OYMZJPk7cVw{Jss~JUy%oPOHrJ&R9%C2 z;$F`D4*F^Y>riHGh>l)wx*l$Y7Ea8TzWihGV^0S}(J)Q$wK| zhVnc@RWNQ9R1rQEYA9H}`Zl;VJOL@3b}cLr7JzAGT@_1Op}&MiCt*HTnW6$W90V1; z|6~wG6H)2fz{cNRuZ6$TXni#Cl|9Q8*I|2DO|cvLB)&)ot|8QOIR5$gelc&0esOEKjdZjiBpC-B`Yk47FT%}}DM+Q);m>@Z|acf`D;o=-MlgyfE)NlsNm<39k z@EXnkYZqkAQBb;X&t^eQ6xpXf1&H=eQK|;VzO=eEoE6_b?=&C$`yqH literal 0 HcmV?d00001 diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.h b/bsp/hpmicro/hpm6750evkmini/rtconfig.h index fec865bbd2..c82acdb500 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.h +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.h @@ -34,7 +34,6 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 #define RT_USING_MEMPOOL #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP @@ -46,8 +45,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50000 -#define RT_USING_HW_ATOMIC +#define RT_VER_NUM 0x50001 /* RT-Thread Components */ @@ -70,6 +68,9 @@ #define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 +/* DFS: device virtual file system */ + + /* Device Drivers */ #define RT_USING_DEVICE_IPC @@ -85,7 +86,14 @@ /* C/C++ and POSIX layer */ -#define RT_LIBC_DEFAULT_TIMEZONE 8 +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* POSIX (Portable Operating System Interface) layer */ @@ -118,6 +126,9 @@ /* Wiced WiFi */ +/* CYW43012 WiFi */ + + /* IoT Cloud */ @@ -187,7 +198,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ @@ -228,7 +239,7 @@ #define BSP_USING_UART #define BSP_USING_UART0 #define BSP_USING_RTC -#define BSP_USING_DRAM +#define BSP_USING_FEMC #define INIT_EXT_RAM_FOR_DATA #endif diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.py b/bsp/hpmicro/hpm6750evkmini/rtconfig.py index 63c7cc149d..77251ab7eb 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.py +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.py @@ -1,4 +1,4 @@ -# Copyright 2021-2022 hpmicro +# Copyright 2021-2023 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os @@ -7,7 +7,6 @@ import sys # toolchains options ARCH='risc-v' CPU='hpmicro' - CHIP_NAME='HPM6750' CROSS_TOOL='gcc' @@ -15,11 +14,32 @@ CROSS_TOOL='gcc' # bsp lib config BSP_LIBRARY_TYPE = None +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + # cross_tool provides the cross compiler -# EXEC_PATH is the compilercute path, for example, CodeSourcery, Keil MDK, IAR +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' if os.getenv('RTT_RISCV_TOOLCHAIN'): @@ -29,8 +49,6 @@ if CROSS_TOOL == 'gcc': else: print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) - - BUILD = 'flash_debug' if PLATFORM == 'gcc': @@ -47,9 +65,8 @@ if PLATFORM == 'gcc': OBJCPY = PREFIX + 'objcopy' STRIP = PREFIX + 'strip' - DEVICE = ' -std=gnu11 -DUSE_NONVECTOR_MODE=1' - ARCH_ABI = ' -mcmodel=medlow ' - CFLAGS = DEVICE + ARCH_ABI + ' -ffunction-sections -fdata-sections -fno-common' + ARCH_ABI = ' -mcmodel=medlow ' + CFLAGS = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' AFLAGS = CFLAGS LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' @@ -81,14 +98,11 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2 -Os' LFLAGS += ' -O2 -Os' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' # module setting - CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' - M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' - M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' - M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ - ' -shared -fPIC -nostartfiles -static-libgcc' + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S deleted file mode 100644 index d84de492f4..0000000000 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2021-2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -.section .vector_table, "a" -.global __vector_table -.align 9 - -__vector_table: - .weak default_isr_trap - .set default_isr_trap, SW_handler - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_HANDLER 11 /* DAC IRQ handler */ - IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_HANDLER 18 /* UART0 IRQ handler */ - IRQ_HANDLER 19 /* UART1 IRQ handler */ - IRQ_HANDLER 20 /* UART2 IRQ handler */ - IRQ_HANDLER 21 /* UART3 IRQ handler */ - IRQ_HANDLER 22 /* UART4 IRQ handler */ - IRQ_HANDLER 23 /* UART5 IRQ handler */ - IRQ_HANDLER 24 /* UART6 IRQ handler */ - IRQ_HANDLER 25 /* UART7 IRQ handler */ - IRQ_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_HANDLER 28 /* PTPC IRQ handler */ - IRQ_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_HANDLER 31 /* TSNS IRQ handler */ - IRQ_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_HANDLER 48 /* SDP IRQ handler */ - IRQ_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_HANDLER 51 /* XDMA IRQ handler */ - IRQ_HANDLER 52 /* HDMA IRQ handler */ - IRQ_HANDLER 53 /* DRAM IRQ handler */ - IRQ_HANDLER 54 /* RNG IRQ handler */ - IRQ_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_HANDLER 57 /* DAO IRQ handler */ - IRQ_HANDLER 58 /* PDM IRQ handler */ - IRQ_HANDLER 59 /* FFA IRQ handler */ - IRQ_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_HANDLER 61 /* USB0 IRQ handler */ - IRQ_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_HANDLER 64 /* PSEC IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PWDG IRQ handler */ - IRQ_HANDLER 67 /* PTMR IRQ handler */ - IRQ_HANDLER 68 /* PUART IRQ handler */ - IRQ_HANDLER 69 /* FUSE IRQ handler */ - IRQ_HANDLER 70 /* SECMON IRQ handler */ - IRQ_HANDLER 71 /* RTC IRQ handler */ - IRQ_HANDLER 72 /* BUTN IRQ handler */ - IRQ_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_HANDLER 74 /* BVIO IRQ handler */ - IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript index 18c366ba28..3e8dd931d3 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript @@ -12,6 +12,7 @@ src = Split(''' if rtconfig.PLATFORM == 'gcc': src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] CPPPATH = [cwd] CPPDEFINES=['D45', rtconfig.CHIP_NAME] diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c index 5d6123bd09..b0bab335d5 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * */ @@ -43,11 +43,19 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __etext[]; extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; extern uint8_t __data_start__[], __data_end__[]; extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,22 +68,28 @@ __attribute__((weak)) void c_startup(void) *(__noncacheable_bss_start__ + i) = 0; } + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); } /* noncacheable init section LMA: etext + data length + ramfunc length */ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); } } diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/port_gcc.S new file mode 100644 index 0000000000..2708b48e45 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S index 16782f98c4..5c47c92afe 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -16,8 +16,15 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer .option pop + /* Enable LMM1 clock */ + la t0, 0xF4000800 + lw t1, 0(t0) + ori t1, t1, 0x80 + sw t1, 0(t0) + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_in_dlm mv sp, t0 @@ -48,6 +55,7 @@ _start: la t0, SW_handler csrw mtvec, t0 + /* System reset handler */ call reset_handler diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S index 555add9927..9e9227b4ad 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c index cb31a6e131..b87eaee524 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -36,12 +36,16 @@ #define IRQ_COP 12 #define IRQ_HOST 13 +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + typedef void (*isr_func_t)(void); static volatile rt_hw_stack_frame_t *s_stack_frame; -static void rt_show_stack_frame(void); - __attribute((weak)) void mchtmr_isr(void) { } @@ -54,141 +58,167 @@ __attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, { } +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + uint32_t exception_handler(uint32_t cause, uint32_t epc) { /* Unhandled Trap */ uint32_t mdcause = read_csr(CSR_MDCAUSE); uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + switch (cause) { case MCAUSE_INSTR_ADDR_MISALIGNED: - rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_INSTR_ACCESS_FAULT: - rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_ILLEGAL_INSTR: - rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); switch (mdcause & 0x07) { case 0: - rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); break; case 1: - rt_kprintf("mdcause: FP disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); break; case 2: - rt_kprintf("mdcause: ACE disabled exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_BREAKPOINT: - rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ADDR_MISALIGNED: - rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); break; case MCAUSE_LOAD_ACCESS_FAULT: - rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); break; case MCAUSE_STORE_AMO_ACCESS_FAULT: - rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); switch (mdcause & 0x07) { case 1: - rt_kprintf("mdcause: ECC/Parity error\r\n"); + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); break; case 2: - rt_kprintf("mdcause: PMP instruction access violation \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); break; case 3: - rt_kprintf("mdcause: BUS error\r\n"); + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); break; case 4: - rt_kprintf("mdcause: Misaligned access \r\n"); + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); break; case 5: - rt_kprintf("mdcause: PMP empty hole access \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); break; case 6: - rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); break; case 7: - rt_kprintf("mdcause: PMA NAMO exception \r\n"); + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); default: - rt_kprintf("mdcause: reserved \r\n"); + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); break; } break; default: - rt_kprintf("Unknown exception happened, cause=%d\n", cause); + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); break; } - rt_show_stack_frame(); - while (1) - { + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { } } -void trap_entry(rt_hw_stack_frame_t *stack_frame); +void trap_entry(void); -void trap_entry(rt_hw_stack_frame_t *stack_frame) +void trap_entry(void) { uint32_t mcause = read_csr(CSR_MCAUSE); uint32_t mepc = read_csr(CSR_MEPC); uint32_t mstatus = read_csr(CSR_MSTATUS); - s_stack_frame = stack_frame; - #if SUPPORT_PFT_ARCH uint32_t mxstatus = read_csr(CSR_MXSTATUS); #endif @@ -272,25 +302,3 @@ void trap_entry(rt_hw_stack_frame_t *stack_frame) write_fcsr(fcsr); #endif } - -static void rt_show_stack_frame(void) -{ - rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); - rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); - rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); - rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); - rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); - rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); - rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); - rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); - rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); - rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); - rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); - rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); - rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); - rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); - rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); - rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); - rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); - rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); -} diff --git a/bsp/hpmicro/libraries/Kconfig b/bsp/hpmicro/libraries/Kconfig index 12f9c7587c..faf5bc5bb4 100644 --- a/bsp/hpmicro/libraries/Kconfig +++ b/bsp/hpmicro/libraries/Kconfig @@ -1,4 +1,4 @@ config SOC_HPM6000_SERIES - bool + bool select ARCH_RISCV32 select ARCH_RISCV_DPU diff --git a/bsp/hpmicro/libraries/drivers/SConscript b/bsp/hpmicro/libraries/drivers/SConscript index a58760f3ad..1eae2a511b 100644 --- a/bsp/hpmicro/libraries/drivers/SConscript +++ b/bsp/hpmicro/libraries/drivers/SConscript @@ -34,6 +34,9 @@ if GetDepend('BSP_USING_GPTMR'): if GetDepend('BSP_USING_CAN'): src += ['drv_can.c'] +if GetDepend('BSP_USING_MCAN'): + src += ['drv_mcan.c'] + if GetDepend('BSP_USING_UART'): if GetDepend(['RT_USING_SERIAL_V2']): src += ['drv_uart_v2.c'] @@ -55,6 +58,9 @@ if GetDepend('BSP_USING_PDM'): if GetDepend('BSP_USING_I2S'): src += ['drv_i2s.c'] +if GetDepend('BSP_USING_MCAN'): + src += ['drv_mcan.c'] + path = [cwd] diff --git a/bsp/hpmicro/libraries/drivers/drv_adc.c b/bsp/hpmicro/libraries/drivers/drv_adc.c index 156869f314..48e3ab5635 100644 --- a/bsp/hpmicro/libraries/drivers/drv_adc.c +++ b/bsp/hpmicro/libraries/drivers/drv_adc.c @@ -1,11 +1,7 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause - * - * Change Logs: - * Date Author Notes - * 2022-05-08 hpmicro the first version */ #include @@ -21,30 +17,52 @@ #endif #include "hpm_sysctl_drv.h" + +typedef struct +{ + bool enabled; +} adc_channel_state_t; + typedef struct { char *adc_name; struct rt_adc_device hpm_adc_device; - uint16_t channel; -#ifdef BSP_USING_ADC12 - ADC12_Type *adc_base; -#endif -#ifdef BSP_USING_ADC16 - ADC16_Type *adc_base; -#endif + bool is_adc12; + bool adc_enabled; + uint32_t adc_base; + adc_channel_state_t chn_state[16]; }hpm_rtt_adc; + + +static uint32_t hpm_adc_init_clock(struct rt_adc_device *device); + +static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled); +static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value); +static rt_uint8_t hpm_get_resolution(struct rt_adc_device *device); +static rt_int16_t hpm_get_vref(struct rt_adc_device *device); + + +static const struct rt_adc_ops hpm_adc_ops = +{ + .enabled = hpm_adc_enabled, + .convert = hpm_get_adc_value, + .get_resolution = hpm_get_resolution, + .get_vref = hpm_get_vref, +}; + + static hpm_rtt_adc hpm_adc_config_tbl[] = { #ifdef BSP_USING_ADC0 { .adc_name = "adc0", #ifdef BSP_USING_ADC12 - .adc_base = HPM_ADC0, -#endif -#ifdef BSP_USING_ADC16 - .adc_base = HPM_ADC0, + .is_adc12 = true, +#else + .is_adc12 = false, #endif + .adc_base = (uint32_t)HPM_ADC0, }, #endif @@ -52,11 +70,11 @@ static hpm_rtt_adc hpm_adc_config_tbl[] = { .adc_name = "adc1", #ifdef BSP_USING_ADC12 - .adc_base = HPM_ADC1, -#endif -#ifdef BSP_USING_ADC16 - .adc_base = HPM_ADC1, + .is_adc12 = true, +#else + .is_adc12 = false, #endif + .adc_base = (uint32_t)HPM_ADC1, }, #endif @@ -64,151 +82,207 @@ static hpm_rtt_adc hpm_adc_config_tbl[] = { .adc_name = "adc2", #ifdef BSP_USING_ADC12 - .adc_base = HPM_ADC2, -#endif -#ifdef BSP_USING_ADC16 - .adc_base = HPM_ADC2, + .is_adc12 = true, +#else + .is_adc12 = false, #endif + .adc_base = (uint32_t)HPM_ADC2, }, #endif #ifdef BSP_USING_ADC3 { .adc_name = "adc3", -#ifdef BSP_USING_ADC12 - .adc_base = HPM_ADC3, -#endif -#ifdef BSP_USING_ADC16 - .adc_base = HPM_ADC3, -#endif + .is_adc12 = false, + .adc_base = (uint32_t)HPM_ADC3, }, #endif }; static uint8_t adc_nums = sizeof(hpm_adc_config_tbl) / sizeof(hpm_rtt_adc); + +static uint32_t hpm_adc_init_clock(struct rt_adc_device *device) +{ + hpm_rtt_adc *hpm_adc; + uint32_t clock_freq = 0; + RT_ASSERT(device != RT_NULL); + hpm_adc = (hpm_rtt_adc *)device->parent.user_data; + +#if defined(ADC12_SOC_MAX_CH_NUM) + if (hpm_adc->is_adc12) + { + clock_freq = board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base); + } else +#endif + { + clock_freq = board_init_adc16_clock((ADC16_Type*)hpm_adc->adc_base); + } + return clock_freq; +} + static rt_err_t init_adc_config(hpm_rtt_adc *adc) { + hpm_stat_t ret; + + if (adc->is_adc12) { #ifdef BSP_USING_ADC12 - adc12_config_t cfg; - hpm_stat_t ret; - - adc12_get_default_config(&cfg); - cfg.res = adc12_res_12_bits; - cfg.conv_mode = adc12_conv_mode_oneshot; - cfg.adc_clk_div = 1; - ret = adc12_init(adc->adc_base, &cfg); - if (ret != status_success) { - return -RT_ERROR; - } + adc12_config_t cfg; + adc12_get_default_config(&cfg); + cfg.res = adc12_res_12_bits; + cfg.conv_mode = adc12_conv_mode_oneshot; + cfg.adc_ahb_en = true; + cfg.adc_clk_div = 3; + ret = adc12_init((ADC12_Type *)adc->adc_base, &cfg); + if (ret != status_success) { + return RT_ERROR; + } #endif - + } else { #ifdef BSP_USING_ADC16 - adc16_config_t cfg; - hpm_stat_t ret; + adc16_config_t cfg; - adc16_get_default_config(&cfg); - cfg.conv_mode = adc16_conv_mode_oneshot; - cfg.adc_clk_div = 3; - cfg.sel_sync_ahb = true; - ret = adc16_init(adc->adc_base, &cfg); - if (ret != status_success) { - return -RT_ERROR; - } + adc16_get_default_config(&cfg); + cfg.conv_mode = adc16_conv_mode_oneshot; + cfg.res = adc16_res_16_bits; + cfg.adc_clk_div = 4; + cfg.sel_sync_ahb = true; + cfg.adc_ahb_en = true; + cfg.wait_dis = 0; + ret = adc16_init((ADC16_Type *)adc->adc_base, &cfg); + if (ret != status_success) { + return RT_ERROR; + } #endif + } return RT_EOK; } -static rt_err_t init_channel_config(hpm_rtt_adc *adc) +static rt_err_t init_channel_config(hpm_rtt_adc *adc, uint16_t channel) { + hpm_stat_t ret; + + if (adc->is_adc12) { #ifdef BSP_USING_ADC12 - adc12_channel_config_t ch_cfg;; - hpm_stat_t ret; + adc12_channel_config_t ch_cfg; - ch_cfg.ch = adc->channel; - ch_cfg.diff_sel = adc12_sample_signal_single_ended; - ch_cfg.sample_cycle = 20; + adc12_get_channel_default_config(&ch_cfg); + ch_cfg.ch = adc->channel; + ch_cfg.diff_sel = adc12_sample_signal_single_ended; + ch_cfg.sample_cycle = 20; - ret = adc12_init_channel(adc->adc_base, &ch_cfg); - if (ret != status_success) { - return -RT_ERROR; - } + ret = adc12_init_channel((ADC12_Type *)adc->adc_base, &ch_cfg); + if (ret != status_success) { + return RT_ERROR; + } #endif - + } else { #ifdef BSP_USING_ADC16 + adc16_channel_config_t ch_cfg; - adc16_channel_config_t ch_cfg;; - hpm_stat_t ret; - - ch_cfg.ch = adc->channel; - ch_cfg.sample_cycle = 20; - - ret = adc16_init_channel(adc->adc_base, &ch_cfg); - if (ret != status_success) { - return -RT_ERROR; - } + adc16_get_channel_default_config(&ch_cfg); + ch_cfg.ch = channel; + ch_cfg.sample_cycle = 20; + ret = adc16_init_channel((ADC16_Type *)adc->adc_base, &ch_cfg); + if (ret != status_success) { + return RT_ERROR; + } #endif + } return RT_EOK; } -static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) { - hpm_rtt_adc *hpm_adc_handler; + hpm_rtt_adc *hpm_adc; rt_err_t ret; RT_ASSERT(device != RT_NULL); - hpm_adc_handler = (hpm_rtt_adc *)device->parent.user_data; - ret = init_adc_config(hpm_adc_handler); - if (ret != RT_EOK) { - return -RT_ERROR; + hpm_adc = (hpm_rtt_adc *)device->parent.user_data; + if (enabled == RT_TRUE) { + if (!hpm_adc->chn_state[channel].enabled) + { + if (!hpm_adc->adc_enabled) + { + (void)hpm_adc_init_clock(device); + ret = init_adc_config(hpm_adc); + if (ret != RT_EOK) { + return RT_ERROR; + } + hpm_adc->adc_enabled = true; + } + hpm_adc->chn_state[channel].enabled = true; + + ret = init_channel_config(hpm_adc, channel); + if (ret != RT_EOK) { + return RT_ERROR; + } + } } - hpm_adc_handler->channel = channel; - ret = init_channel_config(hpm_adc_handler); - if (ret != RT_EOK) { - return -RT_ERROR; + else + { + /* Since the ADC channel cannot be truly disabled, do nothing here */ } return RT_EOK; } -static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) { - hpm_rtt_adc hpm_adc_handler; + hpm_rtt_adc *hpm_adc; rt_err_t ret; rt_uint16_t val; RT_ASSERT(device != RT_NULL); RT_ASSERT(value != RT_NULL); - hpm_adc_handler = *(hpm_rtt_adc *)device->parent.user_data; - hpm_adc_handler.channel = channel; + hpm_adc = (hpm_rtt_adc *)device->parent.user_data; + uint32_t adc_chn = (uint16_t)channel; + if (hpm_adc->is_adc12) { #ifdef BSP_USING_ADC12 - adc12_get_oneshot_result(hpm_adc_handler.adc_base, hpm_adc_handler.channel, &val); - *value = (val >> 4); + adc12_get_oneshot_result((ADC12_Type *)hpm_adc->adc_base, adc_chn, &val); + *value = val; #endif - + } else { #ifdef BSP_USING_ADC16 - adc16_get_oneshot_result(hpm_adc_handler.adc_base, hpm_adc_handler.channel, &val); - *value = val; + hpm_stat_t status = adc16_get_oneshot_result((ADC16_Type *)hpm_adc->adc_base, adc_chn, &val); + *value = val; + // rt_kprintf("%s, status=%d\n", __func__, status); #endif + } return RT_EOK; } -static const struct rt_adc_ops hpm_adc_ops = +static rt_uint8_t hpm_get_resolution(struct rt_adc_device *device) { - .enabled = hpm_adc_enabled, - .convert = hpm_get_adc_value, -}; + hpm_rtt_adc *hpm_adc; + + RT_ASSERT(device != RT_NULL); + hpm_adc = (hpm_rtt_adc *)device->parent.user_data; + if (hpm_adc->is_adc12) { + return 12; + } else { + return 16; + } +} + +static rt_int16_t hpm_get_vref(struct rt_adc_device *device) +{ + return -RT_EIO; +} int rt_hw_adc_init(void) { rt_err_t ret = RT_EOK; for (uint32_t i = 0; i < adc_nums; i++) { - ret = rt_hw_adc_register(&hpm_adc_config_tbl[i].hpm_adc_device, hpm_adc_config_tbl[i].adc_name, &hpm_adc_ops, &hpm_adc_config_tbl[i]); + ret = rt_hw_adc_register(&hpm_adc_config_tbl[i].hpm_adc_device, + hpm_adc_config_tbl[i].adc_name, + &hpm_adc_ops, + &hpm_adc_config_tbl[i]); if (ret != RT_EOK) { - ret = -RT_ERROR; + ret = RT_ERROR; break; } } @@ -216,4 +290,4 @@ int rt_hw_adc_init(void) } INIT_BOARD_EXPORT(rt_hw_adc_init); -#endif +#endif /* BSP_USING_ADC */ diff --git a/bsp/hpmicro/libraries/drivers/drv_adc.h b/bsp/hpmicro/libraries/drivers/drv_adc.h index ab524bfdde..e3f8cc7e42 100644 --- a/bsp/hpmicro/libraries/drivers/drv_adc.h +++ b/bsp/hpmicro/libraries/drivers/drv_adc.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-05-08 hpmicro the first version + * 2022-05-08 HPMicro the first version */ #ifndef LIBRARIES_DRIVERS_DRV_ADC_H_ #define LIBRARIES_DRIVERS_DRV_ADC_H_ diff --git a/bsp/hpmicro/libraries/drivers/drv_can.c b/bsp/hpmicro/libraries/drivers/drv_can.c index 52a8bd0d85..7e4603a802 100644 --- a/bsp/hpmicro/libraries/drivers/drv_can.c +++ b/bsp/hpmicro/libraries/drivers/drv_can.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-05-08 hpmicro the first version + * 2022-05-08 HPMicro the first version + * 2023-05-08 HPMicro Adapt RT-Thread v5.0.0 */ #include @@ -398,7 +399,7 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) RT_ASSERT(filter->count <= CAN_FILTER_NUM_MAX); for (uint32_t i=0; icount; i++) { - drv_can->filter_list[i].index = (filter->items[i].hdr_bank == -1) ? i : filter->items[i].hdr_bank; + drv_can->filter_list[i].index = i; drv_can->filter_list[i].enable = (filter->actived != 0U) ? true : false; drv_can->filter_list[i].code = filter->items[i].id; drv_can->filter_list[i].id_mode = (filter->items[i].ide != 0U) ? can_filter_id_mode_extended_frames : can_filter_id_mode_standard_frames; @@ -699,5 +700,3 @@ int rt_hw_can_init(void) INIT_BOARD_EXPORT(rt_hw_can_init); #endif - - diff --git a/bsp/hpmicro/libraries/drivers/drv_can.h b/bsp/hpmicro/libraries/drivers/drv_can.h index 320248116d..cc528ec510 100644 --- a/bsp/hpmicro/libraries/drivers/drv_can.h +++ b/bsp/hpmicro/libraries/drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/drivers/drv_dao.c b/bsp/hpmicro/libraries/drivers/drv_dao.c index 3ba9096395..eb3e73acff 100644 --- a/bsp/hpmicro/libraries/drivers/drv_dao.c +++ b/bsp/hpmicro/libraries/drivers/drv_dao.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -235,7 +235,7 @@ static rt_ssize_t hpm_dao_transmit(struct rt_audio_device* audio, const void* wr l1c_dc_writeback((uint32_t)writeBuf, size); } - if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config)) { + if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config, true)) { return 0; } @@ -287,4 +287,3 @@ INIT_DEVICE_EXPORT(rt_hw_dao_init); #endif /* BSP_USING_DAO */ - diff --git a/bsp/hpmicro/libraries/drivers/drv_dao.h b/bsp/hpmicro/libraries/drivers/drv_dao.h index 3a7915b2c1..dcd79d66d3 100644 --- a/bsp/hpmicro/libraries/drivers/drv_dao.h +++ b/bsp/hpmicro/libraries/drivers/drv_dao.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.c b/bsp/hpmicro/libraries/drivers/drv_enet.c index 67eb25df2f..538c56621a 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet.c +++ b/bsp/hpmicro/libraries/drivers/drv_enet.c @@ -1,39 +1,33 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021 - 2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-01-11 hpmicro First version - * 2022-07-10 hpmicro Driver optimization for multiple instances + * 2022-01-11 HPMicro First version + * 2022-07-10 HPMicro Driver optimization for multiple instances */ #include #ifdef BSP_USING_ETH #include -#include -#include "board.h" #include "drv_enet.h" -#include "hpm_soc_feature.h" -#include "hpm_enet_soc_drv.h" -#include "hpm_enet_drv.h" - -#define ETH_DEBUG +#include "hpm_otp_drv.h" #ifdef BSP_USING_ETH0 ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) -__RW enet_rx_desc_t enet0_dma_rx_desc_tab[ENET0_RX_BUFF_COUNT] ; /* Ethernet0 Rx DMA Descriptor */ +__RW enet_rx_desc_t enet0_dma_rx_desc_tab[ENET0_RX_BUFF_COUNT]; /* Ethernet0 Rx DMA Descriptor */ ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) -__RW enet_tx_desc_t enet0_dma_tx_desc_tab[ENET0_TX_BUFF_COUNT] ; /* Ethernet0 Tx DMA Descriptor */ +__RW enet_tx_desc_t enet0_dma_tx_desc_tab[ENET0_TX_BUFF_COUNT]; /* Ethernet0 Tx DMA Descriptor */ -ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet0_rx_buff[ENET0_RX_BUFF_COUNT][ENET0_RX_BUFF_SIZE]; /* Ethernet0 Receive Buffer */ -ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet0_tx_buff[ENET0_TX_BUFF_COUNT][ENET0_TX_BUFF_SIZE]; /* Ethernet0 Transmit Buffer */ struct eth_device eth0_dev; @@ -48,11 +42,13 @@ static enet_buff_config_t enet0_tx_buff_cfg = {.buffer = (uint32_t)enet0_tx_buff .size = ENET0_TX_BUFF_SIZE }; -static enet_ptp_time_t ptp_timestamp0 = {0, 0}; -static enet_ptp_config_t ptp_config0 = {.sub_sec_count_res = enet_ptp_count_res_low, +#if __USE_ENET_PTP +static enet_ptp_ts_update_t ptp_timestamp0 = {0, 0}; +static enet_ptp_config_t ptp_config0 = {.timestamp_rollover_mode = enet_ts_dig_rollover_control, .update_method = enet_ptp_time_fine_update, .addend = 0xffffffff, }; +#endif static hpm_enet_t enet0 = {.name = "ETH0", .base = HPM_ENET0, @@ -64,12 +60,18 @@ static hpm_enet_t enet0 = {.name = "ETH0", .tx_buff_cfg = &enet0_tx_buff_cfg, .dma_rx_desc_tab = enet0_dma_rx_desc_tab, .dma_tx_desc_tab = enet0_dma_tx_desc_tab, +#if !BOARD_ENET0_INF + .int_refclk = BOARD_ENET0_INT_REF_CLK, +#else .tx_delay = BOARD_ENET0_TX_DLY, .rx_delay = BOARD_ENET0_RX_DLY, - .ptp_enable = true, +#endif + +#if __USE_ENET_PTP .ptp_clk_src = BOARD_ENET0_PTP_CLOCK, .ptp_config = &ptp_config0, .ptp_timestamp = &ptp_timestamp0 +#endif }; #endif @@ -81,10 +83,10 @@ __RW enet_rx_desc_t enet1_dma_rx_desc_tab[ENET1_RX_BUFF_COUNT]; /* Ethernet1 Rx ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) __RW enet_tx_desc_t enet1_dma_tx_desc_tab[ENET1_TX_BUFF_COUNT]; /* Ethernet1 Tx DMA Descriptor */ -ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet1_rx_buff[ENET1_RX_BUFF_COUNT][ENET1_RX_BUFF_SIZE]; /* Ethernet1 Receive Buffer */ -ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet1_tx_buff[ENET1_TX_BUFF_COUNT][ENET1_TX_BUFF_SIZE]; /* Ethernet1 Transmit Buffer */ struct eth_device eth1_dev; @@ -99,11 +101,13 @@ static enet_buff_config_t enet1_tx_buff_cfg = {.buffer = (uint32_t)enet1_tx_buff .size = ENET1_TX_BUFF_SIZE }; -static enet_ptp_time_t ptp_timestamp1 = {0, 0}; -static enet_ptp_config_t ptp_config1 = {.sub_sec_count_res = enet_ptp_count_res_low, +#if __USE_ENET_PTP +static enet_ptp_ts_update_t ptp_timestamp1 = {0, 0}; +static enet_ptp_config_t ptp_config1 = {.timestamp_rollover_mode = enet_ts_dig_rollover_control, .update_method = enet_ptp_time_fine_update, .addend = 0xffffffff, }; +#endif static hpm_enet_t enet1 = {.name = "ETH1", .base = HPM_ENET1, @@ -115,13 +119,19 @@ static hpm_enet_t enet1 = {.name = "ETH1", .tx_buff_cfg = &enet1_tx_buff_cfg, .dma_rx_desc_tab = enet1_dma_rx_desc_tab, .dma_tx_desc_tab = enet1_dma_tx_desc_tab, +#if !BOARD_ENET1_INF .int_refclk = BOARD_ENET1_INT_REF_CLK, - .ptp_enable = true, +#else + .tx_delay = BOARD_ENET1_TX_DLY, + .rx_delay = BOARD_ENET1_RX_DLY, +#endif + +#if __USE_ENET_PTP .ptp_clk_src = BOARD_ENET1_PTP_CLOCK, .ptp_config = &ptp_config1, .ptp_timestamp = &ptp_timestamp1 +#endif }; - #endif static hpm_enet_t *s_geths[] = { @@ -134,11 +144,31 @@ static hpm_enet_t *s_geths[] = { #endif }; +ATTR_WEAK void enet_get_mac_address(uint8_t *mac) +{ + uint32_t uuid[OTP_SOC_UUID_LEN / sizeof(uint32_t)]; -static hpm_stat_t hpm_enet_init(enet_device *init) + for (int i = 0; i < ARRAY_SIZE(uuid); i++) { + uuid[i] = otp_read_from_shadow(OTP_SOC_UUID_IDX + i); + } + + if (!IS_UUID_INVALID(uuid)) { + uuid[0] &= 0xfc; + memcpy(mac, &uuid, ENET_MAC); + } else { + mac[0] = MAC_ADDR0; + mac[1] = MAC_ADDR1; + mac[2] = MAC_ADDR2; + mac[3] = MAC_ADDR3; + mac[4] = MAC_ADDR4; + mac[5] = MAC_ADDR5; + } +} + +static rt_err_t hpm_enet_init(enet_device *init) { /* Initialize eth controller */ - enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, init->mask, init->dis_mask); + enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, &init->int_config); if (init->media_interface == enet_inf_rmii) { @@ -147,29 +177,37 @@ static hpm_stat_t hpm_enet_init(enet_device *init) enet_rmii_enable_clock(init->instance, init->int_refclk); } +#if ENET_SOC_RGMII_EN /* Set RGMII clock delay */ if (init->media_interface == enet_inf_rgmii) { enet_rgmii_enable_clock(init->instance); enet_rgmii_set_clock_delay(init->instance, init->tx_delay, init->rx_delay); } +#endif - if (init->ptp_enable) - { - /* initialize Ethernet PTP Module */ - init->ptp_config.ssinc = ENET_ONE_SEC_IN_NANOSEC / clock_get_frequency(init->ptp_clk_src); - enet_init_ptp(init->instance, &init->ptp_config); +#if __USE_ENET_PTP + /* initialize PTP Clock */ + board_init_enet_ptp_clock(init->instance); - /* set the initial timestamp */ - enet_set_ptp_timestamp(init->instance, &init->ptp_timestamp); - } + /* initialize Ethernet PTP Module */ + init->ptp_config.ssinc = ENET_ONE_SEC_IN_NANOSEC / clock_get_frequency(init->ptp_clk_src); + enet_init_ptp(init->instance, &init->ptp_config); - /* enable irq */ - intc_m_enable_irq(init->irq_number); + /* set the initial timestamp */ + enet_set_ptp_timestamp(init->instance, &init->ptp_timestamp); +#endif + + /* enable irq */ + intc_m_enable_irq(init->irq_number); + + return RT_EOK; } static rt_err_t rt_hpm_eth_init(rt_device_t dev) { + uint8_t mac[ENET_MAC]; + enet_device *enet_dev = (enet_device *)dev->user_data; /* Initialize GPIOs */ @@ -178,12 +216,25 @@ static rt_err_t rt_hpm_eth_init(rt_device_t dev) /* Reset an enet PHY */ board_reset_enet_phy(enet_dev->instance); - /* Initialize MAC and DMA */ - if (hpm_enet_init(enet_dev) == 0) { - LOG_D("Ethernet control initialize successfully\n"); - } + /* Get MAC address */ + enet_get_mac_address(mac); - return RT_EOK; + /* Set mac0 address */ + enet_dev->mac_config.mac_addr_high[0] = mac[5] << 8 | mac[4]; + enet_dev->mac_config.mac_addr_low[0] = mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]; + enet_dev->mac_config.valid_max_count = 1; + + /* Initialize MAC and DMA */ + if (hpm_enet_init(enet_dev) == 0) + { + LOG_D("Ethernet control initialize successfully\n"); + return RT_EOK; + } + else + { + LOG_D("Ethernet control initialize unsuccessfully\n"); + return RT_ERROR; + } } static rt_err_t rt_hpm_eth_open(rt_device_t dev, rt_uint16_t oflag) @@ -208,22 +259,15 @@ static rt_ssize_t rt_hpm_eth_write(rt_device_t dev, rt_off_t pos, const void * b static rt_err_t rt_hpm_eth_control(rt_device_t dev, int cmd, void * args) { - uint8_t *mac; + uint8_t *mac = (uint8_t *)args; switch (cmd) { case NIOCTL_GADDR: - /* read MAC address */ if (args != NULL) { - mac = (uint8_t *)args; - mac[0] = MAC_ADDR0; - mac[1] = MAC_ADDR1; - mac[2] = MAC_ADDR2; - mac[3] = MAC_ADDR3; - mac[4] = MAC_ADDR4; - mac[5] = MAC_ADDR5; - SMEMCPY(args, mac, 6); + enet_get_mac_address((uint8_t *)mac); + SMEMCPY(args, mac, ENET_MAC); } else { @@ -239,7 +283,7 @@ static rt_err_t rt_hpm_eth_control(rt_device_t dev, int cmd, void * args) static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) { - rt_err_t ret = -RT_ERROR; + rt_err_t ret = RT_ERROR; uint32_t status; enet_device *enet_dev = (enet_device *)dev->user_data; uint32_t tx_buff_size = enet_dev->desc.tx_buff_cfg.size; @@ -255,6 +299,7 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) dma_tx_desc = tx_desc_list_cur; buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1); buffer_offset = 0; + rt_tick_t t_start; /* copy frame from pbufs to driver buffers */ for (q = p; q != NULL; q = q->next) @@ -266,6 +311,16 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) /* Check if the length of data to copy is bigger than Tx buffer size*/ while ((bytes_left_to_copy + buffer_offset) > tx_buff_size) { + /* check DMA own status within timeout */ + t_start = rt_tick_get(); + while (dma_tx_desc->tdes0_bm.own) + { + if (rt_tick_get() - t_start > RT_TICK_PER_SECOND / 100) + { + return ERR_TIMEOUT; + } + } + /* Copy data to Tx buffer*/ SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset), (uint8_t *)((uint8_t *)q->payload + payload_offset), @@ -278,7 +333,7 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) if (dma_tx_desc->tdes0_bm.own != 0) { LOG_E("DMA tx desc buffer is not valid\n"); - return ERR_USE; + return ERR_BUF; } buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1); @@ -289,7 +344,18 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) buffer_offset = 0; } + /* check DMA own status within timeout */ + t_start = rt_tick_get(); + while (dma_tx_desc->tdes0_bm.own) + { + if (rt_tick_get() - t_start > RT_TICK_PER_SECOND / 100) + { + return ERR_TIMEOUT; + } + } + /* Copy the remaining bytes */ + buffer = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset), (uint8_t *)((uint8_t *)q->payload + payload_offset), bytes_left_to_copy); @@ -366,7 +432,7 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) buffer_offset = 0; } /* Copy remaining data in pbuf */ - SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), bytes_left_to_copy); + q->payload = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); buffer_offset = buffer_offset + bytes_left_to_copy; } } @@ -409,7 +475,7 @@ void isr_enet(hpm_enet_t *obj) status = obj->base->DMA_STATUS; if (ENET_DMA_STATUS_GLPII_GET(status)) { - obj->base->DMA_STATUS |= ENET_DMA_STATUS_GLPII_SET(ENET_DMA_STATUS_GLPII_GET(status)); + obj->base->LPI_CSR; } if (ENET_DMA_STATUS_RI_GET(status)) { @@ -436,7 +502,7 @@ SDK_DECLARE_EXT_ISR_M(IRQn_ENET1, isr_enet1) int rt_hw_eth_init(void) { - rt_err_t err = -RT_ERROR; + rt_err_t err = RT_ERROR; for (uint32_t i = 0; i < ARRAY_SIZE(s_geths); i++) { @@ -459,44 +525,43 @@ int rt_hw_eth_init(void) s_geths[i]->enet_dev->desc.rx_buff_cfg.count = s_geths[i]->rx_buff_cfg->count; s_geths[i]->enet_dev->desc.rx_buff_cfg.size = s_geths[i]->rx_buff_cfg->size; - /* Set mac0 address */ - s_geths[i]->enet_dev->mac_config.mac_addr_high[0] = MAC_ADDR5 << 8 | MAC_ADDR4; - s_geths[i]->enet_dev->mac_config.mac_addr_low[0] = MAC_ADDR3 << 24 | MAC_ADDR2 << 16 | MAC_ADDR1 << 8 | MAC_ADDR0; - s_geths[i]->enet_dev->mac_config.valid_max_count = 1; + /* Set DMA PBL */ + s_geths[i]->enet_dev->mac_config.dma_pbl = board_enet_get_dma_pbl(s_geths[i]->base); /* Set instance */ s_geths[i]->enet_dev->instance = s_geths[i]->base; /* Set media interface */ - s_geths[i]->enet_dev->media_interface = s_geths[i]->inf; + s_geths[i]->enet_dev->media_interface = s_geths[i]->inf ? enet_inf_rgmii : enet_inf_rmii; - /* Set refclk */ - s_geths[i]->enet_dev->int_refclk = s_geths[i]->int_refclk; + if (s_geths[i]->enet_dev->media_interface == enet_inf_rmii) + { + /* Set refclk */ + s_geths[i]->enet_dev->int_refclk = s_geths[i]->int_refclk; + } else { + /* Set TX/RX delay */ + s_geths[i]->enet_dev->tx_delay = s_geths[i]->tx_delay; + s_geths[i]->enet_dev->rx_delay = s_geths[i]->rx_delay; + } - /* Set TX delay */ - s_geths[i]->enet_dev->tx_delay = s_geths[i]->tx_delay; - - /* Set RX delay */ - s_geths[i]->enet_dev->rx_delay = s_geths[i]->rx_delay; +#if __USE_ENET_PTP /* Set PTP function */ - s_geths[i]->enet_dev->ptp_enable = s_geths[i]->ptp_enable; s_geths[i]->enet_dev->ptp_clk_src = s_geths[i]->ptp_clk_src; s_geths[i]->enet_dev->ptp_config = *s_geths[i]->ptp_config; s_geths[i]->enet_dev->ptp_timestamp = *s_geths[i]->ptp_timestamp; - +#endif /* Set the interrupt enable mask */ - s_geths[i]->enet_dev->mask = ENET_DMA_INTR_EN_NIE_SET(1) /* Enable normal interrupt summary */ - | ENET_DMA_INTR_EN_RIE_SET(1); /* Enable receive interrupt */ - + s_geths[i]->enet_dev->int_config.int_enable = enet_normal_int_sum_en /* Enable normal interrupt summary */ + | enet_receive_int_en; /* Enable receive interrupt */ /* Set the interrupt disable mask */ - s_geths[i]->enet_dev->dis_mask = ENET_INTR_MASK_RGSMIIIM_SET(1); + + s_geths[i]->enet_dev->int_config.int_mask = enet_rgsmii_int_mask; /* Set the irq number */ s_geths[i]->enet_dev->irq_number = s_geths[i]->irq_num; /* Set the parent parameters */ - s_geths[i]->eth_dev->parent.init = rt_hpm_eth_init; s_geths[i]->eth_dev->parent.open = rt_hpm_eth_open; s_geths[i]->eth_dev->parent.close = rt_hpm_eth_close; diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.h b/bsp/hpmicro/libraries/drivers/drv_enet.h index 4b25be6730..8830980717 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet.h +++ b/bsp/hpmicro/libraries/drivers/drv_enet.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,24 +9,25 @@ #define DRV_ENET_H #include -#include "../../applications/inc/netconf.h" #include "hpm_enet_drv.h" +#include "board.h" typedef struct { ENET_Type * instance; enet_desc_t desc; enet_mac_config_t mac_config; uint8_t media_interface; - uint32_t mask; - uint32_t dis_mask; uint32_t irq_number; bool int_refclk; uint8_t tx_delay; uint8_t rx_delay; + enet_int_config_t int_config; +#if __USE_ENET_PTP bool ptp_enable; uint32_t ptp_clk_src; enet_ptp_config_t ptp_config; - enet_ptp_time_t ptp_timestamp; + enet_ptp_ts_update_t ptp_timestamp; +#endif } enet_device; typedef struct _hpm_enet @@ -45,12 +46,28 @@ typedef struct _hpm_enet uint8_t tx_delay; uint8_t rx_delay; bool int_refclk; +#if __USE_ENET_PTP bool ptp_enable; uint32_t ptp_clk_src; enet_ptp_config_t *ptp_config; - enet_ptp_time_t *ptp_timestamp; + enet_ptp_ts_update_t *ptp_timestamp; +#endif } hpm_enet_t; +#define IS_UUID_INVALID(UUID) (UUID[0] == 0 && \ + UUID[1] == 0 && \ + UUID[2] == 0 && \ + UUID[3] == 0) + +#if ENET_SOC_RGMII_EN +#ifndef ENET0_TX_BUFF_COUNT +#define ENET0_TX_BUFF_COUNT (50U) +#endif + +#ifndef ENET0_RX_BUFF_COUNT +#define ENET0_RX_BUFF_COUNT (60U) +#endif +#else #ifndef ENET0_TX_BUFF_COUNT #define ENET0_TX_BUFF_COUNT (10U) #endif @@ -58,6 +75,7 @@ typedef struct _hpm_enet #ifndef ENET0_RX_BUFF_COUNT #define ENET0_RX_BUFF_COUNT (20U) #endif +#endif #ifndef ENET0_RX_BUFF_SIZE #define ENET0_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE @@ -72,7 +90,7 @@ typedef struct _hpm_enet #endif #ifndef ENET1_RX_BUFF_COUNT -#define ENET1_RX_BUFF_COUNT (20U) +#define ENET1_RX_BUFF_COUNT (30U) #endif #ifndef ENET1_RX_BUFF_SIZE @@ -83,6 +101,30 @@ typedef struct _hpm_enet #define ENET1_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE #endif +#ifndef MAC_ADDR0 +#define MAC_ADDR0 (0x98U) +#endif + +#ifndef MAC_ADDR1 +#define MAC_ADDR1 (0x2CU) +#endif + +#ifndef MAC_ADDR2 +#define MAC_ADDR2 (0xBCU) +#endif + +#ifndef MAC_ADDR3 +#define MAC_ADDR3 (0xB1U) +#endif + +#ifndef MAC_ADDR4 +#define MAC_ADDR4 (0x9FU) +#endif + +#ifndef MAC_ADDR5 +#define MAC_ADDR5 (0x17U) +#endif + int rt_hw_eth_init(void); #endif /* DRV_ENET_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.c b/bsp/hpmicro/libraries/drivers/drv_gpio.c index b6f5b1d76e..887d3a5913 100644 --- a/bsp/hpmicro/libraries/drivers/drv_gpio.c +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.c @@ -1,12 +1,14 @@ /* - * Copyright (c) 2021 hpm + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-01-11 hpmicro First version - * 2022-07-28 hpmicro Fixed compiling warnings + * 2022-01-11 HPMicro First version + * 2022-07-28 HPMicro Fixed compiling warnings + * 2023-05-08 HPMicro Adapt RT-Thread V5.0.0 + * 2023-08-15 HPMicro Enable pad loopback feature */ #include @@ -19,6 +21,7 @@ #include "hpm_gpio_drv.h" #include "hpm_gpiom_drv.h" #include "hpm_clock_drv.h" +#include "hpm_soc_feature.h" typedef struct { @@ -56,7 +59,7 @@ static const gpio_irq_map_t hpm_gpio_irq_map[] = { #endif }; -static struct rt_pin_irq_hdr hpm_gpio_pin_hdr_tbl[IOC_PAD_PZ11]; +static struct rt_pin_irq_hdr hpm_gpio_pin_hdr_tbl[IOC_SOC_PAD_MAX]; static int hpm_get_gpi_irq_num(uint32_t gpio_idx) { @@ -211,6 +214,7 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) /* Invalid mode */ break; } + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; } static rt_int8_t hpm_pin_read(rt_device_t dev, rt_base_t pin) @@ -219,7 +223,7 @@ static rt_int8_t hpm_pin_read(rt_device_t dev, rt_base_t pin) uint32_t gpio_idx = pin >> 5; uint32_t pin_idx = pin & 0x1FU; - return (rt_int8_t) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx); + return (int) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx); } static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) @@ -231,8 +235,11 @@ static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) gpio_write_pin(HPM_GPIO0, gpio_idx, pin_idx, value); } -static rt_err_t hpm_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, - void (*hdr)(void *args), void *args) +static rt_err_t hpm_pin_attach_irq(struct rt_device *device, + rt_base_t pin, + rt_uint8_t mode, + void (*hdr)(void *args), + void *args) { rt_base_t level; @@ -297,7 +304,7 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u } else { - return -RT_EINVAL; + return RT_EINVAL; } return RT_EOK; diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.h b/bsp/hpmicro/libraries/drivers/drv_gpio.h index 87778370b5..17070cb63e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_gpio.h +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c index b03abdd557..6419891456 100644 --- a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c +++ b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -196,7 +196,7 @@ static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim gptmr_channel_config_t config; gptmr_channel_get_default_config(base, &config); - config.cmp[0] = cnt; + config.cmp[0] = 0; config.reload = cnt; timer->mode = mode; @@ -204,7 +204,7 @@ static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim gptmr_channel_config(base, hpm_gptmr->channel, &config, true); gptmr_clear_status(base, 0xFU); - gptmr_enable_irq(base, GPTMR_CH_CMP_IRQ_MASK(0, 0)); + gptmr_enable_irq(base, GPTMR_CH_RLD_IRQ_MASK(hpm_gptmr->channel)); gptmr_channel_update_count(base, hpm_gptmr->channel, 0); gptmr_start_counter(base, hpm_gptmr->channel); @@ -276,4 +276,6 @@ int rt_hw_hwtimer_init(void) return ret; } +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + #endif /* BSP_USING_GPTMR */ diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.h b/bsp/hpmicro/libraries/drivers/drv_hwtimer.h index e04e22ef88..29739f0640 100644 --- a/bsp/hpmicro/libraries/drivers/drv_hwtimer.h +++ b/bsp/hpmicro/libraries/drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/drivers/drv_i2c.c b/bsp/hpmicro/libraries/drivers/drv_i2c.c index 55a148cb75..17b178c033 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2c.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -41,16 +41,16 @@ static struct hpm_i2c hpm_i2cs[] = #endif #if defined(BSP_USING_I2C2) { - .base = HPM_I2C1, - .bus_name = "i2c1", - .clk_name = clock_i2c1, + .base = HPM_I2C2, + .bus_name = "i2c2", + .clk_name = clock_i2c2, }, #endif #if defined(BSP_USING_I2C3) { - .base = HPM_I2C1, - .bus_name = "i2c1", - .clk_name = clock_i2c1, + .base = HPM_I2C3, + .bus_name = "i2c3", + .clk_name = clock_i2c3, }, #endif }; @@ -74,7 +74,7 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct struct hpm_i2c *i2c_info = (struct hpm_i2c *)bus; hpm_stat_t i2c_stat = status_success; - rt_err_t ret = -RT_ERROR; + rt_size_t ret = 0; rt_uint32_t i; for (i = 0; i < num; i++) diff --git a/bsp/hpmicro/libraries/drivers/drv_i2c.h b/bsp/hpmicro/libraries/drivers/drv_i2c.h index 4072da82c7..ef3d4573bc 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2c.h +++ b/bsp/hpmicro/libraries/drivers/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.c b/bsp/hpmicro/libraries/drivers/drv_i2s.c index dbdebfc373..164c788298 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2s.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -154,7 +154,7 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) transfer.sample_rate = 24000U; transfer.protocol = I2S_PROTOCOL_LEFT_JUSTIFIED; transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); /* 1个通道 */ - transfer.audio_depth = I2S_AUDIO_DEPTH_16_BITS; + transfer.audio_depth = i2s_audio_depth_16_bits; transfer.master_mode = true; hpm_audio->transfer = transfer; //将初始参数记录到audio_config @@ -391,7 +391,7 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio //i2s dma方式仅支持采样位宽为：16bit, 32bit assert(hpm_audio->audio_config.samplebits == 16 || hpm_audio->audio_config.samplebits == 32); - hpm_audio->transfer.audio_depth = (hpm_audio->audio_config.samplebits - 16) >> 3; + hpm_audio->transfer.audio_depth = hpm_audio->audio_config.samplebits; if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer)) { @@ -434,7 +434,7 @@ static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream) } if (RT_EOK != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { - return -RT_ERROR; + return RT_ERROR; } } else { return -RT_ERROR; @@ -470,7 +470,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr //支持采样位宽16bit, 32bit uint8_t data_width; uint8_t data_shift_byte; - if (hpm_audio->transfer.audio_depth == I2S_AUDIO_DEPTH_16_BITS) { + if (hpm_audio->transfer.audio_depth == i2s_audio_depth_16_bits) { data_width = DMA_TRANSFER_WIDTH_HALF_WORD; data_shift_byte = 2U ; //16位音频数据位于寄存器的高位 } else { @@ -498,7 +498,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr l1c_dc_writeback((uint32_t)writeBuf, size); } - if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config)) { + if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); return -RT_ERROR; } @@ -516,7 +516,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config)) { + if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); return -RT_ERROR; } @@ -581,4 +581,3 @@ INIT_DEVICE_EXPORT(rt_hw_i2s_init); #endif /* BSP_USING_I2S */ - diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.h b/bsp/hpmicro/libraries/drivers/drv_i2s.h index ff9a369108..8034b1d2f2 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2s.h +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/hpmicro/libraries/drivers/drv_mcan.c b/bsp/hpmicro/libraries/drivers/drv_mcan.c new file mode 100644 index 0000000000..c9dd705757 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_mcan.c @@ -0,0 +1,728 @@ +/* + * Copyright (c) 2021 - 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2023-04-07 HPMicro the first version + */ + +#include +#include +#include +#include "board.h" +#include "hpm_mcan_drv.h" + + +#define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ +#define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ +#define CAN_STD_FILTER_NUM_MAX (128U) /* std Filter number */ +#define CAN_EXT_FILTER_NUM_MAX (64U) /* ext Filter number */ + +#ifdef RT_USING_CAN + +typedef struct _hpm_can_struct +{ + MCAN_Type *can_base; /**< CAN Base address */ + const char *name; /**< CAN device name */ + int32_t irq_num; /**< CAN IRQ index */ + uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */ + mcan_config_t can_config; /**< CAN configuration for IP */ + struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */ + uint32_t irq_txrx_err_enable_mask; /**< CAN TX and RX IRQ Enable Mask */ + uint32_t std_filter_num; /**< std Filter number */ + mcan_filter_elem_t std_can_filters[CAN_STD_FILTER_NUM_MAX]; + uint32_t ext_filter_num; /**< ext Filter number */ + mcan_filter_elem_t ext_can_filters[CAN_EXT_FILTER_NUM_MAX]; +} hpm_can_t; + +static const mcan_filter_elem_t k_default_std_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0U, + /* Don't care if mask is set to all 1s */ + .filter_id = 0U, + /* Accept all messages */ + .filter_mask = 0x7FFU, +}; + +static const mcan_filter_elem_t k_default_ext_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0, + /* Don't care if mask is set to all 1s */ + .filter_id = 0, + /* Accept all messages */ + .filter_mask = 0x1FFFFFFFUL, +}; + + +/** + * @brief Configure CAN controller + * @param [in/out] can CAN device pointer + * @param [in] cfg CAN configuration pointer + * @retval RT_EOK for valid configuration + * @retval -RT_ERROR for invalid configuration + */ +static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg); + +/** + * @brief Control/Get CAN state + * including:interrupt, mode, priority, baudrate, filter, status + * @param [in/out] can CAN device pointer + * @param [in] cmd Control command + * @param [in/out] arg Argument pointer + * @retval RT_EOK for valid control command and arg + * @retval -RT_ERROR for invalid control command or arg + */ +static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg); + +/** + * @brief Send out CAN message + * @param [in] can CAN device pointer + * @param [in] buf CAN message buffer + * @param [in] boxno Mailbox number, it is not used in this porting + * @retval RT_EOK No error + * @retval -RT_ETIMEOUT timeout happened + * @retval -RT_EFULL Transmission buffer is full + */ +static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); + +/** + * @brief Receive message from CAN + * @param [in] can CAN device pointer + * @param [out] buf CAN receive buffer + * @param [in] boxno Mailbox Number, it is not used in this porting + * @retval RT_EOK no error + * @retval -RT_ERROR Error happened during reading receive FIFO + * @retval -RT_EMPTY no data in receive FIFO + */ +static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); + +/** + * @brief Common Interrupt Service routine + * @param [in] hpm_can HPM CAN pointer + */ +static void hpm_mcan_isr(hpm_can_t *hpm_can); + +/** + * @brief Decode data bytes from DLC + * @param [in] dlc Data Length Code + * @return decoded data bytes + */ +static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc); + +#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) +static hpm_can_t dev_can0 = +{ + .can_base = HPM_MCAN0, + .name = "can0", + .irq_num = IRQn_CAN0, + .fifo_index = 0, +}; + +void can0_isr(void) +{ + hpm_mcan_isr(&dev_can0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr); + +#endif + +#if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) +static hpm_can_t dev_can1 = +{ + .can_base = HPM_MCAN1, + .name = "can1", + .irq_num = IRQn_CAN1, + .fifo_index = 1, +}; +void can1_isr(void) +{ + hpm_mcan_isr(&dev_can1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr); +#endif + +#if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) +static hpm_can_t dev_can2 = +{ + .can_base = HPM_MCAN2, + .name = "can2", + .irq_num = IRQn_CAN2, + .fifo_index = 2, +}; +void can2_isr(void) +{ + hpm_mcan_isr(&dev_can2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr); +#endif + +#if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) +static hpm_can_t dev_can3 = +{ + .can_base = HPM_MCAN3, + .name = "can3", + .irq_num = IRQn_CAN3, + .fifo_index = 3, +}; +void can3_isr(void) +{ + hpm_mcan_isr(&dev_can3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr); +#endif + +static hpm_can_t *hpm_cans[] = { +#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) + &dev_can0, +#endif +#if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) + &dev_can1, +#endif +#if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) + &dev_can2, +#endif +#if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) + &dev_can3, +#endif + }; + + +static const struct rt_can_ops hpm_can_ops = { + .configure = hpm_mcan_configure, + .control = hpm_mcan_control, + .sendmsg = hpm_mcan_sendmsg, + .recvmsg = hpm_mcan_recvmsg, +}; + + + +static void hpm_mcan_isr(hpm_can_t *hpm_can) +{ + uint8_t error_flags = mcan_get_last_error_code(hpm_can->can_base); + uint32_t flags = mcan_get_interrupt_flags(hpm_can->can_base); + mcan_error_count_t err_cnt; + /* Transmit completed */ + if ((flags & (MCAN_EVENT_TRANSMIT)) != 0U) { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8)); + } + + /* Data available in FIFO */ + if ((flags & MCAN_EVENT_RECEIVE) != 0) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RX_IND | (hpm_can->fifo_index << 8)); + } + + /* RX FIFO overflow */ + if ((flags & MCAN_INT_RXFIFO0_FULL) != 0U) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); + } + + if ((flags & MCAN_INT_RXFIFO1_FULL) != 0U) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); + } + + /* Error happened on CAN Bus */ + if (((flags & MCAN_EVENT_ERROR) != 0U) || (error_flags != 0U)) + { + mcan_get_error_counter(hpm_can->can_base, &err_cnt); + switch(error_flags) + { + case 3: + hpm_can->can_dev.status.ackerrcnt++; + break; + case 4: + hpm_can->can_dev.status.biterrcnt++; + break; + case 6: + hpm_can->can_dev.status.crcerrcnt++; + break; + case 2: + hpm_can->can_dev.status.formaterrcnt++; + break; + case 1: + hpm_can->can_dev.status.bitpaderrcnt++; + break; + } + + hpm_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count; + hpm_can->can_dev.status.snderrcnt = err_cnt.transmit_error_count; + hpm_can->can_dev.status.lasterrtype = mcan_get_last_error_code(hpm_can->can_base); + hpm_can->can_dev.status.errcode = 0; + if ((error_flags & MCAN_INT_WARNING_STATUS) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRWARNING; + } + if ((error_flags & MCAN_INT_ERROR_PASSIVE) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRPASSIVE; + } + if (mcan_is_in_busoff_state(hpm_can->can_base)) + { + hpm_can->can_dev.status.errcode |= BUSOFF; + } + } + + mcan_clear_interrupt_flags(hpm_can->can_base, flags); +} + +static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg) +{ + RT_ASSERT(can); + RT_ASSERT(cfg); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + +#ifdef RT_CAN_USING_CANFD + drv_can->can_config.enable_canfd = (cfg->enable_canfd != 0) ? true : false; + if (cfg->use_bit_timing != 0U) + { + drv_can->can_config.use_lowlevel_timing_setting = true; + drv_can->can_config.can_timing.prescaler = cfg->can_timing.prescaler; + drv_can->can_config.can_timing.num_seg1 = cfg->can_timing.num_seg1; + drv_can->can_config.can_timing.num_seg2 = cfg->can_timing.num_seg2; + drv_can->can_config.can_timing.num_sjw = cfg->can_timing.num_sjw; + + drv_can->can_config.canfd_timing.prescaler = cfg->canfd_timing.prescaler; + drv_can->can_config.canfd_timing.num_seg1 = cfg->canfd_timing.num_seg1; + drv_can->can_config.canfd_timing.num_seg2 = cfg->canfd_timing.num_seg2; + drv_can->can_config.canfd_timing.num_sjw = cfg->canfd_timing.num_sjw; + } + else +#endif + { + drv_can->can_config.use_lowlevel_timing_setting = false; + drv_can->can_config.baudrate = cfg->baud_rate; +#ifdef RT_CAN_USING_CANFD + drv_can->can_config.baudrate_fd = cfg->baud_rate_fd; +#endif + } + + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + drv_can->can_config.mode = mcan_mode_normal; + break; + case RT_CAN_MODE_LISTEN: + drv_can->can_config.mode = mcan_mode_listen_only; + break; + case RT_CAN_MODE_LOOPBACK: + drv_can->can_config.mode = mcan_mode_loopback_internal; + break; + default: + return -RT_ERROR; + break; + } + + init_can_pins(drv_can->can_base); + uint32_t can_clk = board_init_can_clock(drv_can->can_base); + + drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &drv_can->std_can_filters[0]; + drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = drv_can->std_filter_num; + drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &drv_can->ext_can_filters[0]; + drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = drv_can->ext_filter_num; + drv_can->can_config.all_filters_config.ext_id_mask = (1UL << 30) - 1UL; + + hpm_stat_t status = mcan_init(drv_can->can_base, &drv_can->can_config, can_clk); + if (status != status_success) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + uint32_t arg_val; + rt_err_t err = RT_EOK; + + uint32_t temp; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + arg_val = (uint32_t) arg; + intc_m_disable_irq(drv_can->irq_num); + if (arg_val == RT_DEVICE_FLAG_INT_RX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + } + else if (arg_val == RT_DEVICE_FLAG_INT_TX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + mcan_disable_txbuf_interrupt(drv_can->can_base, ~0UL); + } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { + uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + } else { + err = -RT_ERROR; + } + break; + case RT_DEVICE_CTRL_SET_INT: + arg_val = (uint32_t) arg; + if (arg_val == RT_DEVICE_FLAG_INT_RX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else if (arg_val == RT_DEVICE_FLAG_INT_TX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + mcan_enable_txbuf_interrupt(drv_can->can_base, ~0UL); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else if (arg_val == RT_DEVICE_CAN_INT_ERR) + { + uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else + { + err = -RT_ERROR; + } + break; + case RT_CAN_CMD_SET_FILTER: + { + /* Convert the RT-Thread Filter format to the filter format supported by HPM CAN */ + struct rt_can_filter_config *filter = (struct rt_can_filter_config*)arg; + drv_can->std_filter_num = 0; + drv_can->ext_filter_num = 0; + if (filter != NULL) + { + for (uint32_t i = 0; i < filter->count; i++) + { + if (filter->items[i].ide != 0) + { + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; + drv_can->ext_can_filters[drv_can->ext_filter_num].can_id_type = MCAN_CAN_ID_TYPE_EXTENDED; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_id = filter->items[i].id; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_mask = filter->items[i].mask; + drv_can->ext_filter_num++; + RT_ASSERT(drv_can->ext_filter_num <= CAN_EXT_FILTER_NUM_MAX); + } + else + { + drv_can->std_can_filters[drv_can->std_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; + drv_can->std_can_filters[drv_can->std_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; + drv_can->std_can_filters[drv_can->std_filter_num].can_id_type = MCAN_CAN_ID_TYPE_STANDARD; + drv_can->std_can_filters[drv_can->std_filter_num].filter_id = filter->items[i].id; + drv_can->std_can_filters[drv_can->std_filter_num].filter_mask = filter->items[i].mask; + drv_can->std_filter_num++; + RT_ASSERT(drv_can->std_filter_num <= CAN_STD_FILTER_NUM_MAX); + + } + if (filter->items[i].rtr != 0) + { + if (drv_can->ext_filter_num) + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = true; + } + if (drv_can->std_filter_num) + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = true; + } + } + } + + if (filter->actived != 0U) + { + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + } + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.ext_id_mask = 0x1FFFFFFFUL; + drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &k_default_std_id_filter; + drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = 1; + drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter; + drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = 1; + } + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_MODE: + arg_val = (uint32_t) arg; + if ((arg_val != RT_CAN_MODE_NORMAL) && (arg_val != RT_CAN_MODE_LISTEN) && (arg_val != RT_CAN_MODE_LOOPBACK)) + { + err = -RT_ERROR; + break; + } + if (arg_val != drv_can->can_dev.config.mode) + { + drv_can->can_dev.config.mode = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + + break; + case RT_CAN_CMD_SET_BAUD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.baud_rate) + { + drv_can->can_dev.config.baud_rate = arg_val; + } + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + break; +#ifdef RT_CAN_USING_CANFD + case RT_CAN_CMD_SET_CANFD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.enable_canfd) + { + drv_can->can_dev.config.enable_canfd = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_BAUD_FD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.baud_rate_fd) + { + drv_can->can_dev.config.baud_rate_fd = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_BITTIMING: + { + struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config*)arg; + if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2)) + { + return -RT_ERROR; + } + + if (timing_configs->count != 0U) + { + drv_can->can_dev.config.can_timing = timing_configs->items[0]; + } + if (timing_configs->count == 2) + { + drv_can->can_dev.config.canfd_timing = timing_configs->items[1]; + } + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; +#endif + case RT_CAN_CMD_SET_PRIV: + arg_val = (uint32_t)arg; + if ((arg_val != RT_CAN_MODE_PRIV) && (arg_val != RT_CAN_MODE_NOPRIV)) + { + return -RT_ERROR; + } + if (arg_val != drv_can->can_dev.config.privmode) + { + drv_can->can_dev.config.privmode = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_GET_STATUS: + mcan_error_count_t err_cnt; + mcan_get_error_counter(drv_can->can_base, &err_cnt); + drv_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count; + drv_can->can_dev.status.snderrcnt = err_cnt.transmit_error_count; + drv_can->can_dev.status.lasterrtype = mcan_get_last_error_code(drv_can->can_base); + temp = mcan_get_interrupt_flags(drv_can->can_base); + drv_can->can_dev.status.errcode = 0; + if ((temp & MCAN_INT_WARNING_STATUS) != 0U) + { + drv_can->can_dev.status.errcode |= ERRWARNING; + } + if ((temp & MCAN_INT_ERROR_PASSIVE) != 0U) + { + drv_can->can_dev.status.errcode |= ERRPASSIVE; + } + if (mcan_is_in_busoff_state(drv_can->can_base)) + { + drv_can->can_dev.status.errcode |= BUSOFF; + } + rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); + break; + } +} + +static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + struct rt_can_msg *can_msg = (struct rt_can_msg *) buf; + + mcan_tx_frame_t tx_frame = {0}; + memset(&tx_frame, 0, sizeof(tx_frame)); + if (can_msg->ide == RT_CAN_STDID) + { + tx_frame.use_ext_id = 0; + tx_frame.std_id = can_msg->id; + } + else + { + tx_frame.use_ext_id = 1; + tx_frame.ext_id = can_msg->id; + } + if (can_msg->rtr == RT_CAN_DTR) + { + tx_frame.rtr = false; + } + else + { + tx_frame.rtr = true; + } + + #ifdef RT_CAN_USING_CANFD + if (can_msg->fd_frame != 0) + { + tx_frame.canfd_frame = 1; + tx_frame.bitrate_switch = 1; + RT_ASSERT(can_msg->len <= 15); + } + else + #endif + { + RT_ASSERT(can_msg->len <= 8); + } + + uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len); + for (uint32_t i = 0; i < msg_len; i++) + { + tx_frame.data_8[i] = can_msg->data[i]; + } + tx_frame.dlc = can_msg->len; + + uint32_t delay_cnt = 0; + while (mcan_is_txfifo_full(drv_can->can_base)) + { + rt_thread_mdelay(1); + delay_cnt++; + if (delay_cnt >= CAN_SEND_WAIT_MS_MAX) + { + return -RT_ETIMEOUT; + } + } + hpm_stat_t status = mcan_transmit_via_txbuf_nonblocking(drv_can->can_base, 0, &tx_frame); + if (status != status_success) + { + return -RT_EFULL; + } + + return RT_EOK; +} + +static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + rt_can_msg_t can_msg = (rt_can_msg_t)buf; + mcan_rx_message_t rx_buf; + hpm_stat_t status = mcan_read_rxfifo(drv_can->can_base, 0, &rx_buf); + if (status == status_success) + { + if (rx_buf.use_ext_id) + { + can_msg->ide = RT_CAN_EXTID; + can_msg->id = rx_buf.ext_id; + } + else + { + can_msg->ide = RT_CAN_STDID; + can_msg->id = rx_buf.std_id; + } + + + if (rx_buf.rtr != 0) { + can_msg->rtr = RT_CAN_RTR; + } + else { + can_msg->rtr = RT_CAN_DTR; + } + + can_msg->len = rx_buf.dlc; + uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len); + for(uint32_t i = 0; i < msg_len; i++) { + can_msg->data[i] = rx_buf.data_8[i]; + } + + } + else + { + return -RT_EEMPTY; + } + + return RT_EOK; +} + +int rt_hw_mcan_init(void) +{ + struct can_configure config = CANDEFAULTCONFIG; + config.privmode = RT_CAN_MODE_NOPRIV; + config.sndboxnumber = CAN_SENDBOX_NUM; + config.ticks = 50; + + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) + { + hpm_cans[i]->can_dev.config = config; + hpm_cans[i]->ext_filter_num = 0; + hpm_cans[i]->std_filter_num = 0; + mcan_get_default_config(hpm_cans[i]->can_base, &hpm_cans[i]->can_config); + rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]); + } + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_mcan_init); + +#endif + diff --git a/bsp/hpmicro/libraries/drivers/drv_mcan.h b/bsp/hpmicro/libraries/drivers/drv_mcan.h new file mode 100644 index 0000000000..e5535c7cf0 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_mcan.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRV_MCAN_H +#define DRV_MCAN_H + +int rt_hw_mcan_init(void); + +#endif /* DRV_CAN_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_pdm.c b/bsp/hpmicro/libraries/drivers/drv_pdm.c index 26d9545868..172191bce4 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pdm.c +++ b/bsp/hpmicro/libraries/drivers/drv_pdm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -103,10 +103,8 @@ static rt_err_t hpm_pdm_set_channels(uint32_t channel) mclk_hz = clock_get_frequency(clock_i2s0); i2s_get_default_transfer_config_for_pdm(&transfer); transfer.data_line = I2S_DATA_LINE_0; - if (channel == i2s_mono_left) { + if (channel == 1) { transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); - } else if (channel == i2s_mono_right) { - transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(1); } else if(channel == 2) { transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0) | I2S_CHANNEL_SLOT_MASK(1); } else { @@ -217,7 +215,7 @@ static rt_err_t hpm_pdm_start(struct rt_audio_device* audio, int stream) } if (RT_EOK != hpm_pdm_dma_transmit()) { - return -RT_ERROR; + return RT_ERROR; } } @@ -252,9 +250,9 @@ static rt_err_t hpm_pdm_dma_transmit() ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config)) { + if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); - return -RT_ERROR; + return RT_ERROR; } if (l1c_dc_is_enabled()) { @@ -294,4 +292,3 @@ int rt_hw_pdm_init(void) INIT_DEVICE_EXPORT(rt_hw_pdm_init); #endif /* BSP_USING_PDM */ - diff --git a/bsp/hpmicro/libraries/drivers/drv_pdm.h b/bsp/hpmicro/libraries/drivers/drv_pdm.h index 5f76402b9f..b450d10899 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pdm.h +++ b/bsp/hpmicro/libraries/drivers/drv_pdm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/bsp/hpmicro/libraries/drivers/drv_pwm.c b/bsp/hpmicro/libraries/drivers/drv_pwm.c index 268a917cc5..f8122f68ae 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pwm.c +++ b/bsp/hpmicro/libraries/drivers/drv_pwm.c @@ -1,11 +1,13 @@ /* - * Copyright (c) 2022 hpm + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-01-11 will First version + * 2022-05-09 HPMicro First version + * 2023-04-12 HPMicro Adapt hpm_sdk v1.0.0 + * 2023-05-13 HPMicro Fix compiling error on HPM6360/HPM6200 */ #include @@ -18,12 +20,43 @@ #include "hpm_pwm_drv.h" #include "hpm_clock_drv.h" -static PWM_Type * pwm_base_tbl[4] = {HPM_PWM0, HPM_PWM1, HPM_PWM2, HPM_PWM3}; -static const clock_name_t pwm_clock_tbl[4] = {clock_mot0, clock_mot1, clock_mot2, clock_mot3}; +#ifdef HPM_PWM3 +#define PWM_INSTANCE_NUM 4 +#elif defined(HPM_PWM2) +#define PWM_INSTANCE_NUM 3 +#elif defined(HPM_PWM1) +#define PWM_INSTANCE_NUM 2 +#else +#define PWM_INSTANCE_NUM 1 +#endif + + +static PWM_Type * pwm_base_tbl[PWM_INSTANCE_NUM] = { + HPM_PWM0, +#ifdef HPM_PWM1 + HPM_PWM1, +#endif +#ifdef HPM_PWM2 + HPM_PWM2, +#endif +#ifdef HPM_PWM3 + HPM_PWM3 +#endif + }; +static const clock_name_t pwm_clock_tbl[4] = {clock_mot0, +#if (PWM_INSTANCE_NUM > 1) +clock_mot1, +#endif +#if (PWM_INSTANCE_NUM > 2) +clock_mot2, +#endif +#if (PWM_INSTANCE_NUM > 3) +clock_mot3 +#endif +}; rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) { - uint8_t cmp_index = 0; uint32_t duty; pwm_cmp_config_t cmp_config[4] = {0}; pwm_config_t pwm_config = {0}; @@ -74,8 +107,7 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe if (status_success != pwm_setup_waveform(pwm_name_index, channel, &pwm_config, channel * 2, cmp_config, 2)) { return RT_FALSE; } - pwm_load_cmp_shadow_on_capture(pwm_name_index, cmp_index + 17, 0); - pwm_config_cmp(pwm_name_index, cmp_index + 17, &cmp_config[3]); + pwm_load_cmp_shadow_on_match(pwm_name_index, 17, &cmp_config[3]); pwm_start_counter(pwm_name_index); pwm_issue_shadow_register_lock_event(pwm_name_index); duty = (uint64_t)freq * pulse / 1000000000; @@ -88,7 +120,6 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) { - uint8_t cmp_index = 0; uint32_t duty; pwm_cmp_config_t cmp_config[4] = {0}; pwm_config_t pwm_config = {0}; @@ -107,23 +138,16 @@ rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, ui } pwm_get_default_pwm_config(pwm_name_index, &pwm_config); - pwm_set_reload(pwm_name_index, 0, reload); - cmp_config[3].mode = pwm_cmp_mode_output_compare; cmp_config[3].cmp = reload; cmp_config[3].update_trigger = pwm_shadow_register_update_on_modify; - -// pwm_load_cmp_shadow_on_capture(pwm_name_index, cmp_index + 4, 0); - pwm_config_cmp(pwm_name_index, cmp_index + 4, &cmp_config[3]); - + pwm_config_cmp(pwm_name_index, 17, &cmp_config[3]); pwm_issue_shadow_register_lock_event(pwm_name_index); duty = (uint64_t)freq * pulse / 1000000000; - pwm_update_raw_cmp_central_aligned(pwm_name_index, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1); return RT_TRUE; - } rt_err_t hpm_disable_pwm(uint8_t pwm_index, uint8_t channel) @@ -240,39 +264,56 @@ static struct rt_device hpm_pwm_parent = { .control = hpm_pwm_dev_control }; +#ifdef HPM_PWM0 static struct rt_device_pwm hpm_dev_pwm0 = { .ops = &hpm_pwm_ops, }; +#endif +#ifdef HPM_PWM1 static struct rt_device_pwm hpm_dev_pwm1 = { .ops = &hpm_pwm_ops, }; +#endif +#ifdef HPM_PWM2 static struct rt_device_pwm hpm_dev_pwm2 = { .ops = &hpm_pwm_ops, }; +#endif +#ifdef HPM_PWM3 static struct rt_device_pwm hpm_dev_pwm3 = { .ops = &hpm_pwm_ops, }; +#endif int rt_hw_pwm_init(void) { int ret = RT_EOK; + +#ifdef HPM_PWM0 hpm_dev_pwm0.parent = hpm_pwm_parent; - hpm_dev_pwm1.parent = hpm_pwm_parent; - hpm_dev_pwm2.parent = hpm_pwm_parent; - hpm_dev_pwm3.parent = hpm_pwm_parent; ret = rt_device_pwm_register(&hpm_dev_pwm0, "pwm0", &hpm_pwm_ops, RT_NULL); +#endif + +#ifdef HPM_PWM1 + hpm_dev_pwm1.parent = hpm_pwm_parent; ret = rt_device_pwm_register(&hpm_dev_pwm1, "pwm1", &hpm_pwm_ops, RT_NULL); +#endif +#ifdef HPM_PWM2 + hpm_dev_pwm2.parent = hpm_pwm_parent; ret = rt_device_pwm_register(&hpm_dev_pwm2, "pwm2", &hpm_pwm_ops, RT_NULL); +#endif +#ifdef HPM_PWM3 + hpm_dev_pwm3.parent = hpm_pwm_parent; ret = rt_device_pwm_register(&hpm_dev_pwm3, "pwm3", &hpm_pwm_ops, RT_NULL); +#endif return ret; } INIT_BOARD_EXPORT(rt_hw_pwm_init); -#endif /* BSP_USING_GPIO */ - +#endif /* BSP_USING_PWM */ diff --git a/bsp/hpmicro/libraries/drivers/drv_pwm.h b/bsp/hpmicro/libraries/drivers/drv_pwm.h index 8a99e11989..badbb0da0e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pwm.h +++ b/bsp/hpmicro/libraries/drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/drivers/drv_rtc.c b/bsp/hpmicro/libraries/drivers/drv_rtc.c index a70d27ada1..3c75ff9ecc 100644 --- a/bsp/hpmicro/libraries/drivers/drv_rtc.c +++ b/bsp/hpmicro/libraries/drivers/drv_rtc.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2021-09-19 HPMICRO First version + * 2021-09-19 HPMicro First version + * 2023-05-08 HPMicro Adapt RT-Thread V5.0.0 */ #include "board.h" #include "drv_rtc.h" @@ -37,8 +38,8 @@ static int hpm_rtc_set_timestamp(time_t timestamp); * Variables * ******************************************************************************************/ -static struct rt_device hpm_rtc= { - .type = RT_Device_Class_RTC, +#ifdef RT_USING_DEVICE_OPS +const struct rt_device_ops hpm_rtc_ops = { .init = hpm_rtc_init, .open = hpm_rtc_open, .close = hpm_rtc_close, @@ -46,6 +47,20 @@ static struct rt_device hpm_rtc= { .write = hpm_rtc_write, .control = hpm_rtc_control, }; +#endif +static struct rt_device hpm_rtc= { + .type = RT_Device_Class_RTC, +#ifdef RT_USING_DEVICE_OPS + .ops = &hpm_rtc_ops, +#else + .init = hpm_rtc_init, + .open = hpm_rtc_open, + .close = hpm_rtc_close, + .read = hpm_rtc_read, + .write = hpm_rtc_write, + .control = hpm_rtc_control, +#endif +}; /******************************************************************************************* * @@ -86,7 +101,7 @@ static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args) hpm_rtc_set_timestamp(*(time_t *)args); break; default: - err = -RT_EINVAL; + err = RT_EINVAL; break; } diff --git a/bsp/hpmicro/libraries/drivers/drv_rtc.h b/bsp/hpmicro/libraries/drivers/drv_rtc.h index b92d446924..64bcff898e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_rtc.h +++ b/bsp/hpmicro/libraries/drivers/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,4 +14,4 @@ int rt_hw_rtc_init(void); -#endif /* DRV_RTC_H */ \ No newline at end of file +#endif /* DRV_RTC_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.c b/bsp/hpmicro/libraries/drivers/drv_sdio.c index e8a2250147..ff892f1807 100644 --- a/bsp/hpmicro/libraries/drivers/drv_sdio.c +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.c @@ -1,12 +1,14 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-02-23 hpmicro First version - * 2022-07-19 hpmicro Fixed the multi-block read/write issue + * 2022-02-23 HPMicro First version + * 2022-07-19 HPMicro Fixed the multi-block read/write issue + * 2023-07-27 HPMicro Fixed clock setting issue + * 2023-08-02 HPMicro Add speed mode setting */ #include @@ -25,8 +27,8 @@ #define SDXC_AMDA2_ADDR_ALIGN (4U) #define SDXC_DATA_TIMEOUT (0xFU) -#define SDXC_CACHELINE_ALIGN_DOWN(x) ((uint32_t)(x) & ~((uint32_t)(CACHE_LINESIZE) - 1UL)) -#define SDXC_CACHELINE_ALIGN_UP(x) SDXC_CACHELINE_ALIGN_DOWN((uint32_t)(x) + (uint32_t)(CACHE_LINESIZE) - 1U) +#define SDXC_CACHELINE_ALIGN_DOWN(x) HPM_L1C_CACHELINE_ALIGN_DOWN(x) +#define SDXC_CACHELINE_ALIGN_UP(x) HPM_L1C_CACHELINE_ALIGN_UP(x) #define SDXC_IS_CACHELINE_ALIGNED(n) ((uint32_t)(n) % (uint32_t)(CACHE_LINESIZE) == 0U) struct hpm_mmcsd @@ -34,20 +36,26 @@ struct hpm_mmcsd struct rt_mmcsd_host *host; struct rt_mmcsd_req *req; struct rt_mmcsd_cmd *cmd; - struct rt_timer *timer; - rt_uint32_t *buf; - SDXC_Type *sdxc_base; int32_t irq_num; uint32_t *sdxc_adma2_table; + + uint8_t power_mode; + uint8_t bus_width; + uint8_t timing; + uint8_t bus_mode; + uint32_t freq; + }; static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en); static void hpm_sdmmc_host_recovery(SDXC_Type *base); +static int hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); + static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = { @@ -60,43 +68,68 @@ static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = /* Place the ADMA2 table to non-cacheable region */ ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc_adma2_table[SDXC_ADMA_TABLE_WORDS]; + +static int hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) +{ + hpm_stat_t status; + sdxc_command_t *cmd = xfer->command; + sdxc_data_t *data = xfer->data; + status = sdxc_transfer_nonblocking(base, dma_config, xfer); + if (status != status_success) + { + return -RT_ERROR; + } + /* Wait until idle */ + volatile uint32_t interrupt_status = sdxc_get_interrupt_status(base); + while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_COMPLETE_MASK)) + { + interrupt_status = sdxc_get_interrupt_status(base); + status = sdxc_parse_interrupt_status(base); + HPM_BREAK_IF(status != status_success); + } + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_CMD_COMPLETE_MASK); + if (status == status_success) + { + status = sdxc_receive_cmd_response(base, cmd); + } + if ((status == status_success) && (data != RT_NULL)) + { + interrupt_status = sdxc_get_interrupt_status(base); + while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_STS_ERROR)) + { + interrupt_status = sdxc_get_interrupt_status(base); + status = sdxc_parse_interrupt_status(base); + HPM_BREAK_IF(status != status_success); + } + } + + return (status == status_success) ? RT_EOK : -RT_ERROR; +} + /** * !@brief SDMMC request implementation based on HPMicro SDXC Host */ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - struct hpm_mmcsd *mmcsd; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(req != RT_NULL); + RT_ASSERT(req->cmd != RT_NULL); + sdxc_adma_config_t adma_config = { 0 }; sdxc_xfer_t xfer = { 0 }; sdxc_command_t sdxc_cmd = { 0 }; sdxc_data_t sdxc_data = { 0 }; uint32_t *aligned_buf = NULL; hpm_stat_t err = status_invalid_argument; - - RT_ASSERT(host != RT_NULL); - RT_ASSERT(host->private_data != RT_NULL); - RT_ASSERT(req != RT_NULL); - RT_ASSERT(req->cmd != RT_NULL); - - mmcsd = (struct hpm_mmcsd *) host->private_data; - - cmd = req->cmd; - - data = cmd->data; + struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; + struct rt_mmcsd_cmd *cmd = req->cmd; + struct rt_mmcsd_data *data = cmd->data; /*　configure command　*/ sdxc_cmd.cmd_index = cmd->cmd_code; sdxc_cmd.cmd_argument = cmd->arg; - if (cmd->cmd_code == STOP_TRANSMISSION) - { - sdxc_cmd.cmd_type = sdxc_cmd_type_abort_cmd; - } - else - { - sdxc_cmd.cmd_type = sdxc_cmd_type_normal_cmd; - } + sdxc_cmd.cmd_type = (cmd->cmd_code == STOP_TRANSMISSION) ? sdxc_cmd_type_abort_cmd : sdxc_cmd_type_normal_cmd; switch (cmd->flags & RESP_MASK) { @@ -156,7 +189,7 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r { write_size = SDXC_CACHELINE_ALIGN_UP(write_size); aligned_buf = (uint32_t *) rt_malloc_align(write_size, CACHE_LINESIZE); - memcpy(aligned_buf, data->buf, write_size); + rt_memcpy(aligned_buf, data->buf, write_size); sdxc_data.tx_data = aligned_buf; rt_enter_critical(); l1c_dc_flush((uint32_t) sdxc_data.tx_data, write_size); @@ -188,8 +221,6 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r sdxc_data.tx_data = NULL; } xfer.data = &sdxc_data; - - } else { @@ -201,17 +232,17 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r xfer.data->enable_auto_cmd12 = true; } - err = sdxc_transfer_blocking(mmcsd->sdxc_base, &adma_config, &xfer); + err = hpm_sdmmc_transfer(mmcsd->sdxc_base, &adma_config, &xfer); LOG_I("cmd=%d, arg=%x\n", cmd->cmd_code, cmd->arg); if (err != status_success) { hpm_sdmmc_host_recovery(mmcsd->sdxc_base); - LOG_E(" ***sdxc_transfer_blocking error: %d*** -->\n", err); + LOG_E(" ***hpm_sdmmc_transfer error: %d*** -->\n", err); cmd->err = -RT_ERROR; } else { - LOG_I(" ***sdxc_transfer_blocking passed: %d*** -->\n", err); + LOG_I(" ***hpm_sdmmc_transfer passed: %d*** -->\n", err); if (sdxc_cmd.resp_type == sdxc_dev_resp_r2) { LOG_I("resp:0x%08x 0x%08x 0x%08x 0x%08x\n", sdxc_cmd.response[0], @@ -221,7 +252,6 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r { LOG_I("resp:0x%08x\n", sdxc_cmd.response[0]); } - } if ((sdxc_data.rx_data != NULL) && (cmd->err == RT_EOK)) { @@ -232,7 +262,7 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r rt_enter_critical(); l1c_dc_invalidate((uint32_t) aligned_buf, aligned_read_size); rt_exit_critical(); - memcpy(data->buf, aligned_buf, read_size); + rt_memcpy(data->buf, aligned_buf, read_size); } else { @@ -268,22 +298,35 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r */ static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - struct hpm_mmcsd *mmcsd; - uint32_t sdxc_clk; - uint32_t vdd; - RT_ASSERT(host != RT_NULL);RT_ASSERT(host->private_data != RT_NULL);RT_ASSERT(io_cfg != RT_NULL); + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(io_cfg != RT_NULL); - mmcsd = (struct hpm_mmcsd *) host->private_data; + struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; + uint32_t vdd = io_cfg->vdd; + if (io_cfg->power_mode != mmcsd->power_mode) + { + switch(io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + board_sd_power_switch(mmcsd->sdxc_base, false); + break; + case MMCSD_POWER_ON: + board_sd_power_switch(mmcsd->sdxc_base, true); + break; + case MMCSD_POWER_UP: + board_sd_power_switch(mmcsd->sdxc_base, false); + rt_thread_mdelay(10); + board_sd_power_switch(mmcsd->sdxc_base, true); + break; + default: + /* Do nothing */ + break; + } + mmcsd->power_mode = io_cfg->power_mode; + } - vdd = io_cfg->vdd; - - static bool has_init = false; - - init_sdxc_pins(mmcsd->sdxc_base, false); - - uint32_t sdxc_clock = io_cfg->clock; - - if (sdxc_clock != 0U) + if (mmcsd->bus_width != io_cfg->bus_width) { switch (io_cfg->bus_width) { @@ -297,17 +340,68 @@ static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_c sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_1bit); break; } - board_sd_configure_clock(mmcsd->sdxc_base, sdxc_clk); + mmcsd->bus_width = io_cfg->bus_width; + } + + if (mmcsd->timing != io_cfg->timing) + { + switch (io_cfg->timing) + { + case MMCSD_TIMING_LEGACY: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_normal); + break; + case MMCSD_TIMING_SD_HS: + case MMCSD_TIMING_MMC_HS: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_high); + break; + case MMCSD_TIMING_UHS_SDR12: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_sdr12); + break; + case MMCSD_TIMING_UHS_SDR25: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_sdr25); + break; + case MMCSD_TIMING_UHS_SDR50: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_sdr50); + break; + case MMCSD_TIMING_UHS_SDR104: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_sdr104); + break; + case MMCSD_TIMING_UHS_DDR50: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_sd_speed_ddr50); + break; + case MMCSD_TIMING_MMC_DDR52: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_emmc_speed_high_speed_ddr); + break; + case MMCSD_TIMING_MMC_HS200: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_emmc_speed_hs200); + break; + case MMCSD_TIMING_MMC_HS400: + sdxc_set_speed_mode(mmcsd->sdxc_base, sdxc_emmc_speed_hs400); + break; + } + mmcsd->timing = io_cfg->timing; + } + + board_init_sd_pins(mmcsd->sdxc_base); + uint32_t sdxc_clock = io_cfg->clock; + if (sdxc_clock != 0U) + { + if (mmcsd->freq != sdxc_clock) + { + /* Ensure request frequency from mmcsd stack level doesn't exceed maximum supported frequency by host */ + uint32_t clock_freq = MIN(mmcsd->host->freq_max, sdxc_clock); + board_sd_configure_clock(mmcsd->sdxc_base, clock_freq); + mmcsd->freq = sdxc_clock; + } } - rt_thread_mdelay(5); } static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en) { - RT_ASSERT(host != RT_NULL);RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; - if (en != 0) { intc_m_enable_irq_with_priority(mmcsd->irq_num, 1); diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.h b/bsp/hpmicro/libraries/drivers/drv_sdio.h index 12bb738388..64f81f6a54 100644 --- a/bsp/hpmicro/libraries/drivers/drv_sdio.h +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021 - 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,4 +9,4 @@ int rt_hw_sdio_init(void); -#endif /* DRV_SDIO_H */ \ No newline at end of file +#endif /* DRV_SDIO_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_spi.c b/bsp/hpmicro/libraries/drivers/drv_spi.c index 55f91d3c38..cf033e345c 100644 --- a/bsp/hpmicro/libraries/drivers/drv_spi.c +++ b/bsp/hpmicro/libraries/drivers/drv_spi.c @@ -1,8 +1,13 @@ /* - * Copyright (c) 2021 hpm + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * + * Change Logs: + * Date Author Notes + * 2022-02-01 HPMicro First version + * 2023-02-15 HPMicro Add DMA support + * 2023-07-14 HPMicro Manage the DMA buffer alignment in driver */ #include @@ -12,6 +17,11 @@ #include "drv_spi.h" #include "hpm_spi_drv.h" #include "hpm_sysctl_drv.h" +#include "hpm_dma_manager.h" +#include "hpm_dmamux_drv.h" + +#include "hpm_l1c_drv.h" + struct hpm_spi { @@ -21,11 +31,15 @@ struct hpm_spi spi_control_config_t control_config; struct rt_spi_bus spi_bus; rt_sem_t xfer_sem; - /* TODO: add DMA support later */ + rt_bool_t enable_dma; + rt_uint8_t tx_dmamux; + rt_uint8_t rx_dmamux; + hpm_dma_resource_t tx_dma; + hpm_dma_resource_t rx_dma; }; static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg); -static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg); +static rt_ssize_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg); static struct hpm_spi hpm_spis[] = { @@ -33,24 +47,36 @@ static struct hpm_spi hpm_spis[] = { .bus_name = "spi0", .spi_base = HPM_SPI0, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI0_TX, + .rx_dmamux = HPM_DMA_SRC_SPI0_RX, }, #endif #if defined(BSP_USING_SPI1) { .bus_name = "spi1", .spi_base = HPM_SPI1, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI1_TX, + .rx_dmamux = HPM_DMA_SRC_SPI1_RX, }, #endif #if defined(BSP_USING_SPI2) { .bus_name = "spi2", .spi_base = HPM_SPI2, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI2_TX, + .rx_dmamux = HPM_DMA_SRC_SPI2_RX, }, #endif #if defined(BSP_USING_SPI3) { .bus_name = "spi3", .spi_base = HPM_SPI3, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI3_TX, + .rx_dmamux = HPM_DMA_SRC_SPI3_RX, }, #endif }; @@ -73,7 +99,7 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co if (cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) { - return -RT_EINVAL; + return RT_EINVAL; } spi_master_get_default_timing_config(&timing_config); @@ -108,24 +134,13 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co return RT_EOK; } -static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg) + + +static hpm_stat_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_spi_message *msg) { - RT_ASSERT(device != RT_NULL); - RT_ASSERT(msg != RT_NULL); - RT_ASSERT(device->bus != RT_NULL); - RT_ASSERT(device->bus->parent.user_data != RT_NULL); - - cs_ctrl_callback_t cs_pin_control = (cs_ctrl_callback_t) device->parent.user_data; - struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); - hpm_stat_t spi_stat = status_success; - if ((cs_pin_control != NULL) && msg->cs_take) - { - cs_pin_control(SPI_CS_TAKE); - } - uint32_t remaining_size = msg->length; uint32_t transfer_len; uint8_t *tx_buf = (uint8_t*) msg->send_buf; @@ -133,33 +148,30 @@ static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess while (remaining_size > 0) { transfer_len = MIN(512, remaining_size); + spi->control_config.common_config.tx_dma_enable = false; + spi->control_config.common_config.rx_dma_enable = false; if (msg->send_buf != NULL && msg->recv_buf != NULL) { spi->control_config.common_config.trans_mode = spi_trans_write_read_together; - spi_stat = spi_transfer(spi->spi_base, - &spi->control_config, - NULL, - NULL, - tx_buf, transfer_len, - rx_buf, transfer_len); + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, + NULL, + NULL, tx_buf, transfer_len, rx_buf, transfer_len); } else if (msg->send_buf != NULL) { spi->control_config.common_config.trans_mode = spi_trans_write_only; spi_stat = spi_transfer(spi->spi_base, &spi->control_config, - NULL, - NULL, - (uint8_t*) tx_buf, transfer_len, - NULL, 0); + NULL, + NULL, (uint8_t*) tx_buf, transfer_len, + NULL, 0); } else { spi->control_config.common_config.trans_mode = spi_trans_read_only; spi_stat = spi_transfer(spi->spi_base, &spi->control_config, - NULL, - NULL, - NULL, 0, - rx_buf, transfer_len); + NULL, + NULL, + NULL, 0, rx_buf, transfer_len); } if (spi_stat != status_success) @@ -177,6 +189,245 @@ static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess } remaining_size -= transfer_len; } + + return spi_stat; +} + +hpm_stat_t spi_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t src, uint8_t data_width, uint32_t size) +{ + dma_handshake_config_t config; + config.ch_index = ch_num; + config.dst = (uint32_t)&spi_ptr->DATA; + config.dst_fixed = true; + config.src = src; + config.src_fixed = false; + config.data_width = data_width; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config, true); +} + +hpm_stat_t spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, uint8_t data_width, uint32_t size) +{ + dma_handshake_config_t config; + config.ch_index = ch_num; + config.dst = dst; + config.dst_fixed = false; + config.src = (uint32_t)&spi_ptr->DATA; + config.src_fixed = true; + config.data_width = data_width; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config, true); +} + + +static hpm_stat_t hpm_spi_wait_idle(SPI_Type *ptr) +{ + hpm_stat_t status = status_success; + rt_tick_t start_tick = rt_tick_get(); + while(ptr->STATUS & SPI_STATUS_SPIACTIVE_MASK) + { + if ((rt_tick_get() - start_tick) > RT_TICK_PER_SECOND) + { + status = status_timeout; + break; + } + } + return status; +} + +static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_message *msg) +{ + struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); + hpm_stat_t spi_stat = status_success; + uint32_t remaining_size = msg->length; + uint32_t transfer_len; + uint8_t *raw_alloc_tx_buf = RT_NULL; + uint8_t *raw_alloc_rx_buf = RT_NULL; + uint8_t *aligned_tx_buf = RT_NULL; + uint8_t *aligned_rx_buf = RT_NULL; + uint32_t aligned_len = 0; + if (msg->length > 0) + { + aligned_len = (msg->length + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); + if (msg->send_buf != RT_NULL) + { + if (l1c_dc_is_enabled()) + { + /* The allocated pointer is always RT_ALIGN_SIZE aligned */ + raw_alloc_tx_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); + RT_ASSERT(raw_alloc_tx_buf != RT_NULL); + aligned_tx_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_tx_buf); + rt_memcpy(aligned_tx_buf, msg->send_buf, msg->length); + l1c_dc_flush((uint32_t) aligned_tx_buf, aligned_len); + } + else + { + aligned_tx_buf = (uint8_t*) msg->send_buf; + } + } + if (msg->recv_buf != RT_NULL) + { + if (l1c_dc_is_enabled()) + { + /* The allocated pointer is always RT_ALIGN_SIZE aligned */ + raw_alloc_rx_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); + RT_ASSERT(raw_alloc_rx_buf != RT_NULL); + aligned_rx_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_rx_buf); + } + else + { + aligned_rx_buf = msg->recv_buf; + } + } + } + uint8_t *tx_buf = aligned_tx_buf; + uint8_t *rx_buf = aligned_rx_buf; + + uint32_t core_id = read_csr(CSR_MHARTID); + spi->spi_base->CTRL &= ~(SPI_CTRL_TXDMAEN_MASK | SPI_CTRL_RXDMAEN_MASK); + while (remaining_size > 0) + { + transfer_len = MIN(512, remaining_size); + spi->control_config.common_config.tx_dma_enable = false; + spi->control_config.common_config.rx_dma_enable = false; + if (msg->send_buf != NULL && msg->recv_buf != NULL) + { + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + spi->control_config.common_config.tx_dma_enable = true; + spi->control_config.common_config.rx_dma_enable = true; + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, + transfer_len); + if (spi_stat != status_success) + { + break; + } + + dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); + spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + + /* setup spi rx trigger dma transfer*/ + dmamux_config(HPM_DMAMUX, spi->rx_dma.channel, spi->rx_dmamux, true); + spi_stat = spi_rx_trigger_dma(spi->rx_dma.base, spi->rx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) rx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + if (spi_stat != status_success) + { + break; + } + } + else if (msg->send_buf != NULL) + { + spi->control_config.common_config.tx_dma_enable = true; + spi->control_config.common_config.trans_mode = spi_trans_write_only; + spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, 0); + if (spi_stat != status_success) + { + break; + } + + dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); + spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + if (spi_stat != status_success) + { + break; + } + } + else + { + spi->control_config.common_config.rx_dma_enable = true; + spi->control_config.common_config.trans_mode = spi_trans_read_only; + spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, 0, transfer_len); + if (spi_stat != status_success) + { + break; + } + + /* setup spi rx trigger dma transfer*/ + dmamux_config(HPM_DMAMUX, spi->rx_dma.channel, spi->rx_dmamux, true); + spi_stat = spi_rx_trigger_dma(spi->rx_dma.base, spi->rx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) rx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + if (spi_stat != status_success) + { + break; + } + } + spi_stat = hpm_spi_wait_idle(spi->spi_base); + if (spi_stat != status_success) + { + break; + } + + if (tx_buf != NULL) + { + tx_buf += transfer_len; + } + if (rx_buf != NULL) + { + rx_buf += transfer_len; + } + remaining_size -= transfer_len; + spi->spi_base->CTRL &= ~(SPI_CTRL_TXDMAEN_MASK | SPI_CTRL_RXDMAEN_MASK); + } + + if (l1c_dc_is_enabled() && (msg->length > 0)) + { + /* cache invalidate for receive buff */ + if (aligned_tx_buf != RT_NULL) + { + rt_free(raw_alloc_tx_buf); + raw_alloc_tx_buf = RT_NULL; + aligned_tx_buf = RT_NULL; + } + + if (aligned_rx_buf != RT_NULL) + { + l1c_dc_invalidate((uint32_t) aligned_rx_buf, aligned_len); + rt_memcpy(msg->recv_buf, aligned_rx_buf, msg->length); + rt_free(raw_alloc_rx_buf); + raw_alloc_rx_buf = RT_NULL; + aligned_rx_buf = RT_NULL; + } + } + + return spi_stat; +} + + +static rt_ssize_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(msg != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + cs_ctrl_callback_t cs_pin_control = (cs_ctrl_callback_t) device->parent.user_data; + + struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); + + hpm_stat_t spi_stat = status_success; + + if ((cs_pin_control != NULL) && msg->cs_take) + { + cs_pin_control(SPI_CS_TAKE); + } + + if (spi->enable_dma) + { + spi_stat = hpm_spi_xfer_dma(device, msg); + } + else + { + spi_stat = hpm_spi_xfer_polling(device, msg); + } + if (spi_stat != status_success) { msg->length = 0; @@ -214,12 +465,29 @@ int rt_hw_spi_init(void) { rt_err_t ret = RT_EOK; + hpm_stat_t stat; for (uint32_t i = 0; i < sizeof(hpm_spis) / sizeof(hpm_spis[0]); i++) { - hpm_spis[i].spi_bus.parent.user_data = &hpm_spis[i]; + struct hpm_spi *spi = &hpm_spis[i]; - ret = rt_spi_bus_register(&hpm_spis[i].spi_bus, hpm_spis[i].bus_name, &hpm_spi_ops); + spi->spi_bus.parent.user_data = spi; + if (spi->enable_dma) + { + stat = dma_manager_request_resource(&spi->tx_dma); + if (stat != status_success) + { + return -RT_ERROR; + } + + stat = dma_manager_request_resource(&spi->rx_dma); + if (stat != status_success) + { + return -RT_ERROR; + } + } + + ret = rt_spi_bus_register(&spi->spi_bus, spi->bus_name, &hpm_spi_ops); if (ret != RT_EOK) { break; @@ -236,4 +504,3 @@ int rt_hw_spi_init(void) INIT_BOARD_EXPORT(rt_hw_spi_init); #endif /*BSP_USING_SPI*/ - diff --git a/bsp/hpmicro/libraries/drivers/drv_spi.h b/bsp/hpmicro/libraries/drivers/drv_spi.h index b03349de86..9218ca4897 100644 --- a/bsp/hpmicro/libraries/drivers/drv_spi.h +++ b/bsp/hpmicro/libraries/drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,4 +25,3 @@ int rt_hw_spi_init(void); #endif /* DRV_SPI_H */ - diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.c b/bsp/hpmicro/libraries/drivers/drv_uart.c index df93fb6cd2..3889ee253d 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -415,8 +415,9 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void static int hpm_uart_putc(struct rt_serial_device *serial, char ch) { struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; - uart_send_byte(uart->uart_base, ch); - uart_flush(uart->uart_base); + uart_write_byte(uart->uart_base, ch); + while(!uart_check_status(uart->uart_base, uart_stat_transmitter_empty)) { + } } static int hpm_uart_getc(struct rt_serial_device *serial) diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.h b/bsp/hpmicro/libraries/drivers/drv_uart.h index 6b51451234..4c4a67db82 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart.h +++ b/bsp/hpmicro/libraries/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c index 4dd569333b..eceafb8d0e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c @@ -1,13 +1,14 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-03-08 hpmicro First version - * 2022-07-28 hpmicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined - * 2022-08-08 hpmicro Integrate DMA Manager and support dynamic DMA resource assignment + * 2022-03-08 HPMicro First version + * 2022-07-28 HPMicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined + * 2022-08-08 HPMicro Integrate DMA Manager and support dynamic DMA resource assignment' + * 2023-03-07 HPMicro Fix the issue that the data_width was not initialized before setup dma handshake * */ #include @@ -55,6 +56,9 @@ struct hpm_uart { hpm_dma_channel_handle_t rx_chn_ctx; bool tx_resource_allocated; bool rx_resource_allocated; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t rx_idle_tmp_buffer[1024]; +#endif #endif }; @@ -576,12 +580,29 @@ static void uart_tx_done(struct rt_serial_device *serial) static void uart_rx_done(struct rt_serial_device *serial) { struct rt_serial_rx_fifo *rx_fifo; - rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + uint32_t uart_recv_data_count = 0; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + uint32_t rx_idle_tmp_buffer_size = sizeof(uart->rx_idle_tmp_buffer); + uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_residue_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); if (l1c_dc_is_enabled()) { - l1c_dc_invalidate((uint32_t)rx_fifo->buffer, serial->config.rx_bufsz); + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)uart->rx_idle_tmp_buffer); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)uart->rx_idle_tmp_buffer + rx_idle_tmp_buffer_size); + uint32_t aligned_size = aligned_end - aligned_start; + l1c_dc_invalidate(aligned_start, aligned_size); + } + rt_ringbuffer_put(&(rx_fifo->rb), uart->rx_idle_tmp_buffer, uart_recv_data_count); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE); +#else + if (l1c_dc_is_enabled()) { + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)rx_fifo->rb.buffer_ptr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)rx_fifo->rb.buffer_ptr + serial->config.rx_bufsz); + uint32_t aligned_size = aligned_end - aligned_start; + l1c_dc_invalidate(aligned_start, aligned_size); } rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (serial->config.rx_bufsz << 8)); +#endif /* prepare for next read */ hpm_uart_dma_config(serial, (void *)RT_DEVICE_FLAG_DMA_RX); } @@ -596,41 +617,72 @@ static void hpm_uart_isr(struct rt_serial_device *serial) { struct hpm_uart *uart; rt_uint32_t stat, enabled_irq; + rt_uint8_t irq_id; + rt_uint8_t count = 0; + rt_uint8_t put_char = 0; RT_ASSERT(serial != RT_NULL); uart = (struct hpm_uart *)serial->parent.user_data; RT_ASSERT(uart != RT_NULL); + struct rt_serial_rx_fifo *rx_fifo; + rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; /* enter interrupt */ rt_interrupt_enter(); stat = uart_get_status(uart->uart_base); enabled_irq = uart_get_enabled_irq(uart->uart_base); - if ((enabled_irq & uart_intr_rx_data_avail_or_timeout) && (stat & uart_stat_data_ready)) { - struct rt_serial_rx_fifo *rx_fifo; - rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; - rt_uint8_t put_char = 0; - uart_receive_byte(uart->uart_base, &put_char); - rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); - /* UART in mode Receiver */ + irq_id = uart_get_irq_id(uart->uart_base); + + if (irq_id == uart_intr_id_rx_data_avail) { + while (uart_check_status(uart->uart_base, uart_stat_data_ready)) { + count++; + put_char = uart_read_byte(uart->uart_base); + rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); + /*in order to ensure rx fifo there are remaining bytes*/ + if (count > 12) { + break; + } + } + } + + if (irq_id == uart_intr_id_rx_timeout) { + while ((uart_check_status(uart->uart_base, uart_stat_data_ready)) || (uart_check_status(uart->uart_base, uart_stat_overrun_error))) { + put_char= uart_read_byte(uart->uart_base); + rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); + } rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } + if ((enabled_irq & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { /* UART in mode Transmitter */ struct rt_serial_tx_fifo *tx_fifo; tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; RT_ASSERT(tx_fifo != RT_NULL); rt_uint8_t put_char = 0; - for (;;) { - if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char)) { - uart_send_byte(uart->uart_base, put_char); - } else { - uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); - break; - } + uint32_t fifo_size = 0, ringbuffer_data_len = 0, tx_size = 0; + uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); + fifo_size = uart_get_fifo_size(uart->uart_base); + ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb); + tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len; + for (uint32_t i = 0; i < tx_size; i++) { + rt_ringbuffer_getchar(&tx_fifo->rb, &put_char); + uart_write_byte(uart->uart_base, put_char); + } + ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb);; + if (ringbuffer_data_len) { + uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); + } else { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); } } + #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + if (uart_is_rxline_idle(uart->uart_base)) { + uart_rx_done(serial); + uart_clear_rxline_idle_flag(uart->uart_base); + uart_flush(uart->uart_base); + } +#endif /* leave interrupt */ rt_interrupt_leave(); } @@ -652,6 +704,7 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria uart_config.baudrate = cfg->baud_rate; uart_config.num_of_stop_bits = cfg->stop_bits; uart_config.parity = cfg->parity; + uart_config.rx_fifo_level = uart_rx_fifo_trg_gt_three_quarters; #ifdef RT_SERIAL_USING_DMA if (uart->dma_flags & (RT_DEVICE_FLAG_DMA_TX | RT_DEVICE_FLAG_DMA_RX)) { uart_config.fifo_enable = true; @@ -662,7 +715,14 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria if (uart->dma_flags & RT_DEVICE_FLAG_DMA_RX) { uart_config.rx_fifo_level = uart_rx_fifo_trg_not_empty; } +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + uart_config.rxidle_config.detect_enable = true; + uart_config.rxidle_config.detect_irq_enable = true; + uart_config.rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; + uart_config.rxidle_config.threshold = 10U; /* 10bit */ +#endif } + #endif uart_config.word_length = cfg->data_bits - DATA_BITS_5; @@ -704,7 +764,7 @@ hpm_stat_t hpm_uart_dma_tx_init(struct hpm_uart *uart_ctx) return status; } -static rt_err_t hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) +static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) { rt_ubase_t ctrl_arg = (rt_ubase_t) arg; struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; @@ -714,18 +774,32 @@ static rt_err_t hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; config.ch_index = uart->rx_chn_ctx.resource.channel; - config.dst = (uint32_t) rx_fifo->buffer; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + config.dst = (uint32_t)uart->rx_idle_tmp_buffer; +#else + config.dst = (uint32_t) rx_fifo->rb.buffer_ptr; +#endif + config.dst_fixed = false; config.src = (uint32_t)&(uart->uart_base->RBR); config.src_fixed = true; + config.data_width = DMA_TRANSFER_WIDTH_BYTE; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + config.size_in_byte = sizeof(uart->rx_idle_tmp_buffer); +#else config.size_in_byte = serial->config.rx_bufsz; - if (status_success != dma_setup_handshake(uart->rx_chn_ctx.resource.base, &config)) { - return -RT_ERROR; +#endif + if (status_success != dma_setup_handshake(uart->rx_chn_ctx.resource.base, &config, true)) { + return RT_ERROR; } uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->rx_chn_ctx.resource.base, uart->rx_dma_mux); dmamux_config(BOARD_UART_DMAMUX, uart->rx_chn_ctx.resource.channel, mux, true); + #if !defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) || (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 0) hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL); intc_m_enable_irq(uart->rx_chn_ctx.resource.irq_num); +#else + intc_m_enable_irq_with_priority(uart->irq_num, 1); +#endif } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->tx_chn_ctx.resource.base, uart->tx_dma_mux); dmamux_config(BOARD_UART_DMAMUX, uart->tx_chn_ctx.resource.channel, mux, true); @@ -745,7 +819,8 @@ static void hpm_uart_transmit_dma(DMA_Type *dma, uint32_t ch_num, UART_Type *uar config.src = (uint32_t) src; config.src_fixed = false; config.size_in_byte = size; - dma_setup_handshake(dma, &config); + config.data_width = DMA_TRANSFER_WIDTH_BYTE; + dma_setup_handshake(dma, &config, true); } #endif /* RT_SERIAL_USING_DMA */ @@ -755,6 +830,9 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void RT_ASSERT(serial != RT_NULL); rt_ubase_t ctrl_arg = (rt_ubase_t) arg; + uint8_t *tmp_buffer = NULL; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx; + struct rt_serial_tx_fifo *tx_fifo = (struct rt_serial_tx_fifo*)serial->serial_tx; struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) @@ -821,6 +899,38 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void case RT_DEVICE_CTRL_CONFIG: #ifdef RT_SERIAL_USING_DMA + if ((ctrl_arg == RT_DEVICE_FLAG_DMA_RX) || (ctrl_arg == RT_DEVICE_FLAG_INT_RX)) { + if ((rx_fifo) && (((rt_uint32_t)rx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (rx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) { + rt_free(rx_fifo); + rx_fifo = RT_NULL; + rx_fifo = (struct rt_serial_rx_fifo *) rt_malloc(sizeof(struct rt_serial_rx_fifo)); + RT_ASSERT(rx_fifo != RT_NULL); + tmp_buffer = rt_malloc(serial->config.rx_bufsz + HPM_L1C_CACHELINE_SIZE); + RT_ASSERT(tmp_buffer != RT_NULL); + tmp_buffer += (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE)); + rt_ringbuffer_init(&rx_fifo->rb, tmp_buffer, serial->config.rx_bufsz); + rt_ringbuffer_reset(&rx_fifo->rb); + serial->serial_rx = rx_fifo; + } + } + + if ((ctrl_arg == RT_DEVICE_FLAG_DMA_TX) || (ctrl_arg == RT_DEVICE_FLAG_INT_TX)) { + if ((tx_fifo) && (((rt_uint32_t)tx_fifo->rb.buffer_ptr % HPM_L1C_CACHELINE_SIZE) || (tx_fifo->rb.buffer_size % HPM_L1C_CACHELINE_SIZE))) { + rt_free(tx_fifo); + tx_fifo = RT_NULL; + tx_fifo = (struct rt_serial_tx_fifo *) rt_malloc(sizeof(struct rt_serial_tx_fifo)); + RT_ASSERT(tx_fifo != RT_NULL); + tmp_buffer = rt_malloc(serial->config.tx_bufsz + HPM_L1C_CACHELINE_SIZE); + RT_ASSERT(tmp_buffer != RT_NULL); + tmp_buffer+= (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE)); + rt_ringbuffer_init(&tx_fifo->rb, tmp_buffer, serial->config.tx_bufsz); + rt_ringbuffer_reset(&tx_fifo->rb); + tx_fifo->activated = RT_FALSE; + tx_fifo->put_size = 0; + serial->serial_tx = tx_fifo; + } + } + if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) { hpm_uart_dma_config(serial, (void *)ctrl_arg); } else @@ -872,17 +982,48 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, RT_ASSERT(serial != RT_NULL); RT_ASSERT(buf != RT_NULL); RT_ASSERT(size); - + uint32_t fifo_size = 0, tx_size = 0; + uint32_t ringbuffer_data_len = 0; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + struct rt_serial_tx_fifo *tx_fifo; + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + uint8_t ch = 0; + RT_ASSERT(tx_fifo != RT_NULL); #ifdef RT_SERIAL_USING_DMA - struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX) { hpm_uart_dma_register_channel(serial, true, uart_tx_done, RT_NULL, RT_NULL); intc_m_enable_irq(uart->tx_chn_ctx.resource.irq_num); + if (l1c_dc_is_enabled()) { + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)buf); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)buf + size); + uint32_t aligned_size = aligned_end - aligned_start; + l1c_dc_flush(aligned_start, aligned_size); + } hpm_uart_transmit_dma(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel, uart->uart_base, buf, size); return size; - } + } else { +#else + { #endif - hpm_uart_control(serial, RT_DEVICE_CTRL_CONFIG, (void *)tx_flag); + + if (size > 0) { + if (uart_check_status(uart->uart_base, uart_stat_transmitter_empty)) { + uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); + fifo_size = uart_get_fifo_size(uart->uart_base); + ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb); + tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len; + for (uint32_t i = 0; i < tx_size; i++) { + rt_ringbuffer_getchar(&tx_fifo->rb, &ch); + uart_write_byte(uart->uart_base, ch); + } + if (rt_ringbuffer_data_len(&tx_fifo->rb)) { + uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); + } else { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + } + } + } return size; } @@ -1288,7 +1429,7 @@ int rt_hw_uart_init(void) } if (RT_EOK != hpm_uart_config()) { - return -RT_ERROR; + return RT_ERROR; } for (uint32_t i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.h b/bsp/hpmicro/libraries/drivers/drv_uart_v2.h index 6b51451234..34ca294f74 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart_v2.h +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.h @@ -1,14 +1,14 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#ifndef DRV_UART_H -#define DRV_UART_H +#ifndef DRV_UART_V2_H +#define DRV_UART_V2_H int rt_hw_uart_init(void); -#endif /* DRV_UART_H */ \ No newline at end of file +#endif /* DRV_UART_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_usb.c b/bsp/hpmicro/libraries/drivers/drv_usb.c index fd64d369e4..0d460417c4 100644 --- a/bsp/hpmicro/libraries/drivers/drv_usb.c +++ b/bsp/hpmicro/libraries/drivers/drv_usb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -93,7 +93,7 @@ rt_err_t hpm_usb_control(rt_device_t dev, int cmd, void *args) break; default: - ret = -RT_EINVAL; + ret = RT_EINVAL; break; } @@ -117,4 +117,3 @@ int rt_hw_usb_init(void) } INIT_BOARD_EXPORT(rt_hw_usb_init); - diff --git a/bsp/hpmicro/libraries/drivers/drv_usb.h b/bsp/hpmicro/libraries/drivers/drv_usb.h index dea46136af..16522599fc 100644 --- a/bsp/hpmicro/libraries/drivers/drv_usb.h +++ b/bsp/hpmicro/libraries/drivers/drv_usb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.c b/bsp/hpmicro/libraries/drivers/drv_wdt.c index f999139042..5cf2274d0f 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.c +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021 - 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -207,7 +207,7 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) hpm_wdog_close(wdt); break; default: - ret = -RT_EINVAL; + ret = RT_EINVAL; break; } diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.h b/bsp/hpmicro/libraries/drivers/drv_wdt.h index 4c42938700..4c69255af0 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.h +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md b/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md index 0c5e5cdb4c..a9c9b0be66 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md +++ b/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md @@ -1,25 +1,364 @@ # Change Log -## [0.13.1] - 2022-08-23: +## [1.2.0] - 2023-06-30: + +Main changes since 1.1.0 + +Tested Segger Embedded Studio Version: 7.22 + +### Changed: + - boards: hpm6750evk*: decrease core frequency from 816MHz to 648MHz + - openocd: soc: hpm6280: simplify dual core release core1 approach. + - cmake: segger: configure optimization level according to gcc level. + - soc: dmamux: move it from ip to soc + - soc: interrupt: adjust irq api. #659 + - soc: improve svd file + - soc: hpm_soc_feature.h: remove ADC16_SOC_TEMP_CH_EN for some specified Socs + - components: enet_phy: update the common enet phy header file + - components: sgtl5000 and wm8960: update clock setting + - drivers: uart: update uart driver + - drivers: pdma: improve quality of scale + - drivers: adc: adjust wait_dis type in adc16_config_t struct + - drivers: enet: update rmii reference clock setting API for ENET + - utils: hpm_swap: escape for andes toolchain. + - middleware: hpm_sdmmc: add spi sdcard + - middleware: motor_ctrl: change the file organization + - middleware: motor_ctrl: remove slide control content from foc + - middleware: lvgl: upgrade to v8.3.5 (with pdma) + - middleware: lvgl: Add direct mode + - middleware: cherryusb: update version to v0.8.0 + - samples: I2S_DMA and I2S Interrupt: update sample behavior + - samples: cherryusb: hid host: separate mouse and keyboard urb + - samples: cherryusb: increase max interface and endpoint number Configuration + - samples: cherryusb: uac2: move setting sampling freq to isr + - samples: cherryusb: audio: update descriptor for identification + - samples: audio_codec: set codec voice to max and increase irq priority + - samples: multicore: lvgl_coremark: delete custom linker files and using andes toolchain + - samples: lvgl_audio_player: update CMakeLists.txt to using noncacheable framebuffer + - samples: spi: clean the redundant code + - samples: i2c: improve the processing of FIFO in ISR + - samples: drivers: uart: update uart_rx_timeout demo + - samples: drivers: gptmr: split sample into multiple function samples + - samples: drivers: adc: optimization for all macro definitions in applications + - samples: drivers: adc: update struct member names + - samples: update clock divider setting for ADC-related examples + - samples: cherryusb: move vid/pid etc definition to usb_config.h + - samples: cherryusb: device: update vid to hpmicro 0x34B7 + - samples: cherryusb: change API update for v0.8 + - samples: cherryusb: device: audiov1: change to full speed mode + - samples: tinyusb: uac2: update descriptor and sample + - samples: lwip: disable mmc interrupt settings + - samples: lwip: lwip_ptp: v1: sync precision improvement + +### Added: + - cmake: toolchains: add isa spec 20191213 support. + - cmake: ses: support set ses raw option in CMakeLists.txt + - cmake: add option to specify board search path. + - cmake: generate compile_commands.json file + - soc: hpm_soc_feature: add a common macro for ADC12 and ADC16 + - drivers: cam: add new APIs + - drivers: spi: add new APIs + - drivers: i2c: add new APIs + - drivers: I2S: add i2s_check_data_line_status API + - drivers: dma: add dma_set_transfer_src_width_byte_size() API + - drivers: gptmr: add output capture APIs + - drivers: gptmr: add gptmr_channel_get_dma_request_event api + - drivers: adc: add adc16_trigger_pmt_by_sw API + - drivers: enet: add some APIs related to interrupt settings + - drivers: enet: add a new API for transmisstion + - drivers: usb: add macro CONFIG_USB_DEVICE_FS to set full speed mode + - components: uart_lin: add uart lin component + - components: add smbus + - components: add sccb + - middleware: lvgl: add macro HPM_LVGL_FRAMEBUFFER_NONCACHEABLE + - middleware: add AzureRTOS (threadx/usbx/netx/guix) + - middleware: hpm_mcl: sensorless over-zero + - middleware: add smc + - middleware: hpm_sdmmc Add eMMC support + - middleware: hpm_math: add bit conversion function + - middleware: add uC/OS-III + - middleware: cherryusb: audio: add feedback descriptor + - middleware: cherryusb: audio: add param to set endpoint bmAttributes + - middleware: microros: add microros foxy sources + - samples: drivers: spi: add spi_sdcard_fatfs sample + - samples: drivers: spi: add sd sample + - samples: add uart_lin + - samples: motor_ctrl: sensorless: over-zero demo + - samples: cherryusb: add rndis host dhcp samples + - samples: drivers: sdxc :emmc Added eMMC sample + - samples: drivers: adc12: update irq pattern for sequence usage + - samples: drivers: pla: add pla tamagawa demo + - samples: drivers: gptmr: add counter_sync sample + - samples: drivers: gptmr: add timer_basic sample + - samples: drivers: gptmr: add t_shape_accel_decel sample + - samples: drivers: dma/gptmr: add trigger dma transfer using gptmr event sample + - samples: drivers: uart add uart_rx_timeout sample + - samples: i2c: add smbus samples + - samples: lwip: lwip_tcpecho_freertos: add self-adaption + - samples: cherryusb: hid host: move usbh_submit_urb() out of condition + - samples: cherryusb: add composite freertos sample + - samples: cherryusb: add rndis freertos sample + - samples: cherryusb: add msc freertos sample + - samples: cherryusb: add audio v2 mic speaker freertos sample + - samples: cherryusb: add hid mouse freertos sample + - samples: cherryusb: add hid keyboard freertos sample + - samples: cherryusb: add cdc acm freertos sample + - samples: cherryusb: add rndis tcp server sample + - samples: cherryusb: add rndis device udp_echo sample + - samples: cherryusb: add rndis device http_server sample + - samples: cherryusb: device: add audio_v2_speaker_sync sample + - samples: add several uC/OS-III samples + - samples: smc: add smc demo + - samples: microros: add subscriber, sevice and publisher + - samples: uC/OS-III: mutex + +### Fixed: + - cmake: ses: fix __SEGGER_RTL_vfprintf issue with nds tool in SES 7.20. + - soc: hpm6280: Modify the number of PWM cmps. + - soc: reset.c: __dso_handle needs to be declared for nds toolchain. + - soc: fix max buffer length in sequence mode for ADC + - soc: HPM6750: enet soc drv: fix set clock delay settings + - soc:hpm6360:sdxc Correct clock divider settting issue + - drivers: pla: missing Union Field + - drivers: spi: fix the problem of CMD and ADDR configuration order + - drivers: i2c: fix clock frequency error rate problem + - drivers: i2c: clear CMPL bit in API to avoid blocking the trans + - drivers: i2c: fix i2c slave device read and write fail + - drivers: i2c: fix read data unexpected multi transition. + - drivers: i2c: fix w1c clear status error + - driver: usb: fix w1c clear flag error + - drivers: gptmr: fix dma request enum definition + - drivers: adc: fix logics for judging the validity of arguments + - component: uart_lin: fix break signal problem + - middleware: cherryusb: fix buffer size error + - middleware: lvgl: fix fbbuffer option + - samples: gptmr: fix pwm_measure sample compile waring + - samples: jpeg: fix interchange format of exif support + - samples: jpeg: fix jpeg decode + - samples: drivers: spi: fix the problem of CMD and ADDR configuration order + - samples: drivers: mcan: can_fd loopback test setting is incorrect + - samples: cherryusb: http_server_freertos: fix printf content error + - samples: cherryusb: audio: change endpoint attributes for support MACBOOK + - samples: tinyusb: msc: increase block numbers for windows format + - samples: lwip: lwip_httpsrv: fix reload or refresh error + +## [1.1.0] - 2023-03-31: + +Main changes since 1.0.0 + +Tested Segger Embedded Studio Version: 7.10 + +### Changed: + - docs: add new docs for rtd project. + - soc: ip: enet: update the enet register file + - soc: ip: adc16: update the adc16 header file + - soc: hpm_romapi - Add APIs for configuring remapping, exip regions + - drivers: enet: improve APIs related to PPS + - drivers: adc: change adc bus blocking interface + - drivers: adc: optimize getting oneshot result + - drivers: src: update the default config for ADC12&ADC16 + - boards: rename board-level APIs related to enet + - components: enet_phy: rtl8201: update the register file + - middleware: hpm_math: update dsp version + - middleware: erpc: update to v1.10.0 + - samples: uart: rename uart_dma_rx_idle to uart_software_rx_idle + - samples: uart: add hardware rx idle detection sample + - samples: multicore: erpc: core1 add sdk_compile_options(-O1) + - samples: drivers: gptmr: update sample output. + - samples: lwip: common: arch: ethernetif: update a calling function name + - samples:drivers: adc: optimize oneshot handler + +### Added: + - arch: add FPU related APIs + - soc/board: add HPM6280 support + - soc: HPM6750: acmp: add ACMP section + - components: add mt9m114 support + - drivers: add raw8 pixel format support + - drivers: csr - Implement CSR driver + - drivers: adc: adc16: support resolution setting + - drivers/samples: add SDM/PLA/CRC/MCAN + - drivers: I2C: add new API + - drivers: adc: adc16: support resolution setting + - drivers: enet: add enet control config for transmission + - middleware: cherryusb: audio: update class driver and demo template + - middleware: add mbedtls lib files with SDP acceleration + - freeRTOS: add support for static allocation + - samples: drivers: enet: add a pps demo + - samples: cherryusb: add audio samples + - samples: add the resolution parameter in all demos with ADC16 + - samples: add rfft demo + - sampels: i2c: add interrupt b2b samples + - samples: drivers: i2s: add an i2s_master demo + - samples: drivers: i2s: add an i2s_slave demo + - samples : rom_api : add sw_gm_api filter + - samples: add the resolution parameter in all demos with ADC16 + +### Fixed: + - openocd: hpm6300evk: update sdram initialization. + - drivers: trgmux: trigmux edge filter setting error + - drivers: enet: fix register access error + - drivers: adc16: fix the config error of ADC16_CONFIG1 + - drivers: i2c: fix i2c timing configuration + - drivers: SPI: fix SPI status API + - drivers: fix gptmr cmp value don't minus one + - drivers: mcan: correct the mcan ext_id filter issue + - drivers: I2C: fix issue in i2c_master_address_read API + - drivers: Self_ACK cannot be set in CAN driver + - drivers: rtc rtc_config_alarm always return error code + - cmake: correct source code compilation + - soc: toolchain: gcc: initialize heap for SES + - soc: gcc linker files: add NOLOAD keyword to noncacheable.bss section + - soc: HPM6360: gcc: ld: correct noncacheable region name. + - drivers: qei: Fix speed display always zero + - middleware: freertos: disable global irq before vTaskStartScheduler + - freeRTOS: fix trap when enable float feature + - freeRTOS: fix tick lost + - freeRTOS: fix segger project build warning + - samples: drivers: i2s: fix CFGR config + - samples: drivers: fix acmp toggle error + - samples: lwip: fix the DHCP issue + - samples: uart: fix irq_id judgment + - samples: fix the order of uart pin configuration and clock configuration + - samples: update spi dma sample + - samples: drivers: sysctl: correct reset enable approach. + - samples: fix dma_general_transfer sample memory out of bounds + - samples: drivers: wdog: Fix logic issue on finding the nearest interrupt interval + - sample: audio_codec: decoder_wav: add '\0' to fatfs path + +## [1.00.0] - 2022-12-31: + +Main changes since 0.14.0 + +Tested Segger Embedded Studio Version: 7.10 + +### Changed: + - boards: add version info in banner. + - board: lcdc: move panel para to board + - components: spi component to support to transfer different width of data in dma handshake mode + - drivers: rename dram to femc + - middleware: cherryusb update to v0.7.0 + - middleware: erpc: update for support rtos + - middleware: hpm_mcl: update api naming + - samples: erpc: rename erpc_matrix_multiply_rpmsg to erpc_matrix_multiply_rpmsg_bm + - samples: erpc: reorganize erpc_matrix_multiply_rpmsg samples + - samples: erpc: move samples folder to erpc_matrix_multiply_rpmsg + - samples: update i2c/spi dma channel and dmamux channel definition + - ses: project template: use demo.* as output file naming. + - soc: HPM6750: toolchains: update linker files + - soc: HPM6360: toolchains: update linker files + +### Added: + - arch: riscv: add read_clear_csr() API + - component: add wm8960 support + - component: add usb device iso transfer support + - drivers: hpm_common: include hpm_sdk_version.h. + - drivers: common: add NOP and WFI. + - drivers: uart: add api to recv/send byte directly. + - soc: HPM6750 linker files: rename rpmsg_sh_mem to sh_mem + - cmake: add sdk version header file generation. + - middleware: tinyusb: add audio class + - middleware: hpm_math: add NN library + - samples: erpc: add erpc_two_way_rpc_rpmsg_rtos sample + - samples: erpc: add erpc_matrix_multiply_rpmsg_rtos sample + - samples: add power mode switch demo. #282 + - samples: drivers: adc: add a temperature measurement demo + - samples: drviers: femc: add sram sample + - samples: lwip demo for FreeRTOS + - samples: lwip demo of interrupt usage + - samples: tinyusb: add uac2 demo + - samples: tflm: add face detection demo + - samples: tflm: add MLPerf Tiny benchmark demo + - samples: lwip: common: feature: add a LPI interrupt process + +### Fixed: + - drivers:interrupt: Fix FPU context crashing in nested irq case + - drivers: src: adc: fix adc result in period mode + - segger: update app directory structure in SES. + - soc: disable irq during cache maintenance + - middleware: lvgl: fps calculation to No. + - samples: get off level based on board api. + - samples: multicore: hello: core1 rgb led does not change correctly. + +## [0.14.0] - 2022-10-31: Main changes since 0.13.0 +Tested Segger Embedded Studio Version: 6.34a + ### Changed: - - Driver:I2S: update i2s drivers - - middleware: lwip: optimize variable_name definition - - samples: lwip: lwip_iperf: update readme files - - samples: lwip: common: arch: add LWIP_MEM_SECTION declartion + - drivers: inc: update adc driver + - drivers: gptmr: update reload value + - components: enet_phy: optimize APIs + - components: enet_phy: dp83867: rename functions + - components: conditionally add debug_console + - middleware: add cherryusb (0.6.0) + - middleware: littlevgl: update to v8.3.1 + - middleware: fatfs: file name encoding in utf-8 + - middleware: freertos: support nested irq handling + - middleware: hpm_mcl: Optimized motor control foc speed + - samples: drivers: dma src move to dma_general_transfer folder + - samples: lwip: update all static addresses and all gateway addresses + - samples: lwip: lwip_iperf: optimize the interactive log + - samples: tinyusb: device: hid_generic_inout: optimize the python script + - openocd: HPM6750A1 silicon in hpm6750-dual-core.cfg + - header file: update the enet/conctl register files + - header file: Update TRGMUX0 pin input source definition + - header file: update the ADC12 header files + - scripts: ses: organize file in ses according to real path. + - cmake: split gcc and ses source + - board: bump HPM6750 DCDC voltage to 1200mv ### Fixed: + - drivers: pdma: fix scale api issue + - drivers: i2c: update DATACNT processing + - drivers: i2s: fix i2s interrupt workaround in i2s_init + - drivers: pwm: fix pwm capture function error + - drivers: pwm: fix pwm capture configuration error + - drivers: clock: fix error in clock_set_xxx_source + - drivers: wdg: timeout calculation error + - drivers: trgm_drv: bugfix: include error + - drivers: romapi: call fencei after flash erase/write operation + - drivers: watchdog: overflow + - drivers: usb: host controller initialization issue + - drivers: i2s: i2s_enable() issue fix + - middleware: tinyusb: src: class: fix the HID report desc macro + - samples: drivers: adc: optimize all ADC demos + - samples: drivers: adc: fix all channel initializations without a default value + - samples: motor_ctrl: hardware trigger api usage error + - samples: audio_codec: update clock process for 44100 sample rate + - samples: lcdc: boundary pixel is incorrenct - samples: multicore: BOOT_HEADER was missing in multicore core0 example - - samples: jpeg: Fix encoding and decoding problem - - samples: audio codec: wav decoder: fix 32bit wave file playback - - I2S_DMA: fix wav channel not align problem - - i2s_interrupt: fix I2S FIFO overflow - - fix lack of interrupt claim for swi - - driver: watchdog: overflow - - Fix critical section logic issue in dma manager - - Fix the core1 application debugging issue + - samples: drivers: i2s: correct audio data if depth < 32bit. + - samples: hpm_math: fft_perf_test: Fix error printing information + - samples: fix pdm2dao noise problem + - samples: lwip: fix the enet throughput degradation + - soc: correct address overlapping SES XIP linker file + - soc: correct the interrupt context switch issue + - soc: fix Lack of interrupt claim for swi + - boards: fix some rmii reference clock APIs + +### Added: + - boards: add hpm6750evk2 support + - soc: add initfini.c + - drivers: lcdc: add y8 support + - drivers: spi: update data_length processing + - drivers: spi: add api to enable/disable spi dma request + - drivers: pmp: Add pmp_config_entry API + - components: add ipc_event_mgr + - component: spi: add cache maintain + - middleware: add erpc + - samples: lwip: support self-adaptive port speed and duplex mode + - samples: jpeg: support grayscale + - samples: drivers: spi: use api to get data length + - samples: drivers: spi: add interrupt b2b sample + - samples: drivers: mbx: add singlecore samples + - samples: drivers: add dma circle transfer + - samples: drivers: pwm: add pwm capture demo + - samples: provide OTP API demo + - samples: add cherryusb hid/msc/cdc samples + - samples: add Guomi API example + - samples: add erpc sample + - samples: add segger_rtt ## [0.13.0] - 2022-07-31: diff --git a/bsp/hpmicro/libraries/hpm_sdk/LICENSE b/bsp/hpmicro/libraries/hpm_sdk/LICENSE index d5c5c0ac62..fcbba7dbef 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/LICENSE +++ b/bsp/hpmicro/libraries/hpm_sdk/LICENSE @@ -1,7 +1,7 @@ BSD 3-Clause "New" or "Revised" License https://spdx.org/licenses/BSD-3-Clause.html -Copyright (c) 2021-2022, HPMicro. All rights reserved. +Copyright (c) 2021-2023, HPMicro. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/bsp/hpmicro/libraries/hpm_sdk/README.md b/bsp/hpmicro/libraries/hpm_sdk/README.md index 886e6b489e..95212bc5a7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/README.md +++ b/bsp/hpmicro/libraries/hpm_sdk/README.md @@ -1,16 +1,55 @@ +``` mermaid +gantt + title HPM SDK Release Plan + dateFormat YYYY-MM-DD + section Mainline Release + v1.1.0 :a1, 2023-01-01, 2023-03-31 + v1.2.0 :a2, 2023-04-01, 2023-06-30 + v1.3.0 :a3, 2023-07-01, 2023-09-30 + v1.4.0 :a4, 2023-10-01, 2023-12-31 +``` + +[中文](README_zh.md) + # HPM SDK Overview The HPM SDK Project is a software development kit based on HPMicro's MCUs, which supports a wide range of MCUs, based on the BSD license, including drivers, middleware and RTOS, such as littlevgl/ lwIP/ TinyUSB/ FreeRTOS, etc. It supports a large number of Boards. -# HPM SDK Quick Start Guide +## SDK Directory Structure -## Minium required version of dependencies are: +| Name | Description | +|--------|--------| +| /arch | cpu architecture | +| /boards | board support files | +| /cmake | cmake extensions | +| /components | software components | +| /docs | documentation | +| /drivers | low level driver files | +| /middleware | middleware files | +| /samples | sample source for drivers, middleware, components | +| /scripts | util scripts | +| /soc | SoC specific source | +| /utils | util source | + +## SDK Documentation +- Local: + SDK documentation can be built locally, once it's done, it can be accessed with the following entries: + - >/docs/index.html + - >/docs/index_zh.html + > Please refer to /docs/README.md for more details about documentation building. +- Online: + - http://hpm-sdk.readthedocs.io/ + - http://hpm-sdk-zh.readthedocs.io/ + +## HPM SDK Quick Start Guide + +### Minimum required version of dependencies are: | Name | Version | | -------|---------- | |CMake | 3.13 | | Python | 3.8 | -## Install Dependencies +### Install Dependencies - Ubuntu - install tools @@ -199,15 +238,15 @@ The HPM SDK Project is a software development kit based on HPMicro's MCUs, which Open zadig, click Options-> List All Devices. - ![List All Devices](doc/images/readme/zadig_list_all_devices.png) + ![List All Devices](docs/assets/zadig_list_all_devices.png) Select Dual RS232-HS (Interface 0). - ![Select Dual RS232-HS (Interface 0)](doc/images/readme/zadig_select_dual_rs232-hs.png) + ![Select Dual RS232-HS (Interface 0)](docs/assets/zadig_select_dual_rs232-hs.png) Then click Install Driver or Replace Driver. - ![Replace Driver](doc/images/readme/zadig_replace_driver.png) + ![Replace Driver](docs/assets/zadig_replace_driver.png) 7. Go to hello_world directory @@ -231,7 +270,7 @@ The HPM SDK Project is a software development kit based on HPMicro's MCUs, which 9. connect gdb client to the gdbserver started by openocd, (by default, gdbserver port is 3333) ```GDB - gdb> file build/output/hello_world.elf + gdb> file build/output/demo.elf gdb> target remote localhost:3333 gdb> load gdb> b main @@ -248,3 +287,7 @@ The HPM SDK Project is a software development kit based on HPMicro's MCUs, which Note: openocd executable needs to be found in the PATH variable of current console, otherwise debug configuration will not be generated to project file and needs to be configured manually in Segger Embedded Studio later. # Community Support +- github page: https://hpmicro.github.io +- github: https://github.com/hpmicro/hpm_sdk +- gitee: https://gitee.com/hpmicro/hpm_sdk + diff --git a/bsp/hpmicro/libraries/hpm_sdk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/README_zh.md index 2390421427..2e0c30cd3b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/README_zh.md +++ b/bsp/hpmicro/libraries/hpm_sdk/README_zh.md @@ -1,16 +1,55 @@ +``` mermaid +gantt + title HPM SDK Release Plan + dateFormat YYYY-MM-DD + section Mainline Release + v1.1.0 :a1, 2023-01-01, 2023-03-31 + v1.2.0 :a2, 2023-04-01, 2023-06-30 + v1.3.0 :a3, 2023-07-01, 2023-09-30 + v1.4.0 :a4, 2023-10-01, 2023-12-31 +``` + +[English](README.md) + # HPM SDK 概述 HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多种MCU。基于BSD许可证，包含了底层驱动，中间件和RTOS，例如littlevgl/ lwIP/ TinyUSB/ FreeRTOS等，支持大量评估板。 -# HPM SDK使用说明 +## HPM SDK 目录结构 -## 依赖软件最低版本要求 +| 目录名称 | 描述 | +|--------|--------| +| /arch | cpu架构相关文件 | +| /boards | 板级文件 | +| /cmake | cmake扩展 | +| /components | 软件组件 | +| /docs | 文档 | +| /drivers | 底层驱动文件| +| /middleware | 中间件 | +| /samples | 驱动、中间件以及软件组件示例代码 | +| /scripts | 辅助脚本 | +| /soc | SoC相关文件 | +| /utils | 辅助文件 | + +## SDK文档 +- 本地文档: + SDK文档可以进行本地编译，成功编译之后可以通过以下入口访问本地文档: + - >/docs/index.html + - >/docs/index_zh.html + > 文档编译方式请参考/docs/README.md +- 在线文档： + - http://hpm-sdk.readthedocs.io/ + - http://hpm-sdk-zh.readthedocs.io/ + +## HPM SDK使用说明 + +### 依赖软件最低版本要求 | 软件名称 | 版本号 | |--- | --- | | CMake | 3.13 | | Python | 3.8 | -## 安装依赖 +### 安装依赖 - Ubuntu: - 安装工具: @@ -208,15 +247,15 @@ HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多 打开zadig，点击 Options->List All Devices. - ![List All Devices](doc/images/readme/zadig_list_all_devices.png) + ![List All Devices](docs/assets/zadig_list_all_devices.png) 选择 Dual RS232-HS (Interface 0). - ![Select Dual RS232-HS (Interface 0)](doc/images/readme/zadig_select_dual_rs232-hs.png) + ![Select Dual RS232-HS (Interface 0)](docs/assets/zadig_select_dual_rs232-hs.png) 然后点击 Install Driver 或 Replace Driver. - ![Replace Driver](doc/images/readme/zadig_replace_driver.png) + ![Replace Driver](docs/assets/zadig_replace_driver.png) 7. 切换到hello_world目录 @@ -240,7 +279,7 @@ HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多 9. 连接GDB client到openocd GDB server (缺省状态下, openocd gdbserver 端口为 3333) ```GDB - gdb> file build/output/hello_world.elf + gdb> file build/output/demo.elf gdb> target remote localhost:3333 gdb> load gdb> b main @@ -255,4 +294,7 @@ HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多 注意：openocd可执行文件应该可以通过当前终端的PATH环境变量中可以找到, 否则无法在工程文件中生成相应的调试配置，需要之后在Segger Embedded Studio中手工配置。 -# 社区支持 \ No newline at end of file +## 社区支持 +- github page: https://hpmicro.github.io +- github: https://github.com/hpmicro/hpm_sdk +- gitee: https://gitee.com/hpmicro/hpm_sdk diff --git a/bsp/hpmicro/libraries/hpm_sdk/SConscript b/bsp/hpmicro/libraries/hpm_sdk/SConscript index c682f72863..008c4f6dac 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/SConscript +++ b/bsp/hpmicro/libraries/hpm_sdk/SConscript @@ -14,6 +14,7 @@ src += ['drivers/src/hpm_pmp_drv.c'] src += ['drivers/src/hpm_pllctl_drv.c'] src += ['drivers/src/hpm_pllctlv2_drv.c'] src += ['drivers/src/hpm_dma_drv.c'] +src += ['drivers/src/hpm_pcfg_drv.c'] if GetDepend(['BSP_USING_GPIO']): @@ -36,13 +37,16 @@ if GetDepend(['BSP_USING_WDG']): if GetDepend(['BSP_USING_ADC']): if GetDepend(['BSP_USING_ADC12']): - src += ['drivers/src/hpm_adc12_drv.c'] + src += ['drivers/src/hpm_adc12_drv.c'] if GetDepend(['BSP_USING_ADC16']): - src += ['drivers/src/hpm_adc16_drv.c'] + src += ['drivers/src/hpm_adc16_drv.c'] if GetDepend(['BSP_USING_CAN']): src += ['drivers/src/hpm_can_drv.c'] +if GetDepend(['BSP_USING_MCAN']): + src += ['drivers/src/hpm_mcan_drv.c'] + if GetDepend(['BSP_USING_ETH']): src += ['drivers/src/hpm_enet_drv.c'] @@ -58,8 +62,8 @@ if GetDepend(['BSP_USING_LCD']): if GetDepend(['BSP_USING_GPTMR']): src += ['drivers/src/hpm_gptmr_drv.c'] -if GetDepend(['BSP_USING_DRAM']): - src += ['drivers/src/hpm_dram_drv.c'] +if GetDepend(['BSP_USING_FEMC']): + src += ['drivers/src/hpm_femc_drv.c'] if GetDepend(['BSP_USING_PWM']): src += ['drivers/src/hpm_pwm_drv.c'] @@ -78,6 +82,9 @@ if GetDepend(['BSP_USING_DAO']): src += ['drivers/src/hpm_dao_drv.c'] src += ['drivers/src/hpm_i2s_drv.c'] +if GetDepend(['BSP_USING_PDMA']): + src += ['drivers/src/hpm_pdma_drv.c'] + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/VERSION b/bsp/hpmicro/libraries/hpm_sdk/VERSION index 7be09ab348..cca691de9a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/VERSION +++ b/bsp/hpmicro/libraries/hpm_sdk/VERSION @@ -1,5 +1,5 @@ -VERSION_MAJOR = 0 -VERSION_MINOR = 13 -PATCHLEVEL = 1 +VERSION_MAJOR = 1 +VERSION_MINOR = 2 +PATCHLEVEL = 0 VERSION_TWEAK = 0 EXTRAVERSION = 0 diff --git a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h index 7455ff38bc..4f95f4db9e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h +++ b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -29,6 +29,26 @@ extern "C" { */ #define clear_csr(csr_num, bit) __asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit)) +/** + * @brief read and clear bits in csr + * + * @param csr_num specific csr + * @param bit bits to be cleared + * + * @return csr value before cleared + */ +#define read_clear_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; }) + +/** + * @brief read and set bits in csr + * + * @param csr_num specific csr + * @param bit bits to be set + * + * @return csr value before set + */ +#define read_set_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrs %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; }) + /** * @brief set bits in csr * @@ -67,6 +87,21 @@ extern "C" { */ #define fencei() __asm volatile("fence.i") +/** + * @brief enable fpu + */ +#define enable_fpu() read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK) + +/** + * @brief disable fpu + */ +#define disable_fpu() read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK) + +/** + * @brief clear fcsr + */ +#define clear_fcsr() write_fcsr(0) + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README.md deleted file mode 100644 index 3f8bb83429..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README.md +++ /dev/null @@ -1,75 +0,0 @@ -# HPM6300EVK - - -::::{important} -:::{note} -Need to supplement the content of each module -::: -:::: - -## Overview - -version -Board overall -Board overall hpm6300evk - -- Console serial port parameters: - - - Baud rate: 115200 - - Data bits: 8 bits - - Check Digit: None - - Stop bit: 1 - - Flow Control Bits: None - - Data encoding method: ASCII - -## DIP Switch S1 - -- Bit 1 and 2 controls boot mode - -| bit[2:1] | Description | -| -------- | ---------------------------- | -| OFF, OFF | Boot from Quad SPI NOR flash | -| OFF, ON | Serial boot | -| ON, OFF | ISP | - -(lab_hpm6300_evk_board)= -## Button - -(lab_hpm6300_evk_board_buttons)= -| Function | Position | -| ---- | -------- | -|PBUTN (sw3) |Power Button, TinyUF2 Boot Button, GPIO Button | -|WBUTN (sw1) | WAKE UP Button | -|RESET (sw2) | Reset Button | - -## Pin Description - -- SPI Pin： - -| Function | Position | -| ---- | -------- | -| SPI3.CSN | J28[24] | -| SPI3.SCLK | J28[23] | -| SPI3.MISO | J28[21] | -| SPI3.MOSI | J28[19] | - -- I2C Pin： - -| Function | Position | -| ---- | -------- | -| I2C0.SCL | J28[13] | -| I2C0.SDA | J28[15] | - -- ACMP Pin - -| Function | Position | -| ---- | -------- | -| CMP.INN5 | J26[7] | -| CMP.COMP_1 | J26[5] | - -- GPTMR Pin - -| Function | Position | -| ---- | -------- | -| GPTMR2.CAPT_2 | J28[40] | -| GPTMR2.COMP_2 | J28[35] | \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md deleted file mode 100644 index e5d3b3fc2d..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md +++ /dev/null @@ -1,73 +0,0 @@ -# HPM6300EVK开发板 - - -::::{important} -:::{note} -添加内容 -::: -:::: - -## 概述 - - -- 控制台串口参数： - - - 波特率：115200 - - 数据位：8位 - - 校验位：无 - - 停止位：1 - - 流控位：无 - - 数据编码方式：ASCII - -## 拨码开关 S1 - -- Bit 1，2控制启动模式 - -| Bit[2:1] | 功能描述 | -| -------- | ----------------------- | -| OFF, OFF | Quad SPI NOR flash 启动 | -| OFF, ON | 串行启动 | -| ON, OFF | 在系统编程 | - -(lab_hpm6300_evk_board)= -## 按键 - -(lab_hpm6300_evk_board_buttons)= -| 名称 | 功能 | -| ---- | -------- | -|PBUTN (sw3) | 电源按键, TinyUF2 Boot按键, GPIO 按键| -|WBUTN (sw1) | WAKE UP 按键| -|RESET (sw2) | Reset 按键| - - -## 引脚描述 - -- SPI引脚： - -| 功能 | 位置 | -| ---- | -------- | -| SPI3.CSN | J28[24] | -| SPI3.SCLK | J28[23] | -| SPI3.MISO | J28[21] | -| SPI3.MOSI | J28[19] | - -- I2C引脚： - -| 功能 | 位置 | -| ---- | -------- | -| I2C0.SCL | J28[13] | -| I2C0.SDA | J28[15] | - -- ACMP引脚 - -| 功能 | 位置 | -| ---- | -------- | -| CMP.INN5 | J26[7] | -| CMP.COMP_1 | J26[5] | - -- GPTMR引脚 - -| 功能 | 位置 | -| ---- | -------- | -| GPTMR2.CAPT_2 | J28[40] | -| GPTMR2.COMP_2 | J28[35] | diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README.md deleted file mode 100644 index 97772a5be5..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README.md +++ /dev/null @@ -1,104 +0,0 @@ -# HPM6750EVK - -## Overview - -The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also, it provides various memory interfaces, including SDRAM, Quad SPI NOR Flash, SD/eMMC. It integrates rich audio and video interfaces, including LCD, pixel DMA, camera， and I2S audio interfaces. - - ![hpm6750evk](../../doc/images/boards/hpm6750evk/hpm6750evk.png "hpm6750evk") - -## Hardware - -- HPM6750IVM MCU (816Mhz, 2MB OCRAM) -- Onboard Memory - - 256Mb SDRAM - - 128Mb Quad SPI NOR Flash -- Display & Camera - - LCD connector - - Camera (DVP) -- Ethernet - - 1000 Mbits PHY - - 100 Mbits PHY -- USB - - USB type C (USB 2.0 OTG) connector x3 -- Audio - - Line in - - Mic - - Speaker - - DAO -- Others - - TF Slot - - FT2232 - - Beeper - - RGB LED - - CAN -- Expansion port - - Motor control - -## DIP Switch S1 - -- Bit 1 and 2 controls boot mode - -| bit[2:1] | Description | -| -------- | ---------------------------- | -| OFF, OFF | Boot from Quad SPI NOR flash | -| OFF, ON | Serial boot | -| ON, OFF | ISP | - -- Change the position of bit 3 to select between PWM and 1000Mbit ethernet - -| Bit3 | Description | -| ---- | -------------- | -| OFF | 1000Mbits ENET | -| ON | PWM | - -(lab_hpm6750_evk_board)= -## Button -(lab_hpm6750_evk_board_buttons)= -| Name | FUNCTIONS | -| ---- | -------- | -|PBUTN (S2) | Power Button, TinyUF2 Boot Button, GPIO Button | -|WBUTN (S3) | WAKE UP Button | -|RESET (S4) | Reset Button | - -## Pin Description - -- PWM Pin: - - ![image-1](../../doc/images/boards/hpm6750evk/hpm6750evk_pwm_output_pin.png "image-1") - -- SPI Pin： - -| Function | Position | -| ---- | -------- | -| SPI2.CSN | J20[6] | -| SPI2.SCLK | J20[7] | -| SPI2.MISO | J20[8] | -| SPI2.MOSI | J20[9] | - -- I2C Pin： - -| Function | Position | -| ---- | -------- | -| I2C0.SCL | J20[3] | -| I2C0.SDA | J20[4] | - -- UART for core1 debug console - -| Function | Position | -| ---- | -------- | -| UART13.TXD | J20[5] | -| UART13.RXD | J20[6] | - -- ACMP Pin - -| Function | Position | -| ---- | -------- | -| CMP.INN6 | J12[8] | -| CMP.COMP_1 | J12[6] | - -- GPTMR Pin - -| Function | Function | -| ---- | -------- | -| GPTMR4.CAPT_1 | J12[6] | -| GPTMR3.COMP_1 | J12[7] | diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md deleted file mode 100644 index 80dfcabb93..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md +++ /dev/null @@ -1,107 +0,0 @@ -# HPM6750EVK开发板 - -## 概述 - -HPM6750是一款主频达816Mhz的双核微控制器。该芯片拥有最大2M字节的连续片上RAM，并集成了丰富的存储接口，如SDRAM，Quad SPI NOR flash， SD/eMMC卡。同时它也提供多种音视频接口包括LCD显示，像素DMA，摄像头以及I2S音频接口。 - - ![hpm6750evk](../../doc/images/boards/hpm6750evk/hpm6750evk.png "hpm6750evk") - -## 板上硬件资源 - -- HPM6750IVM 微控制器 (主频816Mhz, 2MB片上内存) -- 板载存储 - - 256Mb SDRAM - - 128Mb Quad SPI NOR Flash -- 显示/摄像头 - - LCD接口 - - 摄像头(DVP)接口 -- 以太网 - - 1000 Mbits PHY - - 100 Mbits PHY -- USB - - USB type C (USB 2.0 OTG) connector x3 -- 音频 - - Line in - - Mic - - Speaker - - DAO -- 其他 - - TF卡槽 - - FT2232 - - 蜂鸣器 - - RGB LED - - CAN -- 扩展口 - - 电机控制 - -## 拨码开关 S1 - -- Bit 1，2控制启动模式 - -| Bit[2:1] | 功能描述 | -| -------- | ----------------------- | -| OFF, OFF | Quad SPI NOR flash 启动 | -| OFF, ON | 串行启动 | -| ON, OFF | 在系统编程 | - -- Bit 3用于选择PWM或是千兆网口 - -| Bit3 | 功能描述 | -| ---- | -------- | -| OFF | 千兆网口 | -| ON | PWM | - -(lab_hpm6750_evk_board)= -## 按键 - -(lab_hpm6750_evk_board_buttons)= -| 名称 | 功能 | -| ---- | -------- | -|PBUTN (S2) | 电源按键, TinyUF2 Boot按键, GPIO 按键| -|WBUTN (S3) | WAKE UP 按键| -|RESET (S4) | Reset 按键| - -## 引脚描述 - -- J12端子的 `P-UH 、P-UL`引脚为PWM输出引脚，如下图所示 - - ![image-1](../../doc/images/boards/hpm6750evk/hpm6750evk_pwm_output_pin.png "image-1") - -- SPI引脚： - -| 功能 | 位置 | -| ---- | -------- | -| SPI2.CSN | J20[6] | -| SPI2.SCLK | J20[7] | -| SPI2.MISO | J20[8] | -| SPI2.MOSI | J20[9] | - -- I2C引脚： - -| 功能 | 位置 | -| ---- | -------- | -| I2C0.SCL | J20[3] | -| I2C0.SDA | J20[4] | - -- CORE1调试串口引脚： - -| 功能 | 位置 | -| ---- | -------- | -| UART13.TXD | J20[5] | -| UART13.RXD | J20[6] | - -- ACMP引脚 - -| 功能 | 位置 | -| ---- | -------- | -| CMP.INN6 | J12[8] | -| CMP.COMP_1 | J12[6] | - -- GPTMR引脚 - -| 功能 | 位置 | -| ---- | -------- | -| GPTMR4.CAPT_1 | J12[6] | -| GPTMR3.COMP_1 | J12[7] | - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README.md deleted file mode 100644 index 97e3a3e929..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README.md +++ /dev/null @@ -1,86 +0,0 @@ -# HPM6750EVKMINI - -## Overview - -The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also, it provides various memory interfaces, including SDRAM, Quad SPI NOR Flash, SD/eMMC. It integrates rich audio and video interfaces, including LCD, pixel DMA, camera， and I2S audio interfaces. - - ![hpm6750evkmini](../../doc/images/boards/hpm6750evkmini/hpm6750evkmini.png "hpm6750evkmini") -## Hardware -- HPM6750IVM MCU (816Mhz, 2MB OCRAM) -- Onboard Memory - - 128Mb SDRAM - - 64Mb Quad SPI NOR Flash -- Display & Camera - - LCD connector - - Camera (DVP) -- WiFi - - RW007 over SPI -- USB - - USB type C (USB 2.0 OTG) connector x2 -- Audio - - Mic - - DAO -- Others - - TF Slot - - FT2232 - - Beeper - - RGB LED -- Expansion port - - ART-PI extension port -## DIP Switch S1 -- Bit 1 and 2 controls boot mode - -| bit[2:1] | Description| -|----------|------------| -|OFF, OFF| Boot from Quad SPI NOR flash | -|OFF, ON| Serial boot | -|ON, OFF| ISP | - -(lab_hpm6750_evkmini_board)= -## Button -(lab_hpm6750_evkmini_board_buttons)= -| Name | FUNCTIONS | -|----------|------------| -|PBUTN (S2) | Power Button, TinyUF2 Boot Button, GPIO Button | -|WBUTN (S3) | WAKE UP Button | -|RESET (S4) | Reset Button | - -## Pin Description - - -- SPI Pin - -| Function | Position | -| ---- | -------- | -| SPI2.CSN | P1[24] | -| SPI2.SCLK | P1[23] | -| SPI2.MISO | P1[21] | -| SPI2.MOSI | P1[19] | - -- I2C Pin： - -| Function | Position | -| ---- | -------- | -| I2C0.SCL | P1[13] | -| I2C0.SDA | P1[15] | - -- UART for core1 debug console： - -| Function | Position | -| ---- | -------- | -| UART13.TXD | P1[8] | -| UART13.RXD | P1[10] | - -- ACMP Pin - -| Function | Position | -| ---- | -------- | -| CMP.INN6 | P2[11] | -| CMP.COMP_1 | P1[7] | - -- GPTMR Pin - -| Function | Position | -| ---- | -------- | -| GPTMR2.CAPT_2 | P2[15] | -| GPTMR2.COMP_2 | P2[19] | \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md deleted file mode 100644 index c17fe961ea..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md +++ /dev/null @@ -1,86 +0,0 @@ -# HPM6750EVKMINI开发板 - -## 概述 -HPM6750是一款主频达816Mhz的双核微控制器。该芯片拥有最大2M字节的连续片上RAM，并集成了丰富的存储接口，如SDRAM，Quad SPI NOR flash， SD/eMMC卡。同时它也提供多种音视频接口包括LCD显示，像素DMA，摄像头以及I2S音频接口。 - - ![hpm6750evkmini](../../doc/images/boards/hpm6750evkmini/hpm6750evkmini.png "hpm6750evkmini") -## 板上硬件资源 -- HPM6750IVM 微控制器 (主频816Mhz, 2MB片上内存) -- 板载存储 - - 128Mb SDRAM - - 64Mb Quad SPI NOR Flash -- 显示/摄像头 - - LCD接口 - - 摄像头(DVP)接口 -- WiFi - - RW007 -- USB - - USB type C (USB 2.0 OTG) connector x2 -- 音频 - - Mic - - DAO -- 其他 - - TF卡槽 - - FT2232 - - 蜂鸣器 - - RGB LED -- 扩展口 - - ART-PI -## 拨码开关 S1 -- Bit 1，2控制启动模式 - -| Bit[2:1] | 功能描述| -|----------|------------| -|OFF, OFF| Quad SPI NOR flash 启动 | -|OFF, ON| 串行启动 | -|ON, OFF| 在系统编程 | - -(lab_hpm6750_evkmini_board)= -## 按键 -(lab_hpm6750_evkmini_board_buttons)= -| 名称 | 功能 | -|----------|------------| -|PBUTN (S2) | 电源按键, TinyUF2 Boot按键, GPIO 按键| -|WBUTN (S3) | WAKE UP 按键| -|RESET (S4) | Reset 按键| - - -## 引脚描述 - - -- SPI引脚： - -| 功能 | 位置 | -| ---- | -------- | -| SPI2.CSN | P1[24] | -| SPI2.SCLK | P1[23] | -| SPI2.MISO | P1[21] | -| SPI2.MOSI | P1[19] | - -- I2C引脚： - -| 功能 | 位置 | -| ---- | -------- | -| I2C0.SCL | P1[13] | -| I2C0.SDA | P1[15] | - -- CORE1调试串口引脚： - -| 功能 | 位置 | -| ---- | -------- | -| UART13.TXD | P1[8] | -| UART13.RXD | P1[10] | - -- ACMP引脚 - -| 功能 | 位置 | -| ---- | -------- | -| CMP.INN6 | P2[11] | -| CMP.COMP_1 | P1[7] | - -- GPTMR引脚 - -| 功能 | 位置 | -| ---- | -------- | -| GPTMR2.CAPT_2 | P2[15] | -| GPTMR2.COMP_2 | P2[19] | \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.c deleted file mode 100644 index 29c32bdd85..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.c +++ /dev/null @@ -1,955 +0,0 @@ -/* - * Copyright (c) 2021 - 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "board.h" -#include "hpm_uart_drv.h" -#include "hpm_gptmr_drv.h" -#include "hpm_lcdc_drv.h" -#include "hpm_i2c_drv.h" -#include "hpm_gpio_drv.h" -#include "hpm_debug_console.h" -#include "hpm_dram_drv.h" -#include "pinmux.h" -#include "hpm_pmp_drv.h" -#include "assert.h" -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_sdxc_drv.h" -#include "hpm_sdxc_soc_drv.h" -#include "hpm_pllctl_drv.h" -#include "hpm_pwm_drv.h" - -static board_timer_cb timer_cb; - -/** - * @brief FLASH configuration option definitions: - * option[0]: - * [31:16] 0xfcf9 - FLASH configuration option tag - * [15:4] 0 - Reserved - * [3:0] option words (exclude option[0]) - * option[1]: - * [31:28] Flash probe type - * 0 - SFDP SDR / 1 - SFDP DDR - * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) - * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V - * 6 - OctaBus DDR (SPI -> OPI DDR) - * 8 - Xccela DDR (SPI -> OPI DDR) - * 10 - EcoXiP DDR (SPI -> OPI DDR) - * [27:24] Command Pads after Power-on Reset - * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI - * [23:20] Command Pads after Configuring FLASH - * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI - * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) - * 0 - Not needed - * 1 - QE bit is at bit 6 in Status Register 1 - * 2 - QE bit is at bit1 in Status Register 2 - * 3 - QE bit is at bit7 in Status Register 2 - * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 - * [15:8] Dummy cycles - * 0 - Auto-probed / detected / default value - * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet - * [7:4] Misc. - * 0 - Not used - * 1 - SPI mode - * 2 - Internal loopback - * 3 - External DQS - * [3:0] Frequency option - * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz - * - * option[2] (Effective only if the bit[3:0] in option[0] > 1) - * [31:20] Reserved - * [19:16] IO voltage - * 0 - 3V / 1 - 1.8V - * [15:12] Pin group - * 0 - 1st group / 1 - 2nd group - * [11:8] Connection selection - * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) - * [7:0] Drive Strength - * 0 - Default value - * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports - * JESD216) - * [31:16] reserved - * [15:12] Sector Erase Command Option, not required here - * [11:8] Sector Size Option, not required here - * [7:0] Flash Size Option - * 0 - 4MB / 1 - 8MB / 2 - 16MB - */ -#if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; -#endif - -#if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; -#endif - -void board_init_console(void) -{ -#if BOARD_CONSOLE_TYPE == console_type_uart - console_config_t cfg; - - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); - - cfg.type = BOARD_CONSOLE_TYPE; - cfg.base = (uint32_t) BOARD_CONSOLE_BASE; - cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); - cfg.baudrate = BOARD_CONSOLE_BAUDRATE; - - init_uart_pins((UART_Type *) cfg.base); - - if (status_success != console_init(&cfg)) { - /* failed to initialize debug console */ - while (1) { - } - } -#else - while(1); -#endif -} - -void board_print_clock_freq(void) -{ - printf("==============================\n"); - printf(" %s clock summary\n", BOARD_NAME); - printf("==============================\n"); - printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); - printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); - printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0)); - printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1)); - printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2)); - printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); - printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); - printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); - printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); - printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); - printf("display:\t %luHz\n", clock_get_frequency(clock_display)); - printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); - printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); - printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); - printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); - printf("==============================\n"); -} - -void board_init_uart(UART_Type *ptr) -{ - init_uart_pins(ptr); -} - -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ -} - -void board_print_banner(void) -{ - const uint8_t banner[] = {"\n\ -----------------------------------------------------------------------\n\ -$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ -$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ -$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ -$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ -$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ -$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ -$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ -\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ -----------------------------------------------------------------------\n"}; - printf("%s", banner); -} - -static void board_turnoff_rgb_led(void) -{ - uint8_t port_pin18_status; - uint8_t port_pin19_status; - uint8_t port_pin20_status; - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; - - HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; - HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; - HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; - - port_pin18_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 18); - port_pin19_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 19); - port_pin20_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 20); -/** - * hpm board evkmini Rev. B led light modification, resulting in two versions of rgb led processing different - * - */ - if ((port_pin18_status & port_pin19_status & port_pin20_status) == 0) { - /*Mini Rev B*/ - pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); - HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; - HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; - HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; - } -} - -void board_ungate_mchtmr_at_lp_mode(void) -{ - /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ - sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); -} - -void board_init(void) -{ - board_turnoff_rgb_led(); - board_init_clock(); - board_init_console(); - board_init_pmp(); - board_init_ahb(); -#if BOARD_SHOW_CLOCK - board_print_clock_freq(); -#endif -#if BOARD_SHOW_BANNER - board_print_banner(); -#endif -} - -void board_init_sdram_pins(void) -{ - init_sdram_pins(); -} - -uint32_t board_init_dram_clock(void) -{ - clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ - return clock_get_frequency(clock_dram); -} - -void board_power_cycle_lcd(void) -{ - /* turn off backlight */ - gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); - - board_delay_ms(150); - /* power recycle */ - gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); - board_delay_ms(20); - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); - board_delay_ms(150); - - /* turn on backlight */ - gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); - -} - -void board_init_lcd(void) -{ - board_init_lcd_clock(); - init_lcd_pins(BOARD_LCD_BASE); - board_power_cycle_lcd(); -} - -void board_delay_ms(uint32_t ms) -{ - clock_cpu_delay_ms(ms); -} - -void board_timer_isr(void) -{ - if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { - gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); - timer_cb(); - } -} -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); - -void board_timer_create(uint32_t ms, board_timer_cb cb) -{ - uint32_t gptmr_freq; - gptmr_channel_config_t config; - - timer_cb = cb; - gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); - - clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); - gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); - - config.reload = gptmr_freq / 1000 * ms; - gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); - gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); - intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); - - gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); -} - -void board_i2c_bus_clear(I2C_Type *ptr) -{ - init_i2c_pins_as_gpio(ptr); - if (ptr == BOARD_CAP_I2C_BASE) { - gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN); - gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); - if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { - printf("CLK is low, please power cycle the board\n"); - while (1) {} - } - if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { - printf("SDA is low, try to issue I2C bus clear\n"); - } else { - printf("I2C bus is ready\n"); - return; - } - - gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); - for (uint8_t i = 0; i < 3; i++) { - for (uint32_t j = 0; j < 9; j++) { - gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1); - board_delay_ms(10); - gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0); - board_delay_ms(10); - } - board_delay_ms(100); - } - printf("I2C bus is cleared\n"); - } -} - -void board_init_i2c(I2C_Type *ptr) -{ - hpm_stat_t stat; - uint32_t freq; - i2c_config_t config; - - board_i2c_bus_clear(ptr); - - init_i2c_pins(ptr); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); - - config.i2c_mode = i2c_mode_normal; - config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); - stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); - if (stat != status_success) { - printf("failed to initialize i2c 0x%lx\n", (uint32_t)BOARD_CAP_I2C_BASE); - while (1) {} - } -} - -uint32_t board_init_uart_clock(UART_Type *ptr) -{ - uint32_t freq = 0U; - if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart0); - } else if (ptr == HPM_UART6) { - clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart6); - } else if (ptr == HPM_UART7) { - clock_set_source_divider(clock_uart7, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart7); - } else if (ptr == HPM_UART13) { - clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart13); - } else if (ptr == HPM_UART14) { - clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart14); - } else { - /* Not supported */ - } - return freq; -} - -uint32_t board_init_spi_clock(SPI_Type *ptr) -{ - if (ptr == HPM_SPI2) { - /* SPI2 clock configure */ - clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); - - return clock_get_frequency(clock_spi2); - } else { - return 0; - } -} - -void board_init_cap_touch(void) -{ - init_cap_pins(); - gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0); - gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); - - board_delay_ms(1); - gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); - board_delay_ms(10); - gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); - - gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); - board_init_i2c(BOARD_CAP_I2C_BASE); -} - - -void board_init_gpio_pins(void) -{ - init_gpio_pins(); -} - -void board_init_spi_pins(SPI_Type *ptr) -{ - init_spi_pins(ptr); -} - -void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) -{ - init_spi_pins_with_gpio_as_cs(ptr); - gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), - GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); -} - -void board_write_spi_cs(uint32_t pin, uint8_t state) -{ - gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); -} - -void board_init_led_pins(void) -{ - init_led_pins_as_gpio(); - gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); -} - -void board_led_toggle(void) -{ - static uint8_t i; - if(BOARD_LED_PULL_STATUS){ - /* hpm6750 Mini Rev A led configure*/ - gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN); - } - else{ - /* hpm6750 Mini Rev B led configure*/ - gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, ((1 << i)) << BOARD_G_GPIO_PIN); - } - i++; - i = i % 3; -} - -void board_led_write(uint8_t state) -{ - gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); -} - -void board_init_cam_pins(void) -{ - init_cam_pins(HPM_CAM0); -} - -void board_init_usb_pins(void) -{ - /* set pull-up for USBx OC pin and ID pin */ - init_usb_pins(HPM_USB0); - - /* configure USBx ID pin as input function */ - gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); - - /* configure USBx OC Flag pin as input function */ - gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); -} - -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ -} - -void board_init_pmp(void) -{ - extern uint32_t __noncacheable_start__[]; - extern uint32_t __noncacheable_end__[]; - - uint32_t start_addr = (uint32_t) __noncacheable_start__; - uint32_t end_addr = (uint32_t) __noncacheable_end__; - uint32_t length = end_addr - start_addr; - - if (length == 0) { - return; - } - - /* Ensure the address and the length are power of 2 aligned */ - assert((length & (length - 1U)) == 0U); - assert((start_addr & (length - 1U)) == 0U); - - pmp_entry_t pmp_entry[1]; - pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); - pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); - - pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); -} - -void board_init_clock(void) -{ - uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); - if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { - /* Configure the External OSC ramp-up time: ~9ms */ - pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); - - /* Select clock setting preset1 */ - sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); - } - - /* Add most Clocks to group 0 */ - clock_add_to_group(clock_cpu0, 0); - clock_add_to_group(clock_mchtmr0, 0); - clock_add_to_group(clock_axi0, 0); - clock_add_to_group(clock_axi1, 0); - clock_add_to_group(clock_axi2, 0); - clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_dram, 0); - clock_add_to_group(clock_xpi0, 0); - clock_add_to_group(clock_xpi1, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_gptmr4, 0); - clock_add_to_group(clock_gptmr5, 0); - clock_add_to_group(clock_gptmr6, 0); - clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); - clock_add_to_group(clock_uart6, 0); - clock_add_to_group(clock_uart7, 0); - clock_add_to_group(clock_uart13, 0); - clock_add_to_group(clock_uart14, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_can2, 0); - clock_add_to_group(clock_can3, 0); - clock_add_to_group(clock_display, 0); - clock_add_to_group(clock_sdxc0, 0); - clock_add_to_group(clock_sdxc1, 0); - clock_add_to_group(clock_camera0, 0); - clock_add_to_group(clock_camera1, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_eth0, 0); - clock_add_to_group(clock_eth1, 0); - clock_add_to_group(clock_sdp, 0); - clock_add_to_group(clock_xdma, 0); - clock_add_to_group(clock_ram0, 0); - clock_add_to_group(clock_ram1, 0); - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_usb1, 0); - clock_add_to_group(clock_jpeg, 0); - clock_add_to_group(clock_pdma, 0); - clock_add_to_group(clock_kman, 0); - clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_hdma, 0); - clock_add_to_group(clock_rng, 0); - clock_add_to_group(clock_mot0, 0); - clock_add_to_group(clock_mot1, 0); - clock_add_to_group(clock_mot2, 0); - clock_add_to_group(clock_mot3, 0); - clock_add_to_group(clock_acmp, 0); - clock_add_to_group(clock_dao, 0); - clock_add_to_group(clock_msyn, 0); - clock_add_to_group(clock_lmm0, 0); - clock_add_to_group(clock_lmm1, 0); - - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_adc2, 0); - clock_add_to_group(clock_adc3, 0); - - clock_add_to_group(clock_i2s0, 0); - clock_add_to_group(clock_i2s1, 0); - clock_add_to_group(clock_i2s2, 0); - clock_add_to_group(clock_i2s3, 0); - - /* Add the CPU1 clock to Group1 */ - clock_add_to_group(clock_mchtmr1, 1); - clock_add_to_group(clock_mbx1, 1); - - /* Connect Group0 to CPU0 */ - clock_connect_group_to_cpu(0, 0); - - if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { - printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); - while(1); - } - - clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); - clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); - /* Connect Group1 to CPU1 */ - clock_connect_group_to_cpu(1, 1); - - clock_update_core_clock(); -} - -uint32_t board_init_cam_clock(CAM_Type *ptr) -{ - uint32_t freq = 0; - if (ptr == HPM_CAM0) { - /* Configure camera clock to 24MHz */ - clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); - freq = clock_get_frequency(clock_camera0); - } else if (ptr == HPM_CAM1) { - /* Configure camera clock to 24MHz */ - clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); - freq = clock_get_frequency(clock_camera1); - } else { - /* Invalid camera instance */ - } - return freq; -} - -uint32_t board_init_lcd_clock(void) -{ - uint32_t freq; - clock_add_to_group(clock_display, 0); - /* Configure LCDC clock to 29.7MHz */ - clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); - freq = clock_get_frequency(clock_display); - return freq; -} - -uint32_t board_init_adc12_clock(ADC12_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; -} - -uint32_t board_init_dao_clock(void) -{ - clock_add_to_group(clock_dao, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); - - return clock_get_frequency(clock_dao); -} - -uint32_t board_init_pdm_clock(void) -{ - clock_add_to_group(clock_pdm, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - - return clock_get_frequency(clock_pdm); -} - -uint32_t board_init_i2s_clock(I2S_Type *ptr) -{ - if (ptr == HPM_I2S0) { - clock_add_to_group(clock_i2s0, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - - return clock_get_frequency(clock_i2s0); - } else { - return 0; - } -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr) -{ - uint32_t freq = 0; - if (ptr == HPM_ADC3) { - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc3); - } - - return freq; -} - -void board_init_can(CAN_Type *ptr) -{ - init_can_pins(ptr); -} - -uint32_t board_init_can_clock(CAN_Type *ptr) -{ - uint32_t freq = 0; - if (ptr == HPM_CAN0) { - /* Set the CAN0 peripheral clock to 80MHz */ - clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); - freq = clock_get_frequency(clock_can0); - } else if (ptr == HPM_CAN1) { - /* Set the CAN1 peripheral clock to 80MHz */ - clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); - freq = clock_get_frequency(clock_can1); - } else if (ptr == HPM_CAN2) { - /* Set the CAN2 peripheral clock to 80MHz */ - clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); - freq = clock_get_frequency(clock_can2); - } else if (ptr == HPM_CAN3) { - /* Set the CAN3 peripheral clock to 80MHz */ - clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); - freq = clock_get_frequency(clock_can3); - } else { - /* Invalid CAN instance */ - } - return freq; -} - -#ifdef INIT_EXT_RAM_FOR_DATA -/* - * this function will be called during startup to initialize external memory for data use - */ -void _init_ext_ram(void) -{ - uint32_t dram_clk_in_hz; - board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); - - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; - - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); - - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; - sdram_config.prescaler = 0x3; - sdram_config.burst_len_in_byte = 8; - sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; - - sdram_config.precharge_to_act_in_ns = 18; /* Trp */ - sdram_config.act_to_rw_in_ns = 18; /* Trcd */ - sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */ - sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ - sdram_config.cke_off_in_ns = 42; /* Trcd */ - sdram_config.act_to_precharge_in_ns = 42; /* Tras */ - - sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */ - sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ - sdram_config.act_to_act_in_ns = 12; /* Trrd */ - sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; - - sdram_config.cs = BOARD_SDRAM_CS; - sdram_config.base_address = BOARD_SDRAM_ADDRESS; - sdram_config.size_in_byte = BOARD_SDRAM_SIZE; - sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; - sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; - sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; - sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; - sdram_config.delay_cell_value = 29; - - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); -} -#endif - -void board_init_sd_pins(SDXC_Type *ptr) -{ - if (ptr == HPM_SDXC1) { - init_sdxc_pins(ptr, false); - } else { - while (1) { - - } - } -} - - -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) -{ - uint32_t actual_freq = 0; - do { - if (ptr != HPM_SDXC1) { - break; - } - clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; - sdxc_enable_inverse_clock(ptr, false); - sdxc_enable_sd_clock(ptr, false); - /* Configure the clock below 400KHz for the identification state */ - if (freq <= 400000UL) { - clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); - } - /* configure the clock to 24MHz for the SDR12/Default speed */ - else if (freq <= 25000000UL) { - clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); - } - /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ - else if (freq <= 50000000UL) { - clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); - } - /* Configure the clock to 100MHz for the SDR50 */ - else if (freq <= 100000000UL) { - clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4); - } - /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ - else if (freq <= 208000000UL) { - clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2); - } - /* For other unsupported clock ranges, configure the clock to 24MHz */ - else { - clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); - } - sdxc_enable_inverse_clock(ptr, true); - sdxc_enable_sd_clock(ptr, true); - actual_freq = clock_get_frequency(sdxc_clk); - } while (false); - - return actual_freq; -} - -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) -{ - sdxc_select_voltage(ptr, sdxc_bus_voltage_sd_1v8); - init_sdxc_pins(ptr, true); -} - -bool board_sd_detect_card(SDXC_Type *ptr) -{ - return sdxc_is_card_inserted(ptr); -} - -void board_init_rgb_pwm_pins(void) -{ - init_led_pins_as_pwm(); -} - -void board_disable_output_rgb_led(uint8_t color) -{ - switch (color) { - case BOARD_RGB_RED: - pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); - break; - case BOARD_RGB_GREEN: - pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); - break; - case BOARD_RGB_BLUE: - pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); - break; - default: - while (1) { - ; - } - } -} - -void board_enable_output_rgb_led(uint8_t color) -{ - switch (color) { - case BOARD_RGB_RED: - pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); - break; - case BOARD_RGB_GREEN: - pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); - break; - case BOARD_RGB_BLUE: - pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); - break; - default: - while (1) { - ; - } - } -} - -void board_init_beep_pwm_pins(void) -{ - init_beep_pwm_pins(); -} - -hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) -{ - if (ptr == HPM_ENET0) { - clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ - } else if (ptr == HPM_ENET1) { - clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ - } else { - return status_invalid_argument; - } - - return status_success; -} - -hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) -{ - if (internal == false) { - return status_success; - } - /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET0) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ - clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); - } else if (ptr == HPM_ENET1) { - /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ - clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ - } else { - return status_invalid_argument; - } - return status_success; -} - -void board_init_adc12_pins(void) -{ - init_adc12_pins(); -} - -void board_init_adc16_pins(void) -{ - init_adc16_pins(); -} - -hpm_stat_t board_init_enet_pins(ENET_Type *ptr) -{ - init_enet_pins(ptr); - - if (ptr == HPM_ENET1) { - gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); - board_delay_ms(1); - gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); - } else { - return status_invalid_argument; - } - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.h b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.h deleted file mode 100644 index e61ab02a64..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.h +++ /dev/null @@ -1,514 +0,0 @@ -/* - * Copyright (c) 2021 - 2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_BOARD_H -#define _HPM_BOARD_H -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_soc_feature.h" -#include "hpm_clock_drv.h" -#include "pinmux.h" - -#define BOARD_NAME "hpm6750evkmini" -#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) - -/* uart section */ -#ifndef BOARD_RUNNING_CORE -#define BOARD_RUNNING_CORE HPM_CORE0 -#endif -#ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART0 -#define BOARD_APP_UART_IRQ IRQn_UART0 -#else -#ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart -#endif -#endif - -/* uart rx idle demo section */ -#define BOARD_UART_IDLE HPM_UART7 -#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART7_RX - -#define BOARD_UART_IDLE_TRGM HPM_TRGM2 -#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 -#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 -#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 -#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI - -#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 -#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 -#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 -#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 -#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 - -#define BOARD_APP_UART_BAUDRATE (115200UL) -#define BOARD_APP_UART_CLK_NAME clock_uart0 - -#ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart -#endif - -#if BOARD_CONSOLE_TYPE == console_type_uart -#ifndef BOARD_CONSOLE_BASE -#if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_BASE HPM_UART0 -#define BOARD_CONSOLE_CLK_NAME clock_uart0 -#else -#define BOARD_CONSOLE_BASE HPM_UART13 -#define BOARD_CONSOLE_CLK_NAME clock_uart13 -#endif -#endif -#define BOARD_CONSOLE_BAUDRATE (115200UL) -#endif - -#define BOARD_FREEMASTER_UART_BASE HPM_UART0 -#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 -#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 - -/* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (16*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS -#define BOARD_SDRAM_REFRESH_COUNT (4096UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) -#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) - -/* lcd section */ -#define BOARD_LCD_BASE HPM_LCDC -#define BOARD_LCD_IRQ IRQn_LCDC_D0 -#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_POWER_GPIO_PIN 12 -#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23 - -/* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C0 -#define BOARD_APP_I2C_IRQ IRQn_I2C0 -#define BOARD_APP_I2C_CLK_NAME clock_i2c0 -#define BOARD_APP_I2C_DMA HPM_HDMA -#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 - -#define BOARD_CAM_I2C_BASE HPM_I2C0 -#define BOARD_CAM_I2C_CLK_NAME clock_i2c0 - -#define BOARD_CAP_I2C_BASE (HPM_I2C0) -#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 -#define BOARD_CAP_RST_GPIO (HPM_GPIO0) -#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_RST_GPIO_PIN (9) -#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) -#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) -#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_INTR_GPIO_PIN (8) -#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) -#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) -#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOB) -#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) - -/* ACMP desction */ -#define BOARD_ACMP HPM_ACMP -#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 -#define BOARD_ACMP_IRQ IRQn_ACMP_1 -#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ -#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ - -/* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX - -/* gptmr section */ -#define BOARD_GPTMR HPM_GPTMR2 -#define BOARD_GPTMR_IRQ IRQn_GPTMR2 -#define BOARD_GPTMR_CHANNEL 0 -#define BOARD_GPTMR_PWM HPM_GPTMR2 -#define BOARD_GPTMR_PWM_CHANNEL 0 - -/* gpio section */ -#define BOARD_R_GPIO_CTRL HPM_GPIO0 -#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_R_GPIO_PIN 19 -#define BOARD_G_GPIO_CTRL HPM_GPIO0 -#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_G_GPIO_PIN 18 -#define BOARD_B_GPIO_CTRL HPM_GPIO0 -#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_B_GPIO_PIN 20 - -#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL -#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX -#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN - -/* - *led Internal pull-up and pull-down resistance direction - *The configurations of Rev-A / B boards are different - */ -#define BOARD_LED_PULL_STATUS IOC_PAD_PAD_CTL_PS_GET(HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL) -#define BOARD_LED_OFF_LEVEL BOARD_LED_PULL_STATUS -#define BOARD_LED_ON_LEVEL !BOARD_LED_PULL_STATUS - -#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ -#define BOARD_APP_GPIO_PIN 2 - -/* pinmux section */ -#define USING_GPIO0_FOR_GPIOZ -#ifndef USING_GPIO0_FOR_GPIOZ -#define BOARD_APP_GPIO_CTRL HPM_BGPIO -#define BOARD_APP_GPIO_IRQ IRQn_BGPIO -#else -#define BOARD_APP_GPIO_CTRL HPM_GPIO0 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z -#endif - -/* gpiom section */ -#define BOARD_APP_GPIOM_BASE HPM_GPIOM -#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO -#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast - -/* spi section */ -#define BOARD_APP_SPI_BASE HPM_SPI2 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) -#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) -#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) -#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 -#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 -#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 -#define BOARD_SPI_CS_PIN IOC_PAD_PB24 -#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) - -/* Flash section */ -#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00000000U) - -#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) -#define BOARD_FLASH_SIZE (8 << 20) - -/* lcd section */ -#ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH (800) -#endif -#ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT (480) -#endif - -/* pdma section */ -#define BOARD_PDMA_BASE HPM_PDMA - -/* i2s section */ -#define BOARD_APP_I2S_CLK_NAME clock_i2s1 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 - - -/* enet section */ -#define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 -#define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOD -#define BOARD_ENET_RMII_RST_GPIO_PIN (15U) -#define BOARD_ENET_RMII HPM_ENET1 -#define BOARD_ENET_RMII_INT_REF_CLK (0U) -#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) - -/* adc section */ -#define BOARD_APP_ADC12_NAME "ADC0" -#define BOARD_APP_ADC12_BASE HPM_ADC0 -#define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC12_CH_1 (7U) - -#define BOARD_APP_ADC16_NAME "ADC3" -#define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC16_BASE HPM_ADC3 -#define BOARD_APP_ADC16_CH_1 (2U) - -#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 -#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 -#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 -#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 -#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT - -/* CAN section */ -#define BOARD_APP_CAN_BASE HPM_CAN1 -#define BOARD_APP_CAN_IRQn IRQn_CAN1 - -/* - * timer for board delay - */ -#define BOARD_DELAY_TIMER (HPM_GPTMR7) -#define BOARD_DELAY_TIMER_CH 0 -#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) - -#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) -#define BOARD_CALLBACK_TIMER_CH 1 -#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 -#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) - -/* timer for 1ms*/ -#define BOARD_TMR_1MS HPM_GPTMR2 -#define BOARD_TMR_1MS_CH 0 -#define BOARD_TMR_1MS_CMP 0 -#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 -#define BOARD_TMR_1MS_RELOAD (100000U) - -/* SDXC section */ -#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) -#define BOARD_APP_SDCARD_SUPPORT_1V8 (1) -#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) -#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (0) -#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO -#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO NULL -#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX 0 -#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 0 -#endif - -/* USB section */ -#define BOARD_USB0_ID_PORT (HPM_GPIO0) -#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) -#define BOARD_USB0_ID_GPIO_PIN (10) - -#define BOARD_USB0_OC_PORT (HPM_GPIO0) -#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) -#define BOARD_USB0_OC_GPIO_PIN (8) - -/* APP PWM */ -#define BOARD_APP_PWM HPM_PWM0 -#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 -#define BOARD_APP_PWM_OUT1 4 -#define BOARD_APP_PWM_OUT2 5 -#define BOARD_APP_TRGM HPM_TRGM0 - -/* RGB LED Section */ -#define BOARD_RED_PWM_IRQ IRQn_PWM1 -#define BOARD_RED_PWM HPM_PWM1 -#define BOARD_RED_PWM_OUT 0 -#define BOARD_RED_PWM_CMP 0 -#define BOARD_RED_PWM_CMP_INITIAL_ZERO true -#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 - -#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 -#define BOARD_GREEN_PWM HPM_PWM1 -#define BOARD_GREEN_PWM_OUT 1 -#define BOARD_GREEN_PWM_CMP 1 -#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true -#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 - -#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 -#define BOARD_BLUE_PWM HPM_PWM0 -#define BOARD_BLUE_PWM_OUT 7 -#define BOARD_BLUE_PWM_CMP 0 -#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true -#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 - -#define BOARD_RGB_RED 0 -#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) -#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) - -/* Beep Section */ -#define BOARD_BEEP_PWM HPM_PWM3 -#define BOARD_BEEP_PWM_OUT 4 -#define BOARD_BEEP_PWM_CLOCK_NAME clock_mot3 - -/*BLDC pwm*/ - -/*PWM define*/ -#define BOARD_BLDCPWM HPM_PWM1 -#define BOARD_BLDC_UH_PWM_OUTPIN (2U) -#define BOARD_BLDC_UL_PWM_OUTPIN (3U) -#define BOARD_BLDC_VH_PWM_OUTPIN (4U) -#define BOARD_BLDC_VL_PWM_OUTPIN (5U) -#define BOARD_BLDC_WH_PWM_OUTPIN (6U) -#define BOARD_BLDC_WL_PWM_OUTPIN (7U) -#define BOARD_BLDCPWM_TRGM HPM_TRGM1 -#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM1 -#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) -#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) -#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) -#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) -#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) -#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) - -/*HALL define*/ - -#define BOARD_BLDC_HALL_BASE HPM_HALL2 -#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 -#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 -#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 -#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 -#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P11 -#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) - - - -/*QEI*/ - -#define BOARD_BLDC_QEI_BASE HPM_QEI2 -#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 -#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 -#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 -#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 -#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) -#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 -#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) - -/*Timer define*/ - -#define BOARD_TMR_1MS HPM_GPTMR2 -#define BOARD_TMR_1MS_CH 0 -#define BOARD_TMR_1MS_CMP 0 -#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 -#define BOARD_TMR_1MS_RELOAD (100000U) - -#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS -#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH -#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP -#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ -#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD - -/*adc*/ -#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 -#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 -#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 -#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete - -#define BOARD_BLDC_ADC_CH_U (1U) -#define BOARD_BLDC_ADC_CH_V (2U) -#define BOARD_BLDC_ADC_CH_W (3U) -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 -#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) -#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG1A -#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM1_INPUT_SRC_PWM1_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 - - -#define BOARD_CPU_FREQ (816000000UL) - -#define BOARD_APP_DISPLAY_CLOCK clock_display - -#ifndef BOARD_SHOW_CLOCK -#define BOARD_SHOW_CLOCK 1 -#endif -#ifndef BOARD_SHOW_BANNER -#define BOARD_SHOW_BANNER 1 -#endif - -#ifndef BOARD_RUNNING_CORE -#define BOARD_RUNNING_CORE 0 -#endif - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -typedef void (*board_timer_cb)(void); - -void board_init(void); -void board_init_console(void); - -void board_init_uart(UART_Type *ptr); -void board_init_i2c(I2C_Type *ptr); -void board_init_lcd(void); - -void board_init_can(CAN_Type *ptr); - -uint32_t board_init_dram_clock(void); - -void board_init_sdram_pins(void); -void board_init_gpio_pins(void); -void board_init_spi_pins(SPI_Type *ptr); -void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); -void board_write_spi_cs(uint32_t pin, uint8_t state); -void board_init_led_pins(void); - -/* cap touch */ -void board_init_cap_touch(void); - -void board_led_write(uint8_t state); -void board_led_toggle(void); - -void board_fpga_power_enable(void); - -void board_init_cam_pins(void); - -/* Initialize SoC overall clocks */ -void board_init_clock(void); - -/* Initialize the UART clock */ -uint32_t board_init_uart_clock(UART_Type *ptr); - -/* Initialize the CAM(camera) dot clock */ -uint32_t board_init_cam_clock(CAM_Type *ptr); - -/* Initialize the LCD pixel clock */ -uint32_t board_init_lcd_clock(void); - -uint32_t board_init_spi_clock(SPI_Type *ptr); - -uint32_t board_init_adc12_clock(ADC12_Type *ptr); - -uint32_t board_init_adc16_clock(ADC16_Type *ptr); - -uint32_t board_init_can_clock(CAN_Type *ptr); - -uint32_t board_init_i2s_clock(I2S_Type *ptr); -uint32_t board_init_pdm_clock(void); -uint32_t board_init_dao_clock(void); - -void board_init_sd_pins(SDXC_Type *ptr); -uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); -bool board_sd_detect_card(SDXC_Type *ptr); - -void board_init_adc12_pins(void); -void board_init_adc16_pins(void); - -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); - -hpm_stat_t board_init_enet_pins(ENET_Type *ptr); -hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); -hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); - -/* - * @brief Initialize PMP and PMA for but not limited to the following purposes: - * -- non-cacheable memory initialization - */ -void board_init_pmp(void); - -void board_delay_ms(uint32_t ms); - -void board_init_beep_pwm_pins(void); -void board_init_rgb_pwm_pins(void); - -void board_timer_create(uint32_t ms, board_timer_cb cb); -void board_enable_output_rgb_led(uint8_t color); -void board_disable_output_rgb_led(uint8_t color); - -/* - * Keep mchtmr clock on low power mode - */ -void board_ungate_mchtmr_at_lp_mode(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c deleted file mode 100644 index 0dc8b5ffde..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * Copyright (c) 2021 - 2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/* - * Note: - * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, - * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that - * expected SoC function can be enabled on these IOs. - * - */ - -#include "board.h" - -void init_uart_pins(UART_Type *ptr) -{ - if (ptr == HPM_UART0) { - HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; - HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; - /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; - } else if (ptr == HPM_UART6) { - HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_UART6_RXD; - HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_UART6_TXD; - } else if (ptr == HPM_UART7) { - HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_UART7_RXD; - HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_UART7_TXD; - } else if (ptr == HPM_UART13) { - HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; - HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; - /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; - HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; - } else if (ptr == HPM_UART14) { - HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_UART14_RXD; - HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_UART14_TXD; - /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_SOC_PZ_10; - HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_SOC_PZ_11; - } -} - -void init_lcd_pins(LCDC_Type *ptr) -{ - HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; - HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; - HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; - HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3; - HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4; - HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5; - HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6; - HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7; - HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0; - HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1; - HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2; - HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3; - HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4; - HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5; - HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6; - HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7; - HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0; - HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1; - HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2; - HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3; - HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4; - HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5; - HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6; - HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7; - HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK; - HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN; - HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC; - HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC; - - /* PWM */ - HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23; - /* PWR */ - HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; -} - -void init_cap_pins(void) -{ - /* CAP_INT */ - HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; - HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08; - /* CAP_RST */ - HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; - HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09; -} - -void init_trgmux_pins(uint32_t pin) -{ - /* all trgmux pin ALT_SELECT fixed to 16*/ - HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); -} - -void init_i2c_pins_as_gpio(I2C_Type *ptr) -{ - if (ptr == HPM_I2C0) { - /* I2C0 */ - HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; - HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; - } else { - while(1); - } -} - -void init_i2c_pins(I2C_Type *ptr) -{ - if (ptr == HPM_I2C0) { - HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL - | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA - | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; - HPM_IOC->PAD[IOC_PAD_PB10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; - } else if (ptr == HPM_I2C3) { - HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_I2C3_SCL - | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_I2C3_SDA - | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; - HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; - } else { - while(1); - } -} - -void init_sdram_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_DRAM_DQ_14; - HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_DRAM_DQ_15; - HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_DRAM_DQ_12; - HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_DRAM_DQ_13; - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_DRAM_DQ_00; - HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_DRAM_DQ_10; - HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_DRAM_DQ_11; - HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_DRAM_DQ_01; - HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_DRAM_DQ_08; - HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_DRAM_DQ_09; - HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_DRAM_DQ_04; - HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DRAM_DQ_03; - HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DRAM_DQ_02; - HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_DRAM_DQ_07; - HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_DRAM_DQ_06; - HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_DRAM_DQ_05; - - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_DRAM_A_11; - HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_DRAM_A_09; - HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_DRAM_A_10; - HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_DRAM_A_08; - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_DRAM_A_07; - HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_DRAM_A_06; - HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_DRAM_A_01; - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_DRAM_A_00; - HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_DRAM_A_05; - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_DRAM_A_04; - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_DRAM_A_03; - HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_DRAM_A_02; - - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_DRAM_BA1; - HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_DRAM_BA0; - HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_DRAM_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_DRAM_CLK; - HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_DRAM_CKE; - HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_DRAM_CS_0; - HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_DRAM_RAS; - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_DRAM_CAS; - HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_DRAM_WE; - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DRAM_DM_0; - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DRAM_DM_1; -} - -void init_gpio_pins(void) -{ - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - - /* Green LED*/ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; - HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; - -#ifdef USING_GPIO0_FOR_GPIOZ - HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; - HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; - /* PZ port IO needs to configure BIOC as well */ - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; -#endif -} - -void init_spi_pins(SPI_Type *ptr) -{ - if (ptr == HPM_SPI1) { - HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_SPI1_CSN; - HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; - HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; - HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } else if (ptr == HPM_SPI2) { - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_SPI2_CSN; - HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } else if (ptr == HPM_SPI3) { - HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_SPI3_CSN; - HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; - HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; - HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } -} - -void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) -{ - if (ptr == HPM_SPI1) { - HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_GPIO_E_03; - HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; - HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; - HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } else if (ptr == HPM_SPI2) { - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; - HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } else if (ptr == HPM_SPI3) { - HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_GPIO_B_29; - HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; - HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; - HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } -} - -void init_pins(void) -{ - init_uart_pins(BOARD_CONSOLE_BASE); - init_sdram_pins(); -} - -void init_gptmr_pins(GPTMR_Type *ptr) -{ - if (ptr == HPM_GPTMR2) { - /* TMR2 capture 0 */ - HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_CAPT_0; - /* TMR2 compare 0 */ - HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_GPTMR2_COMP_0; - } -} - -void init_hall_trgm_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_TRGM2_P_09; - HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11; - HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; -} - -void init_qei_trgm_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_TRGM2_P_06; - HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_TRGM2_P_07; -} - -void init_i2s_pins(I2S_Type *ptr) -{ - if (ptr == HPM_I2S0) { - HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK; - HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK; - HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK; - HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_I2S0_RXD_1; - HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_I2S0_TXD_1; - } -} - -void init_dao_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_DAOR_P; - HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_DAOR_N; -} - -void init_pdm_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; - HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; - /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; -} - -void init_vad_pins(void) -{ - HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; - HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; -} - -void init_cam_pins(CAM_Type *ptr) -{ - if (ptr == HPM_CAM0) { - HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; - HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; - HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC; - HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC; - HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2; - HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3; - HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4; - HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5; - HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6; - HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7; - HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8; - HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9; - } -} - -void init_butn_pins(void) -{ - HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; - HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; - HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; -} - -void init_acmp_pins(void) -{ - /* configure to ACMP_COMP_1(ALT16) function */ - HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ACMP_COMP_1; - /* configure to CMP1_INP7 function */ - HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* configure to CMP1_INN6 function */ - HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; -} - -void init_enet_pins(ENET_Type *ptr) -{ - if (ptr == HPM_ENET1) { - HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; - - HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC; - HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO; - - HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1; - HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0; - HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0; - - HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN; - HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV; - HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1; - - HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PE16_FUNC_CTL_ETH1_REFCLK; - } -} - -void init_pwm_pins(PWM_Type *ptr) -{ - if (ptr == HPM_PWM0) { - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7; - HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_PWM0_P_6; - HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_PWM0_P_5; - HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_PWM0_P_4; - } else if (ptr == HPM_PWM1) { - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_PWM1_P_3; - HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_PWM1_P_2; - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_PWM1_P_5; - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_PWM1_P_4; - HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_PWM1_P_7; - HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_PWM1_P_6; - } else if (ptr == HPM_PWM3) { - HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4; - } -} - -void init_adc12_pins(void) -{ - /* ADC0/1/2/.VINP7 */ - HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2/.VINP8 */ - HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2/.VINP9 */ - HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2/.VINP10 */ - HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; -} - -void init_adc16_pins(void) -{ - /* ADC3.INA2 */ - HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; -} - -void init_adc_bldc_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; -} - -void init_usb_pins(USB_Type *ptr) -{ - if (ptr == HPM_USB0) { - /* USB0 ID */ - HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; - HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB0 OC */ - HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; - HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - } -} - -void init_can_pins(CAN_Type *ptr) -{ - if (ptr == HPM_CAN1) { - HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_CAN1_TXD; - HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_CAN1_RXD; - } -} - -void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) -{ - uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); - uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | - IOC_PAD_PAD_CTL_PS_SET(1); - - if (ptr == HPM_SDXC1) { - /* SDXC1.CLK */ - HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; - - /* SDXC1.CMD */ - HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; - HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; - - /* SDXC1.DATA0 */ - HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; - /* SDXC1.DATA1 */ - HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; - /* SDXC1.DATA2 */ - HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; - /* SDXC1.DATA3 */ - HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; - - /* SDXC1.CDN */ - HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_SDC1_CDN; - HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl; - } - - /* SDXC1.VSEL */ - HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_SDC1_VSEL; - HPM_IOC->PAD[IOC_PAD_PD29].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); -} - -void init_clk_obs_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; -} - -void init_wifi_pins(void) -{ - /* WiFi INT */ - HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_GPIO_E_01; - HPM_IOC->PAD[IOC_PAD_PE01].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_PS_MASK; - /* WiFi RST */ - HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_GPIO_E_02; - - init_spi_pins(HPM_SPI0); -} - -void init_beep_pwm_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4; -} - -void init_led_pins_as_pwm(void) -{ - /* Blue */ - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7; - /* Green */ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PWM1_P_1; - /* Red */ - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM1_P_0; -} - -void init_led_pins_as_gpio(void) -{ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/index.md b/bsp/hpmicro/libraries/hpm_sdk/boards/index.md deleted file mode 100644 index 06e9ecf9ca..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/index.md +++ /dev/null @@ -1,41 +0,0 @@ -# HPM Development Board Introduction - -This chapter describes the board-related configuration - -:::{eval-rst} -.. toctree:: - :maxdepth: 3 - :numbered: - - hpm6750evk/README - hpm6750evkmini/README - hpm6300evk/README - ../doc/boards/README - -::: - -**Board level vocabulary cross-reference table** - -(lab_board_resource)= - -:::{tab} HPM6750EVK -Click [here](lab_hpm6750_evk_board) to view the HPM6750EVK development board -::: -:::{tab} HPM6750EVKMINI -Click [here](lab_hpm6750_evkmini_board) to view the HPM6750EVKMINI development board -::: -:::{tab} HPM6300EVK -Click [here](lab_hpm6300_evk_board) to view the HPM6300EVK development board -::: - -(lab_board_lcd_pin)= -(lab_board_app_i2c_pin)= -(lab_board_cam_i2c_pin)= -(lab_board_cap_i2c_pin)= -(lab_board_rgb_pin)= -(lab_board_app_spi_pin)= -(lab_board_drv_pwm_pin)= -(lab_board_motor_ctrl_pin)= -(lab_board_overiew)= -(lab_board_app_acmp_pin)= -(lab_board_app_gptmr_pin)= diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/index_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/index_zh.md deleted file mode 100644 index 138303ea94..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/index_zh.md +++ /dev/null @@ -1,38 +0,0 @@ -# HPM 开发板介绍 - -:::{eval-rst} -.. toctree:: - :maxdepth: 3 - :numbered: - - hpm6750evk/README_zh - hpm6750evkmini/README_zh - hpm6300evk/README_zh - ../doc/boards/README_zh - -::: - -**开发板引脚对照表** - -:::{tab} HPM6750EVK -点击{ref}`此处 `查看HPM6750EVK开发板 -::: -:::{tab} HPM6750EVKMINI -点击{ref}`此处 `查看HPM6750EVKMINI开发板 -::: -:::{tab} HPM6300EVK -点击{ref}`此处 `查看HPM6300EVK开发板 -::: - -(lab_board_resource)= -(lab_board_lcd_pin)= -(lab_board_app_i2c_pin)= -(lab_board_cam_i2c_pin)= -(lab_board_cap_i2c_pin)= -(lab_board_rgb_pin)= -(lab_board_app_spi_pin)= -(lab_board_drv_pwm_pin)= -(lab_board_motor_ctrl_pin)= -(lab_board_overiew)= -(lab_board_app_acmp_pin)= -(lab_board_app_gptmr_pin)= diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg deleted file mode 100644 index f7fff1cb69..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright 2022 hpmicro -# SPDX-License-Identifier: BSD-3-Clause -# -# assumptions: -# - HPM_SDK_BASE has been defined as environment variable pointing to correct hpm_sdk path -# - current directory is ${HPM_SDK_BASE}/boards/openocd -# -# usage: -# # connect hpm6300evk via ft2232, debugging single core -# $ openocd -c "set HPM_SDK_BASE ${HPM_SDK_BASE}; set BOARD hpm6300evk; set PROBE ft2232;" -f hpm6300_all_in_one.cfg -# -# # supported board to be set to BOARD: -# - hpm6300evk -# - hpm6360evk -# # supported probes to be set to PROBE: -# - ft2232 -# - ft232 -# - jlink -# - cmsis_dap -# - nds_aice_micro - -set HPM_OPENOCD_CONFIG ${HPM_SDK_BASE}/boards/openocd - -if { ![info exists PROBE ] } { - set PROBE ft2232 -} - -if { ![info exists BOARD] } { - set BOARD hpm6300evk -} - -source ${HPM_OPENOCD_CONFIG}/probes/${PROBE}.cfg -source ${HPM_OPENOCD_CONFIG}/soc/hpm6360.cfg -source ${HPM_OPENOCD_CONFIG}/boards/${BOARD}.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg deleted file mode 100644 index cc78b45354..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright 2021 hpmicro -# SPDX-License-Identifier: BSD-3-Clause -# -# assumptions: -# - HPM_SDK_BASE has been defined as environment variable pointing to correct hpm_sdk path -# - current directory is ${HPM_SDK_BASE}/boards/openocd -# -# usage: -# # connect hpm6750evkmini via ft2232, debugging single core -# $ openocd -c "set HPM_SDK_BASE ${HPM_SDK_BASE}; set BOARD hpm6750evkmini; set PROBE ft2232;" -f hpm6750_all_in_one.cfg -# # connect hpm6750evkmini via ft2232, debugging dual core -# $ openocd -c "set HPM_SDK_BASE ${HPM_SDK_BASE}; set BOARD hpm6750evkmini; set PROBE ft2232; set ENABLE_DUALCORE 1" -f hpm6750_all_in_one.cfg -# -# # supported board to be set to BOARD: -# - hpm6750evk -# - hpm6750evkmini -# # supported probes to be set to PROBE: -# - ft2232 -# - ft232 -# - jlink -# - cmsis_dap -# - nds_aice_micro -# # supported core debug type to ENABLE_DUALCORE: -# - 1: enable dual core debugging - -set HPM_OPENOCD_CONFIG ${HPM_SDK_BASE}/boards/openocd - -if { ![info exists PROBE ] } { - set PROBE ft2232 -} - -if { ![info exists BOARD] } { - set BOARD hpm6750evkmini -} - -if { [info exists ENABLE_DUALCORE] && $ENABLE_DUALCORE == 1 } { - set CORE hpm6750-dual-core -} else { - set CORE hpm6750-single-core -} - -source ${HPM_OPENOCD_CONFIG}/probes/${PROBE}.cfg -source ${HPM_OPENOCD_CONFIG}/soc/${CORE}.cfg -source ${HPM_OPENOCD_CONFIG}/boards/${BOARD}.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360-csr.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360-csr.cfg deleted file mode 100644 index abaeb2f373..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360-csr.cfg +++ /dev/null @@ -1,50 +0,0 @@ -riscv expose_csrs 262=scounteren -riscv expose_csrs 800=mcountinhibit -riscv expose_csrs 1984=milmb -riscv expose_csrs 1985=mdlmb -riscv expose_csrs 1986=mecc_code -riscv expose_csrs 1987=mnvec -riscv expose_csrs 1988=mxstatus -riscv expose_csrs 1989=mpft_ctl -riscv expose_csrs 1990=mhsp_ctl -riscv expose_csrs 1991=msp_bound -riscv expose_csrs 1992=msp_base -riscv expose_csrs 1993=mdcause -riscv expose_csrs 1994=mcache_ctl -riscv expose_csrs 1995=mcctlbeginaddr -riscv expose_csrs 1996=mcctlcommand -riscv expose_csrs 1997=mcctldata -riscv expose_csrs 1998=mcounterwen -riscv expose_csrs 1999=mcounterinten -riscv expose_csrs 2000=mmisc_ctl -riscv expose_csrs 2001=mcountermask_m -riscv expose_csrs 2002=mcountermask_s -riscv expose_csrs 2003=mcountermask_u -riscv expose_csrs 2004=mcounterovf -riscv expose_csrs 2005=mslideleg -riscv expose_csrs 2015=mclk_ctl -riscv expose_csrs 2016=dexc2dbg -riscv expose_csrs 2017=ddcause -riscv expose_csrs 2048=uitb -riscv expose_csrs 2049=ucode -riscv expose_csrs 2057=udcause -riscv expose_csrs 2059=ucctlbeginaddr -riscv expose_csrs 2060=ucctlcommand -riscv expose_csrs 2500=slie -riscv expose_csrs 2501=slip -riscv expose_csrs 2505=sdcause -riscv expose_csrs 2509=scctldata -riscv expose_csrs 2511=scounterinten -riscv expose_csrs 2513=scountermask_m -riscv expose_csrs 2514=scountermask_s -riscv expose_csrs 2515=scountermask_u -riscv expose_csrs 2516=scounterovf -riscv expose_csrs 2528=scountinhibit -riscv expose_csrs 2531=shpmevent3 -riscv expose_csrs 2532=shpmevent4 -riscv expose_csrs 2533=shpmevent5 -riscv expose_csrs 2534=shpmevent6 -riscv expose_csrs 4032=micm_cfg -riscv expose_csrs 4033=mdcm_cfg -riscv expose_csrs 4034=mmsc_cfg -riscv expose_csrs 4035=mmsc_cfg2 diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/SConscript b/bsp/hpmicro/libraries/hpm_sdk/components/SConscript index b0bc891f0c..5fe6980bcc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/SConscript +++ b/bsp/hpmicro/libraries/hpm_sdk/components/SConscript @@ -8,30 +8,36 @@ cwd = GetCurrentDir() CPPDEFINES=[] # Update include path -path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_manager') ] +path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_manager')] # The set of source files associated with this SConscript file. src = [] src += [ os.path.join(cwd, 'debug_console', 'hpm_debug_console.c') ] src += [ os.path.join(cwd, 'dma_manager', 'hpm_dma_manager.c') ] -if GetDepend(['BSP_USING_TOUCH_GT911']): - src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_touch_gt911.c') ] - src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_gt911.c') ] - path += [ os.path.join(cwd, 'touch', 'gt911') ] - CPPDEFINES = ['CONFIG_TOUCH_GT911=1'] -if GetDepend(['BSP_USING_TOUCH_FT5406']): - src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_touch_ft5406.c') ] - src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_ft5406.c') ] - path += [ os.path.join(cwd, 'touch', 'ft5406') ] - CPPDEFINES = ['CONFIG_TOUCH_FT5406=1'] -if GetDepend(['BSP_USING_USB_DEVICE']): - src += [ os.path.join(cwd, 'usb', 'device', 'hpm_usb_device.c') ] - path += [ os.path.join(cwd, 'usb', 'device') ] -if GetDepend(['BSP_USING_USB_HOST']): - src += [ os.path.join(cwd, 'usb', 'host', 'hpm_usb_host.c') ] - path += [ os.path.join(cwd, 'usb', 'host') ] +if GetDepend(['BSP_USING_TOUCH_GT911']): + src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_touch_gt911.c') ] + src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_gt911.c') ] + path += [ os.path.join(cwd, 'touch', 'gt911') ] + CPPDEFINES = ['CONFIG_TOUCH_GT911=1'] +if GetDepend(['BSP_USING_TOUCH_FT5406']): + src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_touch_ft5406.c') ] + src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_ft5406.c') ] + path += [ os.path.join(cwd, 'touch', 'ft5406') ] + CPPDEFINES = ['CONFIG_TOUCH_FT5406=1'] +if GetDepend(['BSP_USING_USB_DEVICE']): + src += [ os.path.join(cwd, 'usb', 'device', 'hpm_usb_device.c') ] + path += [ os.path.join(cwd, 'usb', 'device') ] +if GetDepend(['BSP_USING_USB_HOST']): + src += [ os.path.join(cwd, 'usb', 'host', 'hpm_usb_host.c') ] + path += [ os.path.join(cwd, 'usb', 'host') ] +if GetDepend(['BSP_USING_ETH1']): + if GetDepend(['BSP_USING_ENET_PHY_RTL8201']): + src += [ os.path.join(cwd, 'enet_phy/rtl8201/hpm_rtl8201.c') ] + path += [ os.path.join(cwd, 'enet_phy') ] + path += [ os.path.join(cwd, 'enet_phy/rtl8201') ] + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h b/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h index d3ffad6a14..27198476e6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -26,8 +26,7 @@ * @brief An ADC peripheral base address. * */ -typedef union -{ +typedef union { #ifdef CONFIG_HAS_HPMSDK_ADC12 ADC12_Type *adc12; #endif @@ -85,7 +84,7 @@ typedef struct { /** * @brief ADC DMA configuration struct. * - * */ + */ typedef struct { adc_module module; adc_base adc_base; @@ -102,7 +101,7 @@ typedef struct { /** * @brief ADC configuration struct for period mode. * - * */ + */ typedef struct { adc_module module; adc_base adc_base; @@ -119,7 +118,7 @@ typedef struct { /** * @brief ADC configuration struct for sequence mode. * - * */ + */ typedef struct { adc_module module; adc_base adc_base; @@ -136,9 +135,8 @@ typedef struct { /** * @brief ADC trigger configuration struct for preempt mode. * - * */ -typedef struct -{ + */ +typedef struct { adc_module module; adc_base adc_base; struct { @@ -152,8 +150,7 @@ typedef struct } adc_pmt_config_t; -typedef struct -{ +typedef struct { adc_module module; adc_base adc_base; } adc_type; @@ -224,7 +221,7 @@ static inline hpm_stat_t hpm_adc_init(adc_config_t *config) return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -250,7 +247,7 @@ static inline hpm_stat_t hpm_adc_channel_init(adc_channel_config_t *config) return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -277,7 +274,7 @@ static inline hpm_stat_t hpm_adc_set_period_config(adc_prd_config_t *config) return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -303,7 +300,7 @@ static inline hpm_stat_t hpm_adc_set_sequence_config(adc_seq_config_t *config) return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -329,7 +326,7 @@ static inline hpm_stat_t hpm_adc_set_preempt_config(adc_pmt_config_t *config) return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -389,6 +386,44 @@ static inline void hpm_adc_init_seq_dma(adc_dma_config_t *config) } } +/** + * @brief Reset value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus + * until the ADC completes the conversion. + * + * @param[in] config A pointer to configuration struct of "adc_dma_config_t". + */ +static inline void hpm_adc_disable_busywait(adc_dma_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_disable_busywait(config->adc_base.adc12); +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_disable_busywait(config->adc_base.adc16); +#endif + } +} + +/** + * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus + * until the ADC has completed its conversion. + * + * @param[in] config A pointer to configuration struct of "adc_dma_config_t". + */ +static inline void hpm_adc_enable_busywait(adc_dma_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_enable_busywait(config->adc_base.adc12); +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_enable_busywait(config->adc_base.adc16); +#endif + } +} + /** * @brief Get ADC status flags. @@ -403,43 +438,16 @@ static inline uint32_t hpm_adc_get_status_flags(adc_type *ptr) #ifdef CONFIG_HAS_HPMSDK_ADC12 return adc12_get_status_flags(ptr->adc_base.adc12); #else - return 0; + return status_invalid_argument; #endif } else if (ptr->module == adc_module_adc16) { #ifdef CONFIG_HAS_HPMSDK_ADC16 return adc16_get_status_flags(ptr->adc_base.adc16); #else - return 0; + return status_invalid_argument; #endif } else { - return false; - } -} - -/** - * @brief Get the setting value of wait disable. - * - * This status flag is only used when wait_dis is set to disable. - * - * @param[in] ptr An ADC peripheral base address. - * @retval Status It means whether the current setting of wait disable is disable. - */ -static inline bool hpm_adc_get_wait_dis_status(adc_type *ptr) -{ - if (ptr->module == adc_module_adc12) { -#ifdef CONFIG_HAS_HPMSDK_ADC12 - return adc12_get_wait_dis_status(ptr->adc_base.adc12); -#else - return 1; -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef CONFIG_HAS_HPMSDK_ADC16 - return adc16_get_wait_dis_status(ptr->adc_base.adc16); -#else - return 1; -#endif - } else { - return false; + return status_invalid_argument; } } @@ -458,16 +466,16 @@ static inline bool hpm_adc_get_conv_valid_status(adc_type *ptr, uint8_t ch) #ifdef CONFIG_HAS_HPMSDK_ADC12 return adc12_get_conv_valid_status(ptr->adc_base.adc12, ch); #else - return 0; + return status_invalid_argument; #endif } else if (ptr->module == adc_module_adc16) { #ifdef CONFIG_HAS_HPMSDK_ADC16 return adc16_get_conv_valid_status(ptr->adc_base.adc16, ch); #else - return 0; + return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -555,7 +563,7 @@ static inline hpm_stat_t hpm_adc_get_oneshot_result(adc_type *ptr, uint8_t ch, u return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -569,7 +577,7 @@ static inline hpm_stat_t hpm_adc_get_oneshot_result(adc_type *ptr, uint8_t ch, u * @retval status_success Get the result of an ADC12 conversion in periodic mode successfully. * @retval status_invalid_argument Get the result of an ADC12 conversion in periodic mode unsuccessfully because of passing invalid arguments. */ -hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint16_t *result) +static inline hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint16_t *result) { if (ptr->module == adc_module_adc12) { #ifdef CONFIG_HAS_HPMSDK_ADC12 @@ -584,7 +592,7 @@ hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint16_t *result) return status_invalid_argument; #endif } else { - return false; + return status_invalid_argument; } } @@ -594,7 +602,7 @@ hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint16_t *result) * @param[in] ptr An adc peripheral base address. * */ -void hpm_adc_trigger_seq_by_sw(adc_type *ptr) +static inline hpm_stat_t hpm_adc_trigger_seq_by_sw(adc_type *ptr) { if (ptr->module == adc_module_adc12) { #ifdef CONFIG_HAS_HPMSDK_ADC12 @@ -604,10 +612,11 @@ void hpm_adc_trigger_seq_by_sw(adc_type *ptr) #ifdef CONFIG_HAS_HPMSDK_ADC16 return adc16_trigger_seq_by_sw(ptr->adc_base.adc16); #endif + } else { + return status_invalid_argument; } } - #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h index 89d30fef3e..e55587bf4d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,14 +8,21 @@ #ifndef HPM_CAMERA_H #define HPM_CAMERA_H -#if CONFIG_CAMERA_OV7725 +#if defined(CONFIG_CAMERA_OV7725) && CONFIG_CAMERA_OV7725 #include "hpm_ov7725.h" #define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV7725_ACTIVE_IMAGE_WIDTH #define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV7725_ACTIVE_IMAGE_HEIGHT -#elif CONFIG_CAMERA_OV5640 +#define CAMERA_DEVICE_ADDR OV7725_I2C_ADDR +#elif defined(CONFIG_CAMERA_OV5640) && CONFIG_CAMERA_OV5640 #include "hpm_ov5640.h" #define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV5640_ACTIVE_IMAGE_WIDTH #define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV5640_ACTIVE_IMAGE_HEIGHT +#define CAMERA_DEVICE_ADDR OV5640_I2C_ADDR +#elif defined(CONFIG_CAMERA_MT9M114) && CONFIG_CAMERA_MT9M114 +#include "hpm_mt9m114.h" +#define CAMERA_MAX_IMAGE_OUTPUT_WIDTH MT9M114_ACTIVE_IMAGE_WIDTH +#define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT MT9M114_ACTIVE_IMAGE_HEIGHT +#define CAMERA_DEVICE_ADDR MT9M114_I2C_ADDR #else #error "unknown camera type, either have CONFIG_CAMERA_OV7725 or CONFIG_CAMERA_OV5640 defined" #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h index bfb8502c8f..c40b4fe37f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,31 +15,34 @@ /* Macro to define video resolution. */ #define HPM_CAMERA_RESOLUTION(width, height) ((uint32_t)(width) | ((uint32_t)(height) << 16U)) -typedef struct -{ +typedef struct { I2C_Type *ptr; void (*delay_ms)(uint32_t ms); void (*write_rst)(uint8_t state); void (*write_pwdn)(uint8_t state); + uint16_t i2c_device_addr; } camera_context_t; -typedef enum -{ +typedef struct { + bool hsync_active_low; + bool vsync_active_low; +} camera_param_dvp_t; + +typedef enum { camera_interface_dvp, camera_interface_mipi, } camera_interface_t; -typedef struct -{ +typedef struct { uint32_t width; uint32_t height; display_pixel_format_t pixel_format; camera_interface_t interface; + void *interface_param; } camera_config_t; /* Video Resolution definition. */ -typedef enum -{ +typedef enum { video_resolution_5mp = HPM_CAMERA_RESOLUTION(2592, 1944), /* 5MP, 2592 * 1944 */ video_resolution_sxga = HPM_CAMERA_RESOLUTION(1280, 800), /* SXGA, 1280 * 800 */ video_resolution_1080p = HPM_CAMERA_RESOLUTION(1920, 1080), /* 1080P, 1920 * 1280*/ @@ -51,8 +54,7 @@ typedef enum } camera_resolution_t; /* Camera light mode type. */ -typedef enum -{ +typedef enum { camera_light_mode_auto = 0, camera_light_mode_sunny, camera_light_mode_cloudy, @@ -62,8 +64,7 @@ typedef enum } camera_light_mode_t; /* Camera special effect type. */ -typedef enum -{ +typedef enum { camera_special_effect_normal = 0, /* Normal. */ camera_special_effect_bw, /* B & W */ camera_special_effect_sepia, /* Sepia. */ @@ -83,7 +84,7 @@ extern "C" { * camera device initialization */ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config); - +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config); #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c new file mode 100644 index 0000000000..b6c12e37bb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mt9m114.h" + +static camera_param_dvp_t camera_dvp_param = { + .hsync_active_low = true, + .vsync_active_low = true, +}; + +hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) +{ + assert(camera_context->delay_ms != NULL); + + hpm_stat_t stat = status_success; + + /* first check chipid */ + stat = mt9m114_check_chip_id(camera_context); + if (stat != status_success) { + return stat; + } + + /* software reset */ + stat = mt9m114_software_reset(camera_context); + if (stat != status_success) { + return stat; + } + camera_context->delay_ms(20); + + stat = mt9m114_init(camera_context, camera_config); + + return stat; +} + +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) +{ + camera_config->interface_param = (void *)&camera_dvp_param; + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c new file mode 100644 index 0000000000..9571a8f639 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mt9m114.h" +#include "board.h" +#include "hpm_clock_drv.h" +#include + +#if defined(MT9M114_SHOW_DEBUG_INFO) && MT9M114_SHOW_DEBUG_INFO +#define DEBUG_INFO(...) printf(__VA_ARGS__) +#else +#define DEBUG_INFO(...) +#endif + +#if MT9M114_ERROR_ACTION_BLOCK +#define ERROR_ACTION() do { \ + DEBUG_INFO("[ERROR]:%s %d\n", __func__, __LINE__); \ + for (;;) { \ + } \ + } while (0) +#else +#define ERROR_ACTION() return (status_fail) +#endif + +const mt9m114_reg_t mt9m114_vga[] = { + {MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_START, 2, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_START, 2, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_END, 2, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 973 */ + {MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_END, 2, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1293 */ + {MT9M114_VAR_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 0x01E3}, /* cam_sensor_cfg_cpipe_last_row = 483 */ + {MT9M114_VAR_CAM_CROP_WINDOW_WIDTH, 2, 0x0280}, /* cam_crop_window_width = 640 */ + {MT9M114_VAR_CAM_CROP_WINDOW_HEIGHT, 2, 0x01E0}, /* cam_crop_window_height = 480 */ + {MT9M114_VAR_CAM_OUTPUT_WIDTH, 2, 0x0280}, /* cam_output_width = 640 */ + {MT9M114_VAR_CAM_OUTPUT_HEIGHT, 2, 0x01E0}, /* cam_output_height = 480 */ + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 0x027F}, /* cam_stat_awb_clip_window_xend = 639 */ + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 0x01DF}, /* cam_stat_awb_clip_window_yend = 479 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 0x007F}, /* cam_stat_ae_initial_window_xend = 127 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 0x005F}, /* cam_stat_ae_initial_window_yend = 95 */ +}; + +const mt9m114_reg_t mt9m114_init_config[] = { + {MT9M114_REG_LOGICAL_ADDRESS_ACCESS, 2u, 0x1000}, + /* PLL Fout = (Fin * 2 * m) / ((n + 1) * (p + 1)) */ + {MT9M114_VAR_CAM_SYSCTL_PLL_ENABLE, 1u, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_M_N, 2u, 0x0120}, /* cam_sysctl_pll_divider_m_n = 288 */ + {MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_P, 2u, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MT9M114_VAR_CAM_SENSOR_CFG_PIXCLK, 4u, 0x2DC6C00}, /* cam_sensor_cfg_pixclk = 48000000 */ + {0x316A, 2, 0x8270}, /* auto txlo_row for hot pixel and linear full well optimization */ + {0x316C, 2, 0x8270}, /* auto txlo for hot pixel and linear full well optimization */ + {0x3ED0, 2, 0x2305}, /* eclipse setting, ecl range=1, ecl value=2, ivln=3 */ + {0x3ED2, 2, 0x77CF}, /* TX_hi=12 */ + {0x316E, 2, 0x8202}, /* auto ecl , threshold 2x, ecl=0 at high gain, ecl=2 for low gain */ + {0x3180, 2, 0x87FF}, /* enable delta dark */ + {0x30D4, 2, 0x6080}, /* disable column correction due to AE oscillation problem */ + {0xA802, 2, 0x0008}, /* RESERVED_AE_TRACK_02 */ + {0x3E14, 2, 0xFF39}, /* Enabling pixout clamping to VAA during ADC streaming to solve column band issue */ + /* APGA */ + {0xC95E, 2u, 0x0000}, + + {MT9M114_VAR_CAM_SENSOR_CFG_ROW_SPEED, 2u, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2u, 0x01C3}, /* cam_sensor_cfg_fine_integ_time_min = 451 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2u, 0x03BA}, /* cam_sensor_cfg_fine_integ_time_max = 954 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2u, 0x02DE}, /* cam_sensor_cfg_frame_length_lines = 734 */ + {MT9M114_VAR_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2u, 0x04A5}, /* cam_sensor_cfg_line_length_pck = 1189 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FINE_CORRECTION, 2u, 0x00E0}, /* cam_sensor_cfg_fine_correction = 224 */ + {MT9M114_VAR_CAM_SENSOR_CFG_REG_0_DATA, 2u, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MT9M114_VAR_CAM_SENSOR_CONTROL_READ_MODE, 2u, 0x0332}, /* cam_sensor_control_read_mode = 816 */ + {MT9M114_VAR_CAM_CROP_WINDOW_XOFFSET, 2u, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MT9M114_VAR_CAM_CROP_WINDOW_YOFFSET, 2u, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MT9M114_VAR_CAM_CROP_CROPMODE, 1u, 0x03}, /* cam_crop_cropmode = 3 */ + {MT9M114_VAR_CAM_AET_AEMODE, 1u, 0x00}, /* cam_aet_aemode = 0 */ + {MT9M114_VAR_CAM_AET_MAX_FRAME_RATE, 2u, 0x3700}, /* cam_aet_max_frame_rate = 14080 */ + {MT9M114_VAR_CAM_AET_MIN_FRAME_RATE, 2u, 0x3700}, /* cam_aet_min_frame_rate = 14080 */ + + /* Camera control module */ + {0xC892, 2u, 0x0267}, + {0xC894, 2u, 0xFF1A}, + {0xC896, 2u, 0xFFB3}, + {0xC898, 2u, 0xFF80}, + {0xC89A, 2u, 0x0166}, + {0xC89C, 2u, 0x0003}, + {0xC89E, 2u, 0xFF9A}, + {0xC8A0, 2u, 0xFEB4}, + {0xC8A2, 2u, 0x024D}, + {0xC8A4, 2u, 0x01BF}, + {0xC8A6, 2u, 0xFF01}, + {0xC8A8, 2u, 0xFFF3}, + {0xC8AA, 2u, 0xFF75}, + {0xC8AC, 2u, 0x0198}, + {0xC8AE, 2u, 0xFFFD}, + {0xC8B0, 2u, 0xFF9A}, + {0xC8B2, 2u, 0xFEE7}, + {0xC8B4, 2u, 0x02A8}, + {0xC8B6, 2u, 0x01D9}, + {0xC8B8, 2u, 0xFF26}, + {0xC8BA, 2u, 0xFFF3}, + {0xC8BC, 2u, 0xFFB3}, + {0xC8BE, 2u, 0x0132}, + {0xC8C0, 2u, 0xFFE8}, + {0xC8C2, 2u, 0xFFDA}, + {0xC8C4, 2u, 0xFECD}, + {0xC8C6, 2u, 0x02C2}, + {0xC8C8, 2u, 0x0075}, + {0xC8CA, 2u, 0x011C}, + {0xC8CC, 2u, 0x009A}, + {0xC8CE, 2u, 0x0105}, + {0xC8D0, 2u, 0x00A4}, + {0xC8D2, 2u, 0x00AC}, + {0xC8D4, 2u, 0x0A8C}, + {0xC8D6, 2u, 0x0F0A}, + {0xC8D8, 2u, 0x1964}, + + /* Automatic White balance */ + {MT9M114_VAR_CAM_AWB_AWB_XSHIFT_PRE_ADJ, 2u, 0x0033}, + {MT9M114_VAR_CAM_AWB_AWB_YSHIFT_PRE_ADJ, 2u, 0x003C}, + {MT9M114_VAR_CAM_AWB_AWB_XSCALE, 1u, 0x03}, + {MT9M114_VAR_CAM_AWB_AWB_YSCALE, 1u, 0x02}, + {0xC8F4, 2u, 0x0000}, + {0xC8F6, 2u, 0x0000}, + {0xC8F8, 2u, 0x0000}, + {0xC8FA, 2u, 0xE724}, + {0xC8FC, 2u, 0x1583}, + {0xC8FE, 2u, 0x2045}, + {0xC900, 2u, 0x03FF}, + {0xC902, 2u, 0x007C}, + {0xC90C, 1u, 0x80}, + {0xC90D, 1u, 0x80}, + {0xC90E, 1u, 0x80}, + {0xC90F, 1u, 0x88}, + {0xC910, 1u, 0x80}, + {0xC911, 1u, 0x80}, + + /* CPIPE Preference */ + {0xC926, 2u, 0x0020}, + {0xC928, 2u, 0x009A}, + {0xC946, 2u, 0x0070}, + {0xC948, 2u, 0x00F3}, + {0xC944, 1u, 0x20}, + {0xC945, 1u, 0x9A}, + {0xC92A, 1u, 0x80}, + {0xC92B, 1u, 0x4B}, + {0xC92C, 1u, 0x00}, + {0xC92D, 1u, 0xFF}, + {0xC92E, 1u, 0x3C}, + {0xC92F, 1u, 0x02}, + {0xC930, 1u, 0x06}, + {0xC931, 1u, 0x64}, + {0xC932, 1u, 0x01}, + {0xC933, 1u, 0x0C}, + {0xC934, 1u, 0x3C}, + {0xC935, 1u, 0x3C}, + {0xC936, 1u, 0x3C}, + {0xC937, 1u, 0x0F}, + {0xC938, 1u, 0x64}, + {0xC939, 1u, 0x64}, + {0xC93A, 1u, 0x64}, + {0xC93B, 1u, 0x32}, + {0xC93C, 2u, 0x0020}, + {0xC93E, 2u, 0x009A}, + {0xC940, 2u, 0x00DC}, + {0xC942, 1u, 0x38}, + {0xC943, 1u, 0x30}, + {0xC944, 1u, 0x50}, + {0xC945, 1u, 0x19}, + {0xC94A, 2u, 0x0230}, + {0xC94C, 2u, 0x0010}, + {0xC94E, 2u, 0x01CD}, + {0xC950, 1u, 0x05}, + {0xC951, 1u, 0x40}, + {0xC87B, 1u, 0x1B}, + {0xC890, 2u, 0x0080}, + {0xC886, 2u, 0x0100}, + {0xC87C, 2u, 0x005A}, + {0xB42A, 1u, 0x05}, + {0xA80A, 1u, 0x20}, + + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2u, 0x0000}, /* cam_stat_awb_clip_window_xstart = 0 */ + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2u, 0x0000}, /* cam_stat_awb_clip_window_ystart = 0 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2u, 0x0000}, /* cam_stat_ae_initial_window_xstart = 0 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2u, 0x0000}, /* cam_stat_ae_initial_window_ystart = 0 */ + {MT9M114_REG_PAD_SLEW, 2u, 0x0777}, /* Pad slew rate */ + {MT9M114_VAR_CAM_OUTPUT_FORMAT_YUV, 2u, 0x0038}, /* Must set cam_output_format_yuv_clip for CSI */ +}; + +hpm_stat_t mt9m114_read_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, void *value) +{ + hpm_stat_t status; + uint16_t subaddr = ((reg & 0xff) << 8) | ((reg & 0xff00) >> 8); + uint8_t data[4]; + uint8_t i = 0; + + status = i2c_master_address_read(context->ptr, context->i2c_device_addr, \ + (uint8_t *)&subaddr, MT9M114_REG_ADDR_LEN, \ + data, reg_size); + if (status_success == status) { + while (reg_size--) { + ((uint8_t *)value)[i++] = data[reg_size]; + } + } + return status; +} + +hpm_stat_t mt9m114_write_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t value) +{ + uint16_t subaddr = ((reg & 0xff) << 8) | ((reg & 0xff00) >> 8); + uint8_t data[4]; + uint8_t i; + + i = reg_size; + while (i--) { + data[i] = (uint8_t)value; + value >>= 8; + } + return i2c_master_address_write(context->ptr, context->i2c_device_addr, \ + (uint8_t *)&subaddr, MT9M114_REG_ADDR_LEN, \ + data, reg_size); +} + +hpm_stat_t mt9m114_modify_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t mask, uint32_t value) +{ + hpm_stat_t status; + uint32_t reg_value; + + status = mt9m114_read_register(context, reg, reg_size, ®_value); + + if (status_success != status) { + return status; + } + + reg_value = (reg_value & ~(mask)) | (value & mask); + + return mt9m114_write_register(context, reg, reg_size, reg_value); +} + +hpm_stat_t mt9m114_multiwrite(camera_context_t *context, const mt9m114_reg_t regs[], uint32_t num) +{ + hpm_stat_t status = status_success; + + for (uint32_t i = 0; i < num; i++) { + status = mt9m114_write_register(context, regs[i].reg, regs[i].size, regs[i].value); + if (status_success != status) { + ERROR_ACTION(); + } + } + + return status; +} + +hpm_stat_t mt9m114_host_command(camera_context_t *context, uint16_t command) +{ + if (mt9m114_write_register(context, MT9M114_REG_COMMAND_REGISTER, 2, (command | MT9M114_COMMAND_OK)) != 0) { + return status_fail; + } + + for (int i = 0; i < MT9M114_HOST_CMD_TIMEOUT; i++, context->delay_ms(1)) { + uint16_t reg_data; + + if (mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2, ®_data) != 0) { + return status_fail; + } + + if ((reg_data & command) == 0) { + return (reg_data & MT9M114_COMMAND_OK) ? 0 : -1; + } + + if (i == (MT9M114_HOST_CMD_TIMEOUT - 1)) { + return status_fail; + } + } + + return status_success; +} + +hpm_stat_t mt9m114_refresh(camera_context_t *context) +{ + hpm_stat_t ret = mt9m114_host_command(context, MT9M114_COMMAND_REFRESH); + + if (ret != status_success) { + return ret; + } + + uint8_t reg_data; + + if (mt9m114_read_register(context, MT9M114_VAR_SEQ_ERROR_CODE, 1, ®_data) != 0) { + return status_fail; + } + + return reg_data == 0 ? status_success : status_fail; +} + +hpm_stat_t mt9m114_get_current_state(camera_context_t *context, uint8_t *state) +{ + return mt9m114_read_register(context, MT9M114_VAR_SYSMGR_CURRENT_STATE, 1u, state); +} + +hpm_stat_t mt9m114_software_reset(camera_context_t *context) +{ + hpm_stat_t status; + uint16_t value; + assert(context->delay_ms != NULL); + + mt9m114_modify_register(context, MT9M114_REG_RESET_AND_MISC_CONTROL, 2, 0x01, 0x01); + context->delay_ms(1); + mt9m114_modify_register(context, MT9M114_REG_RESET_AND_MISC_CONTROL, 2, 0x01, 0x00); + context->delay_ms(50); + + /* forever loop if softreset is not done. Loop until reg 0x80's bit 1 is 0 */ + while (1) { + status = mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2u, &value); + if (status != status_success) { + ERROR_ACTION(); + } + if (!(value & MT9M114_COMMAND_SET_STATE)) { + DEBUG_INFO("[Camera]:sw reset finish\n"); + break; + } + } + return status_success; +} + +hpm_stat_t mt9m114_setstate(camera_context_t *context, uint16_t next_state) +{ + uint16_t value; + hpm_stat_t status = status_success; + + /* Set the desired next state. */ + status = mt9m114_write_register(context, MT9M114_VAR_SYSMGR_NEXT_STATE, 1, next_state); + if (status_success != status) { + ERROR_ACTION(); + } + + /* Check that the FW is ready to accept a new command. */ + context->delay_ms(1); + while (1) { + status = mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2u, &value); + if (status_success != status) { + ERROR_ACTION(); + } + if (!(value & MT9M114_COMMAND_SET_STATE)) { + break; + } + DEBUG_INFO("[Camera]:Set State cmd bit is already set\n"); + } + DEBUG_INFO("[Camera]:Issue the Set State command 0x%x\n", next_state); + + /* Issue the Set State command. */ + return mt9m114_host_command(context, MT9M114_COMMAND_SET_STATE); +} + +hpm_stat_t mt9m114_set_pixformat(camera_context_t *context, display_pixel_format_t pixformat) +{ + uint16_t reg = 0; + + switch (pixformat) { + case display_pixel_format_yuv422: + reg = MT9M114_OUTPUT_FORMAT_YUV | MT9M114_OUTPUT_FORMAT_SWAP_BYTES; + break; + case display_pixel_format_rgb565: + reg = MT9M114_OUTPUT_FORMAT_RGB | MT9M114_OUTPUT_FORMAT_RGB565 | MT9M114_OUTPUT_FORMAT_SWAP_BYTES; + break; + default: + return status_invalid_argument; + } + + if (mt9m114_write_register(context, MT9M114_VAR_CAM_OUTPUT_FORMAT, 2, reg) != 0) { + return status_fail; + } + + return mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); +} + +hpm_stat_t mt9m114_set_framerate(camera_context_t *context, int framerate) +{ + if (mt9m114_write_register(context, MT9M114_VAR_CAM_AET_MAX_FRAME_RATE, 2, framerate * 256) != 0) { + return status_fail; + } + + if (mt9m114_write_register(context, MT9M114_VAR_CAM_AET_MIN_FRAME_RATE, 2, framerate * 128) != 0) { + return status_fail; + } + + return mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); +} + +hpm_stat_t mt9m114_set_brightness(camera_context_t *context, int level) /* -16 to +16 */ +{ + int new_level = level * 2; + + if ((new_level < -32) || (32 < new_level)) { + return status_fail; + } + + if (mt9m114_write_register(context, MT9M114_VAR_UVC_BRIGHTNESS_CONTROL, 2, new_level + 55) != 0) { + return status_fail; + } + + return mt9m114_refresh(context); +} + +hpm_stat_t mt9m114_start(camera_context_t *handle) +{ + return mt9m114_setstate(handle, MT9M114_SYS_STATE_START_STREAMING); +} + +hpm_stat_t mt9m114_stop(camera_context_t *handle) +{ + return mt9m114_setstate(handle, MT9M114_SYS_STATE_ENTER_SUSPEND); +} + +hpm_stat_t mt9m114_check_chip_id(camera_context_t *handle) +{ + hpm_stat_t status = status_success; + uint16_t chip_id; + + status = mt9m114_read_register(handle, MT9M114_REG_CHIP_ID, 2u, &chip_id); + if (status_success != status) { + DEBUG_INFO("[ERROR] read MT9M114 chipid register failed %d\n", status); + return status_fail; + } + if (MT9M114_CHIP_ID != chip_id) { + DEBUG_INFO("[ERROR] chipid is %04x(expect %04x)\n", chip_id, MT9M114_CHIP_ID); + return status_fail; + } + return status_success; +} + +hpm_stat_t mt9m114_enable_mono(camera_context_t *handle, bool enable) +{ + uint16_t value = 0; + mt9m114_read_register(handle, 0x332E, 2u, &value); + if (enable) + value = value | 0x0004; + else + value = value & 0xFFFB; + mt9m114_write_register(handle, 0x332E, 2u, value); + return 0; +} + +hpm_stat_t mt9m114_init(camera_context_t *context, camera_config_t *camera_config) +{ + hpm_stat_t status = status_success; + + /* set init configs */ + DEBUG_INFO("[Camera]:set frame per sec ...\n"); + mt9m114_multiwrite(context, mt9m114_init_config, ARRAY_SIZE(mt9m114_init_config)); + + /* Pixel format. */ + DEBUG_INFO("[Camera]:set format...\n"); + status = mt9m114_set_pixformat(context, camera_config->pixel_format); + if (status_success != status) { + DEBUG_INFO("[ERROR] set output format %d\n", status); + ERROR_ACTION(); + } + + /* set cam port output control... */ + DEBUG_INFO("[Camera]:set cam port output control...\n"); + status = mt9m114_write_register(context, MT9M114_VAR_CAM_PORT_OUTPUT_CONTROL, 2, 0x8008); + if (status_success != status) { + DEBUG_INFO("[ERROR] set cam port output control... %d\n", status); + ERROR_ACTION(); + } + + /* set resolution... */ + DEBUG_INFO("[Camera]:set resolution...\n"); + status = mt9m114_multiwrite(context, mt9m114_vga, ARRAY_SIZE(mt9m114_vga)); + if (status_success != status) { + DEBUG_INFO("[ERROR] set resolution... %d\n", status); + ERROR_ACTION(); + } + + /* set change command */ + DEBUG_INFO("[Camera]:set change command...\n"); + status = mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); + if (status_success != status) { + DEBUG_INFO("[ERROR] set change command... %d\n", status); + ERROR_ACTION(); + } + DEBUG_INFO("MT9M114 init done\n"); + return status; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h new file mode 100644 index 0000000000..a8e2bf7ae8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h @@ -0,0 +1,867 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MT9M114_H +#define HPM_MT9M114_H +#include "hpm_camera_config.h" +#include "hpm_common.h" + +/* MT9M114_ERROR_ACTION_BLOCK + * 0 : return fail + * 1 : print error message to console and block + */ +#define MT9M114_ERROR_ACTION_BLOCK 0 +#define MT9M114_HOST_CMD_TIMEOUT 100 + +#ifndef MT9M114_ACTIVE_IMAGE_WIDTH +#define MT9M114_ACTIVE_IMAGE_WIDTH (640U) +#endif + +#ifndef MT9M114_ACTIVE_IMAGE_HEIGHT +#define MT9M114_ACTIVE_IMAGE_HEIGHT (480U) +#endif + +#define DUMMY_LINES 8 +#define DUMMY_COLUMNS 8 + +#define SENSOR_WIDTH 1296 +#define SENSOR_HEIGHT 976 + +#define DUMMY_WIDTH_BUFFER 8 +#define DUMMY_HEIGHT_BUFFER 8 + +#define ACTIVE_SENSOR_WIDTH (SENSOR_WIDTH - (2 * DUMMY_COLUMNS)) +#define ACTIVE_SENSOR_HEIGHT (SENSOR_HEIGHT - (2 * DUMMY_LINES)) + +/** + * @brief MT9M114 sensor driver APIs + * @defgroup MT9M114_interface sensor driver APIs + * @ingroup component_interfaces + * @{ + * + + */ +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ + +/** + * @brief MT9M114 definition + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(MT9M114_DUAL_CAMERA) +#define MT9M114_I2C_ADDR 0x48 +#define MT9M114_I2C_ADDR_IR 0x5D +#else +#define MT9M114_I2C_ADDR 0x48 +#endif +#define MT9M114_CHIP_ID 0x2481 + +#define MT9M114_REG_ADDR_LEN (2) + +/*! @brief MT9M114 register definitions.*/ + +/* 1.Core registers */ +#define MT9M114_REG_Y_ADDR_START 0x3002 +#define MT9M114_REG_X_ADDR_START 0x3004 +#define MT9M114_REG_Y_ADDR_END 0x3006 +#define MT9M114_REG_X_ADDR_END 0x3008 +#define MT9M114_REG_FRAME_LENGTH_LINES 0x300A +#define MT9M114_REG_LINE_LENGTH_PCK_ 0x300C +#define MT9M114_REG_COARSE_INTEGRATION_TIME 0x3012 +#define MT9M114_REG_FINE_INTEGRATION_TIME 0x3014 +#define MT9M114_REG_RESET_REGISTER 0x301A +#define MT9M114_REG_FLASH 0x3046 +#define MT9M114_REG_FLASH_COUNT 0x3048 +#define MT9M114_REG_GREEN1_GAIN 0x3056 +#define MT9M114_REG_BLUE_GAIN 0x3058 +#define MT9M114_REG_RED_GAIN 0x305A +#define MT9M114_REG_GREEN2_GAIN 0x305C +#define MT9M114_REG_GLOBAL_GAIN 0x305E +#define MT9M114_REG_FUSE_ID1 0x31F4 +#define MT9M114_REG_FUSE_ID2 0x31F6 +#define MT9M114_REG_FUSE_ID3 0x31F8 +#define MT9M114_REG_FUSE_ID4 0x31FA +#define MT9M114_REG_CHAIN_CONTROL 0x31FC +#define MT9M114_REG_CUSTOMER_REV 0x31FE + +/* 2.SOC1 registers */ +#define MT9M114_REG_COLOR_PIPELINE_CONTROL 0x3210 + +/* 3.SOC2 registers */ +#define MT9M114_REG_P_G1_P0Q0 0x3640 +#define MT9M114_REG_P_G1_P0Q1 0x3642 +#define MT9M114_REG_P_G1_P0Q2 0x3644 +#define MT9M114_REG_P_G1_P0Q3 0x3646 +#define MT9M114_REG_P_G1_P0Q4 0x3648 +#define MT9M114_REG_P_R_P0Q0 0x364A +#define MT9M114_REG_P_R_P0Q1 0x364C +#define MT9M114_REG_P_R_P0Q2 0x364E +#define MT9M114_REG_P_R_P0Q3 0x3650 +#define MT9M114_REG_P_R_P0Q4 0x3652 +#define MT9M114_REG_P_B_P0Q0 0x3654 +#define MT9M114_REG_P_B_P0Q1 0x3656 +#define MT9M114_REG_P_B_P0Q2 0x3658 +#define MT9M114_REG_P_B_P0Q3 0x365A +#define MT9M114_REG_P_B_P0Q4 0x365C +#define MT9M114_REG_P_G2_P0Q0 0x365E +#define MT9M114_REG_P_G2_P0Q1 0x3660 +#define MT9M114_REG_P_G2_P0Q2 0x3662 +#define MT9M114_REG_P_G2_P0Q3 0x3664 +#define MT9M114_REG_P_G2_P0Q4 0x3666 +#define MT9M114_REG_P_G1_P1Q0 0x3680 +#define MT9M114_REG_P_G1_P1Q1 0x3682 +#define MT9M114_REG_P_G1_P1Q2 0x3684 +#define MT9M114_REG_P_G1_P1Q3 0x3686 +#define MT9M114_REG_P_G1_P1Q4 0x3688 +#define MT9M114_REG_P_R_P1Q0 0x368A +#define MT9M114_REG_P_R_P1Q1 0x368C +#define MT9M114_REG_P_R_P1Q2 0x368E +#define MT9M114_REG_P_R_P1Q3 0x3690 +#define MT9M114_REG_P_R_P1Q4 0x3692 +#define MT9M114_REG_P_B_P1Q0 0x3694 +#define MT9M114_REG_P_B_P1Q1 0x3696 +#define MT9M114_REG_P_B_P1Q2 0x3698 +#define MT9M114_REG_P_B_P1Q3 0x369A +#define MT9M114_REG_P_B_P1Q4 0x369C +#define MT9M114_REG_P_G2_P1Q0 0x369E +#define MT9M114_REG_P_G2_P1Q1 0x36A0 +#define MT9M114_REG_P_G2_P1Q2 0x36A2 +#define MT9M114_REG_P_G2_P1Q3 0x36A4 +#define MT9M114_REG_P_G2_P1Q4 0x36A6 +#define MT9M114_REG_P_G1_P2Q0 0x36C0 +#define MT9M114_REG_P_G1_P2Q1 0x36C2 +#define MT9M114_REG_P_G1_P2Q2 0x36C4 +#define MT9M114_REG_P_G1_P2Q3 0x36C6 +#define MT9M114_REG_P_G1_P2Q4 0x36C8 +#define MT9M114_REG_P_R_P2Q0 0x36CA +#define MT9M114_REG_P_R_P2Q1 0x36CC +#define MT9M114_REG_P_R_P2Q2 0x36CE +#define MT9M114_REG_P_R_P2Q3 0x36D0 +#define MT9M114_REG_P_R_P2Q4 0x36D2 +#define MT9M114_REG_P_B_P2Q0 0x36D4 +#define MT9M114_REG_P_B_P2Q1 0x36D6 +#define MT9M114_REG_P_B_P2Q2 0x36D8 +#define MT9M114_REG_P_B_P2Q3 0x36DA +#define MT9M114_REG_P_B_P2Q4 0x36DC +#define MT9M114_REG_P_G2_P2Q0 0x36DE +#define MT9M114_REG_P_G2_P2Q1 0x36E0 +#define MT9M114_REG_P_G2_P2Q2 0x36E2 +#define MT9M114_REG_P_G2_P2Q3 0x36E4 +#define MT9M114_REG_P_G2_P2Q4 0x36E6 +#define MT9M114_REG_P_G1_P3Q0 0x3700 +#define MT9M114_REG_P_G1_P3Q1 0x3702 +#define MT9M114_REG_P_G1_P3Q2 0x3704 +#define MT9M114_REG_P_G1_P3Q3 0x3706 +#define MT9M114_REG_P_G1_P3Q4 0x3708 +#define MT9M114_REG_P_R_P3Q0 0x370A +#define MT9M114_REG_P_R_P3Q1 0x370C +#define MT9M114_REG_P_R_P3Q2 0x370E +#define MT9M114_REG_P_R_P3Q3 0x3710 +#define MT9M114_REG_P_R_P3Q4 0x3712 +#define MT9M114_REG_P_B_P3Q0 0x3714 +#define MT9M114_REG_P_B_P3Q1 0x3716 +#define MT9M114_REG_P_B_P3Q2 0x3718 +#define MT9M114_REG_P_B_P3Q3 0x371A +#define MT9M114_REG_P_B_P3Q4 0x371C +#define MT9M114_REG_P_G2_P3Q0 0x371E +#define MT9M114_REG_P_G2_P3Q1 0x3720 +#define MT9M114_REG_P_G2_P3Q2 0x3722 +#define MT9M114_REG_P_G2_P3Q3 0x3724 +#define MT9M114_REG_P_G2_P3Q4 0x3726 +#define MT9M114_REG_P_G1_P4Q0 0x3740 +#define MT9M114_REG_P_G1_P4Q1 0x3742 +#define MT9M114_REG_P_G1_P4Q2 0x3744 +#define MT9M114_REG_P_G1_P4Q3 0x3746 +#define MT9M114_REG_P_G1_P4Q4 0x3748 +#define MT9M114_REG_P_R_P4Q0 0x374A +#define MT9M114_REG_P_R_P4Q1 0x374C +#define MT9M114_REG_P_R_P4Q2 0x374E +#define MT9M114_REG_P_R_P4Q3 0x3750 +#define MT9M114_REG_P_R_P4Q4 0x3752 +#define MT9M114_REG_P_B_P4Q0 0x3754 +#define MT9M114_REG_P_B_P4Q1 0x3756 +#define MT9M114_REG_P_B_P4Q2 0x3758 +#define MT9M114_REG_P_B_P4Q3 0x375A +#define MT9M114_REG_P_B_P4Q4 0x375C +#define MT9M114_REG_P_G2_P4Q0 0x375E +#define MT9M114_REG_P_G2_P4Q1 0x3760 +#define MT9M114_REG_P_G2_P4Q2 0x3762 +#define MT9M114_REG_P_G2_P4Q3 0x3764 +#define MT9M114_REG_P_G2_P4Q4 0x3766 +#define MT9M114_REG_CENTER_ROW 0x3782 +#define MT9M114_REG_CENTER_COLUMN 0x3784 + +/* 4.SYSCTL registers */ +#define MT9M114_REG_CHIP_ID 0x0000 +#define MT9M114_REG_CLOCKS_CONTROL 0x0016 +#define MT9M114_REG_RESET_AND_MISC_CONTROL 0x001A +#define MT9M114_REG_PAD_SLEW 0x001E +#define MT9M114_REG_USER_DEFINED_DEVICE_ADDRESS_ID 0x002E +#define MT9M114_REG_PAD_CONTROL 0x0032 +#define MT9M114_REG_COMMAND_REGISTER 0x0080 + +/* 5.XDMA registers */ +#define MT9M114_REG_ACCESS_CTL_STAT 0x0982 +#define MT9M114_REG_PHYSICAL_ADDRESS_ACCESS 0x098A +#define MT9M114_REG_LOGICAL_ADDRESS_ACCESS 0x098E +#define MT9M114_REG_MCU_VARIABLE_DATA0 0x0990 +#define MT9M114_REG_MCU_VARIABLE_DATA1 0x0992 +#define MT9M114_REG_MCU_VARIABLE_DATA2 0x0994 +#define MT9M114_REG_MCU_VARIABLE_DATA3 0x0996 +#define MT9M114_REG_MCU_VARIABLE_DATA4 0x0998 +#define MT9M114_REG_MCU_VARIABLE_DATA5 0x099A +#define MT9M114_REG_MCU_VARIABLE_DATA6 0x099C +#define MT9M114_REG_MCU_VARIABLE_DATA7 0x099E + +/*! @brief MT9M114 variables definitions.*/ + +/* 01.Monitor variables */ +#define MT9M114_VAR_MON_MAJOR_VERSION 0x8000 +#define MT9M114_VAR_MON_MINOR_VERSION 0x8002 +#define MT9M114_VAR_MON_RELEASE_VERSION 0x8004 +#define MT9M114_VAR_MON_HEARTBEAT 0x8006 + +/* 02.Sequencer variables */ +#define MT9M114_VAR_SEQ_ERROR_CODE 0x8406 + +/* 03.AE_Rule variables */ +#define MT9M114_VAR_AE_RULE_ALGO 0xA404 +#define MT9M114_VAR_AE_RULE_AVG_Y_FROM_STATS 0xA406 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_0 0xA407 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_1 0xA408 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_2 0xA409 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_3 0xA40A +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_4 0xA40B +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_0 0xA40C +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_1 0xA40D +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_2 0xA40E +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_3 0xA40F +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_4 0xA410 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_0 0xA411 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_1 0xA412 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_2 0xA413 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_3 0xA414 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_4 0xA415 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_0 0xA416 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_1 0xA417 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_2 0xA418 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_3 0xA419 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_4 0xA41A +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_0 0xA41B +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_1 0xA41C +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_2 0xA41D +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_3 0xA41E +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_4 0xA41F +#define MT9M114_VAR_AE_RULE_AE_ADAPTIVE_STRENGTH 0xA420 + +/* 04.AE_Track variables */ +#define MT9M114_VAR_AE_TRACK_STATUS 0xA800 +#define MT9M114_VAR_AE_TRACK_ALGO 0xA804 +#define MT9M114_VAR_AE_TRACK_TARGET_AVERAGE_LUMA 0xA807 +#define MT9M114_VAR_AE_TRACK_GATE_PERCENTAGE 0xA808 +#define MT9M114_VAR_AE_TRACK_CURRENT_AVERAGE_LUMA 0xA809 +#define MT9M114_VAR_AE_TRACK_AE_TRACKING_DAMPENING_SPEED 0xA80A +#define MT9M114_VAR_AE_TRACK_AE_DAMPENING_SPEED 0xA80B +#define MT9M114_VAR_AE_TRACK_SKIP_FRAMES_COUNTER 0xA80D +#define MT9M114_VAR_AE_TRACK_CURRENT_FLICKER_LINES 0xA80E +#define MT9M114_VAR_AE_TRACK_FDZONE 0xA818 +#define MT9M114_VAR_AE_TRACK_ZONE 0xA81B +#define MT9M114_VAR_AE_TRACK_FLICKER_LINES_50HZ 0xA826 +#define MT9M114_VAR_AE_TRACK_VIRT_EXPOSURE_LOG 0xA828 +#define MT9M114_VAR_AE_TRACK_MIN_VIRT_EXPOSURE_LOG_ZONE0 0xA82A +#define MT9M114_VAR_AE_TRACK_MAX_VIRT_EXPOSURE_LOG_ZONE0 0xA82C +#define MT9M114_VAR_AE_TRACK_MAX_VIRT_EXPOSURE_LOG_ZONE1 0xA82E +#define MT9M114_VAR_AE_TRACK_VIRT_GAIN 0xA838 + +/* 05.AWB variables */ +#define MT9M114_VAR_AWB_STATUS 0xAC00 +#define MT9M114_VAR_AWB_MODE 0xAC02 +#define MT9M114_VAR_AWB_R_RATIO_LOWER 0xAC06 +#define MT9M114_VAR_AWB_R_RATIO_UPPER 0xAC07 +#define MT9M114_VAR_AWB_B_RATIO_LOWER 0xAC08 +#define MT9M114_VAR_AWB_B_RATIO_UPPER 0xAC09 +#define MT9M114_VAR_AWB_R_SCENE_RATIO_LOWER 0xAC0A +#define MT9M114_VAR_AWB_R_SCENE_RATIO_UPPER 0xAC0B +#define MT9M114_VAR_AWB_B_SCENE_RATIO_LOWER 0xAC0C +#define MT9M114_VAR_AWB_B_SCENE_RATIO_UPPER 0xAC0D +#define MT9M114_VAR_AWB_R_RATIO_PRE_AWB 0xAC0E +#define MT9M114_VAR_AWB_B_RATIO_PRE_AWB 0xAC0F +#define MT9M114_VAR_AWB_R_GAIN 0xAC12 +#define MT9M114_VAR_AWB_B_GAIN 0xAC14 +#define MT9M114_VAR_AWB_PRE_AWB_RATIOS_TRACKING_SPEED 0xAC16 +#define MT9M114_VAR_AWB_PIXEL_THRESHOLD_COUNT 0xAC18 + +/* 06.BlackLevel variables */ +#define MT9M114_VAR_BLACKLEVEL_ALGO 0xB004 +#define MT9M114_VAR_BLACKLEVEL_MAX_BLACK_LEVEL 0xB00C +#define MT9M114_VAR_BLACKLEVEL_BLACK_LEVEL_DAMPENING 0xB00D + +/* 07.CCM variables */ +#define MT9M114_VAR_CCM_ALGO 0xB404 +#define MT9M114_VAR_CCM_0 0xB406 +#define MT9M114_VAR_CCM_1 0xB408 +#define MT9M114_VAR_CCM_2 0xB40A +#define MT9M114_VAR_CCM_3 0xB40C +#define MT9M114_VAR_CCM_4 0xB40E +#define MT9M114_VAR_CCM_5 0xB410 +#define MT9M114_VAR_CCM_6 0xB412 +#define MT9M114_VAR_CCM_7 0xB414 +#define MT9M114_VAR_CCM_8 0xB416 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_0 0xB418 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_1 0xB41A +#define MT9M114_VAR_CCM_LL_DELTA_CCM_2 0xB41C +#define MT9M114_VAR_CCM_LL_DELTA_CCM_3 0xB41E +#define MT9M114_VAR_CCM_LL_DELTA_CCM_4 0xB420 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_5 0xB422 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_6 0xB424 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_7 0xB426 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_8 0xB428 +#define MT9M114_VAR_CCM_DELTA_GAIN 0xB42A +#define MT9M114_VAR_CCM_DELTA_THRESH 0xB42B + +/* 08.LowLight variables */ +#define MT9M114_VAR_LL_MODE 0xBC02 +#define MT9M114_VAR_LL_ALGO 0xBC04 +#define MT9M114_VAR_LL_GAMMA_SELECT 0xBC07 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_0 0xBC0A +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_1 0xBC0B +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_2 0xBC0C +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_3 0xBC0D +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_4 0xBC0E +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_5 0xBC0F +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_6 0xBC10 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_7 0xBC11 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_8 0xBC12 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_9 0xBC13 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_10 0xBC14 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_11 0xBC15 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_12 0xBC16 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_13 0xBC17 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_14 0xBC18 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_15 0xBC19 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_16 0xBC1A +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_17 0xBC1B +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_18 0xBC1C +#define MT9M114_VAR_LL_GAMMA_NRCURVE_0 0xBC1D +#define MT9M114_VAR_LL_GAMMA_NRCURVE_1 0xBC1E +#define MT9M114_VAR_LL_GAMMA_NRCURVE_2 0xBC1F +#define MT9M114_VAR_LL_GAMMA_NRCURVE_3 0xBC20 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_4 0xBC21 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_5 0xBC22 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_6 0xBC23 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_7 0xBC24 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_8 0xBC25 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_9 0xBC26 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_10 0xBC27 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_11 0xBC28 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_12 0xBC29 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_13 0xBC2A +#define MT9M114_VAR_LL_GAMMA_NRCURVE_14 0xBC2B +#define MT9M114_VAR_LL_GAMMA_NRCURVE_15 0xBC2C +#define MT9M114_VAR_LL_GAMMA_NRCURVE_16 0xBC2D +#define MT9M114_VAR_LL_GAMMA_NRCURVE_17 0xBC2E +#define MT9M114_VAR_LL_GAMMA_NRCURVE_18 0xBC2F +#define MT9M114_VAR_LL_BM_PRECISION_BITS 0xBC31 +#define MT9M114_VAR_LL_AVERAGE_LUMA_FADE_TO_BLACK 0xBC3A +#define MT9M114_VAR_LL_FADE_TO_BLACK_DAMPENING_SPEED 0xBC3C + +/* 09.CameraControl variables */ +#define MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_START 0xC800 +#define MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_START 0xC802 +#define MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_END 0xC804 +#define MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_END 0xC806 +#define MT9M114_VAR_CAM_SENSOR_CFG_PIXCLK 0xC808 +#define MT9M114_VAR_CAM_SENSOR_CFG_ROW_SPEED 0xC80C +#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN 0xC80E +#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX 0xC810 +#define MT9M114_VAR_CAM_SENSOR_CFG_FRAME_LENGTH_LINES 0xC812 +#define MT9M114_VAR_CAM_SENSOR_CFG_LINE_LENGTH_PCK 0xC814 +#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_CORRECTION 0xC816 +#define MT9M114_VAR_CAM_SENSOR_CFG_CPIPE_LAST_ROW 0xC818 +#define MT9M114_VAR_CAM_SENSOR_CFG_REG_0_DATA 0xC826 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_READ_MODE 0xC834 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_ANALOG_GAIN 0xC836 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_VIRT_COLUMN_GAIN 0xC838 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_FRAME_LENGTH_LINES 0xC83A +#define MT9M114_VAR_CAM_SENSOR_CONTROL_COARSE_INTEGRATION_TIME 0xC83C +#define MT9M114_VAR_CAM_SENSOR_CONTROL_FINE_INTEGRATION_TIME 0xC83E +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_RED 0xC840 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_GREEN1 0xC842 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_GREEN2 0xC844 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_BLUE 0xC846 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_SECOND 0xC848 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_SECOND_BLACK_LEVEL 0xC84B +#define MT9M114_VAR_CAM_MODE_SELECT 0xC84C +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_SELECT 0xC84D +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_RED 0xC84E +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_GREEN 0xC850 +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_BLUE 0xC852 +#define MT9M114_VAR_CAM_CROP_WINDOW_XOFFSET 0xC854 +#define MT9M114_VAR_CAM_CROP_WINDOW_YOFFSET 0xC856 +#define MT9M114_VAR_CAM_CROP_WINDOW_WIDTH 0xC858 +#define MT9M114_VAR_CAM_CROP_WINDOW_HEIGHT 0xC85A +#define MT9M114_VAR_CAM_CROP_CROPMODE 0xC85C +#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_MODE 0xC85E +#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_PERCENTAGE 0xC860 +#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_STRETCH_FACTOR 0xC862 +#define MT9M114_VAR_CAM_OUTPUT_WIDTH 0xC868 +#define MT9M114_VAR_CAM_OUTPUT_HEIGHT 0xC86A +#define MT9M114_VAR_CAM_OUTPUT_FORMAT 0xC86C +#define MT9M114_VAR_CAM_OUTPUT_FORMAT_YUV 0xC86E +#define MT9M114_VAR_CAM_OUTPUT_Y_OFFSET 0xC870 +#define MT9M114_VAR_CAM_HUE_ANGLE 0xC873 +#define MT9M114_VAR_CAM_SFX_CONTROL 0xC874 +#define MT9M114_VAR_CAM_SFX_SOLARIZATION_THRESH 0xC875 +#define MT9M114_VAR_CAM_SFX_SEPIA_CR 0xC876 +#define MT9M114_VAR_CAM_SFX_SEPIA_CB 0xC877 +#define MT9M114_VAR_CAM_AET_AEMODE 0xC878 +#define MT9M114_VAR_CAM_AET_SKIP_FRAMES 0xC879 +#define MT9M114_VAR_CAM_AET_TARGET_AVERAGE_LUMA 0xC87A +#define MT9M114_VAR_CAM_AET_TARGET_AVERAGE_LUMA_DARK 0xC87B +#define MT9M114_VAR_CAM_AET_BLACK_CLIPPING_TARGET 0xC87C +#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_INT_TIME_PCLK 0xC87E +#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_DGAIN 0xC880 +#define MT9M114_VAR_CAM_AET_AE_MAX_VIRT_DGAIN 0xC882 +#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_AGAIN 0xC884 +#define MT9M114_VAR_CAM_AET_AE_MAX_VIRT_AGAIN 0xC886 +#define MT9M114_VAR_CAM_AET_AE_VIRT_GAIN_TH_EG 0xC888 +#define MT9M114_VAR_CAM_AET_AE_EG_GATE_PERCENTAGE 0xC88A +#define MT9M114_VAR_CAM_AET_FLICKER_FREQ_HZ 0xC88B +#define MT9M114_VAR_CAM_AET_MAX_FRAME_RATE 0xC88C +#define MT9M114_VAR_CAM_AET_MIN_FRAME_RATE 0xC88E +#define MT9M114_VAR_CAM_AET_TARGET_GAIN 0xC890 +#define MT9M114_VAR_CAM_AWB_CCM_L_0 0xC892 +#define MT9M114_VAR_CAM_AWB_CCM_L_1 0xC894 +#define MT9M114_VAR_CAM_AWB_CCM_L_2 0xC896 +#define MT9M114_VAR_CAM_AWB_CCM_L_3 0xC898 +#define MT9M114_VAR_CAM_AWB_CCM_L_4 0xC89A +#define MT9M114_VAR_CAM_AWB_CCM_L_5 0xC89C +#define MT9M114_VAR_CAM_AWB_CCM_L_6 0xC89E +#define MT9M114_VAR_CAM_AWB_CCM_L_7 0xC8A0 +#define MT9M114_VAR_CAM_AWB_CCM_L_8 0xC8A2 +#define MT9M114_VAR_CAM_AWB_CCM_M_0 0xC8A4 +#define MT9M114_VAR_CAM_AWB_CCM_M_1 0xC8A6 +#define MT9M114_VAR_CAM_AWB_CCM_M_2 0xC8A8 +#define MT9M114_VAR_CAM_AWB_CCM_M_3 0xC8AA +#define MT9M114_VAR_CAM_AWB_CCM_M_4 0xC8AC +#define MT9M114_VAR_CAM_AWB_CCM_M_5 0xC8AE +#define MT9M114_VAR_CAM_AWB_CCM_M_6 0xC8B0 +#define MT9M114_VAR_CAM_AWB_CCM_M_7 0xC8B2 +#define MT9M114_VAR_CAM_AWB_CCM_M_8 0xC8B4 +#define MT9M114_VAR_CAM_AWB_CCM_R_0 0xC8B6 +#define MT9M114_VAR_CAM_AWB_CCM_R_1 0xC8B8 +#define MT9M114_VAR_CAM_AWB_CCM_R_2 0xC8BA +#define MT9M114_VAR_CAM_AWB_CCM_R_3 0xC8BC +#define MT9M114_VAR_CAM_AWB_CCM_R_4 0xC8BE +#define MT9M114_VAR_CAM_AWB_CCM_R_5 0xC8C0 +#define MT9M114_VAR_CAM_AWB_CCM_R_6 0xC8C2 +#define MT9M114_VAR_CAM_AWB_CCM_R_7 0xC8C4 +#define MT9M114_VAR_CAM_AWB_CCM_R_8 0xC8C6 +#define MT9M114_VAR_CAM_AWB_CCM_L_RG_GAIN 0xC8C8 +#define MT9M114_VAR_CAM_AWB_CCM_L_BG_GAIN 0xC8CA +#define MT9M114_VAR_CAM_AWB_CCM_M_RG_GAIN 0xC8CC +#define MT9M114_VAR_CAM_AWB_CCM_M_BG_GAIN 0xC8CE +#define MT9M114_VAR_CAM_AWB_CCM_R_RG_GAIN 0xC8D0 +#define MT9M114_VAR_CAM_AWB_CCM_R_BG_GAIN 0xC8D2 +#define MT9M114_VAR_CAM_AWB_CCM_L_CTEMP 0xC8D4 +#define MT9M114_VAR_CAM_AWB_CCM_M_CTEMP 0xC8D6 +#define MT9M114_VAR_CAM_AWB_CCM_R_CTEMP 0xC8D8 +#define MT9M114_VAR_CAM_AWB_LL_CCM_0 0xC8DA +#define MT9M114_VAR_CAM_AWB_LL_CCM_1 0xC8DC +#define MT9M114_VAR_CAM_AWB_LL_CCM_2 0xC8DE +#define MT9M114_VAR_CAM_AWB_LL_CCM_3 0xC8E0 +#define MT9M114_VAR_CAM_AWB_LL_CCM_4 0xC8E2 +#define MT9M114_VAR_CAM_AWB_LL_CCM_5 0xC8E4 +#define MT9M114_VAR_CAM_AWB_LL_CCM_6 0xC8E6 +#define MT9M114_VAR_CAM_AWB_LL_CCM_7 0xC8E8 +#define MT9M114_VAR_CAM_AWB_LL_CCM_8 0xC8EA +#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE_MIN 0xC8EC +#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE_MAX 0xC8EE +#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE 0xC8F0 +#define MT9M114_VAR_CAM_AWB_AWB_XSCALE 0xC8F2 +#define MT9M114_VAR_CAM_AWB_AWB_YSCALE 0xC8F3 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_0 0xC8F4 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_1 0xC8F6 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_2 0xC8F8 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_3 0xC8FA +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_4 0xC8FC +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_5 0xC8FE +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_6 0xC900 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_7 0xC902 +#define MT9M114_VAR_CAM_AWB_AWB_XSHIFT_PRE_ADJ 0xC904 +#define MT9M114_VAR_CAM_AWB_AWB_YSHIFT_PRE_ADJ 0xC906 +#define MT9M114_VAR_CAM_AWB_AWBMODE 0xC909 +#define MT9M114_VAR_CAM_AWB_TINTS_CTEMP_THRESHOLD 0xC90A +#define MT9M114_VAR_CAM_AWB_K_R_L 0xC90C +#define MT9M114_VAR_CAM_AWB_K_G_L 0xC90D +#define MT9M114_VAR_CAM_AWB_K_B_L 0xC90E +#define MT9M114_VAR_CAM_AWB_K_R_R 0xC90F +#define MT9M114_VAR_CAM_AWB_K_G_R 0xC910 +#define MT9M114_VAR_CAM_AWB_K_B_R 0xC911 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XSTART 0xC914 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YSTART 0xC916 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XEND 0xC918 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YEND 0xC91A +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XSTART 0xC91C +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YSTART 0xC91E +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XEND 0xC920 +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YEND 0xC922 +#define MT9M114_VAR_CAM_LL_LLMODE 0xC924 +#define MT9M114_VAR_CAM_LL_START_BRIGHTNESS 0xC926 +#define MT9M114_VAR_CAM_LL_STOP_BRIGHTNESS 0xC928 +#define MT9M114_VAR_CAM_LL_START_SATURATION 0xC92A +#define MT9M114_VAR_CAM_LL_END_SATURATION 0xC92B +#define MT9M114_VAR_CAM_LL_START_DESATURATION 0xC92C +#define MT9M114_VAR_CAM_LL_END_DESATURATION 0xC92D +#define MT9M114_VAR_CAM_LL_START_DEMOSAIC 0xC92E +#define MT9M114_VAR_CAM_LL_START_AP_GAIN 0xC92F +#define MT9M114_VAR_CAM_LL_START_AP_THRESH 0xC930 +#define MT9M114_VAR_CAM_LL_STOP_DEMOSAIC 0xC931 +#define MT9M114_VAR_CAM_LL_STOP_AP_GAIN 0xC932 +#define MT9M114_VAR_CAM_LL_STOP_AP_THRESH 0xC933 +#define MT9M114_VAR_CAM_LL_START_NR_RED 0xC934 +#define MT9M114_VAR_CAM_LL_START_NR_GREEN 0xC935 +#define MT9M114_VAR_CAM_LL_START_NR_BLUE 0xC936 +#define MT9M114_VAR_CAM_LL_START_NR_THRESH 0xC937 +#define MT9M114_VAR_CAM_LL_STOP_NR_RED 0xC938 +#define MT9M114_VAR_CAM_LL_STOP_NR_GREEN 0xC939 +#define MT9M114_VAR_CAM_LL_STOP_NR_BLUE 0xC93A +#define MT9M114_VAR_CAM_LL_STOP_NR_THRESH 0xC93B +#define MT9M114_VAR_CAM_LL_START_CONTRAST_BM 0xC93C +#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_BM 0xC93E +#define MT9M114_VAR_CAM_LL_GAMMA 0xC940 +#define MT9M114_VAR_CAM_LL_START_CONTRAST_GRADIENT 0xC942 +#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_GRADIENT 0xC943 +#define MT9M114_VAR_CAM_LL_START_CONTRAST_LUMA_PERCENTAGE 0xC944 +#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_LUMA_PERCENTAGE 0xC945 +#define MT9M114_VAR_CAM_LL_START_GAIN_METRIC 0xC946 +#define MT9M114_VAR_CAM_LL_STOP_GAIN_METRIC 0xC948 +#define MT9M114_VAR_CAM_LL_START_FADE_TO_BLACK_LUMA 0xC94A +#define MT9M114_VAR_CAM_LL_STOP_FADE_TO_BLACK_LUMA 0xC94C +#define MT9M114_VAR_CAM_LL_CLUSTER_DC_TH_BM 0xC94E +#define MT9M114_VAR_CAM_LL_CLUSTER_DC_GATE_PERCENTAGE 0xC950 +#define MT9M114_VAR_CAM_LL_SUMMING_SENSITIVITY_FACTOR 0xC951 +#define MT9M114_VAR_CAM_LL_START_TARGET_LUMA_BM 0xC952 +#define MT9M114_VAR_CAM_LL_STOP_TARGET_LUMA_BM 0xC954 +#define MT9M114_VAR_CAM_LL_INV_BRIGHTNESS_METRIC 0xC956 +#define MT9M114_VAR_CAM_LL_GAIN_METRIC 0xC958 +#define MT9M114_VAR_CAM_SEQ_UV_COLOR_BOOST 0xC95A +#define MT9M114_VAR_CAM_PGA_PGA_CONTROL 0xC95E +#define MT9M114_VAR_CAM_PGA_L_CONFIG_COLOUR_TEMP 0xC960 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_GREEN_RED_Q14 0xC962 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_RED_Q14 0xC964 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_GREEN_BLUE_Q14 0xC966 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_BLUE_Q14 0xC968 +#define MT9M114_VAR_CAM_PGA_M_CONFIG_COLOUR_TEMP 0xC96A +#define MT9M114_VAR_CAM_PGA_M_CONFIG_GREEN_RED_Q14 0xC96C +#define MT9M114_VAR_CAM_PGA_M_CONFIG_RED_Q14 0xC96E +#define MT9M114_VAR_CAM_PGA_M_CONFIG_GREEN_BLUE_Q14 0xC970 +#define MT9M114_VAR_CAM_PGA_M_CONFIG_BLUE_Q14 0xC972 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_COLOUR_TEMP 0xC974 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_GREEN_RED_Q14 0xC976 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_RED_Q14 0xC978 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_GREEN_BLUE_Q14 0xC97A +#define MT9M114_VAR_CAM_PGA_R_CONFIG_BLUE_Q14 0xC97C +#define MT9M114_VAR_CAM_SYSCTL_PLL_ENABLE 0xC97E +#define MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_M_N 0xC980 +#define MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_P 0xC982 +#define MT9M114_VAR_CAM_PORT_OUTPUT_CONTROL 0xC984 +#define MT9M114_VAR_CAM_PORT_PORCH 0xC986 +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_HS_ZERO 0xC988 +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_HS_EXIT_HS_TRAIL 0xC98A +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_CLK_POST_CLK_PRE 0xC98C +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_CLK_ZERO 0xC98E +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_LPX 0xC990 +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_INIT_TIMING 0xC992 + +/* 10.UVC_Control variables */ +#define MT9M114_VAR_UVC_AE_MODE_CONTROL 0xCC00 +#define MT9M114_VAR_UVC_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0xCC01 +#define MT9M114_VAR_UVC_AE_PRIORITY_CONTROL 0xCC02 +#define MT9M114_VAR_UVC_POWER_LINE_FREQUENCY_CONTROL 0xCC03 +#define MT9M114_VAR_UVC_EXPOSURE_TIME_ABSOLUTE_CONTROL 0xCC04 +#define MT9M114_VAR_UVC_BACKLIGHT_COMPENSATION_CONTROL 0xCC08 +#define MT9M114_VAR_UVC_BRIGHTNESS_CONTROL 0xCC0A +#define MT9M114_VAR_UVC_CONTRAST_CONTROL 0xCC0C +#define MT9M114_VAR_UVC_GAIN_CONTROL 0xCC0E +#define MT9M114_VAR_UVC_HUE_CONTROL 0xCC10 +#define MT9M114_VAR_UVC_SATURATION_CONTROL 0xCC12 +#define MT9M114_VAR_UVC_SHARPNESS_CONTROL 0xCC14 +#define MT9M114_VAR_UVC_GAMMA_CONTROL 0xCC16 +#define MT9M114_VAR_UVC_WHITE_BALANCE_TEMPERATURE_CONTROL 0xCC18 +#define MT9M114_VAR_UVC_FRAME_INTERVAL_CONTROL 0xCC1C +#define MT9M114_VAR_UVC_MANUAL_EXPOSURE_CONFIGURATION 0xCC20 +#define MT9M114_VAR_UVC_FLICKER_AVOIDANCE_CONFIGURATION 0xCC21 +#define MT9M114_VAR_UVC_ALGO 0xCC22 +#define MT9M114_VAR_UVC_RESULT_STATUS 0xCC24 + +/* 11.SystemManager variables */ +#define MT9M114_VAR_SYSMGR_NEXT_STATE 0xDC00 +#define MT9M114_VAR_SYSMGR_CURRENT_STATE 0xDC01 +#define MT9M114_VAR_SYSMGR_CMD_STATUS 0xDC02 + +/* 12.PatchLoader variables */ +#define MT9M114_VAR_PATCHLDR_LOADER_ADDRESS 0xE000 +#define MT9M114_VAR_PATCHLDR_PATCH_ID 0xE002 +#define MT9M114_VAR_PATCHLDR_FIRMWARE_ID 0xE004 +#define MT9M114_VAR_PATCHLDR_APPLY_STATUS 0xE008 +#define MT9M114_VAR_PATCHLDR_NUM_PATCHES 0xE009 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_0 0xE00A +#define MT9M114_VAR_PATCHLDR_PATCH_ID_1 0xE00C +#define MT9M114_VAR_PATCHLDR_PATCH_ID_2 0xE00E +#define MT9M114_VAR_PATCHLDR_PATCH_ID_3 0xE010 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_4 0xE012 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_5 0xE014 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_6 0xE016 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_7 0xE018 + +/* 13.Patch variables */ +#define MT9M114_VAR_PATCHVARS_DELTA_DK_CORRECTION_FACTOR 0xE400 +#define MT9M114_VAR_CAM_AUTO_BINNING_MODE (0xE801) + +/* 14.CommandHandler variables */ +#define MT9M114_VAR_CMD_HANDLER_WAIT_EVENT_ID 0xFC00 +#define MT9M114_VAR_CMD_HANDLER_NUM_EVENTS 0xFC02 + +/*! @brief MT9M114 command definitions. */ +#define MT9M114_COMMAND_APPLY_PATCH 0x0001 +#define MT9M114_COMMAND_SET_STATE 0x0002 +#define MT9M114_COMMAND_REFRESH 0x0004 +#define MT9M114_COMMAND_WAIT_FOR_EVENT 0x0008 +#define MT9M114_COMMAND_OK 0x8000 + +/*! @brief MT9M114 system state definitions. */ +#define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28 +#define MT9M114_SYS_STATE_STREAMING 0x31 +#define MT9M114_SYS_STATE_START_STREAMING 0x34 +#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40 +#define MT9M114_SYS_STATE_SUSPENDED 0x41 +#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50 +#define MT9M114_SYS_STATE_STANDBY 0x52 +#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54 + +/*! @brief MT9M114 system set-state command retults. */ +#define MT9M114_SYS_STATE_SET_RESULT_ENOERR 0x00 /* command successful */ +#define MT9M114_SYS_STATE_SET_RESULTEINVAL 0x0C /* invalid configuration */ +#define MT9M114_SYS_STATE_SET_RESULTENOSPC 0x0D /* resource not available */ + +#define MT9M114_OUTPUT_FORMAT_SWAP_RB (1 << 0) +#define MT9M114_OUTPUT_FORMAT_SWAP_BYTES (1 << 1) +#define MT9M114_OUTPUT_FORMAT_MONO (1 << 2) +#define MT9M114_OUTPUT_FORMAT_BT656 (1 << 3) +#define MT9M114_OUTPUT_FORMAT_BT656_FIXED (1 << 4) +#define MT9M114_OUTPUT_FORMAT_YUV (0 << 8) +#define MT9M114_OUTPUT_FORMAT_RGB (1 << 8) +#define MT9M114_OUTPUT_FORMAT_BAYER (2 << 8) +#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10 (0 << 10) +#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_PRE (1 << 10) +#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_POST (2 << 10) +#define MT9M114_OUTPUT_FORMAT_PROCESSED_BAYER (3 << 10) +#define MT9M114_OUTPUT_FORMAT_RGB565 (0 << 12) +#define MT9M114_OUTPUT_FORMAT_RGB555 (1 << 12) +#define MT9M114_OUTPUT_FORMAT_XRGB444 (2 << 12) +#define MT9M114_OUTPUT_FORMAT_RGB444X (3 << 12) + +#define MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR (0x1) +#define MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP (0x2) +#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN_MASK (0x30) +#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN (0x30) +#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN_MASK (0x300) +#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN (0x300) + +#ifdef __cplusplus +extern "C" { +#endif +typedef struct { + uint16_t reg; /* 16bit reg address */ + uint8_t size; /* reg size in byte */ + uint32_t value; /* reg value */ +} mt9m114_reg_t; + +/*! + * @brief MT9M114 read register. + * + * @param[in] context camera_operate_context. + * @param[in] reg reg address(16 bits) + * @param[in] reg_size reg size in bytes + * @param[out] value reg data from device + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_read_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, void *value); + +/*! + * @brief MT9M114 write register. + * + * @param[in] context camera_operate_context. + * @param[in] reg reg address(16 bits) + * @param[in] reg_size reg size in bytes + * @param[in] value reg data to device + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_write_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t value); + +/*! + * @brief MT9M114 modify register. + * + * @param[in] context camera_operate_context. + * @param[in] reg reg address(16 bits) + * @param[in] reg_size reg size in bytes + * @param[in] mask bits can be modified + * @param[in] value value should be set + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_modify_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t mask, uint32_t value); + +/*! + * @brief MT9M114 multiwrite registers. + * + * @param[in] context camera_operate_context. + * @param[in] regs pointer to array of mt9m114_reg_t, include reg addr, reg size and value + * @param[in] num array size of [regs] + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_multiwrite(camera_context_t *context, const mt9m114_reg_t regs[], uint32_t num); + +/*! + * @brief MT9M114 check chipid. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_check_chip_id(camera_context_t *context); + +/*! + * @brief MT9M114 set next state and switch to it. + * + * @param[in] context camera_operate_context. + * @param[in] next_state next device state. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_setstate(camera_context_t *context, uint16_t next_state); + +/*! + * @brief MT9M114 get current state. + * + * @param[in] context camera_operate_context. + * @param[out] state current device state. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_get_current_state(camera_context_t *context, uint8_t *state); + +/*! + * @brief MT9M114 soft reset. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_software_reset(camera_context_t *context); + +/*! + * @brief MT9M114 set pixformat. + * + * @param[in] context camera_operate_context. + * @param[in] pixformat pixformat. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_set_pixformat(camera_context_t *context, display_pixel_format_t pixformat); + +/*! + * @brief MT9M114 set framerate. + * + * @param[in] context camera_operate_context. + * @param[in] framerate framerate. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_set_framerate(camera_context_t *context, int framerate); + +/*! + * @brief MT9M114 set brightness. + * + * @param[in] context camera_operate_context. + * @param[in] level brightness. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_set_brightness(camera_context_t *context, int level); + +/*! + * @brief MT9M114 start to transfer image data. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_start(camera_context_t *context); + +/*! + * @brief MT9M114 stop working and enter SUSPEND mode. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_stop(camera_context_t *context); + +/*! + * @brief MT9M114 enable or disable MONO mode. + * + * @param[in] context camera_operate_context. + * @param[in] enable enable or disable mono. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_enable_mono(camera_context_t *context, bool enable); + +/*! + * @brief MT9M114 initialization. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_init(camera_context_t *context, camera_config_t *camera_config); +#ifdef __cplusplus +} +#endif + +/** + * @} + * + */ + +#endif /* HPM_MT9M114_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c index 33e807b0dd..5832531c9e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,11 @@ #include "hpm_ov5640.h" +static camera_param_dvp_t camera_dvp_param = { + .hsync_active_low = true, + .vsync_active_low = false, +}; + hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) { assert(camera_context->delay_ms != NULL); @@ -30,3 +35,8 @@ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t return stat; } +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) +{ + camera_config->interface_param = (void *)&camera_dvp_param; + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c index 672e7055eb..30c195c2d5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -456,12 +456,9 @@ static const ov5640_clock_config_t *ov5640_get_clock_config(const camera_config_ { uint32_t i; - if (camera_interface_dvp == config->interface) - { - for (i = 0; i < ARRAY_SIZE(ov5640_dvp_clock_configs); i++) - { - if (HPM_CAMERA_RESOLUTION(config->width, config->height) == ov5640_dvp_clock_configs[i].resolution) - { + if (camera_interface_dvp == config->interface) { + for (i = 0; i < ARRAY_SIZE(ov5640_dvp_clock_configs); i++) { + if (HPM_CAMERA_RESOLUTION(config->width, config->height) == ov5640_dvp_clock_configs[i].resolution) { return &ov5640_dvp_clock_configs[i]; } } @@ -475,7 +472,12 @@ hpm_stat_t ov5640_read_register(camera_context_t *context, uint16_t reg, uint8_t uint8_t r[2]; r[0] = reg >> 8; r[1] = reg & 0xFF; - return i2c_master_address_read(context->ptr, OV5640_I2C_ADDR, r, sizeof(r), buf, 1); + + hpm_stat_t stat = i2c_master_write(context->ptr, context->i2c_device_addr, r, 2); + if (stat != status_success) { + return stat; + } + return i2c_master_read(context->ptr, context->i2c_device_addr, buf, 1); } hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_t val) @@ -483,7 +485,7 @@ hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_ uint8_t r[2]; r[0] = reg >> 8; r[1] = reg & 0xFF; - return i2c_master_address_write(context->ptr, OV5640_I2C_ADDR, r, sizeof(r), &val, 1); + return i2c_master_address_write(context->ptr, context->i2c_device_addr, r, sizeof(r), &val, 1); } hpm_stat_t ov5640_write_multi_registers(camera_context_t *context, const ov5640_reg_val_t regval[], uint32_t len) @@ -491,8 +493,7 @@ hpm_stat_t ov5640_write_multi_registers(camera_context_t *context, const ov5640_ uint32_t i; hpm_stat_t stat = status_success; - for (i = 0; i < len; i++) - { + for (i = 0; i < len; i++) { HPM_CHECK_RET(ov5640_write_register(context, regval[i].regaddr, regval[i].regval)); } @@ -513,19 +514,19 @@ hpm_stat_t ov5640_set_pixel_format(camera_context_t *context, display_pixel_form { hpm_stat_t stat = status_success; - switch (pixel_format) - { - case display_pixel_format_yuv422: - HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x3F)); - HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x00)); - break; - case display_pixel_format_rgb565: - HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x6F)); - HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x01)); - break; - default: - stat = status_invalid_argument; - break; + switch (pixel_format) { + case display_pixel_format_y8: + case display_pixel_format_yuv422: + HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x30)); + HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x00)); + break; + case display_pixel_format_rgb565: + HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x6F)); + HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x01)); + break; + default: + stat = status_invalid_argument; + break; } return stat; @@ -555,29 +556,28 @@ hpm_stat_t ov5640_set_image_size(camera_context_t *context, camera_config_t *ov_ { hpm_stat_t stat = status_success; - switch(HPM_CAMERA_RESOLUTION(ov_config->width, ov_config->height)) - { - case video_resolution_800_480: - stat = ov5640_write_multi_registers(context, ov5640_resolution_800_480_param, ARRAY_SIZE(ov5640_resolution_800_480_param)); - break; - case video_resolution_vga: - stat = ov5640_write_multi_registers(context, ov5640_resolution_vga_param, ARRAY_SIZE(ov5640_resolution_vga_param)); - break; - case video_resolution_qvga: - stat = ov5640_write_multi_registers(context, ov5640_resolution_qvga_param, ARRAY_SIZE(ov5640_resolution_qvga_param)); - break; - case video_resolution_480_272: - stat = ov5640_write_multi_registers(context, ov5640_resolution_480_272_param, ARRAY_SIZE(ov5640_resolution_480_272_param)); - break; - case video_resolution_720p: - stat = ov5640_write_multi_registers(context, ov5640_resolution_720p_param, ARRAY_SIZE(ov5640_resolution_720p_param)); - break; - case video_resolution_1080p: - stat = ov5640_write_multi_registers(context, ov5640_resolution_1080p_param, ARRAY_SIZE(ov5640_resolution_1080p_param)); - break; - default: - stat = status_invalid_argument; - break; + switch (HPM_CAMERA_RESOLUTION(ov_config->width, ov_config->height)) { + case video_resolution_800_480: + stat = ov5640_write_multi_registers(context, ov5640_resolution_800_480_param, ARRAY_SIZE(ov5640_resolution_800_480_param)); + break; + case video_resolution_vga: + stat = ov5640_write_multi_registers(context, ov5640_resolution_vga_param, ARRAY_SIZE(ov5640_resolution_vga_param)); + break; + case video_resolution_qvga: + stat = ov5640_write_multi_registers(context, ov5640_resolution_qvga_param, ARRAY_SIZE(ov5640_resolution_qvga_param)); + break; + case video_resolution_480_272: + stat = ov5640_write_multi_registers(context, ov5640_resolution_480_272_param, ARRAY_SIZE(ov5640_resolution_480_272_param)); + break; + case video_resolution_720p: + stat = ov5640_write_multi_registers(context, ov5640_resolution_720p_param, ARRAY_SIZE(ov5640_resolution_720p_param)); + break; + case video_resolution_1080p: + stat = ov5640_write_multi_registers(context, ov5640_resolution_1080p_param, ARRAY_SIZE(ov5640_resolution_1080p_param)); + break; + default: + stat = status_invalid_argument; + break; } return stat; @@ -588,8 +588,7 @@ hpm_stat_t ov5640_set_clock_config(camera_context_t *context, camera_config_t *o hpm_stat_t stat = status_success; const ov5640_clock_config_t *clock_config = ov5640_get_clock_config(ov_config); - if(NULL == clock_config) - { + if (NULL == clock_config) { return status_invalid_argument; } @@ -606,8 +605,7 @@ hpm_stat_t ov5640_set_interface(camera_context_t *context, camera_config_t *ov_c { hpm_stat_t stat = status_success; - if (camera_interface_dvp == ov_config->interface) - { + if (camera_interface_dvp == ov_config->interface) { HPM_CHECK_RET(ov5640_write_register(context, 0x3034, 0x1a)); /* Set Frex, Vsync, Href, PCLK, data, GPIO to output. */ @@ -643,18 +641,14 @@ hpm_stat_t ov5640_set_brightness(camera_context_t *context, int32_t brightness) { hpm_stat_t stat = status_success; - if ((brightness < -4) || (brightness > 4)) - { + if ((brightness < -4) || (brightness > 4)) { return status_invalid_argument; } HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); - if (brightness >= 0) - { + if (brightness >= 0) { HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x01)); - } - else - { + } else { brightness = -brightness; HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x09)); } @@ -672,8 +666,7 @@ hpm_stat_t ov5640_set_contrast(camera_context_t *context, int32_t contrast) hpm_stat_t stat = status_success; uint8_t regval; - if ((-4 > contrast) || (4 < contrast)) - { + if ((-4 > contrast) || (4 < contrast)) { return status_invalid_argument; } @@ -697,8 +690,7 @@ hpm_stat_t ov5640_set_saturation(camera_context_t *context, int32_t saturation) hpm_stat_t stat = status_success; uint8_t regval; - if ((-4 > saturation) || (4 < saturation)) - { + if ((-4 > saturation) || (4 < saturation)) { return status_invalid_argument; } @@ -723,10 +715,8 @@ hpm_stat_t ov5640_set_light_mode(camera_context_t *context, int32_t lightmode) hpm_stat_t stat = status_success; uint8_t i; - for (i = 0; i < ARRAY_SIZE(ov5640_light_mode_configs); i++) - { - if (lightmode == (int32_t)ov5640_light_mode_configs[i].lightmode) - { + for (i = 0; i < ARRAY_SIZE(ov5640_light_mode_configs); i++) { + if (lightmode == (int32_t)ov5640_light_mode_configs[i].lightmode) { HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); HPM_CHECK_RET(ov5640_write_register(context, 0x3406, ov5640_light_mode_configs[i].awbctrl)); @@ -753,10 +743,8 @@ hpm_stat_t ov5640_set_special_effect(camera_context_t *context, int32_t effect) hpm_stat_t stat = status_success; uint8_t i; - for (i = 0; i < ARRAY_SIZE(ov5640_special_effect_configs); i++) - { - if (effect == (int32_t)ov5640_special_effect_configs[i].effect) - { + for (i = 0; i < ARRAY_SIZE(ov5640_special_effect_configs); i++) { + if (effect == (int32_t)ov5640_special_effect_configs[i].effect) { HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); HPM_CHECK_RET(ov5640_write_register(context, 0x5580, ov5640_special_effect_configs[i].sdectrl0)); @@ -819,4 +807,4 @@ void ov5640_power_up(camera_context_t *context) context->delay_ms(2); context->write_rst(OV5640_RST_INACTIVE); context->delay_ms(20); -} \ No newline at end of file +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h index 29d8aa311c..d7ab07abbc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c index 55f15d41d5..f140ad2c6b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,11 @@ #include "hpm_ov7725.h" +static camera_param_dvp_t camera_dvp_param = { + .hsync_active_low = true, + .vsync_active_low = false, +}; + hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) { assert(camera_context->delay_ms != NULL); @@ -30,3 +35,8 @@ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t return stat; } +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) +{ + camera_config->interface_param = (void *)&camera_dvp_param; + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c index 5c9e8c405b..675fab0a5c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,19 +8,15 @@ #include "hpm_ov7725.h" static const uint8_t ov7725_default_regs[][2] = { - {COM3, COM3_SWAP_YUV}, - {COM7, COM7_RES_VGA | COM7_FMT_RGB565}, - - {COM4, 0x01}, /* bypass PLL */ - {CLKRC, 0xC0}, /* Res/Bypass pre-scalar */ + {COM4, 0x41}, /* bypass PLL */ /* * VGA Window Size */ - {HSTART, 0x23}, - {HSIZE, 0xA0}, + {HSTART, 0x22}, + {HSIZE, 0xa4}, {VSTART, 0x07}, - {VSIZE, 0xF0}, + {VSIZE, 0xf0}, {HREF, 0x00}, /* @@ -35,14 +31,11 @@ static const uint8_t ov7725_default_regs[][2] = { {FIXGAIN, 0x09}, {AWB_CTRL0, 0xE0}, {DSP_CTRL1, 0xFF}, - - {DSP_CTRL2, DSP_CTRL2_VDCW_EN | DSP_CTRL2_HDCW_EN | DSP_CTRL2_HZOOM_EN | DSP_CTRL2_VZOOM_EN}, - + {DSP_CTRL2, 0x20}, {DSP_CTRL3, 0x00}, {DSP_CTRL4, 0x00}, - {DSPAUTO, 0xFF}, - {COM8, 0xF0}, + {COM8, 0xF8}, {COM6, 0xC5}, {COM9, 0x11}, {COM10, COM10_VSYNC_NEG | COM10_PCLK_MASK}, /* Invert VSYNC and MASK PCLK */ @@ -89,7 +82,7 @@ static const uint8_t ov7725_default_regs[][2] = { {MTX_CTRL, 0x1E}, {BRIGHTNESS, 0x08}, - {CONTRAST, 0x30}, + {CONTRAST, 0x20}, {UVADJ0, 0x81}, {SDE, (SDE_CONT_BRIGHT_EN | SDE_SATURATION_EN)}, @@ -109,26 +102,111 @@ static const uint8_t ov7725_default_regs[][2] = { {LC_COEFB, 0x14}, {LC_COEFR, 0x17}, {LC_CTR, 0x05}, - {COM5, 0xF5}, + {COM5, 0x65}, +}; + + +static const uint8_t ov7725_default_yuv_regs[][2] = { + {COM12, 0x03}, + {HSTART, 0x22}, + {HSIZE, 0xa4}, + {VSTART, 0x07}, + {VSIZE, 0xf0}, + {HREF, 0x00}, + {HOUTSIZE, 0xa0}, + {VOUTSIZE, 0xf0}, + {EXHCH, 0x00}, + {CLKRC, 0x01}, + {TGT_B, 0x7f}, + {FIXGAIN, 0x09}, + {AWB_CTRL0, 0xe0}, + {DSP_CTRL1, 0xff}, + {DSP_CTRL2, 0x20}, + {DSP_CTRL3, 0x00}, + {DSP_CTRL4, 0x48}, + {COM8, 0xf0}, + {COM4, 0x41}, /* 0x51/ 0x61/ 0x71 for different AEC/AGC window */ + {COM6, 0xc5}, + {COM9, 0x11}, + {BDBASE, 0x7f}, + {DBSTEP, 0x03}, + {AEW, 0x40}, + {AEB, 0x30}, + {VPT, 0xa1}, + {EXHCL, 0x00}, + {AWB_CTRL3, 0xaa}, + {COM8, 0xff}, + {EDGE1, 0x05}, + {DNSOFF, 0x01}, + {EDGE2, 0x03}, + {EDGE3, 0x00}, + {MTX1, 0xb0}, + {MTX2, 0x9d}, + {MTX3, 0x13}, + {MTX4, 0x16}, + {MTX5, 0x7b}, + {MTX6, 0x91}, + {MTX_CTRL, 0x1e}, + {BRIGHTNESS, 0x08}, + {CONTRAST, 0x20}, + {UVADJ0, 0x81}, + {SDE, 0x06}, + /* Gamma */ + {GAM1, 0x0c}, + {GAM2, 0x16}, + {GAM3, 0x2a}, + {GAM4, 0x4e}, + {GAM5, 0x61}, + {GAM6, 0x6f}, + {GAM7, 0x7b}, + {GAM8, 0x86}, + {GAM9, 0x8e}, + {GAM10, 0x97}, + {GAM11, 0xa4}, + {GAM12, 0xaf}, + {GAM13, 0xc5}, + {GAM14, 0xd7}, + {GAM15, 0xe8}, + {SLOP, 0x20}, + /* for 30 fps,0Hz */ + {DM_LNL, 0x00}, + {BDBASE, 0x7f}, + {DBSTEP, 0x03}, + + /* Lens Correcon, should be tuned with real camera module */ + {LC_RADI, 0x10}, + {LC_COEF, 0x10}, + {LC_COEFB, 0x14}, + {LC_COEFR, 0x17}, + {LC_CTR, 0x05}, + {COM5, 0x65}, }; hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf) { - return i2c_master_address_read(context->ptr, OV7725_I2C_ADDR, ®, 1, buf, 1); + hpm_stat_t stat = i2c_master_write(context->ptr, context->i2c_device_addr, ®, 1); + if (stat != status_success) { + return stat; + } + return i2c_master_read(context->ptr, context->i2c_device_addr, buf, 1); + } hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val) { - return i2c_master_address_write(context->ptr, OV7725_I2C_ADDR, ®, 1, &val, 1); + return i2c_master_address_write(context->ptr, context->i2c_device_addr, ®, 1, &val, 1); } -void ov7725_restore_default_values(camera_context_t *context) +hpm_stat_t ov7725_load_settings(camera_context_t *context, uint8_t *reg_values, uint32_t count) { - uint32_t i; - for (i = 0; i < (ARRAY_SIZE(ov7725_default_regs)); i++) - { - ov7725_write_register(context, ov7725_default_regs[i][0], ov7725_default_regs[i][1]); + hpm_stat_t stat = status_success; + for (uint32_t i = 0, j = 0; i < count; i++, j += 2) { + stat = ov7725_write_register(context, reg_values[j], reg_values[j+1]); + if (stat != status_success) { + break; + } } + return stat; } hpm_stat_t ov7725_software_reset(camera_context_t *context) @@ -196,15 +274,23 @@ hpm_stat_t ov7725_set_pixel_format(camera_context_t *context, display_pixel_form stat |= ov7725_read_register(context, COM7, &val); val &= ~0x1F; switch (pixel_format) { - case display_pixel_format_rgb565: - val |= COM7_FMT_RGB565; - break; - case display_pixel_format_rgb444: - val |= COM7_FMT_RGB444; - break; - default: - stat = status_invalid_argument; - break; + case display_pixel_format_rgb565: + val |= COM7_FMT_RGB565; + break; + case display_pixel_format_rgb444: + val |= COM7_FMT_RGB444; + break; + case display_pixel_format_yuv422: + case display_pixel_format_y8: + val |= COM7_FMT_YUV; + break; + case display_pixel_format_raw8: + stat |= ov7725_write_register(context, DSP_CTRL4, DSP_CTRL4_RAW8); + val |= COM7_FMT_R_BAYER; + break; + default: + stat = status_invalid_argument; + break; } if (stat != status_success) { return stat; @@ -221,19 +307,22 @@ hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config) { hpm_stat_t stat = status_success; - ov7725_restore_default_values(context); + switch (ov_config->pixel_format) { + case display_pixel_format_yuv422: + case display_pixel_format_y8: + ov7725_load_settings(context, (uint8_t *) ov7725_default_yuv_regs, ARRAY_SIZE(ov7725_default_yuv_regs)); + break; + default: + ov7725_load_settings(context, (uint8_t *) ov7725_default_regs, ARRAY_SIZE(ov7725_default_regs)); + stat |= ov7725_write_register(context, COM7, COM7_RES_VGA | COM7_FMT_RGB565); + stat |= ov7725_write_register(context, COM10, 0); + stat |= ov7725_write_register(context, COM3, 0); + break; + } stat |= ov7725_write_register(context, CLKRC, 0x2); stat |= ov7725_write_register(context, COM4, 0x41); - stat |= ov7725_write_register(context, EXHCL, 0); - stat |= ov7725_write_register(context, DM_LNL, 0); - stat |= ov7725_write_register(context, DM_LNH, 0); - stat |= ov7725_write_register(context, ADVFL, 0); - stat |= ov7725_write_register(context, ADVFH, 0); - stat |= ov7725_write_register(context, COM5, 0x65); - stat |= ov7725_write_register(context, COM10, 0); - stat |= ov7725_write_register(context, COM3, 0); - stat |= ov7725_write_register(context, COM2, 0x3); + stat |= ov7725_set_framesize(context, ov_config->width, ov_config->height); stat |= ov7725_set_pixel_format(context, ov_config->pixel_format); if (stat != status_success) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h index 550ff3ae39..d3df505e88 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,6 +10,23 @@ #include "hpm_common.h" #include "hpm_camera_config.h" +/** + * @brief OV7725 sensor driver APIs + * @defgroup ov7725_interface sensor driver APIs + * @ingroup component_interfaces + * @{ + * + + */ +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ + +/** + * @brief OV7725 definition + */ #define OV7725_ACTIVE_IMAGE_WIDTH (480U) #define OV7725_ACTIVE_IMAGE_HEIGHT (480U) #define OV7725_I2C_ADDR (0x21U) @@ -22,7 +39,9 @@ #define OV7725_RST_INACTIVE 1 #define OV7725_PWDN_ACTIVE 1 #define OV7725_PWDN_INACTIVE 0 - +/** + * @brief OV7725 registers + */ #define GAIN (0x00U) /* AGC – Gain control gain setting */ #define BLUE (0x01U) /* AWB – Blue channel gain setting */ #define RED (0x02U) /* AWB – Red channel gain setting */ @@ -340,31 +359,54 @@ extern "C" { #endif -/* - * ov7725 initialization routine +/** + * @brief ov7725 initialization routine + * @param [in] context camera_context_t + * @param [in] ov_config camera config structure */ hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config); -/* - * ov7725 read register +/** + * @brief ov7725 read register + * @param [in] context camera_context_t + * @param [in] reg register address + * @param [in] buf buffer to store read data + * @retval status_success if everything is okay */ hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf); -/* - * ov7725 write register +/** + * @brief ov7725 write register + * @param [in] context camera_context_t + * @param [in] reg register address + * @param [in] val value to be written + * @retval status_success if everything is okay */ hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val); -/* - * ov7725 reset +/** + * @brief ov7725 reset + * @param [in] context camera_context_t */ hpm_stat_t ov7725_software_reset(camera_context_t *context); -/* - * ov7725 check chip id +/** + * @brief ov7725 check chip id + * @param [in] context camera_context_t */ hpm_stat_t ov7725_check_chip_id(camera_context_t *context); + +/** + * @brief ov7725 load set of register-value pairs + * + * @param [in] context camera_context_t + * @param [in] reg_values register-value pair in 2-d array form, ex. reg_values[][2] = {{COM3, 0x1}}; + * @parma [in] count register-value pair count in 2-d array + * @retval status_success if everything is okay + */ +hpm_stat_t ov7725_load_settings(camera_context_t *context, uint8_t *reg_values, uint32_t count); + /** * @brief ov7725 power up * @@ -375,4 +417,10 @@ void ov7725_power_up(camera_context_t *context); #ifdef __cplusplus } #endif + +/** + * @} + * + */ + #endif /* HPM_OV7725_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c index 1899b3f5ec..46d0068306 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c @@ -1,132 +1,105 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2019 NXP - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#include #include "hpm_sgtl5000.h" -/******************************************************************************* - * Definitations - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ +#ifndef HPM_SGTL5000_MCLK_TOLERANCE +#define HPM_SGTL5000_MCLK_TOLERANCE (4U) +#endif hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config) { assert(context != NULL); assert(config != NULL); - if (sgtl_write_reg(context, CHIP_ANA_POWER, 0x6AFF) != status_success) - { + if (sgtl_write_reg(context, CHIP_ANA_POWER, 0x6AFF) != status_success) { return status_fail; } /* Set the data route */ - if (sgtl_set_data_route(context, config->route) != status_success) - { + if (sgtl_set_data_route(context, config->route) != status_success) { return status_fail; } /* Set sgtl5000 to master or slave */ sgtl_set_master_mode(context, config->master); - /* Input Volume Control - Configure ADC left and right analog volume to desired default. - Example shows volume of 0dB. */ - if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0000U) != status_success) - { + /* + * Input Volume Control + * Configure ADC left and right analog volume to desired default. + * Example shows volume of 0dB. + */ + if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0000U) != status_success) { return status_fail; } - /* Volume and Mute Control - Configure HP_OUT left and right volume to minimum, unmute. - HP_OUT and ramp the volume up to desired volume.*/ - if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x1818U) != status_success) - { + /* + * Volume and Mute Control + * Configure HP_OUT left and right volume to minimum, unmute. + * HP_OUT and ramp the volume up to desired volume. + */ + if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x1818U) != status_success) { return status_fail; } - if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFEFU, 0x0000U) != status_success) - { + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFEFU, 0x0000U) != status_success) { return status_fail; } /* LINEOUT and DAC volume control */ - if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFEFFU, 0x0000U) != status_success) - { + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFEFFU, 0x0000U) != status_success) { return status_fail; } /* Configure DAC left and right digital volume */ - if (sgtl_write_reg(context, CHIP_DAC_VOL, 0x5C5CU) != status_success) - { + if (sgtl_write_reg(context, CHIP_DAC_VOL, 0x5C5CU) != status_success) { return status_fail; } /* Configure ADC volume, reduce 6db. */ - if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0100U) != status_success) - { + if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0100U) != status_success) { return status_fail; } /* Unmute DAC */ - if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFFBU, 0x0000U) != status_success) - { + if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFFBU, 0x0000U) != status_success) { return status_fail; } - if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFF7U, 0x0000U) != status_success) - { + if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFF7U, 0x0000U) != status_success) { return status_fail; } /* Unmute ADC */ - if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFFEU, 0x0000U) != status_success) - { + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFFEU, 0x0000U) != status_success) { return status_fail; } /* Set the audio format */ - if (sgtl_set_protocol(context, config->bus) != status_success) - { + if (sgtl_set_protocol(context, config->bus) != status_success) { return status_fail; } if (sgtl_config_data_format(context, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width) != - status_success) - { + status_success) { return status_fail; } /* sclk valid edge */ - if (config->format.sclk_edge == sgtl_sclk_valid_edge_rising) - { + if (config->format.sclk_edge == sgtl_sclk_valid_edge_rising) { if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE) != - status_success) - { + status_success) { return status_fail; } - } - else - { + } else { if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE) != - status_success) - { + status_success) { return status_fail; } } @@ -150,12 +123,9 @@ hpm_stat_t sgtl_deinit(sgtl_context_t *context) void sgtl_set_master_mode(sgtl_context_t *context, bool master) { - if (master == true) - { + if (master == true) { (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_MASTER); - } - else - { + } else { (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_SLAVE); } } @@ -163,45 +133,44 @@ void sgtl_set_master_mode(sgtl_context_t *context, bool master) hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module) { hpm_stat_t stat = status_success; - switch (module) - { - case sgtl_module_adc: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_ADC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_ADC_POWERUP_SHIFT))); - break; - case sgtl_module_dac: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAC_POWERUP_SHIFT))); - break; - case sgtl_module_dap: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAP_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); - break; - case sgtl_module_i2sin: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_I2S_IN_ENABLE_SHIFT))); - break; - case sgtl_module_i2sout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); - break; - case sgtl_module_hp: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); - break; - case sgtl_module_lineout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_LINEOUT_POWERUP_SHIFT))); - break; - default: - stat = status_invalid_argument; - break; + switch (module) { + case sgtl_module_adc: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_ADC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_ADC_POWERUP_SHIFT))); + break; + case sgtl_module_dac: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAC_POWERUP_SHIFT))); + break; + case sgtl_module_dap: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAP_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); + break; + case sgtl_module_i2sin: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_I2S_IN_ENABLE_SHIFT))); + break; + case sgtl_module_i2sout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); + break; + case sgtl_module_hp: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); + break; + case sgtl_module_lineout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_LINEOUT_POWERUP_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; } return stat; } @@ -209,45 +178,44 @@ hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module) hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module) { hpm_stat_t stat = status_success; - switch (module) - { - case sgtl_module_adc: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_ADC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_ADC_POWERUP_SHIFT))); - break; - case sgtl_module_dac: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAC_POWERUP_SHIFT))); - break; - case sgtl_module_dap: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAP_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); - break; - case sgtl_module_i2sin: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_I2S_IN_ENABLE_SHIFT))); - break; - case sgtl_module_i2sout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); - break; - case sgtl_module_hp: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); - break; - case sgtl_module_lineout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_LINEOUT_POWERUP_SHIFT))); - break; - default: - stat = status_invalid_argument; - break; + switch (module) { + case sgtl_module_adc: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_ADC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_ADC_POWERUP_SHIFT))); + break; + case sgtl_module_dac: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAC_POWERUP_SHIFT))); + break; + case sgtl_module_dap: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAP_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); + break; + case sgtl_module_i2sin: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_I2S_IN_ENABLE_SHIFT))); + break; + case sgtl_module_i2sout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); + break; + case sgtl_module_hp: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); + break; + case sgtl_module_lineout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_LINEOUT_POWERUP_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; } return stat; } @@ -255,69 +223,68 @@ hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module) hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route) { hpm_stat_t stat = status_success; - switch (route) - { - case sgtl_route_bypass: - /* Bypass means from line-in to HP*/ - HPM_CHECK_RET(sgtl_write_reg(context, CHIP_DIG_POWER, 0x0000)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_LINEIN)); - break; - case sgtl_route_playback: - /* Data route I2S_IN-> DAC-> HP */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - break; - case sgtl_route_playback_record: - /* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); - break; - case sgtl_route_playback_with_dap: - /* I2S_IN->DAP->DAC->HP */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - break; - case sgtl_route_playback_with_dap_record: - /* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); - HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, 0x0001)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); - break; - case sgtl_route_record: - /* LINE_IN->ADC->I2S_OUT */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); - break; - default: - stat = status_invalid_argument; - break; + switch (route) { + case sgtl_route_bypass: + /* Bypass means from line-in to HP*/ + HPM_CHECK_RET(sgtl_write_reg(context, CHIP_DIG_POWER, 0x0000)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_LINEIN)); + break; + case sgtl_route_playback: + /* Data route I2S_IN-> DAC-> HP */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + break; + case sgtl_route_playback_record: + /* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + case sgtl_route_playback_with_dap: + /* I2S_IN->DAP->DAC->HP */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + break; + case sgtl_route_playback_with_dap_record: + /* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, 0x0001)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + case sgtl_route_record: + /* LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + default: + stat = status_invalid_argument; + break; } return stat; } @@ -325,35 +292,34 @@ hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route) hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol) { hpm_stat_t stat = status_success; - switch (protocol) - { - case sgtl_bus_i2s: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); - break; - case sgtl_bus_left_justified: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); - break; - case sgtl_bus_right_justified: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_RJ)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); - break; - case sgtl_bus_pcma: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); - break; - case sgtl_bus_pcmb: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); - break; - default: - stat = status_invalid_argument; - break; + switch (protocol) { + case sgtl_bus_i2s: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_left_justified: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_right_justified: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_RJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_pcma: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); + break; + case sgtl_bus_pcmb: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); + break; + default: + stat = status_invalid_argument; + break; } return stat; } @@ -362,45 +328,40 @@ hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32 { uint16_t vol = 0; hpm_stat_t stat = status_success; - switch (module) - { - case sgtl_module_adc: - if (volume > SGTL5000_ADC_MAX_VOLUME_VALUE) - { - return status_invalid_argument; - } + switch (module) { + case sgtl_module_adc: + if (volume > SGTL5000_ADC_MAX_VOLUME_VALUE) { + return status_invalid_argument; + } - vol = (uint16_t)(volume | (volume << 4U)); - stat = sgtl_modify_reg(context, CHIP_ANA_ADC_CTRL, - SGTL5000_ADC_VOL_LEFT_CLR_MASK & SGTL5000_ADC_VOL_RIGHT_CLR_MASK, vol); - break; - case sgtl_module_dac: - if ((volume > SGTL5000_DAC_MAX_VOLUME_VALUE) || (volume < SGTL5000_DAC_MIN_VOLUME_VALUE)) - { - return status_invalid_argument; - } - vol = (uint16_t)(volume | (volume << 8U)); - stat = sgtl_write_reg(context, CHIP_DAC_VOL, vol); - break; - case sgtl_module_hp: - if (volume > SGTL5000_HEADPHONE_MAX_VOLUME_VALUE) - { - return status_invalid_argument; - } - vol = (uint16_t)(volume | (volume << 8U)); - stat = sgtl_write_reg(context, CHIP_ANA_HP_CTRL, vol); - break; - case sgtl_module_lineout: - if (volume > SGTL5000_LINE_OUT_MAX_VOLUME_VALUE) - { - return status_invalid_argument; - } - vol = (uint16_t)(volume | (volume << 8U)); - stat = sgtl_write_reg(context, CHIP_LINE_OUT_VOL, vol); - break; - default: - stat = status_invalid_argument; - break; + vol = (uint16_t)(volume | (volume << 4U)); + stat = sgtl_modify_reg(context, CHIP_ANA_ADC_CTRL, + SGTL5000_ADC_VOL_LEFT_CLR_MASK & SGTL5000_ADC_VOL_RIGHT_CLR_MASK, vol); + break; + case sgtl_module_dac: + if ((volume > SGTL5000_DAC_MAX_VOLUME_VALUE) || (volume < SGTL5000_DAC_MIN_VOLUME_VALUE)) { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_DAC_VOL, vol); + break; + case sgtl_module_hp: + if (volume > SGTL5000_HEADPHONE_MAX_VOLUME_VALUE) { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_ANA_HP_CTRL, vol); + break; + case sgtl_module_lineout: + if (volume > SGTL5000_LINE_OUT_MAX_VOLUME_VALUE) { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_LINE_OUT_VOL, vol); + break; + default: + stat = status_invalid_argument; + break; } return stat; } @@ -410,27 +371,26 @@ uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module) uint16_t vol = 0; hpm_stat_t stat = status_success; - switch (module) - { - case sgtl_module_adc: - stat = sgtl_read_reg(context, CHIP_ANA_ADC_CTRL, &vol); - vol = (vol & (uint16_t)SGTL5000_ADC_VOL_LEFT_GET_MASK) >> SGTL5000_ADC_VOL_LEFT_SHIFT; - break; - case sgtl_module_dac: - stat = sgtl_read_reg(context, CHIP_DAC_VOL, &vol); - vol = (vol & (uint16_t)SGTL5000_DAC_VOL_LEFT_GET_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; - break; - case sgtl_module_hp: - stat = sgtl_read_reg(context, CHIP_ANA_HP_CTRL, &vol); - vol = (vol & (uint16_t)SGTL5000_HP_VOL_LEFT_GET_MASK) >> SGTL5000_HP_VOL_LEFT_SHIFT; - break; - case sgtl_module_lineout: - stat = sgtl_read_reg(context, CHIP_LINE_OUT_VOL, &vol); - vol = (vol & (uint16_t)SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK) >> SGTL5000_LINE_OUT_VOL_LEFT_SHIFT; - break; - default: - vol = 0; - break; + switch (module) { + case sgtl_module_adc: + stat = sgtl_read_reg(context, CHIP_ANA_ADC_CTRL, &vol); + vol = (vol & (uint16_t)SGTL5000_ADC_VOL_LEFT_GET_MASK) >> SGTL5000_ADC_VOL_LEFT_SHIFT; + break; + case sgtl_module_dac: + stat = sgtl_read_reg(context, CHIP_DAC_VOL, &vol); + vol = (vol & (uint16_t)SGTL5000_DAC_VOL_LEFT_GET_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; + break; + case sgtl_module_hp: + stat = sgtl_read_reg(context, CHIP_ANA_HP_CTRL, &vol); + vol = (vol & (uint16_t)SGTL5000_HP_VOL_LEFT_GET_MASK) >> SGTL5000_HP_VOL_LEFT_SHIFT; + break; + case sgtl_module_lineout: + stat = sgtl_read_reg(context, CHIP_LINE_OUT_VOL, &vol); + vol = (vol & (uint16_t)SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK) >> SGTL5000_LINE_OUT_VOL_LEFT_SHIFT; + break; + default: + vol = 0; + break; } return stat == status_success ? vol : 0U; } @@ -438,34 +398,30 @@ uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module) hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute) { hpm_stat_t stat = status_success; - switch (module) - { - case sgtl_module_adc: - stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_ADC_CLR_MASK, mute ? 1U : 0U); - break; - case sgtl_module_dac: - if (mute) - { - stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, - SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x000C); - } - else - { - stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, - SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x0000); - } - break; - case sgtl_module_hp: - stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_HP_CLR_MASK, - ((uint16_t)mute << SGTL5000_MUTE_HP_SHIFT)); - break; - case sgtl_module_lineout: - stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_LO_CLR_MASK, - ((uint16_t)mute << SGTL5000_MUTE_LO_SHIFT)); - break; - default: - stat = status_invalid_argument; - break; + switch (module) { + case sgtl_module_adc: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_ADC_CLR_MASK, mute ? 1U : 0U); + break; + case sgtl_module_dac: + if (mute) { + stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, + SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x000C); + } else { + stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, + SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x0000); + } + break; + case sgtl_module_hp: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_HP_CLR_MASK, + ((uint16_t)mute << SGTL5000_MUTE_HP_SHIFT)); + break; + case sgtl_module_lineout: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_LO_CLR_MASK, + ((uint16_t)mute << SGTL5000_MUTE_LO_SHIFT)); + break; + default: + stat = status_invalid_argument; + break; } return stat; } @@ -474,150 +430,127 @@ hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint3 { uint16_t val = 0; uint16_t regVal = 0; - uint16_t mul_clk = 0U; + uint32_t mul_div = 0U; uint32_t sysFs = 0U; hpm_stat_t stat = status_success; /* Over sample rate can only up to 512, the least to 8k */ - if ((mclk / (MIN(sample_rate * 6U, 96000U)) > 512U) || (mclk / sample_rate < 256U)) - { + if ((mclk / (MIN(sample_rate * 6U, 96000U)) > 512U) || (mclk / sample_rate < 256U)) { return status_invalid_argument; } /* Configure the sample rate */ - switch (sample_rate) - { - case 8000: - if (mclk > 32000U * 512U) - { - val = 0x0038; - sysFs = 48000; - } - else - { - val = 0x0020; - sysFs = 32000; - } - break; - case 11025: - val = 0x0024; - sysFs = 44100; - break; - case 12000: - val = 0x0028; + switch (sample_rate) { + case 8000: + if (mclk > 32000U * 512U) { + val = 0x0038; sysFs = 48000; - break; - case 16000: - if (mclk > 32000U * 512U) - { - val = 0x003C; - sysFs = 96000; - } - else - { - val = 0x0010; - sysFs = 32000; - } - break; - case 22050: - val = 0x0014; - sysFs = 44100; - break; - case 24000: - if (mclk > 48000U * 512U) - { - val = 0x002C; - sysFs = 96000; - } - else - { - val = 0x0018; - sysFs = 48000; - } - break; - case 32000: - val = 0x0000; + } else { + val = 0x0020; sysFs = 32000; - break; - case 44100: - val = 0x0004; - sysFs = 44100; - break; - case 48000: - if (mclk > 48000U * 512U) - { - val = 0x001C; - sysFs = 96000; - } - else - { - val = 0x0008; - sysFs = 48000; - } - break; - case 96000: - val = 0x000C; + } + break; + case 11025: + val = 0x0024; + sysFs = 44100; + break; + case 12000: + val = 0x0028; + sysFs = 48000; + break; + case 16000: + if (mclk > 32000U * 512U) { + val = 0x003C; sysFs = 96000; - break; - default: - stat = status_invalid_argument; - break; + } else { + val = 0x0010; + sysFs = 32000; + } + break; + case 22050: + val = 0x0014; + sysFs = 44100; + break; + case 24000: + if (mclk > 48000U * 512U) { + val = 0x002C; + sysFs = 96000; + } else { + val = 0x0018; + sysFs = 48000; + } + break; + case 32000: + val = 0x0000; + sysFs = 32000; + break; + case 44100: + val = 0x0004; + sysFs = 44100; + break; + case 48000: + if (mclk > 48000U * 512U) { + val = 0x001C; + sysFs = 96000; + } else { + val = 0x0008; + sysFs = 48000; + } + break; + case 96000: + val = 0x000C; + sysFs = 96000; + break; + default: + stat = status_invalid_argument; + break; } - if (stat != status_success) - { + if (stat != status_success) { return stat; } - if (sgtl_read_reg(context, CHIP_I2S_CTRL, ®Val) != status_success) - { + if (sgtl_read_reg(context, CHIP_I2S_CTRL, ®Val) != status_success) { return status_fail; } - /* While as slave, Fs is input */ - if ((regVal & SGTL5000_I2S_MS_GET_MASK) == 0U) - { - sysFs = sample_rate; - } - mul_clk = (uint16_t)(mclk / sysFs); - /* Configure the mul_clk. Sgtl-5000 only support 256, 384 and 512 oversample rate */ - if ((mul_clk / 128U - 2U) > 2U) - { + mul_div = mclk / sysFs; + if (abs(mul_div - 256) <= 256 * HPM_SGTL5000_MCLK_TOLERANCE) { + mul_div = 256; + } else if (abs(mul_div - 384) <= 384 * HPM_SGTL5000_MCLK_TOLERANCE) { + mul_div = 384; + } else if (abs(mul_div - 512) <= 512 * HPM_SGTL5000_MCLK_TOLERANCE) { + mul_div = 512; + } else { return status_invalid_argument; } - else - { - val |= (mul_clk / 128U - 2U); - } + val |= (mul_div / 128U - 2U); - if (sgtl_write_reg(context, CHIP_CLK_CTRL, val) != status_success) - { + if (sgtl_write_reg(context, CHIP_CLK_CTRL, val) != status_success) { return status_fail; } /* Data bits configure,sgtl supports 16bit, 20bit 24bit, 32bit */ - if (sgtl_modify_reg(context, CHIP_I2S_CTRL, 0xFEFF, SGTL5000_I2S_SCLKFREQ_64FS) != status_success) - { + if (sgtl_modify_reg(context, CHIP_I2S_CTRL, 0xFEFF, SGTL5000_I2S_SCLKFREQ_64FS) != status_success) { return status_fail; } - switch (bits) - { - case 16: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_16); - break; - case 20: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_20); - break; - case 24: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_24); - break; - case 32: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_32); - break; - default: - stat = status_invalid_argument; - break; + switch (bits) { + case 16: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_16); + break; + case 20: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_20); + break; + case 24: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_24); + break; + case 32: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_32); + break; + default: + stat = status_invalid_argument; + break; } return stat; @@ -628,13 +561,10 @@ hpm_stat_t sgtl_set_pay(sgtl_context_t *context, uint32_t playSource) uint16_t regValue = 0U, regBitMask = 0x40U; /* headphone source form PGA */ - if (playSource == (uint32_t)sgtl_play_source_linein) - { + if (playSource == (uint32_t)sgtl_play_source_linein) { regValue = 0x40U; - } + } else { /* headphone source from DAC */ - else - { regValue = 0U; } @@ -646,13 +576,10 @@ hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource) uint16_t regValue = 0U, regBitMask = 0x4U; /* ADC source form LINEIN */ - if (recordSource == (uint32_t)sgtl_record_source_linein) - { + if (recordSource == (uint32_t)sgtl_record_source_linein) { regValue = 0x4U; - } - /* ADC source from MIC */ - else - { + } else { + /* ADC source from MIC */ regValue = 0U; } @@ -693,8 +620,7 @@ hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_m /* Read the register value out */ retval = sgtl_read_reg(context, reg, ®_val); - if (retval != status_success) - { + if (retval != status_success) { return status_fail; } @@ -704,8 +630,7 @@ hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_m /* Write the data to register */ retval = sgtl_write_reg(context, reg, reg_val); - if (retval != status_success) - { + if (retval != status_success) { return status_fail; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h index 0d222efbe3..96e676b30e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2019 NXP - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -749,8 +749,7 @@ #define SGTL_I2C_BITRATE 100000U /*! @brief Modules in Sgtl5000 board. */ -typedef enum _sgtl5000_module -{ +typedef enum _sgtl5000_module { sgtl_module_adc = 0x0, /*!< ADC module in SGTL5000 */ sgtl_module_dac, /*!< DAC module in SGTL5000 */ sgtl_module_dap, /*!< DAP module in SGTL5000 */ @@ -767,8 +766,7 @@ typedef enum _sgtl5000_module * @note Only provide some typical data route, not all route listed. * Users cannot combine any routes, once a new route is set, the precios one would be replaced. */ -typedef enum _sgtl_route -{ +typedef enum _sgtl_route { sgtl_route_bypass = 0x0, /*!< LINEIN->Headphone. */ sgtl_route_playback, /*!< I2SIN->DAC->Headphone. */ sgtl_route_playback_record, /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */ @@ -781,8 +779,7 @@ typedef enum _sgtl_route * @brief The audio data transfer protocol choice. * Sgtl5000 only supports I2S format and PCM format. */ -typedef enum _sgtl_protocol -{ +typedef enum _sgtl_protocol { sgtl_bus_i2s = 0x0, /*!< I2S Type */ sgtl_bus_left_justified, /*!< Left justified */ sgtl_bus_right_justified, /*!< Right Justified */ @@ -793,8 +790,7 @@ typedef enum _sgtl_protocol /*! @brief sgtl play channel * @anchor _sgtl_play_channel */ -enum -{ +enum { sgtl_headphone_left = 0, /*!< headphone left channel */ sgtl_headphone_right = 1, /*!< headphone right channel */ sgtl_lineout_left = 2, /*!< lineout left channel */ @@ -804,8 +800,7 @@ enum /*! @brief sgtl record source * _sgtl_record_source */ -enum -{ +enum { sgtl_record_source_linein = 0U, /*!< record source line in */ sgtl_record_source_mic = 1U, /*!< record source single end */ }; @@ -813,22 +808,19 @@ enum /*! @brief sgtl play source * _stgl_play_source */ -enum -{ +enum { sgtl_play_source_linein = 0U, /*!< play source line in */ sgtl_play_source_dac = 1U, /*!< play source line in */ }; /*! @brief SGTL SCLK valid edge */ -typedef enum _sgtl_sclk_edge -{ +typedef enum _sgtl_sclk_edge { sgtl_sclk_valid_edge_rising = 0U, /*!< SCLK valid edge */ sgtl_sclk_valid_edge_failing = 1U, /*!< SCLK failling edge */ } sgtl_sclk_edge_t; /*! @brief Audio format configuration. */ -typedef struct _sgtl_audio_format -{ +typedef struct _sgtl_audio_format { uint32_t mclk_hz; /*!< master clock */ uint32_t sample_rate; /*!< Sample rate */ uint32_t bit_width; /*!< Bit width */ @@ -836,16 +828,14 @@ typedef struct _sgtl_audio_format } sgtl_audio_format_t; /*! @brief Initailize structure of sgtl5000 */ -typedef struct _sgtl_config -{ +typedef struct _sgtl_config { sgtl_route_t route; /*!< Audio data route.*/ sgtl_protocol_t bus; /*!< Audio transfer protocol */ bool master; /*!< Master or slave. True means master, false means slave. */ sgtl_audio_format_t format; /*!< audio format */ } sgtl_config_t; -typedef struct -{ +typedef struct { I2C_Type *ptr;; /*!< sgtl I2C pointer */ uint8_t slave_address; /*!< code device slave address */ } sgtl_context_t; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c new file mode 100644 index 0000000000..d4a7e86037 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c @@ -0,0 +1,540 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_wm8960.h" + +#ifndef HPM_WM8960_MCLK_TOLERANCE +#define HPM_WM8960_MCLK_TOLERANCE (4U) +#endif + +/* wm8960 register default value */ +static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +/* store reg value */ +static uint16_t wm8960_reg_val[WM8960_REG_NUM]; + +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) +{ + assert(control != NULL); + assert(config != NULL); + + hpm_stat_t stat = status_success; + + (void)memcpy(wm8960_reg_val, wm8960_default_reg_val, sizeof(wm8960_default_reg_val)); + + /* Reset */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RESET, 0x00)); + + /* Power on input modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0xFE)); + /* Power on output modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x1F8)); + /* Power on PGA and mixer */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + + /* ADC and DAC uses same clock */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_IFACE2, 0x40)); + + /* set data protocol */ + HPM_CHECK_RET(wm8960_set_protocol(control, config->bus)); + + /* set wm8960 as slave */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); + + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); + + /* ADC volume, 8dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3)); + + /* Digital DAC volume, 0dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, 0x1E0)); + + /* Headphone volume, LOUT1 and ROUT1, 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, 0x17F)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, 0x17F)); + + /* speaker volume 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, 0x1ff)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, 0x1ff)); + /* enable class D output */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xf7)); + + /* Unmute DAC. */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_DACCTL1, 0x0000)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + + HPM_CHECK_RET(wm8960_set_data_format(control, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width)); + + /* set data route */ + HPM_CHECK_RET(wm8960_set_data_route(control, config)); + + return status_success; +} + +hpm_stat_t wm8960_deinit(wm8960_control_t *control) +{ + hpm_stat_t stat = status_success; + + /* power off all modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x00U)); + + return status_success; +} + +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol) +{ + return wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, (uint16_t)protocol); +} + +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable) +{ + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCR_SHIFT))); + break; + case wm8960_module_dac: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACL_MASK, + ((uint16_t)enable << WM8960_POWER2_DACL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACR_MASK, + ((uint16_t)enable << WM8960_POWER2_DACR_SHIFT))); + break; + case wm8960_module_vref: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_VREF_MASK, + ((uint16_t)enable << WM8960_POWER1_VREF_SHIFT))); + break; + case wm8960_module_ana_in: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINL_MASK, + ((uint16_t)enable << WM8960_POWER1_AINL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINR_MASK, + ((uint16_t)enable << WM8960_POWER1_AINR_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_LMIC_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_RMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_RMIC_SHIFT))); + break; + case wm8960_module_lineout: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_LOUT1_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_ROUT1_SHIFT))); + break; + case wm8960_module_micbais: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_MICB_MASK, + ((uint16_t)enable << WM8960_POWER1_MICB_SHIFT))); + break; + case wm8960_module_speaker: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKR_SHIFT))); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xF7)); + break; + case wm8960_module_output_mixer: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LOMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_LOMIX_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_ROMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_ROMIX_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config) +{ + hpm_stat_t stat = status_success; + + /* select left input */ + HPM_CHECK_RET(wm8960_set_left_input(control, config->left_input)); + /* select right input */ + HPM_CHECK_RET(wm8960_set_right_input(control, config->right_input)); + /* select source to output mixer */ + HPM_CHECK_RET(wm8960_config_input_to_output_mixer(control, config->play_source)); + + switch (config->route) { + case wm8960_route_bypass: + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback: + /* I2S_IN-> DAC-> HP */ + /* Set power for DAC */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x0C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback_and_record: + /* Set power */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_record: + /* ANA_IN->ADC->I2S_OUT */ + /* Power up ADC and AIN */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x30)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + /* Update volume */ + vol = (uint16_t)(0x100U | volume); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + } + break; + case wm8960_module_dac: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + } + break; + case wm8960_module_headphone: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + } + break; + case wm8960_module_ana_in: + if (volume > 0x3FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + } + break; + case wm8960_module_speaker: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + } + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) +{ + hpm_stat_t stat = status_success; + uint32_t divider = 0; + uint16_t val = 0; + + /* Compute sample rate divider and SYSCLK Pre-divider, dac and adc are the same sample rate */ + divider = sysclk / sample_rate; + + if (divider > 6 * 512 * HPM_WM8960_MCLK_TOLERANCE / 100 + 6 * 512) { + divider = divider / 2; /* SYSCLK Pre-divider */ + val |= WM8960_CLOCK1_SYSCLKDIV_SET(2U); + } + + if (abs(divider - 256) <= 256 * HPM_WM8960_MCLK_TOLERANCE) { + divider = 256; + } else if (abs(divider - 256 * 1.5) <= 256 * 1.5 * HPM_WM8960_MCLK_TOLERANCE) { + divider = 256 * 1.5; + val |= ((1 << WM8960_CLOCK1_ADCDIV_SHIFT) | (1 << WM8960_CLOCK1_DACDIV_SHIFT)); + } else if (abs(divider - 256 * 2) <= 256 * 2 * HPM_WM8960_MCLK_TOLERANCE) { + divider = 256 * 2; + val |= ((2 << WM8960_CLOCK1_ADCDIV_SHIFT) | (2 << WM8960_CLOCK1_DACDIV_SHIFT)); + } else if (abs(divider - 256 * 3) <= 256 * 3 * HPM_WM8960_MCLK_TOLERANCE) { + divider = 256 * 3; + val |= ((3 << WM8960_CLOCK1_ADCDIV_SHIFT) | (3 << WM8960_CLOCK1_DACDIV_SHIFT)); + } else if (abs(divider - 256 * 4) <= 256 * 4 * HPM_WM8960_MCLK_TOLERANCE) { + divider = 256 * 4; + val |= ((4 << WM8960_CLOCK1_ADCDIV_SHIFT) | (4 << WM8960_CLOCK1_DACDIV_SHIFT)); + } else if (abs(divider - 256 * 5.5) <= 256 * 5.5 * HPM_WM8960_MCLK_TOLERANCE) { + divider = 256 * 5.5; + val |= ((5 << WM8960_CLOCK1_ADCDIV_SHIFT) | (5 << WM8960_CLOCK1_DACDIV_SHIFT)); + } else if (abs(divider - 256 * 6) <= 256 * 6 * HPM_WM8960_MCLK_TOLERANCE) { + divider = 256 * 6; + val |= ((6 << WM8960_CLOCK1_ADCDIV_SHIFT) | (6 << WM8960_CLOCK1_DACDIV_SHIFT)); + } else { + return status_invalid_argument; + } + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); + + /* set sample bit */ + switch (bits) { + case 16: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(0U)); + break; + case 20: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(1U)); + break; + case 24: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(2U)); + break; + case 32: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(3U)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source) +{ + hpm_stat_t stat = status_success; + + if ((play_source & (uint32_t)wm8960_play_source_input_mixer) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_dac) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x100U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x100U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_input3) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x80U)); + } + + return stat; +} + + +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val) +{ + uint8_t buff[2]; + /* The first 7 bits (B15 to B9) are address bits that select which control register */ + /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ + buff[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); + buff[1] = (uint8_t)(val & 0xFFU); + + /* record reg val */ + wm8960_reg_val[reg] = val; + + return i2c_master_write(control->ptr, control->slave_address, buff, 2U); +} + +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val) +{ + if (reg >= WM8960_REG_NUM) { + return status_invalid_argument; + } + *val = wm8960_reg_val[reg]; + + return status_success; +} + +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val) +{ + hpm_stat_t stat = 0; + uint16_t reg_val; + + /* Read the register value out */ + stat = wm8960_read_reg(reg, ®_val); + if (stat != status_success) { + return status_fail; + } + + /* Modify the value */ + reg_val &= (uint16_t)~mask; + reg_val |= val; + + /* Write the data to register */ + stat = wm8960_write_reg(control, reg, reg_val); + if (stat != status_success) { + return status_fail; + } + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h new file mode 100644 index 0000000000..10d4be18e2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_SGTL5000_H_ +#define _HPM_SGTL5000_H_ + +#include "hpm_i2c_drv.h" +#include "hpm_common.h" +#include "hpm_wm8960_regs.h" + +#define WM8960_I2C_ADDR 0x1A + +typedef enum wm8960_module { + wm8960_module_adc = 0, /* ADC module in WM8960 */ + wm8960_module_dac = 1, /* DAC module in WM8960 */ + wm8960_module_vref = 2, /* VREF module */ + wm8960_module_headphone = 3, /* Headphone */ + wm8960_module_micbais = 4, /* Mic bias */ + wm8960_module_ana_in = 6, /* Analog in PGA */ + wm8960_module_lineout = 7, /* Line out module */ + wm8960_module_speaker = 8, /* Speaker module */ + wm8960_module_output_mixer = 9, /* Output mixer */ +} wm8960_module_t; + +/* wm8960 play source for output mixer */ +typedef enum wm8960_play_source { + wm8960_play_source_input_mixer = 1, /* Input Boost Mixer to Output Mixer */ + wm8960_play_source_input3 = 2, /* L/RINPUT3 to Output Mixer */ + wm8960_play_source_dac = 4, /* DAC to Output Mixer */ +} wm8960_play_source_t; + +/* WM8960 data route */ +typedef enum wm8960_route { + wm8960_route_bypass = 0, /* ANA_IN->Headphone. */ + wm8960_route_playback = 1, /* I2SIN->DAC->Headphone. */ + wm8960_route_playback_and_record = 2, /* I2SIN->DAC->Headphone, ANA_IN->ADC->I2SOUT. */ + wm8960_route_record = 5 /* ANA_IN->ADC->I2SOUT. */ +} wm8960_route_t; + +/* The audio data transfer protocol choice */ +typedef enum wm8960_protocol { + wm8960_bus_i2s = 2, /* I2S type */ + wm8960_bus_left_justified = 1, /* Left justified mode */ + wm8960_bus_right_justified = 0, /* Right justified mode */ + wm8960_bus_pcma = 3, /* PCM A mode */ + wm8960_bus_pcmb = 3 | (1 << 4) /* PCM B mode */ +} wm8960_protocol_t; + +/* wm8960 input source */ +typedef enum wm8960_input { + wm8960_input_closed = 0, /* Input device is closed */ + wm8960_input_single_ended_mic = 1, /* Input as single ended mic, only use L/RINPUT1 */ + wm8960_input_differential_mic_input2 = 2, /* Input as differential mic, use L/RINPUT1 and L/RINPUT2 */ + wm8960_input_differential_mic_input3 = 3, /* Input as differential mic, use L/RINPUT1 and L/RINPUT3*/ + wm8960_input_line_input2 = 4, /* Input as line input, only use L/RINPUT2 */ + wm8960_input_line_input3 = 5 /* Input as line input, only use L/RINPUT3 */ +} wm8960_input_t; + +/* wm8960 audio format */ +typedef struct wm8960_audio_format { + uint32_t mclk_hz; /* master clock frequency */ + uint32_t sample_rate; /* sample rate */ + uint32_t bit_width; /* bit width */ +} wm8960_audio_format_t; + +/* configure structure of WM8960 */ +typedef struct wm8960_config { + wm8960_route_t route; /* Audio data route.*/ + wm8960_protocol_t bus; /* Audio transfer protocol */ + bool enable_speaker; /* True means enable class D speaker as output, false means no */ + wm8960_input_t left_input; /* Left input source for WM8960 */ + wm8960_input_t right_input; /* Right input source for wm8960 */ + wm8960_play_source_t play_source; /* play source */ + wm8960_audio_format_t format; /* Audio format */ +} wm8960_config_t; + +typedef struct { + I2C_Type *ptr;; /* I2C bus */ + uint8_t slave_address; /* code device address */ +} wm8960_control_t; + + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief WM8960 initialize function. + * + * @param control WM8960 control structure. + * @param config WM8960 configuration structure. + */ +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Deinit the WM8960 codec. + * + * This function close all modules in WM8960 to save power. + * + * @param control WM8960 control structure pointer. + */ +hpm_stat_t wm8960_deinit(wm8960_control_t *control); + +/** + * @brief Set audio data route in WM8960. + * + * This function would set the data route according to route. + * + * @param control WM8960 control structure. + * @param config Audio configure structure in WM8960. + */ +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Set left audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set right audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set the audio transfer protocol. + * + * @param control WM8960 control structure. + * @param protocol Audio data transfer protocol. + */ +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol); + +/** + * @brief Set the volume of different modules in WM8960. + * + * This function would set the volume of WM8960 modules. Uses need to appoint the module. + * The function assume that left channel and right channel has the same volume. + * + * Module:wm8960_module_adc, volume range value: 0 is mute, 1-255 is -97db to 30db + * Module:wm8960_module_dac, volume range value: 0 is mute, 1-255 is -127db to 0db + * Module:wm8960_module_headphone, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * Module:wm8960_module_ana_in, volume range value: 0 - 0x3F is -17.25db to 30db + * Module:wm8960_module_speaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * + * + * @param control WM8960 control structure. + * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. + * @param volume Volume value need to be set. + */ +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume); + +/** + * @brief Enable/disable expected module. + * + * @param control WM8960 control structure. + * @param module Module expected to enable. + * @param enable Enable or disable moudles. + */ +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable); + +/** + * @brief SET the WM8960 play source. + * + * @param control WM8960 control structure. + * @param play_source play source + * + * @return kStatus_WM8904_Success if successful, different code otherwise.. + */ +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source); + +/** + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * + * @param control WM8960 control structure pointer. + * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. + * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); + + +/** + * @brief Write register to WM8960 using I2C. + * + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val); + +/** + * @brief Read register from WM8960 using I2C. + * @param reg The register address in WM8960. + * @param val Value written to. + */ +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val); + +/** + * @brief Modify some bits in the register using I2C. + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val); + + +#endif /* _HPM_SGTL5000_H_ */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960_regs.h new file mode 100644 index 0000000000..a484f2937c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960_regs.h @@ -0,0 +1,2139 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_REG_H_ +#define _HPM_WM8960_REG_H_ + +/* WM8960 register number */ +#define WM8960_REG_NUM 56U + +/* Define the register address of WM8960 */ +#define WM8960_LINVOL 0x0U /* Left Input Volume */ +#define WM8960_RINVOL 0x1U /* Right Input Volume */ +#define WM8960_LOUT1 0x2U /* LOUT1 Volume */ +#define WM8960_ROUT1 0x3U /* ROUT1 Volume */ +#define WM8960_CLOCK1 0x4U /* Clocking(1) */ +#define WM8960_DACCTL1 0x5U /* ADC and DAC Control (1) */ +#define WM8960_DACCTL2 0x6U /* ADC and DAC Control (2) */ +#define WM8960_IFACE1 0x7U /* Audio Interface */ +#define WM8960_CLOCK2 0x8U /* Clocking(2) */ +#define WM8960_IFACE2 0x9U /* Audio Interface */ +#define WM8960_LDAC 0xaU /* Left DAC */ +#define WM8960_RDAC 0xbU /* Right DAC Volume */ +#define WM8960_RESET 0xfU /* RESET */ +#define WM8960_3D 0x10U /* 3D Control */ +#define WM8960_ALC1 0x11U /* ALC (1) */ +#define WM8960_ALC2 0x12U /* ALC (2) */ +#define WM8960_ALC3 0x13U /* ALC (3) */ +#define WM8960_NOISEG 0x14U /* Noise Gate */ +#define WM8960_LADC 0x15U /* Left ADC Volume */ +#define WM8960_RADC 0x16U /* Right ADC Volume */ +#define WM8960_ADDCTL1 0x17U /* Additional Control (1) */ +#define WM8960_ADDCTL2 0x18U /* Additional Control (2) */ +#define WM8960_POWER1 0x19U /* Power Mgmt (1) */ +#define WM8960_POWER2 0x1aU /* Power Mgmt (2) */ +#define WM8960_ADDCTL3 0x1bU /* Additional Control (3) */ +#define WM8960_APOP1 0x1cU /* Anti-Pop 1 */ +#define WM8960_APOP2 0x1dU /* Anti-pop 2 */ +#define WM8960_LINPATH 0x20U /* ADCL Signal Path */ +#define WM8960_RINPATH 0x21U /* ADCR Signal Path */ +#define WM8960_LOUTMIX 0x22U /* Left Out Mix */ +#define WM8960_ROUTMIX 0x25U /* Right Out Mix */ +#define WM8960_MONOMIX1 0x26U /* Mono Out Mix (1) */ +#define WM8960_MONOMIX2 0x27U /* Mono Out Mix (2) */ +#define WM8960_LOUT2 0x28U /* Left Speaker Volume */ +#define WM8960_ROUT2 0x29U /* Right Speaker Volume */ +#define WM8960_MONO 0x2aU /* OUT3 Volume */ +#define WM8960_INBMIX1 0x2bU /* Left Input Boost Mixer */ +#define WM8960_INBMIX2 0x2cU /* Right Input Boost Mixer */ +#define WM8960_BYPASS1 0x2dU /* Left Bypass */ +#define WM8960_BYPASS2 0x2eU /* Right Bypass */ +#define WM8960_POWER3 0x2fU /* Power Mgmt (3) */ +#define WM8960_ADDCTL4 0x30U /* Additional Control (4) */ +#define WM8960_CLASSD1 0x31U /* Class D Control (1) */ +#define WM8960_CLASSD3 0x33U /* Class D Control (2) */ +#define WM8960_PLL1 0x34U /* PLL (1) */ +#define WM8960_PLL2 0x35U /* PLL (2) */ +#define WM8960_PLL3 0x36U /* PLL (3) */ +#define WM8960_PLL4 0x37U /* PLL (4) */ + +/* Bitfield definition for register: LINVO */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_LINVO_IPVU_MASK (0x100U) +#define WM8960_LINVO_IPVU_SHIFT (8U) +#define WM8960_LINVO_IPVU_SET(x) (((uint16_t)(x) << WM8960_LINVO_IPVU_SHIFT) & WM8960_LINVO_IPVU_MASK) +#define WM8960_LINVO_IPVU_GET(x) (((uint16_t)(x) & WM8960_LINVO_IPVU_MASK) >> WM8960_LINVO_IPVU_SHIFT) + +/* + * LINMUTE (RW) + * + * Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. + */ +#define WM8960_LINVO_LINMUTE_MASK (0x80U) +#define WM8960_LINVO_LINMUTE_SHIFT (7U) +#define WM8960_LINVO_LINMUTE_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINMUTE_SHIFT) & WM8960_LINVO_LINMUTE_MASK) +#define WM8960_LINVO_LINMUTE_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINMUTE_MASK) >> WM8960_LINVO_LINMUTE_SHIFT) + +/* + * LIZC (RW) + * + * Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately + */ +#define WM8960_LINVO_LIZC_MASK (0x40U) +#define WM8960_LINVO_LIZC_SHIFT (6U) +#define WM8960_LINVO_LIZC_SET(x) (((uint16_t)(x) << WM8960_LINVO_LIZC_SHIFT) & WM8960_LINVO_LIZC_MASK) +#define WM8960_LINVO_LIZC_GET(x) (((uint16_t)(x) & WM8960_LINVO_LIZC_MASK) >> WM8960_LINVO_LIZC_SHIFT) + +/* + * LINVOL (RW) + * + * Left Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_LINVO_LINVOL_MASK (0x3FU) +#define WM8960_LINVO_LINVOL_SHIFT (0U) +#define WM8960_LINVO_LINVOL_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINVOL_SHIFT) & WM8960_LINVO_LINVOL_MASK) +#define WM8960_LINVO_LINVOL_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINVOL_MASK) >> WM8960_LINVO_LINVOL_SHIFT) + +/* Bitfield definition for register: RINVOL */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right + * input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_RINVOL_IPVU_MASK (0x100U) +#define WM8960_RINVOL_IPVU_SHIFT (8U) +#define WM8960_RINVOL_IPVU_SET(x) (((uint16_t)(x) << WM8960_RINVOL_IPVU_SHIFT) & WM8960_RINVOL_IPVU_MASK) +#define WM8960_RINVOL_IPVU_GET(x) (((uint16_t)(x) & WM8960_RINVOL_IPVU_MASK) >> WM8960_RINVOL_IPVU_SHIFT) + +/* + * RINMUTE (RW) + * + * Right Input PGA Analogue Mute + * 1 = Enable Mute + * 0 = Disable Mute + * Note: IPVU must be set to un-mute. + */ +#define WM8960_RINVOL_RINMUTE_MASK (0x80U) +#define WM8960_RINVOL_RINMUTE_SHIFT (7U) +#define WM8960_RINVOL_RINMUTE_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINMUTE_SHIFT) & WM8960_RINVOL_RINMUTE_MASK) +#define WM8960_RINVOL_RINMUTE_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINMUTE_MASK) >> WM8960_RINVOL_RINMUTE_SHIFT) + +/* + * RIZC (RW) + * + * Right Input PGA Zero Cross Detector + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_RINVOL_RIZC_MASK (0x40U) +#define WM8960_RINVOL_RIZC_SHIFT (6U) +#define WM8960_RINVOL_RIZC_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RIZC_SHIFT) & WM8960_RINVOL_RIZC_MASK) +#define WM8960_RINVOL_RIZC_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RIZC_MASK) >> WM8960_RINVOL_RIZC_SHIFT) + +/* + * RINVOL (RW) + * + * Right Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_RINVOL_RINVOL_MASK (0x3FU) +#define WM8960_RINVOL_RINVOL_SHIFT (0U) +#define WM8960_RINVOL_RINVOL_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINVOL_SHIFT) & WM8960_RINVOL_RINVOL_MASK) +#define WM8960_RINVOL_RINVOL_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINVOL_MASK) >> WM8960_RINVOL_RINVOL_SHIFT) + +/* Bitfield definition for register: LOUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_LOUT1_OUT1VU_MASK (0x100U) +#define WM8960_LOUT1_OUT1VU_SHIFT (8U) +#define WM8960_LOUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_LOUT1_OUT1VU_SHIFT) & WM8960_LOUT1_OUT1VU_MASK) +#define WM8960_LOUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_LOUT1_OUT1VU_MASK) >> WM8960_LOUT1_OUT1VU_SHIFT) + +/* + * LO1ZC (RW) + * + * Left Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_LOUT1_LO1ZC_MASK (0x80U) +#define WM8960_LOUT1_LO1ZC_SHIFT (7U) +#define WM8960_LOUT1_LO1ZC_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LO1ZC_SHIFT) & WM8960_LOUT1_LO1ZC_MASK) +#define WM8960_LOUT1_LO1ZC_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LO1ZC_MASK) >> WM8960_LOUT1_LO1ZC_SHIFT) + +/* + * LOUT1VOL (RW) + * + * LOUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT1_LOUT1VOL_MASK (0x7FU) +#define WM8960_LOUT1_LOUT1VOL_SHIFT (0U) +#define WM8960_LOUT1_LOUT1VOL_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LOUT1VOL_SHIFT) & WM8960_LOUT1_LOUT1VOL_MASK) +#define WM8960_LOUT1_LOUT1VOL_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LOUT1VOL_MASK) >> WM8960_LOUT1_LOUT1VOL_SHIFT) + +/* Bitfield definition for register: ROUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_ROUT1_OUT1VU_MASK (0x100U) +#define WM8960_ROUT1_OUT1VU_SHIFT (8U) +#define WM8960_ROUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_ROUT1_OUT1VU_SHIFT) & WM8960_ROUT1_OUT1VU_MASK) +#define WM8960_ROUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_ROUT1_OUT1VU_MASK) >> WM8960_ROUT1_OUT1VU_SHIFT) + +/* + * RO1ZC (RW) + * + * Right Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_ROUT1_RO1ZC_MASK (0x80U) +#define WM8960_ROUT1_RO1ZC_SHIFT (7U) +#define WM8960_ROUT1_RO1ZC_SET(x) (((uint16_t)(x) << WM8960_ROUT1_RO1ZC_SHIFT) & WM8960_ROUT1_RO1ZC_MASK) +#define WM8960_ROUT1_RO1ZC_GET(x) (((uint16_t)(x) & WM8960_ROUT1_RO1ZC_MASK) >> WM8960_ROUT1_RO1ZC_SHIFT) + +/* + * ROUT1VOL (RW) + * + * ROUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT1_ROUT1VOL_MASK (0x7FU) +#define WM8960_ROUT1_ROUT1VOL_SHIFT (0U) +#define WM8960_ROUT1_ROUT1VOL_SET(x) (((uint16_t)(x) << WM8960_ROUT1_ROUT1VOL_SHIFT) & WM8960_ROUT1_ROUT1VOL_MASK) +#define WM8960_ROUT1_ROUT1VOL_GET(x) (((uint16_t)(x) & WM8960_ROUT1_ROUT1VOL_MASK) >> WM8960_ROUT1_ROUT1VOL_SHIFT) + +/* Bitfield definition for register: CLOCK1 */ +/* + * ADCDIV (RW) + * + * ADC Sample rate divider (Also determines + * ADCLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_ADCDIV_MASK (0x1C0U) +#define WM8960_CLOCK1_ADCDIV_SHIFT (6U) +#define WM8960_CLOCK1_ADCDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_ADCDIV_SHIFT) & WM8960_CLOCK1_ADCDIV_MASK) +#define WM8960_CLOCK1_ADCDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_ADCDIV_MASK) >> WM8960_CLOCK1_ADCDIV_SHIFT) + +/* + * DACDIV (RW) + * + * DAC Sample rate divider (Also determines + * DACLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_DACDIV_MASK (0x38U) +#define WM8960_CLOCK1_DACDIV_SHIFT (3U) +#define WM8960_CLOCK1_DACDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_DACDIV_SHIFT) & WM8960_CLOCK1_DACDIV_MASK) +#define WM8960_CLOCK1_DACDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_DACDIV_MASK) >> WM8960_CLOCK1_DACDIV_SHIFT) + +/* + * SYSCLKDIV (RW) + * + * SYSCLK Pre-divider. Clock source (MCLK or + * PLL output) will be divided by this value to + * generate SYSCLK. + * 00 = Divide SYSCLK by 1 + * 01 = Reserved + * 10 = Divide SYSCLK by 2 + * 11 = Reserved + */ +#define WM8960_CLOCK1_SYSCLKDIV_MASK (0x6U) +#define WM8960_CLOCK1_SYSCLKDIV_SHIFT (1U) +#define WM8960_CLOCK1_SYSCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_SYSCLKDIV_SHIFT) & WM8960_CLOCK1_SYSCLKDIV_MASK) +#define WM8960_CLOCK1_SYSCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_SYSCLKDIV_MASK) >> WM8960_CLOCK1_SYSCLKDIV_SHIFT) + +/* + * CLKSEL (RW) + * + * SYSCLK Selection + * 0 = SYSCLK derived from MCLK + * 1 = SYSCLK derived from PLL output + */ +#define WM8960_CLOCK1_CLKSEL_MASK (0x1U) +#define WM8960_CLOCK1_CLKSEL_SHIFT (0U) +#define WM8960_CLOCK1_CLKSEL_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_CLKSEL_SHIFT) & WM8960_CLOCK1_CLKSEL_MASK) +#define WM8960_CLOCK1_CLKSEL_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_CLKSEL_MASK) >> WM8960_CLOCK1_CLKSEL_SHIFT) + +/* Bitfield definition for register: DACCTL1 */ +/* + * DACDIV2 (RW) + * + * DAC 6dB Attenuate Enable + * 0 = Disabled (0dB) + * 1 = -6dB Enabled + */ +#define WM8960_DACCTL1_DACDIV2_MASK (0x80U) +#define WM8960_DACCTL1_DACDIV2_SHIFT (7U) +#define WM8960_DACCTL1_DACDIV2_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACDIV2_SHIFT) & WM8960_DACCTL1_DACDIV2_MASK) +#define WM8960_DACCTL1_DACDIV2_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACDIV2_MASK) >> WM8960_DACCTL1_DACDIV2_SHIFT) + +/* + * ADCPOL (RW) + * + * ADC polarity control: + * 00 = Polarity not inverted + * 01 = ADC L inverted + * 10 = ADC R inverted + * 11 = ADC L and R inverted + */ +#define WM8960_DACCTL1_ADCPOL_MASK (0x60U) +#define WM8960_DACCTL1_ADCPOL_SHIFT (5U) +#define WM8960_DACCTL1_ADCPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCPOL_SHIFT) & WM8960_DACCTL1_ADCPOL_MASK) +#define WM8960_DACCTL1_ADCPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCPOL_MASK) >> WM8960_DACCTL1_ADCPOL_SHIFT) + +/* + * DACMU (RW) + * + * DAC Digital Soft Mute + * 1 = Mute + * 0 = No mute (signal active) + */ +#define WM8960_DACCTL1_DACMU_MASK (0x8U) +#define WM8960_DACCTL1_DACMU_SHIFT (3U) +#define WM8960_DACCTL1_DACMU_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACMU_SHIFT) & WM8960_DACCTL1_DACMU_MASK) +#define WM8960_DACCTL1_DACMU_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACMU_MASK) >> WM8960_DACCTL1_DACMU_SHIFT) + +/* + * DEEMPH (RW) + * + * De-emphasis Control + * 11 = 48kHz sample rate + * 10 = 44.1kHz sample rate + * 01 = 32kHz sample rate + * 00 = No de-emphasis + */ +#define WM8960_DACCTL1_DEEMPH_MASK (0x6U) +#define WM8960_DACCTL1_DEEMPH_SHIFT (1U) +#define WM8960_DACCTL1_DEEMPH_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DEEMPH_SHIFT) & WM8960_DACCTL1_DEEMPH_MASK) +#define WM8960_DACCTL1_DEEMPH_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DEEMPH_MASK) >> WM8960_DACCTL1_DEEMPH_SHIFT) + +/* + * ADCHPD (RW) + * + * ADC High Pass Filter Disable + * 0 = Enable high pass filter on left and right channels + * 1 = Disable high pass filter on left and right channels + */ +#define WM8960_DACCTL1_ADCHPD_MASK (0x1U) +#define WM8960_DACCTL1_ADCHPD_SHIFT (0U) +#define WM8960_DACCTL1_ADCHPD_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCHPD_SHIFT) & WM8960_DACCTL1_ADCHPD_MASK) +#define WM8960_DACCTL1_ADCHPD_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCHPD_MASK) >> WM8960_DACCTL1_ADCHPD_SHIFT) + +/* Bitfield definition for register: DACCTL2 */ +/* + * DACPOL (RW) + * + * DAC polarity control: + * 00 = Polarity not inverted + * 01 = DAC L inverted + * 10 = DAC R inverted + * 11 = DAC L and R inverted + */ +#define WM8960_DACCTL2_DACPOL_MASK (0x60U) +#define WM8960_DACCTL2_DACPOL_SHIFT (5U) +#define WM8960_DACCTL2_DACPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACPOL_SHIFT) & WM8960_DACCTL2_DACPOL_MASK) +#define WM8960_DACCTL2_DACPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACPOL_MASK) >> WM8960_DACCTL2_DACPOL_SHIFT) + +/* + * DACSMM (RW) + * + * DAC Soft Mute Mode + * 0 = Disabling soft-mute (DACMU=0) will cause + * the volume to change immediately to the + * LDACVOL / RDACVOL settings + * 1 = Disabling soft-mute (DACMU=0) will cause + * the volume to ramp up gradually to the + * LDACVOL / RDACVOL settings + */ +#define WM8960_DACCTL2_DACSMM_MASK (0x8U) +#define WM8960_DACCTL2_DACSMM_SHIFT (3U) +#define WM8960_DACCTL2_DACSMM_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSMM_SHIFT) & WM8960_DACCTL2_DACSMM_MASK) +#define WM8960_DACCTL2_DACSMM_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSMM_MASK) >> WM8960_DACCTL2_DACSMM_SHIFT) + +/* + * DACMR (RW) + * + * DAC Soft Mute Ramp Rate + * 0 = Fast ramp (24kHz at fs=48k, providing + * maximum delay of 10.7ms) + * 1 = Slow ramp (1.5kHz at fs=48k, providing + * maximum delay of 171ms) + */ +#define WM8960_DACCTL2_DACMR_MASK (0x4U) +#define WM8960_DACCTL2_DACMR_SHIFT (2U) +#define WM8960_DACCTL2_DACMR_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACMR_SHIFT) & WM8960_DACCTL2_DACMR_MASK) +#define WM8960_DACCTL2_DACMR_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACMR_MASK) >> WM8960_DACCTL2_DACMR_SHIFT) + +/* + * DACSLOPE (RW) + * + * Selects DAC filter characteristics + * 0 = Normal mode + * 1 = Sloping stopband + */ +#define WM8960_DACCTL2_DACSLOPE_MASK (0x2U) +#define WM8960_DACCTL2_DACSLOPE_SHIFT (1U) +#define WM8960_DACCTL2_DACSLOPE_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSLOPE_SHIFT) & WM8960_DACCTL2_DACSLOPE_MASK) +#define WM8960_DACCTL2_DACSLOPE_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSLOPE_MASK) >> WM8960_DACCTL2_DACSLOPE_SHIFT) + +/* Bitfield definition for register: IFACE1 */ +/* + * ALRSWAP (RW) + * + * Left/Right ADC Channel Swap + * 1 = Swap left and right ADC data in audio + * interface + * 0 = Output left and right data as normal + */ +#define WM8960_IFACE1_ALRSWAP_MASK (0x100U) +#define WM8960_IFACE1_ALRSWAP_SHIFT (8U) +#define WM8960_IFACE1_ALRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) +#define WM8960_IFACE1_ALRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_ALRSWAP_MASK) >> WM8960_IFACE1_ALRSWAP_SHIFT) + +/* + * BCLKINV (RW) + * + * BCLK invert bit (for master and slave modes) + * 0 = BCLK not inverted + * 1 = BCLK inverted + */ +#define WM8960_IFACE1_BCLKINV_MASK (0x80U) +#define WM8960_IFACE1_BCLKINV_SHIFT (7U) +#define WM8960_IFACE1_BCLKINV_SET(x) (((uint16_t)(x) << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) +#define WM8960_IFACE1_BCLKINV_GET(x) (((uint16_t)(x) & WM8960_IFACE1_BCLKINV_MASK) >> WM8960_IFACE1_BCLKINV_SHIFT) + +/* + * MS (RW) + * + * Master / Slave Mode Control + * 0 = Enable slave mode + * 1 = Enable master mode + */ +#define WM8960_IFACE1_MS_MASK (0x40U) +#define WM8960_IFACE1_MS_SHIFT (6U) +#define WM8960_IFACE1_MS_SET(x) (((uint16_t)(x) << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) +#define WM8960_IFACE1_MS_GET(x) (((uint16_t)(x) & WM8960_IFACE1_MS_MASK) >> WM8960_IFACE1_MS_SHIFT) + +/* + * DLRSWAP (RW) + * + * Left/Right DAC Channel Swap + * 0 = Output left and right data as normal + * 1 = Swap left and right DAC data in audio interface + */ +#define WM8960_IFACE1_DLRSWAP_MASK (0x20U) +#define WM8960_IFACE1_DLRSWAP_SHIFT (5U) +#define WM8960_IFACE1_DLRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) +#define WM8960_IFACE1_DLRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_DLRSWAP_MASK) >> WM8960_IFACE1_DLRSWAP_SHIFT) + +/* + * LRP (RW) + * + * Right, left and I2S modes – LRCLK polarity + * 0 = normal LRCLK polarity + * 1 = invert LRCLK polarity + * DSP Mode – mode A/B select + * 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) + * 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) + */ +#define WM8960_IFACE1_LRP_MASK (0x10U) +#define WM8960_IFACE1_LRP_SHIFT (4U) +#define WM8960_IFACE1_LRP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) +#define WM8960_IFACE1_LRP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_LRP_MASK) >> WM8960_IFACE1_LRP_SHIFT) + +/* + * WL (RW) + * + * Audio Data Word Length + * 00 = 16 bits + * 01 = 20 bits + * 10 = 24 bits + * 11 = 32 bits (see Note) + */ +#define WM8960_IFACE1_WL_MASK (0xCU) +#define WM8960_IFACE1_WL_SHIFT (2U) +#define WM8960_IFACE1_WL_SET(x) (((uint16_t)(x) << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) +#define WM8960_IFACE1_WL_GET(x) (((uint16_t)(x) & WM8960_IFACE1_WL_MASK) >> WM8960_IFACE1_WL_SHIFT) + +/* + * FORMAT (RW) + * + * 00 = Right justified + * 01 = Left justified + * 10 = I2S Format + * 11 = DSP Mode + */ +#define WM8960_IFACE1_FORMAT_MASK (0x3U) +#define WM8960_IFACE1_FORMAT_SHIFT (0U) +#define WM8960_IFACE1_FORMAT_SET(x) (((uint16_t)(x) << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) +#define WM8960_IFACE1_FORMAT_GET(x) (((uint16_t)(x) & WM8960_IFACE1_FORMAT_MASK) >> WM8960_IFACE1_FORMAT_SHIFT) + +/* Bitfield definition for register: CLOCK2 */ +/* + * DCLKDIV (RW) + * + * Class D switching clock divider. + * 000 = SYSCLK / 1.5 (Not recommended) + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 6 + * 101 = SYSCLK / 8 + * 110 = SYSCLK / 12 + * 111 = SYSCLK / 16 + */ +#define WM8960_CLOCK2_DCLKDIV_MASK (0x1C0U) +#define WM8960_CLOCK2_DCLKDIV_SHIFT (6U) +#define WM8960_CLOCK2_DCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_DCLKDIV_SHIFT) & WM8960_CLOCK2_DCLKDIV_MASK) +#define WM8960_CLOCK2_DCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_DCLKDIV_MASK) >> WM8960_CLOCK2_DCLKDIV_SHIFT) + +/* + * BCLKDIV (RW) + * + * BCLK Frequency (Master Mode) + * 0000 = SYSCLK + * 0001 = SYSCLK / 1.5 + * 0010 = SYSCLK / 2 + * 0011 = SYSCLK / 3 + * 0100 = SYSCLK / 4 + * 0101 = SYSCLK / 5.5 + * 0110 = SYSCLK / 6 + * 0111 = SYSCLK / 8 + * 1000 = SYSCLK / 11 + * 1001 = SYSCLK / 12 + * 1010 = SYSCLK / 16 + * 1011 = SYSCLK / 22 + * 1100 = SYSCLK / 24 + * 1101 to 1111 = SYSCLK / 32 + */ +#define WM8960_CLOCK2_BCLKDIV_MASK (0xFU) +#define WM8960_CLOCK2_BCLKDIV_SHIFT (0U) +#define WM8960_CLOCK2_BCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_BCLKDIV_SHIFT) & WM8960_CLOCK2_BCLKDIV_MASK) +#define WM8960_CLOCK2_BCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_BCLKDIV_MASK) >> WM8960_CLOCK2_BCLKDIV_SHIFT) + +/* Bitfield definition for register: IFACE2 */ +/* + * ALRCGPIO (RW) + * + * ADCLRC/GPIO1 Pin Function Select + * 0 = ADCLRC frame clock for ADC + * 1 = GPIO pin + */ +#define WM8960_IFACE2_ALRCGPIO_MASK (0x40U) +#define WM8960_IFACE2_ALRCGPIO_SHIFT (6U) +#define WM8960_IFACE2_ALRCGPIO_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ALRCGPIO_SHIFT) & WM8960_IFACE2_ALRCGPIO_MASK) +#define WM8960_IFACE2_ALRCGPIO_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ALRCGPIO_MASK) >> WM8960_IFACE2_ALRCGPIO_SHIFT) + +/* + * WL8 (RW) + * + * 8-Bit Word Length Select (Used with + * companding) + * 0 = Off + * 1 = Device operates in 8-bit mode. + */ +#define WM8960_IFACE2_WL8_MASK (0x20U) +#define WM8960_IFACE2_WL8_SHIFT (5U) +#define WM8960_IFACE2_WL8_SET(x) (((uint16_t)(x) << WM8960_IFACE2_WL8_SHIFT) & WM8960_IFACE2_WL8_MASK) +#define WM8960_IFACE2_WL8_GET(x) (((uint16_t)(x) & WM8960_IFACE2_WL8_MASK) >> WM8960_IFACE2_WL8_SHIFT) + +/* + * DACCOMP (RW) + * + * DAC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_DACCOMP_MASK (0x18U) +#define WM8960_IFACE2_DACCOMP_SHIFT (3U) +#define WM8960_IFACE2_DACCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_DACCOMP_SHIFT) & WM8960_IFACE2_DACCOMP_MASK) +#define WM8960_IFACE2_DACCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_DACCOMP_MASK) >> WM8960_IFACE2_DACCOMP_SHIFT) + +/* + * ADCCOMP (RW) + * + * ADC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_ADCCOMP_MASK (0x6U) +#define WM8960_IFACE2_ADCCOMP_SHIFT (1U) +#define WM8960_IFACE2_ADCCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ADCCOMP_SHIFT) & WM8960_IFACE2_ADCCOMP_MASK) +#define WM8960_IFACE2_ADCCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ADCCOMP_MASK) >> WM8960_IFACE2_ADCCOMP_SHIFT) + +/* + * LOOPBACK (RW) + * + * Digital Loopback Function + * 0 = No loopback. + * 1 = Loopback enabled, ADC data output is fed + * directly into DAC data input + */ +#define WM8960_IFACE2_LOOPBACK_MASK (0x1U) +#define WM8960_IFACE2_LOOPBACK_SHIFT (0U) +#define WM8960_IFACE2_LOOPBACK_SET(x) (((uint16_t)(x) << WM8960_IFACE2_LOOPBACK_SHIFT) & WM8960_IFACE2_LOOPBACK_MASK) +#define WM8960_IFACE2_LOOPBACK_GET(x) (((uint16_t)(x) & WM8960_IFACE2_LOOPBACK_MASK) >> WM8960_IFACE2_LOOPBACK_SHIFT) + +/* Bitfield definition for register: LDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_LDAC_DACVU_MASK (0x100U) +#define WM8960_LDAC_DACVU_SHIFT (8U) +#define WM8960_LDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_LDAC_DACVU_SHIFT) & WM8960_LDAC_DACVU_MASK) +#define WM8960_LDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_LDAC_DACVU_MASK) >> WM8960_LDAC_DACVU_SHIFT) + +/* + * LDACVOL (RW) + * + * Left DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_LDAC_LDACVOL_MASK (0xFFU) +#define WM8960_LDAC_LDACVOL_SHIFT (0U) +#define WM8960_LDAC_LDACVOL_SET(x) (((uint16_t)(x) << WM8960_LDAC_LDACVOL_SHIFT) & WM8960_LDAC_LDACVOL_MASK) +#define WM8960_LDAC_LDACVOL_GET(x) (((uint16_t)(x) & WM8960_LDAC_LDACVOL_MASK) >> WM8960_LDAC_LDACVOL_SHIFT) + +/* Bitfield definition for register: RDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_RDAC_DACVU_MASK (0x100U) +#define WM8960_RDAC_DACVU_SHIFT (8U) +#define WM8960_RDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_RDAC_DACVU_SHIFT) & WM8960_RDAC_DACVU_MASK) +#define WM8960_RDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_RDAC_DACVU_MASK) >> WM8960_RDAC_DACVU_SHIFT) + +/* + * RDACVOL (RW) + * + * Right DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_RDAC_RDACVOL_MASK (0xFFU) +#define WM8960_RDAC_RDACVOL_SHIFT (0U) +#define WM8960_RDAC_RDACVOL_SET(x) (((uint16_t)(x) << WM8960_RDAC_RDACVOL_SHIFT) & WM8960_RDAC_RDACVOL_MASK) +#define WM8960_RDAC_RDACVOL_GET(x) (((uint16_t)(x) & WM8960_RDAC_RDACVOL_MASK) >> WM8960_RDAC_RDACVOL_SHIFT) + +/* Bitfield definition for register: RESET */ +/* + * RESET (RW) + * + * Writing to this register resets all registers to their default state. + */ +#define WM8960_RESET_RESET_MASK (0x1FFU) +#define WM8960_RESET_RESET_SHIFT (0U) +#define WM8960_RESET_RESET_SET(x) (((uint16_t)(x) << WM8960_RESET_RESET_SHIFT) & WM8960_RESET_RESET_MASK) +#define WM8960_RESET_RESET_GET(x) (((uint16_t)(x) & WM8960_RESET_RESET_MASK) >> WM8960_RESET_RESET_SHIFT) + +/* Bitfield definition for register: 3D */ +/* + * 3DUC (RW) + * + * 3D Enhance Filter Upper Cut-Off Frequency + * 0 = High (Recommended for fs>=32kHz) + * 1 = Low (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DUC_MASK (0x40U) +#define WM8960_3D_3DUC_SHIFT (6U) +#define WM8960_3D_3DUC_SET(x) (((uint16_t)(x) << WM8960_3D_3DUC_SHIFT) & WM8960_3D_3DUC_MASK) +#define WM8960_3D_3DUC_GET(x) (((uint16_t)(x) & WM8960_3D_3DUC_MASK) >> WM8960_3D_3DUC_SHIFT) + +/* + * 3DLC (RW) + * + * 3D Enhance Filter Lower Cut-Off Frequency + * 0 = Low (Recommended for fs>=32kHz) + * 1 = High (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DLC_MASK (0x20U) +#define WM8960_3D_3DLC_SHIFT (5U) +#define WM8960_3D_3DLC_SET(x) (((uint16_t)(x) << WM8960_3D_3DLC_SHIFT) & WM8960_3D_3DLC_MASK) +#define WM8960_3D_3DLC_GET(x) (((uint16_t)(x) & WM8960_3D_3DLC_MASK) >> WM8960_3D_3DLC_SHIFT) + +/* + * 3DDEPTH (RW) + * + * 3D Stereo Depth + * 0000 = 0% (minimum 3D effect) + * 0001 = 6.67% + * .... + * 1110 = 93.3% + * 1111 = 100% (maximum 3D effect) + */ +#define WM8960_3D_3DDEPTH_MASK (0x1EU) +#define WM8960_3D_3DDEPTH_SHIFT (1U) +#define WM8960_3D_3DDEPTH_SET(x) (((uint16_t)(x) << WM8960_3D_3DDEPTH_SHIFT) & WM8960_3D_3DDEPTH_MASK) +#define WM8960_3D_3DDEPTH_GET(x) (((uint16_t)(x) & WM8960_3D_3DDEPTH_MASK) >> WM8960_3D_3DDEPTH_SHIFT) + +/* + * 3DEN (RW) + * + * 3D Stereo Enhancement Enable + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_3D_3DEN_MASK (0x1U) +#define WM8960_3D_3DEN_SHIFT (0U) +#define WM8960_3D_3DEN_SET(x) (((uint16_t)(x) << WM8960_3D_3DEN_SHIFT) & WM8960_3D_3DEN_MASK) +#define WM8960_3D_3DEN_GET(x) (((uint16_t)(x) & WM8960_3D_3DEN_MASK) >> WM8960_3D_3DEN_SHIFT) + +/* Bitfield definition for register: ALC1 */ +/* + * ALCSEL (RW) + * + * ALC Function Select + * 00 = ALC off (PGA gain set by register) + * 01 = Right channel only + * 10 = Left channel only + * 11 = Stereo (PGA registers unused) Note: + * ensure that LINVOL and RINVOL settings + * (reg. 0 and 1) are the same before entering this mode. + */ +#define WM8960_ALC1_ALCSEL_MASK (0x180U) +#define WM8960_ALC1_ALCSEL_SHIFT (7U) +#define WM8960_ALC1_ALCSEL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCSEL_SHIFT) & WM8960_ALC1_ALCSEL_MASK) +#define WM8960_ALC1_ALCSEL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCSEL_MASK) >> WM8960_ALC1_ALCSEL_SHIFT) + +/* + * MAXGAIN (RW) + * + * Set Maximum Gain of PGA (During ALC + * operation) + * 111 : +30dB + * 110 : +24dB + * ….(-6dB steps) + * 001 : -6dB + * 000 : -12dB + */ +#define WM8960_ALC1_MAXGAIN_MASK (0x70U) +#define WM8960_ALC1_MAXGAIN_SHIFT (4U) +#define WM8960_ALC1_MAXGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC1_MAXGAIN_SHIFT) & WM8960_ALC1_MAXGAIN_MASK) +#define WM8960_ALC1_MAXGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC1_MAXGAIN_MASK) >> WM8960_ALC1_MAXGAIN_SHIFT) + +/* + * ALCL (RW) + * + * ALC Target (Sets signal level at ADC input) + * 0000 = -22.5dB FS + * 0001 = -21.0dB FS + * … (1.5dB steps) + * 1101 = -3.0dB FS + * 1110 = -1.5dB FS + * 1111 = -1.5dB FS + */ +#define WM8960_ALC1_ALCL_MASK (0xFU) +#define WM8960_ALC1_ALCL_SHIFT (0U) +#define WM8960_ALC1_ALCL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCL_SHIFT) & WM8960_ALC1_ALCL_MASK) +#define WM8960_ALC1_ALCL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCL_MASK) >> WM8960_ALC1_ALCL_SHIFT) + +/* Bitfield definition for register: ALC2 */ +/* + * MINGAIN (RW) + * + * Set Minimum Gain of PGA (During ALC + * operation) + * 000 = -17.25dB + * 001 = -11.25dB + * 010 = -5.25dB + * 011 = +0.75dB + * 100 = +6.75dB + * 101 = +12.75dB + * 110 = +18.75dB + * 111 = +24.75dB + */ +#define WM8960_ALC2_MINGAIN_MASK (0x70U) +#define WM8960_ALC2_MINGAIN_SHIFT (4U) +#define WM8960_ALC2_MINGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC2_MINGAIN_SHIFT) & WM8960_ALC2_MINGAIN_MASK) +#define WM8960_ALC2_MINGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC2_MINGAIN_MASK) >> WM8960_ALC2_MINGAIN_SHIFT) + +/* + * HLD (RW) + * + * ALC hold time before gain is increased. + * 0000 = 0ms + * 0001 = 2.67ms + * 0010 = 5.33ms + * … (time doubles with every step) + * 1111 = 43.691s + */ +#define WM8960_ALC2_HLD_MASK (0xFU) +#define WM8960_ALC2_HLD_SHIFT (0U) +#define WM8960_ALC2_HLD_SET(x) (((uint16_t)(x) << WM8960_ALC2_HLD_SHIFT) & WM8960_ALC2_HLD_MASK) +#define WM8960_ALC2_HLD_GET(x) (((uint16_t)(x) & WM8960_ALC2_HLD_MASK) >> WM8960_ALC2_HLD_SHIFT) + +/* Bitfield definition for register: ALC3 */ +/* + * ALCMODE (RW) + * + * Determines the ALC mode of operation: + * 0 = ALC mode + * 1 = Limiter mode + */ +#define WM8960_ALC3_ALCMODE_MASK (0x100U) +#define WM8960_ALC3_ALCMODE_SHIFT (8U) +#define WM8960_ALC3_ALCMODE_SET(x) (((uint16_t)(x) << WM8960_ALC3_ALCMODE_SHIFT) & WM8960_ALC3_ALCMODE_MASK) +#define WM8960_ALC3_ALCMODE_GET(x) (((uint16_t)(x) & WM8960_ALC3_ALCMODE_MASK) >> WM8960_ALC3_ALCMODE_SHIFT) + +/* + * DCY (RW) + * + * ALC decay (gain ramp-up) time + * 0000 = 24ms + * 0001 = 48ms + * 0010 = 96ms + * … (time doubles with every step) + * 1010 or higher = 24.58s + */ +#define WM8960_ALC3_DCY_MASK (0xF0U) +#define WM8960_ALC3_DCY_SHIFT (4U) +#define WM8960_ALC3_DCY_SET(x) (((uint16_t)(x) << WM8960_ALC3_DCY_SHIFT) & WM8960_ALC3_DCY_MASK) +#define WM8960_ALC3_DCY_GET(x) (((uint16_t)(x) & WM8960_ALC3_DCY_MASK) >> WM8960_ALC3_DCY_SHIFT) + +/* + * ATK (RW) + * + * ALC attack (gain ramp-down) time + * 0000 = 6ms + * 0001 = 12ms + * 0010 = 24ms + * … (time doubles with every step) + * 1010 or higher = 6.14s + */ +#define WM8960_ALC3_ATK_MASK (0xFU) +#define WM8960_ALC3_ATK_SHIFT (0U) +#define WM8960_ALC3_ATK_SET(x) (((uint16_t)(x) << WM8960_ALC3_ATK_SHIFT) & WM8960_ALC3_ATK_MASK) +#define WM8960_ALC3_ATK_GET(x) (((uint16_t)(x) & WM8960_ALC3_ATK_MASK) >> WM8960_ALC3_ATK_SHIFT) + +/* Bitfield definition for register: NOISEG */ +/* + * NGTH (RW) + * + * Noise gate threshold + * 00000 -76.5dBfs + * 00001 -75dBfs + * … 1.5 dB steps + * 11110 -31.5dBfs + * 11111 -30dBfs + */ +#define WM8960_NOISEG_NGTH_MASK (0xF8U) +#define WM8960_NOISEG_NGTH_SHIFT (3U) +#define WM8960_NOISEG_NGTH_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGTH_SHIFT) & WM8960_NOISEG_NGTH_MASK) +#define WM8960_NOISEG_NGTH_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGTH_MASK) >> WM8960_NOISEG_NGTH_SHIFT) + +/* + * NGAT (RW) + * + * Noise gate function enable + * 0 = disable + * 1 = enable + */ +#define WM8960_NOISEG_NGAT_MASK (0x1U) +#define WM8960_NOISEG_NGAT_SHIFT (0U) +#define WM8960_NOISEG_NGAT_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGAT_SHIFT) & WM8960_NOISEG_NGAT_MASK) +#define WM8960_NOISEG_NGAT_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGAT_MASK) >> WM8960_NOISEG_NGAT_SHIFT) + +/* Bitfield definition for register: LADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and + * RADCVOL) + */ +#define WM8960_LADC_ADCVU_MASK (0x100U) +#define WM8960_LADC_ADCVU_SHIFT (8U) +#define WM8960_LADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_LADC_ADCVU_SHIFT) & WM8960_LADC_ADCVU_MASK) +#define WM8960_LADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_LADC_ADCVU_MASK) >> WM8960_LADC_ADCVU_SHIFT) + +/* + * LADCVOL (RW) + * + * Left ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_LADC_LADCVOL_MASK (0xFFU) +#define WM8960_LADC_LADCVOL_SHIFT (0U) +#define WM8960_LADC_LADCVOL_SET(x) (((uint16_t)(x) << WM8960_LADC_LADCVOL_SHIFT) & WM8960_LADC_LADCVOL_MASK) +#define WM8960_LADC_LADCVOL_GET(x) (((uint16_t)(x) & WM8960_LADC_LADCVOL_MASK) >> WM8960_LADC_LADCVOL_SHIFT) + +/* Bitfield definition for register: RADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and RADCVOL) + */ +#define WM8960_RADC_ADCVU_MASK (0x100U) +#define WM8960_RADC_ADCVU_SHIFT (8U) +#define WM8960_RADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_RADC_ADCVU_SHIFT) & WM8960_RADC_ADCVU_MASK) +#define WM8960_RADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_RADC_ADCVU_MASK) >> WM8960_RADC_ADCVU_SHIFT) + +/* + * RADCVOL (RW) + * + * Right ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_RADC_RADCVOL_MASK (0xFFU) +#define WM8960_RADC_RADCVOL_SHIFT (0U) +#define WM8960_RADC_RADCVOL_SET(x) (((uint16_t)(x) << WM8960_RADC_RADCVOL_SHIFT) & WM8960_RADC_RADCVOL_MASK) +#define WM8960_RADC_RADCVOL_GET(x) (((uint16_t)(x) & WM8960_RADC_RADCVOL_MASK) >> WM8960_RADC_RADCVOL_SHIFT) + +/* Bitfield definition for register: ADDCTL1 */ +/* + * TSDEN (RW) + * + * Thermal Shutdown Enable + * 0 = Thermal shutdown disabled + * 1 = Thermal shutdown enabled + * (TSENSEN must be enabled for this function to work) + */ +#define WM8960_ADDCTL1_TSDEN_MASK (0x100U) +#define WM8960_ADDCTL1_TSDEN_SHIFT (8U) +#define WM8960_ADDCTL1_TSDEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TSDEN_SHIFT) & WM8960_ADDCTL1_TSDEN_MASK) +#define WM8960_ADDCTL1_TSDEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TSDEN_MASK) >> WM8960_ADDCTL1_TSDEN_SHIFT) + +/* + * VSEL (RW) + * + * Analogue Bias Optimisation + * 00 = Reserved + * 01 = Increased bias current optimized for + * AVDD=2.7V + * 1X = Lowest bias current, optimized for + * AVDD=3.3V + */ +#define WM8960_ADDCTL1_VSEL_MASK (0xC0U) +#define WM8960_ADDCTL1_VSEL_SHIFT (6U) +#define WM8960_ADDCTL1_VSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_VSEL_SHIFT) & WM8960_ADDCTL1_VSEL_MASK) +#define WM8960_ADDCTL1_VSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_VSEL_MASK) >> WM8960_ADDCTL1_VSEL_SHIFT) + +/* + * DMONOMIX (RW) + * + * DAC Mono Mix + * 0 = Stereo + * 1 = Mono (Mono MIX output on enabled DACs + */ +#define WM8960_ADDCTL1_DMONOMIX_MASK (0x10U) +#define WM8960_ADDCTL1_DMONOMIX_SHIFT (4U) +#define WM8960_ADDCTL1_DMONOMIX_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DMONOMIX_SHIFT) & WM8960_ADDCTL1_DMONOMIX_MASK) +#define WM8960_ADDCTL1_DMONOMIX_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DMONOMIX_MASK) >> WM8960_ADDCTL1_DMONOMIX_SHIFT) + +/* + * DATSEL (RW) + * + * ADC Data Output Select + * 00: left data = left ADC; right data =right ADC + * 01: left data = left ADC; right data = left ADC + * 10: left data = right ADC; right data =right ADC + * 11: left data = right ADC; right data = left ADC + */ +#define WM8960_ADDCTL1_DATSEL_MASK (0xCU) +#define WM8960_ADDCTL1_DATSEL_SHIFT (2U) +#define WM8960_ADDCTL1_DATSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DATSEL_SHIFT) & WM8960_ADDCTL1_DATSEL_MASK) +#define WM8960_ADDCTL1_DATSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DATSEL_MASK) >> WM8960_ADDCTL1_DATSEL_SHIFT) + +/* + * TOCLKSEL (RW) + * + * Slow Clock Select (Used for volume update + * timeouts and for jack detect debounce) + * 0 = SYSCLK / 221 (Slower Response) + * 1 = SYSCLK / 219 (Faster Response) + */ +#define WM8960_ADDCTL1_TOCLKSEL_MASK (0x2U) +#define WM8960_ADDCTL1_TOCLKSEL_SHIFT (1U) +#define WM8960_ADDCTL1_TOCLKSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOCLKSEL_SHIFT) & WM8960_ADDCTL1_TOCLKSEL_MASK) +#define WM8960_ADDCTL1_TOCLKSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOCLKSEL_MASK) >> WM8960_ADDCTL1_TOCLKSEL_SHIFT) + +/* + * TOEN (RW) + * + * Enables Slow Clock for Volume Update Timeout + * and Jack Detect Debounce + * 0 = Slow clock disabled + * 1 = Slow clock enabled + */ +#define WM8960_ADDCTL1_TOEN_MASK (0x1U) +#define WM8960_ADDCTL1_TOEN_SHIFT (0U) +#define WM8960_ADDCTL1_TOEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOEN_SHIFT) & WM8960_ADDCTL1_TOEN_MASK) +#define WM8960_ADDCTL1_TOEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOEN_MASK) >> WM8960_ADDCTL1_TOEN_SHIFT) + +/* Bitfield definition for register: ADDCTL2 */ +/* + * HPSWEN (RW) + * + * Headphone Switch Enable + * 0 = Headphone switch disabled + * 1 = Headphone switch enabled + */ +#define WM8960_ADDCTL2_HPSWEN_MASK (0x40U) +#define WM8960_ADDCTL2_HPSWEN_SHIFT (6U) +#define WM8960_ADDCTL2_HPSWEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWEN_SHIFT) & WM8960_ADDCTL2_HPSWEN_MASK) +#define WM8960_ADDCTL2_HPSWEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWEN_MASK) >> WM8960_ADDCTL2_HPSWEN_SHIFT) + +/* + * HPSWPOL (RW) + * + * Headphone Switch Polarity + * 0 = HPDETECT high = headphone + * 1 = HPDETECT high = speaker + */ +#define WM8960_ADDCTL2_HPSWPOL_MASK (0x20U) +#define WM8960_ADDCTL2_HPSWPOL_SHIFT (5U) +#define WM8960_ADDCTL2_HPSWPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWPOL_SHIFT) & WM8960_ADDCTL2_HPSWPOL_MASK) +#define WM8960_ADDCTL2_HPSWPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWPOL_MASK) >> WM8960_ADDCTL2_HPSWPOL_SHIFT) + +/* + * TRIS (RW) + * + * Tristates ADCDAT and switches ADCLRC, + * DACLRC and BCLK to inputs. + * 0 = ADCDAT is an output; ADCLRC, DACLRC + * and BCLK are inputs (slave mode) or outputs + * (master mode) + * 1 = ADCDAT is tristated; DACLRC and BCLK + * are inputs; ADCLRC is an input (when not + * configured as a GPIO) + */ +#define WM8960_ADDCTL2_TRIS_MASK (0x8U) +#define WM8960_ADDCTL2_TRIS_SHIFT (3U) +#define WM8960_ADDCTL2_TRIS_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_TRIS_SHIFT) & WM8960_ADDCTL2_TRIS_MASK) +#define WM8960_ADDCTL2_TRIS_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_TRIS_MASK) >> WM8960_ADDCTL2_TRIS_SHIFT) + +/* + * LRCM (RW) + * + * Selects disable mode for ADCLRC and DACLRC + * (Master mode) + * 0 = ADCLRC disabled when ADC (Left and + * Right) disabled; DACLRC disabled when + * DAC (Left and Right) disabled. + * 1 = ADCLRC and DACLRC disabled only when + * ADC (Left and Right) and DAC (Left and Right) + * are disabled. + */ +#define WM8960_ADDCTL2_LRCM_MASK (0x4U) +#define WM8960_ADDCTL2_LRCM_SHIFT (2U) +#define WM8960_ADDCTL2_LRCM_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_LRCM_SHIFT) & WM8960_ADDCTL2_LRCM_MASK) +#define WM8960_ADDCTL2_LRCM_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_LRCM_MASK) >> WM8960_ADDCTL2_LRCM_SHIFT) + +/* Bitfield definition for register: POWER1 */ +/* + * VMIDSEL (RW) + * + * Vmid Divider Enable and Select + * 00 = Vmid disabled (for OFF mode) + * 01 = 2 x 50k divider enabled (for playback / + * record) + * 10 = 2 x 250k divider enabled (for low-power + * standby) + * 11 = 2 x 5k divider enabled (for fast start-up) + */ +#define WM8960_POWER1_VMIDSEL_MASK (0x180U) +#define WM8960_POWER1_VMIDSEL_SHIFT (7U) +#define WM8960_POWER1_VMIDSEL_SET(x) (((uint16_t)(x) << WM8960_POWER1_VMIDSEL_SHIFT) & WM8960_POWER1_VMIDSEL_MASK) +#define WM8960_POWER1_VMIDSEL_GET(x) (((uint16_t)(x) & WM8960_POWER1_VMIDSEL_MASK) >> WM8960_POWER1_VMIDSEL_SHIFT) + +/* + * VREF (RW) + * + * VREF (necessary for all other functions) + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_VREF_MASK (0x40U) +#define WM8960_POWER1_VREF_SHIFT (6U) +#define WM8960_POWER1_VREF_SET(x) (((uint16_t)(x) << WM8960_POWER1_VREF_SHIFT) & WM8960_POWER1_VREF_MASK) +#define WM8960_POWER1_VREF_GET(x) (((uint16_t)(x) & WM8960_POWER1_VREF_MASK) >> WM8960_POWER1_VREF_SHIFT) + +/* + * AINL (RW) + * + * Analogue in PGA Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINL_MASK (0x20U) +#define WM8960_POWER1_AINL_SHIFT (5U) +#define WM8960_POWER1_AINL_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINL_SHIFT) & WM8960_POWER1_AINL_MASK) +#define WM8960_POWER1_AINL_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINL_MASK) >> WM8960_POWER1_AINL_SHIFT) + +/* + * AINR (RW) + * + * Analogue in PGA Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINR_MASK (0x10U) +#define WM8960_POWER1_AINR_SHIFT (4U) +#define WM8960_POWER1_AINR_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINR_SHIFT) & WM8960_POWER1_AINR_MASK) +#define WM8960_POWER1_AINR_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINR_MASK) >> WM8960_POWER1_AINR_SHIFT) + +/* + * ADCL (RW) + * + * ADC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCL_MASK (0x8U) +#define WM8960_POWER1_ADCL_SHIFT (3U) +#define WM8960_POWER1_ADCL_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCL_SHIFT) & WM8960_POWER1_ADCL_MASK) +#define WM8960_POWER1_ADCL_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCL_MASK) >> WM8960_POWER1_ADCL_SHIFT) + +/* + * ADCR (RW) + * + * ADC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCR_MASK (0x4U) +#define WM8960_POWER1_ADCR_SHIFT (2U) +#define WM8960_POWER1_ADCR_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCR_SHIFT) & WM8960_POWER1_ADCR_MASK) +#define WM8960_POWER1_ADCR_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCR_MASK) >> WM8960_POWER1_ADCR_SHIFT) + +/* + * MICB (RW) + * + * MICBIAS + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_MICB_MASK (0x2U) +#define WM8960_POWER1_MICB_SHIFT (1U) +#define WM8960_POWER1_MICB_SET(x) (((uint16_t)(x) << WM8960_POWER1_MICB_SHIFT) & WM8960_POWER1_MICB_MASK) +#define WM8960_POWER1_MICB_GET(x) (((uint16_t)(x) & WM8960_POWER1_MICB_MASK) >> WM8960_POWER1_MICB_SHIFT) + +/* + * DIGENB (RW) + * + * Master Clock Disable + * 0 = Master clock enabled + * 1 = Master clock disabled + */ +#define WM8960_POWER1_DIGENB_MASK (0x1U) +#define WM8960_POWER1_DIGENB_SHIFT (0U) +#define WM8960_POWER1_DIGENB_SET(x) (((uint16_t)(x) << WM8960_POWER1_DIGENB_SHIFT) & WM8960_POWER1_DIGENB_MASK) +#define WM8960_POWER1_DIGENB_GET(x) (((uint16_t)(x) & WM8960_POWER1_DIGENB_MASK) >> WM8960_POWER1_DIGENB_SHIFT) + +/* Bitfield definition for register: POWER2 */ +/* + * DACL (RW) + * + * DAC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACL_MASK (0x100U) +#define WM8960_POWER2_DACL_SHIFT (8U) +#define WM8960_POWER2_DACL_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACL_SHIFT) & WM8960_POWER2_DACL_MASK) +#define WM8960_POWER2_DACL_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACL_MASK) >> WM8960_POWER2_DACL_SHIFT) + +/* + * DACR (RW) + * + * DAC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACR_MASK (0x80U) +#define WM8960_POWER2_DACR_SHIFT (7U) +#define WM8960_POWER2_DACR_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACR_SHIFT) & WM8960_POWER2_DACR_MASK) +#define WM8960_POWER2_DACR_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACR_MASK) >> WM8960_POWER2_DACR_SHIFT) + +/* + * LOUT1 (RW) + * + * LOUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_LOUT1_MASK (0x40U) +#define WM8960_POWER2_LOUT1_SHIFT (6U) +#define WM8960_POWER2_LOUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_LOUT1_SHIFT) & WM8960_POWER2_LOUT1_MASK) +#define WM8960_POWER2_LOUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_LOUT1_MASK) >> WM8960_POWER2_LOUT1_SHIFT) + +/* + * ROUT1 (RW) + * + * ROUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_ROUT1_MASK (0x20U) +#define WM8960_POWER2_ROUT1_SHIFT (5U) +#define WM8960_POWER2_ROUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_ROUT1_SHIFT) & WM8960_POWER2_ROUT1_MASK) +#define WM8960_POWER2_ROUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_ROUT1_MASK) >> WM8960_POWER2_ROUT1_SHIFT) + +/* + * SPKL (RW) + * + * SPK_LP/SPK_LN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKL_MASK (0x10U) +#define WM8960_POWER2_SPKL_SHIFT (4U) +#define WM8960_POWER2_SPKL_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKL_SHIFT) & WM8960_POWER2_SPKL_MASK) +#define WM8960_POWER2_SPKL_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKL_MASK) >> WM8960_POWER2_SPKL_SHIFT) + +/* + * SPKR (RW) + * + * SPK_RP/SPK_RN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKR_MASK (0x8U) +#define WM8960_POWER2_SPKR_SHIFT (3U) +#define WM8960_POWER2_SPKR_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKR_SHIFT) & WM8960_POWER2_SPKR_MASK) +#define WM8960_POWER2_SPKR_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKR_MASK) >> WM8960_POWER2_SPKR_SHIFT) + +/* + * OUT3 (RW) + * + * OUT3 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_OUT3_MASK (0x2U) +#define WM8960_POWER2_OUT3_SHIFT (1U) +#define WM8960_POWER2_OUT3_SET(x) (((uint16_t)(x) << WM8960_POWER2_OUT3_SHIFT) & WM8960_POWER2_OUT3_MASK) +#define WM8960_POWER2_OUT3_GET(x) (((uint16_t)(x) & WM8960_POWER2_OUT3_MASK) >> WM8960_POWER2_OUT3_SHIFT) + +/* + * PLL_EN (RW) + * + * PLL Enable + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_PLL_EN_MASK (0x1U) +#define WM8960_POWER2_PLL_EN_SHIFT (0U) +#define WM8960_POWER2_PLL_EN_SET(x) (((uint16_t)(x) << WM8960_POWER2_PLL_EN_SHIFT) & WM8960_POWER2_PLL_EN_MASK) +#define WM8960_POWER2_PLL_EN_GET(x) (((uint16_t)(x) & WM8960_POWER2_PLL_EN_MASK) >> WM8960_POWER2_PLL_EN_SHIFT) + +/* Bitfield definition for register: ADDCTL3 */ +/* + * VROI (RW) + * + * VREF to Analogue Output Resistance (Disabled + * Outputs) + * 0 = 500 VMID to output + * 1 = 20k VMID to output + */ +#define WM8960_ADDCTL3_VROI_MASK (0x40U) +#define WM8960_ADDCTL3_VROI_SHIFT (6U) +#define WM8960_ADDCTL3_VROI_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_VROI_SHIFT) & WM8960_ADDCTL3_VROI_MASK) +#define WM8960_ADDCTL3_VROI_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_VROI_MASK) >> WM8960_ADDCTL3_VROI_SHIFT) + +/* + * OUT3CAP (RW) + * + * Capless Mode Headphone Switch Enable + * 0 = OUT3 unaffected by jack detect events + * 1 = OUT3 enabled and disabled together with + * HP_L and HP_R in response to jack detect + * events + */ +#define WM8960_ADDCTL3_OUT3CAP_MASK (0x8U) +#define WM8960_ADDCTL3_OUT3CAP_SHIFT (3U) +#define WM8960_ADDCTL3_OUT3CAP_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_OUT3CAP_SHIFT) & WM8960_ADDCTL3_OUT3CAP_MASK) +#define WM8960_ADDCTL3_OUT3CAP_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_OUT3CAP_MASK) >> WM8960_ADDCTL3_OUT3CAP_SHIFT) + +/* + * ADC_ALC_SR (RW) + * + * ALC Sample Rate + * 000 = 44.1k / 48k + * 001 = 32k + * 010 = 22.05k / 24k + * 011 = 16k + * 100 = 11.25k / 12k + * 101 = 8k + * 110 and 111 = Reserved + */ +#define WM8960_ADDCTL3_ADC_ALC_SR_MASK (0x7U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SHIFT (0U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) +#define WM8960_ADDCTL3_ADC_ALC_SR_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) >> WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) + +/* Bitfield definition for register: APOP1 */ +/* + * POBCTRL (RW) + * + * Selects the bias current source for output + * amplifiers and VMID buffer + * 0 = VMID / R bias + * 1 = VGS / R bias + */ +#define WM8960_APOP1_POBCTRL_MASK (0x80U) +#define WM8960_APOP1_POBCTRL_SHIFT (7U) +#define WM8960_APOP1_POBCTRL_SET(x) (((uint16_t)(x) << WM8960_APOP1_POBCTRL_SHIFT) & WM8960_APOP1_POBCTRL_MASK) +#define WM8960_APOP1_POBCTRL_GET(x) (((uint16_t)(x) & WM8960_APOP1_POBCTRL_MASK) >> WM8960_APOP1_POBCTRL_SHIFT) + +/* + * BUFDCOPEN (RW) + * + * Enables the VGS / R current generator + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFDCOPEN_MASK (0x10U) +#define WM8960_APOP1_BUFDCOPEN_SHIFT (4U) +#define WM8960_APOP1_BUFDCOPEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFDCOPEN_SHIFT) & WM8960_APOP1_BUFDCOPEN_MASK) +#define WM8960_APOP1_BUFDCOPEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFDCOPEN_MASK) >> WM8960_APOP1_BUFDCOPEN_SHIFT) + +/* + * BUFIOEN (RW) + * + * Enables the VGS / R current generator and the + * analogue input and output bias + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFIOEN_MASK (0x8U) +#define WM8960_APOP1_BUFIOEN_SHIFT (3U) +#define WM8960_APOP1_BUFIOEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFIOEN_SHIFT) & WM8960_APOP1_BUFIOEN_MASK) +#define WM8960_APOP1_BUFIOEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFIOEN_MASK) >> WM8960_APOP1_BUFIOEN_SHIFT) + +/* + * SOFT_ST (RW) + * + * Enables VMID soft start + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_SOFT_ST_MASK (0x4U) +#define WM8960_APOP1_SOFT_ST_SHIFT (2U) +#define WM8960_APOP1_SOFT_ST_SET(x) (((uint16_t)(x) << WM8960_APOP1_SOFT_ST_SHIFT) & WM8960_APOP1_SOFT_ST_MASK) +#define WM8960_APOP1_SOFT_ST_GET(x) (((uint16_t)(x) & WM8960_APOP1_SOFT_ST_MASK) >> WM8960_APOP1_SOFT_ST_SHIFT) + +/* + * HPSTBY (RW) + * + * Headphone Amplifier Standby + * 0 = Standby mode disabled (Normal operation) + * 1 = Standby mode enabled + */ +#define WM8960_APOP1_HPSTBY_MASK (0x1U) +#define WM8960_APOP1_HPSTBY_SHIFT (0U) +#define WM8960_APOP1_HPSTBY_SET(x) (((uint16_t)(x) << WM8960_APOP1_HPSTBY_SHIFT) & WM8960_APOP1_HPSTBY_MASK) +#define WM8960_APOP1_HPSTBY_GET(x) (((uint16_t)(x) & WM8960_APOP1_HPSTBY_MASK) >> WM8960_APOP1_HPSTBY_SHIFT) + +/* Bitfield definition for register: APOP2 */ +/* + * DISOP (RW) + * + * Discharges the DC-blocking headphone + * capacitors on HP_L and HP_R + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP2_DISOP_MASK (0x40U) +#define WM8960_APOP2_DISOP_SHIFT (6U) +#define WM8960_APOP2_DISOP_SET(x) (((uint16_t)(x) << WM8960_APOP2_DISOP_SHIFT) & WM8960_APOP2_DISOP_MASK) +#define WM8960_APOP2_DISOP_GET(x) (((uint16_t)(x) & WM8960_APOP2_DISOP_MASK) >> WM8960_APOP2_DISOP_SHIFT) + +/* + * DRES (RW) + * + * DRES determines the value of the resistors used + * to discharge the DC-blocking headphone + * capacitors when DISOP=1 + * DRES[1:0] Resistance (Ohms) + * 0 0 400 + * 0 1 200 + * 1 0 600 + * 1 1 150 + */ +#define WM8960_APOP2_DRES_MASK (0x30U) +#define WM8960_APOP2_DRES_SHIFT (4U) +#define WM8960_APOP2_DRES_SET(x) (((uint16_t)(x) << WM8960_APOP2_DRES_SHIFT) & WM8960_APOP2_DRES_MASK) +#define WM8960_APOP2_DRES_GET(x) (((uint16_t)(x) & WM8960_APOP2_DRES_MASK) >> WM8960_APOP2_DRES_SHIFT) + +/* Bitfield definition for register: LINPATH */ +/* + * LMN1 (RW) + * + * Connect LINPUT1 to inverting input of Left Input + * PGA + * 0 = LINPUT1 not connected to PGA + * 1 = LINPUT1 connected to PGA + */ +#define WM8960_LINPATH_LMN1_MASK (0x100U) +#define WM8960_LINPATH_LMN1_SHIFT (8U) +#define WM8960_LINPATH_LMN1_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMN1_SHIFT) & WM8960_LINPATH_LMN1_MASK) +#define WM8960_LINPATH_LMN1_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMN1_MASK) >> WM8960_LINPATH_LMN1_SHIFT) + +/* + * LMP3 (RW) + * + * Connect LINPUT3 to non-inverting input of Left + * Input PGA + * 0 = LINPUT3 not connected to PGA + * 1 = LINPUT3 connected to PGA (Constant input + * impedance) + */ +#define WM8960_LINPATH_LMP3_MASK (0x80U) +#define WM8960_LINPATH_LMP3_SHIFT (7U) +#define WM8960_LINPATH_LMP3_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP3_SHIFT) & WM8960_LINPATH_LMP3_MASK) +#define WM8960_LINPATH_LMP3_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP3_MASK) >> WM8960_LINPATH_LMP3_SHIFT) + +/* + * LMP2 (RW) + * + * Connect LINPUT2 to non-inverting input of Left + * Input PGA + * 0 = LINPUT2 not connected to PGA + * 1 = LINPUT2 connected to PGA (Constant input impedance) + */ +#define WM8960_LINPATH_LMP2_MASK (0x40U) +#define WM8960_LINPATH_LMP2_SHIFT (6U) +#define WM8960_LINPATH_LMP2_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP2_SHIFT) & WM8960_LINPATH_LMP2_MASK) +#define WM8960_LINPATH_LMP2_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP2_MASK) >> WM8960_LINPATH_LMP2_SHIFT) + +/* + * LMICBOOST (RW) + * + * Left Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_LINPATH_LMICBOOST_MASK (0x30U) +#define WM8960_LINPATH_LMICBOOST_SHIFT (4U) +#define WM8960_LINPATH_LMICBOOST_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMICBOOST_SHIFT) & WM8960_LINPATH_LMICBOOST_MASK) +#define WM8960_LINPATH_LMICBOOST_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMICBOOST_MASK) >> WM8960_LINPATH_LMICBOOST_SHIFT) + +/* + * LMIC2B (RW) + * + * Connect Left Input PGA to Left Input Boost Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_LINPATH_LMIC2B_MASK (0x8U) +#define WM8960_LINPATH_LMIC2B_SHIFT (3U) +#define WM8960_LINPATH_LMIC2B_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMIC2B_SHIFT) & WM8960_LINPATH_LMIC2B_MASK) +#define WM8960_LINPATH_LMIC2B_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMIC2B_MASK) >> WM8960_LINPATH_LMIC2B_SHIFT) + +/* Bitfield definition for register: RINPATH */ +/* + * RMN1 (RW) + * + * Connect RINPUT1 to inverting input of Right + * Input PGA + * 0 = RINPUT1 not connected to PGA + * 1 = RINPUT1 connected to PGA + */ +#define WM8960_RINPATH_RMN1_MASK (0x100U) +#define WM8960_RINPATH_RMN1_SHIFT (8U) +#define WM8960_RINPATH_RMN1_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMN1_SHIFT) & WM8960_RINPATH_RMN1_MASK) +#define WM8960_RINPATH_RMN1_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMN1_MASK) >> WM8960_RINPATH_RMN1_SHIFT) + +/* + * RMP3 (RW) + * + * Connect RINPUT3 to non-inverting input of Right + * Input PGA + * 0 = RINPUT3 not connected to PGA + * 1 = RINPUT3 connected to PGA (Constant input impedance) + */ +#define WM8960_RINPATH_RMP3_MASK (0x80U) +#define WM8960_RINPATH_RMP3_SHIFT (7U) +#define WM8960_RINPATH_RMP3_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP3_SHIFT) & WM8960_RINPATH_RMP3_MASK) +#define WM8960_RINPATH_RMP3_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP3_MASK) >> WM8960_RINPATH_RMP3_SHIFT) + +/* + * RMP2 (RW) + * + * Connect RINPUT2 to non-inverting input of Right + * Input PGA + * 0 = RINPUT2 not connected to PGA + * 1 = RINPUT2 connected to PGA (Constant input + * impedance) + */ +#define WM8960_RINPATH_RMP2_MASK (0x40U) +#define WM8960_RINPATH_RMP2_SHIFT (6U) +#define WM8960_RINPATH_RMP2_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP2_SHIFT) & WM8960_RINPATH_RMP2_MASK) +#define WM8960_RINPATH_RMP2_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP2_MASK) >> WM8960_RINPATH_RMP2_SHIFT) + +/* + * RMICBOOST (RW) + * + * Right Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_RINPATH_RMICBOOST_MASK (0x30U) +#define WM8960_RINPATH_RMICBOOST_SHIFT (4U) +#define WM8960_RINPATH_RMICBOOST_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMICBOOST_SHIFT) & WM8960_RINPATH_RMICBOOST_MASK) +#define WM8960_RINPATH_RMICBOOST_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMICBOOST_MASK) >> WM8960_RINPATH_RMICBOOST_SHIFT) + +/* + * RMIC2B (RW) + * + * Connect Right Input PGA to Right Input Boost + * Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_RINPATH_RMIC2B_MASK (0x8U) +#define WM8960_RINPATH_RMIC2B_SHIFT (3U) +#define WM8960_RINPATH_RMIC2B_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMIC2B_SHIFT) & WM8960_RINPATH_RMIC2B_MASK) +#define WM8960_RINPATH_RMIC2B_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMIC2B_MASK) >> WM8960_RINPATH_RMIC2B_SHIFT) + +/* Bitfield definition for register: LOUTMIX */ +/* + * LD2LO (RW) + * + * Left DAC to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LD2LO_MASK (0x100U) +#define WM8960_LOUTMIX_LD2LO_SHIFT (8U) +#define WM8960_LOUTMIX_LD2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LD2LO_SHIFT) & WM8960_LOUTMIX_LD2LO_MASK) +#define WM8960_LOUTMIX_LD2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LD2LO_MASK) >> WM8960_LOUTMIX_LD2LO_SHIFT) + +/* + * LI2LO (RW) + * + * LINPUT3 to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LI2LO_MASK (0x80U) +#define WM8960_LOUTMIX_LI2LO_SHIFT (7U) +#define WM8960_LOUTMIX_LI2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LO_SHIFT) & WM8960_LOUTMIX_LI2LO_MASK) +#define WM8960_LOUTMIX_LI2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LO_MASK) >> WM8960_LOUTMIX_LI2LO_SHIFT) + +/* + * LI2LOVOL (RW) + * + * LINPUT3 to Left Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_LOUTMIX_LI2LOVOL_MASK (0x70U) +#define WM8960_LOUTMIX_LI2LOVOL_SHIFT (4U) +#define WM8960_LOUTMIX_LI2LOVOL_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LOVOL_SHIFT) & WM8960_LOUTMIX_LI2LOVOL_MASK) +#define WM8960_LOUTMIX_LI2LOVOL_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LOVOL_MASK) >> WM8960_LOUTMIX_LI2LOVOL_SHIFT) + +/* Bitfield definition for register: ROUTMIX */ +/* + * RD2RO (RW) + * + * Right DAC to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RD2RO_MASK (0x100U) +#define WM8960_ROUTMIX_RD2RO_SHIFT (8U) +#define WM8960_ROUTMIX_RD2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RD2RO_SHIFT) & WM8960_ROUTMIX_RD2RO_MASK) +#define WM8960_ROUTMIX_RD2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RD2RO_MASK) >> WM8960_ROUTMIX_RD2RO_SHIFT) + +/* + * RI2RO (RW) + * + * RINPUT3 to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RI2RO_MASK (0x80U) +#define WM8960_ROUTMIX_RI2RO_SHIFT (7U) +#define WM8960_ROUTMIX_RI2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2RO_SHIFT) & WM8960_ROUTMIX_RI2RO_MASK) +#define WM8960_ROUTMIX_RI2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2RO_MASK) >> WM8960_ROUTMIX_RI2RO_SHIFT) + +/* + * RI2ROVOL (RW) + * + * RINPUT3 to Right Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_ROUTMIX_RI2ROVOL_MASK (0x70U) +#define WM8960_ROUTMIX_RI2ROVOL_SHIFT (4U) +#define WM8960_ROUTMIX_RI2ROVOL_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2ROVOL_SHIFT) & WM8960_ROUTMIX_RI2ROVOL_MASK) +#define WM8960_ROUTMIX_RI2ROVOL_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2ROVOL_MASK) >> WM8960_ROUTMIX_RI2ROVOL_SHIFT) + +/* Bitfield definition for register: MONOMIX1 */ +/* + * L2MO (RW) + * + * Left Output Mixer to Mono Output Mixer Control + * 0 = Left channel mix disabled + * 1 = Left channel mix enabled + */ +#define WM8960_MONOMIX1_L2MO_MASK (0x80U) +#define WM8960_MONOMIX1_L2MO_SHIFT (7U) +#define WM8960_MONOMIX1_L2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX1_L2MO_SHIFT) & WM8960_MONOMIX1_L2MO_MASK) +#define WM8960_MONOMIX1_L2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX1_L2MO_MASK) >> WM8960_MONOMIX1_L2MO_SHIFT) + +/* Bitfield definition for register: MONOMIX2 */ +/* + * R2MO (RW) + * + * Right Output Mixer to Mono Output Mixer Control + * 0 = Right channel mix disabled + * 1 = Right channel mix enabled + */ +#define WM8960_MONOMIX2_R2MO_MASK (0x80U) +#define WM8960_MONOMIX2_R2MO_SHIFT (7U) +#define WM8960_MONOMIX2_R2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX2_R2MO_SHIFT) & WM8960_MONOMIX2_R2MO_MASK) +#define WM8960_MONOMIX2_R2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX2_R2MO_MASK) >> WM8960_MONOMIX2_R2MO_SHIFT) + +/* Bitfield definition for register: LOUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_LOUT2_SPKVU_MASK (0x100U) +#define WM8960_LOUT2_SPKVU_SHIFT (8U) +#define WM8960_LOUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKVU_SHIFT) & WM8960_LOUT2_SPKVU_MASK) +#define WM8960_LOUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKVU_MASK) >> WM8960_LOUT2_SPKVU_SHIFT) + +/* + * SPKLZC (RW) + * + * Left Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_LOUT2_SPKLZC_MASK (0x80U) +#define WM8960_LOUT2_SPKLZC_SHIFT (7U) +#define WM8960_LOUT2_SPKLZC_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLZC_SHIFT) & WM8960_LOUT2_SPKLZC_MASK) +#define WM8960_LOUT2_SPKLZC_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLZC_MASK) >> WM8960_LOUT2_SPKLZC_SHIFT) + +/* + * SPKLVOL (RW) + * + * SPK_LP/SPK_LN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT2_SPKLVOL_MASK (0x7FU) +#define WM8960_LOUT2_SPKLVOL_SHIFT (0U) +#define WM8960_LOUT2_SPKLVOL_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLVOL_SHIFT) & WM8960_LOUT2_SPKLVOL_MASK) +#define WM8960_LOUT2_SPKLVOL_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLVOL_MASK) >> WM8960_LOUT2_SPKLVOL_SHIFT) + +/* Bitfield definition for register: ROUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right + * speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_ROUT2_SPKVU_MASK (0x100U) +#define WM8960_ROUT2_SPKVU_SHIFT (8U) +#define WM8960_ROUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKVU_SHIFT) & WM8960_ROUT2_SPKVU_MASK) +#define WM8960_ROUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKVU_MASK) >> WM8960_ROUT2_SPKVU_SHIFT) + +/* + * SPKRZC (RW) + * + * Right Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_ROUT2_SPKRZC_MASK (0x80U) +#define WM8960_ROUT2_SPKRZC_SHIFT (7U) +#define WM8960_ROUT2_SPKRZC_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRZC_SHIFT) & WM8960_ROUT2_SPKRZC_MASK) +#define WM8960_ROUT2_SPKRZC_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRZC_MASK) >> WM8960_ROUT2_SPKRZC_SHIFT) + +/* + * SPKRVOL (RW) + * + * SPK_RP/SPK_RN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT2_SPKRVOL_MASK (0x7FU) +#define WM8960_ROUT2_SPKRVOL_SHIFT (0U) +#define WM8960_ROUT2_SPKRVOL_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRVOL_SHIFT) & WM8960_ROUT2_SPKRVOL_MASK) +#define WM8960_ROUT2_SPKRVOL_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRVOL_MASK) >> WM8960_ROUT2_SPKRVOL_SHIFT) + +/* Bitfield definition for register: MONO */ +/* + * MOUTVOL (RW) + * + * Mono Output Mixer Volume Control + * 0 = 0dB + * 1 = -6dB + */ +#define WM8960_MONO_MOUTVOL_MASK (0x40U) +#define WM8960_MONO_MOUTVOL_SHIFT (6U) +#define WM8960_MONO_MOUTVOL_SET(x) (((uint16_t)(x) << WM8960_MONO_MOUTVOL_SHIFT) & WM8960_MONO_MOUTVOL_MASK) +#define WM8960_MONO_MOUTVOL_GET(x) (((uint16_t)(x) & WM8960_MONO_MOUTVOL_MASK) >> WM8960_MONO_MOUTVOL_SHIFT) + +/* Bitfield definition for register: INBMIX1 */ +/* + * LIN3BOOST (RW) + * + * LINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX1_LIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX1_LIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN3BOOST_SHIFT) & WM8960_INBMIX1_LIN3BOOST_MASK) +#define WM8960_INBMIX1_LIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN3BOOST_MASK) >> WM8960_INBMIX1_LIN3BOOST_SHIFT) + +/* + * LIN2BOOST (RW) + * + * LINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX1_LIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX1_LIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN2BOOST_SHIFT) & WM8960_INBMIX1_LIN2BOOST_MASK) +#define WM8960_INBMIX1_LIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN2BOOST_MASK) >> WM8960_INBMIX1_LIN2BOOST_SHIFT) + +/* Bitfield definition for register: INBMIX2 */ +/* + * RIN3BOOST (RW) + * + * RINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX2_RIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX2_RIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN3BOOST_SHIFT) & WM8960_INBMIX2_RIN3BOOST_MASK) +#define WM8960_INBMIX2_RIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN3BOOST_MASK) >> WM8960_INBMIX2_RIN3BOOST_SHIFT) + +/* + * RIN2BOOST (RW) + * + * RINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX2_RIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX2_RIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN2BOOST_SHIFT) & WM8960_INBMIX2_RIN2BOOST_MASK) +#define WM8960_INBMIX2_RIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN2BOOST_MASK) >> WM8960_INBMIX2_RIN2BOOST_SHIFT) + +/* Bitfield definition for register: BYPASS1 */ +/* + * LB2LO (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS1_LB2LO_MASK (0x80U) +#define WM8960_BYPASS1_LB2LO_SHIFT (7U) +#define WM8960_BYPASS1_LB2LO_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LO_SHIFT) & WM8960_BYPASS1_LB2LO_MASK) +#define WM8960_BYPASS1_LB2LO_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LO_MASK) >> WM8960_BYPASS1_LB2LO_SHIFT) + +/* + * LB2LOVOL (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS1_LB2LOVOL_MASK (0x70U) +#define WM8960_BYPASS1_LB2LOVOL_SHIFT (4U) +#define WM8960_BYPASS1_LB2LOVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LOVOL_SHIFT) & WM8960_BYPASS1_LB2LOVOL_MASK) +#define WM8960_BYPASS1_LB2LOVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LOVOL_MASK) >> WM8960_BYPASS1_LB2LOVOL_SHIFT) + +/* Bitfield definition for register: BYPASS2 */ +/* + * RB2RO (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS2_RB2RO_MASK (0x80U) +#define WM8960_BYPASS2_RB2RO_SHIFT (7U) +#define WM8960_BYPASS2_RB2RO_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2RO_SHIFT) & WM8960_BYPASS2_RB2RO_MASK) +#define WM8960_BYPASS2_RB2RO_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2RO_MASK) >> WM8960_BYPASS2_RB2RO_SHIFT) + +/* + * RB2ROVOL (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS2_RB2ROVOL_MASK (0x70U) +#define WM8960_BYPASS2_RB2ROVOL_SHIFT (4U) +#define WM8960_BYPASS2_RB2ROVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2ROVOL_SHIFT) & WM8960_BYPASS2_RB2ROVOL_MASK) +#define WM8960_BYPASS2_RB2ROVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2ROVOL_MASK) >> WM8960_BYPASS2_RB2ROVOL_SHIFT) + +/* Bitfield definition for register: POWER3 */ +/* + * LMIC (RW) + * + * Left Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINL = 1) + */ +#define WM8960_POWER3_LMIC_MASK (0x20U) +#define WM8960_POWER3_LMIC_SHIFT (5U) +#define WM8960_POWER3_LMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_LMIC_SHIFT) & WM8960_POWER3_LMIC_MASK) +#define WM8960_POWER3_LMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_LMIC_MASK) >> WM8960_POWER3_LMIC_SHIFT) + +/* + * RMIC (RW) + * + * Right Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINR = 1) + */ +#define WM8960_POWER3_RMIC_MASK (0x10U) +#define WM8960_POWER3_RMIC_SHIFT (4U) +#define WM8960_POWER3_RMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_RMIC_SHIFT) & WM8960_POWER3_RMIC_MASK) +#define WM8960_POWER3_RMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_RMIC_MASK) >> WM8960_POWER3_RMIC_SHIFT) + +/* + * LOMIX (RW) + * + * Left Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_LOMIX_MASK (0x8U) +#define WM8960_POWER3_LOMIX_SHIFT (3U) +#define WM8960_POWER3_LOMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_LOMIX_SHIFT) & WM8960_POWER3_LOMIX_MASK) +#define WM8960_POWER3_LOMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_LOMIX_MASK) >> WM8960_POWER3_LOMIX_SHIFT) + +/* + * ROMIX (RW) + * + * Right Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_ROMIX_MASK (0x4U) +#define WM8960_POWER3_ROMIX_SHIFT (2U) +#define WM8960_POWER3_ROMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_ROMIX_SHIFT) & WM8960_POWER3_ROMIX_MASK) +#define WM8960_POWER3_ROMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_ROMIX_MASK) >> WM8960_POWER3_ROMIX_SHIFT) + +/* Bitfield definition for register: ADDCTL4 */ +/* + * GPIOPOL (RW) + * + * GPIO Polarity Invert + * 0 = Non inverted + * 1 = Inverted + */ +#define WM8960_ADDCTL4_GPIOPOL_MASK (0x80U) +#define WM8960_ADDCTL4_GPIOPOL_SHIFT (7U) +#define WM8960_ADDCTL4_GPIOPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOPOL_SHIFT) & WM8960_ADDCTL4_GPIOPOL_MASK) +#define WM8960_ADDCTL4_GPIOPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOPOL_MASK) >> WM8960_ADDCTL4_GPIOPOL_SHIFT) + +/* + * GPIOSEL (RW) + * + * ADCLRC/GPIO1 GPIO Function Select: + * 000 = Jack detect input + * 001 = Reserved + * 010 = Temperature ok + * 011 = Debounced jack detect output + * 100 = SYSCLK output + * 101 = PLL lock + * 110 = Logic 0 + * 111 = Logic 1 + */ +#define WM8960_ADDCTL4_GPIOSEL_MASK (0x70U) +#define WM8960_ADDCTL4_GPIOSEL_SHIFT (4U) +#define WM8960_ADDCTL4_GPIOSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOSEL_SHIFT) & WM8960_ADDCTL4_GPIOSEL_MASK) +#define WM8960_ADDCTL4_GPIOSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOSEL_MASK) >> WM8960_ADDCTL4_GPIOSEL_SHIFT) + +/* + * HPSEL (RW) + * + * Headphone Switch Input Select + * 0X = GPIO1 used for jack detect input (Requires + * ADCLRC pin to be configured as a GPIO) + * 10 = JD2 used for jack detect input + * 11 = JD3 used for jack detect input + */ +#define WM8960_ADDCTL4_HPSEL_MASK (0xCU) +#define WM8960_ADDCTL4_HPSEL_SHIFT (2U) +#define WM8960_ADDCTL4_HPSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_HPSEL_SHIFT) & WM8960_ADDCTL4_HPSEL_MASK) +#define WM8960_ADDCTL4_HPSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_HPSEL_MASK) >> WM8960_ADDCTL4_HPSEL_SHIFT) + +/* + * TSENSEN (RW) + * + * Temperature Sensor Enable + * 0 = Temperature sensor disabled + * 1 = Temperature sensor enabled + */ +#define WM8960_ADDCTL4_TSENSEN_MASK (0x2U) +#define WM8960_ADDCTL4_TSENSEN_SHIFT (1U) +#define WM8960_ADDCTL4_TSENSEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_TSENSEN_SHIFT) & WM8960_ADDCTL4_TSENSEN_MASK) +#define WM8960_ADDCTL4_TSENSEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_TSENSEN_MASK) >> WM8960_ADDCTL4_TSENSEN_SHIFT) + +/* + * MBSEL (RW) + * + * Microphone Bias Voltage Control + * 0 = 0.9 * AVDD + * 1 = 0.65 * AVDD + */ +#define WM8960_ADDCTL4_MBSEL_MASK (0x1U) +#define WM8960_ADDCTL4_MBSEL_SHIFT (0U) +#define WM8960_ADDCTL4_MBSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_MBSEL_SHIFT) & WM8960_ADDCTL4_MBSEL_MASK) +#define WM8960_ADDCTL4_MBSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_MBSEL_MASK) >> WM8960_ADDCTL4_MBSEL_SHIFT) + +/* Bitfield definition for register: CLASSD1 */ +/* + * SPK_OP_EN (RW) + * + * Enable Class D Speaker Outputs + * 00 = Off + * 01 = Left speaker only + * 10 = Right speaker only + * 11 = Left and right speakers enabled + */ +#define WM8960_CLASSD1_SPK_OP_EN_MASK (0xC0U) +#define WM8960_CLASSD1_SPK_OP_EN_SHIFT (6U) +#define WM8960_CLASSD1_SPK_OP_EN_SET(x) (((uint16_t)(x) << WM8960_CLASSD1_SPK_OP_EN_SHIFT) & WM8960_CLASSD1_SPK_OP_EN_MASK) +#define WM8960_CLASSD1_SPK_OP_EN_GET(x) (((uint16_t)(x) & WM8960_CLASSD1_SPK_OP_EN_MASK) >> WM8960_CLASSD1_SPK_OP_EN_SHIFT) + +/* Bitfield definition for register: CLASSD3 */ +/* + * DCGAIN (RW) + * + * DC Speaker Boost (Boosts speaker DC output + * level by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_DCGAIN_MASK (0x38U) +#define WM8960_CLASSD3_DCGAIN_SHIFT (3U) +#define WM8960_CLASSD3_DCGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_DCGAIN_SHIFT) & WM8960_CLASSD3_DCGAIN_MASK) +#define WM8960_CLASSD3_DCGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_DCGAIN_MASK) >> WM8960_CLASSD3_DCGAIN_SHIFT) + +/* + * ACGAIN (RW) + * + * AC Speaker Boost (Boosts speaker AC output + * signal by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_ACGAIN_MASK (0x7U) +#define WM8960_CLASSD3_ACGAIN_SHIFT (0U) +#define WM8960_CLASSD3_ACGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_ACGAIN_SHIFT) & WM8960_CLASSD3_ACGAIN_MASK) +#define WM8960_CLASSD3_ACGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_ACGAIN_MASK) >> WM8960_CLASSD3_ACGAIN_SHIFT) + +/* Bitfield definition for register: PLL1 */ +/* + * OPCLKDIV (RW) + * + * SYSCLK Output to GPIO Clock Division ratio + * 000 = SYSCLK + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 5.5 + * 101 = SYSCLK / 6 + */ +#define WM8960_PLL1_OPCLKDIV_MASK (0x1C0U) +#define WM8960_PLL1_OPCLKDIV_SHIFT (6U) +#define WM8960_PLL1_OPCLKDIV_SET(x) (((uint16_t)(x) << WM8960_PLL1_OPCLKDIV_SHIFT) & WM8960_PLL1_OPCLKDIV_MASK) +#define WM8960_PLL1_OPCLKDIV_GET(x) (((uint16_t)(x) & WM8960_PLL1_OPCLKDIV_MASK) >> WM8960_PLL1_OPCLKDIV_SHIFT) + +/* + * SDM (RW) + * + * Enable Integer Mode + * 0 = Integer mode + * 1 = Fractional mode + */ +#define WM8960_PLL1_SDM_MASK (0x20U) +#define WM8960_PLL1_SDM_SHIFT (5U) +#define WM8960_PLL1_SDM_SET(x) (((uint16_t)(x) << WM8960_PLL1_SDM_SHIFT) & WM8960_PLL1_SDM_MASK) +#define WM8960_PLL1_SDM_GET(x) (((uint16_t)(x) & WM8960_PLL1_SDM_MASK) >> WM8960_PLL1_SDM_SHIFT) + +/* + * PLLPRESCALE (RW) + * + * Divide MCLK by 2 before input to PLL + * 0 = Divide by 1 + * 1 = Divide by 2 + */ +#define WM8960_PLL1_PLLPRESCALE_MASK (0x10U) +#define WM8960_PLL1_PLLPRESCALE_SHIFT (4U) +#define WM8960_PLL1_PLLPRESCALE_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLPRESCALE_SHIFT) & WM8960_PLL1_PLLPRESCALE_MASK) +#define WM8960_PLL1_PLLPRESCALE_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLPRESCALE_MASK) >> WM8960_PLL1_PLLPRESCALE_SHIFT) + +/* + * PLLN (RW) + * + * Integer (N) part of PLL input/output frequency + * ratio. Use values greater than 5 and less than 13 + */ +#define WM8960_PLL1_PLLN_MASK (0xFU) +#define WM8960_PLL1_PLLN_SHIFT (0U) +#define WM8960_PLL1_PLLN_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLN_SHIFT) & WM8960_PLL1_PLLN_MASK) +#define WM8960_PLL1_PLLN_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLN_MASK) >> WM8960_PLL1_PLLN_SHIFT) + +/* Bitfield definition for register: PLL2 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL2_PLLK_MASK (0xFFU) +#define WM8960_PLL2_PLLK_SHIFT (0U) +#define WM8960_PLL2_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL2_PLLK_SHIFT) & WM8960_PLL2_PLLK_MASK) +#define WM8960_PLL2_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL2_PLLK_MASK) >> WM8960_PLL2_PLLK_SHIFT) + +/* Bitfield definition for register: PLL3 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL3_PLLK_MASK (0xFFU) +#define WM8960_PLL3_PLLK_SHIFT (0U) +#define WM8960_PLL3_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL3_PLLK_SHIFT) & WM8960_PLL3_PLLK_MASK) +#define WM8960_PLL3_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL3_PLLK_MASK) >> WM8960_PLL3_PLLK_SHIFT) + +/* Bitfield definition for register: PLL4 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL4_PLLK_MASK (0xFFU) +#define WM8960_PLL4_PLLK_SHIFT (0U) +#define WM8960_PLL4_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL4_PLLK_SHIFT) & WM8960_PLL4_PLLK_MASK) +#define WM8960_PLL4_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL4_PLLK_MASK) >> WM8960_PLL4_PLLK_SHIFT) + + +#endif /* _HPM_WM8960_REG_H_ */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c index f330883e74..ac79d81444 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,8 +15,7 @@ hpm_stat_t console_init(console_config_t *cfg) { hpm_stat_t stat = status_fail; - if (cfg->type == console_type_uart) - { + if (cfg->type == CONSOLE_TYPE_UART) { uart_config_t config = {0}; uart_default_config((UART_Type *)cfg->base, &config); config.src_freq_in_hz = cfg->src_freq_in_hz; @@ -30,7 +29,7 @@ hpm_stat_t console_init(console_config_t *cfg) return stat; } -uint8_t console_receive_byte() +uint8_t console_receive_byte(void) { uint8_t c; while (status_success != uart_receive_byte(g_console_uart, &c)) { @@ -45,6 +44,7 @@ void console_send_byte(uint8_t c) } #ifdef __SEGGER_RTL_VERSION +#include #include "__SEGGER_RTL_Int.h" static int _stdin_ungot = EOF; struct __SEGGER_RTL_FILE_impl { /* NOTE: Provides implementation for FILE */ @@ -59,14 +59,12 @@ FILE *stdin = &__SEGGER_RTL_stdin_file; /* NOTE: Provide implementation of std FILE *stdout = &__SEGGER_RTL_stdout_file; /* NOTE: Provide implementation of stdout for RTL. */ FILE *stderr = &__SEGGER_RTL_stderr_file; /* NOTE: Provide implementation of stderr for RTL. */ -int __SEGGER_RTL_X_file_write(__SEGGER_RTL_FILE *file, const char *data, unsigned size) +int __SEGGER_RTL_X_file_write(__SEGGER_RTL_FILE *file, const char *data, unsigned int size) { int count; (void)file; - for(count = 0; count < size; count++) - { - if (data[count] == '\n') - { + for (count = 0; count < size; count++) { + if (data[count] == '\n') { while (status_success != uart_send_byte(g_console_uart, '\r')) { } } @@ -79,7 +77,7 @@ int __SEGGER_RTL_X_file_write(__SEGGER_RTL_FILE *file, const char *data, unsigne } -int __SEGGER_RTL_X_file_read(__SEGGER_RTL_FILE *file, char *s, unsigned size) +int __SEGGER_RTL_X_file_read(__SEGGER_RTL_FILE *file, char *s, unsigned int size) { (void)file; while (status_success != uart_receive_byte(g_console_uart, (uint8_t *)s)) { @@ -122,10 +120,8 @@ int _write(int file, char *data, int size) { int count; (void)file; - for(count = 0; count < size; count++) - { - if (data[count] == '\n') - { + for (count = 0; count < size; count++) { + if (data[count] == '\n') { while (status_success != uart_send_byte(g_console_uart, '\r')) { } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h index 08ab66503b..d625285404 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,15 +7,12 @@ #ifndef _HPM_DEBUG_CONSOLE_H #define _HPM_DEBUG_CONSOLE_H -#include #include "hpm_common.h" -typedef enum console_type { - console_type_uart = 0, -} console_type_t; +#define CONSOLE_TYPE_UART 0 typedef struct { - console_type_t type; + uint32_t type; uint32_t base; uint32_t src_freq_in_hz; uint32_t baudrate; diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c index 1174bd6391..699f55b3b6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,7 +8,6 @@ #include #include "hpm_dma_manager.h" #include "hpm_soc.h" -#include /***************************************************************************************************************** * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h index 6d5ada4548..e7839dd1e3 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,7 +9,11 @@ #define HPM_DMA_MANAGER_H #include "hpm_common.h" +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_soc_feature.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c index 5805e3d516..3721029820 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c @@ -1,69 +1,69 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_dp83848_regs.h" #include "hpm_dp83848.h" -#include "board.h" - -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Internal API - *---------------------------------------------------------------------*/ -static bool dp83848_id_check(ENET_Type *ptr) + *--------------------------------------------------------------------- + */ +static bool dp83848_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_PHYID2); + id1 = enet_read_phy(ptr, DP83848_ADDR, DP83848_PHYIDR1); + id2 = enet_read_phy(ptr, DP83848_ADDR, DP83848_PHYIDR2); - if (DP83848_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && DP83848_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (DP83848_PHYIDR1_OUI_MSB_GET(id1) == DP83848_ID1 && DP83848_PHYIDR2_OUI_LSB_GET(id2) == DP83848_ID2) { return true; } else { return false; } } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t dp83848_register_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void dp83848_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, DP83848_REG_BMCR, DP83848_BMCR_RESET_SET(1)); + enet_write_phy(ptr, DP83848_ADDR, DP83848_BMCR, DP83848_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_BMCR); + data = enet_read_phy(ptr, DP83848_ADDR, DP83848_BMCR); } while (DP83848_BMCR_RESET_GET(data)); } void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config) { - config->loopback = 1; /* Enable PCS loopback mode */ - config->speed = 2; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = false; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = true; /* Enable Auto-Negotiation */ + #endif } bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= DP83848_BMCR_RESET_SET(0) /* Normal operation */ + data |= DP83848_BMCR_RESET_SET(0) /* Normal operation */ | DP83848_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ | DP83848_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ | DP83848_BMCR_PWD_SET(0) /* Normal operation */ @@ -71,22 +71,27 @@ bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config) | DP83848_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ | DP83848_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ - if (config->auto_negotiation == 0) { - para |= DP83848_BMCR_SPEED0_SET(config->speed) | DP83848_BMCR_SPEED1_SET(config->speed >> 1); + if (config->auto_negotiation == false) { + data |= DP83848_BMCR_SPEED0_SET(config->speed); /* Set port speed */ + data |= DP83848_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } /* check the id of dp83848 */ - if (dp83848_id_check(ptr) == false) { + if (dp83848_check_id(ptr) == false) { return false; } - para = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_BMCR) & ~ DP83848_BMCR_SPEED0_MASK; - enet_write_phy(ptr, PHY_ADDR, DP83848_REG_BMCR, para); + enet_write_phy(ptr, DP83848_ADDR, DP83848_BMCR, data); return true; } - -void dp83848_init_auto_negotiation(void) +void dp83848_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { + uint16_t data; + + data = enet_read_phy(ptr, DP83848_ADDR, DP83848_PHYSTS); + status->enet_phy_link = DP83848_PHYSTS_LINK_STATUS_GET(data); + status->enet_phy_speed = DP83848_PHYSTS_SPEED_STATUS_GET(data) ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; + status->enet_phy_duplex = DP83848_PHYSTS_DUPLEX_STATUS_GET(data); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h index e19f70b12a..d00d57e686 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,44 +8,48 @@ #ifndef HPM_DP83848_H #define HPM_DP83848_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- * Macro Const Definitions - *---------------------------------------------------------------------*/ -#define PHY_ADDR (1U) -#define PHY_ID1 (0x2000U) -#define PHY_ID2 (0x17U) + *--------------------------------------------------------------------- + */ +#ifndef DP83848_ADDR +#define DP83848_ADDR (1U) +#endif -/*---------------------------------------------------------------------* +#define DP83848_ID1 (0x2000U) +#define DP83848_ID2 (0x17U) + +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; } dp83848_config_t; #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t dp83848_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void dp83848_reset(ENET_Type *ptr); void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config); bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config); -void dp83848_read_status(ENET_Type *ptr); -void dp83848_control_config(ENET_Type *ptr); -void dp83867_ctl_config(ENET_Type *ptr); -void dp83867_bist_config(ENET_Type *ptr); +void dp83848_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_DP83848_H */ \ No newline at end of file +#endif /* HPM_DP83848_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h index b8483f6374..e99228e847 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h @@ -1,212 +1,1524 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#ifndef HPM_RTL83848_REGS_H -#define HPM_RTL83848_REGS_H - /* RTL Register Definitions */ -#define DP83848_REG_BMCR (0U) /* Basic Mode Control Register */ -#define DP83848_REG_BMSR (1U) /* Basic Mode Status Register */ -#define DP83848_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define DP83848_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define DP83848_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define DP83848_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define DP83848_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ -#define DP83848_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ -#define DP83848_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ -#define DP83848_REG_GBCR (9U) /* 1000Base-T Control Register */ -#define DP83848_REG_GBSR (10U) /* 1000Base-T Status Register */ +#ifndef HPM_DP83848_REGS_H +#define HPM_DP83848_REGS_H -#define DP83848_REG_MACR (13U) /* MMD Access Control Register */ -#define DP83848_REG_MAADR (14U) /* MMD Access Address Data Register */ -#define DP83848_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ -#define DP83848_REG_PHYCR (16U) /* PHY Specific Control Register */ -#define DP83848_REG_PHYSR (17U) /* PHY Specific Status Register */ -#define DP83848_REG_INER (18U) /* Interrupt Enable Register */ -#define DP83848_REG_INSR (19U) /* Interrupt Status Register */ -#define DP83848_REG_RXERC (24U) /* Receive Error Counter */ -#define DP83848_REG_PAGSEL (31U) /* Page Select Register */ +typedef enum { + DP83848_BMCR = 0, /* 0x0: Basic Mode Control Register */ + DP83848_BMSR = 1, /* 0x1: Basic Mode Status Register */ + DP83848_PHYIDR1 = 2, /* 0x2: PHY Identifier Register #1 */ + DP83848_PHYIDR2 = 3, /* 0x3: PHY Identifier Register #2 */ + DP83848_ANAR = 4, /* 0x4: Auto-Negotiation Advertisement Register */ + DP83848_ANLPAR_BP = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */ + DP83848_ANER = 6, /* 0x6: Auto-Negotiate Expansion Register */ + DP83848_ANNPTR = 7, /* 0x7: Auto-Negotiation Next Page Transmit Register */ + DP83848_PHYSTS = 16, /* 0x10: PHY Status Register */ + DP83848_FCSCR = 20, /* 0x14: False Carrier Sense Counter Register */ + DP83848_RECR = 21, /* 0x15: Receiver Error Counter Register */ + DP83848_PCSR = 22, /* 0x16: 100 Mb/s PCS Configuration and Status Register */ + DP83848_RBR = 23, /* 0x17: RMII and Bypass Register */ + DP83848_LEDCR = 24, /* 0x18: LED Direct Control Register */ + DP83848_PHYCR = 25, /* 0x19: PHY Control Register */ + DP83848_10BTSCR = 26, /* 0x1A: 10BASE-T Status/Control Register */ + DP83848_CDCTRL1 = 27, /* 0x1B: CD Test and BIST Extensions Register */ + DP83848_EDCR = 29, /* 0x1D: Energy Detect Control */ +} DP83848_REG_Type; -/* RTL MMD Register Definitions */ -#define DP83848_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define DP83848_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define DP83848_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define DP83848_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define DP83848_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define DP83848_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ - -#define DP83867_REGCR_FUNCTION_ADDR (0 << 14) -#define DP83867_REGCR_FUNCTION_DATA (1 << 14) -#define DP83867_REGCR_DEVAD (0x1f) /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * - * 1: PHY reset - * 0: Normal operation - * Register 0 (BMCR) and register 1 (BMSR) will return to default - * values after a software reset (set Bit15 to 1). - * This action may change the internal PHY state and the state of the - * physical link associated with the PHY. + * Reset: + * 1 = Initiate software Reset / Reset in Process. + * 0 = Normal operation. + * This bit, which is self-clearing, returns a value of one until the reset process is complete. The + * configuration is re-strapped. */ -#define DP83848_BMCR_RESET_MASK (0x8000U) +#define DP83848_BMCR_RESET_MASK (0x8000U) #define DP83848_BMCR_RESET_SHIFT (15U) -#define DP83848_BMCR_RESET_SET(x) (((uint32_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK) -#define DP83848_BMCR_RESET_GET(x) (((uint32_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT) +#define DP83848_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK) +#define DP83848_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * - * Loopback Mode. - * 1: Enable PCS loopback mode - * 0: Disable PCS loopback mode + * Loopback: + * 1 = Loopback enabled. + * 0 = Normal operation. + * The loopback function enables MII transmit data to be routed to the MII receive data path. + * Setting this bit may cause the descrambler to lose synchronization and produce a 500 µs “dead + * time” before any valid data will appear at the MII receive outputs. */ -#define DP83848_BMCR_LOOPBACK_MASK (0x4000U) +#define DP83848_BMCR_LOOPBACK_MASK (0x4000U) #define DP83848_BMCR_LOOPBACK_SHIFT (14U) -#define DP83848_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK) -#define DP83848_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT) +#define DP83848_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK) +#define DP83848_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * Speed Select: + * When auto-negotiation is disabled writing to this bit allows the port speed to be selected. + * 1 = 100 Mb/s. + * 0 = 10 Mb/s. */ -#define DP83848_BMCR_SPEED0_MASK (0x2000U) +#define DP83848_BMCR_SPEED0_MASK (0x2000U) #define DP83848_BMCR_SPEED0_SHIFT (13U) -#define DP83848_BMCR_SPEED0_SET(x) (((uint32_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK) -#define DP83848_BMCR_SPEED0_GET(x) (((uint32_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT) +#define DP83848_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK) +#define DP83848_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT) /* * ANE (RW) * - * Auto-Negotiation Enable. - * 1: Enable Auto-Negotiation - * 0: Disable Auto-Negotiation + * Auto-Negotiation Enable: + * Strap controls initial value at reset. + * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. + * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. */ -#define DP83848_BMCR_ANE_MASK (0x1000U) +#define DP83848_BMCR_ANE_MASK (0x1000U) #define DP83848_BMCR_ANE_SHIFT (12U) -#define DP83848_BMCR_ANE_SET(x) (((uint32_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK) -#define DP83848_BMCR_ANE_GET(x) (((uint32_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT) +#define DP83848_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK) +#define DP83848_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT) /* * PWD (RW) * - * Power Down. - * 1: Power down (only Management Interface and logic are active; link - * is down) - * 0: Normal operation + * Power Down: + * 1 = Power down. + * 0 = Normal operation. + * Setting this bit powers down the PHY. Only the register block is enabled during a power-down + * condition. */ -#define DP83848_BMCR_PWD_MASK (0x0800U) +#define DP83848_BMCR_PWD_MASK (0x800U) #define DP83848_BMCR_PWD_SHIFT (11U) -#define DP83848_BMCR_PWD_SET(x) (((uint32_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK) -#define DP83848_BMCR_PWD_GET(x) (((uint32_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT) +#define DP83848_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK) +#define DP83848_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * - * Isolate. - * 1: RGMII/GMII interface is isolated; the serial management interface - * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. - * 0: Normal operation + * Isolate: + * 1 = Isolates the Port from the MII with the exception of the serial management. + * 0 = Normal operation. */ -#define DP83848_BMCR_ISOLATE_MASK (0x0400U) +#define DP83848_BMCR_ISOLATE_MASK (0x400U) #define DP83848_BMCR_ISOLATE_SHIFT (10U) -#define DP83848_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK) -#define DP83848_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT) +#define DP83848_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK) +#define DP83848_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * - * Restart Auto-Negotiation. - * 1: Restart Auto-Negotiation - * 0: Normal operation + * Restart Auto-Negotiation: + * 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is + * disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until + * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation + * process is not affected by the management entity clearing this bit. + * 0 = Normal operation. */ -#define DP83848_BMCR_RESTART_AN_MASK (0x0200U) +#define DP83848_BMCR_RESTART_AN_MASK (0x200U) #define DP83848_BMCR_RESTART_AN_SHIFT (9U) -#define DP83848_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK) -#define DP83848_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT) +#define DP83848_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK) +#define DP83848_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (RW) * - * Duplex Mode. - * 1: Full Duplex operation - * 0: Half Duplex operation - * This bit is valid only in force mode, i.e., NWay is disabled. + * Duplex Mode: + * When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be + * selected. + * 1 = Full Duplex operation. + * 0 = Half Duplex operation. */ -#define DP83848_BMCR_DUPLEX_MASK (0x0100U) +#define DP83848_BMCR_DUPLEX_MASK (0x100U) #define DP83848_BMCR_DUPLEX_SHIFT (8U) -#define DP83848_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK) -#define DP83848_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT) +#define DP83848_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK) +#define DP83848_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * - * Collision Test. - * 1: Collision test enabled - * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. + * Collision Test: + * 1 = Collision test enabled. + * 0 = Normal operation. + * When set, this bit will cause the COL signal to be asserted in response to the assertion of + * TX_EN within 512-bit times. The COL signal will be deasserted within 4-bit times in response to + * the deassertion of TX_EN. */ -#define DP83848_BMCR_COLLISION_TEST_MASK (0x0080U) +#define DP83848_BMCR_COLLISION_TEST_MASK (0x80U) #define DP83848_BMCR_COLLISION_TEST_SHIFT (7U) -#define DP83848_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK) -#define DP83848_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT) +#define DP83848_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK) +#define DP83848_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT) + +/* Bitfield definition for register: BMSR */ +/* + * 100BASE_TX_FULL_DUPLEX (RO) + * + * 100BASE-TX Full Duplex Capable: + * 1 = Device able to perform 100BASE-TX in full duplex mode. + */ +#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U) +#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U) +#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT) /* - * Speed[1] (RW) + * 100BASE_TX_HALF (RO) * - * Speed Select Bit 1. - * Refer to bit 0.13. + * 100BASE-TX Half Duplex Capable: + * 1 = Device able to perform 100BASE-TX in half duplex mode. */ -#define DP83848_BMCR_SPEED1_MASK (0x0040U) -#define DP83848_BMCR_SPEED1_SHIFT (6U) -#define DP83848_BMCR_SPEED1_SET(x) (((uint32_t)(x) << DP83848_BMCR_SPEED1_SHIFT) & DP83848_BMCR_SPEED1_MASK) -#define DP83848_BMCR_SPEED1_GET(x) (((uint32_t)(x) & DP83848_BMCR_SPEED1_MASK) >> DP83848_BMCR_SPEED1_SHIFT) +#define DP83848_BMSR_100BASE_TX_HALF_MASK (0x2000U) +#define DP83848_BMSR_100BASE_TX_HALF_SHIFT (13U) +#define DP83848_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_HALF_MASK) >> DP83848_BMSR_100BASE_TX_HALF_SHIFT) -/* Bitfield definition for register: PHYID1 */ +/* + * 10BASE_T_FULL_DUPLEX (RO) + * + * 10BASE-T Full Duplex Capable: + * 1 = Device able to perform 10BASE-T in full duplex mode. + */ +#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK (0x1000U) +#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT (12U) +#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT) + +/* + * 10BASE_T_HALF_DUPLEX (RO) + * + * 10BASE-T Half Duplex Capable: + * 1 = Device able to perform 10BASE-T in half duplex mode. + */ +#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK (0x800U) +#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT (11U) +#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT) + +/* + * MF_PREAMBLE_SUPPRESSION (RO) + * + * Preamble suppression Capable: + * 1 = Device able to perform management transaction with preamble suppressed, 32-bits of + * preamble needed only once after reset, invalid opcode or invalid turnaround. + * 0 = Normal management operation. + */ +#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * Auto-Negotiation Complete: + * 1 = Auto-Negotiation process complete. + * 0 = Auto-Negotiation process not complete. + */ +#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RO) + * + * Remote Fault: + * 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Notification from + * Link Partner of Remote Fault. + * 0 = No remote fault condition detected. + */ +#define DP83848_BMSR_REMOTE_FAULT_MASK (0x10U) +#define DP83848_BMSR_REMOTE_FAULT_SHIFT (4U) +#define DP83848_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_BMSR_REMOTE_FAULT_MASK) >> DP83848_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY (RO) + * + * Auto Negotiation Ability: + * 1 = Device is able to perform Auto-Negotiation. + * 0 = Device is not able to perform Auto-Negotiation. + */ +#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status: + * 1 = Valid link established (for either 10 or 100 Mb/s operation). + * 0 = Link not established. + * The criteria for link validity is implementation specific. The occurrence of a link failure condition + * will causes the Link Status bit to clear. Once cleared, this bit may only be set by establishing a + * good link condition and a read through the management interface. + */ +#define DP83848_BMSR_LINK_STATUS_MASK (0x4U) +#define DP83848_BMSR_LINK_STATUS_SHIFT (2U) +#define DP83848_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_BMSR_LINK_STATUS_MASK) >> DP83848_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * Jabber Detect: This bit only has meaning in 10 Mb/s mode. + * 1 = Jabber condition detected. + * 0 = No Jabber. + * This bit is implemented with a latching function, such that the occurrence of a jabber condition + * causes it to set until it is cleared by a read to this register by the management interface or by a + * reset. + */ +#define DP83848_BMSR_JABBER_DETECT_MASK (0x2U) +#define DP83848_BMSR_JABBER_DETECT_SHIFT (1U) +#define DP83848_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_BMSR_JABBER_DETECT_MASK) >> DP83848_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO) + * + * Extended Capability: + * 1 = Extended register capabilities. + * 0 = Basic register set capabilities only. + */ +#define DP83848_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define DP83848_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT) + +/* Bitfield definition for register: PHYIDR1 */ /* * OUI_MSB (RO) * - * Organizationally Unique Identifier Bit 3:18. - * Always 0000000000011100. + * OUI Most Significant Bits: + * Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most + * significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and + * 2). */ -#define DP83848_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define DP83848_PHYID1_OUI_MSB_SHIFT (0U) -#define DP83848_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & DP83848_PHYID1_OUI_MSB_MASK) >> DP83848_PHYID1_OUI_MSB_SHIFT) +#define DP83848_PHYIDR1_OUI_MSB_MASK (0xFFFFU) +#define DP83848_PHYIDR1_OUI_MSB_SHIFT (0U) +#define DP83848_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR1_OUI_MSB_MASK) >> DP83848_PHYIDR1_OUI_MSB_SHIFT) -/* Bitfield definition for register: PHYID2 */ +/* Bitfield definition for register: PHYIDR2 */ /* * OUI_LSB (RO) * - * Organizationally Unique Identifier Bit 19:24. - * Always 110010. + * OUI Least Significant Bits: + * Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register + * respectively. */ -#define DP83848_PHYID2_OUI_MSB_MASK (0xFC00U) -#define DP83848_PHYID2_OUI_MSB_SHIFT (10U) -#define DP83848_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & DP83848_PHYID2_OUI_MSB_MASK) >> DP83848_PHYID2_OUI_MSB_SHIFT) +#define DP83848_PHYIDR2_OUI_LSB_MASK (0xFC00U) +#define DP83848_PHYIDR2_OUI_LSB_SHIFT (10U) +#define DP83848_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_OUI_LSB_MASK) >> DP83848_PHYIDR2_OUI_LSB_SHIFT) -/* Bitfield definition for register: RGMIICTL */ /* - * RGMII_EN (RW) + * VNDR_MDL (RO) * - * RGMII Enable: - * 1 = Enable RGMII interface. - * 0 = Disable RGMII interface + * Vendor Model Number: + * The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit + * 9). */ -#define DP83867_RGMIICTL_RGMII_EN_MASK (0x80) -#define DP83867_RGMIICTL_RGMII_EN_SHIFT (7U) -#define DP83867_RGMIICTL_RGMII_EN_SET(x) (((uint32_t)(x) << DP83867_RGMIICTL_RGMII_EN_SHIFT) & DP83867_RGMIICTL_RGMII_EN_MASK) -#define DP83867_RGMIICTL_RGMII_EN_GET(x) (((uint32_t)(x) & DP83867_RGMIICTL_RGMII_EN_SHIFT) >> DP83867_RGMIICTL_RGMII_EN_MASK) -#endif /* HPM_DP83848_REGS_H */ \ No newline at end of file +#define DP83848_PHYIDR2_VNDR_MDL_MASK (0x3F0U) +#define DP83848_PHYIDR2_VNDR_MDL_SHIFT (4U) +#define DP83848_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_VNDR_MDL_MASK) >> DP83848_PHYIDR2_VNDR_MDL_SHIFT) + +/* + * MDL_REV (RO) + * + * Model Revision Number: + * Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant + * bit to bit 3). This field will be incremented for all major device changes. + */ +#define DP83848_PHYIDR2_MDL_REV_MASK (0xFU) +#define DP83848_PHYIDR2_MDL_REV_SHIFT (0U) +#define DP83848_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_MDL_REV_MASK) >> DP83848_PHYIDR2_MDL_REV_SHIFT) + +/* Bitfield definition for register: ANAR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = Next Page Transfer not desired. + * 1 = Next Page Transfer desired. + */ +#define DP83848_ANAR_NP_MASK (0x8000U) +#define DP83848_ANAR_NP_SHIFT (15U) +#define DP83848_ANAR_NP_SET(x) (((uint16_t)(x) << DP83848_ANAR_NP_SHIFT) & DP83848_ANAR_NP_MASK) +#define DP83848_ANAR_NP_GET(x) (((uint16_t)(x) & DP83848_ANAR_NP_MASK) >> DP83848_ANAR_NP_SHIFT) + +/* + * RF (RW) + * + * Remote Fault: + * 1 = Advertises that this device has detected a Remote Fault. + * 0 = No Remote Fault detected. + */ +#define DP83848_ANAR_RF_MASK (0x2000U) +#define DP83848_ANAR_RF_SHIFT (13U) +#define DP83848_ANAR_RF_SET(x) (((uint16_t)(x) << DP83848_ANAR_RF_SHIFT) & DP83848_ANAR_RF_MASK) +#define DP83848_ANAR_RF_GET(x) (((uint16_t)(x) & DP83848_ANAR_RF_MASK) >> DP83848_ANAR_RF_SHIFT) + +/* + * ASM_DIR (RW) + * + * Asymmetric PAUSE Support for Full Duplex Links: + * The ASM_DIR bit indicates that asymmetric PAUSE is supported. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and + * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer + * and the pause function as specified in clause 31 and annex 31B of 802.3. + * 0= No MAC based full duplex flow control. + */ +#define DP83848_ANAR_ASM_DIR_MASK (0x800U) +#define DP83848_ANAR_ASM_DIR_SHIFT (11U) +#define DP83848_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83848_ANAR_ASM_DIR_SHIFT) & DP83848_ANAR_ASM_DIR_MASK) +#define DP83848_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANAR_ASM_DIR_MASK) >> DP83848_ANAR_ASM_DIR_SHIFT) + +/* + * PAUSE (RW) + * + * PAUSE Support for Full Duplex Links: + * The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE + * functions as defined in Annex 31B. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and + * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer + * and the pause function as specified in clause 31 and annex 31B of 802.3. + * 0= No MAC based full duplex flow control. + */ +#define DP83848_ANAR_PAUSE_MASK (0x400U) +#define DP83848_ANAR_PAUSE_SHIFT (10U) +#define DP83848_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83848_ANAR_PAUSE_SHIFT) & DP83848_ANAR_PAUSE_MASK) +#define DP83848_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANAR_PAUSE_MASK) >> DP83848_ANAR_PAUSE_SHIFT) + +/* + * T4 (RO) + * + * 100BASE-T4 Support: + * 1= 100BASE-T4 is supported by the local device. + * 0 = 100BASE-T4 not supported. + */ +#define DP83848_ANAR_T4_MASK (0x200U) +#define DP83848_ANAR_T4_SHIFT (9U) +#define DP83848_ANAR_T4_GET(x) (((uint16_t)(x) & DP83848_ANAR_T4_MASK) >> DP83848_ANAR_T4_SHIFT) + +/* + * TX_FD (RW) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the local device. + * 0 = 100BASE-TX Full Duplex not supported. + */ +#define DP83848_ANAR_TX_FD_MASK (0x100U) +#define DP83848_ANAR_TX_FD_SHIFT (8U) +#define DP83848_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_FD_SHIFT) & DP83848_ANAR_TX_FD_MASK) +#define DP83848_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_FD_MASK) >> DP83848_ANAR_TX_FD_SHIFT) + +/* + * TX (RW) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the local device. + * 0 = 100BASE-TX not supported. + */ +#define DP83848_ANAR_TX_MASK (0x80U) +#define DP83848_ANAR_TX_SHIFT (7U) +#define DP83848_ANAR_TX_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_SHIFT) & DP83848_ANAR_TX_MASK) +#define DP83848_ANAR_TX_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_MASK) >> DP83848_ANAR_TX_SHIFT) + +/* + * 10_FD (RW) + * + * 10BASE-T Full Duplex Support: + * 1 = 10BASE-T Full Duplex is supported by the local device. + * 0 = 10BASE-T Full Duplex not supported. + */ +#define DP83848_ANAR_10_FD_MASK (0x40U) +#define DP83848_ANAR_10_FD_SHIFT (6U) +#define DP83848_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_FD_SHIFT) & DP83848_ANAR_10_FD_MASK) +#define DP83848_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_FD_MASK) >> DP83848_ANAR_10_FD_SHIFT) + +/* + * 10 (RW) + * + * 10BASE-T Support: + * 1 = 10BASE-T is supported by the local device. + * 0 = 10BASE-T not supported. + */ +#define DP83848_ANAR_10_MASK (0x20U) +#define DP83848_ANAR_10_SHIFT (5U) +#define DP83848_ANAR_10_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_SHIFT) & DP83848_ANAR_10_MASK) +#define DP83848_ANAR_10_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_MASK) >> DP83848_ANAR_10_SHIFT) + +/* + * SELECTOR (RW) + * + * Protocol Selection Bits: + * These bits contain the binary encoded protocol selector supported by this port. <00001> + * indicates that this device supports IEEE 802.3. + */ +#define DP83848_ANAR_SELECTOR_MASK (0x1FU) +#define DP83848_ANAR_SELECTOR_SHIFT (0U) +#define DP83848_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83848_ANAR_SELECTOR_SHIFT) & DP83848_ANAR_SELECTOR_MASK) +#define DP83848_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANAR_SELECTOR_MASK) >> DP83848_ANAR_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANLPAR_BP */ +/* + * NP (RO) + * + * Next Page Indication: + * 0 = Link Partner does not desire Next Page Transfer. + * 1 = Link Partner desires Next Page Transfer. + */ +#define DP83848_ANLPAR_BP_NP_MASK (0x8000U) +#define DP83848_ANLPAR_BP_NP_SHIFT (15U) +#define DP83848_ANLPAR_BP_NP_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_NP_MASK) >> DP83848_ANLPAR_BP_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Link Partner acknowledges reception of the ability data word. + * 0 = Not acknowledged. + * The Auto-Negotiation state machine will automatically control the this bit based on the incoming + * FLP bursts. + */ +#define DP83848_ANLPAR_BP_ACK_MASK (0x4000U) +#define DP83848_ANLPAR_BP_ACK_SHIFT (14U) +#define DP83848_ANLPAR_BP_ACK_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ACK_MASK) >> DP83848_ANLPAR_BP_ACK_SHIFT) + +/* + * RF (RO) + * + * Remote Fault: + * 1 = Remote Fault indicated by Link Partner. + * 0 = No Remote Fault indicated by Link Partner. + */ +#define DP83848_ANLPAR_BP_RF_MASK (0x2000U) +#define DP83848_ANLPAR_BP_RF_SHIFT (13U) +#define DP83848_ANLPAR_BP_RF_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_RF_MASK) >> DP83848_ANLPAR_BP_RF_SHIFT) + +/* + * ASM_DIR (RO) + * + * ASYMMETRIC PAUSE: + * 1 = Asymmetric pause is supported by the Link Partner. + * 0 = Asymmetric pause is not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_ASM_DIR_MASK (0x800U) +#define DP83848_ANLPAR_BP_ASM_DIR_SHIFT (11U) +#define DP83848_ANLPAR_BP_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ASM_DIR_MASK) >> DP83848_ANLPAR_BP_ASM_DIR_SHIFT) + +/* + * PAUSE (RO) + * + * PAUSE: + * 1 = Pause function is supported by the Link Partner. + * 0 = Pause function is not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_PAUSE_MASK (0x400U) +#define DP83848_ANLPAR_BP_PAUSE_SHIFT (10U) +#define DP83848_ANLPAR_BP_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_PAUSE_MASK) >> DP83848_ANLPAR_BP_PAUSE_SHIFT) + +/* + * T4 (RO) + * + * 100BASE-T4 Support: + * 1 = 100BASE-T4 is supported by the Link Partner. + * 0 = 100BASE-T4 not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_T4_MASK (0x200U) +#define DP83848_ANLPAR_BP_T4_SHIFT (9U) +#define DP83848_ANLPAR_BP_T4_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_T4_MASK) >> DP83848_ANLPAR_BP_T4_SHIFT) + +/* + * TX_FD (RO) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the Link Partner. + * 0 = 100BASE-TX Full Duplex not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_TX_FD_MASK (0x100U) +#define DP83848_ANLPAR_BP_TX_FD_SHIFT (8U) +#define DP83848_ANLPAR_BP_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_FD_MASK) >> DP83848_ANLPAR_BP_TX_FD_SHIFT) + +/* + * TX (RO) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the Link Partner. + * 0 = 100BASE-TX not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_TX_MASK (0x80U) +#define DP83848_ANLPAR_BP_TX_SHIFT (7U) +#define DP83848_ANLPAR_BP_TX_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_MASK) >> DP83848_ANLPAR_BP_TX_SHIFT) + +/* + * 10_FD (RO) + * + * 10BASE-T Full Duplex Support: + * 1 = 10BASE-T Full Duplex is supported by the Link Partner. + * 0 = 10BASE-T Full Duplex not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_10_FD_MASK (0x40U) +#define DP83848_ANLPAR_BP_10_FD_SHIFT (6U) +#define DP83848_ANLPAR_BP_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_FD_MASK) >> DP83848_ANLPAR_BP_10_FD_SHIFT) + +/* + * 10 (RO) + * + * 10BASE-T Support: + * 1 = 10BASE-T is supported by the Link Partner. + * 0 = 10BASE-T not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_10_MASK (0x20U) +#define DP83848_ANLPAR_BP_10_SHIFT (5U) +#define DP83848_ANLPAR_BP_10_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_MASK) >> DP83848_ANLPAR_BP_10_SHIFT) + +/* + * SELECTOR (RO) + * + * Protocol Selection Bits: + * Link Partner’s binary encoded protocol selector. + */ +#define DP83848_ANLPAR_BP_SELECTOR_MASK (0x1FU) +#define DP83848_ANLPAR_BP_SELECTOR_SHIFT (0U) +#define DP83848_ANLPAR_BP_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_SELECTOR_MASK) >> DP83848_ANLPAR_BP_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANER */ +/* + * PDF (RO) + * + * Parallel Detection Fault: + * 1 = A fault has been detected through the Parallel Detection function. + * 0 = A fault has not been detected. + */ +#define DP83848_ANER_PDF_MASK (0x10U) +#define DP83848_ANER_PDF_SHIFT (4U) +#define DP83848_ANER_PDF_GET(x) (((uint16_t)(x) & DP83848_ANER_PDF_MASK) >> DP83848_ANER_PDF_SHIFT) + +/* + * LP_NP_ABLE (RO) + * + * Link Partner Next Page Able: + * 1 = Link Partner does support Next Page. + * 0 = Link Partner does not support Next Page. + */ +#define DP83848_ANER_LP_NP_ABLE_MASK (0x8U) +#define DP83848_ANER_LP_NP_ABLE_SHIFT (3U) +#define DP83848_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_NP_ABLE_MASK) >> DP83848_ANER_LP_NP_ABLE_SHIFT) + +/* + * NP_ABLE (RO) + * + * Next Page Able: + * 1 = Indicates local device is able to send additional “Next Pages”. + */ +#define DP83848_ANER_NP_ABLE_MASK (0x4U) +#define DP83848_ANER_NP_ABLE_SHIFT (2U) +#define DP83848_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_NP_ABLE_MASK) >> DP83848_ANER_NP_ABLE_SHIFT) + +/* + * PAGE_RX (RO) + * + * Link Code Word Page Received: + * 1 = Link Code Word has been received, cleared on a read. + * 0 = Link Code Word has not been received. + */ +#define DP83848_ANER_PAGE_RX_MASK (0x2U) +#define DP83848_ANER_PAGE_RX_SHIFT (1U) +#define DP83848_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83848_ANER_PAGE_RX_MASK) >> DP83848_ANER_PAGE_RX_SHIFT) + +/* + * LP_AN_ABLE (RO) + * + * Link Partner Auto-Negotiation Able: + * 1 = indicates that the Link Partner supports Auto-Negotiation. + * 0 = indicates that the Link Partner does not support Auto-Negotiation. + */ +#define DP83848_ANER_LP_AN_ABLE_MASK (0x1U) +#define DP83848_ANER_LP_AN_ABLE_SHIFT (0U) +#define DP83848_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_AN_ABLE_MASK) >> DP83848_ANER_LP_AN_ABLE_SHIFT) + +/* Bitfield definition for register: ANNPTR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = No other Next Page Transfer desired. + * 1 = Another Next Page desired. + */ +#define DP83848_ANNPTR_NP_MASK (0x8000U) +#define DP83848_ANNPTR_NP_SHIFT (15U) +#define DP83848_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_NP_SHIFT) & DP83848_ANNPTR_NP_MASK) +#define DP83848_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_NP_MASK) >> DP83848_ANNPTR_NP_SHIFT) + +/* + * MP (RW) + * + * Message Page: + * 1 = Message Page. + * 0 = Unformatted Page. + */ +#define DP83848_ANNPTR_MP_MASK (0x2000U) +#define DP83848_ANNPTR_MP_SHIFT (13U) +#define DP83848_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_MP_SHIFT) & DP83848_ANNPTR_MP_MASK) +#define DP83848_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_MP_MASK) >> DP83848_ANNPTR_MP_SHIFT) + +/* + * ACK2 (RW) + * + * Acknowledge2: + * 1 = Will comply with message. + * 0 = Cannot comply with message. + * Acknowledge2 is used by the next page function to indicate that Local Device has the ability + * to comply with the message received. + */ +#define DP83848_ANNPTR_ACK2_MASK (0x1000U) +#define DP83848_ANNPTR_ACK2_SHIFT (12U) +#define DP83848_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_ACK2_SHIFT) & DP83848_ANNPTR_ACK2_MASK) +#define DP83848_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_ACK2_MASK) >> DP83848_ANNPTR_ACK2_SHIFT) + +/* + * TOG_TX (RW) + * + * Toggle: + * 1 = Value of toggle bit in previously transmitted Link Code Word was 0. + * 0 = Value of toggle bit in previously transmitted Link Code Word was 1. + * Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization + * with the Link Partner during Next Page exchange. This bit shall always take the opposite + * value of the Toggle bit in the previously exchanged Link Code Word. + */ +#define DP83848_ANNPTR_TOG_TX_MASK (0x800U) +#define DP83848_ANNPTR_TOG_TX_SHIFT (11U) +#define DP83848_ANNPTR_TOG_TX_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_TOG_TX_SHIFT) & DP83848_ANNPTR_TOG_TX_MASK) +#define DP83848_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_TOG_TX_MASK) >> DP83848_ANNPTR_TOG_TX_SHIFT) + +/* + * CODE (RW) + * + * This field represents the code field of the next page transmission. If the MP bit is set (bit 13 + * of this register), then the code shall be interpreted as a "Message Page”, as defined in annex + * 28C of IEEE 802.3. Otherwise, the code shall be interpreted as an "Unformatted Page”, and + * the interpretation is application specific. + * The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE + * 802.3. + */ +#define DP83848_ANNPTR_CODE_MASK (0x400U) +#define DP83848_ANNPTR_CODE_SHIFT (10U) +#define DP83848_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_CODE_SHIFT) & DP83848_ANNPTR_CODE_MASK) +#define DP83848_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_CODE_MASK) >> DP83848_ANNPTR_CODE_SHIFT) + +/* Bitfield definition for register: PHYSTS */ +/* + * MDI_X_MODE (RO) + * + * MDI-X mode as reported by the Auto-Negotiation logic: + * This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the + * PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as + * the Auto-MDIX algorithm swaps between MDI and MDI-X configurations. + * 1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair) + * 0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair) + */ +#define DP83848_PHYSTS_MDI_X_MODE_MASK (0x4000U) +#define DP83848_PHYSTS_MDI_X_MODE_SHIFT (14U) +#define DP83848_PHYSTS_MDI_X_MODE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_MDI_X_MODE_MASK) >> DP83848_PHYSTS_MDI_X_MODE_SHIFT) + +/* + * RECEIVE_ERRORLATCH (RO) + * + * Receive Error Latch: + * This bit will be cleared upon a read of the RECR register. + * 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0). + * 0 = No receive error event has occurred. + */ +#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK (0x2000U) +#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT (13U) +#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK) >> DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT) + +/* + * POLARITY_STATUS (RO) + * + * Polarity Status: + * This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read + * of the 10BTSCR register, but not upon a read of the PHYSTS register. + * 1 = Inverted Polarity detected. + * 0 = Correct Polarity detected. + */ +#define DP83848_PHYSTS_POLARITY_STATUS_MASK (0x1000U) +#define DP83848_PHYSTS_POLARITY_STATUS_SHIFT (12U) +#define DP83848_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_POLARITY_STATUS_MASK) >> DP83848_PHYSTS_POLARITY_STATUS_SHIFT) + +/* + * FALSE_CARRIER_SENSE_LATCH (RO) + * + * False Carrier Sense Latch: + * This bit will be cleared upon a read of the FCSR register. + * 1 = False Carrier event has occurred since last read of FCSCR (address 0x14). + * 0 = No False Carrier event has occurred. + */ +#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK (0x800U) +#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT (11U) +#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK) >> DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT) + +/* + * SIGNAL_DETECT (RO) + * + * 100Base-TX unconditional Signal Detect from PMD. + */ +#define DP83848_PHYSTS_SIGNAL_DETECT_MASK (0x400U) +#define DP83848_PHYSTS_SIGNAL_DETECT_SHIFT (10U) +#define DP83848_PHYSTS_SIGNAL_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SIGNAL_DETECT_MASK) >> DP83848_PHYSTS_SIGNAL_DETECT_SHIFT) + +/* + * DESCRAMBLER_LOCK (RO) + * + * 100Base-TX Descrambler Lock from PMD. + */ +#define DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK (0x200U) +#define DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT (9U) +#define DP83848_PHYSTS_DESCRAMBLER_LOCK_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK) >> DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT) + +/* + * PAGE_RECEIVED (RO) + * + * Link Code Word Page Received: + * This is a duplicate of the Page Received bit in the ANER register, but this bit will not be + * cleared upon a read of the PHYSTS register. + * 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address + * 0x06, bit 1). + * 0 = Link Code Word Page has not been received. + */ +#define DP83848_PHYSTS_PAGE_RECEIVED_MASK (0x100U) +#define DP83848_PHYSTS_PAGE_RECEIVED_SHIFT (8U) +#define DP83848_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_PAGE_RECEIVED_MASK) >> DP83848_PHYSTS_PAGE_RECEIVED_SHIFT) + +/* + * REMOTE_FAULT (RO) + * + * Remote Fault: + * 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by + * reset). Fault criteria: notification from Link Partner of Remote Fault through Auto-Negotiation. + * 0 = No remote fault condition detected. + */ +#define DP83848_PHYSTS_REMOTE_FAULT_MASK (0x40U) +#define DP83848_PHYSTS_REMOTE_FAULT_SHIFT (6U) +#define DP83848_PHYSTS_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_REMOTE_FAULT_MASK) >> DP83848_PHYSTS_REMOTE_FAULT_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * Jabber Detect: This bit only has meaning in 10 Mb/s mode + * This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not + * cleared upon a read of the PHYSTS register. + * 1 = Jabber condition detected. + * 0 = No Jabber. + */ +#define DP83848_PHYSTS_JABBER_DETECT_MASK (0x20U) +#define DP83848_PHYSTS_JABBER_DETECT_SHIFT (5U) +#define DP83848_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_JABBER_DETECT_MASK) >> DP83848_PHYSTS_JABBER_DETECT_SHIFT) + +/* + * AUTO_NEG_COMPLETE (RO) + * + * Auto-Negotiation Complete: + * 1 = Auto-Negotiation complete. + * 0 = Auto-Negotiation not complete. + */ +#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK (0x10U) +#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT (4U) +#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK) >> DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT) + +/* + * LOOPBACK_STATUS (RO) + * + * Loopback: + * 1 = Loopback enabled. + * 0 = Normal operation. + */ +#define DP83848_PHYSTS_LOOPBACK_STATUS_MASK (0x8U) +#define DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT (3U) +#define DP83848_PHYSTS_LOOPBACK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LOOPBACK_STATUS_MASK) >> DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT) + +/* + * DUPLEX_STATUS (RO) + * + * Duplex: + * This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. + * 1 = Full duplex mode. + * 0 = Half duplex mode. + * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid + * link or if Auto-Negotiation is disabled and there is a valid link. + */ +#define DP83848_PHYSTS_DUPLEX_STATUS_MASK (0x4U) +#define DP83848_PHYSTS_DUPLEX_STATUS_SHIFT (2U) +#define DP83848_PHYSTS_DUPLEX_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DUPLEX_STATUS_MASK) >> DP83848_PHYSTS_DUPLEX_STATUS_SHIFT) + +/* + * SPEED_STATUS (RO) + * + * Speed10: + * This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced + * Modes. + * 1 = 10 Mb/s mode. + * 0 = 100 Mb/s mode. + * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid + * link or if Auto-Negotiation is disabled and there is a valid link. + */ +#define DP83848_PHYSTS_SPEED_STATUS_MASK (0x2U) +#define DP83848_PHYSTS_SPEED_STATUS_SHIFT (1U) +#define DP83848_PHYSTS_SPEED_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SPEED_STATUS_MASK) >> DP83848_PHYSTS_SPEED_STATUS_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status: + * This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be + * cleared upon a read of the PHYSTS register. + * 1 = Valid link established (for either 10 or 100 Mb/s operation) + * 0 = Link not established. + */ +#define DP83848_PHYSTS_LINK_STATUS_MASK (0x1U) +#define DP83848_PHYSTS_LINK_STATUS_SHIFT (0U) +#define DP83848_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LINK_STATUS_MASK) >> DP83848_PHYSTS_LINK_STATUS_SHIFT) + +/* Bitfield definition for register: FCSCR */ +/* + * FCSCNT_7_0 (RO) + * + * False Carrier Event Counter: + * This 8-bit counter increments on every false carrier event. This counter sticks when it + * reaches its max count (FFh). + */ +#define DP83848_FCSCR_FCSCNT_7_0_MASK (0xFFU) +#define DP83848_FCSCR_FCSCNT_7_0_SHIFT (0U) +#define DP83848_FCSCR_FCSCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_FCSCR_FCSCNT_7_0_MASK) >> DP83848_FCSCR_FCSCNT_7_0_SHIFT) + +/* Bitfield definition for register: RECR */ +/* + * RXERCNT_7_0 (RO) + * + * RX_ER Counter: + * When a valid carrier is present and there is at least one occurrence of an invalid data + * symbol, this 8-bit counter increments for each receive error detected. This event can + * increment only once per valid carrier event. If a collision is present, the attribute will not + * increment. The counter sticks when it reaches its max count. + */ +#define DP83848_RECR_RXERCNT_7_0_MASK (0xFFU) +#define DP83848_RECR_RXERCNT_7_0_SHIFT (0U) +#define DP83848_RECR_RXERCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_RECR_RXERCNT_7_0_MASK) >> DP83848_RECR_RXERCNT_7_0_SHIFT) + +/* Bitfield definition for register: PCSR */ +/* + * TQ_EN (RW) + * + * 100Mbs True Quiet Mode Enable: + * 1 = Transmit True Quiet Mode. + * 0 = Normal Transmit Mode. + */ +#define DP83848_PCSR_TQ_EN_MASK (0x400U) +#define DP83848_PCSR_TQ_EN_SHIFT (10U) +#define DP83848_PCSR_TQ_EN_SET(x) (((uint16_t)(x) << DP83848_PCSR_TQ_EN_SHIFT) & DP83848_PCSR_TQ_EN_MASK) +#define DP83848_PCSR_TQ_EN_GET(x) (((uint16_t)(x) & DP83848_PCSR_TQ_EN_MASK) >> DP83848_PCSR_TQ_EN_SHIFT) + +/* + * SD_FORCE_PMA (RW) + * + * Signal Detect Force PMA: + * 1 = Forces Signal Detection in PMA. + * 0 = Normal SD operation. + */ +#define DP83848_PCSR_SD_FORCE_PMA_MASK (0x200U) +#define DP83848_PCSR_SD_FORCE_PMA_SHIFT (9U) +#define DP83848_PCSR_SD_FORCE_PMA_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_FORCE_PMA_SHIFT) & DP83848_PCSR_SD_FORCE_PMA_MASK) +#define DP83848_PCSR_SD_FORCE_PMA_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_FORCE_PMA_MASK) >> DP83848_PCSR_SD_FORCE_PMA_SHIFT) + +/* + * SD_OPTION (RW) + * + * Signal Detect Option: + * 1 = Enhanced signal detect algorithm. + * 0 = Reduced signal detect algorithm. + */ +#define DP83848_PCSR_SD_OPTION_MASK (0x100U) +#define DP83848_PCSR_SD_OPTION_SHIFT (8U) +#define DP83848_PCSR_SD_OPTION_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_OPTION_SHIFT) & DP83848_PCSR_SD_OPTION_MASK) +#define DP83848_PCSR_SD_OPTION_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_OPTION_MASK) >> DP83848_PCSR_SD_OPTION_SHIFT) + +/* + * DESC_TIME (RW) + * + * Descrambler Timeout: + * Increase the descrambler timeout. When set this should allow the device to receive larger + * packets (>9k bytes) without loss of synchronization. + * 1 = 2ms + * 0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e) + */ +#define DP83848_PCSR_DESC_TIME_MASK (0x80U) +#define DP83848_PCSR_DESC_TIME_SHIFT (7U) +#define DP83848_PCSR_DESC_TIME_SET(x) (((uint16_t)(x) << DP83848_PCSR_DESC_TIME_SHIFT) & DP83848_PCSR_DESC_TIME_MASK) +#define DP83848_PCSR_DESC_TIME_GET(x) (((uint16_t)(x) & DP83848_PCSR_DESC_TIME_MASK) >> DP83848_PCSR_DESC_TIME_SHIFT) + +/* + * FORCE_100_OK (RW) + * + * Force 100Mb/s Good Link: + * 1 = Forces 100Mb/s Good Link. + * 0 = Normal 100Mb/s operation. + */ +#define DP83848_PCSR_FORCE_100_OK_MASK (0x20U) +#define DP83848_PCSR_FORCE_100_OK_SHIFT (5U) +#define DP83848_PCSR_FORCE_100_OK_SET(x) (((uint16_t)(x) << DP83848_PCSR_FORCE_100_OK_SHIFT) & DP83848_PCSR_FORCE_100_OK_MASK) +#define DP83848_PCSR_FORCE_100_OK_GET(x) (((uint16_t)(x) & DP83848_PCSR_FORCE_100_OK_MASK) >> DP83848_PCSR_FORCE_100_OK_SHIFT) + +/* + * NRZI_BYPASS (RW) + * + * NRZI Bypass Enable: + * 1 = NRZI Bypass Enabled. + * 0 = NRZI Bypass Disabled. + */ +#define DP83848_PCSR_NRZI_BYPASS_MASK (0x4U) +#define DP83848_PCSR_NRZI_BYPASS_SHIFT (2U) +#define DP83848_PCSR_NRZI_BYPASS_SET(x) (((uint16_t)(x) << DP83848_PCSR_NRZI_BYPASS_SHIFT) & DP83848_PCSR_NRZI_BYPASS_MASK) +#define DP83848_PCSR_NRZI_BYPASS_GET(x) (((uint16_t)(x) & DP83848_PCSR_NRZI_BYPASS_MASK) >> DP83848_PCSR_NRZI_BYPASS_SHIFT) + +/* Bitfield definition for register: RBR */ +/* + * RMII_MODE (RW) + * + * Reduced MII Mode: + * 0 = Standard MII Mode + * 1 = Reduced MII Mode + */ +#define DP83848_RBR_RMII_MODE_MASK (0x20U) +#define DP83848_RBR_RMII_MODE_SHIFT (5U) +#define DP83848_RBR_RMII_MODE_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_MODE_SHIFT) & DP83848_RBR_RMII_MODE_MASK) +#define DP83848_RBR_RMII_MODE_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_MODE_MASK) >> DP83848_RBR_RMII_MODE_SHIFT) + +/* + * RMII_REV1_0 (RW) + * + * Reduce MII Revision 1.0: + * 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of + * CRS. + * 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV + * will not toggle at the end of a packet. + */ +#define DP83848_RBR_RMII_REV1_0_MASK (0x10U) +#define DP83848_RBR_RMII_REV1_0_SHIFT (4U) +#define DP83848_RBR_RMII_REV1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_REV1_0_SHIFT) & DP83848_RBR_RMII_REV1_0_MASK) +#define DP83848_RBR_RMII_REV1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_REV1_0_MASK) >> DP83848_RBR_RMII_REV1_0_SHIFT) + +/* + * RX_OVF_STS (RO) + * + * RX FIFO Over Flow Status: + * 0 = Normal + * 1 = Overflow detected + */ +#define DP83848_RBR_RX_OVF_STS_MASK (0x8U) +#define DP83848_RBR_RX_OVF_STS_SHIFT (3U) +#define DP83848_RBR_RX_OVF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_OVF_STS_MASK) >> DP83848_RBR_RX_OVF_STS_SHIFT) + +/* + * RX_UNF_STS (RO) + * + * RX FIFO Under Flow Status: + * 0 = Normal + * 1 = Underflow detected + */ +#define DP83848_RBR_RX_UNF_STS_MASK (0x4U) +#define DP83848_RBR_RX_UNF_STS_SHIFT (2U) +#define DP83848_RBR_RX_UNF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_UNF_STS_MASK) >> DP83848_RBR_RX_UNF_STS_SHIFT) + +/* + * ELAST_BUF_1_0 (RW) + * + * Receive Elasticity Buffer. This field controls the Receive Elasticity Buffer which allows for + * frequency variation tolerance between the 50-MHz RMII clock and the recovered data. The + * following value indicate the tolerance in bits for a single packet. The minimum setting allows + * for standard Ethernet frame sizes at ±50 ppm accuracy for both RMII and Receive clocks. For + * greater frequency tolerance the packet lengths may be scaled (that is, for ±100 ppm, the + * packet lengths need to be divided by 2). + * 00 = 14 bit tolerance (up to 16800 byte packets) + * 01 = 2 bit tolerance (up to 2400 byte packets) + * 10 = 6 bit tolerance (up to 7200 byte packets) + * 11 = 10 bit tolerance (up to 12000 byte packets) + */ +#define DP83848_RBR_ELAST_BUF_1_0_MASK (0x3U) +#define DP83848_RBR_ELAST_BUF_1_0_SHIFT (0U) +#define DP83848_RBR_ELAST_BUF_1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_ELAST_BUF_1_0_SHIFT) & DP83848_RBR_ELAST_BUF_1_0_MASK) +#define DP83848_RBR_ELAST_BUF_1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_ELAST_BUF_1_0_MASK) >> DP83848_RBR_ELAST_BUF_1_0_SHIFT) + +/* Bitfield definition for register: LEDCR */ +/* + * DRV_SPDLED (RW) + * + * 1 = Drive value of SPDLED bit onto LED_SPEED output + * 0 = Normal operation + */ +#define DP83848_LEDCR_DRV_SPDLED_MASK (0x20U) +#define DP83848_LEDCR_DRV_SPDLED_SHIFT (5U) +#define DP83848_LEDCR_DRV_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_SPDLED_SHIFT) & DP83848_LEDCR_DRV_SPDLED_MASK) +#define DP83848_LEDCR_DRV_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_SPDLED_MASK) >> DP83848_LEDCR_DRV_SPDLED_SHIFT) + +/* + * DRV_LNKLED (RW) + * + * 1 = Drive value of LNKLED bit onto LED_LINK output + * 0 = Normal operation + */ +#define DP83848_LEDCR_DRV_LNKLED_MASK (0x10U) +#define DP83848_LEDCR_DRV_LNKLED_SHIFT (4U) +#define DP83848_LEDCR_DRV_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_LNKLED_SHIFT) & DP83848_LEDCR_DRV_LNKLED_MASK) +#define DP83848_LEDCR_DRV_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_LNKLED_MASK) >> DP83848_LEDCR_DRV_LNKLED_SHIFT) + +/* + * SPDLED (RW) + * + * Value to force on LED_SPEED output + */ +#define DP83848_LEDCR_SPDLED_MASK (0x4U) +#define DP83848_LEDCR_SPDLED_SHIFT (2U) +#define DP83848_LEDCR_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_SPDLED_SHIFT) & DP83848_LEDCR_SPDLED_MASK) +#define DP83848_LEDCR_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_SPDLED_MASK) >> DP83848_LEDCR_SPDLED_SHIFT) + +/* + * LNKLED (RW) + * + * Value to force on LED_LINK output + */ +#define DP83848_LEDCR_LNKLED_MASK (0x2U) +#define DP83848_LEDCR_LNKLED_SHIFT (1U) +#define DP83848_LEDCR_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_LNKLED_SHIFT) & DP83848_LEDCR_LNKLED_MASK) +#define DP83848_LEDCR_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_LNKLED_MASK) >> DP83848_LEDCR_LNKLED_SHIFT) + +/* Bitfield definition for register: PHYCR */ +/* + * MDIX_EN (RW) + * + * Auto-MDIX Enable: + * 1 = Enable Auto-neg Auto-MDIX capability. + * 0 = Disable Auto-neg Auto-MDIX capability. + * The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register + * to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well. + */ +#define DP83848_PHYCR_MDIX_EN_MASK (0x8000U) +#define DP83848_PHYCR_MDIX_EN_SHIFT (15U) +#define DP83848_PHYCR_MDIX_EN_SET(x) (((uint16_t)(x) << DP83848_PHYCR_MDIX_EN_SHIFT) & DP83848_PHYCR_MDIX_EN_MASK) +#define DP83848_PHYCR_MDIX_EN_GET(x) (((uint16_t)(x) & DP83848_PHYCR_MDIX_EN_MASK) >> DP83848_PHYCR_MDIX_EN_SHIFT) + +/* + * FORCE_MDIX (RW) + * + * Force MDIX: + * 1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair) + * 0 = Normal operation. + */ +#define DP83848_PHYCR_FORCE_MDIX_MASK (0x4000U) +#define DP83848_PHYCR_FORCE_MDIX_SHIFT (14U) +#define DP83848_PHYCR_FORCE_MDIX_SET(x) (((uint16_t)(x) << DP83848_PHYCR_FORCE_MDIX_SHIFT) & DP83848_PHYCR_FORCE_MDIX_MASK) +#define DP83848_PHYCR_FORCE_MDIX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_FORCE_MDIX_MASK) >> DP83848_PHYCR_FORCE_MDIX_SHIFT) + +/* + * PAUSE_RX (RO) + * + * Pause Receive Negotiated: + * Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and + * ANLPAR[11:10] settings. + * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause + * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex + * technology. + */ +#define DP83848_PHYCR_PAUSE_RX_MASK (0x2000U) +#define DP83848_PHYCR_PAUSE_RX_SHIFT (13U) +#define DP83848_PHYCR_PAUSE_RX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_RX_MASK) >> DP83848_PHYCR_PAUSE_RX_SHIFT) + +/* + * PAUSE_TX (RO) + * + * Pause Transmit Negotiated: + * Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10] and + * ANLPAR[11:10] settings. + * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause + * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex + * technology. + */ +#define DP83848_PHYCR_PAUSE_TX_MASK (0x1000U) +#define DP83848_PHYCR_PAUSE_TX_SHIFT (12U) +#define DP83848_PHYCR_PAUSE_TX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_TX_MASK) >> DP83848_PHYCR_PAUSE_TX_SHIFT) + +/* + * BIST_FE (RW) + * + * BIST Force Error: + * 1 = Force BIST Error. + * 0 = Normal operation. + * This bit forces a single error, and is self clearing. + */ +#define DP83848_PHYCR_BIST_FE_MASK (0x800U) +#define DP83848_PHYCR_BIST_FE_SHIFT (11U) +#define DP83848_PHYCR_BIST_FE_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_FE_SHIFT) & DP83848_PHYCR_BIST_FE_MASK) +#define DP83848_PHYCR_BIST_FE_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_FE_MASK) >> DP83848_PHYCR_BIST_FE_SHIFT) + +/* + * PSR_15 (RW) + * + * BIST Sequence select: + * 1 = PSR15 selected. + * 0 = PSR9 selected. + */ +#define DP83848_PHYCR_PSR_15_MASK (0x400U) +#define DP83848_PHYCR_PSR_15_SHIFT (10U) +#define DP83848_PHYCR_PSR_15_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PSR_15_SHIFT) & DP83848_PHYCR_PSR_15_MASK) +#define DP83848_PHYCR_PSR_15_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PSR_15_MASK) >> DP83848_PHYCR_PSR_15_SHIFT) + +/* + * BIST_STATUS (RO) + * + * BIST Test Status: + * 1 = BIST pass. + * 0 = BIST fail. Latched, cleared when BIST is stopped. + * For a count number of BIST errors, see the BIST Error Count in the CDCTRL1 register. + */ +#define DP83848_PHYCR_BIST_STATUS_MASK (0x200U) +#define DP83848_PHYCR_BIST_STATUS_SHIFT (9U) +#define DP83848_PHYCR_BIST_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_STATUS_MASK) >> DP83848_PHYCR_BIST_STATUS_SHIFT) + +/* + * BIST_START (RW) + * + * BIST Start: + * 1 = BIST start. + * 0 = BIST stop. + */ +#define DP83848_PHYCR_BIST_START_MASK (0x100U) +#define DP83848_PHYCR_BIST_START_SHIFT (8U) +#define DP83848_PHYCR_BIST_START_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_START_SHIFT) & DP83848_PHYCR_BIST_START_MASK) +#define DP83848_PHYCR_BIST_START_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_START_MASK) >> DP83848_PHYCR_BIST_START_SHIFT) + +/* + * BP_STRETCH (RW) + * + * Bypass LED Stretching: + * This will bypass the LED stretching and the LEDs will reflect the internal value. + * 1 = Bypass LED stretching. + * 0 = Normal operation. + */ +#define DP83848_PHYCR_BP_STRETCH_MASK (0x80U) +#define DP83848_PHYCR_BP_STRETCH_SHIFT (7U) +#define DP83848_PHYCR_BP_STRETCH_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BP_STRETCH_SHIFT) & DP83848_PHYCR_BP_STRETCH_MASK) +#define DP83848_PHYCR_BP_STRETCH_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BP_STRETCH_MASK) >> DP83848_PHYCR_BP_STRETCH_SHIFT) + +/* + * LED_CNFG_0 (RW) + * + * LED Configuration + * LED_ CNFG[0] Mode Description + * 1 Mode 1 + * 0 Mode2 + * In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link + * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s + * In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity + * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s + */ +#define DP83848_PHYCR_LED_CNFG_0_MASK (0x20U) +#define DP83848_PHYCR_LED_CNFG_0_SHIFT (5U) +#define DP83848_PHYCR_LED_CNFG_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_LED_CNFG_0_SHIFT) & DP83848_PHYCR_LED_CNFG_0_MASK) +#define DP83848_PHYCR_LED_CNFG_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_LED_CNFG_0_MASK) >> DP83848_PHYCR_LED_CNFG_0_SHIFT) + +/* + * PHYADDR_4_0 (RW) + * + * PHY Address: PHY address for port. + */ +#define DP83848_PHYCR_PHYADDR_4_0_MASK (0x1FU) +#define DP83848_PHYCR_PHYADDR_4_0_SHIFT (0U) +#define DP83848_PHYCR_PHYADDR_4_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PHYADDR_4_0_SHIFT) & DP83848_PHYCR_PHYADDR_4_0_MASK) +#define DP83848_PHYCR_PHYADDR_4_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PHYADDR_4_0_MASK) >> DP83848_PHYCR_PHYADDR_4_0_SHIFT) + +/* Bitfield definition for register: 10BTSCR */ +/* + * SQUELCH (RW) + * + * Squelch Configuration: + * Used to set the Squelch ‘ON’ threshold for the receiver. + * Default Squelch ON is 330-mV peak. + */ +#define DP83848_10BTSCR_SQUELCH_MASK (0xE00U) +#define DP83848_10BTSCR_SQUELCH_SHIFT (9U) +#define DP83848_10BTSCR_SQUELCH_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_SQUELCH_SHIFT) & DP83848_10BTSCR_SQUELCH_MASK) +#define DP83848_10BTSCR_SQUELCH_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_SQUELCH_MASK) >> DP83848_10BTSCR_SQUELCH_SHIFT) + +/* + * LOOPBACK_10_DIS (RW) + * + * In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data + * in addition to transmitting the data on the physical medium. This is for consistency with + * earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting + * this bit disables the loopback function. + * This bit does not affect loopback due to setting BMCR[14]. + */ +#define DP83848_10BTSCR_LOOPBACK_10_DIS_MASK (0x100U) +#define DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT (8U) +#define DP83848_10BTSCR_LOOPBACK_10_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) +#define DP83848_10BTSCR_LOOPBACK_10_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) >> DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) + +/* + * LP_DIS (RW) + * + * Normal Link Pulse Disable: + * 1 = Transmission of NLPs is disabled. + * 0 = Transmission of NLPs is enabled. + */ +#define DP83848_10BTSCR_LP_DIS_MASK (0x80U) +#define DP83848_10BTSCR_LP_DIS_SHIFT (7U) +#define DP83848_10BTSCR_LP_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LP_DIS_SHIFT) & DP83848_10BTSCR_LP_DIS_MASK) +#define DP83848_10BTSCR_LP_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LP_DIS_MASK) >> DP83848_10BTSCR_LP_DIS_SHIFT) + +/* + * FORCE_LINK_10 (RW) + * + * Force 10Mb Good Link: + * 1 = Forced Good 10 Mb Link. + * 0 = Normal Link Status. + */ +#define DP83848_10BTSCR_FORCE_LINK_10_MASK (0x40U) +#define DP83848_10BTSCR_FORCE_LINK_10_SHIFT (6U) +#define DP83848_10BTSCR_FORCE_LINK_10_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_FORCE_LINK_10_SHIFT) & DP83848_10BTSCR_FORCE_LINK_10_MASK) +#define DP83848_10BTSCR_FORCE_LINK_10_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_FORCE_LINK_10_MASK) >> DP83848_10BTSCR_FORCE_LINK_10_SHIFT) + +/* + * POLARITY (RO) + * + * 10Mb Polarity Status: + * This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a + * read of 10BTSCR register, but not upon a read of the PHYSTS register. + * 1 = Inverted Polarity detected. + * 0 = Correct Polarity detected. + */ +#define DP83848_10BTSCR_POLARITY_MASK (0x10U) +#define DP83848_10BTSCR_POLARITY_SHIFT (4U) +#define DP83848_10BTSCR_POLARITY_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_POLARITY_MASK) >> DP83848_10BTSCR_POLARITY_SHIFT) + +/* + * HEARTBEAT_DIS (RW) + * + * Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode. + * 1 = Heartbeat function disabled. + * 0 = Heartbeat function enabled. + * When the device is operating at 100 Mb or configured for full duplex operation, this + * bit will be ignored - the heartbeat function is disabled. + */ +#define DP83848_10BTSCR_HEARTBEAT_DIS_MASK (0x2U) +#define DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT (1U) +#define DP83848_10BTSCR_HEARTBEAT_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) +#define DP83848_10BTSCR_HEARTBEAT_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) >> DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) + +/* + * JABBER_DIS (RW) + * + * Jabber Disable: + * Applicable only in 10BASE-T. + * 1 = Jabber function disabled. + * 0 = Jabber function enabled. + */ +#define DP83848_10BTSCR_JABBER_DIS_MASK (0x1U) +#define DP83848_10BTSCR_JABBER_DIS_SHIFT (0U) +#define DP83848_10BTSCR_JABBER_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_JABBER_DIS_SHIFT) & DP83848_10BTSCR_JABBER_DIS_MASK) +#define DP83848_10BTSCR_JABBER_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_JABBER_DIS_MASK) >> DP83848_10BTSCR_JABBER_DIS_SHIFT) + +/* Bitfield definition for register: CDCTRL1 */ +/* + * BIST_ERROR_COUNT (RO) + * + * BIST ERROR Counter: + * Counts number of errored data nibbles during Packet BIST. This value will reset when + * Packet BIST is restarted. The counter sticks when it reaches its max count. + */ +#define DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK (0xFF00U) +#define DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT (8U) +#define DP83848_CDCTRL1_BIST_ERROR_COUNT_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK) >> DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT) + +/* + * BIST_CONT_MODE (RW) + * + * Packet BIST Continuous Mode: + * Allows continuous pseudo random data transmission without any break in transmission. This + * can be used for transmit VOD testing. This is used in conjunction with the BIST controls in + * the PHYCR Register (0x19h). For 10 Mb operation, jabber function must be disabled, bit 0 of + * the 10BTSCR (0x1Ah), JABBER_DIS = 1. + */ +#define DP83848_CDCTRL1_BIST_CONT_MODE_MASK (0x20U) +#define DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT (5U) +#define DP83848_CDCTRL1_BIST_CONT_MODE_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) +#define DP83848_CDCTRL1_BIST_CONT_MODE_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) >> DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) + +/* + * CDPATTEN_10 (RW) + * + * CD Pattern Enable for 10Mb: + * 1 = Enabled. + * 0 = Disabled. + */ +#define DP83848_CDCTRL1_CDPATTEN_10_MASK (0x10U) +#define DP83848_CDCTRL1_CDPATTEN_10_SHIFT (4U) +#define DP83848_CDCTRL1_CDPATTEN_10_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTEN_10_SHIFT) & DP83848_CDCTRL1_CDPATTEN_10_MASK) +#define DP83848_CDCTRL1_CDPATTEN_10_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTEN_10_MASK) >> DP83848_CDCTRL1_CDPATTEN_10_SHIFT) + +/* + * 10MEG_PATT_GAP ( RW) + * + * Defines gap between data or NLP test sequences: + * 1 = 15 µs. + * 0 = 10 µs. + */ +#define DP83848_CDCTRL1_10MEG_PATT_GAP_MASK (0x4U) +#define DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT (2U) +#define DP83848_CDCTRL1_10MEG_PATT_GAP_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) +#define DP83848_CDCTRL1_10MEG_PATT_GAP_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) >> DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) + +/* + * CDPATTSEL_1_0 (RW) + * + * CD Pattern Select[1:0]: + * If CDPATTEN_10 = 1: + * 00 = Data, EOP0 sequence + * 01 = Data, EOP1 sequence + * 10 = NLPs + * 11 = Constant Manchester 1 s (10-MHz sine wave) for harmonic distortion testing. + */ +#define DP83848_CDCTRL1_CDPATTSEL_1_0_MASK (0x3U) +#define DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT (0U) +#define DP83848_CDCTRL1_CDPATTSEL_1_0_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) +#define DP83848_CDCTRL1_CDPATTSEL_1_0_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) >> DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) + +/* Bitfield definition for register: EDCR */ +/* + * ED_EN (RW) + * + * Energy Detect Enable: + * Allow Energy Detect Mode. + * When Energy Detect is enabled and Auto-Negotiation is disabled through the BMCR + * register, Auto-MDIX should be disabled through the PHYCR register. + */ +#define DP83848_EDCR_ED_EN_MASK (0x8000U) +#define DP83848_EDCR_ED_EN_SHIFT (15U) +#define DP83848_EDCR_ED_EN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_EN_SHIFT) & DP83848_EDCR_ED_EN_MASK) +#define DP83848_EDCR_ED_EN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_EN_MASK) >> DP83848_EDCR_ED_EN_SHIFT) + +/* + * ED_AUTO_UP (RW) + * + * Energy Detect Automatic Power Up: + * Automatically begin power-up sequence when Energy Detect Data Threshold value + * (EDCR[3:0]) is reached. Alternatively, device could be powered up manually using the + * ED_MAN bit (ECDR[12]). + */ +#define DP83848_EDCR_ED_AUTO_UP_MASK (0x4000U) +#define DP83848_EDCR_ED_AUTO_UP_SHIFT (14U) +#define DP83848_EDCR_ED_AUTO_UP_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_UP_SHIFT) & DP83848_EDCR_ED_AUTO_UP_MASK) +#define DP83848_EDCR_ED_AUTO_UP_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_UP_MASK) >> DP83848_EDCR_ED_AUTO_UP_SHIFT) + +/* + * ED_AUTO_DOWN (RW) + * + * Energy Detect Automatic Power Down: + * Automatically begin power-down sequence when no energy is detected. Alternatively, + * device could be powered down using the ED_MAN bit (EDCR[12]). + */ +#define DP83848_EDCR_ED_AUTO_DOWN_MASK (0x2000U) +#define DP83848_EDCR_ED_AUTO_DOWN_SHIFT (13U) +#define DP83848_EDCR_ED_AUTO_DOWN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_DOWN_SHIFT) & DP83848_EDCR_ED_AUTO_DOWN_MASK) +#define DP83848_EDCR_ED_AUTO_DOWN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_DOWN_MASK) >> DP83848_EDCR_ED_AUTO_DOWN_SHIFT) + +/* + * ED_MAN (RW) + * + * Energy Detect Manual Power Up/Down: + * Begin power-up/down sequence when this bit is asserted. When set, the Energy Detect + * algorithm will initiate a change of Energy Detect state regardless of threshold (error or + * data) and timer values. + */ +#define DP83848_EDCR_ED_MAN_MASK (0x1000U) +#define DP83848_EDCR_ED_MAN_SHIFT (12U) +#define DP83848_EDCR_ED_MAN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_MAN_SHIFT) & DP83848_EDCR_ED_MAN_MASK) +#define DP83848_EDCR_ED_MAN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_MAN_MASK) >> DP83848_EDCR_ED_MAN_SHIFT) + +/* + * ED_BURST_DIS (RW) + * + * Energy Detect Bust Disable: + * Disable bursting of energy detect data pulses. By default, Energy Detect (ED) transmits + * a burst of 4 ED data pulses each time the CD is powered up. When bursting is + * disabled, only a single ED data pulse will be send each time the CD is powered up. + */ +#define DP83848_EDCR_ED_BURST_DIS_MASK (0x800U) +#define DP83848_EDCR_ED_BURST_DIS_SHIFT (11U) +#define DP83848_EDCR_ED_BURST_DIS_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_BURST_DIS_SHIFT) & DP83848_EDCR_ED_BURST_DIS_MASK) +#define DP83848_EDCR_ED_BURST_DIS_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_BURST_DIS_MASK) >> DP83848_EDCR_ED_BURST_DIS_SHIFT) + +/* + * ED_PWR_STATE (RO) + * + * Energy Detect Power State: + * Indicates current Energy Detect Power state. When set, Energy Detect is in the + * powered up state. When cleared, Energy Detect is in the powered down state. This bit + * is invalid when Energy Detect is not enabled. + */ +#define DP83848_EDCR_ED_PWR_STATE_MASK (0x400U) +#define DP83848_EDCR_ED_PWR_STATE_SHIFT (10U) +#define DP83848_EDCR_ED_PWR_STATE_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_PWR_STATE_MASK) >> DP83848_EDCR_ED_PWR_STATE_SHIFT) + +/* + * ED_ERR_MET (RO) + * + * Energy Detect Error Threshold Met: + * No action is automatically taken upon receipt of error events. This bit is informational + * only and would be cleared on a read. + */ +#define DP83848_EDCR_ED_ERR_MET_MASK (0x200U) +#define DP83848_EDCR_ED_ERR_MET_SHIFT (9U) +#define DP83848_EDCR_ED_ERR_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_MET_MASK) >> DP83848_EDCR_ED_ERR_MET_SHIFT) + +/* + * ED_DATA_MET (RO) + * + * Energy Detect Data Threshold Met: + * The number of data events that occurred met or surpassed the Energy Detect Data + * Threshold. This bit is cleared on a read. + */ +#define DP83848_EDCR_ED_DATA_MET_MASK (0x100U) +#define DP83848_EDCR_ED_DATA_MET_SHIFT (8U) +#define DP83848_EDCR_ED_DATA_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_MET_MASK) >> DP83848_EDCR_ED_DATA_MET_SHIFT) + +/* + * ED_ERR_COUNT (RW) + * + * Energy Detect Error Threshold: + * Threshold to determine the number of energy detect error events that should cause the + * device to take action. Intended to allow averaging of noise that may be on the line. + * Counter will reset after approximately 2 seconds without any energy detect data + * events. + */ +#define DP83848_EDCR_ED_ERR_COUNT_MASK (0xF0U) +#define DP83848_EDCR_ED_ERR_COUNT_SHIFT (4U) +#define DP83848_EDCR_ED_ERR_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_ERR_COUNT_SHIFT) & DP83848_EDCR_ED_ERR_COUNT_MASK) +#define DP83848_EDCR_ED_ERR_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_COUNT_MASK) >> DP83848_EDCR_ED_ERR_COUNT_SHIFT) + +/* + * ED_DATA_COUNT (RW) + * + * Energy Detect Data Threshold: + * Threshold to determine the number of energy detect events that should cause the + * device to take actions. Intended to allow averaging of noise that may be on the line. + * Counter will reset after approximately 2 seconds without any energy detect data + * events. + */ +#define DP83848_EDCR_ED_DATA_COUNT_MASK (0xFU) +#define DP83848_EDCR_ED_DATA_COUNT_SHIFT (0U) +#define DP83848_EDCR_ED_DATA_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_DATA_COUNT_SHIFT) & DP83848_EDCR_ED_DATA_COUNT_MASK) +#define DP83848_EDCR_ED_DATA_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_COUNT_MASK) >> DP83848_EDCR_ED_DATA_COUNT_SHIFT) + + + + +#endif /* HPM_DP83848_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c index dddf00eaac..8a43504c12 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c @@ -1,166 +1,138 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_dp83867_regs.h" #include "hpm_dp83867.h" -#include "board.h" -/*---------------------------------------------------------------------* - * Interal API - *---------------------------------------------------------------------*/ -bool dp83867_id_check(ENET_Type *ptr) +/*--------------------------------------------------------------------- + * Internal API + *--------------------------------------------------------------------- + */ +bool dp83867_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_PHYID2); + id1 = enet_read_phy(ptr, DP83867_ADDR, DP83867_PHYIDR1); + id2 = enet_read_phy(ptr, DP83867_ADDR, DP83867_PHYIDR2); - if (DP83867_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && DP83867_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (DP83867_PHYIDR1_OUI_MSB_GET(id1) == DP83867_ID1 && DP83867_PHYIDR2_OUI_LSB_GET(id2) == DP83867_ID2) { return true; } else { return false; } } -static void dp83867_phy_write_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) +static void dp83867_write_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) { /* set the control register for register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_ADDR | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_SET(0x1f)); /* write the specified register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, addr); + enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); /* set the control register for register data */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_DATA | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_SET(0x1f)); /* write the specified register data */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, data); + enet_write_phy(ptr, phy_addr, DP83867_ADDAR, data); } -static uint16_t dp83867_phy_read_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) +static uint16_t dp83867_read_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) { /* set the control register for register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_ADDR | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_SET(0x1f)); /* write the specified register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, addr); + enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); /* set the control register for register data */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_DATA | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_SET(0x1f)); /* read the specified register data */ - return enet_read_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR); + return enet_read_phy(ptr, phy_addr, DP83867_ADDAR); } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t DP83867_REGister_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void dp83867_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, DP83867_REG_BMCR, DP83867_BMCR_RESET_SET(1)); + enet_write_phy(ptr, DP83867_ADDR, DP83867_BMCR, DP83867_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_BMCR); + data = enet_read_phy(ptr, DP83867_ADDR, DP83867_BMCR); } while (DP83867_BMCR_RESET_GET(data)); } void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config) { - config->loopback = 0; /* Enable PCS loopback mode */ - config->speed = 2; /* 3: reserved; 2: 1000mbps; 1: 100mbps; 0: 10mbps */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = false; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = true; /* Enable Auto-Negotiation */ + #endif } bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= DP83867_BMCR_RESET_SET(0) /* Normal operation */ + data |= DP83867_BMCR_RESET_SET(0) /* Normal operation */ | DP83867_BMCR_LOOPBACK_SET(config->loopback) /* Configure PCS loopback mode */ | DP83867_BMCR_ANE_SET(config->auto_negotiation) /* Configure Auto-Negotiation */ | DP83867_BMCR_PWD_SET(0) /* Normal operation */ | DP83867_BMCR_ISOLATE_SET(0) /* Normal operation */ | DP83867_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ - | DP83867_BMCR_DUPLEX_SET(config->duplex_mode) /* Config duplex mode */ | DP83867_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ if (config->auto_negotiation == false) { - para |= DP83867_BMCR_SPEED0_SET(config->speed) | DP83867_BMCR_SPEED1_SET(config->speed >> 1); + data |= DP83867_BMCR_SPEED0_SET(config->speed) | DP83867_BMCR_SPEED1_SET(config->speed >> 1); /* Set port speed */ + data |= DP83867_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } /* check the id of dp83867 */ - if (dp83867_id_check(ptr) == false) { + if (dp83867_check_id(ptr) == false) { return false; } - while (dp83867_get_phy_link_status(ptr) == 0) { - - } + enet_write_phy(ptr, DP83867_ADDR, DP83867_BMCR, data); + data = enet_read_phy(ptr, DP83867_ADDR, DP83867_BMCR); return true; } -void dp83867_init_auto_negotiation(void) +void dp83867_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { + uint16_t data; + data = enet_read_phy(ptr, DP83867_ADDR, DP83867_PHYSTS); + status->enet_phy_link = DP83867_PHYSTS_LINK_STATUS_GET(data); + status->enet_phy_speed = DP83867_PHYSTS_SPEED_SELECTION_GET(data) == 0 ? enet_phy_port_speed_10mbps : DP83867_PHYSTS_SPEED_SELECTION_GET(data) == 1 ? enet_phy_port_speed_100mbps : enet_phy_port_speed_1000mbps; + status->enet_phy_duplex = DP83867_PHYSTS_DUPLEX_MODE_GET(data); } -uint16_t dp83867_get_phy_link_status(ENET_Type *ptr) +void dp83867_set_mdi_crossover_mode(ENET_Type *ptr, enet_phy_crossover_mode_t mode) { - return DP83867_BMSR_LINK_STATUS_GET(enet_read_phy(ptr, PHY_ADDR, DP83867_REG_BMSR)); -} - -void dp83867_set_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr, uint8_t delay) -{ - dp83867_phy_write_ext(ptr, phy_addr, DP83867_EXT_REG_RGMIIDCTL, delay); -} - -uint16_t dp83867_get_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr) -{ - uint16_t temp = 0; - - temp = dp83867_phy_read_ext(ptr, phy_addr, DP83867_EXT_REG_RGMIIDCTL); - - return temp; -} - -void dp83867_set_rx_clk_delay(ENET_Type *ptr) -{ - uint16_t para = 0; - - para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL); - dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL, para | 1); -} - -void dp83867_enable_crc_check(ENET_Type *ptr) -{ - uint16_t para = 0; - - para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG); - dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG, para | (1 << 7)); -} - -void dp83867_enable_rmii_inf(ENET_Type *ptr) -{ - uint16_t para = 0; - - para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL); - dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL, para | (1 << 7)); + uint16_t data; + + data = dp83867_read_phy_ext(ptr, DP83867_ADDR, DP83867_PHYCR); + data &= ~DP83867_PHYCR_MDI_CROSSOVER_MASK; + data |= DP83867_PHYCR_MDI_CROSSOVER_SET(mode); + dp83867_write_phy_ext(ptr, DP83867_ADDR, DP83867_PHYCR, data); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h index 5e6365951d..14950e468f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,26 +8,33 @@ #ifndef HPM_DP83867_H #define HPM_DP83867_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- * Macro Const Definitions - *---------------------------------------------------------------------*/ -#define PHY_ADDR (0U) -#define PHY_ID1 (0x2000U) -#define PHY_ID2 (0x28U) + *--------------------------------------------------------------------- + */ +#ifndef DP83867_ADDR +#define DP83867_ADDR (0U) +#endif -/*---------------------------------------------------------------------* +#define DP83867_ID1 (0x2000U) +#define DP83867_ID2 (0x28U) + +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; } dp83867_config_t; typedef enum { @@ -52,25 +59,17 @@ typedef enum { #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t dp83867_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void dp83867_reset(ENET_Type *ptr); void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config); bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config); -void dp83867_read_status(ENET_Type *ptr); -void dp83867_control_config(ENET_Type *ptr); -void dp83867_ctl_config(ENET_Type *ptr); -void dp83867_bist_config(ENET_Type *ptr); -uint16_t dp83867_get_phy_link_status(ENET_Type *ptr); -void dp83867_set_rx_clk_delay(ENET_Type *ptr); -void dp83867_enable_crc_check(ENET_Type *ptr); -void dp83867_set_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr, uint8_t delay); -uint16_t dp83867_get_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr); -void dp83867_enable_rmii_inf(ENET_Type *ptr); +void dp83867_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); +void dp83867_set_mdi_crossover_mode(ENET_Type *ptr, enet_phy_crossover_mode_t mode); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_DP83867_H */ \ No newline at end of file +#endif /* HPM_DP83867_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h index 1c228f3a70..52a6e8a319 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h @@ -1,198 +1,326 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ + #ifndef HPM_DP83867_REGS_H #define HPM_DP83867_REGS_H - /* Register Definitions */ -#define DP83867_REG_BMCR (0U) /* Basic Mode Control Register */ -#define DP83867_REG_BMSR (1U) /* Basic Mode Status Register */ -#define DP83867_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define DP83867_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define DP83867_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define DP83867_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define DP83867_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ -#define DP83867_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ -#define DP83867_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ -#define DP83867_REG_GBCR (9U) /* 1000Base-T Control Register */ -#define DP83867_REG_STATUS (10U) /* Status Register */ +typedef enum { + DP83867_BMCR = 0, /* 0x0: Basic Mode Control Register */ + DP83867_BMSR = 1, /* 0x1: Basic Mode Status Register */ + DP83867_PHYIDR1 = 2, /* 0x2: PHY Identifier Register #1 */ + DP83867_PHYIDR2 = 3, /* 0x3: PHY Identifier Register #2 */ + DP83867_ANAR = 4, /* 0x4: MII Interrupt Control Register */ + DP83867_ANLPAR = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */ + DP83867_ANER = 6, /* 0x6: Auto-Negotiate Expansion Register */ + DP83867_ANNPTR = 7, /* 0x7: Auto-Negotiation Next Page Transmit Register */ + DP83867_ANNPRR = 8, /* 0x8: Auto-Negotiation Next Page Receive Register */ + DP83867_CFG1 = 9, /* 0x9: Configuration Register 1 */ + DP83867_STS1 = 10, /* 0xA: Status Register 1 */ + DP83867_REGCR = 13, /* 0xD: Register Control Register */ + DP83867_ADDAR = 14, /* 0xE: Address or Data Register */ + DP83867_1KSCR = 15, /* 0xF: 1000BASE-T Status Register */ + DP83867_PHYCR = 16, /* 0x10: PHY Control Register */ + DP83867_PHYSTS = 17, /* 0x11: PHY Status Register */ + DP83867_MICR = 18, /* 0x12: MII Interrupt Control Register */ + DP83867_ISR = 19, /* 0x13: Interrupt Status Register */ + DP83867_CRG2 = 20, /* 0x14: Configuration Register 2 */ + DP83867_RECR = 21, /* 0x15: Receiver Error Counter Register */ + DP83867_STS2 = 23, /* 0x17: Status Register 2 */ + DP83867_LEDCR1 = 24, /* 0x18: LED Configuration Register 1 */ + DP83867_LEDCR2 = 25, /* 0x19: LED Configuration Register 2 */ + DP83867_LEDCR3 = 26, /* 0x1A: LED Configuration Register 3 */ + DP83867_CFG3 = 30, /* 0x1E: Configuration Register 3 */ + DP83867_CTRL = 31, /* 0x1F: Control Register */ + DP83867_RGMIIDCTL = 134, /* 0x86: RGMII Delay Control Register */ +} DP83867_REG_Type; -#define DP83867_REG_MACR (13U) /* MMD Access Control Register */ -#define DP83867_REG_MAADR (14U) /* MMD Access Address Data Register */ -#define DP83867_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ -#define DP83867_REG_PHYCR (16U) /* PHY Specific Control Register */ -#define DP83867_REG_PHYSR (17U) /* PHY Specific Status Register */ -#define DP83867_REG_INER (18U) /* Interrupt Enable Register */ -#define DP83867_REG_INSR (19U) /* Interrupt Status Register */ -#define DP83867_REG_RXERC (24U) /* Receive Error Counter */ -#define DP83867_REG_PAGSEL (31U) /* Page Select Register */ - -/* RTL MMD Register Definitions */ -#define DP83867_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define DP83867_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define DP83867_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define DP83867_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define DP83867_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define DP83867_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ - -/* DP83867 */ - -/* DP83867 Extended Registers */ -#define DP83867_EXT_REG_REGCR (0x000DU) /* Register Control Register */ -#define DP83867_EXT_REG_ADDAR (0x000EU) /* Address or Data Register */ -#define DP83867_EXT_REG_BISCR (0x0016U) /* BIST Control Register */ -#define DP83867_EXT_REG_CTRL (0x001fU) /* Control Register */ -#define DP83867_EXT_REG_RGMIICTL (0x0032U) /* RGMII Control Register */ -#define DP83867_EXT_REG_LOOPCR (0x00FEU) /* Loopback Configuration Register */ -#define DP83867_EXT_REG_RXFCFG (0x0134U) /* Recevie Configuration Register */ - -/* DP83867 extended registers */ -#define DP83867_EXT_REG_RGMIIDCTL (0x0086U) /* RGMII Delay Control */ - - -#define DP83867_REGCR_FUNCTION_ADDR (0 << 14) -#define DP83867_REGCR_FUNCTION_DATA (1 << 14) -#define DP83867_REGCR_DEVAD (0x1f) /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * - * 1: PHY reset - * 0: Normal operation - * Register 0 (BMCR) and register 1 (BMSR) will return to default - * values after a software reset (set Bit15 to 1). - * This action may change the internal PHY state and the state of the - * physical link associated with the PHY. + * Reset: + * 1 = Initiate software Reset / Reset in Process. + * 0 = Normal operation. + * This bit, which is self-clearing, returns a value of one until the reset + * process is complete. The configuration is restrapped. */ -#define DP83867_BMCR_RESET_MASK (0x8000U) +#define DP83867_BMCR_RESET_MASK (0x8000U) #define DP83867_BMCR_RESET_SHIFT (15U) -#define DP83867_BMCR_RESET_SET(x) (((uint32_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK) -#define DP83867_BMCR_RESET_GET(x) (((uint32_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT) +#define DP83867_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK) +#define DP83867_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * - * Loopback Mode. - * 1: Enable PCS loopback mode - * 0: Disable PCS loopback mode + * Loopback: + * 1 = Loopback enabled. + * 0 = Normal operation. + * The loopback function enables MAC transmit data to be routed to + * the MAC receive data path. + * Setting this bit may cause the descrambler to lose synchronization + * and produce a 500-µs dead time before any valid data will appear at + * the MII receive outputs. */ -#define DP83867_BMCR_LOOPBACK_MASK (0x4000U) +#define DP83867_BMCR_LOOPBACK_MASK (0x4000U) #define DP83867_BMCR_LOOPBACK_SHIFT (14U) -#define DP83867_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK) -#define DP83867_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT) +#define DP83867_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK) +#define DP83867_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * Speed Select (Bits 6, 13): + * When auto-negotiation is disabled writing to this bit allows the port + * speed to be selected. + * 11 = Reserved + * 10 = 1000 Mbps + * 1 = 100 Mbps + * 0 = 10 Mbps */ -#define DP83867_BMCR_SPEED0_MASK (0x2000U) +#define DP83867_BMCR_SPEED0_MASK (0x2000U) #define DP83867_BMCR_SPEED0_SHIFT (13U) -#define DP83867_BMCR_SPEED0_SET(x) (((uint32_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK) -#define DP83867_BMCR_SPEED0_GET(x) (((uint32_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT) +#define DP83867_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK) +#define DP83867_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT) /* - * ANE (RW) + * ANE (STRAP, RW) * - * Auto-Negotiation Enable. - * 1: Enable Auto-Negotiation - * 0: Disable Auto-Negotiation + * Auto-Negotiation Enable: + * Strap controls initial value at reset. + * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are + * ignored when this bit is set. + * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port + * speed and duplex mode. */ -#define DP83867_BMCR_ANE_MASK (0x1000U) +#define DP83867_BMCR_ANE_MASK (0x1000U) #define DP83867_BMCR_ANE_SHIFT (12U) -#define DP83867_BMCR_ANE_SET(x) (((uint32_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK) -#define DP83867_BMCR_ANE_GET(x) (((uint32_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT) +#define DP83867_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK) +#define DP83867_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT) /* * PWD (RW) * - * Power Down. - * 1: Power down (only Management Interface and logic are active; link - * is down) - * 0: Normal operation + * Power Down: + * 1 = Power down. + * 0 = Normal operation. + * Setting this bit powers down the PHY. Only the register block is + * enabled during a power down condition. This bit is ORd with the + * input from the PWRDOWN_INT pin. When the active low + * PWRDOWN_INT pin is asserted, this bit will be set. */ -#define DP83867_BMCR_PWD_MASK (0x0800U) +#define DP83867_BMCR_PWD_MASK (0x800U) #define DP83867_BMCR_PWD_SHIFT (11U) -#define DP83867_BMCR_PWD_SET(x) (((uint32_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK) -#define DP83867_BMCR_PWD_GET(x) (((uint32_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT) +#define DP83867_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK) +#define DP83867_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * - * Isolate. - * 1: RGMII/GMII interface is isolated; the serial management interface - * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. - * 0: Normal operation + * Isolate: + * 1 = Isolates the Port from the MII with the exception of the serial + * management. + * 0 = Normal operation. */ -#define DP83867_BMCR_ISOLATE_MASK (0x0400U) +#define DP83867_BMCR_ISOLATE_MASK (0x400U) #define DP83867_BMCR_ISOLATE_SHIFT (10U) -#define DP83867_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK) -#define DP83867_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT) +#define DP83867_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK) +#define DP83867_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * - * Restart Auto-Negotiation. - * 1: Restart Auto-Negotiation - * 0: Normal operation + * Restart Auto-Negotiation: + * 1 = Restart Auto-Negotiation. Reinitiates the Auto-Negotiation + * process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is + * ignored. This bit is self-clearing and will return a value of 1 until + * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of + * the Auto-Negotiation process is not affected by the management + * entity clearing this bit. + * 0 = Normal operation. */ -#define DP83867_BMCR_RESTART_AN_MASK (0x0200U) +#define DP83867_BMCR_RESTART_AN_MASK (0x200U) #define DP83867_BMCR_RESTART_AN_SHIFT (9U) -#define DP83867_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK) -#define DP83867_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT) +#define DP83867_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK) +#define DP83867_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (STRAP, RW) * - * Duplex Mode. - * 1: Full Duplex operation - * 0: Half Duplex operation - * This bit is valid only in force mode, i.e., NWay is disabled. + * Duplex Mode: + * When auto-negotiation is disabled writing to this bit allows the port + * Duplex capability to be selected. + * 1 = Full Duplex operation. + * 0 = Half Duplex operation. */ -#define DP83867_BMCR_DUPLEX_MASK (0x0100U) +#define DP83867_BMCR_DUPLEX_MASK (0x100U) #define DP83867_BMCR_DUPLEX_SHIFT (8U) -#define DP83867_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK) -#define DP83867_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT) +#define DP83867_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK) +#define DP83867_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * - * Collision Test. - * 1: Collision test enabled - * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. + * Collision Test: + * 1 = Collision test enabled. + * 0 = Normal operation. + * When set, this bit will cause the COL signal to be asserted in + * response to the assertion of TX_EN within 512-bit times. The COL + * signal will be deasserted within 4-bit times in response to the + * deassertion of TX_EN. */ -#define DP83867_BMCR_COLLISION_TEST_MASK (0x0080U) +#define DP83867_BMCR_COLLISION_TEST_MASK (0x80U) #define DP83867_BMCR_COLLISION_TEST_SHIFT (7U) -#define DP83867_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK) -#define DP83867_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT) +#define DP83867_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK) +#define DP83867_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT) /* - * Speed[1] (RW) + * SPEED1 (RW) * - * Speed Select Bit 1. - * Refer to bit 0.13. + * Speed Select: See description for bit 13. */ -#define DP83867_BMCR_SPEED1_MASK (0x0040U) +#define DP83867_BMCR_SPEED1_MASK (0x40U) #define DP83867_BMCR_SPEED1_SHIFT (6U) -#define DP83867_BMCR_SPEED1_SET(x) (((uint32_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK) -#define DP83867_BMCR_SPEED1_GET(x) (((uint32_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT) +#define DP83867_BMCR_SPEED1_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK) +#define DP83867_BMCR_SPEED1_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT) /* Bitfield definition for register: BMSR */ +/* + * 100BASE_T4 (RO/P) + * + * 100BASE-T4 Capable: + * 0 = Device not able to perform 100BASE-T4 mode. + */ +#define DP83867_BMSR_100BASE_T4_MASK (0x8000U) +#define DP83867_BMSR_100BASE_T4_SHIFT (15U) +#define DP83867_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T4_MASK) >> DP83867_BMSR_100BASE_T4_SHIFT) /* + * 100BASE_TX_FULL_DUPLEX (RO/P) + * + * 100BASE-TX Full Duplex Capable: + * 1 = Device able to perform 100BASE-TX in full duplex mode. + */ +#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U) +#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U) +#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT) + +/* + * 100BASE_TX_HALF_DUPLEX (RO/P) + * + * 100BASE-TX Half Duplex Capable: + * 1 = Device able to perform 100BASE-TX in half duplex mode. + */ +#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK (0x2000U) +#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT (13U) +#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT) + +/* + * 10BASE_TE_FULL_DUPLEX (RO/P) + * + * 10BASE-Te Full Duplex Capable: + * 1 = Device able to perform 10BASE-Te in full duplex mode. + */ +#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK (0x1000U) +#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT (12U) +#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT) + +/* + * 10BASE_TE_HALF_DUPLEX (RO/P) + * + * 10BASE-Te Half Duplex Capable: + * 1 = Device able to perform 10BASE-Te in half duplex mode. + */ +#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK (0x800U) +#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT (11U) +#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT) + +/* + * 100BASE_T2_FULL_DUPLEX (RO/P) + * + * 100BASE-T2 Full Duplex Capable: + * 0 = Device not able to perform 100BASE-T2 in full duplex mode. + */ +#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK (0x400U) +#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT (10U) +#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT) + +/* + * 100BASE_T2_HALF_DUPLEX (RO/P) + * + * 100BASE-T2 Half Duplex Capable: + * 0 = Device not able to perform 100BASE-T2 in half duplex mode. + */ +#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK (0x200U) +#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT (9U) +#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT) + +/* + * EXTENDED_STATUS (RO/P) + * + * 1000BASE-T Extended Status Register: + * 1 = Device supports Extended Status Register 0x0F. + */ +#define DP83867_BMSR_EXTENDED_STATUS_MASK (0x100U) +#define DP83867_BMSR_EXTENDED_STATUS_SHIFT (8U) +#define DP83867_BMSR_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_STATUS_MASK) >> DP83867_BMSR_EXTENDED_STATUS_SHIFT) + +/* + * MF_PREAMBLE_SUPPRESSION (RO/P) + * + * Preamble Suppression Capable: + * 1 = Device able to perform management transaction with preamble + * suppressed, 32-bits of preamble needed only once after reset, + * invalid opcode or invalid turnaround. + * 0 = Normal management operation. + */ +#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * Auto-Negotiation Complete: + * 1 = Auto-Negotiation process complete. + * 0 = Auto-Negotiation process not complete. + */ +#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RO/LH) + * + * Remote Fault: + * 1 = Remote Fault condition detected (cleared on read or by reset). + * Fault criteria: Far-End Fault Indication or notification from Link + * Partner of Remote Fault. + * 0 = No remote fault condition detected. + */ +#define DP83867_BMSR_REMOTE_FAULT_MASK (0x10U) +#define DP83867_BMSR_REMOTE_FAULT_SHIFT (4U) +#define DP83867_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83867_BMSR_REMOTE_FAULT_MASK) >> DP83867_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY ( RO/P ) + * + * Auto Negotiation Ability: + * 1 = Device is able to perform Auto-Negotiation. + * 0 = Device is not able to perform Auto-Negotiation. + */ +#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS ( RO/LL) + * * Link Status: * 1 = Valid link established. * 0 = Link not established. @@ -200,45 +328,2161 @@ * occurrence of a link failure condition will causes the Link Status bit * to clear. Once cleared, this bit may only be set by establishing a * good link condition and a read through the management interface. -*/ -#define DP83867_BMSR_LINK_STATUS_MASK (0x0004U) + */ +#define DP83867_BMSR_LINK_STATUS_MASK (0x4U) #define DP83867_BMSR_LINK_STATUS_SHIFT (2U) -#define DP83867_BMSR_LINK_STATUS_GET(x) (((uint32_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT) +#define DP83867_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT) - - -/* Bitfield definition for register: PHYID1 */ /* - * OUI_MSB (RO) + * JABBER_DETECT ( RO/LH) * - * Organizationally Unique Identifier Bit 3:18. - * Always 0000000000011100. + * Jabber Detect: This bit only has meaning in 10-Mbps mode. + * 1 = Jabber condition detected. + * 0 = No Jabber. + * This bit is implemented with a latching function, such that the + * occurrence of a jabber condition causes it to set until it is cleared by + * a read to this register by the management interface or by a reset. */ -#define DP83867_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define DP83867_PHYID1_OUI_MSB_SHIFT (0U) -#define DP83867_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & DP83867_PHYID1_OUI_MSB_MASK) >> DP83867_PHYID1_OUI_MSB_SHIFT) +#define DP83867_BMSR_JABBER_DETECT_MASK (0x2U) +#define DP83867_BMSR_JABBER_DETECT_SHIFT (1U) +#define DP83867_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_BMSR_JABBER_DETECT_MASK) >> DP83867_BMSR_JABBER_DETECT_SHIFT) -/* Bitfield definition for register: PHYID2 */ /* - * OUI_LSB (RO) + * EXTENDED_CAPABILITY (RO/P) * - * Organizationally Unique Identifier Bit 19:24. - * Always 110010. + * Extended Capability: + * 1 = Extended register capabilities. + * 0 = Basic register set capabilities only. */ -#define DP83867_PHYID2_OUI_MSB_MASK (0xFC00U) -#define DP83867_PHYID2_OUI_MSB_SHIFT (10U) -#define DP83867_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & DP83867_PHYID2_OUI_MSB_MASK) >> DP83867_PHYID2_OUI_MSB_SHIFT) +#define DP83867_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define DP83867_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT) -/* Bitfield definition for register: RGMIICTL */ +/* Bitfield definition for register: PHYIDR1 */ /* - * RGMII_EN (RW) + * OUI_MSB (RO/P) * - * RGMII Enable: - * 1 = Enable RGMII interface. - * 0 = Disable RGMII interface + * OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are + * stored in bits 15 to 0 of this register. The most significant two bits of + * the OUI are ignored (the IEEE standard refers to these as bits 1 and + * 2). */ -#define DP83867_RGMIICTL_RGMII_EN_MASK (0x80) -#define DP83867_RGMIICTL_RGMII_EN_SHIFT (7U) -#define DP83867_RGMIICTL_RGMII_EN_SET(x) (((uint32_t)(x) << DP83867_RGMIICTL_RGMII_EN_SHIFT) & DP83867_RGMIICTL_RGMII_EN_MASK) -#define DP83867_RGMIICTL_RGMII_EN_GET(x) (((uint32_t)(x) & DP83867_RGMIICTL_RGMII_EN_SHIFT) >> DP83867_RGMIICTL_RGMII_EN_MASK) -#endif /* HPM_DP83867_REGS_H */ \ No newline at end of file +#define DP83867_PHYIDR1_OUI_MSB_MASK (0xFFFFU) +#define DP83867_PHYIDR1_OUI_MSB_SHIFT (0U) +#define DP83867_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR1_OUI_MSB_MASK) >> DP83867_PHYIDR1_OUI_MSB_SHIFT) + +/* Bitfield definition for register: PHYIDR2 */ +/* + * OUI_LSB (RO/P) + * + * OUI Least Significant Bits: + * Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of + * this register respectively. + */ +#define DP83867_PHYIDR2_OUI_LSB_MASK (0xFC00U) +#define DP83867_PHYIDR2_OUI_LSB_SHIFT (10U) +#define DP83867_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_OUI_LSB_MASK) >> DP83867_PHYIDR2_OUI_LSB_SHIFT) + +/* + * VNDR_MDL (RO/P) + * + * Vendor Model Number: + * The six bits of vendor model number are mapped from bits 9 to 4 + * (most significant bit to bit 9). + */ +#define DP83867_PHYIDR2_VNDR_MDL_MASK (0x3F0U) +#define DP83867_PHYIDR2_VNDR_MDL_SHIFT (4U) +#define DP83867_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_VNDR_MDL_MASK) >> DP83867_PHYIDR2_VNDR_MDL_SHIFT) + +/* + * MDL_REV (RO/P) + * + * Model Revision Number: + * Four bits of the vendor model revision number are mapped from bits + * 3 to 0 (most significant bit to bit 3). This field will be incremented for + * all major device changes. + */ +#define DP83867_PHYIDR2_MDL_REV_MASK (0xFU) +#define DP83867_PHYIDR2_MDL_REV_SHIFT (0U) +#define DP83867_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_MDL_REV_MASK) >> DP83867_PHYIDR2_MDL_REV_SHIFT) + +/* Bitfield definition for register: ANAR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = Next Page Transfer not desired. + * 1 = Next Page Transfer desired. + */ +#define DP83867_ANAR_NP_MASK (0x8000U) +#define DP83867_ANAR_NP_SHIFT (15U) +#define DP83867_ANAR_NP_SET(x) (((uint16_t)(x) << DP83867_ANAR_NP_SHIFT) & DP83867_ANAR_NP_MASK) +#define DP83867_ANAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANAR_NP_MASK) >> DP83867_ANAR_NP_SHIFT) + +/* + * RF (RW) + * + * Remote Fault: + * 1 = Advertises that this device has detected a Remote Fault. + * 0 = No Remote Fault detected. + */ +#define DP83867_ANAR_RF_MASK (0x2000U) +#define DP83867_ANAR_RF_SHIFT (13U) +#define DP83867_ANAR_RF_SET(x) (((uint16_t)(x) << DP83867_ANAR_RF_SHIFT) & DP83867_ANAR_RF_MASK) +#define DP83867_ANAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANAR_RF_MASK) >> DP83867_ANAR_RF_SHIFT) + +/* + * ASM_DIR (RW) + * + * Asymmetric PAUSE Support for Full Duplex Links: + * The ASM_DIR bit indicates that asymmetric PAUSE is supported. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 + * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution + * status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the + * optional MAC control sublayer and the pause function as specified + * in clause 31 and annex 31B of 802.3u. + * 0 = No MAC based full duplex flow control. + */ +#define DP83867_ANAR_ASM_DIR_MASK (0x800U) +#define DP83867_ANAR_ASM_DIR_SHIFT (11U) +#define DP83867_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83867_ANAR_ASM_DIR_SHIFT) & DP83867_ANAR_ASM_DIR_MASK) +#define DP83867_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANAR_ASM_DIR_MASK) >> DP83867_ANAR_ASM_DIR_SHIFT) + +/* + * PAUSE (RW) + * + * PAUSE Support for Full Duplex Links: + * The PAUSE bit indicates that the device is capable of providing the + * symmetric PAUSE functions as defined in Annex 31B. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 + * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution + * status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the + * optional MAC control sublayer and the pause function as specified + * in clause 31 and annex 31B of 802.3u. + * 0 = No MAC based full duplex flow control. + */ +#define DP83867_ANAR_PAUSE_MASK (0x400U) +#define DP83867_ANAR_PAUSE_SHIFT (10U) +#define DP83867_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83867_ANAR_PAUSE_SHIFT) & DP83867_ANAR_PAUSE_MASK) +#define DP83867_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANAR_PAUSE_MASK) >> DP83867_ANAR_PAUSE_SHIFT) + +/* + * T4 (RO/P) + * + * 100BASE-T4 Support: + * 1 = 100BASE-T4 is supported by the local device. + * 0 = 100BASE-T4 not supported. + */ +#define DP83867_ANAR_T4_MASK (0x200U) +#define DP83867_ANAR_T4_SHIFT (9U) +#define DP83867_ANAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANAR_T4_MASK) >> DP83867_ANAR_T4_SHIFT) + +/* + * TX_FD (STRAP, RW) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the local device. + * 0 = 100BASE-TX Full Duplex not supported. + */ +#define DP83867_ANAR_TX_FD_MASK (0x100U) +#define DP83867_ANAR_TX_FD_SHIFT (8U) +#define DP83867_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_FD_SHIFT) & DP83867_ANAR_TX_FD_MASK) +#define DP83867_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_FD_MASK) >> DP83867_ANAR_TX_FD_SHIFT) + +/* + * TX (STRAP, RW) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the local device. + * 0 = 100BASE-TX not supported. + */ +#define DP83867_ANAR_TX_MASK (0x80U) +#define DP83867_ANAR_TX_SHIFT (7U) +#define DP83867_ANAR_TX_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_SHIFT) & DP83867_ANAR_TX_MASK) +#define DP83867_ANAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_MASK) >> DP83867_ANAR_TX_SHIFT) + +/* + * 10_FD (STRAP, RW) + * + * 10BASE-Te Full Duplex Support: + * 1 = 10BASE-Te Full Duplex is supported by the local device. + * 0 = 10BASE-Te Full Duplex not supported. + */ +#define DP83867_ANAR_10_FD_MASK (0x40U) +#define DP83867_ANAR_10_FD_SHIFT (6U) +#define DP83867_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_10_FD_SHIFT) & DP83867_ANAR_10_FD_MASK) +#define DP83867_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_10_FD_MASK) >> DP83867_ANAR_10_FD_SHIFT) + +/* + * 10BASETE_EN (STRAP, RW) + * + * 10BASE-Te Support: + * 1 = 10BASE-Te is supported by the local device. + * 0 = 10BASE-Te not supported. + */ +#define DP83867_ANAR_10BASETE_EN_MASK (0x20U) +#define DP83867_ANAR_10BASETE_EN_SHIFT (5U) +#define DP83867_ANAR_10BASETE_EN_SET(x) (((uint16_t)(x) << DP83867_ANAR_10BASETE_EN_SHIFT) & DP83867_ANAR_10BASETE_EN_MASK) +#define DP83867_ANAR_10BASETE_EN_GET(x) (((uint16_t)(x) & DP83867_ANAR_10BASETE_EN_MASK) >> DP83867_ANAR_10BASETE_EN_SHIFT) + +/* + * SELECTOR (RW) + * + * Protocol Selection Bits: + * These bits contain the binary encoded protocol selector supported + * by this port. <00001> indicates that this device supports IEEE + * 802.3u. + */ +#define DP83867_ANAR_SELECTOR_MASK (0x1FU) +#define DP83867_ANAR_SELECTOR_SHIFT (0U) +#define DP83867_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83867_ANAR_SELECTOR_SHIFT) & DP83867_ANAR_SELECTOR_MASK) +#define DP83867_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANAR_SELECTOR_MASK) >> DP83867_ANAR_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANLPAR */ +/* + * NP (RO) + * + * Next Page Indication: + * 0 = Link Partner does not desire Next Page Transfer. + * 1 = Link Partner desires Next Page Transfer. + */ +#define DP83867_ANLPAR_NP_MASK (0x8000U) +#define DP83867_ANLPAR_NP_SHIFT (15U) +#define DP83867_ANLPAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_NP_MASK) >> DP83867_ANLPAR_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Link Partner acknowledges reception of the ability data word. + * 0 = Not acknowledged. + * The Auto-Negotiation state machine will automatically control this bit + * based on the incoming FLP bursts. + */ +#define DP83867_ANLPAR_ACK_MASK (0x4000U) +#define DP83867_ANLPAR_ACK_SHIFT (14U) +#define DP83867_ANLPAR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ACK_MASK) >> DP83867_ANLPAR_ACK_SHIFT) + +/* + * RF (RO) + * + * Remote Fault: + * 1 = Remote Fault indicated by Link Partner. + * 0 = No Remote Fault indicated by Link Partner. + */ +#define DP83867_ANLPAR_RF_MASK (0x2000U) +#define DP83867_ANLPAR_RF_SHIFT (13U) +#define DP83867_ANLPAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_RF_MASK) >> DP83867_ANLPAR_RF_SHIFT) + +/* + * ASM_DIR (RO) + * + * ASYMMETRIC PAUSE: + * 1 = Asymmetric pause is supported by the Link Partner. + * 0 = Asymmetric pause is not supported by the Link Partner. + */ +#define DP83867_ANLPAR_ASM_DIR_MASK (0x800U) +#define DP83867_ANLPAR_ASM_DIR_SHIFT (11U) +#define DP83867_ANLPAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ASM_DIR_MASK) >> DP83867_ANLPAR_ASM_DIR_SHIFT) + +/* + * PAUSE (RO) + * + * PAUSE: + * 1 = Pause function is supported by the Link Partner. + * 0 = Pause function is not supported by the Link Partner. + */ +#define DP83867_ANLPAR_PAUSE_MASK (0x400U) +#define DP83867_ANLPAR_PAUSE_SHIFT (10U) +#define DP83867_ANLPAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_PAUSE_MASK) >> DP83867_ANLPAR_PAUSE_SHIFT) + +/* + * T4 (RO) + * + * 100BASE-T4 Support: + * 1 = 100BASE-T4 is supported by the Link Partner. + * 0 = 100BASE-T4 not supported by the Link Partner. + */ +#define DP83867_ANLPAR_T4_MASK (0x200U) +#define DP83867_ANLPAR_T4_SHIFT (9U) +#define DP83867_ANLPAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_T4_MASK) >> DP83867_ANLPAR_T4_SHIFT) + +/* + * TX_FD (RO) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the Link Partner. + * 0 = 100BASE-TX Full Duplex not supported by the Link Partner. + */ +#define DP83867_ANLPAR_TX_FD_MASK (0x100U) +#define DP83867_ANLPAR_TX_FD_SHIFT (8U) +#define DP83867_ANLPAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_FD_MASK) >> DP83867_ANLPAR_TX_FD_SHIFT) + +/* + * TX (RO) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the Link Partner. + * 0 = 100BASE-TX not supported by the Link Partner. + */ +#define DP83867_ANLPAR_TX_MASK (0x80U) +#define DP83867_ANLPAR_TX_SHIFT (7U) +#define DP83867_ANLPAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_MASK) >> DP83867_ANLPAR_TX_SHIFT) + +/* + * 10_FD (RO) + * + * 10BASE-Te Full Duplex Support: + * 1 = 10BASE-Te Full Duplex is supported by the Link Partner. + * 0 = 10BASE-Te Full Duplex not supported by the Link Partner. + */ +#define DP83867_ANLPAR_10_FD_MASK (0x40U) +#define DP83867_ANLPAR_10_FD_SHIFT (6U) +#define DP83867_ANLPAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_FD_MASK) >> DP83867_ANLPAR_10_FD_SHIFT) + +/* + * 10 (RO) + * + * 10BASE-Te Support: + * 1 = 10BASE-Te is supported by the Link Partner. + * 0 = 10BASE-Te not supported by the Link Partner. + */ +#define DP83867_ANLPAR_10_MASK (0x20U) +#define DP83867_ANLPAR_10_SHIFT (5U) +#define DP83867_ANLPAR_10_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_MASK) >> DP83867_ANLPAR_10_SHIFT) + +/* + * SELECTOR (RO) + * + * Protocol Selection Bits: + * Link Partner's binary encoded protocol selector. + */ +#define DP83867_ANLPAR_SELECTOR_MASK (0x1FU) +#define DP83867_ANLPAR_SELECTOR_SHIFT (0U) +#define DP83867_ANLPAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_SELECTOR_MASK) >> DP83867_ANLPAR_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANER */ +/* + * RX_NEXT_PAGE_LOC_ABLE (RO) + * + * Receive Next Page Location Able: + * 1 = Received Next Page storage location is specified by bit 6.5. + * 0 = Received Next Page storage location is not specified by bit 6.5. + */ +#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK (0x40U) +#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT (6U) +#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK) >> DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT) + +/* + * RX_NEXT_PAGE_STOR_LOC (RO) + * + * Receive Next Page Storage Location: + * 1 = Link Partner Next Pages are stored in register 8. + * 0 = Link Partner Next Pages are stored in register 5. + */ +#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK (0x20U) +#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT (5U) +#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK) >> DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT) + +/* + * PDF (RO) + * + * Parallel Detection Fault: + * 1 = A fault has been detected via the Parallel Detection function. + * 0 = A fault has not been detected. + */ +#define DP83867_ANER_PDF_MASK (0x10U) +#define DP83867_ANER_PDF_SHIFT (4U) +#define DP83867_ANER_PDF_GET(x) (((uint16_t)(x) & DP83867_ANER_PDF_MASK) >> DP83867_ANER_PDF_SHIFT) + +/* + * LP_NP_ABLE (RO) + * + * Link Partner Next Page Able: + * 1 = Link Partner does support Next Page. + * 0 = Link Partner does not support Next Page. + */ +#define DP83867_ANER_LP_NP_ABLE_MASK (0x8U) +#define DP83867_ANER_LP_NP_ABLE_SHIFT (3U) +#define DP83867_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_NP_ABLE_MASK) >> DP83867_ANER_LP_NP_ABLE_SHIFT) + +/* + * NP_ABLE (RO/P) + * + * Next Page Able: + * 1 = Indicates local device is able to send additional Next Pages. + */ +#define DP83867_ANER_NP_ABLE_MASK (0x4U) +#define DP83867_ANER_NP_ABLE_SHIFT (2U) +#define DP83867_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_NP_ABLE_MASK) >> DP83867_ANER_NP_ABLE_SHIFT) + +/* + * PAGE_RX (RO/COR) + * + * Link Code Word Page Received: + * 1 = Link Code Word has been received, cleared on a read. + * 0 = Link Code Word has not been received. + */ +#define DP83867_ANER_PAGE_RX_MASK (0x2U) +#define DP83867_ANER_PAGE_RX_SHIFT (1U) +#define DP83867_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83867_ANER_PAGE_RX_MASK) >> DP83867_ANER_PAGE_RX_SHIFT) + +/* + * LP_AN_ABLE (RO) + * + * Link Partner Auto-Negotiation Able: + * 1 = Indicates that the Link Partner supports Auto-Negotiation. + * 0 = Indicates that the Link Partner does not support Auto- + * Negotiation. + */ +#define DP83867_ANER_LP_AN_ABLE_MASK (0x1U) +#define DP83867_ANER_LP_AN_ABLE_SHIFT (0U) +#define DP83867_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_AN_ABLE_MASK) >> DP83867_ANER_LP_AN_ABLE_SHIFT) + +/* Bitfield definition for register: ANNPTR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = No other Next Page Transfer desired. + * 1 = Another Next Page desired. + */ +#define DP83867_ANNPTR_NP_MASK (0x8000U) +#define DP83867_ANNPTR_NP_SHIFT (15U) +#define DP83867_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_NP_SHIFT) & DP83867_ANNPTR_NP_MASK) +#define DP83867_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_NP_MASK) >> DP83867_ANNPTR_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Acknowledge reception of link code word + * 0 = Do not acknowledge of link code word. + */ +#define DP83867_ANNPTR_ACK_MASK (0x4000U) +#define DP83867_ANNPTR_ACK_SHIFT (14U) +#define DP83867_ANNPTR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK_MASK) >> DP83867_ANNPTR_ACK_SHIFT) + +/* + * MP (RW) + * + * Message Page: + * 1 = Current page is a Message Page. + * 0 = Current page is an Unformatted Page. + */ +#define DP83867_ANNPTR_MP_MASK (0x2000U) +#define DP83867_ANNPTR_MP_SHIFT (13U) +#define DP83867_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_MP_SHIFT) & DP83867_ANNPTR_MP_MASK) +#define DP83867_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_MP_MASK) >> DP83867_ANNPTR_MP_SHIFT) + +/* + * ACK2 (RW) + * + * Acknowledge2: + * 1 = Will comply with message. + * 0 = Cannot comply with message. + * Acknowledge2 is used by the next page function to indicate that + * Local Device has the ability to comply with the message received. + */ +#define DP83867_ANNPTR_ACK2_MASK (0x1000U) +#define DP83867_ANNPTR_ACK2_SHIFT (12U) +#define DP83867_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_ACK2_SHIFT) & DP83867_ANNPTR_ACK2_MASK) +#define DP83867_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK2_MASK) >> DP83867_ANNPTR_ACK2_SHIFT) + +/* + * TOG_TX (RO) + * + * Toggle: + * 1 = Value of toggle bit in previously transmitted Link Code Word + * was 0. + * 0 = Value of toggle bit in previously transmitted Link Code Word + * was 1. + * Toggle is used by the Arbitration function within Auto-Negotiation to + * ensure synchronization with the Link Partner during Next Page + * exchange. This bit shall always take the opposite value of the + * Toggle bit in the previously exchanged Link Code Word. + */ +#define DP83867_ANNPTR_TOG_TX_MASK (0x800U) +#define DP83867_ANNPTR_TOG_TX_SHIFT (11U) +#define DP83867_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_TOG_TX_MASK) >> DP83867_ANNPTR_TOG_TX_SHIFT) + +/* + * CODE (RW) + * + * Code: + * This field represents the code field of the next page transmission. If + * the MP bit is set (bit 13 of this register), then the code shall be + * interpreted as a "Message Page”, as defined in Annex 28C of IEEE + * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted + * Page”, and the interpretation is application specific. + * The default value of the CODE represents a Null Page as defined in + * Annex 28C of IEEE 802.3u. + */ +#define DP83867_ANNPTR_CODE_MASK (0x7FFU) +#define DP83867_ANNPTR_CODE_SHIFT (0U) +#define DP83867_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_CODE_SHIFT) & DP83867_ANNPTR_CODE_MASK) +#define DP83867_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_CODE_MASK) >> DP83867_ANNPTR_CODE_SHIFT) + +/* Bitfield definition for register: ANNPRR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = No other Next Page Transfer desired by the link partner. + * 1 = Another Next Page desired by the link partner. + */ +#define DP83867_ANNPRR_NP_MASK (0x8000U) +#define DP83867_ANNPRR_NP_SHIFT (15U) +#define DP83867_ANNPRR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_NP_SHIFT) & DP83867_ANNPRR_NP_MASK) +#define DP83867_ANNPRR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_NP_MASK) >> DP83867_ANNPRR_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Acknowledge reception of link code word by the link partner. + * 0 = Link partner does not acknowledge reception of link code word. + */ +#define DP83867_ANNPRR_ACK_MASK (0x4000U) +#define DP83867_ANNPRR_ACK_SHIFT (14U) +#define DP83867_ANNPRR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK_MASK) >> DP83867_ANNPRR_ACK_SHIFT) + +/* + * MP (RW) + * + * Message Page: + * 1 = Received page is a Message Page. + * 0 = Received page is an Unformatted Page. + */ +#define DP83867_ANNPRR_MP_MASK (0x2000U) +#define DP83867_ANNPRR_MP_SHIFT (13U) +#define DP83867_ANNPRR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_MP_SHIFT) & DP83867_ANNPRR_MP_MASK) +#define DP83867_ANNPRR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_MP_MASK) >> DP83867_ANNPRR_MP_SHIFT) + +/* + * ACK2 (RW) + * + * Acknowledge2: + * 1 = Link partner sets the ACK2 bit. + * 0 = Link partner coes not set the ACK2 bit. + * Acknowledge2 is used by the next page function to indicate that link + * partner has the ability to comply with the message received. + */ +#define DP83867_ANNPRR_ACK2_MASK (0x1000U) +#define DP83867_ANNPRR_ACK2_SHIFT (12U) +#define DP83867_ANNPRR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_ACK2_SHIFT) & DP83867_ANNPRR_ACK2_MASK) +#define DP83867_ANNPRR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK2_MASK) >> DP83867_ANNPRR_ACK2_SHIFT) + +/* + * TOG_TX (RO) + * + * Toggle: + * 1 = Value of toggle bit in previously transmitted Link Code Word + * was 0. + * 0 = Value of toggle bit in previously transmitted Link Code Word + * was 1. + * Toggle is used by the Arbitration function within Auto-Negotiation to + * ensure synchronization with the Link Partner during Next Page + * exchange. This bit shall always take the opposite value of the + * Toggle bit in the previously exchanged Link Code Word. + */ +#define DP83867_ANNPRR_TOG_TX_MASK (0x800U) +#define DP83867_ANNPRR_TOG_TX_SHIFT (11U) +#define DP83867_ANNPRR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_TOG_TX_MASK) >> DP83867_ANNPRR_TOG_TX_SHIFT) + +/* + * CODE (RW) + * + * Code: + * This field represents the code field of the next page transmission. If + * the MP bit is set (bit 13 of this register), then the code shall be + * interpreted as a "Message Page”, as defined in Annex 28C of IEEE + * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted + * Page”, and the interpretation is application specific. + * The default value of the CODE represents a Null Page as defined in + * Annex 28C of IEEE 802.3u. + */ +#define DP83867_ANNPRR_CODE_MASK (0x7FFU) +#define DP83867_ANNPRR_CODE_SHIFT (0U) +#define DP83867_ANNPRR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_CODE_SHIFT) & DP83867_ANNPRR_CODE_MASK) +#define DP83867_ANNPRR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_CODE_MASK) >> DP83867_ANNPRR_CODE_SHIFT) + +/* Bitfield definition for register: CFG1 */ +/* + * TEST_MODE (RW) + * + * Test Mode Select: + * 111 = Test Mode 7 - Repetitive {Pulse, 63 zeros} + * 110 = Test Mode 6 - Repetitive 0001 sequence + * 101 = Test Mode 5 - Scrambled MLT3 Idles + * 100 = Test Mode 4 - Transmit Distortion Test + * 011 = Test Mode 3 - Transmit Jitter Test (Slave Mode) + * 010 = Test Mode 2 - Transmit Jitter Test (Master Mode) + * 001 = Test Mode 1 - Transmit Waveform Test + * 000 = Normal Mode + */ +#define DP83867_CFG1_TEST_MODE_MASK (0xE000U) +#define DP83867_CFG1_TEST_MODE_SHIFT (13U) +#define DP83867_CFG1_TEST_MODE_SET(x) (((uint16_t)(x) << DP83867_CFG1_TEST_MODE_SHIFT) & DP83867_CFG1_TEST_MODE_MASK) +#define DP83867_CFG1_TEST_MODE_GET(x) (((uint16_t)(x) & DP83867_CFG1_TEST_MODE_MASK) >> DP83867_CFG1_TEST_MODE_SHIFT) + +/* + * MASTER_SLAVE_MANUAL_CONFIGURATION (RW) + * + * Enable Manual Master / Slave Configuration: + * 1 = Enable Manual Master/Slave Configuration control. + * 0 = Disable Manual Master/Slave Configuration control. + * Using the manual configuration feature may prevent the PHY from + * establishing link in 1000Base-T mode if a conflict with the link + * partner’s setting exists. + */ +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK (0x1000U) +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT (12U) +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) >> DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) + +/* + * MASTER_SLAVE_CONFIGURATION_VALUE (RW) + * + * Manual Master / Slave Configuration Value: + * 1 = Set PHY as MASTER when register 09h bit 12 = 1. + * 0 = Set PHY as SLAVE when register 09h bit 12 = 1. + * Using the manual configuration feature may prevent the PHY from + * establishing link in 1000Base-T mode if a conflict with the link + * partner’s setting exists. + */ +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK (0x800U) +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT (11U) +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) >> DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) + +/* + * PORT_TYPE (RW) + * + * Advertise Device Type: Multi or single port: + * 1 = Multi-port device. + * 0 = Single-port device. + */ +#define DP83867_CFG1_PORT_TYPE_MASK (0x400U) +#define DP83867_CFG1_PORT_TYPE_SHIFT (10U) +#define DP83867_CFG1_PORT_TYPE_SET(x) (((uint16_t)(x) << DP83867_CFG1_PORT_TYPE_SHIFT) & DP83867_CFG1_PORT_TYPE_MASK) +#define DP83867_CFG1_PORT_TYPE_GET(x) (((uint16_t)(x) & DP83867_CFG1_PORT_TYPE_MASK) >> DP83867_CFG1_PORT_TYPE_SHIFT) + +/* + * 1000BASE_T_FULL_DUPLEX (RW) + * + * Advertise 1000BASE-T Full Duplex Capable: + * 1 = Advertise 1000Base-T Full Duplex ability. + * 0 = Do not advertise 1000Base-T Full Duplex ability. + */ +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK (0x200U) +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT (9U) +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) + +/* + * 1000BASE_T_HALF_DUPLEX (RW) + * + * Advertise 1000BASE-T Half Duplex Capable: + * 1 = Advertise 1000Base-T Half Duplex ability. + * 0 = Do not advertise 1000Base-T Half Duplex ability. + */ +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK (0x100U) +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT (8U) +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) + +/* + * TDR_AUTO_RUN (RW) + * + * Automatic TDR on Link Down: + * 1 = Enable execution of TDR procedure after link down event. + * 0 = Disable automatic execution of TDR. + */ +#define DP83867_CFG1_TDR_AUTO_RUN_MASK (0x80U) +#define DP83867_CFG1_TDR_AUTO_RUN_SHIFT (7U) +#define DP83867_CFG1_TDR_AUTO_RUN_SET(x) (((uint16_t)(x) << DP83867_CFG1_TDR_AUTO_RUN_SHIFT) & DP83867_CFG1_TDR_AUTO_RUN_MASK) +#define DP83867_CFG1_TDR_AUTO_RUN_GET(x) (((uint16_t)(x) & DP83867_CFG1_TDR_AUTO_RUN_MASK) >> DP83867_CFG1_TDR_AUTO_RUN_SHIFT) + +/* Bitfield definition for register: STS1 */ +/* + * MASTER_SLAVE_CONFIGURATION_FAULT (RO, LH, COR) + * + * Master / Slave Manual Configuration Fault Detected: + * 1 = Manual Master/Slave Configuration fault detected. + * 0 = No Manual Master/Slave Configuration fault detected. + */ +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK (0x8000U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT (15U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT) + +/* + * MASTER_SLAVE_CONFIGURATION_RESOLUTION (RO) + * + * Master / Slave Configuration Results: + * 1 = Configuration resolved to MASTER. + * 0 = Configuration resolved to SLAVE. + */ +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK (0x4000U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT (14U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT) + +/* + * LOCAL_RECEIVER_STATUS (RO) + * + * Local Receiver Status: + * 1 = Local receiver is OK. + * 0 = Local receiver is not OK. + */ +#define DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK (0x2000U) +#define DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT (13U) +#define DP83867_STS1_LOCAL_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK) >> DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT) + +/* + * REMOTE_RECEIVER_STATUS (RO) + * + * Remote Receiver Status: + * 1 = Remote receiver is OK. + * 0 = Remote receiver is not OK. + */ +#define DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK (0x1000U) +#define DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT (12U) +#define DP83867_STS1_REMOTE_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK) >> DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT) + +/* + * 1000BASE_T_FULL_DUPLEX (RO) + * + * Link Partner 1000BASE-T Full Duplex Capable: + * 1 = Link Partner capable of 1000Base-T Full Duplex. + * 0 = Link partner not capable of 1000Base-T Full Duplex. + */ +#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK (0x800U) +#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT (11U) +#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT) + +/* + * 1000BASE_T_HALF_DUPLEX (RO) + * + * Link Partner 1000BASE-T Half Duplex Capable: + * 1 = Link Partner capable of 1000Base-T Half Duplex. + * 0 = Link partner not capable of 1000Base-T Half Duplex. + */ +#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK (0x400U) +#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT (10U) +#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT) + +/* + * IDLE_ERROR_COUNTER (RO,COR) + * + * 1000BASE-T Idle Error Counter + */ +#define DP83867_STS1_IDLE_ERROR_COUNTER_MASK (0xFFU) +#define DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT (0U) +#define DP83867_STS1_IDLE_ERROR_COUNTER_GET(x) (((uint16_t)(x) & DP83867_STS1_IDLE_ERROR_COUNTER_MASK) >> DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT) + +/* Bitfield definition for register: REGCR */ +/* + * FUNCTION (RW) + * + * 00 = Address + * 01 = Data, no post increment + * 10 = Data, post increment on read and write + * 11 = Data, post increment on write only + */ +#define DP83867_REGCR_FUNCTION_MASK (0xC000U) +#define DP83867_REGCR_FUNCTION_SHIFT (14U) +#define DP83867_REGCR_FUNCTION_SET(x) (((uint16_t)(x) << DP83867_REGCR_FUNCTION_SHIFT) & DP83867_REGCR_FUNCTION_MASK) +#define DP83867_REGCR_FUNCTION_GET(x) (((uint16_t)(x) & DP83867_REGCR_FUNCTION_MASK) >> DP83867_REGCR_FUNCTION_SHIFT) + +/* + * DEVAD (RW) + * + * Device Address: In general, these bits [4:0] are the device address + * DEVAD that directs any accesses of ADDAR register (0x000E) to + * the appropriate MMD. Specifically, the DP83867 uses the vendor + * specific DEVAD [4:0] = 11111 for accesses. All accesses through + * registers REGCR and ADDAR should use this DEVAD. + * Transactions with other DEVAD are ignored. + */ +#define DP83867_REGCR_DEVAD_MASK (0x1FU) +#define DP83867_REGCR_DEVAD_SHIFT (0U) +#define DP83867_REGCR_DEVAD_SET(x) (((uint16_t)(x) << DP83867_REGCR_DEVAD_SHIFT) & DP83867_REGCR_DEVAD_MASK) +#define DP83867_REGCR_DEVAD_GET(x) (((uint16_t)(x) & DP83867_REGCR_DEVAD_MASK) >> DP83867_REGCR_DEVAD_SHIFT) + +/* Bitfield definition for register: ADDAR */ +/* + * ADDRESS_OR_DATA_REGISTER (RW) + * + * If REGCR register 15:14 = 00, holds the MMD DEVAD's address + * register, otherwise holds the MMD DEVAD's data register + */ +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK (0xFFFFU) +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT (0U) +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SET(x) (((uint16_t)(x) << DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_GET(x) (((uint16_t)(x) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) >> DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) + +/* Bitfield definition for register: 1KSCR */ +/* + * 1000BASE_X_FULL_DUPLEX (RO/P) + * + * 1000BASE-X Full Duplex Support: + * 1 = 1000BASE-X Full Duplex is supported by the local device. + * 0 = 1000BASE-X Full Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK (0x8000U) +#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT (15U) +#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT) + +/* + * 1000BASE_X_HALF_DUPLEX (RO/P) + * + * 1000BASE-X Half Duplex Support: + * 1 = 1000BASE-X Half Duplex is supported by the local device. + * 0 = 1000BASE-X Half Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK (0x4000U) +#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT (14U) +#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT) + +/* + * 1000BASE_T_FULL_DUPLEX (RO/P) + * + * 1000BASE-T Full Duplex Support: + * 1 = 1000BASE-T Full Duplex is supported by the local device. + * 0 = 1000BASE-T Full Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK (0x2000U) +#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT (13U) +#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT) + +/* + * 1000BASE_T_HALF_DUPLEX (RO/P) + * + * 1000BASE-T Half Duplex Support: + * 1 = 1000BASE-T Half Duplex is supported by the local device. + * 0 = 1000BASE-T Half Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK (0x1000U) +#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT (12U) +#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT) + +/* Bitfield definition for register: PHYCR */ +/* + * TX_FIFO_DEPTH (RW) + * + * TX FIFO Depth: + * 11 = 8 bytes/nibbles (1000Mbps/Other Speeds) + * 10 = 6 bytes/nibbles (1000Mbps/Other Speeds) + * 01 = 4 bytes/nibbles (1000Mbps/Other Speeds) + * 00 = 3 bytes/nibbles (1000Mbps/Other Speeds) + * Note: FIFO is enabled only in the following modes: + * 1000BaseT + GMII + * 10BaseT/100BaseTX/1000BaseT + SGMII + */ +#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK (0xC000U) +#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT (14U) +#define DP83867_PHYCR_TX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) +#define DP83867_PHYCR_TX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) + +/* + * RX_FIFO_DEPTH (RW) + * + * RX FIFO Depth: + * 11 = 8 bytes/nibbles (1000 Mbps/Other Speeds) + * 10 = 6 bytes/nibbles (1000 Mbps/Other Speeds) + * 01 = 4 bytes/nibbles (1000 Mbps/Other Speeds) + * 00 = 3 bytes/nibbles (1000 Mbps/Other Speeds) + * Note: FIFO is enabled only in SGMII + */ +#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK (0x3000U) +#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT (12U) +#define DP83867_PHYCR_RX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) +#define DP83867_PHYCR_RX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) + +/* + * SGMII_EN (RW) + * + * SGMII Enable: + * 1 = Enable SGMII + * 0 = Disable SGMII + */ +#define DP83867_PHYCR_SGMII_EN_MASK (0x800U) +#define DP83867_PHYCR_SGMII_EN_SHIFT (11U) +#define DP83867_PHYCR_SGMII_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_SGMII_EN_SHIFT) & DP83867_PHYCR_SGMII_EN_MASK) +#define DP83867_PHYCR_SGMII_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_SGMII_EN_MASK) >> DP83867_PHYCR_SGMII_EN_SHIFT) + +/* + * FORCE_LINK_GOOD (RW) + * + * Force Link Good: + * 1 = Force link good according to the selected speed. + * 0 = Normal operation + */ +#define DP83867_PHYCR_FORCE_LINK_GOOD_MASK (0x400U) +#define DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT (10U) +#define DP83867_PHYCR_FORCE_LINK_GOOD_SET(x) (((uint16_t)(x) << DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) +#define DP83867_PHYCR_FORCE_LINK_GOOD_GET(x) (((uint16_t)(x) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) >> DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) + +/* + * POWER_SAVE_MODE (RW) + * + * Power-Saving Modes: + * 11 = Passive Sleep mode: Power down all digital and analog + * blocks. + * 10 =Active Sleep mode: Power down all digital and analog blocks. + * Automatic power-up is performed when link partner is detected. Link + * pulses are transmitted approximately once per 1.4 Sec in this mode + * to wake up any potential link partner. + * 01 = IEEE mode: power down all digital and analog blocks. + * Note: If DISABLE_CLK_125 (bit [4]of this register) is set to zero, the + * PLL is also powered down. + * 00 = Normal mode + */ +#define DP83867_PHYCR_POWER_SAVE_MODE_MASK (0x300U) +#define DP83867_PHYCR_POWER_SAVE_MODE_SHIFT (8U) +#define DP83867_PHYCR_POWER_SAVE_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) +#define DP83867_PHYCR_POWER_SAVE_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) >> DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) + +/* + * DEEP_POWER_DOWN_EN (RW) + * + * Deep power-down mode enable + * 1 = When power down is initiated through assertion of the external + * power-down pin or through the POWER_DOWN bit in the BMCR, + * the device enters a deep power-down mode. + * 0 = Normal operation. + */ +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK (0x80U) +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT (7U) +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) >> DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) + +/* + * MDI_CROSSOVER (RW) + * + * MDI Crosssover Mode: + * 1x = Enable automatic crossover + * 01 = Manual MDI-X configuration + * 00 = Manual MDI configuration + */ +#define DP83867_PHYCR_MDI_CROSSOVER_MASK (0x60U) +#define DP83867_PHYCR_MDI_CROSSOVER_SHIFT (5U) +#define DP83867_PHYCR_MDI_CROSSOVER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_MDI_CROSSOVER_SHIFT) & DP83867_PHYCR_MDI_CROSSOVER_MASK) +#define DP83867_PHYCR_MDI_CROSSOVER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_MDI_CROSSOVER_MASK) >> DP83867_PHYCR_MDI_CROSSOVER_SHIFT) + +/* + * DISABLE_CLK_125 (RW) + * + * Disable 125MHz Clock: + * This bit may be used in conjunction with POWER_SAVE_MODE + * (bits 9:8 of this register). + * 1 = Disable CLK125. + * 0 = Enable CLK125. + */ +#define DP83867_PHYCR_DISABLE_CLK_125_MASK (0x10U) +#define DP83867_PHYCR_DISABLE_CLK_125_SHIFT (4U) +#define DP83867_PHYCR_DISABLE_CLK_125_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_CLK_125_SHIFT) & DP83867_PHYCR_DISABLE_CLK_125_MASK) +#define DP83867_PHYCR_DISABLE_CLK_125_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_CLK_125_MASK) >> DP83867_PHYCR_DISABLE_CLK_125_SHIFT) + +/* + * STANDBY_MODE (RW) + * + * Standby Mode: + * 1 = Enable standby mode. Digital and analog circuitry are powered + * up, but no link can be established. + * 0 = Normal operation. + */ +#define DP83867_PHYCR_STANDBY_MODE_MASK (0x4U) +#define DP83867_PHYCR_STANDBY_MODE_SHIFT (2U) +#define DP83867_PHYCR_STANDBY_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_STANDBY_MODE_SHIFT) & DP83867_PHYCR_STANDBY_MODE_MASK) +#define DP83867_PHYCR_STANDBY_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_STANDBY_MODE_MASK) >> DP83867_PHYCR_STANDBY_MODE_SHIFT) + +/* + * LINE_DRIVER_INV_EN (RW) + * + * Line Driver Inversion Enable: + * 1 = Invert Line Driver Transmission. + * 0 = Normal operation. + */ +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK (0x2U) +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT (1U) +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) >> DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) + +/* + * DISABLE_JABBER (RW) + * + * Disable Jabber + * 1 = Disable Jabber function. + * 0 = Enable Jabber function. + */ +#define DP83867_PHYCR_DISABLE_JABBER_MASK (0x1U) +#define DP83867_PHYCR_DISABLE_JABBER_SHIFT (0U) +#define DP83867_PHYCR_DISABLE_JABBER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_JABBER_SHIFT) & DP83867_PHYCR_DISABLE_JABBER_MASK) +#define DP83867_PHYCR_DISABLE_JABBER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_JABBER_MASK) >> DP83867_PHYCR_DISABLE_JABBER_SHIFT) + +/* Bitfield definition for register: PHYSTS */ +/* + * SPEED_SELECTION (RO) + * + * Speed Select Status: + * These two bits indicate the speed of operation as determined by + * Auto-Negotiation or as set by manual configuration. + * 11 = Reserved + * 10 = 1000 Mbps + * 01 = 100 Mbps + * 00 = 10 Mbps + */ +#define DP83867_PHYSTS_SPEED_SELECTION_MASK (0xC000U) +#define DP83867_PHYSTS_SPEED_SELECTION_SHIFT (14U) +#define DP83867_PHYSTS_SPEED_SELECTION_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_SELECTION_MASK) >> DP83867_PHYSTS_SPEED_SELECTION_SHIFT) + +/* + * DUPLEX_MODE (RO) + * + * Duplex Mode Status: + * 1 = Full Duplex + * 0 = Half Duplex. + */ +#define DP83867_PHYSTS_DUPLEX_MODE_MASK (0x2000U) +#define DP83867_PHYSTS_DUPLEX_MODE_SHIFT (13U) +#define DP83867_PHYSTS_DUPLEX_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_DUPLEX_MODE_MASK) >> DP83867_PHYSTS_DUPLEX_MODE_SHIFT) + +/* + * PAGE_RECEIVED ( RO, LH, COR) + * + * Page Received: + * This bit is latched high and will be cleared upon a read. + * 1 = Page received. + * 0 = No page received. + */ +#define DP83867_PHYSTS_PAGE_RECEIVED_MASK (0x1000U) +#define DP83867_PHYSTS_PAGE_RECEIVED_SHIFT (12U) +#define DP83867_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_PAGE_RECEIVED_MASK) >> DP83867_PHYSTS_PAGE_RECEIVED_SHIFT) + +/* + * SPEED_DUPLEX_RESOLVED (RO) + * + * Speed Duplex Resolution Status: + * 1 = Auto-Negotiation has completed or is disabled. + * 0 = Auto-Negotiation is enabled and has not completed. + */ +#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK (0x800U) +#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT (11U) +#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK) >> DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status: + * 1 = Link is up. + * 0 = Link is down. + */ +#define DP83867_PHYSTS_LINK_STATUS_MASK (0x400U) +#define DP83867_PHYSTS_LINK_STATUS_SHIFT (10U) +#define DP83867_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_LINK_STATUS_MASK) >> DP83867_PHYSTS_LINK_STATUS_SHIFT) + +/* + * MDI_X_MODE_CD (RO) + * + * MDI/MDIX Resolution Status for C and D Line Driver Pairs: + * 1 = Resolved as MDIX + * 0 = Resolved as MDI. + */ +#define DP83867_PHYSTS_MDI_X_MODE_CD_MASK (0x200U) +#define DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT (9U) +#define DP83867_PHYSTS_MDI_X_MODE_CD_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_CD_MASK) >> DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT) + +/* + * MDI_X_MODE_AB (RO) + * + * MDI/MDIX Resolution Status for A and B Line Driver Pairs: + * 1 = Resolved as MDIX + * 0 = Resolved as MDI. + */ +#define DP83867_PHYSTS_MDI_X_MODE_AB_MASK (0x100U) +#define DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT (8U) +#define DP83867_PHYSTS_MDI_X_MODE_AB_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_AB_MASK) >> DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT) + +/* + * SPEED_OPT_STATUS (RO) + * + * Speed Optimization Status: + * 1 = Auto-Negotiation is currently being performed with Speed + * Optimization masking 1000BaseT abilities (Valid only during Auto- + * Negotiation). + * 0 = Auto-Negotiation is currently being performed without Speed + * Optimization. + */ +#define DP83867_PHYSTS_SPEED_OPT_STATUS_MASK (0x80U) +#define DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT (7U) +#define DP83867_PHYSTS_SPEED_OPT_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_OPT_STATUS_MASK) >> DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT) + +/* + * SLEEP_MODE (RO) + * + * Sleep Mode Status: + * 1 = Device currently in sleep mode. + * 0 = Device currently in active mode. + */ +#define DP83867_PHYSTS_SLEEP_MODE_MASK (0x40U) +#define DP83867_PHYSTS_SLEEP_MODE_SHIFT (6U) +#define DP83867_PHYSTS_SLEEP_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SLEEP_MODE_MASK) >> DP83867_PHYSTS_SLEEP_MODE_SHIFT) + +/* + * WIRE_CROSS (RO) + * + * Crossed Wire Indication: + * Indicates channel polarity in 1000BASE-T linked status. Bits [5:2] + * correspond to channels [D,C,B,A], respectively. + * 1 = Channel polarity is reversed. + * 0 = Channel polarity is normal. + */ +#define DP83867_PHYSTS_WIRE_CROSS_MASK (0x3CU) +#define DP83867_PHYSTS_WIRE_CROSS_SHIFT (2U) +#define DP83867_PHYSTS_WIRE_CROSS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_WIRE_CROSS_MASK) >> DP83867_PHYSTS_WIRE_CROSS_SHIFT) + +/* + * POLARITY_STATUS (RO) + * + * 10BASE-Te Polarity Status: + * 1 = Correct Polarity detected. + * 0 = Inverted Polarity detected. + */ +#define DP83867_PHYSTS_POLARITY_STATUS_MASK (0x2U) +#define DP83867_PHYSTS_POLARITY_STATUS_SHIFT (1U) +#define DP83867_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_POLARITY_STATUS_MASK) >> DP83867_PHYSTS_POLARITY_STATUS_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * Jabber Detect: This bit only has meaning in 10 Mbps mode. + * This bit is a duplicate of the Jabber Detect bit in the BMSR register, + * except that it is not cleared upon a read of the PHYSTS register. + * 1 = Jabber condition detected. + * 0 = No Jabber. + */ +#define DP83867_PHYSTS_JABBER_DETECT_MASK (0x1U) +#define DP83867_PHYSTS_JABBER_DETECT_SHIFT (0U) +#define DP83867_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_JABBER_DETECT_MASK) >> DP83867_PHYSTS_JABBER_DETECT_SHIFT) + +/* Bitfield definition for register: MICR */ +/* + * AUTONEG_ERR_INT_EN (RW) + * + * Enable Auto-Negotiation Error Interrupt: + * 1 = Enable Auto-Negotiation Error interrupt. + * 0 = Disable Auto-Negotiation Error interrupt. + */ +#define DP83867_MICR_AUTONEG_ERR_INT_EN_MASK (0x8000U) +#define DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT (15U) +#define DP83867_MICR_AUTONEG_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) +#define DP83867_MICR_AUTONEG_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) >> DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) + +/* + * SPEED_CHNG_INT_EN (RW) + * + * Enable Speed Change Interrupt: + * 1 = Enable Speed Change interrupt. + * 0 = Disable Speed Change interrupt. + */ +#define DP83867_MICR_SPEED_CHNG_INT_EN_MASK (0x4000U) +#define DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT (14U) +#define DP83867_MICR_SPEED_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) +#define DP83867_MICR_SPEED_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) >> DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) + +/* + * DUPLEX_MODE_CHNG_INT_EN (RW) + * + * Enable Duplex Mode Change Interrupt: + * 1 = Enable Duplex Mode Change interrupt. + * 0 = Disable Duplex Mode Change interrupt. + */ +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK (0x2000U) +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT (13U) +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) + +/* + * PAGE_RECEIVED_INT_EN (RW) + * + * Enable Page Received Interrupt: + * 1 = Enable Page Received Interrupt. + * 0 = Disable Page Received Interrupt. + */ +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK (0x1000U) +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT (12U) +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) >> DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) + +/* + * AUTONEG_COMP_INT_EN (RW) + * + * Enable Auto-Negotiation Complete Interrupt: + * 1 = Enable Auto-Negotiation Complete Interrupt. + * 0 = Disable Auto-Negotiation Complete Interrupt. + */ +#define DP83867_MICR_AUTONEG_COMP_INT_EN_MASK (0x800U) +#define DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT (11U) +#define DP83867_MICR_AUTONEG_COMP_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) +#define DP83867_MICR_AUTONEG_COMP_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) >> DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) + +/* + * LINK_STATUS_CHNG_INT_EN (RW) + * + * Enable Link Status Change Interrupt: + * 1 = Enable Link Status Change interrupt. + * 0 = Disable Link Status Change interrupt. + */ +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK (0x400U) +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT (10U) +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) >> DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) + +/* + * FALSE_CARRIER_INT_EN (RW) + * + * Enable False Carrier Interrupt: + * 1 = Enable False Carrier interrupt. + * 0 = Disable False Carrier interrupt. + */ +#define DP83867_MICR_FALSE_CARRIER_INT_EN_MASK (0x100U) +#define DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT (8U) +#define DP83867_MICR_FALSE_CARRIER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) +#define DP83867_MICR_FALSE_CARRIER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) >> DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) + +/* + * MDI_CROSSOVER_CHNG_INT_EN (RW) + * + * Enable MDI Crossover Change Interrupt: + * 1 = Enable MDI Crossover Change interrupt. + * 0 = Disable MDI Crossover Change interrupt. + */ +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK (0x40U) +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT (6U) +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) >> DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) + +/* + * SPEED_OPT_EVENT_INT_EN (RW) + * + * Enable Speed Optimization Event Interrupt: + * 1 = Enable Speed Optimization Event Interrupt. + * 0 = Disable Speed Optimization Event Interrupt. + */ +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK (0x20U) +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT (5U) +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) >> DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) + +/* + * SLEEP_MODE_CHNG_INT_EN (RW) + * + * Enable Sleep Mode Change Interrupt: + * 1 = Enable Sleep Mode Change Interrupt. + * 0 = Disable Sleep Mode Change Interrupt. + */ +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK (0x10U) +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT (4U) +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) + +/* + * WOL_INT_EN (RW) + * + * Enable Wake-on-LAN Interrupt: + * 1 = Enable Wake-on-LAN Interrupt. + * 0 = Disable Wake-on-LAN Interrupt. + */ +#define DP83867_MICR_WOL_INT_EN_MASK (0x8U) +#define DP83867_MICR_WOL_INT_EN_SHIFT (3U) +#define DP83867_MICR_WOL_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_WOL_INT_EN_SHIFT) & DP83867_MICR_WOL_INT_EN_MASK) +#define DP83867_MICR_WOL_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_WOL_INT_EN_MASK) >> DP83867_MICR_WOL_INT_EN_SHIFT) + +/* + * XGMII_ERR_INT_EN (RW) + * + * Enable xGMII Error Interrupt: + * 1 = Enable xGMII Error Interrupt. + * 0 = Disable xGMII Error Interrupt. + */ +#define DP83867_MICR_XGMII_ERR_INT_EN_MASK (0x4U) +#define DP83867_MICR_XGMII_ERR_INT_EN_SHIFT (2U) +#define DP83867_MICR_XGMII_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) +#define DP83867_MICR_XGMII_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) >> DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) + +/* + * POLARITY_CHNG_INT_EN (RW) + * + * Enable Polarity Change Interrupt: + * 1 = Enable Polarity Change interrupt. + * 0 = Disable Polarity Change interrupt. + */ +#define DP83867_MICR_POLARITY_CHNG_INT_EN_MASK (0x2U) +#define DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT (1U) +#define DP83867_MICR_POLARITY_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) +#define DP83867_MICR_POLARITY_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) >> DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) + +/* + * JABBER_INT_EN (RW) + * + * Enable Jabber Interrupt: + * 1 = Enable Jabber interrupt. + * 0 = Disable Jabber interrupt. + */ +#define DP83867_MICR_JABBER_INT_EN_MASK (0x1U) +#define DP83867_MICR_JABBER_INT_EN_SHIFT (0U) +#define DP83867_MICR_JABBER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_JABBER_INT_EN_SHIFT) & DP83867_MICR_JABBER_INT_EN_MASK) +#define DP83867_MICR_JABBER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_JABBER_INT_EN_MASK) >> DP83867_MICR_JABBER_INT_EN_SHIFT) + +/* Bitfield definition for register: ISR */ +/* + * AUTONEG_ERR_INT (RO, LH, COR) + * + * Auto-Negotiation Error Interrupt: + * 1 = Auto-Negotiation Error interrupt is pending and is cleared by the + * current read. + * 0 = No Auto-Negotiation Error interrupt. + */ +#define DP83867_ISR_AUTONEG_ERR_INT_MASK (0x8000U) +#define DP83867_ISR_AUTONEG_ERR_INT_SHIFT (15U) +#define DP83867_ISR_AUTONEG_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_ERR_INT_MASK) >> DP83867_ISR_AUTONEG_ERR_INT_SHIFT) + +/* + * SPEED_CHNG_INT (RO, LH, COR) + * + * Speed Change Interrupt: + * 1 = Speed Change interrupt is pending and is cleared by the current + * read. + * 0 = No Speed Change interrupt. + */ +#define DP83867_ISR_SPEED_CHNG_INT_MASK (0x4000U) +#define DP83867_ISR_SPEED_CHNG_INT_SHIFT (14U) +#define DP83867_ISR_SPEED_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_CHNG_INT_MASK) >> DP83867_ISR_SPEED_CHNG_INT_SHIFT) + +/* + * DUPLEX_MODE_CHNG_INT (RO, LH, COR) + * + * Duplex Mode Change Interrupt: + * 1 = Duplex Mode Change interrupt is pending and is cleared by the + * current read. + * 0 = No Duplex Mode Change interrupt. + */ +#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK (0x2000U) +#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT (13U) +#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK) >> DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT) + +/* + * PAGE_RECEIVED_INT (RO, LH, COR) + * + * Page Received Interrupt: + * 1 = Page Received Interrupt is pending and is cleared by the + * current read. + * 0 = No Page Received Interrupt is pending. + */ +#define DP83867_ISR_PAGE_RECEIVED_INT_MASK (0x1000U) +#define DP83867_ISR_PAGE_RECEIVED_INT_SHIFT (12U) +#define DP83867_ISR_PAGE_RECEIVED_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_PAGE_RECEIVED_INT_MASK) >> DP83867_ISR_PAGE_RECEIVED_INT_SHIFT) + +/* + * AUTONEG_COMP_INT (RO, LH, COR) + * + * Auto-Negotiation Complete Interrupt: + * 1 = Auto-Negotiation Complete Interrupt is pending and is cleared + * by the current read. + * 0 = No Auto-Negotiation Complete Interrupt is pending. + */ +#define DP83867_ISR_AUTONEG_COMP_INT_MASK (0x800U) +#define DP83867_ISR_AUTONEG_COMP_INT_SHIFT (11U) +#define DP83867_ISR_AUTONEG_COMP_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_COMP_INT_MASK) >> DP83867_ISR_AUTONEG_COMP_INT_SHIFT) + +/* + * LINK_STATUS_CHNG_INT (RO, LH, COR) + * + * Link Status Change Interrupt: + * 1 = Link Status Change interrupt is pending and is cleared by the + * current read. + * 0 = No Link Status Change interrupt is pending. + */ +#define DP83867_ISR_LINK_STATUS_CHNG_INT_MASK (0x400U) +#define DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT (10U) +#define DP83867_ISR_LINK_STATUS_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_LINK_STATUS_CHNG_INT_MASK) >> DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT) + +/* + * FALSE_CARRIER_INT ( RO, LH, COR) + * + * False Carrier Interrupt: + * 1 = False Carrier interrupt is pending and is cleared by the current + * read. + * 0 = No False Carrier interrupt is pending. + */ +#define DP83867_ISR_FALSE_CARRIER_INT_MASK (0x100U) +#define DP83867_ISR_FALSE_CARRIER_INT_SHIFT (8U) +#define DP83867_ISR_FALSE_CARRIER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_FALSE_CARRIER_INT_MASK) >> DP83867_ISR_FALSE_CARRIER_INT_SHIFT) + +/* + * MDI_CROSSOVER_CHNG_INT (RO, LH, COR) + * + * MDI Crossover Change Interrupt: + * 1 = MDI Crossover Change interrupt is pending and is cleared by + * the current read. + * 0 = No MDI Crossover Change interrupt is pending. + */ +#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK (0x40U) +#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT (6U) +#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK) >> DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT) + +/* + * SPEED_OPT_EVENT_INT (RO, LH, COR) + * + * Speed Optimization Event Interrupt: + * 1 = Speed Optimization Event Interrupt is pending and is cleared by + * the current read. + * 0 = No Speed Optimization Event Interrupt is pending. + */ +#define DP83867_ISR_SPEED_OPT_EVENT_INT_MASK (0x20U) +#define DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT (5U) +#define DP83867_ISR_SPEED_OPT_EVENT_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_OPT_EVENT_INT_MASK) >> DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT) + +/* + * SLEEP_MODE_CHNG_INT (RO, LH, COR) + * + * Sleep Mode Change Interrupt: + * 1 = Sleep Mode Change Interrupt is pending and is cleared by the + * current read. + * 0 = No Sleep Mode Change Interrupt is pending. + */ +#define DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK (0x10U) +#define DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT (4U) +#define DP83867_ISR_SLEEP_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK) >> DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT) + +/* + * WOL_INT (RO, LH, COR) + * + * Wake-on-LAN Interrupt: + * 1 = Wake-on-LAN Interrupt is pending. + * 0 = No Wake-on-LAN Interrupt is pending. + */ +#define DP83867_ISR_WOL_INT_MASK (0x8U) +#define DP83867_ISR_WOL_INT_SHIFT (3U) +#define DP83867_ISR_WOL_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_WOL_INT_MASK) >> DP83867_ISR_WOL_INT_SHIFT) + +/* + * XGMII_ERR_INT (RO, LH, COR) + * + * xGMII Error Interrupt: + * 1 = xGMII Error Interrupt is pending and is cleared by the current + * read. + * 0 = No xGMII Error Interrupt is pending. + */ +#define DP83867_ISR_XGMII_ERR_INT_MASK (0x4U) +#define DP83867_ISR_XGMII_ERR_INT_SHIFT (2U) +#define DP83867_ISR_XGMII_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_XGMII_ERR_INT_MASK) >> DP83867_ISR_XGMII_ERR_INT_SHIFT) + +/* + * POLARITY_CHNG_INT (RO, LH, COR) + * + * Polarity Change Interrupt: + * 1 = Polarity Change interrupt is pending and is cleared by the + * current read. + * 0 = No Polarity Change interrupt is pending. + */ +#define DP83867_ISR_POLARITY_CHNG_INT_MASK (0x2U) +#define DP83867_ISR_POLARITY_CHNG_INT_SHIFT (1U) +#define DP83867_ISR_POLARITY_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_POLARITY_CHNG_INT_MASK) >> DP83867_ISR_POLARITY_CHNG_INT_SHIFT) + +/* + * JABBER_INT (RO, LH, COR) + * + * Jabber Interrupt: + * 1 = Jabber interrupt is pending and is cleared by the current read. + * 0 = No Jabber interrupt is pending. + */ +#define DP83867_ISR_JABBER_INT_MASK (0x1U) +#define DP83867_ISR_JABBER_INT_SHIFT (0U) +#define DP83867_ISR_JABBER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_JABBER_INT_MASK) >> DP83867_ISR_JABBER_INT_SHIFT) + +/* Bitfield definition for register: CRG2 */ +/* + * INTERRUPT_POLARITY (RW) + * + * Configure Interrupt Polarity: + * 1 = Interrupt pin is active low. + * 0 = Interrupt pin is active high. + */ +#define DP83867_CRG2_INTERRUPT_POLARITY_MASK (0x2000U) +#define DP83867_CRG2_INTERRUPT_POLARITY_SHIFT (13U) +#define DP83867_CRG2_INTERRUPT_POLARITY_SET(x) (((uint16_t)(x) << DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) +#define DP83867_CRG2_INTERRUPT_POLARITY_GET(x) (((uint16_t)(x) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) >> DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) + +/* + * SPEED_OPT_ATTEMPT_CNT (RO) + * + * Speed Optimization Attempt Count: + * Selects the number of 1000BASE-T link establishment attempt + * failures prior to performing Speed Optimization. + * 11 = 8 + * 10 = 4 + * 01 = 2 + * 00 = 1 + */ +#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK (0xC00U) +#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT (10U) +#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK) >> DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT) + +/* + * SPEED_OPT_EN (RW) + * + * Speed Optimization Enable: + * 1 = Enable Speed Optimization. + * 0 = Disable Speed Optimization. + */ +#define DP83867_CRG2_SPEED_OPT_EN_MASK (0x200U) +#define DP83867_CRG2_SPEED_OPT_EN_SHIFT (9U) +#define DP83867_CRG2_SPEED_OPT_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_EN_MASK) +#define DP83867_CRG2_SPEED_OPT_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_EN_MASK) >> DP83867_CRG2_SPEED_OPT_EN_SHIFT) + +/* + * SPEED_OPT_ENHANCED_EN (RW) + * + * Speed Optimization Enhanced Mode Enable: + * In enhanced mode, speed is optimized if energy is not detected in + * channels C and D. + * 1 = Enable Speed Optimization enhanced mode. + * 0 = Disable Speed Optimization enhanced mode. + */ +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK (0x100U) +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT (8U) +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) >> DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) + +/* + * SGMII_AUTONEG_EN (RW) + * + * SGMII Auto-Negotiation Enable: + * 1 = Enable SGMII Auto-Negotaition. + * 0 = Disable SGMII Auto-Negotaition. + */ +#define DP83867_CRG2_SGMII_AUTONEG_EN_MASK (0x80U) +#define DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT (7U) +#define DP83867_CRG2_SGMII_AUTONEG_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) +#define DP83867_CRG2_SGMII_AUTONEG_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) >> DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) + +/* + * SPEED_OPT_10M_EN (RW) + * + * Enable Speed Optimization to 10BASE-Te: + * 1 = Enable speed optimization to 10BASE-Te if link establishment + * fails in 1000BASE-T and 100BASE-TX . + * 0 = Disable speed optimization to 10BASE-Te. + */ +#define DP83867_CRG2_SPEED_OPT_10M_EN_MASK (0x40U) +#define DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT (6U) +#define DP83867_CRG2_SPEED_OPT_10M_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) +#define DP83867_CRG2_SPEED_OPT_10M_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) >> DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) + +/* Bitfield definition for register: RECR */ +/* + * RXERCNT_15_0 (RO, WSC) + * + * RX_ER Counter: + * Receive error counter. This register saturates at the maximum value + * of 0xFFFF. It is cleared by dummy write to this register. + */ +#define DP83867_RECR_RXERCNT_15_0_MASK (0xFFFFU) +#define DP83867_RECR_RXERCNT_15_0_SHIFT (0U) +#define DP83867_RECR_RXERCNT_15_0_SET(x) (((uint16_t)(x) << DP83867_RECR_RXERCNT_15_0_SHIFT) & DP83867_RECR_RXERCNT_15_0_MASK) +#define DP83867_RECR_RXERCNT_15_0_GET(x) (((uint16_t)(x) & DP83867_RECR_RXERCNT_15_0_MASK) >> DP83867_RECR_RXERCNT_15_0_SHIFT) + +/* Bitfield definition for register: STS2 */ +/* + * PRBS_LOCK (RO) + * + * PRBS Lock Status: + * 1 = PRBS checker is locked to the received byte stream. + * 0 = PRBS checker is not locked. + */ +#define DP83867_STS2_PRBS_LOCK_MASK (0x800U) +#define DP83867_STS2_PRBS_LOCK_SHIFT (11U) +#define DP83867_STS2_PRBS_LOCK_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_MASK) >> DP83867_STS2_PRBS_LOCK_SHIFT) + +/* + * PRBS_LOCK_LOST (RO, LH, COR) + * + * PRBS Lock Lost: + * 1 = PRBS checker has lost lock. + * 0 = PRBS checker has not lost lock. + */ +#define DP83867_STS2_PRBS_LOCK_LOST_MASK (0x400U) +#define DP83867_STS2_PRBS_LOCK_LOST_SHIFT (10U) +#define DP83867_STS2_PRBS_LOCK_LOST_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_LOST_MASK) >> DP83867_STS2_PRBS_LOCK_LOST_SHIFT) + +/* + * PKT_GEN_BUSY (RO) + * + * Packet Generator Busy: + * 1 = Packet generation is in process. + * 0 = Packet generation is not in process. + */ +#define DP83867_STS2_PKT_GEN_BUSY_MASK (0x200U) +#define DP83867_STS2_PKT_GEN_BUSY_SHIFT (9U) +#define DP83867_STS2_PKT_GEN_BUSY_GET(x) (((uint16_t)(x) & DP83867_STS2_PKT_GEN_BUSY_MASK) >> DP83867_STS2_PKT_GEN_BUSY_SHIFT) + +/* + * SCR_MODE_MASTER_1G (RO) + * + * Gigabit Master Scramble Mode: + * 1 = 1G PCS (master) is in legacy encoding mode. + * 0 = 1G PCS (master) is in normal encoding mode.. + */ +#define DP83867_STS2_SCR_MODE_MASTER_1G_MASK (0x100U) +#define DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT (8U) +#define DP83867_STS2_SCR_MODE_MASTER_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_MASTER_1G_MASK) >> DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT) + +/* + * SCR_MODE_SLAVE_1G (RO) + * + * Gigabit Slave Scramble Mode: + * 1 = 1G PCS (slave) is in legacy encoding mode. + * 0 = 1G PCS (slave) is in normal encoding mode.. + */ +#define DP83867_STS2_SCR_MODE_SLAVE_1G_MASK (0x80U) +#define DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT (7U) +#define DP83867_STS2_SCR_MODE_SLAVE_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_SLAVE_1G_MASK) >> DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT) + +/* + * CORE_PWR_MODE (RO) + * + * Core Power Mode: + * 1 = Core is in normal power mode. + * 0 = Core is power-down mode or in sleep mode. + */ +#define DP83867_STS2_CORE_PWR_MODE_MASK (0x40U) +#define DP83867_STS2_CORE_PWR_MODE_SHIFT (6U) +#define DP83867_STS2_CORE_PWR_MODE_GET(x) (((uint16_t)(x) & DP83867_STS2_CORE_PWR_MODE_MASK) >> DP83867_STS2_CORE_PWR_MODE_SHIFT) + +/* Bitfield definition for register: LEDCR1 */ +/* + * LED_GPIO_SEL (RW) + * + * Source of the GPIO LED_3: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_GPIO_SEL_MASK (0xF000U) +#define DP83867_LEDCR1_LED_GPIO_SEL_SHIFT (12U) +#define DP83867_LEDCR1_LED_GPIO_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) +#define DP83867_LEDCR1_LED_GPIO_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) >> DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) + +/* + * LED_2_SEL (RW) + * + * Source of LED_2: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_2_SEL_MASK (0xF00U) +#define DP83867_LEDCR1_LED_2_SEL_SHIFT (8U) +#define DP83867_LEDCR1_LED_2_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_2_SEL_SHIFT) & DP83867_LEDCR1_LED_2_SEL_MASK) +#define DP83867_LEDCR1_LED_2_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_2_SEL_MASK) >> DP83867_LEDCR1_LED_2_SEL_SHIFT) + +/* + * LED_1_SEL (RW) + * + * Source of LED_1: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_1_SEL_MASK (0xF0U) +#define DP83867_LEDCR1_LED_1_SEL_SHIFT (4U) +#define DP83867_LEDCR1_LED_1_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_1_SEL_SHIFT) & DP83867_LEDCR1_LED_1_SEL_MASK) +#define DP83867_LEDCR1_LED_1_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_1_SEL_MASK) >> DP83867_LEDCR1_LED_1_SEL_SHIFT) + +/* + * LED_0_SEL (RW) + * + * Source of LED_0: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_0_SEL_MASK (0xFU) +#define DP83867_LEDCR1_LED_0_SEL_SHIFT (0U) +#define DP83867_LEDCR1_LED_0_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_0_SEL_SHIFT) & DP83867_LEDCR1_LED_0_SEL_MASK) +#define DP83867_LEDCR1_LED_0_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_0_SEL_MASK) >> DP83867_LEDCR1_LED_0_SEL_SHIFT) + +/* Bitfield definition for register: LEDCR2 */ +/* + * LED_GPIO_POLARITY (RW) + * + * GPIO LED Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_GPIO_POLARITY_MASK (0x4000U) +#define DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT (14U) +#define DP83867_LEDCR2_LED_GPIO_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) +#define DP83867_LEDCR2_LED_GPIO_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) >> DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) + +/* + * LED_GPIO_DRV_VAL (RW) + * + * GPIO LED Drive Value: + * Value to force on GPIO LED + * This bit is only valid if enabled through LED_GPIO_DRV_EN. + */ +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK (0x2000U) +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT (13U) +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) + +/* + * LED_GPIO_DRV_EN (RW) + * + * GPIO LED Drive Enable: + * 1 = Force the value of the LED_GPIO_DRV_VAL bit onto the GPIO + * LED. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK (0x1000U) +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT (12U) +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) + +/* + * LED_2_POLARITY (RW) + * + * LED_2 Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_2_POLARITY_MASK (0x400U) +#define DP83867_LEDCR2_LED_2_POLARITY_SHIFT (10U) +#define DP83867_LEDCR2_LED_2_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_POLARITY_SHIFT) & DP83867_LEDCR2_LED_2_POLARITY_MASK) +#define DP83867_LEDCR2_LED_2_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_POLARITY_MASK) >> DP83867_LEDCR2_LED_2_POLARITY_SHIFT) + +/* + * LED_2_DRV_VAL (RW) + * + * LED_2 Drive Value: + * Value to force on LED_2 + * This bit is only valid if enabled through LED_2_DRV_EN. + */ +#define DP83867_LEDCR2_LED_2_DRV_VAL_MASK (0x200U) +#define DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT (9U) +#define DP83867_LEDCR2_LED_2_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_2_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) + +/* + * LED_2_DRV_EN (RW) + * + * LED_2 Drive Enable: + * 1 = Force the value of the LED_2_DRV_VAL bit onto LED_2. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_2_DRV_EN_MASK (0x100U) +#define DP83867_LEDCR2_LED_2_DRV_EN_SHIFT (8U) +#define DP83867_LEDCR2_LED_2_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_2_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) >> DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) + +/* + * LED_1_POLARITY (RW) + * + * LED_1 Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_1_POLARITY_MASK (0x40U) +#define DP83867_LEDCR2_LED_1_POLARITY_SHIFT (6U) +#define DP83867_LEDCR2_LED_1_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_POLARITY_SHIFT) & DP83867_LEDCR2_LED_1_POLARITY_MASK) +#define DP83867_LEDCR2_LED_1_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_POLARITY_MASK) >> DP83867_LEDCR2_LED_1_POLARITY_SHIFT) + +/* + * LED_1_DRV_VAL (RW) + * + * LED_1 Drive Value: + * Value to force on LED_1 + * This bit is only valid if enabled through LED_1_DRV_EN. + */ +#define DP83867_LEDCR2_LED_1_DRV_VAL_MASK (0x20U) +#define DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT (5U) +#define DP83867_LEDCR2_LED_1_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_1_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) + +/* + * LED_1_DRV_EN (RW) + * + * LED_1 Drive Enable: + * 1 = Force the value of the LED_1_DRV_VAL bit onto LED_1. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_1_DRV_EN_MASK (0x10U) +#define DP83867_LEDCR2_LED_1_DRV_EN_SHIFT (4U) +#define DP83867_LEDCR2_LED_1_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_1_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) >> DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) + +/* + * LED_0_POLARITY (RW) + * + * LED_0 Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_0_POLARITY_MASK (0x4U) +#define DP83867_LEDCR2_LED_0_POLARITY_SHIFT (2U) +#define DP83867_LEDCR2_LED_0_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_POLARITY_SHIFT) & DP83867_LEDCR2_LED_0_POLARITY_MASK) +#define DP83867_LEDCR2_LED_0_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_POLARITY_MASK) >> DP83867_LEDCR2_LED_0_POLARITY_SHIFT) + +/* + * LED_0_DRV_VAL (RW) + * + * LED_0 Drive Value: + * Value to force on LED_0 + * This bit is only valid if enabled through LED_0_DRV_EN. + */ +#define DP83867_LEDCR2_LED_0_DRV_VAL_MASK (0x2U) +#define DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT (1U) +#define DP83867_LEDCR2_LED_0_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_0_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) + +/* + * LED_0_DRV_EN (RW) + * + * LED_0 Drive Enable: + * 1 = Force the value of the LED_0_DRV_VAL bit onto LED_0. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_0_DRV_EN_MASK (0x1U) +#define DP83867_LEDCR2_LED_0_DRV_EN_SHIFT (0U) +#define DP83867_LEDCR2_LED_0_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_0_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) >> DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) + +/* Bitfield definition for register: LEDCR3 */ +/* + * LEDS_BYPASS_STRETCHING (RW) + * + * Bypass LED Stretching: + * 1 = Bypass LED Stretching + * 0 = Normal operation + */ +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK (0x4U) +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT (2U) +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) >> DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) + +/* + * LEDS_BLINK_RATE (RW) + * + * LED Blink Rate: + * 11: 2 Hz (500 ms) + * 10: 5 Hz (200 ms) + * 01: 10 Hz (100 ms) + * 00 = 20 Hz (50 ms) + */ +#define DP83867_LEDCR3_LEDS_BLINK_RATE_MASK (0x3U) +#define DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT (0U) +#define DP83867_LEDCR3_LEDS_BLINK_RATE_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) +#define DP83867_LEDCR3_LEDS_BLINK_RATE_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) >> DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) + +/* Bitfield definition for register: CFG3 */ +/* + * FAST_LINK_UP_IN_PARALLEL_DETECT (RW) + * + * Fast Link-Up in Parallel Detect Mode: + * 1 = Enable Fast Link-Up time During Parallel Detection + * 0 = Normal Parallel Detection link establishment + * In Fast Auto MDI-X this bit is automatically set. + */ +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK (0x8000U) +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT (15U) +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) >> DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) + +/* + * FAST_AN_ENABLE (RW) + * + * Fast Auto-Negotiation Enable: + * 1 = Enable Fast Auto-Negotiation mode – The PHY auto- + * negotiates using Timer setting according to Fast AN Sel bits + * 0 = Disable Fast Auto-Negotiation mode – The PHY auto- + * negotiates using normal Timer setting + * Adjusting these bits reduces the time it takes to Auto-negotiate + * between two PHYs. Note: When using this option care must be + * taken to maintain proper operation of the system. While shortening + * these timer intervals may not cause problems in normal operation, + * there are certain situations where this may lead to problems. + */ +#define DP83867_CFG3_FAST_AN_ENABLE_MASK (0x4000U) +#define DP83867_CFG3_FAST_AN_ENABLE_SHIFT (14U) +#define DP83867_CFG3_FAST_AN_ENABLE_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_ENABLE_SHIFT) & DP83867_CFG3_FAST_AN_ENABLE_MASK) +#define DP83867_CFG3_FAST_AN_ENABLE_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_ENABLE_MASK) >> DP83867_CFG3_FAST_AN_ENABLE_SHIFT) + +/* + * FAST_AN_SEL (RW) + * + * Fast Auto-Negotiation Select bits: + * Fast AN Select Break Link Timer(ms) Link Fail Inhibit TImer(ms) Auto-Neg Wait Timer(ms) + * <00> 80 50 35 + * <01> 120 75 50 + * <10> 240 150 100 + * <11> NA NA NA + * Adjusting these bits reduces the time it takes to auto-negotiate + * between two PHYs. In Fast AN mode, both PHYs should be + * configured to the same configuration. These 2 bits define the + * duration for each state of the Auto-Negotiation process according + * to the table above. The new duration time must be enabled by + * setting Fast AN En - bit 4 of this register. Note: Using this mode in + * cases where both link partners are not configured to the same + * Fast Auto-Negotiation configuration might produce scenarios with + * unexpected behavior. + */ +#define DP83867_CFG3_FAST_AN_SEL_MASK (0x3000U) +#define DP83867_CFG3_FAST_AN_SEL_SHIFT (12U) +#define DP83867_CFG3_FAST_AN_SEL_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_SEL_SHIFT) & DP83867_CFG3_FAST_AN_SEL_MASK) +#define DP83867_CFG3_FAST_AN_SEL_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_SEL_MASK) >> DP83867_CFG3_FAST_AN_SEL_SHIFT) + +/* + * EXTENDED_FD_ABILITY (RW) + * + * Extended Full-Duplex Ability: + * 1 = Force Full-Duplex while working with link partner in forced + * 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B- + * TX and the link partner is operated in Force 100B-TX, the link is + * always Full Duplex + * 0 = Disable Extended Full Duplex Ability. Decision to work in Full + * Duplex or Half Duplex mode follows IEEE specification. + */ +#define DP83867_CFG3_EXTENDED_FD_ABILITY_MASK (0x800U) +#define DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT (11U) +#define DP83867_CFG3_EXTENDED_FD_ABILITY_SET(x) (((uint16_t)(x) << DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) +#define DP83867_CFG3_EXTENDED_FD_ABILITY_GET(x) (((uint16_t)(x) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) >> DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) + +/* + * ROBUST_AUTO_MDIX (RW) + * + * Robust Auto-MDIX: + * 1 =Enable Robust Auto MDI/MDIX resolution + * 0 = Normal Auto MDI/MDIX mode + * If link partners are configured to operational modes that are not + * supported by normal Auto MDI/MDIX mode (like Auto-Neg versus + * Force 100Base-TX or Force 100Base-TX versus Force 100Base- + * TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX + * resolution and prevents deadlock. + */ +#define DP83867_CFG3_ROBUST_AUTO_MDIX_MASK (0x200U) +#define DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT (9U) +#define DP83867_CFG3_ROBUST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) +#define DP83867_CFG3_ROBUST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) >> DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) + +/* + * FAST_AUTO_MDIX (RW) + * + * Fast Auto MDI/MDIX: + * 1 = Enable Fast Auto MDI/MDIX mode + * 0 = Normal Auto MDI/MDIX mode + * If both link partners are configured to work in Force 100Base-TX + * mode (Auto-Negotiation is disabled), this mode enables Automatic + * MDI/MDIX resolution in a short time. + */ +#define DP83867_CFG3_FAST_AUTO_MDIX_MASK (0x100U) +#define DP83867_CFG3_FAST_AUTO_MDIX_SHIFT (8U) +#define DP83867_CFG3_FAST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) +#define DP83867_CFG3_FAST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) >> DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) + +/* + * INT_OE (RW) + * + * Interrupt Output Enable: + * 1 = INTN/PWDNN Pad is an Interrupt Output. + * 0 = INTN/PWDNN Pad in a Power-Down Input. + */ +#define DP83867_CFG3_INT_OE_MASK (0x80U) +#define DP83867_CFG3_INT_OE_SHIFT (7U) +#define DP83867_CFG3_INT_OE_SET(x) (((uint16_t)(x) << DP83867_CFG3_INT_OE_SHIFT) & DP83867_CFG3_INT_OE_MASK) +#define DP83867_CFG3_INT_OE_GET(x) (((uint16_t)(x) & DP83867_CFG3_INT_OE_MASK) >> DP83867_CFG3_INT_OE_SHIFT) + +/* + * FORCE_INTERRUPT (RW) + * + * Force Interrupt: + * 1 = Assert interrupt pin. + * 0 = Normal interrupt mode. + */ +#define DP83867_CFG3_FORCE_INTERRUPT_MASK (0x40U) +#define DP83867_CFG3_FORCE_INTERRUPT_SHIFT (6U) +#define DP83867_CFG3_FORCE_INTERRUPT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FORCE_INTERRUPT_SHIFT) & DP83867_CFG3_FORCE_INTERRUPT_MASK) +#define DP83867_CFG3_FORCE_INTERRUPT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FORCE_INTERRUPT_MASK) >> DP83867_CFG3_FORCE_INTERRUPT_SHIFT) + +/* + * TDR_FAIL (RO) + * + * TDR Failure: + * 1 = TDR failed. + * 0 = Normal TDR operation. + */ +#define DP83867_CFG3_TDR_FAIL_MASK (0x4U) +#define DP83867_CFG3_TDR_FAIL_SHIFT (2U) +#define DP83867_CFG3_TDR_FAIL_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_FAIL_MASK) >> DP83867_CFG3_TDR_FAIL_SHIFT) + +/* + * TDR_DONE (RO) + * + * TDR Done: + * 1 = TDR has completed. + * 0 = TDR has not completed. + */ +#define DP83867_CFG3_TDR_DONE_MASK (0x2U) +#define DP83867_CFG3_TDR_DONE_SHIFT (1U) +#define DP83867_CFG3_TDR_DONE_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_DONE_MASK) >> DP83867_CFG3_TDR_DONE_SHIFT) + +/* + * TDR_START (RW) + * + * TDR Start: + * 1 = Start TDR. + * 0 = Normal operation + */ +#define DP83867_CFG3_TDR_START_MASK (0x1U) +#define DP83867_CFG3_TDR_START_SHIFT (0U) +#define DP83867_CFG3_TDR_START_SET(x) (((uint16_t)(x) << DP83867_CFG3_TDR_START_SHIFT) & DP83867_CFG3_TDR_START_MASK) +#define DP83867_CFG3_TDR_START_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_START_MASK) >> DP83867_CFG3_TDR_START_SHIFT) + +/* Bitfield definition for register: CTRL */ +/* + * SW_RESET (RW,SC) + * + * Software Reset: + * 1 = Perform a full reset, including registers. + * 0 = Normal operation. + */ +#define DP83867_CTRL_SW_RESET_MASK (0x8000U) +#define DP83867_CTRL_SW_RESET_SHIFT (15U) +#define DP83867_CTRL_SW_RESET_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESET_SHIFT) & DP83867_CTRL_SW_RESET_MASK) +#define DP83867_CTRL_SW_RESET_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESET_MASK) >> DP83867_CTRL_SW_RESET_SHIFT) + +/* + * SW_RESTART (RW,SC) + * + * Software Restart: + * 1 = Perform a full reset, not including registers. . + * 0 = Normal operation. + */ +#define DP83867_CTRL_SW_RESTART_MASK (0x4000U) +#define DP83867_CTRL_SW_RESTART_SHIFT (14U) +#define DP83867_CTRL_SW_RESTART_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESTART_SHIFT) & DP83867_CTRL_SW_RESTART_MASK) +#define DP83867_CTRL_SW_RESTART_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESTART_MASK) >> DP83867_CTRL_SW_RESTART_SHIFT) + +/* Bitfield definition for register: RGMIIDCTL */ +/* + * RGMII_TX_DELAY_CTRL (RW) + * + * RGMII Transmit Clock Delay: + * 1111: 4.00 ns + * 1110: 3.75 ns + * 1101: 3.50 ns + * 1100: 3.25 ns + * 1011: 3.00 ns + * 1010: 2.75 ns + * 1001: 2.50 ns + * 1000: 2.25 ns + * 0111: 2.00 ns + * 0110: 1.75 ns + * 0101: 1.50 ns + * 0100: 1.25 ns + * 0011: 1.00 ns + * 0010: 0.75 ns + * 0001: 0.50 ns + * 0000: 0.25 ns + */ +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK (0xF0U) +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT (4U) +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) + +/* + * RGMII_RX_DELAY_CTRL (RW) + * + * RGMII Receive Clock Delay: + * 1111: 4.00 ns + * 1110: 3.75 ns + * 1101: 3.50 ns + * 1100: 3.25 ns + * 1011: 3.00 ns + * 1010: 2.75 ns + * 1001: 2.50 ns + * 1000: 2.25 ns + * 0111: 2.00 ns + * 0110: 1.75 ns + * 0101: 1.50 ns + * 0100: 1.25 ns + * 0011: 1.00 ns + * 0010: 0.75 ns + * 0001: 0.50 ns + * 0000: 0.25 ns + */ +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK (0xFU) +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT (0U) +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) + + + + +#endif /* HPM_DP83867_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h new file mode 100644 index 0000000000..e2ff32796e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ENET_PHY_H +#define HPM_ENET_PHY_H +#include + +typedef enum { + enet_phy_port_speed_10mbps = 0, + enet_phy_port_speed_100mbps, + enet_phy_port_speed_1000mbps +} enet_phy_port_speed_t; + +typedef enum { + enet_phy_duplex_half = 0, + enet_phy_duplex_full +} enet_phy_duplex_mode_t; + +typedef enum { + enet_phy_mdi_crossover_manual_mdi = 0, + enet_phy_mdi_crossover_manual_mdix, + enet_phy_mdi_crossover_automatic +} enet_phy_crossover_mode_t; + +typedef struct { + uint8_t enet_phy_link; + uint8_t enet_phy_speed; + uint8_t enet_phy_duplex; +} enet_phy_status_t; + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h index a35bb20547..a82ab02d72 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h @@ -1,18 +1,26 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ - #ifndef HPM_ENET_PHY_COMMON_H #define HPM_ENET_PHY_COMMON_H -typedef enum { - enet_port_speed_10mbps = 0, - enet_port_speed_100msbs, - enet_port_speed_1000mbps -} enet_port_speed_t; +#if defined(__USE_DP83867) && __USE_DP83867 + #include "hpm_dp83867.h" + #include "hpm_dp83867_regs.h" +#elif defined(__USE_RTL8211) && __USE_RTL8211 + #include "hpm_rtl8211.h" + #include "hpm_rtl8211_regs.h" +#elif defined(__USE_DP83848) && __USE_DP83848 + #include "hpm_dp83848.h" + #include "hpm_dp83848_regs.h" +#elif defined(__USE_RTL8201) && __USE_RTL8201 + #include "hpm_rtl8201.h" + #include "hpm_rtl8201_regs.h" +#else + #error no specified Ethernet PHY !!! +#endif - -#endif \ No newline at end of file +#endif /* HPM_ENET_PHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c index 0293637792..2e931f33ed 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c @@ -1,69 +1,72 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_rtl8201_regs.h" #include "hpm_rtl8201.h" #include "board.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Internal API - *---------------------------------------------------------------------*/ -static bool rtl8201_id_check(ENET_Type *ptr) + *--------------------------------------------------------------------- + */ +static bool rtl8201_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_PHYID2); + id1 = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_PHYID1); + id2 = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_PHYID2); - if (RTL8201_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8201_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (RTL8201_PHYID1_OUI_MSB_GET(id1) == RTL8201_ID1 && RTL8201_PHYID2_OUI_LSB_GET(id2) == RTL8201_ID2) { return true; } else { return false; } } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t rtl8201_register_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void rtl8201_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR, RTL8201_BMCR_RESET_SET(1)); + enet_write_phy(ptr, RTL8201_ADDR, RTL8201_BMCR, RTL8201_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR); + data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_BMCR); } while (RTL8201_BMCR_RESET_GET(data)); } void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config) { - config->loopback = 1; /* Enable PCS loopback mode */ - config->speed = 2; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = 0; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + #endif + config->txc_input = true; /* Set TXC as input mode */ } bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= RTL8201_BMCR_RESET_SET(0) /* Normal operation */ + data |= RTL8201_BMCR_RESET_SET(0) /* Normal operation */ | RTL8201_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ | RTL8201_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ | RTL8201_BMCR_PWD_SET(0) /* Normal operation */ @@ -72,27 +75,37 @@ bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config) | RTL8201_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ if (config->auto_negotiation == 0) { - para |= RTL8201_BMCR_SPEED0_SET(config->speed) | RTL8201_BMCR_SPEED1_SET(config->speed >> 1); + data |= RTL8201_BMCR_SPEED0_SET(config->speed); /* Set port speed */ + data |= RTL8201_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } /* check the id of rtl8201 */ - if (rtl8201_id_check(ptr) == false) { + if (rtl8201_check_id(ptr) == false) { return false; } - para = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR) & ~RTL8201_BMCR_SPEED0_MASK; - enet_write_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR, para); + enet_write_phy(ptr, RTL8201_ADDR, RTL8201_BMCR, data); /* select page 7 */ - enet_write_phy(ptr, PHY_ADDR, 31, 7); - para = enet_read_phy(ptr, PHY_ADDR, 16); - para |= 1 << 12; /* set txc as input mode */ - enet_write_phy(ptr, PHY_ADDR, 16, para); + enet_write_phy(ptr, RTL8201_ADDR, RTL8201_PAGESEL, 7); + + /* set txc direction */ + data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_RMSR_P7); + data &= ~RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK; + data |= RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(config->txc_input); + enet_write_phy(ptr, RTL8201_ADDR, RTL8201_RMSR_P7, data); return true; } - -void rtl8201_init_auto_negotiation(void) +void rtl8201_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { + uint16_t data; + + data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_BMSR); + status->enet_phy_link = RTL8201_BMSR_LINK_STATUS_GET(data); + + data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_BMCR); + status->enet_phy_speed = RTL8201_BMCR_SPEED0_GET(data) == 0 ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; + status->enet_phy_duplex = RTL8201_BMCR_DUPLEX_GET(data); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h index 3359412ffe..c48957efef 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h @@ -1,49 +1,56 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#ifndef HPM_rtl8201_H -#define HPM_rtl8201_H +#ifndef HPM_RTL8201_H +#define HPM_RTL8201_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- * Macro Const Definitions - *---------------------------------------------------------------------*/ -#define PHY_ADDR (2U) -#define PHY_ID1 (0x001CU) -#define PHY_ID2 (0x32U) + *--------------------------------------------------------------------- + */ +#ifndef RTL8201_ADDR +#define RTL8201_ADDR (2U) +#endif -/*---------------------------------------------------------------------* +#define RTL8201_ID1 (0x001CU) +#define RTL8201_ID2 (0x32U) + +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; + bool txc_input; } rtl8201_config_t; #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t rtl8201_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void rtl8201_reset(ENET_Type *ptr); void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config); bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config); -void rtl8201_read_status(ENET_Type *ptr); -void rtl8201_control_config(ENET_Type *ptr); +void rtl8201_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_rtl8201_H */ \ No newline at end of file +#endif /* HPM_RTL8201_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h index 436ac80404..404aaa6e6b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h @@ -1,195 +1,407 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ + #ifndef HPM_RTL8201_REGS_H #define HPM_RTL8201_REGS_H - /* RTL Register Definitions */ -#define RTL8201_REG_BMCR (0U) /* Basic Mode Control Register */ -#define RTL8201_REG_BMSR (1U) /* Basic Mode Status Register */ -#define RTL8201_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define RTL8201_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define RTL8201_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define RTL8201_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define RTL8201_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ +typedef enum { + RTL8201_BMCR = 0, /* 0x0: Basic Mode Control Register */ + RTL8201_BMSR = 1, /* 0x1: (Basic Mode Status Register */ + RTL8201_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ + RTL8201_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ + RTL8201_RMSR_P7 = 16, /* 0x10: RMII Mode Setting Register */ + RTL8201_PAGESEL = 31, /* 0x1F: Page Select Register */ +} RTL8201_REG_Type; -#define RTL8201_REG_RXERC (24U) /* Receive Error Counter */ -#define RTL8201_REG_FB_LP (28U) /* Fiber Mode and Loopback Register */ -#define RTL8201_REG_PAGSEL (31U) /* Page Select Register */ - -/* RTL MMD Register Definitions */ -#define RTL8201_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define RTL8201_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define RTL8201_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define RTL8201_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define RTL8201_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define RTL8201_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ - -/* Page 0 Registers */ -#define RTL8201_REG_MACR (13U) /* MMD Access Control Register */ -#define RTL8201_REG_MAADR (14U) /* MMD Access Address Data Register */ - -/* Bitfiled definitions of Register: MACR */ -#define RTL8201_REGCR_FUNCTION_ADDR (0 << 14) -#define RTL8201_REGCR_FUNCTION_DATA (1 << 14) -#define RTL8201_REGCR_DEVAD (0x1f) /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * - * 1: PHY reset - * 0: Normal operation - * Register 0 (BMCR) and register 1 (BMSR) will return to default - * values after a software reset (set Bit15 to 1). + * This bit sets the status and control registers of the PHY in the + * default state. This bit is self-clearing. + * 1: Software reset 0: Normal operation + * Register 0 and register 1 will return to default values after a + * software reset (set Bit15 to 1). * This action may change the internal PHY state and the state of the * physical link associated with the PHY. */ -#define RTL8201_BMCR_RESET_MASK (0x8000U) +#define RTL8201_BMCR_RESET_MASK (0x8000U) #define RTL8201_BMCR_RESET_SHIFT (15U) -#define RTL8201_BMCR_RESET_SET(x) (((uint32_t)(x) << RTL8201_BMCR_RESET_SHIFT) & RTL8201_BMCR_RESET_MASK) -#define RTL8201_BMCR_RESET_GET(x) (((uint32_t)(x) & RTL8201_BMCR_RESET_MASK) >> RTL8201_BMCR_RESET_SHIFT) +#define RTL8201_BMCR_RESET_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESET_SHIFT) & RTL8201_BMCR_RESET_MASK) +#define RTL8201_BMCR_RESET_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESET_MASK) >> RTL8201_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * - * Loopback Mode. - * 1: Enable PCS loopback mode - * 0: Disable PCS loopback mode + * This bit enables loopback of transmit data nibbles TXD3:0 to the + * receive data path. + * 1: Enable loopback 0: Normal operation */ -#define RTL8201_BMCR_LOOPBACK_MASK (0x4000U) +#define RTL8201_BMCR_LOOPBACK_MASK (0x4000U) #define RTL8201_BMCR_LOOPBACK_SHIFT (14U) -#define RTL8201_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << RTL8201_BMCR_LOOPBACK_SHIFT) & RTL8201_BMCR_LOOPBACK_MASK) -#define RTL8201_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & RTL8201_BMCR_LOOPBACK_MASK) >> RTL8201_BMCR_LOOPBACK_SHIFT) +#define RTL8201_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << RTL8201_BMCR_LOOPBACK_SHIFT) & RTL8201_BMCR_LOOPBACK_MASK) +#define RTL8201_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & RTL8201_BMCR_LOOPBACK_MASK) >> RTL8201_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * This bit sets the network speed. + * 1: 100Mbps 0: 10Mbps + * After completing auto negotiation, this bit will reflect the speed + * status. + * 1: 100Base-T 0: 10Base-T + * When 100Base-FX mode is enabled, this bit=1 and is read only. */ -#define RTL8201_BMCR_SPEED0_MASK (0x2000U) +#define RTL8201_BMCR_SPEED0_MASK (0x2000U) #define RTL8201_BMCR_SPEED0_SHIFT (13U) -#define RTL8201_BMCR_SPEED0_SET(x) (((uint32_t)(x) << RTL8201_BMCR_SPEED0_SHIFT) & RTL8201_BMCR_SPEED0_MASK) -#define RTL8201_BMCR_SPEED0_GET(x) (((uint32_t)(x) & RTL8201_BMCR_SPEED0_MASK) >> RTL8201_BMCR_SPEED0_SHIFT) +#define RTL8201_BMCR_SPEED0_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED0_SHIFT) & RTL8201_BMCR_SPEED0_MASK) +#define RTL8201_BMCR_SPEED0_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED0_MASK) >> RTL8201_BMCR_SPEED0_SHIFT) /* * ANE (RW) * - * Auto-Negotiation Enable. - * 1: Enable Auto-Negotiation - * 0: Disable Auto-Negotiation + * This bit enables/disables the NWay auto-negotiation function. + * 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored + * 0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the + * link speed and the data transfer mode, respectively + * When 100Base-FX mode is enabled, this bit=0 and is read only. */ -#define RTL8201_BMCR_ANE_MASK (0x1000U) +#define RTL8201_BMCR_ANE_MASK (0x1000U) #define RTL8201_BMCR_ANE_SHIFT (12U) -#define RTL8201_BMCR_ANE_SET(x) (((uint32_t)(x) << RTL8201_BMCR_ANE_SHIFT) & RTL8201_BMCR_ANE_MASK) -#define RTL8201_BMCR_ANE_GET(x) (((uint32_t)(x) & RTL8201_BMCR_ANE_MASK) >> RTL8201_BMCR_ANE_SHIFT) +#define RTL8201_BMCR_ANE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ANE_SHIFT) & RTL8201_BMCR_ANE_MASK) +#define RTL8201_BMCR_ANE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ANE_MASK) >> RTL8201_BMCR_ANE_SHIFT) /* * PWD (RW) * - * Power Down. - * 1: Power down (only Management Interface and logic are active; link - * is down) - * 0: Normal operation + * This bit turns down the power of the PHY chip, including the + * internal crystal oscillator circuit. + * The MDC, MDIO is still alive for accessing the MAC. + * 1: Power down 0: Normal operation */ -#define RTL8201_BMCR_PWD_MASK (0x0800U) +#define RTL8201_BMCR_PWD_MASK (0x800U) #define RTL8201_BMCR_PWD_SHIFT (11U) -#define RTL8201_BMCR_PWD_SET(x) (((uint32_t)(x) << RTL8201_BMCR_PWD_SHIFT) & RTL8201_BMCR_PWD_MASK) -#define RTL8201_BMCR_PWD_GET(x) (((uint32_t)(x) & RTL8201_BMCR_PWD_MASK) >> RTL8201_BMCR_PWD_SHIFT) +#define RTL8201_BMCR_PWD_SET(x) (((uint16_t)(x) << RTL8201_BMCR_PWD_SHIFT) & RTL8201_BMCR_PWD_MASK) +#define RTL8201_BMCR_PWD_GET(x) (((uint16_t)(x) & RTL8201_BMCR_PWD_MASK) >> RTL8201_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * - * Isolate. - * 1: RGMII/GMII interface is isolated; the serial management interface - * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * 1: Electrically isolate the PHY from MII/GMII/RGMII/RSGMII. + * PHY is still able to respond to MDC/MDIO. * 0: Normal operation */ -#define RTL8201_BMCR_ISOLATE_MASK (0x0400U) +#define RTL8201_BMCR_ISOLATE_MASK (0x400U) #define RTL8201_BMCR_ISOLATE_SHIFT (10U) -#define RTL8201_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << RTL8201_BMCR_ISOLATE_SHIFT) & RTL8201_BMCR_ISOLATE_MASK) -#define RTL8201_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & RTL8201_BMCR_ISOLATE_MASK) >> RTL8201_BMCR_ISOLATE_SHIFT) +#define RTL8201_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ISOLATE_SHIFT) & RTL8201_BMCR_ISOLATE_MASK) +#define RTL8201_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ISOLATE_MASK) >> RTL8201_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * - * Restart Auto-Negotiation. - * 1: Restart Auto-Negotiation - * 0: Normal operation + * This bit allows the NWay auto-negotiation function to be reset. + * 1: Re-start auto-negotiation 0: Normal operation */ -#define RTL8201_BMCR_RESTART_AN_MASK (0x0200U) +#define RTL8201_BMCR_RESTART_AN_MASK (0x200U) #define RTL8201_BMCR_RESTART_AN_SHIFT (9U) -#define RTL8201_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << RTL8201_BMCR_RESTART_AN_SHIFT) & RTL8201_BMCR_RESTART_AN_MASK) -#define RTL8201_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & RTL8201_BMCR_RESTART_AN_MASK) >> RTL8201_BMCR_RESTART_AN_SHIFT) +#define RTL8201_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESTART_AN_SHIFT) & RTL8201_BMCR_RESTART_AN_MASK) +#define RTL8201_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESTART_AN_MASK) >> RTL8201_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (RW) * - * Duplex Mode. - * 1: Full Duplex operation - * 0: Half Duplex operation - * This bit is valid only in force mode, i.e., NWay is disabled. + * This bit sets the duplex mode if auto-negotiation is disabled (bit + * 0:12=0). + * 1: Full duplex 0: Half duplex + * After completing auto-negotiation, this bit will reflect the duplex + * status. + * 1: Full duplex 0: Half duplex */ -#define RTL8201_BMCR_DUPLEX_MASK (0x0100U) +#define RTL8201_BMCR_DUPLEX_MASK (0x100U) #define RTL8201_BMCR_DUPLEX_SHIFT (8U) -#define RTL8201_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << RTL8201_BMCR_DUPLEX_SHIFT) & RTL8201_BMCR_DUPLEX_MASK) -#define RTL8201_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & RTL8201_BMCR_DUPLEX_MASK) >> RTL8201_BMCR_DUPLEX_SHIFT) +#define RTL8201_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << RTL8201_BMCR_DUPLEX_SHIFT) & RTL8201_BMCR_DUPLEX_MASK) +#define RTL8201_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8201_BMCR_DUPLEX_MASK) >> RTL8201_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * * Collision Test. * 1: Collision test enabled * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. + * When set, this bit will cause the COL signal to be asserted in + * response to the TXEN assertion within 512-bit times. The COL + * signal will be de-asserted within 4-bit times in response to the + * TXEN de-assertion. */ -#define RTL8201_BMCR_COLLISION_TEST_MASK (0x0080U) +#define RTL8201_BMCR_COLLISION_TEST_MASK (0x80U) #define RTL8201_BMCR_COLLISION_TEST_SHIFT (7U) -#define RTL8201_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << RTL8201_BMCR_COLLISION_TEST_SHIFT) & RTL8201_BMCR_COLLISION_TEST_MASK) -#define RTL8201_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & RTL8201_BMCR_COLLISION_TEST_MASK) >> RTL8201_BMCR_COLLISION_TEST_SHIFT) +#define RTL8201_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << RTL8201_BMCR_COLLISION_TEST_SHIFT) & RTL8201_BMCR_COLLISION_TEST_MASK) +#define RTL8201_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & RTL8201_BMCR_COLLISION_TEST_MASK) >> RTL8201_BMCR_COLLISION_TEST_SHIFT) /* - * Speed[1] (RW) + * SPEED1 (RW) * * Speed Select Bit 1. - * Refer to bit 0.13. + * Refer to bit 13. */ -#define RTL8201_BMCR_SPEED1_MASK (0x0040U) +#define RTL8201_BMCR_SPEED1_MASK (0x40U) #define RTL8201_BMCR_SPEED1_SHIFT (6U) -#define RTL8201_BMCR_SPEED1_SET(x) (((uint32_t)(x) << RTL8201_BMCR_SPEED1_SHIFT) & RTL8201_BMCR_SPEED1_MASK) -#define RTL8201_BMCR_SPEED1_GET(x) (((uint32_t)(x) & RTL8201_BMCR_SPEED1_MASK) >> RTL8201_BMCR_SPEED1_SHIFT) +#define RTL8201_BMCR_SPEED1_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED1_SHIFT) & RTL8201_BMCR_SPEED1_MASK) +#define RTL8201_BMCR_SPEED1_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED1_MASK) >> RTL8201_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: BMSR */ +/* + * 100BASE_T4 (RO) + * + * 1: Enable 100Base-T4 support + * 0: Suppress 100Base-T4 support + */ +#define RTL8201_BMSR_100BASE_T4_MASK (0x8000U) +#define RTL8201_BMSR_100BASE_T4_SHIFT (15U) +#define RTL8201_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_T4_MASK) >> RTL8201_BMSR_100BASE_T4_SHIFT) + +/* + * 100BASE_TX_FULL (RO) + * + * 1: Enable 100Base-TX full duplex support + * 0: Suppress 100Base-TX full duplex support + */ +#define RTL8201_BMSR_100BASE_TX_FULL_MASK (0x4000U) +#define RTL8201_BMSR_100BASE_TX_FULL_SHIFT (14U) +#define RTL8201_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_FULL_MASK) >> RTL8201_BMSR_100BASE_TX_FULL_SHIFT) + +/* + * 100BASE_TX_HALF (RO) + * + * 1: Enable 100Base-TX half duplex support + * 0: Suppress 100Base-TX half duplex support + */ +#define RTL8201_BMSR_100BASE_TX_HALF_MASK (0x2000U) +#define RTL8201_BMSR_100BASE_TX_HALF_SHIFT (13U) +#define RTL8201_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_HALF_MASK) >> RTL8201_BMSR_100BASE_TX_HALF_SHIFT) + +/* + * 10BASE_T_FULL (RO) + * + * 1: Enable 10Base-T full duplex support + * 0: Suppress 10Base-T full duplex support + */ +#define RTL8201_BMSR_10BASE_T_FULL_MASK (0x1000U) +#define RTL8201_BMSR_10BASE_T_FULL_SHIFT (12U) +#define RTL8201_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_FULL_MASK) >> RTL8201_BMSR_10BASE_T_FULL_SHIFT) + +/* + * 10BASE_T_HALF (RO) + * + * 1: Enable 10Base-T half duplex support + * 0: Suppress 10Base-T half duplex support + */ +#define RTL8201_BMSR_10BASE_T_HALF_MASK (0x800U) +#define RTL8201_BMSR_10BASE_T_HALF_SHIFT (11U) +#define RTL8201_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_HALF_MASK) >> RTL8201_BMSR_10BASE_T_HALF_SHIFT) + +/* + * PREAMBLE_SUPPRESSION (RO) + * + * The RTL8201F/FL/FN will accept management frames + * with preamble suppressed. + * A minimum of 32 preamble bits are required for the first + * management interface read/write transaction after reset. + * One idle bit is required between any two management + * transactions as per IEEE 802.3u specifications. + */ +#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK) >> RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * 1: Auto-negotiation process completed + * 0: Auto-negotiation process not completed + */ +#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RC) + * + * 1: Remote fault condition detected (cleared on read) + * 0: No remote fault condition detected + * When in 100Base-FX mode, this bit means an in-band + * signal Far-End-Fault has been detected (see 8.10 Far End + * Fault Indication, page 39). + */ +#define RTL8201_BMSR_REMOTE_FAULT_MASK (0x10U) +#define RTL8201_BMSR_REMOTE_FAULT_SHIFT (4U) +#define RTL8201_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_REMOTE_FAULT_MASK) >> RTL8201_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY (RO) + * + * 1: PHY is able to perform auto-negotiation + * 0: PHY is not able to perform auto-negotiation + */ +#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS (RO) + * + * 1: Valid link established + * 0: No valid link established + * This bit indicates whether the link was lost since the last + * read. For the current link status, read this register twice. + */ +#define RTL8201_BMSR_LINK_STATUS_MASK (0x4U) +#define RTL8201_BMSR_LINK_STATUS_SHIFT (2U) +#define RTL8201_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & RTL8201_BMSR_LINK_STATUS_MASK) >> RTL8201_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * 1: Jabber condition detected + * 0: No jabber condition detected + */ +#define RTL8201_BMSR_JABBER_DETECT_MASK (0x2U) +#define RTL8201_BMSR_JABBER_DETECT_SHIFT (1U) +#define RTL8201_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_JABBER_DETECT_MASK) >> RTL8201_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO) + * + * 1: Extended register capable (permanently=1) + * 0: Not extended register capable + */ +#define RTL8201_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define RTL8201_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_EXTENDED_CAPABILITY_MASK) >> RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT) /* Bitfield definition for register: PHYID1 */ /* * OUI_MSB (RO) * - * Organizationally Unique Identifier Bit 3:18. - * Always 0000000000011100. + * Composed of the 6 th to 21 st bits of the Organizationally Unique + * Identifier (OUI), respectively. */ -#define RTL8201_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define RTL8201_PHYID1_OUI_MSB_MASK (0xFFFFU) #define RTL8201_PHYID1_OUI_MSB_SHIFT (0U) -#define RTL8201_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8201_PHYID1_OUI_MSB_MASK) >> RTL8201_PHYID1_OUI_MSB_SHIFT) +#define RTL8201_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID1_OUI_MSB_MASK) >> RTL8201_PHYID1_OUI_MSB_SHIFT) /* Bitfield definition for register: PHYID2 */ /* * OUI_LSB (RO) * - * Organizationally Unique Identifier Bit 19:24. - * Always 110010. + * Assigned to the 0 through 5 th bits of the OUI. RO 110010 */ -#define RTL8201_PHYID2_OUI_MSB_MASK (0xFC00U) -#define RTL8201_PHYID2_OUI_MSB_SHIFT (10U) -#define RTL8201_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8201_PHYID2_OUI_MSB_MASK) >> RTL8201_PHYID2_OUI_MSB_SHIFT) +#define RTL8201_PHYID2_OUI_LSB_MASK (0xFC00U) +#define RTL8201_PHYID2_OUI_LSB_SHIFT (10U) +#define RTL8201_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_OUI_LSB_MASK) >> RTL8201_PHYID2_OUI_LSB_SHIFT) -#endif /* HPM_RTL8201_REGS_H */ \ No newline at end of file +/* + * MODEL_NUMBER (RO) + * + * Model Number + */ +#define RTL8201_PHYID2_MODEL_NUMBER_MASK (0x3F0U) +#define RTL8201_PHYID2_MODEL_NUMBER_SHIFT (4U) +#define RTL8201_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_MODEL_NUMBER_MASK) >> RTL8201_PHYID2_MODEL_NUMBER_SHIFT) + +/* + * REVISION_NUMBER (RO) + * + * Revision Number + */ +#define RTL8201_PHYID2_REVISION_NUMBER_MASK (0xFU) +#define RTL8201_PHYID2_REVISION_NUMBER_SHIFT (0U) +#define RTL8201_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_REVISION_NUMBER_MASK) >> RTL8201_PHYID2_REVISION_NUMBER_SHIFT) + +/* Bitfield definition for register: RMSR_P7 */ +/* + * RG_RMII_CLKDIR (RW) + * + * This Bit Sets the Type of TXC in RMII Mode. + * 0: Output + * 1: Input + */ +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK (0x1000U) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT (12U) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) >> RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) + +/* + * RG_RMII_TX_OFFSET (RW) + * + * Adjust RMII TX Interface Timing. + */ +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK (0xF00U) +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT (8U) +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK) +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT) + +/* + * RG_RMII_RX_OFFSET (RW) + * + * Adjust RMII RX Interface Timing. + */ +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK (0xF0U) +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT (4U) +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK) +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT) + +/* + * RMII_MODE (RW) + * + * 0: MII Mode + * 1: RMII Mode + */ +#define RTL8201_RMSR_P7_RMII_MODE_MASK (0x8U) +#define RTL8201_RMSR_P7_RMII_MODE_SHIFT (3U) +#define RTL8201_RMSR_P7_RMII_MODE_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RMII_MODE_SHIFT) & RTL8201_RMSR_P7_RMII_MODE_MASK) +#define RTL8201_RMSR_P7_RMII_MODE_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RMII_MODE_MASK) >> RTL8201_RMSR_P7_RMII_MODE_SHIFT) + +/* + * RG_RMII_RXDV_SEL (RW) + * + * 0: CRS/CRS_DV pin is CRS_DV signal + * 1: CRS/CRS_DV pin is RXDV signal + */ +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK (0x4U) +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT (2U) +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK) +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT) + +/* + * RG_RMII_RXDSEL (RW) + * + * 0: RMII data only + * 1: RMII data with SSD Error + */ +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK (0x2U) +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT (1U) +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK) +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT) + +/* Bitfield definition for register: PAGESEL */ +/* + * PAGE_SEL (RW) + * + * Select Page Address: 00000000~11111111. + */ +#define RTL8201_PAGESEL_PAGE_SEL_MASK (0xFFU) +#define RTL8201_PAGESEL_PAGE_SEL_SHIFT (0U) +#define RTL8201_PAGESEL_PAGE_SEL_SET(x) (((uint16_t)(x) << RTL8201_PAGESEL_PAGE_SEL_SHIFT) & RTL8201_PAGESEL_PAGE_SEL_MASK) +#define RTL8201_PAGESEL_PAGE_SEL_GET(x) (((uint16_t)(x) & RTL8201_PAGESEL_PAGE_SEL_MASK) >> RTL8201_PAGESEL_PAGE_SEL_SHIFT) + + + + +#endif /* HPM_RTL8201_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c index 09094ca2bf..93f1f757b8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c @@ -1,69 +1,71 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_rtl8211_regs.h" #include "hpm_rtl8211.h" #include "board.h" -/*---------------------------------------------------------------------* - * Interal API - *---------------------------------------------------------------------*/ -static bool rtl8211_id_check(ENET_Type *ptr) +/*--------------------------------------------------------------------- + * Internal API + *--------------------------------------------------------------------- + */ +static bool rtl8211_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYID2); + id1 = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_PHYID1); + id2 = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_PHYID2); - if (RTL8211_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8211_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (RTL8211_PHYID1_OUI_MSB_GET(id1) == RTL8211_ID1 && RTL8211_PHYID2_OUI_LSB_GET(id2) == RTL8211_ID2) { return true; } else { return false; } } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t rtl8211_register_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void rtl8211_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR, RTL8211_BMCR_RESET_SET(1)); + enet_write_phy(ptr, RTL8211_ADDR, RTL8211_BMCR, RTL8211_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR); + data = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_BMCR); } while (RTL8211_BMCR_RESET_GET(data)); } void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config) { - config->loopback = 0; /* Enable PCS loopback mode */ - config->speed = 1; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = 0; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + #endif } bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= RTL8211_BMCR_RESET_SET(0) /* Normal operation */ + data |= RTL8211_BMCR_RESET_SET(0) /* Normal operation */ | RTL8211_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ | RTL8211_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ | RTL8211_BMCR_PWD_SET(0) /* Normal operation */ @@ -72,50 +74,27 @@ bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config) | RTL8211_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ if (config->auto_negotiation == 0) { - para |= RTL8211_BMCR_SPEED0_SET(config->speed) | RTL8211_BMCR_SPEED1_SET(config->speed >> 1); + data |= RTL8211_BMCR_SPEED0_SET(config->speed) | RTL8211_BMCR_SPEED1_SET(config->speed >> 1); /* Set port speed */ + data |= RTL8211_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } - enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR, para); + enet_write_phy(ptr, RTL8211_ADDR, RTL8211_BMCR, data); /* check the id of rtl8211 */ - if (rtl8211_id_check(ptr) == false) { + if (rtl8211_check_id(ptr) == false) { return false; } return true; } -void rtl8211_auto_negotiation_init(void) + +void rtl8211_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { - /* TODO */ + uint16_t data; + + data = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_PHYSR); + status->enet_phy_link = RTL8211_PHYSR_LINK_REAL_TIME_GET(data); + status->enet_phy_speed = RTL8211_PHYSR_SPEED_GET(data) == 0 ? enet_phy_port_speed_10mbps : RTL8211_PHYSR_SPEED_GET(data) == 1 ? enet_phy_port_speed_100mbps : enet_phy_port_speed_1000mbps; + status->enet_phy_duplex = RTL8211_PHYSR_DUPLEX_GET(data); } - - -void rtl8211_read_status(ENET_Type *ptr) -{ - uint16_t status; - - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_BMSR); - printf("BMSR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_GBSR); - printf("GBSR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_GBESR); - printf("GBESR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYSR); - printf("PHYSR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_RXERC); - printf("RXERC: %08x\n", status); - - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR); - printf("PHYCR, %x\n", status); -} - -void rtl8211_control_config(ENET_Type *ptr) -{ - uint16_t para = 0; - - para = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR) | (1 << 10); - - enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR, para); - -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h index 5b20857335..c9914ab7a0 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,42 +8,49 @@ #ifndef HPM_RTL8211_H #define HPM_RTL8211_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- + * * Macro Const Definitions - *---------------------------------------------------------------------*/ -#define PHY_ADDR (2U) -#define PHY_ID1 (0x001CU) -#define PHY_ID2 (0x32U) + *--------------------------------------------------------------------- + */ +#ifndef RTL8211_ADDR +#define RTL8211_ADDR (2U) +#endif -/*---------------------------------------------------------------------* +#define RTL8211_ID1 (0x001CU) +#define RTL8211_ID2 (0x32U) + +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; } rtl8211_config_t; #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t rtl8211_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void rtl8211_reset(ENET_Type *ptr); void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config); bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config); -void rtl8211_read_status(ENET_Type *ptr); -void rtl8211_control_config(ENET_Type *ptr); +void rtl8211_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_RTL8211_H */ \ No newline at end of file +#endif /* HPM_RTL8211_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h index 567c76e798..dabd89a6b8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h @@ -1,48 +1,28 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ + #ifndef HPM_RTL8211_REGS_H #define HPM_RTL8211_REGS_H - /* RTL Register Definitions */ -#define RTL8211_REG_BMCR (0U) /* Basic Mode Control Register */ -#define RTL8211_REG_BMSR (1U) /* Basic Mode Status Register */ -#define RTL8211_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define RTL8211_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define RTL8211_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define RTL8211_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define RTL8211_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ -#define RTL8211_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ -#define RTL8211_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ -#define RTL8211_REG_GBCR (9U) /* 1000Base-T Control Register */ -#define RTL8211_REG_GBSR (10U) /* 1000Base-T Status Register */ +typedef enum { + RTL8211_BMCR = 0, /* 0x0: Basic Mode Control Register */ + RTL8211_BMSR = 1, /* 0x1: (Basic Mode Status Register */ + RTL8211_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ + RTL8211_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ + RTL8211_PHYSR = 17, /* 0x11: PHY Specific Status Register */ +} RTL8211_REG_Type; -#define RTL8211_REG_MACR (13U) /* MMD Access Control Register */ -#define RTL8211_REG_MAADR (14U) /* MMD Access Address Data Register */ -#define RTL8211_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ -#define RTL8211_REG_PHYCR (16U) /* PHY Specific Control Register */ -#define RTL8211_REG_PHYSR (17U) /* PHY Specific Status Register */ -#define RTL8211_REG_INER (18U) /* Interrupt Enable Register */ -#define RTL8211_REG_INSR (19U) /* Interrupt Status Register */ -#define RTL8211_REG_RXERC (24U) /* Receive Error Counter */ -#define RTL8211_REG_PAGSEL (31U) /* Page Select Register */ - -/* RTL MMD Register Definitions */ -#define RTL8211_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define RTL8211_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define RTL8211_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define RTL8211_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define RTL8211_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define RTL8211_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * + * Reset. * 1: PHY reset * 0: Normal operation * Register 0 (BMCR) and register 1 (BMSR) will return to default @@ -50,34 +30,38 @@ * This action may change the internal PHY state and the state of the * physical link associated with the PHY. */ -#define RTL8211_BMCR_RESET_MASK (0x8000U) +#define RTL8211_BMCR_RESET_MASK (0x8000U) #define RTL8211_BMCR_RESET_SHIFT (15U) -#define RTL8211_BMCR_RESET_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESET_SHIFT) & RTL8211_BMCR_RESET_MASK) -#define RTL8211_BMCR_RESET_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESET_MASK) >> RTL8211_BMCR_RESET_SHIFT) +#define RTL8211_BMCR_RESET_SET(x) (((uint16_t)(x) << RTL8211_BMCR_RESET_SHIFT) & RTL8211_BMCR_RESET_MASK) +#define RTL8211_BMCR_RESET_GET(x) (((uint16_t)(x) & RTL8211_BMCR_RESET_MASK) >> RTL8211_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * * Loopback Mode. * 1: Enable PCS loopback mode * 0: Disable PCS loopback mode */ -#define RTL8211_BMCR_LOOPBACK_MASK (0x4000U) +#define RTL8211_BMCR_LOOPBACK_MASK (0x4000U) #define RTL8211_BMCR_LOOPBACK_SHIFT (14U) -#define RTL8211_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << RTL8211_BMCR_LOOPBACK_SHIFT) & RTL8211_BMCR_LOOPBACK_MASK) -#define RTL8211_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & RTL8211_BMCR_LOOPBACK_MASK) >> RTL8211_BMCR_LOOPBACK_SHIFT) +#define RTL8211_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << RTL8211_BMCR_LOOPBACK_SHIFT) & RTL8211_BMCR_LOOPBACK_MASK) +#define RTL8211_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & RTL8211_BMCR_LOOPBACK_MASK) >> RTL8211_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * Speed Select (Bits 6, 13): + * When auto-negotiation is disabled writing to this bit allows the port + * speed to be selected. + * 11 = Reserved + * 10 = Reserved + * 1 = 100 Mbps + * 0 = 10 Mbps */ -#define RTL8211_BMCR_SPEED0_MASK (0x2000U) +#define RTL8211_BMCR_SPEED0_MASK (0x2000U) #define RTL8211_BMCR_SPEED0_SHIFT (13U) -#define RTL8211_BMCR_SPEED0_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED0_SHIFT) & RTL8211_BMCR_SPEED0_MASK) -#define RTL8211_BMCR_SPEED0_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED0_MASK) >> RTL8211_BMCR_SPEED0_SHIFT) +#define RTL8211_BMCR_SPEED0_SET(x) (((uint16_t)(x) << RTL8211_BMCR_SPEED0_SHIFT) & RTL8211_BMCR_SPEED0_MASK) +#define RTL8211_BMCR_SPEED0_GET(x) (((uint16_t)(x) & RTL8211_BMCR_SPEED0_MASK) >> RTL8211_BMCR_SPEED0_SHIFT) /* * ANE (RW) @@ -86,10 +70,10 @@ * 1: Enable Auto-Negotiation * 0: Disable Auto-Negotiation */ -#define RTL8211_BMCR_ANE_MASK (0x1000U) +#define RTL8211_BMCR_ANE_MASK (0x1000U) #define RTL8211_BMCR_ANE_SHIFT (12U) -#define RTL8211_BMCR_ANE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ANE_SHIFT) & RTL8211_BMCR_ANE_MASK) -#define RTL8211_BMCR_ANE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ANE_MASK) >> RTL8211_BMCR_ANE_SHIFT) +#define RTL8211_BMCR_ANE_SET(x) (((uint16_t)(x) << RTL8211_BMCR_ANE_SHIFT) & RTL8211_BMCR_ANE_MASK) +#define RTL8211_BMCR_ANE_GET(x) (((uint16_t)(x) & RTL8211_BMCR_ANE_MASK) >> RTL8211_BMCR_ANE_SHIFT) /* * PWD (RW) @@ -99,77 +83,244 @@ * is down) * 0: Normal operation */ -#define RTL8211_BMCR_PWD_MASK (0x0800U) +#define RTL8211_BMCR_PWD_MASK (0x800U) #define RTL8211_BMCR_PWD_SHIFT (11U) -#define RTL8211_BMCR_PWD_SET(x) (((uint32_t)(x) << RTL8211_BMCR_PWD_SHIFT) & RTL8211_BMCR_PWD_MASK) -#define RTL8211_BMCR_PWD_GET(x) (((uint32_t)(x) & RTL8211_BMCR_PWD_MASK) >> RTL8211_BMCR_PWD_SHIFT) +#define RTL8211_BMCR_PWD_SET(x) (((uint16_t)(x) << RTL8211_BMCR_PWD_SHIFT) & RTL8211_BMCR_PWD_MASK) +#define RTL8211_BMCR_PWD_GET(x) (((uint16_t)(x) & RTL8211_BMCR_PWD_MASK) >> RTL8211_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * * Isolate. * 1: RGMII/GMII interface is isolated; the serial management interface * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * RTL8211E-VB(VL)/RTL8211EG-VB ignores TXD[7:0], and TXCLT + * inputs, and presents a high impedance on TXC, RXC, RXCLT, + * RXD[7:0]. * 0: Normal operation */ -#define RTL8211_BMCR_ISOLATE_MASK (0x0400U) +#define RTL8211_BMCR_ISOLATE_MASK (0x400U) #define RTL8211_BMCR_ISOLATE_SHIFT (10U) -#define RTL8211_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ISOLATE_SHIFT) & RTL8211_BMCR_ISOLATE_MASK) -#define RTL8211_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ISOLATE_MASK) >> RTL8211_BMCR_ISOLATE_SHIFT) +#define RTL8211_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << RTL8211_BMCR_ISOLATE_SHIFT) & RTL8211_BMCR_ISOLATE_MASK) +#define RTL8211_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & RTL8211_BMCR_ISOLATE_MASK) >> RTL8211_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * * Restart Auto-Negotiation. * 1: Restart Auto-Negotiation * 0: Normal operation */ -#define RTL8211_BMCR_RESTART_AN_MASK (0x0200U) +#define RTL8211_BMCR_RESTART_AN_MASK (0x200U) #define RTL8211_BMCR_RESTART_AN_SHIFT (9U) -#define RTL8211_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESTART_AN_SHIFT) & RTL8211_BMCR_RESTART_AN_MASK) -#define RTL8211_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESTART_AN_MASK) >> RTL8211_BMCR_RESTART_AN_SHIFT) +#define RTL8211_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << RTL8211_BMCR_RESTART_AN_SHIFT) & RTL8211_BMCR_RESTART_AN_MASK) +#define RTL8211_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & RTL8211_BMCR_RESTART_AN_MASK) >> RTL8211_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (RW) * * Duplex Mode. * 1: Full Duplex operation * 0: Half Duplex operation * This bit is valid only in force mode, i.e., NWay is disabled. */ -#define RTL8211_BMCR_DUPLEX_MASK (0x0100U) +#define RTL8211_BMCR_DUPLEX_MASK (0x100U) #define RTL8211_BMCR_DUPLEX_SHIFT (8U) -#define RTL8211_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << RTL8211_BMCR_DUPLEX_SHIFT) & RTL8211_BMCR_DUPLEX_MASK) -#define RTL8211_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & RTL8211_BMCR_DUPLEX_MASK) >> RTL8211_BMCR_DUPLEX_SHIFT) +#define RTL8211_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << RTL8211_BMCR_DUPLEX_SHIFT) & RTL8211_BMCR_DUPLEX_MASK) +#define RTL8211_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8211_BMCR_DUPLEX_MASK) >> RTL8211_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * * Collision Test. * 1: Collision test enabled * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. */ -#define RTL8211_BMCR_COLLISION_TEST_MASK (0x0080U) +#define RTL8211_BMCR_COLLISION_TEST_MASK (0x80U) #define RTL8211_BMCR_COLLISION_TEST_SHIFT (7U) -#define RTL8211_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << RTL8211_BMCR_COLLISION_TEST_SHIFT) & RTL8211_BMCR_COLLISION_TEST_MASK) -#define RTL8211_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & RTL8211_BMCR_COLLISION_TEST_MASK) >> RTL8211_BMCR_COLLISION_TEST_SHIFT) +#define RTL8211_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << RTL8211_BMCR_COLLISION_TEST_SHIFT) & RTL8211_BMCR_COLLISION_TEST_MASK) +#define RTL8211_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & RTL8211_BMCR_COLLISION_TEST_MASK) >> RTL8211_BMCR_COLLISION_TEST_SHIFT) /* - * Speed[1] (RW) + * SPEED1 (RW) * * Speed Select Bit 1. - * Refer to bit 0.13. + * Refer to bit 13. */ -#define RTL8211_BMCR_SPEED1_MASK (0x0040U) +#define RTL8211_BMCR_SPEED1_MASK (0x40U) #define RTL8211_BMCR_SPEED1_SHIFT (6U) -#define RTL8211_BMCR_SPEED1_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED1_SHIFT) & RTL8211_BMCR_SPEED1_MASK) -#define RTL8211_BMCR_SPEED1_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED1_MASK) >> RTL8211_BMCR_SPEED1_SHIFT) +#define RTL8211_BMCR_SPEED1_SET(x) (((uint16_t)(x) << RTL8211_BMCR_SPEED1_SHIFT) & RTL8211_BMCR_SPEED1_MASK) +#define RTL8211_BMCR_SPEED1_GET(x) (((uint16_t)(x) & RTL8211_BMCR_SPEED1_MASK) >> RTL8211_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: BMSR */ +/* + * 100BASE_T4 (RO) + * + * 100Base-T4 Capability. + * The RTL8211E-VB(VL)/RTL8211EG-VB does not support + * 100Base-T4 mode. This bit should always be 0. + */ +#define RTL8211_BMSR_100BASE_T4_MASK (0x8000U) +#define RTL8211_BMSR_100BASE_T4_SHIFT (15U) +#define RTL8211_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_T4_MASK) >> RTL8211_BMSR_100BASE_T4_SHIFT) + +/* + * 100BASE_TX_FULL (RO) + * + * 100Base-TX Full Duplex Capability. + * 1: Device is able to perform 100Base-TX in full duplex mode + * 0: Device is not able to perform 100Base-TX in full duplex mode + */ +#define RTL8211_BMSR_100BASE_TX_FULL_MASK (0x4000U) +#define RTL8211_BMSR_100BASE_TX_FULL_SHIFT (14U) +#define RTL8211_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_TX_FULL_MASK) >> RTL8211_BMSR_100BASE_TX_FULL_SHIFT) + +/* + * 100BASE_TX_HALF (RO) + * + * 100Base-TX Half Duplex Capability. + * 1: Device is able to perform 100Base-TX in half duplex mode + * 0: Device is not able to perform 100Base-TX in half duplex mode + */ +#define RTL8211_BMSR_100BASE_TX_HALF_MASK (0x2000U) +#define RTL8211_BMSR_100BASE_TX_HALF_SHIFT (13U) +#define RTL8211_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_TX_HALF_MASK) >> RTL8211_BMSR_100BASE_TX_HALF_SHIFT) + +/* + * 10BASE_T_FULL (RO) + * + * 10Base-T Full Duplex Capability. + * 1: Device is able to perform 10Base-T in full duplex mode. + * 0: Device is not able to perform 10Base-T in full duplex mode. + */ +#define RTL8211_BMSR_10BASE_T_FULL_MASK (0x1000U) +#define RTL8211_BMSR_10BASE_T_FULL_SHIFT (12U) +#define RTL8211_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T_FULL_MASK) >> RTL8211_BMSR_10BASE_T_FULL_SHIFT) + +/* + * 10BASE_T_HALF (RO) + * + * 10Base-T Half Duplex Capability. + * 1: Device is able to perform 10Base-T in half duplex mode + * 0: Device is not able to perform 10Base-T in half duplex mode + */ +#define RTL8211_BMSR_10BASE_T_HALF_MASK (0x800U) +#define RTL8211_BMSR_10BASE_T_HALF_SHIFT (11U) +#define RTL8211_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T_HALF_MASK) >> RTL8211_BMSR_10BASE_T_HALF_SHIFT) + +/* + * 10BASE_T2_FULL (RO) + * + * 10Base-T2 Full Duplex Capability. + * The RTL8211E-VB(VL)/RTL8211EG-VB does not support + * 10Base-T2 mode and this bit should always be 0. + */ +#define RTL8211_BMSR_10BASE_T2_FULL_MASK (0x400U) +#define RTL8211_BMSR_10BASE_T2_FULL_SHIFT (10U) +#define RTL8211_BMSR_10BASE_T2_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T2_FULL_MASK) >> RTL8211_BMSR_10BASE_T2_FULL_SHIFT) + +/* + * 10BASE_T2_HALF (RO) + * + * 10Base-T2 Half Duplex Capability. + * The RTL8211E-VB(VL)/RTL8211EG-VB does not support + * 10Base-T2 mode. This bit should always be 0. + */ +#define RTL8211_BMSR_10BASE_T2_HALF_MASK (0x200U) +#define RTL8211_BMSR_10BASE_T2_HALF_SHIFT (9U) +#define RTL8211_BMSR_10BASE_T2_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T2_HALF_MASK) >> RTL8211_BMSR_10BASE_T2_HALF_SHIFT) + +/* + * 1000BASE_T_EXTENDED_STATUS (RO) + * + * 1000Base-T Extended Status Register. + * 1: Device supports Extended Status Register 0x0F (15) + * 0: Device does not support Extended Status Register 0x0F + * This register is read-only and is always set to 1. + */ +#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_MASK (0x100U) +#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_SHIFT (8U) +#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_MASK) >> RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_SHIFT) + +/* + * PREAMBLE_SUPPRESSION (RO) + * + * Preamble Suppression Capability (Permanently On). + * The RTL8211E-VB(VL)/RTL8211EG-VB always accepts + * transactions with preamble suppressed. + */ +#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & RTL8211_BMSR_PREAMBLE_SUPPRESSION_MASK) >> RTL8211_BMSR_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * Auto-Negotiation Complete. + * 1: Auto-Negotiation process complete, and contents of registers + * 5, 6, 8, and 10 are valid + * 0: Auto-Negotiation process not complete + */ +#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RC) + * + * Remote Fault. + * 1: Remote fault condition detected (cleared on read or by reset). + * Indication or notification of remote fault from Link Partner + * 0: No remote fault condition detected + */ +#define RTL8211_BMSR_REMOTE_FAULT_MASK (0x10U) +#define RTL8211_BMSR_REMOTE_FAULT_SHIFT (4U) +#define RTL8211_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & RTL8211_BMSR_REMOTE_FAULT_MASK) >> RTL8211_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY (RO) + * + * Auto Configured Link. + * 1: Device is able to perform Auto-Negotiation + * 0: Device is not able to perform Auto-Negotiation + */ +#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status. + * 1: Linked + * 0: Not Linked + * This register indicates whether the link was lost since the last read. + * For the current link status, either read this register twice or read + * register bit 17.10 Link Real Time. + */ +#define RTL8211_BMSR_LINK_STATUS_MASK (0x4U) +#define RTL8211_BMSR_LINK_STATUS_SHIFT (2U) +#define RTL8211_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & RTL8211_BMSR_LINK_STATUS_MASK) >> RTL8211_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT (RC) + * + * Jabber Detect. + * 1: Jabber condition detected + * 0: No Jabber occurred + */ +#define RTL8211_BMSR_JABBER_DETECT_MASK (0x2U) +#define RTL8211_BMSR_JABBER_DETECT_SHIFT (1U) +#define RTL8211_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & RTL8211_BMSR_JABBER_DETECT_MASK) >> RTL8211_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO) + * + * 1: Extended register capabilities, always 1 + */ +#define RTL8211_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define RTL8211_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define RTL8211_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & RTL8211_BMSR_EXTENDED_CAPABILITY_MASK) >> RTL8211_BMSR_EXTENDED_CAPABILITY_SHIFT) /* Bitfield definition for register: PHYID1 */ /* @@ -178,9 +329,9 @@ * Organizationally Unique Identifier Bit 3:18. * Always 0000000000011100. */ -#define RTL8211_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define RTL8211_PHYID1_OUI_MSB_MASK (0xFFFFU) #define RTL8211_PHYID1_OUI_MSB_SHIFT (0U) -#define RTL8211_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID1_OUI_MSB_MASK) >> RTL8211_PHYID1_OUI_MSB_SHIFT) +#define RTL8211_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & RTL8211_PHYID1_OUI_MSB_MASK) >> RTL8211_PHYID1_OUI_MSB_SHIFT) /* Bitfield definition for register: PHYID2 */ /* @@ -189,8 +340,112 @@ * Organizationally Unique Identifier Bit 19:24. * Always 110010. */ -#define RTL8211_PHYID2_OUI_MSB_MASK (0xFC00U) -#define RTL8211_PHYID2_OUI_MSB_SHIFT (10U) -#define RTL8211_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID2_OUI_MSB_MASK) >> RTL8211_PHYID2_OUI_MSB_SHIFT) +#define RTL8211_PHYID2_OUI_LSB_MASK (0xFC00U) +#define RTL8211_PHYID2_OUI_LSB_SHIFT (10U) +#define RTL8211_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_OUI_LSB_MASK) >> RTL8211_PHYID2_OUI_LSB_SHIFT) -#endif /* HPM_RTL8211_REGS_H */ \ No newline at end of file +/* + * MODEL_NUMBER (RO) + * + * Manufacture’s Model Number + */ +#define RTL8211_PHYID2_MODEL_NUMBER_MASK (0x3F0U) +#define RTL8211_PHYID2_MODEL_NUMBER_SHIFT (4U) +#define RTL8211_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_MODEL_NUMBER_MASK) >> RTL8211_PHYID2_MODEL_NUMBER_SHIFT) + +/* + * REVISION_NUMBER (RO) + * + * Revision Number + */ +#define RTL8211_PHYID2_REVISION_NUMBER_MASK (0xFU) +#define RTL8211_PHYID2_REVISION_NUMBER_SHIFT (0U) +#define RTL8211_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_REVISION_NUMBER_MASK) >> RTL8211_PHYID2_REVISION_NUMBER_SHIFT) + +/* Bitfield definition for register: PHYSR */ +/* + * SPEED (RO) + * + * Link Speed. + * 11: Reserved 10: 1000Mbps + * 01: 100Mbps 00: 10Mbps + */ +#define RTL8211_PHYSR_SPEED_MASK (0xC000U) +#define RTL8211_PHYSR_SPEED_SHIFT (14U) +#define RTL8211_PHYSR_SPEED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_SPEED_MASK) >> RTL8211_PHYSR_SPEED_SHIFT) + +/* + * DUPLEX (RO) + * + * Full/Half Duplex Mode. + * 1: Full duplex 0: Half duplex + */ +#define RTL8211_PHYSR_DUPLEX_MASK (0x2000U) +#define RTL8211_PHYSR_DUPLEX_SHIFT (13U) +#define RTL8211_PHYSR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_DUPLEX_MASK) >> RTL8211_PHYSR_DUPLEX_SHIFT) + +/* + * PAGE_RECEIVED (RC) + * + * New Page Received. + * 1: Page received 0: Page not received + */ +#define RTL8211_PHYSR_PAGE_RECEIVED_MASK (0x1000U) +#define RTL8211_PHYSR_PAGE_RECEIVED_SHIFT (12U) +#define RTL8211_PHYSR_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_PAGE_RECEIVED_MASK) >> RTL8211_PHYSR_PAGE_RECEIVED_SHIFT) + +/* + * SPEED_AND_DUPLEX_RESOLVED (RO) + * + * Speed and Duplex Mode Resolved. + * 1: Resolved 0: Not resolved + */ +#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_MASK (0x800U) +#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_SHIFT (11U) +#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_MASK) >> RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_SHIFT) + +/* + * LINK_REAL_TIME (RO) + * + * Real Time Link Status. + * 1: Link OK 0: Link not OK + */ +#define RTL8211_PHYSR_LINK_REAL_TIME_MASK (0x400U) +#define RTL8211_PHYSR_LINK_REAL_TIME_SHIFT (10U) +#define RTL8211_PHYSR_LINK_REAL_TIME_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_LINK_REAL_TIME_MASK) >> RTL8211_PHYSR_LINK_REAL_TIME_SHIFT) + +/* + * MDI_CROSSOVER_STATUS (RO) + * + * MDI/MDI Crossover Status. + * 1: MDI Crossover 0: MDI + */ +#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_MASK (0x40U) +#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_SHIFT (6U) +#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_MDI_CROSSOVER_STATUS_MASK) >> RTL8211_PHYSR_MDI_CROSSOVER_STATUS_SHIFT) + +/* + * PRE_LINKOK (RO) + * + * Reflects Local Receiver is OK. + * 0: Receiver is not OK + * 1: Receiver is OK + */ +#define RTL8211_PHYSR_PRE_LINKOK_MASK (0x2U) +#define RTL8211_PHYSR_PRE_LINKOK_SHIFT (1U) +#define RTL8211_PHYSR_PRE_LINKOK_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_PRE_LINKOK_MASK) >> RTL8211_PHYSR_PRE_LINKOK_SHIFT) + +/* + * JABBER_REAL_TIME (RO) + * + * Real Time Jabber Indication. + * 1: Jabber Indication 0: No jabber Indication + */ +#define RTL8211_PHYSR_JABBER_REAL_TIME_MASK (0x1U) +#define RTL8211_PHYSR_JABBER_REAL_TIME_SHIFT (0U) +#define RTL8211_PHYSR_JABBER_REAL_TIME_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_JABBER_REAL_TIME_MASK) >> RTL8211_PHYSR_JABBER_REAL_TIME_SHIFT) + + + + +#endif /* HPM_RTL8211_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c new file mode 100644 index 0000000000..100c1db7b9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_ipc_event_mgr.h" +#include "hpm_ipc_event_mgr_mbx_internal.h" + +/***************************************************************************************************************** + * + * Definitions + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Prototypes + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Variables + * + *****************************************************************************************************************/ +static ipc_event_t s_ipc_event_table[ipc_event_table_len]; + +/***************************************************************************************************************** + * + * Codes + * + *****************************************************************************************************************/ +void ipc_init(void) +{ + ipc_init_internal(); +} + +void ipc_enable_event_interrupt(uint32_t priority) +{ + ipc_enable_event_interrupt_internal(priority); +} + +void ipc_disable_event_interrupt(void) +{ + ipc_disable_event_interrupt_internal(); +} + +hpm_stat_t ipc_register_event(ipc_event_type_t type, ipc_event_callback_t callback, void *callback_data) +{ + hpm_stat_t status; + + if ((type >= ipc_event_table_len) || (callback == NULL)) { + status = status_invalid_argument; + } else { + s_ipc_event_table[type].callback = callback; + s_ipc_event_table[type].callback_data = callback_data; + status = status_success; + } + + return status; +} + +hpm_stat_t ipc_tigger_event(ipc_event_type_t type, uint16_t event_data) +{ + hpm_stat_t status; + uint32_t remote_data; + + if (type >= ipc_event_table_len) { + status = status_invalid_argument; + } else { + remote_data = (((uint32_t)type) << 16) | event_data; + ipc_tigger_event_internal(remote_data); + status = status_success; + } + + return status; +} + +void ipc_event_handler(uint32_t data) +{ + uint16_t event_type; + uint16_t event_data; + + if (0U != data) { + event_type = (uint16_t)(data >> 16u); + event_data = (uint16_t)(data & 0x0000FFFFu); + + if (((ipc_event_type_t)event_type >= ipc_remote_start_event) && ((ipc_event_type_t)event_type < ipc_event_table_len)) { + if (s_ipc_event_table[(ipc_event_type_t)event_type].callback != NULL) { + s_ipc_event_table[(ipc_event_type_t)event_type].callback( + event_data, s_ipc_event_table[(ipc_event_type_t)event_type].callback_data); + } + } + } +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h new file mode 100644 index 0000000000..a4c6e4e936 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_IPC_EVENT_MGR_H +#define HPM_IPC_EVENT_MGR_H + +#ifdef __cplusplus + +extern "C" { +#endif + +/** + * @brief Type definition of event callback function pointer. + * + * @param [in] event data + * @param [in] callback context data + */ +typedef void (*ipc_event_callback_t)(uint16_t event_data, void *context); + +/** + * @brief Type definition of structure with event handler and data. + */ +typedef struct { + ipc_event_callback_t callback; /**< Pointer to callback function.*/ + void *callback_data; /**< Context data for callback.*/ +} ipc_event_t; + +/** + * @brief Type definition of event types. + */ +typedef enum { + ipc_remote_start_event = 1, + ipc_remote_rpmsg_event, + ipc_event_table_len +} ipc_event_type_t; + +/** + * @brief IPC Init. + */ +void ipc_init(void); + +/** + * @brief Enbale IPC event interrupt. + * + * @param [in] interrupt priority + */ +void ipc_enable_event_interrupt(uint32_t priority); + +/** + * @brief Disbale IPC event interrupt. + */ +void ipc_disable_event_interrupt(void); + +/** + * @brief Register IPC event + * + * @param [in] event type + * @param [in] event callback function + * @param [in] event callback data + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + */ +hpm_stat_t ipc_register_event(ipc_event_type_t type, ipc_event_callback_t callback, void *callback_data); + +/** + * @brief Trigger IPC event + * + * @param [in] event type + * @param [in] event data + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t ipc_tigger_event(ipc_event_type_t type, uint16_t event_data); + +/*! + * @brief event handler + * + * This function is called when event received + * + * @param [in] event type and data. + */ +void ipc_event_handler(uint32_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_IPC_EVENT_MGR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h new file mode 100644 index 0000000000..f71116127e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_IPC_EVENT_MGR_MBX_CONFIG_H +#define HPM_IPC_EVENT_MGR_MBX_CONFIG_H + + +#if defined(HPM_FEATURE_MBX_SIDE_A) +#define HPM_MBX HPM_MBX0A +#define IRQn_MBX IRQn_MBX0A +#elif defined(HPM_FEATURE_MBX_SIDE_B) +#define HPM_MBX HPM_MBX0B +#define IRQn_MBX IRQn_MBX0B +#endif + + +#endif /* HPM_IPC_EVENT_MGR_MBX_CONFIG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c new file mode 100644 index 0000000000..ebdb0e6c51 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc.h" +#include "hpm_mbx_drv.h" +#include "hpm_ipc_event_mgr.h" +#include "hpm_ipc_event_mgr_mbx_config.h" +#include "hpm_ipc_event_mgr_mbx_internal.h" + +/***************************************************************************************************************** + * + * Definitions + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Prototypes + * + *****************************************************************************************************************/ +static void mbx_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_MBX, mbx_isr) + +/***************************************************************************************************************** + * + * Variables + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Codes + * + *****************************************************************************************************************/ +void ipc_init_internal(void) +{ + mbx_init(HPM_MBX); +} + +void ipc_enable_event_interrupt_internal(uint32_t priority) +{ + mbx_enable_intr(HPM_MBX, MBX_CR_RWMVIE_MASK); + intc_m_enable_irq_with_priority(IRQn_MBX, priority); +} + +void ipc_disable_event_interrupt_internal(void) +{ + mbx_disable_intr(HPM_MBX, MBX_CR_RWMVIE_MASK); + intc_m_disable_irq(IRQn_MBX); +} + +hpm_stat_t ipc_tigger_event_internal(uint32_t remote_data) +{ + return mbx_send_message(HPM_MBX, remote_data); +} + +/*! + * @brief ISR handler + * + * This function is called when data from MBX is received + */ +static void mbx_isr(void) +{ + uint32_t data; + hpm_stat_t state; + + state = mbx_retrieve_message(HPM_MBX, &data); + + if (state == status_success) { + ipc_event_handler(data); + } +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h new file mode 100644 index 0000000000..cb22df04b3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_IPC_EVENT_MGR_MBX_INTERNAL_H +#define HPM_IPC_EVENT_MGR_MBX_INTERNAL_H + +#ifdef __cplusplus + +extern "C" { +#endif + +/** + * @brief Initial MBX. + */ +void ipc_init_internal(void); + +/** + * @brief Enbale MBX event interrupt + * + * @param [in] interrupt priority + */ +void ipc_enable_event_interrupt_internal(uint32_t priority); + +/** + * @brief Disbale MBX event interrupt + */ +void ipc_disable_event_interrupt_internal(void); + +/** + * @brief Trigger MBX event + * + * @param [in] remote data + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t ipc_tigger_event_internal(uint32_t remote_data); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_IPC_EVENT_MGR_MBX_INTERNAL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.c b/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.c new file mode 100644 index 0000000000..3c01164889 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sccb.h" + +hpm_stat_t sccb_master_init(sccb_type sccb) +{ + /*TODO*/ + return status_success; +} + +uint8_t sccb_master_scan(sccb_type sccb) +{ + for (uint8_t addr = 0x01, rxdata; addr < 0xff; addr++) { + if (i2c_master_read(sccb, addr, &rxdata, 1) == status_success) { + return addr; + } + } + return 0; +} + +hpm_stat_t sccb_master_gencall(sccb_type sccb, uint8_t cmd) +{ + uint8_t reg_data = 0; + return i2c_master_address_write(sccb, 0x00, &cmd, 1, ®_data, 1); +} + +hpm_stat_t sccb_master_readb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t *reg_data) +{ + return i2c_master_address_read(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, 1, reg_data, 1); +} + +hpm_stat_t sccb_master_writeb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t reg_data) +{ + return i2c_master_address_write(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, 1, (uint8_t *)®_data, 1); +} + +hpm_stat_t sccb_master_readb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t *reg_data) +{ + uint8_t r[2]; + r[0] = reg_addr >> 8; + r[1] = reg_addr & 0xFF; + return i2c_master_address_read(sccb, (uint16_t)slv_addr, r, sizeof(r), reg_data, 1); +} + +hpm_stat_t sccb_master_writeb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t reg_data) +{ + int ret = 0; + uint8_t r[2]; + r[0] = reg_addr >> 8; + r[1] = reg_addr & 0xFF; + return i2c_master_address_write(sccb, (uint16_t)slv_addr, r, sizeof(r), (uint8_t *)®_data, 1); +} + +hpm_stat_t sccb_master_readw(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t *reg_data) +{ + hpm_stat_t ret = status_success; + ret = i2c_master_address_read(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, + 1, (uint8_t *)reg_data, 2); + if (ret == status_success) { + *reg_data = (*reg_data >> 8) | (*reg_data << 8); + } + return ret; +} + +hpm_stat_t sccb_master_writew(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t reg_data) +{ + reg_data = (reg_data >> 8) | (reg_data << 8); + return i2c_master_address_write(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, 1, (uint8_t *)®_data, 2); +} + +hpm_stat_t sccb_master_readw2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t *reg_data) +{ + hpm_stat_t ret = status_success; + ret = i2c_master_address_read(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, + 2, (uint8_t *)reg_data, 2); + if (ret == status_success) { + *reg_data = (*reg_data >> 8) | (*reg_data << 8); + } + return ret; +} + +hpm_stat_t sccb_master_writew2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t reg_data) +{ + int ret = 0; + reg_data = (reg_data >> 8) | (reg_data << 8); + return i2c_master_address_write(sccb, (uint16_t)slv_addr, + (uint8_t *)®_addr, 2, + (uint8_t *)®_data, 2); +} + +hpm_stat_t sccb_master_read_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags) +{ + return i2c_master_read(sccb, (uint16_t)slv_addr, buf, len); +} + +hpm_stat_t cambus_write_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags) +{ + int ret = 0; + hpm_stat_t sta = status_success; + int _len = len; + int remain = 0; + int offset = 0; + while (_len > 0) { + remain = (_len > 100) ? 100 : _len; + sta = i2c_master_write(sccb, (uint16_t)slv_addr, &buf[offset], remain); + if (sta != status_success) { + return status_fail; + } + offset += remain; + _len -= remain; + } + return sta; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.h b/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.h new file mode 100644 index 0000000000..888c6b3e0a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SCCB_H +#define HPM_SCCB_H + +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_i2c_drv.h" + +typedef I2C_Type *sccb_type; + +typedef enum _sccb_xfer_flag { + /*Normal transfer with start condition, address, data and stop condition.*/ + sccb_xfer_no_flags, + /*This flag allows the next transfer to change direction with repeated start*/ + sccb_xfer_no_stop, + /*This flag allows chaining multiple writes or reads with the same direction*/ + sccb_xfer_suspend, +} sccb_xfer_flags_t; + +typedef struct _sccb_bus { + uint8_t initialzed; + sccb_type sccb; +} hpm_sccb_bus_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief sccb master initialization + * + * @details Initialized sccb working at master mode + * + * @param [in] sccb sccb base address + * @retval hpm_stat_t: status_success if initialization is completed without any error + */ +hpm_stat_t sccb_master_init(sccb_type sccb); + +/** + * @brief sccb master scan slave addr + * + * @details master scan the slave + * + * @param [in] sccb sccb base address + * @retval uint8_t: the slave address val is zero if scan slave fail + */ +uint8_t sccb_master_scan(sccb_type sccb); + +/** + * @brief sccb master gen call slave + * + * @details the controller sends the command to determine whether the slave responds + * + * @param [in] sccb sccb base address + * @param [in] cmd sccb master sends command + * @retval hpm_stat_t: status_success if the slave responds + */ +hpm_stat_t sccb_master_gencall(sccb_type sccb, uint8_t cmd); + +/** + * @brief sccb master read 8bit data of specify 8bit register from certain slave device + * + * @details the function used to access 8 bit register address,read 8bit data + * @note the register address must be 8bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 8bit register address of sccb slave device + * @param [out] reg_data point of the buffer to store 8bit data from device the number of bytes is 1 + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t sccb_master_readb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t *reg_data); + +/** + * @brief sccb master write 8bit data of specify 8bit register from certain slave device + * + * @details the function used to access 8 bit register address,write 8bit data + * @note the register address must be 8bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 8bit register address of sccb slave device + * @param [out] reg_data write 8bit data + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t sccb_master_writeb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t reg_data); + +/** + * @brief sccb master read 8bit data of specify 16bit register from certain slave device + * + * @details the function used to access 16 bit register address,read 8bit data + * @note the register address must be 16bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 16bit register address of sccb slave device + * @param [out] reg_data point of the buffer to store 8bit data from device the number of bytes is 1 + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t sccb_master_readb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t *reg_data); + +/** + * @brief sccb master write 8bit data of specify 16bit register from certain slave device + * + * @details the function used to access 16 bit register address,write 8bit data + * @note the register address must be 8bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 16bit register address of sccb slave device + * @param [out] reg_data wirite 8bit data + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t sccb_master_writeb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t reg_data); + +/** + * @brief sccb master read 16bit data of specify 8bit register from certain slave device + * + * @details the function used to access 8 bit register address,read 16bit data + * @note the register address must be 8bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 8bit register address of sccb slave device + * @param [out] reg_data point of the buffer to store 16bit data from device the number of bytes is 1 + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t sccb_master_readw(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t *reg_data); + +/** + * @brief sccb master write 16bit data of specify 8bit register from certain slave device + * + * @details the function used to access 8 bit register address,write 16bit data + * @note the register address must be 8bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 8bit register address of sccb slave device + * @param [out] reg_data wirite 16bit data + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t sccb_master_writew(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t reg_data); + +/** + * @brief sccb master read 16bit data of specify 16it register from certain slave device + * + * @details the function used to access 16 bit register address,read 16bit data + * @note the register address must be 16bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 16bit register address of sccb slave device + * @param [out] reg_data point of the buffer to store 16bit data from device the number of bytes is 1 + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t sccb_master_readw2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t *reg_data); + +/** + * @brief sccb master write 16bit data of specify 16bit register from certain slave device + * + * @details the function used to access 16bit register address,write 16bit data + * @note the register address must be 16bit + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] reg_addr 16bit register address of sccb slave device + * @param [out] reg_data wirite 16bit data + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t sccb_master_writew2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t reg_data); + +/** + * @brief sccb master reads the specified number of bytes continuously at the specified flag + * + * @details the size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] buf point of the buffer to store 8bit data from device + * @param [out] len size of data to be read in bytes + * @param [in] len size of data to be read in bytes + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t sccb_master_read_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags); + +/** + * @brief sccb master weite the specified number of bytes continuously at the specified flag + * + * @details the size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] sccb sccb base address + * @param [in] slv_addr sccb slave address + * @param [out] buf point of the buffer to store 8bit data from device + * @param [out] len size of data to be write in bytes + * @param [in] len size of data to be write in bytes + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t cambus_write_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h index f50cf48ec0..14cfbe9ef1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h @@ -1,6 +1,6 @@ -// -// Created by hpm15 on 3/11/21. -// +/* */ +/* Created by hpm15 on 3/11/21. */ +/* */ #ifndef SFDP_DEF_H #define SFDP_DEF_H @@ -8,44 +8,42 @@ #include #include "hpm_common.h" -//! @brief Commands for probing the FLASH device +/* ! @brief Commands for probing the FLASH device */ #define kSerialFlash_ReadSFDP (0x5AU) #define kSerialFlash_ReadManufacturerId (0x9FU) -//!@brief SFDP related definitions +/* !@brief SFDP related definitions */ #define SFDP_SIGNATURE (0x50444653UL) /* ASCII: SFDP */ #define kSfdp_Version_Major_1_0 (1U) -#define kSfdp_Version_Minor_0 (0U) // JESD216 -#define kSfdp_Version_Minor_A (5U) // JESD216A -#define kSfdp_Version_Minor_B (6U) // JESD216B -#define kSfdp_Version_Minor_C (7U) // JESD216C -#define kSfdp_Version_Minor_D (8U) // JESD216D +#define kSfdp_Version_Minor_0 (0U) /* JESD216 */ +#define kSfdp_Version_Minor_A (5U) /* JESD216A */ +#define kSfdp_Version_Minor_B (6U) /* JESD216B */ +#define kSfdp_Version_Minor_C (7U) /* JESD216C */ +#define kSfdp_Version_Minor_D (8U) /* JESD216D */ #define kSfdp_BasicProtocolTableSize_Rev0 (36U) #define kSfdp_BasicProtocolTableSize_RevA (64U) #define kSfdp_BasicProtocolTableSize_RevB kSfdp_BasicProtocolTableSize_RevA #define kSfdp_BasicProtocolTableSize_RevC (80U) #define kSfdp_BasicProtocolTableSize_RevD kSfdp_BasicProtocolTableSize_RevC -typedef union _sfdp_header -{ +typedef union _sfdp_header { uint32_t words[2]; - struct - { + struct { uint32_t signature; uint8_t minor_rev; uint8_t major_rev; uint8_t param_hdr_num; - uint8_t sfdp_access_protocol; // Defined in JESD216C, reserved for older version + uint8_t sfdp_access_protocol; /* Defined in JESD216C, reserved for older version */ }; } sfdp_header_t; -//!@brief SFDP parameter Type ID definitions +/* !@brief SFDP parameter Type ID definitions */ #define kParameterID_BasicSpiProtocol (0xFF00U) -// New Table added in JESD216B +/* New Table added in JESD216B */ #define kParameterID_SectorMap (0xFF81U) #define kParameterID_4ByteAddressInstructionTable (0xFF84U) -// New Table added in JESD216C +/* New Table added in JESD216C */ #define kParameterID_xSpiProfile1_0 (0xFF05U) #define kParameterID_xSpiOrofile2_0 (0xFF06U) #define kParameterID_StaCtrlCfgRegMap (0xFF87U) @@ -60,16 +58,14 @@ typedef union _sfdp_header #define kCommandExtensionInverseOfCommand (1U) #define kCommandAndCommandExtension16BitWord (2U) -//!@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D +/* !@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D */ #define kEnterOctalMode_Option0 HPM_BITSMASK(1U, 1) #define kEnterOctalMode_Option1 HPM_BITSMASK(1U, 2) -//!@brief SFDP Parameter Header, see JESD216D doc for more details -typedef union _sfdp_parameter_header -{ +/* !@brief SFDP Parameter Header, see JESD216D doc for more details */ +typedef union _sfdp_parameter_header { uint32_t words[2]; - struct - { + struct { uint8_t parameter_id_lsb; uint8_t minor_rev; uint8_t major_rev; @@ -80,14 +76,11 @@ typedef union _sfdp_parameter_header } sfdp_parameter_header_t; -//!@brief Basic Flash Parameter Table, see JESD216D doc for more details -typedef union _jedec_flash_param_table -{ +/* !@brief Basic Flash Parameter Table, see JESD216D doc for more details */ +typedef union _jedec_flash_param_table { uint32_t words[20]; - struct - { - struct - { + struct { + struct { uint32_t erase_size : 2; uint32_t write_granularity : 1; uint32_t reserved0 : 2; @@ -100,79 +93,69 @@ typedef union _jedec_flash_param_table uint32_t supports_1_4_4_fast_read : 1; uint32_t support_1_1_4_fast_read : 1; uint32_t unused1 : 9; - } misc; // 1st word - uint32_t flash_density; // 2nd word - struct - { + } misc; /* 1st word */ + uint32_t flash_density; /* 2nd word */ + struct { uint32_t dummy_clocks_1_4_4_read : 5; uint32_t mode_clocks_1_4_4_read : 3; uint32_t inst_1_4_4_read : 8; uint32_t dummy_clocks_1_1_4_read : 5; uint32_t mode_clocks_1_1_4_read : 3; uint32_t inst_1_1_4_read : 8; - } read_1_4_info; // 3rd word - struct - { + } read_1_4_info; /* 3rd word */ + struct { uint32_t dummy_clocks_1_2_2_read : 5; uint32_t mode_clocks_1_2_2_read : 3; uint32_t inst_1_2_2_read : 8; uint32_t dummy_clocks_1_1_2_read : 5; uint32_t mode_clocks_1_1_2_read : 3; uint32_t inst_1_1_2_read : 8; - } read_1_2_info; // 4th word + } read_1_2_info; /* 4th word */ - struct - { + struct { uint32_t support_2_2_2_fast_read : 1; uint32_t reserved0 : 3; uint32_t support_4_4_4_fast_read : 1; uint32_t reserved1 : 27; - } read_22_44_check; // 5th word + } read_22_44_check; /* 5th word */ - struct - { + struct { uint32_t reserved0 : 16; uint32_t dummy_clocks_2_2_2_read : 5; uint32_t mode_clocks_2_2_2_read : 3; uint32_t inst_2_2_2_read : 8; - } read_2_2_info; // 6th word - struct - { + } read_2_2_info; /* 6th word */ + struct { uint32_t reserved0 : 16; uint32_t dummy_clocks_4_4_4_read : 5; uint32_t mode_clocks_4_4_4_read : 3; uint32_t inst_4_4_4_read : 8; - } read_4_4_info; // 7th word + } read_4_4_info; /* 7th word */ - struct - { + struct { uint8_t size; uint8_t inst; - } erase_info[4]; // 8th,9th word + } erase_info[4]; /* 8th,9th word */ - uint32_t erase_timing; // 10th word - struct - { + uint32_t erase_timing; /* 10th word */ + struct { uint32_t reserved0 : 4; uint32_t page_size : 4; uint32_t reserved1 : 24; - } chip_erase_progrm_info; // 11th word + } chip_erase_progrm_info; /* 11th word */ - struct - { + struct { uint32_t suspend_resume_spec; uint32_t suspend_resume_inst; - } suspend_resume_info; // 12th, 13th word + } suspend_resume_info; /* 12th, 13th word */ - struct - { + struct { uint32_t reserved0 : 2; uint32_t busy_status_polling : 6; uint32_t reserved1 : 24; - } busy_status_info; // 14th word + } busy_status_info; /* 14th word */ - struct - { + struct { uint32_t mode_4_4_4_disable_seq : 4; uint32_t mode_4_4_4_enable_seq : 5; uint32_t support_mode_0_4_4 : 1; @@ -181,29 +164,26 @@ typedef union _jedec_flash_param_table uint32_t quad_enable_requirement : 3; uint32_t hold_reset_disable : 1; uint32_t reserved0 : 8; - } mode_4_4_info; // 15th word + } mode_4_4_info; /* 15th word */ - struct - { + struct { uint32_t status_reg_write_enable : 7; uint32_t reserved0 : 1; uint32_t soft_reset_rescue_support : 6; uint32_t exit_4_byte_addressing : 10; uint32_t enter_4_byte_addrssing : 8; - } mode_config_info; // 16th word + } mode_config_info; /* 16th word */ - struct - { + struct { uint32_t dummy_clocks_1_8_8_read : 5; uint32_t mode_clocks_1_8_8_read : 3; uint32_t inst_1_8_8_read : 8; uint32_t dummy_clocks_1_1_8_read : 5; uint32_t mode_clocks_1_1_8_read : 3; uint32_t inst_1_1_8_read : 8; - } read_1_8_info; // 17th word + } read_1_8_info; /* 17th word */ - struct - { + struct { uint32_t reserved : 18; uint32_t output_driver_strength : 5; uint32_t jedec_spi_protocol_reset : 1; @@ -213,10 +193,9 @@ typedef union _jedec_flash_param_table uint32_t dqs_support_in_opi_str : 1; uint32_t cmd_and_extension_in_opi_ddr : 2; uint32_t byte_order_in_opi_ddr : 1; - } xpi_misc_info; // 18th word + } xpi_misc_info; /* 18th word */ - struct - { + struct { uint32_t opi_sdr_disable_seq : 4; uint32_t opi_sdr_enable_seq : 5; uint32_t support_mode_0_8_8 : 1; @@ -224,10 +203,9 @@ typedef union _jedec_flash_param_table uint32_t mode_0_8_8_entry_method : 4; uint32_t octal_enable_requirement : 3; uint32_t reserved : 9; - } mode_octal_info; // 19th word + } mode_octal_info; /* 19th word */ - struct - { + struct { uint32_t qpi_sdr_no_dqs : 4; uint32_t qpi_sdr_with_dqs : 4; uint32_t qpi_ddr_no_dqs : 4; @@ -236,19 +214,16 @@ typedef union _jedec_flash_param_table uint32_t opi_sdr_with_dqs : 4; uint32_t opi_ddr_no_dqs : 4; uint32_t opi_ddr_with_dqs : 4; - } max_speed_info_xpi; // 20th word + } max_speed_info_xpi; /* 20th word */ }; } jedec_flash_param_table_t; -//!@brief 4Byte Addressing Instruction Table, see JESD216D doc for more details -typedef union _jedec_4byte_addressing_inst_table -{ +/* !@brief 4Byte Addressing Instruction Table, see JESD216D doc for more details */ +typedef union _jedec_4byte_addressing_inst_table { uint32_t words[2]; - struct - { - struct - { + struct { + struct { uint32_t support_1_1_1_read : 1; uint32_t support_1_1_1_fast_read : 1; uint32_t support_1_1_2_fast_read : 1; @@ -272,101 +247,86 @@ typedef union _jedec_4byte_addressing_inst_table uint32_t reserved : 12; } cmd_4byte_support_info; - struct - { + struct { uint8_t erase_inst[4]; } erase_inst_info; }; } jedec_4byte_addressing_inst_table_t; -typedef union _jedec_cmd_sequence_change_to_octal_mode -{ +typedef union _jedec_cmd_sequence_change_to_octal_mode { uint32_t words[8]; - struct - { - struct - { + struct { + struct { uint32_t byte3_of_1st_command_seq : 8; uint32_t byte2_of_1st_command_seq : 8; uint32_t byte1_of_1st_command_seq : 8; uint32_t length_of_1st_command_seq : 8; - } first_command_sequence_low; // 1st command sequence + } first_command_sequence_low; /* 1st command sequence */ - struct - { + struct { uint32_t byte7_of_first_command_seq : 8; uint32_t byte6_of_first_command_seq : 8; uint32_t byte5_of_first_command_seq : 8; uint32_t byte4_of_first_command_seq : 8; - } first_command_sequence_high; // 1st command sequence + } first_command_sequence_high; /* 1st command sequence */ - struct - { + struct { uint32_t byte3_of_2nd_command_seq : 8; uint32_t byte2_of_2nd_command_seq : 8; uint32_t byte1_of_2nd_command_seq : 8; uint32_t length_of_2nd_command_seq : 8; - } second_command_sequence_low; // 2nd command sequence + } second_command_sequence_low; /* 2nd command sequence */ - struct - { + struct { uint32_t byte7_of_2nd_command_seq : 8; uint32_t byte6_of_2nd_command_seq : 8; uint32_t byte5_of_2nd_command_seq : 8; uint32_t byte4_of_2md_command_seq : 8; - } second_command_sequence_high; // 2nd command sequence + } second_command_sequence_high; /* 2nd command sequence */ - struct - { + struct { uint32_t byte3_of_3rd_command_seq : 8; uint32_t byte2_of_3rd_command_seq : 8; uint32_t byte1_of_3rd_command_seq : 8; uint32_t length_of_3rd_command_seq : 8; - } third_command_sequence_low; // 3rd command sequence + } third_command_sequence_low; /* 3rd command sequence */ - struct - { + struct { uint32_t byte7_of_3rd_command_seq : 8; uint32_t byte6_of_3rd_command_seq : 8; uint32_t byte5_of_3rd_command_seq : 8; uint32_t byte4_of_3rd_command_seq : 8; - } third_command_sequence_high; // 3rd command sequence + } third_command_sequence_high; /* 3rd command sequence */ - struct - { + struct { uint32_t byte3_of_4th_command_seq : 8; uint32_t byte2_of_4th_command_seq : 8; uint32_t byte1_of_4th_command_seq : 8; uint32_t length_of_4th_command_seq : 8; - } fourth_command_sequence_low; // 4th command sequence + } fourth_command_sequence_low; /* 4th command sequence */ - struct - { + struct { uint32_t byte7_of_4th_command_seq : 8; uint32_t byte6_of_4th_command_seq : 8; uint32_t byte5_of_4th_command_seq : 8; uint32_t byte4_of_4th_command_seq : 8; - } fourth_command_sequence_high; // 4th command sequence + } fourth_command_sequence_high; /* 4th command sequence */ }; } jedec_cmd_sequence_change_to_octal_mode_t; -typedef union _jedec_x_spi_profile1_0_table_t -{ +typedef union _jedec_x_spi_profile1_0_table_t { uint32_t words[5]; - struct - { - struct - { + struct { + struct { uint32_t fast_read_wrapped_cmd : 8; uint32_t fast_read_cmd : 8; uint32_t reserved : 16; } table1; - struct - { + struct { uint32_t write_nv_register_cmd : 8; uint32_t write_v_register_cmd : 8; uint32_t reserved : 16; @@ -377,14 +337,11 @@ typedef union _jedec_x_spi_profile1_0_table_t } jedec_x_spi_profile1_0_table_t; -typedef union _jedec_status_control_configuration_reg_map -{ +typedef union _jedec_status_control_configuration_reg_map { uint32_t words[28]; - struct - { + struct { uint32_t unused_table[2]; - struct - { + struct { uint32_t dummy_cycles_1s_1s_1s : 4; uint32_t reserved0 : 2; uint32_t dummy_cycles_8d_8d_8d : 4; @@ -400,15 +357,14 @@ typedef union _jedec_status_control_configuration_reg_map }; } jedec_status_control_configuration_reg_map_t; -typedef struct _jdec_query_table -{ - uint32_t standard_version; // JESD216 version +typedef struct _jdec_query_table { + uint32_t standard_version; /* JESD216 version */ uint32_t flash_param_tbl_size; jedec_flash_param_table_t flash_param_tbl; bool has_4b_addressing_inst_table; jedec_4byte_addressing_inst_table_t flash_4b_inst_tbl; bool has_otcal_ddr_mode_enable_sequence_table; - jedec_cmd_sequence_change_to_octal_mode_t otcal_ddr_mode_enable_sequence; // JESD216C/D + jedec_cmd_sequence_change_to_octal_mode_t otcal_ddr_mode_enable_sequence; /* JESD216C/D */ jedec_x_spi_profile1_0_table_t profile1_0_table; bool has_spi_profile1_0_table; jedec_status_control_configuration_reg_map_t sccr_map; @@ -416,7 +372,7 @@ typedef struct _jdec_query_table } jedec_info_table_t; -//!@brief Typical Serial NOR commands supported by most Serial NOR devices +/* !@brief Typical Serial NOR commands supported by most Serial NOR devices */ #define kSerialNorCmd_BasicRead_3B (0x03U) #define kSerialNorCmd_BasicRead_4B (0x13U) #define kSerialNorCmd_PageProgram_1_1_1_3B (0x02U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c new file mode 100644 index 0000000000..aef45cfddd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_smbus.h" + +static uint8_t hpm_smbus_pec_crc8(uint8_t *data, uint32_t len); + + +hpm_stat_t hpm_smbus_master_write_byte(I2C_Type *ptr, uint8_t slave_address, uint8_t data) +{ + hpm_stat_t stat; + uint8_t buf[3]; + /* addr + rw bit*/ + buf[0] = slave_address << 1; + buf[1] = data; + buf[2] = hpm_smbus_pec_crc8(buf, 2); + stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); + return stat; +} + +hpm_stat_t hpm_smbus_master_read_byte(I2C_Type *ptr, uint8_t slave_address, uint8_t *data) +{ + uint8_t buf[3]; + hpm_stat_t stat; + uint8_t pec; + /* addr + rw bit*/ + buf[0] = (slave_address << 1); + stat = i2c_master_read(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); + if (stat == status_success) { + pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); + if (pec == buf[2]) { + *data = buf[1]; + } else { + stat = status_fail; + } + } + return stat; +} + +hpm_stat_t hpm_smbus_master_write_byte_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t data) +{ + hpm_stat_t stat; + uint8_t buf[4]; + /* addr + rw bit*/ + buf[0] = slave_address << 1; + buf[1] = command; + buf[2] = data; + buf[3] = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); + stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); + return stat; +} + +hpm_stat_t hpm_smbus_master_write_word_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint16_t data) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[5]; + /* addr + rw bit*/ + buf[0] = slave_address << 1; + buf[1] = command; + *(uint16_t *)(&buf[2]) = data; + buf[4] = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); + stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); + return stat; +} + +hpm_stat_t hpm_smbus_master_read_byte_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[5]; + /* addr + rw bit*/ + buf[0] = (slave_address << 1); + buf[1] = command; + /* write command code in smbus spec*/ + stat = i2c_master_seq_transmit(ptr, (const uint16_t)slave_address, &command, sizeof(uint8_t), i2c_frist_frame); + if (stat == status_success) { + /* read */ + buf[2] = (slave_address << 1) | 0x01; + /* now change dir,restart, read the byte */ + stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[3], 1, i2c_frist_frame); + /* read the pec */ + stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[4], 1, i2c_last_frame); + if (stat == status_success) { + pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); + if (pec == buf[4]) { + *data = buf[3]; + } else { + stat = status_fail; + } + } + } + return stat; +} + +hpm_stat_t hpm_smbus_master_read_word_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint16_t *data) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[6]; + /* addr + rw bit*/ + buf[0] = (slave_address << 1); + buf[1] = command; + /* write command code in smbus spec*/ + stat = i2c_master_seq_transmit(ptr, (const uint16_t)slave_address, &command, sizeof(uint8_t), i2c_frist_frame); + if (stat == status_success) { + /* read */ + buf[2] = (slave_address << 1) | 0x01; + /* now change dir,restart, read the word (16 bits)*/ + stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[3], 2, i2c_frist_frame); + /* read the pec */ + stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[5], 1, i2c_last_frame); + if (stat == status_success) { + pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); + if (pec == buf[5]) { + *data = *(uint16_t *)(&buf[3]); + } else { + stat = status_fail; + } + } + } + return stat; +} + +hpm_stat_t hpm_smbus_master_write_block_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data, uint32_t size) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; + uint16_t buf_size; + /* frame included addr, command, data, and pec */ + assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 3)); + /* addr + rw bit*/ + buf[0] = slave_address << 1; + buf[1] = command; + buf[2] = size; + memcpy(&buf[3], data, size); + buf[size + 3] = hpm_smbus_pec_crc8(buf, size + 3); + buf_size = size + 4; + stat = i2c_master_write(ptr, (const uint16_t)slave_address, buf, buf_size); + return stat; +} + +hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data, uint32_t size) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; + uint16_t buf_size; + /* frame included addr, command, data, and pec */ + assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 3)); + /* addr + rw bit*/ + buf[0] = (slave_address << 1); + buf[1] = command; + /* write command code in smbus spec*/ + stat = i2c_master_seq_transmit(ptr, (const uint16_t)slave_address, &command, sizeof(uint8_t), i2c_frist_frame); + /* read */ + buf[2] = (slave_address << 1) | 0x01; + if (stat == status_success) { + /* now change dir,restart, read the block count*/ + stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[3], 1, i2c_frist_frame); + /* read data*/ + stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[4], size, i2c_next_frame); + /* read pec */ + stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[size + 4], 1, i2c_last_frame); + if (stat == status_success) { + pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); + if (pec == buf[size + 4]) { + memcpy(data, &buf[4], size); + } else { + stat = status_fail; + } + } + } + return stat; +} + +hpm_stat_t hpm_smbus_master_write(I2C_Type *ptr, uint8_t slave_address, uint8_t *data, uint32_t size) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; + uint16_t buf_size; + /* frame included addr, data, and pec */ + assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 1)); + /* addr + rw bit*/ + buf[0] = (slave_address << 1) | 0x01; + memcpy(&buf[1], data, size); + buf[size + 1] = hpm_smbus_pec_crc8(buf, size + 1); + buf_size = size + 1; + stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], buf_size); + return stat; +} + +hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, uint8_t *data, uint32_t size) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; + uint16_t buf_size; + /* frame included addr, data, and pec */ + assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); + buf[0] = (slave_address << 1); + stat = i2c_master_read(ptr, slave_address, &buf[1], size + 1); + if (stat == status_success) { + pec = hpm_smbus_pec_crc8(buf, size + 1); + if (pec == buf[size + 1]) { + memcpy(data, &buf[1], size); + } else { + stat = status_fail; + } + } + return stat; +} + +hpm_stat_t hpm_smbus_slave_write(I2C_Type *ptr, uint8_t *data, uint32_t size) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; + uint16_t buf_size; + uint8_t slave_address; + /* frame included addr, data, and pec */ + assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 1)); + slave_address = ptr->ADDR; + /* addr + rw bit*/ + buf[0] = (slave_address << 1); + memcpy(&buf[1], data, size); + buf[size + 1] = hpm_smbus_pec_crc8(buf, size + 1); + buf_size = size + 1; + stat = i2c_slave_write(ptr, &buf[1], buf_size); + return stat; +} + +hpm_stat_t hpm_smbus_slave_read(I2C_Type *ptr, uint8_t *data, uint32_t size) +{ + hpm_stat_t stat; + uint8_t pec; + uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; + uint16_t buf_size; + uint8_t slave_address; + /* frame included addr, data, and pec */ + assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); + /* addr + rw bit*/ + slave_address = ptr->ADDR; + buf[0] = (slave_address << 1) | 0x01; + stat = i2c_slave_read(ptr, &buf[1], size + 1); + if (stat == status_success) { + pec = hpm_smbus_pec_crc8(buf, size + 1); + if (pec == buf[size + 1]) { + memcpy(data, &buf[1], size); + } else { + stat = status_fail; + } + } + return stat; +} + +static uint8_t hpm_smbus_pec_crc8(uint8_t *data, uint32_t len) +{ + /* The PEC is a CRC-8 error-checking byte, calculated on all the message bytes (including addresses and read/write bits) */ + uint32_t i; + uint8_t crc = 0x00; + while (len--) { + crc ^= *data++; + for (i = 0; i < 8; i++) { + if (crc & 0x80) { + crc = (crc << 1) ^ 0x07; + } else { + crc <<= 1; + } + } + } + return crc; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.h b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.h new file mode 100644 index 0000000000..c29ef58305 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SMBUS_H +#define HPM_SMBUS_H + +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_i2c_drv.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief SMbus master write data + * + * @details write data at slave mode + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] data byte to be writed + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t hpm_smbus_master_write_byte(I2C_Type *ptr, uint8_t slave_address, + uint8_t data); + +/** + * @brief SMbus master read byte from certain slave device + * + * @details Read byte from SMbus device + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [out] data pointer of the byte read from device + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t hpm_smbus_master_read_byte(I2C_Type *ptr, uint8_t slave_address, + uint8_t *data); + +/** + * @brief SMbus master write byte from certain slave device in command code + * + * @details write byte from SMbus device in command code + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] command command code + * @param [in] data byte to be writed + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t hpm_smbus_master_write_byte_in_command(I2C_Type *ptr, uint8_t slave_address, + uint8_t command, uint8_t data); + +/** + * @brief SMbus master write word(16bits) from certain slave device in command code + * + * @details write word(16bits) from SMbus device in command code + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] command command code + * @param [in] data word to be writed + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t hpm_smbus_master_write_word_in_command(I2C_Type *ptr, uint8_t slave_address, + uint8_t command, uint16_t data); + +/** + * @brief SMbus master read byte from certain slave device in command code + * + * @details read byte from SMbus device in command code + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] command command code + * @param [in] data byte to be read + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t hpm_smbus_master_read_byte_in_command(I2C_Type *ptr, uint8_t slave_address, + uint8_t command, uint8_t *data); + +/** + * @brief SMbus master read word(16bits) from certain slave device in command code + * + * @details read word from SMbus device in command code + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] command command code + * @param [in] data word to be read + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t hpm_smbus_master_read_word_in_command(I2C_Type *ptr, uint8_t slave_address, + uint8_t command, uint16_t *data); + +/** + * @brief SMbus master block write from certain slave device in command code + * + * @details block write from SMbus device in command code + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] command command code + * @param [in] data pointer of the buffer to store data read from device + * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t hpm_smbus_master_write_block_in_command(I2C_Type *ptr, uint8_t slave_address, + uint8_t command, uint8_t *data, uint32_t size); + +/** + * @brief SMbus master block read from certain slave device in command code + * + * @details block read from SMbus device in command code + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] command command code + * @param [out] data pointer of the buffer to store data read from device + * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_address, + uint8_t command, uint8_t *data, uint32_t size); + +/** + * @brief SMbus master write data to certain slave device + * + * @details Write data to SMbus device + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [in] data pointer of the data to be sent + * @param [in] size size of data to be sent in bytes + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t hpm_smbus_master_write(I2C_Type *ptr, uint8_t slave_address, + uint8_t *data, uint32_t size); + +/** + * @brief SMbus master read data from certain slave device + * + * @details Read data from SMbus device + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] ptr I2C base address + * @param [in] device_address SMbus slave address + * @param [out] data pointer of the buffer to store data read from device + * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, + uint8_t *data, uint32_t size); + +/** + * @brief SMbus slave write data + * + * @details Write data at SMbus slave mode. + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] ptr I2C base address + * @param [in] buf pointer of the buffer to store data sent from device + * @param [in] size size of data to be sent in bytes + * @retval hpm_stat_t status_success if writing is completed without any error + */ +hpm_stat_t hpm_smbus_slave_write(I2C_Type *ptr, uint8_t *data, uint32_t size); + +/** + * @brief SMbus slave read data + * + * @details Read data at SMbus slave mode + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX + * + * @param [in] ptr I2C base address + * @param [in] buf pointer of the buffer to store data read from device + * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t hpm_smbus_slave_read(I2C_Type *ptr, uint8_t *data, uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c index 039132f114..3343bcddc4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,30 +7,36 @@ #include "hpm_spi.h" -static hpm_stat_t hpm_spi_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t src, uint32_t size) +static hpm_stat_t hpm_spi_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t src, uint8_t data_width, uint32_t size) { dma_handshake_config_t config; + + dma_default_handshake_config(dma_ptr, &config); config.ch_index = ch_num; config.dst = (uint32_t)&spi_ptr->DATA; config.dst_fixed = true; config.src = src; config.src_fixed = false; + config.data_width = data_width; config.size_in_byte = size; - return dma_setup_handshake(dma_ptr, &config); + return dma_setup_handshake(dma_ptr, &config, true); } -static hpm_stat_t hpm_spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, uint32_t size) +static hpm_stat_t hpm_spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, uint8_t data_width, uint32_t size) { dma_handshake_config_t config; + + dma_default_handshake_config(dma_ptr, &config); config.ch_index = ch_num; config.dst = dst; config.dst_fixed = false; config.src = (uint32_t)&spi_ptr->DATA; config.src_fixed = true; + config.data_width = data_width; config.size_in_byte = size; - return dma_setup_handshake(dma_ptr, &config); + return dma_setup_handshake(dma_ptr, &config, true); } @@ -39,21 +45,24 @@ void hpm_spi_prepare_dma_tx_descriptors(spi_context_t *context, spi_control_conf { SPI_Type *ptr = context->ptr; uint32_t dma_transfer_size[trans_count]; - uint32_t tx_size = context->tx_size; + uint32_t tx_count = context->tx_count; uint32_t per_trans_size = context->per_trans_max; - uint32_t dmamux_ch = context->dma_context.tx_dmamux_ch; + uint32_t dma_ch = context->dma_context.tx_dma_ch; uint8_t *tx_buff = context->tx_buff; + dma_channel_config_t dma_ch_config; static uint8_t dummy_cmd = 0xff; uint32_t temp32; uint32_t tx_buff_index = 0; + + dma_default_channel_config(context->dma_context.dma_ptr, &dma_ch_config); for (uint32_t i = 0; i < trans_count; i++) { - if (tx_size > per_trans_size) { + if (tx_count > per_trans_size) { temp32 = per_trans_size; - tx_size -= per_trans_size; + tx_count -= per_trans_size; } else { - temp32 = tx_size; + temp32 = tx_count; } *(spi_transctrl + i) = SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode == spi_trans_write_read_together ? @@ -63,7 +72,9 @@ void hpm_spi_prepare_dma_tx_descriptors(spi_context_t *context, spi_control_conf | SPI_TRANSCTRL_RDTRANCNT_SET(temp32 - 1); if (i == 0) { - temp32 = temp32 + 1; /* DMA transmits one byte more than SPI at the first transmission */ + /* Set the count of data transferred by dma to be one more than that of spi */ + /* when dma transfer finished, there are data in SPI fifo, dma should not execute the dma descriptor which changes SPI CTRL register */ + temp32 = temp32 + 1; } if (i == trans_count - 1) { temp32 = temp32 - 1; @@ -71,49 +82,52 @@ void hpm_spi_prepare_dma_tx_descriptors(spi_context_t *context, spi_control_conf dma_transfer_size[i] = temp32; /* SPI CTRL */ - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->trans_size = 1; - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->linked_ptr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); + dma_ch_config.size_in_byte = 4; + dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); + dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); + dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; + dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; + dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); + dma_config_linked_descriptor(context->dma_context.dma_ptr, tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS, dma_ch, &dma_ch_config); /* SPI CMD */ - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->trans_size = 1; - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->linked_ptr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); + dma_ch_config.size_in_byte = 1; + dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); + dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); + dma_ch_config.src_width = DMA_TRANSFER_WIDTH_BYTE; + dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; + dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); + dma_config_linked_descriptor(context->dma_context.dma_ptr, tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1, dma_ch, &dma_ch_config); /* SPI DATA */ - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->trans_size = dma_transfer_size[i]; - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->src_addr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_buff + tx_buff_index)); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) - | DMA_CHCTRL_CTRL_DSTMODE_SET(DMA_HANDSHAKE_MODE_HANDSHAKE) - | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(DMA_ADDRESS_CONTROL_FIXED) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + dma_ch_config.size_in_byte = dma_transfer_size[i] << context->dma_context.data_width; + dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_buff + tx_buff_index)); + dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); + dma_ch_config.src_width = context->dma_context.data_width; + dma_ch_config.dst_width = context->dma_context.data_width; + dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; if (i == trans_count - 1) { - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = 0; + dma_ch_config.linked_ptr = 0; } else { - (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); + dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); } + dma_config_linked_descriptor(context->dma_context.dma_ptr, tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2, dma_ch, &dma_ch_config); - tx_buff_index += temp32; + tx_buff_index += temp32 * context->data_len_in_byte; } } @@ -122,21 +136,24 @@ void hpm_prepare_dma_rx_descriptors(spi_context_t *context, spi_control_config_t { SPI_Type *ptr = context->ptr; uint32_t dma_transfer_size[trans_count]; - uint32_t rx_size = context->rx_size; + uint32_t rx_count = context->rx_count; uint32_t per_trans_size = context->per_trans_max; - uint32_t dmamux_ch = context->dma_context.rx_dmamux_ch; + uint32_t dma_ch = context->dma_context.rx_dma_ch; uint8_t *rx_buff = context->rx_buff; + dma_channel_config_t dma_ch_config; static uint8_t dummy_cmd = 0xff; uint32_t temp32; uint32_t rx_buff_index = 0; + + dma_default_channel_config(context->dma_context.dma_ptr, &dma_ch_config); for (uint32_t i = 0; i < trans_count; i++) { - if (rx_size > per_trans_size) { + if (rx_count > per_trans_size) { temp32 = per_trans_size; - rx_size -= per_trans_size; + rx_count -= per_trans_size; } else { - temp32 = rx_size; + temp32 = rx_count; } *(spi_transctrl + i) = SPI_TRANSCTRL_TRANSMODE_SET(spi_trans_read_only) | @@ -146,70 +163,83 @@ void hpm_prepare_dma_rx_descriptors(spi_context_t *context, spi_control_config_t dma_transfer_size[i] = temp32; /* SPI CTRL */ - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->trans_size = 1; - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->linked_ptr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); + dma_ch_config.size_in_byte = 4; + dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); + dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); + dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; + dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; + dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); + dma_config_linked_descriptor(context->dma_context.dma_ptr, rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS, dma_ch, &dma_ch_config); /* SPI CMD */ - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->trans_size = 1; - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->linked_ptr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); + dma_ch_config.size_in_byte = 1; + dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); + dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); + dma_ch_config.src_width = DMA_TRANSFER_WIDTH_BYTE; + dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; + dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); + dma_config_linked_descriptor(context->dma_context.dma_ptr, rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1, dma_ch, &dma_ch_config); /* SPI DATA */ - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->trans_size = dma_transfer_size[i]; - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->dst_addr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_buff + rx_buff_index)); - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) - | DMA_CHCTRL_CTRL_SRCMODE_SET(DMA_HANDSHAKE_MODE_HANDSHAKE) - | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(DMA_ADDRESS_CONTROL_FIXED) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + dma_ch_config.size_in_byte = dma_transfer_size[i] << context->dma_context.data_width; + dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); + dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_buff + rx_buff_index)); + dma_ch_config.src_width = context->dma_context.data_width; + dma_ch_config.dst_width = context->dma_context.data_width; + dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; if (i == trans_count - 1) { - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = 0; + dma_ch_config.linked_ptr = 0; } else { - (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = - core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); + dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); } - rx_buff_index += temp32; + dma_config_linked_descriptor(context->dma_context.dma_ptr, rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2, dma_ch, &dma_ch_config); + + rx_buff_index += temp32 * context->data_len_in_byte; } } static uint32_t hpm_spi_get_trans_count(spi_context_t *context, spi_control_config_t *config) { - uint32_t total_trans_size, per_trans_size, trans_count; + uint32_t total_trans_count, per_trans_count, trans_count; - per_trans_size = context->per_trans_max; + per_trans_count = context->per_trans_max; if (config->common_config.trans_mode == spi_trans_write_only || config->common_config.trans_mode == spi_trans_dummy_write) { - total_trans_size = context->tx_size; + total_trans_count = context->tx_count; } else if (config->common_config.trans_mode == spi_trans_read_only || config->common_config.trans_mode == spi_trans_dummy_read) { - total_trans_size = context->rx_size; + total_trans_count = context->rx_count; } else { /* write read together */ - assert(context->tx_size == context->rx_size); - total_trans_size = context->tx_size; + assert(context->tx_count == context->rx_count); + total_trans_count = context->tx_count; } - trans_count = (total_trans_size + per_trans_size - 1) / per_trans_size; + trans_count = (total_trans_count + per_trans_count - 1) / per_trans_count; return trans_count; } +/** + * spi with dma chain workflow + * + * 1. call spi_setup_dma_transfer to config SPI for first transmission + * 2. execute data transmission phase in dma chain descriptor + * 3. execute setting SPI CTRL register phase in dma chain descriptor + * 4. execute writing SPI CMD register phase in dma chain descriptor + * 5. Repeat steps 2-4 until finish the transmission + */ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_control_config_t *config) { hpm_stat_t stat = status_success; @@ -227,12 +257,13 @@ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_con /* active spi cs pin */ context->write_cs(context->cs_pin, SPI_CS_ACTIVE); + /* config SPI for first dma transmission */ stat = spi_setup_dma_transfer(spi_ptr, config, &context->cmd, &context->addr, - MIN(context->tx_size, context->per_trans_max), - MIN(context->rx_size, context->per_trans_max)); + MIN(context->tx_count, context->per_trans_max), + MIN(context->rx_count, context->per_trans_max)); if (stat != status_success) { return stat; } @@ -255,9 +286,10 @@ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_con dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); /* spi tx use chained dma descriptor, spi rx use unchained dma */ stat = hpm_spi_rx_trigger_dma(dma_ptr, - context->dma_context.rx_dmamux_ch, + context->dma_context.rx_dma_ch, spi_ptr, core_local_mem_to_sys_address(context->running_core, (uint32_t)context->rx_buff), + context->dma_context.data_width, context->rx_size); if (stat != status_success) { return stat; @@ -266,15 +298,18 @@ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_con /* use a dummy dma transfer to start SPI trans dma chain */ static uint32_t dummy_data1 = 0xff, dummy_data2 = 0xff; + + dma_default_channel_config(context->dma_context.dma_ptr, &dma_ch_config); dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data1); dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data2); dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; dma_ch_config.size_in_byte = 4; + /* start data transmission phase in dma chain */ dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(dma_linked_descriptor + SPI_DMA_DESC_COUNT_PER_TRANS - 1)); - stat = dma_setup_channel(dma_ptr, dma_channel, &dma_ch_config); + stat = dma_setup_channel(dma_ptr, dma_channel, &dma_ch_config, true); if (stat != status_success) { return stat; } @@ -295,7 +330,7 @@ static hpm_stat_t spi_setup_trans_with_dma(spi_context_t *context, spi_control_c } stat = spi_setup_dma_transfer(spi_ptr, config, &context->cmd, &context->addr, - context->tx_size, context->rx_size); + context->tx_count, context->rx_count); if (stat != status_success) { return stat; } @@ -303,29 +338,22 @@ static hpm_stat_t spi_setup_trans_with_dma(spi_context_t *context, spi_control_c if (trans_mode != spi_trans_write_only && trans_mode != spi_trans_dummy_write && trans_mode != spi_trans_no_data) { dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); stat = hpm_spi_rx_trigger_dma(dma_ptr, - context->dma_context.rx_dmamux_ch, + context->dma_context.rx_dma_ch, spi_ptr, core_local_mem_to_sys_address(context->running_core, (uint32_t)context->rx_buff), + context->dma_context.data_width, context->rx_size); if (stat != status_success) { return stat; } - /* cache invalidate for receive buff */ - if (l1c_dc_is_enabled()) { - l1c_dc_invalidate((uint32_t)context->rx_buff, context->rx_size); - } } if (trans_mode != spi_trans_read_only && trans_mode != spi_trans_dummy_read && trans_mode != spi_trans_no_data) { dmamux_config(dmamux_ptr, context->dma_context.tx_dmamux_ch, context->dma_context.tx_req, true); - /* cache writeback for tx buff */ - if (l1c_dc_is_enabled()) { - l1c_dc_writeback((uint32_t)context->tx_buff, context->tx_size); - } - stat = hpm_spi_tx_trigger_dma(dma_ptr, - context->dma_context.tx_dmamux_ch, + context->dma_context.tx_dma_ch, spi_ptr, core_local_mem_to_sys_address(context->running_core, (uint32_t)context->tx_buff), + context->dma_context.data_width, context->tx_size); if (stat != status_success) { return stat; @@ -346,7 +374,24 @@ hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config hpm_stat_t stat = status_success; uint32_t trans_mode = config->common_config.trans_mode; - if ((context->rx_size > context->per_trans_max) || (context->tx_size > context->per_trans_max)) { + if (l1c_dc_is_enabled()) { + /* cache writeback for tx buff */ + if (context->tx_buff != NULL && context->tx_size != 0) { + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)context->tx_buff); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)context->tx_buff + context->tx_size); + uint32_t aligned_size = aligned_end - aligned_start; + l1c_dc_writeback(aligned_start, aligned_size); + } + /* cache invalidate for receive buff */ + if (context->rx_buff != NULL && context->rx_size != 0) { + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)context->rx_buff); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)context->rx_buff + context->rx_size); + uint32_t aligned_size = aligned_end - aligned_start; + l1c_dc_invalidate(aligned_start, aligned_size); + } + } + + if ((context->rx_count > context->per_trans_max) || (context->tx_count > context->per_trans_max)) { /* multiple SPI transmissions with chained DMA */ assert(trans_mode == spi_trans_read_only || trans_mode == spi_trans_dummy_read || trans_mode == spi_trans_write_only || trans_mode == spi_trans_dummy_write diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h index 91d60e2f42..ae022c61fb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,7 +10,11 @@ #include "hpm_common.h" #include "hpm_spi_drv.h" +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" #include "hpm_misc.h" #include "hpm_l1c_drv.h" @@ -31,6 +35,7 @@ typedef struct { uint8_t tx_dmamux_ch; uint8_t rx_req; uint8_t tx_req; + uint8_t data_width; } spi_dma_context_t; typedef struct { @@ -42,7 +47,10 @@ typedef struct { uint8_t running_core; uint32_t addr; uint32_t rx_size; + uint32_t rx_count; uint32_t tx_size; + uint32_t tx_count; + uint32_t data_len_in_byte; uint32_t per_trans_max; uint32_t *spi_transctrl; void (*write_cs)(uint32_t cs_pin, uint8_t state); @@ -57,6 +65,9 @@ extern "C" { /** * @brief hpm_spi setup dma transfer * + * @note if the transferred data count more than SPI_SOC_TRANSFER_COUNT_MAX, this API will using + * DMA chain descriptors to link SPI transmission. + * * @param[in] spi_context A pointer to the struct of "spi_context_t" * @param[in] spi_config A pointer to the struct of "spi_control_config_t" * @retval status_success if SPI transfers data successfully. diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c index 323546a857..d42fd6eb38 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h index b4c01b48fb..3cc2fe2939 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c index 65378eb3bb..a6ef324f7d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c index b4278ae3ee..26fdabfc70 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h index 89b02c4e43..90bbd76134 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c index afb9a2c08e..ee9fb497af 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h index 9af46c35f0..41e68e7a04 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,10 +10,10 @@ #include "hpm_common.h" -#if CONFIG_TOUCH_FT5406 +#if defined(CONFIG_TOUCH_FT5406) && (CONFIG_TOUCH_FT5406 == 1) #include "hpm_ft5406.h" #define HPM_TOUCH_MAX_POINTS (FT5406_MAX_TOUCH_POINTS) -#elif CONFIG_TOUCH_GT911 +#elif defined(CONFIG_TOUCH_GT911) && (CONFIG_TOUCH_GT911 == 1) #include "hpm_gt911.h" #define HPM_TOUCH_MAX_POINTS (GT911_MAX_TOUCH_POINTS) #else diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c new file mode 100644 index 0000000000..8943eddeea --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_uart_lin.h" + +#ifndef HPM_UART_LIN_RETRY_COUNT +#define HPM_UART_LIN_RETRY_COUNT (50000U) +#endif + +#ifndef HPM_UART_LIN_BREAK_LENGTH +#define HPM_UART_LIN_BREAK_LENGTH (13U) +#endif + + +uint8_t hpm_uart_lin_calculate_protected_id(uint8_t id) +{ + uint8_t id0, id1, id2, id3, id4, id5, p0, p1, pid; + + /* P0 = ID0 @ ID1 @ ID2 @ ID3 @ ID4 */ + /* P1 = !(ID1 @ ID2 @ ID3 @ ID4 @ ID5) */ + id0 = (id >> 0U) & 0x1U; + id1 = (id >> 1U) & 0x1U; + id2 = (id >> 2U) & 0x1U; + id3 = (id >> 3U) & 0x1U; + id4 = (id >> 4U) & 0x1U; + id5 = (id >> 5U) & 0x1U; + + p0 = id0 ^ id1 ^ id2 ^ id4; + p1 = !(id1 ^ id3 ^ id4 ^ id5); + pid = (p1 << 7) | (p0 << 6) | id; + return pid; +} + +static uint8_t hpm_uart_lin_calculate_checksum(uint8_t id, uint8_t *data, uint8_t length, bool enhanced_checksum) +{ + assert(length <= 8U); + uint8_t checksum = 0; + uint16_t temp; + for (uint8_t i = 0; i < length; i++) { + temp = checksum + data[i]; + checksum += data[i] + (temp >> 8U); + } + + if (enhanced_checksum) { + temp = checksum + id; + checksum += id + (temp >> 8U); + } + + checksum = ~checksum; + return checksum; +} + +static bool hpm_uart_lin_check_checksum(uint8_t id, uint8_t *data, uint8_t length, bool enhanced_checksum, uint8_t checksum) +{ + uint8_t cal_checksum; + cal_checksum = hpm_uart_lin_calculate_checksum(id, data, length, enhanced_checksum); + + if (cal_checksum != checksum) { + return false; + } + return true; +} + + +static void hpm_uart_lin_send_break(UART_Type *ptr, uart_lin_master_pin_ctrl_t *pin_ctrl) +{ + assert(pin_ctrl->baudrate <= 20000); + + uint32_t bit_period_us = 1000000 / pin_ctrl->baudrate; + uint32_t break_period_us = bit_period_us * HPM_UART_LIN_BREAK_LENGTH; + pin_ctrl->config_uart_pin_as_gpio(ptr); + gpio_set_pin_output(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin); + gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 0); + pin_ctrl->delay_us(break_period_us); + gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 1); + pin_ctrl->delay_us(bit_period_us); + pin_ctrl->config_uart_pin(ptr); +} + +static void hpm_uart_lin_send_sync(UART_Type *ptr) +{ + uart_write_byte(ptr, 0x55); /* sync phase */ +} + +uart_lin_stat_t hpm_uart_lin_master_send_frame(uart_lin_master_config_t *config) +{ + uint32_t retry; + UART_Type *ptr = config->ptr; + uart_lin_data_t data = config->data; + uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); + uint8_t checksum = hpm_uart_lin_calculate_checksum(pid, data.buff, data.length, data.enhance_checksum); + uint8_t send_data[11] = {0}; /* max 8 data bytes + 1 byte 0x55 + 1 byte pid + 1byte checksum */ + uint8_t length = data.length + 3; + + assert(data.length > 0); + + /* 0x55 - pid - data - checksum */ + send_data[0] = 0x55; + send_data[1] = pid; + memcpy(&send_data[2], data.buff, data.length); + send_data[data.length + 2] = checksum; + + hpm_uart_lin_send_break(ptr, &(config->pin_ctrl)); + + for (uint8_t i = 0; i < length; i++) { + retry = 0; + while (!uart_check_status(ptr, uart_stat_tx_slot_avail)) { + if (retry > HPM_UART_LIN_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_UART_LIN_RETRY_COUNT) { + return uart_lin_timeout; + } + + uart_write_byte(ptr, send_data[i]); + } + + return uart_lin_success; +} + + +uart_lin_stat_t hpm_uart_lin_master_receive_frame(uart_lin_master_config_t *config) +{ + uint32_t retry = 0; + UART_Type *ptr = config->ptr; + uart_lin_data_t data = config->data; + uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); + uint8_t checksum; + uint8_t *buff = data.buff; + + assert(data.length > 0); + + /* clear data in rx fifo */ + uart_clear_rx_fifo(ptr); + + hpm_uart_lin_send_break(ptr, &(config->pin_ctrl)); + + hpm_uart_lin_send_sync(ptr); + + uart_write_byte(ptr, pid); + + /* wait for send 0x55 and pid */ + while (!uart_check_status(ptr, uart_stat_tx_slot_avail)) { + if (retry > HPM_UART_LIN_RETRY_COUNT * 2) { + break; + } + retry++; + } + + if (retry > HPM_UART_LIN_RETRY_COUNT * 2) { + return uart_lin_timeout; + } + + /* wait for receive complete */ + for (uint8_t i = 0; i < data.length + 3; i++) { + retry = 0; + while (!uart_check_status(ptr, uart_stat_data_ready)) { + if (retry > HPM_UART_LIN_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_UART_LIN_RETRY_COUNT) { + return uart_lin_timeout; + } + + if (i < 2) { + uart_read_byte(ptr); + } else if (i < data.length + 2) { + *(buff++) = uart_read_byte(ptr); + } else { + checksum = uart_read_byte(ptr); + } + } + + if (!hpm_uart_lin_check_checksum(pid, data.buff, data.length, data.enhance_checksum, checksum)) { + return uart_lin_checksum_error; + } + + return uart_lin_success; +} + +/* generate break with gpio then write 0x55 and pid into uart tx fifo */ +void hpm_uart_lin_master_send_head(uart_lin_master_config_t *config) +{ + UART_Type *ptr = config->ptr; + uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); + + /* clear data in rx fifo */ + uart_clear_rx_fifo(ptr); + + hpm_uart_lin_send_break(ptr, &(config->pin_ctrl)); + + hpm_uart_lin_send_sync(ptr); + + uart_write_byte(ptr, pid); +} + +/* write data into uart tx fifo including data and checksum */ +void hpm_uart_lin_master_send_data(uart_lin_master_config_t *config) +{ + UART_Type *ptr = config->ptr; + uart_lin_data_t data = config->data; + + assert(data.length > 0); + + uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); + uint8_t checksum = hpm_uart_lin_calculate_checksum(pid, data.buff, data.length, data.enhance_checksum); + + for (uint8_t i = 0; i < data.length; i++) { + uart_write_byte(ptr, *(data.buff++)); + } + + uart_write_byte(ptr, checksum); +} + +/* call this function in rx timeout isr */ +/* read data from uart rx fifo */ +uart_lin_stat_t hpm_uart_lin_master_receive_data(uart_lin_master_config_t *config) +{ + UART_Type *ptr = config->ptr; + uart_lin_data_t data = config->data; + uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); + uint8_t checksum; + uint8_t index = 0; + uint8_t *buff = data.buff; + + assert(data.length > 0); + + while (uart_check_status(ptr, uart_stat_data_ready)) { + if (index >= data.length + 3) { + break; + } + if (index < 2) { + uart_read_byte(ptr); /* read 0x55 and pid */ + } else if (index < data.length + 2) { + *(buff++) = uart_read_byte(ptr); + } else { + checksum = uart_read_byte(ptr); + } + index++; + } + + if (index != data.length + 3) { + return uart_lin_frame_error; + } + + if (!hpm_uart_lin_check_checksum(pid, data.buff, data.length, data.enhance_checksum, checksum)) { + return uart_lin_checksum_error; + } + + return uart_lin_success; +} + +/* write data into uart tx fifo including data and checksum */ +void hpm_uart_lin_slave_send_data(uart_lin_slave_config_t *config) +{ + UART_Type *ptr = config->ptr; + uart_lin_data_t data = config->data; + + assert(data.length > 0); + + uint8_t checksum = hpm_uart_lin_calculate_checksum(config->pid, data.buff, data.length, data.enhance_checksum); + + for (uint8_t i = 0; i < data.length; i++) { + uart_write_byte(ptr, *(data.buff++)); + } + + uart_write_byte(ptr, checksum); +} + +/* read data and checksum */ +uart_lin_stat_t hpm_uart_lin_slave_receive_data(uart_lin_slave_config_t *config) +{ + UART_Type *ptr = config->ptr; + uart_lin_data_t data = config->data; + + assert(data.length > 0); + + uint8_t index = 0; + uint8_t checksum = 0; + + /* receive data and checksum */ + while (uart_check_status(ptr, uart_stat_data_ready)) { + if (index == data.length) { + checksum = uart_read_byte(ptr); + break; + } + *(data.buff + index++) = uart_read_byte(ptr); + } + + if (index != data.length) { + return uart_lin_frame_error; + } + + if (!hpm_uart_lin_check_checksum(config->pid, data.buff, data.length, data.enhance_checksum, checksum)) { + return uart_lin_checksum_error; + } + + return uart_lin_success; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h new file mode 100644 index 0000000000..812aabef8d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef UART_LIN_H +#define UART_LIN_H + +#include "hpm_clock_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_uart_drv.h" + +/** + * + * @brief UART Lin component APIs + * @defgroup uart_lin_interface UART component APIs + * @ingroup io_interfaces + * @{ + */ + +typedef struct uart_lin_pin { + GPIO_Type *ptr; + uint32_t baudrate; + void (*config_uart_pin)(UART_Type *ptr); + void (*config_uart_pin_as_gpio)(UART_Type *ptr); + void (*delay_us)(uint32_t us); + uint8_t tx_port; + uint8_t tx_pin; +} uart_lin_master_pin_ctrl_t; + +typedef struct { + uint8_t *buff; + uint8_t length; + bool enhance_checksum; +} uart_lin_data_t; + +typedef enum { + uart_lin_success = 0, + uart_lin_fail = 1, + uart_lin_invalid_argument = 2, + uart_lin_timeout = 3, + uart_lin_id_parity_error = 4, + uart_lin_checksum_error = 5, + uart_lin_frame_error = 6, /*active = 1; p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; - if (data_ptr != NULL) - { + if (data_ptr != NULL) { p_qtd->buffer[0] = (uint32_t)data_ptr; - for(uint8_t i = 1; i < USB_SOC_DCD_QHD_BUFFER_COUNT; i++) - { + for (uint8_t i = 1; i < USB_SOC_DCD_QHD_BUFFER_COUNT; i++) { p_qtd->buffer[i] |= ((p_qtd->buffer[i-1]) & 0xFFFFF000UL) + 4096U; } } } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Device API - *---------------------------------------------------------------------*/ -dcd_qhd_t* usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx) + *--------------------------------------------------------------------- + */ +dcd_qhd_t *usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx) { return &handle->dcd_data->qhd[ep_idx]; } -dcd_qtd_t* usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx) +dcd_qtd_t *usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx) { return &handle->dcd_data->qtd[ep_idx]; } @@ -185,9 +185,10 @@ void usb_device_clear_setup_status(usb_device_handle_t *handle, uint32_t mask) usb_dcd_clear_edpt_setup_status(handle->regs, mask); } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Endpoint API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *config) { uint8_t const epnum = config->ep_addr & 0x0f; @@ -196,10 +197,6 @@ bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *co dcd_qhd_t *p_qhd; - if (config->xfer == usb_xfer_isochronous) { - return false; - } - /* Must not exceed max endpoint number */ if (epnum >= USB_SOC_DCD_MAX_ENDPOINT_COUNT) { return false; @@ -223,15 +220,15 @@ bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t uint8_t const epnum = ep_addr & 0x0f; uint8_t const dir = (ep_addr & 0x80) >> 7; uint8_t const ep_idx = 2 * epnum + dir; - dcd_qhd_t * p_qhd; - dcd_qtd_t * p_qtd; + dcd_qhd_t *p_qhd; + dcd_qtd_t *p_qtd; - if (epnum == 0) - { + if (epnum == 0) { /* follows UM Setup packet handling using setup lockout mechanism * wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out */ - while(usb_dcd_get_edpt_setup_status(handle->regs) & HPM_BITSMASK(1, 0)) {} + while (usb_dcd_get_edpt_setup_status(handle->regs) & HPM_BITSMASK(1, 0)) { + } } p_qhd = &handle->dcd_data->qhd[ep_idx]; @@ -246,6 +243,9 @@ bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t p_qtd->int_on_complete = true; p_qhd->qtd_overlay.next = core_local_mem_to_sys_address(0, (uint32_t) p_qtd); /* link qtd to qhd */ + if (usb_dcd_edpt_get_type(handle->regs, ep_addr) == usb_xfer_isochronous) { + p_qhd->iso_mult = 1; + } usb_dcd_edpt_xfer(handle->regs, ep_idx); return true; @@ -273,4 +273,4 @@ void usb_device_edpt_close_all(usb_device_handle_t *handle) for (i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { usb_device_edpt_close(handle, i); } -} \ No newline at end of file +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h index 0bb9bc568f..a78e7d51d7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,18 +8,21 @@ #ifndef HPM_USB_DEVICE_H #define HPM_USB_DEVICE_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_usb_drv.h" #include "hpm_soc_feature.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macro Constant Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macro Typedef Declaration - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /* Queue Transfer Descriptor */ typedef struct { @@ -27,18 +30,18 @@ typedef struct { volatile uint32_t next; /* Next link pointer This field contains the physical memory address of the next dTD to be processed */ /* Word 1: qTQ Token */ - volatile uint32_t : 3 ; - volatile uint32_t xact_err : 1 ; - volatile uint32_t : 1 ; - volatile uint32_t buffer_err : 1 ; - volatile uint32_t halted : 1 ; - volatile uint32_t active : 1 ; - volatile uint32_t : 2 ; + volatile uint32_t : 3; + volatile uint32_t xact_err : 1; + volatile uint32_t : 1; + volatile uint32_t buffer_err : 1; + volatile uint32_t halted : 1; + volatile uint32_t active : 1; + volatile uint32_t : 2; volatile uint32_t iso_mult_override : 2 ; /* This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. */ - volatile uint32_t : 3 ; - volatile uint32_t int_on_complete : 1 ; - volatile uint32_t total_bytes : 15 ; - volatile uint32_t : 0 ; + volatile uint32_t : 3; + volatile uint32_t int_on_complete : 1; + volatile uint32_t total_bytes : 15; + volatile uint32_t : 0; /* Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ volatile uint32_t buffer[USB_SOC_DCD_QHD_BUFFER_COUNT]; @@ -55,10 +58,10 @@ typedef struct { volatile uint32_t : 15 ; /* Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. */ volatile uint32_t int_on_setup : 1 ; /* Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. */ volatile uint32_t max_packet_size : 11 ; /* This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) */ - volatile uint32_t : 2 ; + volatile uint32_t : 2; volatile uint32_t zero_length_termination : 1 ; /* This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. */ - volatile uint32_t iso_mult : 2 ; - volatile uint32_t : 0 ; + volatile uint32_t iso_mult : 2; + volatile uint32_t : 0; /* Word 1: Current qTD Pointer */ volatile uint32_t qtd_addr; @@ -69,10 +72,11 @@ typedef struct { /* Word 10-11: Setup request (control OUT only) */ volatile usb_control_request_t setup_request; - /*--------------------------------------------------------------------* + /*-------------------------------------------------------------------- * Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes * thus there are 16 bytes padding free that we can make use of. - *--------------------------------------------------------------------*/ + *-------------------------------------------------------------------- + */ volatile uint8_t reserved[16]; } dcd_qhd_t; @@ -90,14 +94,15 @@ typedef struct { extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Function Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /* Get a qhd of the specifed endpoint */ -dcd_qhd_t* usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx); +dcd_qhd_t *usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx); /* Get a qtd of the specifed endpoint */ -dcd_qtd_t* usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx); +dcd_qtd_t *usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx); /* USB bus reset */ void usb_device_bus_reset(usb_device_handle_t *handle, uint16_t ep0_max_packet_size); @@ -165,4 +170,4 @@ void usb_device_clear_setup_status(usb_device_handle_t *handle, uint32_t mask); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_USB_DEVICE_H */ \ No newline at end of file +#endif /* HPM_USB_DEVICE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c index 7a4637558a..2b661df2d7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c @@ -1,36 +1,46 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_usb_host.h" #include "hpm_misc.h" #include "hpm_common.h" #include "board.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macros - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ + #define USB_QHD_TYP_SHIFT (1U) + #define USB_PERIOD_1MS (1U) #define USB_PERIOD_2MS (2U) #define USB_PERIOD_4MS (4U) #define USB_PERIOD_8MS (8U) + #define USB_DEFAULT_ADDR (0U) #define USB_HIGH_SPPED_INTERVAL_MAX (16) +#define USB_SETUP_PACKET_LEN (8U) -/* log2 of a value */ +#define USB_BIN8(x) ((uint8_t) (0b##x)) +#define USB_BIN16(b1, b2) ((uint16_t) (0b##b1##b2)) +#define USB_BIN32(b1, b2, b3, b4) ((uint32_t) (0b##b1##b2##b3##b4)) + +/* helper functions */ static uint8_t usb_log2(uint32_t value) { uint8_t result = 0; while (value >>= 1) { - result++; + result++; } return result; @@ -45,11 +55,11 @@ static void usb_host_list_insert(hcd_link_t *current, hcd_link_t *new, uint8_t n current->address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)new) | (new_type << USB_QHD_TYP_SHIFT); } -static void usb_host_list_remove_qhd_by_addr(hcd_link_t* list_head, uint8_t dev_addr) +static void usb_host_list_remove_qhd_by_addr(hcd_link_t *list_head, uint8_t dev_addr) { hcd_qhd_t *qhd; - for(hcd_link_t* prev = list_head; + for (hcd_link_t *prev = list_head; !prev->terminate && (sys_address_to_core_local_mem(USB_HOST_MCU_CORE, usb_host_align32(prev->address)) != (uint32_t)list_head); prev = (hcd_link_t *)sys_address_to_core_local_mem(USB_HOST_MCU_CORE, (uint32_t)usb_host_list_next(prev))) { @@ -75,27 +85,27 @@ static void usb_host_list_remove_qhd_by_addr(hcd_link_t* list_head, uint8_t dev_ } } -hcd_link_t* usb_host_list_next(hcd_link_t *p_link_pointer) +hcd_link_t *usb_host_list_next(hcd_link_t *p_link_pointer) { - return (hcd_link_t*)usb_host_align32(p_link_pointer->address); + return (hcd_link_t *)usb_host_align32(p_link_pointer->address); } /*************************************************************/ /* qhd functions */ /*************************************************************/ -static hcd_qhd_t* usb_host_qhd_control(usb_host_handle_t *handle, uint8_t dev_addr) +static hcd_qhd_t *usb_host_qhd_control(usb_host_handle_t *handle, uint8_t dev_addr) { return &handle->hcd_data->control[dev_addr].qhd; } -hcd_qhd_t* usb_host_qhd_next(hcd_qhd_t const * p_qhd) +hcd_qhd_t *usb_host_qhd_next(hcd_qhd_t const *p_qhd) { - return (hcd_qhd_t*)usb_host_align32(p_qhd->next.address); + return (hcd_qhd_t *)usb_host_align32(p_qhd->next.address); } -static hcd_qhd_t* usb_host_qhd_find_free(usb_host_handle_t *handle) +static hcd_qhd_t *usb_host_qhd_find_free(usb_host_handle_t *handle) { - for (uint32_t i = 0; i < USB_SOC_HCD_MAX_ENDPOINT_COUNT; i++) { + for (uint32_t i = 0; i < USB_HCD_MAX_QHD_COUNT; i++) { if (!handle->hcd_data->qhd_pool[i].used) { return &handle->hcd_data->qhd_pool[i]; } @@ -104,21 +114,21 @@ static hcd_qhd_t* usb_host_qhd_find_free(usb_host_handle_t *handle) return NULL; } -static hcd_qhd_t* usb_host_qhd_get_from_addr(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) +static hcd_qhd_t *usb_host_qhd_get_from_addr(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) { - hcd_qhd_t* qhd_pool = handle->hcd_data->qhd_pool; + hcd_qhd_t *qhd_pool = handle->hcd_data->qhd_pool; - for(uint32_t i = 0; i < USB_SOC_HCD_MAX_ENDPOINT_COUNT; i++) { + for (uint32_t i = 0; i < USB_HCD_MAX_QHD_COUNT; i++) { if ((qhd_pool[i].dev_addr == dev_addr) && - ep_addr == usb_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid)) { - return &qhd_pool[i]; + ep_addr == usb_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid)) { + return &qhd_pool[i]; } } return NULL; } -static bool usb_host_qhd_init(usb_host_handle_t *handle, hcd_qhd_t *p_qhd, uint8_t dev_addr, usb_desc_endpoint_t const * ep_desc) +static bool usb_host_qhd_init(usb_host_handle_t *handle, hcd_qhd_t *p_qhd, uint8_t dev_addr, usb_desc_endpoint_t const *ep_desc) { uint8_t const xfer_type = ep_desc->bmAttributes.xfer; uint8_t const interval = ep_desc->bInterval; @@ -146,8 +156,8 @@ static bool usb_host_qhd_init(usb_host_handle_t *handle, hcd_qhd_t *p_qhd, uint8 if (interval < 4) { /* sub millisecond interval */ p_qhd->interval_ms = 0; - p_qhd->int_smask = (interval == 1) ? USB_HOST_BIN8(11111111) : - (interval == 2) ? USB_HOST_BIN8(10101010) : USB_HOST_BIN8(01000100); + p_qhd->int_smask = (interval == 1) ? USB_BIN8(11111111) : + (interval == 2) ? USB_BIN8(10101010) : USB_BIN8(01000100); } else { p_qhd->interval_ms = (uint8_t)MIN(1 << (interval - 4), 255); p_qhd->int_smask = HPM_BITSMASK(1, interval % 8); @@ -159,7 +169,7 @@ static bool usb_host_qhd_init(usb_host_handle_t *handle, hcd_qhd_t *p_qhd, uint8 /* Full/Low:(EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes */ p_qhd->int_smask = 0x01; - p_qhd->fl_int_cmask = USB_HOST_BIN8(11100); + p_qhd->fl_int_cmask = USB_BIN8(11100); p_qhd->interval_ms = interval; } } else { @@ -190,28 +200,28 @@ static bool usb_host_qhd_init(usb_host_handle_t *handle, hcd_qhd_t *p_qhd, uint8 return true; } -hcd_qhd_t* usb_host_qhd_async_head(usb_host_handle_t *handle) +hcd_qhd_t *usb_host_qhd_async_head(usb_host_handle_t *handle) { /* control qhd of dev0 is used as async head */ return usb_host_qhd_control(handle, 0); } -bool usb_host_qhd_has_xact_error(hcd_qhd_t * p_qhd) +bool usb_host_qhd_has_xact_error(hcd_qhd_t *p_qhd) { return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err); } -hcd_link_t* usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms) +hcd_link_t *usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms) { - return (hcd_link_t*)&handle->hcd_data->period_head_arr[usb_log2(MIN(USB_HOST_FRAMELIST_SIZE, interval_ms))]; + return (hcd_link_t *)&handle->hcd_data->period_head_arr[usb_log2(MIN(USB_HOST_FRAMELIST_SIZE, interval_ms))]; } /*************************************************************/ /* qtd functions */ /*************************************************************/ -static hcd_qtd_t* usb_host_qtd_find_free(usb_host_handle_t *handle) +static hcd_qtd_t *usb_host_qtd_find_free(usb_host_handle_t *handle) { - for (uint32_t i = 0; i < USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT; i++) { + for (uint32_t i = 0; i < USB_HCD_MAX_QTD_COUNT; i++) { if (!handle->hcd_data->qtd_pool[i].used) { return &handle->hcd_data->qtd_pool[i]; } @@ -220,9 +230,9 @@ static hcd_qtd_t* usb_host_qtd_find_free(usb_host_handle_t *handle) return NULL; } -static hcd_qtd_t* usb_host_qtd_next(hcd_qtd_t const * p_qtd) +static hcd_qtd_t *usb_host_qtd_next(hcd_qtd_t const *p_qtd) { - return (hcd_qtd_t*)usb_host_align32(p_qtd->next.address); + return (hcd_qtd_t *)usb_host_align32(p_qtd->next.address); } static void usb_host_qtd_insert_to_qhd(hcd_qhd_t *p_qhd, hcd_qtd_t *p_qtd_new) @@ -235,7 +245,7 @@ static void usb_host_qtd_insert_to_qhd(hcd_qhd_t *p_qhd, hcd_qtd_t *p_qtd_new) } } -static void usb_host_qtd_init(hcd_qtd_t* p_qtd, void* buffer, uint16_t total_bytes) +static void usb_host_qtd_init(hcd_qtd_t *p_qtd, void *buffer, uint16_t total_bytes) { memset(p_qtd, 0, sizeof(hcd_qtd_t)); @@ -251,7 +261,7 @@ static void usb_host_qtd_init(hcd_qtd_t* p_qtd, void* buffer, uint16_t total_byt if (buffer != NULL) { p_qtd->buffer[0] = (uint32_t)buffer; - for(uint8_t i = 1; i < USB_SOC_HCD_QTD_BUFFER_COUNT; i++) { + for (uint8_t i = 1; i < USB_SOC_HCD_QTD_BUFFER_COUNT; i++) { p_qtd->buffer[i] |= usb_host_align4k(p_qtd->buffer[i-1]) + 4096UL; } } @@ -266,7 +276,7 @@ void usb_host_qtd_remove_1st_from_qhd(hcd_qhd_t *p_qhd) } } -hcd_qtd_t* usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr) +hcd_qtd_t *usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr) { return &handle->hcd_data->control[dev_addr].qtd; } @@ -292,7 +302,7 @@ static void usb_host_init_periodic_list(usb_host_handle_t *handle) hcd_link_t *period_1ms; /* Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only */ - for(uint32_t i = 0; i < 4; i++) { + for (uint32_t i = 0; i < 4; i++) { handle->hcd_data->period_head_arr[i].int_smask = 1; /* queue head in period list must have non-zero smask */ handle->hcd_data->period_head_arr[i].qtd_overlay.halted = 1; /* dummy node, always inactive */ } @@ -305,20 +315,20 @@ static void usb_host_init_periodic_list(usb_host_handle_t *handle) * 1, 5 --> period_head_arr[2] (4ms) * 3 --> period_head_arr[3] (8ms) */ - for(uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i++) { + for (uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i++) { framelist[i].address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)period_1ms); framelist[i].type = usb_qtype_qhd; } - for(uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i+=2) { + for (uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i += 2) { usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_2MS), usb_qtype_qhd); } - for(uint32_t i = 1; i < USB_HOST_FRAMELIST_SIZE; i+=4) { + for (uint32_t i = 1; i < USB_HOST_FRAMELIST_SIZE; i += 4) { usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_4MS), usb_qtype_qhd); } - for(uint32_t i = 3; i < USB_HOST_FRAMELIST_SIZE; i+=8) { + for (uint32_t i = 3; i < USB_HOST_FRAMELIST_SIZE; i += 8) { usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_8MS), usb_qtype_qhd); } @@ -340,6 +350,8 @@ bool usb_host_init(usb_host_handle_t *handle, uint32_t int_mask, uint16_t framel usb_host_init_async_list(handle); usb_host_init_periodic_list(handle); usb_host_vbus_ctrl(handle); + usb_hcd_run(handle->regs); + usb_hcd_enable_port_power(handle->regs); return true; } @@ -392,26 +404,27 @@ void usb_host_device_close(usb_host_handle_t *handle, uint8_t dev_addr) } /* Remove from async list */ - usb_host_list_remove_qhd_by_addr((hcd_link_t*) usb_host_qhd_async_head(handle), dev_addr); + usb_host_list_remove_qhd_by_addr((hcd_link_t *) usb_host_qhd_async_head(handle), dev_addr); /* Remove from all interval period list */ - for(uint8_t i = 0; i < ARRAY_SIZE(handle->hcd_data->period_head_arr); i++) { - usb_host_list_remove_qhd_by_addr((hcd_link_t*)&handle->hcd_data->period_head_arr[i], dev_addr); + for (uint8_t i = 0; i < ARRAY_SIZE(handle->hcd_data->period_head_arr); i++) { + usb_host_list_remove_qhd_by_addr((hcd_link_t *)&handle->hcd_data->period_head_arr[i], dev_addr); } /* Async doorbell (EHCI for operational details) */ usb_hcd_set_command(handle->regs, USB_USBCMD_IAA_MASK); } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Control Pipe API - *---------------------------------------------------------------------*/ -bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) + *--------------------------------------------------------------------- + */ +bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { uint8_t const epnum = usb_edpt_number(ep_addr); uint8_t const dir = usb_edpt_dir(ep_addr); - hcd_qhd_t* qhd; - hcd_qtd_t* qtd; + hcd_qhd_t *qhd; + hcd_qtd_t *qtd; hcd_qhd_t *p_qhd; hcd_qtd_t *p_qtd; @@ -464,8 +477,8 @@ bool usb_host_setup_send(usb_host_handle_t *handle, uint8_t dev_addr, const uint { uint32_t *p = NULL; - hcd_qhd_t* qhd = &handle->hcd_data->control[dev_addr].qhd; - hcd_qtd_t* td = &handle->hcd_data->control[dev_addr].qtd; + hcd_qhd_t *qhd = &handle->hcd_data->control[dev_addr].qhd; + hcd_qtd_t *td = &handle->hcd_data->control[dev_addr].qtd; if (setup_packet != NULL) { p = (uint32_t *)core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)setup_packet); @@ -486,7 +499,7 @@ bool usb_host_setup_send(usb_host_handle_t *handle, uint8_t dev_addr, const uint return true; } -bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const * ep_desc) +bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const *ep_desc) { hcd_qhd_t *p_qhd = NULL; hcd_link_t *list_head = NULL; @@ -496,7 +509,7 @@ bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_en } /* Prepare Queue Head */ - if ( ep_desc->bEndpointAddress == 0 ) { + if (ep_desc->bEndpointAddress == 0) { p_qhd = usb_host_qhd_control(handle, dev_addr); } else { p_qhd = usb_host_qhd_find_free(handle); @@ -506,24 +519,24 @@ bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_en usb_host_qhd_init(handle, p_qhd, dev_addr, ep_desc); switch (ep_desc->bmAttributes.xfer) { - case usb_xfer_control: - case usb_xfer_bulk: - list_head = (hcd_link_t*)usb_host_qhd_async_head(handle); /* control of dev0 is always present as async head */ - break; + case usb_xfer_control: + case usb_xfer_bulk: + list_head = (hcd_link_t *)usb_host_qhd_async_head(handle); /* control of dev0 is always present as async head */ + break; - case usb_xfer_interrupt: - list_head = usb_host_get_period_head(handle, p_qhd->interval_ms); - break; + case usb_xfer_interrupt: + list_head = usb_host_get_period_head(handle, p_qhd->interval_ms); + break; - case usb_xfer_isochronous: - break; + case usb_xfer_isochronous: + break; - default: - break; + default: + break; } /* Insert to list */ - usb_host_list_insert(list_head, (hcd_link_t*)p_qhd, usb_qtype_qhd); + usb_host_list_insert(list_head, (hcd_link_t *)p_qhd, usb_qtype_qhd); return true; } @@ -587,4 +600,4 @@ bool usb_host_edpt_clear_stall(usb_host_handle_t *handle, uint8_t dev_addr, uint p_qhd->qtd_overlay.halted = 0; return true; -} \ No newline at end of file +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h index db6b81329f..91dd5e4fa5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,47 +8,60 @@ #ifndef HPM_USB_HOST_H #define HPM_USB_HOST_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_usb_drv.h" #include "hpm_common.h" #include "hpm_soc_feature.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macros - *---------------------------------------------------------------------*/ -#define USB_HOST_BIN8(x) ((uint8_t) (0b##x)) -#define USB_BIN16(b1, b2) ((uint16_t) (0b##b1##b2)) -#define USB_BIN32(b1, b2, b3, b4) ((uint32_t) (0b##b1##b2##b3##b4)) + *--------------------------------------------------------------------- + */ -#define USB_HCD_PERIODIC_ARR_COUNT (4U) -#define USB_HCD_MAX_CONNECTED_DEVICES (5U) -#define USB_SETUP_PACKET_LEN (8U) -/*---------------------------------------------------------------------* + +#ifndef USB_HCD_PERIODIC_ARR_COUNT +#define USB_HCD_PERIODIC_ARR_COUNT (4U) +#endif + +#ifndef USB_HCD_MAX_CONNECTED_DEVICES +#define USB_HCD_MAX_CONNECTED_DEVICES (5U) +#endif + +#ifndef USB_HCD_MAX_QHD_COUNT +#define USB_HCD_MAX_QHD_COUNT (USB_HCD_MAX_CONNECTED_DEVICES * 16U * 2U) +#endif + +#ifndef USB_HCD_MAX_QTD_COUNT +#define USB_HCD_MAX_QTD_COUNT (USB_HCD_MAX_QHD_COUNT * 2U) +#endif +/*--------------------------------------------------------------------- * Enum Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef enum { usb_max_itd = 4, usb_max_sitd = 16 } usb_max_xtd_t; typedef enum { - usb_qtype_itd = 0 , + usb_qtype_itd = 0, usb_qtype_qhd, usb_qtype_sitd, usb_qtype_fstn } usb_qtype_t; typedef enum { - usb_pid_out = 0 , - usb_pid_in , + usb_pid_out = 0, + usb_pid_in, usb_pid_setup } usb_pid_t; typedef enum { usb_speed_full = 0, - usb_speed_low , + usb_speed_low, usb_speed_high, usb_speed_invalid = 0xff, } usb_speed_t; @@ -86,8 +99,7 @@ typedef union { /* Queue Element Transfer Descriptor */ /* Qtd is used to declare overlay in hcd_qhd_t */ -typedef struct -{ +typedef struct { /* Word 0: Next QTD Pointer */ volatile hcd_link_t next; @@ -123,8 +135,7 @@ typedef struct } hcd_qtd_t; /* Queue Head */ -typedef struct -{ +typedef struct { /* Word 0: Next QHD */ hcd_link_t next; @@ -155,7 +166,8 @@ typedef struct /*-------------------------------------------------------------------- * Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes * thus there are 16 bytes padding free that we can make use of. - *--------------------------------------------------------------------*/ + *-------------------------------------------------------------------- + */ uint8_t used; uint8_t removing; /* removed from async list, waiting for async advance */ uint8_t pid; @@ -168,8 +180,7 @@ typedef struct hcd_qtd_t * volatile p_qtd_list_tail; /* tail of the scheduled TD list */ } hcd_qhd_t; -typedef struct -{ +typedef struct { hcd_link_t period_framelist[USB_HOST_FRAMELIST_SIZE]; /* for ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist) @@ -183,8 +194,8 @@ typedef struct hcd_qtd_t qtd; } control[USB_HCD_MAX_CONNECTED_DEVICES + 1]; - hcd_qhd_t qhd_pool[USB_SOC_HCD_MAX_ENDPOINT_COUNT]; - hcd_qtd_t qtd_pool[USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT]; + hcd_qhd_t qhd_pool[USB_HCD_MAX_QHD_COUNT]; + hcd_qtd_t qtd_pool[USB_HCD_MAX_QTD_COUNT]; uint32_t uframe_number; } hcd_data_t; @@ -202,9 +213,9 @@ typedef struct { /* USB Endpoint Descriptor */ typedef struct __attribute__ ((packed)) { - uint8_t bLength ; - uint8_t bDescriptorType ; - uint8_t bEndpointAddress ; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; struct __attribute__ ((packed)) { uint8_t xfer : 2; @@ -244,19 +255,19 @@ static inline uint8_t usb_edpt_addr(uint8_t num, uint8_t dir) return (uint8_t)(num | (dir ? usb_dir_in_mask : 0)); } -static inline uint32_t usb_host_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); } -static inline uint32_t usb_host_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); } -static inline uint32_t usb_host_align4k (uint32_t value) { return (value & 0xFFFFF000UL); } +static inline uint32_t usb_host_align16(uint32_t value) { return (value & 0xFFFFFFF0UL); } +static inline uint32_t usb_host_align32(uint32_t value) { return (value & 0xFFFFFFE0UL); } +static inline uint32_t usb_host_align4k(uint32_t value) { return (value & 0xFFFFF000UL); } static inline uint32_t usb_host_offset4k(uint32_t value) { return (value & 0xFFFUL); } -bool usb_host_qhd_has_xact_error (hcd_qhd_t * p_qhd); -bool usb_host_qhd_has_xact_error(hcd_qhd_t * p_qhd); +bool usb_host_qhd_has_xact_error(hcd_qhd_t *p_qhd); +bool usb_host_qhd_has_xact_error(hcd_qhd_t *p_qhd); void usb_host_qtd_remove_1st_from_qhd(hcd_qhd_t *p_qhd); -hcd_link_t* usb_host_list_next(hcd_link_t *p_link_pointer); -hcd_link_t* usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms); -hcd_qhd_t* usb_host_qhd_async_head(usb_host_handle_t *handle); -hcd_qhd_t* usb_host_qhd_next(hcd_qhd_t const * p_qhd); -hcd_qtd_t* usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr); +hcd_link_t *usb_host_list_next(hcd_link_t *p_link_pointer); +hcd_link_t *usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms); +hcd_qhd_t *usb_host_qhd_async_head(usb_host_handle_t *handle); +hcd_qhd_t *usb_host_qhd_next(hcd_qhd_t const *p_qhd); +hcd_qtd_t *usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr); uint32_t usb_host_uframe_number(usb_host_handle_t *handle); uint32_t usb_host_status_flags(usb_host_handle_t *handle); uint32_t usb_host_interrupts(usb_host_handle_t *handle); @@ -267,9 +278,9 @@ bool usb_host_init(usb_host_handle_t *handle, uint32_t int_mask, uint16_t framel bool usb_host_get_port_ccs(usb_host_handle_t *handle); bool usb_host_port_csc(usb_host_handle_t *handle); void usb_host_device_close(usb_host_handle_t *handle, uint8_t dev_addr); -bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); +bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen); bool usb_host_setup_send(usb_host_handle_t *handle, uint8_t dev_addr, const uint8_t *setup_packet); -bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const * ep_desc); +bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const *ep_desc); bool usb_host_pipe_queue_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes); bool usb_host_pipe_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete); bool usb_host_edpt_busy(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr); @@ -279,4 +290,4 @@ bool usb_host_edpt_clear_stall(usb_host_handle_t *handle, uint8_t dev_addr, uint #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_USB_HOST_H */ \ No newline at end of file +#endif /* HPM_USB_HOST_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h index c8df2f8399..39e9e48c79 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h index a9a7c5e22d..564cdd47b7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -23,11 +23,10 @@ #define ADC12_IS_SIGNAL_TYPE_INVALID(TYPE) (TYPE > (uint32_t)adc12_sample_signal_count) /** @brief Define ADC12 validity check for the channel number */ -#define ADC12_IS_CHANNEL_INVALID(PTR, CH) ((CH > ADC12_SOC_MAX_CH_NUM && CH != ADC12_SOC_TEMP_CH_NUM) || \ - ((uint32_t)PTR == ADC12_SOC_INVALID_TEMP_BASE && CH == ADC12_SOC_TEMP_CH_NUM)) +#define ADC12_IS_CHANNEL_INVALID(CH) (CH > ADC12_SOC_MAX_CH_NUM) /** @brief Define ADC12 validity check for the trigger number */ -#define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC12_SOC_MAX_TRIG_CH_NUM) +#define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC_SOC_MAX_TRIG_CH_NUM) /** @brief Define ADC12 validity check for the trigger length */ #define ADC12_IS_TRIG_LEN_INVLAID(TRIG_LEN) (TRIG_LEN > ADC_SOC_MAX_TRIG_CH_LEN) @@ -97,12 +96,32 @@ typedef enum { adc12_event_dma_fifo_full = ADC12_INT_STS_DMA_FIFO_FULL_MASK } adc12_irq_event_t; +/** @brief Define ADC12 Clock Divider */ +typedef enum { + adc12_clock_divider_1 = 1, + adc12_clock_divider_2, + adc12_clock_divider_3, + adc12_clock_divider_4, + adc12_clock_divider_5, + adc12_clock_divider_6, + adc12_clock_divider_7, + adc12_clock_divider_8, + adc12_clock_divider_9, + adc12_clock_divider_10, + adc12_clock_divider_11, + adc12_clock_divider_12, + adc12_clock_divider_13, + adc12_clock_divider_14, + adc12_clock_divider_15, + adc12_clock_divider_16, +} adc12_clock_divider_t; + /** @brief ADC12 common configuration struct. */ typedef struct { uint8_t res; uint8_t conv_mode; - uint8_t wait_dis; uint32_t adc_clk_div; + bool wait_dis; bool sel_sync_ahb; bool adc_ahb_en; } adc12_config_t; @@ -138,19 +157,18 @@ typedef struct { /** @brief ADC12 DMA configuration struct for the preemption mode. */ typedef struct { - uint32_t :4; - uint32_t result :12; - uint32_t trig_ch :2; - uint32_t :2; - uint32_t trig_index :4; - uint32_t adc_ch :5; - uint32_t :2; - uint32_t cycle_bit :1; + uint32_t :4; + uint32_t result :12; + uint32_t seq_num :2; + uint32_t :2; + uint32_t trig_ch :4; + uint32_t adc_ch :5; + uint32_t :2; + uint32_t cycle_bit :1; } adc12_pmt_dma_data_t; /** @brief ADC12 configuration struct for the period mode. */ typedef struct { - uint32_t clk_src_freq_in_hz; uint8_t ch; uint8_t prescale; uint8_t period_count; @@ -209,7 +227,7 @@ void adc12_get_channel_default_config(adc12_channel_config_t *config); * @param[in] config A pointer to the configuration struct of @ref adc12_config_t. * @return A result of initializing an ADC12 instance. * @retval status_success Initialize an ADC12 instance successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC12 instance unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC12 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config); @@ -219,8 +237,8 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config); * @param[in] ptr An ADC12 peripheral base address. * @param[in] config A pointer to the configuration struct of @ref adc12_channel_config_t. * @return A result of initializing an ADC12 channel. - * @retval status_success Initialize an ADC12 channel successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC12 channel unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Initialize an ADC12 channel successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC12 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config); @@ -230,8 +248,8 @@ hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config); * @param[in] ptr An ADC12 peripheral base address. * @param[in] config A pointer to the configuration struct of @ref adc12_prd_config_t. * @return A result of configuring the the period mode for an ADC12 instance. - * @retval status_success Configure the the period mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Configure the the period mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config); @@ -241,8 +259,8 @@ hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config); * @param[in] ptr An ADC12 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc12_seq_config_t. * @return A result of configuring the the sequence mode for an ADC12 instance. - * @retval status_success Configure the the sequence mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Configure the the sequence mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config); @@ -252,8 +270,8 @@ hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config); * @param[in] ptr An ADC12 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc12_pmt_config_t. * @return A result of configuring the preemption mode for an ADC12 instance. - * @retval status_success Configure the preemption mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Configure the preemption mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config); @@ -288,13 +306,13 @@ static inline void adc12_init_pmt_dma(ADC12_Type *ptr, uint32_t addr) } /** - * @brief Configure the start address of DMA write operation for the preemption mode. + * @brief Configure the start address of DMA write operation for the sequence mode. * * @param[in] ptr An ADC12 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc12_dma_config_t. * @return An implementation result of DMA initializing for the sequence mode - * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success ADC12 initialize in sequence mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument ADC12 initialize in sequence mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. */ hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *config); @@ -318,16 +336,25 @@ static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr) } /** - * @brief Get the setting value of the WAIT_DIS bit. + * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus + * until the ADC has completed its conversion. * * @param[in] ptr An ADC12 peripheral base address. - * @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled. - * @retval true It means that the WAIT_DIS bit is 1. - * @retval false It means that the WAIT_DIS bit is 0. */ -static inline bool adc12_get_wait_dis_status(ADC12_Type *ptr) +static inline void adc12_disable_busywait(ADC12_Type *ptr) { - return ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0); + ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_SET(1); +} + +/** + * @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus + * until the ADC completes the conversion. + * + * @param[in] ptr An ADC12 peripheral base address. + */ +static inline void adc12_enable_busywait(ADC12_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; } /** @@ -395,11 +422,25 @@ static inline void adc12_disable_interrupts(ADC12_Type *ptr, uint32_t mask) */ /** - * @brief Trigger ADC coversions by software + * @brief Trigger ADC conversions by software in sequence mode * * @param[in] ptr An ADC12 peripheral base address. + * @return An implementation result of getting an ADC12 software trigger. + * @retval status_success ADC12 software triggers successfully. Please refer to @ref hpm_stat_t. + * @retval status_fail ADC12 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. */ -void adc12_trigger_seq_by_sw(ADC12_Type *ptr); +hpm_stat_t adc12_trigger_seq_by_sw(ADC12_Type *ptr); + +/** + * @brief Trigger ADC conversions by software in preemption mode + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] trig_ch A trigger channel number(e.g. TRIG0A,TRIG0B,TRIG0C...). + * @return An implementation result of getting an ADC12 software trigger. + * @retval status_success ADC12 software triggers successfully. Please refer to @ref hpm_stat_t. + * @retval status_fail ADC12 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc12_trigger_pmt_by_sw(ADC12_Type *ptr, uint8_t trig_ch); /** * @brief Get the result in oneshot mode. @@ -408,8 +449,8 @@ void adc12_trigger_seq_by_sw(ADC12_Type *ptr); * @param[in] ch An ADC12 peripheral channel. * @param[out] result A pointer to an ADC12 conversion result. * @return An implementation result of getting an ADC12 conversion result in oneshot mode. - * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result); @@ -420,8 +461,8 @@ hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *resul * @param[in] ch An ADC12 peripheral channel. * @param[out] result A pointer to a specified ADC12 conversion result * @return An implementation of getting an ADC12 conversion result in the period mode. - * @retval status_success Get the result of an ADC12 conversion in the period mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC12 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Get the result of an ADC12 conversion in the period mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC12 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result); diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h index bb6f12e508..0870efbf02 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -20,10 +20,14 @@ */ /** @brief Define ADC16 validity check for the channel number */ +#if defined (ADC16_SOC_TEMP_CH_EN) && ADC16_SOC_TEMP_CH_EN #define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM && CH != ADC16_SOC_TEMP_CH_NUM) +#else +#define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM) +#endif /** @brief Define ADC16 validity check for the trigger number */ -#define ADC16_IS_TRIG_CH_INVLAID(CH) (CH > ADC16_SOC_MAX_TRIG_CH_NUM) +#define ADC16_IS_TRIG_CH_INVLAID(CH) (CH > ADC_SOC_MAX_TRIG_CH_NUM) /** @brief Define ADC16 validity check for the trigger length */ #define ADC16_IS_TRIG_LEN_INVLAID(TRIG_LEN) (TRIG_LEN > ADC_SOC_MAX_TRIG_CH_LEN) @@ -37,6 +41,14 @@ /** @brief Define ADC16 validity check for the DMA buffer length in the preemption mode */ #define ADC16_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)) +/** @brief Define ADC16 resolutions. */ +typedef enum { + adc16_res_8_bits = 9, + adc16_res_10_bits = 11, + adc16_res_12_bits = 14, + adc16_res_16_bits = 21 +} adc16_resolution_t; + /** @brief Define ADC16 conversion modes. */ typedef enum { adc16_conv_mode_oneshot = 0, @@ -45,6 +57,26 @@ typedef enum { adc16_conv_mode_preemption } adc16_conversion_mode_t; +/** @brief Define adc16 Clock Divider */ +typedef enum { + adc16_clock_divider_1 = 1, + adc16_clock_divider_2, + adc16_clock_divider_3, + adc16_clock_divider_4, + adc16_clock_divider_5, + adc16_clock_divider_6, + adc16_clock_divider_7, + adc16_clock_divider_8, + adc16_clock_divider_9, + adc16_clock_divider_10, + adc16_clock_divider_11, + adc16_clock_divider_12, + adc16_clock_divider_13, + adc16_clock_divider_14, + adc16_clock_divider_15, + adc16_clock_divider_16, +} adc16_clock_divider_t; + /** @brief Define ADC16 irq events. */ typedef enum { /** This mask indicates that a trigger conversion is complete. */ @@ -80,11 +112,12 @@ typedef enum { /** @brief ADC16 common configuration struct. */ typedef struct { + uint8_t res; uint8_t conv_mode; - uint8_t wait_dis; uint32_t adc_clk_div; uint16_t conv_duration; bool port3_rela_time; + bool wait_dis; bool sel_sync_ahb; bool adc_ahb_en; } adc16_config_t; @@ -118,18 +151,17 @@ typedef struct { /** @brief ADC16 DMA configuration struct for the preemption mode. */ typedef struct { - uint32_t result :16; - uint32_t trig_ch :2; - uint32_t :2; - uint32_t trig_index :4; - uint32_t adc_ch :5; - uint32_t :2; - uint32_t cycle_bit :1; + uint32_t result :16; + uint32_t seq_num :2; + uint32_t :2; + uint32_t trig_ch :4; + uint32_t adc_ch :5; + uint32_t :2; + uint32_t cycle_bit :1; } adc16_pmt_dma_data_t; /** @brief ADC16 configuration struct for the the period mode. */ typedef struct { - uint32_t clk_src_freq_in_hz; uint8_t ch; uint8_t prescale; uint8_t period_count; @@ -199,8 +231,8 @@ hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config); * @param[in] ptr An ADC16 peripheral base address. * @param[in] config A pointer to the configuration struct of @ref adc16_channel_config_t. * @return A result of initializing an ADC16 channel. - * @retval status_success Initialize an ADC16 channel successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC16 channel unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Initialize an ADC16 channel successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC16 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config); @@ -210,8 +242,8 @@ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config); * @param[in] ptr An ADC16 peripheral base address. * @param[in] config A pointer to the configuration struct of @ref adc16_prd_config_t. * @return A result of configuring the the period mode for an ADC16 instance. - * @retval status_success Configure the the period mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Configure the the period mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config); @@ -221,8 +253,8 @@ hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config); * @param[in] ptr An ADC16 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc16_seq_config_t. * @return A result of configuring the sequence mode for an ADC16 instance. - * @retval status_success Configure the sequence mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Configure the sequence mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config); @@ -232,8 +264,8 @@ hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config); * @param[in] ptr An ADC16 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc16_pmt_config_t. * @return A result of configuring the preemption mode for an ADC16 instance. - * @retval status_success Configure the preemption mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Configure the preemption mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config); @@ -283,8 +315,11 @@ static inline void adc16_init_pmt_dma(ADC16_Type *ptr, uint32_t addr) * * @param[in] ptr An ADC16 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc16_dma_config_t. + * @return An implementation result of DMA initializing for the sequence mode + * @retval status_success ADC16 initialize in sequence mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument ADC16 initialize in sequence mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. */ -void adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *config); +hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *config); /** @} */ @@ -306,16 +341,25 @@ static inline uint32_t adc16_get_status_flags(ADC16_Type *ptr) } /** - * @brief Get the setting value of the WAIT_DIS bit. + * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus + * until the ADC has completed its conversion. * * @param[in] ptr An ADC16 peripheral base address. - * @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled. - * @retval true It means that the WAIT_DIS bit is 1. - * @retval false It means that the WAIT_DIS bit is 0. */ -static inline bool adc16_get_wait_dis_status(ADC16_Type *ptr) +static inline void adc16_disable_busywait(ADC16_Type *ptr) { - return ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0); + ptr->BUF_CFG0 |= ADC16_BUF_CFG0_WAIT_DIS_SET(1); +} + +/** + * @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus + * until the ADC completes the conversion. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_enable_busywait(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; } /** @@ -383,11 +427,26 @@ static inline void adc16_disable_interrupts(ADC16_Type *ptr, uint32_t mask) */ /** - * @brief Trigger ADC coversions by software + * @brief Trigger ADC conversions by software in sequence mode * * @param[in] ptr An ADC16 peripheral base address. + * @return An implementation result of getting an ADC16 software trigger. + * @retval status_success ADC16 software triggers successfully. Please refer to @ref hpm_stat_t. + * @retval status_fail ADC16 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. */ -void adc16_trigger_seq_by_sw(ADC16_Type *ptr); +hpm_stat_t adc16_trigger_seq_by_sw(ADC16_Type *ptr); + +/** + * @brief Trigger ADC conversions by software in preemption mode + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] trig_ch A trigger channel number(e.g. TRIG0A,TRIG0B,TRIG0C...). + * @return An implementation result of getting an ADC16 software trigger. + * @retval status_success ADC16 software triggers successfully. Please refer to @ref hpm_stat_t. + * @retval status_fail ADC16 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc16_trigger_pmt_by_sw(ADC16_Type *ptr, uint8_t trig_ch); + /** * @brief Get the result in oneshot mode. @@ -396,8 +455,8 @@ void adc16_trigger_seq_by_sw(ADC16_Type *ptr); * @param[in] ch An ADC16 peripheral channel. * @param[out] result A pointer to an ADC16 conversion result. * @return An implementation result of getting an ADC16 conversion result in oneshot mode. - * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result); @@ -408,11 +467,27 @@ hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *resul * @param[in] ch An ADC16 peripheral channel. * @param[out] result A pointer to a specified ADC16 conversion result * @return An implementation of getting an ADC16 conversion result in the period mode. - * @retval status_success Get the result of an ADC16 conversion in the period mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC16 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + * @retval status_success Get the result of an ADC16 conversion in the period mode successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC16 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. */ hpm_stat_t adc16_get_prd_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result); +#if defined(ADC16_SOC_TEMP_CH_EN) && ADC16_SOC_TEMP_CH_EN +/** + * @brief Enable the temperature sensor + * + * @param[in] ptr An ADC16 peripheral base address. + */ +void adc16_enable_temp_sensor(ADC16_Type *ptr); + +/** + * @brief Disable the temperature sensor + * + * @param[in] ptr An ADC16 peripheral base address. + */ +void adc16_disable_temp_sensor(ADC16_Type *ptr); +#endif + /** @} */ #ifdef __cplusplus @@ -420,4 +495,4 @@ hpm_stat_t adc16_get_prd_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result); #endif /** @} */ -#endif /* HPM_ADC16_DRV_H */ \ No newline at end of file +#endif /* HPM_ADC16_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h index 0bc21c3eca..b95da752a1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h index 3ce4af2461..2319a99693 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h index 66145706b4..490384fba6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h index 9e4899bcaf..a0a5748645 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -34,35 +34,32 @@ #define CAM_SENSOR_BITWIDTH_10BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(1)) /** - * @brief CAM IRQ flag + * @brief CAM IRQ mask */ -#define CAM_IRQ_UNSUPPORTED_CONFIGURATION (CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) -#define CAM_IRQ_HIST_CALCULATION_DONE (CAM_INT_EN_HIST_DONE_INT_EN_MASK) -#define CAM_IRQ_HRESPONSE_ERROR (CAM_INT_EN_HRESP_ERR_EN_MASK) -#define CAM_IRQ_END_OF_FRAME (CAM_INT_EN_EOF_INT_EN_MASK) -#define CAM_IRQ_STAT_FIFO_OVERRUN (CAM_INT_EN_SF_OR_INT_EN_MASK) -#define CAM_IRQ_RX_FIFO_OVERRUN (CAM_INT_EN_RF_OR_INT_EN_MASK) -#define CAM_IRQ_STAT_FIFO_DMA_TRANSFER_DONE (CAM_INT_EN_SFF_DMA_DONE_INT_EN_MASK) -#define CAM_IRQ_FB2_DMA_TRANSFER_DONE (CAM_INT_EN_FB2_DMA_DONE_INT_EN_MASK) -#define CAM_IRQ_FB1_DMA_TRANSFER_DONE (CAM_INT_EN_FB1_DMA_DONE_INT_EN_MASK) -#define CAM_IRQ_START_OF_FRAME (CAM_INT_EN_SOF_INT_EN_MASK) +typedef enum { + cam_irq_unsupported_configuration = CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK, + cam_irq_hist_calculation_done = CAM_INT_EN_HIST_DONE_INT_EN_MASK, + cam_irq_hresponse_error = CAM_INT_EN_HRESP_ERR_EN_MASK, + cam_irq_end_of_frame = CAM_INT_EN_EOF_INT_EN_MASK, + cam_irq_rx_fifo_overrun = CAM_INT_EN_RF_OR_INTEN_MASK, + cam_irq_fb2_dma_transfer_done = CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK, + cam_irq_fb1_dma_transfer_done = CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK, + cam_irq_start_of_frame = CAM_INT_EN_SOF_INT_EN_MASK +} cam_irq_mask_t; /** - * @brief CAM status flag + * @brief CAM status mask */ -#define CAM_STATUS_UNSUPPORTED_CONFIGURATION (CAM_STA_ERR_CL_BWID_CFG_MASK) -#define CAM_STATUS_HIST_CALCULATION_DONE (CAM_STA_HIST_DONE_MASK) -#define CAM_STATUS_STAT_FIFO_OVERRUN (CAM_STA_SF_OR_INT_MASK) -#define CAM_STATUS_RX_FIFO_OVERRUN (CAM_STA_RF_OR_INT_MASK) -#define CAM_STATUS_STAT_FIFO_DMA_TRANSFER_DONE (CAM_STA_DMA_TSF_DONE_SFF_MASK) -#define CAM_STATUS_STAT_FIFO_FULL (CAM_STA_STATFF_INT_MASK) -#define CAM_STATUS_FB2_DMA_TRANSFER_DONE (CAM_STA_DMA_TSF_DONE_FB2_MASK) -#define CAM_STATUS_FB1_DMA_TRANSFER_DONE (CAM_STA_DMA_TSF_DONE_FB1_MASK) -#define CAM_STATUS_RX_FIFO_FULL (CAM_STA_RXFF_INT_MASK) -#define CAM_STATUS_END_OF_FRAME (CAM_STA_EOF_INT_MASK) -#define CAM_STATUS_START_OF_FRAME (CAM_STA_SOF_INT_MASK) -#define CAM_STATUS_HRESPONSE_ERROR (CAM_STA_HRESP_ERR_INT_MASK) -#define CAM_STATUS_DATA_READY (CAM_STA_DRDY_MASK) +typedef enum { + cam_status_unsupported_configuration = CAM_STA_ERR_CL_BWID_CFG_MASK, + cam_status_hist_calculation_done = CAM_STA_HIST_DONE_MASK, + cam_status_rx_fifo_overrun = CAM_STA_RF_OR_INT_MASK, + cam_status_fb2_dma_transfer_done = CAM_STA_DMA_TSF_DONE_FB2_MASK, + cam_status_fb1_dma_transfer_done = CAM_STA_DMA_TSF_DONE_FB1_MASK, + cam_status_end_of_frame = CAM_STA_EOF_INT_MASK, + cam_status_start_of_frame = CAM_STA_SOF_INT_MASK, + cam_status_hresponse_error = CAM_STA_HRESP_ERR_INT_MASK +} cam_status_mask_t; /** * @brief CAM input color format @@ -72,6 +69,8 @@ #define CAM_COLOR_FORMAT_RGB555 (CAM_CR1_COLOR_FORMATS_SET(6)) #define CAM_COLOR_FORMAT_YCBCR422 (CAM_CR1_COLOR_FORMATS_SET(7)) #define CAM_COLOR_FORMAT_YUV444 (CAM_CR1_COLOR_FORMATS_SET(8)) +#define CAM_COLOR_FORMAT_RAW8 (CAM_CR1_COLOR_FORMATS_SET(0xf)) +#define CAM_COLOR_FORMAT_UNSUPPORTED (1) /** * @brief CAM config @@ -85,7 +84,7 @@ typedef struct { bool color_ext; bool data_pack_msb; bool enable_buffer2; - uint8_t data_store_mode; + uint16_t data_store_mode; uint8_t color_format; uint8_t sensor_bitwidth; uint32_t buffer1; @@ -121,6 +120,26 @@ typedef enum { extern "C" { #endif +/** + * @brief cam get pixel format value + * + * @param format display_pixel_format_t + * @return uint32_t cam color format, like CAM_COLOR_FORMAT_RGB565 + */ +static inline uint32_t cam_get_pixel_format(display_pixel_format_t format) +{ + switch (format) { + case display_pixel_format_rgb565: + return CAM_COLOR_FORMAT_RGB565; + case display_pixel_format_ycbcr422: + return CAM_COLOR_FORMAT_YCBCR422; + case display_pixel_format_raw8: + return CAM_COLOR_FORMAT_RAW8; + default: + return CAM_COLOR_FORMAT_UNSUPPORTED; + } +} + /** * @brief CAM set high and low limits of color key * @@ -167,6 +186,8 @@ void cam_start(CAM_Type *ptr); */ void cam_stop(CAM_Type *ptr); +void cam_update_buffer(CAM_Type *ptr, uint32_t buffer); + /** * @brief CAM enable binary output * @@ -235,6 +256,54 @@ static inline void cam_set_input_pixel_byte_order(CAM_Type *ptr, cam_input_pixel ptr->CR2 = (ptr->CR2 & (~CAM_CR2_CLRBITFORMAT_MASK)) | CAM_CR2_CLRBITFORMAT_SET(order); } +/** + * @brief CAM enable irq + * + * @param [in] ptr CAM base address + * @param [in] irq_mask irq mask value + */ +static inline void cam_enable_irq(CAM_Type *ptr, cam_irq_mask_t irq_mask) +{ + ptr->INT_EN |= irq_mask; +} + + +/** + * @brief CAM disable irq + * + * @param [in] ptr CAM base address + * @param [in] irq_mask irq mask value + */ +static inline void cam_disable_irq(CAM_Type *ptr, cam_irq_mask_t irq_mask) +{ + ptr->INT_EN &= ~irq_mask; +} + +/** + * @brief Check CAM status according to the given status mask + * + * @param [in] ptr CAM base address + * @param sta_mask sta_mask refer to cam_status_mask_t + * @retval true if any bit in given mask is set + * @retval false if none of any bit in given mask is set + */ +static inline bool cam_check_status(CAM_Type *ptr, cam_status_mask_t sta_mask) +{ + return ((ptr->STA & sta_mask) != 0U) ? true : false; +} + +/** + * @brief Clear CAM status according to the given status mask + * + * @param [in] ptr CAM base address + * @param sta_mask sta_mask refer to cam_status_mask_t + */ +static inline void cam_clear_status(CAM_Type *ptr, cam_status_mask_t sta_mask) +{ + ptr->STA |= sta_mask; +} + + /** * @} * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h index d0fe79b6a8..4c9c505ece 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,7 +10,7 @@ #include "hpm_common.h" #include "hpm_can_regs.h" - +#include "hpm_soc_feature.h" /** * @brief CAN driver APIs @@ -103,7 +103,7 @@ typedef enum _can_mode { can_mode_loopback_internal, /**< Internal loopback mode */ can_mode_loopback_external, /**< External loopback mode */ can_mode_listen_only, /**< CAN listen mode */ -} can_mode_t; +} can_node_mode_t; /** * @brief CAN bit timing options @@ -239,7 +239,7 @@ typedef struct { }; }; - can_mode_t mode; /**< CAN work mode */ + can_node_mode_t mode; /**< CAN work mode */ bool use_lowlevel_timing_setting; /**< Use low-level timing setting */ bool enable_canfd; /**< Enable CAN FD */ bool enable_self_ack; /**< CAN self-ack flag */ @@ -257,7 +257,7 @@ typedef struct { } can_config_t; -#ifdef __cpluspuls +#ifdef __cplusplus extern "C" { #endif @@ -289,7 +289,7 @@ static inline void can_reset(CAN_Type *base, bool enable) * @arg can_mode_loopback_external external loopback mode * @arg can_mode_listen_only CAN listen-only mode */ -static inline void can_set_mode(CAN_Type *base, can_mode_t mode) +static inline void can_set_node_mode(CAN_Type *base, can_node_mode_t mode) { uint32_t cfg_stat = base->CMD_STA_CMD_CTRL & ~(CAN_CMD_STA_CMD_CTRL_LBME_MASK | CAN_CMD_STA_CMD_CTRL_LBMI_MASK | CAN_CMD_STA_CMD_CTRL_LOM_MASK); if (mode == can_mode_loopback_internal) { @@ -678,7 +678,11 @@ static inline uint8_t can_get_last_arbitration_lost_position(CAN_Type *base) */ static inline void can_set_transmitter_delay_compensation(CAN_Type *base, uint8_t sample_point, bool enable) { +#if defined(CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND) && (CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND == 1) + base->TDC = CAN_TDC_TDCEN_SET((uint8_t) enable); +#else base->TDC = CAN_TDC_SSPOFF_SET(sample_point) | CAN_TDC_TDCEN_SET((uint8_t) enable); +#endif } /** @@ -874,7 +878,7 @@ hpm_stat_t can_read_received_message(CAN_Type *base, can_receive_buf_t *message) */ -#ifdef __cpluspuls +#ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h index 218f9af87c..78eb6615d8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -43,27 +43,25 @@ #endif #ifndef MAX -#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) #endif #ifndef MIN -#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) #endif -#define HPM_BITSMASK(val,offset) ((uint32_t)(val) << (offset)) -#define IS_HPM_BITMASK_SET(val,mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U) -#define IS_HPM_BIT_SET(val,offset) (((uint32_t)(val) & (1UL << (offset))) != 0U) -#define IS_HPM_BITMASK_CLR(val,mask) (((uint32_t)(val) & (uint32_t)(mask)) == 0U) -#define IS_HPM_BIT_CLR(val,offset) (((uint32_t)(val) & (1UL << (offset))) == 0U) +#define HPM_BITSMASK(val, offset) ((uint32_t)(val) << (offset)) +#define IS_HPM_BITMASK_SET(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U) +#define IS_HPM_BIT_SET(val, offset) (((uint32_t)(val) & (1UL << (offset))) != 0U) +#define IS_HPM_BITMASK_CLR(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) == 0U) +#define IS_HPM_BIT_CLR(val, offset) (((uint32_t)(val) & (1UL << (offset))) == 0U) -#define HPM_BREAK_IF(cond) if(cond) {break;} -#define HPM_CONTINUE_IF(cond) if(cond) {continue;} +#define HPM_BREAK_IF(cond) if (cond) { break; } +#define HPM_CONTINUE_IF(cond) if (cond) { continue; } #define HPM_CHECK_RET(x) \ - do \ - { \ + do { \ stat = (x); \ - if (status_success != stat) \ - { \ + if (status_success != stat) { \ return stat; \ } \ } while (false) @@ -79,11 +77,10 @@ typedef uint32_t hpm_stat_t; * 1000 or above for the application status group * [Code] Valid value: 0-999 * - * */ -#define MAKE_STATUS(group,code) ((uint32_t)(group)*1000U + (uint32_t)(code)) + */ +#define MAKE_STATUS(group, code) ((uint32_t)(group)*1000U + (uint32_t)(code)) /* @brief System status group definitions */ -enum -{ +enum { status_group_common = 0, status_group_uart = 1, status_group_i2c = 2, @@ -93,7 +90,7 @@ enum status_group_xpi = 6, status_group_l1c, status_group_dma, - status_group_dram, + status_group_femc, status_group_sdp, status_group_xpi_nor, status_group_otp, @@ -110,6 +107,7 @@ enum status_group_pllctl, status_group_pllctlv2, status_group_ffa, + status_group_mcan, status_group_middleware_start = 500, status_group_sdmmc = status_group_middleware_start, @@ -118,8 +116,7 @@ enum }; /* @brief Common status code definitions */ -enum -{ +enum { status_success = MAKE_STATUS(status_group_common, 0), status_fail = MAKE_STATUS(status_group_common, 1), status_invalid_argument = MAKE_STATUS(status_group_common, 2), @@ -143,7 +140,7 @@ enum #define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \ ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment) -#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable") +#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss") #define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \ ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment) @@ -160,6 +157,11 @@ ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment) #define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \ ATTR_RAMFUNC ATTR_ALIGN(alignment) +#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem") + +#define NOP() __asm volatile("nop") +#define WFI() __asm volatile("wfi") + #else #error Unknown toolchain #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h new file mode 100644 index 0000000000..90a0f19316 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_CRC_DRV_H +#define HPM_CRC_DRV_H + +/** + * @brief CRC APIs + * @defgroup crc_interface CRC driver APIs + * @ingroup crc_interfaces + * @{ + */ + + +#include "hpm_common.h" +#include "hpm_crc_regs.h" + +/** + * @brief CRC preset definitions + */ +typedef enum crc_preset_enum { + crc_preset_none = 0, + crc_preset_crc32, /*!< Poly: 0x04C11DB7, Init: 0xFFFFFFFF, Refin: True, Refout: True, Xorout: 0xFFFFFFFF */ + crc_preset_crc32_autosar, /*!< Poly: 0xF4ACFB13, Init: 0xFFFFFFFF, Refin: True, Refout: True, Xorout: 0xFFFFFFFF */ + crc_preset_crc16_ccitt, /*!< Poly: 0x1021, Init: 0x0000, Refin: True, Refout: True, Xorout: 0x0000 */ + crc_preset_crc16_xmodem, /*!< Poly: 0x1021, Init: 0x0000, Refin: False, Refout: False, Xorout: 0x0000 */ + crc_preset_crc16_modbus, /*!< Poly: 0x8005, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0x0000 */ + crc_preset_crc16_dnp, /*!< Poly: 0x3D65, Init: 0x0000, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_x25, /*!< Poly: 0x1021, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_usb, /*!< Poly: 0x8005, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_maxim, /*!< Poly: 0x8005, Init: 0x0000, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_ibm, /*!< Poly: 0x8005, Init: 0x0000, Refin: True, Refout: True, Xorout: 0x0000 */ + crc_preset_crc8_maxim, /*!< Poly: 0x31, Init: 0x00, Refin: True, Refout: True, Xorout: 0x00 */ + crc_preset_crc8_rohc, /*!< Poly: 0x07, Init: 0xFF, Refin: True, Refout: True, Xorout: 0x00 */ + crc_preset_crc8_itu, /*!< Poly: 0x07, Init: 0x00, Refin: False, Refout: False, Xorout: 0x55 */ + crc_preset_crc8, /*!< Poly: 0x07, Init: 0x00, Refin: False, Refout: False, Xorout: 0x00 */ + crc_preset_crc5_usb, /*!< Poly: 0x05, Init: 0x1F, Refin: True, Refout: True, Xorout: 0x1F */ +} crc_preset_t; + +/** + * @brief CRC Refin definitions. + */ +typedef enum crc_refin_enum { + crc_refin_false = 0, /*!< Do not manipulate input data stream. */ + crc_refin_true = 1, /*!< Reflect each byte in the input stream bitwise. */ +} crc_refin_t; + +/** + * @brief CRC Refout definitions. + */ +typedef enum crc_refout_enum { + crc_refout_false = 0, /*!< Do not manipulate output data stream. */ + crc_refout_true = 1, /*!< Reflect each byte in the output stream bitwise. */ +} crc_refout_t; + +/** + * @brief crc input data stream byte order definitions. + */ +typedef enum crc_in_byte_order_enum { + crc_in_byte_order_lsb = 0, /*!< Byte order of the CRC DATA LS Byte first. */ + crc_in_byte_order_msb = 1, /*!< Byte order of the CRC DATA MS Byte first. */ +} crc_in_byte_order_t; + +#define CRC_POLY_WIDTH_4 (4U) +#define CRC_POLY_WIDTH_5 (5U) +#define CRC_POLY_WIDTH_6 (6U) +#define CRC_POLY_WIDTH_7 (7U) +#define CRC_POLY_WIDTH_8 (8U) +#define CRC_POLY_WIDTH_16 (16U) +#define CRC_POLY_WIDTH_24 (24U) +#define CRC_POLY_WIDTH_32 (32U) + +/** + * @brief Channel config + */ +typedef struct crc_channel_config { + crc_preset_t preset; /*!< Preset CRC. See "crc_preset_t". */ + uint32_t init; /*!< Initial value for CRC. */ + uint32_t poly; /*!< Poly for CRC. */ + uint32_t poly_width; /*!< CRC poly width. See "CRC_POLY_WIDTH_x". */ + crc_in_byte_order_t in_byte_order; /*!< CRC intput byte order. See "crc_in_byte_order_t". */ + crc_refout_t refout; /*!< CRC reflect output. See "crc_refout_t". */ + crc_refin_t refin; /*!< CRC reflect iutput. See "crc_refin_t". */ + uint32_t xorout; /*!< XOR mask for CRC result (for no mask, should be 0). */ +} crc_channel_config_t; + +#define CRC_REG_WRITE8(addr, data)\ +{\ + uint32_t addr32 = (uint32_t)(addr);\ + (*(volatile uint8_t *)(addr32) = (data));\ +} + +#define CRC_REG_WRITE16(addr, data)\ +{\ + uint32_t addr32 = (uint32_t)(addr);\ + (*(volatile uint16_t *)(addr32) = (data));\ +} + +#define CRC_REG_WRITE32(addr, data)\ +{\ + uint32_t addr32 = (uint32_t)(addr);\ + (*(volatile uint32_t *)(addr32) = (data));\ +} + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reset CRC channel + * + * @param[in] ptr CRC base address + * @param[in] ch_index Index of the channel to be reset + * + */ +static inline void crc_reset(CRC_Type *ptr, uint32_t ch_index) +{ + ptr->CHN[ch_index].CLR |= CRC_CHN_CLR_CLR_MASK; +} + +/** + * @brief Get default channel config + * + * @param[in] ptr CRC base address + * @param[in] cfg Channel config + */ +void crc_get_default_channel_config(crc_channel_config_t *cfg); + +/** + * @brief Setup CRC channel + * + * @param[in] ptr CRC base address + * @param[in] ch_index Target channel index to be configured + * @param[in] cfg Channel config + * + * @return status_success if everything is okay + */ +hpm_stat_t crc_setup_channel_config(CRC_Type *ptr, uint32_t ch_index, + crc_channel_config_t *cfg); + +/** + * @brief Calculate one byte data crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] data Data that to be calculate + */ +static inline void crc_calc_byte(CRC_Type *ptr, uint32_t ch_index, uint8_t data) +{ + CRC_REG_WRITE8(&ptr->CHN[ch_index].DATA, data); +} + +/** + * @brief Calculate length bytes data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is byte + */ +void crc_calc_block_bytes(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length); + +/** + * @brief Calculate half-word data crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] data Data that to be calculate + */ +static inline void crc_calc_half_word(CRC_Type *ptr, uint32_t ch_index, uint16_t data) +{ + CRC_REG_WRITE16(&ptr->CHN[ch_index].DATA, data); +} + +/** + * @brief Calculate length half-words data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is half word(2 bytes) + */ +void crc_calc_block_half_words(CRC_Type *ptr, uint32_t ch_index, uint16_t *pbuffer, uint32_t length); + +/** + * @brief Calculate word data crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] data Data that to be calculate + */ +static inline void crc_calc_word(CRC_Type *ptr, uint32_t ch_index, uint32_t data) +{ + CRC_REG_WRITE32(&ptr->CHN[ch_index].DATA, data); +} + +/** + * @brief Calculate length words data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is word(4 bytes) + */ +void crc_calc_block_words(CRC_Type *ptr, uint32_t ch_index, uint32_t *pbuffer, uint32_t length); + +/** + * @brief Fast calculate length bytes large data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is byte + */ +void crc_calc_large_block_fast(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length); + +/** + * @brief Get CRC result + * + * @param[in] ptr CRC base address + * @param[in] ch_index Index of the channel to be get + * @return CRC result + */ +static inline uint32_t crc_get_result(CRC_Type *ptr, uint32_t ch_index) +{ + return ptr->CHN[ch_index].RESULT; +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_CRC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h new file mode 100644 index 0000000000..acec7c6d76 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CSR_DRV_H +#define HPM_CSR_DRV_H + +#include "hpm_csr_regs.h" +#include "riscv/riscv_core.h" + + +/** + * @brief CSR driver APIs + * @defgroup csr_interface CSR driver APIs + * @ingroup csr_interfaces + * @{ + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable access to CSR_CYCLE and CSR_MCYCLEH + * @note This Function can be called in Machine mode only + * + */ +static inline void hpm_csr_enable_access_to_csr_cycle(void) +{ + uint32_t mcounter_en = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounter_en | CSR_MCOUNTEREN_CY_MASK); +} + +/** + * @brief Disable access to CSR_CYCLE and CSR_MCYCLEH + * @note This Function can be called in Machine mode only + * + */ +static inline void hpm_csr_disable_access_to_csr_cycle(void) +{ + uint32_t mcounter_en = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounter_en & ~CSR_MCOUNTEREN_CY_MASK); +} + +/** + * @brief Get the core cycle value + * @note The CY bit in MCOUNTEREN must be enabled before using this API whendevice is : + * - in supervisor mode if the device supports M/S/U mode, or + * - in user mode if the device supports M/U mode + * + * @return CSR cycle value in 64-bit + */ +static inline uint64_t hpm_csr_get_core_cycle(void) +{ + uint64_t result; + uint32_t resultl_first = read_csr(CSR_CYCLE); + uint32_t resulth = read_csr(CSR_CYCLEH); + uint32_t resultl_second = read_csr(CSR_CYCLE); + if (resultl_first < resultl_second) { + result = ((uint64_t)resulth << 32) | resultl_first; /* if CYCLE didn't roll over, return the value directly */ + } else { + resulth = read_csr(CSR_CYCLEH); + result = ((uint64_t)resulth << 32) | resultl_second; /* if CYCLE rolled over, need to get the CYCLEH again */ + } + return result; + } + +/** + * @brief Get the core mcycle value + * @note This function can be called in machine mode only + * + * @return CSR mcycle value in 64-bit + */ +static inline uint64_t hpm_csr_get_core_mcycle(void) +{ + uint64_t result; + uint32_t resultl_first = read_csr(CSR_MCYCLE); + uint32_t resulth = read_csr(CSR_MCYCLEH); + uint32_t resultl_second = read_csr(CSR_MCYCLE); + if (resultl_first < resultl_second) { + result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ + } else { + resulth = read_csr(CSR_MCYCLEH); + result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ + } + return result; + } + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_CSR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h index cc6d1163fc..5c067f1199 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,9 @@ #include "hpm_dac_regs.h" #include "hpm_soc_feature.h" +/* The range of DAC output value setting is from 0.0 to 10000.0, which is mapped to 0 to 100 in percentage. */ +#define DAC_OUTPUT(PERCENT) (PERCENT / 10000.0f * (DAC_SOC_MAX_DATA + 1)) + #define DAC_AHB_ERROR_EVENT DAC_IRQ_EN_AHB_ERROR_MASK #define DAC_FIFO_EMPTY_EVENT DAC_IRQ_EN_FIFO_EMPTY_MASK #define DAC_BUF1_COMPLETE_EVENT DAC_IRQ_EN_BUF1_CMPT_MASK @@ -33,8 +36,7 @@ typedef enum { typedef struct { bool sync_mode; uint8_t dac_mode; - uint8_t clk_dac_div; - uint16_t div_cfg; + uint8_t ana_div; } dac_config_t; typedef enum { @@ -105,4 +107,4 @@ uint16_t dac_get_current_buffer_offset(DAC_Type *ptr); } #endif -#endif \ No newline at end of file +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h index 19bce00e17..c29f3507ee 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -90,26 +90,6 @@ static inline void dao_disable_hpf(DAO_Type *ptr) ptr->CTRL &= ~DAO_CTRL_HPF_EN_MASK; } -/** - * @brief enable error irq - * - * @param [in] ptr DAO base address - */ -static inline void dao_enable_error_irq(DAO_Type *ptr) -{ - ptr->CTRL |= DAO_CTRL_SAT_ERR_IE_MASK; -} - -/** - * @brief disable error irq - * - * @param [in] ptr DAO base address - */ -static inline void dao_disable_error_irq(DAO_Type *ptr) -{ - ptr->CTRL &= ~DAO_CTRL_SAT_ERR_IE_MASK; -} - /** * @brief enable channel * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h index 3cd4e51765..3031746615 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -50,6 +50,8 @@ typedef enum display_pixel_format { display_pixel_format_gbr422, display_pixel_format_yuv422, display_pixel_format_ycbcr422, + display_pixel_format_y8, + display_pixel_format_raw8, } display_pixel_format_t; /** @@ -160,17 +162,21 @@ extern "C" { static inline uint8_t display_get_pixel_size_in_bit(display_pixel_format_t format) { - switch(format) { - case display_pixel_format_argb8888: - return 32; - case display_pixel_format_rgb565: - return 16; - case display_pixel_format_yuv422: - return 16; - case display_pixel_format_ycbcr422: - return 16; - default: - return 0; + switch (format) { + case display_pixel_format_argb8888: + return 32; + case display_pixel_format_rgb565: + return 16; + case display_pixel_format_yuv422: + return 16; + case display_pixel_format_ycbcr422: + return 16; + case display_pixel_format_y8: + return 8; + case display_pixel_format_raw8: + return 8; + default: + return 0; } } @@ -183,13 +189,13 @@ static inline */ static inline bool display_pixel_format_is_yuv_format(display_pixel_format_t format) { - switch(format) { - case display_pixel_format_yuv422: - return true; - case display_pixel_format_ycbcr422: - return true; - default: - return false; + switch (format) { + case display_pixel_format_yuv422: + return true; + case display_pixel_format_ycbcr422: + return true; + default: + return false; } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h index 78bcbe6655..f732c389ec 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h @@ -1,13 +1,13 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#ifndef HPM_DMA_DRV_H -#define HPM_DMA_DRV_H +#ifndef HPM_DMAV1_DRV_H +#define HPM_DMAV1_DRV_H #include "hpm_common.h" #include "hpm_soc_feature.h" #include "hpm_dma_regs.h" @@ -36,8 +36,6 @@ #define DMA_TRANSFER_WIDTH_HALF_WORD (1U) #define DMA_TRANSFER_WIDTH_WORD (2U) #define DMA_TRANSFER_WIDTH_DOUBLE_WORD (3U) -#define DMA_TRANSFER_WIDTH_QUAD_WORD (4U) -#define DMA_TRANSFER_WIDTH_EIGHT_WORD (5U) #define DMA_STATUS_ERROR_SHIFT (0U) #define DMA_STATUS_ABORT_SHIFT (8U) @@ -123,6 +121,7 @@ typedef struct dma_handshake_config { uint32_t dst; uint32_t src; uint32_t size_in_byte; + uint8_t data_width; /* data width, value defined by DMA_TRANSFER_WIDTH_xxx */ uint8_t ch_index; bool dst_fixed; bool src_fixed; @@ -182,6 +181,96 @@ static inline void dma_disable_channel(DMA_Type *ptr, uint32_t ch_index) ptr->CHCTRL[ch_index].CTRL &= ~DMA_CHCTRL_CTRL_ENABLE_MASK; } +/** + * @brief Check whether DMA channel is enable + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return true if DMA channel is enable + * + */ +static inline bool dma_channel_is_enable(DMA_Type *ptr, uint32_t ch_index) +{ + return (ptr->CHCTRL[ch_index].CTRL & DMA_CHCTRL_CTRL_ENABLE_MASK) ? true : false; +} + +/** + * @brief Get DMA channel residue transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return residue transfer size + * + */ +static inline uint32_t dma_get_residue_transfer_size(DMA_Type *ptr, uint32_t ch_index) +{ + return ptr->CHCTRL[ch_index].TRANSIZE; +} + +/** + * @brief Set DMA channel transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] size_in_width transfer size of the channel. The width is current dma channel configured source width. + * Transfer total bytes are (size_in_width * source width). + * + */ +static inline void dma_set_transfer_size(DMA_Type *ptr, uint32_t ch_index, uint32_t size_in_width) +{ + ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width); +} + +/** + * @brief Set DMA channel transfer width and size in byte + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] src_width transfer source width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + * @param[in] size_in_byte transfer size in byte of the channel. The dma transfer size is (size_in_byte >> src_width). + * + */ +static inline void dma_set_transfer_src_width_byte_size(DMA_Type *ptr, uint32_t ch_index, uint8_t src_width, uint32_t size_in_byte) +{ + assert((src_width == DMA_TRANSFER_WIDTH_BYTE) || (src_width == DMA_TRANSFER_WIDTH_HALF_WORD) + || (src_width == DMA_TRANSFER_WIDTH_WORD) || (src_width == DMA_TRANSFER_WIDTH_DOUBLE_WORD)); + + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCWIDTH_MASK) | DMA_CHCTRL_CTRL_SRCWIDTH_SET(src_width); + ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_byte >> src_width); +} + +/** + * @brief Set DMA channel source address + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr source address + * + */ +static inline void dma_set_source_address(DMA_Type *ptr, uint32_t ch_index, uint32_t addr) +{ + ptr->CHCTRL[ch_index].SRCADDR = addr; +} + +/** + * @brief Set DMA channel destination address + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr destination address + * + */ +static inline void dma_set_destination_address(DMA_Type *ptr, uint32_t ch_index, uint32_t addr) +{ + ptr->CHCTRL[ch_index].DSTADDR = addr; +} + /** * @brief Abort channel transfer with mask * @@ -259,6 +348,18 @@ static inline uint32_t dma_check_transfer_status(DMA_Type *ptr, uint8_t ch_index return dma_status; } +/** + * @brief Clear transfer status + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index + * + */ +static inline void dma_clear_transfer_status(DMA_Type *ptr, uint8_t ch_index) +{ + ptr->INTSTATUS &= ~((1 << (DMA_STATUS_TC_SHIFT + ch_index)) | (1 << (DMA_STATUS_ERROR_SHIFT + ch_index)) | (1 << (DMA_STATUS_ABORT_SHIFT + ch_index))); +} + /** * @brief Enable DMA Channel interrupt * @@ -329,18 +430,32 @@ void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch); * @brief Setup DMA channel * * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index to be configured + * @param[in] ch_num Target channel index to be configured * @param[in] ch Channel config + * @param[in] start_transfer Set true to start transfer * * @return status_success if everything is okay */ -hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint32_t ch_index, - dma_channel_config_t *ch); +hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint8_t ch_num, + dma_channel_config_t *ch, bool start_transfer); + +/** + * @brief Config linked descriptor function + * + * @param[in] ptr DMA base address + * @param[in] descriptor Linked descriptor pointer + * @param[in] ch_num Target channel index to be configured + * @param[in] config Descriptor config pointer + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_config_linked_descriptor(DMA_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config); + /** * @brief Start DMA copy * * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index + * @param[in] ch_num Target channel index * @param[in] dst Destination address * @param[in] src Source Address * @param[in] size_in_byte Size in byte @@ -349,19 +464,43 @@ hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint32_t ch_index, * @return status_success if everthing is okay * @note: dst, src, size should be aligned with burst_len_in_byte */ -hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_index, +hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, uint32_t dst, uint32_t src, uint32_t size_in_byte, uint32_t burst_len_in_byte); +/** + * @brief Get default handshake config + * + * @param[in] ptr DMA base address + * @param[in] config default config + */ +void dma_default_handshake_config(DMA_Type *ptr, dma_handshake_config_t *config); + /** * @brief config dma handshake function * * @param[in] ptr DMA base address * @param[in] pconfig dma handshake config pointer + * @param[in] start_transfer Set true to start transfer * - * @return status_success if everthing is okay + * @return status_success if everything is okay */ -hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig); +hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer); + + +#if defined(DMA_SOC_HAS_IDLE_FLAG) && (DMA_SOC_HAS_IDLE_FLAG == 1) +/** + * @brief Check whether DMA is idle + * @param [in] ptr DMA base address + * @return true DMA is idle + * @return false DMA is busy + */ +static inline bool dma_is_idle(DMA_Type *ptr) +{ + return ((ptr->IDMISC & DMA_IDMISC_IDLE_FLAG_MASK) != 0U); +} +#endif + #ifdef __cplusplus } @@ -369,4 +508,4 @@ hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig); /** * @} */ -#endif /* HPM_DMA_DRV_H */ +#endif /* HPM_DMAV1_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h index 8e0f71f1ef..2e7408a55a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dram_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dram_drv.h deleted file mode 100644 index 8e96d41ccb..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dram_drv.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (c) 2021 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_DRAM_DRV_H -#define _HPM_DRAM_DRV_H -#include "hpm_dram_regs.h" - -/** - * @brief DRAM driver APIs - * @defgroup dram_interface DRAM driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -#define DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE (8UL) -/* @brief dram sdram column address bit width */ -#define DRAM_SDRAM_COLUMN_ADDR_12_BITS (0U) -#define DRAM_SDRAM_COLUMN_ADDR_11_BITS (1U) -#define DRAM_SDRAM_COLUMN_ADDR_10_BITS (2U) -#define DRAM_SDRAM_COLUMN_ADDR_9_BITS (3U) -#define DRAM_SDRAM_COLUMN_ADDR_8_BITS (4U) -/* @brief cas latency */ -#define DRAM_SDRAM_CAS_LATENCY_1 (1U) -#define DRAM_SDRAM_CAS_LATENCY_2 (2U) -#define DRAM_SDRAM_CAS_LATENCY_3 (3U) -/* @brief iomux options */ -#define DRAM_IO_MUX_NOT_USED (0U) -#define DRAM_IO_MUX_CSX0 (1U) -#define DRAM_IO_MUX_CSX1 (2U) -#define DRAM_IO_MUX_CSX2 (3U) -#define DRAM_IO_MUX_CSX3 (4U) -#define DRAM_IO_MUX_RDY (5U) -/* @brief sdram bank number */ -#define DRAM_SDRAM_BANK_NUM_4 (0U) -#define DRAM_SDRAM_BANK_NUM_2 (1U) -/* @brief chip select */ -#define DRAM_SDRAM_CS0 (0U) -#define DRAM_SDRAM_CS1 (1U) -/* @brief sdram port size */ -#define DRAM_SDRAM_PORT_SIZE_8_BITS (0U) -#define DRAM_SDRAM_PORT_SIZE_16_BITS (1U) -#define DRAM_SDRAM_PORT_SIZE_32_BITS (2U) - -#define DRAM_AXI_Q_COUNT (2U) -#define DRAM_AXI_Q_A (0U) -#define DRAM_AXI_Q_B (1U) -/* @brief DQS option */ -#define DRAM_DQS_INTERNAL (0U) -#define DRAM_DQS_FROM_PAD (1U) - -#define DRAM_BR_COUNT (2U) - -#define DRAM_CMD_KEY DRAM_IPCMD_KEY_SET(0xA55A) -#define DRAM_CMD_WRITE_FLAG (1UL << 31) -#define DRAM_CMD_SDRAM_READ (0x8U) -#define DRAM_CMD_SDRAM_WRITE (DRAM_CMD_WRITE_FLAG | 0x9U) -#define DRAM_CMD_SDRAM_MODE_SET (DRAM_CMD_WRITE_FLAG | 0xAU) -#define DRAM_CMD_SDRAM_ACTIVE (0xBU) -#define DRAM_CMD_SDRAM_AUTO_REFRESH (0xCU) -#define DRAM_CMD_SDRAM_SELF_REFRESH (0xDU) -#define DRAM_CMD_SDRAM_PRECHARGE (0xEU) -#define DRAM_CMD_SDRAM_PRECHARGE_ALL (0xFU) - -/** - * @brief Structure for specifying the configuration of AXI queue weight - */ -typedef struct { - bool enable; /**< Enable AXI weight setting flag */ - uint8_t qos; - uint8_t age; - uint8_t slave_hit_wo_rw; - uint8_t slave_hit; /**< only available for queue A */ - uint8_t page_hit; /**< only available for queue B */ - uint8_t bank_rotation; /**< only available for queue B */ -} dram_axi_q_weight_t; - -/** - * @brief Structure for specifying the configuration of SDRAM - */ -typedef struct { - uint32_t base_address; /**< external SDRAM base address */ - uint32_t size_in_byte; /**< external SDRAM size in byte */ - uint32_t refresh_count; /**< referesh count */ - uint8_t col_addr_bits; /**< column address bit count */ - uint8_t cas_latency; /**< CAS latency */ - uint8_t cs; /**< chip select */ - uint8_t cs_mux_pin; /**< chip select mux */ - uint8_t bank_num; /**< bank number */ - uint8_t prescaler; /**< presecaler */ - uint8_t port_size; /**< SDRAM port size */ - uint8_t burst_len_in_byte; /**< 1/2/4/8 bytes */ - uint8_t cke_off_in_ns; /**< Tcks */ - uint8_t act_to_precharge_in_ns; /**< Tras */ - uint8_t precharge_to_act_in_ns; /**< Trp */ - uint8_t act_to_rw_in_ns; /**< Trcd */ - uint8_t act_to_act_in_ns; /**< Trrd */ - uint8_t refresh_to_refresh_in_ns; /**< Trc */ - uint8_t write_recover_in_ns; /**< Tdpl */ - uint8_t self_refresh_recover_in_ns; /**< Txsr */ - uint8_t refresh_recover_in_ns; /**< Txsr */ - uint8_t refresh_in_ms; /**< Tref */ - uint8_t idle_timeout_in_ns; - uint8_t data_width_in_byte; - uint8_t auto_refresh_count_in_one_burst; - uint8_t delay_cell_value; /**< Delay cell value */ -} dram_sdram_config_t; - -/** - * @brief Structure for specifying the configuration of DRAM - */ -typedef struct { - uint8_t dqs; /**< DQS setting */ - uint8_t cmd_timeout; /**< command timeout */ - uint8_t bus_timeout; /**< bus timeout */ - dram_axi_q_weight_t axi_q_weight[DRAM_AXI_Q_COUNT]; -} dram_config_t; - -/** - * @brief Structure for DRAM command - */ -typedef struct { - uint32_t opcode; - uint32_t data; -} dram_cmd_t; - -/* - * @brief DRAM specific status - */ -enum { - status_dram_cmd_err = MAKE_STATUS(status_group_dram, 1), -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief dram enable - * - * Enable DRAM - * - * @param[in] ptr DRAM base address - */ -static inline void dram_enable(DRAM_Type *ptr) -{ - ptr->CTRL &= ~DRAM_CTRL_DIS_MASK; -} - -/** - * @brief dram disable - * - * Disable DRAM - * - * @param[in] ptr DRAM base address - */ -static inline void dram_disable(DRAM_Type *ptr) -{ - while((ptr->STAT0 & (uint32_t) DRAM_STAT0_IDLE_MASK) == 0) {} - ptr->CTRL |= DRAM_CTRL_DIS_MASK; -} - -/** - * @brief dram software reset - * - * Perform software reset - * - * @param[in] ptr DRAM base address - */ -static inline void dram_sw_reset(DRAM_Type *ptr) -{ - ptr->CTRL = DRAM_CTRL_RST_MASK; - while((ptr->CTRL & (uint32_t) DRAM_CTRL_RST_MASK) != 0) {} -} - -/** - * @brief dram get default config - * - * Get DRAM default parameters - * - * @param[in] ptr DRAM base address - * @param[out] config dram_config_t address - */ -void dram_default_config(DRAM_Type *ptr, dram_config_t *config); - -/** - * @brief dram init controller - * - * Initialize DRAM with give dram_config_t - * - * @param[in] ptr DRAM base address - * @param[in] config dram_config_t to initialize dram - */ -void dram_init(DRAM_Type *ptr, dram_config_t *config); - -/** - * @brief dram get typical sdram config - * - * Fill out the structure of dram_sdram_config_t with typical SDRAM parameters which should work - * with most SDRAMs. - * - * @param[in] ptr DRAM base address - * @param[out] config dram_sdram_config_t sdram configuration struction to config dram - */ -void dram_get_typical_sdram_config(DRAM_Type *ptr, dram_sdram_config_t *config); - -/** - * @brief dram config sdram - * - * Configure DRAM controlling external SDRAM using parameters specified in dram_sdram_config - * - * @param[in] ptr DRAM base address - * @param[in] clk_in_hz dram source clock frequency in Hz - * @param[in] config dram_sdram_config_t sdram configuration struction to config dram - */ -hpm_stat_t dram_config_sdram(DRAM_Type *ptr, uint32_t clk_in_hz, dram_sdram_config_t *config); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* _HPM_DRAM_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h index 769cae31aa..c0cf51e96f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,9 +8,10 @@ #ifndef HPM_ENET_DRV_H #define HPM_ENET_DRV_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_common.h" #include "hpm_enet_regs.h" #include "hpm_soc_feature.h" @@ -23,9 +24,10 @@ * @{ */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macro Constant Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #define ENET_HEADER (14U) /**< 6-byte Dest addr, 6-byte Src addr, 2-byte type */ #define ENET_EXTRA (2U) /**< Extra bytes in some cases */ #define ENET_VLAN_TAG (4U) /**< optional 802.1q VLAN Tag */ @@ -34,15 +36,39 @@ #define ENET_MAX_PAYLOAD (1500U) /**< Maximum Ethernet payload size */ #define ENET_MAX_FRAME_SIZE (1524U) /**< ENET_HEADER + ENET_EXTRA + VLAN_TAG + MAX_ENET_PAYLOAD + ENET_CRC */ #define ENET_JUMBO_FRAME_PAYLOAD (9000U) /**< Jumbo frame payload size */ +#define ENET_MAC (6) /**< Ethernet MAC size */ +#define ENET_ERROR (0) /**< ENET error */ +#define ENET_SUCCESS (1) /**< ENET success */ -#define ENET_ERROR (0) /**< ENET error */ -#define ENET_SUCCESS (1) /**< ENET success */ - -#define ENET_ADJ_FREQ_BASE_ADDEND (0x7fffffffUL) /**< PTP base adjustment addend */ +#define ENET_ADJ_FREQ_BASE_ADDEND (0x80000000UL) /**< PTP base adjustment addend */ #define ENET_ONE_SEC_IN_NANOSEC (1000000000UL) /**< one second in nanoseconds */ -/*---------------------------------------------------------------------* + +#define ENET_PPS_CMD_MASK (0x07UL) /**< Enet PPS CMD Mask */ +#define ENET_PPS_CMD_OFS_FAC (3U) /**< Enet PPS CMD OFS Factor */ + +#ifndef ENET_RETRY_CNT +#define ENET_RETRY_CNT (10000UL) /**< Enet retry count for PTP */ +#endif + +/*--------------------------------------------------------------------- * Typedef Enum Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ + +/** @brief Programmable burst length selections */ +typedef enum { + enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK, + enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK, + enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK +} enet_interrupt_enable_t; + +/** @brief Programmable burst length selections */ +typedef enum { + enet_lpi_int_mask = ENET_INTR_MASK_LPIIM_MASK, + enet_rgsmii_int_mask = ENET_INTR_MASK_RGSMIIIM_MASK +} enet_interrupt_mask_t; + + /** @brief Programmable burst length selections */ typedef enum { enet_pbl_1 = 1, @@ -55,13 +81,39 @@ typedef enum { /** @brief Checksum insertion control selections */ typedef enum { - enet_cic_bypass = 0, - enet_cic_insert_ipv4_header, - enet_cic_insert_tcp_udp_icmp, - enet_cic_insert_tcp_upd_icmp, -} enet_insert_t; + enet_cic_disable = 0, + enet_cic_ip = 1, + enet_cic_ip_no_pseudoheader = 2, + enet_cic_ip_pseudoheader = 3 +} enet_cic_insertion_control_t; -/** @brief PHY opeartion selections */ +/** @brief VLAN insertion control selections */ +typedef enum { + enet_vlic_disable = 0, + enet_vlic_remove_vlan_tag = 1, + enet_vlic_insert_vlan_tag = 2, + enet_vlic_replace_vlan_tag = 3 +} enet_vlan_insertion_control_t; + +/** @brief SA insertion or replacement control selections for any selective frames */ +typedef enum { + enet_saic_disable = 0, + enet_saic_insert_mac0 = 1, + enet_saic_replace_mac0 = 2, + enet_saic_insert_mac1 = 5, + enet_saic_replace_mac1 = 6 +} enet_saic_insertion_replacement_control_t; + +/** @brief SA insertion or replacement control selections for all transmit frames */ +typedef enum { + enet_sarc_disable = 0, + enet_sarc_insert_mac0 = 2, + enet_sarc_replace_mac0 = 3, + enet_sarc_insert_mac1 = 6, + enet_sarc_replace_mac1 = 7 +} enet_sarc_insertion_replacement_control_t; + +/** @brief PHY operation selections */ typedef enum { enet_phy_op_read = 0, enet_phy_op_write @@ -70,9 +122,9 @@ typedef enum { /** @brief PHY status */ typedef enum { - enet_phy_idle = 0, - enet_phy_busy -} enet_phy_status_t; + enet_gmii_idle = 0, + enet_gmii_busy +} enet_gmii_status_t; /** @brief CSR clock range and MDC clock selections */ /** @note The suggested range of CSR clock is approximately @@ -105,6 +157,19 @@ typedef enum { enet_inf_rgmii = 1 } enet_inf_type_t; +/** @brief enet line speed */ +typedef enum { + enet_line_speed_1000mbps = 0, + enet_line_speed_10mbps = 2, + enet_line_speed_100mbps = 3 +} enet_line_speed_t; + +/** @brief enet duplex mode */ +typedef enum { + enet_half_duplex = 0, + enet_full_duplex +} enet_duplex_mode_t; + /** @brief enet timestamp update methods */ typedef enum { enet_ptp_time_coarse_update = 0, @@ -136,14 +201,55 @@ typedef enum { enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */ } enet_ts_ss_ptp_msg_t; +/** @brief PTP timer rollover modes */ typedef enum { - enet_ptp_count_res_high = 0, /* ptp sub-second count resolution at 0.465 ns */ - enet_ptp_count_res_low /* ptp su-second count resolution at 1 ns */ -} enet_ptp_count_res_t; + enet_ts_bin_rollover_control = 0, /* timestamp rolls over after 0x7fffffff */ + enet_ts_dig_rollover_control /* timestamp rolls over after 0x3b9ac9ff */ +} enet_ts_rollover_control_t; -/*---------------------------------------------------------------------* +/** @brief PPS indexes */ +typedef enum { + enet_pps_0 = -1, + enet_pps_1 = 0, + enet_pps_2 = 1, + enet_pps_3 = 2 +} enet_pps_idx_t; + +/** @brief PPS0 control for output frequency selections */ +typedef enum { + enet_pps_ctrl_pps = 0, + enet_pps_ctrl_bin_2hz_digital_1hz, + enet_pps_ctrl_bin_4hz_digital_2hz, + enet_pps_ctrl_bin_8hz_digital_4hz, + enet_pps_ctrl_bin_16hz_digital_8hz, + enet_pps_ctrl_bin_32hz_digital_16hz, + enet_pps_ctrl_bin_64hz_digital_32hz, + enet_pps_ctrl_bin_128hz_digital_64hz, + enet_pps_ctrl_bin_256hz_digital_128hz, + enet_pps_ctrl_bin_512hz_digital_256hz, + enet_pps_ctrl_bin_1024hz_digital_512hz, + enet_pps_ctrl_bin_2048hz_digital_1024hz, + enet_pps_ctrl_bin_4096hz_digital_2048hz, + enet_pps_ctrl_bin_8192hz_digital_4096hz, + enet_pps_ctrl_bin_16384hz_digital_8192hz, + enet_pps_ctrl_bin_32867hz_digital_16384hz +} enet_pps_ctrl_t; + +/** @brief PPS0 commands */ +typedef enum { + enet_pps_cmd_no_command = 0, + enet_pps_cmd_start_single_pulse, + enet_pps_cmd_start_pulse_train, + enet_pps_cmd_cancel_start, + enet_pps_cmd_stop_pulse_train_at_time, + enet_pps_cmd_stop_pulse_train_immediately, + enet_pps_cmd_cancel_stop_pulse_train +} enet_pps_cmd_t; + +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /** @brief enet buffer config struct */ typedef struct { uint32_t buffer; @@ -151,12 +257,13 @@ typedef struct { uint16_t size; } enet_buff_config_t; - /** @brief enet mac config struct */ typedef struct { uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT]; uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT]; uint8_t valid_max_count; + uint8_t dma_pbl; + uint8_t sarc; } enet_mac_config_t; /** @brief transmission descriptor struct */ @@ -200,7 +307,7 @@ typedef struct { uint32_t tbs1 : 13; /**< Transmit Buffer 1 Size */ uint32_t reserved: 3; /**< Reserved */ uint32_t tbs2 : 13; /**< Transmit Buffer 2 Size */ - uint32_t saic : 3; /**< SA Inertion Control */ + uint32_t saic : 3; /**< SA Insertion Control */ } tdes1_bm; }; @@ -238,10 +345,8 @@ typedef struct { #endif } enet_tx_desc_t; - /** @brief reception descriptor struct */ -typedef struct -{ +typedef struct { union { uint32_t rdes0; @@ -284,7 +389,7 @@ typedef struct union { uint32_t rdes2; struct { - uint32_t buffer1; /**< Buffer 1 Address */ + uint32_t buffer1; /**< Buffer 1 Address */ } rdes2_bm; }; @@ -300,26 +405,26 @@ typedef struct union { uint32_t rdes4; struct { - uint32_t ip_payload_type : 3; /**< IP Payload Type */ - uint32_t ip_header_err : 1; /**< IP Header Error */ - uint32_t ip_payload_err : 1; /**< IP Payload Error */ - uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ - uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ - uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ - uint32_t msg_type : 4; /**< Message Type */ - uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ - uint32_t ptp_version : 1; /**< PTP Version */ - uint32_t ts_dp : 1; /**< Timestamp Dropped */ - uint32_t reserved0 : 1; /**< Reserved */ - uint32_t av_pkt_recv : 1; /**< AV Packet Received */ - uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ - uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ - uint32_t reserved1 : 3; /**< Reserved */ - uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ - uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ - uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ - uint32_t reserved2 : 4; /**< Reserved */ - } rdes4_bm; + uint32_t ip_payload_type : 3; /**< IP Payload Type */ + uint32_t ip_header_err : 1; /**< IP Header Error */ + uint32_t ip_payload_err : 1; /**< IP Payload Error */ + uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ + uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ + uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ + uint32_t msg_type : 4; /**< Message Type */ + uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ + uint32_t ptp_version : 1; /**< PTP Version */ + uint32_t ts_dp : 1; /**< Timestamp Dropped */ + uint32_t reserved0 : 1; /**< Reserved */ + uint32_t av_pkt_recv : 1; /**< AV Packet Received */ + uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ + uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ + uint32_t reserved1 : 3; /**< Reserved */ + uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ + uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ + uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ + uint32_t reserved2 : 4; /**< Reserved */ + } rdes4_bm; }; struct { @@ -328,7 +433,7 @@ typedef struct struct { uint32_t rtsl; /**< Receive Frame Timestamp Low */ - }rdes6_bm; + } rdes6_bm; struct { uint32_t rtsh; /**< Receive Frame Timestamp High */ @@ -350,6 +455,18 @@ typedef struct { uint32_t seg_count; } enet_rx_frame_info_t; +/** @brief enet control config struct for transmission */ +typedef struct { + bool enable_ioc; /* interrupt on completion */ + bool disable_crc; /* disable CRC */ + bool disable_pad; /* disable Pad */ + bool enable_ttse; /* enable transmit timestamp */ + bool enable_crcr; /* CRC replacement control */ + uint8_t cic; /* checksum insertion control */ + uint8_t vlic; /* VLAN insertion control */ + uint8_t saic; /* SA insertion control */ +} enet_tx_control_config_t; + /** @brief enet description struct */ typedef struct { enet_tx_desc_t *tx_desc_list_head; @@ -359,23 +476,54 @@ typedef struct { enet_buff_config_t tx_buff_cfg; enet_buff_config_t rx_buff_cfg; enet_rx_frame_info_t rx_frame_info; + enet_tx_control_config_t tx_control_config; } enet_desc_t; -/** @brief PTP timestamp struct */ +/** @brief PTP system timestamp struct */ +typedef struct { + uint32_t sec; + uint32_t nsec; +} enet_ptp_ts_system_t; + +/** @brief PTP update timestamp struct */ typedef struct { uint32_t sec; uint32_t nsec; uint8_t sign; -} enet_ptp_time_t; +} enet_ptp_ts_update_t; -/* PTP config strcut */ +/** @brief PTP target timestamp struct */ +typedef struct { + uint32_t sec; + uint32_t nsec; +} enet_ptp_ts_target_t; + +/** @brief PTP config strcut */ typedef struct { uint8_t ssinc; - uint8_t sub_sec_count_res; + uint8_t timestamp_rollover_mode; uint8_t update_method; uint32_t addend; } enet_ptp_config_t; +/** @brief PTP PPS command output config strcut */ +typedef struct { + uint32_t pps_interval; + uint32_t pps_width; + uint32_t target_sec; + uint32_t target_nsec; +} enet_pps_cmd_config_t; + +/** @brief Enet interrupt config struct */ +typedef struct { + uint32_t int_enable; /* DMA_INTR_EN */ + uint32_t int_mask; /* INTR MASK */ + uint32_t mmc_intr_rx; + uint32_t mmc_intr_mask_rx; + uint32_t mmc_intr_tx; + uint32_t mmc_intr_mask_tx; +} enet_int_config_t; + /* * @brief Bit definition of TDES1 */ @@ -385,27 +533,91 @@ typedef struct { #if defined __cplusplus extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ +/** + * @brief Get a default control config for tranmission + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] config A pointer to a control config structure for tranmission + */ +void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config); + +/** + * @brief Get interrupt status + * + * @param[in] ptr An Ethernet peripheral base address + * @return A result of interrupt status + */ +uint32_t enet_get_interrupt_status(ENET_Type *ptr); + +/** + * @brief Mask the specified mmc interrupt evenets of received frames + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] config A mask of the specified evenets + */ +void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask); + +/** + * @brief Mask the specified mmc interrupt evenets of transmitted frames + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] config A mask of the specified evenets + */ +void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask); + +/** + * @brief Get a staus of mmc receive interrupt events + * + * @param[in] ptr An Ethernet peripheral base address + * @return A result of interrupt status + */ +uint32_t enet_get_mmc_rx_interrupt_status(ENET_Type *ptr); +/** + * @brief et a staus of mmc transmission interrupt events + * + * @param[in] ptr An Ethernet peripheral base address + * @return A result of interrupt status + */ +uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr); + /** * @brief Initialize controller * * @param[in] ptr An Ethernet peripheral base address * @param[in] inf_type the specified interface * @param[in] desc A pointer to descriptor config - * @param[in] config A pointer to mac config - * @param[in] intr A mask of all required interrupts - * @pramm[in] mask_intr A mask of all not required interrupts + * @param[in] cfg A pointer to mac config + * @param[in] int_cfg A pointer to the masks of the specified enabled interrupts and the specified masked interrupts */ -int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, uint32_t intr, uint32_t mask_intr); +int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); + +/** + * @brief Set port line speed + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] line_speed An enum variable of @ref enet_line_speed_t + */ +void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed); + +/** + * @brief Set duplex mode + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] mode An enum variable of @ref enet_duplex_mode_t + */ +void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode); + /** * @brief Read phy * * @param[in] ptr An Ethernet peripheral base address * @param[in] phy_addr the specified address of phy * @param[in] addr the specified address of register - * @retval A value corresponding to the specifeid register address + * @retval A value corresponding to the specified register address */ uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); @@ -422,7 +634,7 @@ void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t d /** * @brief Check if there is a received frame * - * @param[out] parent_rx_desc_list_cur a parrent pointer to the current reception descritpion list + * @param[out] parent_rx_desc_list_cur a parent pointer to the current reception description list * @param[in] rx_frame_info A pointer to the information of the reception frames * @retval A result of reception frame. * 1 means that a reception of frame is successful. @@ -433,7 +645,7 @@ uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, ene /** * @brief get a received frame * - * @param[out] parent_rx_desc_list_cur A parrent pointer to the current reception descritpion list + * @param[out] parent_rx_desc_list_cur A parent pointer to the current reception description list * @param[in] rx_frame_info A pointer to the information of the reception frames * @retval A struct of the current reception frame */ @@ -442,7 +654,7 @@ enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, e /** * @brief get a received frame from interrupt * - * @param[out] parent_rx_desc_list_cur the parrent pointer to the current reception descritpion list + * @param[out] parent_rx_desc_list_cur the parent pointer to the current reception description list * @param[in] rx_frame_info A pointer to the information of the reception frames * @param[in] rx_desc_count A total count of the reception descriptors * @retval A struct of the current reception frame @@ -450,7 +662,7 @@ enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, e enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count); /** - * @brief prepare for the transmission descriptors + * @brief prepare for the transmission descriptors (It will be deprecated.) * * @param[in] ptr An Ethernet peripheral base address * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames @@ -458,10 +670,43 @@ enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_l * @param[in] tx_buff_size the size of the transmission buffer * @retval a result of the transmission preparation. * 1 means that the preparation is successful. - * 0 means that the prepartion is unsuccessful. + * 0 means that the preparation is unsuccessful. */ uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size); +/** + * @brief prepare for the transmission descriptors + * + * @param[in] ptr An Ethernet peripheral base address + * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames + * @param[in] config a pointer to the control configuration for the transmission frames + * @param[in] frame_length the length of the transmission + * @param[in] tx_buff_size the size of the transmission buffer + * @retval a result of the transmission preparation. + * 1 means that the preparation is successful. + * 0 means that the preparation is unsuccessful. + */ +uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size); + +/** + * @brief prepare for the transmission descriptors with a timestamp record + * + * @param[in] ptr An Ethernet peripheral base address + * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames + * @param[in] config a pointer to the control configuration for the transmission frames + * @param[in] frame_length the length of the transmission + * @param[in] tx_buff_size the size of the transmission buffer + * @param[out] timestamp a pointer to the timestamp record of a transmitted frame + * @retval a result of the transmission preparation. + * 1 means that the preparation is successful. + * 0 means that the preparation is unsuccessful. + */ +uint32_t enet_prepare_tx_desc_with_ts_record(ENET_Type *ptr, + enet_tx_desc_t **parent_tx_desc_list_cur, + enet_tx_control_config_t *config, + uint16_t frame_length, uint16_t tx_buff_size, + enet_ptp_ts_system_t *timestamp); + /** * @brief Initialize DMA transmission descriptors in chain mode * @@ -497,25 +742,25 @@ void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config); * @brief Set a timestamp to the PTP timer * * @param[in] ptr An Ethernet peripheral base address - * @param[in] timestamp A pointer to a timestamp structure instance + * @param[in] timestamp A pointer to a update timestamp structure instance */ -void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp); +void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_update_t *timestamp); /** * @brief Get a timestamp from the PTP timer * * @param[in] ptr An Ethernet peripheral base address - * @param[out] timestamp A pointer to a timestamp structure instance + * @param[out] timestamp A pointer to a system timestamp structure instance */ -void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp); +void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_system_t *timestamp); /** * @brief Update a timestamp to the PTP timer * * @param[in] ptr An Ethernet peripheral base address - * @param[in] timeoffset A pointer to a timestamp structure instance + * @param[in] timeoffset A pointer to a update timestamp structure instance */ -void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_time_t *timeoffset); +void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_ts_update_t *timeoffset); /** * @brief Adjust the count frequency of the PTP timer @@ -551,6 +796,34 @@ hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_ */ void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg); +/** + * @brief Set the pps0 control output + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] enet_pps_ctrl_t An enum value indicating the specified pps frequency + */ +void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq); + +/** + * @brief Set a pps command for ppsx + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] cmd An enum value indicating the specified pps command + * @param[in] idx An enum value indicating the index of pps instance + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success + */ +hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx); + +/** + * @brief Set a pps config for ppsx + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] cmd An enum value indicating the specified pps config + * @param[in] idx An enum value indicating the index of pps instance + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success + */ +hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx); + #if defined __cplusplus } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h new file mode 100644 index 0000000000..4d532ad4bf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_FEMC_DRV_H +#define _HPM_FEMC_DRV_H +#include "hpm_femc_regs.h" + +/** + * @brief femc driver APIs + * @defgroup dram_interface femc driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +#define FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE (8UL) +/* @brief femc sdram column address bit width */ +#define FEMC_SDRAM_COLUMN_ADDR_12_BITS (0U) +#define FEMC_SDRAM_COLUMN_ADDR_11_BITS (1U) +#define FEMC_SDRAM_COLUMN_ADDR_10_BITS (2U) +#define FEMC_SDRAM_COLUMN_ADDR_9_BITS (3U) +#define FEMC_SDRAM_COLUMN_ADDR_8_BITS (4U) +/* @brief cas latency */ +#define FEMC_SDRAM_CAS_LATENCY_1 (1U) +#define FEMC_SDRAM_CAS_LATENCY_2 (2U) +#define FEMC_SDRAM_CAS_LATENCY_3 (3U) +/* @brief iomux options */ +#define FEMC_IO_MUX_NOT_USED (0U) +#define FEMC_IO_MUX_CSX0 (1U) +#define FEMC_IO_MUX_CSX1 (2U) +#define FEMC_IO_MUX_CSX2 (3U) +#define FEMC_IO_MUX_CSX3 (4U) +#define FEMC_IO_MUX_RDY (5U) +/* @brief sdram bank number */ +#define FEMC_SDRAM_BANK_NUM_4 (0U) +#define FEMC_SDRAM_BANK_NUM_2 (1U) +/* @brief chip select */ +#define FEMC_SDRAM_CS0 (0U) +#define FEMC_SDRAM_CS1 (1U) +/* @brief sdram port size */ +#define FEMC_SDRAM_PORT_SIZE_8_BITS (0U) +#define FEMC_SDRAM_PORT_SIZE_16_BITS (1U) +#define FEMC_SDRAM_PORT_SIZE_32_BITS (2U) + +#define FEMC_AXI_Q_COUNT (2U) +#define FEMC_AXI_Q_A (0U) +#define FEMC_AXI_Q_B (1U) +/* @brief DQS option */ +#define FEMC_DQS_INTERNAL (0U) +#define FEMC_DQS_FROM_PAD (1U) + +#define FEMC_BR_COUNT (2U) + +#define FEMC_CMD_KEY FEMC_IPCMD_KEY_SET(0xA55A) +#define FEMC_CMD_WRITE_FLAG (1UL << 31) +#define FEMC_CMD_SDRAM_READ (0x8U) +#define FEMC_CMD_SDRAM_WRITE (FEMC_CMD_WRITE_FLAG | 0x9U) +#define FEMC_CMD_SDRAM_MODE_SET (FEMC_CMD_WRITE_FLAG | 0xAU) +#define FEMC_CMD_SDRAM_ACTIVE (0xBU) +#define FEMC_CMD_SDRAM_AUTO_REFRESH (0xCU) +#define FEMC_CMD_SDRAM_SELF_REFRESH (0xDU) +#define FEMC_CMD_SDRAM_PRECHARGE (0xEU) +#define FEMC_CMD_SDRAM_PRECHARGE_ALL (0xFU) + +/* @brief sram address mode */ +#define FEMC_SRAM_AD_MUX_MODE (0U) +#define FEMC_SRAM_AD_NONMUX_MODE (3U) + +/* @brief sram adv hold state */ +#define FEMC_SRAM_ADV_HOLD_HIGH (0U) +#define FEMC_SRAM_ADV_HOLD_LOW (1U) + +/* @brief sram adv polarity */ +#define FEMC_SRAM_ADV_ACTIVE_LOW (0U) +#define FEMC_SRAM_ADV_ACTIVE_HIGH (1U) + +/* @brief sram port size */ +#define FEMC_SRAM_PORT_SIZE_8_BITS (0U) +#define FEMC_SRAM_PORT_SIZE_16_BITS (1U) + +/* @brief IO_CSX selection */ +#define FEMC_IO_CSX_SDRAM_CS1 (1U) +#define FEMC_IO_CSX_SRAM_CE (6U) + +/** + * @brief Structure for specifying the configuration of AXI queue weight + */ +typedef struct { + bool enable; /**< Enable AXI weight setting flag */ + uint8_t qos; + uint8_t age; + uint8_t slave_hit_wo_rw; + uint8_t slave_hit; /**< only available for queue A */ + uint8_t page_hit; /**< only available for queue B */ + uint8_t bank_rotation; /**< only available for queue B */ +} femc_axi_q_weight_t; + +/** + * @brief Structure for specifying the configuration of SDRAM + */ +typedef struct { + uint32_t base_address; /**< external SDRAM base address */ + uint32_t size_in_byte; /**< external SDRAM size in byte */ + uint32_t refresh_count; /**< referesh count */ + uint8_t col_addr_bits; /**< column address bit count */ + uint8_t cas_latency; /**< CAS latency */ + uint8_t cs; /**< chip select */ + uint8_t cs_mux_pin; /**< chip select mux */ + uint8_t bank_num; /**< bank number */ + uint8_t prescaler; /**< presecaler */ + uint8_t port_size; /**< SDRAM port size */ + uint8_t burst_len_in_byte; /**< 1/2/4/8 bytes */ + uint8_t cke_off_in_ns; /**< Tcks */ + uint8_t act_to_precharge_in_ns; /**< Tras */ + uint8_t precharge_to_act_in_ns; /**< Trp */ + uint8_t act_to_rw_in_ns; /**< Trcd */ + uint8_t act_to_act_in_ns; /**< Trrd */ + uint8_t refresh_to_refresh_in_ns; /**< Trc */ + uint8_t write_recover_in_ns; /**< Tdpl */ + uint8_t self_refresh_recover_in_ns; /**< Txsr */ + uint8_t refresh_recover_in_ns; /**< Txsr */ + uint8_t refresh_in_ms; /**< Tref */ + uint8_t idle_timeout_in_ns; + uint8_t data_width_in_byte; + uint8_t auto_refresh_count_in_one_burst; + uint8_t delay_cell_value; /**< Delay cell value */ +} femc_sdram_config_t; + +/** + * @brief Structure for specifying the configuration of SRAM + */ +typedef struct { + uint32_t base_address; /**< external SRAM base address */ + uint32_t size_in_byte; /**< external SRAM size in byte */ + uint8_t address_mode; /**< address mode */ + uint8_t port_size; /**< port size */ + uint8_t adv_hold_state; /**< adv hold level */ + uint8_t adv_polarity; /**< adv polarity */ + uint8_t oeh_in_ns; /**< OE high time */ + uint8_t oel_in_ns; /**< OE low time */ + uint8_t weh_in_ns; /**< WE high time */ + uint8_t wel_in_ns; /**< WE low time */ + uint8_t ah_in_ns; /**< address hold time */ + uint8_t as_in_ns; /**< address setup time */ + uint8_t ceh_in_ns; /**< chip enable hold time */ + uint8_t ces_in_ns; /**< chip enable setup time */ +} femc_sram_config_t; + +/** + * @brief Structure for specifying the configuration of FEMC + */ +typedef struct { + uint8_t dqs; /**< DQS setting */ + uint8_t cmd_timeout; /**< command timeout */ + uint8_t bus_timeout; /**< bus timeout */ + femc_axi_q_weight_t axi_q_weight[FEMC_AXI_Q_COUNT]; +} femc_config_t; + +/** + * @brief Structure for FEMC command + */ +typedef struct { + uint32_t opcode; + uint32_t data; +} femc_cmd_t; + +/* + * @brief FEMC specific status + */ +enum { + status_femc_cmd_err = MAKE_STATUS(status_group_femc, 1), +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief femc enable + * + * Enable FEMC + * + * @param[in] ptr FEMC base address + */ +static inline void femc_enable(FEMC_Type *ptr) +{ + ptr->CTRL &= ~FEMC_CTRL_DIS_MASK; +} + +/** + * @brief femc disable + * + * Disable FEMC + * + * @param[in] ptr FEMC base address + */ +static inline void femc_disable(FEMC_Type *ptr) +{ + while ((ptr->STAT0 & (uint32_t) FEMC_STAT0_IDLE_MASK) == 0) { + } + ptr->CTRL |= FEMC_CTRL_DIS_MASK; +} + +/** + * @brief femc software reset + * + * Perform software reset + * + * @param[in] ptr FEMC base address + */ +static inline void femc_sw_reset(FEMC_Type *ptr) +{ + ptr->CTRL = FEMC_CTRL_RST_MASK; + while ((ptr->CTRL & (uint32_t) FEMC_CTRL_RST_MASK) != 0) { + } +} + +/** + * @brief femc get default config + * + * Get FEMC default parameters + * + * @param[in] ptr FEMC base address + * @param[out] config femc_config_t address + */ +void femc_default_config(FEMC_Type *ptr, femc_config_t *config); + +/** + * @brief femc init controller + * + * Initialize FEMC with give femc_config_t + * + * @param[in] ptr FEMC base address + * @param[in] config femc_config_t to initialize femc + */ +void femc_init(FEMC_Type *ptr, femc_config_t *config); + +/** + * @brief femc get typical sdram config + * + * Fill out the structure of femc_sdram_config_t with typical SDRAM parameters which should work + * with most SDRAMs. + * + * @param[in] ptr FEMC base address + * @param[out] config femc_sdram_config_t sdram configuration struction to config femc + */ +void femc_get_typical_sdram_config(FEMC_Type *ptr, femc_sdram_config_t *config); + +/** + * @brief femc config sdram + * + * Configure FEMC controlling external SDRAM using parameters specified in femc_sdram_config_t + * + * @param[in] ptr FEMC base address + * @param[in] clk_in_hz femc source clock frequency in Hz + * @param[in] config femc_sdram_config_t sdram configuration struction to config femc + */ +hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_config_t *config); + +/** + * @brief femc get typical sram config + * + * Fill out the structure of femc_sram_config_t with typical SRAM parameters which should work + * with most SRAMs. + * + * @param[in] ptr FEMC base address + * @param[out] config femc_sdram_config_t sdram configuration struction to config femc + */ +void femc_get_typical_sram_config(FEMC_Type *ptr, femc_sram_config_t *config); + +/** + * @brief femc config sram + * + * Configure FEMC controlling external SRAM using parameters specified in femc_sram_config_t + * + * @param[in] ptr FEMC base address + * @param[in] clk_in_hz femc source clock frequency in Hz + * @param[in] config femc_sram_config_t sram configuration struction to config femc + */ +hpm_stat_t femc_config_sram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sram_config_t *config); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* _HPM_FEMC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h index 915f7c1727..53f520ee17 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h index c15c19b1e2..2f63a38c5e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h index fa64b0c388..e24c96c8dd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -43,7 +43,7 @@ static inline gpiom_gpio_t gpiom_get_pin_controller(GPIOM_Type *ptr, uint8_t pin_index) { return (gpiom_gpio_t)((ptr->ASSIGN[gpio_index].PIN[pin_index] - & (GPIOM_PIN_SELECT_MASK)) >> GPIOM_PIN_SELECT_SHIFT); + & (GPIOM_ASSIGN_PIN_SELECT_MASK)) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT); } /** @@ -60,8 +60,8 @@ static inline void gpiom_set_pin_controller(GPIOM_Type *ptr, gpiom_gpio_t gpio) { ptr->ASSIGN[gpio_index].PIN[pin_index] = - (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~(GPIOM_PIN_SELECT_MASK)) - | GPIOM_PIN_SELECT_SET(gpio); + (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~(GPIOM_ASSIGN_PIN_SELECT_MASK)) + | GPIOM_ASSIGN_PIN_SELECT_SET(gpio); } /** @@ -80,8 +80,8 @@ static inline bool gpiom_check_pin_visibility(GPIOM_Type *ptr, uint8_t pin_index, gpiom_gpio_t gpio) { - return (ptr->ASSIGN[gpio_index].PIN[pin_index] & ((1 << gpio) << GPIOM_PIN_HIDE_SHIFT)) - >> GPIOM_PIN_HIDE_SHIFT >> gpio == gpiom_pin_visible; + return (ptr->ASSIGN[gpio_index].PIN[pin_index] & ((1 << gpio) << GPIOM_ASSIGN_PIN_HIDE_SHIFT)) + >> GPIOM_ASSIGN_PIN_HIDE_SHIFT >> gpio == gpiom_pin_visible; } /** @@ -98,7 +98,7 @@ static inline void gpiom_enable_pin_visibility(GPIOM_Type *ptr, gpiom_gpio_t gpio) { ptr->ASSIGN[gpio_index].PIN[pin_index] = - (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_PIN_HIDE_SHIFT)); + (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_ASSIGN_PIN_HIDE_SHIFT)); } /** @@ -115,8 +115,8 @@ static inline void gpiom_disable_pin_visibility(GPIOM_Type *ptr, gpiom_gpio_t gpio) { ptr->ASSIGN[gpio_index].PIN[pin_index] = - (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_PIN_HIDE_SHIFT)) - | GPIOM_PIN_HIDE_SET(1 << gpio); + (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_ASSIGN_PIN_HIDE_SHIFT)) + | GPIOM_ASSIGN_PIN_HIDE_SET(1 << gpio); } /** @@ -133,8 +133,8 @@ static inline bool gpiom_pin_is_locked(GPIOM_Type *ptr, uint8_t gpio_index, uint8_t pin_index) { - return (ptr->ASSIGN[gpio_index].PIN[pin_index] & GPIOM_PIN_LOCK_MASK) - == GPIOM_PIN_LOCK_MASK; + return (ptr->ASSIGN[gpio_index].PIN[pin_index] & GPIOM_ASSIGN_PIN_LOCK_MASK) + == GPIOM_ASSIGN_PIN_LOCK_MASK; } /** @@ -148,7 +148,7 @@ static inline void gpiom_lock_pin(GPIOM_Type *ptr, uint8_t gpio_index, uint8_t pin_index) { - ptr->ASSIGN[gpio_index].PIN[pin_index] |= GPIOM_PIN_LOCK_MASK; + ptr->ASSIGN[gpio_index].PIN[pin_index] |= GPIOM_ASSIGN_PIN_LOCK_MASK; } #ifdef __cplusplus diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h index d661f7c311..2ba06c88df 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -31,6 +31,11 @@ #define GPTMR_CH_CAP_STAT_MASK(ch) (1 << (ch * 4 + 1)) #define GPTMR_CH_RLD_STAT_MASK(ch) (1 << (ch * 4)) +/** + * @brief GPTMR channel swsynct mask + */ +#define GPTMR_CH_GCR_SWSYNCT_MASK(ch) (1 << ch) + /** * @brief GPTMR one channel support output comparator count */ @@ -61,10 +66,10 @@ typedef enum gptmr_work_mode { * @brief GPTMR DMA request event */ typedef enum gptmr_dma_request_event { - gptmr_dma_request_on_reload = 0, - gptmr_dma_request_on_input_signal_toggle = 1, - gptmr_dma_request_on_cmp0 = 2, - gptmr_dma_request_on_cmp1 = 3, + gptmr_dma_request_on_cmp0 = 0, + gptmr_dma_request_on_cmp1 = 1, + gptmr_dma_request_on_input_signal_toggle = 2, + gptmr_dma_request_on_reload = 3, gptmr_dma_request_disabled = 0xFF, } gptmr_dma_request_event_t; @@ -138,6 +143,9 @@ static inline void gptmr_channel_update_count(GPTMR_Type *ptr, uint8_t ch_index, uint32_t value) { + if (value > 0) { + value--; + } ptr->CHANNEL[ch_index].CNTUPTVAL = GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(value); ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK; } @@ -188,21 +196,21 @@ static inline uint32_t gptmr_channel_get_counter(GPTMR_Type *ptr, { uint32_t value; switch (capture) { - case gptmr_counter_type_rising_edge: - value = (ptr->CHANNEL[ch_index].CAPPOS & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT; - break; - case gptmr_counter_type_falling_edge: - value = (ptr->CHANNEL[ch_index].CAPNEG & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT; - break; - case gptmr_counter_type_measured_period: - value = (ptr->CHANNEL[ch_index].CAPPRD & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT; - break; - case gptmr_counter_type_measured_duty_cycle: - value = (ptr->CHANNEL[ch_index].CAPDTY & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT; - break; - default: - value = (ptr->CHANNEL[ch_index].CNT & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT; - break; + case gptmr_counter_type_rising_edge: + value = (ptr->CHANNEL[ch_index].CAPPOS & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT; + break; + case gptmr_counter_type_falling_edge: + value = (ptr->CHANNEL[ch_index].CAPNEG & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT; + break; + case gptmr_counter_type_measured_period: + value = (ptr->CHANNEL[ch_index].CAPPRD & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT; + break; + case gptmr_counter_type_measured_duty_cycle: + value = (ptr->CHANNEL[ch_index].CAPDTY & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT; + break; + default: + value = (ptr->CHANNEL[ch_index].CNT & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT; + break; } return value; } @@ -295,6 +303,51 @@ static inline void gptmr_stop_counter(GPTMR_Type *ptr, uint8_t ch_index) ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CEN_MASK; } +/** + * @brief gptmr channel enable compare output + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + */ +static inline void gptmr_enable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index) +{ + ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CMPEN_MASK; +} + +/** + * @brief gptmr channel disable compare output + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + */ +static inline void gptmr_disable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index) +{ + ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CMPEN_MASK; +} + +/** + * @brief gptmr channel set capmode + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + */ +static inline void gptmr_channel_set_capmode(GPTMR_Type *ptr, uint8_t ch_index, gptmr_work_mode_t mode) +{ + ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CAPMODE_MASK) | GPTMR_CHANNEL_CR_CAPMODE_SET(mode); +} + +/** + * @brief gptmr channel get capmode + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @retval gptmr_work_mode_t enum gptmr_work_mode_capture_at_rising_edge or gptmr_work_mode_capture_at_falling_edge + */ +static inline gptmr_work_mode_t gptmr_channel_get_capmode(GPTMR_Type *ptr, uint8_t ch_index) +{ + return GPTMR_CHANNEL_CR_CAPMODE_GET(ptr->CHANNEL[ch_index].CR); +} + /** * @brief gptmr channel update comparator * @@ -305,7 +358,22 @@ static inline void gptmr_stop_counter(GPTMR_Type *ptr, uint8_t ch_index) */ static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t cmp_index, uint32_t cmp) { - ptr->CHANNEL[ch_index].CMP[cmp_index] = GPTMR_CMP_CMP_SET(cmp); + if (cmp > 0) { + cmp--; + } + ptr->CHANNEL[ch_index].CMP[cmp_index] = GPTMR_CHANNEL_CMP_CMP_SET(cmp); +} + +/** + * @brief gptmr channel get reload + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @retval RLD register value + */ +static inline uint32_t gptmr_channel_get_reload(GPTMR_Type *ptr, uint8_t ch_index) +{ + return ptr->CHANNEL[ch_index].RLD; } /** @@ -317,9 +385,24 @@ static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t c */ static inline void gptmr_channel_config_update_reload(GPTMR_Type *ptr, uint8_t ch_index, uint32_t reload) { + if (reload > 0) { + reload--; + } ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(reload); } +/** + * @brief gptmr channel get dma request event + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @retval gptmr_dma_request_event_t gptmr_dma_request_on_cmp0 or gptmr_dma_request_on_reload + */ +static inline gptmr_dma_request_event_t gptmr_channel_get_dma_request_event(GPTMR_Type *ptr, uint8_t ch_index) +{ + return GPTMR_CHANNEL_CR_DMASEL_GET(ptr->CHANNEL[ch_index].CR); +} + /** * @brief gptmr channel config * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h index f61aec179f..d62c2a100b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h index 4bf0515246..18f50a25b6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -29,6 +29,11 @@ enum { status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9), }; +/* convert data count value into CTRL[DATACNT] value map */ +/* x range from 1 to I2C_SOC_TRANSFER_COUNT_MAX */ +/* 0 for I2C_SOC_TRANSFER_COUNT_MAX */ +#define I2C_DATACNT_MAP(x) (((x) == I2C_SOC_TRANSFER_COUNT_MAX) ? 0 : x) + /** * @brief I2C CMD */ @@ -97,6 +102,18 @@ typedef enum i2c_mode { i2c_mode_fast_plus, } i2c_mode_t; +/** + * @brief I2c sequential transfer options + * @arg: i2c_frist_frame: has start signal + * @arg: i2c_next_frame: middle transfer + * @arg: i2c_last_frame: has stop signal + */ +typedef enum i2c_seq_transfer_opt { + i2c_frist_frame = 0, + i2c_next_frame, + i2c_last_frame, +} i2c_seq_transfer_opt_t; + #ifdef __cplusplus extern "C" { #endif @@ -208,6 +225,34 @@ static inline bool i2c_is_reading(I2C_Type *ptr) return !i2c_is_writing(ptr); } +/** + * @brief get i2c sda line status + * + * @param [in] ptr I2C base address + * @retval bool value + * @arg true: the sda line is high + * @arg false: the sda line is low + * + */ +static inline bool i2c_get_line_sda_status(I2C_Type *ptr) +{ + return I2C_STATUS_LINESDA_GET(ptr->STATUS); +} + +/** + * @brief get i2c scl line status + * + * @param [in] ptr I2C base address + * @retval bool value + * @arg true: the scl line is high + * @arg false: the scl line is low + * + */ +static inline bool i2c_get_line_scl_status(I2C_Type *ptr) +{ + return I2C_STATUS_LINESCL_GET(ptr->STATUS); +} + /** * @brief clear status * @@ -234,6 +279,19 @@ static inline uint32_t i2c_get_status(I2C_Type *ptr) return ptr->STATUS; } +/** + * @brief i2c get interrupts setting + * + * @details Get interrupt setting register value + * + * @param [in] ptr I2C base address + * @retval [out] uint32_t interrupt setting register value + */ +static inline uint32_t i2c_get_irq_setting(I2C_Type *ptr) +{ + return ptr->INTEN; +} + /** * @brief disable interrupts * @@ -260,6 +318,30 @@ static inline void i2c_enable_irq(I2C_Type *ptr, uint32_t mask) ptr->INTEN |= mask; } +/** + * @brief disable auto ack + * + * @details Disable I2C auto generates proper acknowledgements for each byte received + * + * @param [in] ptr I2C base address + */ +static inline void i2c_disable_auto_ack(I2C_Type *ptr) +{ + ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; +} + +/** + * @brief enable auto ack + * + * @details Enable I2C auto generates proper acknowledgements for each byte received + * + * @param [in] ptr I2C base address + */ +static inline void i2c_enable_auto_ack(I2C_Type *ptr) +{ + ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED; +} + /** * @brief enable 10 bit address mode * @@ -293,6 +375,7 @@ hpm_stat_t i2c_init_master(I2C_Type *ptr, * @brief I2C master write data to specific address of certain slave device * * @details Write to certain I2C device at specific address within that device + * @note the sum of addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] ptr I2C base address * @param [in] device_address I2C slave address @@ -305,7 +388,7 @@ hpm_stat_t i2c_init_master(I2C_Type *ptr, hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address, uint8_t *addr, - uint8_t addr_size_in_byte, + uint32_t addr_size_in_byte, uint8_t *buf, const uint32_t size_in_byte); @@ -313,26 +396,28 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, * @brief I2C master read data from specific address of certain slave device * * @details Read fram certain I2C device at specific address within that device + * @note both addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] ptr I2C base address * @param [in] device_address I2C slave address * @param [in] addr address in that I2C device * @param [in] addr_size_in_byte I2C address in byte * @param [out] buf pointer of the buffer to receive data read from the device - * @param [in] size size of data to be read in bytes + * @param [in] size_in_byte size of data to be read in bytes * @retval hpm_stat_t: status_success if reading is completed without any error */ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, uint8_t *addr, - uint8_t addr_size_in_byte, + uint32_t addr_size_in_byte, uint8_t *buf, - const uint32_t size); + const uint32_t size_in_byte); /** * @brief I2C master write data to certain slave device * * @details Write data to I2C device + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] ptr I2C base address * @param [in] device_address I2C slave address @@ -349,28 +434,33 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, * @brief I2C master start write data by DMA * * @details Write data to I2C device by DMA + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] i2c_ptr I2C base address * @param [in] device_address I2C slave address * @param [in] size size of data to be sent in bytes + * @retval hpm_stat_t status_success if starting transmission without any error */ -void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); +hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); /** * @brief I2C master start read data by DMA * * @details Read data to I2C device by DMA + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] i2c_ptr I2C base address * @param [in] device_address I2C slave address * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t status_success if starting transmission without any error */ -void i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); +hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); /** * @brief I2C master read data from certain slave device * * @details Read data from I2C device + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] ptr I2C base address * @param [in] device_address I2C slave address @@ -400,6 +490,7 @@ hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, * @brief I2C slave read data * * @details Read data at slave mode + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] ptr I2C base address * @param [in] buf pointer of the buffer to store data read from device @@ -412,6 +503,7 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint8_t *buf, const uint32_t size); * @brief I2C slave write data * * @details Write data at slave mode. + * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX * * @param [in] ptr I2C base address * @param [in] buf pointer of the buffer to store data sent from device @@ -454,8 +546,81 @@ static inline void i2c_dma_disable(I2C_Type *ptr) * * @param [in] ptr I2C base address * @param [in] size size of data in bytes + * @retval hpm_stat_t status_success if configuring transmission without any error */ -void i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size); +hpm_stat_t i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size); + +/** + * @brief I2C write byte into FIFO + * + * @param ptr [in] ptr I2C base address + * @param data [in] byte to ne sent + */ +static inline void i2c_write_byte(I2C_Type *ptr, uint8_t data) +{ + ptr->DATA = I2C_DATA_DATA_SET(data); +} + +/** + * @brief I2C read byte into FIFO + * + * @param ptr [in] ptr I2C base address + * @return uint8_t read byte + */ +static inline uint8_t i2c_read_byte(I2C_Type *ptr) +{ + return (uint8_t)I2C_DATA_DATA_GET(ptr->DATA); +} + +/** + * @brief I2C get direction + * + * @note The same value has different meanings in master and slave modes + * + * @param ptr [in] ptr I2C base address + * @return uint8_t direction value + */ +static inline uint8_t i2c_get_direction(I2C_Type *ptr) +{ + return (uint8_t)I2C_CTRL_DIR_GET(ptr->CTRL); +} + +/** + * @brief I2C master configure transfer setting + * + * @param i2c_ptr [in] ptr I2C base address + * @param device_address [in] I2C slave address + * @param size [in] size of data to be transferred in bytes + * @param read [in] true for receive, false for transmit + * @retval hpm_stat_t status_success if configuring transmission without any error + */ +hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read); + +/** + * @brief sequential transmit in master I2C mode an amount of data in blocking + * + * @param i2c_ptr [in] ptr I2C base address + * @param device_address [in] I2C slave address + * @param [in] buf pointer of the buffer to store data sent from device + * @param [in] size size of data to be sent in bytes + * @param [in] opt I2c sequential transfer options + * @retval hpm_stat_t status_success if transmit is completed without any error + */ +hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt); + +/** + * @brief sequential receive in master I2C mode an amount of data in blocking + * + * @param i2c_ptr [in] ptr I2C base address + * @param device_address [in] I2C slave address + * @param [in] buf pointer of the buffer to store data sent from device + * @param [in] size size of data to be sent in bytes + * @param [in] opt I2c sequential transfer options + * @retval hpm_stat_t status_success if receive is completed without any error + */ +hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt); /** * @} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h index 91e99f6315..7ff4be0125 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -22,13 +22,22 @@ #define I2S_PROTOCOL_RIGHT_JUSTIFIED (2U) #define I2S_PROTOCOL_PCM (3U) -#define I2S_AUDIO_DEPTH_16_BITS (0U) -#define I2S_AUDIO_DEPTH_24_BITS (1U) -#define I2S_AUDIO_DEPTH_32_BITS (2U) -#define I2S_AUDIO_DEPTH_IS_NOT_VALID(x) ((x) > I2S_AUDIO_DEPTH_32_BITS) +/** + * @brief I2S audio depth + */ +enum { + i2s_audio_depth_16_bits = 16, + i2s_audio_depth_24_bits = 24, + i2s_audio_depth_32_bits = 32, +}; -#define I2S_CHANNEL_LENGTH_16_BITS (0U) -#define I2S_CHANNEL_LENGTH_32_BITS (1U) +/** + * @brief I2S channel length + */ +enum { + i2s_channel_length_16_bits = 16, + i2s_channel_length_32_bits = 32, +}; /** * @brief I2S stereo/mono channel diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h index 3e5ab32d89..2b6399559f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -19,12 +19,12 @@ * @{ */ -/** - * @brief I2S IRQ mask - */ -#define I2S_IRQ_TX_FIFO_EMPTY I2S_CTRL_TXDNIE_MASK -#define I2S_IRQ_RX_FIFO_DATA_AVAILABLE I2S_CTRL_RXDAIE_MASK -#define I2S_IRQ_ERROR I2S_CTRL_ERRIE_MASK +/* i2s channel slot mask */ +#define I2S_CHANNEL_SLOT_MASK(x) (1U << (x)) +/* convert audio depth value into CFGR[DATASIZ] value map */ +#define I2S_CFGR_DATASIZ(x) ((x - 16) >> 3) +/* convert channel length value into CFGR[CHSIZ] value map */ +#define I2S_CFGR_CHSIZ(x) ((x - 16) >> 4) /** * @brief I2S data line @@ -35,9 +35,6 @@ #define I2S_DATA_LINE_3 (3U) #define I2S_DATA_LINE_MAX I2S_DATA_LINE_3 -/* i2s channel slot mask */ -#define I2S_CHANNEL_SLOT_MASK(x) ((1U << (x)) & I2S_RXDSLOT_EN_MASK) - /** * @brief I2S config */ @@ -64,13 +61,26 @@ typedef struct i2x_transfer_config { bool enable_tdm_mode; uint8_t channel_num_per_frame; uint8_t channel_length; /* 16-bit or 32-bit */ - uint8_t audio_depth; /* 8-bit, 24-bit, 32-bit */ + uint8_t audio_depth; /* 16-bit, 24-bit, 32-bit */ bool master_mode; uint8_t protocol; uint8_t data_line; uint32_t channel_slot_mask; } i2s_transfer_config_t; +typedef enum { + i2s_tx_fifo_threshold_irq_mask = I2S_CTRL_TXDNIE_MASK, + i2s_rx_fifo_threshold_irq_mask = I2S_CTRL_RXDAIE_MASK, + i2s_fifo_error_irq_mask = I2S_CTRL_ERRIE_MASK, /*CTRL |=I2S_CTRL_TX_DMA_EN_MASK; + ptr->CTRL |= I2S_CTRL_TX_DMA_EN_MASK; } /** @@ -186,7 +196,7 @@ static inline void i2s_disable_tx_dma_request(I2S_Type *ptr) */ static inline void i2s_enable_rx_dma_request(I2S_Type *ptr) { - ptr->CTRL |=I2S_CTRL_RX_DMA_EN_MASK; + ptr->CTRL |= I2S_CTRL_RX_DMA_EN_MASK; } /** @@ -228,7 +238,7 @@ static inline void i2s_disable_irq(I2S_Type *ptr, uint32_t mask) */ static inline void i2s_enable(I2S_Type *ptr) { - ptr->CTRL |= ~I2S_CTRL_I2S_EN_MASK; + ptr->CTRL |= I2S_CTRL_I2S_EN_MASK; } /** @@ -293,7 +303,8 @@ static inline void i2s_disable_tx(I2S_Type *ptr, uint8_t tx_mask) static inline void i2s_clear_tx_fifo(I2S_Type *ptr) { ptr->CTRL |= I2S_CTRL_TXFIFOCLR_MASK; - while (ptr->CTRL & I2S_CTRL_TXFIFOCLR_MASK) {} + while (ptr->CTRL & I2S_CTRL_TXFIFOCLR_MASK) { + } } /** @@ -304,7 +315,8 @@ static inline void i2s_clear_tx_fifo(I2S_Type *ptr) static inline void i2s_clear_rx_fifo(I2S_Type *ptr) { ptr->CTRL |= I2S_CTRL_RXFIFOCLR_MASK; - while (ptr->CTRL & I2S_CTRL_RXFIFOCLR_MASK) {} + while (ptr->CTRL & I2S_CTRL_RXFIFOCLR_MASK) { + } } /** @@ -362,7 +374,7 @@ static inline uint32_t i2s_get_tx_fifo_level(I2S_Type *ptr) */ static inline uint32_t i2s_get_tx_line_fifo_level(I2S_Type *ptr, uint8_t line) { - return i2s_get_tx_fifo_level(ptr) & (0xFF << (line << 3)); + return (i2s_get_tx_fifo_level(ptr) & (0xFF << (line << 3))) >> (line << 3); } /** @@ -387,7 +399,49 @@ static inline uint32_t i2s_get_rx_fifo_level(I2S_Type *ptr) */ static inline uint32_t i2s_get_rx_line_fifo_level(I2S_Type *ptr, uint8_t line) { - return i2s_get_rx_fifo_level(ptr) & (0xFF << (line << 3)); + return (i2s_get_rx_fifo_level(ptr) & (0xFF << (line << 3))) >> (line << 3); +} + +/** + * @brief Check I2S data line status + * + * @param[in] ptr I2S base address + * @param[in] line I2S data line + * + * @retval i2s_data_line_rx_fifo_avail data in rx fifo >= threshold + * @retval i2s_data_line_tx_fifo_avail data in tx fifo <= threshold + * @retval i2s_data_line_rx_fifo_overrun rx fifo overrun occured + * @retval i2s_data_line_tx_fifo_underrun tx fifo underrun occured + */ +static inline uint32_t i2s_check_data_line_status(I2S_Type *ptr, uint8_t line) +{ + volatile uint32_t reg_val = ptr->STA; + uint32_t bit_mask; + uint32_t stat = 0; + + bit_mask = 1 << (I2S_STA_RX_DA_SHIFT + line); + if ((bit_mask & reg_val) != 0) { + stat |= i2s_data_line_rx_fifo_avail; + } + + bit_mask = 1 << (I2S_STA_TX_DN_SHIFT + line); + if ((bit_mask & reg_val) != 0) { + stat |= i2s_data_line_tx_fifo_avail; + } + + bit_mask = 1 << (I2S_STA_RX_OV_SHIFT + line); + if ((bit_mask & reg_val) != 0) { + stat |= i2s_data_line_rx_fifo_overrun; + ptr->STA = bit_mask; /* clear flag: W1C*/ + } + + bit_mask = 1 << (I2S_STA_TX_UD_SHIFT + line); + if ((bit_mask & reg_val) != 0) { + stat |= i2s_data_line_tx_fifo_underrun; + ptr->STA = bit_mask; /* clear flag: W1C*/ + } + + return stat; } /** @@ -422,6 +476,14 @@ static inline void i2s_stop_transfer(I2S_Type *ptr) */ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); +/** + * @brief I2S config tx for slave + * + * @param [in] ptr I2S base address + * @param [in] config i2s_transfer_config_t + */ +hpm_stat_t i2s_config_tx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); + /** * @brief I2S config rx * @@ -432,6 +494,15 @@ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config */ hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); +/** + * @brief I2S config rx for slave + * + * @param [in] ptr I2S base address + * @param [in] config i2s_transfer_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t i2s_config_rx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); + /** * @brief I2S config transfer * @@ -442,25 +513,64 @@ hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config */ hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); +/** + * @brief I2S config transfer for slave + * + * @param [in] ptr I2S base address + * @param [in] config i2s_transfer_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t i2s_config_transfer_slave(I2S_Type *ptr, i2s_transfer_config_t *config); + /** * @brief I2S send data * * @param [in] ptr I2S base address * @param [in] tx_line_index data line - * @param [in] src source data buff - * @param [in] size data size + * @param [in] data data to be written */ -uint32_t i2s_send_data(I2S_Type *ptr, uint8_t tx_line_index, uint32_t *src, uint32_t size); +static inline void i2s_send_data(I2S_Type *ptr, uint8_t tx_line_index, uint32_t data) +{ + ptr->TXD[tx_line_index] = data; +} /** * @brief I2S receive data * * @param [in] ptr I2S base address * @param [in] rx_line_index data line + * @param [out] data point to store data address + */ +static inline void i2s_receive_data(I2S_Type *ptr, uint8_t rx_line_index, uint32_t *data) +{ + *data = ptr->RXD[rx_line_index]; +} + +/** + * @brief I2S send data in buff + * + * @param [in] ptr I2S base address + * @param [in] tx_line_index data line + * @param [in] samplebits audio data width + * @param [in] src source data buff + * @param [in] size data size + * + * @retval I2S sent data size in byte + */ +uint32_t i2s_send_buff(I2S_Type *ptr, uint8_t tx_line_index, uint8_t samplebits, uint8_t *src, uint32_t size); + +/** + * @brief I2S receive data in buff + * + * @param [in] ptr I2S base address + * @param [in] rx_line_index data line + * @param [in] samplebits audio data width * @param [out] dst target data buff * @param [in] size data size + * + * @retval I2S sent data size in byte */ -uint32_t i2s_receive_data(I2S_Type *ptr, uint8_t rx_line_index, uint32_t *dst, uint32_t size); +uint32_t i2s_receive_buff(I2S_Type *ptr, uint8_t rx_line_index, uint8_t samplebits, uint8_t *dst, uint32_t size); /** * @brief I2S get default config diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h index b32e4b3547..f7e3ed9e20 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -29,7 +29,7 @@ /** * @brief byte order in a word */ -#define JPEG_BYTE_ORDER_3210 (0U) /**< CAN Receive event *//* no order change, {A3, A2, A1, A0} */ +#define JPEG_BYTE_ORDER_3210 (0U) /**< no order change, {A3, A2, A1, A0} */ #define JPEG_BYTE_ORDER_2301 (1U) /**< order change, {A2, A3, A0, A1} */ #define JPEG_BYTE_ORDER_1032 (2U) /**< order change, {A1, A0, A2, A3} */ #define JPEG_BYTE_ORDER_0123 (3U) /**< order change, {A0, A1, A2, A3} */ @@ -37,10 +37,7 @@ /** * @brief jpeg pixel conversion format */ -#define JPEG_PIXEL_FORMAT_AS_ORIGIN (0U) -#define JPEG_PIXEL_FORMAT_ARGB8888 (1U) -#define JPEG_PIXEL_FORMAT_RGB565 (2U) -#define JPEG_PIXEL_FORMAT_YUV422H1P (3U) + /** * @brief jpeg data format definition @@ -61,6 +58,13 @@ typedef struct { uint8_t vc:2; /**< bit: 7-6 --> Vertical c component */ } jpeg_sampling_t; +typedef struct { + uint8_t pixel_width; + uint8_t ipath; + uint8_t opath; + bool is_rgb; +} jpeg_pixel_t; + /** * @brief jpeg encoding and decoding configuration parameters * @arg bit: 31-27 --> name @@ -76,15 +80,24 @@ typedef enum jpeg_table { jpeg_table_huffsymb = 0x101506, /**< definition Huffman SYMB mem values */ } jpeg_table_t; +typedef enum jpeg_pixel_format { + jpeg_pixel_format_argb8888 = 0, + jpeg_pixel_format_rgb565, + jpeg_pixel_format_yuv422h1p, + jpeg_pixel_format_yuv422h2p, + jpeg_pixel_format_yuv420, + jpeg_pixel_format_y8, +} jpeg_pixel_format_t; + /** * @brief jpeg encoding and decoding configuration parameters */ typedef struct { uint8_t jpeg_format; /**< supported jpeg format */ - uint8_t in_pixel_format; /**< input pixel format */ - uint8_t out_pixel_format; /**< output pixel format */ - uint8_t byte_order; /**< byte order */ - bool enable_csc; /**< enable color space covertion */ + jpeg_pixel_format_t in_pixel_format; + jpeg_pixel_format_t out_pixel_format; + uint8_t in_byte_order; /**< byte order */ + uint8_t out_byte_order; /**< byte order */ bool enable_ycbcr; /**< enable YCbCr or YUV */ uint16_t width_in_pixel; /**< Image width register*/ uint16_t height_in_pixel; /**< Image height register*/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h index 6d75a3805c..dbf9512459 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h new file mode 100644 index 0000000000..b9cf437a79 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_LIN_DRV_H +#define HPM_LIN_DRV_H + +#include +#include "hpm_common.h" +#include "hpm_lin_regs.h" +#include "hpm_soc_feature.h" + +/** bit4 and bit5 encode data length in ID */ +#define LIN_ID_DATA_LEN_SHIFT 4U +#define LIN_ID_DATA_LEN_MASK 0x30U +#define LIN_ID_DATA_LEN_GET(x) (((uint8_t)(x) & LIN_ID_DATA_LEN_MASK) >> LIN_ID_DATA_LEN_SHIFT) + +/** + * @brief LIN driver APIs + * @defgroup lin_interface LIN driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief data length in ID bit4 and bit5 + */ +typedef enum { + id_data_length_2bytes, + id_data_length_2bytes_2, /**< both 0 and 1 represent 2 bytes */ + id_data_length_4bytes, + id_data_length_8bytes +} lin_id_data_length_t; + +/** + * @brief bus inactivity tome to go to sleep + */ +typedef enum { + bus_inactivity_time_4s, + bus_inactivity_time_6s, + bus_inactivity_time_8s, + bus_inactivity_time_10s +} lin_bus_inactivity_time_t; + +/** + * @brief wakeup repeat time + */ +typedef enum { + wakeup_repeat_time_180ms, + wakeup_repeat_time_200ms, + wakeup_repeat_time_220ms, + wakeup_repeat_time_240ms +} lin_wakeup_repeat_time_t; + +typedef struct { + uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ + uint32_t baudrate; /**< Baudrate */ +} lin_timing_t; + +/** + * @brief LIN config + */ +typedef struct { + uint8_t id; /**< ID */ + uint8_t *data_buff; /**< data buff */ + bool data_length_from_id; /**< data length should be decoded from the identifier or not) */ + uint8_t data_length; /**< used when data_length_from_id is false */ + bool enhanced_checksum; /**< true for enhanced checksum; false for classic checksum */ + bool transmit; /**< true for transmit operation; false for receive operation */ + /* bool start; */ /**< true for start operation; false for only configuration */ +} lin_trans_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief lin get STATE register value + * + * @param [in] ptr lin base address + * @return uint8_t STATE register value + */ +static inline uint8_t lin_get_status(LIN_Type *ptr) +{ + return ptr->STATE; +} + +/** + * @brief lin reset interrupt + * + * @param ptr lin base address + */ +static inline void lin_reset_interrupt(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_RESET_INT_MASK; +} + +/** + * @brief lin reset error + * + * @param ptr lin base address + */ +static inline void lin_reset_error(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_RESET_ERROR_MASK; +} + +/** + * @brief lin wakeup + * + * @param ptr lin base address + */ +static inline void lin_wakeup(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_WAKEUP_REQ_MASK; +} + +/** + * @brief lin sleep + * + * @param ptr lin base address + */ +static inline void lin_sleep(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_SLEEP_MASK; +} + +/** + * @brief lin slave stop + * + * @param ptr lin base address + */ +static inline void lin_slave_stop(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_STOP_MASK; +} + +/** + * @brief lin slave ack + * + * @param ptr lin base address + */ +static inline void lin_slave_ack(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; +} + +/** + * @brief lin slave set bus inactivity time + * + * @param ptr lin base address + * @param time lin_bus_inactivity_time_t + */ +static inline void lin_slave_set_bus_inactivity_time(LIN_Type *ptr, lin_bus_inactivity_time_t time) +{ + ptr->TV |= LIN_TV_BUS_INACTIVITY_TIME_SET(time); +} + +/** + * @brief lin slave set wakeup repeat time + * + * @param ptr lin base address + * @param time lin_wakeup_repeat_time_t + */ +static inline void lin_slave_set_wakeup_repeat_time(LIN_Type *ptr, lin_wakeup_repeat_time_t time) +{ + ptr->TV |= LIN_TV_WUP_REPEAT_TIME_SET(time); +} + +/** + * @brief lin set mode + * + * @param ptr lin base address + * @param master true for master mode, false for slave mode + */ +static inline void lin_set_mode(LIN_Type *ptr, bool master) +{ + if (master) { + ptr->TV |= LIN_TV_MASTER_MODE_MASK; + } else { + ptr->TV &= ~LIN_TV_MASTER_MODE_MASK; + } +} + +/** + * @brief lin get data value in byte + * + * @param ptr lin base address + * @param index byte index + * @return uint8_t byte value + */ +static inline uint8_t lin_get_data_byte(LIN_Type *ptr, uint8_t index) +{ + return ptr->DATABYTE[index]; +} + +/** + * @brief lin write data value in byte + * + * @param ptr lin base address + * @param index byte index + * @param data byte value + */ +static inline void lin_write_data_byte(LIN_Type *ptr, uint8_t index, uint8_t data) +{ + ptr->DATABYTE[index] = data; +} + +/** + * @brief lin active status + * + * @param ptr lin base address + * @return bool true for active, false for inactive + */ +static inline bool lin_is_active(LIN_Type *ptr) +{ + return ((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK) ? true : false; +} + +/** + * @brief lin complete status + * + * @param ptr lin base address + * @return bool true for complete, false for incomplete + */ +static inline bool lin_is_complete(LIN_Type *ptr) +{ + return ((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK) ? true : false; +} + +/** + * @brief lin get ID + * + * @param ptr lin base address + * @return uint8_t ID value + */ +static inline uint8_t lin_get_id(LIN_Type *ptr) +{ + return ptr->ID; +} + +/** + * @brief lin configure timing on master mode + * + * @param ptr lin base address + * @param timing lin_timing_t + * @return hpm_stat_t + */ +hpm_stat_t lin_master_configure_timing(LIN_Type *ptr, lin_timing_t *timing); + +/** + * @brief lin config timing on slave mode + * + * @param ptr lin base address + * @param src_freq_in_hz source frequency + * @return hpm_stat_t + */ +hpm_stat_t lin_slave_configure_timing(LIN_Type *ptr, uint32_t src_freq_in_hz); + +/** + * @brief lin transfer on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_master_transfer(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin transfer on slave mode + * + * @note call this function after lin generate data request interrupt + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_slave_transfer(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief get data length + * + * @note data length is determined by DATA_LEN register and ID + * + * @param ptr lin base address + * @return uint8_t data length + */ +uint8_t lin_get_data_length(LIN_Type *ptr); + +/** + * @brief lin send data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_sent(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_receive(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin send data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_sent(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_receive(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_LIN_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h index 1c9c15b993..4f54508a1b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -143,7 +143,7 @@ static inline hpm_stat_t mbx_send_fifo(MBX_Type *ptr, uint32_t *msg, uint32_t co { uint32_t i; hpm_stat_t status = status_success; - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { if (ptr->SR & MBX_SR_TFMA_MASK) { ptr->TXWRD[0] = MBX_TXWRD_TXFIFO_SET(*(msg + i)); count--; @@ -174,7 +174,7 @@ static inline hpm_stat_t mbx_retrieve_fifo(MBX_Type *ptr, uint32_t *msg, uint32_ { uint32_t i; hpm_stat_t status = status_success; - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { if (ptr->SR & MBX_SR_RFMA_MASK) { *(msg + i) = (ptr->RXWRD[0] & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT; count--; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h new file mode 100644 index 0000000000..70b24f8dff --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h @@ -0,0 +1,1577 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_MCAN_DRV_H +#define HPM_MCAN_DRV_H + +#include "hpm_common.h" +#include "hpm_mcan_regs.h" +#include "hpm_mcan_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @brief MCAN driver APIs +* @defgroup mcan_interface MCAN driver APIs +* @ingroup mcan_interfaces +* @{ +* +*/ + + +enum { + status_mcan_filter_index_out_of_range = MAKE_STATUS(status_group_mcan, 0), + status_mcan_rxfifo_empty, + status_mcan_rxfifo_full, + status_mcan_txbuf_full, + status_mcan_txfifo_full, + status_mcan_rxfifo0_busy, + status_mcan_rxfifo1_busy, + status_mcan_txbuf_index_out_of_range, + status_mcan_rxbuf_index_out_of_range, + status_mcan_rxbuf_empty, + status_mcan_tx_evt_fifo_empty, + status_mcan_timestamp_not_exist, + status_mcan_ram_out_of_range, +}; + +/** + * @brief CAN Interrupt Mask + */ +#define MCAN_INT_ACCESS_TO_RESERVED_ADDR MCAN_IR_ARA_MASK /*!< Access to Reserved Address */ +#define MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE MCAN_IR_PED_MASK /*!< Protocol Error Happened at Data Phase */ +#define MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE MCAN_IR_PEA_MASK /*!< Protocol Error Happened at Arbitration Phase */ +#define MCAN_INT_WATCHDOG_INT MCAN_IR_WDI_MASK /*!< Watchdog interrupt */ + +#define MCAN_INT_BUS_OFF_STATUS MCAN_IR_BO_MASK /*!< Bus-off State Change */ +#define MCAN_INT_WARNING_STATUS MCAN_IR_EW_MASK /*!< Error Warning State Change */ +#define MCAN_INT_ERROR_PASSIVE MCAN_IR_EP_MASK /*!< Error Passive State Change */ +#define MCAN_INT_ERROR_LOGGING_OVERFLOW MCAN_IR_ELO_MASK /*!< Error Logging Overflow */ +#define MCAN_INT_BIT_ERROR_UNCORRECTED MCAN_IR_BEU_MASK /*!< Bit Error was not corrected */ +#define MCAN_INT_BIT_ERROR_CORRECTED MCAN_IR_BEC_MASK /*!< Bit Error was corrected */ + +#define MCAN_INT_MSG_STORE_TO_RXBUF MCAN_IR_DRX_MASK /*!< Message was stored to RX Buffer */ +#define MCAN_INT_TIMEOUT_OCCURRED MCAN_IR_TOO_MASK /*!< Timeout Interrupt */ +#define MCAN_INT_MSG_RAM_ACCESS_FAILURE MCAN_IR_MRAF_MASK /*!< Message RAM Access Failure */ +#define MCAN_INT_TIMESTAMP_WRAPAROUND MCAN_IR_TSW_MASK /*!< Timestamp Counter Wrap Around */ + +#define MCAN_INT_TX_EVT_FIFO_EVT_LOST MCAN_IR_TEFL_MASK /*!< TX Event FIFO Element Lost */ +#define MCAN_INT_TX_EVT_FIFO_FULL MCAN_IR_TEFF_MASK /*!< TX Event FIFO Full */ +#define MCAN_INT_TX_EVT_FIFO_WMK_REACHED MCAN_IR_TEFW_MASK /*!< TX Event FIFO Watermark Reached */ +#define MCAN_INT_TX_EVT_FIFO_NEW_ENTRY MCAN_IR_TEFN_MASK /*!< TX Event FIFO New Entry */ + +#define MCAN_INT_TXFIFO_EMPTY MCAN_IR_TFE_MASK /*!< TX FIFO Empty */ +#define MCAN_INT_TX_CANCEL_FINISHED MCAN_IR_TCF_MASK /*!< Transmission Cancellation Finished */ +#define MCAN_INT_TX_COMPLETED MCAN_IR_TC_MASK /*!< Transmission Completed */ +#define MCAN_INT_HIGH_PRIORITY_MSG MCAN_IR_HPM_MASK /*!< High Priority Message */ + +#define MCAN_INT_RXFIFO1_MSG_LOST MCAN_IR_RF1L_MASK /*!< RX FIFO0 Message Lost */ +#define MCAN_INT_RXFIFO1_FULL MCAN_IR_RF1F_MASK /*!< RX FIFO1 Full */ +#define MCAN_INT_RXFIFO1_WMK_REACHED MCAN_IR_RF1W_MASK /*!< RX FIFO1 Watermark Reached */ +#define MCAN_INT_RXFIFO1_NEW_MSG MCAN_IR_RF1N_MASK /*!< RX FIFO1 New Message */ + +#define MCAN_INT_RXFIFO0_MSG_LOST MCAN_IR_RF0L_MASK /*!< RX FIFO0 Message Lost */ +#define MCAN_INT_RXFIFO0_FULL MCAN_IR_RF0F_MASK /*!< RX FIFO0 Full */ +#define MCAN_INT_RXFIFO0_WMK_REACHED MCAN_IR_RF0W_MASK /*!< RX FIFO0 Watermark Reached */ +#define MCAN_INT_RXFIFI0_NEW_MSG MCAN_IR_RF0N_MASK /*!< RX FIFO0 New Message */ + +/** + * @brief MCAN Receive Event Flags + */ +#define MCAN_EVENT_RECEIVE (MCAN_INT_RXFIFI0_NEW_MSG | MCAN_INT_RXFIFO1_NEW_MSG | MCAN_INT_MSG_STORE_TO_RXBUF) + +/** + * @brief MCAN Transmit Event Flags + */ +#define MCAN_EVENT_TRANSMIT (MCAN_INT_TX_COMPLETED) +/** + * @brief MCAN Error Event Flags + */ +#define MCAN_EVENT_ERROR (MCAN_INT_BUS_OFF_STATUS | MCAN_INT_WARNING_STATUS \ + | MCAN_INT_ERROR_PASSIVE | MCAN_INT_BIT_ERROR_UNCORRECTED) + +/** + * @brief Maximum Transmission Retry Count + */ +#define MCAN_TX_RETRY_COUNT_MAX (10000000UL) +/** + * @brief Maximum Receive Wait Retry Count + */ +#define MCAN_RX_RETRY_COUNT_MAX (80000000UL) + +/*********************************************************************************************************************** + * @brief Default CAN RAM definitions + **********************************************************************************************************************/ +#define MCAN_RAM_WORD_SIZE (640U) /*!< RAM WORD Size */ +/* CAN Filter Element Size Definitions */ +#define MCAN_FILTER_ELEM_STD_ID_SIZE (4U) /*!< Standard Filter Element Size in Bytes */ +#define MCAN_FILTER_ELEM_EXT_ID_SIZE (8U) /*!< Extended Filter Element SIze in Bytes */ +#define MCAN_STD_FILTER_ELEM_SIZE_MAX (128U) /*!< Maximum Standard Filter Element Count */ +#define MCAN_EXT_FILTER_ELEM_SIZE_MAX (64U) /*!< Maximum Extended Filter Element Count */ +/* MCAN Default Field Size Definitions for CAN2.0 */ +#define MCAN_TXRX_ELEM_SIZE_CAN_MAX (4U * sizeof(uint32_t)) +#define MCAN_FILTER_SIZE_CAN_DEFAULT (32U) +#define MCAN_TXBUF_SIZE_CAN_DEFAULT (32U) +#define MCAN_RXFIFO_SIZE_CAN_DEFAULT (32U) +#define MCAN_RXBUF_SIZE_CAN_DEFAULT (16U) +/* MCAN Default Field Size Definitions for CANFD */ +#define MCAN_TXRX_ELEM_SIZE_CANFD_MAX (18U * sizeof(uint32_t)) +#define MCAN_FILTER_SIZE_CANFD_DEFAULT (16U) +#define MCAN_TXBUF_SIZE_CANFD_DEFAULT (8U) +#define MCAN_RXFIFO_SIZE_CANFD_DEFAULT (8U) +#define MCAN_RXBUF_SIZE_CANFD_DEFAULT (4U) + +#define MCAN_TXEVT_ELEM_SIZE (8U) + +/** + * @brief CAN Bit Timing Parameters + */ +typedef struct mcan_bit_timing_param_struct { + uint16_t prescaler; /*!< Data Bit Rate Prescaler */ + uint16_t num_seg1; /*!< Time segment before sample point (including prop_seg and phase_sge1 */ + uint16_t num_seg2; /*!< Time segment after sample point */ + uint8_t num_sjw; /*!< Data (Re)Synchronization Jump Width */ + bool enable_tdc; /*!< Enable TDC flag, for CANFD data bit timing only */ +} mcan_bit_timing_param_t; + +/** + * @brief CAN Bit Timing Options + */ +typedef enum mcan_bit_timing_option { + mcan_bit_timing_can2_0, /**< CAN 2.0 bit timing option */ + mcan_bit_timing_canfd_nominal, /**< CANFD nominal timing option */ + mcan_bit_timing_canfd_data, /**< CANFD data timing option */ +} mcan_bit_timing_option_t; + +/** + * @brief CAN Message Header Size + */ +#define MCAN_MESSAGE_HEADER_SIZE_IN_BYTES (8U) +#define MCAN_MESSAGE_HEADER_SIZE_IN_WORDS (2U) + +/** + * @brief CAN Transmit Message Frame + * + * @note Users need to pay attention to the CAN Identifier settings + * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used + * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used + */ +typedef struct mcan_tx_message_struct { + union { + struct { + uint32_t ext_id: 29; /*!< Extended CAN Identifier */ + uint32_t rtr: 1; /*!< Remote Transmission Request */ + uint32_t use_ext_id: 1; /*!< Extended Identifier */ + uint32_t error_state_indicator: 1; /*!< Error State Indicator */ + }; + struct { + uint32_t : 18; + uint32_t std_id: 11; /*!< Standard CAN Identifier */ + uint32_t : 3; + }; + }; + struct { + uint32_t : 8; + uint32_t message_marker_h: 8; /*!< Message Marker[15:8] */ + uint32_t dlc: 4; /*!< Data Length Code */ + uint32_t bitrate_switch: 1; /*!< Bit Rate Switch */ + uint32_t canfd_frame: 1; /*!< CANFD frame */ + uint32_t timestamp_capture_enable: 1; /*!< Timestamp Capture Enable for TSU */ + uint32_t event_fifo_control: 1; /*!< Event FIFO control */ + uint32_t message_marker_l: 8; /*!< Message Marker[7:0] */ + }; + union { + uint8_t data_8[64]; /*!< Data buffer as byte array */ + uint32_t data_32[16]; /*!< Data buffer as word array */ + }; +} mcan_tx_frame_t; + +/** + * @brief CAN Receive Message Frame + * + * @note Users need to pay attention to the CAN Identifier settings + * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used + * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used + */ +typedef struct mcan_rx_message_struct { + union { + struct { + uint32_t ext_id: 29; /*!< Extended CAN Identifier */ + uint32_t rtr: 1; /*!< Remote Frame Flag */ + uint32_t use_ext_id: 1; /*!< Extended Identifier */ + uint32_t error_state_indicator: 1; /*!< Error State Indicator */ + }; + struct { + uint32_t : 18; + uint32_t std_id: 11; /*!< Standard CAN Identifier */ + uint32_t : 3; + }; + }; + struct { + union { + uint16_t rx_timestamp; /*!< Received timestamp */ + struct { + uint16_t rx_timestamp_pointer: 4; /*!< Timestamp Pointer */ + uint16_t rx_timestamp_captured: 1; /*!< Timestamp Captured flag */ + uint16_t : 11; + }; + }; + }; + struct { + uint16_t dlc: 4; /*!< Data Length Code */ + uint16_t bitrate_switch: 1; /*!< Bit rate switch flag */ + uint16_t canfd_frame: 1; /*!< CANFD Frame flag */ + uint16_t : 1; + uint16_t filter_index: 7; /*!< CAN filter index */ + uint16_t accepted_non_matching_frame: 1; /*!< Accept non-matching Frame flag */ + }; + union { + uint8_t data_8[64]; /*!< Data buffer as byte array */ + uint32_t data_32[16]; /*!< Data buffer as word array */ + }; +} mcan_rx_message_t; + +/** + * @brief TX Event Fifo Element Structure + */ +typedef union mcan_tx_event_fifo_elem_struct { + struct { + /* First word */ + union { + struct { + uint32_t ext_id: 29; /*!< CAN Identifier */ + uint32_t rtr: 1; /*!< Remote Transmission Request */ + uint32_t extend_id: 1; /*!< Extended Identifier */ + uint32_t error_state_indicator: 1; /*!< Error State Indicator */ + }; + struct { + uint32_t : 18; + uint32_t std_id: 11; + uint32_t : 3; + }; + }; + + /* first 16-bit of the 2nd word */ + union { + uint16_t tx_timestamp; /*!< Tx Timestamp */ + struct { + uint16_t tx_timestamp_pointer: 4; /*!< TX timestamp pointer */ + uint16_t tx_timestamp_captured: 1; /*!< TX timestamp captured flag */ + uint16_t : 11; + }; + }; + /* high-half 16-bit of the 2nd word */ + struct { + uint16_t dlc: 4; /*!< Data length code */ + uint16_t bitrate_switch: 1; /*!< Bitrate Switch flag */ + uint16_t canfd_frame: 1; /*!< CANFD frame */ + uint16_t event_type: 2; /*!< Event type */ + uint16_t message_marker: 8; /*!< Message Marker */ + }; + }; + uint32_t words[2]; +} mcan_tx_event_fifo_elem_t; + + + +/** + * @brief CAN Identifier Types + */ +#define MCAN_CAN_ID_TYPE_STANDARD (0U) /*!< Standard Identifier */ +#define MCAN_CAN_ID_TYPE_EXTENDED (1U) /*!< Extended Identifier */ + +/** + * @brief MCAN Filter Configuration + */ +typedef union mcan_filter_config_struct { + struct { + uint16_t list_start_addr; /*!< List Start address (CAN Message Buffer Offset) */ + uint16_t list_size; /*!< Element Count */ + }; + uint32_t reg_val; /*!< Register value */ +} mcan_filter_config_t; + +/** + * @brief MCAN RXFIFO Configuration + */ +typedef union mcan_rxfifo_config_struct { + struct { + uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */ + uint32_t fifo_size: 8; /*!< FIFO element count */ + uint32_t watermark: 7; /*!< FIFO watermark */ + uint32_t operation_mode: 1; /*!< Operation mode */ + }; + uint32_t reg_val; /*!< Register value */ +} mcan_rxfifo_config_t; + +/** + * @brief MCAN RXBUF Configuration + */ +typedef struct { + uint32_t start_addr; /*!< Start address (CAN Message Buffer Offset) */ +} mcan_rxbuf_config_t; + +/** + * @brief MCAN Data Field Size Definitions + */ +#define MCAN_DATA_FIELD_SIZE_8BYTES (0U) +#define MCAN_DATA_FIELD_SIZE_12BYTES (1U) +#define MCAN_DATA_FIELD_SIZE_16BYTES (2U) +#define MCAN_DATA_FIELD_SIZE_20BYTES (3U) +#define MCAN_DATA_FIELD_SIZE_24BYTES (4U) +#define MCAN_DATA_FIELD_SIZE_32BYTES (5U) +#define MCAN_DATA_FIELD_SIZE_48BYTES (6U) +#define MCAN_DATA_FIELD_SIZE_64BYTES (7U) + +/** + * @brief MCAN FIFO Operation Mode types + */ +#define MCAN_FIFO_OPERATION_MODE_BLOCKING (0U) +#define MCAN_FIFO_OPERATION_MODE_OVERWRITE (1U) + +/** + * @brief MCAN RXBUF or RXFIFO Element Configuration + */ +typedef union mcan_rx_fifo_or_buf_elem_config_struct { + struct { + uint32_t fifo0_data_field_size: 4; /*!< FIFO0 data field size option */ + uint32_t fifo1_data_field_size: 4; /*!< FIFO1 data field size option */ + uint32_t buf_data_field_size: 4; /*!< Buffer Data field size option */ + uint32_t : 20; + }; + uint32_t reg_val; /*!< Register value */ +} mcan_rx_fifo_or_buf_elem_config_t; + +/** + * @brief MCAN TXBUF operation mode types + */ +#define MCAN_TXBUF_OPERATION_MODE_FIFO (0U) +#define MCAN_TXBUF_OPERATION_MODE_QUEUE (1U) + + +typedef union mcan_txbuf_config_struct { + struct { + uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */ + uint32_t dedicated_tx_buf_size: 6; /*!< Dedicated TX buffer size */ + uint32_t : 2; + uint32_t fifo_queue_size: 6; /*!< FIFO or Queue Size */ + uint32_t tx_fifo_queue_mode: 1; /*!< FIFO or Queue mode selection */ + uint32_t : 1; + }; + uint32_t reg_val; /*!< register value */ +} mcan_txbuf_config_t; + +typedef struct mcan_txbuf_elem_config_struct { + uint32_t data_field_size; /*!< Data Field size option */ +} mcan_txbuf_elem_config_t; + +/** + * @brief MCAN TX Event FIFO Structure + */ +typedef union { + struct { + uint16_t start_addr; /*!< Start Address(CAN Message Buffer Offset */ + uint8_t fifo_size; /*!< FIFO element count */ + uint8_t fifo_watermark; /*!< FIFO watermark */ + }; + uint32_t reg_val; /*!< register value */ +} mcan_tx_evt_fifo_config_t; + +/** + * @brief MCAN RAM Flexible Configuration + * + * @Note This Configration provides the full MCAN RAM configuration, this configuration is recommended only for + * experienced developers who is skilled at the MCAN IP + */ +typedef struct mcan_ram_flexible_config_struct { + bool enable_std_filter; /*!< Enable Standard Identifier Filter */ + bool enable_ext_filter; /*!< Enable Extended Identifier Filter */ + bool enable_rxfifo0; /*!< Enable RXFIFO */ + bool enable_rxfifo1; /*!< Enable RXFIF1 */ + bool enable_rxbuf; /*!< Enable RXBUF */ + bool enable_txbuf; /*!< Enable TXBUF */ + bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */ + + mcan_filter_config_t std_filter_config; /*!< Standard Identifier Filter Configuration */ + mcan_filter_config_t ext_filter_config; /*!< Extended Identifier Filter Configuration */ + + mcan_txbuf_config_t txbuf_config; /*!< TXBUF Configuration */ + mcan_txbuf_elem_config_t txbuf_elem_config; /*!< TXBUF Element Configuration */ + mcan_tx_evt_fifo_config_t tx_evt_fifo_config; /*!< TX Event FIFO Configuration */ + + mcan_rxfifo_config_t rxfifo0_config; /*!< RXFIFO0 Configuration */ + mcan_rxfifo_config_t rxfifo1_config; /*!< RXFIFO1 Configuration */ + mcan_rxbuf_config_t rxbuf_config; /*!< RXBUF Configuration */ + mcan_rx_fifo_or_buf_elem_config_t rx_elem_config; /*!< RX Element Configuration */ +} mcan_ram_flexible_config_t; + +/** + * @brief MCAN RAM configuration + * + * @Note: This Configuration focuses on the minimum required information for MCAN RAM configuration + * The Start address of each BUF/FIFO will be automatically calculated by the MCAN Driver API + * This RAM configuration is recommended for the most developers + */ +typedef struct mcan_ram_config_struct { + bool enable_std_filter; /*!< Enable Standard Identifier Filter */ + uint8_t std_filter_elem_count; /*!< Standard Identifier Filter Element Count */ + + bool enable_ext_filter; /*!< Enable Extended Identifier Filter */ + uint8_t ext_filter_elem_count; /*!< Extended Identifier Filter Element Count */ + + struct { + uint32_t enable: 4; /*!< Enable Flag for RXFIFO */ + uint32_t elem_count: 8; /*!< Element Count for RXFIFO */ + uint32_t watermark: 8; /*!< Watermark for RXFIFO */ + uint32_t operation_mode: 4; /*!< Operation Mode for RXFIFO */ + uint32_t data_field_size: 8; /*!< Data field size option for RXFIFO */ + } rxfifos[2]; + + bool enable_rxbuf; /*!< Enable RXBUF */ + uint8_t rxbuf_elem_count; /*!< RXBUF Element count */ + uint16_t rxbuf_data_field_size; /*!< RXBUF Data Field Size option */ + + bool enable_txbuf; /*!< Enable TXBUF */ + uint8_t txbuf_data_field_size; /*!< TXBUF Data Field Size option */ + uint8_t txbuf_dedicated_txbuf_elem_count; /*!< Dedicated TXBUF element count */ + uint8_t txbuf_fifo_or_queue_elem_count; /*!< FIFO/Queue element count */ + uint8_t txfifo_or_txqueue_mode; /*!< TXFIFO/QUEUE mode */ + + bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */ + uint8_t tx_evt_fifo_elem_count; /*!< TX Event FIFO Element count */ + uint8_t tx_evt_fifo_watermark; /*!< TX Event FIFO Watermark */ +} mcan_ram_config_t; + +/** + * @brief MCAN Accept Non-Matching Frame options + */ +#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0 (0U) /*!< Save non-matching frame to RXFIFO0 */ +#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO1 (1U) /*!< Save non-matching frame to RXFIFO1 */ +#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT (2U) /*!< Reject non-matching frame */ + +/** + * @brief MCAN Global CAN configuration + */ +typedef struct mcan_global_filter_config_struct { + uint8_t accept_non_matching_std_frame_option; /*!< Accept non-matching standard frame option */ + uint8_t accept_non_matching_ext_frame_option; /*!< Accept non-matching extended frame option */ + bool reject_remote_std_frame; /*!< Reject Remote Standard Frame */ + bool reject_remote_ext_frame; /*!< Reject Remote Extended Frame */ +} mcan_global_filter_config_t; + +/** + * @brief MCAN Filter type definitions + */ +#define MCAN_FILTER_TYPE_RANGE_FILTER (0U) /*!< CAN Identifier Range filter */ +#define MCAN_FILTER_TYPE_SPECIFIED_ID_FILTER (1U) /*!< CAN Identifier ID filter */ +#define MCAN_FILTER_TYPE_CLASSIC_FILTER (2U) /*!< CAN classic filter */ +#define MCAN_FILTER_TYPE_FILTER_DISABLED (3U) /*!< CAN filter disabled */ +#define MCAN_FILTER_TYPE_DUAL_ID_EXT_FILTER_IGNORE_MASK /*!< CAN Identifier Range filter, ignoring extended ID mask */ + +/** + * @brief MCAN Filter Configuration Options + */ +#define MCAN_FILTER_ELEM_CFG_DISABLED (0) /*!< Disable Filter Element */ +#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH (1U) /*!< Store data into RXFIFO0 if matching */ +#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO1_IF_MATCH (2U) /*!< Store data into RXFIFO1 if matching */ +#define MCAN_FILTER_ELEM_CFG_REJECT_ID_IF_MATCH (3U) /*!< Reject ID if matching */ +#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_IF_MATCH (4U) /*!< Set Priority if matching */ +/*!< Set Priority and store into RXFIFO0 if matching */ +#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO0_IF_MATCH (5U) +/*!< Set Priority and store into RXFIFO1 if matching */ +#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO1_IF_MATCH (6U) +#define MCAN_FILTER_ELEM_CFG_STORE_INTO_RX_BUFFER_OR_AS_DBG_MSG (7U) /*!< Store into RXBUF if matching */ + +/** + * @brief MCAN Filter Element definitions + */ +typedef struct mcan_std_id_filter_elem_struct { + uint8_t filter_type; /*!< Filter type */ + uint8_t filter_config; /*!< Filter configuration */ + uint8_t can_id_type; /*!< CAN ID type */ + uint8_t sync_message; /*!< Sync Message */ + union { + /* This definition takes effect if the filter type is range filter */ + struct { + uint32_t start_id; /*!< Start of ID range */ + uint32_t end_id; /*!< End of ID range */ + }; + /* This definition takes effect if the filter type is dual id filter */ + struct { + uint32_t id1; /*!< ID1 */ + uint32_t id2; /*!< ID2 */ + }; + /* This definition takes effect if the filter type is classic filter */ + struct { + uint32_t filter_id; /*!< Filter ID */ + uint32_t filter_mask; /*!< Filter Mask */ + }; + /* This definition takes effect if the filter configuration is "store into RX Buffer or as debug message" + * + * In this definition, only the extact ID matching mode is activated + */ + struct { + uint32_t match_id; /*!< Matching ID */ + uint32_t offset: 6; /*!< RX Buffer Index */ + uint32_t filter_event: 3; /*!< Filter event, set to 0 */ + uint32_t store_location: 2; /*!< Store location, 0 - RX buffer */ + uint32_t : 21; + }; + }; +} mcan_filter_elem_t; + +/** + * @brief MCAN Filter Element List structure + */ +typedef struct mcan_filter_elem_list_struct { + uint32_t mcan_filter_elem_count; /*!< Number of Filter element */ + const mcan_filter_elem_t *filter_elem_list; /*!< Filter element list */ +} mcan_filter_elem_list_t; + +/** + * @brief MCAN Configuration for all filters + * + * @Note The MCAN RAM related settings are excluded + */ +typedef struct mcan_all_filters_config_struct { + mcan_global_filter_config_t global_filter_config; /*!< Global Filter configuration */ + uint32_t ext_id_mask; /*!< Extended ID mask */ + mcan_filter_elem_list_t std_id_filter_list; /*!< Standard Identifier Configuration List */ + mcan_filter_elem_list_t ext_id_filter_list; /*!< Extended Identifier Configuration List */ +} mcan_all_filters_config_t; + +/** + * @brief CAN Node Mode types + */ +typedef enum mcan_node_mode_enum { + mcan_mode_normal = 0, /*!< CAN works in normal mode */ + mcan_mode_loopback_internal = 1, /*!< CAN works in internal loopback mode */ + mcan_mode_loopback_external = 2, /*!< CAN works in external loopback mode */ + mcan_mode_listen_only = 3, /*!< CAN works in listen-only mode */ +} mcan_node_mode_t; + +/** + * @brief MCAN Timestamp Value + */ +typedef struct mcan_timestamp_value_struct { + bool is_16bit; /*!< Timestamp is 16-bit */ + bool is_32bit; /*!< Timestamp is 32-bit */ + bool is_64bit; /*!< Timestamp is 64-bit */ + bool is_empty; /*!< Timestamp is empty */ + union { + uint16_t ts_16bit; /*!< 16-bit timestamp value */ + uint32_t ts_32bit; /*!< 32-bit timestamp value */ + uint64_t ts_64bit; /*!< 64-bit timestamp value */ + uint32_t words[2]; /*!< timestamp words */ + }; +} mcan_timestamp_value_t; + +/** + * @brief MCAN TSU Configuration + */ +typedef struct mcan_tsu_config_struct { + uint16_t prescaler; /*!< Prescaler for MCAN clock, Clock source: AHB clock */ + bool capture_on_sof; /*!< Capture On SOF, true - Capture on SOF, false - Capture on EOF */ + bool use_ext_timebase; /*!< Use External Timebase */ + uint16_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */ + bool enable_tsu; /*!< Enable Timestamp Unit */ + bool enable_64bit_timestamp; /*!< Enable 64bit Timestamp */ +} mcan_tsu_config_t; + +/** + * @brief MCAN Timestamp Select + */ +#define MCAN_TIMESTAMP_SEL_MIN (0U) +#define MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO (0U) /*!< Timestamp value always equal to 0 */ +#define MCAN_TIMESTAMP_SEL_VALUE_INCREMENT (1U) /*!< Timestamp value increments according to prescaler */ +#define MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED (2U) /*!< External Timestamp value used */ +#define MCAN_TIMESTAMP_SEL_MAX (MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED) + +/** + * @brief MCAN Internal timestamp configuration + */ +typedef struct mcan_internal_timestamp_config_struct { + uint8_t counter_prescaler; /*!< Timestamp Counter Prescaler, clock source: AHB clock */ + uint8_t timestamp_selection; /*!< Timestamp Select */ +} mcan_internal_timestamp_config_t; + +/** + * @brief MCAN Configuration Structure + */ +typedef struct mcan_config_struct { + union { + /* This struct takes effect if use_lowlevl_timing_setting = false */ + struct { + uint32_t baudrate; /*!< CAN 2.0 baudrate/CAN-FD Nominal Baudrate, in terms of bps */ + uint32_t baudrate_fd; /*!< CANFD data baudrate, in terms of bps */ + uint16_t can20_samplepoint_min; /*!< Value = Minimum CAN2.0 sample point * 10 */ + uint16_t can20_samplepoint_max; /*!< Value = Maximum CAN2.0 sample point * 10 */ + uint16_t canfd_samplepoint_min; /*!< Value = Minimum CANFD sample point * 10 */ + uint16_t canfd_samplepoint_max; /*!< Value = Maximum CANFD sample point * 10 */ + }; + /* This struct takes effect if use_lowlevl_timing_setting = true */ + struct { + mcan_bit_timing_param_t can_timing; /*!< CAN2.0/CANFD nominal timing setting */ + mcan_bit_timing_param_t canfd_timing; /*!< CANFD data timing setting */ + }; + }; + bool use_lowlevel_timing_setting; /*!< Use Low-level timing setting */ + mcan_node_mode_t mode; /*!< CAN node mode */ + bool enable_non_iso_mode; /*!< Enable Non-ISO FD mode */ + bool enable_transmit_pause; /*!< Enable Transmit Pause */ + bool enable_edge_filtering; /*!< Enable Edge Filtering */ + bool disable_protocol_exception_handling; /*!< Disable Protocol Exception Handling */ + bool enable_wide_message_marker; /*!< Enable Wide Message Marker */ + bool use_timestamping_unit; /*!< Use external Timestamp Unit */ + bool enable_canfd; /*!< Enable CANFD mode */ + bool enable_tdc; /*!< Enable transmitter delay compensation */ + mcan_internal_timestamp_config_t timestamp_cfg; /*!< Internal Timestamp Configuration */ + mcan_tsu_config_t tsu_config; /*!< TSU configuration */ + mcan_ram_config_t ram_config; /*!< MCAN RAM configuration */ + mcan_all_filters_config_t all_filters_config; /*!< All Filter configuration */ +} mcan_config_t; + +/** + * @brief MCAN Timeout Selection Options + */ +#define MCAN_TIMEOUT_SEL_TYPE_CONTINUOUS_OPERATION (0U) +#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_TX_EVT_FIFO (1U) +#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO0 (2U) +#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO1 (3U) + +/** + * @brief MCAN Timeout Counter Configuration + */ +typedef struct mcan_timeout_counter_config_struct { + bool enable_timeout_counter; /*!< Enable Timeout counter */ + uint8_t timeout_selection; /*!< Timeout source selection */ + uint16_t timeout_period; /*!< Timeout period */ +} mcan_timeout_counter_config_t; + +/** + * @brief MCAN Error Count Information + */ +typedef struct mcan_error_count_struct { + uint8_t transmit_error_count; /*!< Transmit Error Count */ + uint8_t receive_error_count; /*!< Receive Error Count */ + bool receive_error_passive; /*!< The Receive Error Counter has reached the error passive level */ + uint8_t can_error_logging_count; /*!< CAN Error Logging count */ +} mcan_error_count_t; + +/** + * @brief MCAN Transmitter Delay Compensation Configuration + */ +typedef struct mcan_tdc_config_t { + uint8_t ssp_offset; /*!< SSP offset */ + uint8_t filter_window_length; /*!< Filter Window Length */ +} mcan_tdc_config_t; + + +/** + * @brief MCAN Message Storage Indicator Types + */ +#define MCAN_MESSAGE_STORAGE_INDICATOR_NO_FIFO_SELECTED (0U) +#define MCAN_MESSAGE_STORAGE_INDICATOR_FIFO_MESSAGE_LOST (1U) +#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO0 (2U) +#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO1 (3U) + +/** + * @brief MCAN High Priority Message Status Information + */ +typedef struct mcan_high_priority_message_status_struct { + uint8_t filter_list_type; /*!< Filter List Type, 0 - STD filter, 1 - EXT filter */ + uint8_t filter_index; /*!< Filter Elem List */ + uint8_t message_storage_indicator; /*!< Message Storage Indicator */ + uint8_t buffer_index; +} mcan_high_priority_message_status_t; + +/** + * @brief Enable Transmit Pause + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_transmit_pause(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_TXP_MASK; +} + +/** + * @brief Disable Transmit Pause + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_transmit_pause(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_TXP_MASK; +} + +/** + * @brief Enable Edge Filtering + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_edge_filtering(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_EFBI_MASK; +} + +/** + * @brief Disable Edge Filtering + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_edge_filtering(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; +} + +/** + * @brief Enable Protocol Exception Handling + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_protocol_exception_handling(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK; +} + +/** + * @brief Disable Protocol Exception Handling + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_protocol_exception_handling(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_PXHD_MASK; +} + +/** + * @brief Enable Wide Message Marker + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_wide_message_marker(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_WMM_MASK; +} + +/** + * @brief Disable Wide Message Marker + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_wide_message_marker(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_WMM_MASK; +} + +/** + * @brief Enable External Timestamp Unit + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_tsu(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_UTSU_MASK; +} + +/** + * @brief Disable External Timestamp Unit + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_tsu(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK; +} + +/** + * @brief Check whether TSU is used + * @param [in] ptr MCAN base + * @retval true if TSU is used + * @retval false if TSU is not used + */ +static inline bool mcan_is_tsu_used(MCAN_Type *ptr) +{ + return ((ptr->CCCR & MCAN_CCCR_UTSU_MASK) != 0U); +} + +/** + * @brief Check whether 64-bit TSU timestamp is used + * @param [in] ptr MCAN base + * @retval true if 64-bit timestamp is used + * @retval false if 32-bit timestamp is used + */ +static inline bool mcan_is_64bit_tsu_timestamp_used(MCAN_Type *ptr) +{ + return ((ptr->TSCFG & MCAN_TSCFG_EN64_MASK) != 0U); +} + +/** + * @brief Enable Bit Rate Switch + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_bitrate_switch(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_BRSE_MASK; +} + +/** + * @brief Disable Bit Rate Switch + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_bitrate_switch(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_BRSE_MASK; +} + +/** + * @brief Enable Auto Retransmission + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_auto_retransmission(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_DAR_MASK; +} + +/** + * @brief Disable Auto Transmission + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_auto_retransmission(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_DAR_MASK; +} + +/** + * @brief Disable Bus monitoring Mode + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_MON_MASK; +} + +/** + * @brief Enable Clock Stop Request + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_clock_stop_request(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_CSR_MASK; +} + +/** + * @brief Disable Clock Stop Request + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_clock_stop_request(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_CSR_MASK; +} + +/** + * @brief Enable Clock Stop Acknowledge + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_clock_stop_acknowledge(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_CSA_MASK; +} + +/** + * @brief Disable Clock Stop Acknowledge + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_clock_stop_acknowledge(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_CSA_MASK; +} + +/** + * @brief Disable Restricted Operation Mode + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_restricted_operation_mode(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; +} + +/** + * @brief Get Timestamp Counter Value + * @param [in] ptr MCAN base + * @return timestamp value + */ +static inline uint16_t mcan_get_timestamp_counter_value(MCAN_Type *ptr) +{ + return ptr->TSCV; +} + +/** + * @brief Get Timeout value + * @param [in] ptr MCAN base + * @return timeout value + */ +static inline uint16_t mcan_get_timeout_counter_value(MCAN_Type *ptr) +{ + return ptr->TOCV; +} + +/** + * @brief Get Error Counter Information + * @param [in] ptr MCAN base + * @param [out] err_cnt Error Count buffer + */ +static inline void mcan_get_error_counter(MCAN_Type *ptr, mcan_error_count_t *err_cnt) +{ + uint32_t ecr = ptr->ECR; + err_cnt->transmit_error_count = MCAN_ECR_TEC_GET(ecr); + err_cnt->receive_error_count = MCAN_ECR_REC_GET(ecr); + err_cnt->receive_error_passive = (MCAN_ECR_RP_GET(ecr) == 1U); + err_cnt->can_error_logging_count = MCAN_ECR_CEL_GET(ecr); +} + +/** + * @brief Get Last Error Code + * @param [in] ptr MCAN base + * @return Last Error code + */ +static inline uint8_t mcan_get_last_error_code(MCAN_Type *ptr) +{ + return MCAN_PSR_LEC_GET(ptr->PSR); +} + +/** + * @brief Get Last Data Phase Error Code + * @param [in] ptr MCAN base + * @return Last Error Code in Data phase + */ +static inline uint8_t mcan_get_last_data_error_code(MCAN_Type *ptr) +{ + return MCAN_PSR_DLEC_GET(ptr->PSR); +} + +/** + * @brief Get CAN Activity + * @param [in] ptr MCAN base + * @return CAN IP activity + */ +static inline uint8_t mcan_get_activity(MCAN_Type *ptr) +{ + return MCAN_PSR_ACT_GET(ptr->PSR); +} + +/** + * @brief Check whether the CAN node is under error passive state + * @param [in] ptr MCAN base + * @return true is CAN is under error passive state + */ +static inline bool mcan_is_in_err_passive_state(MCAN_Type *ptr) +{ + return (MCAN_PSR_EP_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether the CAN mode is under Warning State + * @param [in] ptr MCAN base + * @return true if the CAN node is under Error Warning State + */ +static inline bool mcan_is_in_error_warning_state(MCAN_Type *ptr) +{ + return (MCAN_PSR_EW_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether the CAN node is under Bus-off state + * @param [in] ptr MCAN base + * @return true if the CAN node is under Bus-off state + */ +static inline bool mcan_is_in_busoff_state(MCAN_Type *ptr) +{ + return (MCAN_PSR_BO_GET(ptr->PSR) == 1U); +} + +/** + * @brief Get the Last Data Phase Error + * @param [in] ptr MCAN base + * @return The last Data Phase Error + */ +static inline uint8_t mcan_get_data_phase_last_error_code(MCAN_Type *ptr) +{ + return MCAN_PSR_DLEC_GET(ptr->PSR); +} + +/** + * @brief Check Whether the Error Status Indicator Flag is set in the last received CANFD message + * @param [in] ptr MCAN base + * @return true if the Error Status Indicator Flag is set in the last received CANFD Message + */ +static inline bool mcan_is_error_state_indicator_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr) +{ + return (MCAN_PSR_RESI_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether the Bitrate Switch Flag is set in the last received CANFD message + * @param [in] ptr MCAN base + * @return true if Bit rate switch flag is set in the last received CANFD message + */ +static inline bool mcan_is_bitrate_switch_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr) +{ + return (MCAN_PSR_RBRS_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether CANFD messages were received + * @param [in] ptr MCAN base + * @return true if a CANFD message was received + */ +static inline bool mcan_is_canfd_message_received(MCAN_Type *ptr) +{ + return (MCAN_PSR_RFDF_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether Protocol Exception Events were occurred + * @param [in] ptr MCAN base + * @return true if Protocol Exception Events were occurred + */ +static inline bool mcan_is_protocol_exception_event_occurred(MCAN_Type *ptr) +{ + return (MCAN_PSR_PXE_GET(ptr->PSR) == 1U); +} + +/** + * @brief Get the Transmitter Delay Compensation Value + * @param [in] ptr MCAN base + * @return Transmitter Delay Compensation value + */ +static inline uint8_t mcan_get_transmitter_delay_compensation_value(MCAN_Type *ptr) +{ + return MCAN_PSR_TDCV_GET(ptr->PSR); +} + +/** + * @brief Get Interrupt Flags + * @param [in] ptr MCAN base + * @return Interrupt Flags + */ +static inline uint32_t mcan_get_interrupt_flags(MCAN_Type *ptr) +{ + return ptr->IR; +} + +/** + * @brief Clear Interrupt Flags + * @param [in] ptr MCAN base + * @param [in] mask Interrupt Mask + */ +static inline void mcan_clear_interrupt_flags(MCAN_Type *ptr, uint32_t mask) +{ + ptr->IR = mask; +} + +/** + * @brief Enable Interrupts + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_interrupts(MCAN_Type *ptr, uint32_t mask) +{ + ptr->ILS &= ~mask; + ptr->IE |= mask; + ptr->ILE = 1U; +} + +/** + * @brief Enable TXBUF Interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE |= mask; +} + +/** + * @brief Disable TXBUF Interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE &= ~mask; +} + +/** + * @brief Disable Interrupts + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_interrupts(MCAN_Type *ptr, uint32_t mask) +{ + ptr->IE &= ~mask; +} + +/** + * @brief Enable TXBUF Transmission interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE |= mask; +} + +/** + * @brief Disable TXBUF Transmission interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE &= ~mask; +} + +/** + * @brief Enable TXBUF Cancellation Finish interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBCIE |= mask; +} + +/** + * @brief Disable TXBUF Cancellation Finish interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBCIE &= ~mask; +} + +/** + * @brief Select Interrupt Line + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + * @param [in] line_index Interrupt Line Index + */ +static inline void mcan_interrupt_line_select(MCAN_Type *ptr, uint32_t mask, uint8_t line_index) +{ + if (line_index == 0) { + ptr->ILS &= ~mask; + } else { + ptr->ILS |= mask; + } + ptr->ILE = (1UL << line_index); +} + +/** + * @brief Check whether a TXFIFO/TXBUF transmission request is pending + * @param [in] ptr CAN Base + * @param [in] index TXBUF/TXFIFO Index + * @return True is the specified TXFIFO/TXBUF Transmission request is pending + */ +static inline bool mcan_is_transmit_request_pending(MCAN_Type *ptr, uint32_t index) +{ + return ((ptr->TXBRP & ((1UL << index))) != 0U); +} + +/** + * @brief Check whether TXFIFO is full + * @param [in] ptr MCAN base + * @return true if TXFIFO is full + */ +static inline bool mcan_is_txfifo_full(MCAN_Type *ptr) +{ + return ((ptr->TXFQS & MCAN_TXFQS_TFQF_MASK) != 0U); +} + +/** + * @brief Get the TXFIFO Put Index + * @param [in] ptr MCAN base + * @return The TX FIFO Put Index + */ +static inline uint32_t mcan_get_txfifo_put_index(MCAN_Type *ptr) +{ + return MCAN_TXFQS_TFQPI_GET(ptr->TXFQS); +} + +/** + * @brief Request A Transmission via specified TXBUF Index + * @param [in] ptr MCAN Base + * @param [in] index TXBUF index + */ +static inline void mcan_send_add_request(MCAN_Type *ptr, uint32_t index) +{ + ptr->TXBAR = (1UL << index); +} + +/** + * @brief Check whether the Transmission completed via specified TXBUF/TXFIFO + * @param [in] ptr MCAN base + * @param [in] index TXBUF Index + * @return True is the Transmission completed via specified TXBUF + */ +static inline bool mcan_is_transmit_occurred(MCAN_Type *ptr, uint32_t index) +{ + return ((ptr->TXBTO & (1UL << index)) != 0U); +} + +/** + * @brief Check Whether there are data available in specified RXBUF + * @param [in] ptr MCAN Base + * @param [in] index RXBUF index + * @return True if there are data available + */ +static inline bool mcan_is_rxbuf_data_available(MCAN_Type *ptr, uint32_t index) +{ + bool result; + if (index < 32U) { + result = (ptr->NDAT1 & (1UL << index)) != 0U; + } else if (index < 64U) { + result = (ptr->NDAT2 & (1UL << (index - 32U))) != 0U; + } else { + result = false; + } + return result; +} + +/** + * @brief Clear RXBUF Data available Flag for specified RXBUF + * @param [in] ptr MCAN base + * @param [in] index RXBUF index + */ +static inline void mcan_clear_rxbuf_data_available_flag(MCAN_Type *ptr, uint32_t index) +{ + if (index < 32U) { + ptr->NDAT1 = (1UL << index); + } else if (index < 64U) { + ptr->NDAT2 = (1UL << (index - 32U)); + } else { + /* Do nothing */ + } +} + +/** + * @brief Check whether specified Interrupt is set + * @param [in] ptr MCAN Base + * @param [in] mask Interrupt Flags + * @retval true if corresponding bits are set + */ +static inline bool mcan_is_interrupt_flag_set(MCAN_Type *ptr, uint32_t mask) +{ + return ((ptr->IR & mask) != 0U); +} + +static inline bool mcan_is_tsu_timestamp_available(MCAN_Type *ptr, uint32_t index) +{ + bool is_available = false; + if (index < ARRAY_SIZE(ptr->TS_SEL)) { + is_available = ((ptr->TSS1 & (1UL << index)) != 0U); + } + return is_available; +} + +/** + * @brief Read 32bit Timestamp value from TSU + * @param [in] ptr MCAN Base + * @param [in] index Timestamp pointer + * @return Timestamp value + */ +uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index); + +/** + * @brief Read 64bit Timestamp value from TSU + * @param [in] ptr MCAN Base + * @param [in] index Timestamp pointer + * @return Timestamp value + */ +uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index); + +/** + * @brief Get High Priority Message Status + * @param [in] ptr MCAN base + * @param [out] status Pointer to High Priority Message Status Buffer + */ +void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status); + +/** + * @brief Get Default CAN configuration + * @param [in] ptr MCAN base + * @param [out] config CAN configuration + */ +void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config); + +/** + * @brief Get message Size from Data Length Code + * @param [in] dlc Data Length Code + * @return Message Size in Bytes + */ +uint8_t mcan_get_message_size_from_dlc(uint8_t dlc); + +uint8_t mcan_get_data_field_size(uint8_t data_field_size_option); + +/** + * @brief Get Default Full MCAN RAM configuration + * If the device is configured as classic CAN node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 32 + * - Extended Identifier Filter Elements: 32 + * - TXBUF Elements Info: + * - Element Count:32 + * - Dedicated TXBUF element count: 16 + * - TXFIFO/QQueue element count: 16 + * - Data Field Size: 8 + * - RXFIFO0 Elements Info: + * - Element Count :32 + * - Data Field Size: 8 + * - RXFIFO1 Elements Info: + * - Element Count : 32 + * - Data Field Size: 8 + * - RXBUF Element Info: + * - Element Count: 16 + * - Data Field Size : 8 + * - TX Event FIFO Element Count: 32 + * If the device is configured as CANFD node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 16 + * - Extended Identifier Filter Elements: 16 + * - TXBUF Elements Info: + * - Element Count:8 + * - Dedicated TXBUF element count: 4 + * - TXFIFO/QQueue element count: 4 + * - Data Field Size: 64 + * - RXFIFO0 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXFIFO1 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXBUF Element Info: + * - Element Count: 4 + * - Data Field Size : 64 + * - TX Event FIFO Element Count: 8 + * + * @param [in] ptr MCAN base + * @param [out] ram_config CAN RAM Configuration + * @param [in] enable_canfd CANFD enable flag + */ +void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd); + +/** + * @brief Get Default MCAN RAM configuration + * If the device is configured as classic CAN node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 32 + * - Extended Identifier Filter Elements: 32 + * - TXBUF Elements Info: + * - Element Count:32 + * - Dedicated TXBUF element count: 16 + * - TXFIFO/QQueue element count: 16 + * - Data Field Size: 8 + * - RXFIFO0 Elements Info: + * - Element Count :32 + * - Data Field Size: 8 + * - RXFIFO1 Elements Info: + * - Element Count : 32 + * - Data Field Size: 8 + * - RXBUF Element Info: + * - Element Count: 16 + * - Data Field Size : 8 + * - TX Event FIFO Element Count: 32 + * If the device is configured as CANFD node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 16 + * - Extended Identifier Filter Elements: 16 + * - TXBUF Elements Info: + * - Element Count:8 + * - Dedicated TXBUF element count: 4 + * - TXFIFO/QQueue element count: 4 + * - Data Field Size: 64 + * - RXFIFO0 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXFIFO1 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXBUF Element Info: + * - Element Count: 4 + * - Data Field Size : 64 + * - TX Event FIFO Element Count: 8 + * + * @param [in] ptr MCAN base + * @param [out] ram_config CAN RAM Configuration + * @param [in] enable_canfd CANFD enable flag + */ +void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd); + +/** + * @brief Initialize CAN controller + * @param [in] ptr MCAN base + * @param [in] config CAN configuration + * @param [in] src_clk_freq CAN clock frequency + * @retval status_success if operation is successful + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq); + +/** + * @brief Configure MCAN RAM will Full RAM configuration + * @param [in] ptr MCAN base + * @param [in] config MCAN RAM Full Configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config); + +/** + * @brief Configure MCAN RAM will Simplified RAM configuration + * @param [in] ptr MCAN base + * @param [in] config MCAN RAM configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config); + +/** + * @brief Configure All CAN filters + * @param [in] ptr MCAN base + * @param [in] config All CAN Filter configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config); + +/** + * @brief Configure Transmitter Delay Compensation + * @param [in] ptr MCAN base + * @param [in] config Transmitter Delay compensation configure + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config); + +/** + * @brief Configure Global Filter + * @param [in] ptr MCAN base + * @param [in] filter_config Global Filter Configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config); + +/** + * @brief Set CAN filter element + * @param [in] ptr MCAN base + * @param [in] filter_elem CAN filter element + * @param [in] index CAN Filter element index + * @return status_success if no errors reported + */ +hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index); + +/** + * @brief Write Frame to CAN TX Buffer + * @param [in] ptr MCAN base + * @param [in] index TX Buffer Index + * @param [in] tx_frame TX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); + +/** + * @brief Write Frame CAN to TXFIFO + * @param [in] ptr MCAN base + * @param [in] tx_frame TX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); + +/** + * @brief Read message from CAN RXBUF + * @param [in] ptr MCAN base + * @param [in] index Index of RXBUF + * @param [out] rx_frame Buffer to hold RX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame); + +/** + * @brief Read message from CAN RXBUF + * @param [in] ptr MCAN base + * @param [in] fifo_index RXFIFO index, 0 - RXFO0, 1 - RXFIFO1 + * @param [out] rx_frame Buffer to hold RX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame); + +/** + * @brief Read TX Event from CAN TX EVENT FIFO + * @param [in] ptr MCAN base + * @param [out] tx_evt TX Event Buffer + * @retval status_success if no errors happened + * @retval status_mcan_tx_evt_fifo_empty if there are no TX events available + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt); + +/** + * @brief Transmit CAN message in blocking way + * @param [in] ptr MCAN base + * @param [in] tx_frame CAN Transmit Message buffer + * @return status_success if no errors reported + */ +hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); + +/** + * @brief Transmit CAN message via TX in blocking way + * @param [in] ptr MCAN base + * @param [in] tx_frame CAN Transmit Message buffer + * @return status_success if no errors reported + */ +hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); + +/** + * @brief Receive CAN Frame from RXBUF in blocking way + * @param [in] ptr MCAN base + * @param [in] index RXBUF index + * @param [out] rx_frame Buffer to hold Received Frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame); + +/** + * @brief Receive CAN Frame from RXFIFO in blocking way + * @param [in] ptr MCAN base + * @param [in] fifo_index RXFIFO index, 0 - RXFIFO0, 1 - RXFIFO1 + * @param [out] rx_frame Buffer to hold Received Frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame); + +/** + * @brief Get Timstamp from MCAN TX Event + * @param [in] ptr MCAN base + * @param [in] tx_evt TX Event Element + * @param [out] timestamp Timestamp value + * @retval status_success if no errors happened + * @retval status_invalid_argument if any parameters are invalid + * @retval status_mcan_timestamp_not_exist if no timestamp information is available + */ +hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr, + const mcan_tx_event_fifo_elem_t *tx_evt, + mcan_timestamp_value_t *timestamp); + +/** + * @brief Get Timstamp from MCAN RX frame + * @param [in] ptr MCAN base + * @param [in] rx_msg Received message + * @param [out] timestamp Timestamp value + * @retval status_success if no errors happened + * @retval status_invalid_argument if any parameters are invalid + * @retval status_mcan_timestamp_not_exist if no timestamp information is available + */ +hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, + const mcan_rx_message_t *rx_msg, + mcan_timestamp_value_t *timestamp); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* HPM_MCAN_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h index 1226441a6a..a64380ef74 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h index 6ffbb406ab..eaa2a39fad 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h index 3d010fe702..1ddd718c97 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h index 5b27e076a2..c7ab9729a6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h new file mode 100644 index 0000000000..f3be449bfd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLA_DRV_H +#define HPM_PLA_DRV_H + +#include "hpm_common.h" +#include "hpm_pla_regs.h" + +/** + * @brief PLA driver APIs + * @defgroup pla_interface PLA driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define PLA_AOI_16TO8_SIGNAL_NUM (16U) +#define PLA_AOI_8TO7_SIGNAL_NUM (8U) +#define PLA_CHN_CFG_ACTIVE_WORD (0xF00DU) + +#define PLA_AOI_16TO8_CONNECT_(input, value) \ + PLA_CHN_AOI_16TO8_AOI_16TO8_##input##_SET(value) +/** + * @brief Input signal configuration for synthetic aoi_16to8 + * + */ +#define PLA_AOI_16TO8_CONNECT(input_signal, operation) \ + PLA_AOI_16TO8_CONNECT_(input_signal, operation) + +/** + * @brief aoi_16to8 operation on input signals + * + */ +typedef enum pla_aoi_signal_operation_type { + pla_aoi_operation_and_0 = 0, /**< signal & 0 */ + pla_aoi_operation_and_1 = 1, /**< signal & 1 */ + pla_aoi_operation_xor_1 = 2, /**< signal xor 1 */ + pla_aoi_operation_or_1 = 3, /**< signal | 1 */ +} pla_aoi_signal_operation_type_t; + +typedef enum pla_filter_sw_inject_type { + pla_filter_sw_inject_low = 0, + pla_filter_sw_inject_height = 1, + pla_filter_sw_inject_disable = 2, +} pla_filter_sw_inject_type_t; + +/** + * @brief aoi channel index + * + */ +typedef enum pla_channel_type { + pla_chn_0 = PLA_CHN_0, /**< channel 0 */ + pla_chn_1 = PLA_CHN_1, /**< channel 1 */ + pla_chn_2 = PLA_CHN_2, /**< channel 2 */ + pla_chn_3 = PLA_CHN_3, /**< channel 3 */ + pla_chn_4 = PLA_CHN_4, /**< channel 4 */ + pla_chn_5 = PLA_CHN_5, /**< channel 5 */ + pla_chn_6 = PLA_CHN_6, /**< channel 6 */ + pla_chn_7 = PLA_CHN_7, /**< channel 7 */ +} pla_channel_type_t; + +/** + * @brief Raw input signal for aoi16to8 module + * + */ +typedef enum pla_aoi_16to8_input_signal_type { + pla_level1_filter_out_0 = 0, + pla_level1_filter_out_1 = 1, + pla_level1_filter_out_2 = 2, + pla_level1_filter_out_3 = 3, + pla_level1_filter_out_4 = 4, + pla_level1_filter_out_5 = 5, + pla_level1_filter_out_6 = 6, + pla_level1_filter_out_7 = 7, + pla_level1_filter_out_8 = 8, + pla_level1_filter_out_9 = 9, + pla_level1_filter_out_10 = 10, + pla_level1_filter_out_11 = 11, + pla_level1_filter_out_12 = 12, + pla_level1_filter_out_13 = 13, + pla_level1_filter_out_14 = 14, + pla_level1_filter_out_15 = 15, +} pla_aoi_16to8_input_signal_type_t; + +/** + * @brief aoi_16to8 channel index + * + */ +typedef enum pla_aoi_16to8_channel_type { + pla_aoi_16to8_chn_0 = PLA_CHN_AOI_16TO8_AOI_16TO8_00, /**< channel 0 */ + pla_aoi_16to8_chn_1 = PLA_CHN_AOI_16TO8_AOI_16TO8_01, /**< channel 1 */ + pla_aoi_16to8_chn_2 = PLA_CHN_AOI_16TO8_AOI_16TO8_02, /**< channel 2 */ + pla_aoi_16to8_chn_3 = PLA_CHN_AOI_16TO8_AOI_16TO8_03, /**< channel 3 */ + pla_aoi_16to8_chn_4 = PLA_CHN_AOI_16TO8_AOI_16TO8_04, /**< channel 4 */ + pla_aoi_16to8_chn_5 = PLA_CHN_AOI_16TO8_AOI_16TO8_05, /**< channel 5 */ + pla_aoi_16to8_chn_6 = PLA_CHN_AOI_16TO8_AOI_16TO8_06, /**< channel 6 */ + pla_aoi_16to8_chn_7 = PLA_CHN_AOI_16TO8_AOI_16TO8_07, /**< channel 7 */ +} pla_aoi_16to8_channel_type_t; + +/** + * @brief aoi_16to8 config unit + * + */ +typedef struct pla_aoi_16to8_cfg_unit { + pla_aoi_16to8_input_signal_type_t signal; + pla_aoi_signal_operation_type_t op; +} pla_aoi_16to8_cfg_unit_t; + +/** + * @brief aoi_16to8 channel config + * + */ +typedef struct pla_aoi_16to8_chn_cfg { + pla_channel_type_t chn; /**< pla channel */ + pla_aoi_16to8_channel_type_t aoi_16to8_chn; /**< aoi_16to8 channel */ + pla_aoi_16to8_cfg_unit_t input[PLA_AOI_16TO8_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */ +} pla_aoi_16to8_chn_cfg_t; + +/** + * @brief aoi_8_to_7 input signal + * + */ +typedef enum pla_aoi_8to7_input_signal_type { + pla_level2_filter_out_0 = 0, + pla_level2_filter_out_1 = 1, + pla_level2_filter_out_2 = 2, + pla_level2_filter_out_3 = 3, + pla_level2_filter_out_4 = 4, + pla_level2_filter_out_5 = 5, + pla_level2_filter_out_6 = 6, + pla_level2_filter_out_7 = 7, +} pla_aoi_8to7_input_signal_type_t; + +/** + * @brief aoi_8to7 channel number + * + */ +typedef enum pla_aoi_8to7_channel_type { + pla_aoi_8to7_chn_0 = 0, /**< channel 0 */ + pla_aoi_8to7_chn_1 = 1, /**< channel 1 */ + pla_aoi_8to7_chn_2 = 2, /**< channel 2 */ + pla_aoi_8to7_chn_3 = 3, /**< channel 3 */ + pla_aoi_8to7_chn_4 = 4, /**< channel 4 */ + pla_aoi_8to7_chn_5 = 5, /**< channel 5 */ + pla_aoi_8to7_chn_6 = 6, /**< channel 6 */ +} pla_aoi_8to7_channel_type_t; + + +/** + * @brief aoi_8to7 config unit + * + */ +typedef struct pla_aoi_8to7_cfg_unit { + pla_aoi_8to7_input_signal_type_t signal; + pla_aoi_signal_operation_type_t op; +} pla_aoi_8to7_cfg_unit_t; + +/** + * @brief aoi_8_to_7 channel config + * + */ +typedef struct pla_aoi_8to7_chn_cfg { + pla_channel_type_t chn; /**< pla channel */ + pla_aoi_8to7_channel_type_t aoi_8to7_chn; /**< aoi_16to8 channel */ + pla_aoi_8to7_cfg_unit_t input[PLA_AOI_8TO7_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */ +} pla_aoi_8to7_chn_cfg_t; + +/** + * @brief pla filter config + * + */ +typedef union pla_filter_cfg { + struct { + uint32_t sync_edge_filter_disable:1; + uint32_t software_inject:2; + uint32_t filter_reverse:1; + uint32_t edge_dect_en:1; + uint32_t nege_edge_dect_en:1; + uint32_t pose_edge_dect_en:1; + uint32_t filter_sync_level:1; + uint32_t filter_ext_en:1; + uint32_t reserved0:3; + uint32_t filter_ext_type:3; + uint32_t reserved1:1; + uint32_t filter_ext_counter:16; + }; + uint32_t val; +} pla_filter_cfg_t; + +/** + * @brief pla function selection config + * + */ +typedef union pla_ff_cfg { + struct { + uint32_t sel_cfg_ff_type:3; + uint32_t sel_clk_source:1; + uint32_t sel_adder_minus:1; + uint32_t reserved0:11; + uint32_t dis_osc_loop_clamp:1; + uint32_t osc_loop_clamp_value:1; + uint32_t reserved1:14; + }; + uint32_t val; +} pla_ff_cfg_t; + +/** + * @brief pla configurable functions + * + */ +typedef enum pla_ff_type { + pla_ff_type_dff = 0, + pla_ff_type_level3_filter0 = 1, + pla_ff_type_dual_edge_DFF = 2, + pla_ff_type_trigger_ff = 3, + pla_ff_type_jk_ff = 4, + pla_ff_type_latch = 5, + pla_ff_type_adder_minus = 6 +} pla_ff_type_t; + + +typedef enum pla_filter1_inchannel_type { + pla_filter1_inchn0 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0, + pla_filter1_inchn1 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1, + pla_filter1_inchn2 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2, + pla_filter1_inchn3 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3, + pla_filter1_inchn4 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4, + pla_filter1_inchn5 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5, + pla_filter1_inchn6 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6, + pla_filter1_inchn7 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7, +} pla_filter1_inchannel_type_t; + +typedef enum pla_filter1_outchannel_type { + pla_filter1_outchn0 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0, + pla_filter1_outchn1 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1, + pla_filter1_outchn2 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2, + pla_filter1_outchn3 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3, + pla_filter1_outchn4 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4, + pla_filter1_outchn5 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5, + pla_filter1_outchn6 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6, + pla_filter1_outchn7 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7, +} pla_filter1_outchannel_type_t; + + +typedef enum pla_filter2_channel_type { + pla_filter2_chn0 = PLA_CHN_FILTER_2ND_SECOND_FILTER_0, + pla_filter2_chn1 = PLA_CHN_FILTER_2ND_SECOND_FILTER_1, + pla_filter2_chn2 = PLA_CHN_FILTER_2ND_SECOND_FILTER_2, + pla_filter2_chn3 = PLA_CHN_FILTER_2ND_SECOND_FILTER_3, + pla_filter2_chn4 = PLA_CHN_FILTER_2ND_SECOND_FILTER_4, + pla_filter2_chn5 = PLA_CHN_FILTER_2ND_SECOND_FILTER_5, + pla_filter2_chn6 = PLA_CHN_FILTER_2ND_SECOND_FILTER_6, + pla_filter2_chn7 = PLA_CHN_FILTER_2ND_SECOND_FILTER_7, +} pla_filter2_channel_type_t; + +typedef enum pla_filter3_channel_type { + pla_filter3_chn0 = PLA_CHN_FILTER_3RD_THIRD_FILTER_0, + pla_filter3_chn1 = PLA_CHN_FILTER_3RD_THIRD_FILTER_1, + pla_filter3_chn2 = PLA_CHN_FILTER_3RD_THIRD_FILTER_2, + pla_filter3_chn3 = PLA_CHN_FILTER_3RD_THIRD_FILTER_3, + pla_filter3_chn4 = PLA_CHN_FILTER_3RD_THIRD_FILTER_4, + pla_filter3_chn5 = PLA_CHN_FILTER_3RD_THIRD_FILTER_5, + pla_filter3_chn6 = PLA_CHN_FILTER_3RD_THIRD_FILTER_6, +} pla_filter3_channel_type_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configure one channel of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param cfg @ref pla_aoi_16to8_cfg_t + */ +void pla_set_aoi_16to8_one_channel(PLA_Type * pla, + pla_aoi_16to8_chn_cfg_t *cfg); + +/** + * @brief Get one channel of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t + * @param cfg @ref pla_aoi_16to8_chn_cfg_t + */ +void pla_get_aoi_16to8_one_channel(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_chn_cfg_t *cfg); + +/** + * @brief Set one signal of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t + * @param cfg @ref pla_aoi_16to8_cfg_unit_t + */ +static inline void pla_set_aoi_16to8_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_cfg_unit_t *cfg) +{ + pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] = pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] & + ~(((uint32_t)cfg->op) << (cfg->signal << 1)); +} + +/** + * @brief Get one signal of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t + * @param signal @ref pla_aoi_16to8_input_signal_type_t + * @param cfg @ref pla_aoi_16to8_cfg_unit_t + */ +static inline void pla_get_aoi_16to8_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_input_signal_type_t signal, + pla_aoi_16to8_cfg_unit_t *cfg) +{ + cfg->op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (signal << 1)) & 0x03; + cfg->signal = signal; +} + + +/** + * @brief Configure one channel of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param cfg @ref pla_aoi_8to7_chn_cfg_t + */ +void pla_set_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg); + +/** + * @brief Get one channel of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param cfg @ref pla_aoi_8to7_chn_cfg_t + */ +void pla_get_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg); + +/** + * @brief Configure one signal of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_8to7_channel_type_t + * @param cfg @ref pla_aoi_8to7_cfg_unit_t + */ +void pla_set_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_cfg_unit_t *cfg); + +/** + * @brief Get one signal of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_8to7_chn @ref pla_aoi_8to7_channel_type_t + * @param signal @ref pla_aoi_8to7_input_signal_type_t + * @param cfg @ref pla_aoi_8to7_cfg_unit_t + */ +void pla_get_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_input_signal_type_t signal, + pla_aoi_8to7_cfg_unit_t *cfg); + +/** + * @brief Configure filter1 out + * + * @param pla @ref PLA_Type + * @param filter1_out_chn @ref pla_filter1_outchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter1_out(PLA_Type *pla, + pla_filter1_outchannel_type_t filter1_out_chn, + pla_filter_cfg_t *cfg) +{ + pla->FILTER_1ST_PLA_OUT[filter1_out_chn] = cfg->val; +} + +/** + * @brief Get filter1 out + * + * @param pla @ref PLA_Type + * @param filter1_out_chn @ref pla_filter1_outchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter1_out(PLA_Type *pla, + pla_filter1_outchannel_type_t filter1_out_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->FILTER_1ST_PLA_OUT[filter1_out_chn]; +} + +/** + * @brief Configure filter1 in + * + * @param pla @ref PLA_Type + * @param filter1_in_chn @ref pla_filter1_inchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter1_in(PLA_Type *pla, + pla_filter1_inchannel_type_t filter1_in_chn, + pla_filter_cfg_t *cfg) +{ + pla->FILTER_1ST_PLA_IN[filter1_in_chn] = cfg->val; +} + +/** + * @brief Get filter 1 + * + * @param pla @ref PLA_Type + * @param filter1_in_chn @ref pla_filter1_inchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter1_in(PLA_Type *pla, + pla_filter1_inchannel_type_t filter1_in_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->FILTER_1ST_PLA_IN[filter1_in_chn]; +} + +/** + * @brief Configure filter 2 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter2_chn @ref pla_filter2_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter2(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter2_channel_type_t filter2_chn, + pla_filter_cfg_t *cfg) +{ + pla->CHN[chn].FILTER_2ND[filter2_chn] = cfg->val; +} + +/** + * @brief Get filter2 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter2_chn @ref pla_filter2_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter2(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter2_channel_type_t filter2_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->CHN[chn].FILTER_2ND[filter2_chn]; +} + +/** + * @brief Configure filter3 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter3_chn @ref pla_filter3_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter3(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter3_channel_type_t filter3_chn, + pla_filter_cfg_t *cfg) +{ + pla->CHN[chn].FILTER_3RD[filter3_chn] = cfg->val; +} + +/** + * @brief Get filter3 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter3_chn @ref pla_filter3_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter3(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter3_channel_type_t filter3_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->CHN[chn].FILTER_3RD[filter3_chn]; +} + +/** + * @brief Set ff function + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param cfg @ref pla_ff_cfg_t + */ +static inline void pla_set_ff(PLA_Type *pla, + pla_channel_type_t chn, + pla_ff_cfg_t *cfg) +{ + pla->CHN[chn].CFG_FF = cfg->val; +} + +/** + * @brief Get ff function + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param cfg @ref pla_ff_cfg_t + */ +static inline void pla_get_ff(PLA_Type *pla, + pla_channel_type_t chn, + pla_ff_cfg_t *cfg) +{ + cfg->val = pla->CHN[chn].CFG_FF; +} + +/** + * @brief enable pla channel + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + */ +static inline void pla_channel_enable(PLA_Type *pla, + pla_channel_type_t chn) +{ + pla->CHN_CFG_ACTIVE[chn] = PLA_CHN_CFG_ACTIVE_WORD; +} + +/** + * @brief disable pla channel + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + */ +static inline void pla_channel_disable(PLA_Type *pla, + pla_channel_type_t chn) +{ + pla->CHN_CFG_ACTIVE[chn] = false; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_PLA_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h index 56d52a2049..fcfd3215bf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h index 631a0bc9a9..cbc85cfb5f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -139,6 +139,7 @@ void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, u /** * @brief Initialize PLL to specified frequency + * Note: the specified PLL clock needs to be enabled before being configured * @param [in] ptr PLLCTLV2 base * @param [in] pll PLL index * @param [in] freq_in_hz expected PLL frequency diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h index 7893fb2a36..51f928f263 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h index e735dc0073..0e514c9174 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -183,12 +183,23 @@ uint32_t read_pmp_addr(uint32_t idx); */ uint32_t read_pma_addr(uint32_t idx); + +/** + * @brief Configure PMP and PMA for specified PMP/PMA entry + * + * @param[in] entry PMP entry + * @param entry_index PMP/PMA entry index + * @retval status_invalid_argument Invalid Arguments were detected + * @retval status_success Configuration completed without errors + */ +hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index); + /** * @brief Configure PMP and PMA based on the PMP entry list * @param entry start of the PMP entry list * @param num_of_entries Number of entries in the PMP entry list - * @return #status_invalid_argument - Invalid Arguments were detected - * #status_success - Configuration completed without errors + * @retval status_invalid_argument Invalid Arguments were detected + * @retval status_success Configuration completed without errors */ hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries); diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h index 3cc5c1606e..5ffa929585 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -55,11 +55,11 @@ static inline psec_lifecycle_t psec_get_pmic_lifecycle(PSEC_Type *ptr) static inline hpm_stat_t psec_switch_pmic_state(PSEC_Type *ptr, psec_state_t state) { - if ((state == psec_state_secure)) { + if (state == psec_state_secure) { if (!PSEC_SECURE_STATE_ALLOW_SEC_GET(ptr->SECURE_STATE)) { return status_psec_switch_state_not_allowed; } - } else if ((state == psec_state_non_secure)) { + } else if (state == psec_state_non_secure) { if (!PSEC_SECURE_STATE_ALLOW_NSC_GET(ptr->SECURE_STATE)) { return status_psec_switch_state_not_allowed; } @@ -156,11 +156,11 @@ static inline psec_lifecycle_t psec_get_batt_lifecycle(PSEC_Type *ptr) static inline hpm_stat_t psec_switch_batt_state(PSEC_Type *ptr, batt_sec_state_t state) { - if ((state == batt_sec_state_secure)) { + if (state == batt_sec_state_secure) { if (!PSEC_SECURE_STATE_ALLOW_SEC_GET(ptr->SECURE_STATE)) { return status_psec_switch_state_not_allowed; } - } else if ((state == batt_sec_state_non_secure)) { + } else if (state == batt_sec_state_non_secure) { if (!PSEC_SECURE_STATE_ALLOW_NSC_GET(ptr->SECURE_STATE)) { return status_psec_switch_state_not_allowed; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h index 34e42a244a..5e9d06d1fd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h index 34b403f6da..deb4995222 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -62,7 +62,7 @@ typedef enum pwm_register_update { } pwm_shadow_register_update_trigger_t; /** - * @brief configure the state of channel 0∼7 outputs when the forced output is in effect + * @brief configure the state of channel 0-7 outputs when the forced output is in effect * */ typedef enum pwm_fault_mode { @@ -132,11 +132,17 @@ typedef enum pwm_output_type { typedef struct pwm_cmp_config { uint32_t cmp; /**< compare value */ bool enable_ex_cmp; /**< enable extended compare value */ +#if PWM_SOC_HRPWM_SUPPORT + bool enable_hrcmp; /**< enable high precision pwm */ +#endif uint8_t mode; /**< compare work mode: pwm_cmp_mode_output_compare or pwm_cmp_mode_input_capture */ uint8_t update_trigger; /**< compare configuration update trigger */ uint8_t ex_cmp; /**< extended compare value */ uint8_t half_clock_cmp; /**< half clock compare value*/ uint8_t jitter_cmp; /**< jitter compare value */ +#if PWM_SOC_HRPWM_SUPPORT + uint8_t hrcmp; /**< high precision pwm */ +#endif } pwm_cmp_config_t; /** @@ -238,6 +244,22 @@ static inline void pwm_set_start_count(PWM_Type *pwm_x, | PWM_STA_STA_SET(start); } +#if PWM_SOC_HRPWM_SUPPORT + +/** + * @brief set hrpwm counter start value + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param start pwm timer counter start value + */ +static inline void pwm_set_hrpwm_start_count(PWM_Type *pwm_x, + uint32_t start) +{ + pwm_x->STA_HRPWM = PWM_STA_HRPWM_STA_SET(start); +} + +#endif + /** * @brief set the reload value * @@ -254,6 +276,26 @@ static inline void pwm_set_reload(PWM_Type *pwm_x, | PWM_RLD_RLD_SET(reload); } +#if PWM_SOC_HRPWM_SUPPORT + +/** + * @brief set the hr pwm reload value + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param hr_reload pwm timer counter hrpwm reload value + * @param reload pwm timer counter reload value + */ +static inline void pwm_set_hrpwm_reload(PWM_Type *pwm_x, + uint16_t hrpwm_reload, + uint32_t reload) +{ + pwm_shadow_register_unlock(pwm_x); + pwm_x->RLD_HRPWM = PWM_RLD_HRPWM_RLD_HR_SET(hrpwm_reload) + | PWM_RLD_HRPWM_RLD_SET(reload); +} + +#endif + /** * @brief clear pwm status register * @@ -270,6 +312,20 @@ static inline void pwm_clear_status(PWM_Type *pwm_x, uint32_t mask) pwm_x->SR |= mask; } +#if PWM_SOC_TIMER_RESET_SUPPORT + +/** + * @brief Reset timer and extension timer + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_timer_reset(PWM_Type *pwm_x) +{ + pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_TIMERRESET_MASK)) | PWM_GCR_TIMERRESET_SET(1)); +} + +#endif + /** * @brief get pwm status register * @@ -388,24 +444,56 @@ static inline void pwm_set_load_counter_shadow_register_trigger(PWM_Type *pwm_x, } /** - * @brief configure the hardware to trigger the shadow register to update the CMP + * @brief Configure input capture cmp to trigger shadow register updates * * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] edge which edge is used as shadow register hardware load event + * @param[in] is_falling_edge which edge is used as shadow register hardware load event * @arg 1- falling edge * @arg 0- rising edge */ static inline void pwm_load_cmp_shadow_on_capture(PWM_Type *pwm_x, uint8_t index, - bool edge) + bool is_falling_edge) { pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_CMPSHDWSEL_MASK | PWM_GCR_HWSHDWEDG_MASK)) | PWM_GCR_CMPSHDWSEL_SET(index) - | PWM_GCR_HWSHDWEDG_SET(edge)); + | PWM_GCR_HWSHDWEDG_SET(is_falling_edge)); } +#if PWM_SOC_SHADOW_TRIG_SUPPORT +/** + * @brief Set the timer shadow register to update the trigger edge + * + * @param[in] pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] is_falling_edge which edge is used as shadow register hardware load event + * @arg 1- falling edge + * @arg 0- rising edge + */ +static inline void pwm_set_cnt_shadow_trig_edge(PWM_Type *pwm_x, + bool is_falling_edge) +{ + pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_EDGE_MASK) + | PWM_SHCR_CNT_UPDATE_EDGE_SET(is_falling_edge)); +} + +/** + * @brief Set the force output shadow register to update the trigger edge + * + * @param[in] pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] is_falling_edge which edge is used as shadow register hardware load event + * @arg 1- falling edge + * @arg 0- rising edge + */ +static inline void pwm_set_force_shadow_trig_edge(PWM_Type *pwm_x, + bool is_falling_edge) +{ + pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_FORCE_UPDATE_EDGE_MASK) + | PWM_SHCR_FORCE_UPDATE_EDGE_SET(is_falling_edge)); +} + +#endif /** * @brief disable pwn cmp half clock * @@ -455,6 +543,35 @@ static inline void pwm_cmp_update_cmp_value(PWM_Type *pwm_x, uint8_t index, | PWM_CMP_CMP_SET(cmp) | PWM_CMP_XCMP_SET(ex_cmp); } +#if PWM_SOC_HRPWM_SUPPORT +/** + * @brief update high-precision cmp value + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] cmp clock counter compare value + * @param[in] hrcmp high-precision pwm + */ +static inline void pwm_cmp_update_hrcmp_value(PWM_Type *pwm_x, uint8_t index, + uint32_t cmp, uint16_t hrcmp) +{ + pwm_x->CMP_HRPWM[index] = (pwm_x->CMP_HRPWM[index] & ~(PWM_CMP_HRPWM_CMP_MASK | PWM_CMP_HRPWM_CMP_HR_MASK)) + | PWM_CMP_HRPWM_CMP_SET(cmp) | PWM_CMP_HRPWM_CMP_HR_SET(hrcmp); +} +#endif + +/** + * @brief Forced update of pwm cmp register value, cmp content guaranteed accurate by user + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] cmp cmp register data + */ +static inline void pwm_cmp_force_value(PWM_Type *pwm_x, uint8_t index, uint32_t cmp) +{ + pwm_x->CMP[index] = cmp; +} + /** * @brief config pwm cmp * @@ -466,12 +583,22 @@ static inline void pwm_config_cmp(PWM_Type *pwm_x, uint8_t index, pwm_cmp_config { pwm_shadow_register_unlock(pwm_x); if (config->mode == pwm_cmp_mode_output_compare) { - pwm_x->CMPCFG[index] = PWM_CMPCFG_XCNTCMPEN_SET(config->enable_ex_cmp) +#if PWM_SOC_HRPWM_SUPPORT + if (config->enable_hrcmp) { + pwm_x->CMPCFG[index] = PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); + pwm_x->CMP[index] = PWM_CMP_HRPWM_CMP_SET(config->cmp) + | PWM_CMP_HRPWM_CMP_HR_SET(config->hrcmp); + } else { +#endif + pwm_x->CMPCFG[index] = PWM_CMPCFG_XCNTCMPEN_SET(config->enable_ex_cmp) | PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); - pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) + pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) | PWM_CMP_XCMP_SET(config->ex_cmp) | PWM_CMP_CMPHLF_SET(config->half_clock_cmp) | PWM_CMP_CMPJIT_SET(config->jitter_cmp); +#if PWM_SOC_HRPWM_SUPPORT + } +#endif } else { pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; } @@ -771,14 +898,108 @@ hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, * @brief update raw compare value for central aligned waveform * * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] cmp1_index index of cmp1 to be adjusted (cmp1_index must even number) - * @param[in] cmp2_index index of cmp2 to be adjusted (cmp2_index must odd number) + * @param[in] cmp1_index index of cmp1 to be adjusted (cmp1_index must be even number) + * @param[in] cmp2_index index of cmp2 to be adjusted (cmp2_index must be odd number) * @param[in] target_cmp1 target compare value for cmp1 * @param[in] target_cmp2 target compare value for cmp2 * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success cmp1_index */ hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2); +#if PWM_SOC_HRPWM_SUPPORT +/** + * @brief Enable high-precision pwm + * + * @param[in] pwm_x @ref PWM_Type PWM base address + */ +static inline void pwm_enable_hrpwm(PWM_Type *pwm_x) +{ + pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK)) | PWM_GCR_HR_PWM_EN_SET(1); +} + +/** + * @brief Disable high-precision pwm + * + * @param[in] pwm_x @ref PWM_Type PWM base address + */ +static inline void pwm_disable_hrpwm(PWM_Type *pwm_x) +{ + pwm_x->GCR = pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK); +} + +/** + * @brief Calibrate all channels of hrpwm + * + * @param[in] pwm_x @ref PWM_Type PWM base address + */ +static inline void pwm_cal_hrpwm_start(PWM_Type *pwm_x) +{ + pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_MASK; +} + +/** + * @brief Calibrate specified hrpwm channels + * + * @param[in] pwm_x @ref PWM_Type PWM base address + * @param[in] chn Channel number + */ +static inline void pwm_cal_hrpwm_chn_start(PWM_Type *pwm_x, uint8_t chn) +{ + pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_SET(chn); +} + +/** + * @brief Wait for the completion of calibration of the specified channel of high-precision PWM, blocking + * + * @param[in] pwm_x @ref PWM_Type PWM base address + * @param[in] chn Channel number + */ +static inline void pwm_cal_hrpwm_chn_wait(PWM_Type *pwm_x, uint8_t chn) +{ + while (PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn])) { + }; +} + +/** + * @brief get calibration status + * + * @param[in] pwm_x pwm_x @ref PWM_Type PWM base address + * @param[in] chn Channel number + * @return uint32_t finished will be set zero. + */ +static inline uint32_t pwm_get_cal_hrpwm_status(PWM_Type *pwm_x, uint8_t chn) +{ + return PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn]); +} + +/** + * @brief update raw high-precision compare value for edge aligned waveform + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] cmp_index index of cmp to be adjusted (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] target_cmp target compare value + * @param[in] target_hrcmp target high-precision compare value + * @return hpm_stat_t + */ +hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp, + uint16_t target_hrcmp); + +/** + * @brief update raw high-precision compare value for central aligned waveform + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] cmp1_index index of cmp1 to be adjusted (cmp1_index must be even number) + * @param[in] cmp2_index index of cmp2 to be adjusted (cmp2_index must be odd number) + * @param[in] target_cmp1 target compare value for cmp1 + * @param[in] target_cmp2 target compare value for cmp2 + * @param[in] target_hrcmp1 target high-precision compare value for cmp1 + * @param[in] target_hrcmp2 target high-precision compare value for cmp2 + * @return hpm_stat_t + */ +hpm_stat_t pwm_update_raw_hrcmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, + uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2, + uint16_t target_hrcmp1, uint16_t target_hrcmp2); +#endif #ifdef __cplusplus } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h index 098210d5e0..6b52d498ba 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -62,6 +62,17 @@ typedef enum qei_work_mode { qei_work_mode_ud = 2, /**< Up and Down (UD) mode */ } qei_work_mode_t; +/** + * @brief speed history type + * + */ +typedef enum qei_speed_his_type { + qei_speed_his0 = QEI_SPDHIS_SPDHIS0, /**< Speed history0 */ + qei_speed_his1 = QEI_SPDHIS_SPDHIS1, /**< Speed history1 */ + qei_speed_his2 = QEI_SPDHIS_SPDHIS2, /**< Speed history2 */ + qei_speed_his3 = QEI_SPDHIS_SPDHIS3, /**< Speed history3 */ +} qei_speed_his_type_t; + #ifdef __cplusplus extern "C" { #endif @@ -272,8 +283,7 @@ static inline bool qei_get_bit_status(QEI_Type *qei_x, uint32_t mask) { if ((qei_x->SR & mask) == mask) { return true; - } - else{ + } else { return false; } } @@ -394,16 +404,12 @@ static inline uint32_t qei_get_count_on_snap1_event(QEI_Type *qei_x, * @brief get speed history * * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] hist_index @ref QEI_SPDHIS_SPDHIS1 ,QEI_SPDHIS_SPDHISx(x=0...n) + * @param[in] hist_index @ref qei_speed_his_type_t * @retval speed history value - * @arg 0 - hist_index out of range * @arg counter value */ -static inline uint32_t qei_get_speed_history(QEI_Type *qei_x, uint8_t hist_index) +static inline uint32_t qei_get_speed_history(QEI_Type *qei_x, qei_speed_his_type_t hist_index) { - if (hist_index > QEI_SPDHIS_SPDHIS3) { - return 0; - } return QEI_SPDHIS_SPDHIS0_GET(qei_x->SPDHIS[hist_index]); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h index 665a228b97..e35f01c503 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h index 7a4514caa8..6b9cbeb554 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -165,7 +165,7 @@ typedef struct { uint8_t enable_differential_clk; /**< Enable differential clock */ uint8_t reserved1[5]; /**< Reserved */ uint32_t access_flags; /**< Access flags */ -}xpi_config_t; +} xpi_config_t; /** * @brief XPI Device Configuration structure diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h index b9af512fad..dd5e63319f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_ram_def.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_ram_def.h index 400d713015..01990ca2fd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_ram_def.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_ram_def.h @@ -75,8 +75,7 @@ typedef struct { /** * @brief XPI RAM type options */ -enum -{ +enum { xpi_ram_type_apmemory_x8 = 0, /**< APMemory PSRAM X8 */ xpi_ram_type_hyperram = 1, /**< HyperRAM */ xpi_ram_type_apmemory_x4 = 2, /**< APMemory PSRAM X4 */ @@ -85,8 +84,7 @@ enum /** * @brief HyperRAM voltage options */ -enum -{ +enum { xpi_ram_option_misc_hyperram_3v0, xpi_ram_option_misc_hyperram_1v8, }; @@ -95,8 +93,7 @@ enum /** * @brief XPI RAM maximum CS low time definition */ -enum -{ +enum { xpi_ram_default_max_cs_low_time_us = 4, /**< Default Maximum CS low internal is 4us */ }; @@ -122,7 +119,7 @@ enum { typedef struct { uint8_t cmd_type; /**< Command type */ uint8_t param_size; /**< Size of the parameter */ -}device_config_t; +} device_config_t; /** * @brief XPI RAM information structure diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h index b38e699c26..a959fef11d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,6 +33,7 @@ typedef struct { */ #define RTC_ALARM_TYPE_ONE_SHOT (0U) /**< The RTC alarm will be triggered only once */ #define RTC_ALARM_TYPE_PERIODIC (1U) /**< The RTC alarm will be triggered periodically */ +#define RTC_ALARM_TYPE_ABSOLUTE_TIME_ONE_SHOT (2U) /**< The RTC alarm will be triggered via the absolute time provided via period */ /** * @brief Typical RTC alarm period definitions @@ -87,8 +88,7 @@ static inline void rtc_enable_alarm_interrupt(RTC_Type *base, uint32_t index, bo if (enable) { base->ALARM_EN |= mask; - } - else { + } else { base->ALARM_EN &= ~mask; } } @@ -134,4 +134,4 @@ static inline bool rtc_is_alarm_flag_asserted(RTC_Type *base, uint32_t index) * */ -#endif // HPM_RTC_DRV_H +#endif /* HPM_RTC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h new file mode 100644 index 0000000000..184bd46681 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h @@ -0,0 +1,468 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDM_DRV_H +#define HPM_SDM_DRV_H + +#include "hpm_common.h" +#include "hpm_sdm_regs.h" + +/* defined channel mask macro */ +#define SAMPLING_MODE_MASK (0x7U) +#define CHN_SAMPLING_MODE_SHIFT(ch) ((ch) * 3U + SDM_CTRL_CHMD_SHIFT) +#define CHN_SAMPLING_MODE_MASK(ch) (SAMPLING_MODE_MASK << CHN_SAMPLING_MODE_SHIFT(ch)) + +#define CH0_EN_MASK (0x1U << SDM_CTRL_CH_EN_SHIFT) +#define CHN_EN_MASK(ch) (CH0_EN_MASK << (ch)) + +#define CHN_ERR_MASK(ch) (SDM_INT_EN_CH0ERR_MASK << (ch)) +#define CHN_DRY_MASK(ch) (SDM_INT_EN_CH0DRY_MASK << (ch)) + +typedef enum { + sdm_sampling_rising_clk_edge = 0, + sdm_sampling_every_clk_edge = 1, + sdm_sampling_manchester_mode = 2, + sdm_sampling_falling_clk_edge = 3, + sdm_sampling_rising_two_clk_edge = 4, + sdm_sampling_falling_two_clk_edge = 5 +} sdm_sampling_mode_t; + +typedef enum { + sdm_filter_sinc1 = 0, + sdm_filter_sinc2 = 1, + sdm_filter_sinc3 = 2, + sdm_filter_fast_sinc2 = 3 +} sdm_filter_type_t; + +typedef struct { + bool clk_signal_sync; + bool data_signal_sync; + bool interrupt_en; +} sdm_control_t; + +typedef struct { + uint8_t sampling_mode; + bool enable_err_interrupt; + bool enable_data_ready_interrupt; +} sdm_channel_common_config_t; + +typedef struct { + uint16_t high_threshold; + uint16_t zero_cross_threshold; + uint16_t low_threshold; + + bool en_zero_cross_threshold_int; + bool en_clock_invalid_int; + bool en_high_threshold_int; + bool en_low_threshold_int; + uint8_t filter_type; /**< sdm_filter_type_t */ + uint8_t oversampling_rate; /**< 1 - 32 */ + uint8_t ignore_invalid_samples; + bool enable; +} sdm_comparator_config_t; + +typedef struct { + uint8_t fifo_threshold; + bool en_fifo_threshold_int; + uint8_t manchester_threshold :8; + uint8_t wdg_threshold :8; + uint8_t en_af_int :1; + uint8_t en_data_overflow_int :1; + uint8_t en_cic_data_saturation_int :1; + uint8_t en_data_ready_int :1; + uint8_t sync_source :6; + uint8_t fifo_clean_on_sync :1; /**< fifo clean by hardware when fifo interrupt occurred */ + uint8_t wtsynaclr :1; + uint8_t wtsynmclr :1; + uint8_t wtsyncen :1; + uint8_t output_32bit :1; + uint8_t data_ready_flag_by_fifo :1; + uint8_t enable :1; + + uint8_t filter_type; /**< sdm_filter_type_t */ + bool pwm_signal_sync; + uint8_t output_offset; /**< 16bit mode need configure this */ + uint16_t oversampling_rate; /**< 1-256 */ + uint8_t ignore_invalid_samples; +} sdm_filter_config_t; + +typedef struct { + uint32_t count; + uint8_t *buff; + uint8_t data_len_in_bytes; /* 16bit-2 32bit-4 */ + bool using_fifo; +} sdm_output_config_t; + +typedef enum { + sdm_comparator_no_event = 0, + sdm_comparator_event_out_high_threshold = SDM_CH_SCST_CMPH_MASK, + sdm_comparator_event_out_low_threshold = SDM_CH_SCST_CMPL_MASK, + sdm_comparator_event_hz = SDM_CH_SCST_HZ_MASK, + sdm_comparator_event_invalid_clk = SDM_CH_SCST_MF_MASK +} sdm_comparator_event_t; + +typedef enum { + sdm_chn0_error_mask = SDM_INT_EN_CH0ERR_MASK, + sdm_chn1_error_mask = SDM_INT_EN_CH1ERR_MASK, + sdm_chn2_error_mask = SDM_INT_EN_CH2ERR_MASK, + sdm_chn3_error_mask = SDM_INT_EN_CH3ERR_MASK, + sdm_chn0_data_ready_mask = SDM_INT_EN_CH0DRY_MASK, + sdm_chn1_data_ready_mask = SDM_INT_EN_CH1DRY_MASK, + sdm_chn2_data_ready_mask = SDM_INT_EN_CH2DRY_MASK, + sdm_chn3_data_ready_mask = SDM_INT_EN_CH3DRY_MASK +} sdm_channel_int_status_mask_t; + +typedef enum { + sdm_chn0_enable_mask = 1U << SDM_CTRL_CH_EN_SHIFT, + sdm_chn1_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 1U), + sdm_chn2_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 2U), + sdm_chn3_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 3U) +} sdm_channel_enable_mask_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief sdm enable module interrupt + * + * @param ptr SDM base address + * @param enable true for enable, false for disable + */ +static inline void sdm_enable_module_interrupt(SDM_Type *ptr, bool enable) +{ + if (enable) { + ptr->CTRL |= SDM_CTRL_IE_MASK; + } else { + ptr->CTRL &= ~SDM_CTRL_IE_MASK; + } +} + +/** + * @brief sdm enable channel + * + * @param ptr SDM base address + * @param ch_index channel index + * @param enable true for enable, false for disable + */ +static inline void sdm_enable_channel(SDM_Type *ptr, uint8_t ch_index, bool enable) +{ + if (enable) { + ptr->CTRL |= CHN_EN_MASK(ch_index); + } else { + ptr->CTRL &= ~CHN_EN_MASK(ch_index); + } +} + +/** + * @brief sdm enable channel by mask + * + * @note ch_mask supports bitwise or operation, this API could enable multiple channels at the same time + * + * @param ptr SDM base address + * @param ch_mask sdm_channel_enable_mask_t + */ +static inline void sdm_enable_channel_by_mask(SDM_Type *ptr, uint32_t ch_mask) +{ + ptr->CTRL = (ptr->CTRL & (~SDM_CTRL_CH_EN_MASK)) | ch_mask; +} + +/** + * @brief sdm set channel sampling mode + * + * @param ptr SDM base address + * @param ch_index channel index + * @param mode sdm_sampling_mode_t + */ +static inline void sdm_set_channel_sampling_mode(SDM_Type *ptr, uint8_t ch_index, sdm_sampling_mode_t mode) +{ + ptr->CTRL &= ~CHN_SAMPLING_MODE_MASK(ch_index); + ptr->CTRL |= mode << (SDM_CTRL_CHMD_SHIFT + ch_index); +} + +/** + * @brief sdm enable channel interrupt + * + * @param ptr SDM base address + * @param mask sdm_channel_int_status_mask_t, support bitwise or operation + */ +static inline void sdm_enable_channel_interrupt(SDM_Type *ptr, uint32_t mask) +{ + ptr->INT_EN |= mask; +} + +/** + * @brief sdm get status register value + * + * @param ptr SDM base address + * @return uint32_t sdm status register value + */ +static inline uint32_t sdm_get_status(SDM_Type *ptr) +{ + return ptr->STATUS; +} + +/** + * @brief get channel data ready status + * + * @param ptr SDM base address + * @param ch channel + * @return true data ready + * @return false not ready + */ +static inline bool sdm_get_channel_data_ready_status(SDM_Type *ptr, uint8_t ch) +{ + return (((ptr->STATUS) & CHN_DRY_MASK(ch)) == CHN_DRY_MASK(ch)); +} + +/** + * @brief get channel error status + * + * @param ptr SDM base address + * @param ch channel + * @return true error occur + * @return false no error + */ +static inline bool sdm_get_channel_data_error_status(SDM_Type *ptr, uint8_t ch) +{ + return (((ptr->STATUS) & CHN_ERR_MASK(ch)) == CHN_ERR_MASK(ch)); +} + +/** + * @brief sdm set channel's fifo threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param threshold threshold value + */ +static inline void sdm_set_ch_fifo_threshold(SDM_Type *ptr, uint8_t ch, uint8_t threshold) +{ + ptr->CH[ch].SDFIFOCTRL = SDM_CH_SDFIFOCTRL_THRSH_SET(threshold); +} + +/** + * @brief sdm get channel fifo threshold + * + * @param ptr SDM base address + * @param ch channel index + * @return uint8_t fifo threshold value + */ +static inline uint8_t sdm_get_ch_fifo_threshold(SDM_Type *ptr, uint8_t ch) +{ + return (uint8_t)(SDM_CH_SDFIFOCTRL_THRSH_GET(ptr->CH[ch].SDFIFOCTRL)); +} + +/** + * @brief sdm get channel filter status + * + * @param ptr SDM base address + * @param ch channel index + * @return uint32_t channel filter status register value + */ +static inline uint32_t sdm_get_channel_filter_status(SDM_Type *ptr, uint8_t ch) +{ + return ptr->CH[ch].SDST; +} + +/** + * @brief sdm get channel data count in fifo + * + * @param ptr SDM base address + * @param ch channel index + * @return uint8_t data count + */ +static inline uint8_t sdm_get_channel_fifo_data_count(SDM_Type *ptr, uint8_t ch) +{ + return (uint8_t)(SDM_CH_SDST_FILL_GET(ptr->CH[ch].SDST)); +} + +/** + * @brief sdm get channel filter output data in fifo + * + * @param ptr SDM base address + * @param ch channel index + * @return int32_t data + */ +static inline int32_t sdm_get_channel_fifo_data(SDM_Type *ptr, uint8_t ch) +{ + return ptr->CH[ch].SDFIFO; +} + +/** + * @brief sdm get channel input clock cycle count + * + * @param ptr SDM base address + * @param ch channel index + * @return uint8_t clock cycle count + */ +static inline uint8_t sdm_get_channel_clock_cycle_count(SDM_Type *ptr, uint8_t ch) +{ + return (uint8_t)(SDM_CH_SDST_PERIOD_MCLK_GET(ptr->CH[ch].SDST)); +} + +/** + * @brief sdm get channel comparator data + * + * @param ptr SDM base address + * @param ch channel index + * @return uint16_t comparator data + */ +static inline uint16_t sdm_get_channel_comparator_data(SDM_Type *ptr, uint8_t ch) +{ + return (uint16_t)(ptr->CH[ch].SCAMP); +} + +/** + * @brief sdm set channel comparator high threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param value high threshold value + */ +static inline void sdm_set_channel_comparator_high_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) +{ + ptr->CH[ch].SCHTL = value; +} + +/** + * @brief sdm set channel comparator zero crossing threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param value zero crossing threshold value + */ +static inline void sdm_set_channel_comparator_zero_crossing_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) +{ + ptr->CH[ch].SCHTLZ = value; +} + +/** + * @brief sdm set channel comparator low threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param value low threshold value + */ +static inline void sdm_set_channel_comparator_low_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) +{ + ptr->CH[ch].SCLLT = value; +} + +/** + * @brief sdm get channel comparator status register value + * + * @param ptr SDM base address + * @param ch channel index + * @return uint32_t channel comparator status register value + */ +static inline uint32_t sdm_get_channel_comparator_status(SDM_Type *ptr, uint8_t ch) +{ + return ptr->CH[ch].SCST; +} + +/** + * @brief sdm get default module control + * + * @param ptr SDM base address + * @param control sdm_control_t + */ +void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control); + +/** + * @brief sdm init module + * + * @param ptr SDM base address + * @param control sdm_control_t + */ +void sdm_init_module(SDM_Type *ptr, sdm_control_t *control); + +/** + * @brief sdm get channel common setting + * + * @param ptr SDM base address + * @param config sdm_channel_common_config_t + */ +void sdm_get_channel_common_setting(SDM_Type *ptr, sdm_channel_common_config_t *config); + +/** + * @brief sdm config channel's common setting + * + * @param ptr SDM base address + * @param ch_index channel index + * @param config sdm_channel_common_config_t + */ +void sdm_config_channel_common_setting(SDM_Type *ptr, uint8_t ch_index, sdm_channel_common_config_t *config); + +/** + * @brief sdm get channel default filter config + * + * @param ptr SDM base address + * @param filter_config sdm_filter_config_t + */ +void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *filter_config); + +/** + * @brief sdm config channel filter + * + * @param ptr SDM base address + * @param ch_index channel index + * @param filter_config sdm_filter_config_t + */ +void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_config_t *filter_config); + +/** + * @brief sdm get channel default comparator config + * + * @param ptr SDM base address + * @param cmp_config sdm_comparator_config_t + */ +void sdm_get_channel_default_comparator_config(SDM_Type *ptr, sdm_comparator_config_t *cmp_config); + +/** + * @brief sdm config channel comparator + * + * @param ptr SDM base address + * @param ch_index channel index + * @param cmp_config sdm_comparator_config_t + */ +void sdm_config_channel_comparator(SDM_Type *ptr, uint8_t ch_index, sdm_comparator_config_t *cmp_config); + +/** + * @brief sdm receive one filter data + * + * @param ptr SDM base address + * @param ch_index channel index + * @param using_fifo true for getting data from fifo, false for getting data from register + * @param data data buff + * @param data_len_in_bytes output data len in bytes + * @retval hpm_stat_t status_success only if it succeeds + */ +hpm_stat_t sdm_receive_one_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint8_t data_len_in_bytes); + +/** + * @brief sdm receive filter data + * + * @param ptr SDM base address + * @param ch_index channel index + * @param using_fifo true for getting data from fifo, false for getting data from register + * @param data data buff + * @param count data count + * @param data_len_in_bytes output data len in bytes + * @retval hpm_stat_t status_success only if it succeeds + */ +hpm_stat_t sdm_receive_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint32_t count, uint8_t data_len_in_bytes); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_SDM_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h index 319af4f7df..b7c20a6fcf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,6 +18,7 @@ #include "hpm_common.h" #include "hpm_sdp_regs.h" +#include "hpm_soc_feature.h" /*********************************************************************************************************************** * Definitions @@ -26,32 +27,71 @@ * @brief SDP AES key bit options */ typedef enum { - sdp_aes_keybits_128, /**< 128 bit AES key */ - sdp_aes_keybits_256, /**< 256 bit AES key */ -} sdp_aes_key_bits_t; + sdp_aes_keybits_128 = 0, /**< 128 bit AES key */ + sdp_aes_keybits_256 = 1, /**< 256 bit AES key */ +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + sdp_sm4_keybits_128 = sdp_aes_keybits_128, /* SM4 Key bits */ +#endif +} sdp_crypto_key_bits_t; + +typedef sdp_crypto_key_bits_t sdp_aes_key_bits_t; + +typedef sdp_crypto_key_bits_t sdp_sm4_key_bits_t; /** - * @brief AES operation option + * @brief Crypto operation option */ typedef enum { - sdp_aes_op_encrypt, /**< AES Encrypt operation */ - sdp_aes_op_decrypt, /**< AES Decrypt operation */ -} sdp_aes_op_t; + sdp_aes_op_encrypt, /**< AES Encrypt operation */ + sdp_aes_op_decrypt, /**< AES Decrypt operation */ +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + sdp_sm4_op_encrypt = sdp_aes_op_encrypt, /**< SM4 Encrypt operation */ + sdp_sm4_op_decrypt = sdp_aes_op_decrypt, /**< SM4 Decrypt operation */ +#endif +} sdp_crypto_op_t; + +typedef sdp_crypto_op_t sdp_aes_op_t; + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + +typedef sdp_crypto_op_t sdp_sm4_op_t; + +#endif + +/** + * @brief SDP Crypto algorithms + * + */ +typedef enum { + sdp_crypto_alg_aes, /**< AES */ +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + sdp_crypto_alg_sm4, /**< SM4 */ +#endif +} sdp_crypto_alg_t; /** * @brief SDP HASH algorithm definitions */ typedef enum { - sdp_hash_alg_sha1, /**< SDP SHA1 */ - sdp_hash_alg_crc32, /**< SDP CRC32 */ - sdp_hash_alg_sha256, /**< SDP SHA256 */ + sdp_hash_alg_sha1 = 0, /**< SDP SHA1 */ + sdp_hash_alg_crc32 = 1, /**< SDP CRC32 */ + sdp_hash_alg_sha256 = 2, /**< SDP SHA256 */ +#if defined(SDP_HAS_SM3_SUPPORT) && (SDP_HAS_SM3_SUPPORT == 1) + sdp_hash_alg_sm3 = 8, /**< SDP SM3 */ + sdp_hash_alg_max = sdp_hash_alg_sm3, +#else sdp_hash_alg_max = sdp_hash_alg_sha256, +#endif } sdp_hash_alg_t; -#define HASH_BLOCK_SIZE (64U) /**< Hash block size in bytes */ -#define AES_BLOCK_SIZE (16U) /**< AES block size in bytes */ -#define AES_128_KEY_SIZE (0x10U) /**< AES 128-bit key size in bytes */ -#define AES_256_KEY_SIZE (0x20U) /**< AES 256-bit key size in bytes */ +#define HASH_BLOCK_SIZE (64U) /**< Hash block size in bytes */ +#define AES_BLOCK_SIZE (16U) /**< AES block size in bytes */ +#define AES_128_KEY_SIZE (0x10U) /**< AES 128-bit key size in bytes */ +#define AES_256_KEY_SIZE (0x20U) /**< AES 256-bit key size in bytes */ + +#define SM4_BLOCK_SIZE (AES_BLOCK_SIZE) /**< SM4 block size in bytes */ +#define SM4_KEY_SIZE (AES_128_KEY_SIZE) /**< SM4 Key size in bytes */ + /** * @brief Bitfield definitions for the PKT_CTRL */ @@ -68,15 +108,15 @@ typedef struct _sdp_packet_struct { struct _sdp_packet_struct *next_cmd; union { struct { - uint32_t RESERVED0 : 1; - uint32_t PKTINT : 1; /**< Packet interrupt flag */ - uint32_t DCRSEMA : 1; /**< Descrement Semaphore flag */ - uint32_t CHAIN : 1; /**< Chain Packet flag */ - uint32_t HASHINIT : 1; /**< Hash initialize flag */ - uint32_t HASHFINISH : 1; /**< Hash finish flag */ - uint32_t CIPHIV : 1; /**< Cipher IV flag */ - uint32_t RESERVED1 : 17; - uint32_t PKTTAG : 8; /**< Packet tag flag, not used */ + uint32_t RESERVED0: 1; + uint32_t PKTINT: 1; /**< Packet interrupt flag */ + uint32_t DCRSEMA: 1; /**< Descrement Semaphore flag */ + uint32_t CHAIN: 1; /**< Chain Packet flag */ + uint32_t HASHINIT: 1; /**< Hash initialize flag */ + uint32_t HASHFINISH: 1; /**< Hash finish flag */ + uint32_t CIPHIV: 1; /**< Cipher IV flag */ + uint32_t RESERVED1: 17; + uint32_t PKTTAG: 8; /**< Packet tag flag, not used */ }; uint32_t PKT_CTRL; /**< Packet control word */ } pkt_ctrl; @@ -92,13 +132,19 @@ typedef struct _sdp_packet_struct { typedef struct { uint8_t key_idx; /**< AES key index */ uint8_t key_bits; /**< AES key bits */ - uint16_t reserved; + uint16_t crypto_algo; sdp_pkt_struct_t sdp_pkt; /**< SDP packet for AES operation */ uint32_t buf0[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf0 */ uint32_t buf1[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf1 */ uint32_t buf2[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf2 */ uint32_t buf3[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf3 */ -} sdp_aes_ctx_t; +} sdp_crypto_ctx_t; + +typedef sdp_crypto_ctx_t sdp_aes_ctx_t; + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +typedef sdp_crypto_ctx_t sdp_sm4_ctx_t; +#endif /** * @brief SDP DMA context @@ -130,7 +176,8 @@ enum { status_sdp_error_dst = MAKE_STATUS(status_group_sdp, 8), /**< Error destination address */ status_sdp_error_hash = MAKE_STATUS(status_group_sdp, 9), /**< Error Hash digest */ status_sdp_error_chain = MAKE_STATUS(status_group_sdp, 10), /**< Error packet chain */ - status_sdp_error_invalid_mac, /**< Inavlid Message Athenticaion Code (MAC) */ + status_sdp_error_invalid_mac = MAKE_STATUS(status_group_sdp, 11),/**< Inavlid Message Athenticaion Code (MAC) */ + status_sdp_invalid_alg = MAKE_STATUS(status_group_sdp, 12), /**< Invalid algorithm */ }; @@ -143,168 +190,298 @@ extern "C" /*********************************************************************************************************************** * Prototypes **********************************************************************************************************************/ - /** - * @brief Initialize the SDP controller - * @param [in] base SDP base address - * @retval API execution status. - */ - hpm_stat_t sdp_init(SDP_Type * base); +/** + * @brief Initialize the SDP controller + * @param [in] base SDP base address + * @retval API execution status. + */ +hpm_stat_t sdp_init(SDP_Type *base); - /** - * @brief De-initialize the SDP controller - * @param [in] base SDP base address - * @retval API execution status. - */ - hpm_stat_t sdp_deinit(SDP_Type *base); +/** + * @brief De-initialize the SDP controller + * @param [in] base SDP base address + * @retval API execution status. + */ +hpm_stat_t sdp_deinit(SDP_Type *base); - /** - * @brief Set the AES key for the SDP AES operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] key AES key - * @param [in] key_bits AES key-bit option - * @param [in] key_idx AES key index - * @retval API execution status. - */ - hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, - uint32_t key_idx); +/** + * @brief Set the AES key for the SDP AES operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] key AES key + * @param [in] key_bits AES key-bit option + * @param [in] key_idx AES key index + * @retval API execution status. + */ +hpm_stat_t sdp_aes_set_key(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, + uint32_t key_idx); - /** - * @brief Perform the basic AES ECB operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] op AES operation option - * @param [in] len AES data length in bytes - * @param [in] in Input buffer - * @param [out] out Output buffer - * @retval API execution status. - */ - hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, - uint8_t *out); +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Set the SM4 key for the SDP SM4 operation + * @param [in] base SDP base address + * @param [in] sm4_ctx AES operation context + * @param [in] key SM4 key + * @param [in] key_bits SM4 key-bit option + * @param [in] key_idx AES key index + * @retval API execution status. + */ +hpm_stat_t sdp_sm4_set_key(SDP_Type *base, + sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx); +#endif - /** - * @brief Perform the AES CBC operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] op AES operation option - * @param [in] length AES data length in bytes - * @param [in] iv Initial vector/nonce - * @param [in] input Input buffer - * @param [out] output Output buffer - * @retval API execution status. - */ - hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, - const uint8_t iv[16], const uint8_t *input, uint8_t *output); +/** + * @brief Perform the basic AES ECB operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] op AES operation option + * @param [in] len AES data length in bytes + * @param [in] in Input buffer + * @param [out] out Output buffer + * @retval API execution status. + */ +hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out); - /** - * @brief Perform the AES-CTR operation - * See NIST Special Publication800-38A for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] nonce_counter AES-CTR nounce/counter - * @param [in] input Input buffer - * @param [out] output Output buffer - * @param [in] length Length of data for AES-CTR operation - * @retval API execution status. - */ - hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_counter, uint8_t *input, - uint8_t *output, uint32_t length); +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the basic SM4 ECB operation + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] op SM4 operation option + * @param [in] len SM4 data length in bytes + * @param [in] in Input buffer + * @param [out] out Output buffer + * @retval API execution status. + */ +#define sdp_sm4_crypt_ecb sdp_aes_crypt_ecb +#endif - /** - * @brief Perform the AES-CCM generate and encrypt - * See NIST Special Publication 800-38C for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [out] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @retval API execution status. - */ - hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, uint8_t *tag, uint32_t tag_len); +/** + * @brief Perform the AES CBC operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] op AES operation option + * @param [in] length AES data length in bytes + * @param [in] iv Initial vector/nonce + * @param [in] input Input buffer + * @param [out] output Output buffer + * @retval API execution status. + */ +hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + const uint8_t iv[16], + const uint8_t *input, + uint8_t *output); - /** - * @brief Perform the AES-CCM decrypt and verify - * See NIST Special Publication 800-38C for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [in] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @retval API execution status. - */ - hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, const uint8_t *tag, uint32_t tag_len); +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4 CBC operation + * @param [in] base SM4 base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] op SM4 operation option + * @param [in] length SM4 data length in bytes + * @param [in] iv Initial vector/nonce + * @param [in] input Input buffer + * @param [out] output Output buffer + * @retval API execution status. + */ +#define sdp_sm4_crypt_cbc sdp_aes_crypt_cbc +#endif - /** - * @brief Perform the DMA accelerated memcpy - * @param [in] base SDP base address - * @param [in] sdp_ctx SDP DMA context - * @param [out] dst Destination address for memcpy operation - * @param [in] src Source address for memcpy operation - * @param [in] length Length of the data to be copied - * @retval API execution status. - */ - hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, const void *src, uint32_t length); +/** + * @brief Perform the AES-CTR operation + * See NIST Special Publication800-38A for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] nonce_counter AES-CTR nounce/counter + * @param [in] input Input buffer + * @param [out] output Output buffer + * @param [in] length Length of data for AES-CTR operation + * @retval API execution status. + */ +hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint8_t *nonce_counter, + uint8_t *input, + uint8_t *output, + uint32_t length); - /** - * @brief Perform the DMA accelerated memset - * @param [in] base SDP base address - * @param [in] sdp_ctx SDP DMA context - * @param [out] dst SDP destination address for memset operation - * @param [in] pattern pattern for memset operation - * @param [in] length length of the memory for memset operation - * @retval API execution status. - */ - hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length); +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4-CTR operation + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] nonce_counter SM4-CTR nounce/counter + * @param [in] input Input buffer + * @param [out] output Output buffer + * @param [in] length Length of data for SM4-CTR operation + * @retval API execution status. + */ +#define sdp_sm4_crypt_ctr sdp_aes_crypt_ctr +#endif - /** - * @brief Initialize the HASH engine - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [in] alg Hash algorithm - * @retval API execution status. status_success or status_invalid_argument - */ - hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); +/** + * @brief Perform the AES-CCM generate and encrypt + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [out] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); - /** - * @brief Compute the HASH digest - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [in] data Data for HASH computing - * @param [in] length Data size for HASH computing - * @retval API execution status. - */ - hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4-CCM generate and encrypt + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [out] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +#define sdp_sm4_ccm_generate_encrypt sdp_aes_ccm_generate_encrypt +#endif - /** - * @brief Finish the HASH calculation and output the digest - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [out] digest Digest buffer - * @retval API execution status. - */ - hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest); +/** + * @brief Perform the AES-CCM decrypt and verify + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [in] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); - /** - * @brief Wait until the SDP operation gets done - * @retval API execution status. - */ - hpm_stat_t sdp_wait_done(SDP_Type *base); +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4-CCM decrypt and verify + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [in] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +#define sdp_sm4_ccm_decrypt_verify sdp_aes_ccm_decrypt_verify +#endif +/** + * @brief Perform the DMA accelerated memcpy + * @param [in] base SDP base address + * @param [in] sdp_ctx SDP DMA context + * @param [out] dst Destination address for memcpy operation + * @param [in] src Source address for memcpy operation + * @param [in] length Length of the data to be copied + * @retval API execution status. + */ +hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, const void *src, uint32_t length); + +/** + * @brief Perform the DMA accelerated memset + * @param [in] base SDP base address + * @param [in] sdp_ctx SDP DMA context + * @param [out] dst SDP destination address for memset operation + * @param [in] pattern pattern for memset operation + * @param [in] length length of the memory for memset operation + * @retval API execution status. + */ +hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length); + +/** + * @brief Initialize the HASH engine + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [in] alg Hash algorithm + * @retval API execution status. status_success or status_invalid_argument + */ +hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + +/** + * @brief Compute the HASH digest + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [in] data Data for HASH computing + * @param [in] length Data size for HASH computing + * @retval API execution status. + */ +hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + +/** + * @brief Finish the HASH calculation and output the digest + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [out] digest Digest buffer + * @retval API execution status. + */ +hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + +/** + * @brief Wait until the SDP operation gets done + * @retval API execution status. + */ +hpm_stat_t sdp_wait_done(SDP_Type *base); #ifdef __cplusplus } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h index cf8ca7cb8e..9c824d1d8b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,7 +33,7 @@ #define SDXC_STS_CMD_ERR (SDXC_INT_STAT_CMD_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK |\ SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK | SDXC_INT_STAT_AUTO_CMD_ERR_MASK) -#define SDXC_STS_DATA_ERR (SDXC_INT_STAT_DATA_TOUT_ERR_MASK| SDXC_INT_STAT_DATA_CRC_ERR_MASK | \ +#define SDXC_STS_DATA_ERR (SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_DATA_CRC_ERR_MASK | \ SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) #define SDXC_STS_CARD_ERR (SDXC_INT_STAT_CARD_REMOVAL_MASK) #define SDXC_STS_ERROR (SDXC_INT_STAT_ERR_INTERRUPT_MASK | SDXC_STS_CMD_ERR | SDXC_STS_DATA_ERR | SDXC_STS_CARD_ERR) @@ -366,9 +366,8 @@ typedef struct _sdxc_data { */ enum { sdxc_xfer_data_normal = 0U, /**< Transfer normal read/write data */ - sdxc_xfer_data_tuning = 1U, /**< Transfer Tuning data */ - sdxc_xfer_data_boot = 2U, /**< Transfer boot data */ - sdxc_xfer_data_boot_continuous = 3U, /**< Transfer boot data continuously */ + sdxc_xfer_data_boot = 1U, /**< Transfer boot data */ + sdxc_xfer_data_boot_continuous = 2U, /**< Transfer boot data continuously */ }; /** @@ -696,8 +695,7 @@ static inline void sdxc_enable_software_tuning(SDXC_Type *base, bool enable) { if (enable) { base->AUTO_TUNING_CTRL |= SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK; - } - else { + } else { base->AUTO_TUNING_CTRL &= ~SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK; } } @@ -749,6 +747,28 @@ static inline uint32_t sdxc_get_present_status(SDXC_Type *base) return base->PSTATE; } +/** + * @brief Check whether the Data Buffer is writable or not + * @param [in] base SDXC base address + * @retval true Data buffer is writeable + * @retval false Data buffer write is disabled + */ +static inline bool sdxc_is_data_buf_writable(SDXC_Type *base) +{ + return ((base->PSTATE & SDXC_PSTATE_BUF_WR_ENABLE_MASK) != 0U); +} + +/** + * @brief Check whether the data buffer is readable + * @param [in] base SDXC base address + * @retval true There are data available in data buffer + * @retval false there is no data available in data buffer, read is disabled + */ +static inline bool sdxc_is_data_buf_readable(SDXC_Type *base) +{ + return ((base->PSTATE & SDXC_PSTATE_BUF_RD_ENABLE_MASK) != 0U); +} + /** * @brief Read data from SDXC using non-DMA mode * @param [in] base SDXC base address @@ -855,8 +875,7 @@ static inline void sdxc_enable_enhanced_strobe(SDXC_Type *base, bool enable) { if (enable) { base->EMMC_BOOT_CTRL |= SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK; - } - else { + } else { base->EMMC_BOOT_CTRL &= ~SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK; } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h index 3521aec688..3c65a380bf 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,6 +8,7 @@ #ifndef HPM_SPI_DRV_H #define HPM_SPI_DRV_H #include "hpm_spi_regs.h" +#include "hpm_soc_feature.h" /** * @brief SPI driver APIs @@ -16,6 +17,26 @@ * @{ */ +/** + * @brief spi dma enable + */ +typedef enum { + spi_tx_dma_enable = SPI_CTRL_TXDMAEN_MASK, + spi_rx_dma_enable = SPI_CTRL_RXDMAEN_MASK +} spi_dma_enable_t; + +/** + * @brief spi interrupt mask + */ +typedef enum { + spi_rx_fifo_overflow_int = SPI_INTREN_RXFIFOORINTEN_MASK, + spi_tx_fifo_underflow_int = SPI_INTREN_TXFIFOURINTEN_MASK, + spi_rx_fifo_threshold_int = SPI_INTREN_RXFIFOINTEN_MASK, + spi_tx_fifo_threshold_int = SPI_INTREN_TXFIFOINTEN_MASK, + spi_end_int = SPI_INTREN_ENDINTEN_MASK, + spi_slave_cmd_int = SPI_INTREN_SLVCMDEN_MASK, +} spi_interrupt_t; + /** * @brief spi mode selection */ @@ -267,38 +288,40 @@ void spi_format_init(SPI_Type *ptr, spi_format_config_t *config); * * @param [in] ptr SPI base address * @param [in] config spi_control_config_t - * @param [in] cmd spi transfer mode + * @param [in,out] cmd spi transfer command address * @param [in] addr spi transfer target address * @param [in] wbuff spi sent data buff address - * @param [in] wsize spi sent data size in byte - * @param [in] rbuff spi receive data buff address - * @param [in] rsize spi receive data size + * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @param [out] rbuff spi receive data buff address + * @param [in] rcount spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX * @retval hpm_stat_t status_success if spi transfer without any error */ hpm_stat_t spi_transfer(SPI_Type *ptr, spi_control_config_t *config, uint8_t *cmd, uint32_t *addr, - uint8_t *wbuff, uint32_t wsize, uint8_t *rbuff, uint32_t rsize); + uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount); /** * @brief spi setup dma transfer * * @param [in] ptr SPI base address * @param [in] config spi_control_config_t - * @param [in] cmd spi transfer mode + * @param [in] cmd spi transfer command address * @param [in] addr spi transfer target address - * @param [in] wsize spi sent data size in byte - * @param [in] rsize spi receive data size + * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @param [in] rcount spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX * @retval hpm_stat_t status_success if spi setup dma transfer without any error */ hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, spi_control_config_t *config, uint8_t *cmd, uint32_t *addr, - uint32_t wsize, uint32_t rsize); + uint32_t wcount, uint32_t rcount); /** * @brief spi wait for idle status * + * @note on slave mode, if CS signal is asserted, take it as busy; if SPI CS signal is de-asserted, take it as idle. + * * @param [in] ptr SPI base address * @retval hpm_stat_t status_success if spi in idle status */ @@ -307,11 +330,395 @@ hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr); /** * @brief spi wait for busy status * + * @note on slave mode, if CS signal is asserted, take it as busy; if SPI CS signal is de-asserted, take it as idle. + * * @param [in] ptr SPI base address * @retval hpm_stat_t status_success if spi in busy status */ hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr); +/** + * @brief SPI set TX FIFO threshold + * + * This function configures SPI TX FIFO threshold. + * + * @param ptr SPI base address. + * @param threshold The FIFO threshold value, the value should not greater than FIFO size. + */ +static inline void spi_set_tx_fifo_threshold(SPI_Type *ptr, uint32_t threshold) +{ + ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_TXTHRES_MASK) | SPI_CTRL_TXTHRES_SET(threshold); +} + +/** + * @brief SPI set RX FIFO threshold + * + * This function configures SPI RX FIFO threshold. + * + * @param ptr SPI base address. + * @param threshold The FIFO threshold value, the value should not greater than FIFO size. + */ +static inline void spi_set_rx_fifo_threshold(SPI_Type *ptr, uint32_t threshold) +{ + ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_RXTHRES_MASK) | SPI_CTRL_RXTHRES_SET(threshold); +} + +/** + * @brief Enables the SPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the SPI. The parameters are base and a DMA mask. + * + * @param ptr SPI base address. + * @param mask The dma enable mask; Use the spi_dma_enable_t. + */ +static inline void spi_enable_dma(SPI_Type *ptr, uint32_t mask) +{ + ptr->CTRL |= mask; +} + +/*! + * @brief Disables the SPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the SPI. The parameters are base and a DMA mask. + * + * @param ptr SPI base address. + * @param mask The dma enable mask; Use the spi_dma_enable_t. + */ +static inline void spi_disable_dma(SPI_Type *ptr, uint32_t mask) +{ + ptr->CTRL &= ~mask; +} + +/** + * @brief Get the SPI interrupt status. + * + * This function gets interrupt status of the SPI. + * + * @param ptr SPI base address. + * @retval SPI interrupt status register value + */ +static inline uint32_t spi_get_interrupt_status(SPI_Type *ptr) +{ + return ptr->INTRST; +} + +/** + * @brief Clear the SPI interrupt status. + * + * This function clears interrupt status of the SPI. + * + * @param ptr SPI base address. + * @param mask The interrupt mask; Use the spi_interrupt_t. + * + */ +static inline void spi_clear_interrupt_status(SPI_Type *ptr, uint32_t mask) +{ + /* write 1 to clear */ + ptr->INTRST = mask; +} + +/** + * @brief Enables the SPI interrupt. + * + * This function configures interrupt of the SPI. The parameters are base and a interrupt mask. + * + * @param ptr SPI base address. + * @param mask The interrupt mask; Use the spi_interrupt_t. + */ +static inline void spi_enable_interrupt(SPI_Type *ptr, uint32_t mask) +{ + ptr->INTREN |= mask; +} + +/*! + * @brief Disables the SPI interrupt. + * + * This function configures interrupt of the SPI. The parameters are base and a interrupt mask. + * + * @param ptr SPI base address. + * @param mask The interrupt mask; Use the spi_interrupt_t. + */ +static inline void spi_disable_interrupt(SPI_Type *ptr, uint32_t mask) +{ + ptr->INTREN &= ~mask; +} + +/** + * @brief spi write and read data + * + * @note Call this function after SPI CONTROL is configured by spi_control_init. + * The order of reading and writing is controlled by spi_control_init. + * + * @param [in] ptr SPI base address + * @param [in] data_len_in_bytes data length in bytes + * @param [in] wbuff spi sent data buff address + * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @param [out] rbuff spi receive data buff address + * @param [in] rcount spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount); + +/** + * @brief spi read data + * + * @note Call this function after SPI CONTROL is configured by spi_control_init. + * + * @param [in] ptr SPI base address + * @param [in] data_len_in_bytes data length in bytes + * @param [out] buff spi receive data buff address + * @param [in] count spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count); + +/** + * @brief spi write data + * + * @note Call this function after SPI CONTROL is configured by spi_control_init. + * + * @param [in] ptr SPI base address + * @param [in] data_len_in_bytes data length in bytes + * @param [in] buff spi sent data buff address + * @param [in] count spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count); + +/** + * @brief spi write command + * + * Writing operations on this register will trigger SPI transfers, call this function on master mode. + * + * @param [in] ptr SPI base address + * @param [in] mode spi mode, use the spi_mode_selection_t + * @param [in] config point to spi_control_config_t + * @param [in] cmd command data address + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd); + +/** + * @brief spi read command + * + * On slave mode, the command field of the last received SPI transaction is stored in this SPI Command Register + * + * @param [in] ptr SPI base address + * @param [in] mode spi mode, use the spi_mode_selection_t + * @param [in] config point to spi_control_config_t + * @param [out] cmd command data address + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd); + +/** + * @brief spi write address + * + * @note Call this function on master mode. + * + * @param [in] ptr SPI base address + * @param [in] mode spi mode, use the spi_mode_selection_t + * @param [in] config point to spi_control_config_t + * @param [in] addr point to address + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr); + +/** + * @brief spi control initialization + * + * @param [in] ptr SPI base address + * @param [in] config point to spi_control_config_t + * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @param [in] rcount spi receive count, not greater than SPI_SOC_TRANSFER_COUNT_MAX + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_t wcount, uint32_t rcount); + +/** + * @brief Get the SPI data length in bits. + * + * @param ptr SPI base address. + * @retval SPI data length in bits + */ +static inline uint8_t spi_get_data_length_in_bits(SPI_Type *ptr) +{ + return ((ptr->TRANSFMT & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) + 1; +} + +/** + * @brief Get the SPI data length in bytes. + * + * @param ptr SPI base address. + * @retval SPI data length in bytes + */ +static inline uint8_t spi_get_data_length_in_bytes(SPI_Type *ptr) +{ + return ((spi_get_data_length_in_bits(ptr) + 7U) / 8U); +} + +/** + * @brief SPI get active status. + * + * @param ptr SPI base address. + * @retval bool true for active, false for inactive + */ +static inline bool spi_is_active(SPI_Type *ptr) +{ + return ((ptr->STATUS & SPI_STATUS_SPIACTIVE_MASK) == SPI_STATUS_SPIACTIVE_MASK) ? true : false; +} + +/** + * @brief SPI enable tx dma + * + * @param ptr SPI base address + */ +static inline void spi_enable_tx_dma(SPI_Type *ptr) +{ + ptr->CTRL |= SPI_CTRL_TXDMAEN_MASK; +} + +/** + * @brief SPI disable tx dma + * + * @param ptr SPI base address + */ +static inline void spi_disable_tx_dma(SPI_Type *ptr) +{ + ptr->CTRL &= ~SPI_CTRL_TXDMAEN_MASK; +} + +/** + * @brief SPI enable rx dma + * + * @param ptr SPI base address + */ +static inline void spi_enable_rx_dma(SPI_Type *ptr) +{ + ptr->CTRL |= SPI_CTRL_RXDMAEN_MASK; +} + +/** + * @brief SPI disable rx dma + * + * @param ptr SPI base address + */ +static inline void spi_disable_rx_dma(SPI_Type *ptr) +{ + ptr->CTRL &= ~SPI_CTRL_RXDMAEN_MASK; +} + +/** + * @brief SPI slave get sent data count + * + * @param ptr SPI base address + * @retval uint32_t data count + */ +static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr) +{ + return SPI_SLVDATACNT_WCNT_GET(ptr->SLVDATACNT); +} + +/** + * @brief SPI slave get received data count + * + * @param ptr SPI base address + * @retval uint32_t data count + */ +static inline uint32_t spi_slave_get_received_data_count(SPI_Type *ptr) +{ + return SPI_SLVDATACNT_RCNT_GET(ptr->SLVDATACNT); +} + +/** + * @brief set spi clock phase + * + * @param [in] ptr SPI base address + * @param [in] clock_phase clock phase enum + */ +static inline void spi_set_clock_phase(SPI_Type *ptr, spi_sclk_sampling_clk_edges_t clock_phase) +{ + ptr->TRANSCTRL |= SPI_TRANSFMT_CPHA_SET(clock_phase); +} + +/** + * @brief get spi clock phase + * + * @param [in] ptr SPI base address + * @retval spi_sclk_sampling_clk_edges_t spi_sclk_sampling_odd_clk_edges if CPHA is 0 + */ +static inline spi_sclk_sampling_clk_edges_t spi_get_clock_phase(SPI_Type *ptr) +{ + return SPI_TRANSFMT_CPHA_GET(ptr->TRANSCTRL); +} + +/** + * @brief set spi clock polarity + * + * @param [in] ptr SPI base address + * @param [in] clock_polarity clock polarity enum + */ +static inline void spi_set_clock_polarity(SPI_Type *ptr, spi_sclk_idle_state_t clock_polarity) +{ + ptr->TRANSCTRL |= SPI_TRANSFMT_CPOL_SET(clock_polarity); +} + +/** + * @brief get spi clock phase + * + * @param [in] ptr SPI base address + * @retval spi_sclk_idle_state_t spi_sclk_low_idle if CPOL is 0 + */ +static inline spi_sclk_idle_state_t spi_get_clock_polarity(SPI_Type *ptr) +{ + return SPI_TRANSFMT_CPOL_GET(ptr->TRANSCTRL); +} + +/** + * @brief set spi the length of each data unit in bits + * + * @param [in] nbit the actual bits number of a data + * @retval hpm_stat_t status_success if spi transfer without any error + */ +static inline hpm_stat_t spi_set_data_bits(SPI_Type *ptr, uint8_t nbits) +{ + if (nbits > 32) { + return status_invalid_argument; + } else { + ptr->TRANSFMT |= SPI_TRANSFMT_DATALEN_SET(nbits - 1); + return status_success; + } +} + +/** + * @brief SPI transmit fifo reset + * + * @param ptr SPI base address + */ +static inline void spi_transmit_fifo_reset(SPI_Type *ptr) +{ + ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK; +} + +/** + * @brief SPI receive fifo reset + * + * @param ptr SPI base address + */ +static inline void spi_receive_fifo_reset(SPI_Type *ptr) +{ + ptr->CTRL |= SPI_CTRL_RXFIFORST_MASK; +} + +/** + * @brief SPI reset + * + * @param ptr SPI base address + */ +static inline void spi_reset(SPI_Type *ptr) +{ + ptr->CTRL |= SPI_CTRL_SPIRST_MASK; +} /** * @} */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h index cba7cb967f..f8ef750689 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h index a42ee6f8f5..fd4392e240 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,7 +9,7 @@ #define HPM_TRGM_DRV_H #include "hpm_common.h" -#include "hpm_trgm_drv.h" +#include "hpm_trgm_regs.h" #include "hpm_trgmmux_src.h" /** @@ -185,8 +185,9 @@ static inline void trgm_output_update_source(TRGM_Type *ptr, uint8_t output, uin static inline void trgm_output_config(TRGM_Type *ptr, uint8_t output, trgm_output_t *config) { ptr->TRGOCFG[output] = TRGM_TRGOCFG_TRIGOSEL_SET(config->input) - | TRGM_TRGOCFG_FEDG2PEN_SET(config->type) - | TRGM_TRGOCFG_REDG2PEN_SET(config->type); + | (config->type & TRGM_TRGOCFG_FEDG2PEN_MASK) + | (config->type & TRGM_TRGOCFG_REDG2PEN_MASK) + | TRGM_TRGOCFG_OUTINV_SET(config->invert); } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h index ff58d6ce91..fc88c6a538 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h index a1f465afa1..63367abfb4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #define HPM_UART_DRV_H #include "hpm_common.h" #include "hpm_uart_regs.h" +#include "hpm_soc_feature.h" /** * @@ -62,6 +63,28 @@ typedef enum uart_fifo_trg_lvl { uart_tx_fifo_trg_lt_one_quarter = 3, } uart_fifo_trg_lvl_t; +#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +/* @brief UART new fifo trigger levels */ +typedef enum uart_new_fifo_trg_lvl { + uart_fifo_1_byte = 0, + uart_fifo_2_bytes = 1, + uart_fifo_3_bytes = 2, + uart_fifo_4_bytes = 3, + uart_fifo_5_bytes = 4, + uart_fifo_6_bytes = 5, + uart_fifo_7_bytes = 6, + uart_fifo_8_bytes = 7, + uart_fifo_9_bytes = 8, + uart_fifo_10_bytes = 9, + uart_fifo_11_bytes = 10, + uart_fifo_12_bytes = 11, + uart_fifo_13_bytes = 12, + uart_fifo_14_bytes = 13, + uart_fifo_15_bytes = 14, + uart_fifo_16_bytes = 15, +} uart_new_fifo_trg_lvl_t; +#endif + /* @brief UART signals */ typedef enum uart_signal { uart_signal_rts = UART_MCR_RTS_MASK, @@ -85,6 +108,9 @@ typedef enum uart_intr_enable { uart_intr_tx_slot_avail = UART_IER_ETHEI_MASK, uart_intr_rx_line_stat = UART_IER_ELSI_MASK, uart_intr_modem_stat = UART_IER_EMSI_MASK, +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + uart_intr_rx_line_idle = UART_IER_ERXIDLE_MASK, +#endif } uart_intr_enable_t; /* @brief UART interrupt IDs */ @@ -98,7 +124,7 @@ typedef enum uart_intr_id { /* @brief UART status */ typedef enum uart_stat { - uart_stat_data_ready = UART_LSR_DR_MASK, + uart_stat_data_ready = UART_LSR_DR_MASK, /* rx data ready in fifo */ uart_stat_overrun_error = UART_LSR_OE_MASK, uart_stat_parity_error = UART_LSR_PE_MASK, uart_stat_framing_error = UART_LSR_FE_MASK, @@ -117,23 +143,67 @@ typedef struct uart_modem_config { bool set_rts_high; /**< Set signal RTS level high flag */ } uart_modem_config_t; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +/** + * @brief UART RX Line Idle detection conditions + */ +typedef enum hpm_uart_rxline_idle_cond { + uart_rxline_idle_cond_rxline_logic_one = 0, /**< Treat as idle if the RX Line high duration exceeds threshold */ + uart_rxline_idle_cond_state_machine_idle = 1 /**< Treat as idle if the RX state machine idle state duration exceeds threshold */ +} uart_rxline_idle_cond_t; + +typedef struct hpm_uart_rxline_idle_detect_config { + bool detect_enable; /**< RX Line Idle detection flag */ + bool detect_irq_enable; /**< Enable RX Line Idle detection interrupt */ + uart_rxline_idle_cond_t idle_cond; /**< RX Line Idle detection condition */ + uint8_t threshold; /**< UART RX Line Idle detection threshold, in terms of bits */ +} uart_rxline_idle_config_t; +#endif + /** * @brief UART config */ typedef struct hpm_uart_config { - - uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ - uint32_t baudrate; /**< Baudrate */ - uint8_t num_of_stop_bits; /**< Number of stop bits */ - uint8_t word_length; /**< Word length */ - uint8_t parity; /**< Parity */ - uint8_t tx_fifo_level; /**< TX Fifo level */ - uint8_t rx_fifo_level; /**< RX Fifo level */ - bool dma_enable; /**< DMA Enable flag */ - bool fifo_enable; /**< Fifo Enable flag */ - uart_modem_config_t modem_config; /**< Modem config */ + uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ + uint32_t baudrate; /**< Baudrate */ + uint8_t num_of_stop_bits; /**< Number of stop bits */ + uint8_t word_length; /**< Word length */ + uint8_t parity; /**< Parity */ + uint8_t tx_fifo_level; /**< TX Fifo level */ + uint8_t rx_fifo_level; /**< RX Fifo level */ +#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) + bool using_new_fifo_thr; +#endif + bool dma_enable; /**< DMA Enable flag */ + bool fifo_enable; /**< Fifo Enable flag */ + uart_modem_config_t modem_config; /**< Modem config */ +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + uart_rxline_idle_config_t rxidle_config; /**< RX Idle configuration */ +#endif +#if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) + bool rx_enable; /**< RX Enable configuration */ +#endif } uart_config_t; +#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +typedef struct { + uint16_t stop_bit_len; + bool en_stop_bit_insert; + bool hardware_trig; + bool trig_mode; + bool trig_clr_rxfifo; +} uart_trig_config_t; +#endif + +typedef struct { + uint8_t tx_fifo_level; /**< TX Fifo level */ + uint8_t rx_fifo_level; /**< RX Fifo level */ + bool reset_tx_fifo; /**< reset tx Fifo */ + bool reset_rx_fifo; /**< reset rx Fifo */ + bool dma_enable; /**< DMA Enable flag */ + bool fifo_enable; /**< Fifo Enable flag */ +} uart_fifo_ctrl_t; + #ifdef __cplusplus extern "C" { #endif @@ -141,7 +211,7 @@ extern "C" { /** * @brief Get fifo size * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval size of Fifo */ static inline uint8_t uart_get_fifo_size(UART_Type *ptr) @@ -149,46 +219,71 @@ static inline uint8_t uart_get_fifo_size(UART_Type *ptr) return 16 << ((ptr->CFG & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT); } +/** + * @brief uart config fifo control + * + * @note fifo control register is WO access, prepare all bitfiled value to write + * + * @param [in] ptr UART base address + * @param [in] ctrl uart_fifo_ctrl_t + */ +void uart_config_fifo_ctrl(UART_Type *ptr, uart_fifo_ctrl_t *ctrl); + +/** + * @brief uart clear rx fifo by reading data + * + * @note read out all data in rx fifo, the uart_intr_rx_data_avail_or_timeout is cleared + * when RBR register is read + * + * @param [in] ptr UART base address + */ +static inline void uart_clear_rx_fifo(UART_Type *ptr) +{ + while (ptr->LSR & UART_LSR_DR_MASK) { + ptr->RBR; + } +} + /** * @brief Reset TX Fifo * - * @param ptr UART base address + * @note this API may modify other bit fields in FIFO control register + * + * @param [in] ptr UART base address */ static inline void uart_reset_tx_fifo(UART_Type *ptr) { - if (ptr->FCR & UART_FCR_FIFOE_MASK) { - ptr->FCR |= UART_FCR_TFIFORST_MASK; - } + ptr->FCR = UART_FCR_TFIFORST_MASK; } /** * @brief Reset RX Fifo * - * @param ptr UART base address + * @note this API may modify other bit fields in FIFO control register + * + * @param [in] ptr UART base address */ static inline void uart_reset_rx_fifo(UART_Type *ptr) { - if (ptr->FCR & UART_FCR_FIFOE_MASK) { - ptr->FCR |= UART_FCR_RFIFORST_MASK; - } + ptr->FCR = UART_FCR_RFIFORST_MASK; } /** - * @brief Reset both TX and RX Fifo + * @brief [in] Reset both TX and RX Fifo * - * @param ptr UART base address + * @note this API may modify other bit fields in FIFO control register + * + * @param [in] ptr UART base address */ static inline void uart_reset_all_fifo(UART_Type *ptr) { - if (ptr->FCR & UART_FCR_FIFOE_MASK) { - ptr->FCR |= UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK; - } + ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK; } /** * @brief Enable modem loopback * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_enable_loopback(UART_Type *ptr) { @@ -198,7 +293,7 @@ static inline void uart_modem_enable_loopback(UART_Type *ptr) /** * @brief Disable modem loopback * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_disable_loopback(UART_Type *ptr) { @@ -208,7 +303,7 @@ static inline void uart_modem_disable_loopback(UART_Type *ptr) /** * @brief Disable modem auto flow control * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_disable_auto_flow_control(UART_Type *ptr) @@ -219,7 +314,7 @@ static inline void uart_modem_disable_auto_flow_control(UART_Type *ptr) /** * @brief Enable modem auto flow control * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_enable_auto_flow_control(UART_Type *ptr) { @@ -229,7 +324,7 @@ static inline void uart_modem_enable_auto_flow_control(UART_Type *ptr) /** * @brief Configure modem * - * @param ptr UART base address + * @param [in] ptr UART base address * @param config Pointer to modem config struct */ static inline void uart_modem_config(UART_Type *ptr, uart_modem_config_t *config) @@ -242,7 +337,7 @@ static inline void uart_modem_config(UART_Type *ptr, uart_modem_config_t *config /** * @brief Get modem status * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval Current modem status */ static inline uint8_t uart_get_modem_status(UART_Type *ptr) @@ -250,24 +345,46 @@ static inline uint8_t uart_get_modem_status(UART_Type *ptr) return ptr->MSR; } +/** + * @brief Write byte to TX + * + * @param ptr UART base address + * @param c data to be sent + */ +static inline void uart_write_byte(UART_Type *ptr, uint8_t c) +{ + ptr->THR = UART_THR_THR_SET(c); +} + + +/** + * @brief Read byte from RX + * + * @param ptr UART base address + * @retval RX byte + */ +static inline uint8_t uart_read_byte(UART_Type *ptr) +{ + return (ptr->RBR & UART_RBR_RBR_MASK); +} /** * @brief Check modem status with given mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param mask Status mask value to be checked against * @retval true if any bit in given mask is set * @retval false if none of any bit in given mask is set */ static inline bool uart_check_modem_status(UART_Type *ptr, uart_modem_stat_t mask) { - return (ptr->MSR & mask); + return ((ptr->MSR & mask) != 0U) ? true : false; } /** * @brief Disable IRQ with mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param irq_mask IRQ mask value to be disabled */ static inline void uart_disable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) @@ -278,7 +395,7 @@ static inline void uart_disable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) /** * @brief Enable IRQ with mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param irq_mask IRQ mask value to be enabled */ static inline void uart_enable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) @@ -289,7 +406,7 @@ static inline void uart_enable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) /** * @brief Get Enabled IRQ * - * @param ptr UART base address + * @param [in] ptr UART base address * @return enabled irq */ static inline uint32_t uart_get_enabled_irq(UART_Type *ptr) @@ -300,7 +417,7 @@ static inline uint32_t uart_get_enabled_irq(UART_Type *ptr) /** * @brief Get interrupt identification * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval interrupt id */ static inline uint8_t uart_get_irq_id(UART_Type *ptr) @@ -308,10 +425,58 @@ static inline uint8_t uart_get_irq_id(UART_Type *ptr) return (ptr->IIR & UART_IIR_INTRID_MASK); } +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +/** + * @brief Determine whether UART RX Line is idle + * @param [in] ptr UART base address + */ +static inline bool uart_is_rxline_idle(UART_Type *ptr) +{ + return ((ptr->IIR & UART_IIR_RXIDLE_FLAG_MASK) != 0U) ? true : false; +} + +/** + * @brief Clear UART RX Line Idle Flag + * @param [in] ptr UART base address + */ +static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) +{ + ptr->IIR = UART_IIR_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ +} + +/** + * @brief Enable UART RX Idle Line detection logic + * @param [in] ptr UART base address + */ +static inline void uart_enable_rxline_idle_detection(UART_Type *ptr) +{ + ptr->IDLE_CFG |= UART_IDLE_CFG_RX_IDLE_EN_MASK; +} + +/** + * @brief Disable UART RX Idle Line detection logic + * + * @param [in] ptr UART base address + */ +static inline void uart_disable_rxline_idle_detection(UART_Type *ptr) +{ + ptr->IDLE_CFG &= ~UART_IDLE_CFG_RX_IDLE_EN_MASK; +} + +/** + * @brief Configure UART RX Line detection + * @param [in] ptr UART base address + * @param [in] rxidle_config RXLine IDLE detection configuration + * @retval status_success if no error occurs + */ +hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config); + +#endif + /** * @brief Get status * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval current status */ static inline uint8_t uart_get_status(UART_Type *ptr) @@ -322,20 +487,20 @@ static inline uint8_t uart_get_status(UART_Type *ptr) /** * @brief Check uart status according to the given status mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param mask Status mask value to be checked against * @retval true if any bit in given mask is set * @retval false if none of any bit in given mask is set */ static inline bool uart_check_status(UART_Type *ptr, uart_stat_t mask) { - return (ptr->LSR & mask); + return ((ptr->LSR & mask) != 0U) ? true : false; } /** * @brief Get default config * - * @param ptr UART base address + * @param [in] ptr UART base address * @param config Pointer to the buffer to save default values */ void uart_default_config(UART_Type *ptr, uart_config_t *config); @@ -343,25 +508,25 @@ void uart_default_config(UART_Type *ptr, uart_config_t *config); /** * @brief Initialization * - * @param ptr UART base address + * @param [in] ptr UART base address * @param config Pointer to config struct * @retval status_success only if it succeeds */ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config); /** - * @brief Send one byte + * @brief Send one byte after checking thresh hold status * - * @param ptr UART base address + * @param [in] ptr UART base address * @param c Byte to be sent * @retval status_success only if it succeeds */ hpm_stat_t uart_send_byte(UART_Type *ptr, uint8_t c); /** - * @brief Receive one byte + * @brief Receive one byte after checking data ready status * - * @param ptr UART base address + * @param [in] ptr UART base address * @param c Pointer to buffer to save the byte received on UART * @retval status_success only if it succeeds */ @@ -370,7 +535,7 @@ hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *c); /** * @brief Set uart signal output level * - * @param ptr UART base address + * @param [in] ptr UART base address * @param signal Target signal * @param level Target signal level */ @@ -381,7 +546,7 @@ void uart_set_signal_level(UART_Type *ptr, /** * @brief Flush sending buffer/fifo * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval status_success only if it succeeds */ hpm_stat_t uart_flush(UART_Type *ptr); @@ -389,7 +554,7 @@ hpm_stat_t uart_flush(UART_Type *ptr); /** * @brief Receive bytes blocking * - * @param ptr UART base address + * @param [in] ptr UART base address * @param buf Pointer to the buffer to save received data * @param size_in_byte Size in byte to be sent * @retval status_success only if it succeeds @@ -399,14 +564,13 @@ hpm_stat_t uart_receive_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte /** * @brief Send bytes blocking * - * @param ptr UART base address + * @param [in] ptr UART base address * @param buf Pointer to the buffer to be sent * @param size_in_byte Size in byte to be sent * @retval status_success only if it succeeds */ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); - /** * @brief Sets UART baudrate. * @@ -421,6 +585,50 @@ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); */ hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz); + +#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +/** + * @brief Config uart trigger mode for communication + * + * This function is used to tomagawa communication, uart sent out data in fifo then generate interrupt after + * received specify count of data into fifo. + * + * @param ptr UART base address + * @param uart_trig_config_t config + */ +void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config); + +/** + * @brief uart trigger communication + * + * This function triggers uart communication, the communication configed by uart_config_trig_mode() + * + * @param ptr UART base address + */ +static inline void uart_trigger_communication(UART_Type *ptr) +{ + ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; + ptr->MOTO_CFG |= UART_MOTO_CFG_SWTRG_MASK; +} + +/** + * @brief uart enable hardware trigger mode + * + * This function configures uart start communication by hardware trigger from motor periphrals + * + * @param ptr UART base address + * @param bool enable + */ +static inline void uart_enable_hardware_trigger_mode(UART_Type *ptr, bool enable) +{ + if (enable) { + ptr->MOTO_CFG |= UART_MOTO_CFG_HWTRG_EN_MASK; + } else { + ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; + } +} +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h index b0d7bda720..7cf3ec4143 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,9 +7,10 @@ #ifndef HPM_USB_DRV_H #define HPM_USB_DRV_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_common.h" #include "hpm_usb_regs.h" #include "hpm_soc_feature.h" @@ -21,15 +22,17 @@ * @{ */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macro Constant Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #define USB_PHY_INIT_DELAY_COUNT (16U) /**< a delay count for USB phy initialization */ #define USB_HOST_FRAMELIST_SIZE (8U) /**< a frame list size in USB host mode */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macro Enum Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /** * @brief USB transfer direction types */ @@ -74,13 +77,14 @@ typedef enum { usb_tran_parallel = 0, usb_tran_serial = 1 } usb_transceiver_t; -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Structure Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /** * @brief Control request structure */ -typedef struct __attribute__ ((packed)){ +typedef struct __attribute__ ((packed)) { union { struct __attribute__ ((packed)) { uint8_t recipient : 5; @@ -110,9 +114,10 @@ typedef struct { extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Common API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /** * @brief Get the mask of all enabled interrupts @@ -158,7 +163,7 @@ static inline uint32_t usb_get_status_flags(USB_Type *ptr) static inline void usb_clear_status_flags(USB_Type *ptr, uint32_t mask) { - ptr->USBSTS |= mask; + ptr->USBSTS = mask; } /** @@ -205,9 +210,17 @@ static inline uint8_t usb_get_port_speed(USB_Type *ptr) return USB_PORTSC1_PSPD_GET(ptr->PORTSC1); } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Device API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ + +/** + * @brief Initialize USB phy + * + * @param[in] ptr A USB peripheral base address + */ +void usb_phy_init(USB_Type *ptr); /** * @brief USB device bus reset @@ -245,6 +258,15 @@ void usb_dcd_remote_wakeup(USB_Type *ptr); * @param[in] config A pointer to the specified endpoint config struct */ void usb_dcd_edpt_open(USB_Type *ptr, usb_endpoint_config_t *config); + +/** + * @brief get a specified endpoint type + * + * @param[in] ptr A USB peripheral base address + * @param[in] ep_addr Endpoint address + */ +uint8_t usb_dcd_edpt_get_type(USB_Type *ptr, uint8_t ep_addr); + /** * @brief Submit a transfer * @@ -310,7 +332,7 @@ static inline uint32_t usb_dcd_get_edpt_setup_status(USB_Type *ptr) */ static inline void usb_dcd_clear_edpt_setup_status(USB_Type *ptr, uint32_t mask) { - ptr->ENDPTSETUPSTAT |= mask; + ptr->ENDPTSETUPSTAT = mask; } /** @@ -365,12 +387,13 @@ static inline uint32_t usb_dcd_get_edpt_complete_status(USB_Type *ptr) */ static inline void usb_dcd_clear_edpt_complete_status(USB_Type *ptr, uint32_t mask) { - ptr->ENDPTCOMPLETE |= mask; + ptr->ENDPTCOMPLETE = mask; } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Host API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /** * @brief Initialize controller to host mode * @@ -393,7 +416,7 @@ void usb_hcd_port_reset(USB_Type *ptr); * @param[in] ptr A USB peripheral base address * @param[in] mask A mask of all required commands */ -static inline void usb_hcd_set_command(USB_Type *ptr ,uint32_t mask) +static inline void usb_hcd_set_command(USB_Type *ptr, uint32_t mask) { ptr->USBCMD |= mask; } @@ -420,6 +443,16 @@ static inline bool usb_hcd_get_port_csc(USB_Type *ptr) return USB_PORTSC1_CSC_GET(ptr->PORTSC1); } +/** + * @brief Enable port power + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_hcd_enable_port_power(USB_Type *ptr) +{ + ptr->PORTSC1 |= USB_PORTSC1_PP_MASK; +} + /** * @brief Get port connect status changeSet async list address * @@ -442,6 +475,26 @@ static inline void usb_hcd_set_periodic_list_addr(USB_Type *ptr, uint32_t addr) ptr->PERIODICLISTBASE = addr & USB_PERIODICLISTBASE_BASEADR_MASK; } +/** + * @brief Start hcd controller + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_hcd_run(USB_Type *ptr) +{ + ptr->USBCMD |= USB_USBCMD_RS_MASK; +} + +/** + * @brief Stop hcd controller + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_hcd_stop(USB_Type *ptr) +{ + ptr->USBCMD &= ~USB_USBCMD_RS_MASK; +} + #if defined __cplusplus } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h index b0661bde27..3c4dffb0d4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h index 21b9782ed3..51e81cb30f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -23,14 +23,14 @@ * @brief WDG Reset Interval definitions */ typedef enum reset_interval_enum { - reset_interval_clock_period_mult_128 = 0, - reset_interval_clock_period_mult_256, - reset_interval_clock_period_mult_512, - reset_interval_clock_period_mult_1k, - reset_interval_clock_period_mult_2k, - reset_interval_clock_period_mult_4k, - reset_interval_clock_period_mult_8k, - reset_interval_clock_period_mult_16k, + reset_interval_clock_period_mult_128 = 0, + reset_interval_clock_period_mult_256 = 1, + reset_interval_clock_period_mult_512 = 2, + reset_interval_clock_period_mult_1k = 3, + reset_interval_clock_period_mult_2k = 4, + reset_interval_clock_period_mult_4k = 5, + reset_interval_clock_period_mult_8k = 6, + reset_interval_clock_period_mult_16k = 7, reset_interval_max = reset_interval_clock_period_mult_16k, reset_interval_out_of_range, } reset_interval_t; @@ -39,23 +39,22 @@ typedef enum reset_interval_enum { * @brief WDG Interrupt interval definitions */ typedef enum interrupt_interval_enum { - interrupt_interval_clock_period_multi_64, - interrupt_interval_clock_period_multi_256, - interrupt_interval_clock_period_multi_1k, - interrupt_interval_clock_period_multi_2k, - interrupt_interval_clock_period_multi_4k, - interrupt_interval_clock_period_multi_8k, - interrupt_interval_clock_period_multi_16k, - interrupt_interval_clock_period_multi_32k, - interrupt_interval_clock_period_multi_128k, - interrupt_interval_clock_period_multi_512k, - interrupt_interval_clock_period_multi_2m, - interrupt_interval_clock_period_multi_4m, - interrupt_interval_clock_period_multi_8m, - interrupt_interval_clock_period_multi_32m, - interrupt_interval_clock_period_multi_128m, - interrupt_interval_clock_period_multi_512m, - interrupt_interval_clock_period_multi_2g, + interrupt_interval_clock_period_multi_64 = 0, + interrupt_interval_clock_period_multi_256 = 1, + interrupt_interval_clock_period_multi_1k = 2, + interrupt_interval_clock_period_multi_2k = 3, + interrupt_interval_clock_period_multi_4k = 4, + interrupt_interval_clock_period_multi_8k = 5, + interrupt_interval_clock_period_multi_16k = 6, + interrupt_interval_clock_period_multi_32k = 7, + interrupt_interval_clock_period_multi_128k = 8, + interrupt_interval_clock_period_multi_512k = 9, + interrupt_interval_clock_period_multi_2m = 10, + interrupt_interval_clock_period_multi_8m = 11, + interrupt_interval_clock_period_multi_32m = 12, + interrupt_interval_clock_period_multi_128m = 13, + interrupt_interval_clock_period_multi_512m = 14, + interrupt_interval_clock_period_multi_2g = 15, interrupt_interval_max = interrupt_interval_clock_period_multi_2g, interrupt_interval_out_of_range, } interrupt_interval_t; @@ -180,8 +179,7 @@ static inline void wdg_clksrc_select(WDG_Type *base, wdg_clksrc_t clksrc) { if (clksrc == wdg_clksrc_extclk) { base->CTRL &= ~WDG_CTRL_CLKSEL_MASK; - } - else { + } else { base->CTRL |= WDG_CTRL_CLKSEL_MASK; } } @@ -238,6 +236,26 @@ hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl); */ reset_interval_t wdg_convert_reset_interval_from_us(const uint32_t src_freq, const uint32_t reset_us); +/** + * @brief Convert the interrupt interval value based on the WDG source clock frequency and the expected interrupt interval + * in terms of microseconds + * + * @param [in] src_freq WDG source clock frequency + * @param [in] interval Expected Interrupt interval + * @retval Converted WDG interrupt interval in us + */ + uint64_t wdg_convert_interrupt_interval_to_us(const uint32_t src_freq, interrupt_interval_t interval); + +/** + * @brief Convert the Reset interval value based on the WDG source clock frequency and the expected reset interval + * in terms of microseconds + * + * @param [in] src_freq WDG source clock frequency + * @param [in] interval Expected Reset interval + * @retval Converted WDG reset interval in us + */ +uint32_t wdg_convert_reset_interval_to_us(const uint32_t src_freq, reset_interval_t interval); + /** * @brief Convert the interrupt interval value based on the WDG source clock frequency and the expected interrupt interval * in terms of microseconds @@ -255,7 +273,7 @@ interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_f * @param [in] src_freq WDG source clock frequency * @return Converted WDG interrupt interval in terms of microseconds */ -uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq); +uint64_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq); /** * @brief Get Actual WDG Reset Interval in terms of microseconds @@ -264,7 +282,7 @@ uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_fre * @param [in] src_freq WDG source clock frequency * @return Converted WDG total reset interval in terms of microseconds */ -uint32_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq); +uint64_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq); #ifdef __cplusplus } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c index 3b2ed8cf80..10f57d1f54 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c index a8b0c2cd52..844b559a8d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,8 +12,8 @@ void adc12_get_default_config(adc12_config_t *config) { config->res = adc12_res_12_bits; config->conv_mode = adc12_conv_mode_oneshot; - config->adc_clk_div = 1; - config->wait_dis = 0; + config->adc_clk_div = adc12_clock_divider_1; + config->wait_dis = true; config->sel_sync_ahb = true; config->adc_ahb_en = false; } @@ -102,13 +102,13 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) | ADC12_ANA_CTRL1_SELRES_SET(config->res); /* Set convert clock number and clock period */ - if (config->adc_clk_div > ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) { + if ((config->adc_clk_div - 1) > ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) { return status_invalid_argument; } /* Set ADC minimum conversion cycle and ADC clock divider */ ptr->CONV_CFG1 = ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(2 * config->res + 7) - | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div); + | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div - 1); /* Set ADC Config0 */ ptr->ADC_CFG0 = ADC12_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb) @@ -153,7 +153,8 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) /*------------------------------------------------------------------------------- * End of calibration - *------------------------------------------------------------------------------*/ + *------------------------------------------------------------------------------ + */ return status_success; } @@ -161,7 +162,7 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->ch)) { return status_invalid_argument; } @@ -215,7 +216,7 @@ hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *dma_config) hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->ch)) { return status_invalid_argument; } @@ -236,9 +237,14 @@ hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config) return status_success; } -void adc12_trigger_seq_by_sw(ADC12_Type *ptr) +hpm_stat_t adc12_trigger_seq_by_sw(ADC12_Type *ptr) { + if (ADC12_INT_STS_SEQ_SW_CFLCT_GET(ptr->INT_STS)) { + return status_fail; + } ptr->SEQ_CFG0 |= ADC12_SEQ_CFG0_SW_TRIG_MASK; + + return status_success; } /* Note: the sequence length can not be larger or equal than 2 in HPM6750EVK Revision A0 */ @@ -258,7 +264,7 @@ hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config) /* Set sequence queue */ for (int i = 0; i < config->seq_len; i++) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, config->queue[i].ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->queue[i].ch)) { return status_invalid_argument; } @@ -269,6 +275,13 @@ hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config) return status_success; } +hpm_stat_t adc12_trigger_pmt_by_sw(ADC12_Type *ptr, uint8_t trig_ch) +{ + ptr->TRG_SW_STA = ADC12_TRG_SW_STA_TRG_SW_STA_MASK | ADC12_TRG_SW_STA_TRIG_SW_INDEX_SET(trig_ch); + + return status_success; +} + hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config) { uint32_t temp = 0; @@ -278,10 +291,15 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config) return status_invalid_argument; } + /* Check the triggier channel */ + if (ADC12_IS_TRIG_CH_INVLAID(config->trig_ch)) { + return status_invalid_argument; + } + temp |= ADC12_CONFIG_TRIG_LEN_SET(config->trig_len - 1); for (int i = 0; i < config->trig_len; i++) { - if (ADC12_IS_CHANNEL_INVALID(ptr, config->trig_ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->adc_ch[i])) { return status_invalid_argument; } @@ -296,12 +314,21 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config) hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) { + uint32_t bus_res; + /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) { + if (ADC12_IS_CHANNEL_INVALID(ch)) { return status_invalid_argument; } - *result = ADC12_BUS_RESULT_CHAN_RESULT_GET(ptr->BUS_RESULT[ch]); + bus_res = ptr->BUS_RESULT[ch]; + *result = ADC12_BUS_RESULT_CHAN_RESULT_GET(bus_res); + + if (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)) { + if (!ADC12_BUS_RESULT_VALID_GET(bus_res)) { + return status_fail; + } + } return status_success; } @@ -309,11 +336,11 @@ hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *resul hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) { + if (ADC12_IS_CHANNEL_INVALID(ch)) { return status_invalid_argument; } - *result = ptr->PRD_CFG[ch].PRD_RESULT; + *result = ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(ptr->PRD_CFG[ch].PRD_RESULT); return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c index ca90cf24d0..19f35d7dc6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,9 +11,9 @@ void adc16_get_default_config(adc16_config_t *config) { config->conv_mode = adc16_conv_mode_oneshot; - config->adc_clk_div = 1; - config->wait_dis = 0; + config->adc_clk_div = adc16_clock_divider_1; config->conv_duration = 0; + config->wait_dis = true; config->sel_sync_ahb = true; config->port3_rela_time = false; config->adc_ahb_en = false; @@ -46,7 +46,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - /* Enable ADC clock */ + /* Enable ADC config clock */ ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { @@ -65,14 +65,14 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) /* Enable ahb_en */ ptr->ADC_CFG0 |= ADC16_ADC_CFG0_ADC_AHB_EN_MASK; - /* Disable ADC clock */ + /* Disable ADC config clock */ ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; /* Recover input clock divider */ ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); - for(j = 0; j < 4; j++) { + for (j = 0; j < 4; j++) { /* Set startcal */ ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_STARTCAL_MASK; @@ -80,7 +80,8 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_STARTCAL_MASK; /* Polling calibration status */ - while (ADC16_ANA_STATUS_CALON_GET(ptr->ANA_STATUS)) {} + while (ADC16_ANA_STATUS_CALON_GET(ptr->ANA_STATUS)) { + } /* Read parameters */ for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { @@ -108,7 +109,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) adc16_params[i] >>= 6; } - /* Enable ADC clock */ + /* Enable ADC config clock */ ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) @@ -135,7 +136,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); - /* Disable ADC clock */ + /* Disable ADC config clock */ ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; return status_success; @@ -143,18 +144,21 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) { + uint32_t clk_div_temp; + /* Set convert clock number and clock period */ - if (config->adc_clk_div > ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) { + if (config->adc_clk_div - 1 > ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) { return status_invalid_argument; } /* Set ADC minimum conversion cycle and ADC clock divider */ - ptr->CONV_CFG1 = ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(21) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div); + ptr->CONV_CFG1 = ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(config->res) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div - 1); /* Set ahb_en */ - /* Set convert duration */ - ptr->ADC_CFG0 = ADC16_ADC_CFG0_ADC_AHB_EN_SET(config->sel_sync_ahb) + /* Set the duration of the conversion */ + ptr->ADC_CFG0 = ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb) + | ADC16_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en) | ADC16_ADC_CFG0_CONVERT_DURATION_SET(config->conv_duration); /* Set wait_dis */ @@ -163,6 +167,27 @@ hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); } + /* Get input clock divider */ + clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); + + /* Set input clock divider temporarily */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Enable ADC config clock */ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Set end count */ + ptr->ADC16_CONFIG1 &= ~ADC16_ADC16_CONFIG1_COV_END_CNT_MASK; + ptr->ADC16_CONFIG1 |= ADC16_ADC16_CONFIG1_COV_END_CNT_SET(ADC16_SOC_MAX_CONV_CLK_NUM - config->res + 1); + + /* Disable ADC config clock */ + ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Recover input clock divider */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); + /* Do a calibration */ adc16_do_calibration(ptr); @@ -188,8 +213,13 @@ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config) return status_success; } -void adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) +hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) { + /* Check the DMA buffer length */ + if (ADC16_IS_SEQ_DMA_BUFF_LEN_INVLAID(dma_config->buff_len_in_4bytes)) { + return status_invalid_argument; + } + /* Reset ADC DMA */ ptr->SEQ_DMA_CFG |= ADC16_SEQ_DMA_CFG_DMA_RST_MASK; @@ -204,7 +234,7 @@ void adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) /* Set ADC DMA memory dword length */ ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) - | ADC16_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes); + | ADC16_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes - 1); /* Set stop_en and stop_pos */ if (dma_config->stop_en) { @@ -212,6 +242,8 @@ void adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) | ADC16_SEQ_DMA_CFG_STOP_EN_MASK | ADC16_SEQ_DMA_CFG_STOP_POS_SET(dma_config->stop_pos); } + + return status_success; } hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config) @@ -221,11 +253,12 @@ hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config) return status_invalid_argument; } + /* Check the prescale */ if (config->prescale > (ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)) { return status_invalid_argument; } - /* periodic prescale */ + /* Set periodic prescale */ ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) | ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(config->prescale); @@ -237,15 +270,21 @@ hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config) return status_success; } -void adc16_trigger_seq_by_sw(ADC16_Type *ptr) +hpm_stat_t adc16_trigger_seq_by_sw(ADC16_Type *ptr) { + if (ADC16_INT_STS_SEQ_SW_CFLCT_GET(ptr->INT_STS)) { + return status_fail; + } ptr->SEQ_CFG0 |= ADC16_SEQ_CFG0_SW_TRIG_MASK; + + return status_success; } /* Note: the sequence length can not be larger or equal than 2 in HPM6750EVK Revision A0 */ hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config) { - if (config->seq_len > ADC_SOC_SEQ_MAX_LEN) { + /* Check sequence length */ + if (ADC16_IS_SEQ_LEN_INVLAID(config->seq_len)) { return status_invalid_argument; } @@ -263,12 +302,19 @@ hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config) } ptr->SEQ_QUE[i] = ADC16_SEQ_QUE_SEQ_INT_EN_SET(config->queue[i].seq_int_en) - | ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(config->queue[i].ch); + | ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(config->queue[i].ch); } return status_success; } +hpm_stat_t adc16_trigger_pmt_by_sw(ADC16_Type *ptr, uint8_t trig_ch) +{ + ptr->TRG_SW_STA = ADC16_TRG_SW_STA_TRG_SW_STA_MASK | ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(trig_ch); + + return status_success; +} + hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config) { uint32_t temp = 0; @@ -278,10 +324,15 @@ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config) return status_invalid_argument; } + /* Check the triggier channel */ + if (ADC16_IS_TRIG_CH_INVLAID(config->trig_ch)) { + return status_invalid_argument; + } + temp |= ADC16_CONFIG_TRIG_LEN_SET(config->trig_len - 1); for (int i = 0; i < config->trig_len; i++) { - if (ADC16_IS_CHANNEL_INVALID(config->trig_ch)) { + if (ADC16_IS_CHANNEL_INVALID(config->adc_ch[i])) { return status_invalid_argument; } @@ -296,12 +347,12 @@ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config) hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool enable) { -#if ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT == 1 /* Check the specified trigger channel */ if (ADC16_IS_TRIG_CH_INVLAID(trig_ch)) { return status_invalid_argument; } +#if ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT == 1 /* Set queue enable control */ ptr->CONFIG[trig_ch] |= ADC16_CONFIG_QUEUE_EN_SET(enable); return status_success; @@ -313,11 +364,21 @@ hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool ena /* one shot mode */ hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result) { + uint32_t bus_res; + + /* Check the specified channel number */ if (ADC16_IS_CHANNEL_INVALID(ch)) { return status_invalid_argument; } - *result = ADC16_BUS_RESULT_CHAN_RESULT_GET(ptr->BUS_RESULT[ch]); + bus_res = ptr->BUS_RESULT[ch]; + *result = ADC16_BUS_RESULT_CHAN_RESULT_GET(bus_res); + + if (ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)) { + if (!ADC16_BUS_RESULT_VALID_GET(bus_res)) { + return status_fail; + } + } return status_success; } @@ -325,11 +386,63 @@ hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *resul /* period mode */ hpm_stat_t adc16_get_prd_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result) { + /* Check the specified channel number */ if (ADC16_IS_CHANNEL_INVALID(ch)) { return status_invalid_argument; } - *result = ptr->PRD_CFG[ch].PRD_RESULT; + *result = ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(ptr->PRD_CFG[ch].PRD_RESULT); return status_success; } + +#if defined(ADC16_SOC_TEMP_CH_EN) && ADC16_SOC_TEMP_CH_EN +void adc16_enable_temp_sensor(ADC16_Type *ptr) +{ + uint32_t clk_div_temp; + + /* Get input clock divider */ + clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); + + /* Set input clock divider temporarily */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Enable ADC config clock */ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Enable the temperature sensor */ + ptr->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK | ADC16_ADC16_CONFIG0_REG_EN_MASK + | ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK | ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(5); + + /* Disable ADC config clock */ + ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Recover input clock divider */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); +} + +void adc16_disable_temp_sensor(ADC16_Type *ptr) +{ + uint32_t clk_div_temp; + + /* Get input clock divider */ + clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); + + /* Set input clock divider temporarily */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Enable ADC config clock */ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Disable the temp sensor */ + ptr->ADC16_CONFIG0 &= ~ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK; + + /* Disable ADC config clock */ + ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Recover input clock divider */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c index e4bd1f3b4d..3c58d8a844 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -20,43 +20,43 @@ void cam_get_default_config(CAM_Type *ptr, cam_config_t *config, display_pixel_f config->data_pack_msb = false; config->enable_buffer2 = false; config->data_store_mode = CAM_DATA_STORE_MODE_NORMAL; - config->color_format = CAM_COLOR_FORMAT_RGB565; + config->color_format = pixel_format; config->sensor_bitwidth = CAM_SENSOR_BITWIDTH_10BITS; - switch(pixel_format) { - case display_pixel_format_yuv422: - config->csc_config.enable = true; - config->csc_config.ycbcr_mode = false; - config->csc_config.yuv2rgb_coef.c0 = 0x100; - config->csc_config.yuv2rgb_coef.uv_offset = 0; - config->csc_config.yuv2rgb_coef.y_offset = 0; - config->csc_config.yuv2rgb_coef.c1 = 0x123; - config->csc_config.yuv2rgb_coef.c2 = 0x76B; - config->csc_config.yuv2rgb_coef.c3 = 0x79C; - config->csc_config.yuv2rgb_coef.c4 = 0x208; - break; - case display_pixel_format_ycbcr422: - config->csc_config.enable = true; - config->csc_config.ycbcr_mode = true; - config->csc_config.yuv2rgb_coef.c0 = 0x12A; - config->csc_config.yuv2rgb_coef.uv_offset = 0x180; - config->csc_config.yuv2rgb_coef.y_offset = 0x1F0; - config->csc_config.yuv2rgb_coef.c1 = 0x198; - config->csc_config.yuv2rgb_coef.c2 = 0x730; - config->csc_config.yuv2rgb_coef.c3 = 0x79C; - config->csc_config.yuv2rgb_coef.c4 = 0x204; - break; - default: - config->csc_config.enable = false; - config->csc_config.ycbcr_mode = false; - config->csc_config.yuv2rgb_coef.c0 = 0; - config->csc_config.yuv2rgb_coef.uv_offset = 0; - config->csc_config.yuv2rgb_coef.y_offset = 0; - config->csc_config.yuv2rgb_coef.c1 = 0; - config->csc_config.yuv2rgb_coef.c2 = 0; - config->csc_config.yuv2rgb_coef.c3 = 0; - config->csc_config.yuv2rgb_coef.c4 = 0; - break; + switch (pixel_format) { + case display_pixel_format_yuv422: + config->csc_config.enable = true; + config->csc_config.ycbcr_mode = false; + config->csc_config.yuv2rgb_coef.c0 = 0x100; + config->csc_config.yuv2rgb_coef.uv_offset = 0; + config->csc_config.yuv2rgb_coef.y_offset = 0; + config->csc_config.yuv2rgb_coef.c1 = 0x123; + config->csc_config.yuv2rgb_coef.c2 = 0x76B; + config->csc_config.yuv2rgb_coef.c3 = 0x79C; + config->csc_config.yuv2rgb_coef.c4 = 0x208; + break; + case display_pixel_format_ycbcr422: + config->csc_config.enable = true; + config->csc_config.ycbcr_mode = true; + config->csc_config.yuv2rgb_coef.c0 = 0x12A; + config->csc_config.yuv2rgb_coef.uv_offset = 0x180; + config->csc_config.yuv2rgb_coef.y_offset = 0x1F0; + config->csc_config.yuv2rgb_coef.c1 = 0x198; + config->csc_config.yuv2rgb_coef.c2 = 0x730; + config->csc_config.yuv2rgb_coef.c3 = 0x79C; + config->csc_config.yuv2rgb_coef.c4 = 0x204; + break; + default: + config->csc_config.enable = false; + config->csc_config.ycbcr_mode = false; + config->csc_config.yuv2rgb_coef.c0 = 0; + config->csc_config.yuv2rgb_coef.uv_offset = 0; + config->csc_config.yuv2rgb_coef.y_offset = 0; + config->csc_config.yuv2rgb_coef.c1 = 0; + config->csc_config.yuv2rgb_coef.c2 = 0; + config->csc_config.yuv2rgb_coef.c3 = 0; + config->csc_config.yuv2rgb_coef.c4 = 0; + break; } } @@ -73,6 +73,19 @@ void cam_reset(CAM_Type *ptr) hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) { hpm_stat_t stat = status_success; + uint32_t pixel_format, width; + + pixel_format = config->color_format; + width = config->width; + + if (pixel_format == CAM_COLOR_FORMAT_RAW8) { + if ((width % 2) != 0) { + return status_invalid_argument; + } + /* use rgb565 format to receive raw8 data and adjust the width to half */ + pixel_format = CAM_COLOR_FORMAT_RGB565; + width /= 2; + } cam_reset(ptr); @@ -83,11 +96,11 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) | CAM_CR1_COLOR_EXT_SET(config->color_ext) | CAM_CR1_PACK_DIR_SET(config->data_pack_msb) | config->data_store_mode - | config->color_format + | pixel_format | config->sensor_bitwidth; ptr->IDEAL_WN_SIZE = CAM_IDEAL_WN_SIZE_HEIGHT_SET(config->height) - | CAM_IDEAL_WN_SIZE_WIDTH_SET(config->width); + | CAM_IDEAL_WN_SIZE_WIDTH_SET(width); ptr->MAX_WN_CYCLE = CAM_MAX_WN_CYCLE_ROW_SET(1200) | CAM_MAX_WN_CYCLE_COL_SET(2090); @@ -112,6 +125,11 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) return stat; } +void cam_update_buffer(CAM_Type *ptr, uint32_t buffer) +{ + ptr->DMASA_FB1 = buffer; +} + void cam_stop(CAM_Type *ptr) { ptr->CR18 &= ~CAM_CR18_CAM_ENABLE_MASK; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c index c52908c32b..b7a10b0669 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -84,42 +84,41 @@ typedef struct { /** * @brief CAN bit timing list for all supported bit timing modes */ -static const can_bit_timing_table_t s_can_bit_timing_tbl[3] = +static const can_bit_timing_table_t s_can_bit_timing_tbl[3] = { { - { - .tq_min = NUM_TQ_MIN_FOR_CAN2_0, - .tq_max = NUM_TQ_MAX_FOR_CAN2_0, - .seg1_min = TSEG1_MIN_FOR_CAN2_0, - .seg1_max = TSEG1_MAX_FOR_CAN2_0, - .seg2_min = TSEG2_MIN_FOR_CAN2_0, - .seg2_max = TSEG2_MAX_FOR_CAN2_0, - .sjw_min = TSJW_MIN_FOR_CAN2_0, - .sjw_max = TSJW_MAX_FOR_CAN2_0, - .min_diff_seg1_minus_seg2 = 2, - }, - { - .tq_min = NUM_TQ_MIN_FOR_CANFD_NOMINAL, - .tq_max = NUM_TQ_MAX_FOR_CANFD_NOMINAL, - .seg1_min = TSEG1_MIN_FOR_CANFD_NORMINAL, - .seg1_max = TSEG1_MAX_FOR_CANFD_NORMINAL, - .seg2_min = TSEG2_MIN_FOR_CANFD_NORMINAL, - .seg2_max = TSEG2_MAX_FOR_CANFD_NORMINAL, - .sjw_min = TSJW_MIN_FOR_CANFD_NORMINAL, - .sjw_max = TSJW_MAX_FOR_CANFD_NORMINAL, - .min_diff_seg1_minus_seg2 = 2, - }, - { - .tq_min = NUM_TQ_MIN_FOR_CANFD_DATA, - .tq_max = NUM_TQ_MAX_FOR_CANFD_DATA, - .seg1_min = TSEG1_MIN_FOR_CANFD_DATA, - .seg1_max = TSEG1_MAX_FOR_CANFD_DATA, - .seg2_min = TSEG2_MIN_FOR_CANFD_DATA, - .seg2_max = TSEG2_MAX_FOR_CANFD_DATA, - .sjw_min = TSJW_MIN_FOR_CANFD_DATA, - .sjw_max = TSJW_MAX_FOR_CANFD_DATA, - .min_diff_seg1_minus_seg2 = 1, - } - }; + .tq_min = NUM_TQ_MIN_FOR_CAN2_0, + .tq_max = NUM_TQ_MAX_FOR_CAN2_0, + .seg1_min = TSEG1_MIN_FOR_CAN2_0, + .seg1_max = TSEG1_MAX_FOR_CAN2_0, + .seg2_min = TSEG2_MIN_FOR_CAN2_0, + .seg2_max = TSEG2_MAX_FOR_CAN2_0, + .sjw_min = TSJW_MIN_FOR_CAN2_0, + .sjw_max = TSJW_MAX_FOR_CAN2_0, + .min_diff_seg1_minus_seg2 = 2, + }, + { + .tq_min = NUM_TQ_MIN_FOR_CANFD_NOMINAL, + .tq_max = NUM_TQ_MAX_FOR_CANFD_NOMINAL, + .seg1_min = TSEG1_MIN_FOR_CANFD_NORMINAL, + .seg1_max = TSEG1_MAX_FOR_CANFD_NORMINAL, + .seg2_min = TSEG2_MIN_FOR_CANFD_NORMINAL, + .seg2_max = TSEG2_MAX_FOR_CANFD_NORMINAL, + .sjw_min = TSJW_MIN_FOR_CANFD_NORMINAL, + .sjw_max = TSJW_MAX_FOR_CANFD_NORMINAL, + .min_diff_seg1_minus_seg2 = 2, + }, + { + .tq_min = NUM_TQ_MIN_FOR_CANFD_DATA, + .tq_max = NUM_TQ_MAX_FOR_CANFD_DATA, + .seg1_min = TSEG1_MIN_FOR_CANFD_DATA, + .seg1_max = TSEG1_MAX_FOR_CANFD_DATA, + .seg2_min = TSEG2_MIN_FOR_CANFD_DATA, + .seg2_max = TSEG2_MAX_FOR_CANFD_DATA, + .sjw_min = TSJW_MIN_FOR_CANFD_DATA, + .sjw_max = TSJW_MAX_FOR_CANFD_DATA, + .min_diff_seg1_minus_seg2 = 1, + } +}; /*********************************************************************************************************************** * @@ -150,16 +149,16 @@ static uint32_t find_closest_prescaler(uint32_t num_tq_mul_prescaler, uint32_t s ++prescaler; continue; } else { - has_found = true; - break; - } - uint32_t tq = num_tq_mul_prescaler / prescaler; - if (tq * prescaler == num_tq_mul_prescaler) { - has_found = true; - break; - } else if (tq < min_tq) { - has_found = false; - break; + uint32_t tq = num_tq_mul_prescaler / prescaler; + if (tq * prescaler == num_tq_mul_prescaler) { + has_found = true; + break; + } else if (tq < min_tq) { + has_found = false; + break; + } else { + ++prescaler; + } } } @@ -323,30 +322,30 @@ static uint8_t can_get_data_words_from_dlc(uint32_t dlc) copy_words = (dlc + 3U) / sizeof(uint32_t); } else { switch (dlc) { - case can_payload_size_12: - copy_words = 3U; - break; - case can_payload_size_16: - copy_words = 4U; - break; - case can_payload_size_20: - copy_words = 5U; - break; - case can_payload_size_24: - copy_words = 6U; - break; - case can_payload_size_32: - copy_words = 8U; - break; - case can_payload_size_48: - copy_words = 12U; - break; - case can_payload_size_64: - copy_words = 16U; - break; - default: - /* Code should never touch here */ - break; + case can_payload_size_12: + copy_words = 3U; + break; + case can_payload_size_16: + copy_words = 4U; + break; + case can_payload_size_20: + copy_words = 5U; + break; + case can_payload_size_24: + copy_words = 6U; + break; + case can_payload_size_32: + copy_words = 8U; + break; + case can_payload_size_48: + copy_words = 12U; + break; + case can_payload_size_64: + copy_words = 16U; + break; + default: + /* Code should never touch here */ + break; } } @@ -412,7 +411,7 @@ hpm_stat_t can_send_high_priority_message_blocking(CAN_Type *base, const can_tra hpm_stat_t status = status_invalid_argument; do { - HPM_BREAK_IF ((base == NULL) || (message == NULL)); + HPM_BREAK_IF((base == NULL) || (message == NULL)); status = status_success; /* Select the high-priority buffer */ @@ -491,7 +490,7 @@ hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *messa hpm_stat_t status = status_invalid_argument; do { - HPM_BREAK_IF ((base == NULL) || (message == NULL)); + HPM_BREAK_IF((base == NULL) || (message == NULL)); while (CAN_CMD_STA_CMD_CTRL_RSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_RXBUF_IS_EMPTY) { @@ -684,8 +683,6 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSSS_MASK; } - can_enable_self_ack(base, config->enable_self_ack); - /* Configure CAN filters */ if (config->filter_list_num > CAN_FILTER_NUM_MAX) { status = status_can_filter_num_invalid; @@ -713,8 +710,11 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) can_reset(base, false); + /* Set Self-ack mode*/ + can_enable_self_ack(base, config->enable_self_ack); + /* Set CAN work mode */ - can_set_mode(base, config->mode); + can_set_node_mode(base, config->mode); /* Configure TX Buffer priority mode */ can_select_tx_buffer_priority_mode(base, config->enable_tx_buffer_priority_mode); diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c new file mode 100644 index 0000000000..862666bc41 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_crc_drv.h" + +void crc_get_default_channel_config(crc_channel_config_t *cfg) +{ + cfg->preset = crc_preset_crc32; + cfg->poly = 0x4C11DB7ul; + cfg->init = 0xFFFFFFFul; + cfg->in_byte_order = crc_in_byte_order_lsb; + cfg->refout = crc_refout_true; + cfg->refin = crc_refin_true; + cfg->poly_width = CRC_POLY_WIDTH_32; + cfg->xorout = 0xFFFFFFF; +} + +hpm_stat_t crc_setup_channel_config(CRC_Type *ptr, uint32_t ch_index, + crc_channel_config_t *cfg) +{ + ptr->CHN[ch_index].CLR |= CRC_CHN_CLR_CLR_MASK; + ptr->CHN[ch_index].PRE_SET = cfg->preset; + + if (!ptr->CHN[ch_index].PRE_SET) { + ptr->CHN[ch_index].POLY = cfg->poly; + ptr->CHN[ch_index].INIT_DATA = cfg->init; + ptr->CHN[ch_index].XOROUT = cfg->xorout; + ptr->CHN[ch_index].MISC_SETTING = CRC_CHN_MISC_SETTING_REV_OUT_SET(cfg->refout) | + CRC_CHN_MISC_SETTING_REV_IN_SET(cfg->refin) | + CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(cfg->poly_width); + } + + ptr->CHN[ch_index].MISC_SETTING |= CRC_CHN_MISC_SETTING_BYTE_REV_SET(cfg->in_byte_order); + return status_success; +} + +void crc_calc_block_bytes(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length) +{ + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + + for (uint32_t i = 0; i < length; i++) { + CRC_REG_WRITE8(addr, pbuffer[i]); + } +} + +void crc_calc_block_half_words(CRC_Type *ptr, uint32_t ch_index, uint16_t *pbuffer, uint32_t length) +{ + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + + for (uint32_t i = 0; i < length; i++) { + CRC_REG_WRITE16(addr, pbuffer[i]); + } +} + +void crc_calc_block_words(CRC_Type *ptr, uint32_t ch_index, uint32_t *pbuffer, uint32_t length) +{ + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + + for (uint32_t i = 0; i < length; i++) { + CRC_REG_WRITE32(addr, pbuffer[i]); + } +} + +void crc_calc_large_block_fast(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length) +{ + if (length < 16) { + crc_calc_block_bytes(ptr, ch_index, pbuffer, length); + return; + } + + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + uint32_t start_byte_addr = (uint32_t)pbuffer; + uint32_t start_byte_len = 4ul - (start_byte_addr & 0x03ul); + uint32_t word_addr = start_byte_addr + start_byte_len; + uint32_t word_len = (length - start_byte_len) & (~0x03ul); + uint32_t end_byte_addr = word_addr + word_len; + uint32_t end_byte_len = (length - start_byte_len - word_len); + + for (uint32_t i = 0; i < start_byte_len; i++) { + CRC_REG_WRITE8(addr, *(volatile uint8_t *)(start_byte_addr + i)); + } + + for (uint32_t i = 0; i < word_len; i += 4) { + CRC_REG_WRITE32(addr, *(volatile uint32_t *)(word_addr + i)); + } + + for (uint32_t i = 0; i < end_byte_len; i++) { + CRC_REG_WRITE8(addr, *(volatile uint8_t *)(end_byte_addr + i)); + } +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c index 32db96de46..470022cede 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,14 +7,11 @@ #include "hpm_dac_drv.h" -ATTR_PLACE_AT_NONCACHEABLE_BSS static uint32_t dac_cfg0; - void dac_get_default_config(dac_config_t *config) { config->sync_mode = false; config->dac_mode = dac_mode_direct; - config->clk_dac_div = dac_ana_div_2; - config->div_cfg = 167; + config->ana_div = dac_ana_div_2; } hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) @@ -23,27 +20,27 @@ hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) return status_invalid_argument; } - if (config->clk_dac_div > dac_ana_div_8) { + if (config->ana_div > dac_ana_div_8) { return status_invalid_argument; } /* reset DAC output data */ - dac_cfg0 &= ~DAC_CFG0_SW_DAC_DATA_MASK; + ptr->CFG0_BAK &= ~DAC_CFG0_SW_DAC_DATA_MASK; /* set sync mode */ - dac_cfg0 &= ~DAC_CFG0_SYNC_MODE_MASK; - dac_cfg0 |= DAC_CFG0_SYNC_MODE_SET(config->sync_mode); + ptr->CFG0_BAK &= ~DAC_CFG0_SYNC_MODE_MASK; + ptr->CFG0_BAK |= DAC_CFG0_SYNC_MODE_SET(config->sync_mode); /* set DAC mode */ - dac_cfg0 &= ~DAC_CFG0_DAC_MODE_MASK; - dac_cfg0 |= DAC_CFG0_DAC_MODE_SET(config->dac_mode); + ptr->CFG0_BAK &= ~DAC_CFG0_DAC_MODE_MASK; + ptr->CFG0_BAK |= DAC_CFG0_DAC_MODE_SET(config->dac_mode); /* refresh the CFG0 */ - ptr->CFG0 = dac_cfg0; + ptr->CFG0 = ptr->CFG0_BAK; /* set DAC clock config */ ptr->CFG1 &= ~DAC_CFG1_ANA_DIV_CFG_MASK; - ptr->CFG1 |= DAC_CFG1_ANA_DIV_CFG_SET(config->clk_dac_div); + ptr->CFG1 |= DAC_CFG1_ANA_DIV_CFG_SET(config->ana_div); if (config->dac_mode == dac_mode_direct) { /* set ANA_CLK_EN */ @@ -115,18 +112,18 @@ hpm_stat_t dac_set_buffer_config(DAC_Type *ptr, dac_buffer_config_t *config) } /* disable the internal DMA */ - dac_cfg0 &= ~DAC_CFG0_DMA_AHB_EN_MASK; + ptr->CFG0_BAK &= ~DAC_CFG0_DMA_AHB_EN_MASK; /* refresh the CFG0 */ - ptr->CFG0 = dac_cfg0; + ptr->CFG0 = ptr->CFG0_BAK; /* set buffer data mode */ - dac_cfg0 &= ~DAC_CFG0_BUF_DATA_MODE_MASK; - dac_cfg0 |= DAC_CFG0_BUF_DATA_MODE_SET(config->buf_data_mode); + ptr->CFG0_BAK &= ~DAC_CFG0_BUF_DATA_MODE_MASK; + ptr->CFG0_BAK |= DAC_CFG0_BUF_DATA_MODE_SET(config->buf_data_mode); /* set burst type */ - dac_cfg0 &= ~DAC_CFG0_HBURST_CFG_MASK; - dac_cfg0 |= DAC_CFG0_HBURST_CFG_SET(config->burst); + ptr->CFG0_BAK &= ~DAC_CFG0_HBURST_CFG_MASK; + ptr->CFG0_BAK |= DAC_CFG0_HBURST_CFG_SET(config->burst); /* reset DMA and FIFO */ ptr->CFG2 |= DAC_CFG2_DMA_RST1_MASK | DAC_CFG2_DMA_RST0_MASK | DAC_CFG2_FIFO_CLR_MASK; @@ -156,10 +153,10 @@ hpm_stat_t dac_set_buffer_config(DAC_Type *ptr, dac_buffer_config_t *config) ptr->BUF_LENGTH |= DAC_BUF_LENGTH_BUF1_LEN_SET(config->buf1.len - 1); /* enable the internal DMA */ - dac_cfg0 |= DAC_CFG0_DMA_AHB_EN_MASK; + ptr->CFG0_BAK |= DAC_CFG0_DMA_AHB_EN_MASK; /* refresh the CFG0 */ - ptr->CFG0 = dac_cfg0; + ptr->CFG0 = ptr->CFG0_BAK; return status_success; } @@ -171,11 +168,11 @@ hpm_stat_t dac_set_direct_config(DAC_Type *ptr, uint16_t data) } /* set dac data to analog output */ - dac_cfg0 &= ~DAC_CFG0_SW_DAC_DATA_MASK; - dac_cfg0 |= DAC_CFG0_SW_DAC_DATA_SET(data); + ptr->CFG0_BAK &= ~DAC_CFG0_SW_DAC_DATA_MASK; + ptr->CFG0_BAK |= DAC_CFG0_SW_DAC_DATA_SET(data); /* refresh the CFG0 */ - ptr->CFG0 = dac_cfg0; + ptr->CFG0 = ptr->CFG0_BAK; return status_success; } @@ -200,10 +197,10 @@ hpm_stat_t dac_set_step_sw_trigger(DAC_Type *ptr, uint8_t step_sw_trig_idx) } /* disable hw trigger */ - dac_cfg0 &= ~DAC_CFG0_HW_TRIG_EN_MASK; + ptr->CFG0_BAK &= ~DAC_CFG0_HW_TRIG_EN_MASK; /* refresh the CFG0 */ - ptr->CFG0 = dac_cfg0; + ptr->CFG0 = ptr->CFG0_BAK; /* enable sw trigger */ ptr->CFG2 |= 1 << step_sw_trig_idx; @@ -214,10 +211,10 @@ hpm_stat_t dac_set_step_sw_trigger(DAC_Type *ptr, uint8_t step_sw_trig_idx) void dac_set_buffer_sw_trigger(DAC_Type *ptr) { /* disable hw trigger */ - dac_cfg0 &= ~DAC_CFG0_HW_TRIG_EN_MASK; + ptr->CFG0_BAK &= ~DAC_CFG0_HW_TRIG_EN_MASK; /* refresh the CFG0 */ - ptr->CFG0 = dac_cfg0; + ptr->CFG0 = ptr->CFG0_BAK; /* enable sw trigger */ ptr->CFG2 |= DAC_CFG2_BUF_SW_TRIG_MASK; @@ -230,11 +227,11 @@ void dac_set_buffer_DMA_reset(DAC_Type *ptr) void dac_set_hw_trigger_enable(DAC_Type *ptr, bool enable) { - dac_cfg0 &= ~DAC_CFG0_HW_TRIG_EN_MASK; - dac_cfg0 |= DAC_CFG0_HW_TRIG_EN_SET(enable); + ptr->CFG0_BAK &= ~DAC_CFG0_HW_TRIG_EN_MASK; + ptr->CFG0_BAK |= DAC_CFG0_HW_TRIG_EN_SET(enable); /* refresh the CFG0 */ - ptr->CFG0 = dac_cfg0; + ptr->CFG0 = ptr->CFG0_BAK; } void dac_enable_conversion(DAC_Type *ptr, bool enable) diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c index fb6110b149..b9d9500f02 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c @@ -1,9 +1,9 @@ /* -* Copyright (c) 2021 hpmicro -* -* SPDX-License-Identifier: BSD-3-Clause -* -*/ + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ #include "hpm_dao_drv.h" void dao_get_default_config(DAO_Type *ptr, dao_config_t *config) diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c index 23991b5642..d4b29da0d2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,27 +7,26 @@ #include "hpm_dma_drv.h" -hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint32_t ch_num, dma_channel_config_t *ch) +hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint8_t ch_num, dma_channel_config_t *ch, bool start_transfer) { uint32_t tmp; + if ((ch->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (ch->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr))) { + || (ch->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch_num >= DMA_SOC_CHANNEL_NUM)) { return status_invalid_argument; } if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) || (ch->src_addr & ((1 << ch->src_width) - 1)) - || (ch->src_addr & (((1 << ch->src_width) << ch->src_burst_size) - 1)) || (ch->dst_addr & ((1 << ch->dst_width) - 1)) - || (ch->dst_addr & (((1 << ch->dst_width) << ch->src_burst_size) - 1)) || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) - || (((1 << ch->src_width) << ch->src_burst_size) & ((1 << ch->dst_width) - 1)) || ((ch->linked_ptr & 0x7))) { return status_dma_alignment_error; } ptr->CHCTRL[ch_num].SRCADDR = DMA_CHCTRL_SRCADDR_SRCADDRL_SET(ch->src_addr); ptr->CHCTRL[ch_num].DSTADDR = DMA_CHCTRL_DSTADDR_DSTADDRL_SET(ch->dst_addr); ptr->CHCTRL[ch_num].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_width); - ptr->CHCTRL[ch_num].LLPOINTER = DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(ch->linked_ptr >> 3); + ptr->CHCTRL[ch_num].LLPOINTER = DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(ch->linked_ptr >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); #if DMA_SUPPORT_64BIT_ADDR ptr->CHCTRL[ch_num].SRCADDRH = DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(ch->src_addr_high); @@ -48,12 +47,12 @@ hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint32_t ch_num, dma_channel_config_ | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(ch->dst_addr_ctrl) | DMA_CHCTRL_CTRL_SRCREQSEL_SET(ch_num) | DMA_CHCTRL_CTRL_DSTREQSEL_SET(ch_num) - | ch->interrupt_mask - | DMA_CHCTRL_CTRL_ENABLE_MASK; - ptr->CHCTRL[ch_num].CTRL = tmp; - if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_num)) { - return status_fail; + | ch->interrupt_mask; + + if (start_transfer) { + tmp |= DMA_CHCTRL_CTRL_ENABLE_MASK; } + ptr->CHCTRL[ch_num].CTRL = tmp; return status_success; } @@ -68,12 +67,58 @@ void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch) ch->src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; ch->dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; ch->interrupt_mask = DMA_INTERRUPT_MASK_NONE; - ch->linked_ptr= 0; + ch->linked_ptr = 0; #if DMA_SUPPORT_64BIT_ADDR ch->linked_ptr_high = 0; #endif } +hpm_stat_t dma_config_linked_descriptor(DMA_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config) +{ + uint32_t tmp; + + if ((config->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (config->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch_num >= DMA_SOC_CHANNEL_NUM)) { + return status_invalid_argument; + } + if ((config->size_in_byte & ((1 << config->dst_width) - 1)) + || (config->src_addr & ((1 << config->src_width) - 1)) + || (config->dst_addr & ((1 << config->dst_width) - 1)) + || ((1 << config->src_width) & ((1 << config->dst_width) - 1)) + || ((config->linked_ptr & 0x7))) { + return status_dma_alignment_error; + } + descriptor->src_addr = DMA_CHCTRL_SRCADDR_SRCADDRL_SET(config->src_addr); + descriptor->dst_addr = DMA_CHCTRL_DSTADDR_DSTADDRL_SET(config->dst_addr); + descriptor->trans_size = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(config->size_in_byte >> config->src_width); + descriptor->linked_ptr = DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(config->linked_ptr >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); + +#if DMA_SUPPORT_64BIT_ADDR + descriptor->src_addr_high = DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(config->src_addr_high); + descriptor->dst_addr_high = DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(config->dst_addr_high); + descriptor->linked_ptr_high = DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(config->linked_ptr_high); +#endif + + tmp = DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(0) + | DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(0) + | DMA_CHCTRL_CTRL_PRIORITY_SET(config->priority) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(config->src_burst_size) + | DMA_CHCTRL_CTRL_SRCWIDTH_SET(config->src_width) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(config->dst_width) + | DMA_CHCTRL_CTRL_SRCMODE_SET(config->src_mode) + | DMA_CHCTRL_CTRL_DSTMODE_SET(config->dst_mode) + | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(config->src_addr_ctrl) + | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(config->dst_addr_ctrl) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(ch_num) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(ch_num) + | config->interrupt_mask + | DMA_CHCTRL_CTRL_ENABLE_MASK; + descriptor->ctrl = tmp; + + return status_success; +} + hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, uint32_t dst, uint32_t src, uint32_t size, uint32_t burst_len_in_byte) @@ -97,9 +142,7 @@ hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, return status_invalid_argument; } - if ((size & (burst_len_in_byte - 1)) - || (dst & (burst_len_in_byte - 1)) - || (src & (burst_len_in_byte - 1))) { + if ((size & (burst_len_in_byte - 1))) { return status_dma_alignment_error; } burst_size = get_first_set_bit_from_lsb(burst_len_in_byte); @@ -130,7 +173,7 @@ hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, config.size_in_byte = size; config.src_burst_size = burst_size; - stat = dma_setup_channel(ptr, ch_num, &config); + stat = dma_setup_channel(ptr, ch_num, &config, true); if (stat != status_success) { return stat; } @@ -138,7 +181,12 @@ hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, return stat; } -hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig) +void dma_default_handshake_config(DMA_Type *ptr, dma_handshake_config_t *config) +{ + memset(config, 0, sizeof(dma_handshake_config_t)); +} + +hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer) { hpm_stat_t stat = status_success; dma_channel_config_t config = {0}; @@ -153,19 +201,18 @@ hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig) config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; } - if (pconfig->ch_index > DMA_SOC_CHANNEL_NUM) { + if (pconfig->ch_index >= DMA_SOC_CHANNEL_NUM) { return status_invalid_argument; } - /* In DMA handshake case, source width and destination width must be BYTE. */ - config.src_width = DMA_TRANSFER_WIDTH_BYTE; - config.dst_width = DMA_TRANSFER_WIDTH_BYTE; + config.src_width = pconfig->data_width; + config.dst_width = pconfig->data_width; config.src_addr = pconfig->src; config.dst_addr = pconfig->dst; config.size_in_byte = pconfig->size_in_byte; - /* In DMA handshake case, source burst size must be 1 transfer, that is 0. */ + /* In DMA handshake case, source burst size must be 1 transfer, that is 0. */ config.src_burst_size = 0; - stat = dma_setup_channel(ptr, pconfig->ch_index, &config); + stat = dma_setup_channel(ptr, pconfig->ch_index, &config, start_transfer); if (stat != status_success) { return stat; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dram_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dram_drv.c deleted file mode 100644 index 9c6f7febbd..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dram_drv.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright (c) 2021 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_dram_drv.h" - -#ifndef HPM_DRAM_DRV_DEFAULT_PRESCALER -#define HPM_DRAM_DRV_DEFAULT_PRESCALER (0x3UL) -#endif - -#ifndef HPM_DRAM_DRV_RETRY_COUNT -#define HPM_DRAM_DRV_RETRY_COUNT (5000U) -#endif - -#define DRAM_PRESCALER_MAX (256UL) - -static void dram_config_delay_cell(DRAM_Type *ptr, uint32_t delay_cell_value) -{ - ptr->DLYCFG &= ~DRAM_DLYCFG_OE_MASK; - ptr->DLYCFG = DRAM_DLYCFG_DLYSEL_SET(delay_cell_value) | DRAM_DLYCFG_DLYEN_MASK; - ptr->DLYCFG |= DRAM_DLYCFG_OE_MASK; -} - -static hpm_stat_t dram_ip_cmd_done(DRAM_Type *ptr) -{ - uint32_t intr_status = 0; - uint32_t retry = 0; - do { - if (retry > HPM_DRAM_DRV_RETRY_COUNT) { - break; - } - retry++; - intr_status = ptr->INTR - & (uint32_t)(DRAM_INTR_IPCMDDONE_MASK | DRAM_INTR_IPCMDERR_MASK); - } while (intr_status == 0); - - if (retry > HPM_DRAM_DRV_RETRY_COUNT) { - return status_timeout; - } - - ptr->INTR |= DRAM_INTR_IPCMDDONE_MASK | DRAM_INTR_IPCMDERR_MASK; - if (intr_status & DRAM_INTR_IPCMDERR_MASK) { - return status_dram_cmd_err; - } - return status_success; -} - -static uint32_t dram_make_cmd(uint32_t opcode) -{ - return (opcode & ~DRAM_CMD_WRITE_FLAG) | DRAM_CMD_KEY; -} - -static bool dram_is_write_cmd(uint32_t opcode) -{ - return ((opcode & DRAM_CMD_WRITE_FLAG) == DRAM_CMD_WRITE_FLAG); -} - -uint32_t dram_issue_ip_cmd(DRAM_Type *ptr, uint32_t base_address, dram_cmd_t *cmd) -{ - bool read_data = !dram_is_write_cmd(cmd->opcode); - ptr->SADDR = base_address; - if (!read_data) { - ptr->IPTX = cmd->data; - } - ptr->IPCMD = dram_make_cmd(cmd->opcode); - - if (dram_ip_cmd_done(ptr) < 0) { - return status_dram_cmd_err; - } - - if (read_data) { - cmd->data = ptr->IPRX; - } - return status_success; -} - -void dram_default_config(DRAM_Type *ptr, dram_config_t *config) -{ - dram_axi_q_weight_t *q; - config->dqs = DRAM_DQS_FROM_PAD; - config->cmd_timeout = 0; - config->bus_timeout = 0x10; - q = &config->axi_q_weight[DRAM_AXI_Q_A]; - q->enable = true; - q->qos = 4; - q->age = 2; - q->slave_hit = 0x5; - q->slave_hit_wo_rw = 0x3; - - q = &config->axi_q_weight[DRAM_AXI_Q_B]; - q->enable = true; - q->qos = 4; - q->age = 2; - q->page_hit = 0x5; - q->slave_hit_wo_rw = 0x3; - q->bank_rotation = 0x6; -} - -void dram_get_typical_sdram_config(DRAM_Type *ptr, dram_sdram_config_t *config) -{ - config->col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - config->cas_latency = DRAM_SDRAM_CAS_LATENCY_3; - config->bank_num = DRAM_SDRAM_BANK_NUM_4; - config->prescaler = HPM_DRAM_DRV_DEFAULT_PRESCALER; - config->burst_len_in_byte = 8; - config->auto_refresh_count_in_one_burst = 1; - config->precharge_to_act_in_ns = 20; - config->act_to_rw_in_ns = 20; - config->refresh_recover_in_ns = 70; - config->write_recover_in_ns = 12; - config->cke_off_in_ns = 42; - config->act_to_precharge_in_ns = 42; - - config->self_refresh_recover_in_ns = 70; - config->refresh_to_refresh_in_ns = 60; - config->act_to_act_in_ns = 12; - config->idle_timeout_in_ns = 6; - config->cs_mux_pin = DRAM_IO_MUX_NOT_USED; -} - -void dram_init(DRAM_Type *ptr, dram_config_t *config) -{ - uint32_t i; - dram_axi_q_weight_t *q; - for (i = 0; i < DRAM_BR_COUNT; i++) { - ptr->BR[i] = 0; - } - - dram_sw_reset(ptr); - dram_disable(ptr); - ptr->CTRL |= DRAM_CTRL_BTO_SET(config->bus_timeout) - | DRAM_CTRL_CTO_SET(config->cmd_timeout) - | DRAM_CTRL_DQS_SET(config->dqs); - - q = &config->axi_q_weight[DRAM_AXI_Q_A]; - if (q->enable) { - ptr->BMW0 = DRAM_BMW0_QOS_SET(q->qos) - | DRAM_BMW0_AGE_SET(q->age) - | DRAM_BMW0_SH_SET(q->slave_hit) - | DRAM_BMW0_RWS_SET(q->slave_hit_wo_rw); - } else { - ptr->BMW0 = 0; - } - - q = &config->axi_q_weight[DRAM_AXI_Q_B]; - if (q->enable) { - ptr->BMW1 = DRAM_BMW1_QOS_SET(q->qos) - | DRAM_BMW1_AGE_SET(q->age) - | DRAM_BMW1_PH_SET(q->page_hit) - | DRAM_BMW1_BR_SET(q->bank_rotation) - | DRAM_BMW1_RWS_SET(q->slave_hit_wo_rw); - } else { - ptr->BMW1 = 0; - } - - dram_enable(ptr); -} - -static uint8_t dram_convert_actual_size_to_memory_size(uint32_t size_in_kb) -{ - uint8_t size = 0; - if (size_in_kb == 4) { - return 0; - } - - if (size_in_kb > 2 * 1 << 20) { - return 0x1F; - } - - size = 1; - size_in_kb >>= 3; - while (size_in_kb > 1) { - size_in_kb >>= 1; - size++; - } - return size; -} - -static uint8_t dram_convert_burst_len(uint8_t burst_len_in_byte) -{ - if ((burst_len_in_byte == 0) - || (burst_len_in_byte > DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE)) { - return DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; - } - - switch (burst_len_in_byte) { - case 1: - case 2: - case 4: - return burst_len_in_byte >> 1; - case 8: - return (burst_len_in_byte - 1) >> 1; - default: - return DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; - } -} - -static uint32_t ns2cycle(uint32_t freq_in_hz, uint32_t ns) -{ - uint32_t ns_per_cycle; - ns_per_cycle = 1000000000 / freq_in_hz ; - if (ns < ns_per_cycle) { - return 1; - } - return ns / ns_per_cycle; -} - -hpm_stat_t dram_config_sdram(DRAM_Type *ptr, uint32_t clk_in_hz, dram_sdram_config_t *config) -{ - hpm_stat_t err; - uint32_t prescaler; - uint32_t refresh_cycle; - uint32_t clk_in_khz = clk_in_hz / 1000; - dram_cmd_t cmd = {0}; - uint8_t size = dram_convert_actual_size_to_memory_size(config->size_in_byte >> 10); - uint8_t burst_len = dram_convert_burst_len(config->burst_len_in_byte); - - prescaler = ((config->prescaler == 0) ? DRAM_PRESCALER_MAX : config->prescaler); - refresh_cycle = clk_in_khz * config->refresh_in_ms / config->refresh_count / (prescaler << 4); - - if ((prescaler == 0) || (prescaler > DRAM_PRESCALER_MAX) - || (refresh_cycle == 0) || (refresh_cycle > DRAM_PRESCALER_MAX)) { - return status_invalid_argument; - } - - if (prescaler == DRAM_PRESCALER_MAX) { - prescaler = 0; - } - - if (refresh_cycle == DRAM_PRESCALER_MAX) { - refresh_cycle = 0; - } - - ptr->BR[config->cs] = DRAM_BR_BASE_SET(config->base_address >> DRAM_BR_BASE_SHIFT) - | DRAM_BR_SIZE_SET(size) | DRAM_BR_VLD_MASK; - - ptr->SDRCTRL0 = DRAM_SDRCTRL0_PORTSZ_SET(config->port_size) - | DRAM_SDRCTRL0_BURSTLEN_SET(burst_len) - | DRAM_SDRCTRL0_COL_SET(config->col_addr_bits) - | DRAM_SDRCTRL0_COL8_SET(config->col_addr_bits == DRAM_SDRAM_COLUMN_ADDR_8_BITS) - | DRAM_SDRCTRL0_CAS_SET(config->cas_latency) - | DRAM_SDRCTRL0_BANK2_SET(config->bank_num); - - ptr->SDRCTRL1 = DRAM_SDRCTRL1_PRE2ACT_SET(ns2cycle(clk_in_hz, config->precharge_to_act_in_ns)) - | DRAM_SDRCTRL1_ACT2RW_SET(ns2cycle(clk_in_hz, config->act_to_rw_in_ns)) - | DRAM_SDRCTRL1_RFRC_SET(ns2cycle(clk_in_hz, config->refresh_recover_in_ns)) - | DRAM_SDRCTRL1_WRC_SET(ns2cycle(clk_in_hz, config->write_recover_in_ns)) - | DRAM_SDRCTRL1_CKEOFF_SET(ns2cycle(clk_in_hz, config->cke_off_in_ns)) - | DRAM_SDRCTRL1_ACT2PRE_SET(ns2cycle(clk_in_hz, config->act_to_precharge_in_ns)); - - ptr->SDRCTRL2 = DRAM_SDRCTRL2_SRRC_SET(ns2cycle(clk_in_hz, config->self_refresh_recover_in_ns)) - | DRAM_SDRCTRL2_REF2REF_SET(ns2cycle(clk_in_hz, config->refresh_to_refresh_in_ns)) - | DRAM_SDRCTRL2_ACT2ACT_SET(ns2cycle(clk_in_hz, config->act_to_act_in_ns)) - | DRAM_SDRCTRL2_ITO_SET(ns2cycle(clk_in_hz, config->idle_timeout_in_ns)); - - ptr->SDRCTRL3 = DRAM_SDRCTRL3_PRESCALE_SET(prescaler) - | DRAM_SDRCTRL3_RT_SET(refresh_cycle) - | DRAM_SDRCTRL3_UT_SET(refresh_cycle) - | DRAM_SDRCTRL3_REBL_SET(config->auto_refresh_count_in_one_burst - 1); - /* - * - * DATSZ[2:0]: Data size in byte - * 0b - 4 - * 1b - 1 - * 2b - 2 - * 3b - 3 - * > 3b - 4 - */ - ptr->DATSZ = DRAM_DATSZ_DATSZ_SET((config->data_width_in_byte & (0x3UL))); - ptr->BYTEMSK = 0; - - cmd.opcode = DRAM_CMD_SDRAM_PRECHARGE_ALL; - cmd.data = 0; - err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - - cmd.opcode = DRAM_CMD_SDRAM_AUTO_REFRESH; - err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - - /* - * - * DATSZ[2:0]: Data size in byte - * 0b - 4 - * 1b - 1 - * 2b - 2 - * 3b - 3 - * > 3b - 4 - */ - ptr->DATSZ = DRAM_DATSZ_DATSZ_SET((config->data_width_in_byte & (0x3UL))); - ptr->BYTEMSK = 0; - - /* - * config delay cell - */ - dram_config_delay_cell(ptr, config->delay_cell_value); - - cmd.opcode = DRAM_CMD_SDRAM_PRECHARGE_ALL; - cmd.data = 0; - err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - - cmd.opcode = DRAM_CMD_SDRAM_AUTO_REFRESH; - err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - - cmd.opcode = DRAM_CMD_SDRAM_MODE_SET; - /* FIXME: the mode register layout definition better to be passed in? */ - cmd.data = (uint32_t)(burst_len | config->cas_latency << 4); - err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - ptr->SDRCTRL3 |= DRAM_SDRCTRL3_REN_MASK; - - return status_success; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c index bcd2de27b9..4741b45c81 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c @@ -1,19 +1,21 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_enet_soc_drv.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Internal API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ static void enet_mode_init(ENET_Type *ptr, uint32_t intr) { /* receive and transmit store and forward */ @@ -30,19 +32,21 @@ static void enet_mode_init(ENET_Type *ptr, uint32_t intr) ptr->DMA_INTR_EN |= intr; - while (ENET_DMA_BUS_STATUS_AXIRDSTS_GET(ptr->DMA_BUS_STATUS) || ENET_DMA_BUS_STATUS_AXWHSTS_GET(ptr->DMA_BUS_STATUS)) {} + while (ENET_DMA_BUS_STATUS_AXIRDSTS_GET(ptr->DMA_BUS_STATUS) || ENET_DMA_BUS_STATUS_AXWHSTS_GET(ptr->DMA_BUS_STATUS)) { + } /* start the receive and transmit dma */ ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_ST_MASK | ENET_DMA_OP_MODE_SR_MASK; } -static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr) +static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr, uint8_t pbl) { /* generate software reset */ ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_SWR_MASK; /* wait for the completion of reset process */ - while (ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)) {} + while (ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)) { + } /* initialize bus mode register */ ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_AAL_MASK; @@ -53,7 +57,8 @@ static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr) ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBLX8_MASK; /* set programmable burst length */ - ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBL_SET(enet_pbl_32); + ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_PBL_SHIFT; + ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBL_SET(pbl); /* disable separate pbl */ ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_USP_MASK; @@ -68,8 +73,7 @@ static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr) /* set the maximum enabled burst length */ if (ENET_DMA_BUS_MODE_FB_GET(ptr->DMA_BUS_MODE) == 0) { ptr->DMA_AXI_MODE |= ENET_DMA_AXI_MODE_BLEN4_MASK | ENET_DMA_AXI_MODE_BLEN8_MASK | ENET_DMA_AXI_MODE_BLEN16_MASK; - } - else { + } else { /* TODO: set BLENX_MASK */ } @@ -86,26 +90,28 @@ static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr) return true; } -static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_type_t inf_type, uint32_t mask_intr) +static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_type_t inf_type) { for (int i = 0; i < config->valid_max_count; i++) { if (i == 0) { - ptr->MAC_ADDR_0_HIGH = ENET_MAC_ADDR_0_HIGH_AE_MASK; + ptr->MAC_ADDR_0_HIGH &= ~ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK; + ptr->MAC_ADDR_0_LOW &= ~ENET_MAC_ADDR_0_LOW_ADDRLO_MASK; ptr->MAC_ADDR_0_HIGH |= ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(config->mac_addr_high[i]); - ptr->MAC_ADDR_0_LOW = ENET_MAC_ADDR_0_LOW_ADDRLO_SET(config->mac_addr_low[i]); + ptr->MAC_ADDR_0_LOW |= ENET_MAC_ADDR_0_LOW_ADDRLO_SET(config->mac_addr_low[i]); } else { - ptr->MAC_ADDR[i].HIGH |= ENET_MAC_ADDR_HIGH_ADDRHI_SET(config->mac_addr_high[i]); - ptr->MAC_ADDR[i].LOW |= ENET_MAC_ADDR_LOW_ADDRLO_SET(config->mac_addr_low[i]); + ptr->MAC_ADDR[i-1].HIGH &= ~ENET_MAC_ADDR_HIGH_ADDRHI_MASK; + ptr->MAC_ADDR[i-1].LOW &= ~ENET_MAC_ADDR_LOW_ADDRLO_MASK; + ptr->MAC_ADDR[i-1].HIGH |= ENET_MAC_ADDR_HIGH_AE_MASK | ENET_MAC_ADDR_HIGH_ADDRHI_SET(config->mac_addr_high[i]); + ptr->MAC_ADDR[i-1].LOW |= ENET_MAC_ADDR_LOW_ADDRLO_SET(config->mac_addr_low[i]); } } - /* set the appropriate filters for the incoming frames */ ptr->MACFF |= ENET_MACFF_RA_SET(1); /* receive all */ /* replace the content of the mac address 0 in the sa field of all transmitted frames */ - ptr->MACCFG &= ENET_MACCFG_SARC_MASK; - ptr->MACCFG |= ENET_MACCFG_SARC_SET(0x3); + ptr->MACCFG &= ~ENET_MACCFG_SARC_MASK; + ptr->MACCFG |= ENET_MACCFG_SARC_SET(config->sarc); ptr->MACCFG |= ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK; @@ -129,15 +135,44 @@ static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_typ /* enable transmitter enable and receiver */ ptr->MACCFG |= ENET_MACCFG_TE_MASK | ENET_MACCFG_RE_MASK; - /* enable mask interrupt */ - ptr->INTR_MASK |= mask_intr; - return true; } -/*---------------------------------------------------------------------* +static void enet_mask_interrupt_event(ENET_Type *ptr, uint32_t mask) +{ + /* mask the specified interrupts */ + ptr->INTR_MASK |= mask; +} + +/*--------------------------------------------------------------------- * Driver API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ +uint32_t enet_get_interrupt_status(ENET_Type *ptr) +{ + return ptr->INTR_STATUS; +} + +void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask) +{ + ptr->MMC_INTR_MASK_RX |= mask; +} + +uint32_t enet_get_mmc_rx_interrupt_status(ENET_Type *ptr) +{ + return ptr->MMC_INTR_RX; +} + +void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask) +{ + ptr->MMC_INTR_MASK_TX |= mask; +} + +uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr) +{ + return ptr->MMC_INTR_TX; +} + void enet_dma_flush(ENET_Type *ptr) { /* flush DMA transmit FIFO */ @@ -157,10 +192,11 @@ void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t d | ENET_GMII_ADDR_GR_SET(addr) | ENET_GMII_ADDR_CR_SET(enet_csr_150m_to_250m_mdc_csr_div_102) | ENET_GMII_ADDR_GW_SET(enet_phy_op_write) - | ENET_GMII_ADDR_GB_SET(enet_phy_busy); + | ENET_GMII_ADDR_GB_SET(enet_gmii_busy); /* wait until the write operation is completed */ - while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) {} + while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) { + } } uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) @@ -170,37 +206,55 @@ uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) | ENET_GMII_ADDR_GR_SET(addr) | ENET_GMII_ADDR_CR_SET(enet_csr_150m_to_250m_mdc_csr_div_102) | ENET_GMII_ADDR_GW_SET(enet_phy_op_read) - | ENET_GMII_ADDR_GB_SET(enet_phy_busy); + | ENET_GMII_ADDR_GB_SET(enet_gmii_busy); /* wait until the write operation is completed */ - while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) {} + while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) { + } /* read and return data */ return (uint16_t)ENET_GMII_DATA_GD_GET(ptr->GMII_DATA); } -void enet_set_mask_interrupt(ENET_Type *ptr, uint32_t mask_intr) +void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed) { - ptr->INTR_MASK |= mask_intr; + ptr->MACCFG &= ~(ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK); + ptr->MACCFG |= speed << ENET_MACCFG_FES_SHIFT; } -int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, uint32_t intr, uint32_t mask_intr) +void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode) { - /* select RGMII */ + ptr->MACCFG &= ~ENET_MACCFG_DM_MASK; + ptr->MACCFG |= ENET_MACCFG_DM_SET(mode); +} + +int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, enet_int_config_t *int_config) +{ + /* select an interface */ enet_intf_selection(ptr, inf_type); /* initialize DMA */ - enet_dma_init(ptr, desc, intr); + enet_dma_init(ptr, desc, int_config->int_enable, config->dma_pbl); - /* Initialize MAC */ - enet_mac_init(ptr, config, inf_type, mask_intr); + /* initialize MAC */ + enet_mac_init(ptr, config, inf_type); + + /* mask the specified interrupts */ + enet_mask_interrupt_event(ptr, int_config->int_mask); + + /* mask the mmc rx interrupts */ + enet_mask_mmc_rx_interrupt_event(ptr, int_config->mmc_intr_mask_rx); + + /* mask the mmc tx interrupts */ + enet_mask_mmc_tx_interrupt_event(ptr, int_config->mmc_intr_mask_tx); return true; } -/******************************************************************************/ -/* DMA API */ -/******************************************************************************/ +/***************************************************************************** + * DMA API + ***************************************************************************** + */ uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) { enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; @@ -325,6 +379,216 @@ enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_l return frame; } +void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config) +{ + config->enable_ioc = false; + config->disable_crc = true; + config->disable_pad = false; + config->enable_ttse = false; + config->enable_crcr = true; + config->cic = enet_cic_ip_pseudoheader; + config->vlic = enet_vlic_disable; + config->saic = enet_saic_disable; +} + +uint32_t enet_prepare_tx_desc_with_ts_record(ENET_Type *ptr, + enet_tx_desc_t **parent_tx_desc_list_cur, + enet_tx_control_config_t *config, + uint16_t frame_length, uint16_t tx_buff_size, + enet_ptp_ts_system_t *timestamp) +{ + uint32_t buf_count = 0, size = 0, i = 0; + uint32_t retry_cnt = ENET_RETRY_CNT; + enet_tx_desc_t *dma_tx_desc; + enet_tx_desc_t *tx_desc_list_cur = *parent_tx_desc_list_cur; + + if (tx_buff_size == 0) { + return ENET_ERROR; + } + /* check if the descriptor is owned by the Ethernet DMA (when set) or CPU (when reset) */ + + dma_tx_desc = tx_desc_list_cur; + + if (frame_length > tx_buff_size) { + buf_count = frame_length / tx_buff_size; + if (frame_length % tx_buff_size) { + buf_count++; + } + } else { + buf_count = 1; + } + + if (buf_count == 1) { + /*set the last and the first segment */ + dma_tx_desc->tdes0_bm.own = 0; + dma_tx_desc->tdes0_bm.fs = 1; + dma_tx_desc->tdes0_bm.ls = 1; + dma_tx_desc->tdes0_bm.ic = config->enable_ioc; + dma_tx_desc->tdes0_bm.dc = config->disable_crc; + dma_tx_desc->tdes0_bm.dp = config->disable_pad; + dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; + dma_tx_desc->tdes0_bm.cic = config->cic; + dma_tx_desc->tdes0_bm.vlic = config->vlic; + dma_tx_desc->tdes0_bm.ttse = config->enable_ttse; + dma_tx_desc->tdes1_bm.saic = config->saic; + /* set the frame size */ + dma_tx_desc->tdes1_bm.tbs1 = (frame_length & ENET_DMATxDesc_TBS1); + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + + if (dma_tx_desc->tdes0_bm.ttse == true) { + do { + + } while (dma_tx_desc->tdes0_bm.own == 1 && retry_cnt-- > 0); + + if (retry_cnt == 0) { + return ENET_ERROR; + } + + timestamp->sec = dma_tx_desc->tdes7_bm.ttsh; + timestamp->nsec = dma_tx_desc->tdes6_bm.ttsl; + } + + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + } else { + for (i = 0; i < buf_count; i++) { + /* get the next available tx descriptor */ + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + + /* clear first and last segment bits */ + dma_tx_desc->tdes0_bm.fs = 0; + dma_tx_desc->tdes0_bm.ls = 0; + + if (i == 0) { + /* setting the first segment bit */ + dma_tx_desc->tdes0_bm.fs = 1; + dma_tx_desc->tdes0_bm.dc = config->disable_crc; + dma_tx_desc->tdes0_bm.dp = config->disable_pad; + dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; + dma_tx_desc->tdes0_bm.cic = config->cic; + dma_tx_desc->tdes0_bm.vlic = config->vlic; + dma_tx_desc->tdes0_bm.ttse = config->enable_ttse; + dma_tx_desc->tdes1_bm.saic = config->saic; + + if (dma_tx_desc->tdes0_bm.ttse == true) { + do { + + } while (dma_tx_desc->tdes0_bm.own == 1 && retry_cnt-- > 0); + + if (retry_cnt == 0) { + return ENET_ERROR; + } + + timestamp->sec = dma_tx_desc->tdes7_bm.ttsh; + timestamp->nsec = dma_tx_desc->tdes6_bm.ttsl; + } + } + + /* set the buffer 1 size */ + dma_tx_desc->tdes1_bm.tbs1 = (tx_buff_size & ENET_DMATxDesc_TBS1); + + if (i == (buf_count - 1)) { + /* set the last segment bit */ + dma_tx_desc->tdes0_bm.ls = 1; + dma_tx_desc->tdes0_bm.ic = config->enable_ioc; + size = frame_length - (buf_count - 1) * tx_buff_size; + dma_tx_desc->tdes1_bm.tbs1 = (size & ENET_DMATxDesc_TBS1); + + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + } + } + } + + tx_desc_list_cur = dma_tx_desc; + *parent_tx_desc_list_cur = tx_desc_list_cur; + + return ENET_SUCCESS; +} + +uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size) +{ + uint32_t buf_count = 0, size = 0, i = 0; + enet_tx_desc_t *dma_tx_desc; + enet_tx_desc_t *tx_desc_list_cur = *parent_tx_desc_list_cur; + + if (tx_buff_size == 0) { + return ENET_ERROR; + } + /* check if the descriptor is owned by the Ethernet DMA (when set) or CPU (when reset) */ + dma_tx_desc = tx_desc_list_cur; + if (frame_length > tx_buff_size) { + buf_count = frame_length / tx_buff_size; + if (frame_length % tx_buff_size) { + buf_count++; + } + } else { + buf_count = 1; + } + + if (buf_count == 1) { + /*set the last and the first segment */ + dma_tx_desc->tdes0_bm.own = 0; + dma_tx_desc->tdes0_bm.fs = 1; + dma_tx_desc->tdes0_bm.ls = 1; + dma_tx_desc->tdes0_bm.ic = config->enable_ioc; + dma_tx_desc->tdes0_bm.dc = config->disable_crc; + dma_tx_desc->tdes0_bm.dp = config->disable_pad; + dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; + dma_tx_desc->tdes0_bm.cic = config->cic; + dma_tx_desc->tdes0_bm.vlic = config->vlic; + dma_tx_desc->tdes1_bm.saic = config->saic; + /* set the frame size */ + dma_tx_desc->tdes1_bm.tbs1 = (frame_length & ENET_DMATxDesc_TBS1); + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + } else { + for (i = 0; i < buf_count; i++) { + /* clear first and last segment bits */ + dma_tx_desc->tdes0_bm.fs = 0; + dma_tx_desc->tdes0_bm.ls = 0; + + if (i == 0) { + /* setting the first segment bit */ + dma_tx_desc->tdes0_bm.fs = 1; + dma_tx_desc->tdes0_bm.dc = config->disable_crc; + dma_tx_desc->tdes0_bm.dp = config->disable_pad; + dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; + dma_tx_desc->tdes0_bm.cic = config->cic; + dma_tx_desc->tdes0_bm.vlic = config->vlic; + dma_tx_desc->tdes1_bm.saic = config->saic; + } + + /* set the buffer 1 size */ + dma_tx_desc->tdes1_bm.tbs1 = (tx_buff_size & ENET_DMATxDesc_TBS1); + + if (i == (buf_count - 1)) { + /* set the last segment bit */ + dma_tx_desc->tdes0_bm.ls = 1; + dma_tx_desc->tdes0_bm.ic = config->enable_ioc; + size = frame_length - (buf_count - 1) * tx_buff_size; + dma_tx_desc->tdes1_bm.tbs1 = (size & ENET_DMATxDesc_TBS1); + + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + } + + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + } + } + + tx_desc_list_cur = dma_tx_desc; + *parent_tx_desc_list_cur = tx_desc_list_cur; + + return ENET_SUCCESS; +} + uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size) { uint32_t buf_count = 0, size = 0, i = 0; @@ -348,11 +612,13 @@ uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t ** if (buf_count == 1) { /*set the last and the first segment */ dma_tx_desc->tdes0_bm.own = 0; + dma_tx_desc->tdes0_bm.ic = 0; dma_tx_desc->tdes0_bm.fs = 1; dma_tx_desc->tdes0_bm.ls = 1; dma_tx_desc->tdes0_bm.dc = 1; dma_tx_desc->tdes0_bm.dp = 0; - dma_tx_desc->tdes0_bm.crcr = 0; + dma_tx_desc->tdes0_bm.crcr = 1; + dma_tx_desc->tdes0_bm.cic = 3; dma_tx_desc->tdes1_bm.saic = 2; /* set the frame size */ @@ -465,12 +731,6 @@ void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc) ptr->DMA_RX_DESC_LIST_ADDR = (uint32_t)desc->rx_desc_list_head; } -void enet_mask_interrupt_event(ENET_Type *ptr, uint32_t mask) -{ - /* mask the specified interrupts */ - ptr->INTR_MASK |= mask; -} - void enet_timestamp_enable(ENET_Type *ptr, bool enable) { /* enable the timestamp */ @@ -484,7 +744,7 @@ void enet_set_subsecond_increment(ENET_Type *ptr, uint8_t ssinc) ptr->SUB_SEC_INCR |= ENET_SUB_SEC_INCR_SSINC_SET(ssinc); } -void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp) +void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_update_t *timestamp) { ptr->SYST_SEC_UPD = timestamp->sec; ptr->SYST_NSEC_UPD = timestamp->nsec; @@ -495,17 +755,17 @@ void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp) } } -void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp) +void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_system_t *timestamp) { timestamp->sec = ptr->SYST_SEC; timestamp->nsec = ptr->SYST_NSEC; } -void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_time_t *timeoffset) +void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_ts_update_t *timeoffset) { /* write the offset (positive or negative ) in the timestamp update high and low registers */ ptr->SYST_SEC_UPD = ENET_SYST_SEC_UPD_TSS_SET(timeoffset->sec); - ptr->SYST_NSEC_UPD = ENET_SYST_NSEC_UPD_ADDSUB_SET(timeoffset->sign) | ENET_SYST_NSEC_UPD_TSSS_SET(timeoffset->nsec / ptr->SUB_SEC_INCR); + ptr->SYST_NSEC_UPD = ENET_SYST_NSEC_UPD_ADDSUB_SET(timeoffset->sign) | ENET_SYST_NSEC_UPD_TSSS_SET(timeoffset->nsec); /* update the timestamp */ ptr->TS_CTRL |= ENET_TS_CTRL_TSUPDT_MASK; @@ -518,7 +778,7 @@ void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_time_t *timeoffset) void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj) { - ptr->TS_ADDEND = (uint32_t)((int64_t)adj * ENET_ADJ_FREQ_BASE_ADDEND / (ENET_ONE_SEC_IN_NANOSEC - adj) + ENET_ADJ_FREQ_BASE_ADDEND);; + ptr->TS_ADDEND = (uint32_t)((int64_t)adj * ENET_ADJ_FREQ_BASE_ADDEND / (ENET_ONE_SEC_IN_NANOSEC - adj) + ENET_ADJ_FREQ_BASE_ADDEND); ptr->TS_CTRL |= ENET_TS_CTRL_TSADDREG_MASK; @@ -527,11 +787,6 @@ void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj) } } -void enet_eanble_timestamp(ENET_Type *ptr) -{ - ptr->TS_CTRL |= ENET_TS_CTRL_TSENA_MASK; -} - void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver) { ptr->TS_CTRL &= ~ENET_TS_CTRL_TSVER2ENA_MASK; @@ -573,7 +828,7 @@ void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config) /* select the resolution of nanosecond */ ptr->TS_CTRL &= ~ENET_TS_CTRL_TSCTRLSSR_MASK; - ptr->TS_CTRL |= ENET_TS_CTRL_TSCTRLSSR_SET(config->sub_sec_count_res); + ptr->TS_CTRL |= ENET_TS_CTRL_TSCTRLSSR_SET(config->timestamp_rollover_mode); /* enable timestamping */ ptr->TS_CTRL |= ENET_TS_CTRL_TSENALL_MASK | ENET_TS_CTRL_TSENA_MASK; @@ -601,3 +856,72 @@ void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config) ptr->TS_CTRL &= ~ENET_TS_CTRL_TSCFUPDT_MASK; } } + +void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq) +{ + ptr->PPS_CTRL &= ~ENET_PPS_CTRL_PPSEN0_MASK; + ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSCTRLCMD0_SET(freq); +} + +hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx) +{ + if (idx >= ENET_SOC_PPS_MAX_COUNT) { + return status_invalid_argument; + } + + /* Wait the last command to complete */ + while (ptr->PPS_CTRL & (ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC))) { + + } + + /* Set the specified pps output with a specified command */ + ptr->PPS_CTRL |= cmd << ((idx + 1) << ENET_PPS_CMD_OFS_FAC); + + return status_success; +} + +hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx) +{ + if (idx >= ENET_SOC_PPS_MAX_COUNT) { + return status_invalid_argument; + } + + /* Set the interval and width for PPSx */ + if (idx == enet_pps_0) { + ptr->PPS0_INTERVAL = cmd_cfg->pps_interval - 1; + ptr->PPS0_WIDTH = cmd_cfg->pps_width - 1; + } else { + ptr->PPS[idx].INTERVAL = cmd_cfg->pps_interval - 1; + ptr->PPS[idx].WIDTH = cmd_cfg->pps_width - 1; + } + + /* Set the target timestamp */ + if (idx == enet_pps_0) { + ptr->TGTTM_SEC = cmd_cfg->target_sec; + ptr->TGTTM_NSEC = cmd_cfg->target_nsec; + } else { + ptr->PPS[idx].TGTTM_SEC = cmd_cfg->target_sec; + ptr->PPS[idx].TGTTM_NSEC = cmd_cfg->target_nsec; + } + + /* Set PPS0 as the command function */ + if (idx == enet_pps_0) { + ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSEN0_MASK; + } + +#if ENET_SOC_PPS1_EN + if (idx == enet_pps_1) { + ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSEN1_MASK; + } +#endif + + /* Wait the last command to complete */ + while (ptr->PPS_CTRL & (ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC))) { + + } + + /* Initialize with the No Command */ + ptr->PPS_CTRL &= ~(ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC)); + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c new file mode 100644 index 0000000000..888f39ee4d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_femc_drv.h" + +#ifndef HPM_FEMC_DRV_DEFAULT_PRESCALER +#define HPM_FEMC_DRV_DEFAULT_PRESCALER (0x3UL) +#endif + +#ifndef HPM_FEMC_DRV_RETRY_COUNT +#define HPM_FEMC_DRV_RETRY_COUNT (5000U) +#endif + +#define FEMC_PRESCALER_MAX (256UL) + +static void femc_config_delay_cell(FEMC_Type *ptr, uint32_t delay_cell_value) +{ + ptr->DLYCFG &= ~FEMC_DLYCFG_OE_MASK; + ptr->DLYCFG = FEMC_DLYCFG_DLYSEL_SET(delay_cell_value) | FEMC_DLYCFG_DLYEN_MASK; + ptr->DLYCFG |= FEMC_DLYCFG_OE_MASK; +} + +static hpm_stat_t femc_ip_cmd_done(FEMC_Type *ptr) +{ + uint32_t intr_status = 0; + uint32_t retry = 0; + do { + if (retry > HPM_FEMC_DRV_RETRY_COUNT) { + break; + } + retry++; + intr_status = ptr->INTR + & (uint32_t)(FEMC_INTR_IPCMDDONE_MASK | FEMC_INTR_IPCMDERR_MASK); + } while (intr_status == 0); + + if (retry > HPM_FEMC_DRV_RETRY_COUNT) { + return status_timeout; + } + + ptr->INTR |= FEMC_INTR_IPCMDDONE_MASK | FEMC_INTR_IPCMDERR_MASK; + if (intr_status & FEMC_INTR_IPCMDERR_MASK) { + return status_femc_cmd_err; + } + return status_success; +} + +static uint32_t femc_make_cmd(uint32_t opcode) +{ + return (opcode & ~FEMC_CMD_WRITE_FLAG) | FEMC_CMD_KEY; +} + +static bool femc_is_write_cmd(uint32_t opcode) +{ + return ((opcode & FEMC_CMD_WRITE_FLAG) == FEMC_CMD_WRITE_FLAG); +} + +uint32_t femc_issue_ip_cmd(FEMC_Type *ptr, uint32_t base_address, femc_cmd_t *cmd) +{ + bool read_data = !femc_is_write_cmd(cmd->opcode); + ptr->SADDR = base_address; + if (!read_data) { + ptr->IPTX = cmd->data; + } + ptr->IPCMD = femc_make_cmd(cmd->opcode); + + if (femc_ip_cmd_done(ptr) < 0) { + return status_femc_cmd_err; + } + + if (read_data) { + cmd->data = ptr->IPRX; + } + return status_success; +} + +void femc_default_config(FEMC_Type *ptr, femc_config_t *config) +{ + femc_axi_q_weight_t *q; + config->dqs = FEMC_DQS_FROM_PAD; + config->cmd_timeout = 0; + config->bus_timeout = 0x10; + q = &config->axi_q_weight[FEMC_AXI_Q_A]; + q->enable = true; + q->qos = 4; + q->age = 2; + q->slave_hit = 0x5; + q->slave_hit_wo_rw = 0x3; + + q = &config->axi_q_weight[FEMC_AXI_Q_B]; + q->enable = true; + q->qos = 4; + q->age = 2; + q->page_hit = 0x5; + q->slave_hit_wo_rw = 0x3; + q->bank_rotation = 0x6; +} + +void femc_get_typical_sdram_config(FEMC_Type *ptr, femc_sdram_config_t *config) +{ + config->col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + config->cas_latency = FEMC_SDRAM_CAS_LATENCY_3; + config->bank_num = FEMC_SDRAM_BANK_NUM_4; + config->prescaler = HPM_FEMC_DRV_DEFAULT_PRESCALER; + config->burst_len_in_byte = 8; + config->auto_refresh_count_in_one_burst = 1; + config->precharge_to_act_in_ns = 20; + config->act_to_rw_in_ns = 20; + config->refresh_recover_in_ns = 70; + config->write_recover_in_ns = 12; + config->cke_off_in_ns = 42; + config->act_to_precharge_in_ns = 42; + + config->self_refresh_recover_in_ns = 70; + config->refresh_to_refresh_in_ns = 60; + config->act_to_act_in_ns = 12; + config->idle_timeout_in_ns = 6; + config->cs_mux_pin = FEMC_IO_MUX_NOT_USED; +} + +void femc_init(FEMC_Type *ptr, femc_config_t *config) +{ + uint32_t i; + femc_axi_q_weight_t *q; + for (i = 0; i < FEMC_BR_COUNT; i++) { + ptr->BR[i] = 0; + } + + femc_sw_reset(ptr); + femc_disable(ptr); + ptr->CTRL |= FEMC_CTRL_BTO_SET(config->bus_timeout) + | FEMC_CTRL_CTO_SET(config->cmd_timeout) + | FEMC_CTRL_DQS_SET(config->dqs); + + q = &config->axi_q_weight[FEMC_AXI_Q_A]; + if (q->enable) { + ptr->BMW0 = FEMC_BMW0_QOS_SET(q->qos) + | FEMC_BMW0_AGE_SET(q->age) + | FEMC_BMW0_SH_SET(q->slave_hit) + | FEMC_BMW0_RWS_SET(q->slave_hit_wo_rw); + } else { + ptr->BMW0 = 0; + } + + q = &config->axi_q_weight[FEMC_AXI_Q_B]; + if (q->enable) { + ptr->BMW1 = FEMC_BMW1_QOS_SET(q->qos) + | FEMC_BMW1_AGE_SET(q->age) + | FEMC_BMW1_PH_SET(q->page_hit) + | FEMC_BMW1_BR_SET(q->bank_rotation) + | FEMC_BMW1_RWS_SET(q->slave_hit_wo_rw); + } else { + ptr->BMW1 = 0; + } + + femc_enable(ptr); +} + +static uint8_t femc_convert_actual_size_to_memory_size(uint32_t size_in_kb) +{ + uint8_t size = 0; + if (size_in_kb == 4) { + return 0; + } + + if (size_in_kb > 2 * 1 << 20) { + return 0x1F; + } + + size = 1; + size_in_kb >>= 3; + while (size_in_kb > 1) { + size_in_kb >>= 1; + size++; + } + return size; +} + +static uint8_t femc_convert_burst_len(uint8_t burst_len_in_byte) +{ + if ((burst_len_in_byte == 0) + || (burst_len_in_byte > FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE)) { + return FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; + } + + switch (burst_len_in_byte) { + case 1: + case 2: + case 4: + return burst_len_in_byte >> 1; + case 8: + return (burst_len_in_byte - 1) >> 1; + default: + return FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; + } +} + +static uint32_t ns2cycle(uint32_t freq_in_hz, uint32_t ns) +{ + uint32_t ns_per_cycle; + ns_per_cycle = 1000000000 / freq_in_hz; + return (ns / ns_per_cycle); +} + +hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_config_t *config) +{ + hpm_stat_t err; + uint32_t prescaler; + uint32_t refresh_cycle; + uint32_t clk_in_khz = clk_in_hz / 1000; + femc_cmd_t cmd = {0}; + uint8_t size = femc_convert_actual_size_to_memory_size(config->size_in_byte >> 10); + uint8_t burst_len = femc_convert_burst_len(config->burst_len_in_byte); + + prescaler = ((config->prescaler == 0) ? FEMC_PRESCALER_MAX : config->prescaler); + refresh_cycle = clk_in_khz * config->refresh_in_ms / config->refresh_count / (prescaler << 4); + + if ((prescaler == 0) || (prescaler > FEMC_PRESCALER_MAX) + || (refresh_cycle == 0) || (refresh_cycle > FEMC_PRESCALER_MAX)) { + return status_invalid_argument; + } + + if (prescaler == FEMC_PRESCALER_MAX) { + prescaler = 0; + } + + if (refresh_cycle == FEMC_PRESCALER_MAX) { + refresh_cycle = 0; + } + + ptr->BR[config->cs] = FEMC_BR_BASE_SET(config->base_address >> FEMC_BR_BASE_SHIFT) + | FEMC_BR_SIZE_SET(size) | FEMC_BR_VLD_MASK; + + ptr->SDRCTRL0 = FEMC_SDRCTRL0_PORTSZ_SET(config->port_size) + | FEMC_SDRCTRL0_BURSTLEN_SET(burst_len) + | FEMC_SDRCTRL0_COL_SET(config->col_addr_bits) + | FEMC_SDRCTRL0_COL8_SET(config->col_addr_bits == FEMC_SDRAM_COLUMN_ADDR_8_BITS) + | FEMC_SDRCTRL0_CAS_SET(config->cas_latency) + | FEMC_SDRCTRL0_BANK2_SET(config->bank_num); + + ptr->SDRCTRL1 = FEMC_SDRCTRL1_PRE2ACT_SET(ns2cycle(clk_in_hz, config->precharge_to_act_in_ns)) + | FEMC_SDRCTRL1_ACT2RW_SET(ns2cycle(clk_in_hz, config->act_to_rw_in_ns)) + | FEMC_SDRCTRL1_RFRC_SET(ns2cycle(clk_in_hz, config->refresh_recover_in_ns)) + | FEMC_SDRCTRL1_WRC_SET(ns2cycle(clk_in_hz, config->write_recover_in_ns)) + | FEMC_SDRCTRL1_CKEOFF_SET(ns2cycle(clk_in_hz, config->cke_off_in_ns)) + | FEMC_SDRCTRL1_ACT2PRE_SET(ns2cycle(clk_in_hz, config->act_to_precharge_in_ns)); + + ptr->SDRCTRL2 = FEMC_SDRCTRL2_SRRC_SET(ns2cycle(clk_in_hz, config->self_refresh_recover_in_ns)) + | FEMC_SDRCTRL2_REF2REF_SET(ns2cycle(clk_in_hz, config->refresh_to_refresh_in_ns)) + | FEMC_SDRCTRL2_ACT2ACT_SET(ns2cycle(clk_in_hz, config->act_to_act_in_ns)) + | FEMC_SDRCTRL2_ITO_SET(ns2cycle(clk_in_hz, config->idle_timeout_in_ns)); + + ptr->SDRCTRL3 = FEMC_SDRCTRL3_PRESCALE_SET(prescaler) + | FEMC_SDRCTRL3_RT_SET(refresh_cycle) + | FEMC_SDRCTRL3_UT_SET(refresh_cycle) + | FEMC_SDRCTRL3_REBL_SET(config->auto_refresh_count_in_one_burst - 1); + /* + * + * DATSZ[2:0]: Data size in byte + * 0b - 4 + * 1b - 1 + * 2b - 2 + * 3b - 3 + * > 3b - 4 + */ + ptr->DATSZ = FEMC_DATSZ_DATSZ_SET((config->data_width_in_byte & (0x3UL))); + ptr->BYTEMSK = 0; + + cmd.opcode = FEMC_CMD_SDRAM_PRECHARGE_ALL; + cmd.data = 0; + err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + cmd.opcode = FEMC_CMD_SDRAM_AUTO_REFRESH; + err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + /* + * + * DATSZ[2:0]: Data size in byte + * 0b - 4 + * 1b - 1 + * 2b - 2 + * 3b - 3 + * > 3b - 4 + */ + ptr->DATSZ = FEMC_DATSZ_DATSZ_SET((config->data_width_in_byte & (0x3UL))); + ptr->BYTEMSK = 0; + + /* + * config delay cell + */ + femc_config_delay_cell(ptr, config->delay_cell_value); + + cmd.opcode = FEMC_CMD_SDRAM_PRECHARGE_ALL; + cmd.data = 0; + err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + cmd.opcode = FEMC_CMD_SDRAM_AUTO_REFRESH; + err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + cmd.opcode = FEMC_CMD_SDRAM_MODE_SET; + /* FIXME: the mode register layout definition better to be passed in? */ + cmd.data = (uint32_t)(burst_len | config->cas_latency << 4); + err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + ptr->SDRCTRL3 |= FEMC_SDRCTRL3_REN_MASK; + + return status_success; +} + +void femc_get_typical_sram_config(FEMC_Type *ptr, femc_sram_config_t *config) +{ + config->base_address = 0x48000000; + config->size_in_byte = 4096; + config->address_mode = FEMC_SRAM_AD_NONMUX_MODE; + config->port_size = FEMC_SRAM_PORT_SIZE_8_BITS; + config->adv_hold_state = FEMC_SRAM_ADV_HOLD_LOW; + config->adv_polarity = FEMC_SRAM_ADV_ACTIVE_HIGH; + config->oeh_in_ns = 0; + config->oel_in_ns = 50; + config->weh_in_ns = 0; + config->wel_in_ns = 50; + config->ah_in_ns = 50; + config->as_in_ns = 0; + config->ceh_in_ns = 0; + config->ces_in_ns = 0; +} + +hpm_stat_t femc_config_sram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sram_config_t *config) +{ + uint8_t size = femc_convert_actual_size_to_memory_size(config->size_in_byte >> 10); + + ptr->IOCTRL = FEMC_IOCTRL_IO_CSX_SET(FEMC_IO_CSX_SRAM_CE); + + ptr->BR[FEMC_BR_BASE6] = FEMC_BR_BASE_SET(config->base_address >> FEMC_BR_BASE_SHIFT) + | FEMC_BR_SIZE_SET(size) + | FEMC_BR_VLD_MASK; + + ptr->SRCTRL0 = FEMC_SRCTRL0_ADVH_SET(config->adv_hold_state) + | FEMC_SRCTRL0_ADVP_SET(config->adv_polarity) + | FEMC_SRCTRL0_ADM_SET(config->address_mode) + | FEMC_SRCTRL0_PORTSZ_SET(config->port_size); + + ptr->SRCTRL1 = FEMC_SRCTRL1_OEH_SET(ns2cycle(clk_in_hz, config->oeh_in_ns)) + | FEMC_SRCTRL1_OEL_SET(ns2cycle(clk_in_hz, config->oel_in_ns)) + | FEMC_SRCTRL1_WEH_SET(ns2cycle(clk_in_hz, config->weh_in_ns)) + | FEMC_SRCTRL1_WEL_SET(ns2cycle(clk_in_hz, config->wel_in_ns)) + | FEMC_SRCTRL1_AH_SET(ns2cycle(clk_in_hz, config->ah_in_ns)) + | FEMC_SRCTRL1_AS_SET(ns2cycle(clk_in_hz, config->as_in_ns)) + | FEMC_SRCTRL1_CEH_SET(ns2cycle(clk_in_hz, config->ceh_in_ns)) + | FEMC_SRCTRL1_CES_SET(ns2cycle(clk_in_hz, config->ces_in_ns)); + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c index 8be0349a1f..25f8a7c774 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c index 822f2acb49..521a86d20f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -31,27 +31,27 @@ void gpio_toggle_pin_interrupt_trigger_type(GPIO_Type *ptr, uint32_t gpio_index, void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_index, gpio_interrupt_trigger_t trigger) { - switch(trigger) { - case gpio_interrupt_trigger_level_high: - case gpio_interrupt_trigger_level_low: - ptr->TP[gpio_index].CLEAR = 1 << pin_index; - if (trigger == gpio_interrupt_trigger_level_high) { - ptr->PL[gpio_index].CLEAR = 1 << pin_index; - } else { - ptr->PL[gpio_index].SET = 1 << pin_index; - } - break; - case gpio_interrupt_trigger_edge_falling: - case gpio_interrupt_trigger_edge_rising: - ptr->TP[gpio_index].SET = 1 << pin_index; - if (trigger == gpio_interrupt_trigger_edge_rising) { - ptr->PL[gpio_index].CLEAR = 1 << pin_index; - } else { - ptr->PL[gpio_index].SET = 1 << pin_index; - } - break; - default: - return; + switch (trigger) { + case gpio_interrupt_trigger_level_high: + case gpio_interrupt_trigger_level_low: + ptr->TP[gpio_index].CLEAR = 1 << pin_index; + if (trigger == gpio_interrupt_trigger_level_high) { + ptr->PL[gpio_index].CLEAR = 1 << pin_index; + } else { + ptr->PL[gpio_index].SET = 1 << pin_index; + } + break; + case gpio_interrupt_trigger_edge_falling: + case gpio_interrupt_trigger_edge_rising: + ptr->TP[gpio_index].SET = 1 << pin_index; + if (trigger == gpio_interrupt_trigger_edge_rising) { + ptr->PL[gpio_index].CLEAR = 1 << pin_index; + } else { + ptr->PL[gpio_index].SET = 1 << pin_index; + } + break; + default: + return; } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c index 4f8d62be6c..d24205d03a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,7 +12,7 @@ void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *c config->mode = gptmr_work_mode_no_capture; config->dma_request_event = gptmr_dma_request_disabled; config->synci_edge = gptmr_synci_edge_none; - for(uint8_t i = 0; i < GPTMR_CH_CMP_COUNT; i++) { + for (uint8_t i = 0; i < GPTMR_CH_CMP_COUNT; i++) { config->cmp[i] = 0; } config->reload = 0xFFFFFFFFUL; @@ -29,6 +29,8 @@ hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, bool enable) { uint32_t v = 0; + uint32_t tmp_value; + if (config->enable_sync_follow_previous_channel && !ch_index) { return status_invalid_argument; } @@ -46,10 +48,18 @@ hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, | GPTMR_CHANNEL_CR_CEN_SET(enable) | config->synci_edge; - for (uint8_t i = 0; i < GPTMR_CH_CMP_COUNT; i++) { - ptr->CHANNEL[ch_index].CMP[i] = GPTMR_CMP_CMP_SET(config->cmp[i]); + for (uint8_t i = GPTMR_CH_CMP_COUNT; i > 0; i--) { + tmp_value = config->cmp[i - 1]; + if (tmp_value > 0) { + tmp_value--; + } + ptr->CHANNEL[ch_index].CMP[i - 1] = GPTMR_CHANNEL_CMP_CMP_SET(tmp_value); } - ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(config->reload); + tmp_value = config->reload; + if (tmp_value > 0) { + tmp_value--; + } + ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(tmp_value); ptr->CHANNEL[ch_index].CR = v; return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c index ddb1a8cc59..66370dcd64 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,15 +11,11 @@ #define HPM_I2C_DRV_DEFAULT_TPM (0U) #endif -#ifndef HPM_I2C_DRV_DEFAULT_SCL_RATIO -#define HPM_I2C_DRV_DEFAULT_SCL_RATIO (1U) -#endif - #ifndef HPM_I2C_DRV_DEFAULT_RETRY_COUNT #define HPM_I2C_DRV_DEFAULT_RETRY_COUNT (5000U) #endif -#define period_in_ns(freq) (1000000000UL / (freq)) +#define period_in_100ps(freq) (10000000000UL / (freq)) typedef struct { uint32_t t_high; @@ -27,8 +23,7 @@ typedef struct { uint16_t t_sp; uint16_t t_sudat; uint16_t t_hddat; - uint16_t t_sclhi_min1; - uint16_t t_sclhi_min2; + uint16_t t_sclhi; uint16_t t_sclratio; } i2c_timing_t; @@ -36,28 +31,45 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, i2c_mode_t i2c_mode, i2c_timing_t *timing) { + int32_t setup_time, hold_time, period; + int32_t temp1, temp2, temp3; + int32_t tpclk = period_in_100ps(src_clk_in_hz); + switch (i2c_mode) { - /* - * |Standard mode | Fast mode | Fast mode plus | Uint - * ---------+--------------+-----------+----------------+------- - * t_high | 4.0 | 0.6 | 0.26 | us - * t_low | 4.7 | 1.3 | 0.5 | us - * - */ - case i2c_mode_fast: - timing->t_high = 600; - timing->t_low = 1300; - break; - case i2c_mode_fast_plus: - timing->t_high = 260; - timing->t_low = 500; - break; - case i2c_mode_normal: - timing->t_high = 4000; - timing->t_low = 4700; - break; - default: - return status_i2c_not_supported; + /* + * |Standard mode | Fast mode | Fast mode plus | Uint + * ---------+--------------+-----------+----------------+------- + * t_high | 4.0 | 0.6 | 0.26 | us + * t_low | 4.7 | 1.3 | 0.5 | us + * + */ + /* time uint: 100ps */ + case i2c_mode_fast: + timing->t_high = 6000; + timing->t_low = 13000; + timing->t_sclratio = 2; + setup_time = 1000; + hold_time = 3000; + period = period_in_100ps(400000); /**< baudrate 400KHz */ + break; + case i2c_mode_fast_plus: + timing->t_high = 2600; + timing->t_low = 5000; + timing->t_sclratio = 2; + setup_time = 500; + hold_time = 0; + period = period_in_100ps(1000000); /**< baudrate 1MHz */ + break; + case i2c_mode_normal: + timing->t_high = 40000; + timing->t_low = 47000; + timing->t_sclratio = 1; + setup_time = 2500; + hold_time = 3000; + period = period_in_100ps(100000); /**< baudrate 100KHz */ + break; + default: + return status_i2c_not_supported; } /* @@ -66,9 +78,9 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, * ------------------+----------+-----------+----------------+------- * t_sp (min) | - | 0 - 50 | 0 - 50 | ns * - * T_SP = 50ns / (25ns * (TPM + 1)) + * T_SP = 50ns / (tpclk * (TPM + 1)) */ - timing->t_sp = 50 / period_in_ns(src_clk_in_hz) / (HPM_I2C_DRV_DEFAULT_TPM + 1); + timing->t_sp = 500 / period_in_100ps(src_clk_in_hz) / (HPM_I2C_DRV_DEFAULT_TPM + 1); /* * Setup time |Standard mode | Fast mode | Fast mode plus | Uint @@ -77,8 +89,8 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, * * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk * (TPM + 1) */ - timing->t_sudat = (250 - 2 * period_in_ns(src_clk_in_hz)) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; - + temp1 = (setup_time - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; + timing->t_sudat = MAX(temp1, 0); /* * Hold time |Standard mode | Fast mode | Fast mode plus | Uint * ----------------+--------------+-----------+----------------+------- @@ -86,20 +98,29 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, * * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk * (TPM + 1) */ - timing->t_hddat = (300 - 2 * period_in_ns(src_clk_in_hz)) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; + temp1 = (hold_time - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; + timing->t_hddat = MAX(temp1, 0); /* * SCLK High period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk * (TPM + 1) > t_high; */ - timing->t_sclhi_min1 = (timing->t_high - 2 * period_in_ns(src_clk_in_hz)) - / (HPM_I2C_DRV_DEFAULT_TPM + 1) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; + temp1 = (timing->t_high - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; + + /* + * SCLK High period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk * (TPM + 1) > period / (1 + ratio); + */ + temp2 = (period / (1 + timing->t_sclratio) - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; /* * SCLK Low period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM + 1) > t_low; */ - timing->t_sclhi_min2 = ((timing->t_low - 2 * period_in_ns(src_clk_in_hz)) - / (HPM_I2C_DRV_DEFAULT_TPM + 1) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp) - / (timing->t_sclratio); + temp3 = ((timing->t_low - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp) / (timing->t_sclratio); + + timing->t_sclhi = MAX(MAX(temp1, temp2), temp3); + + /* update high_period and low_period to calculated value */ + timing->t_high = 2 * tpclk + (2 + timing->t_sp + timing->t_sclhi) * tpclk; + timing->t_low = timing->t_high * timing->t_sclratio; return status_success; } @@ -118,7 +139,6 @@ hpm_stat_t i2c_init_master(I2C_Type *ptr, uint32_t src_clk_in_hz, i2c_config_t * i2c_reset(ptr); - timing.t_sclratio = HPM_I2C_DRV_DEFAULT_SCL_RATIO; stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); if (status_success != stat) { return stat; @@ -130,7 +150,7 @@ hpm_stat_t i2c_init_master(I2C_Type *ptr, uint32_t src_clk_in_hz, i2c_config_t * | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) - | I2C_SETUP_T_SCLHI_SET(MAX(timing.t_sclhi_min1, timing.t_sclhi_min2)) + | I2C_SETUP_T_SCLHI_SET(timing.t_sclhi) | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) | I2C_SETUP_IICEN_MASK | I2C_SETUP_MASTER_MASK; @@ -139,22 +159,36 @@ hpm_stat_t i2c_init_master(I2C_Type *ptr, uint32_t src_clk_in_hz, i2c_config_t * } hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, - uint8_t *addr, uint8_t addr_size_in_byte, + uint8_t *addr, uint32_t addr_size_in_byte, uint8_t *buf, const uint32_t size_in_byte) { hpm_stat_t stat = status_success; uint32_t left; uint32_t retry; - ptr->CMD = I2C_CMD_RESET; + assert(addr_size_in_byte > 0 && addr_size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) - | I2C_CTRL_DATACNT_SET(addr_size_in_byte); + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(addr_size_in_byte)); ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); @@ -175,6 +209,8 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->CTRL = I2C_CTRL_PHASE_START_MASK @@ -182,7 +218,7 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) - | I2C_CTRL_DATACNT_SET(size_in_byte); + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte)); ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; @@ -214,19 +250,34 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK; return stat; } hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address, - uint8_t *addr, uint8_t addr_size_in_byte, + uint8_t *addr, uint32_t addr_size_in_byte, uint8_t *buf, const uint32_t size_in_byte) { hpm_stat_t stat = status_success; uint32_t left; uint32_t retry; - ptr->CMD = I2C_CMD_RESET; + assert(addr_size_in_byte > 0 && addr_size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + assert(addr_size_in_byte + size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); @@ -235,7 +286,7 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) - | I2C_CTRL_DATACNT_SET(size_in_byte + addr_size_in_byte); + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte + addr_size_in_byte)); left = addr_size_in_byte; while (left) { @@ -275,9 +326,6 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address return status_timeout; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK; - - ptr->CMD = I2C_CMD_RESET; return stat; } @@ -288,6 +336,22 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, uint32_t left; uint32_t retry; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); ptr->CTRL = I2C_CTRL_PHASE_START_MASK @@ -295,7 +359,7 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) - | I2C_CTRL_DATACNT_SET(size); + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; @@ -304,9 +368,6 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { *(buf++) = ptr->DATA; left--; - if (left) { - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - } retry = 0; } else { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -335,9 +396,6 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, return status_fail; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK; - - ptr->INTEN = 0; if (i2c_get_data_count(ptr)) { return status_i2c_transmit_not_completed; } @@ -352,6 +410,22 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, uint32_t retry; uint32_t left; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); ptr->CTRL = I2C_CTRL_PHASE_START_MASK @@ -359,7 +433,7 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) - | I2C_CTRL_DATACNT_SET(size); + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); retry = 0; left = size; @@ -390,14 +464,11 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK; - ptr->INTEN = 0; if (i2c_get_data_count(ptr)) { return status_i2c_transmit_not_completed; } - ptr->CMD = I2C_CMD_RESET; return stat; } @@ -411,7 +482,6 @@ hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, ptr->ADDR = I2C_ADDR_ADDR_SET(slave_address); - timing.t_sclratio = HPM_I2C_DRV_DEFAULT_SCL_RATIO; stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); if (status_success != stat) { return stat; @@ -423,7 +493,7 @@ hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) - | I2C_SETUP_T_SCLHI_SET(MAX(timing.t_sclhi_min1, timing.t_sclhi_min2)) + | I2C_SETUP_T_SCLHI_SET(timing.t_sclhi) | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) | I2C_SETUP_IICEN_MASK; @@ -436,6 +506,24 @@ hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) uint32_t retry; uint32_t left; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + /* wait for address hit */ + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_fail; + } + + /* W1C, clear CMPL bit and clear ADDRHIT bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; + retry = 0; left = size; while (left) { @@ -466,7 +554,7 @@ hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) return status_timeout; } /* clear status, CMPL must to be cleared at slave mode before next transaction */ - i2c_clear_status(ptr, ptr->STATUS); + ptr->STATUS = I2C_STATUS_CMPL_MASK; if (i2c_get_data_count(ptr) != size) { return status_i2c_transmit_not_completed; @@ -483,6 +571,24 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint32_t retry; uint32_t left; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + /* wait for address hit */ + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_fail; + } + + /* W1C, clear CMPL bit and clear ADDRHIT bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; + retry = 0; left = size; while (left) { @@ -513,7 +619,7 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, return status_timeout; } /* clear status, CMPL must to be cleared at slave mode before next transaction */ - i2c_clear_status(ptr, ptr->STATUS); + ptr->STATUS = I2C_STATUS_CMPL_MASK; if (i2c_get_data_count(ptr) != size) { return status_i2c_transmit_not_completed; @@ -522,39 +628,271 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, return status_success; } -void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) +hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { + uint32_t retry = 0; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK | I2C_CTRL_PHASE_STOP_MASK | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) - | I2C_CTRL_DATACNT_SET(size); + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + return status_success; } -void i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) +hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { + uint32_t retry = 0; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK | I2C_CTRL_PHASE_STOP_MASK | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) - | I2C_CTRL_DATACNT_SET(size); + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + return status_success; } -void i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) +hpm_stat_t i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) { - i2c_ptr->CTRL |= I2C_CTRL_DATACNT_SET(size); + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; + + i2c_ptr->CTRL |= I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; + + return status_success; } + +hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read) +{ + uint32_t retry = 0; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; + i2c_ptr->CMD = I2C_CMD_CLEAR_FIFO; + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(read) + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + + i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + return status_success; +} + +hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt) +{ + uint32_t ctrl; + uint32_t retry = 0; + uint32_t left = 0; + + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + + switch (opt) { + case i2c_frist_frame: + ctrl = I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(false) \ + | I2C_CTRL_PHASE_ADDR_SET(true); + break; + case i2c_next_frame: + ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(false) \ + | I2C_CTRL_PHASE_ADDR_SET(false); + break; + case i2c_last_frame: + ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(true) \ + | I2C_CTRL_PHASE_ADDR_SET(false); + break; + default: + return status_invalid_argument; + } + + ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) \ + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + /* enable auto ack */ + ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; + + retry = 0; + left = size; + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { + ptr->DATA = *(buf++); + left--; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* clear status, CMPL must to be cleared at slave mode before next transaction */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + return status_success; +} + +hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt) +{ + uint32_t ctrl; + uint32_t retry = 0; + uint32_t left = 0; + + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + + switch (opt) { + case i2c_frist_frame: + ctrl = I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(false) \ + | I2C_CTRL_PHASE_ADDR_SET(true); + break; + case i2c_next_frame: + ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(false) \ + | I2C_CTRL_PHASE_ADDR_SET(false); + break; + case i2c_last_frame: + ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(true) \ + | I2C_CTRL_PHASE_ADDR_SET(false); + break; + default: + return status_invalid_argument; + } + + ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) \ + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + + /* disable auto ack */ + ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + retry = 0; + left = size; + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { + *(buf++) = ptr->DATA; + left--; + if ((left == 0) && (opt == i2c_last_frame)) { + ptr->CMD = I2C_CMD_NACK; + } else { + ptr->CMD = I2C_CMD_ACK; + } + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + if (opt == i2c_last_frame) { + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + } + /* clear status, CMPL must to be cleared at slave mode before next transaction */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + /* default auto ack */ + ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; + + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c index 0d34d1bc92..3dfe9054c5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,30 @@ #include "hpm_i2s_drv.h" +#define HPM_I2S_DRV_DEFAULT_RETRY_COUNT 5000U + +#ifndef HPM_I2S_BCLK_TOLERANCE +#define HPM_I2S_BCLK_TOLERANCE (4U) +#endif + +static bool i2s_audio_depth_is_valid(uint8_t bits) +{ + /* i2s audio depth only support 16bits, 24bits, 32bits */ + if (bits == i2s_audio_depth_16_bits || bits == i2s_audio_depth_24_bits || bits == i2s_audio_depth_32_bits) { + return true; + } + return false; +} + +static bool i2s_channel_length_is_valid(uint8_t bits) +{ + /* i2s channel length only support 16bits or 32bits */ + if (bits == i2s_channel_length_16_bits || bits == i2s_channel_length_32_bits) { + return true; + } + return false; +} + void i2s_reset_all(I2S_Type *ptr) { /* gate off bclk */ @@ -70,9 +94,9 @@ void i2s_init(I2S_Type *ptr, i2s_config_t *config) * @brief i2s interrupt work_around * */ - for (uint32_t i = 0; i < I2S_DATA_LINE_MAX; i++) { + for (uint32_t i = 0; i <= I2S_DATA_LINE_MAX; i++) { ptr->TXDSLOT[i] = 0; - for (uint32_t j = 0; j < I2S_SOC_MAX_TX_CHANNEL_NUM; j++) { + for (uint32_t j = 0; j <= I2S_SOC_MAX_TX_CHANNEL_NUM; j++) { ptr->TXD[i] = 0x01; } } @@ -83,38 +107,67 @@ static void i2s_config_cfgr(I2S_Type *ptr, i2s_transfer_config_t *config) { i2s_gate_bclk(ptr); - ptr->CFGR = I2S_CFGR_BCLK_DIV_SET(bclk_div) - | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) - | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) - | I2S_CFGR_STD_SET(config->protocol) - | I2S_CFGR_DATSIZ_SET(config->audio_depth) - | I2S_CFGR_CHSIZ_SET(config->channel_length); + ptr->CFGR = (ptr->CFGR & ~(I2S_CFGR_BCLK_DIV_MASK | I2S_CFGR_TDM_EN_MASK | I2S_CFGR_CH_MAX_MASK | I2S_CFGR_STD_MASK | I2S_CFGR_DATSIZ_MASK | I2S_CFGR_CHSIZ_MASK)) + | I2S_CFGR_BCLK_DIV_SET(bclk_div) + | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) + | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) + | I2S_CFGR_STD_SET(config->protocol) + | I2S_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) + | I2S_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); i2s_ungate_bclk(ptr); } -hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +static void i2s_config_cfgr_slave(I2S_Type *ptr, + i2s_transfer_config_t *config) +{ + ptr->CFGR = (ptr->CFGR & ~(I2S_CFGR_TDM_EN_MASK | I2S_CFGR_CH_MAX_MASK | I2S_CFGR_STD_MASK | I2S_CFGR_DATSIZ_MASK | I2S_CFGR_CHSIZ_MASK)) + | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) + | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) + | I2S_CFGR_STD_SET(config->protocol) + | I2S_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) + | I2S_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); +} + +static bool i2s_calculate_bclk_divider(uint32_t mclk_in_hz, uint32_t bclk_in_hz, uint32_t *div_out) { - uint32_t bclk_freq_in_hz; uint32_t bclk_div; - if (I2S_AUDIO_DEPTH_IS_NOT_VALID(config->audio_depth) - || !config->sample_rate - || !config->channel_num_per_frame - || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || !(config->channel_slot_mask & ((1U << config->channel_num_per_frame) - 1U))) { - return status_invalid_argument; - } + uint32_t delta1, delta2; + + bclk_div = mclk_in_hz / bclk_in_hz; - bclk_freq_in_hz = config->sample_rate * ((config->channel_length << 4) + 16) * config->channel_num_per_frame; - bclk_div = mclk_in_hz / bclk_freq_in_hz; if ((bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { - return status_invalid_argument; - } - if ((bclk_div * bclk_freq_in_hz) < mclk_in_hz) { - bclk_div++; + return false; } - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); + delta1 = mclk_in_hz - bclk_in_hz * bclk_div; + delta2 = bclk_in_hz * (bclk_div + 1) - mclk_in_hz; + if (delta2 < delta1) { + bclk_div++; + if ((bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { + return false; + } + } + + if (MIN(delta1, delta2) && ((MIN(delta1, delta2) * 100 / bclk_in_hz) > HPM_I2S_BCLK_TOLERANCE)) { + return false; + } + + *div_out = bclk_div; + return true; +} + +static hpm_stat_t _i2s_config_tx(I2S_Type *ptr, i2s_transfer_config_t *config) +{ + /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ + if (!i2s_audio_depth_is_valid(config->audio_depth) + || !i2s_channel_length_is_valid(config->channel_length) + || !config->sample_rate + || !config->channel_num_per_frame + || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || (config->channel_num_per_frame & 1U) + || ((!config->enable_tdm_mode) && (config->channel_num_per_frame > 2))) { + return status_invalid_argument; + } if (config->channel_slot_mask) { ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; @@ -122,66 +175,46 @@ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_TX_EN_MASK)) | I2S_CTRL_TX_EN_SET(1 << config->data_line) | I2S_CTRL_I2S_EN_MASK; + return status_success; } -hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +static hpm_stat_t _i2s_config_rx(I2S_Type *ptr, i2s_transfer_config_t *config) { - uint32_t bclk_freq_in_hz; - uint32_t bclk_div; - if (I2S_AUDIO_DEPTH_IS_NOT_VALID(config->audio_depth) - || !config->sample_rate - || !config->channel_num_per_frame - || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || !(config->channel_slot_mask & ((1U << config->channel_num_per_frame) - 1U))) { + /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ + if (!i2s_audio_depth_is_valid(config->audio_depth) + || !i2s_channel_length_is_valid(config->channel_length) + || !config->sample_rate + || !config->channel_num_per_frame + || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || (config->channel_num_per_frame & 1U) + || ((!config->enable_tdm_mode) && (config->channel_num_per_frame > 2))) { return status_invalid_argument; } - bclk_freq_in_hz = config->sample_rate * ((config->channel_length << 4) + 16) * config->channel_num_per_frame; - bclk_div = mclk_in_hz / bclk_freq_in_hz; - if (!bclk_div || (bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { - return status_invalid_argument; - } - if ((bclk_div * bclk_freq_in_hz) < mclk_in_hz) { - bclk_div++; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - if (config->channel_slot_mask) { ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; } ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK)) | I2S_CTRL_RX_EN_SET(1 << config->data_line) | I2S_CTRL_I2S_EN_MASK; + return status_success; } -hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +static hpm_stat_t _i2s_config_transfer(I2S_Type *ptr, i2s_transfer_config_t *config) { - uint32_t bclk_freq_in_hz; - uint32_t bclk_div; - if (I2S_AUDIO_DEPTH_IS_NOT_VALID(config->audio_depth) - || !config->sample_rate - || !config->channel_num_per_frame - || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || !(config->channel_slot_mask & ((1U << config->channel_num_per_frame) - 1U))) { + /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ + if (!i2s_audio_depth_is_valid(config->audio_depth) + || !i2s_channel_length_is_valid(config->channel_length) + || !config->sample_rate + || !config->channel_num_per_frame + || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || (config->channel_num_per_frame & 1U) + || ((!config->enable_tdm_mode) && (config->channel_num_per_frame > 2))) { return status_invalid_argument; } - bclk_freq_in_hz = config->sample_rate * ((config->channel_length << 4) + 16) * config->channel_num_per_frame; - bclk_div = mclk_in_hz / bclk_freq_in_hz; - if (!bclk_div || (bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { - return status_invalid_argument; - } - if ((bclk_div * bclk_freq_in_hz) < mclk_in_hz) { - bclk_div++; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - if (config->channel_slot_mask) { /* Suppose RX and TX use same channel */ ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; @@ -197,33 +230,162 @@ hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_ | I2S_CTRL_RX_EN_SET(1 << config->data_line) | I2S_CTRL_TX_EN_SET(1 << config->data_line) | I2S_CTRL_I2S_EN_MASK; + return status_success; } -uint32_t i2s_send_data(I2S_Type *ptr, uint8_t tx_line_index, uint32_t *src, uint32_t size) +hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) { - register uint32_t count; - for (count = 0; count < size; count ++) { - ptr->TXD[tx_line_index] = *(src + count); + uint32_t bclk_in_hz; + uint32_t bclk_div; + + bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { + return status_invalid_argument; } - return count; + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + return _i2s_config_tx(ptr, config); } -uint32_t i2s_receive_data(I2S_Type *ptr, uint8_t rx_line_index, uint32_t *dst, uint32_t size) +hpm_stat_t i2s_config_tx_slave(I2S_Type *ptr, i2s_transfer_config_t *config) { - register uint32_t count; - for (count = 0; count < size; count++) { - *(dst + count) = ptr->RXD[rx_line_index]; + i2s_disable(ptr); + i2s_config_cfgr_slave(ptr, config); + + return _i2s_config_tx(ptr, config); +} + +hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_in_hz; + uint32_t bclk_div; + + bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { + return status_invalid_argument; } - return count; + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + return _i2s_config_rx(ptr, config); +} + +hpm_stat_t i2s_config_rx_slave(I2S_Type *ptr, i2s_transfer_config_t *config) +{ + i2s_disable(ptr); + i2s_config_cfgr_slave(ptr, config); + + return _i2s_config_rx(ptr, config); +} + +hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_in_hz; + uint32_t bclk_div; + + bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { + return status_invalid_argument; + } + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + return _i2s_config_transfer(ptr, config); +} + +hpm_stat_t i2s_config_transfer_slave(I2S_Type *ptr, i2s_transfer_config_t *config) +{ + i2s_disable(ptr); + i2s_config_cfgr_slave(ptr, config); + + return _i2s_config_transfer(ptr, config); +} + +uint32_t i2s_send_buff(I2S_Type *ptr, uint8_t tx_line_index, uint8_t samplebits, uint8_t *src, uint32_t size) +{ + uint32_t data; + uint32_t retry = 0; + uint8_t bytes = samplebits / 8U; + uint32_t left; + + if (!i2s_audio_depth_is_valid(samplebits)) { + return 0; + } + + if ((size % bytes) != 0) { + return 0; + } + + left = size; + while (left) { + /* check fifo status */ + if (i2s_get_tx_line_fifo_level(ptr, tx_line_index) < I2S_FIFO_THRESH_TX_GET(ptr->FIFO_THRESH)) { + /* Move valid data to high position */ + data = *((uint32_t *)(src)) << (32 - samplebits); + ptr->TXD[tx_line_index] = data; + src += bytes; + left -= bytes; + retry = 0; + } else { + if (retry > HPM_I2S_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + + return size - left; +} + +uint32_t i2s_receive_buff(I2S_Type *ptr, uint8_t rx_line_index, uint8_t samplebits, uint8_t *dst, uint32_t size) +{ + uint32_t data; + uint32_t left; + uint32_t retry = 0; + uint8_t bytes = samplebits / 8U; + + if (!i2s_audio_depth_is_valid(samplebits)) { + return 0; + } + + if ((size % bytes) != 0) { + return 0; + } + + left = size; + while (left) { + /* check fifo status */ + if (i2s_get_rx_line_fifo_level(ptr, rx_line_index) < I2S_FIFO_THRESH_RX_GET(ptr->FIFO_THRESH)) { + /* valid data on high position */ + data = ptr->RXD[rx_line_index] >> (32 - samplebits); + for (uint8_t n = 0; n < bytes; n++) { + *dst = (uint8_t)(data >> (8U * n)) & 0xFFU; + dst++; + left--; + retry = 0; + } + } else { + if (retry > HPM_I2S_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + + return size - left; } void i2s_get_default_transfer_config_for_pdm(i2s_transfer_config_t *transfer) { transfer->sample_rate = PDM_SOC_SAMPLE_RATE_IN_HZ; - transfer->channel_num_per_frame = 16; - transfer->channel_length = I2S_CHANNEL_LENGTH_32_BITS; - transfer->audio_depth = I2S_AUDIO_DEPTH_32_BITS; + transfer->channel_num_per_frame = 8; + transfer->channel_length = i2s_channel_length_32_bits; + transfer->audio_depth = i2s_audio_depth_32_bits; transfer->enable_tdm_mode = true; transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; } @@ -232,8 +394,8 @@ void i2s_get_default_transfer_config_for_dao(i2s_transfer_config_t *transfer) { transfer->sample_rate = DAO_SOC_SAMPLE_RATE_IN_HZ; transfer->channel_num_per_frame = 2; - transfer->channel_length = I2S_CHANNEL_LENGTH_32_BITS; - transfer->audio_depth = I2S_AUDIO_DEPTH_32_BITS; + transfer->channel_length = i2s_channel_length_32_bits; + transfer->audio_depth = i2s_audio_depth_32_bits; transfer->enable_tdm_mode = false; transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; transfer->data_line = I2S_DATA_LINE_0; @@ -244,8 +406,8 @@ void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer) { transfer->sample_rate = 48000U; transfer->channel_num_per_frame = 2; - transfer->channel_length = I2S_CHANNEL_LENGTH_32_BITS; - transfer->audio_depth = I2S_AUDIO_DEPTH_32_BITS; + transfer->channel_length = i2s_channel_length_32_bits; + transfer->audio_depth = i2s_audio_depth_32_bits; transfer->enable_tdm_mode = false; transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; transfer->data_line = I2S_DATA_LINE_0; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c index 03fb6ab440..c52ee65e8d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,8 @@ #include "hpm_jpeg_drv.h" +#define HPM_JPEG_DEFAULT_MAX_OT (2) + const jpeg_sampling_t jpeg_supported_sampling[5] = { {2, 2, 1, 1}, /* 420 */ {2, 1, 1, 1}, /* 422H */ @@ -15,6 +17,15 @@ const jpeg_sampling_t jpeg_supported_sampling[5] = { {1, 1, 0, 0}, /* 400 */ }; +const jpeg_pixel_t jpeg_supported_pixel_format[6] = { + {4, 1, 1, true}, /* JPEG_PIXEL_FORMAT_ARGB8888 */ + {2, 2, 2, true}, /* JPEG_PIXEL_FORMAT_RGB565 */ + {2, 3, 0, false}, /* JPEG_PIXEL_FORMAT_YUV422H1P */ + {1, 0, 0, false}, /* JPEG_PIXEL_FORMAT_YUV422H2P */ + {1, 0, 0, false}, /* JPEG_PIXEL_FORMAT_YUV420 */ + {1, 0, 0, false}, /* JPEG_PIXEL_FORMAT_Y8 */ +}; + void jpeg_disable_irq(JPEG_Type *ptr, uint32_t mask) { if (mask & JPEG_EVENT_IN_DMA_FINISH) { @@ -50,6 +61,7 @@ void jpeg_reset(JPEG_Type *ptr) jpeg_stop(ptr); jpeg_software_reset(ptr); ptr->STAT = 0xFFFFFFFFUL; + } void jpeg_init(JPEG_Type *ptr) @@ -58,9 +70,9 @@ void jpeg_init(JPEG_Type *ptr) jpeg_reset(ptr); } -static uint8_t jpeg_get_pixel_size(uint8_t pixel_format) +static bool jpeg_need_csc(jpeg_pixel_format_t in, jpeg_pixel_format_t out) { - return (pixel_format == JPEG_PIXEL_FORMAT_ARGB8888) ? 4 : 2; + return (jpeg_supported_pixel_format[in].is_rgb != jpeg_supported_pixel_format[out].is_rgb); } static bool jpeg_is_valid_size(uint8_t format, uint32_t width, uint32_t height) @@ -101,14 +113,14 @@ static void jpeg_config_interal_regs(JPEG_Type *ptr, hc = JPEG_HC(&jpeg_supported_sampling[format]); vc = JPEG_VC(&jpeg_supported_sampling[format]); - if (format == JPEG_SUPPORTED_FORMAT_400) { - ptr->IMGREG1 = JPEG_IMGREG1_RE_MASK; + if (format != JPEG_SUPPORTED_FORMAT_400) { + ptr->IMGREG1 = JPEG_IMGREG1_NCOL_SET(2); } else { - ptr->IMGREG1 = JPEG_IMGREG1_RE_MASK | JPEG_IMGREG1_NCOL_SET(2); + ptr->IMGREG1 = 8; } ptr->IMGREG2 = JPEG_IMGREG2_NMCU_SET(macro_block_count - 1); - ptr->IMGREG3 = JPEG_IMGREG3_NRST_SET(1); - ptr->IMGREG[0] = JPEG_IMGREG_NBLOCK_SET(hy * vy -1); + ptr->IMGREG3 = 0; + ptr->IMGREG[0] = JPEG_IMGREG_NBLOCK_SET(hy * vy - 1); if (format == JPEG_SUPPORTED_FORMAT_400) { ptr->IMGREG[1] = 0; ptr->IMGREG[2] = 0; @@ -136,6 +148,9 @@ hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) return status_invalid_argument; } + jpeg_disable(ptr); + jpeg_software_reset(ptr); + sampling = (jpeg_sampling_t *)&jpeg_supported_sampling[config->jpeg_format]; macro_block_count = jpeg_calculate_macro_block_count(config->width_in_pixel, config->height_in_pixel, sampling); macro_block_bytes = (JPEG_HY(sampling) * JPEG_VY(sampling) @@ -144,14 +159,15 @@ hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) /* input DMA setting */ ptr->INDMA_MISC = JPEG_INDMA_MISC_IN_DMA_ID_SET(0) - | JPEG_INDMA_MISC_PACK_DIR_SET(config->byte_order) - | JPEG_INDMA_MISC_MAX_OT_SET(4) + | JPEG_INDMA_MISC_MAX_OT_SET(HPM_JPEG_DEFAULT_MAX_OT) | JPEG_INDMA_MISC_INDMA2D_MASK - | JPEG_INDMA_MISC_IN_DMA_REQ_MASK ; - - ptr->INDMA_CTRL0 = JPEG_INDMA_CTRL0_TTLEN_SET(total_bytes) - | JPEG_INDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_get_pixel_size(config->in_pixel_format)); + | JPEG_INDMA_MISC_IN_DMA_REQ_MASK + | JPEG_INDMA_MISC_PACK_DIR_SET(config->in_byte_order); ptr->INDMABASE = JPEG_INDMABASE_ADDR_SET(config->in_buffer); + ptr->INDMA_CTRL0 = JPEG_INDMA_CTRL0_TTLEN_SET(total_bytes) + | JPEG_INDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_supported_pixel_format[config->in_pixel_format].pixel_width); + ptr->INDMA_CTRL1 = JPEG_INDMA_CTRL1_ROWLEN_SET(total_bytes >> 16); + ptr->INXT_CMD = JPEG_INXT_CMD_ADDR_SET(5) | JPEG_INXT_CMD_OP_VALID_MASK; /* output DMA setting */ @@ -159,10 +175,12 @@ hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) | JPEG_OUTDMA_MISC_INI_OUTCNT_MASK | JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(1) | JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK - | JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK; + | JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK + | JPEG_OUTDMA_MISC_PACK_DIR_SET(config->out_byte_order); ptr->OUTDMABASE = JPEG_OUTDMABASE_ADDR_SET(config->out_buffer); ptr->OUTDMA_CTRL0 = JPEG_OUTDMA_CTRL0_TTLEN_SET(total_bytes); - ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(2); + ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(total_bytes >> 16); + ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(5) | JPEG_ONXT_CMD_OP_VALID_MASK; jpeg_config_interal_regs(ptr, false, macro_block_count, config->jpeg_format); @@ -170,7 +188,7 @@ hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) ptr->WIDTH = config->width_in_pixel - 1; ptr->HEIGHT = config->height_in_pixel - 1; - if (config->enable_csc) { + if (jpeg_need_csc(config->in_pixel_format, config->out_pixel_format)) { if (config->enable_ycbcr) { ptr->RGB2YUV_COEF0 = JPEG_RGB2YUV_COEF0_C0_SET(0x42) | JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(0x80) @@ -189,7 +207,6 @@ hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) ptr->RGB2YUV_COEF0 = JPEG_RGB2YUV_COEF0_C0_SET(0x4D) | JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(0) | JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(0x0) - | JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK | JPEG_RGB2YUV_COEF0_ENABLE_MASK; ptr->RGB2YUV_COEF1 = JPEG_RGB2YUV_COEF1_C1_SET(0x96) | JPEG_RGB2YUV_COEF1_C4_SET(0x7B6); @@ -204,10 +221,13 @@ hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) ptr->RGB2YUV_COEF0 = 0x04030000; } - ptr->CFG = JPEG_CFG_CFG_IPATH_SEL_SET(config->in_pixel_format) + ptr->CFG = JPEG_CFG_CFG_IPATH_SEL_SET(jpeg_supported_pixel_format[config->in_pixel_format].ipath) + | JPEG_CFG_CFG_OPATH_SEL_SET(jpeg_supported_pixel_format[config->out_pixel_format].opath) + | JPEG_CFG_CLKGATE_MASK | JPEG_CFG_JDATA_FORMAT_SET(config->jpeg_format) | JPEG_CFG_JPEG_EN_MASK | JPEG_CFG_START_MASK; + return status_success; } @@ -225,6 +245,9 @@ hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, return status_invalid_argument; } + jpeg_disable(ptr); + jpeg_software_reset(ptr); + sampling = (jpeg_sampling_t *)&jpeg_supported_sampling[config->jpeg_format]; macro_block_count = jpeg_calculate_macro_block_count(config->width_in_pixel, config->height_in_pixel, sampling); macro_block_bytes = (JPEG_HY(sampling) * JPEG_VY(sampling) @@ -233,41 +256,44 @@ hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, /* input DMA setting */ ptr->INDMA_MISC = JPEG_INDMA_MISC_IN_DMA_ID_SET(1) - | JPEG_INDMA_MISC_IN_DMA_REQ_MASK; + | JPEG_INDMA_MISC_IN_DMA_REQ_MASK + | JPEG_INDMA_MISC_MAX_OT_SET(2) + | JPEG_INDMA_MISC_PACK_DIR_SET(config->in_byte_order); ptr->INDMABASE = JPEG_INDMABASE_ADDR_SET(config->in_buffer); /* TODO: check if it has to use the compressed length */ ptr->INDMA_CTRL0 = JPEG_INDMA_CTRL0_TTLEN_SET(length); ptr->INDMA_CTRL1 = JPEG_INDMA_CTRL1_ROWLEN_SET(length >> 16); - ptr->INXT_CMD = JPEG_INXT_CMD_ADDR_SET(0x14) | JPEG_INXT_CMD_OP_VALID_MASK; + ptr->INXT_CMD = JPEG_INXT_CMD_ADDR_SET(5) | JPEG_INXT_CMD_OP_VALID_MASK; /* output DMA setting */ ptr->OUTDMA_MISC = JPEG_OUTDMA_MISC_EN_OUTCNT_MASK | JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(0) - | JPEG_OUTDMA_MISC_PACK_DIR_SET(config->byte_order) | JPEG_OUTDMA_MISC_INI_OUTCNT_MASK | JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK - | JPEG_OUTDMA_MISC_OUTDMA2D_MASK; + | JPEG_OUTDMA_MISC_OUTDMA2D_MASK + | JPEG_OUTDMA_MISC_PACK_DIR_SET(config->out_byte_order); ptr->OUTDMABASE = JPEG_OUTDMABASE_ADDR_SET(config->out_buffer); ptr->OUTDMA_CTRL0 = JPEG_OUTDMA_CTRL0_TTLEN_SET(total_bytes) - | JPEG_OUTDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_get_pixel_size(config->out_pixel_format)); - ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(2); - ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(0x14) | JPEG_ONXT_CMD_OP_VALID_MASK; + | JPEG_OUTDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_supported_pixel_format[config->in_pixel_format].pixel_width); + ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(total_bytes >> 16); + ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(5) | JPEG_ONXT_CMD_OP_VALID_MASK; jpeg_config_interal_regs(ptr, true, macro_block_count, config->jpeg_format); ptr->WIDTH = config->width_in_pixel - 1; ptr->HEIGHT = config->height_in_pixel - 1; - ptr->CSC_COEF0 = 0x04AB01F0 + ptr->CSC_COEF0 = 0x4ab01f0 | JPEG_CSC_COEF0_YCBCR_MODE_SET(config->enable_ycbcr) - | JPEG_CSC_COEF0_ENABLE_SET(config->enable_csc); + | JPEG_CSC_COEF0_ENABLE_SET(jpeg_need_csc(config->in_pixel_format, config->out_pixel_format)); ptr->CSC_COEF1 = 0x01980204; ptr->CSC_COEF2 = 0x0730079C; - ptr->CFG = JPEG_CFG_CFG_OPATH_SEL_SET(config->out_pixel_format) + ptr->CFG = JPEG_CFG_CFG_OPATH_SEL_SET(jpeg_supported_pixel_format[config->out_pixel_format].opath) | JPEG_CFG_JDATA_FORMAT_SET(config->jpeg_format) | JPEG_CFG_JPEG_EN_MASK | JPEG_CFG_START_MASK + | JPEG_CFG_CLKGATE_MASK | JPEG_CFG_MODE_MASK; return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c index 480f57af9c..1b15b00a99 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,16 +13,20 @@ static uint32_t lcdc_pixel_format(display_pixel_format_t format) { switch (format) { - case display_pixel_format_argb8888: - return 9; - case display_pixel_format_rgb565: - return 4; - case display_pixel_format_yuv422: - return 7; - case display_pixel_format_ycbcr422: - return 7; - default: - return 9; + case display_pixel_format_argb8888: + return 9; + case display_pixel_format_rgb565: + return 4; + case display_pixel_format_yuv422: + return 7; + case display_pixel_format_ycbcr422: + return 7; + case display_pixel_format_y8: + return 0xb; + case display_pixel_format_raw8: + return 0xb; + default: + return 9; } } @@ -35,12 +39,12 @@ static uint32_t lcdc_pixel_format(display_pixel_format_t format) static uint8_t lcdc_byteorder(display_byteorder_t byteorder) { switch (byteorder) { - case display_byteorder_a3a2a1a0: /* LSB */ - return 0; - case display_byteorder_a0a1a2a3: /* MSB */ - return 1; - default: - return 0; + case display_byteorder_a3a2a1a0: /* LSB */ + return 0; + case display_byteorder_a0a1a2a3: /* MSB */ + return 1; + default: + return 0; } } @@ -67,40 +71,40 @@ void lcdc_get_default_layer_config(LCDC_Type *ptr, lcdc_layer_config_t *layer, d layer->alphablend.dst_alpha_op = display_alpha_op_invalid; layer->alphablend.mode = display_alphablend_mode_clear; - switch(pixel_format) { - case display_pixel_format_yuv422: - layer->csc_config.enable = true; - layer->csc_config.ycbcr_mode = false; - layer->csc_config.yuv2rgb_coef.c0 = 0x100; - layer->csc_config.yuv2rgb_coef.uv_offset = 0; - layer->csc_config.yuv2rgb_coef.y_offset = 0; - layer->csc_config.yuv2rgb_coef.c1 = 0x123; - layer->csc_config.yuv2rgb_coef.c2 = 0x76B; - layer->csc_config.yuv2rgb_coef.c3 = 0x79C; - layer->csc_config.yuv2rgb_coef.c4 = 0x208; - break; - case display_pixel_format_ycbcr422: - layer->csc_config.enable = true; - layer->csc_config.ycbcr_mode = true; - layer->csc_config.yuv2rgb_coef.c0 = 0x12A; - layer->csc_config.yuv2rgb_coef.uv_offset = 0x180; - layer->csc_config.yuv2rgb_coef.y_offset = 0x1F0; - layer->csc_config.yuv2rgb_coef.c1 = 0x198; - layer->csc_config.yuv2rgb_coef.c2 = 0x730; - layer->csc_config.yuv2rgb_coef.c3 = 0x79C; - layer->csc_config.yuv2rgb_coef.c4 = 0x204; - break; - default: - layer->csc_config.enable = false; - layer->csc_config.ycbcr_mode = false; - layer->csc_config.yuv2rgb_coef.c0 = 0; - layer->csc_config.yuv2rgb_coef.uv_offset = 0; - layer->csc_config.yuv2rgb_coef.y_offset = 0; - layer->csc_config.yuv2rgb_coef.c1 = 0; - layer->csc_config.yuv2rgb_coef.c2 = 0; - layer->csc_config.yuv2rgb_coef.c3 = 0; - layer->csc_config.yuv2rgb_coef.c4 = 0; - break; + switch (pixel_format) { + case display_pixel_format_yuv422: + layer->csc_config.enable = true; + layer->csc_config.ycbcr_mode = false; + layer->csc_config.yuv2rgb_coef.c0 = 0x100; + layer->csc_config.yuv2rgb_coef.uv_offset = 0; + layer->csc_config.yuv2rgb_coef.y_offset = 0; + layer->csc_config.yuv2rgb_coef.c1 = 0x123; + layer->csc_config.yuv2rgb_coef.c2 = 0x76B; + layer->csc_config.yuv2rgb_coef.c3 = 0x79C; + layer->csc_config.yuv2rgb_coef.c4 = 0x208; + break; + case display_pixel_format_ycbcr422: + layer->csc_config.enable = true; + layer->csc_config.ycbcr_mode = true; + layer->csc_config.yuv2rgb_coef.c0 = 0x12A; + layer->csc_config.yuv2rgb_coef.uv_offset = 0x180; + layer->csc_config.yuv2rgb_coef.y_offset = 0x1F0; + layer->csc_config.yuv2rgb_coef.c1 = 0x198; + layer->csc_config.yuv2rgb_coef.c2 = 0x730; + layer->csc_config.yuv2rgb_coef.c3 = 0x79C; + layer->csc_config.yuv2rgb_coef.c4 = 0x204; + break; + default: + layer->csc_config.enable = false; + layer->csc_config.ycbcr_mode = false; + layer->csc_config.yuv2rgb_coef.c0 = 0; + layer->csc_config.yuv2rgb_coef.uv_offset = 0; + layer->csc_config.yuv2rgb_coef.y_offset = 0; + layer->csc_config.yuv2rgb_coef.c1 = 0; + layer->csc_config.yuv2rgb_coef.c2 = 0; + layer->csc_config.yuv2rgb_coef.c3 = 0; + layer->csc_config.yuv2rgb_coef.c4 = 0; + break; } } @@ -258,13 +262,15 @@ void lcdc_turn_off_display(LCDC_Type *ptr) /* 1. wait for current frame end */ ptr->ST = 0xFFFFFFFF; - while((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0); + while ((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0) { + } /* 2. issue display off */ ptr->ST = 0xFFFFFFFF; lcdc_software_reset(ptr); ptr->CTRL &= ~LCDC_CTRL_DISP_ON_MASK; - while((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0); + while ((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0) { + } } return; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c new file mode 100644 index 0000000000..9411fb3da5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_lin_drv.h" + +#define HPM_LIN_DRV_RETRY_COUNT (50000U) + +hpm_stat_t lin_master_configure_timing(LIN_Type *ptr, lin_timing_t *timing) +{ + assert(timing->src_freq_in_hz >= 8000000U); + assert((timing->baudrate >= 1000U) && (timing->baudrate <= 20000U)); + + uint8_t prescaler, bt_mul; + uint16_t bt_div; + + /** set master mode */ + ptr->TV |= LIN_TV_MASTER_MODE_MASK; + ptr->TV |= LIN_TV_INITIAL_MODE_MASK; + ptr->TV &= ~LIN_TV_INITIAL_MODE_MASK; + + bt_mul = 20000U / timing->baudrate - 1U; + prescaler = log((timing->src_freq_in_hz / ((bt_mul + 1U) * timing->baudrate * 200U))) / log(2U) - 1U; + bt_div = timing->src_freq_in_hz / ((1U << (prescaler + 1U)) * (bt_mul + 1U) * timing->baudrate); + + if ((bt_div < 200) || (bt_div > 512)) { + return status_invalid_argument; + } + + /** src =20MHz baudrate = 19.2KHz */ + /** bt_div = 260, scaler = 1, bt_mul = 0 */ + ptr->BAUDRATE_CTL_LOW = bt_div & 0xFF; + ptr->BARDRATE_CTL_HIGH = LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(bt_div >> 8U) + | LIN_BARDRATE_CTL_HIGH_BT_MUL_SET(bt_mul) + | LIN_BARDRATE_CTL_HIGH_PRESCL_SET(prescaler); + + return status_success; +} + +hpm_stat_t lin_slave_configure_timing(LIN_Type *ptr, uint32_t src_freq_in_hz) +{ + assert(src_freq_in_hz >= 8000000U); + + uint8_t prescaler; + uint16_t bt_div; + + /** set slave mode */ + ptr->TV &= ~LIN_TV_MASTER_MODE_MASK; + ptr->TV |= LIN_TV_INITIAL_MODE_MASK; + ptr->TV &= ~LIN_TV_INITIAL_MODE_MASK; + + prescaler = log((src_freq_in_hz / (20000U * 200U))) / log(2U) - 1U; + bt_div = src_freq_in_hz / ((1U << (prescaler + 1U)) * 20000U); + + if ((bt_div < 200) || (bt_div > 512)) { + return status_invalid_argument; + } + + /** src = 20MHz, prescaler = 1, bt_div = 250 */ + ptr->BAUDRATE_CTL_LOW = bt_div & 0xFF; + ptr->BARDRATE_CTL_HIGH = LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(bt_div >> 8U) + | LIN_BARDRATE_CTL_HIGH_PRESCL_SET(prescaler); + + return status_success; +} + +uint8_t lin_get_data_length_from_id(uint8_t id) +{ + switch (LIN_ID_DATA_LEN_GET(id)) { + case id_data_length_2bytes: + return 2; + case id_data_length_2bytes_2: + return 2; + case id_data_length_4bytes: + return 4; + case id_data_length_8bytes: + return 8; + default: + return 8; + } +} + +uint8_t lin_get_data_length(LIN_Type *ptr) +{ + uint8_t data_length = 0; + if (((ptr->DATA_LEN) & LIN_DATA_LEN_DATA_LENGTH_MASK) == LIN_DATA_LEN_DATA_LENGTH_MASK) { + data_length = lin_get_data_length_from_id(ptr->ID); + } else { + data_length = LIN_DATA_LEN_DATA_LENGTH_GET(ptr->DATA_LEN); + } + return data_length; +} + +void lin_master_transfer(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + ptr->ID = config->id; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + /** sent or receive */ + ptr->CONTROL = 0U; + if (config->transmit) { + ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + } + + /** start */ + ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; +} + +hpm_stat_t lin_master_sent(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length = 0; + + /** lin active */ + while (((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + ptr->ID = config->id; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; + + /** load data into registers */ + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + + /** start */ + ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; + + /** lin complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_master_receive(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** lin active */ + while (((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + ptr->ID = config->id; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + /** receive */ + ptr->CONTROL = 0U; + /** start */ + ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; + + /** waiting for receive complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_fail; + } + + /** load register data into buffer */ + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATABYTE[i]; + } + + return status_success; +} + +void lin_slave_transfer(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + /** transmit or receive */ + ptr->CONTROL = LIN_CONTROL_TRANSMIT_SET(config->transmit); + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + } + + /** data ack */ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; +} + +hpm_stat_t lin_slave_sent(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** lin data_req */ + /** lin active? */ + while (((ptr->STATE & LIN_STATE_DATA_REQ_MASK) == LIN_STATE_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** transmit */ + ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + + /** data ack */ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; + + /** lin complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_slave_receive(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** lin data_req */ + while (((ptr->STATE & LIN_STATE_DATA_REQ_MASK) == LIN_STATE_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** receive */ + ptr->CONTROL = 0U; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + /** data ack */ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; + + /** lin complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATABYTE[i]; + } + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c new file mode 100644 index 0000000000..044a95c71f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c @@ -0,0 +1,1685 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_mcan_drv.h" +#include +#include + +#define MCAN_CAN_BAUDRATE_DEFAULT (500UL * 1000UL) /*!< Default CAN2.0 baudrate:500 kbps */ +#define MCAN_CANFD_BAUDRATE_DEFAULT (2UL * 1000UL * 1000UL) /*!< Default CANFD baudrate: 2 Mbps */ + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ +#define NUM_TQ_SYNC_SEG (1U) + +/** + * @brief CAN2.0 Timing related definitions + */ +#define TSEG1_MIN_FOR_CAN2_0 (2U) +#define TSEG1_MAX_FOR_CAN2_0 (256U) +#define TSEG2_MIN_FOR_CAN2_0 (2U) +#define TSEG2_MAX_FOR_CAN2_0 (128U) +#define TSJW_MIN_FOR_CAN2_0 (1U) +#define TSJW_MAX_FOR_CAN2_0 (128U) +#define PRESCALER_MIN_FOR_CAN2_0 (1U) +#define PRESCALER_MAX_FOR_CAN2_0 (512U) +#define NUM_TQ_MIN_FOR_CAN2_0 (8U) +#define NUM_TQ_MAX_FOR_CAN2_0 (TSEG1_MAX_FOR_CAN2_0 + TSEG2_MAX_FOR_CAN2_0) + +/** + * @brief CANFD Nominal Timing related definitions + */ +#define TSEG1_MIN_FOR_CANFD_NOMINAL (2U) +#define TSEG1_MAX_FOR_CANFD_NOMINAL (256U) +#define TSEG2_MIN_FOR_CANFD_NOMINAL (1U) +#define TSEG2_MAX_FOR_CANFD_NOMINAL (32U) +#define TSJW_MIN_FOR_CANFD_NOMINAL (1U) +#define TSJW_MAX_FOR_CANFD_NOMINAL (128U) +#define NUM_TQ_MIN_FOR_CANFD_NOMINAL (8U) +#define NUM_TQ_MAX_FOR_CANFD_NOMINAL (TSEG1_MAX_FOR_CANFD_NOMINAL + TSEG2_MAX_FOR_CANFD_NOMINAL) +#define PRESCALER_MIN_FOR_CANFD_NOMINAL (1U) +#define PRESCALER_MAX_FOR_CANFD_NOMINAL (512U) + +/** + * @brief CANFD Data Timing related definitions + */ +#define TSEG1_MIN_FOR_CANFD_DATA (2U) +#define TSEG1_MAX_FOR_CANFD_DATA (31U) +#define TSEG2_MIN_FOR_CANFD_DATA (0U) +#define TSEG2_MAX_FOR_CANFD_DATA (15U) +#define TSJW_MIN_FOR_CANFD_DATA (0U) +#define TSJW_MAX_FOR_CANFD_DATA (15U) +#define PRESCALER_MIN_FOR_CANFD_DATA (1U) +#define PRESCALER_MAX_FOR_CANFD_DATA (32U) + +#define NUM_TQ_MIN_FOR_CANFD_DATA (8U) +#define NUM_TQ_MAX_FOR_CANFD_DATA (TSEG1_MAX_FOR_CANFD_DATA + TSEG2_MAX_FOR_CANFD_DATA) + +#define MIN_TQ_MUL_PRESCALE (8U) +#define NUM_PRESCALE_MAX (256U) + +#define CAN_SAMPLEPOINT_MIN (750U) +#define CAN_SAMPLEPOINT_MAX (875U) + +/* Invalid start address of MCAN RAM */ +#define MCAN_RAM_ADDR_INVALID ((1UL << 16) - 1U) + +/* Maximum CAN TDC offset value */ +#define MCAN_MAX_TDC_OFFSET ((uint32_t)(MCAN_TDCR_TDCO_MASK >> MCAN_TDCR_TDCO_SHIFT)) + +/** + * @brief MCAN bit timing table + */ +typedef struct mcan_bit_timing_table_struct { + uint16_t tq_min; /*!< Minimum Tq */ + uint16_t tq_max; /*!< Maximum Tq */ + uint16_t seg1_min; /*!< Minimum TSEG1 */ + uint16_t seg1_max; /*!< Maximum TSEG1 */ + uint8_t seg2_min; /*!< Minimum TSEG2 */ + uint8_t seg2_max; /*!< Maximum TSEG2 */ + uint8_t sjw_min; /*!< Minimum SJW */ + uint8_t sjw_max; /*!< Maximum SJW */ + uint8_t min_diff_seg1_minus_seg2; /*!< Minimum value of (TSEG1 - TSEG2 ) */ + uint8_t prescaler_min; /*!< Minimum Prescaler value */ + uint16_t prescaler_max; /*!< Maximum Prescaler value */ +} mcan_bit_timing_table_t; + +/*********************************************************************************************************************** + * + * Variables + * + **********************************************************************************************************************/ +static const mcan_bit_timing_table_t k_mcan_bit_timing_tbl[3] = { + /* CAN2.0 bit timing requirement */ + { + /* TQ range */ + .tq_min = NUM_TQ_MIN_FOR_CAN2_0, .tq_max = NUM_TQ_MAX_FOR_CAN2_0, + /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg1 */ + .seg1_min = TSEG1_MIN_FOR_CAN2_0, .seg1_max = TSEG1_MAX_FOR_CAN2_0, + /* SEG2 Range */ + .seg2_min = TSEG2_MIN_FOR_CAN2_0, .seg2_max = TSEG2_MAX_FOR_CAN2_0, + /* SJW range */ + .sjw_min = TSJW_MIN_FOR_CAN2_0, .sjw_max = TSJW_MAX_FOR_CAN2_0, .min_diff_seg1_minus_seg2 = 2, + /* Prescaler range */ + .prescaler_min = PRESCALER_MIN_FOR_CAN2_0, .prescaler_max = PRESCALER_MAX_FOR_CAN2_0, + }, + /* CANFD Nominal Bit timing requirement */ + { + /* TQ range */ + .tq_min = NUM_TQ_MIN_FOR_CANFD_NOMINAL, .tq_max = NUM_TQ_MAX_FOR_CANFD_NOMINAL, + /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg1 */ + .seg1_min = TSEG1_MIN_FOR_CANFD_NOMINAL, .seg1_max = TSEG1_MAX_FOR_CANFD_NOMINAL, + /* SEG2 range */ + .seg2_min = TSEG2_MIN_FOR_CANFD_NOMINAL, .seg2_max = TSEG2_MAX_FOR_CANFD_NOMINAL, + /* SJW range */ + .sjw_min = TSJW_MIN_FOR_CANFD_NOMINAL, .sjw_max = TSJW_MAX_FOR_CANFD_NOMINAL, .min_diff_seg1_minus_seg2 = 2, + /* Prescaler range */ + .prescaler_min = PRESCALER_MIN_FOR_CANFD_NOMINAL, .prescaler_max = PRESCALER_MAX_FOR_CANFD_NOMINAL + }, + /* CANFD Data Bit timing requirement */ + { + /* TQ range */ + .tq_min = NUM_TQ_MIN_FOR_CANFD_DATA, .tq_max = NUM_TQ_MAX_FOR_CANFD_DATA, + /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg2 */ + .seg1_min = TSEG1_MIN_FOR_CANFD_DATA, .seg1_max = TSEG1_MAX_FOR_CANFD_DATA, + /* SEG2 range */ + .seg2_min = TSEG2_MIN_FOR_CANFD_DATA, .seg2_max = TSEG2_MAX_FOR_CANFD_DATA, + /* SJW range */ + .sjw_min = TSJW_MIN_FOR_CANFD_DATA, .sjw_max = TSJW_MAX_FOR_CANFD_DATA, .min_diff_seg1_minus_seg2 = 1, + /* Prescaler range */ + .prescaler_min = PRESCALER_MIN_FOR_CANFD_DATA, .prescaler_max = PRESCALER_MAX_FOR_CANFD_DATA + }}; + +static const mcan_filter_elem_t k_default_std_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0U, + /* Don't care if mask is set to all 1s */ + .filter_id = 0U, + /* Accept all messages */ + .filter_mask = 0x7FFU, +}; + +static const mcan_filter_elem_t k_default_ext_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0, + /* Don't care if mask is set to all 1s */ + .filter_id = 0, + /* Accept all messages */ + .filter_mask = 0x1FFFFFFFUL, +}; + +/*********************************************************************************************************************** + * + * Prototypes + * + **********************************************************************************************************************/ +/** + * @brief Set Nominal Bit timing + * + * @param [in] ptr MCAN base + * @param [in] bit_timing Bit timing parameter + */ +static void mcan_set_can_nominal_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing); + +/** + * @brief Set CANFD Data Bit timing + * + * @param [in] ptr MCAN base + * + * @param [in] bit_timing Bit timing parameter + */ +static void mcan_set_can_data_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing); + +/** + * @brief Calculate the closest prescaler + * + * @param [in] num_tq_mul_prescaler Number of TQ * Prescaler + * @param [in] start_prescaler Start of Prescaler value + * @param [in] max_tq Maximum Timing Quantum + * @param [in] min_tq Minimum Timing Quantum + * + * @return Calculated prescaler value + */ +static uint32_t mcan_calculate_closest_prescaler(uint32_t num_tq_mul_prescaler, + uint32_t start_prescaler, + uint32_t max_tq, + uint32_t min_tq); + +/** + * @brief Calculate Bit timing from baudrate + * + * @param [in] src_clk_freq CAN IP clock used for generating bit timing + * @param [in] option CAN bit timing option + * @param [in] baudrate CAN baudrate in bps + * @param [in] samplepoint_min Minimum sample point, value = actual sample point * 1000 + * @param [in] samplepoint_max Maximum sample point, value = actual sample point * 1000 + * @param [out] timing_param Calculated Bit timing parameter + * + * @retval status_success if no errors happened + * @retval status_invalid_argument if the timing parameters cannot be calculated from specified baudrate + */ +static hpm_stat_t mcan_calc_bit_timing_from_baudrate(uint32_t src_clk_freq, + mcan_bit_timing_option_t option, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max, + mcan_bit_timing_param_t *timing_param); + +/** + * @brief Set MCAN bit timing from Baudrate + * + * @param [in] ptr MCAN base + * @param [in] option MCAN bit timing option + * @param [in] src_clk_freq CAN IP clock used for generating bit timing + * @param [in] baudrate Baudrate in bps + * @param [in] samplepoint_min Minimum sample point, value = actual sample point * 1000 + * @param [in] samplepoint_max Maximum sample point, value = actual sample point * 1000 + * + * @retval status_success if no errors happened + * @retval status_invalid_argument if the timing parameters cannot be calculated from specified baudrate + */ +static hpm_stat_t mcan_set_bit_timing_from_baudrate(MCAN_Type *ptr, + mcan_bit_timing_option_t option, + uint32_t src_clk_freq, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max); + +/** + * @brief Configure MCAN TSU + * + * @param [in] ptr MCAN base + * @param [in] config TSU configuration + * @retval status_success if no errors happened + * + * @retval status_invalid_arugment if any parameters are invalid + */ +static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config); + +/** + * @brief Configure MCAN internal timestamp + * + * @param [in] ptr MCAN base + * @param [in] config Internal Timestamp Configuratiojn + * @retval status_success if no errors happened + * + * @retval status_invalid_arugment if any parameters are invalid + */ +static hpm_stat_t mcan_set_internal_timestamp(MCAN_Type *ptr, mcan_internal_timestamp_config_t *config); + +/*********************************************************************************************************************** + * + * Codes + */ +static void mcan_set_can_nominal_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing) +{ + ptr->NBTP = MCAN_NBTP_NBRP_SET(bit_timing->prescaler - 1U) | MCAN_NBTP_NTSEG1_SET(bit_timing->num_seg1 - 1U) | + MCAN_NBTP_NTSEG2_SET(bit_timing->num_seg2 - 1U) | MCAN_NBTP_NSJW_SET(bit_timing->num_sjw - 1U); +} + +static void mcan_set_can_data_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing) +{ + ptr->DBTP = MCAN_DBTP_DBRP_SET(bit_timing->prescaler - 1U) | MCAN_DBTP_DTSEG1_SET(bit_timing->num_seg1 - 1U) | + MCAN_DBTP_DTSEG2_SET(bit_timing->num_seg2 - 1U) | MCAN_DBTP_DSJW_SET(bit_timing->num_sjw - 1U) | + MCAN_DBTP_TDC_SET((uint32_t) bit_timing->enable_tdc); +} + +static uint32_t mcan_calculate_closest_prescaler(uint32_t num_tq_mul_prescaler, + uint32_t start_prescaler, + uint32_t max_tq, + uint32_t min_tq) +{ + bool has_found = false; + + uint32_t prescaler = start_prescaler; + + while (!has_found) { + if ((num_tq_mul_prescaler / prescaler > max_tq) || (num_tq_mul_prescaler % prescaler != 0)) { + ++prescaler; + continue; + } else { + uint32_t tq = num_tq_mul_prescaler / prescaler; + if (tq * prescaler == num_tq_mul_prescaler) { + has_found = true; + break; + } else if (tq < min_tq) { + has_found = false; + break; + } else { + ++prescaler; + } + } + } + + return has_found ? prescaler : 0U; +} + +static hpm_stat_t mcan_calc_bit_timing_from_baudrate(uint32_t src_clk_freq, + mcan_bit_timing_option_t option, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max, + mcan_bit_timing_param_t *timing_param) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((option > mcan_bit_timing_canfd_data) || (baudrate == 0U) || + (src_clk_freq / baudrate < MIN_TQ_MUL_PRESCALE) || (timing_param == NULL)) { + break; + } + + const mcan_bit_timing_table_t *tbl = &k_mcan_bit_timing_tbl[(uint8_t) option]; + + /* According to the CAN specification 2.0, + * the Tq must be in range specified in the above CAN bit-timing table + */ + if (src_clk_freq / baudrate < tbl->tq_min) { + break; + } + + uint32_t num_tq_mul_prescaler = src_clk_freq / baudrate; + uint32_t start_prescaler = 1U; + uint32_t num_seg1, num_seg2; + bool has_found = false; + + /* Find out the minimum prescaler */ + uint32_t current_prescaler; + while (!has_found) { + current_prescaler = + mcan_calculate_closest_prescaler(num_tq_mul_prescaler, start_prescaler, tbl->tq_max, tbl->tq_min); + if ((current_prescaler < start_prescaler) || (current_prescaler > NUM_PRESCALE_MAX)) { + break; + } + uint32_t num_tq = num_tq_mul_prescaler / current_prescaler; + + num_seg2 = (num_tq - tbl->min_diff_seg1_minus_seg2) / 2U; + num_seg1 = num_tq - num_seg2; + while (num_seg2 > tbl->seg2_max) { + num_seg2--; + num_seg1++; + } + + /* Recommended sample point is 75% - 87.5% */ + while ((num_seg1 * 1000U) / num_tq < samplepoint_min) { + ++num_seg1; + --num_seg2; + } + + if ((num_seg1 * 1000U) / num_tq > samplepoint_max) { + break; + } + + if ((num_seg2 >= tbl->seg2_min) && (num_seg1 <= tbl->seg1_max)) { + has_found = true; + } else { + start_prescaler = current_prescaler + 1U; + } + } + + if (has_found) { + uint32_t num_sjw = MIN(tbl->sjw_max, num_seg2); + timing_param->num_seg1 = num_seg1 - NUM_TQ_SYNC_SEG; /* Should exclude the Sync_Reg */ + timing_param->num_seg2 = num_seg2; + timing_param->num_sjw = num_sjw; + timing_param->prescaler = current_prescaler; + status = status_success; + } + } while (false); + + return status; +} + +static hpm_stat_t mcan_set_bit_timing_from_baudrate(MCAN_Type *ptr, + mcan_bit_timing_option_t option, + uint32_t src_clk_freq, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if (ptr == NULL) { + break; + } + + mcan_bit_timing_param_t timing_param = { 0 }; + status = mcan_calc_bit_timing_from_baudrate(src_clk_freq, + option, + baudrate, + samplepoint_min, + samplepoint_max, + &timing_param); + + if (status == status_success) { + if (option < mcan_bit_timing_canfd_data) { + mcan_set_can_nominal_bit_timing(ptr, &timing_param); + } else { + mcan_set_can_data_bit_timing(ptr, &timing_param); + } + status = status_success; + } + + } while (false); + + return status; +} + +void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd) +{ + (void) memset(simple_config, 0, sizeof(mcan_ram_config_t)); + uint32_t start_addr = mcan_get_ram_offset(ptr); + + if (!enable_canfd) { + simple_config->enable_std_filter = true; + simple_config->std_filter_elem_count = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + simple_config->enable_ext_filter = true; + simple_config->ext_filter_elem_count = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + simple_config->enable_txbuf = true; + simple_config->txbuf_dedicated_txbuf_elem_count = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + simple_config->txbuf_fifo_or_queue_elem_count = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + simple_config->txfifo_or_txqueue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + simple_config->txbuf_data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + for (uint32_t i = 0; i < ARRAY_SIZE(simple_config->rxfifos); i++) { + simple_config->rxfifos[i].enable = true; + simple_config->rxfifos[i].elem_count = MCAN_RXFIFO_SIZE_CAN_DEFAULT; + simple_config->rxfifos[i].operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + simple_config->rxfifos[i].watermark = 1U; + simple_config->rxfifos[i].data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + } + simple_config->enable_rxbuf = true; + simple_config->rxbuf_elem_count = MCAN_RXBUF_SIZE_CAN_DEFAULT; + simple_config->rxbuf_data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_RXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + } else { + simple_config->enable_std_filter = true; + simple_config->std_filter_elem_count = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + simple_config->enable_ext_filter = true; + simple_config->ext_filter_elem_count = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + simple_config->enable_txbuf = true; + simple_config->txbuf_dedicated_txbuf_elem_count = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + simple_config->txbuf_fifo_or_queue_elem_count = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + simple_config->txfifo_or_txqueue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + simple_config->txbuf_data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_TXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + + for (uint32_t i = 0; i < ARRAY_SIZE(simple_config->rxfifos); i++) { + simple_config->rxfifos[i].enable = true; + simple_config->rxfifos[i].elem_count = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; + simple_config->rxfifos[i].operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + simple_config->rxfifos[i].watermark = 1U; + simple_config->rxfifos[i].data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + } + simple_config->enable_rxbuf = true; + simple_config->rxbuf_elem_count = MCAN_RXBUF_SIZE_CANFD_DEFAULT; + simple_config->rxbuf_data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_RXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + } + simple_config->enable_tx_evt_fifo = true; + uint32_t tx_fifo_elem_count = + simple_config->txbuf_dedicated_txbuf_elem_count + simple_config->txbuf_fifo_or_queue_elem_count; + simple_config->tx_evt_fifo_elem_count = tx_fifo_elem_count; + simple_config->tx_evt_fifo_watermark = 1U; + + start_addr += MCAN_TXEVT_ELEM_SIZE * tx_fifo_elem_count; + + assert((start_addr - mcan_get_ram_offset(ptr)) <= mcan_get_ram_size(ptr)); +} + +void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd) +{ + (void) memset(ram_config, 0, sizeof(mcan_ram_config_t)); + uint32_t start_addr = mcan_get_ram_offset(ptr); + + if (!enable_canfd) { + ram_config->enable_std_filter = true; + ram_config->std_filter_config.list_start_addr = start_addr; + ram_config->std_filter_config.list_size = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + ram_config->enable_ext_filter = true; + ram_config->ext_filter_config.list_start_addr = start_addr; + ram_config->ext_filter_config.list_size = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + ram_config->enable_txbuf = true; + ram_config->txbuf_config.start_addr = start_addr; + ram_config->txbuf_config.dedicated_tx_buf_size = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + ram_config->txbuf_config.fifo_queue_size = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + ram_config->txbuf_config.tx_fifo_queue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + ram_config->txbuf_elem_config.data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxfifo0 = true; + ram_config->rxfifo0_config.start_addr = start_addr; + ram_config->rxfifo0_config.fifo_size = MCAN_RXFIFO_SIZE_CAN_DEFAULT; + ram_config->rxfifo0_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo0_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxfifo1 = true; + ram_config->rxfifo1_config.start_addr = start_addr; + ram_config->rxfifo1_config.fifo_size = MCAN_RXFIFO_SIZE_CAN_DEFAULT; + ram_config->rxfifo1_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo1_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxbuf = true; + ram_config->rxbuf_config.start_addr = start_addr; + start_addr += MCAN_RXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + } else { + ram_config->enable_std_filter = true; + ram_config->std_filter_config.list_start_addr = start_addr; + ram_config->std_filter_config.list_size = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + ram_config->enable_ext_filter = true; + ram_config->ext_filter_config.list_start_addr = start_addr; + ram_config->ext_filter_config.list_size = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + ram_config->enable_txbuf = true; + ram_config->txbuf_config.start_addr = start_addr; + ram_config->txbuf_config.dedicated_tx_buf_size = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + ram_config->txbuf_config.fifo_queue_size = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + ram_config->txbuf_config.tx_fifo_queue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + ram_config->txbuf_elem_config.data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxfifo0 = true; + ram_config->rxfifo0_config.start_addr = start_addr; + ram_config->rxfifo0_config.fifo_size = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; + ram_config->rxfifo0_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo0_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + + ram_config->enable_rxfifo1 = true; + ram_config->rxfifo1_config.start_addr = start_addr; + ram_config->rxfifo1_config.fifo_size = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; + ram_config->rxfifo1_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo1_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + + ram_config->enable_rxbuf = true; + ram_config->rxbuf_config.start_addr = start_addr; + start_addr += MCAN_RXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + } + ram_config->enable_tx_evt_fifo = true; + ram_config->tx_evt_fifo_config.start_addr = start_addr; + uint32_t tx_fifo_size = ram_config->txbuf_config.dedicated_tx_buf_size + ram_config->txbuf_config.fifo_queue_size; + ram_config->tx_evt_fifo_config.fifo_size = tx_fifo_size; + ram_config->tx_evt_fifo_config.fifo_watermark = 1U; + + start_addr += MCAN_TXEVT_ELEM_SIZE * tx_fifo_size; + + /* Ensure the requested MCAN RAM size is less than or equal to the total MCAN RAM size */ + assert((start_addr - mcan_get_ram_offset(ptr)) <= mcan_get_ram_size(ptr)); +} + +void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config) +{ + (void) memset(config, 0, sizeof(mcan_config_t)); + config->baudrate = MCAN_CAN_BAUDRATE_DEFAULT; + config->baudrate_fd = MCAN_CANFD_BAUDRATE_DEFAULT; + config->can20_samplepoint_max = CAN_SAMPLEPOINT_MAX; + config->can20_samplepoint_min = CAN_SAMPLEPOINT_MIN; + config->canfd_samplepoint_max = CAN_SAMPLEPOINT_MAX; + config->canfd_samplepoint_min = CAN_SAMPLEPOINT_MIN; + + config->mode = mcan_mode_normal; + config->enable_canfd = false; + + /* Default Filter settings */ + mcan_all_filters_config_t *filters_config = &config->all_filters_config; + filters_config->global_filter_config.reject_remote_ext_frame = false; + filters_config->global_filter_config.reject_remote_std_frame = false; + filters_config->global_filter_config.accept_non_matching_std_frame_option = + MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + filters_config->global_filter_config.accept_non_matching_ext_frame_option = + MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + filters_config->ext_id_mask = 0x1FFFFFFFUL; + filters_config->std_id_filter_list.filter_elem_list = &k_default_std_id_filter; + filters_config->std_id_filter_list.mcan_filter_elem_count = 1; + filters_config->ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter; + filters_config->ext_id_filter_list.mcan_filter_elem_count = 1; + + /* Default MCAN RAM Configuration */ + mcan_ram_config_t *ram_config = &config->ram_config; + mcan_get_default_ram_config(ptr, ram_config, false); + + /* Default Internal Timestamp Configuration */ + mcan_internal_timestamp_config_t *ts_config = &config->timestamp_cfg; + ts_config->counter_prescaler = 1U; + ts_config->timestamp_selection = MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO; + + /* Default TSU configuration */ + mcan_tsu_config_t *tsu_config = &config->tsu_config; + tsu_config->prescaler = 1U; + tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_PTP; + tsu_config->use_ext_timebase = false; + tsu_config->capture_on_sof = false; + tsu_config->enable_tsu = false; +} + +static void mcan_config_rxfifo(MCAN_Type *ptr, uint32_t index, uint32_t reg_val) +{ + if (index == 0U) { + ptr->RXF0C = reg_val; + } else { + ptr->RXF1C = reg_val; + } +} + +hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t elem_bytes; + uint32_t elem_count; + uint32_t start_addr = mcan_get_ram_offset(ptr); + if (config->enable_std_filter) { + mcan_filter_config_t filter_config = { .reg_val = 0 }; + filter_config.list_size = config->std_filter_elem_count; + filter_config.list_start_addr = start_addr; + ptr->SIDFC = filter_config.reg_val; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * (uint32_t) config->std_filter_elem_count; + } else { + ptr->SIDFC = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_ext_filter) { + mcan_filter_config_t filter_config = { .reg_val = 0 }; + filter_config.list_size = config->ext_filter_elem_count; + filter_config.list_start_addr = start_addr; + ptr->XIDFC = filter_config.reg_val; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * (uint32_t) config->std_filter_elem_count; + } else { + ptr->XIDFC = MCAN_RAM_ADDR_INVALID; + } + + mcan_rx_fifo_or_buf_elem_config_t rx_fifo_buf_elem_config = { .reg_val = 0U }; + + for (uint32_t i = 0; i < ARRAY_SIZE(config->rxfifos); i++) { + if (config->rxfifos[i].enable) { + elem_bytes = + mcan_get_data_field_size(config->rxfifos[i].data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + elem_count = config->rxfifos[i].elem_count; + mcan_rxfifo_config_t rxfifo_config = { .reg_val = 0 }; + rxfifo_config.start_addr = start_addr; + rxfifo_config.watermark = 1U; + rxfifo_config.operation_mode = config->rxfifos[i].operation_mode; + rxfifo_config.fifo_size = elem_count; + mcan_config_rxfifo(ptr, i, rxfifo_config.reg_val); + + if (i == 0) { + rx_fifo_buf_elem_config.fifo0_data_field_size = config->rxfifos[i].data_field_size; + } else { + rx_fifo_buf_elem_config.fifo1_data_field_size = config->rxfifos[i].data_field_size; + } + + start_addr += elem_bytes * elem_count; + } else { + mcan_config_rxfifo(ptr, i, MCAN_RAM_ADDR_INVALID); + if (i == 0) { + rx_fifo_buf_elem_config.fifo0_data_field_size = 0; + } else { + rx_fifo_buf_elem_config.fifo1_data_field_size = 0; + } + } + } + + if (config->enable_rxbuf) { + elem_bytes = mcan_get_data_field_size(config->rxbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + elem_count = config->rxbuf_elem_count; + ptr->RXBC = start_addr; + rx_fifo_buf_elem_config.buf_data_field_size = config->rxbuf_data_field_size; + + start_addr += elem_bytes * elem_count;; + } else { + rx_fifo_buf_elem_config.buf_data_field_size = 0; + ptr->RXBC = MCAN_RAM_ADDR_INVALID; + } + ptr->RXESC = rx_fifo_buf_elem_config.reg_val; + + mcan_txbuf_config_t txbuf_config = { .reg_val = 0 }; + if (config->enable_txbuf) { + txbuf_config.start_addr = start_addr; + txbuf_config.fifo_queue_size = config->txbuf_fifo_or_queue_elem_count; + txbuf_config.dedicated_tx_buf_size = config->txbuf_dedicated_txbuf_elem_count; + txbuf_config.tx_fifo_queue_mode = config->txfifo_or_txqueue_mode; + + elem_count = config->txbuf_fifo_or_queue_elem_count + config->txbuf_dedicated_txbuf_elem_count; + elem_bytes = mcan_get_data_field_size(config->txbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + start_addr += elem_count * elem_bytes; + ptr->TXESC = (uint32_t) config->txbuf_data_field_size; + } else { + ptr->TXESC = MCAN_RAM_ADDR_INVALID; + } + + ptr->TXBC = txbuf_config.reg_val; + + mcan_tx_evt_fifo_config_t txevt_fifo_config = { .reg_val = 0 }; + if (config->enable_tx_evt_fifo) { + elem_bytes = sizeof(mcan_tx_event_fifo_elem_t); + elem_count = config->tx_evt_fifo_elem_count; + txevt_fifo_config.start_addr = start_addr; + txevt_fifo_config.fifo_size = elem_count; + txevt_fifo_config.fifo_watermark = 1U; + ptr->TXEFC = txevt_fifo_config.reg_val; + + start_addr += elem_bytes * elem_count; + } else { + ptr->TXEFC = MCAN_RAM_ADDR_INVALID; + } + + /* Check whether the requested RAM space exceeds the valid RAM range */ + uint32_t requested_ram_size = start_addr - mcan_get_ram_offset(ptr); + if (requested_ram_size > mcan_get_ram_size(ptr)) { + status = status_mcan_ram_out_of_range; + break; + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + do { + if (config->enable_std_filter) { + ptr->SIDFC = config->std_filter_config.reg_val; + } else { + ptr->SIDFC = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_ext_filter) { + ptr->XIDFC = config->ext_filter_config.reg_val; + } else { + ptr->XIDFC = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_rxfifo0) { + ptr->RXF0C = config->rxfifo0_config.reg_val; + } else { + ptr->RXF0C = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_rxfifo1) { + ptr->RXF1C = config->rxfifo1_config.reg_val; + } else { + ptr->RXF1C = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_rxbuf) { + ptr->RXBC = config->rxbuf_config.start_addr; + } else { + ptr->RXBC = MCAN_RAM_ADDR_INVALID; + } + + ptr->RXESC = config->rx_elem_config.reg_val; + if (config->enable_txbuf) { + ptr->TXESC = config->txbuf_elem_config.data_field_size; + } else { + ptr->TXESC = MCAN_RAM_ADDR_INVALID; + } + + ptr->TXBC = config->txbuf_config.reg_val; + + if (config->enable_tx_evt_fifo) { + ptr->TXEFC = config->tx_evt_fifo_config.reg_val; + } else { + ptr->TXEFC = MCAN_RAM_ADDR_INVALID; + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + ptr->XIDAM = config->ext_id_mask; + + ptr->GFC = MCAN_GFC_RRFE_SET(config->global_filter_config.reject_remote_ext_frame) | + MCAN_GFC_RRFS_SET(config->global_filter_config.reject_remote_std_frame) | + MCAN_GFC_ANFE_SET(config->global_filter_config.accept_non_matching_ext_frame_option) | + MCAN_GFC_ANFS_SET(config->global_filter_config.accept_non_matching_std_frame_option); + + uint32_t elem_count = 0; + const mcan_filter_elem_t *elem = NULL; + if (config->ext_id_filter_list.mcan_filter_elem_count > 0) { + elem_count = config->ext_id_filter_list.mcan_filter_elem_count; + elem = config->ext_id_filter_list.filter_elem_list; + for (uint32_t i = 0; i < elem_count; i++) { + if (elem->can_id_type != MCAN_CAN_ID_TYPE_EXTENDED) { + status = status_invalid_argument; + break; + } + + status = mcan_set_filter_element(ptr, elem, i); + if (status != status_success) { + break; + } + ++elem; + } + if (status != status_success) { + break; + } + } + if (config->std_id_filter_list.mcan_filter_elem_count > 0) { + elem_count = config->std_id_filter_list.mcan_filter_elem_count; + elem = config->std_id_filter_list.filter_elem_list; + for (uint32_t i = 0; i < elem_count; i++) { + if (elem->can_id_type != MCAN_CAN_ID_TYPE_STANDARD) { + status = status_invalid_argument; + break; + } + status = mcan_set_filter_element(ptr, elem, i); + if (status != status_success) { + break; + } + ++elem; + } + if (status != status_success) { + break; + } + } + status = status_success; + + } while (false); + + return status; +} + +static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t tscfg = 0; + + if ((config->prescaler < 1U) || (config->prescaler > 256U) || + (config->ext_timebase_src > MCAN_TSU_EXT_TIMEBASE_SRC_MAX)) { + break; + } + + if (config->enable_tsu) { + tscfg |= MCAN_TSCFG_TSUE_MASK; + } + if (config->capture_on_sof) { + tscfg |= MCAN_TSCFG_SCP_MASK; + } + if (config->use_ext_timebase) { + tscfg |= MCAN_TSCFG_TBCS_MASK; + mcan_set_tsu_ext_timebase_src(ptr, config->ext_timebase_src); + } + if (config->enable_64bit_timestamp) { + tscfg |= MCAN_TSCFG_EN64_MASK; + } + + tscfg |= MCAN_TSCFG_TBPRE_SET(config->prescaler - 1U); + + ptr->TSCFG = tscfg; + + status = status_success; + } while (false); + + return status; +} + +static hpm_stat_t mcan_set_internal_timestamp(MCAN_Type *ptr, mcan_internal_timestamp_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((config->counter_prescaler < 1U) || (config->counter_prescaler > 16) || + (config->timestamp_selection > MCAN_TIMESTAMP_SEL_MAX)) { + break; + } + + ptr->TSCC = MCAN_TSCC_TCP_SET(config->counter_prescaler - 1U) | MCAN_TSCC_TSS_SET(config->timestamp_selection); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + ptr->CCCR |= MCAN_CCCR_INIT_MASK; + while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) == 0) { + + } + ptr->CCCR |= MCAN_CCCR_CCE_MASK; + + if (!config->use_lowlevel_timing_setting) { + if (config->enable_canfd) { + status = mcan_set_bit_timing_from_baudrate(ptr, + mcan_bit_timing_canfd_nominal, + src_clk_freq, + config->baudrate, + config->can20_samplepoint_min, + config->can20_samplepoint_max); + HPM_BREAK_IF(status != status_success); + status = mcan_set_bit_timing_from_baudrate(ptr, + mcan_bit_timing_canfd_data, + src_clk_freq, + config->baudrate_fd, + config->canfd_samplepoint_min, + config->canfd_samplepoint_max); + } else { + status = mcan_set_bit_timing_from_baudrate(ptr, + mcan_bit_timing_can2_0, + src_clk_freq, + config->baudrate, + config->can20_samplepoint_min, + config->can20_samplepoint_max); + } + HPM_BREAK_IF(status != status_success); + } else { + mcan_set_can_nominal_bit_timing(ptr, &config->can_timing); + if (config->enable_canfd) { + mcan_set_can_data_bit_timing(ptr, &config->canfd_timing); + } + } + + switch (config->mode) { + default: + case mcan_mode_normal: + ptr->CCCR &= ~(MCAN_CCCR_MON_MASK | MCAN_CCCR_TEST_MASK); + break; + case mcan_mode_loopback_internal: + ptr->CCCR |= MCAN_CCCR_MON_MASK | MCAN_CCCR_TEST_MASK; + ptr->TEST |= MCAN_TEST_LBCK_MASK; + break; + case mcan_mode_loopback_external: + ptr->CCCR |= MCAN_CCCR_TEST_MASK; + ptr->TEST |= MCAN_TEST_LBCK_MASK; + break; + case mcan_mode_listen_only: + ptr->CCCR |= MCAN_CCCR_MON_MASK; + break; + } + + if (config->enable_canfd) { + ptr->CCCR |= MCAN_CCCR_FDOE_MASK | MCAN_CCCR_BRSE_MASK; + } else { + ptr->CCCR &= ~(MCAN_CCCR_FDOE_MASK | MCAN_CCCR_BRSE_MASK); + } + if (config->enable_non_iso_mode) { + ptr->CCCR |= MCAN_CCCR_NISO_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_NISO_MASK; + } + + if (config->enable_transmit_pause) { + ptr->CCCR |= MCAN_CCCR_TXP_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_TXP_MASK; + } + + if (config->disable_protocol_exception_handling) { + ptr->CCCR |= MCAN_CCCR_PXHD_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK; + } + + if (config->enable_wide_message_marker) { + ptr->CCCR |= MCAN_CCCR_WMM_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_WMM_MASK; + } + + if (config->enable_edge_filtering) { + ptr->CCCR |= MCAN_CCCR_EFBI_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; + } + + /* Configure Transmitter Delay Compensation */ + if (config->enable_tdc) { + ptr->DBTP |= MCAN_DBTP_TDC_MASK; + ptr->TDCR &= ~MCAN_TDCR_TDCO_MASK; + uint32_t data_seg1 = MCAN_DBTP_DTSEG1_GET(ptr->DBTP); + uint32_t prescaler = MCAN_DBTP_DSJW_GET(ptr->DBTP); + + uint32_t calc_val = (data_seg1 + 2U) * (prescaler + 1U); + if (calc_val < MCAN_MAX_TDC_OFFSET) { + ptr->TDCR |= MCAN_TDCR_TDCO_SET(calc_val); + } else { + ptr->TDCR |= MCAN_TDCR_TDCO_SET(MCAN_MAX_TDC_OFFSET); + } + } else { + ptr->DBTP &= ~MCAN_DBTP_TDC_MASK; + } + + /* Configure TSU */ + if (config->use_timestamping_unit) { + ptr->CCCR |= MCAN_CCCR_UTSU_MASK; + status = mcan_set_tsu(ptr, &config->tsu_config); + HPM_BREAK_IF(status != status_success); + } else { + ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK; + } + + /* Configure Internal Timestamp */ + status = mcan_set_internal_timestamp(ptr, &config->timestamp_cfg); + HPM_BREAK_IF(status != status_success); + + /* Initialize CAN RAM */ + uint32_t can_ram_size = mcan_get_ram_size(ptr); + uint32_t *ram_base = (uint32_t *) (mcan_get_ram_base(ptr) + mcan_get_ram_offset(ptr)); + for (uint32_t i = 0U; i < can_ram_size / sizeof(uint32_t); i++) { + ram_base[i] = 0UL; + } + status = mcan_config_ram(ptr, &config->ram_config); + HPM_BREAK_IF(status != status_success); + + /* Configure Filters */ + status = mcan_config_all_filters(ptr, &config->all_filters_config); + HPM_BREAK_IF(status != status_success); + + /* Clear all Interrupt Flags */ + mcan_clear_interrupt_flags(ptr, ~0UL); + + ptr->CCCR &= ~MCAN_CCCR_INIT_MASK; + while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) != 0U) { + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (filter_elem == NULL)) { + break; + } + bool is_ext_id = (filter_elem->can_id_type == MCAN_CAN_ID_TYPE_EXTENDED); + + uint32_t ram_offset; + uint32_t filter_elem_size; + uint32_t size_max; + if (is_ext_id) { + ram_offset = MCAN_XIDFC_FLESA_GET(ptr->XIDFC) << MCAN_XIDFC_FLESA_SHIFT; + filter_elem_size = MCAN_FILTER_ELEM_EXT_ID_SIZE; + size_max = MCAN_XIDFC_LSE_GET(ptr->XIDFC); + } else { + ram_offset = MCAN_SIDFC_FLSSA_GET(ptr->SIDFC) << MCAN_SIDFC_FLSSA_SHIFT; + filter_elem_size = MCAN_FILTER_ELEM_STD_ID_SIZE; + size_max = MCAN_SIDFC_LSS_GET(ptr->SIDFC); + } + + if (index >= size_max) { + status = status_mcan_filter_index_out_of_range; + break; + } + + volatile uint32_t *config_start; + config_start = (volatile uint32_t *) (mcan_get_ram_base(ptr) + ram_offset + filter_elem_size * index); + + uint32_t config_words[2] = { 0, 0 }; + if (is_ext_id) { + /* EFEC + EFID1 */ + config_words[0] = ((uint32_t) (filter_elem->filter_config) << 29) | filter_elem->id1; + + /* EFT + ESYNC + EFFID2 */ + config_words[1] = filter_elem->id2; + config_words[1] |= (filter_elem->sync_message != 0) ? (1UL << 29) : 0; + config_words[1] |= ((uint32_t) filter_elem->filter_type) << 30; + + config_start[0] = config_words[0]; + config_start[1] = config_words[1]; + } else { + config_words[0] = (filter_elem->id2 & 0x7FFUL) | ((filter_elem->id1 & 0x7FFU) << 16); + config_words[0] |= (filter_elem->sync_message != 0) ? (1UL << 15) : 0; + config_words[0] |= ((uint32_t) filter_elem->filter_config) << 27; + config_words[0] |= ((uint32_t) filter_elem->filter_type) << 30; + + config_start[0] = config_words[0]; + } + + status = status_success; + + } while (false); + + return status; +} + +static uint32_t mcan_get_rxfifo0_base(MCAN_Type *ptr) +{ + uint32_t rxfifo0_buf_offset = MCAN_RXF0C_F0SA_GET(ptr->RXF0C) << 2; + uint32_t fifo_addr_base = mcan_get_ram_base(ptr) + rxfifo0_buf_offset; + return fifo_addr_base; +} + +static uint32_t mcan_get_rxfifo1_base(MCAN_Type *ptr) +{ + uint32_t rxfifo1_buf_offset = MCAN_RXF1C_F1SA_GET(ptr->RXF1C) << 2; + uint32_t fifo_addr_base = mcan_get_ram_base(ptr) + rxfifo1_buf_offset; + return fifo_addr_base; +} + +static uint32_t mcan_get_rxbuf_elem_addr(MCAN_Type *ptr, uint32_t index) +{ + uint32_t elem_size; + uint32_t elem_size_option = MCAN_RXESC_RBDS_GET(ptr->RXESC); + if (elem_size_option < 5U) { + elem_size = 8U + 4U * elem_size_option; + } else { + elem_size = 32U + (elem_size_option - 5U) * 16U; + } + elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + uint32_t rxbuf_offset = MCAN_RXBC_RBSA_GET(ptr->RXBC) << MCAN_RXBC_RBSA_SHIFT; + + uint32_t rxbuf_addr_base = mcan_get_ram_base(ptr) + rxbuf_offset; + + uint32_t elem_addr = rxbuf_addr_base + elem_size * index; + + return elem_addr; +} + +static uint32_t mcan_get_txbuf_elem_addr(MCAN_Type *ptr, uint32_t index) +{ + uint32_t elem_size; + uint32_t elem_size_option = MCAN_TXESC_TBDS_GET(ptr->TXESC); + if (elem_size_option < 5U) { + elem_size = 8U + 4U * elem_size_option; + } else { + elem_size = 32U + (elem_size_option - 5U) * 16U; + } + elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + uint32_t txbuf_offset = MCAN_TXBC_TBSA_GET(ptr->TXBC) << MCAN_TXBC_TBSA_SHIFT; + + uint32_t txbuf_addr_base = mcan_get_ram_base(ptr) + txbuf_offset; + + uint32_t elem_addr = txbuf_addr_base + elem_size * index; + + return elem_addr; +} + +uint8_t mcan_get_message_size_from_dlc(uint8_t dlc) +{ + uint32_t msg_size; + if (dlc <= 8U) { + msg_size = dlc; + } else if (dlc <= 12U) { + msg_size = 8 + (dlc - 8) * 4; + } else { + msg_size = 32 + (dlc - 13) * 16U; + } + return msg_size; +} + +uint8_t mcan_get_data_field_size(uint8_t data_field_size_option) +{ + uint8_t size_in_bytes = 0; + + switch (data_field_size_option) { + case MCAN_DATA_FIELD_SIZE_8BYTES: + size_in_bytes = 8U; + break; + case MCAN_DATA_FIELD_SIZE_12BYTES: + size_in_bytes = 12U; + break; + case MCAN_DATA_FIELD_SIZE_16BYTES: + size_in_bytes = 16U; + break; + case MCAN_DATA_FIELD_SIZE_20BYTES: + size_in_bytes = 20U; + break; + case MCAN_DATA_FIELD_SIZE_24BYTES: + size_in_bytes = 24U; + break; + case MCAN_DATA_FIELD_SIZE_32BYTES: + size_in_bytes = 32U; + break; + case MCAN_DATA_FIELD_SIZE_48BYTES: + size_in_bytes = 48U; + break; + case MCAN_DATA_FIELD_SIZE_64BYTES: + size_in_bytes = 64U; + break; + default: + /* Invalid option */ + break; + } + return size_in_bytes; +} + +hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + + uint32_t txbuf_index_max = MCAN_TXBC_NDTB_GET(ptr->TXBC); + if (index >= txbuf_index_max) { + status = status_mcan_txbuf_index_out_of_range; + break; + } + + if (!mcan_is_transmit_request_pending(ptr, index)) { + uint32_t *msg_hdr = (uint32_t *) mcan_get_txbuf_elem_addr(ptr, index); + uint32_t *msg_data = msg_hdr + 2; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(tx_frame->dlc) + 3U) / sizeof(uint32_t); + uint32_t *tx_frame_u32 = (uint32_t *) tx_frame; + msg_hdr[0] = tx_frame_u32[0]; + msg_hdr[1] = tx_frame_u32[1]; + + for (uint32_t i = 0; i < msg_size_words; i++) { + msg_data[i] = tx_frame->data_32[i]; + } + + status = status_success; + } else { + status = status_fail; + } + } while (false); + + return status; +} + +hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + if (!mcan_is_txfifo_full(ptr)) { + uint32_t put_index = mcan_get_txfifo_put_index(ptr); + uint32_t *msg_hdr = (uint32_t *) mcan_get_txbuf_elem_addr(ptr, put_index); + uint32_t *msg_data = msg_hdr + 2; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(tx_frame->dlc) + 3U) / sizeof(uint32_t); + uint32_t *tx_frame_u32 = (uint32_t *) tx_frame; + msg_hdr[0] = tx_frame_u32[0]; + msg_hdr[1] = tx_frame_u32[1]; + + for (uint32_t i = 0; i < msg_size_words; i++) { + msg_data[i] = tx_frame->data_32[i]; + } + status = status_success; + } else { + status = status_mcan_txfifo_full; + } + } while (false); + + return status; +} + +hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (rx_frame == NULL)) { + break; + } + + if (!mcan_is_rxbuf_data_available(ptr, index)) { + status = status_mcan_rxbuf_empty; + break; + } + + uint32_t *msg_hdr = (uint32_t *) mcan_get_rxbuf_elem_addr(ptr, index); + uint32_t *msg_data = msg_hdr + 2; + uint32_t *rx_frame_u32 = (uint32_t *) rx_frame; + rx_frame_u32[0] = msg_hdr[0]; + rx_frame_u32[1] = msg_hdr[1]; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(rx_frame->dlc) + 3) / 4; + for (uint32_t i = 0; i < msg_size_words; i++) { + rx_frame->data_32[i] = msg_data[i]; + } + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (rx_frame == NULL)) { + break; + } + + uint32_t base_addr; + uint32_t elem_index; + uint32_t elem_size; + uint32_t elem_size_option; + if (fifo_index == 0) { + uint32_t rxf0s = ptr->RXF0S; + if (MCAN_RXF0S_F0FL_GET(rxf0s) == 0) { + status = status_mcan_rxfifo_empty; + break; + } + base_addr = mcan_get_rxfifo0_base(ptr); + elem_size_option = MCAN_RXESC_F0DS_GET(ptr->RXESC); + elem_index = MCAN_RXF0S_F0GI_GET(rxf0s); + } else { + uint32_t rxf1s = ptr->RXF1S; + if (MCAN_RXF1S_F1FL_GET(rxf1s) == 0) { + status = status_mcan_rxfifo_empty; + break; + } + base_addr = mcan_get_rxfifo1_base(ptr); + elem_size_option = MCAN_RXESC_F1DS_GET(ptr->RXESC); + elem_index = MCAN_RXF1S_F1GI_GET(rxf1s); + } + + + if (elem_size_option < 5U) { + elem_size = 8U + 4U * elem_size_option; + } else { + elem_size = 32U + (elem_size_option - 5U) * 16U; + } + elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + uint32_t elem_addr = base_addr + elem_size * elem_index; + uint32_t *msg_hdr = (uint32_t *) elem_addr; + uint32_t *msg_data = msg_hdr + 2; + uint32_t *rx_frame_u32 = (uint32_t *) rx_frame; + rx_frame_u32[0] = msg_hdr[0]; + rx_frame_u32[1] = msg_hdr[1]; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(rx_frame->dlc) + 3) / 4; + for (uint32_t i = 0; i < msg_size_words; i++) { + rx_frame->data_32[i] = msg_data[i]; + } + + if (fifo_index == 0) { + ptr->RXF0A = MCAN_RXF0S_F0GI_GET(ptr->RXF0S); + } else { + ptr->RXF1A = MCAN_RXF1S_F1GI_GET(ptr->RXF1S); + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (tx_evt == NULL)) { + break; + } + + uint32_t txefs = ptr->TXEFS; + + if (MCAN_TXEFS_EFFL_GET(txefs) == 0U) { + status = status_mcan_tx_evt_fifo_empty; + break; + } + + uint32_t base_addr = mcan_get_ram_base(ptr) + (MCAN_TXEFC_EFSA_GET(ptr->TXEFC) << MCAN_TXEFC_EFSA_SHIFT); + uint32_t elem_size = sizeof(mcan_tx_event_fifo_elem_t); + uint32_t elem_index = MCAN_TXEFS_EFGI_GET(txefs); + + uint32_t elem_addr = base_addr + elem_size * elem_index; + uint32_t *tx_evt_buf = (uint32_t *) elem_addr; + + tx_evt->words[0] = tx_evt_buf[0]; + tx_evt->words[1] = tx_evt_buf[1]; + + ptr->TXEFA = MCAN_TXEFA_EFAI_SET(elem_index); + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + + status = mcan_write_txbuf(ptr, index, tx_frame); + HPM_BREAK_IF(status != status_success); + + mcan_send_add_request(ptr, index); + status = status_success; + + } while (false); + return status; +} + +hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + if (mcan_is_txfifo_full(ptr)) { + status = status_mcan_txfifo_full; + break; + } + + status = mcan_write_txfifo(ptr, tx_frame); + HPM_BREAK_IF(status != status_success); + + uint32_t put_index = mcan_get_txfifo_put_index(ptr); + mcan_send_add_request(ptr, put_index); + + uint32_t retry_cnt = 0; + while (!mcan_is_transmit_occurred(ptr, put_index)) { + retry_cnt++; + if (retry_cnt >= MCAN_TX_RETRY_COUNT_MAX) { + break; + } + } + if (retry_cnt >= MCAN_TX_RETRY_COUNT_MAX) { + status = status_timeout; + } else { + status = status_success; + } + } while (false); + return status; +} + +hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t retry_cnt = 0; + + while (!mcan_is_rxbuf_data_available(ptr, index)) { + retry_cnt++; + if (retry_cnt >= MCAN_RX_RETRY_COUNT_MAX) { + status = status_timeout; + break; + } + } + if (status == status_timeout) { + break; + } + + mcan_clear_rxbuf_data_available_flag(ptr, index); + status = mcan_read_rxbuf(ptr, index, rx_frame); + } while (false); + + return status; +} + +hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t retry_cnt = 0; + uint32_t interrupt_flag = (fifo_index == 0U) ? MCAN_IR_RF0N_MASK : MCAN_IR_RF1N_MASK; + + while (!mcan_is_interrupt_flag_set(ptr, interrupt_flag)) { + retry_cnt++; + if (retry_cnt >= MCAN_RX_RETRY_COUNT_MAX) { + status = status_timeout; + break; + } + } + if (status == status_timeout) { + break; + } + + mcan_clear_interrupt_flags(ptr, interrupt_flag); + status = mcan_read_rxfifo(ptr, fifo_index, rx_frame); + } while (false); + + return status; +} + +void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status) +{ + uint32_t hpms = ptr->HPMS; + status->buffer_index = MCAN_HPMS_BIDX_GET(hpms); + status->filter_index = MCAN_HPMS_FIDX_GET(hpms); + status->filter_list_type = MCAN_HPMS_FLST_GET(hpms); + status->message_storage_indicator = MCAN_HPMS_MSI_GET(hpms); +} + +hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (filter_config == NULL)) { + break; + } + + ptr->GFC = MCAN_GFC_ANFE_SET(filter_config->accept_non_matching_ext_frame_option) | + MCAN_GFC_ANFS_SET(filter_config->accept_non_matching_std_frame_option) | + MCAN_GFC_RRFS_SET(filter_config->reject_remote_std_frame) | + MCAN_GFC_RRFE_SET(filter_config->reject_remote_ext_frame); + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + ptr->TDCR = MCAN_TDCR_TDCO_SET(config->ssp_offset) | MCAN_TDCR_TDCF_SET(config->filter_window_length); + status = status_success; + + } while (false); + return status; +} + +uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index) +{ + uint32_t ts_val = 0U; + if (index < ARRAY_SIZE(ptr->TS_SEL)) { + ts_val = ptr->TS_SEL[index]; + } + return ts_val; +} + +uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index) +{ + uint64_t ts_val = 0U; + uint32_t real_index = index & 0x7U; /* Clear bit3 according to IP design */ + if (index < ARRAY_SIZE(ptr->TS_SEL)) { + ts_val = ((uint64_t) (ptr->TS_SEL[2U * real_index + 1]) << 32U); + ts_val |= ptr->TS_SEL[2U * real_index]; + /* Workaround: dummy read to clear the corresponding bits in TSS1 if the index is equal to/greater than 8 */ + if (index >= 8U) { + (void) ptr->TS_SEL[index]; + } + } + + return ts_val; +} + +hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr, + const mcan_tx_event_fifo_elem_t *tx_evt, + mcan_timestamp_value_t *timestamp) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((ptr == NULL) || (tx_evt == NULL) || (timestamp == NULL)); + + (void) memset(timestamp, 0, sizeof(mcan_timestamp_value_t)); + + bool is_tsu_used = mcan_is_tsu_used(ptr); + if (!is_tsu_used) { + timestamp->is_16bit = true; + timestamp->ts_16bit = tx_evt->tx_timestamp; + } else if (tx_evt->tx_timestamp_captured != 0U) { + bool is_64bit_ts = mcan_is_64bit_tsu_timestamp_used(ptr); + uint32_t ts_index = tx_evt->tx_timestamp_pointer; + if (!is_64bit_ts) { + timestamp->is_32bit = true; + timestamp->ts_32bit = mcan_read_32bit_tsu_timestamp(ptr, ts_index); + } else { + timestamp->is_64bit = true; + timestamp->ts_64bit = mcan_read_64bit_tsu_timestamp(ptr, ts_index); + } + status = status_success; + } else { + status = status_mcan_timestamp_not_exist; + } + + } while (false); + + return status; +} + +hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, + const mcan_rx_message_t *rx_msg, + mcan_timestamp_value_t *timestamp) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((ptr == NULL) || (rx_msg == NULL) || (timestamp == NULL)); + + (void) memset(timestamp, 0, sizeof(mcan_timestamp_value_t)); + + bool is_tsu_used = mcan_is_tsu_used(ptr); + if (!is_tsu_used) { + timestamp->is_16bit = true; + timestamp->ts_16bit = rx_msg->rx_timestamp; + } else if (rx_msg->rx_timestamp_captured != 0U) { + bool is_64bit_ts = mcan_is_64bit_tsu_timestamp_used(ptr); + uint32_t ts_index = rx_msg->rx_timestamp_pointer; + if (!is_64bit_ts) { + timestamp->is_32bit = true; + timestamp->ts_32bit = mcan_read_32bit_tsu_timestamp(ptr, ts_index); + } else { + timestamp->is_64bit = true; + timestamp->ts_64bit = mcan_read_64bit_tsu_timestamp(ptr, ts_index); + } + status = status_success; + } else { + status = status_mcan_timestamp_not_exist; + } + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c index 68cdc573ff..b606cc6a3d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c index 695a56ecc5..d26825b437 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -92,3 +92,13 @@ void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config) | PCFG_RC24M_TRACK_RETURN_SET(config->return_to_default_on_xtal_loss) | PCFG_RC24M_TRACK_TRACK_SET(config->free_run); } + +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv) +{ + hpm_stat_t stat = status_success; + if ((mv < PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV) || (mv > PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV)) { + return status_invalid_argument; + } + ptr->DCDC_LPMODE = (ptr->DCDC_LPMODE & ~PCFG_DCDC_LPMODE_STBY_VOLT_MASK) | PCFG_DCDC_LPMODE_STBY_VOLT_SET(mv); + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c index 087f49bec8..0b2a4fc48f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c index cbadccaafa..cb156fa71a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,8 @@ #include "hpm_pdma_drv.h" #define PDMA_SCALE_FRAC_BITS 12 +/* x_offset might need to be adjusted when scaling YUV format */ +#define PDMA_YUV_SCALE_DEFAULT_X_OFFSET (0x800) void pdma_set_block_size(PDMA_Type *ptr, pdma_blocksize_t size) { @@ -20,18 +22,18 @@ void pdma_enable_plane(PDMA_Type *ptr, pdma_plane_t enable_plane, bool enable) { uint32_t mask; switch (enable_plane) { - case pdma_plane_both: - mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); - break; - case pdma_plane_src: - mask = PDMA_CTRL_P0_EN_MASK; - break; - case pdma_plane_dst: - mask = PDMA_CTRL_P1_EN_MASK; - break; - default: - mask = 0; - break; + case pdma_plane_both: + mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); + break; + case pdma_plane_src: + mask = PDMA_CTRL_P0_EN_MASK; + break; + case pdma_plane_dst: + mask = PDMA_CTRL_P1_EN_MASK; + break; + default: + mask = 0; + break; } if (!mask) { return; @@ -59,7 +61,11 @@ void pdma_get_default_config(PDMA_Type *ptr, pdma_config_t *config, display_pixe config->enable_plane = pdma_plane_src; if (display_pixel_format_is_yuv_format(pixel_format)) { - config->byteorder = display_byteorder_a0a1a2a3; /* change yuv fromat output byte order to YUYV format */ + if (pixel_format == display_pixel_format_ycbcr422) { + config->byteorder = display_byteorder_a2a3a0a1; + } else { + config->byteorder = display_byteorder_a0a1a2a3; + } } else { config->byteorder = display_byteorder_a3a2a1a0; } @@ -88,19 +94,19 @@ void pdma_get_default_plane_config(PDMA_Type *ptr, pdma_plane_config_t *config, config->height = 0; config->pitch = 0; - switch(pixel_format) { - case display_pixel_format_yuv422: - config->ycbcr_mode = false; - config->bypass_colorspace_conversion = false; - break; - case display_pixel_format_ycbcr422: - config->ycbcr_mode = true; - config->bypass_colorspace_conversion = false; - break; - default: - config->ycbcr_mode = false; - config->bypass_colorspace_conversion = true; - break; + switch (pixel_format) { + case display_pixel_format_yuv422: + config->ycbcr_mode = false; + config->bypass_colorspace_conversion = false; + break; + case display_pixel_format_ycbcr422: + config->ycbcr_mode = true; + config->bypass_colorspace_conversion = false; + break; + default: + config->ycbcr_mode = false; + config->bypass_colorspace_conversion = true; + break; } } @@ -108,34 +114,34 @@ void pdma_get_default_yuv2rgb_coef_config(PDMA_Type *ptr, display_yuv2rgb_coef_t { /* Two plane share one YUV2RGB_COEF, not support one plane format is yuv422 and another is ycbcr422 */ - switch(source_format) { - case display_pixel_format_yuv422: - yuv2rgb_coef->c0 = 0x100; - yuv2rgb_coef->uv_offset = 0; - yuv2rgb_coef->y_offset = 0; - yuv2rgb_coef->c1 = 0x123; - yuv2rgb_coef->c2 = 0x76B; - yuv2rgb_coef->c3 = 0x79C; - yuv2rgb_coef->c4 = 0x208; - break; - case display_pixel_format_ycbcr422: - yuv2rgb_coef->c0 = 0x12A; - yuv2rgb_coef->uv_offset = 0x180; - yuv2rgb_coef->y_offset = 0x1F0; - yuv2rgb_coef->c1 = 0x198; - yuv2rgb_coef->c2 = 0x730; - yuv2rgb_coef->c3 = 0x79C; - yuv2rgb_coef->c4 = 0x204; - break; - default: - yuv2rgb_coef->c0 = 0; - yuv2rgb_coef->uv_offset = 0; - yuv2rgb_coef->y_offset = 0; - yuv2rgb_coef->c1 = 0; - yuv2rgb_coef->c2 = 0; - yuv2rgb_coef->c3 = 0; - yuv2rgb_coef->c4 = 0; - break; + switch (source_format) { + case display_pixel_format_yuv422: + yuv2rgb_coef->c0 = 0x100; + yuv2rgb_coef->uv_offset = 0; + yuv2rgb_coef->y_offset = 0; + yuv2rgb_coef->c1 = 0x123; + yuv2rgb_coef->c2 = 0x76B; + yuv2rgb_coef->c3 = 0x79C; + yuv2rgb_coef->c4 = 0x208; + break; + case display_pixel_format_ycbcr422: + yuv2rgb_coef->c0 = 0x12A; + yuv2rgb_coef->uv_offset = 0x180; + yuv2rgb_coef->y_offset = 0x1F0; + yuv2rgb_coef->c1 = 0x198; + yuv2rgb_coef->c2 = 0x730; + yuv2rgb_coef->c3 = 0x79C; + yuv2rgb_coef->c4 = 0x204; + break; + default: + yuv2rgb_coef->c0 = 0; + yuv2rgb_coef->uv_offset = 0; + yuv2rgb_coef->y_offset = 0; + yuv2rgb_coef->c1 = 0; + yuv2rgb_coef->c2 = 0; + yuv2rgb_coef->c3 = 0; + yuv2rgb_coef->c4 = 0; + break; } } @@ -159,52 +165,52 @@ void pdma_get_default_output_config(PDMA_Type *ptr, pdma_output_config_t *config config->height = 0; config->pitch = 0; - switch(pixel_format) { - case display_pixel_format_yuv422: - config->rgb2yuv_config.enable = true; - config->rgb2yuv_config.ycbcr_mode = false; - config->rgb2yuv_config.c0 = 0x4D; - config->rgb2yuv_config.uv_offset = 0; - config->rgb2yuv_config.y_offset = 0; - config->rgb2yuv_config.c1 = 0x96; - config->rgb2yuv_config.c2 = 0x1D; - config->rgb2yuv_config.c3 = 0x7DA; - config->rgb2yuv_config.c4 = 0x7B6; - config->rgb2yuv_config.c5 = 0x70; - config->rgb2yuv_config.c6 = 0x9D; - config->rgb2yuv_config.c7 = 0x77C; - config->rgb2yuv_config.c8 = 0x7E6; - break; - case display_pixel_format_ycbcr422: - config->rgb2yuv_config.enable = true; - config->rgb2yuv_config.ycbcr_mode = true; - config->rgb2yuv_config.c0 = 0x42; - config->rgb2yuv_config.uv_offset = 0x80; - config->rgb2yuv_config.y_offset = 0x10; - config->rgb2yuv_config.c1 = 0x81; - config->rgb2yuv_config.c2 = 0x19; - config->rgb2yuv_config.c3 = 0x7DA; - config->rgb2yuv_config.c4 = 0x7B5; - config->rgb2yuv_config.c5 = 0x70; - config->rgb2yuv_config.c6 = 0x70; - config->rgb2yuv_config.c7 = 0x7A2; - config->rgb2yuv_config.c8 = 0x7EE; - break; - default: - config->rgb2yuv_config.enable = false; - config->rgb2yuv_config.ycbcr_mode = false; - config->rgb2yuv_config.c0 = 0; - config->rgb2yuv_config.uv_offset = 0; - config->rgb2yuv_config.y_offset = 0; - config->rgb2yuv_config.c1 = 0; - config->rgb2yuv_config.c2 = 0; - config->rgb2yuv_config.c3 = 0; - config->rgb2yuv_config.c4 = 0; - config->rgb2yuv_config.c5 = 0; - config->rgb2yuv_config.c6 = 0; - config->rgb2yuv_config.c7 = 0; - config->rgb2yuv_config.c8 = 0; - break; + switch (pixel_format) { + case display_pixel_format_yuv422: + config->rgb2yuv_config.enable = true; + config->rgb2yuv_config.ycbcr_mode = false; + config->rgb2yuv_config.c0 = 0x4D; + config->rgb2yuv_config.uv_offset = 0; + config->rgb2yuv_config.y_offset = 0; + config->rgb2yuv_config.c1 = 0x96; + config->rgb2yuv_config.c2 = 0x1D; + config->rgb2yuv_config.c3 = 0x7DA; + config->rgb2yuv_config.c4 = 0x7B6; + config->rgb2yuv_config.c5 = 0x70; + config->rgb2yuv_config.c6 = 0x9D; + config->rgb2yuv_config.c7 = 0x77C; + config->rgb2yuv_config.c8 = 0x7E6; + break; + case display_pixel_format_ycbcr422: + config->rgb2yuv_config.enable = true; + config->rgb2yuv_config.ycbcr_mode = true; + config->rgb2yuv_config.c0 = 0x42; + config->rgb2yuv_config.uv_offset = 0x80; + config->rgb2yuv_config.y_offset = 0x10; + config->rgb2yuv_config.c1 = 0x81; + config->rgb2yuv_config.c2 = 0x19; + config->rgb2yuv_config.c3 = 0x7DA; + config->rgb2yuv_config.c4 = 0x7B5; + config->rgb2yuv_config.c5 = 0x70; + config->rgb2yuv_config.c6 = 0x70; + config->rgb2yuv_config.c7 = 0x7A2; + config->rgb2yuv_config.c8 = 0x7EE; + break; + default: + config->rgb2yuv_config.enable = false; + config->rgb2yuv_config.ycbcr_mode = false; + config->rgb2yuv_config.c0 = 0; + config->rgb2yuv_config.uv_offset = 0; + config->rgb2yuv_config.y_offset = 0; + config->rgb2yuv_config.c1 = 0; + config->rgb2yuv_config.c2 = 0; + config->rgb2yuv_config.c3 = 0; + config->rgb2yuv_config.c4 = 0; + config->rgb2yuv_config.c5 = 0; + config->rgb2yuv_config.c6 = 0; + config->rgb2yuv_config.c7 = 0; + config->rgb2yuv_config.c8 = 0; + break; } } @@ -220,18 +226,18 @@ void pdma_init(PDMA_Type *ptr, pdma_config_t *config) uint32_t mask; pdma_stop(ptr); switch (config->enable_plane) { - case pdma_plane_both: - mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); - break; - case pdma_plane_dst: - mask = PDMA_CTRL_P1_EN_MASK; - break; - case pdma_plane_src: - mask = PDMA_CTRL_P0_EN_MASK; - break; - default: - mask = 0; - break; + case pdma_plane_both: + mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); + break; + case pdma_plane_dst: + mask = PDMA_CTRL_P1_EN_MASK; + break; + case pdma_plane_src: + mask = PDMA_CTRL_P0_EN_MASK; + break; + default: + mask = 0; + break; } if (config->block_size == pdma_blocksize_16x16) { @@ -241,19 +247,19 @@ void pdma_init(PDMA_Type *ptr, pdma_config_t *config) ptr->CTRL = PDMA_CTRL_PACK_DIR_SET(config->byteorder) | mask; } -static uint32_t pdma_pixel_format(display_pixel_format_t display_format) +static uint32_t pdma_pixel_format(display_pixel_format_t display_format, bool is_out_plane) { switch (display_format) { - case display_pixel_format_rgb565: - return 0xE; - case display_pixel_format_argb8888: - return 0; - case display_pixel_format_yuv422: - return 0x13; - case display_pixel_format_ycbcr422: - return 0x13; - default: - return 0; + case display_pixel_format_rgb565: + return 0xE; + case display_pixel_format_argb8888: + return 0; + case display_pixel_format_yuv422: + return 0x13; + case display_pixel_format_ycbcr422: + return is_out_plane ? 0x12 : 0x13; + default: + return 0; } } @@ -274,7 +280,7 @@ void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_ if (plane_dst != NULL) { assert((plane_dst->bypass_colorspace_conversion) || (yuv2rgb != NULL)); } - if ((plane_src != NULL) || (plane_dst != NULL)) { + if ((plane_src != NULL) && (plane_dst != NULL)) { assert(!(display_pixel_format_is_yuv_format(plane_src->pixel_format) && display_pixel_format_is_yuv_format(plane_dst->pixel_format)) || (plane_src->pixel_format == plane_dst->pixel_format)); } @@ -285,7 +291,7 @@ void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_ } else { pitch = plane_src->pitch; } - format = pdma_pixel_format(plane_src->pixel_format); + format = pdma_pixel_format(plane_src->pixel_format, false); ptr->PS[pdma_plane_src].BUF = PDMA_PS_BUF_ADDR_SET((uint32_t) plane_src->buffer); ptr->PS[pdma_plane_src].PITCH = PDMA_PS_PITCH_BYTELEN_SET(pitch); ptr->PS[pdma_plane_src].BKGD = PDMA_PS_BKGD_COLOR_SET(plane_src->background); @@ -303,7 +309,7 @@ void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_ | PDMA_PS_CTRL_YCBCR_MODE_SET(plane_src->ycbcr_mode) | PDMA_PS_CTRL_BYPASS_SET(plane_src->bypass_colorspace_conversion) | ((plane_src->flip << PDMA_PS_CTRL_HFLIP_SHIFT) - & (PDMA_PS_CTRL_VFLIP_MASK| PDMA_PS_CTRL_HFLIP_MASK)) + & (PDMA_PS_CTRL_VFLIP_MASK | PDMA_PS_CTRL_HFLIP_MASK)) | PDMA_PS_CTRL_ROTATE_SET(plane_src->rotate) | PDMA_PS_CTRL_DECY_SET(plane_src->y_dec) | PDMA_PS_CTRL_DECX_SET(plane_src->x_dec) @@ -317,7 +323,7 @@ void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_ } else { pitch = plane_dst->pitch; } - format = pdma_pixel_format(plane_dst->pixel_format); + format = pdma_pixel_format(plane_dst->pixel_format, false); ptr->PS[pdma_plane_dst].BUF = PDMA_PS_BUF_ADDR_SET((uint32_t) plane_dst->buffer); ptr->PS[pdma_plane_dst].PITCH = PDMA_PS_PITCH_BYTELEN_SET(pitch); ptr->PS[pdma_plane_dst].BKGD = PDMA_PS_BKGD_COLOR_SET(plane_dst->background); @@ -335,7 +341,7 @@ void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_ | PDMA_PS_CTRL_YCBCR_MODE_SET(plane_dst->ycbcr_mode) | PDMA_PS_CTRL_BYPASS_SET(plane_dst->bypass_colorspace_conversion) | ((plane_dst->flip << PDMA_PS_CTRL_HFLIP_SHIFT) - & (PDMA_PS_CTRL_VFLIP_MASK| PDMA_PS_CTRL_HFLIP_MASK)) + & (PDMA_PS_CTRL_VFLIP_MASK | PDMA_PS_CTRL_HFLIP_MASK)) | PDMA_PS_CTRL_ROTATE_SET(plane_dst->rotate) | PDMA_PS_CTRL_DECY_SET(plane_dst->y_dec) | PDMA_PS_CTRL_DECX_SET(plane_dst->x_dec) @@ -343,7 +349,7 @@ void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_ | PDMA_PS_CTRL_FORMAT_SET(format); } - if(yuv2rgb != NULL) { + if (yuv2rgb != NULL) { ptr->YUV2RGB_COEF0 = PDMA_YUV2RGB_COEF0_C0_SET(yuv2rgb->c0) | PDMA_YUV2RGB_COEF0_UV_OFFSET_SET(yuv2rgb->uv_offset) | PDMA_YUV2RGB_COEF0_Y_OFFSET_SET(yuv2rgb->y_offset); @@ -365,7 +371,7 @@ void pdma_config_output(PDMA_Type *ptr, pdma_output_config_t *config) } else { pitch = config->pitch; } - format = pdma_pixel_format(config->pixel_format); + format = pdma_pixel_format(config->pixel_format, true); ptr->OUT_BUF = PDMA_OUT_BUF_ADDR_SET((uint32_t) config->buffer); ptr->OUT_PITCH = PDMA_OUT_PITCH_BYTELEN_SET(pitch); ptr->OUT_LRC = PDMA_OUT_LRC_X_SET(config->width) @@ -440,9 +446,9 @@ hpm_stat_t pdma_fill_color(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, display_yuv2rgb_coef_t yuv2rgb_coef; pdma_output_config_t output; - if (((display_pixel_format_is_yuv_format(format)) && (width & 2)) + if (((display_pixel_format_is_yuv_format(format)) && (width & 1)) || !(width > 8 || height > 8)) { - return status_invalid_argument; + return status_invalid_argument; } pdma_get_default_config(ptr, &config, format); @@ -488,7 +494,7 @@ hpm_stat_t pdma_fill_color(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, hpm_stat_t stat; do { stat = pdma_check_status(ptr, status); - } while((stat != status_pdma_done) && (stat != status_pdma_error)); + } while ((stat != status_pdma_done) && (stat != status_pdma_error)); pdma_stop(ptr); return stat; } @@ -509,8 +515,8 @@ hpm_stat_t pdma_flip_rotate(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, pdma_output_config_t output; if ((width + x > dst_width) - /* YUV422 requires width to be 2-byte aligned */ - || ((display_pixel_format_is_yuv_format(format)) && (width & 2)) + /* YUV422 requires width to be 2-pixel aligned */ + || ((display_pixel_format_is_yuv_format(format)) && (width & 1)) || !(width > 8 || height > 8)) { return status_invalid_argument; } @@ -573,7 +579,7 @@ hpm_stat_t pdma_flip_rotate(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, hpm_stat_t stat; do { stat = pdma_check_status(ptr, status); - } while((stat != status_pdma_done) && (stat != status_pdma_error)); + } while ((stat != status_pdma_done) && (stat != status_pdma_error)); pdma_stop(ptr); return stat; } @@ -595,8 +601,8 @@ hpm_stat_t pdma_blit(PDMA_Type *ptr, pdma_output_config_t output; if ((width + x > dst_width) - /* YUV422 requires width to be 2-byte aligned */ - || ((display_pixel_format_is_yuv_format(format)) && (width & 2)) + /* YUV422 requires width to be 2-pixel aligned */ + || ((display_pixel_format_is_yuv_format(format)) && (width & 1)) || !(width > 8 || height > 8)) { return status_invalid_argument; } @@ -653,7 +659,7 @@ hpm_stat_t pdma_blit(PDMA_Type *ptr, hpm_stat_t stat; do { stat = pdma_check_status(ptr, status); - } while((stat != status_pdma_done) && (stat != status_pdma_error)); + } while ((stat != status_pdma_done) && (stat != status_pdma_error)); pdma_stop(ptr); return stat; } @@ -667,14 +673,14 @@ static void pdma_calculate_scale(uint32_t t, uint32_t target_t, tmp = ((t << PDMA_SCALE_FRAC_BITS) / target_t) >> PDMA_SCALE_FRAC_BITS; if (tmp >= 16) { *dec = pdma_decimation_by_8; - *scale = 2; + *scale = 2U << PDMA_SCALE_FRAC_BITS; return; } - if (tmp >= 8) { + if (tmp > 8) { *dec = pdma_decimation_by_8; - } else if (tmp >= 4) { + } else if (tmp > 4) { *dec = pdma_decimation_by_4; - } else if (tmp >= 2) { + } else if (tmp > 2) { *dec = pdma_decimation_by_2; } else { *dec = pdma_decimation_by_1; @@ -702,9 +708,9 @@ hpm_stat_t pdma_scale(PDMA_Type *ptr, display_yuv2rgb_coef_t yuv2rgb_coef; pdma_output_config_t output; - if ((width + x > dst_width) - /* YUV422 requires width to be 2-byte aligned */ - || ((display_pixel_format_is_yuv_format(format)) && (width & 2)) + if ((target_width + x > dst_width) + /* YUV422 requires width to be 2-pixel aligned */ + || ((display_pixel_format_is_yuv_format(format)) && (width & 1)) || !(width > 8 || height > 8)) { return status_invalid_argument; } @@ -730,12 +736,16 @@ hpm_stat_t pdma_scale(PDMA_Type *ptr, pdma_calculate_scale(width, target_width, &dec, &scale); plane_src.x_scale = scale; - plane_src.x_dec = dec, + plane_src.x_dec = dec; pdma_calculate_scale(height, target_height, &dec, &scale); plane_src.y_scale = scale; - plane_src.y_dec = dec, + plane_src.y_dec = dec; plane_src.background = 0x00FFFFFF; + if (display_pixel_format_is_yuv_format(format)) { + plane_src.x_offset = PDMA_YUV_SCALE_DEFAULT_X_OFFSET; + } + plane_dst.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); plane_dst.width = width; plane_dst.height = height; @@ -768,7 +778,7 @@ hpm_stat_t pdma_scale(PDMA_Type *ptr, hpm_stat_t stat; do { stat = pdma_check_status(ptr, status); - } while((stat != status_pdma_done) && (stat != status_pdma_error)); + } while ((stat != status_pdma_done) && (stat != status_pdma_error)); pdma_stop(ptr); return stat; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c new file mode 100644 index 0000000000..ef835894aa --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc_feature.h" +#include "hpm_pla_drv.h" + +void pla_set_aoi_16to8_one_channel(PLA_Type *pla, + pla_aoi_16to8_chn_cfg_t *cfg) +{ + uint8_t i; + uint32_t value; + + value = 0; + for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) { + value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1); + } + pla->CHN[cfg->chn].AOI_16TO8[cfg->aoi_16to8_chn] = value; +} + +void pla_get_aoi_16to8_one_channel(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_chn_cfg_t *cfg) +{ + uint8_t i; + + for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (i << 1)) & 0x03; + } +} + +void pla_set_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg) +{ + uint8_t i; + uint32_t value; + + value = 0; + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1); + } + switch (cfg->aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_1: + pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_2: + pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_3: + pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_4: + pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_5: + pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_6: + pla->CHN[cfg->chn].AOI_8TO7_06 = value; + break; + default: + break; + } +} + +void pla_get_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg) +{ + uint8_t i; + + switch (cfg->aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 1)) & 0x03; + } + break; + case pla_aoi_8to7_chn_1: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 17)) & 0x03; + } + break; + case pla_aoi_8to7_chn_2: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 1)) & 0x03; + } + break; + case pla_aoi_8to7_chn_3: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 17)) & 0x03; + } + break; + case pla_aoi_8to7_chn_4: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 1)) & 0x03; + } + break; + case pla_aoi_8to7_chn_5: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 17)) & 0x03; + } + break; + case pla_aoi_8to7_chn_6: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_06 >> (i << 1)) & 0x03; + } + break; + default: + break; + } +} + +void pla_set_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_cfg_unit_t *cfg) +{ + uint32_t value; + + value = ((uint32_t)cfg->op) << (cfg->signal << 1); + switch (aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_1: + pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_2: + pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_3: + pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_4: + pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_5: + pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_6: + pla->CHN[chn].AOI_8TO7_06 = value; + break; + default: + break; + } +} + +void pla_get_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_input_signal_type_t signal, + pla_aoi_8to7_cfg_unit_t *cfg) +{ + + switch (aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 1)) & 0x03; + break; + case pla_aoi_8to7_chn_1: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 17)) & 0x03; + break; + case pla_aoi_8to7_chn_2: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 1)) & 0x03; + break; + case pla_aoi_8to7_chn_3: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 17)) & 0x03; + break; + case pla_aoi_8to7_chn_4: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 1)) & 0x03; + break; + case pla_aoi_8to7_chn_5: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 17)) & 0x03; + break; + case pla_aoi_8to7_chn_6: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_06 >> (signal << 1)) & 0x03; + break; + default: + break; + } +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c index 7e5c002a86..e261a3572f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c index bb60f4694c..7ba66efbe1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,10 @@ #include "hpm_pllctlv2_drv.h" + +#define PLLCTLV2_PLL_MFN_FACTOR (10U) /*!< PLLCTLV2 PLL MFN Factor */ +#define PLLCTLV2_PLL_MFD_DEFAULT (240UL * 1000000UL) /*!< PLLCTLV2 PLL Default MFD value */ + #define PLLCTLV2_PLL_MFI_MIN (16U) #define PLLCTLV2_PLL_MFI_MAX (42U) #define PLLCTLV2_PLL_XTAL_FREQ (24000000UL) @@ -16,20 +20,27 @@ hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz) { + hpm_stat_t status; if ((ptr == NULL) || (freq_in_hz < PLLCTLV2_PLL_FREQ_MIN) || (freq_in_hz > PLLCTLV2_PLL_FREQ_MAX) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - return status_invalid_argument; + status = status_invalid_argument; + } else { + uint32_t mfn = freq_in_hz % PLLCTLV2_PLL_XTAL_FREQ; + uint32_t mfi = freq_in_hz / PLLCTLV2_PLL_XTAL_FREQ; + + if (PLLCTLV2_PLL_MFI_MFI_GET(ptr->PLL[pll].MFI) == mfi) { + ptr->PLL[pll].MFI = mfi - 1U; + } + + ptr->PLL[pll].MFI = mfi; + /* + * NOTE: Default MFD value is 240M + */ + ptr->PLL[pll].MFN = mfn * PLLCTLV2_PLL_MFN_FACTOR; + + status = status_success; } - - uint32_t mfn = freq_in_hz % PLLCTLV2_PLL_XTAL_FREQ; - uint32_t mfi = freq_in_hz / PLLCTLV2_PLL_XTAL_FREQ; - - ptr->PLL[pll].MFI = mfi; - ptr->PLL[pll].MFN = mfn * 10UL; - - while (!pllctlv2_pll_is_stable(ptr, pll)) { - } - return status_success; + return status; } void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop) @@ -54,8 +65,8 @@ void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, ui { if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { ptr->PLL[pll].DIV[div_index] = - (ptr->PLL[pll].DIV[div_index] & PLLCTLV2_DIV_DIV_MASK) | PLLCTLV2_DIV_DIV_SET(div_value) | - PLLCTLV2_DIV_ENABLE_MASK; + (ptr->PLL[pll].DIV[div_index] & ~PLLCTLV2_PLL_DIV_DIV_MASK) | PLLCTLV2_PLL_DIV_DIV_SET(div_value) | + PLLCTLV2_PLL_DIV_ENABLE_MASK; } } @@ -75,9 +86,9 @@ uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, ui { uint32_t postdiv_freq = 0; if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { - uint32_t postdiv = PLLCTLV2_DIV_DIV_GET(ptr->PLL[pll].DIV[div_index]); + uint32_t postdiv = PLLCTLV2_PLL_DIV_DIV_GET(ptr->PLL[pll].DIV[div_index]); uint32_t pll_freq = pllctlv2_get_pll_freq_in_hz(ptr, pll); - postdiv_freq = (uint32_t) (pll_freq / (1 + postdiv * 1.0 / 5)); + postdiv_freq = (uint32_t) (pll_freq / (1U + postdiv * 1.0 / 5U)); } return postdiv_freq; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c index 1e2f41cc81..cb66dd02ea 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -328,6 +328,36 @@ uint32_t read_pma_addr(uint32_t idx) return ret_val; } +hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF((entry == NULL) || (entry_index > 15U)); + + uint32_t idx = entry_index / 4; + uint32_t offset = (entry_index * 8) & 0x1F; + + uint32_t pmp_cfg = read_pmp_cfg(idx); + pmp_cfg &= ~(0xFFUL << offset); + pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; + uint32_t pma_cfg = read_pma_cfg(idx); + pma_cfg &= ~(0xFFUL << offset); + pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; + + write_pmp_addr(entry->pmp_addr, entry_index); + write_pma_addr(entry->pma_addr, entry_index); + + write_pma_cfg(pma_cfg, idx); + write_pmp_cfg(pmp_cfg, idx); + fencei(); + + status = status_success; + + } while (false); + + return status; +} + hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries) { hpm_stat_t status = status_invalid_argument; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c index 7ca8226907..689035e2d1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c index 91373418cd..fa94e2a4fe 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -25,11 +25,11 @@ void pwm_get_captured_count(PWM_Type *pwm_x, uint32_t *buf, pwm_counter_type_t c { uint32_t i; if (counter == pwm_counter_type_capture_falling_edge) { - for (i = start_index; i < num; i++) { + for (i = start_index; i < start_index + num; i++) { *buf = pwm_x->CAPNEG[i]; } } else { - for (i = start_index; i < num; i++) { + for (i = start_index; i < start_index + num; i++) { *buf = pwm_x->CAPPOS[i]; } } @@ -40,6 +40,10 @@ void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config) config->mode = pwm_cmp_mode_output_compare; config->update_trigger = pwm_shadow_register_update_on_modify; config->enable_ex_cmp = false; +#if PWM_SOC_HRPWM_SUPPORT + config->enable_hrcmp = false; + config->hrcmp = 0; +#endif config->cmp = 0; config->ex_cmp = 0; config->half_clock_cmp = 0; @@ -151,4 +155,31 @@ hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_inde pwm_cmp_update_cmp_value(pwm_x, cmp1_index, target_cmp1, 0); pwm_cmp_update_cmp_value(pwm_x, cmp2_index, target_cmp2, 0); return status_success; -} \ No newline at end of file +} +#if PWM_SOC_HRPWM_SUPPORT + +hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp, + uint16_t target_hrcmp) +{ + pwm_shadow_register_unlock(pwm_x); + pwm_cmp_update_hrcmp_value(pwm_x, cmp_index, target_cmp, target_hrcmp); + return status_success; +} + +hpm_stat_t pwm_update_raw_hrcmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, + uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2, + uint16_t target_hrcmp1, uint16_t target_hrcmp2) +{ + uint32_t reload = PWM_RLD_RLD_GET(pwm_x->RLD); + if (!target_cmp1) { + target_cmp1 = reload + 1; + } + if (!target_cmp2) { + target_cmp2 = reload + 1; + } + pwm_shadow_register_unlock(pwm_x); + pwm_cmp_update_hrcmp_value(pwm_x, cmp1_index, target_cmp1, target_hrcmp1); + pwm_cmp_update_hrcmp_value(pwm_x, cmp2_index, target_cmp2, target_hrcmp2); + return status_success; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c index 72c3da50de..d0efa75103 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c index ab71612036..68d230c907 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,10 +9,6 @@ #include "hpm_rtc_drv.h" -#define RTC_ALARM_TYPE_ONE_SHOT (0U) -#define RTC_ALARM_TYPE_PERIODIC (1U) - - hpm_stat_t rtc_config_time(RTC_Type *base, time_t time) { base->SECOND = (uint32_t)time; @@ -28,32 +24,39 @@ time_t rtc_get_time(RTC_Type *base) hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config) { hpm_stat_t status = status_invalid_argument; - do{ - if ((config == NULL) || (config->index > 1U) || (config->type > RTC_ALARM_TYPE_PERIODIC)) { + do { + if ((config == NULL) || (config->index > 1U) || (config->type > RTC_ALARM_TYPE_ABSOLUTE_TIME_ONE_SHOT)) { break; } uint32_t alarm_inc = 0; - uint32_t current_sec = base->SECOND; - uint32_t alarm = current_sec + config->period; + uint32_t alarm; if (config->type == RTC_ALARM_TYPE_ONE_SHOT) { - alarm_inc = 0; - } - else { + uint32_t current_sec = base->SECOND; + alarm = current_sec + config->period; + if (alarm < current_sec) { + break; + } + } else if (config->type == RTC_ALARM_TYPE_PERIODIC) { + uint32_t current_sec = base->SECOND; alarm_inc = config->period; - } - if (alarm < current_sec) { - break; + alarm = current_sec + config->period; + if (alarm < current_sec) { + break; + } + } else { + alarm = config->period; } if (config->index == 0U) { base->ALARM0 = alarm; base->ALARM0_INC = alarm_inc; - } - else { + } else { base->ALARM1 = alarm; base->ALARM1_INC = alarm_inc; } - }while(false); + + status = status_success; + } while (false); return status; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c new file mode 100644 index 0000000000..1d5a0f72f2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sdm_drv.h" + +#ifndef HPM_LIN_DRV_RETRY_COUNT +#define HPM_LIN_DRV_RETRY_COUNT (5000U) +#endif + + +void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control) +{ + control->clk_signal_sync = true; + control->data_signal_sync = true; + control->interrupt_en = false; +} + +void sdm_init_module(SDM_Type *ptr, sdm_control_t *control) +{ + /* software reset */ + ptr->CTRL |= SDM_CTRL_SFTRST_MASK; + ptr->CTRL &= ~SDM_CTRL_SFTRST_MASK; + + ptr->CTRL |= SDM_CTRL_SYNC_MCLK_SET(control->clk_signal_sync) + | SDM_CTRL_SYNC_MDAT_SET(control->data_signal_sync) + | SDM_CTRL_IE_SET(control->interrupt_en); +} + +void sdm_get_channel_common_setting(SDM_Type *ptr, sdm_channel_common_config_t *config) +{ + config->sampling_mode = sdm_sampling_rising_clk_edge; + config->enable_err_interrupt = false; + config->enable_data_ready_interrupt = false; +} + +void sdm_config_channel_common_setting(SDM_Type *ptr, uint8_t ch_index, sdm_channel_common_config_t *config) +{ + if (config->enable_err_interrupt) { + ptr->INT_EN |= CHN_ERR_MASK(ch_index); + } + + if (config->enable_data_ready_interrupt) { + ptr->INT_EN |= CHN_DRY_MASK(ch_index); + } + + ptr->CTRL &= ~CHN_SAMPLING_MODE_MASK(ch_index); + ptr->CTRL |= config->sampling_mode << CHN_SAMPLING_MODE_SHIFT(ch_index); +} + +void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *filter_config) +{ + filter_config->fifo_threshold = 8; + filter_config->en_fifo_threshold_int = true; + filter_config->manchester_threshold = 0; + filter_config->wdg_threshold = 255; + filter_config->en_af_int = 0; + filter_config->en_data_overflow_int = 1; + filter_config->en_cic_data_saturation_int = 1; + filter_config->en_data_ready_int = 1; + filter_config->sync_source = 0; + filter_config->fifo_clean_on_sync = 0; + filter_config->wtsynaclr = 0; + filter_config->wtsynmclr = 0; + filter_config->wtsyncen = 0; + filter_config->output_32bit = 1; + filter_config->data_ready_flag_by_fifo = 1; + filter_config->enable = 1; + + filter_config->filter_type = sdm_filter_sinc1; + filter_config->pwm_signal_sync = 0; + filter_config->output_offset = 0; + filter_config->oversampling_rate = 32; /**< 1- 256 */ + filter_config->ignore_invalid_samples = 0; +} + +void sdm_get_channel_default_comparator_config(SDM_Type *ptr, sdm_comparator_config_t *cmp_config) +{ + cmp_config->high_threshold = 0xffff; + cmp_config->zero_cross_threshold = 0xffff; + cmp_config->low_threshold = 0x0; + + cmp_config->en_zero_cross_threshold_int = false; + cmp_config->en_clock_invalid_int = false; + cmp_config->en_high_threshold_int = false; + cmp_config->en_low_threshold_int = false; + cmp_config->filter_type = sdm_filter_sinc1; + cmp_config->oversampling_rate = 32; /**< 1-32, when 32, write 0 into bitfield */ + cmp_config->ignore_invalid_samples = 0; + cmp_config->enable = true; +} + +void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_config_t *filter_config) +{ + /* fifo setting */ + ptr->CH[ch_index].SDFIFOCTRL = SDM_CH_SDFIFOCTRL_THRSH_SET(filter_config->fifo_threshold) + | SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(filter_config->en_fifo_threshold_int); + + ptr->CH[ch_index].SDCTRLE = SDM_CH_SDCTRLE_SGD_ORDR_SET(filter_config->filter_type) + | SDM_CH_SDCTRLE_PWMSYNC_SET(filter_config->pwm_signal_sync) + | SDM_CH_SDCTRLE_CIC_SCL_SET(filter_config->output_offset) + | SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(filter_config->oversampling_rate - 1) + | SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(filter_config->ignore_invalid_samples); + + ptr->CH[ch_index].SDCTRLP = SDM_CH_SDCTRLP_MANCH_THR_SET(filter_config->manchester_threshold) + | SDM_CH_SDCTRLP_WDOG_THR_SET(filter_config->wdg_threshold) + | SDM_CH_SDCTRLP_AF_IE_SET(filter_config->en_af_int) + | SDM_CH_SDCTRLP_DFFOVIE_SET(filter_config->en_data_overflow_int) + | SDM_CH_SDCTRLP_DSATIE_SET(filter_config->en_cic_data_saturation_int) + | SDM_CH_SDCTRLP_DRIE_SET(filter_config->en_data_ready_int) + | SDM_CH_SDCTRLP_SYNCSEL_SET(filter_config->sync_source) + | SDM_CH_SDCTRLP_FFSYNCCLREN_SET(filter_config->fifo_clean_on_sync) + | SDM_CH_SDCTRLP_WTSYNACLR_SET(filter_config->wtsynaclr) + | SDM_CH_SDCTRLP_WTSYNMCLR_SET(filter_config->wtsynmclr) + | SDM_CH_SDCTRLP_WTSYNCEN_SET(filter_config->wtsyncen) + | SDM_CH_SDCTRLP_D32_SET(filter_config->output_32bit) + | SDM_CH_SDCTRLP_DR_OPT_SET(filter_config->data_ready_flag_by_fifo); + + ptr->CH[ch_index].SDCTRLP |= SDM_CH_SDCTRLP_EN_SET(filter_config->enable); +} + +void sdm_config_channel_comparator(SDM_Type *ptr, uint8_t ch_index, sdm_comparator_config_t *cmp_config) +{ + ptr->CH[ch_index].SCHTL = cmp_config->high_threshold; + ptr->CH[ch_index].SCLLT = cmp_config->low_threshold; + ptr->CH[ch_index].SCHTLZ = cmp_config->zero_cross_threshold; + + ptr->CH[ch_index].SCCTRL = SDM_CH_SCCTRL_HZ_EN_SET(cmp_config->en_zero_cross_threshold_int) + | SDM_CH_SCCTRL_MF_IE_SET(cmp_config->en_clock_invalid_int) + | SDM_CH_SCCTRL_HL_IE_SET(cmp_config->en_high_threshold_int) + | SDM_CH_SCCTRL_LL_IE_SET(cmp_config->en_low_threshold_int) + | SDM_CH_SCCTRL_SGD_ORDR_SET(cmp_config->filter_type) + | SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(cmp_config->oversampling_rate) + | SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(cmp_config->ignore_invalid_samples); + + ptr->CH[ch_index].SCCTRL |= SDM_CH_SCCTRL_EN_SET(cmp_config->enable); +} + +hpm_stat_t sdm_receive_one_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint8_t data_len_in_bytes) +{ + uint32_t retry = 0; + int32_t output; + + while (!sdm_get_channel_data_ready_status(ptr, ch_index)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + if (using_fifo) { + output = ptr->CH[ch_index].SDFIFO; + } else { + output = ptr->CH[ch_index].SDATA; + } + + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + *(data++) = (int8_t)(output >> (i * 8)); + } + + return status_success; +} + +hpm_stat_t sdm_receive_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint32_t count, uint8_t data_len_in_bytes) +{ + for (uint32_t i = 0; i < count; i++) { + if (status_success != sdm_receive_one_filter_data(ptr, ch_index, using_fifo, data, data_len_in_bytes)) { + return status_fail; + } + + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + data++; + } + } + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c index 34ea15f765..97e102d027 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -32,14 +32,17 @@ #define AES_CTR_BLOCK_UNIT (16U) typedef enum { - sdp_state_hash_init, - sdp_state_hash_update, + sdp_state_hash_init, sdp_state_hash_update, } sdp_hash_alg_state_t; #define AES_BLOCK_SIZE (16U) #define HASH_BLOCK_SIZE (64U) #define HASH_DIGEST_SIZE_MAX (32) +#define SDP_CRYPTO_ALG_IDX_AES128 (0U) +#define SDP_CRYPTO_ALG_IDX_AES256 (1U) +#define SDP_CRYPTO_ALG_IDX_SM4 (8U) + typedef struct { union { uint32_t words[HASH_BLOCK_SIZE / sizeof(uint32_t)]; @@ -74,7 +77,8 @@ static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes); static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num); -static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, +static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t input_len, const uint8_t *iv, @@ -86,14 +90,17 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *mac, uint32_t mac_len); -static void aes_ccm_format_b0(uint8_t *block, const uint8_t *iv, uint32_t iv_len, uint32_t mac_len, uint32_t aad_len, +static void aes_ccm_format_b0(uint8_t *block, + const uint8_t *iv, + uint32_t iv_len, + uint32_t mac_len, + uint32_t aad_len, uint32_t input_len); static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len); static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len); - /*********************************************************************************************************************** * Codes **********************************************************************************************************************/ @@ -105,23 +112,17 @@ hpm_stat_t sdp_wait_done(SDP_Type *base) sdp_sta = base->STA; if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRSET_MASK)) { status = status_sdp_error_setup; - } - else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRPKT_MASK)) { + } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRPKT_MASK)) { status = status_sdp_error_packet; - } - else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRSRC_MASK)) { + } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRSRC_MASK)) { status = status_sdp_error_src; - } - else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRDST_MASK)) { + } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRDST_MASK)) { status = status_sdp_error_dst; - } - else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRHAS_MASK)) { + } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRHAS_MASK)) { status = status_sdp_error_hash; - } - else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRCHAIN_MASK)) { + } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRCHAIN_MASK)) { status = status_sdp_error_chain; - } - else { + } else { status = status_success; } } while (IS_HPM_BITMASK_CLR(sdp_sta, SDP_STA_PKTCNT0_MASK)); @@ -141,7 +142,6 @@ hpm_stat_t sdp_init(SDP_Type *base) return status; } - hpm_stat_t sdp_deinit(SDP_Type *base) { hpm_stat_t status = status_invalid_argument; @@ -152,7 +152,10 @@ hpm_stat_t sdp_deinit(SDP_Type *base) return status; } -hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, +hpm_stat_t sdp_aes_set_key(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, uint32_t key_idx) { union { @@ -164,7 +167,7 @@ hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t hpm_stat_t status = status_invalid_argument; do { - //TODO: AES_KEY index validity check + aes_ctx->crypto_algo = sdp_crypto_alg_aes; if (IS_HPM_BITMASK_SET(base->SDPCR, SDP_SDPCR_CIPDIS_MASK)) { status = status_sdp_no_crypto_support; @@ -187,12 +190,10 @@ hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t base->KEYDAT = aes_key.words[idx++]; } } - } - else if ((key_idx >= AES_KEY_SRC_KEYMAN_START_IDX) && (key_idx <= AES256_KEY_SRC_KEYMAN_END_IDX)) { + } else if ((key_idx >= AES_KEY_SRC_KEYMAN_START_IDX) && (key_idx <= AES256_KEY_SRC_KEYMAN_END_IDX)) { key128_idx = (key_idx - AES_KEY_SRC_KEYMAN_START_IDX) * 2U + AES_KEY_SRC_KEYMAN_START_IDX; } - } - else { + } else { if (key_idx <= AES128_KEY_SRC_SDP_END_IDX) { (void) memcpy(aes_key.bytes, key, 16); base->KEYADDR = SDP_KEYADDR_INDEX_SET(key_idx); @@ -211,7 +212,32 @@ hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t return status; } -hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +hpm_stat_t sdp_sm4_set_key(SDP_Type *base, + sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx) +{ + hpm_stat_t status = status_invalid_argument; + if (key_bits != sdp_sm4_keybits_128) { + return status; + } + status = sdp_aes_set_key(base, sm4_ctx, key, (sdp_aes_key_bits_t) key_bits, key_idx); + if (status != status_success) { + return status; + } + sm4_ctx->crypto_algo = sdp_crypto_alg_sm4; + + return status; +} +#endif + +hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, uint8_t *out) { assert((base != NULL) && (aes_ctx != NULL)); @@ -219,7 +245,7 @@ hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ hpm_stat_t status; base->SDPCR = SDP_SDPCR_CIPHEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; base->PKTSRC = (uint32_t) in; @@ -236,17 +262,28 @@ hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ #endif sdp_clear_error_status(base); - if (aes_ctx->key_bits == sdp_aes_keybits_128) { - base->MODCTRL = SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op); + if (aes_ctx->crypto_algo == sdp_crypto_alg_aes) { + if (aes_ctx->key_bits == sdp_aes_keybits_128) { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES128) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op); + } else { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES256) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op); + } } +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + else if (aes_ctx->crypto_algo == sdp_crypto_alg_sm4) { + base->MODCTRL = SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_SM4) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op); + } +#endif else { - base->MODCTRL = SDP_MODCTRL_AESALG_SET(1) - | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op); + return status_sdp_invalid_alg; } -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -258,8 +295,13 @@ hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ return status; } -hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, - const uint8_t iv[16], const uint8_t *input, uint8_t *output) +hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + const uint8_t iv[16], + const uint8_t *input, + uint8_t *output) { assert((base != NULL) && (aes_ctx != NULL)); assert((op <= sdp_aes_op_decrypt) && (input != NULL) && (output != NULL)); @@ -267,7 +309,7 @@ hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ hpm_stat_t status; base->SDPCR = SDP_SDPCR_CIPHEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKT_CTRL_CIPHIV_MASK; base->PKTSRC = (uint32_t) input; @@ -284,25 +326,35 @@ hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ sdp_clear_error_status(base); - if (aes_ctx->key_bits == sdp_aes_keybits_128) { - base->MODCTRL = SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op) - | SDP_MODCTRL_AESMOD_SET(1); - } else { - base->MODCTRL = SDP_MODCTRL_AESALG_SET(1) - | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op) - | SDP_MODCTRL_AESMOD_SET(1); + if (aes_ctx->crypto_algo == sdp_crypto_alg_aes) { + if (aes_ctx->key_bits == sdp_aes_keybits_128) { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES128) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); + } else { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES256) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); + } + } +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + else if (aes_ctx->crypto_algo == sdp_crypto_alg_sm4) { + base->MODCTRL = SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_SM4) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); + } +#endif + else { + return status_sdp_invalid_alg; } - // Set IV, copy the IV to the context first in case the IV address is not 32-bit aligned + /* Set IV, copy the IV to the context first in case the IV address is not 32-bit aligned */ uint32_t iv_32[4]; (void) memcpy(iv_32, iv, 16); for (uint32_t i = 0; i < 4; i++) { base->CIPHIV[i] = iv_32[i]; } (void) memset(iv_32, 0, sizeof(iv_32)); -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -327,17 +379,21 @@ static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes) } } -hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_counter, uint8_t *input, - uint8_t *output, uint32_t length) +hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint8_t *nonce_counter, + uint8_t *input, + uint8_t *output, + uint32_t length) { hpm_stat_t status = status_invalid_argument; do { HPM_BREAK_IF( - (base == NULL) || (aes_ctx == NULL) || (nonce_counter == NULL) || (input == NULL) || (output == NULL)); + (base == NULL) || (aes_ctx == NULL) || (nonce_counter == NULL) || (input == NULL) || (output == NULL)); uint32_t calc_len; - uint8_t *cipher_nonce = (uint8_t*)&aes_ctx->buf3; + uint8_t *cipher_nonce = (uint8_t *) &aes_ctx->buf3; while (length > 0) { calc_len = (length < 16U) ? length : 16U; status = sdp_aes_crypt_ecb(base, aes_ctx, sdp_aes_op_encrypt, 16, nonce_counter, cipher_nonce); @@ -385,7 +441,11 @@ static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num) * byte (16-q...15) input length * */ -static void aes_ccm_format_b0(uint8_t *block, const uint8_t *iv, uint32_t iv_len, uint32_t mac_len, uint32_t aad_len, +static void aes_ccm_format_b0(uint8_t *block, + const uint8_t *iv, + uint32_t iv_len, + uint32_t mac_len, + uint32_t aad_len, uint32_t input_len) { uint8_t q = 15U - iv_len; @@ -420,8 +480,8 @@ static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len) (void) memcpy(ctr + 1U, iv, iv_len); } - -static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, +static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t input_len, const uint8_t *iv, @@ -460,7 +520,8 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, /* - * Follow A2.2.2 in NIST Special Publication 800-38C, only supports up to 2^32 bytes*/ + * Follow A2.2.2 in NIST Special Publication 800-38C, only supports up to 2^32 bytes + */ if (aad_len > 0U) { uint32_t calc_len = 0U; const uint8_t *aad_src = aad; @@ -473,8 +534,7 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_to_be(b, 2, aad_len); calc_len = MIN(remaining_len, 14U); (void) memcpy(&b[2], aad_src, calc_len); - } - else { + } else { b[0] = 0xFFU; b[1] = 0xFEU; uint32_to_be(&b[6], 4, calc_len); @@ -553,15 +613,32 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, return status; } -hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, uint8_t *tag, uint32_t tag_len) +hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len) { - return aes_ccm_auth_crypt(base, aes_ctx, sdp_aes_op_encrypt, input_len, iv, iv_len, aad, aad_len, input, output, - tag, tag_len); + return aes_ccm_auth_crypt(base, + aes_ctx, + sdp_aes_op_encrypt, + input_len, + iv, + iv_len, + aad, + aad_len, + input, + output, + tag, + tag_len); } - static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len) { uint8_t result = 0U; @@ -578,9 +655,17 @@ static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t return result; } -hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, const uint8_t *tag, uint32_t tag_len) +hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len) { hpm_stat_t status; @@ -588,13 +673,22 @@ hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, ui uint32_t calc_mac[4]; - status = aes_ccm_auth_crypt(base, aes_ctx, sdp_aes_op_decrypt, input_len, iv, iv_len, aad, aad_len, input, - output, (uint8_t *) &calc_mac, tag_len); + status = aes_ccm_auth_crypt(base, + aes_ctx, + sdp_aes_op_decrypt, + input_len, + iv, + iv_len, + aad, + aad_len, + input, + output, + (uint8_t *) &calc_mac, + tag_len); HPM_BREAK_IF(status != status_success); if (sdp_constant_time_cmp(calc_mac, tag, tag_len) != 0U) { status = status_sdp_error_invalid_mac; - } - else { + } else { status = status_success; } @@ -612,7 +706,7 @@ hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_ break; } - // Initialize the SDP HASH context + /* Initialize the SDP HASH context */ sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; (void) memset(ctx_internal, 0, sizeof(*ctx_internal)); ctx_internal->alg = alg; @@ -635,7 +729,6 @@ static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_c ctx_internal->hash_finish = false; } - static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size) { sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &ctx->internal; @@ -653,7 +746,7 @@ static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, } base->SDPCR = SDP_SDPCR_HASHEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->NPKTPTR = 0UL; base->PKTCTL = pkt_ctrl; @@ -672,7 +765,7 @@ static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, sdp_clear_error_status(base); base->MODCTRL = SDP_MODCTRL_HASALG_SET(ctx_internal->alg); -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -689,7 +782,7 @@ static hpm_stat_t sdp_hash_process_message(SDP_Type *base, sdp_hash_ctx_t *ctx, hpm_stat_t status = status_invalid_argument; sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &ctx->internal; - // If there is partially filled internal buffer, fill it to full block + /* If there is partially filled internal buffer, fill it to full block */ if (ctx_internal->blk_size > 0U) { uint32_t size_to_copy = HASH_BLOCK_SIZE - ctx_internal->blk_size; (void) memcpy(&ctx_internal->block.bytes[ctx_internal->blk_size], msg, size_to_copy); @@ -703,7 +796,7 @@ static hpm_stat_t sdp_hash_process_message(SDP_Type *base, sdp_hash_ctx_t *ctx, } } - // Process all full blocks in message + /* Process all full blocks in message */ uint32_t full_blk_size = (msg_size >> 6) << 6; if (full_blk_size > 0U) { status = sdp_hash_internal_update(base, ctx, msg, full_blk_size); @@ -739,8 +832,7 @@ hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8 ctx_internal->blk_size += length; status = status_success; break; - } - else { + } else { if (ctx_internal->state != sdp_state_hash_update) { sdp_hash_internal_engine_init(base, hash_ctx); ctx_internal->state = sdp_state_hash_update; @@ -793,6 +885,9 @@ hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *di } break; case sdp_hash_alg_sha256: +#if defined(SDP_HAS_SM3_SUPPORT) && (SDP_HAS_SM3_SUPPORT == 1) + case sdp_hash_alg_sm3: +#endif copy_bytes = SHA256_DIGEST_SIZE_IN_BYTES; digest_words = copy_bytes / sizeof(uint32_t); for (uint32_t i = 0; i < digest_words; i++) { @@ -800,7 +895,7 @@ hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *di } break; default: - // Never reach here + /* Never reach here */ break; } (void) memcpy(digest, ctx_internal->running_hash, copy_bytes); @@ -819,7 +914,7 @@ hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const v } base->SDPCR = SDP_SDPCR_MCPEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->NPKTPTR = 0; base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKTCTL_PKTTAG_SET(1); @@ -838,7 +933,7 @@ hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const v sdp_clear_error_status(base); base->MODCTRL = 0; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -854,11 +949,11 @@ hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t { hpm_stat_t status; - uint32_t pattern_32 = - (pattern) | ((uint32_t) pattern << 8) | ((uint32_t) pattern << 16) | ((uint32_t) pattern << 24); + uint32_t + pattern_32 = (pattern) | ((uint32_t) pattern << 8) | ((uint32_t) pattern << 16) | ((uint32_t) pattern << 24); base->SDPCR = SDP_SDPCR_CONFEN_MASK; - #if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; base->PKTSRC = (uint32_t) pattern_32; @@ -875,7 +970,7 @@ hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t sdp_clear_error_status(base); base->MODCTRL = 0; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c index df3520c794..3e4d96e481 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,8 +7,6 @@ #include "hpm_sdxc_drv.h" - - #define SDXC_DMA_MAX_XFER_LEN_26BIT ((1UL << 26) - 4U) #define SDXC_DMA_MAX_XFER_LEN_16BIT ((1UL << 16) - 4U) @@ -30,13 +28,13 @@ static const uint32_t s_sdxc_boot_dummy = 0; static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags, uint32_t block_size, uint32_t block_cnt, uint32_t *new_flags); -static uint32_t sdxc_read_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words); +static void sdxc_read_data_buf(SDXC_Type *base, uint32_t *data, uint32_t num_of_words); -static hpm_stat_t sdxc_read_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data); +static hpm_stat_t sdxc_read_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data); -static uint32_t sdxc_write_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words); +static void sdxc_write_data_buf(SDXC_Type *base, const uint32_t *data, uint32_t num_of_words); -static hpm_stat_t sdxc_write_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data); +static hpm_stat_t sdxc_write_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data); static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data, bool enable_dma); @@ -48,9 +46,9 @@ static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags, uint32_t block_size, uint32_t block_cnt, uint32_t *new_flags) { uint32_t flags = base->CMD_XFER & ~(SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | - SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK | - SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | - SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK); + SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK | + SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | + SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK); if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CMD_INHIBIT_MASK)) { return status_sdxc_busy; } else { @@ -107,8 +105,8 @@ hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd) if (cmd->resp_type == sdxc_dev_resp_r2) { /* R3-R2-R1-R0 (lowest 8 bits are invalid bits) has the same format as R2 format in SD spec - * after removing internal CRC7 and end bit - */ + * after removing internal CRC7 and end bit + */ cmd->response[0] = (base->RESP[0] << 8); cmd->response[1] = (base->RESP[1] << 8) | (base->RESP[0] >> 24); cmd->response[2] = (base->RESP[2] << 8) | (base->RESP[1] >> 24); @@ -123,7 +121,7 @@ hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd) /* check response flag */ if ((cmd->resp_error_flags != 0U) && ((cmd->resp_type == sdxc_dev_resp_r1) || (cmd->resp_type == sdxc_dev_resp_r1b) || - (cmd->resp_type == sdxc_dev_resp_r6) || (cmd->resp_type == sdxc_dev_resp_r5))) { + (cmd->resp_type == sdxc_dev_resp_r6) || (cmd->resp_type == sdxc_dev_resp_r5))) { if ((cmd->resp_error_flags & cmd->response[0]) != 0U) { status = status_sdxc_send_cmd_failed; } @@ -132,131 +130,122 @@ hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd) return status; } -static uint32_t sdxc_read_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words) +static void sdxc_read_data_buf(SDXC_Type *base, uint32_t *data, uint32_t num_of_words) { - uint32_t total_words = 0U; + if (sdxc_is_data_buf_readable(base)) { + for (uint32_t i = 0; i < num_of_words; i++) { + data[i] = sdxc_read_data(base); + } + } +} - if (IS_HPM_BITMASK_CLR(base->CMD_XFER, SDXC_CMD_XFER_DMA_ENABLE_MASK)) { +static hpm_stat_t sdxc_read_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data) +{ + uint32_t interrupt_status = 0; + hpm_stat_t status = status_success; + do { + /* For multi-block transfer, the block size must be 4-byte aligned */ + if ((data->block_cnt > 1) && (data->block_size % sizeof(uint32_t) != 0)) { + status = status_invalid_argument; + break; + } if (data->block_size % sizeof(uint32_t) != 0U) { data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); } - total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); - uint32_t i = 0; - while (i < total_words) { - data->rx_data[transferred_words++] = sdxc_read_data(base); - i++; - } - } - return transferred_words; -} + uint32_t words_per_block = data->block_size / sizeof(uint32_t); + uint32_t remaining_blocks = data->block_cnt; + uint32_t *read_buf = data->rx_data; + while (remaining_blocks > 0) { + uint32_t status_flags = SDXC_INT_STAT_BUF_RD_READY_MASK | SDXC_STS_DATA_ERR; + /* Wait until data is ready or timeout event occurs */ + do { + interrupt_status = sdxc_get_interrupt_status(base); + } while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)); -static hpm_stat_t sdxc_read_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data) -{ - uint32_t total_words = 0; - uint32_t transferred_words = 0; - uint32_t interrupt_status = 0; - hpm_stat_t status = status_success; - - if (data->block_size % sizeof(uint32_t) != 0U) { - data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); - } - - total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); - - uint32_t status_flags = SDXC_INT_STAT_BUF_RD_READY_MASK | SDXC_STS_DATA_ERR | SDXC_INT_STAT_TUNING_ERR_MASK; - while ((status == status_success) && (transferred_words < total_words)) { - while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)) { - interrupt_status = sdxc_get_interrupt_status(base); - } - - if ((data->data_type == (uint8_t) sdxc_xfer_data_tuning) && - IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_BUF_RD_READY_MASK)) { - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); - return status_success; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_TUNING_ERR_MASK); - status = status_sdxc_tuning_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_DATA_ERR)) { - if (!data->enable_ignore_error) { - status = status_fail; + if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_CRC_ERR_MASK)) { + /* Handle Data CRC error */ + if (!data->enable_ignore_error) { + status = status_sdxc_data_crc_error; + break; + } + sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { + /* Handle Data timeout error */ + status = status_sdxc_data_timeout_error; + break; + } else { + /* Receive data block by block */ + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); + sdxc_read_data_buf(base, read_buf, words_per_block); + read_buf += words_per_block; + remaining_blocks--; } - sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); - } else { - // Do nothing } - if (status == status_success) { - transferred_words = sdxc_read_data_port(base, data, transferred_words); - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); - interrupt_status = 0; - } - } - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK); + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK); + + } while (false); return status; } -static uint32_t sdxc_write_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words) +static void sdxc_write_data_buf(SDXC_Type *base, const uint32_t *data, uint32_t num_of_words) { - uint32_t total_words = 0; + if (sdxc_is_data_buf_writable(base)) { + for (uint32_t i = 0; i < num_of_words; i++) { + sdxc_write_data(base, data[i]); + } + } +} - if (!IS_HPM_BITMASK_SET(base->CMD_XFER, SDXC_CMD_XFER_DMA_ENABLE_MASK)) { +static hpm_stat_t sdxc_write_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data) +{ + uint32_t interrupt_status = 0; + hpm_stat_t status = status_success; + do { + /* For multi-block transfer, the block size must be 4-byte aligned */ + if ((data->block_cnt > 1) && (data->block_size % sizeof(uint32_t) != 0)) { + status = status_invalid_argument; + break; + } if (data->block_size % sizeof(uint32_t) != 0U) { data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); } - total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); + uint32_t words_per_block = data->block_size / sizeof(uint32_t); + uint32_t remaining_blocks = data->block_cnt; + const uint32_t *write_buf = data->tx_data; + while (remaining_blocks > 0) { + uint32_t status_flags = SDXC_INT_STAT_BUF_WR_READY_MASK | SDXC_STS_DATA_ERR; + /* Wait until write data is allowed or timeout event occurs */ + do { + interrupt_status = sdxc_get_interrupt_status(base); + } while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)); - uint32_t i = 0; - while (i < total_words) { - sdxc_write_data(base, data->tx_data[transferred_words++]); - ++i; - } - } - - return transferred_words; -} - -static hpm_stat_t sdxc_write_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data) -{ - uint32_t total_words = 0; - uint32_t transferred_words = 0; - uint32_t interrupt_status = 0; - - hpm_stat_t status = status_success; - - if (data->block_size % sizeof(uint32_t) != 0U) { - data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); - } - - total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); - - uint32_t status_flags = SDXC_INT_STAT_BUF_WR_READY_MASK | SDXC_STS_DATA_ERR | SDXC_INT_STAT_TUNING_ERR_MASK; - while ((status == status_success) && (transferred_words < total_words)) { - - while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)) { - interrupt_status = sdxc_get_interrupt_status(base); - } - - if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { - return status_sdxc_tuning_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_DATA_ERR)) { - if (!data->enable_ignore_error) { - status = status_fail; + if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_CRC_ERR_MASK)) { + /* Handle Data CRC error */ + if (!data->enable_ignore_error) { + status = status_sdxc_data_crc_error; + break; + } + sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { + /* Handle Data timeout error */ + status = status_sdxc_data_timeout_error; + break; + } else { + /* Receive data block by block */ + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_WR_READY_MASK); + sdxc_write_data_buf(base, write_buf, words_per_block); + write_buf += words_per_block; + remaining_blocks--; } - sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); - } else { - // DO nothing } - if (status == status_success) { - transferred_words = sdxc_write_data_port(base, data, transferred_words); - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_WR_READY_MASK); - interrupt_status = 0; - } - } - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_STS_DATA_ERR); + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK); + + } while (false); return status; } @@ -306,23 +295,23 @@ hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd) if ((cmd->resp_type == sdxc_dev_resp_r1) || (cmd->resp_type == sdxc_dev_resp_r5) || (cmd->resp_type == sdxc_dev_resp_r6) || (cmd->resp_type == sdxc_dev_resp_r7)) { flags |= SDXC_CMD_RESP_LEN_48 | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | - SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK; + SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK; } else if ((cmd->resp_type == sdxc_dev_resp_r1b) || (cmd->resp_type == sdxc_dev_resp_r5b)) { flags |= SDXC_CMD_RESP_LEN_48B | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | - SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK; + SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK; } else if (cmd->resp_type == sdxc_dev_resp_r2) { flags |= SDXC_CMD_RESP_LEN_136 | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK; } else if ((cmd->resp_type == sdxc_dev_resp_r3) || (cmd->resp_type == sdxc_dev_resp_r4)) { flags |= SDXC_CMD_RESP_LEN_48; } else { - // do nothing + /* do nothing */ } if (IS_HPM_BITMASK_SET(flags, SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK)) { flags |= SDXC_CMD_XFER_RESP_INT_DISABLE_MASK; } } - switch(cmd->cmd_type) { + switch (cmd->cmd_type) { case sdxc_cmd_type_abort_cmd: flags |= SDXC_CMD_TYPE_ABORT; break; @@ -338,18 +327,19 @@ hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd) } cmd_xfer &= ~(SDXC_CMD_XFER_CMD_INDEX_MASK | SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK - | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | - SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | - SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | - SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK); + | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | + SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | + SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | + SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK); cmd_xfer |= SDXC_CMD_XFER_CMD_INDEX_SET(cmd->cmd_index) | - ((flags & (SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK - | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | - SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | - SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | - SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_MASK | - SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK))); + ((flags & (SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK + | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | + SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | + SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | + SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | + SDXC_CMD_XFER_RESP_TYPE_MASK | + SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK))); base->CMD_ARG = cmd->cmd_argument; base->CMD_XFER = cmd_xfer; @@ -404,7 +394,7 @@ hpm_stat_t sdxc_parse_interrupt_status(SDXC_Type *base) status = status_sdxc_response_error; } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_BOOT_ACK_ERR_MASK)) { status = status_sdxc_boot_ack_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CARD_REMOVAL_MASK)) { + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CARD_REMOVAL_MASK)) { status = status_sdxc_card_removed; } else { status = status_sdxc_error; @@ -463,7 +453,7 @@ static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data status = status_sdxc_transfer_data_failed; } } else { - // Do nothing + /* Do nothing */ } if ((data->data_type == (uint8_t) sdxc_xfer_data_boot_continuous) && (status == status_success)) { @@ -473,12 +463,12 @@ static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data } else { if (data->rx_data != NULL) { - status = sdxc_read_by_data_port_blocking(base, data); + status = sdxc_read_via_data_buf_blocking(base, data); if (status != status_success) { return status; } } else { - status = sdxc_write_by_data_port_blocking(base, data); + status = sdxc_write_via_data_buf_blocking(base, data); if (status != status_success) { return status; } @@ -497,13 +487,13 @@ void sdxc_init(SDXC_Type *base, const sdxc_config_t *config) prot_ctrl &= ~(SDXC_PROT_CTRL_DMA_SEL_MASK | SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK); - prot_ctrl |= (1UL << 8); + prot_ctrl |= SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK; sdxc_set_data_timeout(base, config->data_timeout, NULL); base->PROT_CTRL = prot_ctrl; - // Enable SD internal clock and the output clock + /* Enable SD internal clock and the output clock */ base->SYS_CTRL |= SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK; while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)) { @@ -527,12 +517,12 @@ void sdxc_init(SDXC_Type *base, const sdxc_config_t *config) void sdxc_set_data_timeout(SDXC_Type *base, uint32_t timeout_in_ms, uint32_t *actual_timeout_ms) { static uint32_t pre_calc_timeout_list[15] = { - 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, - 32768,65536, 131072 + 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, + 32768, 65536, 131072 }; uint32_t field_value = 0; - for(uint32_t i = 0; i < ARRAY_SIZE(pre_calc_timeout_list); i++) { + for (uint32_t i = 0; i < ARRAY_SIZE(pre_calc_timeout_list); i++) { if (timeout_in_ms < pre_calc_timeout_list[i]) { field_value = i; break; @@ -562,12 +552,12 @@ void sdxc_set_mmc_boot_config(SDXC_Type *base, const sdxc_boot_config_t *config) emmc_boot_reg |= SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK; } - //TODO: Auto stop at block gap, how to handle this? + /* TODO: Auto stop at block gap, how to handle this? */ uint32_t block_attr_reg = base->BLK_ATTR & ~(SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK | SDXC_BLK_ATTR_BLOCK_CNT_MASK); block_attr_reg |= SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(config->block_size) | - SDXC_BLK_ATTR_BLOCK_CNT_SET(config->block_cnt); + SDXC_BLK_ATTR_BLOCK_CNT_SET(config->block_cnt); base->BLK_ATTR = block_attr_reg; base->EMMC_BOOT_CTRL = emmc_boot_reg; @@ -602,7 +592,7 @@ hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, con base->ADMA_SYS_ADDR = (uint32_t) dma_cfg->adma_table; } - // Set DMA mode + /* Set DMA mode */ uint32_t sys_ctl = base->SYS_CTRL; base->PROT_CTRL = (base->PROT_CTRL & ~SDXC_PROT_CTRL_DMA_SEL_MASK) | SDXC_PROT_CTRL_DMA_SEL_SET(dma_cfg->dma_type); base->SYS_CTRL = sys_ctl; @@ -647,7 +637,7 @@ hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, uint32_t adma_table_words, co start_idx = i; - //add one entry as dummy entry + /* add one entry as dummy entry */ min_entries += 1U; } @@ -718,7 +708,7 @@ hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, sdxc_adma_config_t *dma_c status = sdxc_set_adma2_desc(dma_cfg->adma_table, dma_cfg->adma_table_words, data, block_size, flags); } else if (dma_cfg->dma_type == sdxc_dmasel_adma2_or_3) { - //TODO: To be implemented + /* TODO: To be implemented */ } else { status = status_invalid_argument; @@ -746,7 +736,7 @@ bool sdxc_reset(SDXC_Type *base, sdxc_sw_reset_type_t reset_type, uint32_t timeo reset_mask = SDXC_SYS_CTRL_SW_RST_DAT_MASK; break; default: - // Do nothing + /* Do nothing */ break; } base->SYS_CTRL |= reset_mask; @@ -765,7 +755,7 @@ void sdxc_select_voltage(SDXC_Type *base, sdxc_bus_voltage_option_t option) uint32_t option_u32 = (uint32_t) option; base->PROT_CTRL = (base->PROT_CTRL & ~SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) | - SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(option_u32); + SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(option_u32); if ((option == sdxc_bus_voltage_sd_1v8) || (option == sdxc_bus_voltage_emmc_1v8)) { base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; @@ -796,7 +786,7 @@ void sdxc_set_data_bus_width(SDXC_Type *base, sdxc_bus_width_t width) } else if (width == sdxc_bus_width_8bit) { host_ctrl |= SDXC_PROT_CTRL_EXT_DAT_XFER_SET(1U); } else { - // Do nothing + /* Do nothing */ } base->PROT_CTRL = host_ctrl; @@ -823,7 +813,7 @@ void sdxc_set_speed_mode(SDXC_Type *base, sdxc_speed_mode_t mode) uint32_t mode_u32 = (uint32_t) mode; base->AC_HOST_CTRL = (base->AC_HOST_CTRL & ~SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) | - SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(mode_u32); + SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(mode_u32); if ((mode_u32 & 0xFU) > sdxc_sd_speed_sdr12) { base->PROT_CTRL |= SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; } else { @@ -836,7 +826,6 @@ hpm_stat_t sdxc_transfer_nonblocking(SDXC_Type *base, sdxc_adma_config_t *dma_co hpm_stat_t status = status_invalid_argument; sdxc_command_t *cmd = xfer->command; sdxc_data_t *data = xfer->data; - bool enable_tuning = ((data == NULL)) ? false : (data->data_type == (uint8_t) sdxc_xfer_data_tuning); uint32_t xfer_flags = (uint32_t) sdxc_cmd_only; uint32_t block_size = 0U; @@ -851,7 +840,7 @@ hpm_stat_t sdxc_transfer_nonblocking(SDXC_Type *base, sdxc_adma_config_t *dma_co uint32_t new_xfer_flags = 0; if (data != NULL) { - if ((dma_config != NULL) && (!enable_tuning)) { + if (dma_config != NULL) { uint32_t flags = IS_HPM_BITMASK_SET(data->data_type, sdxc_xfer_data_boot) ? sdxc_adma_desc_multi_flag : sdxc_adma_desc_single_flag; status = sdxc_set_adma_table_config(base, dma_config, data, flags); @@ -916,7 +905,7 @@ hpm_stat_t sdxc_error_recovery(SDXC_Type *base) hpm_stat_t status = status_success; /* D8, D3-D0 of ERROR_INT_STAT */ uint32_t cmdline_err_mask = - SDXC_INT_STAT_AUTO_CMD_ERR_MASK | SDXC_INT_STAT_CMD_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK | + SDXC_INT_STAT_AUTO_CMD_ERR_MASK | SDXC_INT_STAT_CMD_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK | SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK; if ((base->INT_STAT & cmdline_err_mask) != 0U) { @@ -946,7 +935,7 @@ hpm_stat_t sdxc_error_recovery(SDXC_Type *base) /* Check D9, D6-D4 in ERR_INT_STAT */ uint32_t dataline_err_mask = - SDXC_INT_STAT_ADMA_ERR_MASK | SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_DATA_CRC_ERR_MASK | + SDXC_INT_STAT_ADMA_ERR_MASK | SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_DATA_CRC_ERR_MASK | SDXC_INT_STAT_DATA_END_BIT_ERR_MASK; if ((base->INT_STAT & dataline_err_mask) != 0U) { @@ -993,7 +982,8 @@ hpm_stat_t sdxc_perform_tuning_flow_sequence(SDXC_Type *base, uint8_t tuning_cmd base->BLK_ATTR = block_size; base->SDMASA = 1; sdxc_send_command(base, &cmd); - while (!IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_BUF_RD_READY_MASK)) {} + while (!IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_BUF_RD_READY_MASK)) { + } sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); } while (IS_HPM_BITMASK_SET(base->AC_HOST_CTRL, SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK)); @@ -1091,7 +1081,12 @@ hpm_stat_t sdxc_perform_software_tuning(SDXC_Type *base, uint8_t tuning_cmd) hpm_stat_t sdxc_perform_auto_tuning(SDXC_Type *base, uint8_t tuning_cmd) { + bool need_inverse = sdxc_is_inverse_clock_enabled(base); + sdxc_enable_inverse_clock(base, false); + sdxc_enable_sd_clock(base, false); sdxc_enable_auto_tuning(base, true); + sdxc_enable_inverse_clock(base, need_inverse); + sdxc_enable_sd_clock(base, true); return sdxc_perform_tuning_flow_sequence(base, tuning_cmd); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c index 893258e5c0..6a5624f5bb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,12 +13,6 @@ #define HPM_SPI_DRV_DEFAULT_RETRY_COUNT (5000U) #endif -typedef enum { - spi_data_length_8_bits = 7, - spi_data_length_16_bits = 15, - spi_data_length_31_bits = 30 -} spi_data_length_in_bits_t; - hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr) { uint32_t status; @@ -30,7 +24,7 @@ hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr) break; } retry++; - } while(status & SPI_STATUS_SPIACTIVE_MASK); + } while (status & SPI_STATUS_SPIACTIVE_MASK); if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; @@ -50,7 +44,7 @@ hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr) break; } retry++; - } while(!(status & SPI_STATUS_SPIACTIVE_MASK)); + } while (!(status & SPI_STATUS_SPIACTIVE_MASK)); if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; @@ -59,7 +53,7 @@ hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr) return status_success; } -static hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd) +hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd) { if (mode == spi_master_mode) { if (config->master_config.cmd_enable == true) { @@ -67,8 +61,7 @@ static hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, sp return status_invalid_argument; } ptr->CMD = SPI_CMD_CMD_SET(*cmd); - } - else { + } else { ptr->CMD = SPI_CMD_CMD_SET(0xff); /* Write a dummy byte */ } } @@ -76,14 +69,21 @@ static hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, sp return status_success; } -static void spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, uint8_t *cmd) +hpm_stat_t spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd) { if (mode == spi_slave_mode) { - *cmd = (uint8_t)(ptr->CMD & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT; + if (config->slave_config.slave_data_only == false) { + if (cmd == NULL) { + return status_invalid_argument; + } + *cmd = (uint8_t)(ptr->CMD & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT; + } } + + return status_success; } -static hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr) +hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr) { if (mode == spi_master_mode) { if (config->master_config.addr_enable == true) { @@ -97,39 +97,32 @@ static hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, sp return status_success; } -static hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t datalen, uint8_t *buff, uint32_t size) +hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count) { uint32_t status; uint32_t transferred = 0; uint32_t retry = 0; + uint32_t temp; /* check parameter validity */ - if (buff == NULL || size == 0) { + if (buff == NULL || count == 0) { + return status_invalid_argument; + } + + if (data_len_in_bytes > 4 || data_len_in_bytes < 1) { return status_invalid_argument; } /* data transfer */ - while (transferred < size) - { + while (transferred < count) { status = ptr->STATUS; if (!(status & SPI_STATUS_TXFULL_MASK)) { /* write data into the txfifo */ - if (datalen <= spi_data_length_8_bits) { - ptr->DATA = *(uint8_t *)buff & ((1UL << (datalen + 1)) - 1); - buff += sizeof(uint8_t); - } - else if (datalen <= spi_data_length_16_bits) { - ptr->DATA = *(uint16_t *)buff & ((1UL << (datalen + 1)) - 1); - buff += sizeof(uint16_t); - } - else if (datalen <= spi_data_length_31_bits) { - ptr->DATA = *(uint32_t *)buff & ((1UL << (datalen + 1)) - 1); - buff += sizeof(uint32_t); - } - else { - ptr->DATA = *(uint32_t *)buff & 0xffffffff; - buff += sizeof(uint32_t); + temp = 0; + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + temp += *(buff++) << i * 8; } + ptr->DATA = temp; /* transfer count increment */ transferred++; retry = 0; @@ -149,38 +142,30 @@ static hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t datalen, uint8_t *buff, return status_success; } -static hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t datalen, uint8_t *buff, uint32_t size) +hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count) { uint32_t status; uint32_t transferred = 0; uint32_t retry = 0; + uint32_t temp; /* check parameter validity */ - if (buff == NULL || size == 0) { + if (buff == NULL || count == 0) { + return status_invalid_argument; + } + + if (data_len_in_bytes > 4 || data_len_in_bytes < 1) { return status_invalid_argument; } /* data transfer */ - while (transferred < size) - { + while (transferred < count) { status = ptr->STATUS; if (!(status & SPI_STATUS_RXEMPTY_MASK)) { /* read data from the txfifo */ - if (datalen <= spi_data_length_8_bits) { - *(uint8_t *)buff = (uint8_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); - buff += sizeof(uint8_t); - } - else if (datalen <= spi_data_length_16_bits) { - *(uint16_t *)buff = (uint16_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); - buff += sizeof(uint16_t); - } - else if (datalen <= spi_data_length_31_bits) { - *(uint32_t *)buff = (uint32_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); - buff += sizeof(uint32_t); - } - else { - *(uint32_t *)buff = (uint32_t)(ptr->DATA & 0xffffffff); - buff += sizeof(uint32_t); + temp = ptr->DATA; + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + *(buff++) = (uint8_t)(temp >> (i * 8)); } /* transfer count increment */ transferred++; @@ -201,41 +186,35 @@ static hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t datalen, uint8_t *buff, u return status_success; } -static hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t datalen, uint8_t *wbuff, uint32_t wsize, uint8_t *rbuff, uint32_t rsize) +hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount) { uint32_t status; uint32_t wtransferred = 0; uint32_t rtransferred = 0; uint32_t retry = 0; + uint32_t temp; /* check parameter validity */ - if (wbuff == NULL || wsize == 0 || rbuff == NULL || rsize == 0) { + if (wbuff == NULL || wcount == 0 || rbuff == NULL || rcount == 0) { + return status_invalid_argument; + } + + if (data_len_in_bytes > 4 || data_len_in_bytes < 1) { return status_invalid_argument; } /* data transfer */ - while (wtransferred < wsize || rtransferred < rsize) { + while (wtransferred < wcount || rtransferred < rcount) { status = ptr->STATUS; - if (wtransferred < wsize) { + if (wtransferred < wcount) { /* write data into the txfifo */ if (!(status & SPI_STATUS_TXFULL_MASK)) { - if (datalen <= spi_data_length_8_bits) { - ptr->DATA = *(uint8_t *)wbuff & ((1UL << (datalen + 1)) - 1); - wbuff += sizeof(uint8_t); - } - else if (datalen <= spi_data_length_16_bits) { - ptr->DATA = *(uint16_t *)wbuff & ((1UL << (datalen + 1)) - 1); - wbuff += sizeof(uint16_t); - } - else if (datalen <= spi_data_length_31_bits) { - ptr->DATA = *(uint32_t *)wbuff & ((1UL << (datalen + 1)) - 1); - wbuff += sizeof(uint32_t); - } - else { - ptr->DATA = *(uint32_t *)wbuff & 0xffffffff; - wbuff += sizeof(uint32_t); + temp = 0; + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + temp += *(wbuff++) << i * 8; } + ptr->DATA = temp; /* transfer count increment */ wtransferred++; retry = 0; @@ -247,25 +226,12 @@ static hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t datalen, uint8_t *w } } - if (rtransferred < rsize) { + if (rtransferred < rcount) { /* read data from the txfifo */ if (!(status & SPI_STATUS_RXEMPTY_MASK)) { - - if (datalen <= spi_data_length_8_bits) { - *(uint8_t *)rbuff = (uint8_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); - rbuff += sizeof(uint8_t); - } - else if (datalen <= spi_data_length_16_bits) { - *(uint16_t *)rbuff = (uint16_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); - rbuff += sizeof(uint16_t); - } - else if (datalen <= spi_data_length_31_bits) { - *(uint32_t *)rbuff = (uint32_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); - rbuff += sizeof(uint32_t); - } - else { - *(uint32_t *)rbuff = (uint32_t)(ptr->DATA & 0xffffffff); - rbuff += sizeof(uint32_t); + temp = ptr->DATA; + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + *(rbuff++) = (uint8_t)(temp >> (i * 8)); } /* transfer count increment */ rtransferred++; @@ -289,17 +255,11 @@ static hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t datalen, uint8_t *w static hpm_stat_t spi_no_data(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config) { - hpm_stat_t stat; if (mode == spi_master_mode) { if (config->master_config.cmd_enable == false && config->master_config.addr_enable == false) { return status_invalid_argument; } } - else { - HPM_CHECK_RET(spi_wait_for_busy_status(ptr)); - HPM_CHECK_RET(spi_wait_for_idle_status(ptr)); - } - return status_success; } @@ -366,8 +326,7 @@ hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config) if (config->master_config.clk_src_freq_in_hz > config->master_config.sclk_freq_in_hz) { sclk_div = (config->master_config.clk_src_freq_in_hz / config->master_config.sclk_freq_in_hz) / 2 - 1; - } - else { + } else { sclk_div = 0xff; } @@ -390,13 +349,16 @@ void spi_format_init(SPI_Type *ptr, spi_format_config_t *config) SPI_TRANSFMT_CPHA_SET(config->common_config.cpha); } -hpm_stat_t spi_transfer(SPI_Type *ptr, - spi_control_config_t *config, - uint8_t *cmd, uint32_t *addr, - uint8_t *wbuff, uint32_t wsize, uint8_t *rbuff, uint32_t rsize) +hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_t wcount, uint32_t rcount) { - hpm_stat_t stat = status_fail; - uint8_t mode ,data_len, trans_mode; + if (wcount > SPI_SOC_TRANSFER_COUNT_MAX || rcount > SPI_SOC_TRANSFER_COUNT_MAX) { + return status_invalid_argument; + } + + /* slave data only mode only works on write read together transfer mode */ + if (config->slave_config.slave_data_only == true && config->common_config.trans_mode != spi_trans_write_read_together) { + return status_invalid_argument; + } ptr->TRANSCTRL = SPI_TRANSCTRL_SLVDATAONLY_SET(config->slave_config.slave_data_only) | SPI_TRANSCTRL_CMDEN_SET(config->master_config.cmd_enable) | @@ -405,16 +367,32 @@ hpm_stat_t spi_transfer(SPI_Type *ptr, SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode) | SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) | SPI_TRANSCTRL_TOKENEN_SET(config->master_config.token_enable) | - SPI_TRANSCTRL_WRTRANCNT_SET(wsize - 1) | + SPI_TRANSCTRL_WRTRANCNT_SET(wcount - 1) | SPI_TRANSCTRL_TOKENVALUE_SET(config->master_config.token_value) | SPI_TRANSCTRL_DUMMYCNT_SET(config->common_config.dummy_cnt) | - SPI_TRANSCTRL_RDTRANCNT_SET(rsize - 1); + SPI_TRANSCTRL_RDTRANCNT_SET(rcount - 1); /* reset txfifo, rxfifo and control */ ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK | SPI_CTRL_SPIRST_MASK; + return status_success; +} + +hpm_stat_t spi_transfer(SPI_Type *ptr, + spi_control_config_t *config, + uint8_t *cmd, uint32_t *addr, + uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount) +{ + hpm_stat_t stat = status_fail; + uint8_t mode, data_len_in_bytes, trans_mode; + + stat = spi_control_init(ptr, config, wcount, rcount); + if (stat != status_success) { + return stat; + } + /* read data length */ - data_len = (ptr->TRANSFMT & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT; + data_len_in_bytes = spi_get_data_length_in_bytes(ptr); /* read spi control mode */ mode = (ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT; @@ -422,83 +400,62 @@ hpm_stat_t spi_transfer(SPI_Type *ptr, /* read spi transfer mode */ trans_mode = config->common_config.trans_mode; - /* command phase */ - stat = spi_write_command(ptr, mode, config, cmd); + /* write address on master mode */ + stat = spi_write_address(ptr, mode, config, addr); if (stat != status_success) { return stat; } - /* address phase */ - stat = spi_write_address(ptr, mode, config, addr); + /* write command on master mode */ + stat = spi_write_command(ptr, mode, config, cmd); if (stat != status_success) { return stat; } /* data phase */ if (trans_mode == spi_trans_write_read_together) { - stat = spi_write_read_data(ptr, data_len, wbuff, wsize, rbuff, rsize); - } - else if (trans_mode == spi_trans_write_only || trans_mode == spi_trans_dummy_write) { - stat = spi_write_data(ptr, data_len, wbuff, wsize); - } - else if (trans_mode == spi_trans_read_only || trans_mode == spi_trans_dummy_read) { - stat = spi_read_data(ptr, data_len, rbuff, rsize); - } - else if (trans_mode == spi_trans_write_read || trans_mode == spi_trans_write_dummy_read) { - stat = spi_write_read_data(ptr, data_len, wbuff, wsize, rbuff, rsize); - } - else if (trans_mode == spi_trans_read_write || trans_mode == spi_trans_read_dummy_write) { - stat = spi_write_read_data(ptr, data_len, wbuff, wsize, rbuff, rsize); - } - else if (trans_mode == spi_trans_no_data) { + stat = spi_write_read_data(ptr, data_len_in_bytes, wbuff, wcount, rbuff, rcount); + } else if (trans_mode == spi_trans_write_only || trans_mode == spi_trans_dummy_write) { + stat = spi_write_data(ptr, data_len_in_bytes, wbuff, wcount); + } else if (trans_mode == spi_trans_read_only || trans_mode == spi_trans_dummy_read) { + stat = spi_read_data(ptr, data_len_in_bytes, rbuff, rcount); + } else if (trans_mode == spi_trans_write_read || trans_mode == spi_trans_write_dummy_read) { + stat = spi_write_read_data(ptr, data_len_in_bytes, wbuff, wcount, rbuff, rcount); + } else if (trans_mode == spi_trans_read_write || trans_mode == spi_trans_read_dummy_write) { + stat = spi_write_read_data(ptr, data_len_in_bytes, wbuff, wcount, rbuff, rcount); + } else if (trans_mode == spi_trans_no_data) { stat = spi_no_data(ptr, mode, config); - } - else { + } else { stat = status_invalid_argument; } - /* read command and address */ - if (stat == status_success) { - spi_read_command(ptr, mode, cmd); - } - if (stat != status_success) { return stat; } + /* read command on slave mode */ + stat = spi_read_command(ptr, mode, config, cmd); + if (stat != status_success) { + return stat; + } + /* on the slave mode, if master keeps asserting the cs signal, it's maybe timeout */ stat = spi_wait_for_idle_status(ptr); - return stat; } hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, spi_control_config_t *config, uint8_t *cmd, uint32_t *addr, - uint32_t wsize, uint32_t rsize) + uint32_t wcount, uint32_t rcount) { hpm_stat_t stat = status_fail; uint8_t mode; - stat = spi_wait_for_idle_status(ptr); + stat = spi_control_init(ptr, config, wcount, rcount); if (stat != status_success) { return stat; } - ptr->TRANSCTRL = SPI_TRANSCTRL_SLVDATAONLY_SET(config->slave_config.slave_data_only) | - SPI_TRANSCTRL_CMDEN_SET(config->master_config.cmd_enable) | - SPI_TRANSCTRL_ADDREN_SET(config->master_config.addr_enable) | - SPI_TRANSCTRL_ADDRFMT_SET(config->master_config.addr_phase_fmt) | - SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode) | - SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) | - SPI_TRANSCTRL_TOKENEN_SET(config->master_config.token_enable) | - SPI_TRANSCTRL_WRTRANCNT_SET(wsize - 1) | - SPI_TRANSCTRL_TOKENVALUE_SET(config->master_config.token_value) | - SPI_TRANSCTRL_DUMMYCNT_SET(config->common_config.dummy_cnt) | - SPI_TRANSCTRL_RDTRANCNT_SET(rsize - 1); - - /* reset txfifo, rxfifo and control */ - ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK | SPI_CTRL_SPIRST_MASK; - if (config->common_config.tx_dma_enable) { ptr->CTRL |= SPI_CTRL_TXDMAEN_MASK; } @@ -509,21 +466,16 @@ hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, /* read spi control mode */ mode = (ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT; - /* command phase */ - stat = spi_write_command(ptr, mode, config, cmd); - if (stat != status_success) { - return stat; - } - /* address phase */ stat = spi_write_address(ptr, mode, config, addr); if (stat != status_success) { return stat; } - /* read command and address */ - if (stat == status_success) { - spi_read_command(ptr, mode, cmd); + /* command phase */ + stat = spi_write_command(ptr, mode, config, cmd); + if (stat != status_success) { + return stat; } return stat; diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c index e277bfea40..3db13a698e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c index e52c52bbaa..557b7ddb48 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,6 +33,15 @@ void uart_default_config(UART_Type *ptr, uart_config_t *config) config->modem_config.auto_flow_ctrl_en = false; config->modem_config.loop_back_en = false; config->modem_config.set_rts_high = false; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + config->rxidle_config.detect_enable = false; + config->rxidle_config.detect_irq_enable = false; + config->rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; + config->rxidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ +#endif +#if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) + config->rx_enable = true; +#endif } static bool uart_calculate_baudrate(uint32_t freq, uint32_t baudrate, uint16_t *div_out, uint8_t *osc_out) @@ -105,7 +114,7 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) tmp = ptr->LCR & (~UART_LCR_DLAB_MASK); tmp &= ~(UART_LCR_SPS_MASK | UART_LCR_EPS_MASK | UART_LCR_PEN_MASK); - switch(config->parity) { + switch (config->parity) { case parity_none: break; case parity_odd: @@ -127,7 +136,7 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) } tmp &= ~(UART_LCR_STB_MASK | UART_LCR_WLS_MASK); - switch(config->num_of_stop_bits) { + switch (config->num_of_stop_bits) { case stop_bits_1: break; case stop_bits_1_5: @@ -147,17 +156,44 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) ptr->LCR = tmp | UART_LCR_WLS_SET(config->word_length); +#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) + ptr->FCRR = UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK; + if (config->fifo_enable) { + /* Enable FIFO, reset TX and RX. */ + if (config->using_new_fifo_thr) { + ptr->FCRR = UART_FCRR_FIFOT4EN_MASK + | UART_FCRR_FIFOE_MASK + | UART_FCRR_TFIFOT4_SET(config->tx_fifo_level) + | UART_FCRR_RFIFOT4_SET(config->rx_fifo_level) + | UART_FCRR_DMAE_SET(config->dma_enable); + } else { + ptr->FCR = UART_FCRR_FIFOE_MASK + | UART_FCRR_TFIFOT_SET(config->tx_fifo_level) + | UART_FCRR_RFIFOT_SET(config->rx_fifo_level) + | UART_FCRR_DMAE_SET(config->dma_enable); + } + } +#else ptr->FCR = UART_FCR_TFIFORST_MASK | UART_FCR_RFIFORST_MASK; if (config->fifo_enable) { /* Enable FIFO, reset TX and RX. */ - ptr->FCR = UART_FCR_TFIFORST_MASK - | UART_FCR_RFIFORST_MASK | UART_FCR_FIFOE_MASK + ptr->FCR = UART_FCR_FIFOE_MASK | UART_FCR_TFIFOT_SET(config->tx_fifo_level) | UART_FCR_RFIFOT_SET(config->rx_fifo_level) | UART_FCR_DMAE_SET(config->dma_enable); } +#endif uart_modem_config(ptr, &config->modem_config); + +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + uart_init_rxline_idle_detection(ptr, config->rxidle_config); +#endif +#if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) + if (config->rx_enable) { + ptr->IDLE_CFG |= UART_IDLE_CFG_RXEN_MASK; + } +#endif return status_success; } @@ -240,12 +276,9 @@ hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *byte) void uart_set_signal_level(UART_Type *ptr, uart_signal_t signal, uart_signal_level_t level) { - if (level == uart_signal_level_low) - { + if (level == uart_signal_level_low) { ptr->MCR = (ptr->MCR | signal); - } - else - { + } else { ptr->MCR = (ptr->MCR & ~signal); } } @@ -269,3 +302,45 @@ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte } return status_success; } + + +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config) +{ + ptr->IDLE_CFG = UART_IDLE_CFG_RX_IDLE_EN_SET(rxidle_config.detect_enable) + | UART_IDLE_CFG_RX_IDLE_THR_SET(rxidle_config.threshold) + | UART_IDLE_CFG_RX_IDLE_COND_SET(rxidle_config.idle_cond); + + if (rxidle_config.detect_irq_enable) { + uart_enable_irq(ptr, uart_intr_rx_line_idle); + } else { + uart_disable_irq(ptr, uart_intr_rx_line_idle); + } + + return status_success; +} +#endif + +#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config) +{ + ptr->MOTO_CFG &= ~UART_MOTO_CFG_TXSTP_BITS_MASK; + + ptr->MOTO_CFG = UART_MOTO_CFG_TXSTP_BITS_SET(config->stop_bit_len) + | UART_MOTO_CFG_HWTRG_EN_SET(config->hardware_trig) + | UART_MOTO_CFG_TRG_MODE_SET(config->trig_mode) + | UART_MOTO_CFG_TRG_CLR_RFIFO_SET(config->trig_clr_rxfifo) + | UART_MOTO_CFG_TXSTOP_INSERT_SET(config->en_stop_bit_insert); +} +#endif + +/* FCR is WO register, preprae all bit field to write */ +void uart_config_fifo_ctrl(UART_Type *ptr, uart_fifo_ctrl_t *ctrl) +{ + ptr->FCR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) + | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) + | UART_FCR_TFIFORST_SET(ctrl->reset_tx_fifo) + | UART_FCR_RFIFORST_SET(ctrl->reset_rx_fifo) + | UART_FCR_DMAE_SET(ctrl->dma_enable) + | UART_FCR_FIFOE_SET(ctrl->fifo_enable); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c index f131c23967..f8dbb290b4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c @@ -1,36 +1,60 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Include - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_usb_drv.h" #include "hpm_misc.h" #include "hpm_soc_feature.h" #include "hpm_common.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macro Enum Declaration - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /* ENDPTCTRL */ enum { ENDPTCTRL_STALL = HPM_BITSMASK(1, 0), - ENDPTCTRL_TYPE = HPM_BITSMASK(1, 2), + ENDPTCTRL_TYPE = HPM_BITSMASK(3, 2), ENDPTCTRL_TOGGLE_INHIBIT = HPM_BITSMASK(1, 5), ENDPTCTRL_TOGGLE_RESET = HPM_BITSMASK(1, 6), ENDPTCTRL_ENABLE = HPM_BITSMASK(1, 7), }; -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Internal API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ +/* De-initialize USB phy */ +static void usb_phy_deinit(USB_Type *ptr) +{ + ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ + + ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ + + ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clear cfg_rst_n */ + + ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* clear otg_suspendm */ +} + +static uint8_t usb_phy_get_line_state(USB_Type *ptr) +{ + return USB_PHY_STATUS_LINE_STATE_GET(ptr->PHY_STATUS); +} + +/*--------------------------------------------------------------------- + * Driver API + *--------------------------------------------------------------------- + */ /* Initialize USB phy */ -static void usb_phy_init(USB_Type *ptr) +void usb_phy_init(USB_Type *ptr) { uint32_t status; @@ -61,25 +85,6 @@ static void usb_phy_init(USB_Type *ptr) ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* set otg_suspendm */ } -/* De-initialize USB phy */ -static void usb_phy_deinit(USB_Type *ptr) -{ - ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ - - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ - - ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clear cfg_rst_n */ - - ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* clear otg_suspendm */ -} - -static uint8_t usb_phy_get_line_state(USB_Type *ptr) -{ - return USB_PHY_STATUS_LINE_STATE_GET(ptr->PHY_STATUS); -} -/*---------------------------------------------------------------------* - * Driver API - *---------------------------------------------------------------------*/ void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size) { /* The reset value for all endpoint types is the control endpoint. If one endpoint @@ -89,7 +94,7 @@ void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size) * for the data PID tracking on the active endpoint. */ - for(int i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { + for (int i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { ptr->ENDPTCTRL[i] = USB_ENDPTCTRL_TXT_SET(usb_xfer_bulk) | USB_ENDPTCTRL_RXT_SET(usb_xfer_bulk); } @@ -100,9 +105,11 @@ void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size) ptr->ENDPTSETUPSTAT = ptr->ENDPTSETUPSTAT; ptr->ENDPTCOMPLETE = ptr->ENDPTCOMPLETE; - while (ptr->ENDPTPRIME) {} + while (ptr->ENDPTPRIME) { + } ptr->ENDPTFLUSH = 0xFFFFFFFF; - while (ptr->ENDPTFLUSH) {} + while (ptr->ENDPTFLUSH) { + } } void usb_dcd_init(USB_Type *ptr) @@ -112,7 +119,8 @@ void usb_dcd_init(USB_Type *ptr) /* Reset controller */ ptr->USBCMD |= USB_USBCMD_RST_MASK; - while(USB_USBCMD_RST_GET(ptr->USBCMD)) {} + while (USB_USBCMD_RST_GET(ptr->USBCMD)) { + } /* Set mode to device, must be set immediately after reset */ ptr->USBMODE &= ~USB_USBMODE_CM_MASK; @@ -133,6 +141,11 @@ void usb_dcd_init(USB_Type *ptr) /* Set parallel transceiver width */ ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; +#ifdef CONFIG_USB_DEVICE_FS + /* Set usb forced to full speed mode */ + ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; +#endif + /* Not use interrupt threshold. */ ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; @@ -147,7 +160,8 @@ void usb_dcd_deinit(USB_Type *ptr) /* Reset controller */ ptr->USBCMD |= USB_USBCMD_RST_MASK; - while(USB_USBCMD_RST_GET(ptr->USBCMD)) {} + while (USB_USBCMD_RST_GET(ptr->USBCMD)) { + } /* De-initialize USB phy */ usb_phy_deinit(ptr); @@ -182,23 +196,35 @@ void usb_dcd_disconnect(USB_Type *ptr) /* Wait a SOF (It will not be a dead loop even usb cable is not connected.) */ while (USB_USBSTS_SRI_GET(ptr->USBSTS) == 0) { - } /* Disconnect */ ptr->USBCMD &= ~USB_USBCMD_RS_MASK; } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Endpoint API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ void usb_dcd_edpt_open(USB_Type *ptr, usb_endpoint_config_t *config) { uint8_t const epnum = config->ep_addr & 0x0f; uint8_t const dir = (config->ep_addr & 0x80) >> 7; /* Enable EP Control */ - ptr->ENDPTCTRL[epnum] |= ((config->xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); + uint32_t temp = ptr->ENDPTCTRL[epnum]; + temp &= ~((0x03 << 2) << (dir ? 16 : 0)); + temp |= ((config->xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); + ptr->ENDPTCTRL[epnum] = temp; +} + +uint8_t usb_dcd_edpt_get_type(USB_Type *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + uint32_t temp = ptr->ENDPTCTRL[epnum]; + + return dir ? USB_ENDPTCTRL_TXT_GET(temp) : USB_ENDPTCTRL_RXT_GET(temp); } void usb_dcd_edpt_xfer(USB_Type *ptr, uint8_t ep_idx) @@ -232,7 +258,7 @@ void usb_dcd_edpt_close(USB_Type *ptr, uint8_t ep_addr) uint8_t const epnum = ep_addr & 0x0f; uint8_t const dir = (ep_addr & 0x80) >> 7; - uint32_t primebit = HPM_BITSMASK(1, epnum) + ( dir ? 16 : 0 ); + uint32_t primebit = HPM_BITSMASK(1, epnum) << (dir ? 16 : 0); /* Flush the endpoint to stop a transfer. */ do { @@ -240,16 +266,18 @@ void usb_dcd_edpt_close(USB_Type *ptr, uint8_t ep_addr) ptr->ENDPTFLUSH |= primebit; /* Wait until all bits in the ENDPTFLUSH register are cleared. */ - while (0U != (ptr->ENDPTFLUSH & primebit)) {} + while (0U != (ptr->ENDPTFLUSH & primebit)) { + } /* - * Read the ENDPTSTAT register to ensure that for all endpoints - * commanded to be flushed, that the corresponding bits - * are now cleared. - */ + * Read the ENDPTSTAT register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ } while (0U != (ptr->ENDPTSTAT & primebit)); /* Disable the endpoint */ ptr->ENDPTCTRL[epnum] &= ~((ENDPTCTRL_TYPE | ENDPTCTRL_ENABLE | ENDPTCTRL_STALL) << (dir ? 16 : 0)); + ptr->ENDPTCTRL[epnum] |= (usb_xfer_bulk << 2) << (dir ? 16 : 0); } void usb_dcd_remote_wakeup(USB_Type *ptr) @@ -275,7 +303,8 @@ bool usb_hcd_init(USB_Type *ptr, uint32_t int_mask, uint16_t framelist_size) /* Reset controller */ ptr->USBCMD |= USB_USBCMD_RST_MASK; - while(USB_USBCMD_RST_GET(ptr->USBCMD)) {} + while (USB_USBCMD_RST_GET(ptr->USBCMD)) { + } /* Set mode to host, must be set immediately after reset */ ptr->USBMODE &= ~USB_USBMODE_CM_MASK; @@ -298,13 +327,9 @@ bool usb_hcd_init(USB_Type *ptr, uint32_t int_mask, uint16_t framelist_size) ptr->USBINTR |= int_mask; /* USB CMD Register */ - ptr->USBCMD = USB_USBCMD_RS_MASK - | USB_USBCMD_ASE_MASK | USB_USBCMD_PSE_MASK - | USB_USBCMD_FS_2_SET(framelist_size_bf >> 2) - | USB_USBCMD_FS_1_SET(framelist_size_bf); - - /* enable port power */ - ptr->PORTSC1 |= USB_PORTSC1_PP_MASK; + ptr->USBCMD = USB_USBCMD_ASE_MASK | USB_USBCMD_PSE_MASK + | USB_USBCMD_FS_2_SET(framelist_size_bf >> 2) + | USB_USBCMD_FS_1_SET(framelist_size_bf); return true; } @@ -321,5 +346,6 @@ void usb_hcd_port_reset(USB_Type *ptr) ptr->PORTSC1 |= USB_PORTSC1_PR_MASK; /* wait until port reset sequence is completed */ - while (USB_PORTSC1_PR_GET(ptr->PORTSC1)) {} + while (USB_PORTSC1_PR_GET(ptr->PORTSC1)) { + } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c index 17b73938e5..ce2f643a27 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c index 581e632a6a..111b77ea2d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -21,40 +21,38 @@ typedef struct { interrupt_interval_t interval; } interrupt_interval_map_t; - static const reset_interval_map_t k_reset_interval_map[reset_interval_out_of_range + 1U] = { - { 128UL, reset_interval_clock_period_mult_128 }, - { 256UL, reset_interval_clock_period_mult_256 }, - { 512UL, reset_interval_clock_period_mult_512 }, - { 1UL * TICKS_1K, reset_interval_clock_period_mult_1k }, - { 2UL * TICKS_1K, reset_interval_clock_period_mult_2k }, - { 4UL * TICKS_1K, reset_interval_clock_period_mult_4k }, - { 8UL * TICKS_1K, reset_interval_clock_period_mult_8k }, - { 16UL * TICKS_1K, reset_interval_clock_period_mult_16k }, - { 0xFFFFFFFFUL, reset_interval_out_of_range }, - }; + {128UL, reset_interval_clock_period_mult_128}, + {256UL, reset_interval_clock_period_mult_256}, + {512UL, reset_interval_clock_period_mult_512}, + {1UL * TICKS_1K, reset_interval_clock_period_mult_1k}, + {2UL * TICKS_1K, reset_interval_clock_period_mult_2k}, + {4UL * TICKS_1K, reset_interval_clock_period_mult_4k}, + {8UL * TICKS_1K, reset_interval_clock_period_mult_8k}, + {16UL * TICKS_1K, reset_interval_clock_period_mult_16k}, + {0xFFFFFFFFUL, reset_interval_out_of_range}, +}; static const interrupt_interval_map_t k_interrupt_interval_map[interrupt_interval_out_of_range + 1U] = { - { 64UL, interrupt_interval_clock_period_multi_64 }, - { 256UL, interrupt_interval_clock_period_multi_256 }, - { 1UL * TICKS_1K, interrupt_interval_clock_period_multi_1k }, - { 2UL * TICKS_1K, interrupt_interval_clock_period_multi_2k }, - { 4UL * TICKS_1K, interrupt_interval_clock_period_multi_4k }, - { 8UL * TICKS_1K, interrupt_interval_clock_period_multi_8k }, - { 16UL * TICKS_1K, interrupt_interval_clock_period_multi_16k }, - { 32UL * TICKS_1K, interrupt_interval_clock_period_multi_32k }, - { 128UL * TICKS_1K, interrupt_interval_clock_period_multi_128k }, - { 512UL * TICKS_1K, interrupt_interval_clock_period_multi_512k }, - { 2UL * TICKS_1M, interrupt_interval_clock_period_multi_2m }, - { 4UL * TICKS_1M, interrupt_interval_clock_period_multi_4m }, - { 8UL * TICKS_1M, interrupt_interval_clock_period_multi_8m }, - { 32UL * TICKS_1M, interrupt_interval_clock_period_multi_32m }, - { 128UL * TICKS_1M, interrupt_interval_clock_period_multi_128m }, - { 512UL * TICKS_1M, interrupt_interval_clock_period_multi_512m }, - { 2UL * TICKS_1G, interrupt_interval_clock_period_multi_2g }, - { 0xFFFFFFFFUL, interrupt_interval_out_of_range } + {64UL, interrupt_interval_clock_period_multi_64}, + {256UL, interrupt_interval_clock_period_multi_256}, + {1UL * TICKS_1K, interrupt_interval_clock_period_multi_1k}, + {2UL * TICKS_1K, interrupt_interval_clock_period_multi_2k}, + {4UL * TICKS_1K, interrupt_interval_clock_period_multi_4k}, + {8UL * TICKS_1K, interrupt_interval_clock_period_multi_8k}, + {16UL * TICKS_1K, interrupt_interval_clock_period_multi_16k}, + {32UL * TICKS_1K, interrupt_interval_clock_period_multi_32k}, + {128UL * TICKS_1K, interrupt_interval_clock_period_multi_128k}, + {512UL * TICKS_1K, interrupt_interval_clock_period_multi_512k}, + {2UL * TICKS_1M, interrupt_interval_clock_period_multi_2m}, + {8UL * TICKS_1M, interrupt_interval_clock_period_multi_8m}, + {32UL * TICKS_1M, interrupt_interval_clock_period_multi_32m}, + {128UL * TICKS_1M, interrupt_interval_clock_period_multi_128m}, + {512UL * TICKS_1M, interrupt_interval_clock_period_multi_512m}, + {2UL * TICKS_1G, interrupt_interval_clock_period_multi_2g}, + {0xFFFFFFFFUL, interrupt_interval_out_of_range} - }; +}; /* See hpm_wdg_drv.h for more details */ hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl) @@ -64,8 +62,8 @@ hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl) HPM_BREAK_IF((base == NULL) || (wdg_ctrl == NULL)); HPM_BREAK_IF((wdg_ctrl->reset_interval > reset_interval_max) || - (wdg_ctrl->interrupt_interval > interrupt_interval_max) || - (wdg_ctrl->clksrc > wdg_clksrc_pclk)); + (wdg_ctrl->interrupt_interval > interrupt_interval_max) || + (wdg_ctrl->clksrc > wdg_clksrc_pclk)); uint32_t rst_time = (uint32_t) wdg_ctrl->reset_interval; uint32_t int_time = (uint32_t) wdg_ctrl->interrupt_interval; @@ -124,8 +122,7 @@ interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_f src_clk_one_tick_in_ns = 1U; } - uint32_t interrupt_interval_ticks = ((uint64_t) interval_us * 1000UL) / src_clk_one_tick_in_ns; - + uint32_t interrupt_interval_ticks = ((uint64_t) interval_us * 1000L) / src_clk_one_tick_in_ns; for (uint32_t i = 0; i < ARRAY_SIZE(k_interrupt_interval_map); i++) { if (interrupt_interval_ticks <= k_interrupt_interval_map[i].top) { interrupt_interval = k_interrupt_interval_map[i].interval; @@ -136,15 +133,29 @@ interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_f return interrupt_interval; } +uint64_t wdg_convert_interrupt_interval_to_us(const uint32_t src_freq, interrupt_interval_t interval) +{ + uint64_t time_in_us = 0; + if ((src_freq != 0) && (interval < interrupt_interval_out_of_range)) { + uint32_t interrupt_interval_in_reg = (uint32_t) interval; -uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq) + double tick_in_ns = 1.0 * ONE_SECOND_TICKS_IN_NS / src_freq; + uint64_t + total_interval_in_ns = (uint64_t)(tick_in_ns * k_interrupt_interval_map[interrupt_interval_in_reg].top); + + time_in_us = total_interval_in_ns / 1000UL; + } + + return time_in_us; +} + +uint32_t wdg_convert_reset_interval_to_us(const uint32_t src_freq, reset_interval_t interval) { uint32_t time_in_us = 0; - if ((base != NULL) && (src_freq != 0)) { - uint32_t interrupt_interval_in_reg = WDG_CTRL_INTTIME_GET(base->CTRL); - - double tick_in_ns = 1.0 * TICKS_1G / src_freq; - uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_interrupt_interval_map[interrupt_interval_in_reg].top); + if ((src_freq != 0) && (interval < reset_interval_out_of_range)) { + uint32_t reset_interval_in_reg = (uint32_t) interval; + double tick_in_ns = 1.0 * ONE_SECOND_TICKS_IN_NS / src_freq; + uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_reset_interval_map[reset_interval_in_reg].top); time_in_us = (uint32_t)(total_interval_in_ns / 1000UL); } @@ -152,15 +163,26 @@ uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_fre return time_in_us; } -uint32_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq) +uint64_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq) { - uint32_t time_in_us = 0; + uint64_t time_in_us = 0; if ((base != NULL) && (src_freq != 0)) { - uint32_t reset_interval_in_reg = WDG_CTRL_RSTTIME_GET(base->CTRL); - double tick_in_ns = 1.0 * TICKS_1G / src_freq; - uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_reset_interval_map[reset_interval_in_reg].top); + interrupt_interval_t interval = (interrupt_interval_t) WDG_CTRL_INTTIME_GET(base->CTRL); - time_in_us = (uint32_t)(total_interval_in_ns / 1000UL) + wdg_get_interrupt_interval_in_us(base, src_freq); + time_in_us = wdg_convert_interrupt_interval_to_us(src_freq, interval); + } + + return time_in_us; +} + +uint64_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq) +{ + uint64_t time_in_us = 0; + if ((base != NULL) && (src_freq != 0)) { + reset_interval_t reset_interval = (reset_interval_t) WDG_CTRL_RSTTIME_GET(base->CTRL); + interrupt_interval_t interrupt_interval = (interrupt_interval_t) WDG_CTRL_INTTIME_GET(base->CTRL); + time_in_us = wdg_convert_reset_interval_to_us(src_freq, reset_interval) + + wdg_convert_interrupt_interval_to_us(src_freq, interrupt_interval); } return time_in_us; diff --git a/bsp/hpmicro/libraries/hpm_sdk/env.sh b/bsp/hpmicro/libraries/hpm_sdk/env.sh deleted file mode 100644 index 6fe994e10b..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/env.sh +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (c) 2021 hpmicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -if [ "X$MSYSTEM" "==" "X" ]; then - if [ "X$name" "==" "Xenv.sh" ]; then - echo "Please source this file, rather than executing it." - exit - fi - env_name=$0 -else - env_name=$1 -fi - -script=$(cd -P -- "$(dirname -- "$env_name")" && printf '%s\n' "$(pwd -P)/$(basename -- "$env_name")") -if [ "X$MSYSTEM" "==" "X" ]; then - export HPM_SDK_BASE=$(dirname "$script") -else - export HPM_SDK_BASE=$script -fi - -echo $HPM_SDK_BASE - -export OPENOCD_SCRIPTS=${HPM_SDK_BASE}/boards/openocd - diff --git a/bsp/hpmicro/libraries/hpm_sdk/hpm_sdk_version.h.in b/bsp/hpmicro/libraries/hpm_sdk/hpm_sdk_version.h.in new file mode 100644 index 0000000000..c195586cbe --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/hpm_sdk_version.h.in @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDK_VERSION_H +#define HPM_SDK_VERSION_H + +#cmakedefine SDK_VERSION_CODE @SDK_VERSION_CODE@ +#define SDK_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) + +#define SDKVERSION @SDKVERSION@ +#define SDK_VERSION_NUMBER @SDK_VERSION_NUMBER@ +#define SDK_VERSION_MAJOR @SDK_VERSION_MAJOR@ +#define SDK_VERSION_MINOR @SDK_VERSION_MINOR@ +#define SDK_PATCHLEVEL @SDK_PATCHLEVEL@ +#define SDK_VERSION_STRING @SDK_VERSION_STRING@ + +#define BUILD_VERSION @BUILD_VERSION@ + + +#endif /* HPM_SDK_VERSION_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/index.md b/bsp/hpmicro/libraries/hpm_sdk/index.md deleted file mode 100644 index 5d9467a976..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/index.md +++ /dev/null @@ -1,15 +0,0 @@ -hpm sdk -=================================== -:::{eval-rst} -.. toctree:: - :maxdepth: 1 - :caption: Contents - :name: HPM README Document - - CHANGELOG - README - boards/index - samples/index - doc/src/sdk_doc/README - -::: \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/index_zh.md b/bsp/hpmicro/libraries/hpm_sdk/index_zh.md deleted file mode 100644 index c9dad49754..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/index_zh.md +++ /dev/null @@ -1,15 +0,0 @@ -hpm sdk -=================================== - -:::{eval-rst} -.. toctree:: - :maxdepth: 1 - :caption: 目录 - :name: HPM README Document - - CHANGELOG - README_zh - boards/index_zh - samples/index_zh - doc/src/sdk_doc/README_zh -::: \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/SConscript new file mode 100644 index 0000000000..5717c3e631 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/SConscript @@ -0,0 +1,25 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + hpm_otp_drv.c + boot/hpm_bootheader.c +''') + + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c new file mode 100644 index 0000000000..57cdf5aa2e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h new file mode 100644 index 0000000000..d7f22fd824 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h new file mode 100644 index 0000000000..ed18058f0e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BATT_IOMUX_H +#define HPM_BATT_IOMUX_H + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_BATT_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_BATT_TAMPER_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_BATT_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_BATT_TAMPER_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_BATT_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_BATT_TAMPER_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_BATT_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_BATT_TAMPER_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_BATT_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_BATT_TAMPER_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_BATT_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_BATT_TAMPER_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_BATT_TAMPER_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_BATT_TAMPER_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h new file mode 100644 index 0000000000..00dfb6fcf3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BCFG_DRV_H +#define HPM_BCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_bcfg_regs.h" + +/** + * + * @brief BCFG driver APIs + * @defgroup bcfg_interface BCFG driver APIs + * @ingroup io_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief disable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief enable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +/** + * @brief disable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BCFG_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h new file mode 100644 index 0000000000..50cbd1b455 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BCFG_H +#define HPM_BCFG_H + +typedef struct { + __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ + __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ + __RW uint32_t CLK_CFG; /* 0x10: Clock config */ +} BCFG_Type; + + +/* Bitfield definition for register: VBG_CFG */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) +#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) +#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) +#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) + +/* + * LP_MODE (RW) + * + * Bandgap works in low power mode + * 0: not in low power mode + * 1: bandgap work in low power mode + */ +#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) +#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) +#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) +#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Bandgap works in power save mode + * 0: not in power save mode + * 1: bandgap work in power save mode + */ +#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) +#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) +#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) +#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) + +/* + * VBG_1P0 (RW) + * + * Bandgap 1.0V output trim + */ +#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) +#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) +#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) +#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) + +/* + * VBG_P65 (RW) + * + * Bandgap 0.65V output trim + */ +#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) +#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) +#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) +#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) + +/* + * VBG_P50 (RW) + * + * Bandgap 0.50V output trim + */ +#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) +#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) +#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) +#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) + +/* Bitfield definition for register: IRC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) +#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: XTAL32K_CFG */ +/* + * HYST_EN (RW) + * + * crystal 32k hysteres enable + */ +#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) +#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) +#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) +#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) + +/* + * GMSEL (RW) + * + * crystal 32k gm selection + */ +#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) +#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) +#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) +#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) + +/* + * CFG (RW) + * + * crystal 32k config + */ +#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) +#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) +#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) +#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) + +/* + * AMP (RW) + * + * crystal 32k amplifier + */ +#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) +#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) +#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) +#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) + +/* Bitfield definition for register: CLK_CFG */ +/* + * XTAL_SEL (RO) + * + * crystal selected + */ +#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) +#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) +#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) + +/* + * KEEP_IRC (RW) + * + * force irc32k run + */ +#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) +#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) +#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) +#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) + +/* + * FORCE_XTAL (RW) + * + * force switch to crystal + */ +#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) +#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) +#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) +#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) + + + + +#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h similarity index 98% rename from bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h index 613c35e96e..46bb7beb07 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -112,4 +112,4 @@ typedef struct { -#endif /* HPM_BGPR_H */ \ No newline at end of file +#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_drv.h similarity index 55% rename from bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_drv.h index 88d014f13b..e37bac24b1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -22,11 +22,11 @@ /** @brief Define BPOR power on cause */ typedef enum { - bpor_power_on_cause_wbutn = 0, - bpor_power_on_cause_safety_violation = 1, - bpor_power_on_cause_rtc_0 = 2, - bpor_power_on_cause_rtc_1 = 3, - bpor_power_on_cause_gpio = 4 + bpor_power_on_cause_wbutn = 1 << 0, + bpor_power_on_cause_safety_violation = 1 << 1, + bpor_power_on_cause_rtc_0 = 1 << 2, + bpor_power_on_cause_rtc_1 = 1 << 3, + bpor_power_on_cause_gpio = 1 << 4 } bpor_power_on_cause_t; @@ -46,14 +46,47 @@ static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) } /** - * @brief Select power on cause + * @brief Clear power on cause * * @param[in] ptr BPOR base address - * @param[in] cause bpor_power_on_cause_t + * @param[in] mask cause status to be cleared */ -static inline void bpor_select_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) { - ptr->POR_SELECT |= 1 << cause; + ptr->POR_CAUSE |= mask; +} + +/** + * @brief enable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be enabled + */ +static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT |= cause; +} + +/** + * @brief disable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be disabled + */ +static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT &= ~cause; +} + +/** + * @brief Set power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be used + */ +static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) +{ + ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; } /** diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h similarity index 97% rename from bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h index 36daa1f041..32147d05a2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -76,4 +76,4 @@ typedef struct { -#endif /* HPM_BPOR_H */ \ No newline at end of file +#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c new file mode 100644 index 0000000000..e4e9ee440c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c @@ -0,0 +1,498 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_soc.h" +#include "hpm_common.h" +#include "hpm_pllctlv2_drv.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (400000000UL) +#define FREQ_PRESET1_PLL0_CLK1 (333333333UL) +#define FREQ_PRESET1_PLL1_CLK2 (250000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (480000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (320000000UL) +#define FREQ_PRESET1_PLL2_CLK0 (5160960000UL) +#define FREQ_PRESET1_PLL2_CLK1 (4515840000UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) +#define WDG_INSTANCE_NUM (2U) +#define BUS_FREQ_MAX (200000000UL) +#define FREQ_1MHz (1000000UL) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + + + +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for ADC + */ +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); + +/** + * @brief Get Clock frequency for DAC + */ +static uint32_t get_frequency_for_dac(uint32_t instance); + +/** + * @brief Get Clock frequency for WDG + */ +static uint32_t get_frequency_for_wdg(uint32_t instance); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + +static uint32_t get_frequency_for_cpu(void); +static uint32_t get_frequency_for_axi(void); +static uint32_t get_frequency_for_ahb(void); + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ana0, clock_node_ahb, +}; + +static const clock_node_t s_dac_clk_mux_node[] = { + clock_node_ana3, clock_node_ahb +}; + +static WDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1 }; + +uint32_t hpm_core_clock; + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); + break; + case CLK_SRC_GROUP_DAC: + clk_freq = get_frequency_for_dac(node_or_instance); + break; + case CLK_SRC_GROUP_WDG: + clk_freq = get_frequency_for_wdg(node_or_instance); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_CPU0: + clk_freq = get_frequency_for_cpu(); + break; + case CLK_SRC_GROUP_AHB: + clk_freq = get_frequency_for_ahb(); + break; + case CLK_SRC_GROUP_AXI: + clk_freq = get_frequency_for_axi(); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); + break; + case clock_source_pll0_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); + break; + case clock_source_pll0_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); + break; + case clock_source_pll1_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); + break; + case clock_source_pll1_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); + break; + case clock_source_pll2_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); + break; + case clock_source_pll2_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + uint32_t adc_index = instance; + + (void) clk_src_type; + + if (adc_index < ADC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); + if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { + node = s_adc_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node != clock_node_ahb) { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } else { + clk_freq = get_frequency_for_ahb(); + } + } + return clk_freq; +} + +static uint32_t get_frequency_for_dac(uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + if (instance < DAC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); + if (mux_in_reg < ARRAY_SIZE(s_dac_clk_mux_node)) { + node = s_dac_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node == clock_node_ahb) { + clk_freq = get_frequency_for_ahb(); + } else { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } + } + + return clk_freq; +} + +static uint32_t get_frequency_for_wdg(uint32_t instance) +{ + uint32_t freq_in_hz; + /* EXT clock is chosen */ + if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { + freq_in_hz = get_frequency_for_cpu(); + } + /* PCLK is chosen */ + else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_cpu(void) +{ + uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_source(mux) / div); +} + +static uint32_t get_frequency_for_axi(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +static uint32_t get_frequency_for_ahb(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_WDG; + clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); + } + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_CPU0: + case CLK_SRC_GROUP_AHB: + case CLK_SRC_GROUP_AXI: + clk_src_group = CLK_SRC_GROUP_CPU0; + clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src <= clk_adc_src_ahb0) || (src >= clk_adc_src_ana2)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_dac_src_ana3) || (src > clk_dac_src_ahb0)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->DACCLK[node_or_instance] = + (HPM_SYSCTL->DACCLK[node_or_instance] & SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, (clock_source_t) src, div); + } + break; + case CLK_SRC_GROUP_ADC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + if (src == clk_wdg_src_ahb0) { + s_wdgs[node_or_instance]->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } else if (src == clk_wdg_src_osc32k) { + s_wdgs[node_or_instance]->CTRL |= WDG_CTRL_CLKSEL_MASK; + } else { + status = status_clk_src_invalid; + } + } + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AHB: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_AXI: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_CPU0: + if (node_or_instance == clock_node_cpu0) { + /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency + * changes, the AXI and AHB clock changes accordingly, here the driver ensures the + * AXI and AHB bus clock frequency is in valid range. + */ + uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; + uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, axi_sub_div, ahb_sub_div); + } else { + status = status_clk_shared_cpu0; + } + break; + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } else if (resource == RESOURCE_SHARED_PTPC) { + sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } else if (resource == RESOURCE_SHARED_PTPC) { + sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, false); + } +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t) ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_update_core_clock(void) +{ + uint32_t hart_id = read_csr(CSR_MHARTID); + clock_name_t cpu_clk_name = (hart_id == 1U) ? clock_cpu1 : clock_cpu0; + hpm_core_clock = clock_get_frequency(cpu_clk_name); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h new file mode 100644 index 0000000000..dbfcc718f5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" + + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), + status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), + status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), + status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), + status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), + status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), + +}; + + + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_WDG (3U) +#define CLK_SRC_GROUP_PMIC (4U) +#define CLK_SRC_GROUP_AHB (5U) +#define CLK_SRC_GROUP_AXI (6U) +#define CLK_SRC_GROUP_DAC (7U) +#define CLK_SRC_GROUP_CPU0 (9U) +#define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 2), + clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 3), + + clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + + +#define RESOURCE_INVALID (0xFFFFU) +#define RESOURCE_SHARED_PTPC (0xFFFEU) +#define RESOURCE_SHARED_CPU0 (0xFFFDU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_cpu1 = MAKE_CLOCK_NAME(sysctl_resource_cpu1, CLK_SRC_GROUP_CPU0, clock_node_cpu1), + clock_mchtmr1 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr1, CLK_SRC_GROUP_COMMON, clock_node_mchtmr1), + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), + clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), + clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), + clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), + clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), + clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), + clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), + clock_lin0 = MAKE_CLOCK_NAME(sysctl_resource_lin0, CLK_SRC_GROUP_COMMON, clock_node_lin0), + clock_lin1 = MAKE_CLOCK_NAME(sysctl_resource_lin1, CLK_SRC_GROUP_COMMON, clock_node_lin1), + clock_lin2 = MAKE_CLOCK_NAME(sysctl_resource_lin2, CLK_SRC_GROUP_COMMON, clock_node_lin2), + clock_lin3 = MAKE_CLOCK_NAME(sysctl_resource_lin3, CLK_SRC_GROUP_COMMON, clock_node_lin3), + + clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), + clock_axi = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_ahbp = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_AHB, clock_node_ahb), + + clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), + clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), + clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI, 3), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI, 4), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 3), + clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 4), + clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 5), + clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 6), + clock_mot2 = MAKE_CLOCK_NAME(sysctl_resource_mot2, CLK_SRC_GROUP_AHB, 7), + clock_mot3 = MAKE_CLOCK_NAME(sysctl_resource_mot3, CLK_SRC_GROUP_AHB, 8), + clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 9), + clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), + clock_msyn = MAKE_CLOCK_NAME(sysctl_resource_msyn, CLK_SRC_GROUP_AHB, 11), + clock_sdm0 = MAKE_CLOCK_NAME(sysctl_resource_sdm0, CLK_SRC_GROUP_AHB, 13), + clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), + clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU0, 1), + clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_CPU0, 2), + + + /* For ADC, there are 2-stage clock source and divider configurations */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), + clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), + clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), + + /* For DAC, there are 2-stage clock source and divider configurations */ + clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), + clock_ana4 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana4), + clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), + clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), + clk_pll2clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), + clk_pll2clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), +} clock_name_t; + +extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + +/** + * @brief Get Clock frequency for selected clock source + * @param [in] source clock source + * @return clock frequency for selected clock source + */ +uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @param [in] clock_name clock name + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @return #status_success Setting ADC clock source is successful + * #status_clk_invalid Invalid ADC clock + * #status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set DAC clock source + * @param[in] clock_name DAC clock name + * @param[in] src DAC clock source + * + * @return #status_success Setting DAC clock source is successful + * #status_clk_invalid Invalid DAC clock + * #status_clk_src_invalid Invalid DAC clock source + */ +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @return #status_success Setting Clock source and divider is successful. + * #status_clk_src_invalid clock source is invalid. + * #status_clk_fixed clock source and divider is a fixed value + * #status_clk_shared_ahb Clock is shared with the AHB clock + * #status_clk_shared_axi0 Clock is shared with the AXI0 clock + * #status_clk_shared_axi1 CLock is shared with the AXI1 clock + * #status_clk_shared_axi2 Clock is shared with the AXI2 clock + * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h new file mode 100644 index 0000000000..cc29018e11 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h @@ -0,0 +1,6512 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_SSTATUS (0x100) +#define CSR_SEDELEG (0x102) +#define CSR_SIDELEG (0x103) +#define CSR_SIE (0x104) +#define CSR_STVEC (0x105) +#define CSR_SSCRATCH (0x140) +#define CSR_SEPC (0x141) +#define CSR_SCAUSE (0x142) +#define CSR_STVAL (0x143) +#define CSR_SIP (0x144) +#define CSR_SATP (0x180) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MEDELEG (0x302) +#define CSR_MIDELEG (0x303) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_PMACFG0 (0xBC0) +#define CSR_PMACFG1 (0xBC1) +#define CSR_PMACFG2 (0xBC2) +#define CSR_PMACFG3 (0xBC3) +#define CSR_PMAADDR0 (0xBD0) +#define CSR_PMAADDR1 (0xBD1) +#define CSR_PMAADDR2 (0xBD2) +#define CSR_PMAADDR3 (0xBD3) +#define CSR_PMAADDR4 (0xBD4) +#define CSR_PMAADDR5 (0xBD5) +#define CSR_PMAADDR6 (0xBD6) +#define CSR_PMAADDR7 (0xBD7) +#define CSR_PMAADDR8 (0xBD8) +#define CSR_PMAADDR9 (0xBD9) +#define CSR_PMAADDR10 (0xBDA) +#define CSR_PMAADDR11 (0xBDB) +#define CSR_PMAADDR12 (0xBDC) +#define CSR_PMAADDR13 (0xBDD) +#define CSR_PMAADDR14 (0xBDE) +#define CSR_PMAADDR15 (0xBDF) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_SCOUNTEREN (0x106) +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_MSLIDELEG (0x7D5) +#define CSR_MCLK_CTL (0x7DF) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_SLIE (0x9C4) +#define CSR_SLIP (0x9C5) +#define CSR_SDCAUSE (0x9C9) +#define CSR_SCCTLDATA (0x9CD) +#define CSR_SCOUNTERINTEN (0x9CF) +#define CSR_SCOUNTERMASK_M (0x9D1) +#define CSR_SCOUNTERMASK_S (0x9D2) +#define CSR_SCOUNTERMASK_U (0x9D3) +#define CSR_SCOUNTEROVF (0x9D4) +#define CSR_SCOUNTINHIBIT (0x9E0) +#define CSR_SHPMEVENT3 (0x9E3) +#define CSR_SHPMEVENT4 (0x9E4) +#define CSR_SHPMEVENT5 (0x9E5) +#define CSR_SHPMEVENT6 (0x9E6) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: SSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_SSTATUS_SD_MASK (0x80000000UL) +#define CSR_SSTATUS_SD_SHIFT (31U) +#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_SSTATUS_MXR_MASK (0x80000UL) +#define CSR_SSTATUS_MXR_SHIFT (19U) +#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) +#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_SSTATUS_SUM_MASK (0x40000UL) +#define CSR_SSTATUS_SUM_SHIFT (18U) +#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) +#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggeredwhen XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. + * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_XS_MASK (0x18000UL) +#define CSR_SSTATUS_XS_SHIFT (15U) +#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. + * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_FS_MASK (0x6000U) +#define CSR_SSTATUS_FS_SHIFT (13U) +#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) +#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_SSTATUS_SPP_MASK (0x100U) +#define CSR_SSTATUS_SPP_SHIFT (8U) +#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) +#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_SSTATUS_SPIE_MASK (0x20U) +#define CSR_SSTATUS_SPIE_SHIFT (5U) +#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) +#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_SSTATUS_UPIE_MASK (0x10U) +#define CSR_SSTATUS_UPIE_SHIFT (4U) +#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) +#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_SIE_MASK (0x2U) +#define CSR_SSTATUS_SIE_SHIFT (1U) +#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) +#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_UIE_MASK (0x1U) +#define CSR_SSTATUS_UIE_SHIFT (0U) +#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) +#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: SEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SPF_MASK (0x8000U) +#define CSR_SEDELEG_SPF_SHIFT (15U) +#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) +#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LPF_MASK (0x2000U) +#define CSR_SEDELEG_LPF_SHIFT (13U) +#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) +#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IPF_MASK (0x1000U) +#define CSR_SEDELEG_IPF_SHIFT (12U) +#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) +#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_UEC_MASK (0x100U) +#define CSR_SEDELEG_UEC_SHIFT (8U) +#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) +#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAF_MASK (0x80U) +#define CSR_SEDELEG_SAF_SHIFT (7U) +#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) +#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAM_MASK (0x40U) +#define CSR_SEDELEG_SAM_SHIFT (6U) +#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) +#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAF_MASK (0x20U) +#define CSR_SEDELEG_LAF_SHIFT (5U) +#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) +#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAM_MASK (0x10U) +#define CSR_SEDELEG_LAM_SHIFT (4U) +#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) +#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) + +/* + * B (RW) + * + * B indicates whether an exception triggered by breakpoint will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_B_MASK (0x8U) +#define CSR_SEDELEG_B_SHIFT (3U) +#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) +#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_II_MASK (0x4U) +#define CSR_SEDELEG_II_SHIFT (2U) +#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) +#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAF_MASK (0x2U) +#define CSR_SEDELEG_IAF_SHIFT (1U) +#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) +#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAM_MASK (0x1U) +#define CSR_SEDELEG_IAM_SHIFT (0U) +#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) +#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: SIDELEG */ +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UEI_MASK (0x100U) +#define CSR_SIDELEG_UEI_SHIFT (8U) +#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) +#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UTI_MASK (0x10U) +#define CSR_SIDELEG_UTI_SHIFT (4U) +#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) +#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_USI_MASK (0x1U) +#define CSR_SIDELEG_USI_SHIFT (0U) +#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) +#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) + +/* Bitfield definition for register: SIE */ +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SEIE_MASK (0x200U) +#define CSR_SIE_SEIE_SHIFT (9U) +#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) +#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UEIE_MASK (0x100U) +#define CSR_SIE_UEIE_SHIFT (8U) +#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) +#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_STIE_MASK (0x20U) +#define CSR_SIE_STIE_SHIFT (5U) +#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) +#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UTIE_MASK (0x10U) +#define CSR_SIE_UTIE_SHIFT (4U) +#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) +#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SSIE_MASK (0x2U) +#define CSR_SIE_SSIE_SHIFT (1U) +#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) +#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_USIE_MASK (0x1U) +#define CSR_SIE_USIE_SHIFT (0U) +#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) +#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) + +/* Bitfield definition for register: STVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_STVEC_BASE_31_2_SHIFT (2U) +#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) +#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: SSCRATCH */ +/* + * SSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) +#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) +#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) + +/* Bitfield definition for register: SEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_SEPC_EPC_SHIFT (1U) +#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) +#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) + +/* Bitfield definition for register: SCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) +#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 256+16:Slave port ECC error interrupt (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt(S-mode) + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:10:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) +#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: STVAL */ +/* + * STVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) +#define CSR_STVAL_STVAL_SHIFT (0U) +#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) +#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) + +/* Bitfield definition for register: SIP */ +/* + * SEIP (RO) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SEIP_MASK (0x200U) +#define CSR_SIP_SEIP_SHIFT (9U) +#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UEIP_MASK (0x100U) +#define CSR_SIP_UEIP_SHIFT (8U) +#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) +#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) + +/* + * STIP (RO) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_STIP_MASK (0x20U) +#define CSR_SIP_STIP_SHIFT (5U) +#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) + +/* + * UTIP (RO) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UTIP_MASK (0x10U) +#define CSR_SIP_UTIP_SHIFT (4U) +#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SSIP_MASK (0x2U) +#define CSR_SIP_SSIP_SHIFT (1U) +#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) +#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_USIP_MASK (0x1U) +#define CSR_SIP_USIP_SHIFT (0U) +#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) +#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) + +/* Bitfield definition for register: SATP */ +/* + * MODE (RW) + * + * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is + * not supported in the product, this CSR will be + * hardwired to 0. + * 0:No page translation + * 1:Page-based 32-bit virtual addressing + */ +#define CSR_SATP_MODE_MASK (0x80000000UL) +#define CSR_SATP_MODE_SHIFT (31U) +#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) +#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) + +/* + * ASID (RW) + * + * ASID holds the address space identifier. + */ +#define CSR_SATP_ASID_MASK (0x7FC00000UL) +#define CSR_SATP_ASID_SHIFT (22U) +#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) +#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) + +/* + * PPN (RW) + * + * PPN holds the physical page number of the root page table. + */ +#define CSR_SATP_PPN_MASK (0x3FFFFFUL) +#define CSR_SATP_PPN_SHIFT (0U) +#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) +#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * TSR (RW) + * + * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TSR_MASK (0x400000UL) +#define CSR_MSTATUS_TSR_SHIFT (22U) +#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) +#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) + +/* + * TW (RW) + * + * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TW_MASK (0x200000UL) +#define CSR_MSTATUS_TW_SHIFT (21U) +#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) +#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) + +/* + * TVM (RW) + * + * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. + * 0:Normal execution + * 1:Raising exceptions + */ +#define CSR_MSTATUS_TVM_MASK (0x100000UL) +#define CSR_MSTATUS_TVM_SHIFT (20U) +#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) +#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_MSTATUS_SUM_MASK (0x40000UL) +#define CSR_MSTATUS_SUM_SHIFT (18U) +#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) +#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_MSTATUS_SPP_MASK (0x100U) +#define CSR_MSTATUS_SPP_SHIFT (8U) +#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) +#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_MSTATUS_SPIE_MASK (0x20U) +#define CSR_MSTATUS_SPIE_SHIFT (5U) +#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) +#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_SIE_MASK (0x2U) +#define CSR_MSTATUS_SIE_SHIFT (1U) +#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) +#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SPF_MASK (0x8000U) +#define CSR_MEDELEG_SPF_SHIFT (15U) +#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) +#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LPF_MASK (0x2000U) +#define CSR_MEDELEG_LPF_SHIFT (13U) +#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) +#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IPF_MASK (0x1000U) +#define CSR_MEDELEG_IPF_SHIFT (12U) +#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) +#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) + +/* + * SEC (RW) + * + * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SEC_MASK (0x200U) +#define CSR_MEDELEG_SEC_SHIFT (9U) +#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) +#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_UEC_MASK (0x100U) +#define CSR_MEDELEG_UEC_SHIFT (8U) +#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) +#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAF_MASK (0x80U) +#define CSR_MEDELEG_SAF_SHIFT (7U) +#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) +#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAM_MASK (0x40U) +#define CSR_MEDELEG_SAM_SHIFT (6U) +#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) +#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAF_MASK (0x20U) +#define CSR_MEDELEG_LAF_SHIFT (5U) +#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) +#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAM_MASK (0x10U) +#define CSR_MEDELEG_LAM_SHIFT (4U) +#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) +#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_II_MASK (0x4U) +#define CSR_MEDELEG_II_SHIFT (2U) +#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) +#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAF_MASK (0x2U) +#define CSR_MEDELEG_IAF_SHIFT (1U) +#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) +#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAM_MASK (0x1U) +#define CSR_MEDELEG_IAM_SHIFT (0U) +#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) +#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: MIDELEG */ +/* + * SEI (RW) + * + * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SEI_MASK (0x200U) +#define CSR_MIDELEG_SEI_SHIFT (9U) +#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) +#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) + +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UEI_MASK (0x100U) +#define CSR_MIDELEG_UEI_SHIFT (8U) +#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) +#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) + +/* + * STI (RW) + * + * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_STI_MASK (0x20U) +#define CSR_MIDELEG_STI_SHIFT (5U) +#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) +#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UTI_MASK (0x10U) +#define CSR_MIDELEG_UTI_SHIFT (4U) +#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) +#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) + +/* + * SSI (RW) + * + * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SSI_MASK (0x2U) +#define CSR_MIDELEG_SSI_SHIFT (1U) +#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) +#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_USI_MASK (0x1U) +#define CSR_MIDELEG_USI_SHIFT (0U) +#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) +#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SEIE_MASK (0x200U) +#define CSR_MIE_SEIE_SHIFT (9U) +#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) +#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_STIE_MASK (0x20U) +#define CSR_MIE_STIE_SHIFT (5U) +#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) +#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SSIE_MASK (0x2U) +#define CSR_MIE_SSIE_SHIFT (1U) +#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) +#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_MCONTROL_S_MASK (0x10U) +#define CSR_MCONTROL_S_SHIFT (4U) +#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) +#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ICOUNT_S_MASK (0x80U) +#define CSR_ICOUNT_S_SHIFT (7U) +#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) +#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ITRIGGER_S_MASK (0x80U) +#define CSR_ITRIGGER_S_SHIFT (7U) +#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) +#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ETRIGGER_S_MASK (0x80U) +#define CSR_ETRIGGER_S_SHIFT (7U) +#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) +#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKS (RW) + * + * This bit controls the behavior of EBREAK instructions in Supervisor Mode. + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKS_MASK (0x2000U) +#define CSR_DCSR_EBREAKS_SHIFT (13U) +#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) +#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: PMACFG0 */ +/* + * PMA3CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) +#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) +#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) +#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) + +/* + * PMA2CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) +#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) +#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) +#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) + +/* + * PMA1CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) +#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) +#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) +#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) + +/* + * PMA0CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) +#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) +#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) +#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) + +/* Bitfield definition for register: PMACFG1 */ +/* + * PMA7CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) +#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) +#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) +#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) + +/* + * PMA6CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) +#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) +#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) +#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) + +/* + * PMA5CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) +#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) +#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) +#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) + +/* + * PMA4CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) +#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) +#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) +#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) + +/* Bitfield definition for register: PMACFG2 */ +/* + * PMA11CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) +#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) +#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) +#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) + +/* + * PMA10CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) +#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) +#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) +#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) + +/* + * PMA9CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) +#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) +#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) +#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) + +/* + * PMA8CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) +#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) +#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) +#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) + +/* Bitfield definition for register: PMACFG3 */ +/* + * PMA15CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) +#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) +#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) +#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) + +/* + * PMA14CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) +#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) +#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) +#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) + +/* + * PMA13CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) +#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) +#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) +#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) + +/* + * PMA12CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) +#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) +#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) +#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaaaaaaaaaa Reserved + * . . . . . . + * aaaa. . . aa011111111 Reserved + * aaaa. . . a0111111111 2^{12} + * aaaa. . . 01111111111 2^{13} + * . . . . . . + * aa01. . . 11111111111 2^{XLEN} + * a011. . . 11111111111 2^{XLEN+1} + * 0111. . . 11111111111 2^{XLEN+2} + * 1111. . . 11111111111 Reserved + */ +#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) +#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) +#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) +#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) +#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) +#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) +#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) +#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) +#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) +#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) +#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) +#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) +#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) +#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) +#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) +#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) +#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: SCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) +#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) +#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) +#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) +#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_IR_MASK (0x4U) +#define CSR_SCOUNTEREN_IR_SHIFT (2U) +#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) +#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_CY_MASK (0x1U) +#define CSR_SCOUNTEREN_CY_SHIFT (0U) +#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) +#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * PM (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MDCAUSE_PM_MASK (0x60U) +#define CSR_MDCAUSE_PM_SHIFT (5U) +#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) +#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) + +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * DC_WAROUND (RW) + * + * Cache Write-Around threshold + * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. + * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. + * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. + * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. + */ +#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) +#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) +#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) +#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) + +/* + * DC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) + +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * DPREF_EN (RW) + * + * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 + * 0:Disable hardware prefetch on load/store memory accesses + * 1:Enable hardware prefetch on load/store memory accesses + */ +#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) +#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) +#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) +#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) + +/* + * IPREF_EN (RW) + * + * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 + * 0:Disable hardware prefetch on instruction fetches + * 1:Enable hardware prefetch on instruction fetches + */ +#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) +#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) +#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) +#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * NBLD_EN (RW) + * + * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. + * 0:Load to memory regions are blocking. + * 1:Load to memory regions are non-blocking. + */ +#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) +#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) +#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) +#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) + +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: MSLIDELEG */ +/* + * PMOVI (RW) + * + * Delegate S-mode performance monitor overflow local interrupt to S-mode. + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) +#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) +#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) +#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Delegate S-mode bus read/write transaction error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) +#define CSR_MSLIDELEG_BWEI_SHIFT (17U) +#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) +#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Delegate S-mode slave-port ECC error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) +#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) +#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) +#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) + +/* Bitfield definition for register: MCLK_CTL */ +/* + * FUNIT (RW) + * + * Level 2 clock gating enable for function units listed in the following table. + * 16:integer arithmetic unit + * 17:integer permutation unit + * 18:integer mask unit + * 19:integer division unit + * 20:integer multiply and add unit + * 21:floating-point multiply and add + * unit + * 22:floating-point miscellaneous unit + * 23:floating-point division unit + * 24:load/store unit + * 31:25:Reserved + */ +#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) +#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) +#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) +#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) + +/* + * VI (RW) + * + * Level 1 clock gating enable for the vector/floating-point issue queues. + */ +#define CSR_MCLK_CTL_VI_MASK (0x8000U) +#define CSR_MCLK_CTL_VI_SHIFT (15U) +#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) +#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) + +/* + * VR (RW) + * + * Level 1 clock gating enable for the vector/floating-point register file. + */ +#define CSR_MCLK_CTL_VR_MASK (0x4000U) +#define CSR_MCLK_CTL_VR_SHIFT (14U) +#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) +#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) + +/* + * AQ (RW) + * + * Level 1 clock gating enable for ACE load/store queues. + */ +#define CSR_MCLK_CTL_AQ_MASK (0x2000U) +#define CSR_MCLK_CTL_AQ_SHIFT (13U) +#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) +#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) + +/* + * DQ (RW) + * + * Level 1 clock gating enable for data cache load/store queues. + */ +#define CSR_MCLK_CTL_DQ_MASK (0x1000U) +#define CSR_MCLK_CTL_DQ_SHIFT (12U) +#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) +#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) + +/* + * UQ (RW) + * + * Level 1 clock gating enable for uncached queues + */ +#define CSR_MCLK_CTL_UQ_MASK (0x800U) +#define CSR_MCLK_CTL_UQ_SHIFT (11U) +#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) +#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) + +/* + * FP (RW) + * + * Level 1 clock gating enable for scalar floating point issue unit and queues. + */ +#define CSR_MCLK_CTL_FP_MASK (0x400U) +#define CSR_MCLK_CTL_FP_SHIFT (10U) +#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) +#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) + +/* + * CLKGATE (RW) + * + * One-hot clock gating levels. + * 0:Level 1 clock gating in module level + * 1:Level 2 clock gating in unit level + * 2:Level 3 clock gating in VPU level + * 7:3:Reserved + */ +#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) +#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) +#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) +#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * SPF (RW) + * + * Indicates whether store page fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) +#define CSR_DEXC2DBG_SPF_SHIFT (18U) +#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) +#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) + +/* + * LPF (RW) + * + * Indicates whether load fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) +#define CSR_DEXC2DBG_LPF_SHIFT (17U) +#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) +#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) + +/* + * IPF (RW) + * + * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) +#define CSR_DEXC2DBG_IPF_SHIFT (16U) +#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) +#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * SEC (RW) + * + * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SEC_MASK (0x200U) +#define CSR_DEXC2DBG_SEC_SHIFT (9U) +#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) +#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: SLIE */ +/* + * PMOVI (RW) + * + * Enable S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_PMOVI_MASK (0x40000UL) +#define CSR_SLIE_PMOVI_SHIFT (18U) +#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) +#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_BWEI_MASK (0x20000UL) +#define CSR_SLIE_BWEI_SHIFT (17U) +#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) +#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Enable S-mode slave-port ECC error local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_IMECCI_MASK (0x10000UL) +#define CSR_SLIE_IMECCI_SHIFT (16U) +#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) +#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) + +/* Bitfield definition for register: SLIP */ +/* + * PMOVI (RW) + * + * Pending control and status of S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_PMOVI_MASK (0x40000UL) +#define CSR_SLIP_PMOVI_SHIFT (18U) +#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) +#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_BWEI_MASK (0x20000UL) +#define CSR_SLIP_BWEI_SHIFT (17U) +#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) +#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Pending control and status of S-mode slave-port ECC error local interrupt.. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_IMECCI_MASK (0x10000UL) +#define CSR_SLIP_IMECCI_SHIFT (16U) +#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) +#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) + +/* Bitfield definition for register: SDCAUSE */ +/* + * PM (RW) + * + * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0:User mode + * 1:Supervisor mode + * 2:Reserved + * 3:Machine mode + */ +#define CSR_SDCAUSE_PM_MASK (0x60U) +#define CSR_SDCAUSE_PM_SHIFT (5U) +#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) +#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) + +/* + * SDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. + * The value of SDCAUSE for precise exception: + * When scause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When scause == 2 (Illegal instruction): + * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When scause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When scause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of SDCAUSE for imprecise exception: + * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) +#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) +#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) +#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) + +/* Bitfield definition for register: SCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_SCCTLDATA_VA_MASK (0x1FU) +#define CSR_SCCTLDATA_VA_SHIFT (0U) +#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) +#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: SCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) +#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) +#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) +#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) +#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) +#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) +#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) +#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) +#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) +#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) +#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) +#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) +#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) +#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) +#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) +#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) +#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) +#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) +#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) +#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) +#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) +#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) +#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) +#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) +#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) +#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) +#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) +#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) +#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_IR_MASK (0x4U) +#define CSR_SCOUNTEROVF_IR_SHIFT (2U) +#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) +#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_CY_MASK (0x1U) +#define CSR_SCOUNTEROVF_CY_SHIFT (0U) +#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) +#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) +#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) +#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) +#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) +#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) +#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) +#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) +#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: SHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT3_SEL_SHIFT (4U) +#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) +#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) +#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT4_SEL_SHIFT (4U) +#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) +#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) +#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT5_SEL_SHIFT (4U) +#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) +#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) +#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT6_SEL_SHIFT (4U) +#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) +#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) +#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_regs.h similarity index 97% rename from bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmamux_regs.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_regs.h index 25ccad5e55..640355344e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmamux_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -61,4 +61,4 @@ typedef struct { #define DMAMUX_MUXCFG_XDMA_MUX7 (15UL) -#endif /* HPM_DMAMUX_H */ \ No newline at end of file +#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h new file mode 100644 index 0000000000..b444f371ec --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_SPI0_RX (0x0UL) +#define HPM_DMA_SRC_SPI0_TX (0x1UL) +#define HPM_DMA_SRC_SPI1_RX (0x2UL) +#define HPM_DMA_SRC_SPI1_TX (0x3UL) +#define HPM_DMA_SRC_SPI2_RX (0x4UL) +#define HPM_DMA_SRC_SPI2_TX (0x5UL) +#define HPM_DMA_SRC_SPI3_RX (0x6UL) +#define HPM_DMA_SRC_SPI3_TX (0x7UL) +#define HPM_DMA_SRC_UART0_RX (0x8UL) +#define HPM_DMA_SRC_UART0_TX (0x9UL) +#define HPM_DMA_SRC_UART1_RX (0xAUL) +#define HPM_DMA_SRC_UART1_TX (0xBUL) +#define HPM_DMA_SRC_UART2_RX (0xCUL) +#define HPM_DMA_SRC_UART2_TX (0xDUL) +#define HPM_DMA_SRC_UART3_RX (0xEUL) +#define HPM_DMA_SRC_UART3_TX (0xFUL) +#define HPM_DMA_SRC_UART4_RX (0x10UL) +#define HPM_DMA_SRC_UART4_TX (0x11UL) +#define HPM_DMA_SRC_UART5_RX (0x12UL) +#define HPM_DMA_SRC_UART5_TX (0x13UL) +#define HPM_DMA_SRC_UART6_RX (0x14UL) +#define HPM_DMA_SRC_UART6_TX (0x15UL) +#define HPM_DMA_SRC_UART7_RX (0x16UL) +#define HPM_DMA_SRC_UART7_TX (0x17UL) +#define HPM_DMA_SRC_MOT0_0 (0x18UL) +#define HPM_DMA_SRC_MOT0_1 (0x19UL) +#define HPM_DMA_SRC_MOT0_2 (0x1AUL) +#define HPM_DMA_SRC_MOT0_3 (0x1BUL) +#define HPM_DMA_SRC_MOT1_0 (0x1CUL) +#define HPM_DMA_SRC_MOT1_1 (0x1DUL) +#define HPM_DMA_SRC_MOT1_2 (0x1EUL) +#define HPM_DMA_SRC_MOT1_3 (0x1FUL) +#define HPM_DMA_SRC_MOT2_0 (0x20UL) +#define HPM_DMA_SRC_MOT2_1 (0x21UL) +#define HPM_DMA_SRC_MOT2_2 (0x22UL) +#define HPM_DMA_SRC_MOT2_3 (0x23UL) +#define HPM_DMA_SRC_MOT3_0 (0x24UL) +#define HPM_DMA_SRC_MOT3_1 (0x25UL) +#define HPM_DMA_SRC_MOT3_2 (0x26UL) +#define HPM_DMA_SRC_MOT3_3 (0x27UL) +#define HPM_DMA_SRC_GPTMR0_0 (0x28UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x29UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x2AUL) +#define HPM_DMA_SRC_GPTMR0_3 (0x2BUL) +#define HPM_DMA_SRC_GPTMR1_0 (0x2CUL) +#define HPM_DMA_SRC_GPTMR1_1 (0x2DUL) +#define HPM_DMA_SRC_GPTMR1_2 (0x2EUL) +#define HPM_DMA_SRC_GPTMR1_3 (0x2FUL) +#define HPM_DMA_SRC_GPTMR2_0 (0x30UL) +#define HPM_DMA_SRC_GPTMR2_1 (0x31UL) +#define HPM_DMA_SRC_GPTMR2_2 (0x32UL) +#define HPM_DMA_SRC_GPTMR2_3 (0x33UL) +#define HPM_DMA_SRC_GPTMR3_0 (0x34UL) +#define HPM_DMA_SRC_GPTMR3_1 (0x35UL) +#define HPM_DMA_SRC_GPTMR3_2 (0x36UL) +#define HPM_DMA_SRC_GPTMR3_3 (0x37UL) +#define HPM_DMA_SRC_I2C0 (0x38UL) +#define HPM_DMA_SRC_I2C1 (0x39UL) +#define HPM_DMA_SRC_I2C2 (0x3AUL) +#define HPM_DMA_SRC_I2C3 (0x3BUL) +#define HPM_DMA_SRC_XPI0_RX (0x3CUL) +#define HPM_DMA_SRC_XPI0_TX (0x3DUL) +#define HPM_DMA_SRC_DAC0 (0x3EUL) +#define HPM_DMA_SRC_DAC1 (0x3FUL) +#define HPM_DMA_SRC_ACMP_0 (0x40UL) +#define HPM_DMA_SRC_ACMP_1 (0x41UL) +#define HPM_DMA_SRC_ACMP_2 (0x42UL) +#define HPM_DMA_SRC_ACMP_3 (0x43UL) +#define HPM_DMA_SRC_MCAN0 (0x44UL) +#define HPM_DMA_SRC_MCAN1 (0x45UL) +#define HPM_DMA_SRC_MCAN2 (0x46UL) +#define HPM_DMA_SRC_MCAN3 (0x47UL) + + + +#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h new file mode 100644 index 0000000000..22bff319b2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[16]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 + * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + */ +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 1: soc gpio1; + * 2: cpu0 fastgpio + * 3: cpu1 fast gpio + */ +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOC (2UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) +#define GPIOM_ASSIGN_GPIOZ (15UL) + + +#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h new file mode 100644 index 0000000000..efeeaa312e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum hpm6300_gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_soc_gpio1 = 1, + gpiom_core0_fast = 2, + gpiom_core1_fast = 3, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h new file mode 100644 index 0000000000..22859a6ee4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h @@ -0,0 +1,1040 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Machine mode API: these APIs are supposed to be called at machine mode */ + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask and return mstatus + * + * @param[in] mask interrupt mask to be disabled + * @retval current mstatus value before irq disabled + */ +ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) +{ + return read_clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Delegate IRQ handling + * + * @param[in] mask interrupt mask to be delegated + */ +ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) +{ + set_csr(CSR_MIDELEG, mask); +} + +/** + * @brief Undelegate IRQ handling + * + * @param[in] mask interrupt mask to be undelegated + */ +ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) +{ + clear_csr(CSR_MIDELEG, mask); +} + + +/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ + +/** + * @brief Enable global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) +{ + set_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask and return sstatus for supervisor mode + * + * @param[in] mask interrupt mask to be disabled + * @retval current sstatus value before irq mask is disabled + */ +ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) +{ + return read_clear_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) +{ + set_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) +{ + set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ for supervisor mode + */ +ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) +{ + set_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) +{ + clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while (0) + + + +/* Supervisor mode */ + +/** + * @brief Enable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) +{ + set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Disable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Trigger software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) +{ + set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + + +/** + * @brief Complete software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) +{ + clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + +/* + * @brief Enable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Disable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +#define intc_set_s_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) + +/* + * @brief Complete IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Claim IRQ for supervisor mode + * + */ +#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) + +/* + * @brief Enable IRQ for supervisor mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_s_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_s_enable_irq(irq); \ + } while (0) + + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +/* Machine mode */ +extern int __vector_table[]; +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int) default_irq_entry; +} + +/* Supervisor mode */ +extern int __vector_s_table[]; +extern void default_s_irq_entry(void); +/** + * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) +{ + __vector_s_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) +{ + __vector_s_table[irq] = (int) default_s_irq_entry; +} + + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) +#endif + +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ +#define CONTEXT_REG_NUM (4 * (16 + 4)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#if __riscv_flen == 32 +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ +} +#else /*__riscv_flen == 64*/ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} + +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fssr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: DSP context registers are stored at word offset 41 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("rdov s0\n"); \ +} +/* + * @brief Restore DSP context + * @note DSP context registers are stored at word offset 41 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("csrw ucode, s0\n"); \ +} + +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile ("\n\ + c.li a5, 8\n\ + csrs mstatus, a5\n"); \ +} + +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("\n\ + lui a5, 0x1\n\ + addi a5, a5, -2048\n\ + csrc mie, a5\n"); \ + __asm volatile("\n\ + lui a4, 0xe4200\n");\ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)\n\ + fence io, io\n"); \ + __asm volatile("csrs mie, a5"); \ +} + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + + +#define ENTER_NESTED_IRQ_HANDLING_S() {\ + __asm volatile("\n\ + csrr s2, sepc \n\ + csrr s3, sstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile ("\n\ + c.li a5, 8\n\ + csrs sstatus, a5\n"); \ +} +#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ + __asm volatile("\n\ + lui a5, 0x1\n\ + addi a5, a5, -2048\n\ + csrc sie, a5\n"); \ + __asm volatile("\n\ + lui a4, 0xe4201\n");\ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)\n\ + fence io, io\n"); \ + __asm volatile("csrs sie, a5"); \ +} + + +/* + * @brief Exit Nested IRQ Handling at supervisor mode + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * SCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * SSTATUS = word offset 18 + */ +#define EXIT_NESTED_IRQ_HANDLING_S() { \ + __asm volatile("\n\ + csrw sstatus, s3 \n\ + csrw sepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +/* + * @brief Nested IRQ exit macro : Restore CSRs + * @param[in] irq Target interrupt number + */ +#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ +do { \ + clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ + __asm volatile("fence io, io"); \ + set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ +} while (0) + +#ifdef __cplusplus +#define EXTERN_C extern "C" +#else +#define EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +#define ISR_NAME_S(irq_num) default_isr_s_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("mret\n");\ +} + +/** + * @brief Declare an external interrupt handler for supervisor mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_s_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ +void ISR_NAME_S(irq_num)(void) {\ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_S();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_S(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_S();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("sret\n");\ +} + +#else + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) { \ + isr(); \ +} + +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_S(irq_num)(void) { \ + isr(); \ +} + +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) {\ + isr();\ +} + +/* Supervisor mode */ + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_s_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR_S(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_s_isr(void) {\ + isr();\ +} + +#define CSR_MSTATUS_MPP_S_MODE (0x1) +#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ +do { \ + if (label) { \ + write_csr(mepc, label); \ + } \ + clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ + set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ +} while(0) + +typedef void (*s_mode_entry)(void); + +/** + * @brief Switch mode to supervisor from machine + * + * @param[in] entry - entry point after mode is switched + */ +static inline void switch_to_s_mode(s_mode_entry entry) +{ + write_csr(CSR_SEPC, entry); + MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); + if (entry) { + __asm("mret"); + } +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h new file mode 100644 index 0000000000..cf272e6f79 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[488]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * … + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * HYS (RW) + * + * schmitt trigger enable + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) +#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) +#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) +#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) + +/* + * PRS (RW) + * + * select pull up/down internal resistance strength: + * For pull down, only have 100 Kohm resistance + * For pull up: + * 00: 100 KOhm + * 01: 47 KOhm + * 10: 22 KOhm + * 11: 22 KOhm + */ +#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) +#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) +#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) +#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) +#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) +#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * KE (RW) + * + * keeper capability enable + * 0: keeper disable + * 1: keeper enable + */ +#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) +#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) +#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) +#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SR (RW) + * + * slew rate + * 0: Slow slew rate + * 1: Fast slew rate + */ +#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) +#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) +#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) +#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) + +/* + * SPD (RW) + * + * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise + * 00: Slow frequency slew rate(50Mhz) + * 01: Medium frequency slew rate(100 Mhz) + * 10: Fast frequency slew rate(150 Mhz) + * 11: Max frequency slew rate(200Mhz) + */ +#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) +#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) +#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) +#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) + +/* + * DS (RW) + * + * drive strength + * 1.8V Mode: + * 000: 260 Ohm + * 001: 260 Ohm + * 010: 130 Ohm + * 011: 88 Ohm + * 100: 65 Ohm + * 101: 52 Ohm + * 110: 43 Ohm + * 111: 37 Ohm + * 3.3V Mode: + * 000: 157 Ohm + * 001: 157 Ohm + * 010: 78 Ohm + * 011: 53 Ohm + * 100: 39 Ohm + * 101: 32 Ohm + * 110: 26 Ohm + * 111: 23 Ohm + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PB16 (48UL) +#define IOC_PAD_PB17 (49UL) +#define IOC_PAD_PB18 (50UL) +#define IOC_PAD_PB19 (51UL) +#define IOC_PAD_PB20 (52UL) +#define IOC_PAD_PB21 (53UL) +#define IOC_PAD_PB22 (54UL) +#define IOC_PAD_PB23 (55UL) +#define IOC_PAD_PB24 (56UL) +#define IOC_PAD_PB25 (57UL) +#define IOC_PAD_PB26 (58UL) +#define IOC_PAD_PB27 (59UL) +#define IOC_PAD_PB28 (60UL) +#define IOC_PAD_PB29 (61UL) +#define IOC_PAD_PB30 (62UL) +#define IOC_PAD_PB31 (63UL) +#define IOC_PAD_PC00 (64UL) +#define IOC_PAD_PC01 (65UL) +#define IOC_PAD_PC02 (66UL) +#define IOC_PAD_PC03 (67UL) +#define IOC_PAD_PC04 (68UL) +#define IOC_PAD_PC05 (69UL) +#define IOC_PAD_PC06 (70UL) +#define IOC_PAD_PC07 (71UL) +#define IOC_PAD_PC08 (72UL) +#define IOC_PAD_PC09 (73UL) +#define IOC_PAD_PC10 (74UL) +#define IOC_PAD_PC11 (75UL) +#define IOC_PAD_PC12 (76UL) +#define IOC_PAD_PC13 (77UL) +#define IOC_PAD_PC14 (78UL) +#define IOC_PAD_PC15 (79UL) +#define IOC_PAD_PC16 (80UL) +#define IOC_PAD_PC17 (81UL) +#define IOC_PAD_PC18 (82UL) +#define IOC_PAD_PC19 (83UL) +#define IOC_PAD_PC20 (84UL) +#define IOC_PAD_PC21 (85UL) +#define IOC_PAD_PC22 (86UL) +#define IOC_PAD_PC23 (87UL) +#define IOC_PAD_PC24 (88UL) +#define IOC_PAD_PC25 (89UL) +#define IOC_PAD_PC26 (90UL) +#define IOC_PAD_PC27 (91UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (417UL) +#define IOC_PAD_PX02 (418UL) +#define IOC_PAD_PX03 (419UL) +#define IOC_PAD_PX04 (420UL) +#define IOC_PAD_PX05 (421UL) +#define IOC_PAD_PX06 (422UL) +#define IOC_PAD_PX07 (423UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) +#define IOC_PAD_PZ00 (480UL) +#define IOC_PAD_PZ01 (481UL) +#define IOC_PAD_PZ02 (482UL) +#define IOC_PAD_PZ03 (483UL) +#define IOC_PAD_PZ04 (484UL) +#define IOC_PAD_PZ05 (485UL) +#define IOC_PAD_PZ06 (486UL) +#define IOC_PAD_PZ07 (487UL) + + +#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h new file mode 100644 index 0000000000..223f5145c0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h @@ -0,0 +1,958 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA00_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA00_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA01_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA01_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA02_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA02_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA03_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA03_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA04_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA05_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA06_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA06_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA06_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA07_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA07_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA07_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA07_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA08_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA08_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA09_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA09_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA09_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA10_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA10_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA10_FUNC_CTL_PWM3_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA11_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA11_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA11_FUNC_CTL_PWM3_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA12_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA12_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA12_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA12_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA12_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA12_FUNC_CTL_TRGM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA13_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA13_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA13_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA13_FUNC_CTL_TRGM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA13_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA14_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA14_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA14_FUNC_CTL_TRGM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA14_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA15_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA15_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA15_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA16_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA16_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA17_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA17_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA18_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA18_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA19_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA19_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA19_FUNC_CTL_TRGM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA20_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA20_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA20_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA20_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA20_FUNC_CTL_PWM3_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA21_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA21_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA21_FUNC_CTL_PWM3_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA22_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA22_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA22_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA22_FUNC_CTL_PWM3_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA23_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA23_FUNC_CTL_PWM3_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA24_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA24_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA24_FUNC_CTL_PWM3_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA25_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA25_FUNC_CTL_PWM3_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA26_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA26_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA26_FUNC_CTL_PWM3_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA27_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA27_FUNC_CTL_PWM3_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA28_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA28_FUNC_CTL_TRGM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA29_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA29_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA30_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA30_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA31_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA31_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA31_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB00_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB00_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB01_FUNC_CTL_TRGM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB02_FUNC_CTL_TRGM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB03_FUNC_CTL_TRGM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB04_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB04_FUNC_CTL_TRGM3_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB05_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB05_FUNC_CTL_TRGM3_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB06_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB07_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB07_FUNC_CTL_TRGM3_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB08_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB09_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB12_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB12_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB13_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB13_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB14_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB15_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB15_FUNC_CTL_TRGM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB16_FUNC_CTL function mux definitions */ +#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB16_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB16_FUNC_CTL_TRGM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB17_FUNC_CTL function mux definitions */ +#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB17_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB17_FUNC_CTL_TRGM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB18_FUNC_CTL function mux definitions */ +#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB18_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB18_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB18_FUNC_CTL_TRGM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB19_FUNC_CTL function mux definitions */ +#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB19_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB19_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB19_FUNC_CTL_TRGM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB20_FUNC_CTL function mux definitions */ +#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB20_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB20_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB20_FUNC_CTL_TRGM2_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB21_FUNC_CTL function mux definitions */ +#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB21_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB21_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB21_FUNC_CTL_TRGM2_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB22_FUNC_CTL function mux definitions */ +#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB22_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB22_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB22_FUNC_CTL_TRGM2_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB22_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB23_FUNC_CTL function mux definitions */ +#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB23_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB23_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB23_FUNC_CTL_TRGM2_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB23_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB24_FUNC_CTL function mux definitions */ +#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB24_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB24_FUNC_CTL_PWM2_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB24_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB25_FUNC_CTL function mux definitions */ +#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB25_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB25_FUNC_CTL_PWM2_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB25_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB26_FUNC_CTL function mux definitions */ +#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB26_FUNC_CTL_PWM2_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB26_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB27_FUNC_CTL function mux definitions */ +#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB27_FUNC_CTL_PWM2_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB27_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB28_FUNC_CTL function mux definitions */ +#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB28_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB28_FUNC_CTL_PWM2_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB28_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB29_FUNC_CTL function mux definitions */ +#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB29_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB29_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB29_FUNC_CTL_PWM2_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB29_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB30_FUNC_CTL function mux definitions */ +#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB30_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB30_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB30_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB30_FUNC_CTL_PWM2_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB31_FUNC_CTL function mux definitions */ +#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB31_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB31_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB31_FUNC_CTL_PWM2_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC00_FUNC_CTL function mux definitions */ +#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC00_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC00_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC00_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC01_FUNC_CTL function mux definitions */ +#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC01_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC01_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC02_FUNC_CTL function mux definitions */ +#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC02_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC02_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC02_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC03_FUNC_CTL function mux definitions */ +#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC03_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC03_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC03_FUNC_CTL_TRGM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC04_FUNC_CTL function mux definitions */ +#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC04_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC04_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC04_FUNC_CTL_TRGM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC05_FUNC_CTL function mux definitions */ +#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC05_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC05_FUNC_CTL_TRGM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC05_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC06_FUNC_CTL function mux definitions */ +#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC06_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC06_FUNC_CTL_TRGM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC06_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC07_FUNC_CTL function mux definitions */ +#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC07_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC07_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC07_FUNC_CTL_TRGM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC07_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC08_FUNC_CTL function mux definitions */ +#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC08_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC08_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC08_FUNC_CTL_PWM2_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC08_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC09_FUNC_CTL function mux definitions */ +#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC09_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC09_FUNC_CTL_PWM2_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC10_FUNC_CTL function mux definitions */ +#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC10_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PC11_FUNC_CTL function mux definitions */ +#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC11_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PC12_FUNC_CTL function mux definitions */ +#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC12_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC12_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PC13_FUNC_CTL function mux definitions */ +#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC13_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC13_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC13_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC14_FUNC_CTL function mux definitions */ +#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC14_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC15_FUNC_CTL function mux definitions */ +#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC15_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC15_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC16_FUNC_CTL function mux definitions */ +#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC16_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC16_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC16_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC17_FUNC_CTL function mux definitions */ +#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC17_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PC18_FUNC_CTL function mux definitions */ +#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC18_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PC19_FUNC_CTL function mux definitions */ +#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC19_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PC20_FUNC_CTL function mux definitions */ +#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC20_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC20_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PC20_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC21_FUNC_CTL function mux definitions */ +#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC21_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC21_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC21_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PC21_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC22_FUNC_CTL function mux definitions */ +#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC22_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC22_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC22_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC23_FUNC_CTL function mux definitions */ +#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC23_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC23_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC24_FUNC_CTL function mux definitions */ +#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC24_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC25_FUNC_CTL function mux definitions */ +#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC25_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC26_FUNC_CTL function mux definitions */ +#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC26_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC27_FUNC_CTL function mux definitions */ +#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC27_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC27_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY01_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY02_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY03_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY04_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY05_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY06_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY07_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ02_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ03_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PZ04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PZ05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ06_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ07_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + + +#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.c new file mode 100644 index 0000000000..c55600dcdc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address; + register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } + + write_csr(CSR_MSTATUS, csr); +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i(void) +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h new file mode 100644 index 0000000000..e328193a07 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" +#include "hpm_soc.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 32KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 64B */ +#define HPM_L1C_CACHELINE_SIZE (64) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h new file mode 100644 index 0000000000..db03cea0ae --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MCAN_SOC_H +#define HPM_MCAN_SOC_H + +#include +#include "hpm_mcan_regs.h" + +/** + * @brief TSU External Timebase Sources + */ +#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN1 (1U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN2 (2U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN3 (3U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_PTP (4U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_PTP) + +#ifdef __cpluspus +extern "C" { +#endif + +/** + * @brief Set External Timebase Source for MCAN TSU + * @param [in] ptr MCAN base + * @param [in] src External Timebase source + */ +static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) +{ + ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); +} + +/** + * @brief Enable Standby Pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Disable Standby pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Get RAM base for MCAN + * @param [in] ptr MCAN base + * @return RAM base for MCAN + */ +static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) +{ + return (uint32_t) &ptr->MESSAGE_BUFF[0]; +} + +/** + * @brief Get the MCAN RAM offset in the dedicated/shared RAM for + * @param [in] ptr MCAN base + * @return RAM offset for MCAN + */ +static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) +{ + return 0U; +} + +/** + * @brief Get MCAN RAM size + * @param [in] ptr MCAN base + * @return RAM size in bytes + */ +static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) +{ + return sizeof(ptr->MESSAGE_BUFF); +} + +#ifdef __cpluspus +} +#endif + +#endif /* HPM_MCAN_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h new file mode 100644 index 0000000000..9875958d95 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define CORE0_ILM_LOCAL_BASE (0x0U) +#define CORE0_ILM_SIZE_IN_BYTE (0x20000U) +#define CORE0_DLM_LOCAL_BASE (0x80000U) +#define CORE0_DLM_SIZE_IN_BYTE (0x20000U) +#define CORE1_ILM_LOCAL_BASE (0x20000U) +#define CORE1_ILM_SIZE_IN_BYTE (0x20000U) +#define CORE1_DLM_LOCAL_BASE (0xA0000U) +#define CORE1_DLM_SIZE_IN_BYTE (0x20000U) +#define CORE0_ILM_SYSTEM_BASE (0x0U) +#define CORE0_DLM_SYSTEM_BASE (0x80000U) +#define CORE1_ILM_SYSTEM_BASE (0x20000U) +#define CORE1_DLM_SYSTEM_BASE (0xA0000U) + +#define HPM_CORE0 (0U) +#define HPM_CORE1 (1U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + return addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.c new file mode 100644 index 0000000000..dbab299955 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP->SHADOW[addr] : HPM_OTPSHW->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->FUSE[addr]; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + /* Wait until LDO is ready */ + while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { + } + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + for (uint32_t i = 0; i < num_of_words; i++) { + HPM_OTP->FUSE[addr++] = *src++; + } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h new file mode 100644 index 0000000000..8c9559a986 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +} otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +} otp_lock_option_t; + +enum { + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + +/** + * @brief Initialize OTP controller + */ +void otp_init(void); + +/** + * @brief De-initialize OTP controller + */ +void otp_deinit(void); + +/** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_shadow(uint32_t addr); + +/** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_ip(uint32_t addr); + +/** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + +/** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ +hpm_stat_t otp_reload(otp_region_t region); + +/** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + +/** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [val] val Data to be written + * @return API execution status + */ +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h similarity index 60% rename from bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h index 4f0b34dc8b..e99e0837a5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,28 +18,13 @@ * @ingroup io_interfaces * @{ */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) -#define PCFG_DCDC_MODE_TURN_OFF (0U) -#define PCFG_DCDC_MODE_PERFORMACE (1U) -#define PCFG_DCDC_MODE_GENERIC (2U) -#define PCFG_DCDC_MODE_EXPERT (3U) - -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x11U) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x10U) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x01U) - -/* @brief PCFG modules */ -typedef enum { - pcfg_module_fuse = 0, - pcfg_module_sram, - pcfg_module_vad, - pcfg_module_gpio, - pcfg_module_ioc, - pcfg_module_timer, - pcfg_module_wdog, - pcfg_module_uart, - pcfg_module_debug, -} pcfg_module_t; +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) +#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) /* @brief PCFG irc24m reference */ typedef enum { @@ -47,6 +32,39 @@ typedef enum { pcfg_irc24m_reference_24m_xtal = 1 } pcfg_irc24m_reference_t; +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_fuse = 0, + pcfg_pmc_periph_ram = 2, + pcfg_pmc_periph_vad = 4, + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, + pcfg_pmc_periph_debug = 16, +} pcfg_pmc_periph_t; + /* @brief PCFG status */ enum { status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), @@ -76,7 +94,7 @@ extern "C" { /** * @brief bandgap disable power save mode * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) { @@ -86,13 +104,18 @@ static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) /** * @brief bandgap enable power save mode * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) { ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; } +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) { ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; @@ -101,7 +124,7 @@ static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) /** * @brief bandgap enable low power mode * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) { @@ -111,9 +134,9 @@ static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) /** * @brief check if bandgap is trimmed or not * - * @param ptr base address + * @param[in] ptr base address * - * @return true if bandgap is trimmed + * @retval true if bandgap is trimmed */ static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) { @@ -123,7 +146,7 @@ static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) /** * @brief bandgap reload trim value * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) { @@ -133,7 +156,7 @@ static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) /** * @brief turn off LDO 1V * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) { @@ -143,25 +166,17 @@ static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) /** * @brief turn of LDO 1V * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) { ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; } -/* - * @brief set output voltage of LDO 1V in mV - * @param ptr base address - * @param mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - /** * @brief turn off LDO2P5 * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) { @@ -171,7 +186,7 @@ static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) /** * @brief turn on LDO 2.5V * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) { @@ -181,33 +196,18 @@ static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) /** * @brief check if LDO 2.5V is stable * - * @param ptr base address + * @param[in] ptr base address * - * @return true if LDO2P5 is stable + * @retval true if LDO2P5 is stable */ static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) { return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); } -/* - * @brief set output voltage of LDO 2.5V in mV - * @param ptr base address - * @param mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param ptr base address - * @param mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); /* * @brief check if DCDC is stable or not - * @param ptr base address + * @param[in] ptr base address * @retval true if DCDC is stable */ static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) @@ -216,39 +216,31 @@ static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) } /* - * @brief check if DCDC is stable or not - * @param ptr base address + * @brief set DCDC work mode + * @param[in] ptr base address */ static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) { - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(ptr->DCDC_MODE); + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); } -/* - * @brief set DCDC voltage at standby mode - * @param ptr base address - * @param mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - /** * @brief set low power current limit * - * @param ptr base address - * @param limit current limit at low power mode - * @param under_limit set to true means current is less than limit + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + * @param[in] over_limit set to true means current is greater than limit */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, uint8_t limit, bool under_limit) +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) { ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(!under_limit); + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); } /** * @brief disable power loss protection * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) { @@ -258,7 +250,7 @@ static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) /** * @brief enable power loss protection * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) { @@ -268,9 +260,9 @@ static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) /** * @brief check if power loss flag is set * - * @param ptr base address + * @param[in] ptr base address * - * @return true if power loss is set + * @retval true if power loss is set */ static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) { @@ -280,7 +272,7 @@ static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) /** * @brief disable over voltage protection * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) { @@ -290,7 +282,7 @@ static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) /** * @brief enable over voltage protection * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) { @@ -300,8 +292,8 @@ static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) /** * @brief checkover voltage flag * - * @param ptr base address - * @return true if flag is set + * @param[in] ptr base address + * @retval true if flag is set */ static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) { @@ -311,7 +303,7 @@ static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) /** * @brief disable current measurement * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) { @@ -321,7 +313,7 @@ static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) /** * @brief enable current measurement * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) { @@ -331,31 +323,23 @@ static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) /** * @brief check if measured current is valid * - * @param ptr base address + * @param[in] ptr base address * - * @return true if measured current is valid + * @retval true if measured current is valid */ static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) { return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; } -/* - * @brief get current DCDC current level in mA - * - * @param ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - /** * @brief get DCDC start time in number of 24MHz clock cycles * - * @param ptr base address + * @param[in] ptr base address * - * @return dcdc start time in cycles + * @retval dcdc start time in cycles */ -static inline uint32_t pcfg_get_dcdc_start_time_in_cycle(PCFG_Type *ptr) +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) { return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); } @@ -363,11 +347,11 @@ static inline uint32_t pcfg_get_dcdc_start_time_in_cycle(PCFG_Type *ptr) /** * @brief get DCDC resume time in number of 24MHz clock cycles * - * @param ptr base address + * @param[in] ptr base address * - * @return dcdc resuem time in cycles + * @retval dcdc resuem time in cycles */ -static inline uint32_t pcfg_get_dcdc_resume_time_in_cycle(PCFG_Type *ptr) +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) { return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); } @@ -375,10 +359,10 @@ static inline uint32_t pcfg_get_dcdc_resume_time_in_cycle(PCFG_Type *ptr) /** * @brief set DCDC start time in 24MHz clock cycles * - * @param ptr base address - * @param cycles start time in cycles + * @param[in] ptr base address + * @param[in] cycles start time in cycles */ -static inline void pcfg_set_dcdc_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) { ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); } @@ -386,18 +370,29 @@ static inline void pcfg_set_dcdc_start_time_in_cycle(PCFG_Type *ptr, uint32_t cy /** * @brief set DCDC resuem time in 24MHz clock cycles * - * @param ptr base address - * @param cycles resume time in cycles + * @param[in] ptr base address + * @param[in] cycles resume time in cycles */ -static inline void pcfg_set_dcdc_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) { ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); } +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + /** * @brief disable power trap * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_disable_power_trap(PCFG_Type *ptr) { @@ -407,7 +402,7 @@ static inline void pcfg_disable_power_trap(PCFG_Type *ptr) /** * @brief enable power trap * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_enable_power_trap(PCFG_Type *ptr) { @@ -417,9 +412,9 @@ static inline void pcfg_enable_power_trap(PCFG_Type *ptr) /** * @brief check if power trap is triggered * - * @param ptr base address + * @param[in] ptr base address * - * @return true if power trap is triggered + * @retval true if power trap is triggered */ static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) { @@ -429,7 +424,7 @@ static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) /** * @brief clear power trap trigger flag * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) { @@ -439,7 +434,7 @@ static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) /** * @brief disable dcdc retention * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) { @@ -449,7 +444,7 @@ static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) /** * @brief enable dcdc retention to retain soc sram data * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) { @@ -459,8 +454,8 @@ static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) /** * @brief clear wakeup cause flag * - * @param ptr base address - * @param mask mask of flags to be cleared + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared */ static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) { @@ -470,9 +465,9 @@ static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) /** * @brief get wakeup cause * - * @param ptr base address + * @param[in] ptr base address * - * @return mask of wake cause + * @retval mask of wake cause */ static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) { @@ -482,8 +477,8 @@ static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) /** * @brief enable wakeup source * - * @param ptr base address - * @param mask wakeup source mask + * @param[in] ptr base address + * @param[in] mask wakeup source mask */ static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) { @@ -493,8 +488,8 @@ static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) /** * @brief disable wakeup source * - * @param ptr base address - * @param mask source to be disabled as wakeup source + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source */ static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) { @@ -502,17 +497,63 @@ static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) } /** - * @brief set clock gate mode in pmic domain + * @brief set clock gate mode in vpmc domain * - * @param ptr base address - * @param mode clock gate mode mask + * @param[in] ptr base address + * @param[in] mode clock gate mode mask */ -static inline void pcfg_set_clock_gate_in_pmic(PCFG_Type *ptr, uint32_t mode) +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) { ptr->SCG_CTRL = mode; } -static inline void pcfg_config_debug_stop_source(PCFG_Type *ptr, uint8_t mask) +/** + * @brief Disable CPU0 debug stop notficiation to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Enable CPU0 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Disable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Enable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Configure CPU core debug stop notification to peripherals + * + * @param[in] ptr + * @param[in] mask + */ +static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) { ptr->DEBUG_STOP = mask; } @@ -520,9 +561,9 @@ static inline void pcfg_config_debug_stop_source(PCFG_Type *ptr, uint8_t mask) /** * @brief check if irc24m is trimmed * - * @param ptr base address + * @param[in] ptr base address * - * @return true if it is trimmed + * @retval true if it is trimmed */ static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) { @@ -532,7 +573,7 @@ static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) /** * @brief reload irc24m trim value * - * @param ptr base address + * @param[in] ptr base address */ static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) { @@ -542,11 +583,52 @@ static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) /** * @brief config irc24m track * - * @param ptr base address - * @param config config data + * @param[in] ptr base address + * @param[in] config config data */ void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + #ifdef __cplusplus } #endif @@ -554,4 +636,4 @@ void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); * @} */ -#endif /* HPM_PMIC_PCFG_DRV_H */ +#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h new file mode 100644 index 0000000000..b454667b37 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h @@ -0,0 +1,925 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ + __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * LOWPOWER_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) +#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) +#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) +#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) +#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) +#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) +#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) +#define PCFG_LDO1P1_ENABLE_SHIFT (16U) +#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) +#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: trun off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RW) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * DISABLE_POWER_LOSS (RW) + * + * disable power loss protection + * 0: power loss protection enabled, DCDC shuts down when power loss + * 1: power loss protection disabled, DCDC try working after power voltage drop + */ +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * ouput over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit0-1: fuse + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + * bit16-17:debug + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: DEBUG_STOP */ +/* + * CPU1 (RW) + * + * Stop peripheral when CPU1 enter debug mode + * 0: peripheral keep running when CPU1 in debug mode + * 1: peripheral enter debug mode when CPU1 enter debug + */ +#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) +#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) +#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) + +/* + * CPU0 (RW) + * + * Stop peripheral when CPU0 enter debug mode + * 0: peripheral keep running when CPU0 in debug mode + * 1: peripheral enter debug mode when CPU0 enter debug + */ +#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) +#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) +#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h similarity index 99% rename from bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h index ae9378a07d..0369149bdd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -208,4 +208,4 @@ typedef struct { -#endif /* HPM_PGPR_H */ \ No newline at end of file +#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_plic_drv.h new file mode 100644 index 0000000000..9595051f90 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_plic_drv.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h new file mode 100644 index 0000000000..b611842ecb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_WDOG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h similarity index 98% rename from bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h index a0b2c0da32..b1eb6e6ac5 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h similarity index 99% rename from bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h index b4c2e280e0..21cb6fc237 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -191,4 +191,4 @@ typedef struct { -#endif /* HPM_PPOR_H */ \ No newline at end of file +#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h new file mode 100644 index 0000000000..849508c575 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h @@ -0,0 +1,1021 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_sdp_drv.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, + uint32_t serial_root_clk_freq, + uint32_t data_valid_time, + xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t + (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t + (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t + (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t + (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t + (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t + (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief XPI RAM driver interface + */ +typedef struct { + /**< XPI RAM driver interface: API version */ + uint32_t version; + + /**< Get XPI RAM configuration based on cfg_option */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); + + /**< XPI RAM driver interface: Initialize XPI RAM */ + hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); +} xpi_ram_driver_interface_t; + +/** + * @brief SDP API interface + */ +typedef struct { + /**< SDP API interface: API version */ + uint32_t version; + /**< SDP API interface: Initialize IP */ + hpm_stat_t (*sdp_ip_init)(void); + /**< SDP API interface: Deinitialize IP */ + hpm_stat_t (*sdp_ip_deinit)(void); + /**< SDP API interface: Set AES key */ + hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: AES ECB crypto operation */ + hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API interface: AES CBC crypto operation */ + hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API interface: AES CTR crypto operation */ + hpm_stat_t + (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API interface: AES CCM encryption */ + hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: AES CCM Decrypt and verify */ + hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: memcpy */ + hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); + /**< SDP API interface: memset */ + hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); + /**< SDP API interface: HASH initialization */ + hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + /**< SDP API interface: HASH update */ + hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + /**< SDP API interface: HASH finish */ + hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + /**< SDP API interface: Set SM4 Key */ + hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: SM4 Crypto ECB mode */ + hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API Interface: SM4 Crypto CBC mode*/ + hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API Interface: SM4 CTR mode */ + hpm_stat_t + (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API Interface: SM4 CCM Encryption */ + hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API Interface: SM4 CCM Decrypt and Verify */ + hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); +} sdp_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + const hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const xpi_ram_driver_interface_t *xpi_ram_driver_if; + /**< Bootloader API table: sdp driver interface address */ + const sdp_driver_interface_t *sdp_driver_if; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Setup API Runtime environment on demand + */ +static inline void rom_xpi_nor_api_setup(void) +{ + static const uint32_t s_setup_code[] = { + 0x300027f3, 0xf6b36719, 0xe68100e7, 0x90738fd9, 0x80823007, + }; + if (ROM_API_TABLE_ROOT->version == 0x56010000UL) { + typedef void (*api_setup_entry_t)(void); + api_setup_entry_t entry = (api_setup_entry_t) &s_setup_code[0]; + entry(); + } +} + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + xpi_nor_config_option_t *cfg_option) +{ + rom_xpi_nor_api_setup(); + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); +} + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if + ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API execution address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, + xpi_nor_config_t *config, + xpi_nor_config_option_t *cfg_option) +{ + rom_xpi_nor_api_setup(); + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + uint32_t property_id, + uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + if ((base != HPM_XPI0) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) + || ((offset & 0xFFF) != 0)) { + return false; + } + static const uint8_t k_mc_xpi_remap_config[] = { + 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, + 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, + 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, + }; + typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); + remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; + bool result = cb(base, start, len, offset); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_disable[] = { + 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, + 0xf5, 0x42, 0x82, 0x80, + }; + typedef void (*remap_disable_cb_t)(XPI_Type *); + remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; + cb(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_enabled[] = { + 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, + }; + typedef bool (*remap_chk_cb_t)(XPI_Type *); + remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; + return chk_cb(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + if (base != HPM_XPI0) { + return false; + } + static const uint8_t k_mc_exip_region_config[] = { + 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, + 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, + 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, + 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, + 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, + 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, + 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, + 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, + 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, + }; + typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); + exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; + cb(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return true; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @@param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + static const uint8_t k_mc_exip_region_disable[] = { + 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, + 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, + 0xe7, 0xd0, 0x82, 0x80 + }; + typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); + exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; + cb(base, index); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_enable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, + 0xf5, 0xc0, 0x82, 0x80 + }; + typedef void (*exip_enable_cb_t)(XPI_Type *); + exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; + cb(base); +} + +/** + * @brief Disable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_disable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, + 0x82, 0x80 + }; + typedef void (*exip_disable_cb_t)(XPI_Type *); + exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; + cb(base); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/*********************************************************************************************************************** + * + * + * XPI RAM Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Get XPI RAM configuration based on cfg_option + * @param [in] base XPI base address + * @param [out] ram_cfg XPI RAM configuration structure + * @param [in] cfg_option XPI RAM configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, + xpi_ram_config_t *ram_cfg, + xpi_ram_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); +} + +/** + * @brief Initialize XPI RAM + * @param [in] base XPI base address + * @param [in] ram_cfg XPI ram configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); +} + +/*********************************************************************************************************************** + * + * + * SDP Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Initialize SDP IP + */ +static inline void rom_sdp_init(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); +} + +/** + * @brief De-initialize SDP IP + */ +static inline void rom_sdp_deinit(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); +} + +/** + * @brief Set AES key to SDP + * @param [in] aes_ctx AES context + * @param [in] key AES key buffer + * @param [in] key_bits AES key-bit option + * @param[in] key_idx AES key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] len Data length for AES encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); +} + +/** + * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] length Data length for AES encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); +} + +/** + * @brief Set SM4 key to SDP + * @param [in] sm4_ctx SM4 context + * @param [in] key SM4 key buffer + * @param [in] key_bits SM4 key-bit option + * @param[in] key_idx SM4 key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] len Data length for SM4 encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); +} + +/** + * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); +} + +/** + * @brief HASH initialization + * @param [in] hash_ctx HASH context + * @param [in] alg HASH algorithm + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); +} + +/** + * @brief HASH Update + * @param [in] hash_ctx HASH context + * @param [in] data Data for HASH operation + * @param [in] length of the data for HASH operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); +} + +/** + * @brief HASH finialize + * @param [in] hash_ctx HASH context + * @param [out] digest the output digest + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); +} + +/** + * @brief SDP memcpy operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memcpy + * @param [in] src Source address for memcpy + * @param [in] length Size of data for memcpy operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); +} + +/** + * @brief SDP memset operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memset + * @param [in] pattern pattern for memset + * @param [in] length Size of data for memset operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi_xpi_soc_def.h new file mode 100644 index 0000000000..ea3ba9e8f9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union { + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml new file mode 100644 index 0000000000..ce9cb93e72 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml @@ -0,0 +1,44747 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml new file mode 100644 index 0000000000..de6e896482 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml @@ -0,0 +1,770 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h new file mode 100644 index 0000000000..ea9c0a00cb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h @@ -0,0 +1,709 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ +#define IRQn_GPIO1_A 8 /* GPIO1_A IRQ */ +#define IRQn_GPIO1_B 9 /* GPIO1_B IRQ */ +#define IRQn_GPIO1_C 10 /* GPIO1_C IRQ */ +#define IRQn_GPIO1_D 11 /* GPIO1_D IRQ */ +#define IRQn_GPIO1_X 12 /* GPIO1_X IRQ */ +#define IRQn_GPIO1_Y 13 /* GPIO1_Y IRQ */ +#define IRQn_GPIO1_Z 14 /* GPIO1_Z IRQ */ +#define IRQn_ADC0 15 /* ADC0 IRQ */ +#define IRQn_ADC1 16 /* ADC1 IRQ */ +#define IRQn_ADC2 17 /* ADC2 IRQ */ +#define IRQn_SDFM 18 /* SDFM IRQ */ +#define IRQn_DAC0 19 /* DAC0 IRQ */ +#define IRQn_DAC1 20 /* DAC1 IRQ */ +#define IRQn_ACMP_0 21 /* ACMP[0] IRQ */ +#define IRQn_ACMP_1 22 /* ACMP[1] IRQ */ +#define IRQn_ACMP_2 23 /* ACMP[2] IRQ */ +#define IRQn_ACMP_3 24 /* ACMP[3] IRQ */ +#define IRQn_SPI0 25 /* SPI0 IRQ */ +#define IRQn_SPI1 26 /* SPI1 IRQ */ +#define IRQn_SPI2 27 /* SPI2 IRQ */ +#define IRQn_SPI3 28 /* SPI3 IRQ */ +#define IRQn_UART0 29 /* UART0 IRQ */ +#define IRQn_UART1 30 /* UART1 IRQ */ +#define IRQn_UART2 31 /* UART2 IRQ */ +#define IRQn_UART3 32 /* UART3 IRQ */ +#define IRQn_UART4 33 /* UART4 IRQ */ +#define IRQn_UART5 34 /* UART5 IRQ */ +#define IRQn_UART6 35 /* UART6 IRQ */ +#define IRQn_UART7 36 /* UART7 IRQ */ +#define IRQn_CAN0 37 /* CAN0 IRQ */ +#define IRQn_CAN1 38 /* CAN1 IRQ */ +#define IRQn_CAN2 39 /* CAN2 IRQ */ +#define IRQn_CAN3 40 /* CAN3 IRQ */ +#define IRQn_PTPC 41 /* PTPC IRQ */ +#define IRQn_WDG0 42 /* WDG0 IRQ */ +#define IRQn_WDG1 43 /* WDG1 IRQ */ +#define IRQn_TSNS 44 /* TSNS IRQ */ +#define IRQn_MBX0A 45 /* MBX0A IRQ */ +#define IRQn_MBX0B 46 /* MBX0B IRQ */ +#define IRQn_MBX1A 47 /* MBX1A IRQ */ +#define IRQn_MBX1B 48 /* MBX1B IRQ */ +#define IRQn_GPTMR0 49 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 50 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 51 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 52 /* GPTMR3 IRQ */ +#define IRQn_I2C0 53 /* I2C0 IRQ */ +#define IRQn_I2C1 54 /* I2C1 IRQ */ +#define IRQn_I2C2 55 /* I2C2 IRQ */ +#define IRQn_I2C3 56 /* I2C3 IRQ */ +#define IRQn_PWM0 57 /* PWM0 IRQ */ +#define IRQn_HALL0 58 /* HALL0 IRQ */ +#define IRQn_QEI0 59 /* QEI0 IRQ */ +#define IRQn_PWM1 60 /* PWM1 IRQ */ +#define IRQn_HALL1 61 /* HALL1 IRQ */ +#define IRQn_QEI1 62 /* QEI1 IRQ */ +#define IRQn_PWM2 63 /* PWM2 IRQ */ +#define IRQn_HALL2 64 /* HALL2 IRQ */ +#define IRQn_QEI2 65 /* QEI2 IRQ */ +#define IRQn_PWM3 66 /* PWM3 IRQ */ +#define IRQn_HALL3 67 /* HALL3 IRQ */ +#define IRQn_QEI3 68 /* QEI3 IRQ */ +#define IRQn_SDP 69 /* SDP IRQ */ +#define IRQn_XPI0 70 /* XPI0 IRQ */ +#define IRQn_XDMA 71 /* XDMA IRQ */ +#define IRQn_HDMA 72 /* HDMA IRQ */ +#define IRQn_RNG 73 /* RNG IRQ */ +#define IRQn_USB0 74 /* USB0 IRQ */ +#define IRQn_PSEC 75 /* PSEC IRQ */ +#define IRQn_PGPIO 76 /* PGPIO IRQ */ +#define IRQn_PWDG 77 /* PWDG IRQ */ +#define IRQn_PTMR 78 /* PTMR IRQ */ +#define IRQn_PUART 79 /* PUART IRQ */ +#define IRQn_FUSE 80 /* FUSE IRQ */ +#define IRQn_SECMON 81 /* SECMON IRQ */ +#define IRQn_RTC 82 /* RTC IRQ */ +#define IRQn_BUTN 83 /* BUTN IRQ */ +#define IRQn_BGPIO 84 /* BGPIO IRQ */ +#define IRQn_BVIO 85 /* BVIO IRQ */ +#define IRQn_BROWNOUT 86 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 87 /* SYSCTL IRQ */ +#define IRQn_DEBUG_0 88 /* DEBUG[0] IRQ */ +#define IRQn_DEBUG_1 89 /* DEBUG[1] IRQ */ +#define IRQn_LIN0 90 /* LIN0 IRQ */ +#define IRQn_LIN1 91 /* LIN1 IRQ */ +#define IRQn_LIN2 92 /* LIN2 IRQ */ +#define IRQn_LIN3 93 /* LIN3 IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF0000000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* GPIO1 base address */ +#define HPM_GPIO1_BASE (0xF0004000UL) +/* GPIO1 base pointer */ +#define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF40DC000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) +/* BGPIO base address */ +#define HPM_BGPIO_BASE (0xF5014000UL) +/* BGPIO base pointer */ +#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +/* Address of XBUS_SOC instances */ +/* GPV_SOC base address */ +#define HPM_GPV_SOC_BASE (0x30100000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF0008000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF0010000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) +/* ADC1 base address */ +#define HPM_ADC1_BASE (0xF0014000UL) +/* ADC1 base pointer */ +#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) +/* ADC2 base address */ +#define HPM_ADC2_BASE (0xF0018000UL) +/* ADC2 base pointer */ +#define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE) + +#include "hpm_sdm_regs.h" +/* Address of SDM instances */ +/* SDM base address */ +#define HPM_SDM_BASE (0xF001C000UL) +/* SDM base pointer */ +#define HPM_SDM ((SDM_Type *) HPM_SDM_BASE) + +#include "hpm_acmp_regs.h" +/* Address of ACMP instances */ +/* ACMP base address */ +#define HPM_ACMP_BASE (0xF0020000UL) +/* ACMP base pointer */ +#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) + +#include "hpm_dac_regs.h" +/* Address of DAC instances */ +/* DAC0 base address */ +#define HPM_DAC0_BASE (0xF0024000UL) +/* DAC0 base pointer */ +#define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE) +/* DAC1 base address */ +#define HPM_DAC1_BASE (0xF0028000UL) +/* DAC1 base pointer */ +#define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0030000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0034000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0038000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF003C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* UART4 base address */ +#define HPM_UART4_BASE (0xF0050000UL) +/* UART4 base pointer */ +#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) +/* UART5 base address */ +#define HPM_UART5_BASE (0xF0054000UL) +/* UART5 base pointer */ +#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) +/* UART6 base address */ +#define HPM_UART6_BASE (0xF0058000UL) +/* UART6 base pointer */ +#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) +/* UART7 base address */ +#define HPM_UART7_BASE (0xF005C000UL) +/* UART7 base pointer */ +#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF40E4000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_mcan_regs.h" +/* Address of MCAN instances */ +/* MCAN0 base address */ +#define HPM_MCAN0_BASE (0xF0080000UL) +/* MCAN0 base pointer */ +#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) +/* MCAN1 base address */ +#define HPM_MCAN1_BASE (0xF0084000UL) +/* MCAN1 base pointer */ +#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) +/* MCAN2 base address */ +#define HPM_MCAN2_BASE (0xF0088000UL) +/* MCAN2 base pointer */ +#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) +/* MCAN3 base address */ +#define HPM_MCAN3_BASE (0xF008C000UL) +/* MCAN3 base pointer */ +#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) + +#include "hpm_wdg_regs.h" +/* Address of WDOG instances */ +/* WDG0 base address */ +#define HPM_WDG0_BASE (0xF0090000UL) +/* WDG0 base pointer */ +#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE) +/* WDG1 base address */ +#define HPM_WDG1_BASE (0xF0094000UL) +/* WDG1 base pointer */ +#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE) +/* PWDG base address */ +#define HPM_PWDG_BASE (0xF40E8000UL) +/* PWDG base pointer */ +#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) +/* MBX1A base address */ +#define HPM_MBX1A_BASE (0xF00A8000UL) +/* MBX1A base pointer */ +#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) +/* MBX1B base address */ +#define HPM_MBX1B_BASE (0xF00AC000UL) +/* MBX1B base pointer */ +#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) + +#include "hpm_ptpc_regs.h" +/* Address of PTPC instances */ +/* PTPC base address */ +#define HPM_PTPC_BASE (0xF00B0000UL) +/* PTPC base pointer */ +#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) + +#include "hpm_crc_regs.h" +/* Address of CRC instances */ +/* CRC base address */ +#define HPM_CRC_BASE (0xF00B8000UL) +/* CRC base pointer */ +#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C0000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dma_regs.h" +/* Address of DMA instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C4000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE) +/* XDMA base address */ +#define HPM_XDMA_BASE (0xF3048000UL) +/* XDMA base pointer */ +#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE) + +#include "hpm_rng_regs.h" +/* Address of RNG instances */ +/* RNG base address */ +#define HPM_RNG_BASE (0xF00C8000UL) +/* RNG base pointer */ +#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF00CC000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_pwm_regs.h" +/* Address of PWM instances */ +/* PWM0 base address */ +#define HPM_PWM0_BASE (0xF0200000UL) +/* PWM0 base pointer */ +#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) +/* PWM1 base address */ +#define HPM_PWM1_BASE (0xF0210000UL) +/* PWM1 base pointer */ +#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) +/* PWM2 base address */ +#define HPM_PWM2_BASE (0xF0220000UL) +/* PWM2 base pointer */ +#define HPM_PWM2 ((PWM_Type *) HPM_PWM2_BASE) +/* PWM3 base address */ +#define HPM_PWM3_BASE (0xF0230000UL) +/* PWM3 base pointer */ +#define HPM_PWM3 ((PWM_Type *) HPM_PWM3_BASE) + +#include "hpm_hall_regs.h" +/* Address of HALL instances */ +/* HALL0 base address */ +#define HPM_HALL0_BASE (0xF0204000UL) +/* HALL0 base pointer */ +#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE) +/* HALL1 base address */ +#define HPM_HALL1_BASE (0xF0214000UL) +/* HALL1 base pointer */ +#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE) +/* HALL2 base address */ +#define HPM_HALL2_BASE (0xF0224000UL) +/* HALL2 base pointer */ +#define HPM_HALL2 ((HALL_Type *) HPM_HALL2_BASE) +/* HALL3 base address */ +#define HPM_HALL3_BASE (0xF0234000UL) +/* HALL3 base pointer */ +#define HPM_HALL3 ((HALL_Type *) HPM_HALL3_BASE) + +#include "hpm_qei_regs.h" +/* Address of QEI instances */ +/* QEI0 base address */ +#define HPM_QEI0_BASE (0xF0208000UL) +/* QEI0 base pointer */ +#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE) +/* QEI1 base address */ +#define HPM_QEI1_BASE (0xF0218000UL) +/* QEI1 base pointer */ +#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE) +/* QEI2 base address */ +#define HPM_QEI2_BASE (0xF0228000UL) +/* QEI2 base pointer */ +#define HPM_QEI2 ((QEI_Type *) HPM_QEI2_BASE) +/* QEI3 base address */ +#define HPM_QEI3_BASE (0xF0238000UL) +/* QEI3 base pointer */ +#define HPM_QEI3 ((QEI_Type *) HPM_QEI3_BASE) + +#include "hpm_trgm_regs.h" +/* Address of TRGM instances */ +/* TRGM0 base address */ +#define HPM_TRGM0_BASE (0xF020C000UL) +/* TRGM0 base pointer */ +#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) +/* TRGM1 base address */ +#define HPM_TRGM1_BASE (0xF021C000UL) +/* TRGM1 base pointer */ +#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE) +/* TRGM2 base address */ +#define HPM_TRGM2_BASE (0xF022C000UL) +/* TRGM2 base pointer */ +#define HPM_TRGM2 ((TRGM_Type *) HPM_TRGM2_BASE) +/* TRGM3 base address */ +#define HPM_TRGM3_BASE (0xF023C000UL) +/* TRGM3 base pointer */ +#define HPM_TRGM3 ((TRGM_Type *) HPM_TRGM3_BASE) + +#include "hpm_pla_regs.h" +/* Address of PLA instances */ +/* PLA0 base address */ +#define HPM_PLA0_BASE (0xF020E000UL) +/* PLA0 base pointer */ +#define HPM_PLA0 ((PLA_Type *) HPM_PLA0_BASE) +/* PLA1 base address */ +#define HPM_PLA1_BASE (0xF021E000UL) +/* PLA1 base pointer */ +#define HPM_PLA1 ((PLA_Type *) HPM_PLA1_BASE) + +#include "hpm_synt_regs.h" +/* Address of SYNT instances */ +/* SYNT base address */ +#define HPM_SYNT_BASE (0xF0240000UL) +/* SYNT base pointer */ +#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) + +/* Address of PLA_X2 instances */ +/* PLA_X2 base address */ +#define HPM_PLA_X2_BASE (0xF024E000UL) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF2020000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF3000000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF3004000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* GPTMR2 base address */ +#define HPM_GPTMR2_BASE (0xF3008000UL) +/* GPTMR2 base pointer */ +#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) +/* GPTMR3 base address */ +#define HPM_GPTMR3_BASE (0xF300C000UL) +/* GPTMR3 base pointer */ +#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF40E0000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF3020000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF3024000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF3028000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF302C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_lin_regs.h" +/* Address of LIN instances */ +/* LIN0 base address */ +#define HPM_LIN0_BASE (0xF3030000UL) +/* LIN0 base pointer */ +#define HPM_LIN0 ((LIN_Type *) HPM_LIN0_BASE) +/* LIN1 base address */ +#define HPM_LIN1_BASE (0xF3034000UL) +/* LIN1 base pointer */ +#define HPM_LIN1 ((LIN_Type *) HPM_LIN1_BASE) +/* LIN2 base address */ +#define HPM_LIN2_BASE (0xF3038000UL) +/* LIN2 base pointer */ +#define HPM_LIN2 ((LIN_Type *) HPM_LIN2_BASE) +/* LIN3 base address */ +#define HPM_LIN3_BASE (0xF303C000UL) +/* LIN3 base pointer */ +#define HPM_LIN3 ((LIN_Type *) HPM_LIN3_BASE) + +#include "hpm_sdp_regs.h" +/* Address of SDP instances */ +/* SDP base address */ +#define HPM_SDP_BASE (0xF304C000UL) +/* SDP base pointer */ +#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) + +/* Address of ROMC instances */ +/* ROMC base address */ +#define HPM_ROMC_BASE (0xF3054000UL) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF40D8000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) +/* BIOC base address */ +#define HPM_BIOC_BASE (0xF5010000UL) +/* BIOC base pointer */ +#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTPSHW base address */ +#define HPM_OTPSHW_BASE (0xF4080000UL) +/* OTPSHW base pointer */ +#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE) +/* OTP base address */ +#define HPM_OTP_BASE (0xF40C8000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF40C0000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF40C4000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_psec_regs.h" +/* Address of PSEC instances */ +/* PSEC base address */ +#define HPM_PSEC_BASE (0xF40CC000UL) +/* PSEC base pointer */ +#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) + +#include "hpm_pmon_regs.h" +/* Address of PMON instances */ +/* PMON base address */ +#define HPM_PMON_BASE (0xF40D0000UL) +/* PMON base pointer */ +#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR base address */ +#define HPM_PGPR_BASE (0xF40D4000UL) +/* PGPR base pointer */ +#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE) + +#include "hpm_pllctlv2_regs.h" +/* Address of PLLCTLV2 instances */ +/* PLLCTLV2 base address */ +#define HPM_PLLCTLV2_BASE (0xF4100000UL) +/* PLLCTLV2 base pointer */ +#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) + +#include "hpm_tsns_regs.h" +/* Address of TSNS instances */ +/* TSNS base address */ +#define HPM_TSNS_BASE (0xF4104000UL) +/* TSNS base pointer */ +#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) + +/* Address of BACC instances */ +/* BACC base address */ +#define HPM_BACC_BASE (0xF5000000UL) + +#include "hpm_bpor_regs.h" +/* Address of BPOR instances */ +/* BPOR base address */ +#define HPM_BPOR_BASE (0xF5004000UL) +/* BPOR base pointer */ +#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) + +#include "hpm_bcfg_regs.h" +/* Address of BCFG instances */ +/* BCFG base address */ +#define HPM_BCFG_BASE (0xF5008000UL) +/* BCFG base pointer */ +#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) + +#include "hpm_butn_regs.h" +/* Address of BUTN instances */ +/* BUTN base address */ +#define HPM_BUTN_BASE (0xF500C000UL) +/* BUTN base pointer */ +#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) + +#include "hpm_bgpr_regs.h" +/* Address of BGPR instances */ +/* BGPR base address */ +#define HPM_BGPR_BASE (0xF5018000UL) +/* BGPR base pointer */ +#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) + +#include "hpm_bsec_regs.h" +/* Address of BSEC instances */ +/* BSEC base address */ +#define HPM_BSEC_BASE (0xF5040000UL) +/* BSEC base pointer */ +#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) + +#include "hpm_rtc_regs.h" +/* Address of RTC instances */ +/* RTC base address */ +#define HPM_RTC_BASE (0xF5044000UL) +/* RTC base pointer */ +#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) + +#include "hpm_bkey_regs.h" +/* Address of BKEY instances */ +/* BKEY base address */ +#define HPM_BKEY_BASE (0xF5048000UL) +/* BKEY base pointer */ +#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) + +#include "hpm_bmon_regs.h" +/* Address of BMON instances */ +/* BMON base address */ +#define HPM_BMON_BASE (0xF504C000UL) +/* BMON base pointer */ +#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) + +#include "hpm_tamp_regs.h" +/* Address of TAMP instances */ +/* TAMP base address */ +#define HPM_TAMP_BASE (0xF5050000UL) +/* TAMP base pointer */ +#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) + +#include "hpm_mono_regs.h" +/* Address of MONO instances */ +/* MONO base address */ +#define HPM_MONO_BASE (0xF5054000UL) +/* MONO base pointer */ +#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_trgmmux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#include "hpm_batt_iomux.h" +#endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h new file mode 100644 index 0000000000..4b3ce8b362 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" + +/* + * UART section + */ +#define UART_SOC_FIFO_SIZE (16U) +#define UART_SOC_HAS_RXLINE_IDLE_DETECTION (1U) + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (256U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (3U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (16U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_BUS_NUM (1U) +#define DMA_SOC_CHANNEL_NUM (8U) +#define DMA_SOC_MAX_COUNT (2U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) +#define DMA_SOC_HAS_IDLE_FLAG (1U) + +/* + * PDMA Section + */ +#define PDMA_SOC_PS_MAX_COUNT (0U) + +/* + * LCDC Section + */ +#define LCDC_SOC_MAX_LAYER_COUNT (0U) +#define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U) +#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) +#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) + +/* + * USB Section + */ +#define USB_SOC_MAX_COUNT (1U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_QTD_ALIGNMENT (32U) +#define USB_SOC_DCD_QHD_ALIGNMENT (64U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) +#define USB_SOC_HCD_QTD_ALIGNMENT (32U) +#define USB_SOC_HCD_QHD_ALIGNMENT (32U) +#define USB_SOC_HCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT (USB_SOC_HCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) +#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) + +/* + * ADC Section + */ +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (4096U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (15U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * CAN Section + */ +#define CAN_SOC_MAX_COUNT (2U) + +/* + * SDP Section + */ +#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) +#define SDP_HAS_SM3_SUPPORT (1U) +#define SDP_HAS_SM4_SUPPORT (1U) + +/* + * SOC Privilege mdoe + */ +#define SOC_HAS_S_MODE (1U) + +/* + * DAC Section + */ +#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) +#define DAC_SOC_MAX_DATA (4095U) +#define DAC_SOC_MAX_BUFF_COUNT (65536U) +#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) + + +/* + * SDXC Section + */ +#define SDXC_SOC_HAS_MISC_CTRL0 (1) +#define SDXC_SOC_HAS_MISC_CTRL1 (1) + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (512U) +#define SPI_SOC_FIFO_DEPTH (4U) + +/** + * PWM Section + * + */ +#define PWM_SOC_HRPWM_SUPPORT (1U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (1U) +#define PWM_SOC_TIMER_RESET_SUPPORT (1U) + +/** + * IOC Section + * + */ +#define IOC_SOC_PAD_MAX (487) + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c new file mode 100644 index 0000000000..ffc21973f7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 +#define SYSCTL_RESOURCE_GROUP1 1 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) + +static inline bool sysctl_valid_cpu_index(uint8_t cpu) +{ +#ifdef SYSCTL_CPU_CPU1 + return (cpu > SYSCTL_CPU_CPU1) ? false : true; +#else + return (cpu != SYSCTL_CPU_CPU0) ? false : true; +#endif +} + +hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) +{ + uint32_t i; + if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { + return status_invalid_argument; + } + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[cpu].GPR[i]; + } + return status_success; +} + +static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[cpu].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); +} + +hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); +} + +static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[cpu].GPR[start + i] = *(data + i); + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 1, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu1_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t slice, monitor_config_t *config) +{ + ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL & + ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | + SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | + (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | + SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | + SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | + SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | + SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | + SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = { 0 }; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].GPR[0] = entry; + ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); + return status_success; +} + +hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return sysctl_set_cpu_entry(ptr, 1, entry); +} + +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return sysctl_set_cpu_entry(ptr, 0, entry); +} + +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource, + bool enable) +{ + uint32_t index, offset; + if (linkable_resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + break; + case SYSCTL_RESOURCE_GROUP1: + ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, false); +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, clock_source_t source, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t axi_sub_div, + uint32_t ahb_sub_div) +{ + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + + uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; + if (origin_cpu_div == cpu_div) { + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | + SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + } + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | + SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); + + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + + return status_success; +} + +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) +{ + if (source >= clock_source_adc_clk_end) { + return status_invalid_argument; + } + uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); + if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { + return status_invalid_argument; + } + + ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); + + return status_success; +} + +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source) +{ + if (source >= clock_source_dac_clk_end) { + return status_invalid_argument; + } + uint32_t dac_index = (uint32_t) (node - clock_node_dac_start); + if (dac_index >= ARRAY_SIZE(ptr->DACCLK)) { + return status_invalid_argument; + } + + ptr->DACCLK[dac_index] = (ptr->DACCLK[dac_index] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(source); + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h new file mode 100644 index 0000000000..77b317159e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h @@ -0,0 +1,1521 @@ +/** + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + sysctl_retention_domain_cpu1 = 4, + sysctl_retention_domain_xtal24m = 6, + sysctl_retention_domain_pll0 = 7, + sysctl_retention_domain_pll1 = 8, + sysctl_retention_domain_pll2 = 9, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_cpu0, + sysctl_reset_domain_cpu1, +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0, + sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0, + sysctl_resource_cpu1 = SYSCTL_RESOURCE_CPU1, + sysctl_resource_cpx1 = SYSCTL_RESOURCE_CPX1, + sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0, + sysctl_resource_pow_cpu1 = SYSCTL_RESOURCE_POW_CPU1, + sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC, + sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0, + sysctl_resource_rst_cpu1 = SYSCTL_RESOURCE_RST_CPU1, + sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL, + sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0, + sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0, + sysctl_resource_clk1_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0, + sysctl_resource_clk2_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0, + sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1, + sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1, + sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1, + sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2, + sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2, + sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2, + sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF, + sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF, + sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF, + + sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0, + sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0, + sysctl_resource_clk_top_mchtmr1 = SYSCTL_RESOURCE_CLK_TOP_MCT1, + sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0, + sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0, + sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1, + sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2, + sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3, + sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0, + sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1, + sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2, + sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3, + sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4, + sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5, + sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6, + sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7, + sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0, + sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1, + sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2, + sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3, + sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0, + sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1, + sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2, + sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3, + sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0, + sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1, + sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2, + sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3, + sysctl_resource_clk_top_ptpc = SYSCTL_RESOURCE_CLK_TOP_PTPC, + sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0, + sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1, + sysctl_resource_clk_top_ana2 = SYSCTL_RESOURCE_CLK_TOP_ANA2, + sysctl_resource_clk_top_ana3 = SYSCTL_RESOURCE_CLK_TOP_ANA3, + sysctl_resource_clk_top_ana4 = SYSCTL_RESOURCE_CLK_TOP_ANA4, + sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0, + sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1, + sysctl_resource_clk_top_lin0 = SYSCTL_RESOURCE_CLK_TOP_LIN0, + sysctl_resource_clk_top_lin1 = SYSCTL_RESOURCE_CLK_TOP_LIN1, + sysctl_resource_clk_top_lin2 = SYSCTL_RESOURCE_CLK_TOP_LIN2, + sysctl_resource_clk_top_lin3 = SYSCTL_RESOURCE_CLK_TOP_LIN3, + sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0, + sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1, + sysctl_resource_clk_top_adc2 = SYSCTL_RESOURCE_CLK_TOP_ADC2, + sysctl_resource_clk_top_dac0 = SYSCTL_RESOURCE_CLK_TOP_DAC0, + sysctl_resource_clk_top_dac1 = SYSCTL_RESOURCE_CLK_TOP_DAC1, + + + sysctl_resource_linkable_start = 256, + sysctl_resource_ahbp = SYSCTL_RESOURCE_AHBP, + sysctl_resource_axis = SYSCTL_RESOURCE_AXIS, + sysctl_resource_axic = SYSCTL_RESOURCE_AXIC, + sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0, + sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0, + sysctl_resource_lmm1 = SYSCTL_RESOURCE_LMM1, + sysctl_resource_mchtmr1 = SYSCTL_RESOURCE_MCT1, + sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0, + sysctl_resource_ram0 = SYSCTL_RESOURCE_RAM0, + sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0, + sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1, + sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2, + sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3, + sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0, + sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1, + sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2, + sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3, + sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO, + sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0, + sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1, + sysctl_resource_adc2 = SYSCTL_RESOURCE_ADC2, + sysctl_resource_dac0 = SYSCTL_RESOURCE_DAC0, + sysctl_resource_dac1 = SYSCTL_RESOURCE_DAC1, + sysctl_resource_acmp = SYSCTL_RESOURCE_ACMP, + sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0, + sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1, + sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2, + sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3, + sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0, + sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0, + sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1, + sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2, + sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3, + sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4, + sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5, + sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6, + sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7, + sysctl_resource_lin0 = SYSCTL_RESOURCE_LIN0, + sysctl_resource_lin1 = SYSCTL_RESOURCE_LIN1, + sysctl_resource_lin2 = SYSCTL_RESOURCE_LIN2, + sysctl_resource_lin3 = SYSCTL_RESOURCE_LIN3, + sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC, + sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0, + sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1, + sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2, + sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3, + sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0, + sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1, + sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0, + sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1, + sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0, + sysctl_resource_mot0 = SYSCTL_RESOURCE_MOT0, + sysctl_resource_mot1 = SYSCTL_RESOURCE_MOT1, + sysctl_resource_mot2 = SYSCTL_RESOURCE_MOT2, + sysctl_resource_mot3 = SYSCTL_RESOURCE_MOT3, + sysctl_resource_msyn = SYSCTL_RESOURCE_MSYN, + sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0, + sysctl_resource_dma0 = SYSCTL_RESOURCE_HDMA, + sysctl_resource_dma1 = SYSCTL_RESOURCE_XDMA, + sysctl_resource_kman = SYSCTL_RESOURCE_KMAN, + sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0, + sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0, + sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS, + sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0, + sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0, + sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ + sysctl_resource_mode_force_on, /*!< Force the resource clock on */ + sysctl_resource_mode_force_off, /*!< Force the resource clock off */ +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, + clock_node_mchtmr1 = SYSCTL_CLOCK_CLK_TOP_MCT1, + clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, + clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, + clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, + clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, + clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, + clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, + clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, + clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, + clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, + clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, + clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, + clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, + clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, + clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, + clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, + clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, + clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, + clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, + clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, + clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, + clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, + clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, + clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, + clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, + clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, + clock_node_ptpc = SYSCTL_CLOCK_CLK_TOP_PTPC, + clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, + clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, + clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, + clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, + clock_node_ana4 = SYSCTL_CLOCK_CLK_TOP_ANA4, + clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, + clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, + clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0, + clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1, + clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2, + clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3, + + clock_node_adc_start, + clock_node_adc0 = clock_node_adc_start, + clock_node_adc1, + clock_node_adc2, + clock_node_adc3, + + clock_node_dac_start, + clock_node_dac0 = clock_node_dac_start, + clock_node_dac1, + clock_node_end, + + clock_node_core_start = 0xfc, + clock_node_cpu0 = clock_node_core_start, + clock_node_cpu1 = clock_node_cpu0, + clock_node_axi, + clock_node_ahb, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll0_clk1 = 2, + clock_source_pll0_clk2 = 3, + clock_source_pll1_clk0 = 4, + clock_source_pll1_clk1 = 5, + clock_source_pll2_clk0 = 6, + clock_source_pll2_clk1 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC clock sources + */ +typedef enum { + clock_source_adc_ana_clock = 0, + clock_source_adc_ahb_clock = 1, + clock_source_adc_clk_end, +} clock_source_adc_t; + +/** + * @brief DAC clock sources + */ +typedef enum { + clock_source_dac_ana_clock = 0, + clock_source_dac_ahb_clock = 1, + clock_source_dac_clk_end, +} clock_source_dac_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +/* Monitor Target types */ +typedef enum { + monitor_target_clk_32k = 0, + monitor_target_clk_irc24m = 1, + monitor_target_clk_xtal_24m = 2, + monitor_target_clk_usb0_phy = 3, + monitor_target_clk_usb1_phy = 4, + monitor_target_clk0_osc0 = 8, + monitor_target_clk0_pll0 = 9, + monitor_target_clk1_pll0 = 10, + monitor_target_clk2_pll0 = 11, + monitor_target_clk0_pll1 = 12, + monitor_target_clk1_pll1 = 13, + monitor_target_clk0_pll2 = 14, + monitor_target_clk1_pll2 = 15, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_mchtmr1 = 130, + monitor_target_clk_top_xpi0 = 131, + monitor_target_clk_top_gptmr0 = 132, + monitor_target_clk_top_gptmr1 = 133, + monitor_target_clk_top_gptmr2 = 134, + monitor_target_clk_top_gptmr3 = 135, + monitor_target_clk_top_uart0 = 136, + monitor_target_clk_top_uart1 = 137, + monitor_target_clk_top_uart2 = 138, + monitor_target_clk_top_uart3 = 139, + monitor_target_clk_top_uart4 = 140, + monitor_target_clk_top_uart5 = 141, + monitor_target_clk_top_uart6 = 142, + monitor_target_clk_top_uart7 = 143, + monitor_target_clk_top_i2c0 = 144, + monitor_target_clk_top_i2c1 = 145, + monitor_target_clk_top_i2c2 = 146, + monitor_target_clk_top_i2c3 = 147, + monitor_target_clk_top_spi0 = 148, + monitor_target_clk_top_spi1 = 149, + monitor_target_clk_top_spi2 = 150, + monitor_target_clk_top_spi3 = 151, + monitor_target_clk_top_can0 = 152, + monitor_target_clk_top_can1 = 153, + monitor_target_clk_top_can2 = 154, + monitor_target_clk_top_can3 = 155, + monitor_target_clk_top_ptpc = 156, + monitor_target_clk_top_ana0 = 157, + monitor_target_clk_top_ana1 = 158, + monitor_target_clk_top_ana2 = 159, + monitor_target_clk_top_ana3 = 160, + monitor_target_clk_top_ana4 = 161, + monitor_target_clk_top_ref0 = 162, + monitor_target_clk_top_ref1 = 163, + monitor_target_clk_top_lin0 = 164, + monitor_target_clk_top_lin1 = 165, + monitor_target_clk_top_lin2 = 166, + monitor_target_clk_top_lin3 = 167, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, +} monitor_reference_t; + +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | + (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit_high, + uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Disable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Disable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 1, value); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, + uint8_t cpu_index, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + uint8_t set_mask = 0x1; + if (domain < sysctl_retention_domain_xtal24m) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Retain target domain for specific CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem); +} + +/** + * @brief Check if cpu clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; +} + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Get target CPU0 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 0, status_index); +} + +/** + * @brief Get target CPU1 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 1, status_index); +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index, + uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Check CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); +} + +/** + * @brief Check CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask); +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); +} + + +/** + * @brief Disable CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask); +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Disable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); +} + + +/** + * @brief Disable CPU1 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num); +} + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); +} + +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Enable CPU1 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num); +} + +/** + * @brief Lock CPU gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); +} + +/** + * @brief Lock CPU1 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask); +} + +/** + * @brief Lock CPU lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + sysctl_cpu_lock(ptr, 0); +} + +/** + * @brief Lock CPU1 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr) +{ + sysctl_cpu_lock(ptr, 1); +} + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) +{ + ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); +} + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 0, mode); +} + +/** + * @brief Set CPU1 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 1, mode); +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= + ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Clear CPU1 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 1, flags); +} + +/** + * @brief Get CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ptr->CPU[cpu_index].LP & + (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); +} + +/** + * @brief Get CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 0); +} + +/** + * @brief Get CPU1 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 1); +} + +/** + * @brief Release cpu + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK; +} + +/** + * @brief Release cpu1 + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) +{ + sysctl_release_cpu(ptr, 1); +} + +/** + * @brief Check whether CPU is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval true CPU is released + * @retval false CPU is on-hold + */ +static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); +} + +/** + * @brief Check whether CPU1 is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @retval true CPU1 is released + * @retval false CPU1 is on-hold + */ +static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) +{ + return sysctl_is_cpu_released(ptr, 1); +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); + +/** + * @brief Configure CPU domain clock + * @param ptr SYSCTL base address + * @param source clock source to be used + * @param cpu_div CPU divider + * @param axi_sub_div AXI BUS divider based on divided CPU clock + * @param ahb_sub_div AHB BUS divider based on divided CPU clock + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t axi_sub_div, + uint32_t ahb_sub_div); + +/** + * @brief Set ADC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); + + +/** + * @brief Set DAC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source); + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource, + bool enable); +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Add resource to CPU1 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be added to CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU1 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); + +/** + * @brief Save data to GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved from GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set data to CPU1 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved in CPU1 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU boot or wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu CPU index + * @param[in] entry Entry address for CPU + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + +/** + * @brief Set entry point on either CPU1 boot or wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h new file mode 100644 index 0000000000..35ed3a3f6e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h @@ -0,0 +1,1403 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[322]; /* 0x0 - 0x504: Resource control register for cpu0_core */ + __R uint8_t RESERVED0[760]; /* 0x508 - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Group setting */ + __RW uint32_t SET; /* 0x804: Group setting */ + __RW uint32_t CLEAR; /* 0x808: Group setting */ + __RW uint32_t TOGGLE; /* 0x80C: Group setting */ + } GROUP0[3]; + __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x840: Group setting */ + __RW uint32_t SET; /* 0x844: Group setting */ + __RW uint32_t CLEAR; /* 0x848: Group setting */ + __RW uint32_t TOGGLE; /* 0x84C: Group setting */ + } GROUP1[3]; + __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[2]; + struct { + __RW uint32_t VALUE; /* 0x920: Retention Contol */ + __RW uint32_t SET; /* 0x924: Retention Contol */ + __RW uint32_t CLEAR; /* 0x928: Retention Contol */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + } RETENTION[2]; + __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + } POWER[2]; + __R uint8_t RESERVED4[992]; /* 0x1020 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[3]; + __R uint8_t RESERVED5[976]; /* 0x1430 - 0x17FF: Reserved */ + __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ + __RW uint32_t CLOCK[39]; /* 0x1804 - 0x189C: Clock setting */ + __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[3]; /* 0x1C00 - 0x1C08: Clock setting */ + __RW uint32_t DACCLK[2]; /* 0x1C0C - 0x1C10: Clock setting */ + __R uint8_t RESERVED7[1004]; /* 0x1C14 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: CPU0 LP control */ + __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ + __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ + __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ + __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ + } CPU[2]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK) +#define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK) +#define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK) +#define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * bit0: cpu0 depends on group0 + * bit1: cpu0 depends on group1 + * bit2: cpu0 depends on group2 + * bit3: cpu0 depends on group3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0，each bit represents a group + * 0: no effect + * 1: the group is assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: the group is not assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: toggle the result that whether the group is assigned to CPU0 before + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * bit00: soc_mem is kept on while cpu0 stop + * bit01: soc_ctx is kept on while cpu0 stop + * bit02: cpu0_mem is kept on while cpu0 stop + * bit03: cpu0_ctx is kept on while cpu0 stop + * bit04: cpu1_mem is kept on while cpu0 stop + * bit05: cpu1_ctx is kept on while cpu0 stop + * bit06: xtal_hold is kept on while cpu0 stop + * bit07: pll0_hold is kept on while cpu0 stop + * bit08: pll1_hold is kept on while cpu0 stop + * bit09: pll2_hold is kept on while cpu0 stop + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: keep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: no keep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: toggle the result that whether the resource is kept on while CPU0 stop before + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automaticly + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK_CPU */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) +#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) + +/* + * SUB1_DIV (RW) + * + * ahb bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xF00000UL) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20U) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) + +/* + * SUB0_DIV (RW) + * + * axi bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll2_clk0 + * 7:pll2_clk1 + */ +#define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) +#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) +#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) +#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll2_clk0 + * 7:pll2_clk1 + */ +#define SYSCTL_CLOCK_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) +#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ana clock + * 1: ahb clock + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x100U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: DACCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) +#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ana clock + * 1: ahb clock + */ +#define SYSCTL_DACCLK_MUX_MASK (0x100U) +#define SYSCTL_DACCLK_MUX_SHIFT (8U) +#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) +#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * MUX (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + */ +#define SYSCTL_GLOBAL00_MUX_MASK (0xFU) +#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) +#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) +#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * refrence clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + * 0: clk_32k + * 1: clk_irc24m + * 2: clk_xtal_24m + * 3: clk_usb0_phy + * 8: clk0_osc0 + * 9: clk0_pll0 + * 10: clk1_pll0 + * 11: clk2_pll0 + * 12: clk0_pll1 + * 13: clk1_pll1 + * 14: clk0_pll2 + * 15: clk1_pll2 + * 128: clk_top_cpu0 + * 129: clk_top_mct0 + * 130: clk_top_mct1 + * 131: clk_top_xpi0 + * 132: clk_top_tmr0 + * 133: clk_top_tmr1 + * 134: clk_top_tmr2 + * 135: clk_top_tmr3 + * 136: clk_top_urt0 + * 137: clk_top_urt1 + * 138: clk_top_urt2 + * 139: clk_top_urt3 + * 140: clk_top_urt4 + * 141: clk_top_urt5 + * 142: clk_top_urt6 + * 143: clk_top_urt7 + * 144: clk_top_i2c0 + * 145: clk_top_i2c1 + * 146: clk_top_i2c2 + * 147: clk_top_i2c3 + * 148: clk_top_spi0 + * 149: clk_top_spi1 + * 150: clk_top_spi2 + * 151: clk_top_spi3 + * 152: clk_top_can0 + * 153: clk_top_can1 + * 154: clk_top_can2 + * 155: clk_top_can3 + * 156: clk_top_ptpc + * 157: clk_top_ana0 + * 158: clk_top_ana1 + * 159: clk_top_ana2 + * 160: clk_top_ana3 + * 161: clk_top_ana4 + * 162: clk_top_ref0 + * 163: clk_top_ref1 + * 164: clk_top_lin0 + * 165: clk_top_lin1 + * 166: clk_top_lin2 + * 167: clk_top_lin3 + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wake up happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 reset not happened + * 1: CPU0 reset happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0 (0UL) +#define SYSCTL_RESOURCE_CPX0 (1UL) +#define SYSCTL_RESOURCE_CPU1 (8UL) +#define SYSCTL_RESOURCE_CPX1 (9UL) +#define SYSCTL_RESOURCE_POW_CPU0 (21UL) +#define SYSCTL_RESOURCE_POW_CPU1 (22UL) +#define SYSCTL_RESOURCE_RST_SOC (23UL) +#define SYSCTL_RESOURCE_RST_CPU0 (24UL) +#define SYSCTL_RESOURCE_RST_CPU1 (25UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT1 (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (70UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (71UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT0 (72UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT1 (73UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT2 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT3 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT4 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT5 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT6 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT7 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTPC (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA4 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN0 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN1 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN2 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN3 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC1 (132UL) +#define SYSCTL_RESOURCE_AHBP (256UL) +#define SYSCTL_RESOURCE_AXIS (257UL) +#define SYSCTL_RESOURCE_AXIC (258UL) +#define SYSCTL_RESOURCE_LMM0 (259UL) +#define SYSCTL_RESOURCE_MCT0 (260UL) +#define SYSCTL_RESOURCE_LMM1 (261UL) +#define SYSCTL_RESOURCE_MCT1 (262UL) +#define SYSCTL_RESOURCE_ROM0 (263UL) +#define SYSCTL_RESOURCE_RAM0 (264UL) +#define SYSCTL_RESOURCE_I2C0 (265UL) +#define SYSCTL_RESOURCE_I2C1 (266UL) +#define SYSCTL_RESOURCE_I2C2 (267UL) +#define SYSCTL_RESOURCE_I2C3 (268UL) +#define SYSCTL_RESOURCE_TMR0 (269UL) +#define SYSCTL_RESOURCE_TMR1 (270UL) +#define SYSCTL_RESOURCE_TMR2 (271UL) +#define SYSCTL_RESOURCE_TMR3 (272UL) +#define SYSCTL_RESOURCE_GPIO (273UL) +#define SYSCTL_RESOURCE_ADC0 (274UL) +#define SYSCTL_RESOURCE_ADC1 (275UL) +#define SYSCTL_RESOURCE_ADC2 (276UL) +#define SYSCTL_RESOURCE_DAC0 (277UL) +#define SYSCTL_RESOURCE_DAC1 (278UL) +#define SYSCTL_RESOURCE_ACMP (279UL) +#define SYSCTL_RESOURCE_SPI0 (280UL) +#define SYSCTL_RESOURCE_SPI1 (281UL) +#define SYSCTL_RESOURCE_SPI2 (282UL) +#define SYSCTL_RESOURCE_SPI3 (283UL) +#define SYSCTL_RESOURCE_SDM0 (284UL) +#define SYSCTL_RESOURCE_URT0 (285UL) +#define SYSCTL_RESOURCE_URT1 (286UL) +#define SYSCTL_RESOURCE_URT2 (287UL) +#define SYSCTL_RESOURCE_URT3 (288UL) +#define SYSCTL_RESOURCE_URT4 (289UL) +#define SYSCTL_RESOURCE_URT5 (290UL) +#define SYSCTL_RESOURCE_URT6 (291UL) +#define SYSCTL_RESOURCE_URT7 (292UL) +#define SYSCTL_RESOURCE_LIN0 (293UL) +#define SYSCTL_RESOURCE_LIN1 (294UL) +#define SYSCTL_RESOURCE_LIN2 (295UL) +#define SYSCTL_RESOURCE_LIN3 (296UL) +#define SYSCTL_RESOURCE_PTPC (297UL) +#define SYSCTL_RESOURCE_CAN0 (298UL) +#define SYSCTL_RESOURCE_CAN1 (299UL) +#define SYSCTL_RESOURCE_CAN2 (300UL) +#define SYSCTL_RESOURCE_CAN3 (301UL) +#define SYSCTL_RESOURCE_WDG0 (302UL) +#define SYSCTL_RESOURCE_WDG1 (303UL) +#define SYSCTL_RESOURCE_MBX0 (304UL) +#define SYSCTL_RESOURCE_MBX1 (305UL) +#define SYSCTL_RESOURCE_CRC0 (306UL) +#define SYSCTL_RESOURCE_MOT0 (307UL) +#define SYSCTL_RESOURCE_MOT1 (308UL) +#define SYSCTL_RESOURCE_MOT2 (309UL) +#define SYSCTL_RESOURCE_MOT3 (310UL) +#define SYSCTL_RESOURCE_MSYN (311UL) +#define SYSCTL_RESOURCE_XPI0 (312UL) +#define SYSCTL_RESOURCE_HDMA (313UL) +#define SYSCTL_RESOURCE_XDMA (314UL) +#define SYSCTL_RESOURCE_KMAN (315UL) +#define SYSCTL_RESOURCE_SDP0 (316UL) +#define SYSCTL_RESOURCE_RNG0 (317UL) +#define SYSCTL_RESOURCE_TSNS (318UL) +#define SYSCTL_RESOURCE_USB0 (319UL) +#define SYSCTL_RESOURCE_REF0 (320UL) +#define SYSCTL_RESOURCE_REF1 (321UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_LINK0 (0UL) +#define SYSCTL_GROUP0_LINK1 (1UL) +#define SYSCTL_GROUP0_LINK2 (2UL) + +/* GROUP1 register group index macro definition */ +#define SYSCTL_GROUP1_LINK0 (0UL) +#define SYSCTL_GROUP1_LINK1 (1UL) +#define SYSCTL_GROUP1_LINK2 (2UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) +#define SYSCTL_AFFILIATE_CPU1 (1UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) +#define SYSCTL_RETENTION_CPU1 (1UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_CPU0 (0UL) +#define SYSCTL_POWER_CPU1 (1UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CPU0 (1UL) +#define SYSCTL_RESET_CPU1 (2UL) + +/* CLOCK_CPU register group index macro definition */ +#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_MCT1 (1UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR0 (3UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR1 (4UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR2 (5UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR3 (6UL) +#define SYSCTL_CLOCK_CLK_TOP_URT0 (7UL) +#define SYSCTL_CLOCK_CLK_TOP_URT1 (8UL) +#define SYSCTL_CLOCK_CLK_TOP_URT2 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_URT3 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_URT4 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_URT5 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_URT6 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_URT7 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN2 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN3 (26UL) +#define SYSCTL_CLOCK_CLK_TOP_PTPC (27UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA2 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA3 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA4 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN0 (35UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN1 (36UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN2 (37UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN3 (38UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) + +/* DACCLK register group index macro definition */ +#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) +#define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) +#define SYSCTL_CPU_CPU1 (1UL) + + +#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h new file mode 100644 index 0000000000..3d21001266 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGM_H +#define HPM_TRGM_H + +typedef struct { + __RW uint32_t FILTCFG[20]; /* 0x0 - 0x4C: Filter configure register */ + __R uint8_t RESERVED0[176]; /* 0x50 - 0xFF: Reserved */ + __RW uint32_t TRGOCFG[68]; /* 0x100 - 0x20C: Trigger manager output configure register */ + __R uint8_t RESERVED1[240]; /* 0x210 - 0x2FF: Reserved */ + __RW uint32_t DMACFG[4]; /* 0x300 - 0x30C: DMA request configure register */ + __R uint8_t RESERVED2[240]; /* 0x310 - 0x3FF: Reserved */ + __RW uint32_t GCR; /* 0x400: General Control Register */ +} TRGM_Type; + + +/* Bitfield definition for register array: FILTCFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) +#define TRGM_FILTCFG_OUTINV_SHIFT (16U) +#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) +#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stalbe low mode; + * 111-stable high mode + */ +#define TRGM_FILTCFG_MODE_MASK (0xE000U) +#define TRGM_FILTCFG_MODE_SHIFT (13U) +#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) +#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) +#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) +#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) +#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) + +/* + * FILTLEN (RW) + * + * This bitfields defines the filter counter length. + */ +#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) +#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) +#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) +#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) + +/* Bitfield definition for register array: TRGOCFG */ +/* + * OUTINV (RW) + * + * 1- Invert the output + */ +#define TRGM_TRGOCFG_OUTINV_MASK (0x200U) +#define TRGM_TRGOCFG_OUTINV_SHIFT (9U) +#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) +#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) + +/* + * FEDG2PEN (RW) + * + * 1- The selected input signal falling edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x100U) +#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (8U) +#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) +#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) + +/* + * REDG2PEN (RW) + * + * 1- The selected input signal rising edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_REDG2PEN_MASK (0x80U) +#define TRGM_TRGOCFG_REDG2PEN_SHIFT (7U) +#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) +#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) + +/* + * TRIGOSEL (RW) + * + * This bitfield selects one of the TRGM inputs as output. + */ +#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x7FU) +#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) +#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) +#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) + +/* Bitfield definition for register array: DMACFG */ +/* + * DMASRCSEL (RW) + * + * This field selects one of the DMA requests as the DMA request output. + */ +#define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU) +#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) +#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) +#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * TRGOPEN (RW) + * + * The bitfield enable the TRGM outputs. + */ +#define TRGM_GCR_TRGOPEN_MASK (0xFFFU) +#define TRGM_GCR_TRGOPEN_SHIFT (0U) +#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) +#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) + + + +/* FILTCFG register group index macro definition */ +#define TRGM_FILTCFG_PWM_IN0 (0UL) +#define TRGM_FILTCFG_PWM_IN1 (1UL) +#define TRGM_FILTCFG_PWM_IN2 (2UL) +#define TRGM_FILTCFG_PWM_IN3 (3UL) +#define TRGM_FILTCFG_PWM_IN4 (4UL) +#define TRGM_FILTCFG_PWM_IN5 (5UL) +#define TRGM_FILTCFG_PWM_IN6 (6UL) +#define TRGM_FILTCFG_PWM_IN7 (7UL) +#define TRGM_FILTCFG_TRGM_IN0 (8UL) +#define TRGM_FILTCFG_TRGM_IN1 (9UL) +#define TRGM_FILTCFG_TRGM_IN2 (10UL) +#define TRGM_FILTCFG_TRGM_IN3 (11UL) +#define TRGM_FILTCFG_TRGM_IN4 (12UL) +#define TRGM_FILTCFG_TRGM_IN5 (13UL) +#define TRGM_FILTCFG_TRGM_IN6 (14UL) +#define TRGM_FILTCFG_TRGM_IN7 (15UL) +#define TRGM_FILTCFG_TRGM_IN8 (16UL) +#define TRGM_FILTCFG_TRGM_IN9 (17UL) +#define TRGM_FILTCFG_TRGM_IN10 (18UL) +#define TRGM_FILTCFG_TRGM_IN11 (19UL) + +/* TRGOCFG register group index macro definition */ +#define TRGM_TRGOCFG_TRGM_OUT0 (0UL) +#define TRGM_TRGOCFG_TRGM_OUT1 (1UL) +#define TRGM_TRGOCFG_TRGM_OUT2 (2UL) +#define TRGM_TRGOCFG_TRGM_OUT3 (3UL) +#define TRGM_TRGOCFG_TRGM_OUT4 (4UL) +#define TRGM_TRGOCFG_TRGM_OUT5 (5UL) +#define TRGM_TRGOCFG_TRGM_OUT6 (6UL) +#define TRGM_TRGOCFG_TRGM_OUT7 (7UL) +#define TRGM_TRGOCFG_TRGM_OUT8 (8UL) +#define TRGM_TRGOCFG_TRGM_OUT9 (9UL) +#define TRGM_TRGOCFG_TRGM_OUT10 (10UL) +#define TRGM_TRGOCFG_TRGM_OUT11 (11UL) +#define TRGM_TRGOCFG_TRGM_OUTX0 (12UL) +#define TRGM_TRGOCFG_TRGM_OUTX1 (13UL) +#define TRGM_TRGOCFG_PWM_SYNCI (14UL) +#define TRGM_TRGOCFG_PWM_FRCI (15UL) +#define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL) +#define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL) +#define TRGM_TRGOCFG_PWM_FAULTI0 (18UL) +#define TRGM_TRGOCFG_PWM_FAULTI1 (19UL) +#define TRGM_TRGOCFG_PWM_FAULTI2 (20UL) +#define TRGM_TRGOCFG_PWM_FAULTI3 (21UL) +#define TRGM_TRGOCFG_PWM_IN8 (22UL) +#define TRGM_TRGOCFG_PWM_IN9 (23UL) +#define TRGM_TRGOCFG_PWM_IN10 (24UL) +#define TRGM_TRGOCFG_PWM_IN11 (25UL) +#define TRGM_TRGOCFG_PWM_IN12 (26UL) +#define TRGM_TRGOCFG_PWM_IN13 (27UL) +#define TRGM_TRGOCFG_PWM_IN14 (28UL) +#define TRGM_TRGOCFG_PWM_IN15 (29UL) +#define TRGM_TRGOCFG_PLA_IN0 (30UL) +#define TRGM_TRGOCFG_PLA_IN1 (31UL) +#define TRGM_TRGOCFG_PLA_IN2 (32UL) +#define TRGM_TRGOCFG_PLA_IN3 (33UL) +#define TRGM_TRGOCFG_PLA_IN4 (34UL) +#define TRGM_TRGOCFG_PLA_IN5 (35UL) +#define TRGM_TRGOCFG_PLA_IN6 (36UL) +#define TRGM_TRGOCFG_PLA_IN7 (37UL) +#define TRGM_TRGOCFG_QEI_A (38UL) +#define TRGM_TRGOCFG_QEI_B (39UL) +#define TRGM_TRGOCFG_QEI_Z (40UL) +#define TRGM_TRGOCFG_QEI_H (41UL) +#define TRGM_TRGOCFG_QEI_PAUSE (42UL) +#define TRGM_TRGOCFG_QEI_SNAPI (43UL) +#define TRGM_TRGOCFG_HALL_U (44UL) +#define TRGM_TRGOCFG_HALL_V (45UL) +#define TRGM_TRGOCFG_HALL_W (46UL) +#define TRGM_TRGOCFG_HALL_SNAPI (47UL) +#define TRGM_TRGOCFG_ADC0_STRGI (48UL) +#define TRGM_TRGOCFG_ADC1_STRGI (49UL) +#define TRGM_TRGOCFG_ADC2_STRGI (50UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) +#define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL) +#define TRGM_TRGOCFG_GPTMRA_IN2 (56UL) +#define TRGM_TRGOCFG_GPTMRA_IN3 (57UL) +#define TRGM_TRGOCFG_DAC_BUF_TRIG (58UL) +#define TRGM_TRGOCFG_DAC0_STEP_TRIG (59UL) +#define TRGM_TRGOCFG_DAC1_STEP_TRIG (60UL) +#define TRGM_TRGOCFG_CMPX_WIN (61UL) +#define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL) +#define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL) +#define TRGM_TRGOCFG_SDFM_EVT0 (64UL) +#define TRGM_TRGOCFG_SDFM_EVT1 (65UL) +#define TRGM_TRGOCFG_SDFM_EVT2 (66UL) +#define TRGM_TRGOCFG_SDFM_EVT3 (67UL) + +/* DMACFG register group index macro definition */ +#define TRGM_DMACFG_0 (0UL) +#define TRGM_DMACFG_1 (1UL) +#define TRGM_DMACFG_2 (2UL) +#define TRGM_DMACFG_3 (3UL) + + +#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h new file mode 100644 index 0000000000..4c0194a674 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h @@ -0,0 +1,734 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGMMUX_SRC_H +#define HPM_TRGMMUX_SRC_H + +/* trgm0_input mux definitions */ +#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) +#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) +#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x1CUL) +#define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x1DUL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM0_INPUT_SRC_SYNT_CH0 (0x20UL) +#define HPM_TRGM0_INPUT_SRC_SYNT_CH1 (0x21UL) +#define HPM_TRGM0_INPUT_SRC_SYNT_CH2 (0x22UL) +#define HPM_TRGM0_INPUT_SRC_SYNT_CH3 (0x23UL) +#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x26UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x27UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT0 (0x38UL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT1 (0x39UL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT2 (0x3AUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT3 (0x3BUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT4 (0x3CUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT5 (0x3DUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT6 (0x3EUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT7 (0x3FUL) + +/* trgm1_input mux definitions */ +#define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) +#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) +#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) +#define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x1CUL) +#define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x1DUL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x20UL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x21UL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x22UL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x23UL) +#define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2 (0x26UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT3 (0x27UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT0 (0x38UL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT1 (0x39UL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT2 (0x3AUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT3 (0x3BUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT4 (0x3CUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT5 (0x3DUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT6 (0x3EUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT7 (0x3FUL) + +/* trgm2_input mux definitions */ +#define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) +#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) +#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) +#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) +#define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x1CUL) +#define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x1DUL) +#define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x20UL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x21UL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x22UL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x23UL) +#define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT2 (0x26UL) +#define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT3 (0x27UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM2_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM2_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM2_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM2_INPUT_SRC_CMP3_OUT (0x37UL) + +/* trgm3_input mux definitions */ +#define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) +#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) +#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) +#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) +#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) +#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) +#define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x1CUL) +#define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x1DUL) +#define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x20UL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x21UL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x22UL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x23UL) +#define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 (0x26UL) +#define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT3 (0x27UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM3_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM3_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM3_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM3_INPUT_SRC_CMP3_OUT (0x37UL) + +/* trgm0_output mux definitions */ +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN0 (0x1EUL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN1 (0x1FUL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN2 (0x20UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN3 (0x21UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN4 (0x22UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN5 (0x23UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN6 (0x24UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN7 (0x25UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) +#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) +#define HPM_TRGM0_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG0 (0x40UL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG1 (0x41UL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG2 (0x42UL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG3 (0x43UL) + +/* trgm1_output mux definitions */ +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN0 (0x1EUL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN1 (0x1FUL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN2 (0x20UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN3 (0x21UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN4 (0x22UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN5 (0x23UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN6 (0x24UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN7 (0x25UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) +#define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_SYNCI (0x37UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN2 (0x38UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN3 (0x39UL) +#define HPM_TRGM1_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) +#define HPM_TRGM1_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM1_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG4 (0x40UL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG5 (0x41UL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG6 (0x42UL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG7 (0x43UL) + +/* trgm2_output mux definitions */ +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) +#define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) +#define HPM_TRGM2_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) +#define HPM_TRGM2_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM2_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) +#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG8 (0x40UL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG9 (0x41UL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG10 (0x42UL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG11 (0x43UL) + +/* trgm3_output mux definitions */ +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) +#define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_SYNCI (0x37UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN2 (0x38UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN3 (0x39UL) +#define HPM_TRGM3_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) +#define HPM_TRGM3_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM3_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) +#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG12 (0x40UL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG13 (0x41UL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG14 (0x42UL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 (0x43UL) + +/* trgm0_filter mux definitions */ +#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) + +/* trgm1_filter mux definitions */ +#define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) + +/* trgm2_filter mux definitions */ +#define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) + +/* trgm3_filter mux definitions */ +#define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) + +/* trgm0_dma mux definitions */ +#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) +#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) +#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) +#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) +#define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) +#define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) + +/* trgm1_dma mux definitions */ +#define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) +#define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) +#define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) +#define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) +#define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) +#define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) + +/* trgm2_dma mux definitions */ +#define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) +#define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) +#define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) +#define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) +#define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) +#define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) + +/* trgm3_dma mux definitions */ +#define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) +#define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) +#define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) +#define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) +#define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) +#define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) + + + +#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list new file mode 100644 index 0000000000..9298048682 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/soc_modules.list @@ -0,0 +1,40 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause +# +# In this file, all modules available on this part are listed + +CONFIG_HAS_HPMSDK_UART=y +CONFIG_HAS_HPMSDK_FEMC=n +CONFIG_HAS_HPMSDK_SDP=y +CONFIG_HAS_HPMSDK_I2C=y +CONFIG_HAS_HPMSDK_PMP=y +CONFIG_HAS_HPMSDK_RNG=y +CONFIG_HAS_HPMSDK_GPIO=y +CONFIG_HAS_HPMSDK_SPI=y +CONFIG_HAS_HPMSDK_WDG=y +CONFIG_HAS_HPMSDK_DMA=y +CONFIG_HAS_HPMSDK_GPTMR=y +CONFIG_HAS_HPMSDK_PWM=y +CONFIG_HAS_HPMSDK_PLLCTLV2=y +CONFIG_HAS_HPMSDK_USB=y +CONFIG_HAS_HPMSDK_RTC=y +CONFIG_HAS_HPMSDK_ACMP=y +CONFIG_HAS_HPMSDK_I2S=n +CONFIG_HAS_HPMSDK_DAO=n +CONFIG_HAS_HPMSDK_PDM=n +CONFIG_HAS_HPMSDK_VAD=n +CONFIG_HAS_HPMSDK_MCAN=y +CONFIG_HAS_HPMSDK_ENET=n +CONFIG_HAS_HPMSDK_SDXC=n +CONFIG_HAS_HPMSDK_ADC16=y +CONFIG_HAS_HPMSDK_PCFG=y +CONFIG_HAS_HPMSDK_PMU=y +CONFIG_HAS_HPMSDK_PTPC=y +CONFIG_HAS_HPMSDK_MCHTMR=y +CONFIG_HAS_HPMSDK_FFA=n +CONFIG_HAS_HPMSDK_TSNS=y +CONFIG_HAS_HPMSDK_DAC=y +CONFIG_HAS_HPMSDK_CRC=y +CONFIG_HAS_HPMSDK_PLA=y +CONFIG_HAS_HPMSDK_SDM=y +CONFIG_HAS_HPMSDK_LIN=y diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c new file mode 100644 index 0000000000..3f742ad69a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/system.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif + +#ifdef USE_S_MODE_IRQ + disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + disable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + + disable_irq_from_intc(); +#ifdef USE_S_MODE_IRQ + disable_s_irq_from_intc(); +#endif + + enable_plic_feature(); + enable_irq_from_intc(); + +#ifdef USE_S_MODE_IRQ + delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); + enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif +#else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif +#endif + +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + l1c_dc_invalidate_all(); +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld new file mode 100644 index 0000000000..7dee6bf34f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .vectors ORIGIN(ILM) : AT(etext) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld new file mode 100644 index 0000000000..393656ec2f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld new file mode 100644 index 0000000000..cdc8b12f88 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/initfini.c new file mode 100644 index 0000000000..7d2b85799c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld new file mode 100644 index 0000000000..3fa899eae5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld new file mode 100644 index 0000000000..4417aac7b4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00020000, LENGTH = 128K + DLM (w) : ORIGIN = 0x000A0000, LENGTH = 96K + NONCACHEABLE_RAM (w) : ORIGIN = 0x000B8000, LENGTH = 32K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S new file mode 100644 index 0000000000..a321897e75 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidentally */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c new file mode 100644 index 0000000000..626e5dec16 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + + +extern void system_init(void); + + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debugging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable register */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while (1) { + ; + } +} + +__attribute__((weak)) void reset_handler(void) +{ + l1c_dc_disable(); + l1c_dc_invalidate_all(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Entry function */ + main(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +{ +} + +#if !defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes) +void *__dso_handle = (void *) &__dso_handle; +#endif + +__attribute__((weak)) void _init(void) +{ +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf new file mode 100644 index 0000000000..068eed7c42 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.* // "ramfunc" section + }; +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf new file mode 100644 index 0000000000..043a144210 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .uf2_signature }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf new file mode 100644 index 0000000000..f252f2a4ef --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf new file mode 100644 index 0000000000..c41b4ef3f5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors, block vectors_s }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf new file mode 100644 index 0000000000..d9d916b359 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00020000 size 128k]; /* ILM */ +define region DLM = [from 0x000A0000 size 96k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x000B8000 size 32k]; /* AXI SRAM1 */ +define region SHARE_RAM = [from 0x010BC000 size 16k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block cherryusb_usbh_class_info { section .usbh_class_info }; +define block framebuffer { section .framebuffer }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in DLM { block cherryusb_usbh_class_info }; +place in DLM { block framebuffer }; +place in DLM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s new file mode 100644 index 0000000000..a88a10bc91 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s @@ -0,0 +1,392 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_RISCV_crt0.s +Purpose : Generic runtime init startup code for RISC-V CPUs. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + +#include "hpm_csr_regs.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT reset_handler +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .type \Name, function +\Name: +.endm + +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .global \Name + .weak \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + .option push + .option norelax + lui gp, %hi(__global_pointer$) + addi gp, gp, %lo(__global_pointer$) + lui tp, %hi(__thread_pointer$) + addi tp, tp, %lo(__thread_pointer$) + .option pop + + csrw mstatus, zero + csrw mcause, zero + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + + lui t0, %hi(__stack_end__) + addi sp, t0, %lo(__stack_end__) + +#ifndef __NO_SYSTEM_INIT + // + // Call _init + // + call _init +#endif + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + lw a0, (s0) // Get next initialization function from table + add s0, s0, 4 // Increment table pointer to point to function arguments + jalr a0 // Call initialization function + j L(RunInit) + // +MARK_FUNC __SEGGER_init_done + // + // Time to call main(), the application entry point. + // + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#endif + +#if !defined(USE_NONVECTOR_MODE) + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + +MARK_FUNC start +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init a0 and a1. + // + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + j . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load a0 and a1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args + + call APP_ENTRY_POINT // Call to application entry point (usually main()) + call exit // Call exit function + j . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + +#ifdef FULL_LIBRARY + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args +#else + li a0, 0 + li a1, 0 +#endif + + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mv s1, a0 // Save the exit parameter/return result + // + // Call destructors + // + la s0, __dtors_start__ +L(Loop): + la t0, __dtors_end__ + beq s0, t0, L(End) + lw t1, 0(s0) + addi s0, s0, 4 + jalr t1 + j L(Loop) +L(End): + // + // Call atexit functions + // + call _execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mv a0, s1 + call debug_exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + j L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE + .size args, .-args + .type args, %object +#endif + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" + +/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c new file mode 100644 index 0000000000..4a38669a36 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ +#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ +#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ +#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ +#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ +#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +__attribute__((weak)) long exception_s_handler(long cause, long epc) +{ + return epc; +} + +__attribute__((weak)) void swi_s_isr(void) +{ +} + +__attribute__((weak)) void mchtmr_s_isr(void) +{ +} + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +#ifndef CONFIG_FREERTOS +void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4))); +#else +void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); +#endif +void irq_handler_s_trap(void) +{ + long scause = read_csr(CSR_SCAUSE); + long sepc = read_csr(CSR_SEPC); + long sstatus = read_csr(CSR_SSTATUS); + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { + /* Machine timer interrupt */ + mchtmr_s_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_s_global_irq(CSR_SSTATUS_SIE_MASK); +#endif + ((isr_func_t)__vector_s_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); + + } +#endif + + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_s_isr(); + intc_s_complete_swi(); + } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + sepc += 4; + } else { + sepc = exception_s_handler(scause, sepc); + } + + /* Restore CSR */ + write_csr(CSR_SSTATUS, sstatus); + write_csr(CSR_SEPC, sepc); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h new file mode 100644 index 0000000000..e48c61d0fd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + + +.global default_irq_s_handler +.weak default_irq_s_handler +.align 2 +default_irq_s_handler: +1: j 1b + +.macro IRQ_S_HANDLER irq + .weak default_isr_s_\irq + .set default_isr_s_\irq, default_irq_s_handler + .long default_isr_s_\irq +.endm + +.section .vector_s_table, "a" +.global __vector_s_table +.align 9 + +__vector_s_table: + .weak default_isr_s_trap + .set default_isr_s_trap, irq_handler_s_trap + .long default_isr_s_trap + IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_S_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_S_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_S_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_S_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_S_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_S_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_S_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_S_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_S_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_S_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_S_HANDLER 18 /* SDFM IRQ handler */ + IRQ_S_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_S_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_S_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_S_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_S_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_S_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_S_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_S_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_S_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_S_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_S_HANDLER 29 /* UART0 IRQ handler */ + IRQ_S_HANDLER 30 /* UART1 IRQ handler */ + IRQ_S_HANDLER 31 /* UART2 IRQ handler */ + IRQ_S_HANDLER 32 /* UART3 IRQ handler */ + IRQ_S_HANDLER 33 /* UART4 IRQ handler */ + IRQ_S_HANDLER 34 /* UART5 IRQ handler */ + IRQ_S_HANDLER 35 /* UART6 IRQ handler */ + IRQ_S_HANDLER 36 /* UART7 IRQ handler */ + IRQ_S_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_S_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_S_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_S_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_S_HANDLER 41 /* PTPC IRQ handler */ + IRQ_S_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_S_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_S_HANDLER 44 /* TSNS IRQ handler */ + IRQ_S_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_S_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_S_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_S_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_S_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_S_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_S_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_S_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_S_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_S_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_S_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_S_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_S_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_S_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_S_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_S_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_S_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_S_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_S_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_S_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_S_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_S_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_S_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_S_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_S_HANDLER 69 /* SDP IRQ handler */ + IRQ_S_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_S_HANDLER 71 /* XDMA IRQ handler */ + IRQ_S_HANDLER 72 /* HDMA IRQ handler */ + IRQ_S_HANDLER 73 /* RNG IRQ handler */ + IRQ_S_HANDLER 74 /* USB0 IRQ handler */ + IRQ_S_HANDLER 75 /* PSEC IRQ handler */ + IRQ_S_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_S_HANDLER 77 /* PWDG IRQ handler */ + IRQ_S_HANDLER 78 /* PTMR IRQ handler */ + IRQ_S_HANDLER 79 /* PUART IRQ handler */ + IRQ_S_HANDLER 80 /* FUSE IRQ handler */ + IRQ_S_HANDLER 81 /* SECMON IRQ handler */ + IRQ_S_HANDLER 82 /* RTC IRQ handler */ + IRQ_S_HANDLER 83 /* BUTN IRQ handler */ + IRQ_S_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_S_HANDLER 85 /* BVIO IRQ handler */ + IRQ_S_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_S_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_S_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_S_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_S_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_S_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_S_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_S_HANDLER 93 /* LIN3 IRQ handler */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml deleted file mode 100644 index cfa1eedc02..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml +++ /dev/null @@ -1,103475 +0,0 @@ - - - HPMICRO - HPM6360 - HPM6300 - 1.0 - HPM6300 device - - /* - * Copyright (c) 2021-2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - 8 - 32 - - 32 - 0x0 - 0xFFFFFFFF - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - DI_GPIOA_VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOA_SET - GPIO input set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOA_CLEAR - GPIO input clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOA_TOGGLE - GPIO input toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_VALUE - GPIOB input - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_SET - GPIO input set - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_CLEAR - GPIO input clear - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_TOGGLE - GPIO input toggle - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_VALUE - GPIOC input - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_SET - GPIO input set - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_CLEAR - GPIO input clear - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_TOGGLE - GPIO input toggle - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_VALUE - GPIOX input - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_SET - GPIO input set - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_CLEAR - GPIO input clear - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_TOGGLE - GPIO input toggle - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_VALUE - GPIOY input - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_SET - GPIO input set - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_CLEAR - GPIO input clear - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_TOGGLE - GPIO input toggle - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_VALUE - GPIOZ input - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_SET - GPIO input set - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_CLEAR - GPIO input clear - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_TOGGLE - GPIO input toggle - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DO_GPIOA_VALUE - GPIO output value - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOA_SET - GPIO output set - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOA_CLEAR - GPIO output clear - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOA_TOGGLE - GPIO output toggle - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_VALUE - GPIOB output - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_SET - GPIO output set - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_CLEAR - GPIO output clear - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_TOGGLE - GPIO output toggle - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_VALUE - GPIOC output - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_SET - GPIO output set - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_CLEAR - GPIO output clear - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_TOGGLE - GPIO output toggle - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_VALUE - GPIOX output - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_SET - GPIO output set - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_CLEAR - GPIO output clear - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_TOGGLE - GPIO output toggle - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_VALUE - GPIOY output - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_SET - GPIO output set - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_CLEAR - GPIO output clear - 0x1e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_TOGGLE - GPIO output toggle - 0x1ec - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_VALUE - GPIOZ output - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_SET - GPIO output set - 0x1f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_CLEAR - GPIO output clear - 0x1f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_TOGGLE - GPIO output toggle - 0x1fc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - OE_GPIOA_VALUE - GPIO direction value - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOA_SET - GPIO direction set - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOA_CLEAR - GPIO direction clear - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOA_TOGGLE - GPIO direction toggle - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_VALUE - GPIOB direction - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_SET - GPIO direction set - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_CLEAR - GPIO direction clear - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_TOGGLE - GPIO direction toggle - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_VALUE - GPIOC direction - 0x220 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_SET - GPIO direction set - 0x224 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_CLEAR - GPIO direction clear - 0x228 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_TOGGLE - GPIO direction toggle - 0x22c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_VALUE - GPIOX direction - 0x2d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_SET - GPIO direction set - 0x2d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_CLEAR - GPIO direction clear - 0x2d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_TOGGLE - GPIO direction toggle - 0x2dc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_VALUE - GPIOY direction - 0x2e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_SET - GPIO direction set - 0x2e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_CLEAR - GPIO direction clear - 0x2e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_TOGGLE - GPIO direction toggle - 0x2ec - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_VALUE - GPIOZ direction - 0x2f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_SET - GPIO direction set - 0x2f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_CLEAR - GPIO direction clear - 0x2f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_TOGGLE - GPIO direction toggle - 0x2fc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - IF_GPIOA_VALUE - GPIO interrupt flag value - 0x300 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOA_SET - GPIO interrupt flag set - 0x304 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOA_CLEAR - GPIO interrupt flag clear - 0x308 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOA_TOGGLE - GPIO interrupt flag toggle - 0x30c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_VALUE - GPIOB interrupt flag - 0x310 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_SET - GPIO interrupt flag set - 0x314 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_CLEAR - GPIO interrupt flag clear - 0x318 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_TOGGLE - GPIO interrupt flag toggle - 0x31c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_VALUE - GPIOC interrupt flag - 0x320 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_SET - GPIO interrupt flag set - 0x324 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_CLEAR - GPIO interrupt flag clear - 0x328 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_TOGGLE - GPIO interrupt flag toggle - 0x32c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_VALUE - GPIOX interrupt flag - 0x3d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_SET - GPIO interrupt flag set - 0x3d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_CLEAR - GPIO interrupt flag clear - 0x3d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_TOGGLE - GPIO interrupt flag toggle - 0x3dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_VALUE - GPIOY interrupt flag - 0x3e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_SET - GPIO interrupt flag set - 0x3e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_CLEAR - GPIO interrupt flag clear - 0x3e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_TOGGLE - GPIO interrupt flag toggle - 0x3ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_VALUE - GPIOZ interrupt flag - 0x3f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_SET - GPIO interrupt flag set - 0x3f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_CLEAR - GPIO interrupt flag clear - 0x3f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_TOGGLE - GPIO interrupt flag toggle - 0x3fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IE_GPIOA_VALUE - GPIO interrupt enable value - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOA_SET - GPIO interrupt enable set - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOA_CLEAR - GPIO interrupt enable clear - 0x408 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOA_TOGGLE - GPIO interrupt enable toggle - 0x40c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_VALUE - GPIOB interrupt enable - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_SET - GPIO interrupt enable set - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_CLEAR - GPIO interrupt enable clear - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_TOGGLE - GPIO interrupt enable toggle - 0x41c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_VALUE - GPIOC interrupt enable - 0x420 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_SET - GPIO interrupt enable set - 0x424 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_CLEAR - GPIO interrupt enable clear - 0x428 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_TOGGLE - GPIO interrupt enable toggle - 0x42c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_VALUE - GPIOX interrupt enable - 0x4d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_SET - GPIO interrupt enable set - 0x4d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_CLEAR - GPIO interrupt enable clear - 0x4d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_TOGGLE - GPIO interrupt enable toggle - 0x4dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_VALUE - GPIOY interrupt enable - 0x4e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_SET - GPIO interrupt enable set - 0x4e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_CLEAR - GPIO interrupt enable clear - 0x4e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_TOGGLE - GPIO interrupt enable toggle - 0x4ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_VALUE - GPIOZ interrupt enable - 0x4f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_SET - GPIO interrupt enable set - 0x4f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_CLEAR - GPIO interrupt enable clear - 0x4f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_TOGGLE - GPIO interrupt enable toggle - 0x4fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - PL_GPIOA_VALUE - GPIO interrupt polarity value - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOA_SET - GPIO interrupt polarity set - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOA_CLEAR - GPIO interrupt polarity clear - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOA_TOGGLE - GPIO interrupt polarity toggle - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_VALUE - GPIOB interrupt polarity - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_SET - GPIO interrupt polarity set - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_CLEAR - GPIO interrupt polarity clear - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_TOGGLE - GPIO interrupt polarity toggle - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_VALUE - GPIOC interrupt polarity - 0x520 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_SET - GPIO interrupt polarity set - 0x524 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_CLEAR - GPIO interrupt polarity clear - 0x528 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_TOGGLE - GPIO interrupt polarity toggle - 0x52c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_VALUE - GPIOX interrupt polarity - 0x5d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_SET - GPIO interrupt polarity set - 0x5d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_CLEAR - GPIO interrupt polarity clear - 0x5d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_TOGGLE - GPIO interrupt polarity toggle - 0x5dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_VALUE - GPIOY interrupt polarity - 0x5e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_SET - GPIO interrupt polarity set - 0x5e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_CLEAR - GPIO interrupt polarity clear - 0x5e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_TOGGLE - GPIO interrupt polarity toggle - 0x5ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_VALUE - GPIOZ interrupt polarity - 0x5f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_SET - GPIO interrupt polarity set - 0x5f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_CLEAR - GPIO interrupt polarity clear - 0x5f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_TOGGLE - GPIO interrupt polarity toggle - 0x5fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TP_GPIOA_VALUE - GPIO interrupt type value - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOA_SET - GPIO interrupt type set - 0x604 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOA_CLEAR - GPIO interrupt type clear - 0x608 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOA_TOGGLE - GPIO interrupt type toggle - 0x60c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_VALUE - GPIOB interrupt type - 0x610 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_SET - GPIO interrupt type set - 0x614 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_CLEAR - GPIO interrupt type clear - 0x618 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_TOGGLE - GPIO interrupt type toggle - 0x61c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_VALUE - GPIOC interrupt type - 0x620 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_SET - GPIO interrupt type set - 0x624 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_CLEAR - GPIO interrupt type clear - 0x628 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_TOGGLE - GPIO interrupt type toggle - 0x62c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_VALUE - GPIOX interrupt type - 0x6d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_SET - GPIO interrupt type set - 0x6d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_CLEAR - GPIO interrupt type clear - 0x6d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_TOGGLE - GPIO interrupt type toggle - 0x6dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_VALUE - GPIOY interrupt type - 0x6e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_SET - GPIO interrupt type set - 0x6e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_CLEAR - GPIO interrupt type clear - 0x6e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_TOGGLE - GPIO interrupt type toggle - 0x6ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_VALUE - GPIOZ interrupt type - 0x6f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_SET - GPIO interrupt type set - 0x6f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_CLEAR - GPIO interrupt type clear - 0x6f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_TOGGLE - GPIO interrupt type toggle - 0x6fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - AS_GPIOA_VALUE - GPIO interrupt asynchronous value - 0x700 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOA_SET - GPIO interrupt asynchronous set - 0x704 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOA_CLEAR - GPIO interrupt asynchronous clear - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOA_TOGGLE - GPIO interrupt asynchronous toggle - 0x70c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_VALUE - GPIOB interrupt asynchronous - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_SET - GPIO interrupt asynchronous set - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_CLEAR - GPIO interrupt asynchronous clear - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_TOGGLE - GPIO interrupt asynchronous toggle - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_VALUE - GPIOC interrupt asynchronous - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_SET - GPIO interrupt asynchronous set - 0x724 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_CLEAR - GPIO interrupt asynchronous clear - 0x728 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_TOGGLE - GPIO interrupt asynchronous toggle - 0x72c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_VALUE - GPIOX interrupt asynchronous - 0x7d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_SET - GPIO interrupt asynchronous set - 0x7d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_CLEAR - GPIO interrupt asynchronous clear - 0x7d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_TOGGLE - GPIO interrupt asynchronous toggle - 0x7dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_VALUE - GPIOY interrupt asynchronous - 0x7e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_SET - GPIO interrupt asynchronous set - 0x7e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_CLEAR - GPIO interrupt asynchronous clear - 0x7e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_TOGGLE - GPIO interrupt asynchronous toggle - 0x7ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_VALUE - GPIOZ interrupt asynchronous - 0x7f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_SET - GPIO interrupt asynchronous set - 0x7f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_CLEAR - GPIO interrupt asynchronous clear - 0x7f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_TOGGLE - GPIO interrupt asynchronous toggle - 0x7fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf0000000 - - - PGPIO - PGPIO - GPIO - 0xf40dc000 - - - BGPIO - BGPIO - GPIO - 0xf5014000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - FEATURE - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - PRIORITY_PRIORITY1 - Source priority - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY2 - Source priority - 0x8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY3 - Source priority - 0xc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY4 - Source priority - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY5 - Source priority - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY6 - Source priority - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY7 - Source priority - 0x1c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY8 - Source priority - 0x20 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY9 - Source priority - 0x24 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY10 - Source priority - 0x28 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY11 - Source priority - 0x2c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY12 - Source priority - 0x30 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY13 - Source priority - 0x34 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY14 - Source priority - 0x38 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY15 - Source priority - 0x3c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY16 - Source priority - 0x40 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY17 - Source priority - 0x44 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY18 - Source priority - 0x48 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY19 - Source priority - 0x4c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY20 - Source priority - 0x50 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY21 - Source priority - 0x54 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY22 - Source priority - 0x58 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY23 - Source priority - 0x5c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY24 - Source priority - 0x60 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY25 - Source priority - 0x64 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY26 - Source priority - 0x68 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY27 - Source priority - 0x6c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY28 - Source priority - 0x70 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY29 - Source priority - 0x74 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY30 - Source priority - 0x78 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY31 - Source priority - 0x7c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY32 - Source priority - 0x80 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY33 - Source priority - 0x84 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY34 - Source priority - 0x88 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY35 - Source priority - 0x8c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY36 - Source priority - 0x90 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY37 - Source priority - 0x94 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY38 - Source priority - 0x98 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY39 - Source priority - 0x9c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY40 - Source priority - 0xa0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY41 - Source priority - 0xa4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY42 - Source priority - 0xa8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY43 - Source priority - 0xac - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY44 - Source priority - 0xb0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY45 - Source priority - 0xb4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY46 - Source priority - 0xb8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY47 - Source priority - 0xbc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY48 - Source priority - 0xc0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY49 - Source priority - 0xc4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY50 - Source priority - 0xc8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY51 - Source priority - 0xcc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY52 - Source priority - 0xd0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY53 - Source priority - 0xd4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY54 - Source priority - 0xd8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY55 - Source priority - 0xdc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY56 - Source priority - 0xe0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY57 - Source priority - 0xe4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY58 - Source priority - 0xe8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY59 - Source priority - 0xec - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY60 - Source priority - 0xf0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY61 - Source priority - 0xf4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY62 - Source priority - 0xf8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY63 - Source priority - 0xfc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY64 - Source priority - 0x100 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY65 - Source priority - 0x104 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY66 - Source priority - 0x108 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY67 - Source priority - 0x10c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY68 - Source priority - 0x110 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY69 - Source priority - 0x114 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY70 - Source priority - 0x118 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY71 - Source priority - 0x11c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY72 - Source priority - 0x120 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY73 - Source priority - 0x124 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY74 - Source priority - 0x128 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY75 - Source priority - 0x12c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY76 - Source priority - 0x130 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY77 - Source priority - 0x134 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY78 - Source priority - 0x138 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY79 - Source priority - 0x13c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY80 - Source priority - 0x140 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY81 - Source priority - 0x144 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY82 - Source priority - 0x148 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY83 - Source priority - 0x14c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY84 - Source priority - 0x150 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY85 - Source priority - 0x154 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY86 - Source priority - 0x158 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY87 - Source priority - 0x15c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY88 - Source priority - 0x160 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY89 - Source priority - 0x164 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY90 - Source priority - 0x168 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY91 - Source priority - 0x16c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY92 - Source priority - 0x170 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY93 - Source priority - 0x174 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY94 - Source priority - 0x178 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY95 - Source priority - 0x17c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY96 - Source priority - 0x180 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY97 - Source priority - 0x184 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY98 - Source priority - 0x188 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY99 - Source priority - 0x18c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY100 - Source priority - 0x190 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY101 - Source priority - 0x194 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY102 - Source priority - 0x198 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY103 - Source priority - 0x19c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY104 - Source priority - 0x1a0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY105 - Source priority - 0x1a4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY106 - Source priority - 0x1a8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY107 - Source priority - 0x1ac - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY108 - Source priority - 0x1b0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY109 - Source priority - 0x1b4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY110 - Source priority - 0x1b8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY111 - Source priority - 0x1bc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY112 - Source priority - 0x1c0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY113 - Source priority - 0x1c4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY114 - Source priority - 0x1c8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY115 - Source priority - 0x1cc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY116 - Source priority - 0x1d0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY117 - Source priority - 0x1d4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY118 - Source priority - 0x1d8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY119 - Source priority - 0x1dc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY120 - Source priority - 0x1e0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY121 - Source priority - 0x1e4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY122 - Source priority - 0x1e8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY123 - Source priority - 0x1ec - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY124 - Source priority - 0x1f0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY125 - Source priority - 0x1f4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY126 - Source priority - 0x1f8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY127 - Source priority - 0x1fc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PENDING_PENDING0 - Pending status - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - PENDING_PENDING1 - Pending status - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - PENDING_PENDING2 - Pending status - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - PENDING_PENDING3 - Pending status - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TRIGGER_TRIGGER0 - Trigger type - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - TRIGGER_TRIGGER1 - Trigger type - 0x1084 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - TRIGGER_TRIGGER2 - Trigger type - 0x1088 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - TRIGGER_TRIGGER3 - Trigger type - 0x108c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - TARGETINT_TARGET0_INTEN0 - machine interrupt enable - 0x2000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET0_INTEN1 - machine interrupt enable - 0x2004 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET0_INTEN2 - machine interrupt enable - 0x2008 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET0_INTEN3 - machine interrupt enable - 0x200c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN0 - supervisor interrupt enable - 0x2080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN1 - supervisor interrupt enable - 0x2084 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN2 - supervisor interrupt enable - 0x2088 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN3 - supervisor interrupt enable - 0x208c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET0_THRESHOLD - Target0 priority threshold - 0x200000 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET0_CLAIM - Target claim and complete - 0x200004 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - TARGETCONFIG_TARGET0_PPS - Preempted priority stack - 0x200400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET1_THRESHOLD - Target1 priority threshold - 0x201000 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET1_CLAIM - Target claim and complete - 0x201004 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - TARGETCONFIG_TARGET1_PPS - Preempted priority stack - 0x201400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLIC_SW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPIOM - GPIOM - GPIOM - 0xf0008000 - - 0x0 - 0x800 - registers - - - - ASSIGN_GPIOA_PIN_PIN00 - GPIO mananger - 0x0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN01 - GPIO mananger - 0x4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN02 - GPIO mananger - 0x8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN03 - GPIO mananger - 0xc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN04 - GPIO mananger - 0x10 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN05 - GPIO mananger - 0x14 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN06 - GPIO mananger - 0x18 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN07 - GPIO mananger - 0x1c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN08 - GPIO mananger - 0x20 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN09 - GPIO mananger - 0x24 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN10 - GPIO mananger - 0x28 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN11 - GPIO mananger - 0x2c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN12 - GPIO mananger - 0x30 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN13 - GPIO mananger - 0x34 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN14 - GPIO mananger - 0x38 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN15 - GPIO mananger - 0x3c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN16 - GPIO mananger - 0x40 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN17 - GPIO mananger - 0x44 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN18 - GPIO mananger - 0x48 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN19 - GPIO mananger - 0x4c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN20 - GPIO mananger - 0x50 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN21 - GPIO mananger - 0x54 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN22 - GPIO mananger - 0x58 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN23 - GPIO mananger - 0x5c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN24 - GPIO mananger - 0x60 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN25 - GPIO mananger - 0x64 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN26 - GPIO mananger - 0x68 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN27 - GPIO mananger - 0x6c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN28 - GPIO mananger - 0x70 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN29 - GPIO mananger - 0x74 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN30 - GPIO mananger - 0x78 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN31 - GPIO mananger - 0x7c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN00 - GPIO mananger - 0x80 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN01 - GPIO mananger - 0x84 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN02 - GPIO mananger - 0x88 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN03 - GPIO mananger - 0x8c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN04 - GPIO mananger - 0x90 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN05 - GPIO mananger - 0x94 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN06 - GPIO mananger - 0x98 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN07 - GPIO mananger - 0x9c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN08 - GPIO mananger - 0xa0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN09 - GPIO mananger - 0xa4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN10 - GPIO mananger - 0xa8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN11 - GPIO mananger - 0xac - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN12 - GPIO mananger - 0xb0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN13 - GPIO mananger - 0xb4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN14 - GPIO mananger - 0xb8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN15 - GPIO mananger - 0xbc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN16 - GPIO mananger - 0xc0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN17 - GPIO mananger - 0xc4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN18 - GPIO mananger - 0xc8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN19 - GPIO mananger - 0xcc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN20 - GPIO mananger - 0xd0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN21 - GPIO mananger - 0xd4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN22 - GPIO mananger - 0xd8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN23 - GPIO mananger - 0xdc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN24 - GPIO mananger - 0xe0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN25 - GPIO mananger - 0xe4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN26 - GPIO mananger - 0xe8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN27 - GPIO mananger - 0xec - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN28 - GPIO mananger - 0xf0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN29 - GPIO mananger - 0xf4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN30 - GPIO mananger - 0xf8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN31 - GPIO mananger - 0xfc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN00 - GPIO mananger - 0x100 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN01 - GPIO mananger - 0x104 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN02 - GPIO mananger - 0x108 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN03 - GPIO mananger - 0x10c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN04 - GPIO mananger - 0x110 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN05 - GPIO mananger - 0x114 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN06 - GPIO mananger - 0x118 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN07 - GPIO mananger - 0x11c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN08 - GPIO mananger - 0x120 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN09 - GPIO mananger - 0x124 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN10 - GPIO mananger - 0x128 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN11 - GPIO mananger - 0x12c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN12 - GPIO mananger - 0x130 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN13 - GPIO mananger - 0x134 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN14 - GPIO mananger - 0x138 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN15 - GPIO mananger - 0x13c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN16 - GPIO mananger - 0x140 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN17 - GPIO mananger - 0x144 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN18 - GPIO mananger - 0x148 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN19 - GPIO mananger - 0x14c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN20 - GPIO mananger - 0x150 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN21 - GPIO mananger - 0x154 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN22 - GPIO mananger - 0x158 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN23 - GPIO mananger - 0x15c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN24 - GPIO mananger - 0x160 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN25 - GPIO mananger - 0x164 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN26 - GPIO mananger - 0x168 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN27 - GPIO mananger - 0x16c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN28 - GPIO mananger - 0x170 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN29 - GPIO mananger - 0x174 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN30 - GPIO mananger - 0x178 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN31 - GPIO mananger - 0x17c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN00 - GPIO mananger - 0x680 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN01 - GPIO mananger - 0x684 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN02 - GPIO mananger - 0x688 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN03 - GPIO mananger - 0x68c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN04 - GPIO mananger - 0x690 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN05 - GPIO mananger - 0x694 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN06 - GPIO mananger - 0x698 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN07 - GPIO mananger - 0x69c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN08 - GPIO mananger - 0x6a0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN09 - GPIO mananger - 0x6a4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN10 - GPIO mananger - 0x6a8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN11 - GPIO mananger - 0x6ac - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN12 - GPIO mananger - 0x6b0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN13 - GPIO mananger - 0x6b4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN14 - GPIO mananger - 0x6b8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN15 - GPIO mananger - 0x6bc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN16 - GPIO mananger - 0x6c0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN17 - GPIO mananger - 0x6c4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN18 - GPIO mananger - 0x6c8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN19 - GPIO mananger - 0x6cc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN20 - GPIO mananger - 0x6d0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN21 - GPIO mananger - 0x6d4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN22 - GPIO mananger - 0x6d8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN23 - GPIO mananger - 0x6dc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN24 - GPIO mananger - 0x6e0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN25 - GPIO mananger - 0x6e4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN26 - GPIO mananger - 0x6e8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN27 - GPIO mananger - 0x6ec - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN28 - GPIO mananger - 0x6f0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN29 - GPIO mananger - 0x6f4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN30 - GPIO mananger - 0x6f8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN31 - GPIO mananger - 0x6fc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN00 - GPIO mananger - 0x700 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN01 - GPIO mananger - 0x704 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN02 - GPIO mananger - 0x708 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN03 - GPIO mananger - 0x70c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN04 - GPIO mananger - 0x710 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN05 - GPIO mananger - 0x714 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN06 - GPIO mananger - 0x718 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN07 - GPIO mananger - 0x71c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN08 - GPIO mananger - 0x720 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN09 - GPIO mananger - 0x724 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN10 - GPIO mananger - 0x728 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN11 - GPIO mananger - 0x72c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN12 - GPIO mananger - 0x730 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN13 - GPIO mananger - 0x734 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN14 - GPIO mananger - 0x738 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN15 - GPIO mananger - 0x73c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN16 - GPIO mananger - 0x740 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN17 - GPIO mananger - 0x744 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN18 - GPIO mananger - 0x748 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN19 - GPIO mananger - 0x74c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN20 - GPIO mananger - 0x750 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN21 - GPIO mananger - 0x754 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN22 - GPIO mananger - 0x758 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN23 - GPIO mananger - 0x75c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN24 - GPIO mananger - 0x760 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN25 - GPIO mananger - 0x764 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN26 - GPIO mananger - 0x768 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN27 - GPIO mananger - 0x76c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN28 - GPIO mananger - 0x770 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN29 - GPIO mananger - 0x774 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN30 - GPIO mananger - 0x778 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN31 - GPIO mananger - 0x77c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN00 - GPIO mananger - 0x780 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN01 - GPIO mananger - 0x784 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN02 - GPIO mananger - 0x788 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN03 - GPIO mananger - 0x78c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN04 - GPIO mananger - 0x790 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN05 - GPIO mananger - 0x794 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN06 - GPIO mananger - 0x798 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN07 - GPIO mananger - 0x79c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN08 - GPIO mananger - 0x7a0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN09 - GPIO mananger - 0x7a4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN10 - GPIO mananger - 0x7a8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN11 - GPIO mananger - 0x7ac - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN12 - GPIO mananger - 0x7b0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN13 - GPIO mananger - 0x7b4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN14 - GPIO mananger - 0x7b8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN15 - GPIO mananger - 0x7bc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN16 - GPIO mananger - 0x7c0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN17 - GPIO mananger - 0x7c4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN18 - GPIO mananger - 0x7c8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN19 - GPIO mananger - 0x7cc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN20 - GPIO mananger - 0x7d0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN21 - GPIO mananger - 0x7d4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN22 - GPIO mananger - 0x7d8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN23 - GPIO mananger - 0x7dc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN24 - GPIO mananger - 0x7e0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN25 - GPIO mananger - 0x7e4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN26 - GPIO mananger - 0x7e8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN27 - GPIO mananger - 0x7ec - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN28 - GPIO mananger - 0x7f0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN29 - GPIO mananger - 0x7f4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN30 - GPIO mananger - 0x7f8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN31 - GPIO mananger - 0x7fc - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - - - ADC0 - ADC0 - ADC16 - 0xf0010000 - - 0x0 - 0x1464 - registers - - - - CONFIG_TRG0A - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG0B - No description avaiable - 0x4 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG0C - No description avaiable - 0x8 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1A - No description avaiable - 0xc - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1B - No description avaiable - 0x10 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1C - No description avaiable - 0x14 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2A - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2B - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2C - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3A - No description avaiable - 0x24 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3B - No description avaiable - 0x28 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3C - No description avaiable - 0x2c - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - TRG_DMA_ADDR - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - BUS_RESULT_CHN0 - No description avaiable - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN1 - No description avaiable - 0x404 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN2 - No description avaiable - 0x408 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN3 - No description avaiable - 0x40c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN4 - No description avaiable - 0x410 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN5 - No description avaiable - 0x414 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN6 - No description avaiable - 0x418 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN7 - No description avaiable - 0x41c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN8 - No description avaiable - 0x420 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN9 - No description avaiable - 0x424 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN10 - No description avaiable - 0x428 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN11 - No description avaiable - 0x42c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN12 - No description avaiable - 0x430 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN13 - No description avaiable - 0x434 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN14 - No description avaiable - 0x438 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN15 - No description avaiable - 0x43c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUF_CFG0 - No description avaiable - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - SEQ_CFG0 - No description avaiable - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - SEQ_DMA_ADDR - No description avaiable - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - SEQ_WR_ADDR - No description avaiable - 0x808 - 32 - 0x00000000 - 0x00000FFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 12 - read-only - - - - - SEQ_DMA_CFG - No description avaiable - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - SEQ_QUE_CFG0 - No description avaiable - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG1 - No description avaiable - 0x814 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG2 - No description avaiable - 0x818 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG3 - No description avaiable - 0x81c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG4 - No description avaiable - 0x820 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG5 - No description avaiable - 0x824 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG6 - No description avaiable - 0x828 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG7 - No description avaiable - 0x82c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG8 - No description avaiable - 0x830 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG9 - No description avaiable - 0x834 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG10 - No description avaiable - 0x838 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG11 - No description avaiable - 0x83c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG12 - No description avaiable - 0x840 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG13 - No description avaiable - 0x844 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG14 - No description avaiable - 0x848 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG15 - No description avaiable - 0x84c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - PRD_CFG_CHN0_PRD_CFG - No description avaiable - 0xc00 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN0_PRD_THSHD_CFG - No description avaiable - 0xc04 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN0_PRD_RESULT - No description avaiable - 0xc08 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN1_PRD_CFG - No description avaiable - 0xc10 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN1_PRD_THSHD_CFG - No description avaiable - 0xc14 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN1_PRD_RESULT - No description avaiable - 0xc18 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN2_PRD_CFG - No description avaiable - 0xc20 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN2_PRD_THSHD_CFG - No description avaiable - 0xc24 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN2_PRD_RESULT - No description avaiable - 0xc28 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN3_PRD_CFG - No description avaiable - 0xc30 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN3_PRD_THSHD_CFG - No description avaiable - 0xc34 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN3_PRD_RESULT - No description avaiable - 0xc38 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN4_PRD_CFG - No description avaiable - 0xc40 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN4_PRD_THSHD_CFG - No description avaiable - 0xc44 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN4_PRD_RESULT - No description avaiable - 0xc48 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN5_PRD_CFG - No description avaiable - 0xc50 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN5_PRD_THSHD_CFG - No description avaiable - 0xc54 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN5_PRD_RESULT - No description avaiable - 0xc58 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN6_PRD_CFG - No description avaiable - 0xc60 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN6_PRD_THSHD_CFG - No description avaiable - 0xc64 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN6_PRD_RESULT - No description avaiable - 0xc68 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN7_PRD_CFG - No description avaiable - 0xc70 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN7_PRD_THSHD_CFG - No description avaiable - 0xc74 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN7_PRD_RESULT - No description avaiable - 0xc78 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN8_PRD_CFG - No description avaiable - 0xc80 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN8_PRD_THSHD_CFG - No description avaiable - 0xc84 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN8_PRD_RESULT - No description avaiable - 0xc88 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN9_PRD_CFG - No description avaiable - 0xc90 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN9_PRD_THSHD_CFG - No description avaiable - 0xc94 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN9_PRD_RESULT - No description avaiable - 0xc98 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN10_PRD_CFG - No description avaiable - 0xca0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN10_PRD_THSHD_CFG - No description avaiable - 0xca4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN10_PRD_RESULT - No description avaiable - 0xca8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN11_PRD_CFG - No description avaiable - 0xcb0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN11_PRD_THSHD_CFG - No description avaiable - 0xcb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN11_PRD_RESULT - No description avaiable - 0xcb8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN12_PRD_CFG - No description avaiable - 0xcc0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN12_PRD_THSHD_CFG - No description avaiable - 0xcc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN12_PRD_RESULT - No description avaiable - 0xcc8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN13_PRD_CFG - No description avaiable - 0xcd0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN13_PRD_THSHD_CFG - No description avaiable - 0xcd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN13_PRD_RESULT - No description avaiable - 0xcd8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN14_PRD_CFG - No description avaiable - 0xce0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN14_PRD_THSHD_CFG - No description avaiable - 0xce4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN14_PRD_RESULT - No description avaiable - 0xce8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN15_PRD_CFG - No description avaiable - 0xcf0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN15_PRD_THSHD_CFG - No description avaiable - 0xcf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN15_PRD_RESULT - No description avaiable - 0xcf8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - SAMPLE_CFG_CHN0 - No description avaiable - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN1 - No description avaiable - 0x1004 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN2 - No description avaiable - 0x1008 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN3 - No description avaiable - 0x100c - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN4 - No description avaiable - 0x1010 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN5 - No description avaiable - 0x1014 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN6 - No description avaiable - 0x1018 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN7 - No description avaiable - 0x101c - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN8 - No description avaiable - 0x1020 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN9 - No description avaiable - 0x1024 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN10 - No description avaiable - 0x1028 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN11 - No description avaiable - 0x102c - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN12 - No description avaiable - 0x1030 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN13 - No description avaiable - 0x1034 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN14 - No description avaiable - 0x1038 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN15 - No description avaiable - 0x103c - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - CONV_CFG1 - No description avaiable - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); -user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. -set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. - 0 - 4 - read-write - - - - - ADC_CFG0 - No description avaiable - 0x1108 - 32 - 0x00000000 - 0xAFFFF001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - CONVERT_DURATION - for trigger queue, from trg_sample_req to trg_convert_req - 12 - 16 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - INT_STS - No description avaiable - 0x1110 - 32 - 0x00000000 - 0xFFE03FFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description avaiable - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description avaiable - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrup, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description avaiable - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 14 - read-write - - - - - INT_EN - No description avaiable - 0x1114 - 32 - 0x00000000 - 0xFFE03FFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description avaiable - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description avaiable - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrup, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description avaiable - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 14 - read-write - - - - - ANA_CTRL0 - No description avaiable - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ANA_STATUS - No description avaiable - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - ADC16_PARAMS_ADC16_PARA00 - No description avaiable - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA01 - No description avaiable - 0x1402 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA02 - No description avaiable - 0x1404 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA03 - No description avaiable - 0x1406 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA04 - No description avaiable - 0x1408 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA05 - No description avaiable - 0x140a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA06 - No description avaiable - 0x140c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA07 - No description avaiable - 0x140e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA08 - No description avaiable - 0x1410 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA09 - No description avaiable - 0x1412 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA10 - No description avaiable - 0x1414 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA11 - No description avaiable - 0x1416 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA12 - No description avaiable - 0x1418 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA13 - No description avaiable - 0x141a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA14 - No description avaiable - 0x141c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA15 - No description avaiable - 0x141e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA16 - No description avaiable - 0x1420 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA17 - No description avaiable - 0x1422 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA18 - No description avaiable - 0x1424 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA19 - No description avaiable - 0x1426 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA20 - No description avaiable - 0x1428 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA21 - No description avaiable - 0x142a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA22 - No description avaiable - 0x142c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA23 - No description avaiable - 0x142e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA24 - No description avaiable - 0x1430 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA25 - No description avaiable - 0x1432 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA26 - No description avaiable - 0x1434 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA27 - No description avaiable - 0x1436 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA28 - No description avaiable - 0x1438 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA29 - No description avaiable - 0x143a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA30 - No description avaiable - 0x143c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA31 - No description avaiable - 0x143e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA32 - No description avaiable - 0x1440 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA33 - No description avaiable - 0x1442 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_CONFIG0 - No description avaiable - 0x1444 - 32 - 0x00000000 - 0x03F07FFF - - - TEMPSNS_EN - set to enable temp senser - 25 - 1 - read-write - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - convertion parameter - 0 - 14 - read-write - - - - - ADC16_CONFIG1 - No description avaiable - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number). - 8 - 5 - read-write - - - - - - - ADC1 - ADC1 - ADC16 - 0xf0014000 - - - ADC2 - ADC2 - ADC16 - 0xf0018000 - - - ACMP - ACMP - ACMP - 0xf0020000 - - 0x0 - 0x80 - registers - - - - CHANNEL_CHN0_CFG - Configure Register - 0x0 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN0_DACCFG - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN0_SR - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN0_IRQEN - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN0_DMAEN - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN1_CFG - Configure Register - 0x20 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN1_DACCFG - DAC configure register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN1_SR - Status register - 0x30 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN1_IRQEN - Interrupt request enable register - 0x34 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN1_DMAEN - DMA request enable register - 0x38 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN2_CFG - Configure Register - 0x40 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN2_DACCFG - DAC configure register - 0x44 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN2_SR - Status register - 0x50 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN2_IRQEN - Interrupt request enable register - 0x54 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN2_DMAEN - DMA request enable register - 0x58 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN3_CFG - Configure Register - 0x60 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN3_DACCFG - DAC configure register - 0x64 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN3_SR - Status register - 0x70 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN3_IRQEN - Interrupt request enable register - 0x74 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN3_DMAEN - DMA request enable register - 0x78 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - DAC - DAC - DAC - 0xf0024000 - - 0x0 - 0x4c - registers - - - - CFG0 - No description avaiable - 0x0 - 32 - 0x00000000 - 0x0FFF03FF - - - SW_DAC_DATA - dac data used in direct mode(dac_mode==2'b10) - 16 - 12 - write-only - - - DMA_AHB_EN - set to enable internal DMA, it will read one burst if enough space in FIFO. -Should only be used in buffer mode. - 9 - 1 - write-only - - - SYNC_MODE - 1: sync dac clock and ahb clock. - all HW trigger signals are pulse in sync mode, can get faster response; -0: async dac clock and ahb_clock - all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - 8 - 1 - write-only - - - TRIG_MODE - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; -1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - 7 - 1 - write-only - - - HW_TRIG_EN - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - 6 - 1 - write-only - - - DAC_MODE - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) -01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - 4 - 2 - write-only - - - BUF_DATA_MODE - data structure for buffer mode, -0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. -1: each 32-bit data contains 1 point, b11:0 for first - 3 - 1 - write-only - - - HBURST_CFG - DAC support following fixed burst only -000-SINGLE; 011-INCR4; 101: INCR8 -others are reserved - 0 - 3 - write-only - - - - - CFG1 - No description avaiable - 0x4 - 32 - 0x00010000 - 0x0007FFFF - - - ANA_CLK_EN - set to enable analog clock(divided by ana_div_cfg) - 18 - 1 - read-write - - - ANA_DIV_CFG - clock divider config for ana_clk to dac analog; -00: div2 -01: div4 -10: div6 -11: div8 - 16 - 2 - read-write - - - DIV_CFG - how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. -Used for step mode and buffer mode, if set to continual trigger mode - 0 - 16 - read-write - - - - - CFG2 - No description avaiable - 0x8 - 32 - 0x00000000 - 0x000000FF - - - DMA_RST1 - set to reset dma read pointer to buf1_start_addr; -if set both dma_rst0&dma_rst1, will set to buf0_start_addr -user can set fifo_clr bit when use dma_rst* - 7 - 1 - write-only - - - DMA_RST0 - set to reset dma read pointer to buf0_start_addr - 6 - 1 - write-only - - - FIFO_CLR - set to clear FIFO content(set both read/write pointer to 0) - 5 - 1 - write-only - - - BUF_SW_TRIG - software trigger for buffer mode, -W1C in single mode. -RW in continual mode - 4 - 1 - read-write - - - STEP_SW_TRIG3 - No description avaiable - 3 - 1 - read-write - - - STEP_SW_TRIG2 - No description avaiable - 2 - 1 - read-write - - - STEP_SW_TRIG1 - No description avaiable - 1 - 1 - read-write - - - STEP_SW_TRIG0 - software trigger0 for step mode, -W1C in single mode. -RW in continual mode - 0 - 1 - read-write - - - - - STEP_CFG_STEP0 - No description avaiable - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - ROUND_MODE - 0: stop at end point; -1: reload start point, step again - 29 - 1 - read-write - - - UP_DOWN - 0 for up, 1 for down - 28 - 1 - read-write - - - END_POINT - No description avaiable - 16 - 12 - read-write - - - STEP_NUM - output data change step_num each DAC clock cycle. -Ex: if step_num=3, output data sequence is 0,3,6,9 -NOTE: user should make sure end_point can be reached if step_num is not 1 -if step_num is 0, output data will always at start point - 12 - 4 - read-write - - - START_POINT - No description avaiable - 0 - 12 - read-write - - - - - STEP_CFG_STEP1 - No description avaiable - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - ROUND_MODE - 0: stop at end point; -1: reload start point, step again - 29 - 1 - read-write - - - UP_DOWN - 0 for up, 1 for down - 28 - 1 - read-write - - - END_POINT - No description avaiable - 16 - 12 - read-write - - - STEP_NUM - output data change step_num each DAC clock cycle. -Ex: if step_num=3, output data sequence is 0,3,6,9 -NOTE: user should make sure end_point can be reached if step_num is not 1 -if step_num is 0, output data will always at start point - 12 - 4 - read-write - - - START_POINT - No description avaiable - 0 - 12 - read-write - - - - - STEP_CFG_STEP2 - No description avaiable - 0x18 - 32 - 0x00000000 - 0x3FFFFFFF - - - ROUND_MODE - 0: stop at end point; -1: reload start point, step again - 29 - 1 - read-write - - - UP_DOWN - 0 for up, 1 for down - 28 - 1 - read-write - - - END_POINT - No description avaiable - 16 - 12 - read-write - - - STEP_NUM - output data change step_num each DAC clock cycle. -Ex: if step_num=3, output data sequence is 0,3,6,9 -NOTE: user should make sure end_point can be reached if step_num is not 1 -if step_num is 0, output data will always at start point - 12 - 4 - read-write - - - START_POINT - No description avaiable - 0 - 12 - read-write - - - - - STEP_CFG_STEP3 - No description avaiable - 0x1c - 32 - 0x00000000 - 0x3FFFFFFF - - - ROUND_MODE - 0: stop at end point; -1: reload start point, step again - 29 - 1 - read-write - - - UP_DOWN - 0 for up, 1 for down - 28 - 1 - read-write - - - END_POINT - No description avaiable - 16 - 12 - read-write - - - STEP_NUM - output data change step_num each DAC clock cycle. -Ex: if step_num=3, output data sequence is 0,3,6,9 -NOTE: user should make sure end_point can be reached if step_num is not 1 -if step_num is 0, output data will always at start point - 12 - 4 - read-write - - - START_POINT - No description avaiable - 0 - 12 - read-write - - - - - BUF_ADDR_BUF0 - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFD - - - BUF_START_ADDR - buffer start address, should be 4-byte aligned -AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - 2 - 30 - read-write - - - BUF_STOP - set to stop read point at end of bufffer0 - 0 - 1 - read-write - - - - - BUF_ADDR_BUF1 - No description avaiable - 0x24 - 32 - 0x00000000 - 0xFFFFFFFD - - - BUF_START_ADDR - buffer start address, should be 4-byte aligned -AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - 2 - 30 - read-write - - - BUF_STOP - set to stop read point at end of bufffer0 - 0 - 1 - read-write - - - - - BUF_LENGTH - No description avaiable - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF1_LEN - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer - 16 - 16 - read-write - - - BUF0_LEN - No description avaiable - 0 - 16 - read-write - - - - - IRQ_STS - No description avaiable - 0x30 - 32 - 0x00000000 - 0x0000000F - - - AHB_ERROR - set if hresp==2'b01(ERROR) - 3 - 1 - read-write - - - FIFO_EMPTY - No description avaiable - 2 - 1 - read-write - - - BUF1_CMPT - No description avaiable - 1 - 1 - read-write - - - BUF0_CMPT - No description avaiable - 0 - 1 - read-write - - - - - IRQ_EN - No description avaiable - 0x34 - 32 - 0x00000000 - 0x0000000F - - - AHB_ERROR - No description avaiable - 3 - 1 - read-write - - - FIFO_EMPTY - No description avaiable - 2 - 1 - read-write - - - BUF1_CMPT - No description avaiable - 1 - 1 - read-write - - - BUF0_CMPT - No description avaiable - 0 - 1 - read-write - - - - - DMA_EN - No description avaiable - 0x38 - 32 - 0x00000000 - 0x00000003 - - - BUF1_CMPT - No description avaiable - 1 - 1 - read-write - - - BUF0_CMPT - No description avaiable - 0 - 1 - read-write - - - - - ANA_CFG0 - No description avaiable - 0x40 - 32 - 0x00000110 - 0x000001FF - - - DAC12BIT_LP_MODE - No description avaiable - 8 - 1 - read-write - - - DAC_CONFIG - No description avaiable - 4 - 4 - read-write - - - CALI_DELTA_V_CFG - No description avaiable - 2 - 2 - read-write - - - BYPASS_CALI_GM - No description avaiable - 1 - 1 - read-write - - - DAC12BIT_EN - No description avaiable - 0 - 1 - read-write - - - - - STATUS0 - No description avaiable - 0x48 - 32 - 0x00000000 - 0x00FFFF80 - - - CUR_BUF_OFFSET - No description avaiable - 8 - 16 - read-write - - - CUR_BUF_INDEX - No description avaiable - 7 - 1 - read-write - - - - - - - SPI0 - SPI0 - SPI - 0xf0030000 - - 0x10 - 0x70 - registers - - - - TRANSFMT - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - RESERVED - No description avaiable - 18 - 14 - read-write - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - DIRECTIO - Direct IO Control Register - 0x14 - 32 - 0x00003100 - 0x013F3F3F - - - DIRECTIOEN - Enable Direct IO -0x0: Disable -0x1: Enable - 24 - 1 - read-write - - - HOLD_OE - Output enable for the SPI Flash hold signal - 21 - 1 - read-write - - - WP_OE - Output enable for the SPI Flash write protect signal - 20 - 1 - read-write - - - MISO_OE - Output enable fo the SPI MISO signal - 19 - 1 - read-write - - - MOSI_OE - Output enable for the SPI MOSI signal - 18 - 1 - read-write - - - SCLK_OE - Output enable for the SPI SCLK signal - 17 - 1 - read-write - - - CS_OE - Output enable for SPI CS (chip select) signal - 16 - 1 - read-write - - - HOLD_O - Output value for the SPI Flash hold signal - 13 - 1 - read-write - - - WP_O - Output value for the SPI Flash write protect signal - 12 - 1 - read-write - - - MISO_O - Output value for the SPI MISO signal - 11 - 1 - read-write - - - MOSI_O - Output value for the SPI MOSI signal - 10 - 1 - read-write - - - SCLK_O - Output value for the SPI SCLK signal - 9 - 1 - read-write - - - CS_O - Output value for the SPI CS (chip select) signal - 8 - 1 - read-write - - - HOLD_I - Status of the SPI Flash hold signal - 5 - 1 - read-only - - - WP_I - Status of the SPI Flash write protect signal - 4 - 1 - read-only - - - MISO_I - Status of the SPI MISO signal - 3 - 1 - read-only - - - MOSI_I - Status of the SPI MOSI signal - 2 - 1 - read-only - - - SCLK_I - Status of the SPI SCLK signal - 1 - 1 - read-only - - - CS_I - Status of the SPI CS (chip select) signal - 0 - 1 - read-only - - - - - TRANSCTRL - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - CMD - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - ADDR - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - DATA - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - CTRL - Control Register - 0x30 - 32 - 0x00000000 - 0x00FFFF1F - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - STATUS - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - INTREN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - INTRST - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - read-write - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - read-write - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - read-write - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - read-write - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - read-write - - - - - TIMING - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SLVST - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - read-write - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SLVDATACNT - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - CONFIG - Configuration Register - 0x7c - 32 - 0x00004311 - 0x00004BFF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - DIRECTIO - Support for Direct SPI IO - 11 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0034000 - - - SPI2 - SPI2 - SPI - 0xf0038000 - - - SPI3 - SPI3 - SPI - 0xf003c000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x10 - 0x2c - registers - - - - CFG - Configuration Register - 0x10 - 32 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 2 - 30 - read-write - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: The over-sample ratio is 32 -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - 0x24 - 32 - 0x00000000 - 0x0000000F - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - 0x28 - 32 - 0x00000001 - 0x000000CF - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - PUART - PUART - UART - 0xf40e4000 - - - CAN0 - CAN0 - CAN - 0xf0080000 - - 0x0 - 0xca - registers - - - - RBUF_BUF0 - receive buffer registers and reception time stamp - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF1 - receive buffer registers and reception time stamp - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF2 - receive buffer registers and reception time stamp - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF3 - receive buffer registers and reception time stamp - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF4 - receive buffer registers and reception time stamp - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF5 - receive buffer registers and reception time stamp - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF6 - receive buffer registers and reception time stamp - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF7 - receive buffer registers and reception time stamp - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF8 - receive buffer registers and reception time stamp - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF9 - receive buffer registers and reception time stamp - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF10 - receive buffer registers and reception time stamp - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF11 - receive buffer registers and reception time stamp - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF12 - receive buffer registers and reception time stamp - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF13 - receive buffer registers and reception time stamp - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF14 - receive buffer registers and reception time stamp - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF15 - receive buffer registers and reception time stamp - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF16 - receive buffer registers and reception time stamp - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF17 - receive buffer registers and reception time stamp - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF18 - receive buffer registers and reception time stamp - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF19 - receive buffer registers and reception time stamp - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - TBUF_BUF0 - transmit buffer register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF1 - transmit buffer register - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF2 - transmit buffer register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF3 - transmit buffer register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF4 - transmit buffer register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF5 - transmit buffer register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF6 - transmit buffer register - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF7 - transmit buffer register - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF8 - transmit buffer register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF9 - transmit buffer register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF10 - transmit buffer register - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF11 - transmit buffer register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF12 - transmit buffer register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF13 - transmit buffer register - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF14 - transmit buffer register - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF15 - transmit buffer register - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF16 - transmit buffer register - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF17 - transmit buffer register - 0x94 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TTS_WRD0 - transmission time stamp, LSB 32bit - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - TTS_WRD1 - transmission time stamp, MSB 32bit - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - CMD_STA_CMD_CTRL - config, status, command and control bits - 0xa0 - 32 - 0x00900080 - 0xFBF3FFFF - - - SACK - Self-ACKnowledge -0 – no self-ACK -1 – self-ACK when LBME=1 - 31 - 1 - read-write - - - ROM - Receive buffer Overflow Mode -In case of a full RBUF when a new message is received, then ROM selects the following: -1 – The new message will not be stored. -0 – The oldest message will be overwritten. - 30 - 1 - read-write - - - ROV - Receive buffer OVerflow -1 – Overflow. At least one message is lost. -0 – No Overflow. -ROV is cleared by setting RREL=1. - 29 - 1 - read-only - - - RREL - Receive buffer RELease -The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL -core points to the next RB slot. RSTAT gets updated. -1 – Release: The host has read the RB. -0 – No release - 28 - 1 - read-write - - - RBALL - Receive Buffer stores ALL data frames -0 – normal operation -1 – RB stores correct data frames as well as data frames with error - 27 - 1 - read-write - - - RSTAT - Receive buffer STATus -00 - empty -01 - > empty and < almost full (AFWL) -10 -  almost full (programmable threshold by AFWL) but not full and no overflow -11 - full (stays set in case of overflow – for overflow signaling see ROV) - 24 - 2 - read-only - - - FD_ISO - CAN FD ISO mode -0 - Bosch CAN FD (non-ISO) mode -1 - ISO CAN FD mode (ISO 11898-1:2015) -ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. -Both modes are incompatible and must not be mixed in one CAN network. -This bit has no impact to CAN 2.0B. -This bit is only writeable if RESET=1. - 23 - 1 - read-write - - - TSNEXT - Transmit buffer Secondary NEXT -0 - no action -1 - STB slot filled, select next slot. -After all frame bytes are written to the TBUF registers, the host controller has to set -TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF -registers to the next slot. Once a slot is marked as filled a transmission can be started -using TSONE or TSALL. -It is possible to set TSNEXT and TSONE or TSALL together in one write access. -TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL -core immediately after it was set. -Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and -automatically cleared. It does not do any harm. -If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. -TSNEXT has no meaning in TTCAN mode and is fixed to 0. - 22 - 1 - read-write - - - TSMODE - Transmit buffer Secondary operation MODE -0 - FIFO mode -1 - priority decision mode -In FIFO mode frames are transmitted in the order in that they are written into the STB. -In priority decision mode the frame with the highest priority in the STB is automatically -transmitted first. The ID of a frame is used for the priority decision. A lower ID means a -higher priority of a frame. A frame in the PTB has always the highest priority regardless of -the ID. -TSMODE shall be switched only if the STB if empty - 21 - 1 - read-write - - - TTTBM - TTCAN Transmit Buffer Mode -If TTEN=0 then TTTBM is ignored, otherwise the following is valid: -0 - separate PTB and STB, behavior defined by TSMODE -1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR -For event-driven CAN communication (TTEN=0), the system provides PTB and STB and -the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. -For time-triggered CAN communication (TTEN=1) with full support of all features including -time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are -addressable using TTPTR and TBPTR. -For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode -and the behavior can be selected by TSMODE. -TTTBM shall be switched only if the TBUF is empty. - 20 - 1 - read-write - - - TSSTAT - Transmission Secondary STATus bits -If TTEN=0 or TTTBM=0: -00 – STB is empty -01 – STB is less than or equal to half full -10 – STB is more than half full -11 – STB is full -If the STB is disabled using STB_DISABLE, then TSSTAT=00. -If TTEN=1 and TTTBM=1: -00 – PTB and STB are empty -01 – PTB and STB are not empty and not full -11 – PTB and STB are full - 16 - 2 - read-only - - - TBSEL - Transmit Buffer Select -Selects the transmit buffer to be loaded with a message. Use the TBUF registers for -access. TBSEL needs to be stable all the time the TBUF registers are written and when -TSNEXT is set. -0 - PTB (high-priority buffer) -1 - STB -The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - 15 - 1 - read-write - - - LOM - Listen Only Mode -0 - Disabled -1 - Enabled -LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM -is enabled and LBME is disabled. -LOM=1 and LBME=0 disables all transmissions. -LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables -the transmission of own frames. - 14 - 1 - read-write - - - STBY - Transceiver Standby Mode -0 - Disabled -1 - Enabled -This register bit is connected to the output signal stby which can be used to control a -standby mode of a transceiver. -STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. -If the host sets STBY to 0 then the host needs to wait for the time required by the -transceiver to start up before the host requests a new transmission. - 13 - 1 - read-write - - - TPE - Transmit Primary Enable -1 - Transmission enable for the message in the high-priority PTB -0 - No transmission for the PTB -If TPE is set, the message from the PTB will be transmitted at the next possible transmit -position. A started transmission from the STB will be completed before, but pending new -messages are delayed until the PTB message has been transmitted. -TPE stays set until the message has been transmitted successfully or it is aborted using -TPA. -The host controller can set TPE to 1 but can not reset it to 0. This would only be possible -using TPA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 12 - 1 - read-write - - - TPA - Transmit Primary Abort -1 – Aborts a transmission from PTB which has been requested by TPE=1 but not -started yet. (The data bytes of the message remains in the PTB.) -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA -automatically de-asserts TPE. -The host controller can set TPA to 1 but can not reset it to 0. -During the short time while the CAN-CTRL core resets the bit, it cannot be set by the -host. -The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). -TPA should not be set simultaneously with TPE. - 11 - 1 - read-write - - - TSONE - Transmit Secondary ONE frame -1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message -and in priority mode this is the one with the highest priority. -TSONE in priority mode is difficult to handle, because it is not always clear which -message will be transmitted if new messages are written to the STB meanwhile. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSONE stays set until the message has been transmitted successfully or it is aborted -using TSA. -The host controller can set TSONE to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 10 - 1 - read-write - - - TSALL - Transmit Secondary ALL frames -1 – Transmission enable of all messages in the STB. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSALL stays set until all messages have been transmitted successfully or they are aborted -using TSA. -The host controller can set TSALL to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the messages. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). -If during a transmission the STB is loaded with a new frame then the new frame will be -transmitted too. In other words: a transmission initiated by TSALL is finished when the -STB becomes empty. - 9 - 1 - read-write - - - TSA - Transmit Secondary Abort -1 – Aborts a transmission from STB which has been requested but not started yet. -For a TSONE transmission, only one frame is aborted while for a TSALL -Transmission, all frames are aborted. -One or all message slots will be released which updates TSSTAT. -All aborted messages are lost because they are not accessible any more. -If in priority mode a TSONE transmission is aborted, then it is not clear which -frame will be aborted if new frames are written to the STB meanwhile. -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. -The host controller can set TSA to 1 but can not reset it to 0. -The bit will be reset to the hardware reset value if RESET=1. -TSA should not be set simultaneously with TSONE or TSALL. - 8 - 1 - read-write - - - RESET - RESET request bit -1 - The host controller performs a local reset of CAN-CTRL. -0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. -Bit RESET forces several components to a reset state. -RESET is automatically set if the node enters “bus off” state. -Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. -This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. -The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - 7 - 1 - read-write - - - LBME - Loop Back Mode, External -0 - Disabled -1 - EnabledLBME should not be enabled while a transmission is active - 6 - 1 - read-write - - - LBMI - Loop Back Mode, Internal -0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - 5 - 1 - read-write - - - TPSS - Transmission Primary Single Shot mode for PTB -0 - Disabled -1 - Enabled - 4 - 1 - read-write - - - TSSS - Transmission Secondary Single Shot mode for STB -0 - Disabled -1 - Enabled - 3 - 1 - read-write - - - RACTIVE - Reception ACTIVE (Receive Status bit) -1 - The controller is currently receiving a frame. -0 - No receive activity. - 2 - 1 - read-only - - - TACTIVE - Transmission ACTIVE (Transmit Status bit) -1 - The controller is currently transmitting a frame. -0 - No transmit activity. - 1 - 1 - read-only - - - BUSOFF - Bus Off (Bus Status bit) -1 - The controller status is “bus off”. -0 - The controller status is “bus on”. -Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. -See Chapter 3.9.10.6 for details. - 0 - 1 - read-write - - - - - RTIE - Receive and Transmit Interrupt Enable Register RTIE - 0xa4 - 8 - 0xFE - 0xFF - - - RIE - Receive Interrupt Enable -0 – Disabled, 1 – Enabled - 7 - 1 - read-write - - - ROIE - RB Overrun Interrupt Enable -0 – Disabled, 1 – Enabled - 6 - 1 - read-write - - - RFIE - RB Full Interrupt Enable -0 – Disabled, 1 – Enabled - 5 - 1 - read-write - - - RAFIE - RB Almost Full Interrupt Enable -0 – Disabled, 1 – Enabled - 4 - 1 - read-write - - - TPIE - Transmission Primary Interrupt Enable -0 – Disabled, 1 – Enabled - 3 - 1 - read-write - - - TSIE - Transmission Secondary Interrupt Enable -0 – Disabled, 1 – Enabled - 2 - 1 - read-write - - - EIE - Error Interrupt Enable -0 – Disabled, 1 – Enabled - 1 - 1 - read-write - - - TSFF - If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag -1 - The STB is filled with the maximal number of messages. -0 - The STB is not filled with the maximal number of messages. -If the STB is disabled using STB_DISABLE, then TSFF=0. -If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag -1 - The buffer slot selected by TBPTR is filled. -0 - The buffer slot selected by TBPTR is empty. - 0 - 1 - read-only - - - - - RTIF - Receive and Transmit Interrupt Flag Register RTIF (0xa5) - 0xa5 - 8 - 0x00 - 0xFF - - - RIF - Receive Interrupt Flag -1 - Data or a remote frame has been received and is available in the receive buffer. -0 - No frame has been received. - 7 - 1 - read-write - - - ROIF - RB Overrun Interrupt Flag -1 - At least one received message has been overwritten in the RB. -0 - No RB overwritten. -In case of an overrun both ROIF and RFIF will be set. - 6 - 1 - read-write - - - RFIF - RB Full Interrupt Flag -1 - All RBs are full. If no RB will be released until the next valid message is received, -the oldest message will be lost. -0 - The RB FIFO is not full. - 5 - 1 - read-write - - - RAFIF - RB Almost Full Interrupt Flag -1 - number of filled RB slots >= AFWL_i -0 - number of filled RB slots < AFWL_i - 4 - 1 - read-write - - - TPIF - Transmission Primary Interrupt Flag -1 - The requested transmission of the PTB has been successfully completed. -0 - No transmission of the PTB has been completed. -In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - 3 - 1 - read-write - - - TSIF - Transmission Secondary Interrupt Flag -1 - The requested transmission of the STB has been successfully completed. -0 - No transmission of the STB has been completed successfully. -In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of -the message. - 2 - 1 - read-write - - - EIF - Error Interrupt Flag -1 - The border of the error warning limit has been crossed in either direction, -or the BUSOFF bit has been changed in either direction. -0 - There has been no change. - 1 - 1 - read-write - - - AIF - Abort Interrupt Flag -1 - After setting TPA or TSA the appropriated message(s) have been aborted. -It is recommended to not set both TPA and TSA simultaneously because both -source AIF. -0 - No abort has been executed. -The AIF does not have an associated enable register. - 0 - 1 - read-write - - - - - ERRINT - ERRor INTerrupt Enable and Flag Register ERRINT - 0xa6 - 8 - 0x00 - 0xFF - - - EWARN - Error WARNing limit reached -1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - 7 - 1 - read-only - - - EPASS - Error Passive mode active -0 - not active (node is error active) -1 - active (node is error passive) - 6 - 1 - read-only - - - EPIE - Error Passive Interrupt Enable - 5 - 1 - read-write - - - EPIF - Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error -active to error passive or vice versa and if this interrupt is enabled. - 4 - 1 - read-write - - - ALIE - Arbitration Lost Interrupt Enable - 3 - 1 - read-write - - - ALIF - Arbitration Lost Interrupt Flag - 2 - 1 - read-write - - - BEIE - Bus Error Interrupt Enable - 1 - 1 - read-write - - - BEIF - Bus Error Interrupt Flag - 0 - 1 - read-write - - - - - LIMIT - Warning Limits Register LIMIT - 0xa7 - 8 - 0x1B - 0xFF - - - AFWL - receive buffer Almost Full Warning Limit -AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. -AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . -AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) -AFWL_i > nRB is meaningless and automatically treated as nRB. -AFWL_i = nRB is a valid value, but note that RFIF also exists. - 4 - 4 - read-write - - - EWL - Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. -The value of EWL controls EIF. - 0 - 4 - read-write - - - - - S_PRESC - Bit Timing Register(Slow Speed) - 0xa8 - 32 - 0x01020203 - 0xFF7F7FFF - - - S_PRESC - Prescaler (slow speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - S_SJW - Synchronization Jump Width (slow speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 7 - read-write - - - S_SEG_2 - Bit Timing Segment 2 (slow speed) -Time after the sample point. - 8 - 7 - read-write - - - S_SEG_1 - Bit Timing Segment 1 (slow speed) -The sample point will be set to after start of bit time. - 0 - 8 - read-write - - - - - F_PRESC - Bit Timing Register(Fast Speed) - 0xac - 32 - 0x01020203 - 0xFF0F0F0F - - - F_PRESC - Prescaler (fast speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - F_SJW - Synchronization Jump Width (fast speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 4 - read-write - - - F_SEG_2 - Bit Timing Segment 2 (fast speed) -Time after the sample point - 8 - 4 - read-write - - - F_SEG_1 - Bit Timing Segment 1 (fast speed) -The sample point will be set to after start of bit time. - 0 - 4 - read-write - - - - - EALCAP - Error and Arbitration Lost Capture Register EALCAP - 0xb0 - 8 - 0x00 - 0xFF - - - KOER - Kind Of ERror (Error code) -000 - no error -001 - BIT ERROR -010 - FORM ERROR -011 - STUFF ERROR -100 - ACKNOWLEDGEMENT ERROR -101 - CRC ERROR -110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) -111 - not used -KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - 5 - 3 - read-only - - - ALC - Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - 0 - 5 - read-only - - - - - TDC - Transmitter Delay Compensation Register TDC - 0xb1 - 8 - 0x00 - 0xFF - - - TDCEN - Transmitter Delay Compensation ENable -TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - 7 - 1 - read-write - - - SSPOFF - Secondary Sample Point OFFset -The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. -SSPOFF is given as a number of TQ. - 0 - 7 - read-write - - - - - RECNT - Error Counter Registers RECNT - 0xb2 - 8 - 0x00 - 0xFF - - - RECNT - Receive Error CouNT (number of errors during reception) -RECNT is incremented and decremented as defined in the CAN specification. -RECNT does not overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - TECNT - Error Counter Registers TECNT - 0xb3 - 8 - 0x00 - 0xFF - - - TECNT - Transmit Error CouNT (number of errors during transmission) -TECNT is incremented and decremented as defined in the CAN specification. -In case of the “bus off state” TECNT may overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - ACFCTRL - Acceptance Filter Control Register ACFCTRL - 0xb4 - 8 - 0x00 - 0x2F - - - SELMASK - SELect acceptance MASK -0 - Registers ACF_x point to acceptance code -1 - Registers ACF_x point to acceptance mask. -ACFADR selects one specific acceptance filter. - 5 - 1 - read-write - - - ACFADR - acceptance filter address -ACFADR points to a specific acceptance filter. -The selected filter is accessible using theregisters ACF_x. -Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. -A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. -ACF_NUMBER = 16. - 0 - 4 - read-write - - - - - TIMECFG - CiA 603 Time-Stamping TIMECFG - 0xb5 - 8 - 0x00 - 0x03 - - - TIMEPOS - TIME-stamping POSition -0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - 1 - 1 - read-write - - - TIMEEN - TIME-stamping ENable -0 – disabled -1 – enabled - 0 - 1 - read-write - - - - - ACF_EN - Acceptance Filter Enable ACF_EN - 0xb6 - 16 - 0x0000 - 0xFFFF - - - ACF_EN - Acceptance filter Enable -1 - acceptance filter enabled -0 - acceptance filter disable -Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. -Disabled filters reject a message. Only enabled filters can accept a message if the -appropriate AMASK / ACODE configuration matches. - 0 - 16 - read-write - - - - - ACF - Acceptance CODE ACODE or ACMASK - 0xb8 - 32 - 0x00000000 - 0x7FFFFFFF - - - AIDEE - Acceptance mask IDE bit check enable -1 - acceptance filter accepts either standard or extended as defined by AIDE -0 - acceptance filter accepts both standard or extended frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 30 - 1 - read-write - - - AIDE - Acceptance mask IDE bit value -If AIDEE=1 then: -1 - acceptance filter accepts only extended frames -0 - acceptance filter accepts only standard frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 29 - 1 - read-write - - - CODE_MASK - Acceptance CODE -1 - ACC bit value to compare with ID bit of the received message -0 - ACC bit value to compare with ID bit of the received message -ACODE_x(10:0) will be used for extended frames. -ACODE_x(28:0) will be used for extended frames. -Only filter 0 is affected by the power-on reset. -Acceptance MASK(if SELMASK ==1 ) -1 - acceptance check for these bits of receive identifier disabled -0 - acceptance check for these bits of receive identifier enable -AMASK_x(10:0) will be used for extended frames. -AMASK_x(28:0) will be used for extended frames. -Disabled bits result in accepting the message. Therefore the default configuration after -reset for filter 0 accepts all messages. -Only filter 0 is affected by the power-on reset. - 0 - 29 - read-write - - - - - VER - Version Information VER - 0xbc - 16 - 0x0000 - 0xFFFF - - - VERSION - Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and -VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - 0 - 16 - read-write - - - - - TBSLOT - TTCAN: TB Slot Pointer TBSLOT - 0xbe - 8 - 0x00 - 0xFF - - - TBE - set TB slot to “Empty” -1 - slot selected by TBPTR shall be marked as “empty” -0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. -If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - transmissionis not active any more. -If both TBF and TBE are set, then TBE wins - 7 - 1 - read-write - - - TBF - set TB slot to “Filled” -1 - slot selected by TBPTR shall be marked as “filled” -0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. -If both TBF and TBE are set, then TBE wins. - 6 - 1 - read-write - - - TBPTR - Pointer to a TB message slot. -0x00 - Pointer to the PTB -others - Pointer to a slot in the STB -The message slot pointed to by TBPTR is readable / writable using the TBUF registers. -Write access is only possible if TSFF=0. -Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. -TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. -TBPTR can only point to buffer slots, that exist in the hardware. -Unusable bits ofTBPTR are fixed to 0. -TBPTR is limited to the PTB and 63 STB slots. - More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - 0 - 6 - read-write - - - - - TTCFG - TTCAN: Time Trigger Configuration TTCFG - 0xbf - 8 - 0x00 - 0xFF - - - WTIE - Watch Trigger Interrupt Enable - 7 - 1 - read-write - - - WTIF - Watch Trigger Interrupt Flag -WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - 6 - 1 - read-write - - - TEIF - Trigger Error Interrupt Flag -The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - 5 - 1 - read-write - - - TTIE - Time Trigger Interrupt Enable -If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - 4 - 1 - read-write - - - TTIF - Time Trigger Interrupt Flag -TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. -Writing an one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. -If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - 3 - 1 - read-write - - - T_PRESC - TTCAN Timer PRESCaler -00b - 1 -01b - 2 -10b - 4 -11b - 8 -The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. -T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - 1 - 2 - read-write - - - TTEN - Time Trigger Enable -1 - TTCAN enabled, timer is running0 - disabled - 0 - 1 - read-write - - - - - REF_MSG - TTCAN: Reference Message REF_MSG - 0xc0 - 32 - 0x00000000 - 0x9FFFFFFF - - - REF_IDE - REFerence message IDE bit. - 31 - 1 - read-write - - - REF_MSG - REFerence message IDentifier. -If REF_IDE is -1 - REF_ID(28:0) is valid (extended ID) -0 - REF_ID(10:0) is valid (standard ID) -REF_ID is used in TTCAN mode to detect a reference message. This holds for time -slaves (reception) as well as for the time master (transmission). If the reference -message is detected and there are no errors, then the Sync_Mark of this frame will -become the Ref_Mark. -REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. -These bits are used for up to 8 potential time masters. -CAN-CTRL recognizes the reference message only by ID. The payload is not tested. -Additional note: A time master will transmit a reference message in the same way as a -normal frame. REF_ID is intended for detection of a successful transmission of a -reference message. - 0 - 29 - read-write - - - - - TRIG_CFG - TTCAN: Trigger Configuration TRIG_CFG - 0xc4 - 16 - 0x0000 - 0xF73F - - - TEW - Transmit Enable Window -For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time -where the frame is allowed to start. TWE+1 defines the number of ticks. -TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - 12 - 4 - read-write - - - TTYPE - Trigger Type -000b - Immediate Trigger for immediate transmission -001b - Time Trigger for receive triggers -010b - Single Shot Transmit Trigger for exclusive time windows -011b - Transmit Start Trigger for merged arbitrating time windows -100b - Transmit Stop Trigger for merged arbitrating time windows -others - no action -The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the -transmit triggers. See Chapter 6.4 for more details. - 8 - 3 - read-write - - - TTPTR - Transmit Trigger TB slot Pointer -If TTPTR is too big and points to a slot that is not available, then TEIF is set and no -new trigger can be activated after a write access to TT_TRIG_1. -If TTPTR points to an empty slot, then TEIF will be set at the moment, when the -trigger time is reached. - 0 - 6 - read-write - - - - - TT_TRIG - TTCAN: Trigger Time TT_TRIG - 0xc6 - 16 - 0x0000 - 0xFFFF - - - TT_TRIG - Trigger Time -TT_TRIG(15:0) defines the cycle time for a trigger. -For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - 0 - 16 - read-write - - - - - TT_WTRIG - TTCAN: Watch Trigger Time TT_WTRIG - 0xc8 - 16 - 0x0000 - 0xFFFF - - - TT_WTRIG - Watch Trigger Time -TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - 0 - 16 - read-write - - - - - - - CAN1 - CAN1 - CAN - 0xf0084000 - - - WDG0 - WDG0 - WDOG - 0xf0090000 - - 0x10 - 0x10 - registers - - - - CTRL - Control Register - 0x10 - 32 - 0x00000000 - 0x000007FF - - - RSTTIME - The time interval of the reset stage: -0: Clock period x 2^7 -1: Clock period x 2^8 -2: Clock period x 2^9 -3: Clock period x 2^10 -4: Clock period x 2^11 -5: Clock period x 2^12 -6: Clock period x 2^13 -7: Clock period x 2^14 - 8 - 3 - read-write - - - INTTIME - The timer interval of the interrupt stage: -0: Clock period x 2^6 -1: Clock period x 2^8 -2: Clock period x 2^10 -3: Clock period x 2^11 -4: Clock period x 2^12 -5: Clock period x 2^13 -6: Clock period x 2^14 -7: Clock period x 2^15 -8: Clock period x 2^17 -9: Clock period x 2^19 -10: Clock period x 2^21 -11: Clock period x 2^23 -12: Clock period x 2^25 -13: Clock period x 2^27 -14: Clock period x 2^29 -15: Clock period x 2^31 - 4 - 4 - read-write - - - RSTEN - Enable or disable the watchdog reset -0: Disable -1: Enable - 3 - 1 - read-write - - - INTEN - Enable or disable the watchdog interrupt -0: Disable -1: Enable - 2 - 1 - read-write - - - CLKSEL - Clock source of timer: -0: EXTCLK -1: PCLK - 1 - 1 - read-write - - - EN - Enable or disable the watchdog timer -0: Disable -1: Enable - 0 - 1 - read-write - - - - - RESTART - Restart Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - RESTART - Write the magic number -ATCWDT200_RESTART_NUM to restart the -watchdog timer. - 0 - 16 - write-only - - - - - WREN - Write Protection Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - WEN - Write the magic code to disable the write -protection of the Control Register and the -Restart Register. - 0 - 16 - write-only - - - - - ST - Status Register - 0x1c - 32 - 0x00000000 - 0x00000001 - - - INTEXPIRED - The status of the watchdog interrupt timer -0: timer is not expired yet -1: timer is expired - 0 - 1 - read-write - - - - - - - WDG1 - WDG1 - WDOG - 0xf0094000 - - - PWDG - PWDG - WDOG - 0xf40e8000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - RESERVED - Reserved - 16 - 15 - read-only - - - BARCTL - Bus Acccess Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - RESERVED - Reserved - 9 - 5 - read-only - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - RESERVED - Reserved - 2 - 2 - read-only - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RESERVED - Not used - 24 - 8 - read-only - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - read-write - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - read-write - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - read-write - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - read-write - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - read-write - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - read-write - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - RESERVED - Not used - 2 - 2 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - TXWRD_TXFIFO0 - TXFIFO for sending message to other core - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - RXWRD_RXFIFO0 - RXFIFO for receiving message from other core - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - PTPC - PTPC - PTPC - 0xf00b0000 - - 0x0 - 0x200c - registers - - - - PTPC_0_CTRL0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description avaiable - 6 - 1 - read-write - - - RESERVED - No description avaiable - 5 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow -1: coarse update, ns counter add ss_incr[7:0] each clk - 1 - 1 - read-write - - - TIMER_ENABLE - No description avaiable - 0 - 1 - read-write - - - - - PTPC_0_CTRL1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - PTPC_0_TIMEH - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description avaiable - 0 - 32 - read-only - - - - - PTPC_0_TIMEL - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description avaiable - 0 - 32 - read-only - - - - - PTPC_0_TS_UPDTH - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - PTPC_0_TS_UPDTL - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description avaiable - 0 - 31 - read-write - - - - - PTPC_0_ADDEND - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - PTPC_0_TARH - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - PTPC_0_TARL - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description avaiable - 0 - 32 - read-write - - - - - PTPC_0_PPS_CTRL - No description avaiable - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description avaiable - 0 - 4 - read-write - - - - - PTPC_0_CAPT_SNAPH - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - PTPC_0_CAPT_SNAPL - No description avaiable - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description avaiable - 0 - 32 - read-write - - - - - PTPC_1_CTRL0 - Control Register 0 - 0x1000 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description avaiable - 6 - 1 - read-write - - - RESERVED - No description avaiable - 5 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow -1: coarse update, ns counter add ss_incr[7:0] each clk - 1 - 1 - read-write - - - TIMER_ENABLE - No description avaiable - 0 - 1 - read-write - - - - - PTPC_1_CTRL1 - Control Register 1 - 0x1004 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - PTPC_1_TIMEH - timestamp high - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description avaiable - 0 - 32 - read-only - - - - - PTPC_1_TIMEL - timestamp low - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description avaiable - 0 - 32 - read-only - - - - - PTPC_1_TS_UPDTH - timestamp update high - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - PTPC_1_TS_UPDTL - timestamp update low - 0x1014 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description avaiable - 0 - 31 - read-write - - - - - PTPC_1_ADDEND - No description avaiable - 0x1018 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - PTPC_1_TARH - No description avaiable - 0x101c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - PTPC_1_TARL - No description avaiable - 0x1020 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description avaiable - 0 - 32 - read-write - - - - - PTPC_1_PPS_CTRL - No description avaiable - 0x102c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description avaiable - 0 - 4 - read-write - - - - - PTPC_1_CAPT_SNAPH - No description avaiable - 0x1030 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - PTPC_1_CAPT_SNAPL - No description avaiable - 0x1034 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description avaiable - 0 - 32 - read-write - - - - - TIME_SEL - No description avaiable - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description avaiable - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description avaiable - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description avaiable - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - INT_STS - No description avaiable - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description avaiable - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description avaiable - 17 - 1 - read-write - - - PPS_INT_STS1 - No description avaiable - 16 - 1 - read-write - - - COMP_INT_STS0 - No description avaiable - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description avaiable - 1 - 1 - read-write - - - PPS_INT_STS0 - No description avaiable - 0 - 1 - read-write - - - - - INT_EN - No description avaiable - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description avaiable - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description avaiable - 17 - 1 - read-write - - - PPS_INT_STS1 - No description avaiable - 16 - 1 - read-write - - - COMP_INT_STS0 - No description avaiable - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description avaiable - 1 - 1 - read-write - - - PPS_INT_STS0 - No description avaiable - 0 - 1 - read-write - - - - - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c0000 - - 0x0 - 0x40 - registers - - - - MUXCFG_HDMA_MUX0 - HDMA MUX0 Configuration - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX1 - HDMA MUX1 Configuration - 0x4 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX2 - HDMA MUX2 Configuration - 0x8 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX3 - HDMA MUX3 Configuration - 0xc - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX4 - HDMA MUX4 Configuration - 0x10 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX5 - HDMA MUX5 Configuration - 0x14 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX6 - HDMA MUX6 Configuration - 0x18 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX7 - HDMA MUX7 Configuration - 0x1c - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX0 - XDMA MUX0 Configuration - 0x20 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX1 - XDMA MUX1 Configuration - 0x24 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX2 - XDMA MUX2 Configuration - 0x28 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX3 - XDMA MUX3 Configuration - 0x2c - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX4 - XDMA MUX4 Configuration - 0x30 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX5 - XDMA MUX5 Configuration - 0x34 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX6 - XDMA MUX6 Configuration - 0x38 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX7 - XDMA MUX7 Configuration - 0x3c - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMA - 0xf00c4000 - - 0x10 - 0x15c - registers - - - - DMACFG - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACTRL - DMAC Control Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - CHABORT - Channel Abort Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - INTSTATUS - Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0x00FFFFFF - - - TC - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 16 - 8 - read-write - - - ABORT - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 8 - 8 - read-write - - - ERROR - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 8 - read-write - - - - - CHEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - CHCTRL_CH0_CTRL - Channel n Control Register - 0x40 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH0_TRANSIZE - Channel n Transfer Size Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH0_SRCADDR - Channel n Source Address Low Part Register - 0x48 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH0_SRCADDRH - Channel n Source Address High Part Register - 0x4c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH0_DSTADDR - Channel n Destination Address Low Part Register - 0x50 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH0_DSTADDRH - Channel n Destination Address High Part Register - 0x54 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH0_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x58 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH0_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH1_CTRL - Channel n Control Register - 0x60 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH1_TRANSIZE - Channel n Transfer Size Register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH1_SRCADDR - Channel n Source Address Low Part Register - 0x68 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH1_SRCADDRH - Channel n Source Address High Part Register - 0x6c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH1_DSTADDR - Channel n Destination Address Low Part Register - 0x70 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH1_DSTADDRH - Channel n Destination Address High Part Register - 0x74 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH1_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x78 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH1_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH2_CTRL - Channel n Control Register - 0x80 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH2_TRANSIZE - Channel n Transfer Size Register - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH2_SRCADDR - Channel n Source Address Low Part Register - 0x88 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH2_SRCADDRH - Channel n Source Address High Part Register - 0x8c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH2_DSTADDR - Channel n Destination Address Low Part Register - 0x90 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH2_DSTADDRH - Channel n Destination Address High Part Register - 0x94 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH2_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x98 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH2_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH3_CTRL - Channel n Control Register - 0xa0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH3_TRANSIZE - Channel n Transfer Size Register - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH3_SRCADDR - Channel n Source Address Low Part Register - 0xa8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH3_SRCADDRH - Channel n Source Address High Part Register - 0xac - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH3_DSTADDR - Channel n Destination Address Low Part Register - 0xb0 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH3_DSTADDRH - Channel n Destination Address High Part Register - 0xb4 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH3_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0xb8 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH3_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH4_CTRL - Channel n Control Register - 0xc0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH4_TRANSIZE - Channel n Transfer Size Register - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH4_SRCADDR - Channel n Source Address Low Part Register - 0xc8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH4_SRCADDRH - Channel n Source Address High Part Register - 0xcc - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH4_DSTADDR - Channel n Destination Address Low Part Register - 0xd0 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH4_DSTADDRH - Channel n Destination Address High Part Register - 0xd4 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH4_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0xd8 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH4_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH5_CTRL - Channel n Control Register - 0xe0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH5_TRANSIZE - Channel n Transfer Size Register - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH5_SRCADDR - Channel n Source Address Low Part Register - 0xe8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH5_SRCADDRH - Channel n Source Address High Part Register - 0xec - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH5_DSTADDR - Channel n Destination Address Low Part Register - 0xf0 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH5_DSTADDRH - Channel n Destination Address High Part Register - 0xf4 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH5_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0xf8 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH5_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH6_CTRL - Channel n Control Register - 0x100 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH6_TRANSIZE - Channel n Transfer Size Register - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH6_SRCADDR - Channel n Source Address Low Part Register - 0x108 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH6_SRCADDRH - Channel n Source Address High Part Register - 0x10c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH6_DSTADDR - Channel n Destination Address Low Part Register - 0x110 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH6_DSTADDRH - Channel n Destination Address High Part Register - 0x114 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH6_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x118 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH6_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH7_CTRL - Channel n Control Register - 0x120 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH7_TRANSIZE - Channel n Transfer Size Register - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH7_SRCADDR - Channel n Source Address Low Part Register - 0x128 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH7_SRCADDRH - Channel n Source Address High Part Register - 0x12c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH7_DSTADDR - Channel n Destination Address Low Part Register - 0x130 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH7_DSTADDRH - Channel n Destination Address High Part Register - 0x134 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH7_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x138 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH7_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - - - XDMA - XDMA - DMA - 0xf3048000 - - - RNG - RNG - RNG - 0xf00c8000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 7 - 25 - read-write - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - RESERVED - Not used - 2 - 2 - read-only - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 7 - 25 - read-only - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - RESERVED - Not used - 2 - 2 - read-only - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 24 - 8 - read-only - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - RESERVED - Not used - 17 - 4 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - RESERVED - Not used - 7 - 1 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - RESERVED - Not used - 0 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - RESERVED - OSC1 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 24 - 8 - read-only - - - RESERVED - OSC0 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - RESERVED - Statistical test error -Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is -cleared by a hardware or software reset or by writing 1 to the CMD[CE]. -0 No fail for the statistical tests. -1 Failed the statistical tests during the initialization - 4 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 2 - 1 - read-only - - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 1 - 1 - read-only - - - RESERVED - Linear feedback shift register (LFSR) error -When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. - 0 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - R2SK_FO2S0 - FIFO out to SDP as AES engine key - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S1 - FIFO out to SDP as AES engine key - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S2 - FIFO out to SDP as AES engine key - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S3 - FIFO out to SDP as AES engine key - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S4 - FIFO out to SDP as AES engine key - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S5 - FIFO out to SDP as AES engine key - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S6 - FIFO out to SDP as AES engine key - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S7 - FIFO out to SDP as AES engine key - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf00cc000 - - 0x0 - 0x50 - registers - - - - SOFTMKEY_SFK0 - software set symmetric key - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK1 - software set symmetric key - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK2 - software set symmetric key - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK3 - software set symmetric key - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK4 - software set symmetric key - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK5 - software set symmetric key - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK6 - software set symmetric key - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK7 - software set symmetric key - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK0 - system asymmetric key - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK1 - system asymmetric key - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK2 - system asymmetric key - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK3 - system asymmetric key - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK4 - system asymmetric key - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK5 - system asymmetric key - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK6 - system asymmetric key - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK7 - system asymmetric key - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of followings -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of followings -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - I2S0 - I2S0 - I2S - 0xf0100000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 19 - 13 - read-write - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 16 - 16 - read-write - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 17 - 15 - read-only - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - read-write - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - read-write - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - RSV - Reserved - 0 - 1 - read-only - - - - - RXD_DATA0 - Rx Data0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - RXD_DATA1 - Rx Data1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - RXD_DATA2 - Rx Data2 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - RXD_DATA3 - Rx Data3 - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - TXD_DATA0 - Tx Data0 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - TXD_DATA1 - Tx Data1 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - TXD_DATA2 - Tx Data2 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - TXD_DATA3 - Tx Data3 - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - RSV - Reserved - 31 - 1 - read-write - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[3:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -... - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - RSV - Reserved - 14 - 18 - read-write - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - RSV - Reserved - 11 - 1 - read-write - - - RSV - Reserved - 10 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - RXDSLOT_DATA0 - Rx Slots Enable for Rx Data0 - 0x60 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - RXDSLOT_DATA1 - Rx Slots Enable for Rx Data1 - 0x64 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - RXDSLOT_DATA2 - Rx Slots Enable for Rx Data2 - 0x68 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - RXDSLOT_DATA3 - Rx Slots Enable for Rx Data3 - 0x6c - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA0 - Tx Slots Enable for Tx Data0. - 0x70 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA1 - Tx Slots Enable for Tx Data1. - 0x74 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA2 - Tx Slots Enable for Tx Data2. - 0x78 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA3 - Tx Slots Enable for Tx Data3. - 0x7c - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0104000 - - - DAO - DAO - DAO - 0xf0110000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000300FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to comsume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x000007C0 - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0114000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - read-write - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - read-write - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - read-write - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - read-write - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description avaiable - 18 - 2 - read-write - - - CH8_TYPE - No description avaiable - 16 - 2 - read-write - - - CH7_TYPE - No description avaiable - 14 - 2 - read-write - - - CH6_TYPE - No description avaiable - 12 - 2 - read-write - - - CH5_TYPE - No description avaiable - 10 - 2 - read-write - - - CH4_TYPE - No description avaiable - 8 - 2 - read-write - - - CH3_TYPE - No description avaiable - 6 - 2 - read-write - - - CH2_TYPE - No description avaiable - 4 - 2 - read-write - - - CH1_TYPE - No description avaiable - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMADDR - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMDATA - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PWM0 - PWM0 - PWM - 0xf0200000 - - 0x0 - 0x290 - registers - - - - UNLK - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - STA - Counter start register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - RESERVED - reserved - 0 - 4 - read-write - - - - - RLD - Counter reload register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - RESERVED - reserved - 0 - 4 - read-write - - - - - CMP_0 - Comparator register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_1 - Comparator register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_2 - Comparator register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_3 - Comparator register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_4 - Comparator register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_5 - Comparator register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_6 - Comparator register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_7 - Comparator register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_8 - Comparator register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_9 - Comparator register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_10 - Comparator register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_11 - Comparator register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_12 - Comparator register - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_13 - Comparator register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_14 - Comparator register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_15 - Comparator register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_16 - Comparator register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_17 - Comparator register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_18 - Comparator register - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_19 - Comparator register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_20 - Comparator register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_21 - Comparator register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_22 - Comparator register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_23 - Comparator register - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - FRCMD - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0~7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - SHLK - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, wirte access is not permitted - 31 - 1 - read-write - - - - - CHCFG_0 - Output channel configure register - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_1 - Output channel configure register - 0x84 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_2 - Output channel configure register - 0x88 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_3 - Output channel configure register - 0x8c - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_4 - Output channel configure register - 0x90 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_5 - Output channel configure register - 0x94 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_6 - Output channel configure register - 0x98 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_7 - Output channel configure register - 0x9c - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_8 - Output channel configure register - 0xa0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_9 - Output channel configure register - 0xa4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_10 - Output channel configure register - 0xa8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_11 - Output channel configure register - 0xac - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_12 - Output channel configure register - 0xb0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_13 - Output channel configure register - 0xb4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_14 - Output channel configure register - 0xb8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_15 - Output channel configure register - 0xbc - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_16 - Output channel configure register - 0xc0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_17 - Output channel configure register - 0xc4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_18 - Output channel configure register - 0xc8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_19 - Output channel configure register - 0xcc - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_20 - Output channel configure register - 0xd0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_21 - Output channel configure register - 0xd4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_22 - Output channel configure register - 0xd8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_23 - Output channel configure register - 0xdc - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - GCR - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFE7 - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - read-write - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - SHCR - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x00001FFF - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - CAPPOS_0 - Capture rising edge register - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_1 - Capture rising edge register - 0x104 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_2 - Capture rising edge register - 0x108 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_3 - Capture rising edge register - 0x10c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_4 - Capture rising edge register - 0x110 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_5 - Capture rising edge register - 0x114 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_6 - Capture rising edge register - 0x118 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_7 - Capture rising edge register - 0x11c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_8 - Capture rising edge register - 0x120 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_9 - Capture rising edge register - 0x124 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_10 - Capture rising edge register - 0x128 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_11 - Capture rising edge register - 0x12c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_12 - Capture rising edge register - 0x130 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_13 - Capture rising edge register - 0x134 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_14 - Capture rising edge register - 0x138 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_15 - Capture rising edge register - 0x13c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_16 - Capture rising edge register - 0x140 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_17 - Capture rising edge register - 0x144 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_18 - Capture rising edge register - 0x148 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_19 - Capture rising edge register - 0x14c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_20 - Capture rising edge register - 0x150 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_21 - Capture rising edge register - 0x154 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_22 - Capture rising edge register - 0x158 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_23 - Capture rising edge register - 0x15c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CNT - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - RESERVED - read-only as 0 - 0 - 4 - read-only - - - - - CAPNEG_0 - Capture falling edge register - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_1 - Capture falling edge register - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_2 - Capture falling edge register - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_3 - Capture falling edge register - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_4 - Capture falling edge register - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_5 - Capture falling edge register - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_6 - Capture falling edge register - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_7 - Capture falling edge register - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_8 - Capture falling edge register - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_9 - Capture falling edge register - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_10 - Capture falling edge register - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_11 - Capture falling edge register - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_12 - Capture falling edge register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_13 - Capture falling edge register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_14 - Capture falling edge register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_15 - Capture falling edge register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_16 - Capture falling edge register - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_17 - Capture falling edge register - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_18 - Capture falling edge register - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_19 - Capture falling edge register - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_20 - Capture falling edge register - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_21 - Capture falling edge register - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_22 - Capture falling edge register - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_23 - Capture falling edge register - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CNTCOPY - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - RESERVED - read-only as 0 - 0 - 4 - read-only - - - - - PWMCFG_0 - PWM channel configure register - 0x200 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_1 - PWM channel configure register - 0x204 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_2 - PWM channel configure register - 0x208 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_3 - PWM channel configure register - 0x20c - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_4 - PWM channel configure register - 0x210 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_5 - PWM channel configure register - 0x214 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_6 - PWM channel configure register - 0x218 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_7 - PWM channel configure register - 0x21c - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - SR - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - read-write - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - read-write - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - read-write - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - read-write - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - read-write - - - - - IRQEN - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - DMAEN - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - CMPCFG_CMPCFG0 - Comparator configure register - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_1 - Comparator configure register - 0x234 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_2 - Comparator configure register - 0x238 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_3 - Comparator configure register - 0x23c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_4 - Comparator configure register - 0x240 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_5 - Comparator configure register - 0x244 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_6 - Comparator configure register - 0x248 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_7 - Comparator configure register - 0x24c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_8 - Comparator configure register - 0x250 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_9 - Comparator configure register - 0x254 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_10 - Comparator configure register - 0x258 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_11 - Comparator configure register - 0x25c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_12 - Comparator configure register - 0x260 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_13 - Comparator configure register - 0x264 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_14 - Comparator configure register - 0x268 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_15 - Comparator configure register - 0x26c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_16 - Comparator configure register - 0x270 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_17 - Comparator configure register - 0x274 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_18 - Comparator configure register - 0x278 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_19 - Comparator configure register - 0x27c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_20 - Comparator configure register - 0x280 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_21 - Comparator configure register - 0x284 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_22 - Comparator configure register - 0x288 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_23 - Comparator configure register - 0x28c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - - - PWM1 - PWM1 - PWM - 0xf0210000 - - - HALL0 - HALL0 - HALL - 0xf0204000 - - 0x0 - 0x8c - registers - - - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x8001083F - - - READ - 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - RESERVED - reserved - 16 - 1 - read-write - - - SNAPEN - 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - 11 - 1 - read-write - - - RESERVED - reserved - 5 - 1 - read-write - - - RSTCNT - set to reset all counter and related snapshots - 4 - 1 - read-write - - - RESERVED - reserved - 2 - 2 - read-write - - - RESERVED - reserved - 0 - 2 - read-write - - - - - PHCFG - Phase configure register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLYSEL - This bit select delay start time: -1- start counting delay after pre-trigger -0- start counting delay after u,v,w toggle - 31 - 1 - read-write - - - RESERVED - reserved - 24 - 7 - read-write - - - DLYCNT - delay clock cycles number - 0 - 24 - read-write - - - - - WDGCFG - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - UVWCFG - U,V,W configure register - 0xc - 32 - 0x00000000 - 0x07FFFFFF - - - RESERVED - reserved - 24 - 3 - read-write - - - PRECNT - the clock cycle number which the pre flag will set before the next uvw transition - 0 - 24 - read-write - - - - - TRGOEN - Trigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- enable trigger output when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- enable trigger output when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- enable trigger output when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFEN - 1- enable trigger output when u flag set - 23 - 1 - read-write - - - VFEN - 1- enable trigger output when v flag set - 22 - 1 - read-write - - - WFEN - 1- enable trigger output when w flag set - 21 - 1 - read-write - - - - - READEN - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- load counters to their read registers when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- load counters to their read registers when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- load counters to their read registers when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFEN - 1- load counters to their read registers when u flag set - 23 - 1 - read-write - - - VFEN - 1- load counters to their read registers when v flag set - 22 - 1 - read-write - - - WFEN - 1- load counters to their read registers when w flag set - 21 - 1 - read-write - - - - - DMAEN - DMA enable register - 0x24 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- generate dma request when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- generate dma request when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- generate dma request when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFEN - 1- generate dma request when u flag set - 23 - 1 - read-write - - - VFEN - 1- generate dma request when v flag set - 22 - 1 - read-write - - - WFEN - 1- generate dma request when w flag set - 21 - 1 - read-write - - - - - SR - Status register - 0x28 - 32 - 0x00000000 - 0xFFE00000 - - - WDGF - watchdog count timeout flag - 31 - 1 - read-write - - - PHUPTF - phase update flag, will set when any of u, v, w signal toggle - 30 - 1 - read-write - - - PHPREF - phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - 29 - 1 - read-write - - - PHDLYF - phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UF - u flag, will set when u signal toggle - 23 - 1 - read-write - - - VF - v flag, will set when v signal toggle - 22 - 1 - read-write - - - WF - w flag, will set when w signal toggle - 21 - 1 - read-write - - - - - IRQEN - Interrupt request enable register - 0x2c - 32 - 0x00000000 - 0xFFE00000 - - - WDGIE - 1- generate interrupt request when wdg flag set - 31 - 1 - read-write - - - PHUPTIE - 1- generate interrupt request when phupt flag set - 30 - 1 - read-write - - - PHPREIE - 1- generate interrupt request when phpre flag set - 29 - 1 - read-write - - - PHDLYIE - 1- generate interrupt request when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFIE - 1- generate interrupt request when u flag set - 23 - 1 - read-write - - - VFIE - 1- generate interrupt request when v flag set - 22 - 1 - read-write - - - WFIE - 1- generate interrupt request when w flag set - 21 - 1 - read-write - - - - - COUNT_CURRENT_W - W counter - 0x30 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_CURRENT_V - V counter - 0x34 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_CURRENT_U - U counter - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_CURRENT_TMR - Timer counter - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_READ_W - W read register - 0x40 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_READ_V - V read register - 0x44 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_READ_U - U read register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_READ_TMR - Timer read register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP0_W - W snap register 0 - 0x50 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP0_V - V snap register 0 - 0x54 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP0_U - Usnap register 0 - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP0_TMR - Timer snap register 0 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP1_W - W snap register 1 - 0x60 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP1_V - V snap register 1 - 0x64 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP1_U - U snap register 1 - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP1_TMR - Timer snap register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - HIS_U_HIS0 - history register 0 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - HIS_U_HIS1 - history register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - HIS_V_HIS0 - V histroy register 0 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - HIS_V_HIS1 - V histroy register 1 - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - HIS_W_HIS0 - W histroy register 0 - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - HIS_W_HIS1 - W histroy register 1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - - - HALL1 - HALL1 - HALL - 0xf0214000 - - - QEI0 - QEI0 - QEI - 0xf0208000 - - 0x0 - 0x80 - registers - - - - CR - Control register - 0x0 - 32 - 0x00000000 - 0x80077F3F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - HRSTSPD - 1- reset spdcnt when H assert - 18 - 1 - read-write - - - HRSTPH - 1- reset phcnt when H assert - 17 - 1 - read-write - - - HRSTZ - 1- reset zcnt when H assert - 16 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - RESERVED - 00-x1, phase_cnt will increase at each A posedge -01-x2, phase_cnt will increase at each A/B posedge -10-x4, phase_cnt will increase at each edge(A/B, pos/neg) - 2 - 2 - read-write - - - ENCTYP - 00-abz; 01-pd; 10-ud; 11-reserved - 0 - 2 - read-write - - - - - PHCFG - Phase configure register - 0x4 - 32 - 0x00000000 - 0x007FFFFF - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert - 21 - 1 - read-write - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 21 - read-write - - - - - WDGCFG - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - PHIDX - Phase index register - 0xc - 32 - 0x00000000 - 0x001FFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 21 - read-write - - - - - TRGOEN - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - - - READEN - Read event enable register - 0x14 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - - - ZCMP - Z comparator - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - PHCMP - Phase comparator - 0x1c - 32 - 0x00000000 - 0xE01FFFFF - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - PHCMP - phcnt position compare value - 0 - 21 - read-write - - - - - SPDCMP - Speed comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - DMAEN - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - - - SR - Status register - 0x28 - 32 - 0x00000000 - 0xF0000000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - - - IRQEN - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xF0000000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - - - COUNT_CURRENT_Z - Z counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_CURRENT_PH - Phase counter - 0x34 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_CURRENT_SPD - Speed counter - 0x38 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_CURRENT_TMR - Timer counter - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_READ_Z - Z counter - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_READ_PH - Phase counter - 0x44 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_READ_SPD - Speed counter - 0x48 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_READ_TMR - Timer counter - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP0_Z - Z snap register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_SNAP0_PH - Phase snap register - 0x54 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_SNAP0_SPD - Speed snap register - 0x58 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_SNAP0_TMR - Timer snap register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP1_Z - Z snap register 1 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_SNAP1_PH - Phase snap register 1 - 0x64 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_SNAP1_SPD - Speed snap register 1 - 0x68 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_SNAP1_TMR - Timer snap register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS0 - Speed history - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS1 - Speed history 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS2 - Speed history 2 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS3 - Speed history 3 - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - - - QEI1 - QEI1 - QEI - 0xf0218000 - - - TRGM0 - TRGM0 - TRGM - 0xf020c000 - - 0x0 - 0x404 - registers - - - - FILTCFG_PWM_IN0 - Filter configure register - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN1 - Filter configure register - 0x4 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN2 - Filter configure register - 0x8 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN3 - Filter configure register - 0xc - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN4 - Filter configure register - 0x10 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN5 - Filter configure register - 0x14 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN6 - Filter configure register - 0x18 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN7 - Filter configure register - 0x1c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN0 - Filter configure register - 0x20 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN1 - Filter configure register - 0x24 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN2 - Filter configure register - 0x28 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN3 - Filter configure register - 0x2c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN4 - Filter configure register - 0x30 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN5 - Filter configure register - 0x34 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN6 - Filter configure register - 0x38 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN7 - Filter configure register - 0x3c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN8 - Filter configure register - 0x40 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN9 - Filter configure register - 0x44 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN10 - Filter configure register - 0x48 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN11 - Filter configure register - 0x4c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - TRGOCFG_TRGM_OUT0 - Trigger manager output configure register - 0x100 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT1 - Trigger manager output configure register - 0x104 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT2 - Trigger manager output configure register - 0x108 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT3 - Trigger manager output configure register - 0x10c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT4 - Trigger manager output configure register - 0x110 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT5 - Trigger manager output configure register - 0x114 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT6 - Trigger manager output configure register - 0x118 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT7 - Trigger manager output configure register - 0x11c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT8 - Trigger manager output configure register - 0x120 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT9 - Trigger manager output configure register - 0x124 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT10 - Trigger manager output configure register - 0x128 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT11 - Trigger manager output configure register - 0x12c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUTX0 - Trigger manager output configure register - 0x130 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUTX1 - Trigger manager output configure register - 0x134 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_SYNCI - Trigger manager output configure register - 0x138 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FRCI - Trigger manager output configure register - 0x13c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FRCSYNCI - Trigger manager output configure register - 0x140 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_SHRLDSYNCI - Trigger manager output configure register - 0x144 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI0 - Trigger manager output configure register - 0x148 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI1 - Trigger manager output configure register - 0x14c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI2 - Trigger manager output configure register - 0x150 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI3 - Trigger manager output configure register - 0x154 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN8 - Trigger manager output configure register - 0x158 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN9 - Trigger manager output configure register - 0x15c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN10 - Trigger manager output configure register - 0x160 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN11 - Trigger manager output configure register - 0x164 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN12 - Trigger manager output configure register - 0x168 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN13 - Trigger manager output configure register - 0x16c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN14 - Trigger manager output configure register - 0x170 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN15 - Trigger manager output configure register - 0x174 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN16 - Trigger manager output configure register - 0x178 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN17 - Trigger manager output configure register - 0x17c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN18 - Trigger manager output configure register - 0x180 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN19 - Trigger manager output configure register - 0x184 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN20 - Trigger manager output configure register - 0x188 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN21 - Trigger manager output configure register - 0x18c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN22 - Trigger manager output configure register - 0x190 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN23 - Trigger manager output configure register - 0x194 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_A - Trigger manager output configure register - 0x198 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_B - Trigger manager output configure register - 0x19c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_Z - Trigger manager output configure register - 0x1a0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_H - Trigger manager output configure register - 0x1a4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_PAUSE - Trigger manager output configure register - 0x1a8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_SNAPI - Trigger manager output configure register - 0x1ac - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_U - Trigger manager output configure register - 0x1b0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_V - Trigger manager output configure register - 0x1b4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_W - Trigger manager output configure register - 0x1b8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_SNAPI - Trigger manager output configure register - 0x1bc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC0_STRGI - Trigger manager output configure register - 0x1c0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC1_STRGI - Trigger manager output configure register - 0x1c4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC2_STRGI - Trigger manager output configure register - 0x1c8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC3_STRGI - Trigger manager output configure register - 0x1cc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADCX_PTRGI0A - Trigger manager output configure register - 0x1d0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADCX_PTRGI0B - Trigger manager output configure register - 0x1d4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADCX_PTRGI0C - Trigger manager output configure register - 0x1d8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRA_SYNCI - Trigger manager output configure register - 0x1dc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRA_IN2 - Trigger manager output configure register - 0x1e0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRA_IN3 - Trigger manager output configure register - 0x1e4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRB_SYNCI - Trigger manager output configure register - 0x1e8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRB_IN2 - Trigger manager output configure register - 0x1ec - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRB_IN3 - Trigger manager output configure register - 0x1f0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_CMPX_WIN - Trigger manager output configure register - 0x1f4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_CAN_PTPC0_CAP - Trigger manager output configure register - 0x1f8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_CAN_PTPC1_CAP - Trigger manager output configure register - 0x1fc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - DMACFG_0 - DMA request configure register - 0x200 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - DMACFG_1 - DMA request configure register - 0x204 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - DMACFG_2 - DMA request configure register - 0x208 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - DMACFG_3 - DMA request configure register - 0x20c - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - GCR - General Control Register - 0x400 - 32 - 0x00000000 - 0x00000FFF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 12 - read-write - - - - - - - TRGM1 - TRGM1 - TRGM - 0xf021c000 - - - SYNT - SYNT - SYNT - 0xf0240000 - - 0x0 - 0x30 - registers - - - - GCR - Global control register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - RLD - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - CNT - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - CMP_0 - Comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - CMP_1 - Comparator - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - CMP_2 - Comparator - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - CMP_3 - Comparator - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - ENET0 - ENET0 - ENET - 0xf2000000 - - 0x0 - 0x3028 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configuration. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - VERSION - Version Register - 0x20 - 32 - 0x00000000 - 0x0000FFFF - - - USERVER - User-defined Version - 8 - 8 - read-only - - - SNPSVER - Synopsys-defined Version (3.7) - 0 - 8 - read-only - - - - - DEBUGGING - Debug Register - 0x24 - 32 - 0x00000000 - 0x037F0377 - - - TXSTSFSTS - MTL TxStatus FIFO Full Status - When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. - 25 - 1 - read-only - - - TXFSTS - MTL Tx FIFO Not Empty Status -When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. - 24 - 1 - read-only - - - TWCSTS - MTL Tx FIFO Write Controller Status -When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. - 22 - 1 - read-only - - - TRCSTS - MTL Tx FIFO Read Controller Status -This field indicates the state of the Tx FIFO Read Controller: -- 00: IDLE state -- 01: READ state (transferring data to the MAC transmitter) -- 10: Waiting for TxStatus from the MAC transmitter -- 11: Writing the received TxStatus or flushing the Tx FIFO - 20 - 2 - read-only - - - TXPAUSED - MAC Transmitter in Pause -When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. - 19 - 1 - read-only - - - TFCSTS - MAC Transmit Frame Controller Status -This field indicates the state of the MAC Transmit Frame Controller module: -- 00: IDLE state -- 01: Waiting for status of previous frame or IFG or backoff period to be over -- 10: Generating and transmitting a Pause frame (in the full-duplex mode) -- 11: Transferring input frame for transmission - 17 - 2 - read-only - - - TPESTS - MAC GMII or MII Transmit Protocol Engine Status - When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. - 16 - 1 - read-only - - - RXFSTS - MTL RxFIFO Fill-Level Status -This field gives the status of the fill-level of the Rx FIFO: -- 00: Rx FIFO Empty -- 01: Rx FIFO fill-level below flow-control deactivate threshold -- 10: Rx FIFO fill-level above flow-control activate threshold -- 11: Rx FIFO Full - 8 - 2 - read-only - - - RRCSTS - MTL RxFIFO Read Controller State -This field gives the state of the Rx FIFO read Controller: -- 00: IDLE state -- 01: Reading frame data -- 10: Reading frame status (or timestamp) -- 11: Flushing the frame data and status - 5 - 2 - read-only - - - RWCSTS - MTL Rx FIFO Write Controller Active Status - When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. - 4 - 1 - read-only - - - RFCFCSTS - MAC Receive Frame FIFO Controller Status - When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. - 1 - 2 - read-only - - - RPESTS - MAC GMII or MII Receive Protocol Engine Status -When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. - 0 - 1 - read-only - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Regsiter - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is always set to 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - MAC_ADDR_1_HIGH - MAC Address High Register - 0x48 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_1_LOW - MAC Address Low Register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - MAC_ADDR_2_HIGH - MAC Address2 High Register - 0x50 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_2_LOW - MAC Address2 Low Register - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - MAC_ADDR_3_HIGH - MAC Address3 High Register - 0x58 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_3_LOW - MAC Address3 Low Register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - MAC_ADDR_4_HIGH - MAC Address4 High Register - 0x60 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_4_LOW - MAC Address4 Low Register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0001003F - - - SMIDRXS - Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). - 16 - 1 - read-only - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - GPIO - General Purpose IO Register - 0xe0 - 32 - 0x00000000 - 0x0F0F0F0F - - - GPIT - No description avaiable - 24 - 4 - read-write - - - GPIE - No description avaiable - 16 - 4 - read-write - - - GPO - No description avaiable - 8 - 4 - read-write - - - GPIS - No description avaiable - 0 - 4 - read-write - - - - - MMC_CNTRL - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - MMC_INTR_RX - MMC Receive Interrupt maintains the interrupt generated from all -of the receive statistic counters. - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - MMC_INTR_TX - MMC Transmit Interrupt maintains the interrupt generated from all -of the transmit statistic counters - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - MMC_INTR_MASK_RX - MMC Receive Interrupt mask maintains the mask for the interrupt -generated from all of the receive statistic counters - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - MMC_INTR_MASK_TX - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - TXOCTETCOUNT_GB - Number of bytes transmitted, exclusive of preamble and retried -bytes, in good and bad frames. - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. - 0 - 32 - read-write - - - - - TXFRAMECOUNT_GB - Number of good and bad frames transmitted, exclusive of retried -frames. - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted, exclusive of retried frames. - 0 - 32 - read-write - - - - - TXBROADCASTFRAMES_G - Number of good broadcast frames transmitted - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good broadcast frames transmitted. - 0 - 32 - read-write - - - - - TXMLTICASTFRAMES_G - Number of good multicast frames transmitted - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good multicast frames transmitted. - 0 - 32 - read-write - - - - - TX64OCTETS_GB - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX65TO127OCTETS_GB - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX128TO255OCTETS_GB - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX256TO511OCTETS_GB - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX512TO1023OCTETS_GB - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX1024TOMAXOCTETS_GB - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TXUNICASTFRAMES_GB - Number of good and bad unicast frames transmitted. - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad unicast frames transmitted. - 0 - 32 - read-write - - - - - TXMULTICASTFRAMES_GB - Number of good and bad multicast frames transmitted. - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad multicast frames transmitted. - 0 - 32 - read-write - - - - - TXBROADCASTFRAMES_GB - Number of good and bad broadcast frames transmitted. - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad broadcast frames transmitted. - 0 - 32 - read-write - - - - - TXUNDERFLOWERROR - Number of frames aborted because of frame underflow error. - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of frame underflow error. - 0 - 32 - read-write - - - - - TXSINGLECOL_G - Number of successfully transmitted frames after a single collision -in the half-duplex mode. - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after a single collision in the half-duplex mode. - 0 - 32 - read-write - - - - - TXMULTICOL_G - Number of successfully transmitted frames after multiple collisions -in the half-duplex mode. - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after multiple collisions in the half-duplex mode. - 0 - 32 - read-write - - - - - TXDEFERRED - Number of successfully transmitted frames after a deferral in the -half-duplex mode. - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after a deferral in the half-duplex mode. - 0 - 32 - read-write - - - - - TXLATECOL - Number of frames aborted because of late collision error - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of late collision error. - 0 - 32 - read-write - - - - - TXEXESSCOL - Number of frames aborted because of excessive (16) collision -errors - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of excessive (16) collision errors. - 0 - 32 - read-write - - - - - TXCARRIERERROR - Number of frames aborted because of carrier sense error (no -carrier or loss of carrier). - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of carrier sense error (no carrier or loss of carrier). - 0 - 32 - read-write - - - - - TXOCTETCOUNT_G - Number of bytes transmitted, exclusive of preamble, only in good -frames. - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes transmitted, exclusive of preamble, only in good frames. - 0 - 32 - read-write - - - - - TXFRAMECOUNT_G - Number of good frames transmitted - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good frames transmitted. - 0 - 32 - read-write - - - - - TXEXCESSDEF - Number of frames aborted because of excessive deferral error -(deferred for more than two max-sized frame times). - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). - 0 - 32 - read-write - - - - - TXPAUSEFRAMES - Number of good Pause frames transmitted - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good Pause frames transmitted. - 0 - 32 - read-write - - - - - TXVLANFRAMES_G - Number of good VLAN frames transmitted, exclusive of retried -frames. - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good VLAN frames transmitted, exclusive of retried frames. - 0 - 32 - read-write - - - - - TXOVERSIZE_G - Number of frames transmitted without errors and with length -greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged -frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC -Configuration Register)). - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 - read-write - - - - - RXFRAMECOUNT_GB - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - RXOCTETCOUNT_G - Number of bytes received, exclusive of preamble, only in good -frames. - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received, exclusive of preamble, in good and bad frames. - 0 - 32 - read-write - - - - - RXOCTETCOUNT_GB - Number of bytes received, exclusive of preamble, in good and bad -frames. - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received, exclusive of preamble, only in good frames. - 0 - 32 - read-write - - - - - RXBROADCASTFRAMES_G - Number of good broadcast frames received - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good broadcast frames received. - 0 - 32 - read-write - - - - - RXMULTICASTFRAMES_G - Number of good multicast frames received - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good multicast frames received. - 0 - 32 - read-write - - - - - RXCRCERROR - Number of frames received with CRC error - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with CRC error. - 0 - 32 - read-write - - - - - RXALIGNMENTERROR - Number of frames received with alignment (dribble) error. Valid -only in 10/100 mode - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. - 0 - 32 - read-write - - - - - RXRUNTERROR - Number of frames received with runt (<64 bytes and CRC error) -error. - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with runt (<64 bytes and CRC error) error. - 0 - 32 - read-write - - - - - RXJABBERERROR - Number of giant frames received with length (including CRC) -greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with -CRC error. If Jumbo Frame mode is enabled, then frames of -length greater than 9,018 bytes (9,022 for VLAN tagged) are -considered as giant frames. - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - 0 - 32 - read-write - - - - - RXUNDERSIZE_G - Number of frames received with length less than 64 bytes, without -any errors. - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length less than 64 bytes, without any errors. - 0 - 32 - read-write - - - - - RXOVERSIZE_G - Number of frames received without errors, with length greater -than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 -bytes if enabled in Bit 27 of Register 0 (MAC Configuration -Register)) - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 - read-write - - - - - RX64OCTETS_GB - Number of good and bad frames received with length 64 bytes, -exclusive of preamble. - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length 64 bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX65TO127OCTETS_GB - No description avaiable - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX128TO255OCTETS_GB - No description avaiable - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX256TO511OCTETS_GB - Number of good and bad frames received with length between -256 and 511 (inclusive) bytes, exclusive of preamble. - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX512TO1023OCTETS_GB - Number of good and bad frames received with length between -512 and 1023 (inclusive) bytes, exclusive of preamble. - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX1024TOMAXOCTETS_GB - Number of good and bad frames received with length between -1024 and maxsize (inclusive) bytes, exclusive of preamble. - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - RXUNICASTFRAMES_G - Number of received good unicast frames. - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good unicast frames. - 0 - 32 - read-write - - - - - RXLENGTHERROR - Number of frames received with length error (Length type field ≠ -frame size), for all frames with valid length field. - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. - 0 - 32 - read-write - - - - - RXOUTOFRANGETYPE - Number of frames received with length field not equal to the valid -frame size (greater than 1,500 but less than 1,536). - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - 0 - 32 - read-write - - - - - RXPAUSEFRAMES - Number of good and valid Pause frames received. - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and valid Pause frames received. - 0 - 32 - read-write - - - - - RXFIFOOVERFLOW - Number of missed received frames because of FIFO overflow. -This counter is not present in the GMAC-CORE configuration. - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. - 0 - 32 - read-write - - - - - RXVLANFRAMES_GB - Number of good and bad VLAN frames received. - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad VLAN frames received. - 0 - 32 - read-write - - - - - RXWATCHDOGERROR - Number of frames received with error because of watchdog -timeout error (frames with a data load larger than 2,048 bytes or -the value programmed in Register 55 (Watchdog Timeout -Register)). - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). - 0 - 32 - read-write - - - - - RXRCVERROR - Number of frames received with Receive error or Frame Extension -error on the GMII or MII interface. - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. - 0 - 32 - read-write - - - - - RXCTRLFRAMES_G - Number of received good control frames - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good control frames. - 0 - 32 - read-write - - - - - MMC_IPC_INTR_MASK_RX - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - MMC_IPC_INTR_RX - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - RXIPV4_GD_FMS - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - RXIPV4_HDRERR_FRMS - Number of IPv4 datagrams received with header (checksum, -length, or version mismatch) errors - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors - 0 - 32 - read-write - - - - - RXIPV4_NOPAY_FRMS - Number of IPv4 datagram frames received that did not have a -TCP, UDP, or ICMP payload processed by the Checksum engine - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine - 0 - 32 - read-write - - - - - RXIPV4_FRAG_FRMS - Number of good IPv4 datagrams with fragmentation - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams with fragmentation - 0 - 32 - read-write - - - - - RXIPV4_UDSBL_FRMS - Number of good IPv4 datagrams received that had a UDP -payload with checksum disabled - 0x220 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received that had a UDP payload with checksum disabled - 0 - 32 - read-write - - - - - RXIPV6_GD_FRMS - Number of good IPv6 datagrams received with TCP, UDP, or -ICMP payloads - 0x224 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads - 0 - 32 - read-write - - - - - RXIPV6_HDRERR_FRMS - Number of IPv6 datagrams received with header errors (length or -version mismatch) - 0x228 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv6 datagrams received with header errors (length or version mismatch) - 0 - 32 - read-write - - - - - RXIPV6_NOPAY_FRMS - Number of IPv6 datagram frames received that did not have a -TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with -fragmentation or security extension headers - 0x22c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers - 0 - 32 - read-write - - - - - RXUDP_GD_FRMS - Number of good IP datagrams with a good UDP payload. This -counter is not updated when the rxipv4_udsbl_frms counter is -incremented. - 0x230 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. - 0 - 32 - read-write - - - - - RXUDP_ERR_FRMS - Number of good IP datagrams whose UDP payload has a -checksum error - 0x234 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose UDP payload has a checksum error - 0 - 32 - read-write - - - - - RXTCP_GD_FRMS - Number of good IP datagrams with a good TCP payload - 0x238 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good TCP payload - 0 - 32 - read-write - - - - - RXTCP_ERR_FRMS - Number of good IP datagrams whose TCP payload has a -checksum error - 0x23c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose TCP payload has a checksum error - 0 - 32 - read-write - - - - - RXICMP_GD_FRMS - Number of good IP datagrams with a good ICMP payload - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good ICMP payload - 0 - 32 - read-write - - - - - RXICMP_ERR_FRMS - Number of good IP datagrams whose ICMP payload has a -checksum error - 0x244 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose ICMP payload has a checksum error - 0 - 32 - read-write - - - - - RXIPV4_GD_OCTETS - Number of bytes received in good IPv4 datagrams encapsulating -TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad -bytes are not included in this counter or in the octet counters listed -below). - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). - 0 - 32 - read-write - - - - - RXIPV4_HDRERR_OCTETS - Number of bytes received in IPv4 datagrams with header errors -(checksum, length, version mismatch). The value in the Length -field of IPv4 header is used to update this counter. - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_NOPAY_OCTETS - Number of bytes received in IPv4 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv4 header’s -Length field is used to update this counter. - 0x258 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_FRAG_OCTETS - Number of bytes received in fragmented IPv4 datagrams. The -value in the IPv4 header’s Length field is used to update this -counter - 0x25c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_UDSBL_OCTETS - Number of bytes received in a UDP segment that had the UDP -checksum disabled. This counter does not count IP Header bytes. - 0x260 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. - 0 - 32 - read-write - - - - - RXIPV6_GD_OCTETS - Number of bytes received in good IPv6 datagrams encapsulating -TCP, UDP or ICMPv6 data - 0x264 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data - 0 - 32 - read-write - - - - - RXIPV6_HDRERR_OCTETS - Number of bytes received in IPv6 datagrams with header errors -(length, version mismatch). The value in the IPv6 header’s Length -field is used to update this counter. - 0x268 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV6_NOPAY_OCTETS - Number of bytes received in IPv6 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv6 header’s -Length field is used to update this counter. - 0x26c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXUDP_GD_OCTETS - Number of bytes received in a good UDP segment. This counter -(and the counters below) does not count IP header bytes. - 0x270 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. - 0 - 32 - read-write - - - - - RXUDP_ERR_OCTETS - Number of bytes received in a UDP segment that had checksum -errors - 0x274 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a UDP segment that had checksum errors - 0 - 32 - read-write - - - - - RXTCP_GD_OCTETS - Number of bytes received in a good TCP segment - 0x278 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good TCP segment - 0 - 32 - read-write - - - - - RXTCP_ERR_OCTETS - Number of bytes received in a TCP segment with checksum -errors - 0x27c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a TCP segment with checksum errors - 0 - 32 - read-write - - - - - RXICMP_GD_OCTETS - Number of bytes received in a good ICMP segment - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good ICMP segment - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x400 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_0_L4_ADDR - Layer 4 Address Register - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_0 - Layer 3 Address 0 Register - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_1 - Layer 3 Address 1 Register - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_2 - Layer 3 Address 2 Register - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_3 - Layer 3 Address 3 Register - 0x41c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x430 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_1_L4_ADDR - Layer 4 Address Register - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_0 - Layer 3 Address 0 Register - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_1 - Layer 3 Address 1 Register - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_2 - Layer 3 Address 2 Register - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_3 - Layer 3 Address 3 Register - 0x44c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x460 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_2_L4_ADDR - Layer 4 Address Register - 0x464 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_0 - Layer 3 Address 0 Register - 0x470 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_1 - Layer 3 Address 1 Register - 0x474 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_2 - Layer 3 Address 2 Register - 0x478 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_3 - Layer 3 Address 3 Register - 0x47c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x490 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_3_L4_ADDR - Layer 4 Address Register - 0x494 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_0 - Layer 3 Address 0 Register - 0x4a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_1 - Layer 3 Address 1 Register - 0x4a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_2 - Layer 3 Address 2 Register - 0x4a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_3 - Layer 3 Address 3 Register - 0x4ac - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER0 - Hash Table Register 0 - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER1 - Hash Table Register 1 - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER2 - Hash Table Register 2 - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER3 - Hash Table Register 3 - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER4 - Hash Table Register 4 - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER5 - Hash Table Register 5 - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER6 - Hash Table Register 6 - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER7 - Hash Table Register 7 - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-write - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-write - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description avaiable - 7 - 1 - read-only - - - TSTARGT2 - No description avaiable - 6 - 1 - read-only - - - TSTRGTERR1 - No description avaiable - 5 - 1 - read-only - - - TSTARGT1 - No description avaiable - 4 - 1 - read-only - - - TSTRGTERR - No description avaiable - 3 - 1 - read-only - - - AUXTSTRIG - No description avaiable - 2 - 1 - read-only - - - TSTARGT - No description avaiable - 1 - 1 - read-only - - - TSSOVF - No description avaiable - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - read-write - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - read-write - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - read-write - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRL0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-write - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-write - - - - - PPS0_INTERVAL - PPS0 Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS0 Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_1_TGTTM_SEC - PPS Target Time Seconds Register - 0x780 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - PPS_1_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x784 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - PPS_1_INTERVAL - PPS Interval Register - 0x788 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_1_WIDTH - PPS Width Register - 0x78c - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_2_TGTTM_SEC - PPS2 Target Time Seconds Register - 0x7a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - PPS_2_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x7a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - PPS_2_INTERVAL - PPS Interval Register - 0x7a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_2_WIDTH - PPS Width Register - 0x7ac - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_3_TGTTM_SEC - PPS3 Target Time Seconds Register - 0x7c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - PPS_3_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x7c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - PPS_3_INTERVAL - PPS Interval Register - 0x7c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_3_WIDTH - PPS Width Register - 0x7cc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_HW_FEATURE - HW Feature Register - 0x1058 - 32 - 0x00000000 - 0x7FFFFFFF - - - ACTPHYIF - Active or selected PHY interface -When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. -- 000: GMII or MII -- 001: RGMII -- 010: SGMII -- 011: TBI -- 100: RMII -- 101: RTBI -- 110: SMII -- 111: RevMII - All Others: Reserved - 28 - 3 - read-write - - - SAVLANINS - Source Address or VLAN Insertion - 27 - 1 - read-write - - - FLEXIPPSEN - Flexible Pulse-Per-Second Output - 26 - 1 - read-write - - - INTTSEN - Timestamping with Internal System Time - 25 - 1 - read-write - - - ENHDESSEL - Alternate (Enhanced Descriptor) - 24 - 1 - read-write - - - TXCHCNT - Number of additional Tx Channels - 22 - 2 - read-write - - - RXCHCNT - Number of additional Rx Channels - 20 - 2 - read-write - - - RXFIFOSIZE - Rx FIFO > 2,048 Bytes - 19 - 1 - read-write - - - RXTYP2COE - IP Checksum Offload (Type 2) in Rx - 18 - 1 - read-write - - - RXTYP1COE - IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. - 17 - 1 - read-write - - - TXCOESEL - Checksum Offload in Tx - 16 - 1 - read-write - - - AVSEL - AV feature - 15 - 1 - read-write - - - EEESEL - Energy Efficient Ethernet - 14 - 1 - read-write - - - TSVER2SEL - IEEE 1588-2008 Advanced timestamp - 13 - 1 - read-write - - - TSVER1SEL - Only IEEE 1588-2002 timestamp - 12 - 1 - read-write - - - MMCSEL - RMON module - 11 - 1 - read-write - - - MGKSEL - PMT magic packet - 10 - 1 - read-write - - - RWKSEL - PMT remote wake-up frame - 9 - 1 - read-write - - - SMASEL - SMA (MDIO) Interface - 8 - 1 - read-write - - - L3L4FLTREN - Layer 3 and Layer 4 feature - 7 - 1 - read-write - - - PCSSEL - PCS registers (TBI, SGMII, or RTBI PHY interface) - 6 - 1 - read-write - - - ADDMACADRSEL - Multiple MAC Address registers - 5 - 1 - read-write - - - HASHSEL - HASH filter - 4 - 1 - read-write - - - EXTHASHEN - Expanded DA Hash filter - 3 - 1 - read-write - - - HDSEL - Half-duplex support - 2 - 1 - read-write - - - GMIISEL - 1000 Mbps support - 1 - 1 - read-write - - - MIISEL - 10 or 100 Mbps support - 0 - 1 - read-write - - - - - CTRL0 - Control Register 0 - 0x3000 - 32 - 0x00000000 - 0x000003FF - - - ENET0_RXCLK_DLY_SEL - No description avaiable - 5 - 5 - read-write - - - ENET0_TXCLK_DLY_SEL - No description avaiable - 0 - 5 - read-write - - - - - CTRL2 - Control Register 1 - 0x3008 - 32 - 0x00000000 - 0xF808F400 - - - ENET0_IRQ_EN - No description avaiable - 27 - 5 - read-write - - - ENET0_REFCLK_OE - No description avaiable - 19 - 1 - read-write - - - ENET0_PHY_INF_SEL - No description avaiable - 13 - 3 - read-write - - - ENET0_FLOWCTRL - No description avaiable - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - No description avaiable - 10 - 1 - read-write - - - - - - - NTMR0 - NTMR0 - TMR - 0xf2010000 - - 0x0 - 0x20c - registers - - - - CHANNEL_CH0_CR - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH0_CMP0 - Comparator register 0 - 0x4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH0_CMP1 - Comparator register 1 - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH0_RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH0_CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH0_CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH0_CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH0_CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH0_CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH0_CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - CHANNEL_CH1_CR - Control Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH1_CMP0 - Comparator register 0 - 0x44 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH1_CMP1 - Comparator register 1 - 0x48 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH1_RLD - Reload register - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH1_CNTUPTVAL - Counter update value register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH1_CAPPOS - Capture rising edge register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH1_CAPNEG - Capture falling edge register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH1_CAPPRD - PWM period measure register - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH1_CAPDTY - PWM duty cycle measure register - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH1_CNT - Counter - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - CHANNEL_CH2_CR - Control Register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH2_CMP0 - Comparator register 0 - 0x84 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH2_CMP1 - Comparator register 1 - 0x88 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH2_RLD - Reload register - 0x8c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH2_CNTUPTVAL - Counter update value register - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH2_CAPPOS - Capture rising edge register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPNEG - Capture falling edge register - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPPRD - PWM period measure register - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPDTY - PWM duty cycle measure register - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH2_CNT - Counter - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - CHANNEL_CH3_CR - Control Register - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH3_CMP0 - Comparator register 0 - 0xc4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH3_CMP1 - Comparator register 1 - 0xc8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH3_RLD - Reload register - 0xcc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH3_CNTUPTVAL - Counter update value register - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH3_CAPPOS - Capture rising edge register - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH3_CAPNEG - Capture falling edge register - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH3_CAPPRD - PWM period measure register - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH3_CAPDTY - PWM duty cycle measure register - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH3_CNT - Counter - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 16 - 16 - read-write - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - read-write - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - read-write - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - read-write - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - read-write - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - read-write - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - read-write - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - read-write - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - read-write - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - read-write - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - read-write - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - read-write - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - read-write - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - read-write - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - read-write - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - read-write - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - read-write - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 16 - 16 - read-write - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software coutner sync event - 0 - 4 - read-write - - - - - - - GPTMR0 - GPTMR0 - TMR - 0xf3000000 - - - GPTMR1 - GPTMR1 - TMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - TMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - TMR - 0xf300c000 - - - PTMR - PTMR - TMR - 0xf40e0000 - - - USB0 - USB0 - USB - 0xf2020000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00000000 - 0x00FFEB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0x00FF00FF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 8 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 8 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0x00FF00FF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 8 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 8 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x000000FF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 8 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0x00FF00FF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0x00FF00FF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0x00FF00FF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0x00FF00FF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTCTRL_ENDPTCTRL0 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL1 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c4 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL2 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c8 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL3 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1cc - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL4 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL5 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d4 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL6 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d8 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL7 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1dc - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description avaiable - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description avaiable - 25 - 1 - read-write - - - AUTORESUME_EN - No description avaiable - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description avaiable - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description avaiable - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description avaiable - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description avaiable - 10 - 1 - read-write - - - OTG_POWER_MASK - No description avaiable - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description avaiable - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description avaiable - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description avaiable - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description avaiable - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description avaiable - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description avaiable - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description avaiable - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description avaiable - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description avaiable - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description avaiable - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description avaiable - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description avaiable - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description avaiable - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description avaiable - 31 - 1 - read-write - - - - - PHY_STATUS - No description avaiable - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description avaiable - 31 - 1 - read-write - - - LINE_STATE - No description avaiable - 6 - 2 - read-write - - - HOST_DISCONNECT - No description avaiable - 5 - 1 - read-write - - - ID_DIG - No description avaiable - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description avaiable - 2 - 1 - read-write - - - VBUS_VALID - No description avaiable - 0 - 1 - read-write - - - - - - - SDXC0 - SDXC0 - SDXC - 0xf2030000 - - 0x0 - 0x3008 - registers - - - - SDMASA - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description avaiable - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description avaiable - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description avaiable - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - RESP_RESP01 - No description avaiable - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP23 - No description avaiable - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP45 - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP67 - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - BUF_DATA - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description avaiable - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description avaiable - 0x28 - 32 - 0x00000000 - 0x070F0E3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description avaiable - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description avaiable - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgement Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description avaiable - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description avaiable - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description avaiable - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description avaiable - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description avaiable - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description avaiable - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description avaiable - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description avaiable - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description avaiable - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description avaiable - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - PRESET_INIT - No description avaiable - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_DS - No description avaiable - 0x62 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_HS - No description avaiable - 0x64 - 16 - 0x0001 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR12 - No description avaiable - 0x66 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR25 - No description avaiable - 0x68 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR50 - No description avaiable - 0x6a - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR104 - No description avaiable - 0x6c - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_DDR50 - No description avaiable - 0x6e - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_UHS2 - No description avaiable - 0x74 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description avaiable - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description avaiable - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description avaiable - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description avaiable - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description avaiable - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description avaiable - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description avaiable - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description avaiable - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description avaiable - 0 - 1 - read-write - - - - - CQCTL - No description avaiable - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description avaiable - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description avaiable - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description avaiable - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description avaiable - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description avaiable - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description avaiable - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description avaiable - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description avaiable - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description avaiable - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description avaiable - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description avaiable - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description avaiable - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description avaiable - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description avaiable - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description avaiable - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description avaiable - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description avaiable - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description avaiable - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description avaiable - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description avaiable - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description avaiable - 0 - 32 - read-only - - - - - MBIU_CTRL - Y - 0x510 - 32 - 0x00000000 - 0x0000000F - - - BURST_INCR16_EN - No description avaiable - 3 - 1 - read-write - - - BURST_INCR8_EN - No description avaiable - 2 - 1 - read-write - - - BUSRT_INCR4_EN - No description avaiable - 1 - 1 - read-write - - - UNDEFL_INCR_EN - No description avaiable - 0 - 1 - read-write - - - - - EMMC_BOOT_CTRL - No description avaiable - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description avaiable - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description avaiable - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - MISC_CTRL0 - No description avaiable - 0x3000 - 32 - 0x00000000 - 0xD0021FFF - - - IRQ_EN - No description avaiable - 30 - 2 - read-write - - - CARDCLK_INV_EN - No description avaiable - 28 - 1 - read-write - - - PAD_CLK_SEL_B - No description avaiable - 17 - 1 - read-write - - - CARDCLK_EN_SW - No description avaiable - 12 - 1 - read-write - - - FREQ_SEL_SW_EN - No description avaiable - 11 - 1 - read-write - - - TMCLK_EN - No description avaiable - 10 - 1 - read-write - - - FREQ_SEL_SW - No description avaiable - 0 - 10 - read-write - - - - - MISC_CTRL1 - No description avaiable - 0x3004 - 32 - 0x00000000 - 0xB0000000 - - - CARD_ACTIVE - No description avaiable - 31 - 1 - read-write - - - CARD_ACTIVE_PERIOD_SEL - No description avaiable - 28 - 2 - read-write - - - - - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x4 - 0x30 - registers - - - - CFG - Configuration Register - 0x10 - 32 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 2 - 30 - read-write - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - INTEN - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 10 - 22 - read-write - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - STATUS - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 15 - 17 - read-write - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - read-write - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - read-write - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - read-write - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - read-write - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - read-write - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - read-write - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - read-write - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - ADDR - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 10 - 22 - read-write - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - DATA - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 8 - 24 - read-write - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - CTRL - Control Register - 0x24 - 32 - 0x00001E00 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 13 - 19 - read-write - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - CMD - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 3 - 29 - read-write - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - SETUP - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 29 - 3 - read-write - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - RESERVED - No description avaiable - 14 - 2 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 5 - 27 - read-write - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - RESERVED - Not used - 24 - 4 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - RESERVED - Reserved - 18 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - RESERVED - Not used - 17 - 1 - read-only - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - CRCEN - CRC enable. -1x1, CRC is enabled. -1x0, CRC is disabled. - 11 - 1 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - RESERVED - Not used - 8 - 1 - read-only - - - RESERVED - Not used - 6 - 2 - read-only - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 31 - 1 - read-write - - - RESERVED - Not used - 30 - 1 - read-write - - - RESERVED - Not used - 24 - 6 - read-only - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - read-write - - - RESERVED - Not used - 21 - 2 - read-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - read-write - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - read-write - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - read-write - - - RESERVED - Not used - 6 - 10 - read-only - - - ERRSET - Working mode setup error. - 5 - 1 - read-write - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - read-write - - - ERRSRC - Source Buffer Access Error - 3 - 1 - read-write - - - ERRDST - Destination Buffer Error - 2 - 1 - read-write - - - ERRHAS - Hashing Check Error - 1 - 1 - read-write - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - read-write - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - RESERVED - Not used - 24 - 8 - read-only - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - RESERVED - Not used - 2 - 14 - read-only - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV0 - Cipher Initializtion Vector 0 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV1 - Cipher Initializtion Vector 1 - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV2 - Cipher Initializtion Vector 2 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV3 - Cipher Initializtion Vector 3 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - HASWRD_HASWRD0 - Hash Data Word 0 - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD1 - Hash Data Word 1 - 0x2c - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD2 - Hash Data Word 2 - 0x30 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD3 - Hash Data Word 3 - 0x34 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD4 - Hash Data Word 4 - 0x38 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD5 - Hash Data Word 5 - 0x3c - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD6 - Hash Data Word 6 - 0x40 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD7 - Hash Data Word 7 - 0x44 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - RESERVED - Not used - 7 - 17 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - RESERVED - Not used - 0 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description avaiable - 0 - 32 - read-write - - - - - - - DRAM - DRAM - DRAM - 0xf3050000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 - read-write - - - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 - read-write - - - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 - 1 - read-write - - - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 - 1 - read-write - - - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 - 1 - read-write - - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 - read-write - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BR_BASE0 - Base Register 0 (for SDRAM CS0 device) - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - BR_BASE1 - Base Register 1 (for SDRAM CS1 device) - 0x14 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - INTEN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 - 1 - read-write - - - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 - 1 - read-write - - - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 - 1 - read-write - - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 - 1 - read-write - - - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 - 1 - read-write - - - IPCMDDONE - IP command normal done interrupt - 0 - 1 - read-write - - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 - 1 - read-write - - - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 - read-write - - - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 - read-write - - - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 - 1 - read-write - - - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 - read-write - - - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 - 1 - read-write - - - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 - read-write - - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 - read-write - - - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 - read-write - - - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 - read-write - - - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 - read-write - - - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 - read-write - - - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 - read-write - - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 - read-write - - - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 - read-write - - - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 - read-write - - - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - 0 - 8 - read-write - - - - - SDRCTRL3 - SDRAM Control Register 3 - 0x4c - 32 - 0x00000000 - 0xFFFFFF0F - - - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 - read-write - - - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 - read-write - - - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 - read-write - - - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 - read-write - - - REN - Refresh enable - 0 - 1 - read-write - - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SA - Slave address - 0 - 32 - read-write - - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 - read-write - - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked - 3 - 1 - read-write - - - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked - 2 - 1 - read-write - - - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked - 1 - 1 - read-write - - - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked - 0 - 1 - read-write - - - - - IPCMD - IP Command Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. - 16 - 16 - write-only - - - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write - - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 - 1 - read-only - - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 - 1 - read-write - - - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells - 1 - 5 - read-write - - - DLYEN - delay line enable - 0 - 1 - read-write - - - - - - - FFA - FFA - FFA - 0xf3058000 - - 0x0 - 0x48 - registers - - - - CTRL - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFFFFFE01 - - - SFTRST - software reset the module if asserted to be 1. -EN is only active after this bit is zero. - 31 - 1 - read-write - - - RSV - Reserved - 9 - 22 - read-write - - - EN - Asserted to enable the module - 0 - 1 - read-write - - - - - STATUS - No description avaiable - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 8 - 24 - read-only - - - FIR_OV - FIR Overflow err - 7 - 1 - read-only - - - FFT_OV - FFT Overflow Err - 6 - 1 - read-only - - - WR_ERR - AXI Data Write Error - 5 - 1 - read-only - - - RD_NXT_ERR - AXI Read Bus Error for NXT DATA - 4 - 1 - read-only - - - RD_ERR - AXI Data Read Error - 3 - 1 - read-only - - - RSV - Reserved - 2 - 1 - read-only - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - read-only - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - read-only - - - - - INT_EN - No description avaiable - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRSV1 - Reserved - 8 - 24 - read-write - - - FIR_OV - FIR Overflow err - 7 - 1 - read-write - - - FFT_OV - FFT Overflow Err - 6 - 1 - read-write - - - WR_ERR - Enable Data Write Error interrupt - 5 - 1 - read-write - - - RD_NXT_ERR - Enable Read Bus Error for NXT DATA interrupt - 4 - 1 - read-write - - - RD_ERR - Enable Data Read Error interrupt - 3 - 1 - read-write - - - RSV - Write as zero - 2 - 1 - read-write - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - read-write - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - read-write - - - - - OP_CTRL - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - NXT_ADDR - The address for the next command. -It will be processed after CUR_CMD is executed and done.. - 2 - 30 - read-write - - - NXT_EN - Whether NXT_CMD is enabled. -Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. - 1 - 1 - read-write - - - EN - Whether CUR_CMD is enabled. -Asserted to enable the CUR_CMD - 0 - 1 - read-write - - - - - OP_CMD - No description avaiable - 0x24 - 32 - 0x00000000 - 0x01FFFEFF - - - CONJ_C - asserted to have conjuate value for coefs in computation - 24 - 1 - read-write - - - CMD - The Command Used: -0: FIR -2: FFT -Others: Reserved - 18 - 6 - read-write - - - OUTD_TYPE - Output data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - 15 - 3 - read-write - - - COEF_TYPE - Coef data type (used for FIR): -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - 12 - 3 - read-write - - - IND_TYPE - Input data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - 9 - 3 - read-write - - - NXT_CMD_LEN - The length of nxt commands in 32-bit words - 0 - 8 - read-write - - - - - OP_REG0 - No description avaiable - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC - No description avaiable - 0x28 - 32 - 0x00000000 - 0x00003FFF - - - FIR_COEF_TAPS - Length of FIR coefs - 0 - 14 - read-write - - - - - OP_FFT_MISC - No description avaiable - 0x28 - 32 - 0x00000000 - 0x000007FF - - - FFT_LEN - FFT length -0:8, -..., -n:2^(3+n) - 7 - 4 - read-write - - - IFFT - Asserted to indicate IFFT - 6 - 1 - read-write - - - RSV - Reserved. Should be written as zero - 4 - 2 - read-write - - - TMP_BLK - Memory block for indata. Should be assigned as 1 - 2 - 2 - read-write - - - IND_BLK - Memory block for indata. Should be assigned as 0 - 0 - 2 - read-write - - - - - OP_REG1 - No description avaiable - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC1 - No description avaiable - 0x2c - 32 - 0x00000000 - 0x003FFFFF - - - OUTD_MEM_BLK - Should be assigned as 0 - 20 - 2 - read-write - - - COEF_MEM_BLK - Should be assigned as 1 - 18 - 2 - read-write - - - IND_MEM_BLK - Should be assigned as 2 - 16 - 2 - read-write - - - FIR_DATA_TAPS - The input data data length - 0 - 16 - read-write - - - - - OP_REG2 - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FFT_INRBUF - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG3 - No description avaiable - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_INBUF - No description avaiable - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input data buffer pointer - 0 - 32 - read-write - - - - - OP_REG4 - No description avaiable - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_COEFBUF - No description avaiable - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The coef buf pointer - 0 - 32 - read-write - - - - - OP_FFT_OUTRBUF - No description avaiable - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG5 - No description avaiable - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_OUTBUF - No description avaiable - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） - 0 - 32 - read-write - - - - - OP_REG6 - No description avaiable - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_REG7 - No description avaiable - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x2ffc - registers - - - - RESOURCE_CPU0 - Resource control register for cpu0_core - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CPX0 - Resource control register for cpu0_subsys - 0x4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_POW_CPU0 - Resource control register for pow_cpu0 - 0x54 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RST_SOC - Resource control register for rst_soc - 0x58 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RST_CPU0 - Resource control register for rst_cpu0 - 0x5c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_XTAL - Resource control register for xtal - 0x80 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL0 - Resource control register for pll0 - 0x84 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_CLK0_PLL0 - Resource control register for clk0_pll0 - 0x88 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_CLK1_PLL0 - Resource control register for clk1_pll0 - 0x8c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_CLK2_PLL0 - Resource control register for clk2_pll0 - 0x90 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL1 - Resource control register for pll1 - 0x94 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_CLK0_PLL1 - Resource control register for clk0_pll1 - 0x98 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_CLK1_PLL1 - Resource control register for clk1_pll1 - 0x9c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL2 - Resource control register for pll2 - 0xa0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_CLK0_PLL2 - Resource control register for clk0_pll2 - 0xa4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_CLK1_PLL2 - Resource control register for clk1_pll2 - 0xa8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL0_REF - Resource control register for pll0 ref clock - 0xac - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL1_REF - Resource control register for pll1 ref clock - 0xb0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL2_REF - Resource control register for pll2 ref clock - 0xb4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CPU0 - Resource control register for clk_top_cpu0 - 0x100 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_MCT0 - Resource control register for clk_top_mct0 - 0x104 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_DRAM - Resource control register for clk_top_dram - 0x108 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_XPI0 - Resource control register for clk_top_xpi0 - 0x10c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_XPI1 - Resource control register for clk_top_xpi1 - 0x110 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_TMR0 - Resource control register for clk_top_tmr0 - 0x114 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_TMR1 - Resource control register for clk_top_tmr1 - 0x118 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_TMR2 - Resource control register for clk_top_tmr2 - 0x11c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_TMR3 - Resource control register for clk_top_tmr3 - 0x120 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT0 - Resource control register for clk_top_urt0 - 0x124 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT1 - Resource control register for clk_top_urt1 - 0x128 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT2 - Resource control register for clk_top_urt2 - 0x12c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT3 - Resource control register for clk_top_urt3 - 0x130 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT4 - Resource control register for clk_top_urt4 - 0x134 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT5 - Resource control register for clk_top_urt5 - 0x138 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT6 - Resource control register for clk_top_urt6 - 0x13c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_URT7 - Resource control register for clk_top_urt7 - 0x140 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C0 - Resource control register for clk_top_i2c0 - 0x144 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C1 - Resource control register for clk_top_i2c1 - 0x148 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C2 - Resource control register for clk_top_i2c2 - 0x14c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C3 - Resource control register for clk_top_i2c3 - 0x150 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI0 - Resource control register for clk_top_spi0 - 0x154 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI1 - Resource control register for clk_top_spi1 - 0x158 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI2 - Resource control register for clk_top_spi2 - 0x15c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI3 - Resource control register for clk_top_spi3 - 0x160 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAN0 - Resource control register for clk_top_can0 - 0x164 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAN1 - Resource control register for clk_top_can1 - 0x168 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_PTPC - Resource control register for clk_top_ptpc - 0x16c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ANA0 - Resource control register for clk_top_ana0 - 0x170 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ANA1 - Resource control register for clk_top_ana1 - 0x174 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ANA2 - Resource control register for clk_top_ana2 - 0x178 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ANA3 - Resource control register for clk_top_ana3 - 0x17c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_AUD0 - Resource control register for clk_top_aud0 - 0x180 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_AUD1 - Resource control register for clk_top_aud1 - 0x184 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ETH0 - Resource control register for clk_top_eth0 - 0x188 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_PTP0 - Resource control register for clk_top_ptp0 - 0x18c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_REF0 - Resource control register for clk_top_ref0 - 0x190 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_REF1 - Resource control register for clk_top_ref1 - 0x194 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_NTM0 - Resource control register for clk_top_ntm0 - 0x198 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SDC0 - Resource control register for clk_top_sdc0 - 0x19c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ADC0 - Resource control register for clk_top_adc0 - 0x200 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ADC1 - Resource control register for clk_top_adc1 - 0x204 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ADC2 - Resource control register for clk_top_adc2 - 0x208 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_DAC0 - Resource control register for clk_top_dac0 - 0x20c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2S0 - Resource control register for clk_top_i2s0 - 0x210 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2S1 - Resource control register for clk_top_i2s1 - 0x214 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_AHBP - Resource control register for ahbapb_bus - 0x400 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_AXIS - Resource control register for soc_bus - 0x404 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_AXIC - Resource control register for conn_bus - 0x408 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_DRAM - Resource control register for dram - 0x40c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ROM0 - Resource control register for rom - 0x410 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_LMM0 - Resource control register for lmm0 - 0x414 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RAM0 - Resource control register for axi_sram - 0x418 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MCT0 - Resource control register for mchtmr0 - 0x41c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_XPI0 - Resource control register for xpi0 - 0x420 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_XPI1 - Resource control register for xpi1 - 0x424 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SDP0 - Resource control register for sdp - 0x428 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RNG0 - Resource control register for rng - 0x42c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_KMAN - Resource control register for keym - 0x430 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_DMA0 - Resource control register for hdma - 0x434 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_DMA1 - Resource control register for xdma - 0x438 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_FFA0 - Resource control register for ffa - 0x43c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPIO - Resource control register for gpio - 0x440 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MBX0 - Resource control register for mbx - 0x444 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_WDG0 - Resource control register for wdg0 - 0x448 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_WDG1 - Resource control register for wdg1 - 0x44c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_TSNS - Resource control register for tsns - 0x450 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_TMR0 - Resource control register for tmr0 - 0x454 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_TMR1 - Resource control register for tmr1 - 0x458 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_TMR2 - Resource control register for tmr2 - 0x45c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_TMR3 - Resource control register for tmr3 - 0x460 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT0 - Resource control register for uart0 - 0x464 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT1 - Resource control register for uart1 - 0x468 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT2 - Resource control register for uart2 - 0x46c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT3 - Resource control register for uart3 - 0x470 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT4 - Resource control register for uart4 - 0x474 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT5 - Resource control register for uart5 - 0x478 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT6 - Resource control register for uart6 - 0x47c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_URT7 - Resource control register for uart7 - 0x480 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C0 - Resource control register for i2c0 - 0x484 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C1 - Resource control register for i2c1 - 0x488 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C2 - Resource control register for i2c2 - 0x48c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C3 - Resource control register for i2c3 - 0x490 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI0 - Resource control register for spi0 - 0x494 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI1 - Resource control register for spi1 - 0x498 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI2 - Resource control register for spi2 - 0x49c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI3 - Resource control register for spi3 - 0x4a0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAN0 - Resource control register for can0 - 0x4a4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAN1 - Resource control register for can1 - 0x4a8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_PTPC - Resource control register for ptpc - 0x4ac - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ADC0 - Resource control register for adc0 - 0x4b0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ADC1 - Resource control register for adc1 - 0x4b4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ADC2 - Resource control register for adc2 - 0x4b8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_DAC0 - Resource control register for dac - 0x4bc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ACMP - Resource control register for acmp - 0x4c0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2S0 - Resource control register for i2s0 - 0x4c4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2S1 - Resource control register for i2s1 - 0x4c8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_PDM0 - Resource control register for pdm - 0x4cc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_DAO - Resource control register for dao - 0x4d0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MSYN - Resource control register for msyn - 0x4d4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MOT0 - Resource control register for mot0 - 0x4d8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MOT1 - Resource control register for mot1 - 0x4dc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ETH0 - Resource control register for enet - 0x4e0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_NTM0 - Resource control register for ntmr - 0x4e4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SDC0 - Resource control register for sdxc - 0x4e8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_USB0 - Resource control register for usb - 0x4ec - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_REF0 - Resource control register for ref0 - 0x4f0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_REF1 - Resource control register for ref1 - 0x4f4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - GROUP0_LINK0_VALUE - Group setting - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_LINK0_SET - Group setting - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - GROUP0_LINK0_CLEAR - Group setting - 0x808 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - GROUP0_LINK0_TOGGLE - Group setting - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - GROUP0_LINK1_VALUE - Group setting - 0x810 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_LINK1_SET - Group setting - 0x814 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - GROUP0_LINK1_CLEAR - Group setting - 0x818 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - GROUP0_LINK1_TOGGLE - Group setting - 0x81c - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - AFFILIATE_CPU0_VALUE - Affiliate of Group - 0x900 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU0_SET - Affiliate of Group - 0x904 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 - 0 - 4 - read-write - - - - - AFFILIATE_CPU0_CLEAR - Affiliate of Group - 0x908 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 - 0 - 4 - read-write - - - - - AFFILIATE_CPU0_TOGGLE - Affiliate of Group - 0x90c - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before - 0 - 4 - read-write - - - - - RETENTION_CPU0_VALUE - Retention Contol - 0x920 - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu stop, -bit01: soc_ctx is kept on while cpu stop, -bit02: cpu0_mem is kept on while cpu stop, -bit03: cpu0_ctx is kept on while cpu stop, -bit04: xtal_hold is kept on while cpu stop, -bit05: pll0_hold is kept on while cpu stop, -bit06: pll1_hold is kept on while cpu stop, -bit07: pll2_hold is kept on while cpu stop, - 0 - 8 - read-write - - - - - RETENTION_CPU0_SET - Retention Contol - 0x924 - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep - 0 - 8 - read-write - - - - - RETENTION_CPU0_CLEAR - Retention Contol - 0x928 - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep - 0 - 8 - read-write - - - - - RETENTION_CPU0_TOGGLE - Retention Contol - 0x92c - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before - 0 - 8 - read-write - - - - - POWER_CPU0_STATUS - Power Setting - 0x1000 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - POWER_CPU0_LF_WAIT - Power Setting - 0x1004 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_CPU0_OFF_WAIT - Power Setting - 0x100c - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - RESET_SOC_CONTROL - Reset Setting - 0x1400 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - RESET_SOC_CONFIG - Reset Setting - 0x1404 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - RESET_SOC_COUNTER - Reset Setting - 0x140c - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - RESET_CPU0_CONTROL - Reset Setting - 0x1410 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - RESET_CPU0_CONFIG - Reset Setting - 0x1414 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - RESET_CPU0_COUNTER - Reset Setting - 0x141c - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - CLOCK_CPU_CLK_TOP_CPU0 - Clock setting - 0x1800 - 32 - 0x00000000 - 0xD0FF0FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - SUB1_DIV - ahb bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 20 - 4 - read-write - - - SUB0_DIV - axi bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 16 - 4 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_MCT0 - Clock setting - 0x1804 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_DRAM - Clock setting - 0x1808 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_XPI0 - Clock setting - 0x180c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_XPI1 - Clock setting - 0x1810 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_TMR0 - Clock setting - 0x1814 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_TMR1 - Clock setting - 0x1818 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_TMR2 - Clock setting - 0x181c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_TMR3 - Clock setting - 0x1820 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT0 - Clock setting - 0x1824 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT1 - Clock setting - 0x1828 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT2 - Clock setting - 0x182c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT3 - Clock setting - 0x1830 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT4 - Clock setting - 0x1834 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT5 - Clock setting - 0x1838 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT6 - Clock setting - 0x183c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_URT7 - Clock setting - 0x1840 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C0 - Clock setting - 0x1844 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C1 - Clock setting - 0x1848 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C2 - Clock setting - 0x184c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C3 - Clock setting - 0x1850 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI0 - Clock setting - 0x1854 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI1 - Clock setting - 0x1858 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI2 - Clock setting - 0x185c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI3 - Clock setting - 0x1860 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAN0 - Clock setting - 0x1864 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAN1 - Clock setting - 0x1868 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_PTPC - Clock setting - 0x186c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ANA0 - Clock setting - 0x1870 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ANA1 - Clock setting - 0x1874 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ANA2 - Clock setting - 0x1878 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ANA3 - Clock setting - 0x187c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_AUD0 - Clock setting - 0x1880 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_AUD1 - Clock setting - 0x1884 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ETH0 - Clock setting - 0x1888 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_PTP0 - Clock setting - 0x188c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_REF0 - Clock setting - 0x1890 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_REF1 - Clock setting - 0x1894 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_NTM0 - Clock setting - 0x1898 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SDC0 - Clock setting - 0x189c - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - ADCCLK_CLK_TOP_ADC0 - Clock setting - 0x1c00 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 - read-write - - - - - ADCCLK_CLK_TOP_ADC1 - Clock setting - 0x1c04 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 - read-write - - - - - ADCCLK_CLK_TOP_ADC2 - Clock setting - 0x1c08 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 - read-write - - - - - DACCLK_CLK_TOP_DAC0 - Clock setting - 0x1c0c - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 - read-write - - - - - I2SCLK_CLK_TOP_I2S0 - Clock setting - 0x1c10 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: aud clock 0 -1: aud clock 1 - 8 - 1 - read-write - - - - - I2SCLK_CLK_TOP_I2S1 - Clock setting - 0x1c14 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: aud clock 0 -1: aud clock 1 - 8 - 1 - read-write - - - - - GLOBAL00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 - 0 - 4 - read-write - - - - - MONITOR_SLICE0_CONTROL - Clock measure and monitor control - 0x2400 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE0_CURRENT - Clock measure result - 0x2404 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE0_LOW_LIMIT - Clock lower limit - 0x2408 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE0_HIGH_LIMIT - Clock upper limit - 0x240c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE1_CONTROL - Clock measure and monitor control - 0x2420 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE1_CURRENT - Clock measure result - 0x2424 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE1_LOW_LIMIT - Clock lower limit - 0x2428 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE1_HIGH_LIMIT - Clock upper limit - 0x242c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE2_CONTROL - Clock measure and monitor control - 0x2440 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE2_CURRENT - Clock measure result - 0x2444 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE2_LOW_LIMIT - Clock lower limit - 0x2448 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE2_HIGH_LIMIT - Clock upper limit - 0x244c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE3_CONTROL - Clock measure and monitor control - 0x2460 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE3_CURRENT - Clock measure result - 0x2464 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE3_LOW_LIMIT - Clock lower limit - 0x2468 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE3_HIGH_LIMIT - Clock upper limit - 0x246c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - CPU_CPU0_LP - CPU0 LP control - 0x2800 - 32 - 0x00001000 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - CPU_CPU0_LOCK - CPU0 Lock GPR - 0x2804 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - CPU_CPU0_GPR0 - CPU0 GPR0 - 0x2808 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR1 - CPU0 GPR1 - 0x280c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR2 - CPU0 GPR2 - 0x2810 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR3 - CPU0 GPR3 - 0x2814 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR4 - CPU0 GPR4 - 0x2818 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR5 - CPU0 GPR5 - 0x281c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR6 - CPU0 GPR6 - 0x2820 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR7 - CPU0 GPR7 - 0x2824 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR8 - CPU0 GPR8 - 0x2828 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR9 - CPU0 GPR9 - 0x282c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR10 - CPU0 GPR10 - 0x2830 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR11 - CPU0 GPR11 - 0x2834 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR12 - CPU0 GPR12 - 0x2838 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR13 - CPU0 GPR13 - 0x283c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_STATUS0 - CPU0 wakeup IRQ status - 0x2840 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS1 - CPU0 wakeup IRQ status - 0x2844 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS2 - CPU0 wakeup IRQ status - 0x2848 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS3 - CPU0 wakeup IRQ status - 0x284c - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_ENABLE0 - CPU0 wakeup IRQ enable - 0x2880 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE1 - CPU0 wakeup IRQ enable - 0x2884 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE2 - CPU0 wakeup IRQ enable - 0x2888 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE3 - CPU0 wakeup IRQ enable - 0x288c - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf64 - registers - - - - PAD_PA00_FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA00_PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA01_FUNC_CTL - ALT SELECT - 0x8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA01_PAD_CTL - PAD SETTINGS - 0xc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA02_FUNC_CTL - ALT SELECT - 0x10 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA02_PAD_CTL - PAD SETTINGS - 0x14 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA03_FUNC_CTL - ALT SELECT - 0x18 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA03_PAD_CTL - PAD SETTINGS - 0x1c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA04_FUNC_CTL - ALT SELECT - 0x20 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA04_PAD_CTL - PAD SETTINGS - 0x24 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA05_FUNC_CTL - ALT SELECT - 0x28 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA05_PAD_CTL - PAD SETTINGS - 0x2c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA06_FUNC_CTL - ALT SELECT - 0x30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA06_PAD_CTL - PAD SETTINGS - 0x34 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA07_FUNC_CTL - ALT SELECT - 0x38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA07_PAD_CTL - PAD SETTINGS - 0x3c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA08_FUNC_CTL - ALT SELECT - 0x40 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA08_PAD_CTL - PAD SETTINGS - 0x44 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA09_FUNC_CTL - ALT SELECT - 0x48 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA09_PAD_CTL - PAD SETTINGS - 0x4c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA10_FUNC_CTL - ALT SELECT - 0x50 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA10_PAD_CTL - PAD SETTINGS - 0x54 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA11_FUNC_CTL - ALT SELECT - 0x58 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA11_PAD_CTL - PAD SETTINGS - 0x5c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA12_FUNC_CTL - ALT SELECT - 0x60 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA12_PAD_CTL - PAD SETTINGS - 0x64 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA13_FUNC_CTL - ALT SELECT - 0x68 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA13_PAD_CTL - PAD SETTINGS - 0x6c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA14_FUNC_CTL - ALT SELECT - 0x70 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA14_PAD_CTL - PAD SETTINGS - 0x74 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA15_FUNC_CTL - ALT SELECT - 0x78 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA15_PAD_CTL - PAD SETTINGS - 0x7c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA16_FUNC_CTL - ALT SELECT - 0x80 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA16_PAD_CTL - PAD SETTINGS - 0x84 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA17_FUNC_CTL - ALT SELECT - 0x88 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA17_PAD_CTL - PAD SETTINGS - 0x8c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA18_FUNC_CTL - ALT SELECT - 0x90 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA18_PAD_CTL - PAD SETTINGS - 0x94 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA19_FUNC_CTL - ALT SELECT - 0x98 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA19_PAD_CTL - PAD SETTINGS - 0x9c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA20_FUNC_CTL - ALT SELECT - 0xa0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA20_PAD_CTL - PAD SETTINGS - 0xa4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA21_FUNC_CTL - ALT SELECT - 0xa8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA21_PAD_CTL - PAD SETTINGS - 0xac - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA22_FUNC_CTL - ALT SELECT - 0xb0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA22_PAD_CTL - PAD SETTINGS - 0xb4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA23_FUNC_CTL - ALT SELECT - 0xb8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA23_PAD_CTL - PAD SETTINGS - 0xbc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA24_FUNC_CTL - ALT SELECT - 0xc0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA24_PAD_CTL - PAD SETTINGS - 0xc4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA25_FUNC_CTL - ALT SELECT - 0xc8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA25_PAD_CTL - PAD SETTINGS - 0xcc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA26_FUNC_CTL - ALT SELECT - 0xd0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA26_PAD_CTL - PAD SETTINGS - 0xd4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA27_FUNC_CTL - ALT SELECT - 0xd8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA27_PAD_CTL - PAD SETTINGS - 0xdc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA28_FUNC_CTL - ALT SELECT - 0xe0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA28_PAD_CTL - PAD SETTINGS - 0xe4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA29_FUNC_CTL - ALT SELECT - 0xe8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA29_PAD_CTL - PAD SETTINGS - 0xec - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA30_FUNC_CTL - ALT SELECT - 0xf0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA30_PAD_CTL - PAD SETTINGS - 0xf4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PA31_FUNC_CTL - ALT SELECT - 0xf8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA31_PAD_CTL - PAD SETTINGS - 0xfc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB00_FUNC_CTL - ALT SELECT - 0x100 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB00_PAD_CTL - PAD SETTINGS - 0x104 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB01_FUNC_CTL - ALT SELECT - 0x108 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB01_PAD_CTL - PAD SETTINGS - 0x10c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB02_FUNC_CTL - ALT SELECT - 0x110 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB02_PAD_CTL - PAD SETTINGS - 0x114 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB03_FUNC_CTL - ALT SELECT - 0x118 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB03_PAD_CTL - PAD SETTINGS - 0x11c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB04_FUNC_CTL - ALT SELECT - 0x120 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB04_PAD_CTL - PAD SETTINGS - 0x124 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB05_FUNC_CTL - ALT SELECT - 0x128 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB05_PAD_CTL - PAD SETTINGS - 0x12c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB06_FUNC_CTL - ALT SELECT - 0x130 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB06_PAD_CTL - PAD SETTINGS - 0x134 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB07_FUNC_CTL - ALT SELECT - 0x138 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB07_PAD_CTL - PAD SETTINGS - 0x13c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB08_FUNC_CTL - ALT SELECT - 0x140 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB08_PAD_CTL - PAD SETTINGS - 0x144 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB09_FUNC_CTL - ALT SELECT - 0x148 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB09_PAD_CTL - PAD SETTINGS - 0x14c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB10_FUNC_CTL - ALT SELECT - 0x150 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB10_PAD_CTL - PAD SETTINGS - 0x154 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB11_FUNC_CTL - ALT SELECT - 0x158 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB11_PAD_CTL - PAD SETTINGS - 0x15c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB12_FUNC_CTL - ALT SELECT - 0x160 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB12_PAD_CTL - PAD SETTINGS - 0x164 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB13_FUNC_CTL - ALT SELECT - 0x168 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB13_PAD_CTL - PAD SETTINGS - 0x16c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB14_FUNC_CTL - ALT SELECT - 0x170 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB14_PAD_CTL - PAD SETTINGS - 0x174 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB15_FUNC_CTL - ALT SELECT - 0x178 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB15_PAD_CTL - PAD SETTINGS - 0x17c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB16_FUNC_CTL - ALT SELECT - 0x180 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB16_PAD_CTL - PAD SETTINGS - 0x184 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB17_FUNC_CTL - ALT SELECT - 0x188 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB17_PAD_CTL - PAD SETTINGS - 0x18c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB18_FUNC_CTL - ALT SELECT - 0x190 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB18_PAD_CTL - PAD SETTINGS - 0x194 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB19_FUNC_CTL - ALT SELECT - 0x198 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB19_PAD_CTL - PAD SETTINGS - 0x19c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB20_FUNC_CTL - ALT SELECT - 0x1a0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB20_PAD_CTL - PAD SETTINGS - 0x1a4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB21_FUNC_CTL - ALT SELECT - 0x1a8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB21_PAD_CTL - PAD SETTINGS - 0x1ac - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB22_FUNC_CTL - ALT SELECT - 0x1b0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB22_PAD_CTL - PAD SETTINGS - 0x1b4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB23_FUNC_CTL - ALT SELECT - 0x1b8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB23_PAD_CTL - PAD SETTINGS - 0x1bc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB24_FUNC_CTL - ALT SELECT - 0x1c0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB24_PAD_CTL - PAD SETTINGS - 0x1c4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB25_FUNC_CTL - ALT SELECT - 0x1c8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB25_PAD_CTL - PAD SETTINGS - 0x1cc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB26_FUNC_CTL - ALT SELECT - 0x1d0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB26_PAD_CTL - PAD SETTINGS - 0x1d4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB27_FUNC_CTL - ALT SELECT - 0x1d8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB27_PAD_CTL - PAD SETTINGS - 0x1dc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB28_FUNC_CTL - ALT SELECT - 0x1e0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB28_PAD_CTL - PAD SETTINGS - 0x1e4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB29_FUNC_CTL - ALT SELECT - 0x1e8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB29_PAD_CTL - PAD SETTINGS - 0x1ec - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB30_FUNC_CTL - ALT SELECT - 0x1f0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB30_PAD_CTL - PAD SETTINGS - 0x1f4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PB31_FUNC_CTL - ALT SELECT - 0x1f8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB31_PAD_CTL - PAD SETTINGS - 0x1fc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC00_FUNC_CTL - ALT SELECT - 0x200 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC00_PAD_CTL - PAD SETTINGS - 0x204 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC01_FUNC_CTL - ALT SELECT - 0x208 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC01_PAD_CTL - PAD SETTINGS - 0x20c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC02_FUNC_CTL - ALT SELECT - 0x210 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC02_PAD_CTL - PAD SETTINGS - 0x214 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC03_FUNC_CTL - ALT SELECT - 0x218 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC03_PAD_CTL - PAD SETTINGS - 0x21c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC04_FUNC_CTL - ALT SELECT - 0x220 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC04_PAD_CTL - PAD SETTINGS - 0x224 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC05_FUNC_CTL - ALT SELECT - 0x228 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC05_PAD_CTL - PAD SETTINGS - 0x22c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC06_FUNC_CTL - ALT SELECT - 0x230 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC06_PAD_CTL - PAD SETTINGS - 0x234 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC07_FUNC_CTL - ALT SELECT - 0x238 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC07_PAD_CTL - PAD SETTINGS - 0x23c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC08_FUNC_CTL - ALT SELECT - 0x240 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC08_PAD_CTL - PAD SETTINGS - 0x244 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC09_FUNC_CTL - ALT SELECT - 0x248 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC09_PAD_CTL - PAD SETTINGS - 0x24c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC10_FUNC_CTL - ALT SELECT - 0x250 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC10_PAD_CTL - PAD SETTINGS - 0x254 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC11_FUNC_CTL - ALT SELECT - 0x258 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC11_PAD_CTL - PAD SETTINGS - 0x25c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC12_FUNC_CTL - ALT SELECT - 0x260 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC12_PAD_CTL - PAD SETTINGS - 0x264 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC13_FUNC_CTL - ALT SELECT - 0x268 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC13_PAD_CTL - PAD SETTINGS - 0x26c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC14_FUNC_CTL - ALT SELECT - 0x270 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC14_PAD_CTL - PAD SETTINGS - 0x274 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC15_FUNC_CTL - ALT SELECT - 0x278 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC15_PAD_CTL - PAD SETTINGS - 0x27c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC16_FUNC_CTL - ALT SELECT - 0x280 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC16_PAD_CTL - PAD SETTINGS - 0x284 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC17_FUNC_CTL - ALT SELECT - 0x288 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC17_PAD_CTL - PAD SETTINGS - 0x28c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC18_FUNC_CTL - ALT SELECT - 0x290 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC18_PAD_CTL - PAD SETTINGS - 0x294 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC19_FUNC_CTL - ALT SELECT - 0x298 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC19_PAD_CTL - PAD SETTINGS - 0x29c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC20_FUNC_CTL - ALT SELECT - 0x2a0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC20_PAD_CTL - PAD SETTINGS - 0x2a4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC21_FUNC_CTL - ALT SELECT - 0x2a8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC21_PAD_CTL - PAD SETTINGS - 0x2ac - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC22_FUNC_CTL - ALT SELECT - 0x2b0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC22_PAD_CTL - PAD SETTINGS - 0x2b4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC23_FUNC_CTL - ALT SELECT - 0x2b8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC23_PAD_CTL - PAD SETTINGS - 0x2bc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC24_FUNC_CTL - ALT SELECT - 0x2c0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC24_PAD_CTL - PAD SETTINGS - 0x2c4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC25_FUNC_CTL - ALT SELECT - 0x2c8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC25_PAD_CTL - PAD SETTINGS - 0x2cc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC26_FUNC_CTL - ALT SELECT - 0x2d0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC26_PAD_CTL - PAD SETTINGS - 0x2d4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC27_FUNC_CTL - ALT SELECT - 0x2d8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC27_PAD_CTL - PAD SETTINGS - 0x2dc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC28_FUNC_CTL - ALT SELECT - 0x2e0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC28_PAD_CTL - PAD SETTINGS - 0x2e4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC29_FUNC_CTL - ALT SELECT - 0x2e8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC29_PAD_CTL - PAD SETTINGS - 0x2ec - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC30_FUNC_CTL - ALT SELECT - 0x2f0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC30_PAD_CTL - PAD SETTINGS - 0x2f4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PC31_FUNC_CTL - ALT SELECT - 0x2f8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC31_PAD_CTL - PAD SETTINGS - 0x2fc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD00_FUNC_CTL - ALT SELECT - 0x300 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD00_PAD_CTL - PAD SETTINGS - 0x304 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD01_FUNC_CTL - ALT SELECT - 0x308 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD01_PAD_CTL - PAD SETTINGS - 0x30c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD02_FUNC_CTL - ALT SELECT - 0x310 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD02_PAD_CTL - PAD SETTINGS - 0x314 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD03_FUNC_CTL - ALT SELECT - 0x318 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD03_PAD_CTL - PAD SETTINGS - 0x31c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD04_FUNC_CTL - ALT SELECT - 0x320 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD04_PAD_CTL - PAD SETTINGS - 0x324 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD05_FUNC_CTL - ALT SELECT - 0x328 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD05_PAD_CTL - PAD SETTINGS - 0x32c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD06_FUNC_CTL - ALT SELECT - 0x330 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD06_PAD_CTL - PAD SETTINGS - 0x334 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD07_FUNC_CTL - ALT SELECT - 0x338 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD07_PAD_CTL - PAD SETTINGS - 0x33c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD08_FUNC_CTL - ALT SELECT - 0x340 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD08_PAD_CTL - PAD SETTINGS - 0x344 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD09_FUNC_CTL - ALT SELECT - 0x348 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD09_PAD_CTL - PAD SETTINGS - 0x34c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD10_FUNC_CTL - ALT SELECT - 0x350 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD10_PAD_CTL - PAD SETTINGS - 0x354 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD11_FUNC_CTL - ALT SELECT - 0x358 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD11_PAD_CTL - PAD SETTINGS - 0x35c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD12_FUNC_CTL - ALT SELECT - 0x360 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD12_PAD_CTL - PAD SETTINGS - 0x364 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD13_FUNC_CTL - ALT SELECT - 0x368 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD13_PAD_CTL - PAD SETTINGS - 0x36c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD14_FUNC_CTL - ALT SELECT - 0x370 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD14_PAD_CTL - PAD SETTINGS - 0x374 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD15_FUNC_CTL - ALT SELECT - 0x378 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD15_PAD_CTL - PAD SETTINGS - 0x37c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD16_FUNC_CTL - ALT SELECT - 0x380 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD16_PAD_CTL - PAD SETTINGS - 0x384 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD17_FUNC_CTL - ALT SELECT - 0x388 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD17_PAD_CTL - PAD SETTINGS - 0x38c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD18_FUNC_CTL - ALT SELECT - 0x390 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD18_PAD_CTL - PAD SETTINGS - 0x394 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD19_FUNC_CTL - ALT SELECT - 0x398 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD19_PAD_CTL - PAD SETTINGS - 0x39c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD20_FUNC_CTL - ALT SELECT - 0x3a0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD20_PAD_CTL - PAD SETTINGS - 0x3a4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD21_FUNC_CTL - ALT SELECT - 0x3a8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD21_PAD_CTL - PAD SETTINGS - 0x3ac - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD22_FUNC_CTL - ALT SELECT - 0x3b0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD22_PAD_CTL - PAD SETTINGS - 0x3b4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PD23_FUNC_CTL - ALT SELECT - 0x3b8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD23_PAD_CTL - PAD SETTINGS - 0x3bc - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX00_FUNC_CTL - ALT SELECT - 0xd00 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX00_PAD_CTL - PAD SETTINGS - 0xd04 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX01_FUNC_CTL - ALT SELECT - 0xd08 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX01_PAD_CTL - PAD SETTINGS - 0xd0c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX02_FUNC_CTL - ALT SELECT - 0xd10 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX02_PAD_CTL - PAD SETTINGS - 0xd14 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX03_FUNC_CTL - ALT SELECT - 0xd18 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX03_PAD_CTL - PAD SETTINGS - 0xd1c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX04_FUNC_CTL - ALT SELECT - 0xd20 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX04_PAD_CTL - PAD SETTINGS - 0xd24 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX05_FUNC_CTL - ALT SELECT - 0xd28 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX05_PAD_CTL - PAD SETTINGS - 0xd2c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX06_FUNC_CTL - ALT SELECT - 0xd30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX06_PAD_CTL - PAD SETTINGS - 0xd34 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PX07_FUNC_CTL - ALT SELECT - 0xd38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX07_PAD_CTL - PAD SETTINGS - 0xd3c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY00_FUNC_CTL - ALT SELECT - 0xe00 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY00_PAD_CTL - PAD SETTINGS - 0xe04 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY01_FUNC_CTL - ALT SELECT - 0xe08 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY01_PAD_CTL - PAD SETTINGS - 0xe0c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY02_FUNC_CTL - ALT SELECT - 0xe10 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY02_PAD_CTL - PAD SETTINGS - 0xe14 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY03_FUNC_CTL - ALT SELECT - 0xe18 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY03_PAD_CTL - PAD SETTINGS - 0xe1c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY04_FUNC_CTL - ALT SELECT - 0xe20 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY04_PAD_CTL - PAD SETTINGS - 0xe24 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY05_FUNC_CTL - ALT SELECT - 0xe28 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY05_PAD_CTL - PAD SETTINGS - 0xe2c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY06_FUNC_CTL - ALT SELECT - 0xe30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY06_PAD_CTL - PAD SETTINGS - 0xe34 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY07_FUNC_CTL - ALT SELECT - 0xe38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY07_PAD_CTL - PAD SETTINGS - 0xe3c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY08_FUNC_CTL - ALT SELECT - 0xe40 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY08_PAD_CTL - PAD SETTINGS - 0xe44 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY09_FUNC_CTL - ALT SELECT - 0xe48 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY09_PAD_CTL - PAD SETTINGS - 0xe4c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY10_FUNC_CTL - ALT SELECT - 0xe50 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY10_PAD_CTL - PAD SETTINGS - 0xe54 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PY11_FUNC_CTL - ALT SELECT - 0xe58 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY11_PAD_CTL - PAD SETTINGS - 0xe5c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ00_FUNC_CTL - ALT SELECT - 0xf00 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ00_PAD_CTL - PAD SETTINGS - 0xf04 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ01_FUNC_CTL - ALT SELECT - 0xf08 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ01_PAD_CTL - PAD SETTINGS - 0xf0c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ02_FUNC_CTL - ALT SELECT - 0xf10 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ02_PAD_CTL - PAD SETTINGS - 0xf14 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ03_FUNC_CTL - ALT SELECT - 0xf18 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ03_PAD_CTL - PAD SETTINGS - 0xf1c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ04_FUNC_CTL - ALT SELECT - 0xf20 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ04_PAD_CTL - PAD SETTINGS - 0xf24 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ05_FUNC_CTL - ALT SELECT - 0xf28 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ05_PAD_CTL - PAD SETTINGS - 0xf2c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ06_FUNC_CTL - ALT SELECT - 0xf30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ06_PAD_CTL - PAD SETTINGS - 0xf34 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ07_FUNC_CTL - ALT SELECT - 0xf38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ07_PAD_CTL - PAD SETTINGS - 0xf3c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ08_FUNC_CTL - ALT SELECT - 0xf40 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ08_PAD_CTL - PAD SETTINGS - 0xf44 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ09_FUNC_CTL - ALT SELECT - 0xf48 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ09_PAD_CTL - PAD SETTINGS - 0xf4c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ10_FUNC_CTL - ALT SELECT - 0xf50 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ10_PAD_CTL - PAD SETTINGS - 0xf54 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - PAD_PZ11_FUNC_CTL - ALT SELECT - 0xf58 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ11_PAD_CTL - PAD SETTINGS - 0xf5c - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - - - PIOC - PIOC - IOC - 0xf40d8000 - - - BIOC - BIOC - IOC - 0xf5010000 - - - OTPSHW - OTPSHW - OTP - 0xf4080000 - - 0x0 - 0xc08 - registers - - - - SHADOW_SHADOW000 - Fuse shadow registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW001 - Fuse shadow registers - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW002 - Fuse shadow registers - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW003 - Fuse shadow registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW004 - Fuse shadow registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW005 - Fuse shadow registers - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW006 - Fuse shadow registers - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW007 - Fuse shadow registers - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW008 - Fuse shadow registers - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW009 - Fuse shadow registers - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW010 - Fuse shadow registers - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW011 - Fuse shadow registers - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW012 - Fuse shadow registers - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW013 - Fuse shadow registers - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW014 - Fuse shadow registers - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW015 - Fuse shadow registers - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW016 - Fuse shadow registers - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW017 - Fuse shadow registers - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW018 - Fuse shadow registers - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW019 - Fuse shadow registers - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW020 - Fuse shadow registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW021 - Fuse shadow registers - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW022 - Fuse shadow registers - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW023 - Fuse shadow registers - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW024 - Fuse shadow registers - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW025 - Fuse shadow registers - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW026 - Fuse shadow registers - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW027 - Fuse shadow registers - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW028 - Fuse shadow registers - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW029 - Fuse shadow registers - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW030 - Fuse shadow registers - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW031 - Fuse shadow registers - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW032 - Fuse shadow registers - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW033 - Fuse shadow registers - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW034 - Fuse shadow registers - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW035 - Fuse shadow registers - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW036 - Fuse shadow registers - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW037 - Fuse shadow registers - 0x94 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW038 - Fuse shadow registers - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW039 - Fuse shadow registers - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW040 - Fuse shadow registers - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW041 - Fuse shadow registers - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW042 - Fuse shadow registers - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW043 - Fuse shadow registers - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW044 - Fuse shadow registers - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW045 - Fuse shadow registers - 0xb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW046 - Fuse shadow registers - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW047 - Fuse shadow registers - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW048 - Fuse shadow registers - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW049 - Fuse shadow registers - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW050 - Fuse shadow registers - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW051 - Fuse shadow registers - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW052 - Fuse shadow registers - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW053 - Fuse shadow registers - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW054 - Fuse shadow registers - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW055 - Fuse shadow registers - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW056 - Fuse shadow registers - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW057 - Fuse shadow registers - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW058 - Fuse shadow registers - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW059 - Fuse shadow registers - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW060 - Fuse shadow registers - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW061 - Fuse shadow registers - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW062 - Fuse shadow registers - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW063 - Fuse shadow registers - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW064 - Fuse shadow registers - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW065 - Fuse shadow registers - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW066 - Fuse shadow registers - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW067 - Fuse shadow registers - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW068 - Fuse shadow registers - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW069 - Fuse shadow registers - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW070 - Fuse shadow registers - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW071 - Fuse shadow registers - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW072 - Fuse shadow registers - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW073 - Fuse shadow registers - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW074 - Fuse shadow registers - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW075 - Fuse shadow registers - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW076 - Fuse shadow registers - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW077 - Fuse shadow registers - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW078 - Fuse shadow registers - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW079 - Fuse shadow registers - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW080 - Fuse shadow registers - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW081 - Fuse shadow registers - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW082 - Fuse shadow registers - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW083 - Fuse shadow registers - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW084 - Fuse shadow registers - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW085 - Fuse shadow registers - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW086 - Fuse shadow registers - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW087 - Fuse shadow registers - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW088 - Fuse shadow registers - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW089 - Fuse shadow registers - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW090 - Fuse shadow registers - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW091 - Fuse shadow registers - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW092 - Fuse shadow registers - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW093 - Fuse shadow registers - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW094 - Fuse shadow registers - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW095 - Fuse shadow registers - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW096 - Fuse shadow registers - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW097 - Fuse shadow registers - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW098 - Fuse shadow registers - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW099 - Fuse shadow registers - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW100 - Fuse shadow registers - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW101 - Fuse shadow registers - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW102 - Fuse shadow registers - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW103 - Fuse shadow registers - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW104 - Fuse shadow registers - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW105 - Fuse shadow registers - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW106 - Fuse shadow registers - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW107 - Fuse shadow registers - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW108 - Fuse shadow registers - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW109 - Fuse shadow registers - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW110 - Fuse shadow registers - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW111 - Fuse shadow registers - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW112 - Fuse shadow registers - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW113 - Fuse shadow registers - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW114 - Fuse shadow registers - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW115 - Fuse shadow registers - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW116 - Fuse shadow registers - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW117 - Fuse shadow registers - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW118 - Fuse shadow registers - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW119 - Fuse shadow registers - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW120 - Fuse shadow registers - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW121 - Fuse shadow registers - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW122 - Fuse shadow registers - 0x1e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW123 - Fuse shadow registers - 0x1ec - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW124 - Fuse shadow registers - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW125 - Fuse shadow registers - 0x1f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW126 - Fuse shadow registers - 0x1f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW127 - Fuse shadow registers - 0x1fc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK00 - Fuse shadow lock - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK01 - Fuse shadow lock - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK02 - Fuse shadow lock - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK03 - Fuse shadow lock - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK04 - Fuse shadow lock - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK05 - Fuse shadow lock - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK06 - Fuse shadow lock - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK07 - Fuse shadow lock - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_FUSE000 - Fuse Array - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE001 - Fuse Array - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE002 - Fuse Array - 0x408 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE003 - Fuse Array - 0x40c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE004 - Fuse Array - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE005 - Fuse Array - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE006 - Fuse Array - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE007 - Fuse Array - 0x41c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE008 - Fuse Array - 0x420 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE009 - Fuse Array - 0x424 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE010 - Fuse Array - 0x428 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE011 - Fuse Array - 0x42c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE012 - Fuse Array - 0x430 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE013 - Fuse Array - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE014 - Fuse Array - 0x438 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE015 - Fuse Array - 0x43c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE016 - Fuse Array - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE017 - Fuse Array - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE018 - Fuse Array - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE019 - Fuse Array - 0x44c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE020 - Fuse Array - 0x450 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE021 - Fuse Array - 0x454 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE022 - Fuse Array - 0x458 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE023 - Fuse Array - 0x45c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE024 - Fuse Array - 0x460 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE025 - Fuse Array - 0x464 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE026 - Fuse Array - 0x468 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE027 - Fuse Array - 0x46c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE028 - Fuse Array - 0x470 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE029 - Fuse Array - 0x474 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE030 - Fuse Array - 0x478 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE031 - Fuse Array - 0x47c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE032 - Fuse Array - 0x480 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE033 - Fuse Array - 0x484 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE034 - Fuse Array - 0x488 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE035 - Fuse Array - 0x48c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE036 - Fuse Array - 0x490 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE037 - Fuse Array - 0x494 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE038 - Fuse Array - 0x498 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE039 - Fuse Array - 0x49c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE040 - Fuse Array - 0x4a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE041 - Fuse Array - 0x4a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE042 - Fuse Array - 0x4a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE043 - Fuse Array - 0x4ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE044 - Fuse Array - 0x4b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE045 - Fuse Array - 0x4b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE046 - Fuse Array - 0x4b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE047 - Fuse Array - 0x4bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE048 - Fuse Array - 0x4c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE049 - Fuse Array - 0x4c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE050 - Fuse Array - 0x4c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE051 - Fuse Array - 0x4cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE052 - Fuse Array - 0x4d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE053 - Fuse Array - 0x4d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE054 - Fuse Array - 0x4d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE055 - Fuse Array - 0x4dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE056 - Fuse Array - 0x4e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE057 - Fuse Array - 0x4e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE058 - Fuse Array - 0x4e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE059 - Fuse Array - 0x4ec - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE060 - Fuse Array - 0x4f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE061 - Fuse Array - 0x4f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE062 - Fuse Array - 0x4f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE063 - Fuse Array - 0x4fc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE064 - Fuse Array - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE065 - Fuse Array - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE066 - Fuse Array - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE067 - Fuse Array - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE068 - Fuse Array - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE069 - Fuse Array - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE070 - Fuse Array - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE071 - Fuse Array - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE072 - Fuse Array - 0x520 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE073 - Fuse Array - 0x524 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE074 - Fuse Array - 0x528 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE075 - Fuse Array - 0x52c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE076 - Fuse Array - 0x530 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE077 - Fuse Array - 0x534 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE078 - Fuse Array - 0x538 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE079 - Fuse Array - 0x53c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE080 - Fuse Array - 0x540 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE081 - Fuse Array - 0x544 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE082 - Fuse Array - 0x548 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE083 - Fuse Array - 0x54c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE084 - Fuse Array - 0x550 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE085 - Fuse Array - 0x554 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE086 - Fuse Array - 0x558 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE087 - Fuse Array - 0x55c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE088 - Fuse Array - 0x560 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE089 - Fuse Array - 0x564 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE090 - Fuse Array - 0x568 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE091 - Fuse Array - 0x56c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE092 - Fuse Array - 0x570 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE093 - Fuse Array - 0x574 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE094 - Fuse Array - 0x578 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE095 - Fuse Array - 0x57c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE096 - Fuse Array - 0x580 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE097 - Fuse Array - 0x584 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE098 - Fuse Array - 0x588 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE099 - Fuse Array - 0x58c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE100 - Fuse Array - 0x590 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE101 - Fuse Array - 0x594 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE102 - Fuse Array - 0x598 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE103 - Fuse Array - 0x59c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE104 - Fuse Array - 0x5a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE105 - Fuse Array - 0x5a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE106 - Fuse Array - 0x5a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE107 - Fuse Array - 0x5ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE108 - Fuse Array - 0x5b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE109 - Fuse Array - 0x5b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE110 - Fuse Array - 0x5b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE111 - Fuse Array - 0x5bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE112 - Fuse Array - 0x5c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE113 - Fuse Array - 0x5c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE114 - Fuse Array - 0x5c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE115 - Fuse Array - 0x5cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE116 - Fuse Array - 0x5d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE117 - Fuse Array - 0x5d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE118 - Fuse Array - 0x5d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE119 - Fuse Array - 0x5dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE120 - Fuse Array - 0x5e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE121 - Fuse Array - 0x5e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE122 - Fuse Array - 0x5e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE123 - Fuse Array - 0x5ec - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE124 - Fuse Array - 0x5f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE125 - Fuse Array - 0x5f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE126 - Fuse Array - 0x5f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE127 - Fuse Array - 0x5fc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK00 - Fuse lock - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK01 - Fuse lock - 0x604 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK02 - Fuse lock - 0x608 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK03 - Fuse lock - 0x60c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK04 - Fuse lock - 0x610 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK05 - Fuse lock - 0x614 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK06 - Fuse lock - 0x618 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK07 - Fuse lock - 0x61c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - REGION_LOAD_REGION0 - LOAD region - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - REGION_LOAD_REGION1 - LOAD region - 0xa24 - 32 - 0x00001008 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - REGION_LOAD_REGION2 - LOAD region - 0xa28 - 32 - 0x00000010 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - REGION_LOAD_REGION3 - LOAD region - 0xa2c - 32 - 0x00000000 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf40c8000 - - - PPOR - PPOR - PPOR - 0xf40c0000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOT - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_COLD - reset type attribute - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PMU - 0xf40c4000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0001044C - 0x00010FFF - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x00B010B0 - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: trun off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00B010B0 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000000 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-write - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - ouput over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x00EF1C6E - 0x073F007F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_AUTOLP - enable auto enter low power mode -0: do not enter low power mode -1: enter low power mode if current is detected low - 4 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00EF1C6E - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: clock gated according to low power flow -10: clock is always off -11: clock is always on -bit0-1: fuse -bit2-3: sram -bit4-5: vad -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:debug - 0 - 32 - read-write - - - - - DEBUG_STOP - Debug stop config - 0x50 - 32 - 0x00000001 - 0x00000003 - - - CPU1 - Stop peripheral when CPU1 enter debug mode -0: peripheral keep running when CPU1 in debug mode -1: peripheral enter debug mode when CPU1 enter debug - 1 - 1 - read-write - - - CPU0 - Stop peripheral when CPU0 enter debug mode -0: peripheral keep running when CPU0 in debug mode -1: peripheral enter debug mode when CPU0 enter debug - 0 - 1 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000316 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PSEC - PSEC - PSEC - 0xf40cc000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf40d0000 - - 0x0 - 0x48 - registers - - - - MONITOR_GLITCH0_CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_GLITCH0_STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_GLITCH1_CONTROL - Glitch and clock monitor control - 0x8 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_GLITCH1_STATUS - Glitch and clock monitor status - 0xc - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_CONTROL - Glitch and clock monitor control - 0x10 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_STATUS - Glitch and clock monitor status - 0x14 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_CLOCK1_CONTROL - Glitch and clock monitor control - 0x18 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_CLOCK1_STATUS - Glitch and clock monitor status - 0x1c - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - IRQ_FLAG - No description avaiable - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description avaiable - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - PGPR - PGPR - PGPR - 0xf40d4000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - PLLCTLV2 - PLLCTLV2 - PLLCTLV2 - 0xf4100000 - - 0x0 - 0x244 - registers - - - - XTAL - OSC configuration - 0x0 - 32 - 0x0001FFFF - 0xB00FFFFF - - - BUSY - Busy flag -0: Oscillator is working or shutdown -1: Oscillator is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of RC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - PLL_PLL0_MFI - PLL0 multiple register - 0x80 - 32 - 0x00000010 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - PLL_PLL0_MFN - PLL0 fraction numerator register - 0x84 - 32 - 0x09896800 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - PLL_PLL0_MFD - PLL0 fraction demoninator register - 0x88 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - PLL_PLL0_SS_STEP - PLL0 spread spectrum step register - 0x8c - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - PLL_PLL0_SS_STOP - PLL0 spread spectrum stop register - 0x90 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - PLL_PLL0_CONFIG - PLL0 confguration register - 0x94 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - PLL_PLL0_LOCKTIME - PLL0 lock time register - 0x98 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - PLL_PLL0_STEPTIME - PLL0 step time register - 0x9c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - PLL_PLL0_ADVANCED - PLL0 advance configuration register - 0xa0 - 32 - 0x00000000 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - PLL_PLL0_DIV0 - PLL0 divider output 0 configuration register - 0xc0 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL0_DIV1 - PLL0 divider output 1 configuration register - 0xc4 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL0_DIV2 - PLL0 divider output 2 configuration register - 0xc8 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL1_MFI - PLL1 multiple register - 0x100 - 32 - 0x00000018 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - PLL_PLL1_MFN - PLL1 fraction numerator register - 0x104 - 32 - 0x00000000 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - PLL_PLL1_MFD - PLL1 fraction demoninator register - 0x108 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - PLL_PLL1_SS_STEP - PLL1 spread spectrum step register - 0x10c - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - PLL_PLL1_SS_STOP - PLL1 spread spectrum stop register - 0x110 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - PLL_PLL1_CONFIG - PLL1 confguration register - 0x114 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - PLL_PLL1_LOCKTIME - PLL1 lock time register - 0x118 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - PLL_PLL1_STEPTIME - PLL1 step time register - 0x11c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - PLL_PLL1_ADVANCED - PLL1 advance configuration register - 0x120 - 32 - 0x000009C4 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - PLL_PLL1_DIV0 - PLL1 divider output 0 configuration register - 0x140 - 32 - 0x00000001 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL1_DIV1 - PLL1 divider output 1 configuration register - 0x144 - 32 - 0x00000004 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL1_DIV2 - PLL1 divider output 0 configuration register - 0x148 - 32 - 0x00000001 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL2_MFI - PLL2 multiple register - 0x180 - 32 - 0x0000001E - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - PLL_PLL2_MFN - PLL2 fraction numerator register - 0x184 - 32 - 0x00182B80 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - PLL_PLL2_MFD - PLL2 fraction demoninator register - 0x188 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - PLL_PLL2_SS_STEP - PLL2 spread spectrum step register - 0x18c - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - PLL_PLL2_SS_STOP - PLL2 spread spectrum stop register - 0x190 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - PLL_PLL2_CONFIG - PLL2 confguration register - 0x194 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - PLL_PLL2_LOCKTIME - PLL2 lock time register - 0x198 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - PLL_PLL2_STEPTIME - PLL2 step time register - 0x19c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - PLL_PLL2_ADVANCED - PLL2 advance configuration register - 0x1a0 - 32 - 0x000009C4 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - PLL_PLL2_DIV0 - PLL2 divider output 0 configuration register - 0x1c0 - 32 - 0x00000002 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL2_DIV1 - PLL2 divider output 1 configuration register - 0x1c4 - 32 - 0x00000003 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - PLL_PLL2_DIV2 - PLL2 divider output 0 configuration register - 0x1c8 - 32 - 0x00000002 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - - - TSNS - TSNS - TSNS - 0xf4104000 - - 0x0 - 0x3c - registers - - - - T - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Signed number of temperature in 256 x celsius degree - 0 - 32 - read-only - - - - - TMAX - No description avaiable - 0x4 - 32 - 0x007FFFFF - 0xFFFFFFFF - - - T - maximum temperature ever found - 0 - 32 - read-only - - - - - TMIN - No description avaiable - 0x8 - 32 - 0xFF800000 - 0xFFFFFFFF - - - T - minimum temperature ever found - 0 - 32 - read-only - - - - - AGE - No description avaiable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - AGE - age of T register in 24MHz clock cycles - 0 - 32 - read-only - - - - - STATUS - No description avaiable - 0x10 - 32 - 0x00000000 - 0x80000001 - - - VALID - indicate value in T is valid or not -0: not valid -1:valid - 31 - 1 - read-only - - - TRIGGER - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - 0 - 1 - read-write - - - - - CONFIG - No description avaiable - 0x14 - 32 - 0x00300300 - 0xC3FF0713 - - - IRQ_EN - Enable interrupt - 31 - 1 - read-write - - - RST_EN - Enable reset - 30 - 1 - read-write - - - COMPARE_MIN_EN - Enable compare for minimum temperature - 25 - 1 - read-write - - - COMPARE_MAX_EN - Enable compare for maximum temperature - 24 - 1 - read-write - - - SPEED - cycles of a progressive step in 24M clock, valide from 24-255, default 63 -24: 24 cycle for a step -25: 25 cycle for a step -26: 26 cycle for a step -... -255: 255 cycle for a step - 16 - 8 - read-write - - - AVERAGE - Average time, defaul tin 2 -0: measure and return -1: twice and average -2: 4 times and average(default) -. . . -7: 128 times and average - 8 - 3 - read-write - - - CONTINUOUS - continuous mode that keep sampling temperature peridically -0: trigger mode -1: continuous mode - 4 - 1 - read-write - - - ASYNC - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value -0: active mode -1: Async mode - 1 - 1 - read-write - - - ENABLE - Enable temperature -0: disable, temperature sensor is shut down -1: enable. Temperature sensor enabled - 0 - 1 - read-write - - - - - VALIDITY - No description avaiable - 0x18 - 32 - 0x016E3600 - 0xFFFFFFFF - - - VALIDITY - time for temperature values to expire in 24M clock cycles - 0 - 32 - read-write - - - - - FLAG - No description avaiable - 0x1c - 32 - 0x00000000 - 0x00330001 - - - RECORD_MIN_CLR - Clear minimum recorder of temerature, write 1 to clear - 21 - 1 - read-write - - - RECORD_MAX_CLR - Clear maximum recorder of temerature, write 1 to clear - 20 - 1 - read-write - - - UNDER_TEMP - Clear under temperature status, write 1 to clear - 17 - 1 - read-write - - - OVER_TEMP - Clear over temperature status, write 1 to clear - 16 - 1 - read-write - - - IRQ - IRQ flag, write 1 to clear - 0 - 1 - read-write - - - - - UPPER_LIM_IRQ - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_IRQ - No description avaiable - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - UPPER_LIM_RST - No description avaiable - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_RST - No description avaiable - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - ASYNC - No description avaiable - 0x30 - 32 - 0x00000000 - 0x010107FF - - - ASYNC_TYPE - Compare hotter than or colder than in asynchoronous mode -0: hotter than -1: colder than - 24 - 1 - read-write - - - POLARITY - No description avaiable - 16 - 1 - read-write - - - VALUE - Value of async mode to compare - 0 - 11 - read-write - - - - - ADVAN - No description avaiable - 0x38 - 32 - 0x00000000 - 0x03010003 - - - ASYNC_IRQ - interrupt status of asynchronous mode - 25 - 1 - read-only - - - ACTIVE_IRQ - interrupt status of active mode - 24 - 1 - read-only - - - SAMPLING - temperature sampling is working - 16 - 1 - read-only - - - NEG_ONLY - use negative compare polarity only - 1 - 1 - read-write - - - POS_ONLY - use positive compare polarity only - 0 - 1 - read-write - - - - - - - BPOR - BPOR - BPOR - 0xf5004000 - - 0x0 - 0x10 - registers - - - - POR_CAUSE - Power on cause - 0x0 - 32 - 0x00000000 - 0x0000001F - - - CAUSE - Power on cause, each bit represnts one cause, write 1 to clear each bit -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_SELECT - Power on select - 0x4 - 32 - 0x00000000 - 0x0000001F - - - SELECT - Power on cause select, each bit represnts one cause, value 1 enables corresponding cause -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_CONFIG - Power on reset config - 0x8 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - POR_CONTROL - Power down control - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - COUNTER - Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - 0 - 16 - read-write - - - - - - - BCFG - BCFG - TRIM - 0xf5008000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x811F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf500c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf5018000 - - 0x0 - 0x20 - registers - - - - BATT_GPR0 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR1 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR2 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR3 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR4 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR5 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR6 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR7 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - BSEC - BSEC - BSEC - 0xf5040000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - RTC - RTC - RTC - 0xf5044000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - BKEY - BKEY - BKEY - 0xf5048000 - - 0x0 - 0x4c - registers - - - - KEY_0_DATA_0 - Key data - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_1 - Key data - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_2 - Key data - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_3 - Key data - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_4 - Key data - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_5 - Key data - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_6 - Key data - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_7 - Key data - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_0 - Key data - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_1 - Key data - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_2 - Key data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_3 - Key data - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_4 - Key data - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_5 - Key data - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_6 - Key data - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_7 - Key data - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - ECC_KEY0 - Key ECC and access control - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - ECC_KEY1 - Key 1 ECC and access control - 0x44 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf504c000 - - 0x0 - 0x1c - registers - - - - MONITOR_GLITCH0_CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_GLITCH0_STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_CONTROL - Glitch and clock monitor control - 0x10 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_STATUS - Glitch and clock monitor status - 0x14 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - TAMP - TAMP - TAMP - 0xf5050000 - - 0x0 - 0x88 - registers - - - - TAMP_TAMP0_CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP0_POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP0_LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP1_CONTROL - Tamper1 control - 0x10 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP1_POLY - Tamper1 Polynomial of LFSR - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP1_LFSR - Tamper1 LFSR shift register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP2_CONTROL - Tamper2 control - 0x20 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP2_POLY - Tamper2 Polynomial of LFSR - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP2_LFSR - Tamper2 LFSR shift register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP3_CONTROL - Tamper3 control - 0x30 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP3_POLY - Tamper3 Polynomial of LFSR - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP3_LFSR - Tamper3 LFSR shift register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disapeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf5054000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/SConscript index 985fd5d7e6..5717c3e631 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/SConscript +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/SConscript @@ -15,6 +15,7 @@ src = Split(''' hpm_l1c_drv.c hpm_sysctl_drv.c hpm_clock_drv.c + hpm_otp_drv.c boot/hpm_bootheader.c ''') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c index 30c2edc202..57cdf5aa2e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h index c2bf30d0b0..d7f22fd824 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h index 8d6e337a35..a85b8eb003 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -55,27 +55,5 @@ #define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -/* IOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -/* IOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_BATT_IOMUX_H */ \ No newline at end of file +#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h new file mode 100644 index 0000000000..00dfb6fcf3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BCFG_DRV_H +#define HPM_BCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_bcfg_regs.h" + +/** + * + * @brief BCFG driver APIs + * @defgroup bcfg_interface BCFG driver APIs + * @ingroup io_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief disable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief enable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +/** + * @brief disable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BCFG_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h new file mode 100644 index 0000000000..50cbd1b455 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BCFG_H +#define HPM_BCFG_H + +typedef struct { + __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ + __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ + __RW uint32_t CLK_CFG; /* 0x10: Clock config */ +} BCFG_Type; + + +/* Bitfield definition for register: VBG_CFG */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) +#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) +#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) +#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) + +/* + * LP_MODE (RW) + * + * Bandgap works in low power mode + * 0: not in low power mode + * 1: bandgap work in low power mode + */ +#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) +#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) +#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) +#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Bandgap works in power save mode + * 0: not in power save mode + * 1: bandgap work in power save mode + */ +#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) +#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) +#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) +#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) + +/* + * VBG_1P0 (RW) + * + * Bandgap 1.0V output trim + */ +#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) +#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) +#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) +#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) + +/* + * VBG_P65 (RW) + * + * Bandgap 0.65V output trim + */ +#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) +#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) +#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) +#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) + +/* + * VBG_P50 (RW) + * + * Bandgap 0.50V output trim + */ +#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) +#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) +#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) +#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) + +/* Bitfield definition for register: IRC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) +#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: XTAL32K_CFG */ +/* + * HYST_EN (RW) + * + * crystal 32k hysteres enable + */ +#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) +#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) +#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) +#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) + +/* + * GMSEL (RW) + * + * crystal 32k gm selection + */ +#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) +#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) +#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) +#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) + +/* + * CFG (RW) + * + * crystal 32k config + */ +#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) +#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) +#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) +#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) + +/* + * AMP (RW) + * + * crystal 32k amplifier + */ +#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) +#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) +#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) +#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) + +/* Bitfield definition for register: CLK_CFG */ +/* + * XTAL_SEL (RO) + * + * crystal selected + */ +#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) +#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) +#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) + +/* + * KEEP_IRC (RW) + * + * force irc32k run + */ +#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) +#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) +#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) +#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) + +/* + * FORCE_XTAL (RW) + * + * force switch to crystal + */ +#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) +#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) +#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) +#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) + + + + +#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h new file mode 100644 index 0000000000..46bb7beb07 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BGPR_H +#define HPM_BGPR_H + +typedef struct { + __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ + __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ + __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ + __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ + __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ + __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ + __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ + __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ +} BGPR_Type; + + +/* Bitfield definition for register: BATT_GPR0 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR0_GPR_SHIFT (0U) +#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) +#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR1 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR1_GPR_SHIFT (0U) +#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) +#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR2 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR2_GPR_SHIFT (0U) +#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) +#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR3 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR3_GPR_SHIFT (0U) +#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) +#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR4 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR4_GPR_SHIFT (0U) +#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) +#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR5 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR5_GPR_SHIFT (0U) +#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) +#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR6 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR6_GPR_SHIFT (0U) +#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) +#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR7 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR7_GPR_SHIFT (0U) +#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) +#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) + + + + +#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_drv.h new file mode 100644 index 0000000000..e37bac24b1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_drv.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BPOR_DRV_H +#define HPM_BPOR_DRV_H + +#include "hpm_common.h" +#include "hpm_bpor_regs.h" + +/** + * + * @brief BPOR driver APIs + * @defgroup bpor_interface BPOR driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +/** @brief Define BPOR power on cause */ +typedef enum { + bpor_power_on_cause_wbutn = 1 << 0, + bpor_power_on_cause_safety_violation = 1 << 1, + bpor_power_on_cause_rtc_0 = 1 << 2, + bpor_power_on_cause_rtc_1 = 1 << 3, + bpor_power_on_cause_gpio = 1 << 4 +} bpor_power_on_cause_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get power on cause + * + * @param[in] ptr BPOR base address + * @retval POR_CAUSE register value + */ +static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) +{ + return ptr->POR_CAUSE; +} + +/** + * @brief Clear power on cause + * + * @param[in] ptr BPOR base address + * @param[in] mask cause status to be cleared + */ +static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) +{ + ptr->POR_CAUSE |= mask; +} + +/** + * @brief enable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be enabled + */ +static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT |= cause; +} + +/** + * @brief disable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be disabled + */ +static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT &= ~cause; +} + +/** + * @brief Set power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be used + */ +static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) +{ + ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; +} + +/** + * @brief Enable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Disable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Set power down counter + * + * @param[in] ptr BPOR base address + * @param[in] counter counter value + */ +static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) +{ + ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h new file mode 100644 index 0000000000..32147d05a2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BPOR_H +#define HPM_BPOR_H + +typedef struct { + __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ + __RW uint32_t POR_SELECT; /* 0x4: Power on select */ + __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ + __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ +} BPOR_Type; + + +/* Bitfield definition for register: POR_CAUSE */ +/* + * CAUSE (RW) + * + * Power on cause, each bit represnts one cause, write 1 to clear each bit + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) +#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) +#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) +#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: POR_SELECT */ +/* + * SELECT (RW) + * + * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) +#define BPOR_POR_SELECT_SELECT_SHIFT (0U) +#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) +#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) + +/* Bitfield definition for register: POR_CONFIG */ +/* + * RETENTION (RW) + * + * retention battery domain setting + * 0: battery reset on reset pin reset happen + * 1: battery domain retention when reset pin reset happen + */ +#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) +#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) +#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) +#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) + +/* Bitfield definition for register: POR_CONTROL */ +/* + * COUNTER (RW) + * + * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + */ +#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) +#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) +#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) +#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) + + + + +#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c index f9e821af6d..f800e4ac59 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,8 +9,6 @@ #include "hpm_soc.h" #include "hpm_common.h" #include "hpm_pllctlv2_drv.h" -#include "hpm_csr_regs.h" -#include "riscv/riscv_core.h" /*********************************************************************************************************************** * Definitions **********************************************************************************************************************/ @@ -354,7 +352,7 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); return status_success; } @@ -368,13 +366,13 @@ hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src != clk_dac_src_ana) && (src != clk_dac_src_ahb)) { + if ((src != clk_dac_src_ana) || (src != clk_dac_src_ahb)) { return status_clk_src_invalid; } uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); HPM_SYSCTL->DACCLK[node_or_instance] = - (HPM_SYSCTL->DACCLK[node_or_instance] & SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); + (HPM_SYSCTL->DACCLK[node_or_instance] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); return status_success; } @@ -388,13 +386,13 @@ hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src != clk_i2s_src_aud0) && (src != clk_i2s_src_aud1)) { + if ((src != clk_i2s_src_aud0) || (src != clk_i2s_src_aud1)) { return status_clk_src_invalid; } uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); HPM_SYSCTL->I2SCLK[node_or_instance] = - (HPM_SYSCTL->I2SCLK[node_or_instance] & SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); + (HPM_SYSCTL->I2SCLK[node_or_instance] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); return status_success; } @@ -445,10 +443,11 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint * changes, the AXI and AHB clock changes accordingly, here the driver ensures the * AXI and AHB bus clock frequency is in valid range. */ - uint32_t expected_freq = get_frequency_for_source(src) / div; + clock_source_t source = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + uint32_t expected_freq = get_frequency_for_source(source) / div; uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, src, div, axi_sub_div, ahb_sub_div); + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, source, div, axi_sub_div, ahb_sub_div); } else { status = status_clk_shared_cpu0; } @@ -522,39 +521,23 @@ void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) } } - -static uint64_t get_core_mcycle(void) -{ - uint64_t result; - uint32_t resultl_first = read_csr(CSR_CYCLE); - uint32_t resulth = read_csr(CSR_CYCLEH); - uint32_t resultl_second = read_csr(CSR_CYCLE); - if (resultl_first < resultl_second) { - result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ - } else { - resulth = read_csr(CSR_MCYCLEH); - result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ - } - return result; - } - void clock_cpu_delay_us(uint32_t us) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } void clock_cpu_delay_ms(uint32_t ms) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } void clock_update_core_clock(void) { hpm_core_clock = clock_get_frequency(clock_cpu0); -} \ No newline at end of file +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h index 9841dac595..b0bada18b2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #include "hpm_common.h" #include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" /** @@ -98,7 +99,7 @@ typedef enum _clock_sources { typedef enum _clock_name { clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_dram = MAKE_CLOCK_NAME(sysctl_resource_dram, CLK_SRC_GROUP_COMMON, clock_node_dram), + clock_femc = MAKE_CLOCK_NAME(sysctl_resource_femc, CLK_SRC_GROUP_COMMON, clock_node_femc), clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), clock_xpi1 = MAKE_CLOCK_NAME(sysctl_resource_xpi1, CLK_SRC_GROUP_COMMON, clock_node_xpi1), clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), @@ -180,14 +181,14 @@ typedef enum _clock_name { clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), - clk_pll0clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), - clk_pll0clk2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), - clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), - clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), - clk_pll2clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), - clk_pll2clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), + clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), + clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 6), + clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 7), } clock_name_t; #ifdef __cplusplus diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h index 72f6fb746f..cc29018e11 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -6509,4 +6509,4 @@ #define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) -#endif /* HPM_CSR_H */ \ No newline at end of file +#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h new file mode 100644 index 0000000000..640355344e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_regs.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_H +#define HPM_DMAMUX_H + +typedef struct { + __RW uint32_t MUXCFG[16]; /* 0x0 - 0x3C: HDMA MUX0 Configuration */ +} DMAMUX_Type; + + +/* Bitfield definition for register array: MUXCFG */ +/* + * ENABLE (RW) + * + * DMA Mux Channel Enable + * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be + * used to disable or reconfigure a DMA channel. + * 0b - DMA Mux channel is disabled + * 1b - DMA Mux channel is enabled + */ +#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) +#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) +#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) +#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) + +/* + * SOURCE (RW) + * + * DMA Channel Source + * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + */ +#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) +#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) +#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) + + + +/* MUXCFG register group index macro definition */ +#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) +#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) +#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) +#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) +#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) +#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) +#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) +#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) +#define DMAMUX_MUXCFG_XDMA_MUX0 (8UL) +#define DMAMUX_MUXCFG_XDMA_MUX1 (9UL) +#define DMAMUX_MUXCFG_XDMA_MUX2 (10UL) +#define DMAMUX_MUXCFG_XDMA_MUX3 (11UL) +#define DMAMUX_MUXCFG_XDMA_MUX4 (12UL) +#define DMAMUX_MUXCFG_XDMA_MUX5 (13UL) +#define DMAMUX_MUXCFG_XDMA_MUX6 (14UL) +#define DMAMUX_MUXCFG_XDMA_MUX7 (15UL) + + +#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h index 6d595d073f..3ded193a05 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -80,4 +80,4 @@ -#endif /* HPM_DMAMUX_SRC_H */ \ No newline at end of file +#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h index 449405b137..c85abfc8ec 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,6 +13,46 @@ extern "C" { #endif +static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL2 &= ~ENET_CTRL2_ENET0_PHY_INF_SEL_MASK; + ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type); + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL2 |= ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL2 &= ~ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) { hpm_stat_t stat = status_fail; @@ -40,22 +80,8 @@ static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) return stat; } -static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_PHY_INF_SEL_MASK; - ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type); - } else { - return status_invalid_argument; - } - - return stat; -} - #if defined __cplusplus } /* __cplusplus */ #endif -#endif /* HPM_ENET_SOC_DRV_H */ \ No newline at end of file +#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h index 3ac71c4c38..414dca8ee1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,10 +24,10 @@ typedef struct { * 0: fields can be changed * 1: fields locked to current value, not changeable */ -#define GPIOM_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_PIN_LOCK_SHIFT (31U) -#define GPIOM_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_PIN_LOCK_SHIFT) & GPIOM_PIN_LOCK_MASK) -#define GPIOM_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_PIN_LOCK_MASK) >> GPIOM_PIN_LOCK_SHIFT) +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) /* * HIDE (RW) @@ -36,10 +36,10 @@ typedef struct { * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 * bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio */ -#define GPIOM_PIN_HIDE_MASK (0x300U) -#define GPIOM_PIN_HIDE_SHIFT (8U) -#define GPIOM_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_PIN_HIDE_SHIFT) & GPIOM_PIN_HIDE_MASK) -#define GPIOM_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_PIN_HIDE_MASK) >> GPIOM_PIN_HIDE_SHIFT) +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0x300U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) /* * SELECT (RW) @@ -48,10 +48,10 @@ typedef struct { * 0: soc gpio0; * 1: cpu0 fastgpio */ -#define GPIOM_PIN_SELECT_MASK (0x1U) -#define GPIOM_PIN_SELECT_SHIFT (0U) -#define GPIOM_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_PIN_SELECT_SHIFT) & GPIOM_PIN_SELECT_MASK) -#define GPIOM_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_PIN_SELECT_MASK) >> GPIOM_PIN_SELECT_SHIFT) +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x1U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) @@ -98,4 +98,4 @@ typedef struct { #define GPIOM_ASSIGN_GPIOZ (15UL) -#endif /* HPM_GPIOM_H */ \ No newline at end of file +#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h index e4b460359a..1377f27d61 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h index afbf13d54f..e2305ab7ed 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -37,13 +37,24 @@ ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) } /** - * @brief Disable global IRQ with mask + * @brief Disable global IRQ with mask return mstatus * * @param[in] mask interrupt mask to be disabled + * @retval current mstatus value before irq disabled */ -ATTR_ALWAYS_INLINE static inline void disable_global_irq(uint32_t mask) +ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) { - clear_csr(CSR_MSTATUS, mask); + return read_clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); } /** @@ -115,15 +126,27 @@ ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) } /** - * @brief Disable global IRQ with mask for supervisor mode + * @brief Disable global IRQ with mask and return sstatus for supervisor mode * * @param[in] mask interrupt mask to be disabled + * @retval current sstatus value before irq mask is disabled */ -ATTR_ALWAYS_INLINE static inline void disable_s_global_irq(uint32_t mask) +ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) { - clear_csr(CSR_SSTATUS, mask); + return read_clear_csr(CSR_SSTATUS, mask); } +/** + * @brief Restore global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) +{ + set_csr(CSR_SSTATUS, mask); +} + + /** * @brief Disable IRQ from interrupt controller for supervisor mode * @@ -498,7 +521,7 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) */ #define RESTORE_CSR(r) write_csr(r, __##r); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) #else @@ -523,71 +546,129 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) #endif #ifdef __riscv_flen -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP) + 21 FPU caller registers */ -#define CONTEXT_REG_NUM (4*(16 + 4 + 1 + 21)) +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) +#endif + #else /* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ -#define CONTEXT_REG_NUM (4*(16 + 4 + 1)) +#define CONTEXT_REG_NUM (4 * (16 + 4)) #endif #ifdef __riscv_flen /* * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack */ +#if __riscv_flen == 32 #define SAVE_FPU_CONTEXT() { \ - __asm volatile("fsw ft0, 21*4(sp) \n\ - fsw ft1, 22*4(sp) \n\ - fsw ft2, 23*4(sp) \n\ - fsw ft3, 24*4(sp) \n\ - fsw ft4, 25*4(sp) \n\ - fsw ft5, 26*4(sp) \n\ - fsw ft6, 27*4(sp) \n\ - fsw ft7, 28*4(sp) \n\ - fsw fa0, 29*4(sp) \n\ - fsw fa1, 30*4(sp) \n\ - fsw fa2, 31*4(sp) \n\ - fsw fa3, 32*4(sp) \n\ - fsw fa4, 33*4(sp) \n\ - fsw fa5, 34*4(sp) \n\ - fsw fa6, 35*4(sp) \n\ - fsw fa7, 36*4(sp) \n\ - fsw ft8, 37*4(sp) \n\ - fsw ft9, 38*4(sp) \n\ - fsw ft10, 39*4(sp) \n\ - fsw ft11, 40*4(sp) \n\ - frsr t6 \n\ - sw t6, 41*4(sp) \n");\ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ } /* * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack */ #define RESTORE_FPU_CONTEXT() { \ - __asm volatile("flw ft0, 21*4(sp) \n\ - flw ft1, 22*4(sp) \n\ - flw ft2, 23*4(sp) \n\ - flw ft3, 24*4(sp) \n\ - flw ft4, 25*4(sp) \n\ - flw ft5, 26*4(sp) \n\ - flw ft6, 27*4(sp) \n\ - flw ft7, 28*4(sp) \n\ - flw fa0, 29*4(sp) \n\ - flw fa1, 30*4(sp) \n\ - flw fa2, 31*4(sp) \n\ - flw fa3, 32*4(sp) \n\ - flw fa4, 33*4(sp) \n\ - flw fa5, 34*4(sp) \n\ - flw fa6, 35*4(sp) \n\ - flw fa7, 36*4(sp) \n\ - flw ft8, 37*4(sp) \n\ - flw ft9, 38*4(sp) \n\ - flw ft10, 39*4(sp) \n\ - flw ft11, 40*4(sp) \n\ - lw t6, 41*4(sp) \n\ - fssr t6, t6 \n");\ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ } +#else /*__riscv_flen == 64*/ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif #else #define SAVE_FPU_CONTEXT() #define RESTORE_FPU_CONTEXT() @@ -598,66 +679,88 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) */ #define SAVE_CALLER_CONTEXT() { \ __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("sw ra, 0*4(sp) \n\ - sw t0, 1*4(sp) \n\ - sw t1, 2*4(sp) \n\ - sw t2, 3*4(sp) \n\ - sw a0, 4*4(sp) \n\ - sw a1, 5*4(sp) \n\ - sw a2, 6*4(sp) \n\ - sw a3, 7*4(sp) \n\ - sw a4, 8*4(sp) \n\ - sw a5, 9*4(sp) \n\ - sw a6, 10*4(sp) \n\ - sw a7, 11*4(sp) \n\ - sw t3, 12*4(sp) \n\ - sw t4, 13*4(sp) \n\ - sw t5, 14*4(sp) \n\ - sw t6, 15*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ } /** * @brief Restore the caller registers based on the RISC-V ABI specification */ #define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("lw ra, 0*4(sp) \n\ - lw t0, 1*4(sp) \n\ - lw t1, 2*4(sp) \n\ - lw t2, 3*4(sp) \n\ - lw a0, 4*4(sp) \n\ - lw a1, 5*4(sp) \n\ - lw a2, 6*4(sp) \n\ - lw a3, 7*4(sp) \n\ - lw a4, 8*4(sp) \n\ - lw a5, 9*4(sp) \n\ - lw a6, 10*4(sp) \n\ - lw a7, 11*4(sp) \n\ - lw t3, 12*4(sp) \n\ - lw t4, 13*4(sp) \n\ - lw t5, 14*4(sp) \n\ - lw t6, 15*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ } +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fssr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + #ifdef __riscv_dsp /* * Save DSP context - * NOTE: To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + * NOTE: DSP context registers are stored at word offset 41 in the stack */ #define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrr t6, ucode\n\ - sw t6, 20*4(sp)\n"); \ + __asm volatile("rdov s0\n"); \ } /* * @brief Restore DSP context - * @note To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + * @note DSP context registers are stored at word offset 41 in the stack */ #define RESTORE_DSP_CONTEXT() {\ - __asm volatile("lw t6, 20*4(sp)\n\ - csrw ucode, t6 \n"); \ + __asm volatile("csrw ucode, s0\n"); \ } + #else #define SAVE_DSP_CONTEXT() #define RESTORE_DSP_CONTEXT() @@ -671,60 +774,32 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) * MSTATUS = word offset 18 * MXSTATUS = word offset 19 */ -#define ENTER_NESTED_IRQ_HANDLING_M() {\ - __asm volatile("csrr t6, mepc \n\ - sw t6, 17*4(sp) \n\ - csrr t6, mstatus \n\ - sw t6, 18*4(sp) \n\ - csrr t6, %0\n\ - sw t6, 19*4(sp) \n\ - " : : "i" CSR_MSTATUS);\ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile("li t6, %0\n" : : "i" (CSR_MSTATUS_MIE_MASK)); \ - __asm volatile("csrrs t6, mstatus, t6\n"); \ -} -#define COMPLETE_IRQ_HANDLING_M(irq_num) {\ - __asm volatile("li t0, 0xe4000000 \n\ - li t1, 0x200004 \n\ - add t0, t0, t1 \n\ - lui t1, 0 \n\ - slli t2, t1, 0xc \n\ - add t0, t0, t2 \n");\ - __asm volatile("li t1, %0" : : "i" (irq_num) :); \ - __asm volatile("sw t1, 0(t0) \n\ - fence io, io \n\ - li t6, 1\n\ - addi t6, t6, -0x800\n\ - csrrs t6, mie, t6 \n"); \ + __asm volatile ("\n\ + c.li a5, 8\n\ + csrs mstatus, a5\n"); \ } -#define ENTER_NESTED_IRQ_HANDLING_S() {\ - __asm volatile("csrr t6, sepc \n\ - sw t6, 17*4(sp) \n\ - csrr t6, sstatus \n\ - sw t6, 18*4(sp) \n\ - csrr t6, %0\n\ - sw t6, 19*4(sp) \n\ - " : : "i" CSR_SSTATUS);\ - SAVE_DSP_CONTEXT(); \ - __asm volatile("li t6, %0\n" : : "i" (CSR_SSTATUS_SIE_MASK)); \ - __asm volatile("csrrs t6, sstatus, t6\n"); \ +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("\n\ + lui a5, 0x1\n\ + addi a5, a5, -2048\n\ + csrc mie, a5\n"); \ + __asm volatile("\n\ + lui a4, 0xe4200\n");\ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)\n\ + fence io, io\n"); \ + __asm volatile("csrs mie, a5"); \ } -#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("li t0, 0xe4000000 \n\ - li t1, 0x201004 \n\ - add t0, t0, t1 \n\ - lui t1, 0 \n\ - slli t2, t1, 0xc \n\ - add t0, t0, t2 \n");\ - __asm volatile("li t1, %0" : : "i" (irq_num) :); \ - __asm volatile("sw t1, 0(t0) \n\ - fence io, io \n\ - li t6, 1\n\ - addi t6, t6, -0x200\n\ - csrrs t6, sie, t6 \n"); \ -} - /* * @brief Exit Nested IRQ Handling @@ -735,16 +810,38 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) * MXSTATUS = word offset 19 */ #define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("csrrci t6, mstatus, 8 \n\ - lw t6, 18*4(sp) \n\ - csrw mstatus, t6 \n\ - lw t6, 17*4(sp) \n\ - csrw mepc, t6 \n\ - lw t6, 19*4(sp) \n\ - csrw %0, t6 \n" : : "i" CSR_MSTATUS);\ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ RESTORE_DSP_CONTEXT(); \ } + +#define ENTER_NESTED_IRQ_HANDLING_S() {\ + __asm volatile("\n\ + csrr s2, sepc \n\ + csrr s3, sstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile ("\n\ + c.li a5, 8\n\ + csrs sstatus, a5\n"); \ +} +#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ + __asm volatile("\n\ + lui a5, 0x1\n\ + addi a5, a5, -2048\n\ + csrc sie, a5\n"); \ + __asm volatile("\n\ + lui a4, 0xe4201\n");\ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)\n\ + fence io, io\n"); \ + __asm volatile("csrs sie, a5"); \ +} + + /* * @brief Exit Nested IRQ Handling at supervisor mode * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: @@ -753,13 +850,10 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) * SSTATUS = word offset 18 */ #define EXIT_NESTED_IRQ_HANDLING_S() { \ - __asm volatile("csrrci t6, sstatus, 2 \n\ - lw t6, 18*4(sp) \n\ - csrw sstatus, t6 \n\ - lw t6, 17*4(sp) \n\ - csrw sepc, t6 \n\ - lw t6, 19*4(sp) \n\ - csrw %0, t6 \n" : : "i" CSR_SSTATUS);\ + __asm volatile("\n\ + csrw sstatus, s3 \n\ + csrw sepc, s2 \n");\ + RESTORE_FPU_STATE(); \ RESTORE_DSP_CONTEXT(); \ } @@ -774,7 +868,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) /* @brief Nested IRQ exit macro : Restore CSRs */ #define NESTED_IRQ_EXIT() \ - clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); \ RESTORE_CSR(CSR_MSTATUS) \ RESTORE_CSR(CSR_MEPC) \ RESTORE_MXSTATUS() \ @@ -812,13 +905,14 @@ do { \ #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ void isr(void) __attribute__((section(".isr_vector")));\ EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) {\ +void ISR_NAME_M(irq_num)(void) \ +{ \ SAVE_CALLER_CONTEXT(); \ ENTER_NESTED_IRQ_HANDLING_M();\ __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ __asm volatile("jalr t1\n");\ - EXIT_NESTED_IRQ_HANDLING_M();\ COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ __asm volatile("mret\n");\ } @@ -837,8 +931,8 @@ void ISR_NAME_S(irq_num)(void) {\ ENTER_NESTED_IRQ_HANDLING_S();\ __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ __asm volatile("jalr t1\n");\ - EXIT_NESTED_IRQ_HANDLING_S();\ COMPLETE_IRQ_HANDLING_S(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_S();\ RESTORE_CALLER_CONTEXT();\ __asm volatile("sret\n");\ } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h index c38a47cea2..cf272e6f79 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,7 +13,7 @@ typedef struct { struct { __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[492]; + } PAD[488]; } IOC_Type; @@ -282,34 +282,6 @@ typedef struct { #define IOC_PAD_PC25 (89UL) #define IOC_PAD_PC26 (90UL) #define IOC_PAD_PC27 (91UL) -#define IOC_PAD_PC28 (92UL) -#define IOC_PAD_PC29 (93UL) -#define IOC_PAD_PC30 (94UL) -#define IOC_PAD_PC31 (95UL) -#define IOC_PAD_PD00 (96UL) -#define IOC_PAD_PD01 (97UL) -#define IOC_PAD_PD02 (98UL) -#define IOC_PAD_PD03 (99UL) -#define IOC_PAD_PD04 (100UL) -#define IOC_PAD_PD05 (101UL) -#define IOC_PAD_PD06 (102UL) -#define IOC_PAD_PD07 (103UL) -#define IOC_PAD_PD08 (104UL) -#define IOC_PAD_PD09 (105UL) -#define IOC_PAD_PD10 (106UL) -#define IOC_PAD_PD11 (107UL) -#define IOC_PAD_PD12 (108UL) -#define IOC_PAD_PD13 (109UL) -#define IOC_PAD_PD14 (110UL) -#define IOC_PAD_PD15 (111UL) -#define IOC_PAD_PD16 (112UL) -#define IOC_PAD_PD17 (113UL) -#define IOC_PAD_PD18 (114UL) -#define IOC_PAD_PD19 (115UL) -#define IOC_PAD_PD20 (116UL) -#define IOC_PAD_PD21 (117UL) -#define IOC_PAD_PD22 (118UL) -#define IOC_PAD_PD23 (119UL) #define IOC_PAD_PX00 (416UL) #define IOC_PAD_PX01 (417UL) #define IOC_PAD_PX02 (418UL) @@ -326,10 +298,6 @@ typedef struct { #define IOC_PAD_PY05 (453UL) #define IOC_PAD_PY06 (454UL) #define IOC_PAD_PY07 (455UL) -#define IOC_PAD_PY08 (456UL) -#define IOC_PAD_PY09 (457UL) -#define IOC_PAD_PY10 (458UL) -#define IOC_PAD_PY11 (459UL) #define IOC_PAD_PZ00 (480UL) #define IOC_PAD_PZ01 (481UL) #define IOC_PAD_PZ02 (482UL) @@ -338,10 +306,6 @@ typedef struct { #define IOC_PAD_PZ05 (485UL) #define IOC_PAD_PZ06 (486UL) #define IOC_PAD_PZ07 (487UL) -#define IOC_PAD_PZ08 (488UL) -#define IOC_PAD_PZ09 (489UL) -#define IOC_PAD_PZ10 (490UL) -#define IOC_PAD_PZ11 (491UL) -#endif /* HPM_IOC_H */ \ No newline at end of file +#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h index 5b1a771099..b2f71da5d0 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,7 +15,6 @@ #define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA00_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA00_FUNC_CTL_XPI_SLV_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA01_FUNC_CTL function mux definitions */ #define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -23,7 +22,6 @@ #define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA01_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA01_FUNC_CTL_XPI_SLV_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA02_FUNC_CTL function mux definitions */ #define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -31,7 +29,6 @@ #define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA02_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA02_FUNC_CTL_XPI_SLV_ADQ_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA03_FUNC_CTL function mux definitions */ #define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -39,7 +36,6 @@ #define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA03_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA03_FUNC_CTL_XPI_SLV_ADQ_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA04_FUNC_CTL function mux definitions */ #define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -48,7 +44,6 @@ #define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA04_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA04_FUNC_CTL_XPI_SLV_ADQ_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA05_FUNC_CTL function mux definitions */ #define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -57,8 +52,6 @@ #define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA05_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA05_FUNC_CTL_ADC2_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA05_FUNC_CTL_XPI_SLV_ADQ_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA06_FUNC_CTL function mux definitions */ #define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -69,8 +62,6 @@ #define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA06_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA06_FUNC_CTL_ADC1_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA06_FUNC_CTL_XPI_SLV_ADQ_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA07_FUNC_CTL function mux definitions */ #define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -80,8 +71,6 @@ #define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA07_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA07_FUNC_CTL_ADC0_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA07_FUNC_CTL_XPI_SLV_ADQ_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA08_FUNC_CTL function mux definitions */ #define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -94,7 +83,6 @@ #define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA08_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PA08_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA08_FUNC_CTL_XPI_SLV_ADQ_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA09_FUNC_CTL function mux definitions */ #define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -106,7 +94,6 @@ #define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PA09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PA09_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA09_FUNC_CTL_XPI_SLV_ADQ_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA10_FUNC_CTL function mux definitions */ #define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -185,7 +172,6 @@ #define IOC_PA16_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) #define IOC_PA16_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) #define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA16_FUNC_CTL_XPI_SLV_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA17_FUNC_CTL function mux definitions */ #define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -195,7 +181,6 @@ #define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA17_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) #define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA17_FUNC_CTL_XPI_SLV_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA18_FUNC_CTL function mux definitions */ #define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -205,7 +190,6 @@ #define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA18_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) #define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA18_FUNC_CTL_XPI_SLV_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PA19_FUNC_CTL function mux definitions */ #define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -253,7 +237,7 @@ #define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA23_FUNC_CTL_DRAM_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA23_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA23_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) @@ -264,7 +248,7 @@ #define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA24_FUNC_CTL_DRAM_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA24_FUNC_CTL_FEMC_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA24_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) @@ -274,7 +258,7 @@ #define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA25_FUNC_CTL_DRAM_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA25_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA25_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) #define IOC_PA25_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) @@ -286,7 +270,7 @@ #define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA26_FUNC_CTL_DRAM_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA26_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA26_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) #define IOC_PA26_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) @@ -294,7 +278,7 @@ /* IOC_PA27_FUNC_CTL function mux definitions */ #define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA27_FUNC_CTL_DRAM_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA27_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PA27_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) @@ -303,7 +287,7 @@ #define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA28_FUNC_CTL_DRAM_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA28_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PA29_FUNC_CTL function mux definitions */ @@ -311,7 +295,7 @@ #define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA29_FUNC_CTL_DRAM_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA29_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PA30_FUNC_CTL function mux definitions */ @@ -319,42 +303,42 @@ #define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA30_FUNC_CTL_DRAM_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA30_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PA31_FUNC_CTL function mux definitions */ #define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA31_FUNC_CTL_DRAM_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA31_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB00_FUNC_CTL function mux definitions */ #define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB00_FUNC_CTL_DRAM_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB00_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB01_FUNC_CTL function mux definitions */ #define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB01_FUNC_CTL_DRAM_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB01_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB02_FUNC_CTL function mux definitions */ #define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB02_FUNC_CTL_DRAM_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB02_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB03_FUNC_CTL function mux definitions */ #define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB03_FUNC_CTL_DRAM_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB03_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB03_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -362,7 +346,7 @@ #define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB04_FUNC_CTL_DRAM_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB04_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB04_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -370,14 +354,14 @@ #define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB05_FUNC_CTL_DRAM_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB05_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB05_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB06_FUNC_CTL function mux definitions */ #define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_DRAM_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB06_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -385,7 +369,7 @@ #define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB07_FUNC_CTL_DRAM_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB07_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB07_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -393,7 +377,7 @@ #define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_DRAM_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB08_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB08_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -401,7 +385,7 @@ #define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_DRAM_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB09_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB09_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -409,7 +393,7 @@ #define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB10_FUNC_CTL_DRAM_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB10_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB10_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -417,7 +401,7 @@ #define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB11_FUNC_CTL_DRAM_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB11_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB11_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -425,7 +409,7 @@ #define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB12_FUNC_CTL_DRAM_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB12_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB12_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -433,7 +417,7 @@ #define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB13_FUNC_CTL_DRAM_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB13_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB13_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -443,7 +427,7 @@ #define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB14_FUNC_CTL_DRAM_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB14_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB14_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -452,7 +436,7 @@ #define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB15_FUNC_CTL_DRAM_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB15_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB15_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -461,14 +445,14 @@ #define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB16_FUNC_CTL_DRAM_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB16_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB16_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB17_FUNC_CTL function mux definitions */ #define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB17_FUNC_CTL_DRAM_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB17_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB17_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) @@ -480,7 +464,7 @@ #define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB18_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB18_FUNC_CTL_DRAM_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB18_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB19_FUNC_CTL function mux definitions */ @@ -490,7 +474,7 @@ #define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB19_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB19_FUNC_CTL_DRAM_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB19_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB20_FUNC_CTL function mux definitions */ @@ -501,7 +485,7 @@ #define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB20_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB20_FUNC_CTL_DRAM_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB20_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB21_FUNC_CTL function mux definitions */ @@ -511,7 +495,7 @@ #define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB21_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB21_FUNC_CTL_DRAM_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB21_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB22_FUNC_CTL function mux definitions */ @@ -521,7 +505,7 @@ #define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB22_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB22_FUNC_CTL_DRAM_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB22_FUNC_CTL_FEMC_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -532,7 +516,7 @@ #define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB23_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB23_FUNC_CTL_DRAM_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB23_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -542,7 +526,7 @@ #define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB24_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB24_FUNC_CTL_DRAM_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB24_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB25_FUNC_CTL function mux definitions */ @@ -551,14 +535,14 @@ #define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PB25_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB25_FUNC_CTL_DRAM_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB25_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB26_FUNC_CTL function mux definitions */ #define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB26_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB26_FUNC_CTL_DRAM_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB26_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB27_FUNC_CTL function mux definitions */ @@ -566,7 +550,7 @@ #define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB27_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB27_FUNC_CTL_DRAM_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB27_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB28_FUNC_CTL function mux definitions */ @@ -574,7 +558,7 @@ #define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB28_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB28_FUNC_CTL_DRAM_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB28_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB29_FUNC_CTL function mux definitions */ @@ -582,7 +566,7 @@ #define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB29_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB29_FUNC_CTL_DRAM_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB29_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB30_FUNC_CTL function mux definitions */ @@ -591,7 +575,7 @@ #define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB30_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB30_FUNC_CTL_DRAM_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB30_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB31_FUNC_CTL function mux definitions */ @@ -599,7 +583,7 @@ #define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB31_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB31_FUNC_CTL_DRAM_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB31_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PC00_FUNC_CTL function mux definitions */ @@ -608,7 +592,7 @@ #define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC00_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC00_FUNC_CTL_DRAM_SRDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC00_FUNC_CTL_FEMC_SRDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -617,7 +601,7 @@ #define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC01_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC01_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC01_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) @@ -769,7 +753,6 @@ #define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC18_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC18_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC19_FUNC_CTL function mux definitions */ #define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -777,7 +760,6 @@ #define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC19_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC19_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC19_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC20_FUNC_CTL function mux definitions */ #define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -821,7 +803,6 @@ #define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC24_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC24_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC24_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC25_FUNC_CTL function mux definitions */ #define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -829,7 +810,6 @@ #define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC25_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC25_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC26_FUNC_CTL function mux definitions */ #define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -847,259 +827,6 @@ #define IOC_PC27_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PC27_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -/* IOC_PC28_FUNC_CTL function mux definitions */ -#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC28_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC28_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC28_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC28_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC29_FUNC_CTL function mux definitions */ -#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC29_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC29_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC29_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC29_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC30_FUNC_CTL function mux definitions */ -#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC30_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC30_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC30_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC31_FUNC_CTL function mux definitions */ -#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC31_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC31_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC31_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD00_FUNC_CTL function mux definitions */ -#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD00_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD00_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD00_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD00_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD00_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD00_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD00_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD00_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD01_FUNC_CTL function mux definitions */ -#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD01_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD01_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD01_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD01_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD01_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD01_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD01_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD02_FUNC_CTL function mux definitions */ -#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD02_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD02_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD02_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD02_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD02_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD02_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD02_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD02_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD03_FUNC_CTL function mux definitions */ -#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD03_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD03_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD03_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD03_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD03_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD03_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD03_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD03_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD03_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD04_FUNC_CTL function mux definitions */ -#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD04_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD04_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD04_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD04_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD04_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD04_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD04_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD05_FUNC_CTL function mux definitions */ -#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD05_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD05_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD05_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD05_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD05_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD05_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD05_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD06_FUNC_CTL function mux definitions */ -#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD06_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD06_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD06_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD06_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD06_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD06_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD06_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD07_FUNC_CTL function mux definitions */ -#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD07_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD07_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD07_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD07_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD07_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD07_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD08_FUNC_CTL function mux definitions */ -#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD08_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD08_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD08_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD08_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD08_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD08_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD09_FUNC_CTL function mux definitions */ -#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD09_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD09_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD09_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD10_FUNC_CTL function mux definitions */ -#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD10_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD10_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD10_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD10_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD10_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD11_FUNC_CTL function mux definitions */ -#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD11_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD11_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD11_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD11_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD11_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD11_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD12_FUNC_CTL function mux definitions */ -#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD12_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD12_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD12_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD12_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD12_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD13_FUNC_CTL function mux definitions */ -#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD13_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD13_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD13_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD13_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD13_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD14_FUNC_CTL function mux definitions */ -#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD14_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD14_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD14_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD14_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD14_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD14_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD14_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD15_FUNC_CTL function mux definitions */ -#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD15_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD15_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD15_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD15_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD15_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD15_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD15_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD16_FUNC_CTL function mux definitions */ -#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD16_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD16_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD16_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD16_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD16_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD16_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD17_FUNC_CTL function mux definitions */ -#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD17_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD17_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD17_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD17_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD17_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD18_FUNC_CTL function mux definitions */ -#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD18_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD18_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD18_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD18_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD18_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD19_FUNC_CTL function mux definitions */ -#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD19_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD19_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD19_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD19_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD20_FUNC_CTL function mux definitions */ -#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD20_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD20_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD20_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD20_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD20_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD20_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD21_FUNC_CTL function mux definitions */ -#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD21_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD21_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD21_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD21_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD21_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD22_FUNC_CTL function mux definitions */ -#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD22_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PD23_FUNC_CTL function mux definitions */ -#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD23_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - /* IOC_PX00_FUNC_CTL function mux definitions */ #define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) @@ -1130,7 +857,7 @@ /* IOC_PX07_FUNC_CTL function mux definitions */ #define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PX07_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PX07_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) /* IOC_PY00_FUNC_CTL function mux definitions */ @@ -1145,7 +872,6 @@ #define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PY01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY01_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PY02_FUNC_CTL function mux definitions */ #define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1186,18 +912,6 @@ #define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PY07_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -/* IOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - /* IOC_PZ00_FUNC_CTL function mux definitions */ #define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) @@ -1212,13 +926,11 @@ #define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ02_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PZ03_FUNC_CTL function mux definitions */ #define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ03_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PZ04_FUNC_CTL function mux definitions */ #define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1240,17 +952,5 @@ #define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -/* IOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -/* IOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - - -#endif /* HPM_IOMUX_H */ \ No newline at end of file +#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c index 418f3eb409..c55600dcdc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c @@ -1,12 +1,10 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#include "hpm_common.h" -#include "hpm_soc.h" #include "hpm_l1c_drv.h" #include @@ -19,14 +17,18 @@ static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) { register uint32_t i; - register uint32_t next_address = 0; + register uint32_t next_address; register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); #define CCTL_VERSION (3U << 18) if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { l1c_cctl_address(address); - while (next_address < (address + size)) { + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { l1c_cctl_cmd(opcode); next_address = l1c_cctl_get_address(); } @@ -36,6 +38,8 @@ static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) tmp += HPM_L1C_CACHELINE_SIZE; } } + + write_csr(CSR_MSTATUS, csr); } void l1c_dc_enable(void) @@ -89,6 +93,11 @@ void l1c_dc_writeback_all(void) l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); } +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + void l1c_dc_fill_lock(uint32_t address, uint32_t size) { ASSERT_ADDR_SIZE(address, size); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h index d64cd4791f..e328193a07 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #define _HPM_L1_CACHE_H #include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_soc.h" /** * @@ -468,6 +469,11 @@ void l1c_dc_invalidate_all(void); */ void l1c_dc_writeback_all(void); +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h index 3ad12ad240..d4ff0c6671 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.c index ef0fa1cfc4..dbab299955 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h index 09f62879ec..8c9559a986 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h new file mode 100644 index 0000000000..e99e0837a5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h @@ -0,0 +1,639 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) +#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_fuse = 0, + pcfg_pmc_periph_ram = 2, + pcfg_pmc_periph_vad = 4, + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, + pcfg_pmc_periph_debug = 16, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap enable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief bandgap enable low power mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) +{ + ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn of LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) +{ + ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + * @param[in] over_limit set to true means current is greater than limit + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); +} + +/** + * @brief disable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief enable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/** + * @brief Disable CPU0 debug stop notficiation to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Enable CPU0 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Disable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Enable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Configure CPU core debug stop notification to peripherals + * + * @param[in] ptr + * @param[in] mask + */ +static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) +{ + ptr->DEBUG_STOP = mask; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h similarity index 99% rename from bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h index c1c7b99304..b05080feac 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -735,7 +735,7 @@ typedef struct { * SCG (RW) * * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: clock gated according to low power flow + * 00,01: reserved * 10: clock is always off * 11: clock is always on * bit0-1: fuse @@ -924,4 +924,4 @@ typedef struct { -#endif /* HPM_PCFG_H */ \ No newline at end of file +#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h new file mode 100644 index 0000000000..0369149bdd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_plic_drv.h index dc0b95e00e..9595051f90 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_plic_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_plic_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h index 197dcb8c4f..8990b9849e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -57,27 +57,5 @@ #define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -/* IOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -/* IOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ \ No newline at end of file +#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h new file mode 100644 index 0000000000..b1eb6e6ac5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_temperature = 1 << 1, + ppor_reset_pin = 1 << 2, + ppor_reset_debug = 1 << 4, + ppor_reset_security_violation = 1 << 5, + ppor_reset_jtag = 1 << 6, + ppor_reset_cpu0_lockup = 1 << 8, + ppor_reset_cpu1_lockup = 1 << 9, + ppor_reset_cpu0_request = 1 << 10, + ppor_reset_cpu1_request = 1 << 11, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_wdog2 = 1 << 18, + ppor_reset_wdog3 = 1 << 19, + ppor_reset_pmic_wdog = 1 << 20, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG |= mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD = mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD &= ~mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT = mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT &= ~mask; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h new file mode 100644 index 0000000000..21cb6fc237 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ + __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ + __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RW) + * + * current status of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * STATUS (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) +#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) +#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_HOT */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOT_TYPE_SHIFT (0U) +#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) +#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) + +/* Bitfield definition for register: RESET_COLD */ +/* + * FLAG (RW) + * + * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_COLD_FLAG_SHIFT (0U) +#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) +#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h index 5797f26e0d..05edd7fd57 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -52,6 +52,14 @@ typedef union { }; } api_boot_arg_t; +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + #define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ #define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ #define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ @@ -61,6 +69,19 @@ typedef union { #define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ #define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ +typedef struct { + uint32_t _internal[138]; +} sm3_context_t; + + +#define SM4_ENCRYPT 1 +#define SM4_DECRYPT 0 + +typedef struct { + uint32_t mode; + uint32_t _internal[116]; +} sm4_context_t; + /** * @brief OTP driver interface */ @@ -277,6 +298,43 @@ typedef struct { hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); } sdp_driver_interface_t; +typedef struct { + /**< SM3 API version*/ + uint32_t version; + /**< SM3 API itnerface: HASH Initialization */ + hpm_stat_t (*init)(sm3_context_t *ctx); + /**< SM3 API interface: HASH update */ + hpm_stat_t (*update)(sm3_context_t *ctx, const void *input, uint32_t len); + /**< SM3 API interface: HASH finish */ + hpm_stat_t (*finalize)(sm3_context_t *ctx, uint8_t output[32]); +} sm3_api_interface_t; + +typedef struct { + /**< SM4 API interface: Version */ + uint32_t version; + /**< SM4 API interface: Set encryption key */ + void (*setkey_enc)(sm4_context_t *ctx, const uint8_t key[16]); + /**< SM4 API interface: Set decryption key */ + void (*setkey_dec)(sm4_context_t *ctx, const uint8_t key[16]); + /**< SM4 API interface: SM4 ECB operation */ + hpm_stat_t (*crypt_ecb)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output); + /**< SM4 API interface: SM4 CBC operation */ + hpm_stat_t (*crypt_cbc)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], + const uint8_t *input, uint8_t *output); + /**< SM4 API interface: SM4 CTR operation */ + hpm_stat_t (*crypt_ctr)(sm4_context_t *ctx, uint8_t *nonce_counter, const uint8_t *input, + uint8_t *output, uint32_t length); + /**< SM4 API interface: SM4 CCB encryption */ + hpm_stat_t (*ccm_gen_enc)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, uint8_t *tag, uint32_t tag_len); + /**< SM4 API interface: SM4 CCM Decryption and verifying */ + hpm_stat_t (*ccm_dec_verify)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, const uint8_t *tag, uint32_t tag_len); +} sm4_api_interface_t; + + /** * @brief Bootloader API table */ @@ -297,6 +355,9 @@ typedef struct { const xpi_ram_driver_interface_t *xpi_ram_driver_if; /**< Bootloader API table: sdp driver interface address */ const sdp_driver_interface_t *sdp_driver_if; + const uint32_t reserved0; + const sm3_api_interface_t *sm3_api_if; /* SM3 driver interface address */ + const sm4_api_interface_t *sm4_api_if; /* SM4 driver itnerface address */ } bootloader_api_table_t; /**< Bootloader API table Root */ @@ -340,8 +401,9 @@ static inline hpm_stat_t rom_enter_bootloader(void *ctx) * @param [in] cfg_option XPI NOR configuration option * @return API execution status */ -static inline hpm_stat_t -rom_xpi_nor_get_config(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option) +static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + xpi_nor_config_option_t *cfg_option) { return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); } @@ -372,7 +434,9 @@ static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, uint32_t start, uint32_t length) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + fencei(); + return status; } /** @@ -383,10 +447,14 @@ static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, * @param[in] start Sector address * @return API execution status */ -static inline hpm_stat_t -rom_xpi_nor_erase_sector(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start) +static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + fencei(); + return status; } /** @@ -413,10 +481,14 @@ static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, * @param[in] start Block address * @return API execution status */ -static inline hpm_stat_t -rom_xpi_nor_erase_block(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start) +static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + fencei(); + return status; } /** @@ -442,8 +514,9 @@ static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, * @param[in] nor_config XPI NOR configuration * @return API execution status */ -static inline hpm_stat_t -rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config) +static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) { return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); } @@ -455,10 +528,13 @@ rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor * @param[in] nor_config XPI NOR configuration * @return API execution status */ -static inline hpm_stat_t -rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config) +static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + fencei(); + return status; } /** @@ -478,7 +554,9 @@ static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, uint32_t dst_addr, uint32_t length) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + fencei(); + return status; } /** @@ -529,8 +607,9 @@ static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, * @param [in] cfg_option XPI NOR configuration option * @return API execution status */ -static inline hpm_stat_t -rom_xpi_nor_auto_config(XPI_Type *base, xpi_nor_config_t *config, xpi_nor_config_option_t *cfg_option) +static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, + xpi_nor_config_t *config, + xpi_nor_config_option_t *cfg_option) { return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); } @@ -543,12 +622,185 @@ rom_xpi_nor_auto_config(XPI_Type *base, xpi_nor_config_t *config, xpi_nor_config * @param [out] value property value retrieved by this API * @return API execution status */ -static inline hpm_stat_t -rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value) +static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + uint32_t property_id, + uint32_t *value) { return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); } +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + if (((base != HPM_XPI0) && (base != HPM_XPI1)) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) + || ((offset & 0xFFF) != 0)) { + return false; + } + static const uint8_t k_mc_xpi_remap_config[] = { + 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, + 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, + 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, + }; + typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); + remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; + bool result = cb(base, start, len, offset); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_disable[] = { + 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, + 0xf5, 0x42, 0x82, 0x80, + }; + typedef void (*remap_disable_cb_t)(XPI_Type *); + remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; + cb(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_enabled[] = { + 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, + }; + typedef bool (*remap_chk_cb_t)(XPI_Type *); + remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; + return chk_cb(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + if (base != HPM_XPI0) { + return false; + } + static const uint8_t k_mc_exip_region_config[] = { + 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, + 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, + 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, + 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, + 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, + 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, + 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, + 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, + 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, + }; + typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); + exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; + cb(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return true; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @@param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + static const uint8_t k_mc_exip_region_disable[] = { + 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, + 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, + 0xe7, 0xd0, 0x82, 0x80 + }; + typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); + exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; + cb(base, index); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_enable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, + 0xf5, 0xc0, 0x82, 0x80 + }; + typedef void (*exip_enable_cb_t)(XPI_Type *); + exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; + cb(base); +} + +/** + * @brief Disable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_disable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, + 0x82, 0x80 + }; + typedef void (*exip_disable_cb_t)(XPI_Type *); + exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; + cb(base); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} /*********************************************************************************************************************** * @@ -564,8 +816,9 @@ rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t pro * @param [in] cfg_option XPI RAM configuration option * @return API execution status */ -static inline hpm_stat_t -rom_xpi_ram_get_config(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option) +static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, + xpi_ram_config_t *ram_cfg, + xpi_ram_config_option_t *cfg_option) { return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); } @@ -612,8 +865,10 @@ static inline void rom_sdp_deinit(void) * @param[in] key_idx AES key index * @return API execution status */ -static inline hpm_stat_t -rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, uint32_t key_idx) +static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, + uint32_t key_idx) { return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); } @@ -627,8 +882,11 @@ rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits * @param [out] out Output data * @return API execution status */ -static inline hpm_stat_t -rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out) +static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) { return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); } @@ -713,6 +971,111 @@ static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8 return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); } + +/*********************************************************************************************************************** + * + * + * SM3 Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief SM4 initialization + * + * @param [in] ctx SM3 context + * @return API execution status + */ +static inline hpm_stat_t rom_sm3_init(sm3_context_t *ctx) +{ + return ROM_API_TABLE_ROOT->sm3_api_if->init(ctx); +} + +/** + * @brief SM3 update operation + * + * @param [in,out] ctx SM3 context + * @param [in] input Data for SM3 calculation + * @param [in] len length of the data for SM3 calculation + * @return API execution status + */ +static inline hpm_stat_t rom_sm3_update(sm3_context_t *ctx, const void *input, uint32_t len) +{ + return ROM_API_TABLE_ROOT->sm3_api_if->update(ctx, input, len); +} + +/** + * @brief SM3 finalize + * Return the computing SM3 digest + * + * @param [in] ctx SM3 context + * @param [out] output SM3 digest calculated by the above API + * @return API execution status + */ +static inline hpm_stat_t rom_sm3_finalize(sm3_context_t *ctx, uint8_t output[32]) +{ + return ROM_API_TABLE_ROOT->sm3_api_if->finalize(ctx, output); +} + +/*********************************************************************************************************************** + * + * + * SM4 Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Set SM4 encryption key + * + * @param [in] ctx SM4 context + * @param [in] key SM4 encryption key + */ +static inline void rom_sm4_setkey_enc(sm4_context_t *ctx, const uint8_t key[16]) +{ + ROM_API_TABLE_ROOT->sm4_api_if->setkey_enc(ctx, key); +} + +/** + * @brief Set SM4 decryption key + * + * @param [in] ctx SM4 context + * @param [in] key SM4 decryption key + */ +static inline void rom_sm4_setkey_dec(sm4_context_t *ctx, const uint8_t key[16]) +{ + ROM_API_TABLE_ROOT->sm4_api_if->setkey_dec(ctx, key); +} + +/** + * @brief SM4 ECB crypto operation(Encrypt or Decrypt) + * @param [in] ctx SM4 context + * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] input Input data + * @param [out] output Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output) +{ + return ROM_API_TABLE_ROOT->sm4_api_if->crypt_ecb(ctx, mode, length, input, output); +} + +/** + * @brief SM4 CBC crypto operation(Encrypt or Decrypt) + * @param [in] ctx SM4 context + * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] input Input data + * @param [out] output Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sm4_crypt_cbc(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], const uint8_t *input, uint8_t *output) +{ + return ROM_API_TABLE_ROOT->sm4_api_if->crypt_cbc(ctx, mode, length, iv, input, output); +} + + + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi_xpi_soc_def.h index 13edd92e2c..ce18ef5544 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi_xpi_soc_def.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi_xpi_soc_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h index 9f39f2ef07..76d3dc52fe 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,12 +33,13 @@ static inline void sdxc_disable_freq_selection(SDXC_Type *base) static inline void sdxc_set_clock_divider(SDXC_Type *base, uint32_t div) { - base->MISC_CTRL0 = (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div) | SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; + base->MISC_CTRL0 = (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div - 1U) | + SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; } static inline uint32_t sdxc_get_clock_divider(SDXC_Type *base) { - return SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(base->MISC_CTRL0); + return (1U + SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(base->MISC_CTRL0)); } /** @@ -63,6 +64,26 @@ static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) } } +static inline bool sdxc_is_inverse_clock_enabled(SDXC_Type *base) +{ + return ((base->MISC_CTRL0 & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) != 0U); +} + +static inline void sdxc_select_cardclk_delay_source(SDXC_Type *base, bool loopback_from_pad) +{ + if (!loopback_from_pad) { + base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; + } else { + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; + } +} + +static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t number_of_delaycells) +{ + base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) | + SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(number_of_delaycells); +} + #if defined(__cplusplus) } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml index 3d3d1e7c66..ee67d133ae 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml @@ -4,75 +4,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -220,75 +166,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -582,75 +474,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -798,75 +636,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1160,75 +944,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1376,75 +1106,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1738,75 +1414,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1954,75 +1576,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -2730,28 +2298,28 @@ - + - + - + - + - + - + - + - + @@ -2793,962 +2361,582 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -3902,6 +3090,10 @@ + + + + @@ -3982,7 +3174,7 @@ - + @@ -4601,6 +3793,10 @@ + + + + @@ -4681,7 +3877,7 @@ - + @@ -5300,6 +4496,10 @@ + + + + @@ -5380,7 +4580,7 @@ - + @@ -6040,18 +5240,21 @@ + + + @@ -6062,6 +5265,16 @@ + + + + + + + + + + @@ -6079,27 +5292,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -6175,7 +5367,6 @@ - @@ -6194,27 +5385,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -6290,7 +5460,6 @@ - @@ -6309,27 +5478,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -6405,7 +5553,6 @@ - @@ -6424,27 +5571,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -6520,7 +5646,6 @@ - @@ -8914,28 +8039,28 @@ - + - + - + - + - + - + - + - + @@ -9032,34 +8157,33 @@ - + - + - + - + - + - + - + - + - @@ -9531,6 +8655,7 @@ + @@ -10306,6 +9431,7 @@ + @@ -11141,7 +10267,6 @@ - @@ -11160,7 +10285,6 @@ - @@ -11179,7 +10303,6 @@ - @@ -11198,7 +10321,6 @@ - @@ -11302,7 +10424,6 @@ - @@ -11321,7 +10442,6 @@ - @@ -11340,7 +10460,6 @@ - @@ -11359,7 +10478,6 @@ - @@ -12529,24 +11647,6 @@ - - - - - - - - - - - - - - - - - - @@ -12641,7 +11741,6 @@ - @@ -12652,12 +11751,6 @@ - - - - - - @@ -12808,132 +11901,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -12997,86 +11967,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -13107,20 +11997,6 @@ - - - - - - - - - - - - - - @@ -13137,20 +12013,6 @@ - - - - - - - - - - - - - - @@ -13167,20 +12029,6 @@ - - - - - - - - - - - - - - @@ -13197,30 +12045,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -13303,10 +12127,11 @@ + - + @@ -13491,55 +12316,11 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -13553,10 +12334,10 @@ - + - + @@ -13582,7 +12363,7 @@ - + @@ -13596,10 +12377,10 @@ - + - + @@ -13625,7 +12406,7 @@ - + @@ -13639,10 +12420,10 @@ - + - + @@ -13668,7 +12449,7 @@ - + @@ -13682,10 +12463,10 @@ - + - + @@ -13754,7 +12535,7 @@ - + @@ -13768,10 +12549,10 @@ - + - + @@ -13797,7 +12578,7 @@ - + @@ -13811,10 +12592,10 @@ - + - + @@ -13840,7 +12621,7 @@ - + @@ -13854,10 +12635,10 @@ - + - + @@ -13883,7 +12664,7 @@ - + @@ -13897,10 +12678,10 @@ - + - + @@ -13969,7 +12750,7 @@ - + @@ -13983,10 +12764,10 @@ - + - + @@ -14012,7 +12793,7 @@ - + @@ -14026,10 +12807,10 @@ - + - + @@ -14055,7 +12836,7 @@ - + @@ -14069,10 +12850,10 @@ - + - + @@ -14098,7 +12879,7 @@ - + @@ -14112,10 +12893,10 @@ - + - + @@ -14184,7 +12965,7 @@ - + @@ -14198,10 +12979,10 @@ - + - + @@ -14227,7 +13008,7 @@ - + @@ -14241,10 +13022,10 @@ - + - + @@ -14270,7 +13051,7 @@ - + @@ -14284,10 +13065,10 @@ - + - + @@ -14313,7 +13094,7 @@ - + @@ -14327,10 +13108,10 @@ - + - + @@ -14399,7 +13180,7 @@ - + @@ -14413,10 +13194,10 @@ - + - + @@ -14442,7 +13223,7 @@ - + @@ -14456,10 +13237,10 @@ - + - + @@ -14485,7 +13266,7 @@ - + @@ -14499,10 +13280,10 @@ - + - + @@ -14528,7 +13309,7 @@ - + @@ -14542,10 +13323,10 @@ - + - + @@ -14614,7 +13395,7 @@ - + @@ -14628,10 +13409,10 @@ - + - + @@ -14657,7 +13438,7 @@ - + @@ -14671,10 +13452,10 @@ - + - + @@ -14700,7 +13481,7 @@ - + @@ -14714,10 +13495,10 @@ - + - + @@ -14743,7 +13524,7 @@ - + @@ -14757,10 +13538,10 @@ - + - + @@ -14931,8 +13712,6 @@ - - @@ -15089,8 +13868,6 @@ - - @@ -15188,6 +13965,7 @@ + @@ -15425,8 +14203,6 @@ - - @@ -15560,10 +14336,8 @@ - - @@ -15618,7 +14392,7 @@ - + @@ -15693,7 +14467,7 @@ - + @@ -15768,7 +14542,7 @@ - + @@ -15843,7 +14617,7 @@ - + @@ -16003,7 +14777,7 @@ - + @@ -16011,6 +14785,9 @@ + + + @@ -16034,6 +14811,11 @@ + + + + + @@ -16076,6 +14858,22 @@ + + + + + + + + + + + + + + + + @@ -16310,7 +15108,7 @@ - + @@ -16545,7 +15343,7 @@ - + @@ -16944,7 +15742,7 @@ - + @@ -17351,70 +16149,70 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -18891,454 +17689,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19595,70 +17945,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19787,70 +18073,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21325,454 +19547,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22029,70 +19803,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22221,70 +19931,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23759,454 +21405,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -24463,70 +21661,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -24655,70 +21789,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -26745,21 +23815,19 @@ - - - + - + - + @@ -26797,21 +23865,13 @@ - - - + - - - - - - - + @@ -26849,21 +23909,13 @@ - - - + - - - - - - - + @@ -26950,6 +24002,7 @@ + @@ -27089,52 +24142,52 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h index bdde731cb1..1ce6856807 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -63,7 +63,7 @@ #define IRQn_XPI1 50 /* XPI1 IRQ */ #define IRQn_XDMA 51 /* XDMA IRQ */ #define IRQn_HDMA 52 /* HDMA IRQ */ -#define IRQn_DRAM 53 /* DRAM IRQ */ +#define IRQn_FEMC 53 /* FEMC IRQ */ #define IRQn_RNG 54 /* RNG IRQ */ #define IRQn_I2S0 55 /* I2S0 IRQ */ #define IRQn_I2S1 56 /* I2S1 IRQ */ @@ -456,12 +456,12 @@ /* SDP base pointer */ #define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) -#include "hpm_dram_regs.h" -/* Address of DRAM instances */ -/* DRAM base address */ -#define HPM_DRAM_BASE (0xF3050000UL) -/* DRAM base pointer */ -#define HPM_DRAM ((DRAM_Type *) HPM_DRAM_BASE) +#include "hpm_femc_regs.h" +/* Address of FEMC instances */ +/* FEMC base address */ +#define HPM_FEMC_BASE (0xF3050000UL) +/* FEMC base pointer */ +#define HPM_FEMC ((FEMC_Type *) HPM_FEMC_BASE) /* Address of ROMC instances */ /* ROMC base address */ @@ -640,8 +640,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#include "hpm_ioc_regs.h" -#include "hpm_gpiom_regs.h" -#include "hpm_sysctl_regs.h" -#include "hpm_trgm_regs.h" #endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h index d4cb0fd4c3..cec19fe25b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,6 +14,7 @@ * I2C Section */ #define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (256U) /* * PMIC Section @@ -30,6 +31,7 @@ */ #define I2S_SOC_MAX_CHANNEL_NUM (16U) #define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) +#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) #define PDM_I2S HPM_I2S0 #define DAO_I2S HPM_I2S1 #define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) @@ -55,7 +57,6 @@ #define PWM_SOC_PWM_MAX_COUNT (8U) #define PWM_SOC_CMP_MAX_COUNT (24U) #define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) -#define PWM_SOC_OUTPUT_MAX_COUNT (24U) /* * DMA Section @@ -97,35 +98,38 @@ #define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) #define USB_SOC_HCD_QTD_ALIGNMENT (32U) #define USB_SOC_HCD_QHD_ALIGNMENT (32U) -#define USB_SOC_HCD_MAX_ENDPOINT_COUNT (8U) -#define USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT (USB_SOC_HCD_MAX_ENDPOINT_COUNT * 2U) #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) #define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) /* * ENET Section */ +#define ENET_SOC_RGMII_EN (0U) #define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) #define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) #define ENET_SOC_ADDR_MAX_COUNT (5U) -#define ENET_SOC_ADVANCED_TIMESTAMP_EN (1U) -#define ENET_SOC_IPC_FULL_CHKSUM_OFFLOAD_ENGINE (0U) -#define ENET_SOC_ALT_EHD_DES_LEN (ENET_SOC_ADVANCED_TIMESTAMP_EN || ENET_SOC_IPC_FULL_CHKSUM_OFFLOAD_ENGINE) ? (8U) : (4U) +#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) +#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) +#define ENET_SOC_ALT_EHD_DES_LEN (8U) +#define ENET_SOC_PPS_MAX_COUNT (2L) +#define ENET_SOC_PPS1_EN (1U) + /* * ADC Section */ #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_MAX_TRIG_CH_NUM (11U) #define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) #define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) #define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (1024U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (4096U) #define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) #define ADC16_SOC_PARAMS_LEN (34U) #define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_TEMP_CH_NUM (16U) -#define ADC16_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) /* * SYSCTL Section @@ -177,10 +181,37 @@ * SPI Section */ #define SPI_SOC_TRANSFER_COUNT_MAX (512U) +#define SPI_SOC_FIFO_DEPTH (4U) /* * SDXC Section */ #define SDXC_SOC_MAX_COUNT (1) +/* + * ROM API section + */ +#define ROMAPI_HAS_SW_SM3 (1) +#define ROMAPI_HAS_SW_SM4 (1) + +/* + * OTP Section + */ +#define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ + +/** + * PWM Section + * + */ +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (1U) + +/** + * IOC Section + * + */ +#define IOC_SOC_PAD_MAX (487) + #endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c index ece6d90972..d03e8a864f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,7 +11,7 @@ #define SYSCTL_RESOURCE_GROUP0 0 #define SYSCTL_RESOURCE_GROUP1 1 -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24 )) +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) static inline bool sysctl_valid_cpu_index(uint8_t cpu) { @@ -147,15 +147,6 @@ hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) return _sysctl_set_cpu_entry(ptr, 0, entry); } -hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu, cpu_lp_mode_t mode) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].LP = (ptr->CPU[cpu].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); - return status_success; -} - hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource, bool enable) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h index cb10353254..22416c7dc3 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -25,22 +25,21 @@ typedef enum { sysctl_retention_domain_sys = 0, sysctl_retention_domain_cpu0 = 2, - sysctl_retention_domain_cpu1 = 4, - sysctl_retention_domain_conn = 6, - sysctl_retention_domain_vis = 8, - sysctl_retention_domain_xtal24m = 10, - sysctl_retention_domain_pll0 = 11, - sysctl_retention_domain_pll1 = 12, - sysctl_retention_domain_pll2 = 13, - sysctl_retention_domain_pll3 = 14, - sysctl_retention_domain_pll4 = 15, + + sysctl_retention_domain_xtal24m = 4, + sysctl_retention_domain_pll0 = 5, + sysctl_retention_domain_pll1 = 6, + sysctl_retention_domain_pll2 = 7, } sysctl_retention_domain_t; /** * @brief Clock presets */ typedef enum { - sysctl_preset_0 = 1 << 0, sysctl_preset_1 = 1 << 1, sysctl_preset_2 = 1 << 2, sysctl_preset_3 = 1 << 3, + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, } sysctl_preset_t; /** @@ -48,10 +47,7 @@ typedef enum { */ typedef enum { sysctl_reset_domain_soc = 0, - sysctl_reset_domain_con, - sysctl_reset_domain_vis, sysctl_reset_domain_cpu0, - sysctl_reset_domain_cpu1, } sysctl_reset_domain_t; /** @@ -91,7 +87,7 @@ typedef enum { sysctl_resource_dft_start_bus = 51, sysctl_resource_clk_top_cpu0 = 64, sysctl_resource_clk_top_mchtmr0 = 65, - sysctl_resource_clk_top_dram = 66, + sysctl_resource_clk_top_femc = 66, sysctl_resource_clk_top_xpi0 = 67, sysctl_resource_clk_top_xpi1 = 68, sysctl_resource_clk_top_gptmr0 = 69, @@ -141,7 +137,7 @@ typedef enum { sysctl_resource_usb0_mem = 194, sysctl_resource_ram0_mem = 195, sysctl_resource_ahbp_mem = 196, - sysctl_resource_dram_mem = 197, + sysctl_resource_femc_mem = 197, sysctl_resource_rom0_mem = 198, sysctl_resource_xpi0_mem = 199, sysctl_resource_xpi1_mem = 200, @@ -161,7 +157,7 @@ typedef enum { sysctl_resource_ahbp = 256, sysctl_resource_axis = 257, sysctl_resource_axic = 258, - sysctl_resource_dram = 259, + sysctl_resource_femc = 259, sysctl_resource_rom0 = 260, sysctl_resource_lmm0 = 261, sysctl_resource_ram0 = 262, @@ -238,7 +234,7 @@ typedef enum { */ typedef enum { clock_node_mchtmr0 = 0, - clock_node_dram = 1, + clock_node_femc = 1, clock_node_xpi0 = 2, clock_node_xpi1 = 3, clock_node_gptmr0 = 4, @@ -336,34 +332,27 @@ typedef enum { monitor_target_clk_irc24m = 1, monitor_target_clk_xtal_24m = 2, monitor_target_clk_usb0_phy = 3, - monitor_target_clk_usb1_phy = 4, + monitor_target_clk0_osc0 = 8, monitor_target_clk0_pll0 = 9, - monitor_target_clk0_pll1 = 10, - monitor_target_clk1_pll1 = 11, - monitor_target_clk0_pll2 = 12, - monitor_target_clk1_pll2 = 13, - monitor_target_clk0_pll3 = 14, - monitor_target_clk0_pll4 = 15, + monitor_target_clk1_pll0 = 10, + monitor_target_clk2_pll0 = 11, + monitor_target_clk0_pll1 = 12, + monitor_target_clk1_pll1 = 13, + monitor_target_clk0_pll2 = 14, + monitor_target_clk1_pll2 = 15, + monitor_target_clk_top_cpu0 = 128, monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_cpu1 = 130, - monitor_target_clk_top_mchtmr1 = 131, - monitor_target_clk_top_axi0 = 132, - monitor_target_clk_top_axi1 = 133, - monitor_target_clk_top_axi2 = 134, - monitor_target_clk_top_ahb0 = 135, - monitor_target_clk_top_dram = 136, + + monitor_target_clk_top_femc = 136, monitor_target_clk_top_xpi0 = 137, monitor_target_clk_top_xpi1 = 138, monitor_target_clk_top_gptmr0 = 139, monitor_target_clk_top_gptmr1 = 140, monitor_target_clk_top_gptmr2 = 141, monitor_target_clk_top_gptmr3 = 142, - monitor_target_clk_top_gptmr4 = 143, - monitor_target_clk_top_gptmr5 = 144, - monitor_target_clk_top_gptmr6 = 145, - monitor_target_clk_top_gptmr7 = 146, + monitor_target_clk_top_uart0 = 147, monitor_target_clk_top_uart1 = 148, monitor_target_clk_top_uart2 = 149, @@ -372,14 +361,7 @@ typedef enum { monitor_target_clk_top_uart5 = 152, monitor_target_clk_top_uart6 = 153, monitor_target_clk_top_uart7 = 154, - monitor_target_clk_top_uart8 = 155, - monitor_target_clk_top_uart9 = 156, - monitor_target_clk_top_uarta = 157, - monitor_target_clk_top_uartb = 158, - monitor_target_clk_top_uartc = 159, - monitor_target_clk_top_uartd = 160, - monitor_target_clk_top_uarte = 161, - monitor_target_clk_top_uartf = 162, + monitor_target_clk_top_i2c0 = 163, monitor_target_clk_top_i2c1 = 164, monitor_target_clk_top_i2c2 = 165, @@ -390,51 +372,58 @@ typedef enum { monitor_target_clk_top_spi3 = 170, monitor_target_clk_top_can0 = 171, monitor_target_clk_top_can1 = 172, - monitor_target_clk_top_can2 = 173, - monitor_target_clk_top_can3 = 174, + monitor_target_clk_top_ptpc = 175, monitor_target_clk_top_ana0 = 176, monitor_target_clk_top_ana1 = 177, monitor_target_clk_top_ana2 = 178, - monitor_target_clk_top_aud0 = 179, - monitor_target_clk_top_aud1 = 180, - monitor_target_clk_top_aud2 = 181, - monitor_target_clk_top_dis0 = 182, - monitor_target_clk_top_cam0 = 183, - monitor_target_clk_top_cam1 = 184, + monitor_target_clk_top_ana3 = 179, + monitor_target_clk_top_aud0 = 180, + monitor_target_clk_top_aud1 = 181, + monitor_target_clk_top_eth0 = 185, - monitor_target_clk_top_eth1 = 186, + monitor_target_clk_top_ptp0 = 187, - monitor_target_clk_top_ptp1 = 188, + monitor_target_clk_top_ref0 = 189, monitor_target_clk_top_ref1 = 190, monitor_target_clk_top_ntmr0 = 191, - monitor_target_clk_top_ntmr1 = 192, + monitor_target_clk_top_sdxc0 = 193, - monitor_target_clk_top_sdxc1 = 194, + } monitor_target_t; /** * @brief Monitor work mode */ typedef enum { - monitor_work_mode_compare = 0, monitor_work_mode_record = 1, + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, } monitor_work_mode_t; /** * @brief Monitor accuracy */ typedef enum { - monitor_accuracy_1khz = 0, monitor_accuracy_1hz = 1, + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, } monitor_accuracy_t; /** * @brief Monitor reference clock source */ typedef enum { - monitor_reference_32khz = 0, monitor_reference_24mhz = 1, + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, } monitor_reference_t; +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + /** * @brief Monitor config */ @@ -648,11 +637,23 @@ sysctl_resource_target_set_mode(SYSCTL_Type *ptr, sysctl_resource_t resource, sy * @param[in] cpu_index cpu index * @param[in] mask bit mask to clear */ -static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) { ptr->RETENTION[cpu_index].CLEAR = mask; } +/** + * @brief Disable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, + uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); +} + /** * @brief Enable resource retention when specific CPU enters stop mode * @@ -660,11 +661,60 @@ static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, uin * @param[in] cpu_index cpu index * @param[in] mask bit mask to set */ -static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) { ptr->RETENTION[cpu_index].SET = mask; } +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, + uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, + uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + /** * @brief Retain target domain for specific CPU * @@ -674,7 +724,7 @@ static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, uint8 * @param[in] retain_mem set true to retain memory/register of target domain */ static inline void -sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, uint8_t cpu_index, sysctl_retention_domain_t domain, bool retain_mem) +sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, uint8_t cpu_index, sysctl_retention_domain_t domain, bool retain_mem) { uint8_t set_mask = 0x1; if (domain < sysctl_retention_domain_xtal24m) { @@ -683,6 +733,20 @@ sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, uint8_t cpu_index, sysctl_retentio ptr->RETENTION[cpu_index].SET = (set_mask << domain); } +/** + * @brief Retain target domain for specific CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); +} + /** * @brief Check if cpu clock is busy * @@ -798,6 +862,19 @@ static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; } +/** + * @brief Get target CPU0 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, + uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 0, status_index); +} + /** * @brief Check wakeup source status with mask * @@ -813,6 +890,22 @@ sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; } +/** + * @brief Check CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline + uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); +} + /** * @brief Enable wakeup source status with mask * @@ -827,6 +920,20 @@ sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint8 ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; } +/** + * @brief Enable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; +} + /** * @brief Disable wakeup source status with mask * @@ -841,6 +948,21 @@ sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; } +/** + * @brief Disable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); +} + + /** * @brief Disable wakeup source status with irq * @@ -853,6 +975,19 @@ static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8 ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); } +/** + * @brief Disable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); +} + + /** * @brief Enable wakeup source status with irq * @@ -862,18 +997,57 @@ static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8 */ static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) { - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num % 32); + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); } +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Lock CPU gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint16_t gpr_mask) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + + /** * @brief Lock CPU0 gpr with mask * * @param[in] ptr SYSCTL_Type base address * @param[in] gpr_mask bit mask of gpr registers to be locked */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, + uint16_t gpr_mask) { - ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); + sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); +} + +/** + * @brief Lock CPU lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; } /** @@ -883,7 +1057,76 @@ static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr */ static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) { - ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; + sysctl_cpu_lock(ptr, 0); +} + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) +{ + ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); +} + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 0, mode); +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Get CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); +} + +/** + * @brief Get CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 0); } /** @@ -919,16 +1162,6 @@ hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t sour */ hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_i2s_t source); -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mode target mode to set - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode); - /** * @brief Enable group resource * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h index ffe34cb8c9..6e9f31b3bd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -1053,10 +1053,10 @@ typedef struct { * * register for software to handle resume, can save resume address or status */ -#define SYSCTL_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_GPR_GPR_SHIFT (0U) -#define SYSCTL_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_GPR_GPR_SHIFT) & SYSCTL_GPR_GPR_MASK) -#define SYSCTL_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_GPR_GPR_MASK) >> SYSCTL_GPR_GPR_SHIFT) +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) /* Bitfield definition for register of struct array CPU: STATUS0 */ /* @@ -1064,9 +1064,9 @@ typedef struct { * * IRQ values */ -#define SYSCTL_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_WAKEUP_STATUS_STATUS_SHIFT) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) /* Bitfield definition for register of struct array CPU: ENABLE0 */ /* @@ -1074,10 +1074,10 @@ typedef struct { * * IRQ wakeup enable */ -#define SYSCTL_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) @@ -1103,7 +1103,7 @@ typedef struct { #define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL) #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) -#define SYSCTL_RESOURCE_CLK_TOP_DRAM (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_FEMC (66UL) #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL) #define SYSCTL_RESOURCE_CLK_TOP_XPI1 (68UL) #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (69UL) @@ -1150,7 +1150,7 @@ typedef struct { #define SYSCTL_RESOURCE_AHBP (256UL) #define SYSCTL_RESOURCE_AXIS (257UL) #define SYSCTL_RESOURCE_AXIC (258UL) -#define SYSCTL_RESOURCE_DRAM (259UL) +#define SYSCTL_RESOURCE_FEMC (259UL) #define SYSCTL_RESOURCE_ROM0 (260UL) #define SYSCTL_RESOURCE_LMM0 (261UL) #define SYSCTL_RESOURCE_RAM0 (262UL) @@ -1232,7 +1232,7 @@ typedef struct { /* CLOCK register group index macro definition */ #define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) -#define SYSCTL_CLOCK_CLK_TOP_DRAM (1UL) +#define SYSCTL_CLOCK_CLK_TOP_FEMC (1UL) #define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL) #define SYSCTL_CLOCK_CLK_TOP_XPI1 (3UL) #define SYSCTL_CLOCK_CLK_TOP_TMR0 (4UL) @@ -1321,4 +1321,4 @@ typedef struct { #define SYSCTL_CPU_CPU0 (0UL) -#endif /* HPM_SYSCTL_H */ \ No newline at end of file +#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h index e34cb1bd5e..e737a08c7b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -226,4 +226,4 @@ typedef struct { #define TRGM_DMACFG_3 (3UL) -#endif /* HPM_TRGM_H */ \ No newline at end of file +#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h index 8fcaecc9d1..d5a723d17a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,18 +12,18 @@ /* trgm0_input mux definitions */ #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN0 (0x2UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN1 (0x3UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN2 (0x4UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN3 (0x5UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN4 (0x6UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN5 (0x7UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN6 (0x8UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN7 (0x9UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN8 (0xAUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN9 (0xBUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN10 (0xCUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN11 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) @@ -367,4 +367,4 @@ -#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file +#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list index 99fa6f61a8..4c1e15a065 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list @@ -1,10 +1,10 @@ -# Copyright 2022 hpmicro +# Copyright (c) 2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # In this file, all modules available on this part are listed CONFIG_HAS_HPMSDK_UART=y -CONFIG_HAS_HPMSDK_DRAM=y +CONFIG_HAS_HPMSDK_FEMC=y CONFIG_HAS_HPMSDK_SDP=y CONFIG_HAS_HPMSDK_I2C=y CONFIG_HAS_HPMSDK_PMP=y diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c index d6396d9d6f..3f742ad69a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,6 +10,10 @@ #include "hpm_soc.h" #include "hpm_l1c_drv.h" +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + void enable_plic_feature(void) { uint32_t plic_feature = 0; @@ -17,7 +21,7 @@ void enable_plic_feature(void) /* enabled vector mode and preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; #endif -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) /* enabled preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; #endif @@ -48,10 +52,14 @@ __attribute__((weak)) void system_init(void) #ifdef USE_S_MODE_IRQ delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif #else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif +#endif #ifndef CONFIG_NOT_ENABLE_ICACHE l1c_ic_enable(); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld index 1bf808a0e4..53680819fb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld @@ -1,5 +1,5 @@ /* - * Copyright 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,11 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (wx) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } SECTIONS @@ -50,6 +51,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -122,9 +132,9 @@ SECTIONS *(.fast) . = ALIGN(8); __ramfunc_end__ = .; - } > AXI_SRAM + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -139,13 +149,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > DLM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > AXI_SRAM .framebuffer (NOLOAD) : { @@ -154,11 +157,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) @@ -166,7 +174,22 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM_NONCACHEABLE - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; @@ -177,4 +200,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld index ffe3ebf65d..8b78e8ec14 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld @@ -1,5 +1,5 @@ /* - * Copyright 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,11 +12,12 @@ UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20 MEMORY { XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM : ORIGIN = 0x0, LENGTH = 128K - DLM : ORIGIN = 0x80000, LENGTH = 128K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } SECTIONS @@ -52,6 +53,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -68,7 +78,6 @@ SECTIONS __vector_ram_end__ = .; } > ILM - .data : AT(etext) { . = ALIGN(8); __data_start__ = .; @@ -128,9 +137,9 @@ SECTIONS *(.fast) . = ALIGN(8); __ramfunc_end__ = .; - } > AXI_SRAM + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -145,13 +154,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > AXI_SRAM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > SDRAM .framebuffer (NOLOAD) : { @@ -160,11 +162,16 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) @@ -172,13 +179,28 @@ SECTIONS . = ALIGN(8); } > SDRAM_NONCACHEABLE - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; . = ALIGN(8); PROVIDE (_stack = .); - PROVIDE (_stack_in_dlm = .); + PROVIDE (_stack_safe = .); } > DLM __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld index 314ed67616..7d957c2972 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld @@ -1,5 +1,5 @@ /* - * Copyright 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,11 +11,12 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM : ORIGIN = 0, LENGTH = 128K - DLM : ORIGIN = 0x80000, LENGTH = 128K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -69,6 +70,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -85,7 +95,6 @@ SECTIONS __vector_ram_end__ = .; } > ILM - .data : AT(etext) { . = ALIGN(8); __data_start__ = .; @@ -145,10 +154,10 @@ SECTIONS *(.fast) . = ALIGN(8); __ramfunc_end__ = .; - } > AXI_SRAM + } > ILM __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -163,13 +172,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > AXI_SRAM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > SDRAM .framebuffer (NOLOAD) : { @@ -178,11 +180,16 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) @@ -190,7 +197,22 @@ SECTIONS . = ALIGN(8); } > SDRAM_NONCACHEABLE - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld index 9badc91602..f2cce578a9 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld @@ -1,5 +1,5 @@ /* - * Copyright 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,10 +12,11 @@ UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20 MEMORY { XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (wx) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } SECTIONS @@ -51,6 +52,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -126,9 +136,9 @@ SECTIONS *(.fast) . = ALIGN(8); __ramfunc_end__ = .; - } > AXI_SRAM + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -143,13 +153,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > DLM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > AXI_SRAM .framebuffer (NOLOAD) : { @@ -158,11 +161,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) @@ -170,7 +178,22 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM_NONCACHEABLE - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; @@ -181,4 +204,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld index 1807e0eef0..412c1d320c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld @@ -1,5 +1,5 @@ /* - * Copyright 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,11 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (wx) : ORIGIN = 0x80000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -68,6 +69,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -143,10 +153,10 @@ SECTIONS *(.fast) . = ALIGN(8); __ramfunc_end__ = .; - } > AXI_SRAM + } > ILM __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -161,13 +171,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > DLM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > AXI_SRAM .framebuffer (NOLOAD) : { @@ -176,11 +179,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) @@ -188,7 +196,22 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM_NONCACHEABLE - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; @@ -199,4 +222,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/initfini.c new file mode 100644 index 0000000000..7d2b85799c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld index 5c082c283d..0aec08c67b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld @@ -1,5 +1,5 @@ /* - * Copyright 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,13 +10,11 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K - /* It's alias address of core0 ILM+DLM, but accessing via system bus */ - CORE0_LM_SLV (wx) : ORIGIN = 0x1040000, LENGTH = 256K - - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } SECTIONS @@ -58,6 +56,13 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); PROVIDE (__etext = .); @@ -117,7 +122,7 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > DLM + } > AXI_SRAM .fast : AT(etext + __data_end__ - __data_start__) { . = ALIGN(8); @@ -125,9 +130,9 @@ SECTIONS *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -142,29 +147,24 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > DLM + } > AXI_SRAM .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > AXI_SRAM - - .dual_core_share (NOLOAD) : { - KEEP(*(.dual_core_share)) - } > AXI_SRAM - - .heap : { . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM - } > DLM - - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) @@ -172,7 +172,22 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM_NONCACHEABLE - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; @@ -183,5 +198,5 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT(__stack_base__ >= __heap_end__, "stack overlapped with heap") + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S index 53fc18f75a..a862981d75 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -40,6 +40,24 @@ _start: la t0, _stack mv sp, t0 + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + #ifndef NO_CLEANUP_AT_START /* clean up */ call _clean_up @@ -51,12 +69,27 @@ _start: csrw uitb, t0 #endif -#ifndef CONFIG_FREERTOS - #define HANDLER_TRAP SW_handler - #define HANDLER_S_TRAP irq_handler_s_trap -#else +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS #define HANDLER_TRAP freertos_risc_v_trap_handler #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap #endif #ifndef USE_NONVECTOR_MODE diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c index f25b2e75b9..626e5dec16 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c @@ -1,5 +1,5 @@ /* - * Copyright 2022 hpmicro + * Copyright (c) 2022 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,15 +9,9 @@ #include "hpm_l1c_drv.h" #include "hpm_interrupt.h" -#ifdef __cplusplus -extern "C" { -#endif + extern void system_init(void); -extern void __libc_init_array(void); -extern void __libc_fini_array(void); -#ifdef __cplusplus -} -#endif + __attribute__((weak)) void _clean_up(void) { @@ -93,22 +87,10 @@ __attribute__((weak)) void reset_handler(void) { l1c_dc_disable(); l1c_dc_invalidate_all(); -#if !defined(__SEGGER_RTL_VERSION) || defined(__GNU_LINKER) - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); -#endif /* Call platform specific hardware initialization */ system_init(); -#ifdef __cplusplus - /* Do global constructors */ - __libc_init_array(); -#endif - /* Entry function */ main(); } @@ -118,12 +100,12 @@ __attribute__((weak)) void reset_handler(void) * a call to __cxa_atexit() with __dso_handle as one of the arguments. * The dummy versions of these symbols should be provided. */ -void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) { } -#ifndef __SEGGER_RTL_VERSION -void* __dso_handle = (void *) &__dso_handle; +#if !defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes) +void *__dso_handle = (void *) &__dso_handle; #endif __attribute__((weak)) void _init(void) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf index 846a935841..49c9d960d2 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf @@ -1,89 +1,95 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x0 size 128k]; /* ILM */ -define region DLM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.* // "ramfunc" section + }; +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf index e2e66adf50..3375a1f678 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf @@ -1,85 +1,96 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH ]; -define region AXI_SRAM = [from 0x1040000 size 768K]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of AXI_SRAM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 512k]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in SDRAM { block cherryusb_usbh_class_info }; +place in SDRAM { block framebuffer }; +place in AXI_SRAM then SDRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in SDRAM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .uf2_signature }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf index 99ca6bbe92..4ece100f24 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf @@ -1,98 +1,106 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x0 size 256K]; -define region DLM = [from 0x80000 size 256K]; -define region AXI_SRAM = [from 0x1080000 size 512K]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM with auto order { block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 512k]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in SDRAM { block cherryusb_usbh_class_info }; +place in SDRAM { block framebuffer }; +place in AXI_SRAM then SDRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in SDRAM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf index 9e99e1e753..bdac6a9b9f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf @@ -1,87 +1,97 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0 size 128k]; /* ILM slave */ -define region DLM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of ILM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .uf2_signature }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf index 8ead4f2e24..6a7fa6d009 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf @@ -1,98 +1,107 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0 size 128k]; /* ILM */ -define region DLM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM with fixed order { block vectors, block vectors_s }; -initialize by copy { block vectors, block vectors_s }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section - -place in DLM with auto order { block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf index c618182147..1b5d3d7af6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf @@ -1,78 +1,91 @@ -/* - * Copyright 2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0 size 128k]; /* ILM */ -define region RAM = [from 0x80000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x10C0000 size 256K]; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; -define block safe_stack with size = 512, readwrite access {}; -define exported symbol _stack_safe = end of block safe_stack + 1; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block framebuffer { section .framebuffer }; - - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -/* Explicit placement in AXI_SRAM */ -place in AXI_SRAM { block framebuffer }; - -place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in RAM { block heap }; // Heap reserved block -place at end of RAM { block stack, block safe_stack }; // Stack reserved block at the end +/* + * Copyright (c) 2022-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors, block vectors_s }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s index 9e77d4215b..523086e602 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s @@ -38,20 +38,20 @@ File : SEGGER_RISCV_crt0.s Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce + Designed to work with the SEGGER linker to produce smallest possible executables. - + This file does not normally require any customization. Additional information: Preprocessor Definitions FULL_LIBRARY - If defined then + If defined then - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - the exit symbol is defined and executes on return from main. - the exit symbol calls destructors, atexit functions and then calls SEGGER_SEMIHOST_Exit(). - + If not defined then - argc and argv are not valid (main is assumed to not take parameters) - the exit symbol is defined, executes on return from main and @@ -147,16 +147,16 @@ Additional information: * _start * * Function description -* Entry point for the startup code. +* Entry point for the startup code. * Usually called by the reset handler. -* Performs all initialisation, based on the entries in the +* Performs all initialisation, based on the entries in the * linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an +* It is device independent, so there should not be any need for an * end-user to modify it. * * Additional information -* At this point, the stack pointer should already have been -* initialized +* At this point, the stack pointer should already have been +* initialized * - by hardware (such as on Cortex-M), * - by the device-specific reset handler, * - or by the debugger (such as for RAM Code). @@ -223,12 +223,27 @@ MARK_FUNC __SEGGER_init_done call _clean_up #endif -#ifndef CONFIG_FREERTOS - #define HANDLER_TRAP SW_handler - #define HANDLER_S_TRAP irq_handler_s_trap -#else +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS #define HANDLER_TRAP freertos_risc_v_trap_handler #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap #endif #if !defined(USE_NONVECTOR_MODE) @@ -321,14 +336,14 @@ END_FUNC _start * * Function description * Exit of the system. -* Called on return from application entry point or explicit call +* Called on return from application entry point or explicit call * to exit. * * Additional information * In a hosted environment exit gracefully, by * saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, +* calling destructurs of global objects, +* calling registered atexit functions, * and notifying the host/debugger. */ #undef L diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c index 608c0d55e8..4a38669a36 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -99,17 +99,17 @@ __attribute__((weak)) void mchtmr_s_isr(void) { } -#ifndef CONFIG_FREERTOS -void SW_handler(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); #else -void SW_handler(void) __attribute__ ((section(".isr_vector"))); +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); #endif -void SW_handler(void) +void irq_handler_trap(void) { long mcause = read_csr(CSR_MCAUSE); long mepc = read_csr(CSR_MEPC); long mstatus = read_csr(CSR_MSTATUS); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH long mxstatus = read_csr(CSR_MXSTATUS); #endif #ifdef __riscv_dsp @@ -140,7 +140,7 @@ void SW_handler(void) uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); if (irq_index) { /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif ((isr_func_t)__vector_table[irq_index])(); @@ -176,7 +176,7 @@ void SW_handler(void) /* Restore CSR */ write_csr(CSR_MSTATUS, mstatus); write_csr(CSR_MEPC, mepc); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH write_csr(CSR_MXSTATUS, mxstatus); #endif #ifdef __riscv_dsp @@ -217,7 +217,7 @@ void irq_handler_s_trap(void) /* Machine-level interrupt from PLIC */ uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) enable_s_global_irq(CSR_SSTATUS_SIE_MASK); #endif ((isr_func_t)__vector_s_table[irq_index])(); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h index bc4e4434ad..27938d76ef 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -22,7 +22,7 @@ default_irq_handler: __vector_table: .weak default_isr_trap - .set default_isr_trap, SW_handler + .set default_isr_trap, irq_handler_trap .long default_isr_trap IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ @@ -76,7 +76,7 @@ __vector_table: IRQ_HANDLER 50 /* XPI1 IRQ handler */ IRQ_HANDLER 51 /* XDMA IRQ handler */ IRQ_HANDLER 52 /* HDMA IRQ handler */ - IRQ_HANDLER 53 /* DRAM IRQ handler */ + IRQ_HANDLER 53 /* FEMC IRQ handler */ IRQ_HANDLER 54 /* RNG IRQ handler */ IRQ_HANDLER 55 /* I2S0 IRQ handler */ IRQ_HANDLER 56 /* I2S1 IRQ handler */ @@ -176,7 +176,7 @@ __vector_s_table: IRQ_S_HANDLER 50 /* XPI1 IRQ handler */ IRQ_S_HANDLER 51 /* XDMA IRQ handler */ IRQ_S_HANDLER 52 /* HDMA IRQ handler */ - IRQ_S_HANDLER 53 /* DRAM IRQ handler */ + IRQ_S_HANDLER 53 /* FEMC IRQ handler */ IRQ_S_HANDLER 54 /* RNG IRQ handler */ IRQ_S_HANDLER 55 /* I2S0 IRQ handler */ IRQ_S_HANDLER 56 /* I2S1 IRQ handler */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml deleted file mode 100644 index 4cb4a912c3..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml +++ /dev/null @@ -1,133497 +0,0 @@ - - - HPMICRO - HPM6750 - HPM6700/HPM6400 - 1.0 - HPM6700/HPM6400 device - - /* - * Copyright (c) 2021-2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - 8 - 32 - - 32 - 0x0 - 0xFFFFFFFF - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - DI_GPIOA_VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOA_SET - GPIO input set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOA_CLEAR - GPIO input clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOA_TOGGLE - GPIO input toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_VALUE - GPIOB input - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_SET - GPIO input set - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_CLEAR - GPIO input clear - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOB_TOGGLE - GPIO input toggle - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_VALUE - GPIOC input - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_SET - GPIO input set - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_CLEAR - GPIO input clear - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOC_TOGGLE - GPIO input toggle - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOD_VALUE - GPIOD input - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOD_SET - GPIO input set - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOD_CLEAR - GPIO input clear - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOD_TOGGLE - GPIO input toggle - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOE_VALUE - GPIOE input - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOE_SET - GPIO input set - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOE_CLEAR - GPIO input clear - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOE_TOGGLE - GPIO input toggle - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOF_VALUE - GPIOF input - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOF_SET - GPIO input set - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOF_CLEAR - GPIO input clear - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOF_TOGGLE - GPIO input toggle - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_VALUE - GPIOX input - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_SET - GPIO input set - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_CLEAR - GPIO input clear - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOX_TOGGLE - GPIO input toggle - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_VALUE - GPIOY input - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_SET - GPIO input set - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_CLEAR - GPIO input clear - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOY_TOGGLE - GPIO input toggle - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_VALUE - GPIOZ input - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_SET - GPIO input set - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_CLEAR - GPIO input clear - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DI_GPIOZ_TOGGLE - GPIO input toggle - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-write - - - - - DO_GPIOA_VALUE - GPIO output value - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOA_SET - GPIO output set - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOA_CLEAR - GPIO output clear - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOA_TOGGLE - GPIO output toggle - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_VALUE - GPIOB output - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_SET - GPIO output set - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_CLEAR - GPIO output clear - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOB_TOGGLE - GPIO output toggle - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_VALUE - GPIOC output - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_SET - GPIO output set - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_CLEAR - GPIO output clear - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOC_TOGGLE - GPIO output toggle - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOD_VALUE - GPIOD output - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOD_SET - GPIO output set - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOD_CLEAR - GPIO output clear - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOD_TOGGLE - GPIO output toggle - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOE_VALUE - GPIOE output - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOE_SET - GPIO output set - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOE_CLEAR - GPIO output clear - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOE_TOGGLE - GPIO output toggle - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOF_VALUE - GPIOF output - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOF_SET - GPIO output set - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOF_CLEAR - GPIO output clear - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOF_TOGGLE - GPIO output toggle - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_VALUE - GPIOX output - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_SET - GPIO output set - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_CLEAR - GPIO output clear - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOX_TOGGLE - GPIO output toggle - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_VALUE - GPIOY output - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_SET - GPIO output set - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_CLEAR - GPIO output clear - 0x1e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOY_TOGGLE - GPIO output toggle - 0x1ec - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_VALUE - GPIOZ output - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_SET - GPIO output set - 0x1f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_CLEAR - GPIO output clear - 0x1f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - DO_GPIOZ_TOGGLE - GPIO output toggle - 0x1fc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - OE_GPIOA_VALUE - GPIO direction value - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOA_SET - GPIO direction set - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOA_CLEAR - GPIO direction clear - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOA_TOGGLE - GPIO direction toggle - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_VALUE - GPIOB direction - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_SET - GPIO direction set - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_CLEAR - GPIO direction clear - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOB_TOGGLE - GPIO direction toggle - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_VALUE - GPIOC direction - 0x220 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_SET - GPIO direction set - 0x224 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_CLEAR - GPIO direction clear - 0x228 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOC_TOGGLE - GPIO direction toggle - 0x22c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOD_VALUE - GPIOD direction - 0x230 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOD_SET - GPIO direction set - 0x234 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOD_CLEAR - GPIO direction clear - 0x238 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOD_TOGGLE - GPIO direction toggle - 0x23c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOE_VALUE - GPIOE direction - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOE_SET - GPIO direction set - 0x244 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOE_CLEAR - GPIO direction clear - 0x248 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOE_TOGGLE - GPIO direction toggle - 0x24c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOF_VALUE - GPIOF direction - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOF_SET - GPIO direction set - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOF_CLEAR - GPIO direction clear - 0x258 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOF_TOGGLE - GPIO direction toggle - 0x25c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_VALUE - GPIOX direction - 0x2d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_SET - GPIO direction set - 0x2d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_CLEAR - GPIO direction clear - 0x2d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOX_TOGGLE - GPIO direction toggle - 0x2dc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_VALUE - GPIOY direction - 0x2e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_SET - GPIO direction set - 0x2e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_CLEAR - GPIO direction clear - 0x2e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOY_TOGGLE - GPIO direction toggle - 0x2ec - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_VALUE - GPIOZ direction - 0x2f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_SET - GPIO direction set - 0x2f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_CLEAR - GPIO direction clear - 0x2f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - OE_GPIOZ_TOGGLE - GPIO direction toggle - 0x2fc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - IF_GPIOA_VALUE - GPIO interrupt flag value - 0x300 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOA_SET - GPIO interrupt flag set - 0x304 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOA_CLEAR - GPIO interrupt flag clear - 0x308 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOA_TOGGLE - GPIO interrupt flag toggle - 0x30c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_VALUE - GPIOB interrupt flag - 0x310 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_SET - GPIO interrupt flag set - 0x314 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_CLEAR - GPIO interrupt flag clear - 0x318 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOB_TOGGLE - GPIO interrupt flag toggle - 0x31c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_VALUE - GPIOC interrupt flag - 0x320 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_SET - GPIO interrupt flag set - 0x324 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_CLEAR - GPIO interrupt flag clear - 0x328 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOC_TOGGLE - GPIO interrupt flag toggle - 0x32c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOD_VALUE - GPIOD interrupt flag - 0x330 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOD_SET - GPIO interrupt flag set - 0x334 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOD_CLEAR - GPIO interrupt flag clear - 0x338 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOD_TOGGLE - GPIO interrupt flag toggle - 0x33c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOE_VALUE - GPIOE interrupt flag - 0x340 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOE_SET - GPIO interrupt flag set - 0x344 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOE_CLEAR - GPIO interrupt flag clear - 0x348 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOE_TOGGLE - GPIO interrupt flag toggle - 0x34c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOF_VALUE - GPIOF interrupt flag - 0x350 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOF_SET - GPIO interrupt flag set - 0x354 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOF_CLEAR - GPIO interrupt flag clear - 0x358 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOF_TOGGLE - GPIO interrupt flag toggle - 0x35c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_VALUE - GPIOX interrupt flag - 0x3d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_SET - GPIO interrupt flag set - 0x3d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_CLEAR - GPIO interrupt flag clear - 0x3d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOX_TOGGLE - GPIO interrupt flag toggle - 0x3dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_VALUE - GPIOY interrupt flag - 0x3e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_SET - GPIO interrupt flag set - 0x3e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_CLEAR - GPIO interrupt flag clear - 0x3e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOY_TOGGLE - GPIO interrupt flag toggle - 0x3ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_VALUE - GPIOZ interrupt flag - 0x3f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_SET - GPIO interrupt flag set - 0x3f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_CLEAR - GPIO interrupt flag clear - 0x3f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IF_GPIOZ_TOGGLE - GPIO interrupt flag toggle - 0x3fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - read-write - - - - - IE_GPIOA_VALUE - GPIO interrupt enable value - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOA_SET - GPIO interrupt enable set - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOA_CLEAR - GPIO interrupt enable clear - 0x408 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOA_TOGGLE - GPIO interrupt enable toggle - 0x40c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_VALUE - GPIOB interrupt enable - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_SET - GPIO interrupt enable set - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_CLEAR - GPIO interrupt enable clear - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOB_TOGGLE - GPIO interrupt enable toggle - 0x41c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_VALUE - GPIOC interrupt enable - 0x420 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_SET - GPIO interrupt enable set - 0x424 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_CLEAR - GPIO interrupt enable clear - 0x428 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOC_TOGGLE - GPIO interrupt enable toggle - 0x42c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOD_VALUE - GPIOD interrupt enable - 0x430 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOD_SET - GPIO interrupt enable set - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOD_CLEAR - GPIO interrupt enable clear - 0x438 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOD_TOGGLE - GPIO interrupt enable toggle - 0x43c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOE_VALUE - GPIOE interrupt enable - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOE_SET - GPIO interrupt enable set - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOE_CLEAR - GPIO interrupt enable clear - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOE_TOGGLE - GPIO interrupt enable toggle - 0x44c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOF_VALUE - GPIOF interrupt enable - 0x450 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOF_SET - GPIO interrupt enable set - 0x454 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOF_CLEAR - GPIO interrupt enable clear - 0x458 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOF_TOGGLE - GPIO interrupt enable toggle - 0x45c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_VALUE - GPIOX interrupt enable - 0x4d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_SET - GPIO interrupt enable set - 0x4d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_CLEAR - GPIO interrupt enable clear - 0x4d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOX_TOGGLE - GPIO interrupt enable toggle - 0x4dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_VALUE - GPIOY interrupt enable - 0x4e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_SET - GPIO interrupt enable set - 0x4e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_CLEAR - GPIO interrupt enable clear - 0x4e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOY_TOGGLE - GPIO interrupt enable toggle - 0x4ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_VALUE - GPIOZ interrupt enable - 0x4f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_SET - GPIO interrupt enable set - 0x4f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_CLEAR - GPIO interrupt enable clear - 0x4f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - IE_GPIOZ_TOGGLE - GPIO interrupt enable toggle - 0x4fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - PL_GPIOA_VALUE - GPIO interrupt polarity value - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOA_SET - GPIO interrupt polarity set - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOA_CLEAR - GPIO interrupt polarity clear - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOA_TOGGLE - GPIO interrupt polarity toggle - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_VALUE - GPIOB interrupt polarity - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_SET - GPIO interrupt polarity set - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_CLEAR - GPIO interrupt polarity clear - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOB_TOGGLE - GPIO interrupt polarity toggle - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_VALUE - GPIOC interrupt polarity - 0x520 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_SET - GPIO interrupt polarity set - 0x524 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_CLEAR - GPIO interrupt polarity clear - 0x528 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOC_TOGGLE - GPIO interrupt polarity toggle - 0x52c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOD_VALUE - GPIOD interrupt polarity - 0x530 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOD_SET - GPIO interrupt polarity set - 0x534 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOD_CLEAR - GPIO interrupt polarity clear - 0x538 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOD_TOGGLE - GPIO interrupt polarity toggle - 0x53c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOE_VALUE - GPIOE interrupt polarity - 0x540 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOE_SET - GPIO interrupt polarity set - 0x544 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOE_CLEAR - GPIO interrupt polarity clear - 0x548 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOE_TOGGLE - GPIO interrupt polarity toggle - 0x54c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOF_VALUE - GPIOF interrupt polarity - 0x550 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOF_SET - GPIO interrupt polarity set - 0x554 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOF_CLEAR - GPIO interrupt polarity clear - 0x558 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOF_TOGGLE - GPIO interrupt polarity toggle - 0x55c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_VALUE - GPIOX interrupt polarity - 0x5d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_SET - GPIO interrupt polarity set - 0x5d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_CLEAR - GPIO interrupt polarity clear - 0x5d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOX_TOGGLE - GPIO interrupt polarity toggle - 0x5dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_VALUE - GPIOY interrupt polarity - 0x5e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_SET - GPIO interrupt polarity set - 0x5e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_CLEAR - GPIO interrupt polarity clear - 0x5e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOY_TOGGLE - GPIO interrupt polarity toggle - 0x5ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_VALUE - GPIOZ interrupt polarity - 0x5f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_SET - GPIO interrupt polarity set - 0x5f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_CLEAR - GPIO interrupt polarity clear - 0x5f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - PL_GPIOZ_TOGGLE - GPIO interrupt polarity toggle - 0x5fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TP_GPIOA_VALUE - GPIO interrupt type value - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOA_SET - GPIO interrupt type set - 0x604 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOA_CLEAR - GPIO interrupt type clear - 0x608 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOA_TOGGLE - GPIO interrupt type toggle - 0x60c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_VALUE - GPIOB interrupt type - 0x610 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_SET - GPIO interrupt type set - 0x614 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_CLEAR - GPIO interrupt type clear - 0x618 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOB_TOGGLE - GPIO interrupt type toggle - 0x61c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_VALUE - GPIOC interrupt type - 0x620 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_SET - GPIO interrupt type set - 0x624 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_CLEAR - GPIO interrupt type clear - 0x628 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOC_TOGGLE - GPIO interrupt type toggle - 0x62c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOD_VALUE - GPIOD interrupt type - 0x630 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOD_SET - GPIO interrupt type set - 0x634 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOD_CLEAR - GPIO interrupt type clear - 0x638 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOD_TOGGLE - GPIO interrupt type toggle - 0x63c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOE_VALUE - GPIOE interrupt type - 0x640 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOE_SET - GPIO interrupt type set - 0x644 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOE_CLEAR - GPIO interrupt type clear - 0x648 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOE_TOGGLE - GPIO interrupt type toggle - 0x64c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOF_VALUE - GPIOF interrupt type - 0x650 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOF_SET - GPIO interrupt type set - 0x654 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOF_CLEAR - GPIO interrupt type clear - 0x658 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOF_TOGGLE - GPIO interrupt type toggle - 0x65c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_VALUE - GPIOX interrupt type - 0x6d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_SET - GPIO interrupt type set - 0x6d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_CLEAR - GPIO interrupt type clear - 0x6d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOX_TOGGLE - GPIO interrupt type toggle - 0x6dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_VALUE - GPIOY interrupt type - 0x6e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_SET - GPIO interrupt type set - 0x6e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_CLEAR - GPIO interrupt type clear - 0x6e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOY_TOGGLE - GPIO interrupt type toggle - 0x6ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_VALUE - GPIOZ interrupt type - 0x6f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_SET - GPIO interrupt type set - 0x6f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_CLEAR - GPIO interrupt type clear - 0x6f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TP_GPIOZ_TOGGLE - GPIO interrupt type toggle - 0x6fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - AS_GPIOA_VALUE - GPIO interrupt asynchronous value - 0x700 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOA_SET - GPIO interrupt asynchronous set - 0x704 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOA_CLEAR - GPIO interrupt asynchronous clear - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOA_TOGGLE - GPIO interrupt asynchronous toggle - 0x70c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_VALUE - GPIOB interrupt asynchronous - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_SET - GPIO interrupt asynchronous set - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_CLEAR - GPIO interrupt asynchronous clear - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOB_TOGGLE - GPIO interrupt asynchronous toggle - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_VALUE - GPIOC interrupt asynchronous - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_SET - GPIO interrupt asynchronous set - 0x724 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_CLEAR - GPIO interrupt asynchronous clear - 0x728 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOC_TOGGLE - GPIO interrupt asynchronous toggle - 0x72c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOD_VALUE - GPIOD interrupt asynchronous - 0x730 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOD_SET - GPIO interrupt asynchronous set - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOD_CLEAR - GPIO interrupt asynchronous clear - 0x738 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOD_TOGGLE - GPIO interrupt asynchronous toggle - 0x73c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOE_VALUE - GPIOE interrupt asynchronous - 0x740 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOE_SET - GPIO interrupt asynchronous set - 0x744 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOE_CLEAR - GPIO interrupt asynchronous clear - 0x748 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOE_TOGGLE - GPIO interrupt asynchronous toggle - 0x74c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOF_VALUE - GPIOF interrupt asynchronous - 0x750 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOF_SET - GPIO interrupt asynchronous set - 0x754 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOF_CLEAR - GPIO interrupt asynchronous clear - 0x758 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOF_TOGGLE - GPIO interrupt asynchronous toggle - 0x75c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_VALUE - GPIOX interrupt asynchronous - 0x7d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_SET - GPIO interrupt asynchronous set - 0x7d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_CLEAR - GPIO interrupt asynchronous clear - 0x7d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOX_TOGGLE - GPIO interrupt asynchronous toggle - 0x7dc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_VALUE - GPIOY interrupt asynchronous - 0x7e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_SET - GPIO interrupt asynchronous set - 0x7e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_CLEAR - GPIO interrupt asynchronous clear - 0x7e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOY_TOGGLE - GPIO interrupt asynchronous toggle - 0x7ec - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_VALUE - GPIOZ interrupt asynchronous - 0x7f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_SET - GPIO interrupt asynchronous set - 0x7f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_CLEAR - GPIO interrupt asynchronous clear - 0x7f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - AS_GPIOZ_TOGGLE - GPIO interrupt asynchronous toggle - 0x7fc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf0000000 - - - GPIO1 - GPIO1 - GPIO - 0xf0004000 - - - PGPIO - PGPIO - GPIO - 0xf40dc000 - - - BGPIO - BGPIO - GPIO - 0xf5014000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - FEATURE - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - PRIORITY_PRIORITY1 - Source priority - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY2 - Source priority - 0x8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY3 - Source priority - 0xc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY4 - Source priority - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY5 - Source priority - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY6 - Source priority - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY7 - Source priority - 0x1c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY8 - Source priority - 0x20 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY9 - Source priority - 0x24 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY10 - Source priority - 0x28 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY11 - Source priority - 0x2c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY12 - Source priority - 0x30 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY13 - Source priority - 0x34 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY14 - Source priority - 0x38 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY15 - Source priority - 0x3c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY16 - Source priority - 0x40 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY17 - Source priority - 0x44 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY18 - Source priority - 0x48 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY19 - Source priority - 0x4c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY20 - Source priority - 0x50 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY21 - Source priority - 0x54 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY22 - Source priority - 0x58 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY23 - Source priority - 0x5c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY24 - Source priority - 0x60 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY25 - Source priority - 0x64 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY26 - Source priority - 0x68 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY27 - Source priority - 0x6c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY28 - Source priority - 0x70 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY29 - Source priority - 0x74 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY30 - Source priority - 0x78 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY31 - Source priority - 0x7c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY32 - Source priority - 0x80 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY33 - Source priority - 0x84 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY34 - Source priority - 0x88 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY35 - Source priority - 0x8c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY36 - Source priority - 0x90 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY37 - Source priority - 0x94 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY38 - Source priority - 0x98 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY39 - Source priority - 0x9c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY40 - Source priority - 0xa0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY41 - Source priority - 0xa4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY42 - Source priority - 0xa8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY43 - Source priority - 0xac - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY44 - Source priority - 0xb0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY45 - Source priority - 0xb4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY46 - Source priority - 0xb8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY47 - Source priority - 0xbc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY48 - Source priority - 0xc0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY49 - Source priority - 0xc4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY50 - Source priority - 0xc8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY51 - Source priority - 0xcc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY52 - Source priority - 0xd0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY53 - Source priority - 0xd4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY54 - Source priority - 0xd8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY55 - Source priority - 0xdc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY56 - Source priority - 0xe0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY57 - Source priority - 0xe4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY58 - Source priority - 0xe8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY59 - Source priority - 0xec - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY60 - Source priority - 0xf0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY61 - Source priority - 0xf4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY62 - Source priority - 0xf8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY63 - Source priority - 0xfc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY64 - Source priority - 0x100 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY65 - Source priority - 0x104 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY66 - Source priority - 0x108 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY67 - Source priority - 0x10c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY68 - Source priority - 0x110 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY69 - Source priority - 0x114 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY70 - Source priority - 0x118 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY71 - Source priority - 0x11c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY72 - Source priority - 0x120 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY73 - Source priority - 0x124 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY74 - Source priority - 0x128 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY75 - Source priority - 0x12c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY76 - Source priority - 0x130 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY77 - Source priority - 0x134 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY78 - Source priority - 0x138 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY79 - Source priority - 0x13c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY80 - Source priority - 0x140 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY81 - Source priority - 0x144 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY82 - Source priority - 0x148 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY83 - Source priority - 0x14c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY84 - Source priority - 0x150 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY85 - Source priority - 0x154 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY86 - Source priority - 0x158 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY87 - Source priority - 0x15c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY88 - Source priority - 0x160 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY89 - Source priority - 0x164 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY90 - Source priority - 0x168 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY91 - Source priority - 0x16c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY92 - Source priority - 0x170 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY93 - Source priority - 0x174 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY94 - Source priority - 0x178 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY95 - Source priority - 0x17c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY96 - Source priority - 0x180 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY97 - Source priority - 0x184 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY98 - Source priority - 0x188 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY99 - Source priority - 0x18c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY100 - Source priority - 0x190 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY101 - Source priority - 0x194 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY102 - Source priority - 0x198 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY103 - Source priority - 0x19c - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY104 - Source priority - 0x1a0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY105 - Source priority - 0x1a4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY106 - Source priority - 0x1a8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY107 - Source priority - 0x1ac - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY108 - Source priority - 0x1b0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY109 - Source priority - 0x1b4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY110 - Source priority - 0x1b8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY111 - Source priority - 0x1bc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY112 - Source priority - 0x1c0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY113 - Source priority - 0x1c4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY114 - Source priority - 0x1c8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY115 - Source priority - 0x1cc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY116 - Source priority - 0x1d0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY117 - Source priority - 0x1d4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY118 - Source priority - 0x1d8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY119 - Source priority - 0x1dc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY120 - Source priority - 0x1e0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY121 - Source priority - 0x1e4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY122 - Source priority - 0x1e8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY123 - Source priority - 0x1ec - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY124 - Source priority - 0x1f0 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY125 - Source priority - 0x1f4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY126 - Source priority - 0x1f8 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PRIORITY_PRIORITY127 - Source priority - 0x1fc - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - PENDING_PENDING0 - Pending status - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - PENDING_PENDING1 - Pending status - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - PENDING_PENDING2 - Pending status - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - PENDING_PENDING3 - Pending status - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TRIGGER_TRIGGER0 - Trigger type - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - TRIGGER_TRIGGER1 - Trigger type - 0x1084 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - TRIGGER_TRIGGER2 - Trigger type - 0x1088 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - TRIGGER_TRIGGER3 - Trigger type - 0x108c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - TARGETINT_TARGET0_INTEN0 - machine interrupt enable - 0x2000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET0_INTEN1 - machine interrupt enable - 0x2004 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET0_INTEN2 - machine interrupt enable - 0x2008 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET0_INTEN3 - machine interrupt enable - 0x200c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN0 - supervisor interrupt enable - 0x2080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN1 - supervisor interrupt enable - 0x2084 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN2 - supervisor interrupt enable - 0x2088 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETINT_TARGET1_INTEN_INTEN3 - supervisor interrupt enable - 0x208c - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET0_THRESHOLD - Target0 priority threshold - 0x200000 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET0_CLAIM - Target claim and complete - 0x200004 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - TARGETCONFIG_TARGET0_PPS - Preempted priority stack - 0x200400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET1_THRESHOLD - Target1 priority threshold - 0x201000 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - TARGETCONFIG_TARGET1_CLAIM - Target claim and complete - 0x201004 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - TARGETCONFIG_TARGET1_PPS - Preempted priority stack - 0x201400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLIC_SW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPIOM - GPIOM - GPIOM - 0xf0008000 - - 0x0 - 0x800 - registers - - - - ASSIGN_GPIOA_PIN_PIN00 - GPIO mananger - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN01 - GPIO mananger - 0x4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN02 - GPIO mananger - 0x8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN03 - GPIO mananger - 0xc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN04 - GPIO mananger - 0x10 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN05 - GPIO mananger - 0x14 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN06 - GPIO mananger - 0x18 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN07 - GPIO mananger - 0x1c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN08 - GPIO mananger - 0x20 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN09 - GPIO mananger - 0x24 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN10 - GPIO mananger - 0x28 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN11 - GPIO mananger - 0x2c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN12 - GPIO mananger - 0x30 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN13 - GPIO mananger - 0x34 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN14 - GPIO mananger - 0x38 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN15 - GPIO mananger - 0x3c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN16 - GPIO mananger - 0x40 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN17 - GPIO mananger - 0x44 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN18 - GPIO mananger - 0x48 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN19 - GPIO mananger - 0x4c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN20 - GPIO mananger - 0x50 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN21 - GPIO mananger - 0x54 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN22 - GPIO mananger - 0x58 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN23 - GPIO mananger - 0x5c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN24 - GPIO mananger - 0x60 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN25 - GPIO mananger - 0x64 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN26 - GPIO mananger - 0x68 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN27 - GPIO mananger - 0x6c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN28 - GPIO mananger - 0x70 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN29 - GPIO mananger - 0x74 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN30 - GPIO mananger - 0x78 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOA_PIN_PIN31 - GPIO mananger - 0x7c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN00 - GPIO mananger - 0x80 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN01 - GPIO mananger - 0x84 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN02 - GPIO mananger - 0x88 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN03 - GPIO mananger - 0x8c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN04 - GPIO mananger - 0x90 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN05 - GPIO mananger - 0x94 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN06 - GPIO mananger - 0x98 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN07 - GPIO mananger - 0x9c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN08 - GPIO mananger - 0xa0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN09 - GPIO mananger - 0xa4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN10 - GPIO mananger - 0xa8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN11 - GPIO mananger - 0xac - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN12 - GPIO mananger - 0xb0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN13 - GPIO mananger - 0xb4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN14 - GPIO mananger - 0xb8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN15 - GPIO mananger - 0xbc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN16 - GPIO mananger - 0xc0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN17 - GPIO mananger - 0xc4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN18 - GPIO mananger - 0xc8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN19 - GPIO mananger - 0xcc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN20 - GPIO mananger - 0xd0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN21 - GPIO mananger - 0xd4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN22 - GPIO mananger - 0xd8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN23 - GPIO mananger - 0xdc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN24 - GPIO mananger - 0xe0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN25 - GPIO mananger - 0xe4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN26 - GPIO mananger - 0xe8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN27 - GPIO mananger - 0xec - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN28 - GPIO mananger - 0xf0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN29 - GPIO mananger - 0xf4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN30 - GPIO mananger - 0xf8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOB_PIN_PIN31 - GPIO mananger - 0xfc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN00 - GPIO mananger - 0x100 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN01 - GPIO mananger - 0x104 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN02 - GPIO mananger - 0x108 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN03 - GPIO mananger - 0x10c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN04 - GPIO mananger - 0x110 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN05 - GPIO mananger - 0x114 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN06 - GPIO mananger - 0x118 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN07 - GPIO mananger - 0x11c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN08 - GPIO mananger - 0x120 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN09 - GPIO mananger - 0x124 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN10 - GPIO mananger - 0x128 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN11 - GPIO mananger - 0x12c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN12 - GPIO mananger - 0x130 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN13 - GPIO mananger - 0x134 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN14 - GPIO mananger - 0x138 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN15 - GPIO mananger - 0x13c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN16 - GPIO mananger - 0x140 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN17 - GPIO mananger - 0x144 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN18 - GPIO mananger - 0x148 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN19 - GPIO mananger - 0x14c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN20 - GPIO mananger - 0x150 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN21 - GPIO mananger - 0x154 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN22 - GPIO mananger - 0x158 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN23 - GPIO mananger - 0x15c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN24 - GPIO mananger - 0x160 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN25 - GPIO mananger - 0x164 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN26 - GPIO mananger - 0x168 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN27 - GPIO mananger - 0x16c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN28 - GPIO mananger - 0x170 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN29 - GPIO mananger - 0x174 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN30 - GPIO mananger - 0x178 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN31 - GPIO mananger - 0x17c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN00 - GPIO mananger - 0x180 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN01 - GPIO mananger - 0x184 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN02 - GPIO mananger - 0x188 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN03 - GPIO mananger - 0x18c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN04 - GPIO mananger - 0x190 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN05 - GPIO mananger - 0x194 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN06 - GPIO mananger - 0x198 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN07 - GPIO mananger - 0x19c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN08 - GPIO mananger - 0x1a0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN09 - GPIO mananger - 0x1a4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN10 - GPIO mananger - 0x1a8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN11 - GPIO mananger - 0x1ac - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN12 - GPIO mananger - 0x1b0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN13 - GPIO mananger - 0x1b4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN14 - GPIO mananger - 0x1b8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN15 - GPIO mananger - 0x1bc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN16 - GPIO mananger - 0x1c0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN17 - GPIO mananger - 0x1c4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN18 - GPIO mananger - 0x1c8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN19 - GPIO mananger - 0x1cc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN20 - GPIO mananger - 0x1d0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN21 - GPIO mananger - 0x1d4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN22 - GPIO mananger - 0x1d8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN23 - GPIO mananger - 0x1dc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN24 - GPIO mananger - 0x1e0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN25 - GPIO mananger - 0x1e4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN26 - GPIO mananger - 0x1e8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN27 - GPIO mananger - 0x1ec - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN28 - GPIO mananger - 0x1f0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN29 - GPIO mananger - 0x1f4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN30 - GPIO mananger - 0x1f8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN31 - GPIO mananger - 0x1fc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN00 - GPIO mananger - 0x200 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN01 - GPIO mananger - 0x204 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN02 - GPIO mananger - 0x208 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN03 - GPIO mananger - 0x20c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN04 - GPIO mananger - 0x210 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN05 - GPIO mananger - 0x214 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN06 - GPIO mananger - 0x218 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN07 - GPIO mananger - 0x21c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN08 - GPIO mananger - 0x220 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN09 - GPIO mananger - 0x224 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN10 - GPIO mananger - 0x228 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN11 - GPIO mananger - 0x22c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN12 - GPIO mananger - 0x230 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN13 - GPIO mananger - 0x234 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN14 - GPIO mananger - 0x238 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN15 - GPIO mananger - 0x23c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN16 - GPIO mananger - 0x240 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN17 - GPIO mananger - 0x244 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN18 - GPIO mananger - 0x248 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN19 - GPIO mananger - 0x24c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN20 - GPIO mananger - 0x250 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN21 - GPIO mananger - 0x254 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN22 - GPIO mananger - 0x258 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN23 - GPIO mananger - 0x25c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN24 - GPIO mananger - 0x260 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN25 - GPIO mananger - 0x264 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN26 - GPIO mananger - 0x268 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN27 - GPIO mananger - 0x26c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN28 - GPIO mananger - 0x270 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN29 - GPIO mananger - 0x274 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN30 - GPIO mananger - 0x278 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOE_PIN_PIN31 - GPIO mananger - 0x27c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN00 - GPIO mananger - 0x280 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN01 - GPIO mananger - 0x284 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN02 - GPIO mananger - 0x288 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN03 - GPIO mananger - 0x28c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN04 - GPIO mananger - 0x290 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN05 - GPIO mananger - 0x294 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN06 - GPIO mananger - 0x298 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN07 - GPIO mananger - 0x29c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN08 - GPIO mananger - 0x2a0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN09 - GPIO mananger - 0x2a4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN10 - GPIO mananger - 0x2a8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN11 - GPIO mananger - 0x2ac - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN12 - GPIO mananger - 0x2b0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN13 - GPIO mananger - 0x2b4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN14 - GPIO mananger - 0x2b8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN15 - GPIO mananger - 0x2bc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN16 - GPIO mananger - 0x2c0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN17 - GPIO mananger - 0x2c4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN18 - GPIO mananger - 0x2c8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN19 - GPIO mananger - 0x2cc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN20 - GPIO mananger - 0x2d0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN21 - GPIO mananger - 0x2d4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN22 - GPIO mananger - 0x2d8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN23 - GPIO mananger - 0x2dc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN24 - GPIO mananger - 0x2e0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN25 - GPIO mananger - 0x2e4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN26 - GPIO mananger - 0x2e8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN27 - GPIO mananger - 0x2ec - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN28 - GPIO mananger - 0x2f0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN29 - GPIO mananger - 0x2f4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN30 - GPIO mananger - 0x2f8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOF_PIN_PIN31 - GPIO mananger - 0x2fc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN00 - GPIO mananger - 0x680 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN01 - GPIO mananger - 0x684 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN02 - GPIO mananger - 0x688 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN03 - GPIO mananger - 0x68c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN04 - GPIO mananger - 0x690 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN05 - GPIO mananger - 0x694 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN06 - GPIO mananger - 0x698 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN07 - GPIO mananger - 0x69c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN08 - GPIO mananger - 0x6a0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN09 - GPIO mananger - 0x6a4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN10 - GPIO mananger - 0x6a8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN11 - GPIO mananger - 0x6ac - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN12 - GPIO mananger - 0x6b0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN13 - GPIO mananger - 0x6b4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN14 - GPIO mananger - 0x6b8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN15 - GPIO mananger - 0x6bc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN16 - GPIO mananger - 0x6c0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN17 - GPIO mananger - 0x6c4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN18 - GPIO mananger - 0x6c8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN19 - GPIO mananger - 0x6cc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN20 - GPIO mananger - 0x6d0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN21 - GPIO mananger - 0x6d4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN22 - GPIO mananger - 0x6d8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN23 - GPIO mananger - 0x6dc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN24 - GPIO mananger - 0x6e0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN25 - GPIO mananger - 0x6e4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN26 - GPIO mananger - 0x6e8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN27 - GPIO mananger - 0x6ec - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN28 - GPIO mananger - 0x6f0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN29 - GPIO mananger - 0x6f4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN30 - GPIO mananger - 0x6f8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOX_PIN_PIN31 - GPIO mananger - 0x6fc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN00 - GPIO mananger - 0x700 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN01 - GPIO mananger - 0x704 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN02 - GPIO mananger - 0x708 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN03 - GPIO mananger - 0x70c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN04 - GPIO mananger - 0x710 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN05 - GPIO mananger - 0x714 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN06 - GPIO mananger - 0x718 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN07 - GPIO mananger - 0x71c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN08 - GPIO mananger - 0x720 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN09 - GPIO mananger - 0x724 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN10 - GPIO mananger - 0x728 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN11 - GPIO mananger - 0x72c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN12 - GPIO mananger - 0x730 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN13 - GPIO mananger - 0x734 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN14 - GPIO mananger - 0x738 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN15 - GPIO mananger - 0x73c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN16 - GPIO mananger - 0x740 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN17 - GPIO mananger - 0x744 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN18 - GPIO mananger - 0x748 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN19 - GPIO mananger - 0x74c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN20 - GPIO mananger - 0x750 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN21 - GPIO mananger - 0x754 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN22 - GPIO mananger - 0x758 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN23 - GPIO mananger - 0x75c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN24 - GPIO mananger - 0x760 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN25 - GPIO mananger - 0x764 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN26 - GPIO mananger - 0x768 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN27 - GPIO mananger - 0x76c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN28 - GPIO mananger - 0x770 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN29 - GPIO mananger - 0x774 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN30 - GPIO mananger - 0x778 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOY_PIN_PIN31 - GPIO mananger - 0x77c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN00 - GPIO mananger - 0x780 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN01 - GPIO mananger - 0x784 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN02 - GPIO mananger - 0x788 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN03 - GPIO mananger - 0x78c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN04 - GPIO mananger - 0x790 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN05 - GPIO mananger - 0x794 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN06 - GPIO mananger - 0x798 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN07 - GPIO mananger - 0x79c - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN08 - GPIO mananger - 0x7a0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN09 - GPIO mananger - 0x7a4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN10 - GPIO mananger - 0x7a8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN11 - GPIO mananger - 0x7ac - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN12 - GPIO mananger - 0x7b0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN13 - GPIO mananger - 0x7b4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN14 - GPIO mananger - 0x7b8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN15 - GPIO mananger - 0x7bc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN16 - GPIO mananger - 0x7c0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN17 - GPIO mananger - 0x7c4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN18 - GPIO mananger - 0x7c8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN19 - GPIO mananger - 0x7cc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN20 - GPIO mananger - 0x7d0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN21 - GPIO mananger - 0x7d4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN22 - GPIO mananger - 0x7d8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN23 - GPIO mananger - 0x7dc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN24 - GPIO mananger - 0x7e0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN25 - GPIO mananger - 0x7e4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN26 - GPIO mananger - 0x7e8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN27 - GPIO mananger - 0x7ec - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN28 - GPIO mananger - 0x7f0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN29 - GPIO mananger - 0x7f4 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN30 - GPIO mananger - 0x7f8 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN31 - GPIO mananger - 0x7fc - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - - - ADC0 - ADC0 - ADC12 - 0xf0010000 - - 0x0 - 0x1214 - registers - - - - CONFIG_TRG0A - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG0B - No description avaiable - 0x4 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG0C - No description avaiable - 0x8 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1A - No description avaiable - 0xc - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1B - No description avaiable - 0x10 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1C - No description avaiable - 0x14 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2A - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2B - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2C - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3A - No description avaiable - 0x24 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3B - No description avaiable - 0x28 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3C - No description avaiable - 0x2c - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - TRG_DMA_ADDR - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - BUS_RESULT_CHN0 - No description avaiable - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN1 - No description avaiable - 0x404 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN2 - No description avaiable - 0x408 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN3 - No description avaiable - 0x40c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN4 - No description avaiable - 0x410 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN5 - No description avaiable - 0x414 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN6 - No description avaiable - 0x418 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN7 - No description avaiable - 0x41c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN8 - No description avaiable - 0x420 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN9 - No description avaiable - 0x424 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN10 - No description avaiable - 0x428 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN11 - No description avaiable - 0x42c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN12 - No description avaiable - 0x430 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN13 - No description avaiable - 0x434 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN14 - No description avaiable - 0x438 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN15 - No description avaiable - 0x43c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN16 - No description avaiable - 0x440 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN17 - No description avaiable - 0x444 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN18 - No description avaiable - 0x448 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUF_CFG0 - No description avaiable - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - SEQ_CFG0 - No description avaiable - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - SEQ_DMA_ADDR - No description avaiable - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - SEQ_WR_ADDR - No description avaiable - 0x808 - 32 - 0x00000000 - 0x00000FFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 12 - read-only - - - - - SEQ_DMA_CFG - No description avaiable - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - SEQ_QUE_CFG0 - No description avaiable - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG1 - No description avaiable - 0x814 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG2 - No description avaiable - 0x818 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG3 - No description avaiable - 0x81c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG4 - No description avaiable - 0x820 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG5 - No description avaiable - 0x824 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG6 - No description avaiable - 0x828 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG7 - No description avaiable - 0x82c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG8 - No description avaiable - 0x830 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG9 - No description avaiable - 0x834 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG10 - No description avaiable - 0x838 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG11 - No description avaiable - 0x83c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG12 - No description avaiable - 0x840 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG13 - No description avaiable - 0x844 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG14 - No description avaiable - 0x848 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG15 - No description avaiable - 0x84c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - PRD_CFG_CHN0_PRD_CFG - No description avaiable - 0xc00 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN0_PRD_THSHD_CFG - No description avaiable - 0xc04 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN0_PRD_RESULT - No description avaiable - 0xc08 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN1_PRD_CFG - No description avaiable - 0xc10 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN1_PRD_THSHD_CFG - No description avaiable - 0xc14 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN1_PRD_RESULT - No description avaiable - 0xc18 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN2_PRD_CFG - No description avaiable - 0xc20 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN2_PRD_THSHD_CFG - No description avaiable - 0xc24 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN2_PRD_RESULT - No description avaiable - 0xc28 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN3_PRD_CFG - No description avaiable - 0xc30 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN3_PRD_THSHD_CFG - No description avaiable - 0xc34 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN3_PRD_RESULT - No description avaiable - 0xc38 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN4_PRD_CFG - No description avaiable - 0xc40 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN4_PRD_THSHD_CFG - No description avaiable - 0xc44 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN4_PRD_RESULT - No description avaiable - 0xc48 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN5_PRD_CFG - No description avaiable - 0xc50 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN5_PRD_THSHD_CFG - No description avaiable - 0xc54 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN5_PRD_RESULT - No description avaiable - 0xc58 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN6_PRD_CFG - No description avaiable - 0xc60 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN6_PRD_THSHD_CFG - No description avaiable - 0xc64 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN6_PRD_RESULT - No description avaiable - 0xc68 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN7_PRD_CFG - No description avaiable - 0xc70 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN7_PRD_THSHD_CFG - No description avaiable - 0xc74 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN7_PRD_RESULT - No description avaiable - 0xc78 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN8_PRD_CFG - No description avaiable - 0xc80 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN8_PRD_THSHD_CFG - No description avaiable - 0xc84 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN8_PRD_RESULT - No description avaiable - 0xc88 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN9_PRD_CFG - No description avaiable - 0xc90 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN9_PRD_THSHD_CFG - No description avaiable - 0xc94 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN9_PRD_RESULT - No description avaiable - 0xc98 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN10_PRD_CFG - No description avaiable - 0xca0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN10_PRD_THSHD_CFG - No description avaiable - 0xca4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN10_PRD_RESULT - No description avaiable - 0xca8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN11_PRD_CFG - No description avaiable - 0xcb0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN11_PRD_THSHD_CFG - No description avaiable - 0xcb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN11_PRD_RESULT - No description avaiable - 0xcb8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN12_PRD_CFG - No description avaiable - 0xcc0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN12_PRD_THSHD_CFG - No description avaiable - 0xcc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN12_PRD_RESULT - No description avaiable - 0xcc8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN13_PRD_CFG - No description avaiable - 0xcd0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN13_PRD_THSHD_CFG - No description avaiable - 0xcd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN13_PRD_RESULT - No description avaiable - 0xcd8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN14_PRD_CFG - No description avaiable - 0xce0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN14_PRD_THSHD_CFG - No description avaiable - 0xce4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN14_PRD_RESULT - No description avaiable - 0xce8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN15_PRD_CFG - No description avaiable - 0xcf0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN15_PRD_THSHD_CFG - No description avaiable - 0xcf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN15_PRD_RESULT - No description avaiable - 0xcf8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN16_PRD_CFG - No description avaiable - 0xd00 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN16_PRD_THSHD_CFG - No description avaiable - 0xd04 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN16_PRD_RESULT - No description avaiable - 0xd08 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN17_PRD_CFG - No description avaiable - 0xd10 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN17_PRD_THSHD_CFG - No description avaiable - 0xd14 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN17_PRD_RESULT - No description avaiable - 0xd18 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN18_PRD_CFG - No description avaiable - 0xd20 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN18_PRD_THSHD_CFG - No description avaiable - 0xd24 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN18_PRD_RESULT - No description avaiable - 0xd28 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - SAMPLE_CFG_CHN0 - No description avaiable - 0x1000 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN1 - No description avaiable - 0x1004 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN2 - No description avaiable - 0x1008 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN3 - No description avaiable - 0x100c - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN4 - No description avaiable - 0x1010 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN5 - No description avaiable - 0x1014 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN6 - No description avaiable - 0x1018 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN7 - No description avaiable - 0x101c - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN8 - No description avaiable - 0x1020 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN9 - No description avaiable - 0x1024 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN10 - No description avaiable - 0x1028 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN11 - No description avaiable - 0x102c - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN12 - No description avaiable - 0x1030 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN13 - No description avaiable - 0x1034 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN14 - No description avaiable - 0x1038 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN15 - No description avaiable - 0x103c - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN16 - No description avaiable - 0x1040 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN17 - No description avaiable - 0x1044 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN18 - No description avaiable - 0x1048 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - CONV_CFG1 - No description avaiable - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); -set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC convertion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. -set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - ADC_CFG0 - No description avaiable - 0x1108 - 32 - 0x00000000 - 0xA0000000 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - - - INT_STS - No description avaiable - 0x1110 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description avaiable - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description avaiable - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrup, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description avaiable - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - No description avaiable - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1 - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - INT_EN - No description avaiable - 0x1114 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description avaiable - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description avaiable - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrup, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description avaiable - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - ANA_CTRL0 - No description avaiable - 0x1200 - 32 - 0x00000000 - 0x7F7F487E - - - CAL_VAL_DIFF - calibration value for differential mode - 24 - 7 - read-write - - - CAL_VAL_SE - calibration value for single-end mode - 16 - 7 - read-write - - - REARM_EN - set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number - 14 - 1 - read-write - - - SELRANGE_LDO - Defines the range for the LDO reference (vdd_soc) -selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] -selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] - 11 - 1 - read-write - - - ENLDO - set to enable adc LDO, need at least 20us for LDO to be stable. - 6 - 1 - read-write - - - ENADC - set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. - 5 - 1 - read-write - - - RESETADC - set to 1 to reset adc analog; default high. - 4 - 1 - read-write - - - RESETCAL - set to 1 to reset calibration logic; default high. - 3 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - LOADCAL - Signal that loads the offset calibration word into the internal registers (Active H) - 1 - 1 - read-write - - - - - ANA_CTRL1 - No description avaiable - 0x1204 - 32 - 0x00000000 - 0x000000C0 - - - SELRES - 11-12bit -10-10bit -01-8bit -00-6bit - 6 - 2 - read-write - - - - - ANA_STATUS - No description avaiable - 0x1210 - 32 - 0x00000000 - 0x000000FF - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - CAL_OUT - No description avaiable - 0 - 7 - read-write - - - - - - - ADC1 - ADC1 - ADC12 - 0xf0014000 - - - ADC2 - ADC2 - ADC12 - 0xf0018000 - - - ADC3 - ADC3 - ADC16 - 0xf001c000 - - 0x0 - 0x1464 - registers - - - - CONFIG_TRG0A - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG0B - No description avaiable - 0x4 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG0C - No description avaiable - 0x8 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1A - No description avaiable - 0xc - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1B - No description avaiable - 0x10 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG1C - No description avaiable - 0x14 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2A - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2B - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2C - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3A - No description avaiable - 0x24 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3B - No description avaiable - 0x28 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG3C - No description avaiable - 0x2c - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - TRG_DMA_ADDR - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - BUS_RESULT_CHN0 - No description avaiable - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN1 - No description avaiable - 0x404 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN2 - No description avaiable - 0x408 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN3 - No description avaiable - 0x40c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN4 - No description avaiable - 0x410 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN5 - No description avaiable - 0x414 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN6 - No description avaiable - 0x418 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN7 - No description avaiable - 0x41c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUF_CFG0 - No description avaiable - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - SEQ_CFG0 - No description avaiable - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - SEQ_DMA_ADDR - No description avaiable - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - SEQ_WR_ADDR - No description avaiable - 0x808 - 32 - 0x00000000 - 0x00000FFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 12 - read-only - - - - - SEQ_DMA_CFG - No description avaiable - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - SEQ_QUE_CFG0 - No description avaiable - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG1 - No description avaiable - 0x814 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG2 - No description avaiable - 0x818 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG3 - No description avaiable - 0x81c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG4 - No description avaiable - 0x820 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG5 - No description avaiable - 0x824 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG6 - No description avaiable - 0x828 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG7 - No description avaiable - 0x82c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG8 - No description avaiable - 0x830 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG9 - No description avaiable - 0x834 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG10 - No description avaiable - 0x838 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG11 - No description avaiable - 0x83c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG12 - No description avaiable - 0x840 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG13 - No description avaiable - 0x844 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG14 - No description avaiable - 0x848 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - SEQ_QUE_CFG15 - No description avaiable - 0x84c - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - PRD_CFG_CHN0_PRD_CFG - No description avaiable - 0xc00 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN0_PRD_THSHD_CFG - No description avaiable - 0xc04 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN0_PRD_RESULT - No description avaiable - 0xc08 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN1_PRD_CFG - No description avaiable - 0xc10 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN1_PRD_THSHD_CFG - No description avaiable - 0xc14 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN1_PRD_RESULT - No description avaiable - 0xc18 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN2_PRD_CFG - No description avaiable - 0xc20 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN2_PRD_THSHD_CFG - No description avaiable - 0xc24 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN2_PRD_RESULT - No description avaiable - 0xc28 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN3_PRD_CFG - No description avaiable - 0xc30 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN3_PRD_THSHD_CFG - No description avaiable - 0xc34 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN3_PRD_RESULT - No description avaiable - 0xc38 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN4_PRD_CFG - No description avaiable - 0xc40 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN4_PRD_THSHD_CFG - No description avaiable - 0xc44 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN4_PRD_RESULT - No description avaiable - 0xc48 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN5_PRD_CFG - No description avaiable - 0xc50 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN5_PRD_THSHD_CFG - No description avaiable - 0xc54 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN5_PRD_RESULT - No description avaiable - 0xc58 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN6_PRD_CFG - No description avaiable - 0xc60 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN6_PRD_THSHD_CFG - No description avaiable - 0xc64 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN6_PRD_RESULT - No description avaiable - 0xc68 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - PRD_CFG_CHN7_PRD_CFG - No description avaiable - 0xc70 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - PRD_CFG_CHN7_PRD_THSHD_CFG - No description avaiable - 0xc74 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - PRD_CFG_CHN7_PRD_RESULT - No description avaiable - 0xc78 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - SAMPLE_CFG_CHN0 - No description avaiable - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN1 - No description avaiable - 0x1004 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN2 - No description avaiable - 0x1008 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN3 - No description avaiable - 0x100c - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN4 - No description avaiable - 0x1010 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN5 - No description avaiable - 0x1014 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN6 - No description avaiable - 0x1018 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - SAMPLE_CFG_CHN7 - No description avaiable - 0x101c - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - CONV_CFG1 - No description avaiable - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); -user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. -set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. - 0 - 4 - read-write - - - - - ADC_CFG0 - No description avaiable - 0x1108 - 32 - 0x00000000 - 0xAFFFF001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - CONVERT_DURATION - for trigger queue, from trg_sample_req to trg_convert_req - 12 - 16 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - INT_STS - No description avaiable - 0x1110 - 32 - 0x00000000 - 0xFFE03FFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description avaiable - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description avaiable - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrup, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description avaiable - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 14 - read-write - - - - - INT_EN - No description avaiable - 0x1114 - 32 - 0x00000000 - 0xFFE03FFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description avaiable - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description avaiable - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrup, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description avaiable - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 14 - read-write - - - - - ANA_CTRL0 - No description avaiable - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ANA_STATUS - No description avaiable - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - ADC16_PARAMS_ADC16_PARA00 - No description avaiable - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA01 - No description avaiable - 0x1402 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA02 - No description avaiable - 0x1404 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA03 - No description avaiable - 0x1406 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA04 - No description avaiable - 0x1408 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA05 - No description avaiable - 0x140a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA06 - No description avaiable - 0x140c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA07 - No description avaiable - 0x140e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA08 - No description avaiable - 0x1410 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA09 - No description avaiable - 0x1412 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA10 - No description avaiable - 0x1414 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA11 - No description avaiable - 0x1416 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA12 - No description avaiable - 0x1418 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA13 - No description avaiable - 0x141a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA14 - No description avaiable - 0x141c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA15 - No description avaiable - 0x141e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA16 - No description avaiable - 0x1420 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA17 - No description avaiable - 0x1422 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA18 - No description avaiable - 0x1424 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA19 - No description avaiable - 0x1426 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA20 - No description avaiable - 0x1428 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA21 - No description avaiable - 0x142a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA22 - No description avaiable - 0x142c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA23 - No description avaiable - 0x142e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA24 - No description avaiable - 0x1430 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA25 - No description avaiable - 0x1432 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA26 - No description avaiable - 0x1434 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA27 - No description avaiable - 0x1436 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA28 - No description avaiable - 0x1438 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA29 - No description avaiable - 0x143a - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA30 - No description avaiable - 0x143c - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA31 - No description avaiable - 0x143e - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA32 - No description avaiable - 0x1440 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_PARAMS_ADC16_PARA33 - No description avaiable - 0x1442 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description avaiable - 0 - 16 - read-write - - - - - ADC16_CONFIG0 - No description avaiable - 0x1444 - 32 - 0x00000000 - 0x03F07FFF - - - TEMPSNS_EN - set to enable temp senser - 25 - 1 - read-write - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - convertion parameter - 0 - 14 - read-write - - - - - ADC16_CONFIG1 - No description avaiable - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number). - 8 - 5 - read-write - - - - - - - ACMP - ACMP - ACMP - 0xf0020000 - - 0x0 - 0x80 - registers - - - - CHANNEL_CHN0_CFG - Configure Register - 0x0 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN0_DACCFG - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN0_SR - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN0_IRQEN - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN0_DMAEN - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN1_CFG - Configure Register - 0x20 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN1_DACCFG - DAC configure register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN1_SR - Status register - 0x30 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN1_IRQEN - Interrupt request enable register - 0x34 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN1_DMAEN - DMA request enable register - 0x38 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN2_CFG - Configure Register - 0x40 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN2_DACCFG - DAC configure register - 0x44 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN2_SR - Status register - 0x50 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN2_IRQEN - Interrupt request enable register - 0x54 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN2_DMAEN - DMA request enable register - 0x58 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN3_CFG - Configure Register - 0x60 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - CHANNEL_CHN3_DACCFG - DAC configure register - 0x64 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value - 0 - 8 - read-write - - - - - CHANNEL_CHN3_SR - Status register - 0x70 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - CHANNEL_CHN3_IRQEN - Interrupt request enable register - 0x74 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - CHANNEL_CHN3_DMAEN - DMA request enable register - 0x78 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - SPI0 - SPI0 - SPI - 0xf0030000 - - 0x10 - 0x70 - registers - - - - TRANSFMT - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - RESERVED - No description avaiable - 18 - 14 - read-write - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - DIRECTIO - Direct IO Control Register - 0x14 - 32 - 0x00003100 - 0x013F3F3F - - - DIRECTIOEN - Enable Direct IO -0x0: Disable -0x1: Enable - 24 - 1 - read-write - - - HOLD_OE - Output enable for the SPI Flash hold signal - 21 - 1 - read-write - - - WP_OE - Output enable for the SPI Flash write protect signal - 20 - 1 - read-write - - - MISO_OE - Output enable fo the SPI MISO signal - 19 - 1 - read-write - - - MOSI_OE - Output enable for the SPI MOSI signal - 18 - 1 - read-write - - - SCLK_OE - Output enable for the SPI SCLK signal - 17 - 1 - read-write - - - CS_OE - Output enable for SPI CS (chip select) signal - 16 - 1 - read-write - - - HOLD_O - Output value for the SPI Flash hold signal - 13 - 1 - read-write - - - WP_O - Output value for the SPI Flash write protect signal - 12 - 1 - read-write - - - MISO_O - Output value for the SPI MISO signal - 11 - 1 - read-write - - - MOSI_O - Output value for the SPI MOSI signal - 10 - 1 - read-write - - - SCLK_O - Output value for the SPI SCLK signal - 9 - 1 - read-write - - - CS_O - Output value for the SPI CS (chip select) signal - 8 - 1 - read-write - - - HOLD_I - Status of the SPI Flash hold signal - 5 - 1 - read-only - - - WP_I - Status of the SPI Flash write protect signal - 4 - 1 - read-only - - - MISO_I - Status of the SPI MISO signal - 3 - 1 - read-only - - - MOSI_I - Status of the SPI MOSI signal - 2 - 1 - read-only - - - SCLK_I - Status of the SPI SCLK signal - 1 - 1 - read-only - - - CS_I - Status of the SPI CS (chip select) signal - 0 - 1 - read-only - - - - - TRANSCTRL - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - CMD - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - ADDR - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - DATA - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - CTRL - Control Register - 0x30 - 32 - 0x00000000 - 0x00FFFF1F - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - STATUS - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - INTREN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - INTRST - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - read-write - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - read-write - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - read-write - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - read-write - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - read-write - - - - - TIMING - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SLVST - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - read-write - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SLVDATACNT - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - CONFIG - Configuration Register - 0x7c - 32 - 0x00004311 - 0x00004BFF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - DIRECTIO - Support for Direct SPI IO - 11 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0034000 - - - SPI2 - SPI2 - SPI - 0xf0038000 - - - SPI3 - SPI3 - SPI - 0xf003c000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x10 - 0x2c - registers - - - - CFG - Configuration Register - 0x10 - 32 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 2 - 30 - read-write - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: The over-sample ratio is 32 -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - 0x24 - 32 - 0x00000000 - 0x0000000F - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - 0x28 - 32 - 0x00000001 - 0x000000CF - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - UART8 - UART8 - UART - 0xf0060000 - - - UART9 - UART9 - UART - 0xf0064000 - - - UART10 - UART10 - UART - 0xf0068000 - - - UART11 - UART11 - UART - 0xf006c000 - - - UART12 - UART12 - UART - 0xf0070000 - - - UART13 - UART13 - UART - 0xf0074000 - - - UART14 - UART14 - UART - 0xf0078000 - - - UART15 - UART15 - UART - 0xf007c000 - - - PUART - PUART - UART - 0xf40e4000 - - - CAN0 - CAN0 - CAN - 0xf0080000 - - 0x0 - 0xca - registers - - - - RBUF_BUF0 - receive buffer registers and reception time stamp - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF1 - receive buffer registers and reception time stamp - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF2 - receive buffer registers and reception time stamp - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF3 - receive buffer registers and reception time stamp - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF4 - receive buffer registers and reception time stamp - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF5 - receive buffer registers and reception time stamp - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF6 - receive buffer registers and reception time stamp - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF7 - receive buffer registers and reception time stamp - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF8 - receive buffer registers and reception time stamp - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF9 - receive buffer registers and reception time stamp - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF10 - receive buffer registers and reception time stamp - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF11 - receive buffer registers and reception time stamp - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF12 - receive buffer registers and reception time stamp - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF13 - receive buffer registers and reception time stamp - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF14 - receive buffer registers and reception time stamp - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF15 - receive buffer registers and reception time stamp - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF16 - receive buffer registers and reception time stamp - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF17 - receive buffer registers and reception time stamp - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF18 - receive buffer registers and reception time stamp - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - RBUF_BUF19 - receive buffer registers and reception time stamp - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - TBUF_BUF0 - transmit buffer register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF1 - transmit buffer register - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF2 - transmit buffer register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF3 - transmit buffer register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF4 - transmit buffer register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF5 - transmit buffer register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF6 - transmit buffer register - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF7 - transmit buffer register - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF8 - transmit buffer register - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF9 - transmit buffer register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF10 - transmit buffer register - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF11 - transmit buffer register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF12 - transmit buffer register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF13 - transmit buffer register - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF14 - transmit buffer register - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF15 - transmit buffer register - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF16 - transmit buffer register - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TBUF_BUF17 - transmit buffer register - 0x94 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - TTS_WRD0 - transmission time stamp, LSB 32bit - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - TTS_WRD1 - transmission time stamp, MSB 32bit - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - CMD_STA_CMD_CTRL - config, status, command and control bits - 0xa0 - 32 - 0x00900080 - 0xFBF3FFFF - - - SACK - Self-ACKnowledge -0 – no self-ACK -1 – self-ACK when LBME=1 - 31 - 1 - read-write - - - ROM - Receive buffer Overflow Mode -In case of a full RBUF when a new message is received, then ROM selects the following: -1 – The new message will not be stored. -0 – The oldest message will be overwritten. - 30 - 1 - read-write - - - ROV - Receive buffer OVerflow -1 – Overflow. At least one message is lost. -0 – No Overflow. -ROV is cleared by setting RREL=1. - 29 - 1 - read-only - - - RREL - Receive buffer RELease -The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL -core points to the next RB slot. RSTAT gets updated. -1 – Release: The host has read the RB. -0 – No release - 28 - 1 - read-write - - - RBALL - Receive Buffer stores ALL data frames -0 – normal operation -1 – RB stores correct data frames as well as data frames with error - 27 - 1 - read-write - - - RSTAT - Receive buffer STATus -00 - empty -01 - > empty and < almost full (AFWL) -10 -  almost full (programmable threshold by AFWL) but not full and no overflow -11 - full (stays set in case of overflow – for overflow signaling see ROV) - 24 - 2 - read-only - - - FD_ISO - CAN FD ISO mode -0 - Bosch CAN FD (non-ISO) mode -1 - ISO CAN FD mode (ISO 11898-1:2015) -ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. -Both modes are incompatible and must not be mixed in one CAN network. -This bit has no impact to CAN 2.0B. -This bit is only writeable if RESET=1. - 23 - 1 - read-write - - - TSNEXT - Transmit buffer Secondary NEXT -0 - no action -1 - STB slot filled, select next slot. -After all frame bytes are written to the TBUF registers, the host controller has to set -TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF -registers to the next slot. Once a slot is marked as filled a transmission can be started -using TSONE or TSALL. -It is possible to set TSNEXT and TSONE or TSALL together in one write access. -TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL -core immediately after it was set. -Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and -automatically cleared. It does not do any harm. -If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. -TSNEXT has no meaning in TTCAN mode and is fixed to 0. - 22 - 1 - read-write - - - TSMODE - Transmit buffer Secondary operation MODE -0 - FIFO mode -1 - priority decision mode -In FIFO mode frames are transmitted in the order in that they are written into the STB. -In priority decision mode the frame with the highest priority in the STB is automatically -transmitted first. The ID of a frame is used for the priority decision. A lower ID means a -higher priority of a frame. A frame in the PTB has always the highest priority regardless of -the ID. -TSMODE shall be switched only if the STB if empty - 21 - 1 - read-write - - - TTTBM - TTCAN Transmit Buffer Mode -If TTEN=0 then TTTBM is ignored, otherwise the following is valid: -0 - separate PTB and STB, behavior defined by TSMODE -1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR -For event-driven CAN communication (TTEN=0), the system provides PTB and STB and -the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. -For time-triggered CAN communication (TTEN=1) with full support of all features including -time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are -addressable using TTPTR and TBPTR. -For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode -and the behavior can be selected by TSMODE. -TTTBM shall be switched only if the TBUF is empty. - 20 - 1 - read-write - - - TSSTAT - Transmission Secondary STATus bits -If TTEN=0 or TTTBM=0: -00 – STB is empty -01 – STB is less than or equal to half full -10 – STB is more than half full -11 – STB is full -If the STB is disabled using STB_DISABLE, then TSSTAT=00. -If TTEN=1 and TTTBM=1: -00 – PTB and STB are empty -01 – PTB and STB are not empty and not full -11 – PTB and STB are full - 16 - 2 - read-only - - - TBSEL - Transmit Buffer Select -Selects the transmit buffer to be loaded with a message. Use the TBUF registers for -access. TBSEL needs to be stable all the time the TBUF registers are written and when -TSNEXT is set. -0 - PTB (high-priority buffer) -1 - STB -The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - 15 - 1 - read-write - - - LOM - Listen Only Mode -0 - Disabled -1 - Enabled -LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM -is enabled and LBME is disabled. -LOM=1 and LBME=0 disables all transmissions. -LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables -the transmission of own frames. - 14 - 1 - read-write - - - STBY - Transceiver Standby Mode -0 - Disabled -1 - Enabled -This register bit is connected to the output signal stby which can be used to control a -standby mode of a transceiver. -STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. -If the host sets STBY to 0 then the host needs to wait for the time required by the -transceiver to start up before the host requests a new transmission. - 13 - 1 - read-write - - - TPE - Transmit Primary Enable -1 - Transmission enable for the message in the high-priority PTB -0 - No transmission for the PTB -If TPE is set, the message from the PTB will be transmitted at the next possible transmit -position. A started transmission from the STB will be completed before, but pending new -messages are delayed until the PTB message has been transmitted. -TPE stays set until the message has been transmitted successfully or it is aborted using -TPA. -The host controller can set TPE to 1 but can not reset it to 0. This would only be possible -using TPA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 12 - 1 - read-write - - - TPA - Transmit Primary Abort -1 – Aborts a transmission from PTB which has been requested by TPE=1 but not -started yet. (The data bytes of the message remains in the PTB.) -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA -automatically de-asserts TPE. -The host controller can set TPA to 1 but can not reset it to 0. -During the short time while the CAN-CTRL core resets the bit, it cannot be set by the -host. -The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). -TPA should not be set simultaneously with TPE. - 11 - 1 - read-write - - - TSONE - Transmit Secondary ONE frame -1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message -and in priority mode this is the one with the highest priority. -TSONE in priority mode is difficult to handle, because it is not always clear which -message will be transmitted if new messages are written to the STB meanwhile. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSONE stays set until the message has been transmitted successfully or it is aborted -using TSA. -The host controller can set TSONE to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 10 - 1 - read-write - - - TSALL - Transmit Secondary ALL frames -1 – Transmission enable of all messages in the STB. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSALL stays set until all messages have been transmitted successfully or they are aborted -using TSA. -The host controller can set TSALL to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the messages. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). -If during a transmission the STB is loaded with a new frame then the new frame will be -transmitted too. In other words: a transmission initiated by TSALL is finished when the -STB becomes empty. - 9 - 1 - read-write - - - TSA - Transmit Secondary Abort -1 – Aborts a transmission from STB which has been requested but not started yet. -For a TSONE transmission, only one frame is aborted while for a TSALL -Transmission, all frames are aborted. -One or all message slots will be released which updates TSSTAT. -All aborted messages are lost because they are not accessible any more. -If in priority mode a TSONE transmission is aborted, then it is not clear which -frame will be aborted if new frames are written to the STB meanwhile. -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. -The host controller can set TSA to 1 but can not reset it to 0. -The bit will be reset to the hardware reset value if RESET=1. -TSA should not be set simultaneously with TSONE or TSALL. - 8 - 1 - read-write - - - RESET - RESET request bit -1 - The host controller performs a local reset of CAN-CTRL. -0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. -Bit RESET forces several components to a reset state. -RESET is automatically set if the node enters “bus off” state. -Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. -This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. -The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - 7 - 1 - read-write - - - LBME - Loop Back Mode, External -0 - Disabled -1 - EnabledLBME should not be enabled while a transmission is active - 6 - 1 - read-write - - - LBMI - Loop Back Mode, Internal -0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - 5 - 1 - read-write - - - TPSS - Transmission Primary Single Shot mode for PTB -0 - Disabled -1 - Enabled - 4 - 1 - read-write - - - TSSS - Transmission Secondary Single Shot mode for STB -0 - Disabled -1 - Enabled - 3 - 1 - read-write - - - RACTIVE - Reception ACTIVE (Receive Status bit) -1 - The controller is currently receiving a frame. -0 - No receive activity. - 2 - 1 - read-only - - - TACTIVE - Transmission ACTIVE (Transmit Status bit) -1 - The controller is currently transmitting a frame. -0 - No transmit activity. - 1 - 1 - read-only - - - BUSOFF - Bus Off (Bus Status bit) -1 - The controller status is “bus off”. -0 - The controller status is “bus on”. -Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. -See Chapter 3.9.10.6 for details. - 0 - 1 - read-write - - - - - RTIE - Receive and Transmit Interrupt Enable Register RTIE - 0xa4 - 8 - 0xFE - 0xFF - - - RIE - Receive Interrupt Enable -0 – Disabled, 1 – Enabled - 7 - 1 - read-write - - - ROIE - RB Overrun Interrupt Enable -0 – Disabled, 1 – Enabled - 6 - 1 - read-write - - - RFIE - RB Full Interrupt Enable -0 – Disabled, 1 – Enabled - 5 - 1 - read-write - - - RAFIE - RB Almost Full Interrupt Enable -0 – Disabled, 1 – Enabled - 4 - 1 - read-write - - - TPIE - Transmission Primary Interrupt Enable -0 – Disabled, 1 – Enabled - 3 - 1 - read-write - - - TSIE - Transmission Secondary Interrupt Enable -0 – Disabled, 1 – Enabled - 2 - 1 - read-write - - - EIE - Error Interrupt Enable -0 – Disabled, 1 – Enabled - 1 - 1 - read-write - - - TSFF - If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag -1 - The STB is filled with the maximal number of messages. -0 - The STB is not filled with the maximal number of messages. -If the STB is disabled using STB_DISABLE, then TSFF=0. -If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag -1 - The buffer slot selected by TBPTR is filled. -0 - The buffer slot selected by TBPTR is empty. - 0 - 1 - read-only - - - - - RTIF - Receive and Transmit Interrupt Flag Register RTIF (0xa5) - 0xa5 - 8 - 0x00 - 0xFF - - - RIF - Receive Interrupt Flag -1 - Data or a remote frame has been received and is available in the receive buffer. -0 - No frame has been received. - 7 - 1 - read-write - - - ROIF - RB Overrun Interrupt Flag -1 - At least one received message has been overwritten in the RB. -0 - No RB overwritten. -In case of an overrun both ROIF and RFIF will be set. - 6 - 1 - read-write - - - RFIF - RB Full Interrupt Flag -1 - All RBs are full. If no RB will be released until the next valid message is received, -the oldest message will be lost. -0 - The RB FIFO is not full. - 5 - 1 - read-write - - - RAFIF - RB Almost Full Interrupt Flag -1 - number of filled RB slots >= AFWL_i -0 - number of filled RB slots < AFWL_i - 4 - 1 - read-write - - - TPIF - Transmission Primary Interrupt Flag -1 - The requested transmission of the PTB has been successfully completed. -0 - No transmission of the PTB has been completed. -In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - 3 - 1 - read-write - - - TSIF - Transmission Secondary Interrupt Flag -1 - The requested transmission of the STB has been successfully completed. -0 - No transmission of the STB has been completed successfully. -In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of -the message. - 2 - 1 - read-write - - - EIF - Error Interrupt Flag -1 - The border of the error warning limit has been crossed in either direction, -or the BUSOFF bit has been changed in either direction. -0 - There has been no change. - 1 - 1 - read-write - - - AIF - Abort Interrupt Flag -1 - After setting TPA or TSA the appropriated message(s) have been aborted. -It is recommended to not set both TPA and TSA simultaneously because both -source AIF. -0 - No abort has been executed. -The AIF does not have an associated enable register. - 0 - 1 - read-write - - - - - ERRINT - ERRor INTerrupt Enable and Flag Register ERRINT - 0xa6 - 8 - 0x00 - 0xFF - - - EWARN - Error WARNing limit reached -1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - 7 - 1 - read-only - - - EPASS - Error Passive mode active -0 - not active (node is error active) -1 - active (node is error passive) - 6 - 1 - read-only - - - EPIE - Error Passive Interrupt Enable - 5 - 1 - read-write - - - EPIF - Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error -active to error passive or vice versa and if this interrupt is enabled. - 4 - 1 - read-write - - - ALIE - Arbitration Lost Interrupt Enable - 3 - 1 - read-write - - - ALIF - Arbitration Lost Interrupt Flag - 2 - 1 - read-write - - - BEIE - Bus Error Interrupt Enable - 1 - 1 - read-write - - - BEIF - Bus Error Interrupt Flag - 0 - 1 - read-write - - - - - LIMIT - Warning Limits Register LIMIT - 0xa7 - 8 - 0x1B - 0xFF - - - AFWL - receive buffer Almost Full Warning Limit -AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. -AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . -AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) -AFWL_i > nRB is meaningless and automatically treated as nRB. -AFWL_i = nRB is a valid value, but note that RFIF also exists. - 4 - 4 - read-write - - - EWL - Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. -The value of EWL controls EIF. - 0 - 4 - read-write - - - - - S_PRESC - Bit Timing Register(Slow Speed) - 0xa8 - 32 - 0x01020203 - 0xFF7F7FFF - - - S_PRESC - Prescaler (slow speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - S_SJW - Synchronization Jump Width (slow speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 7 - read-write - - - S_SEG_2 - Bit Timing Segment 2 (slow speed) -Time after the sample point. - 8 - 7 - read-write - - - S_SEG_1 - Bit Timing Segment 1 (slow speed) -The sample point will be set to after start of bit time. - 0 - 8 - read-write - - - - - F_PRESC - Bit Timing Register(Fast Speed) - 0xac - 32 - 0x01020203 - 0xFF0F0F0F - - - F_PRESC - Prescaler (fast speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - F_SJW - Synchronization Jump Width (fast speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 4 - read-write - - - F_SEG_2 - Bit Timing Segment 2 (fast speed) -Time after the sample point - 8 - 4 - read-write - - - F_SEG_1 - Bit Timing Segment 1 (fast speed) -The sample point will be set to after start of bit time. - 0 - 4 - read-write - - - - - EALCAP - Error and Arbitration Lost Capture Register EALCAP - 0xb0 - 8 - 0x00 - 0xFF - - - KOER - Kind Of ERror (Error code) -000 - no error -001 - BIT ERROR -010 - FORM ERROR -011 - STUFF ERROR -100 - ACKNOWLEDGEMENT ERROR -101 - CRC ERROR -110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) -111 - not used -KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - 5 - 3 - read-only - - - ALC - Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - 0 - 5 - read-only - - - - - TDC - Transmitter Delay Compensation Register TDC - 0xb1 - 8 - 0x00 - 0xFF - - - TDCEN - Transmitter Delay Compensation ENable -TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - 7 - 1 - read-write - - - SSPOFF - Secondary Sample Point OFFset -The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. -SSPOFF is given as a number of TQ. - 0 - 7 - read-write - - - - - RECNT - Error Counter Registers RECNT - 0xb2 - 8 - 0x00 - 0xFF - - - RECNT - Receive Error CouNT (number of errors during reception) -RECNT is incremented and decremented as defined in the CAN specification. -RECNT does not overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - TECNT - Error Counter Registers TECNT - 0xb3 - 8 - 0x00 - 0xFF - - - TECNT - Transmit Error CouNT (number of errors during transmission) -TECNT is incremented and decremented as defined in the CAN specification. -In case of the “bus off state” TECNT may overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - ACFCTRL - Acceptance Filter Control Register ACFCTRL - 0xb4 - 8 - 0x00 - 0x2F - - - SELMASK - SELect acceptance MASK -0 - Registers ACF_x point to acceptance code -1 - Registers ACF_x point to acceptance mask. -ACFADR selects one specific acceptance filter. - 5 - 1 - read-write - - - ACFADR - acceptance filter address -ACFADR points to a specific acceptance filter. -The selected filter is accessible using theregisters ACF_x. -Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. -A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. -ACF_NUMBER = 16. - 0 - 4 - read-write - - - - - TIMECFG - CiA 603 Time-Stamping TIMECFG - 0xb5 - 8 - 0x00 - 0x03 - - - TIMEPOS - TIME-stamping POSition -0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - 1 - 1 - read-write - - - TIMEEN - TIME-stamping ENable -0 – disabled -1 – enabled - 0 - 1 - read-write - - - - - ACF_EN - Acceptance Filter Enable ACF_EN - 0xb6 - 16 - 0x0000 - 0xFFFF - - - ACF_EN - Acceptance filter Enable -1 - acceptance filter enabled -0 - acceptance filter disable -Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. -Disabled filters reject a message. Only enabled filters can accept a message if the -appropriate AMASK / ACODE configuration matches. - 0 - 16 - read-write - - - - - ACF - Acceptance CODE ACODE or ACMASK - 0xb8 - 32 - 0x00000000 - 0x7FFFFFFF - - - AIDEE - Acceptance mask IDE bit check enable -1 - acceptance filter accepts either standard or extended as defined by AIDE -0 - acceptance filter accepts both standard or extended frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 30 - 1 - read-write - - - AIDE - Acceptance mask IDE bit value -If AIDEE=1 then: -1 - acceptance filter accepts only extended frames -0 - acceptance filter accepts only standard frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 29 - 1 - read-write - - - CODE_MASK - Acceptance CODE -1 - ACC bit value to compare with ID bit of the received message -0 - ACC bit value to compare with ID bit of the received message -ACODE_x(10:0) will be used for extended frames. -ACODE_x(28:0) will be used for extended frames. -Only filter 0 is affected by the power-on reset. -Acceptance MASK(if SELMASK ==1 ) -1 - acceptance check for these bits of receive identifier disabled -0 - acceptance check for these bits of receive identifier enable -AMASK_x(10:0) will be used for extended frames. -AMASK_x(28:0) will be used for extended frames. -Disabled bits result in accepting the message. Therefore the default configuration after -reset for filter 0 accepts all messages. -Only filter 0 is affected by the power-on reset. - 0 - 29 - read-write - - - - - VER - Version Information VER - 0xbc - 16 - 0x0000 - 0xFFFF - - - VERSION - Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and -VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - 0 - 16 - read-write - - - - - TBSLOT - TTCAN: TB Slot Pointer TBSLOT - 0xbe - 8 - 0x00 - 0xFF - - - TBE - set TB slot to “Empty” -1 - slot selected by TBPTR shall be marked as “empty” -0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. -If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - transmissionis not active any more. -If both TBF and TBE are set, then TBE wins - 7 - 1 - read-write - - - TBF - set TB slot to “Filled” -1 - slot selected by TBPTR shall be marked as “filled” -0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. -If both TBF and TBE are set, then TBE wins. - 6 - 1 - read-write - - - TBPTR - Pointer to a TB message slot. -0x00 - Pointer to the PTB -others - Pointer to a slot in the STB -The message slot pointed to by TBPTR is readable / writable using the TBUF registers. -Write access is only possible if TSFF=0. -Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. -TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. -TBPTR can only point to buffer slots, that exist in the hardware. -Unusable bits ofTBPTR are fixed to 0. -TBPTR is limited to the PTB and 63 STB slots. - More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - 0 - 6 - read-write - - - - - TTCFG - TTCAN: Time Trigger Configuration TTCFG - 0xbf - 8 - 0x00 - 0xFF - - - WTIE - Watch Trigger Interrupt Enable - 7 - 1 - read-write - - - WTIF - Watch Trigger Interrupt Flag -WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - 6 - 1 - read-write - - - TEIF - Trigger Error Interrupt Flag -The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - 5 - 1 - read-write - - - TTIE - Time Trigger Interrupt Enable -If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - 4 - 1 - read-write - - - TTIF - Time Trigger Interrupt Flag -TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. -Writing an one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. -If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - 3 - 1 - read-write - - - T_PRESC - TTCAN Timer PRESCaler -00b - 1 -01b - 2 -10b - 4 -11b - 8 -The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. -T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - 1 - 2 - read-write - - - TTEN - Time Trigger Enable -1 - TTCAN enabled, timer is running0 - disabled - 0 - 1 - read-write - - - - - REF_MSG - TTCAN: Reference Message REF_MSG - 0xc0 - 32 - 0x00000000 - 0x9FFFFFFF - - - REF_IDE - REFerence message IDE bit. - 31 - 1 - read-write - - - REF_MSG - REFerence message IDentifier. -If REF_IDE is -1 - REF_ID(28:0) is valid (extended ID) -0 - REF_ID(10:0) is valid (standard ID) -REF_ID is used in TTCAN mode to detect a reference message. This holds for time -slaves (reception) as well as for the time master (transmission). If the reference -message is detected and there are no errors, then the Sync_Mark of this frame will -become the Ref_Mark. -REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. -These bits are used for up to 8 potential time masters. -CAN-CTRL recognizes the reference message only by ID. The payload is not tested. -Additional note: A time master will transmit a reference message in the same way as a -normal frame. REF_ID is intended for detection of a successful transmission of a -reference message. - 0 - 29 - read-write - - - - - TRIG_CFG - TTCAN: Trigger Configuration TRIG_CFG - 0xc4 - 16 - 0x0000 - 0xF73F - - - TEW - Transmit Enable Window -For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time -where the frame is allowed to start. TWE+1 defines the number of ticks. -TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - 12 - 4 - read-write - - - TTYPE - Trigger Type -000b - Immediate Trigger for immediate transmission -001b - Time Trigger for receive triggers -010b - Single Shot Transmit Trigger for exclusive time windows -011b - Transmit Start Trigger for merged arbitrating time windows -100b - Transmit Stop Trigger for merged arbitrating time windows -others - no action -The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the -transmit triggers. See Chapter 6.4 for more details. - 8 - 3 - read-write - - - TTPTR - Transmit Trigger TB slot Pointer -If TTPTR is too big and points to a slot that is not available, then TEIF is set and no -new trigger can be activated after a write access to TT_TRIG_1. -If TTPTR points to an empty slot, then TEIF will be set at the moment, when the -trigger time is reached. - 0 - 6 - read-write - - - - - TT_TRIG - TTCAN: Trigger Time TT_TRIG - 0xc6 - 16 - 0x0000 - 0xFFFF - - - TT_TRIG - Trigger Time -TT_TRIG(15:0) defines the cycle time for a trigger. -For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - 0 - 16 - read-write - - - - - TT_WTRIG - TTCAN: Watch Trigger Time TT_WTRIG - 0xc8 - 16 - 0x0000 - 0xFFFF - - - TT_WTRIG - Watch Trigger Time -TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - 0 - 16 - read-write - - - - - - - CAN1 - CAN1 - CAN - 0xf0084000 - - - CAN2 - CAN2 - CAN - 0xf0088000 - - - CAN3 - CAN3 - CAN - 0xf008c000 - - - WDG0 - WDG0 - WDOG - 0xf0090000 - - 0x10 - 0x10 - registers - - - - CTRL - Control Register - 0x10 - 32 - 0x00000000 - 0x000007FF - - - RSTTIME - The time interval of the reset stage: -0: Clock period x 2^7 -1: Clock period x 2^8 -2: Clock period x 2^9 -3: Clock period x 2^10 -4: Clock period x 2^11 -5: Clock period x 2^12 -6: Clock period x 2^13 -7: Clock period x 2^14 - 8 - 3 - read-write - - - INTTIME - The timer interval of the interrupt stage: -0: Clock period x 2^6 -1: Clock period x 2^8 -2: Clock period x 2^10 -3: Clock period x 2^11 -4: Clock period x 2^12 -5: Clock period x 2^13 -6: Clock period x 2^14 -7: Clock period x 2^15 -8: Clock period x 2^17 -9: Clock period x 2^19 -10: Clock period x 2^21 -11: Clock period x 2^23 -12: Clock period x 2^25 -13: Clock period x 2^27 -14: Clock period x 2^29 -15: Clock period x 2^31 - 4 - 4 - read-write - - - RSTEN - Enable or disable the watchdog reset -0: Disable -1: Enable - 3 - 1 - read-write - - - INTEN - Enable or disable the watchdog interrupt -0: Disable -1: Enable - 2 - 1 - read-write - - - CLKSEL - Clock source of timer: -0: EXTCLK -1: PCLK - 1 - 1 - read-write - - - EN - Enable or disable the watchdog timer -0: Disable -1: Enable - 0 - 1 - read-write - - - - - RESTART - Restart Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - RESTART - Write the magic number -ATCWDT200_RESTART_NUM to restart the -watchdog timer. - 0 - 16 - write-only - - - - - WREN - Write Protection Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - WEN - Write the magic code to disable the write -protection of the Control Register and the -Restart Register. - 0 - 16 - write-only - - - - - ST - Status Register - 0x1c - 32 - 0x00000000 - 0x00000001 - - - INTEXPIRED - The status of the watchdog interrupt timer -0: timer is not expired yet -1: timer is expired - 0 - 1 - read-write - - - - - - - WDG1 - WDG1 - WDOG - 0xf0094000 - - - WDG2 - WDG2 - WDOG - 0xf0098000 - - - WDG3 - WDG3 - WDOG - 0xf009c000 - - - PWDG - PWDG - WDOG - 0xf40e8000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - RESERVED - Reserved - 16 - 15 - read-only - - - BARCTL - Bus Acccess Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - RESERVED - Reserved - 9 - 5 - read-only - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - RESERVED - Reserved - 2 - 2 - read-only - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RESERVED - Not used - 24 - 8 - read-only - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - read-write - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - read-write - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - read-write - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - read-write - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - read-write - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - read-write - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - RESERVED - Not used - 2 - 2 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - TXWRD_TXFIFO0 - TXFIFO for sending message to other core - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - RXWRD_RXFIFO0 - RXFIFO for receiving message from other core - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - MBX1A - MBX1A - MBX - 0xf00a8000 - - - MBX1B - MBX1B - MBX - 0xf00ac000 - - - PTPC - PTPC - PTPC - 0xf00b0000 - - 0x0 - 0x200c - registers - - - - PTPC_0_CTRL0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description avaiable - 6 - 1 - read-write - - - RESERVED - No description avaiable - 5 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow -1: coarse update, ns counter add ss_incr[7:0] each clk - 1 - 1 - read-write - - - TIMER_ENABLE - No description avaiable - 0 - 1 - read-write - - - - - PTPC_0_CTRL1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - PTPC_0_TIMEH - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description avaiable - 0 - 32 - read-only - - - - - PTPC_0_TIMEL - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description avaiable - 0 - 32 - read-only - - - - - PTPC_0_TS_UPDTH - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - PTPC_0_TS_UPDTL - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description avaiable - 0 - 31 - read-write - - - - - PTPC_0_ADDEND - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - PTPC_0_TARH - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - PTPC_0_TARL - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description avaiable - 0 - 32 - read-write - - - - - PTPC_0_PPS_CTRL - No description avaiable - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description avaiable - 0 - 4 - read-write - - - - - PTPC_0_CAPT_SNAPH - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - PTPC_0_CAPT_SNAPL - No description avaiable - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description avaiable - 0 - 32 - read-write - - - - - PTPC_1_CTRL0 - Control Register 0 - 0x1000 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description avaiable - 6 - 1 - read-write - - - RESERVED - No description avaiable - 5 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow -1: coarse update, ns counter add ss_incr[7:0] each clk - 1 - 1 - read-write - - - TIMER_ENABLE - No description avaiable - 0 - 1 - read-write - - - - - PTPC_1_CTRL1 - Control Register 1 - 0x1004 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - PTPC_1_TIMEH - timestamp high - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description avaiable - 0 - 32 - read-only - - - - - PTPC_1_TIMEL - timestamp low - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description avaiable - 0 - 32 - read-only - - - - - PTPC_1_TS_UPDTH - timestamp update high - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - PTPC_1_TS_UPDTL - timestamp update low - 0x1014 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description avaiable - 0 - 31 - read-write - - - - - PTPC_1_ADDEND - No description avaiable - 0x1018 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - PTPC_1_TARH - No description avaiable - 0x101c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - PTPC_1_TARL - No description avaiable - 0x1020 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description avaiable - 0 - 32 - read-write - - - - - PTPC_1_PPS_CTRL - No description avaiable - 0x102c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description avaiable - 0 - 4 - read-write - - - - - PTPC_1_CAPT_SNAPH - No description avaiable - 0x1030 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - PTPC_1_CAPT_SNAPL - No description avaiable - 0x1034 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description avaiable - 0 - 32 - read-write - - - - - TIME_SEL - No description avaiable - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description avaiable - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description avaiable - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description avaiable - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - INT_STS - No description avaiable - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description avaiable - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description avaiable - 17 - 1 - read-write - - - PPS_INT_STS1 - No description avaiable - 16 - 1 - read-write - - - COMP_INT_STS0 - No description avaiable - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description avaiable - 1 - 1 - read-write - - - PPS_INT_STS0 - No description avaiable - 0 - 1 - read-write - - - - - INT_EN - No description avaiable - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description avaiable - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description avaiable - 17 - 1 - read-write - - - PPS_INT_STS1 - No description avaiable - 16 - 1 - read-write - - - COMP_INT_STS0 - No description avaiable - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description avaiable - 1 - 1 - read-write - - - PPS_INT_STS0 - No description avaiable - 0 - 1 - read-write - - - - - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c0000 - - 0x0 - 0x40 - registers - - - - MUXCFG_HDMA_MUX0 - HDMA MUX0 Configuration - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX1 - HDMA MUX1 Configuration - 0x4 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX2 - HDMA MUX2 Configuration - 0x8 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX3 - HDMA MUX3 Configuration - 0xc - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX4 - HDMA MUX4 Configuration - 0x10 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX5 - HDMA MUX5 Configuration - 0x14 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX6 - HDMA MUX6 Configuration - 0x18 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_HDMA_MUX7 - HDMA MUX7 Configuration - 0x1c - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX0 - XDMA MUX0 Configuration - 0x20 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX1 - XDMA MUX1 Configuration - 0x24 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX2 - XDMA MUX2 Configuration - 0x28 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX3 - XDMA MUX3 Configuration - 0x2c - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX4 - XDMA MUX4 Configuration - 0x30 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX5 - XDMA MUX5 Configuration - 0x34 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX6 - XDMA MUX6 Configuration - 0x38 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - MUXCFG_XDMA_MUX7 - XDMA MUX7 Configuration - 0x3c - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMA - 0xf00c4000 - - 0x10 - 0x15c - registers - - - - DMACFG - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACTRL - DMAC Control Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - CHABORT - Channel Abort Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - INTSTATUS - Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0x00FFFFFF - - - TC - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 16 - 8 - read-write - - - ABORT - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 8 - 8 - read-write - - - ERROR - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 8 - read-write - - - - - CHEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - CHCTRL_CH0_CTRL - Channel n Control Register - 0x40 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH0_TRANSIZE - Channel n Transfer Size Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH0_SRCADDR - Channel n Source Address Low Part Register - 0x48 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH0_SRCADDRH - Channel n Source Address High Part Register - 0x4c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH0_DSTADDR - Channel n Destination Address Low Part Register - 0x50 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH0_DSTADDRH - Channel n Destination Address High Part Register - 0x54 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH0_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x58 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH0_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH1_CTRL - Channel n Control Register - 0x60 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH1_TRANSIZE - Channel n Transfer Size Register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH1_SRCADDR - Channel n Source Address Low Part Register - 0x68 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH1_SRCADDRH - Channel n Source Address High Part Register - 0x6c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH1_DSTADDR - Channel n Destination Address Low Part Register - 0x70 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH1_DSTADDRH - Channel n Destination Address High Part Register - 0x74 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH1_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x78 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH1_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH2_CTRL - Channel n Control Register - 0x80 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH2_TRANSIZE - Channel n Transfer Size Register - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH2_SRCADDR - Channel n Source Address Low Part Register - 0x88 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH2_SRCADDRH - Channel n Source Address High Part Register - 0x8c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH2_DSTADDR - Channel n Destination Address Low Part Register - 0x90 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH2_DSTADDRH - Channel n Destination Address High Part Register - 0x94 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH2_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x98 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH2_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH3_CTRL - Channel n Control Register - 0xa0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH3_TRANSIZE - Channel n Transfer Size Register - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH3_SRCADDR - Channel n Source Address Low Part Register - 0xa8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH3_SRCADDRH - Channel n Source Address High Part Register - 0xac - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH3_DSTADDR - Channel n Destination Address Low Part Register - 0xb0 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH3_DSTADDRH - Channel n Destination Address High Part Register - 0xb4 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH3_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0xb8 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH3_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH4_CTRL - Channel n Control Register - 0xc0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH4_TRANSIZE - Channel n Transfer Size Register - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH4_SRCADDR - Channel n Source Address Low Part Register - 0xc8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH4_SRCADDRH - Channel n Source Address High Part Register - 0xcc - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH4_DSTADDR - Channel n Destination Address Low Part Register - 0xd0 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH4_DSTADDRH - Channel n Destination Address High Part Register - 0xd4 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH4_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0xd8 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH4_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH5_CTRL - Channel n Control Register - 0xe0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH5_TRANSIZE - Channel n Transfer Size Register - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH5_SRCADDR - Channel n Source Address Low Part Register - 0xe8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH5_SRCADDRH - Channel n Source Address High Part Register - 0xec - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH5_DSTADDR - Channel n Destination Address Low Part Register - 0xf0 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH5_DSTADDRH - Channel n Destination Address High Part Register - 0xf4 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH5_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0xf8 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH5_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH6_CTRL - Channel n Control Register - 0x100 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH6_TRANSIZE - Channel n Transfer Size Register - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH6_SRCADDR - Channel n Source Address Low Part Register - 0x108 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH6_SRCADDRH - Channel n Source Address High Part Register - 0x10c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH6_DSTADDR - Channel n Destination Address Low Part Register - 0x110 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH6_DSTADDRH - Channel n Destination Address High Part Register - 0x114 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH6_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x118 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH6_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH7_CTRL - Channel n Control Register - 0x120 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - CHCTRL_CH7_TRANSIZE - Channel n Transfer Size Register - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - CHCTRL_CH7_SRCADDR - Channel n Source Address Low Part Register - 0x128 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH7_SRCADDRH - Channel n Source Address High Part Register - 0x12c - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH7_DSTADDR - Channel n Destination Address Low Part Register - 0x130 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - CHCTRL_CH7_DSTADDRH - Channel n Destination Address High Part Register - 0x134 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - CHCTRL_CH7_LLPOINTER - Channel n Linked List Pointer Low Part Register - 0x138 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - CHCTRL_CH7_LLPOINTERH - Channel n Linked List Pointer High Part Register - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - - - XDMA - XDMA - DMA - 0xf3048000 - - - RNG - RNG - RNG - 0xf00c8000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 7 - 25 - read-write - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - RESERVED - Not used - 2 - 2 - read-only - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 7 - 25 - read-only - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - RESERVED - Not used - 2 - 2 - read-only - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 24 - 8 - read-only - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - RESERVED - Not used - 17 - 4 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - RESERVED - Not used - 7 - 1 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - RESERVED - Not used - 0 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - RESERVED - OSC1 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 24 - 8 - read-only - - - RESERVED - OSC0 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - RESERVED - Statistical test error -Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is -cleared by a hardware or software reset or by writing 1 to the CMD[CE]. -0 No fail for the statistical tests. -1 Failed the statistical tests during the initialization - 4 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 2 - 1 - read-only - - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 1 - 1 - read-only - - - RESERVED - Linear feedback shift register (LFSR) error -When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. - 0 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - R2SK_FO2S0 - FIFO out to SDP as AES engine key - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S1 - FIFO out to SDP as AES engine key - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S2 - FIFO out to SDP as AES engine key - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S3 - FIFO out to SDP as AES engine key - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S4 - FIFO out to SDP as AES engine key - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S5 - FIFO out to SDP as AES engine key - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S6 - FIFO out to SDP as AES engine key - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - R2SK_FO2S7 - FIFO out to SDP as AES engine key - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf00cc000 - - 0x0 - 0x50 - registers - - - - SOFTMKEY_SFK0 - software set symmetric key - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK1 - software set symmetric key - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK2 - software set symmetric key - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK3 - software set symmetric key - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK4 - software set symmetric key - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK5 - software set symmetric key - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK6 - software set symmetric key - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTMKEY_SFK7 - software set symmetric key - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK0 - system asymmetric key - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK1 - system asymmetric key - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK2 - system asymmetric key - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK3 - system asymmetric key - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK4 - system asymmetric key - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK5 - system asymmetric key - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK6 - system asymmetric key - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SOFTPKEY_SPK7 - system asymmetric key - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of followings -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of followings -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - I2S0 - I2S0 - I2S - 0xf0100000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 19 - 13 - read-write - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 16 - 16 - read-write - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 17 - 15 - read-only - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - read-write - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - read-write - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - RSV - Reserved - 0 - 1 - read-only - - - - - RXD_DATA0 - Rx Data0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - RXD_DATA1 - Rx Data1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - RXD_DATA2 - Rx Data2 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - RXD_DATA3 - Rx Data3 - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - read-only - - - - - TXD_DATA0 - Tx Data0 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - TXD_DATA1 - Tx Data1 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - TXD_DATA2 - Tx Data2 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - TXD_DATA3 - Tx Data3 - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description avaiable - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - RSV - Reserved - 31 - 1 - read-write - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[3:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -... - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - RSV - Reserved - 14 - 18 - read-write - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - RSV - Reserved - 11 - 1 - read-write - - - RSV - Reserved - 10 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - RXDSLOT_DATA0 - Rx Slots Enable for Rx Data0 - 0x60 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - RXDSLOT_DATA1 - Rx Slots Enable for Rx Data1 - 0x64 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - RXDSLOT_DATA2 - Rx Slots Enable for Rx Data2 - 0x68 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - RXDSLOT_DATA3 - Rx Slots Enable for Rx Data3 - 0x6c - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA0 - Tx Slots Enable for Tx Data0. - 0x70 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA1 - Tx Slots Enable for Tx Data1. - 0x74 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA2 - Tx Slots Enable for Tx Data2. - 0x78 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - TXDSLOT_DATA3 - Tx Slots Enable for Tx Data3. - 0x7c - 32 - 0x0000FFFF - 0xFFFFFFFF - - - EN - No description avaiable - 0 - 32 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0104000 - - - I2S2 - I2S2 - I2S - 0xf0108000 - - - I2S3 - I2S3 - I2S - 0xf010c000 - - - DAO - DAO - DAO - 0xf0110000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000300FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to comsume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x000007C0 - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0114000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - read-write - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - read-write - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - read-write - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - read-write - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description avaiable - 18 - 2 - read-write - - - CH8_TYPE - No description avaiable - 16 - 2 - read-write - - - CH7_TYPE - No description avaiable - 14 - 2 - read-write - - - CH6_TYPE - No description avaiable - 12 - 2 - read-write - - - CH5_TYPE - No description avaiable - 10 - 2 - read-write - - - CH4_TYPE - No description avaiable - 8 - 2 - read-write - - - CH3_TYPE - No description avaiable - 6 - 2 - read-write - - - CH2_TYPE - No description avaiable - 4 - 2 - read-write - - - CH1_TYPE - No description avaiable - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMADDR - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMDATA - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PWM0 - PWM0 - PWM - 0xf0200000 - - 0x0 - 0x290 - registers - - - - UNLK - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - STA - Counter start register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - RESERVED - reserved - 0 - 4 - read-write - - - - - RLD - Counter reload register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - RESERVED - reserved - 0 - 4 - read-write - - - - - CMP_0 - Comparator register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_1 - Comparator register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_2 - Comparator register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_3 - Comparator register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_4 - Comparator register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_5 - Comparator register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_6 - Comparator register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_7 - Comparator register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_8 - Comparator register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_9 - Comparator register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_10 - Comparator register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_11 - Comparator register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_12 - Comparator register - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_13 - Comparator register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_14 - Comparator register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_15 - Comparator register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_16 - Comparator register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_17 - Comparator register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_18 - Comparator register - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_19 - Comparator register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_20 - Comparator register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_21 - Comparator register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_22 - Comparator register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - CMP_23 - Comparator register - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - FRCMD - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0~7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - SHLK - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, wirte access is not permitted - 31 - 1 - read-write - - - - - CHCFG_0 - Output channel configure register - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_1 - Output channel configure register - 0x84 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_2 - Output channel configure register - 0x88 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_3 - Output channel configure register - 0x8c - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_4 - Output channel configure register - 0x90 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_5 - Output channel configure register - 0x94 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_6 - Output channel configure register - 0x98 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_7 - Output channel configure register - 0x9c - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_8 - Output channel configure register - 0xa0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_9 - Output channel configure register - 0xa4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_10 - Output channel configure register - 0xa8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_11 - Output channel configure register - 0xac - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_12 - Output channel configure register - 0xb0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_13 - Output channel configure register - 0xb4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_14 - Output channel configure register - 0xb8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_15 - Output channel configure register - 0xbc - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_16 - Output channel configure register - 0xc0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_17 - Output channel configure register - 0xc4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_18 - Output channel configure register - 0xc8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_19 - Output channel configure register - 0xcc - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_20 - Output channel configure register - 0xd0 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_21 - Output channel configure register - 0xd4 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_22 - Output channel configure register - 0xd8 - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - CHCFG_23 - Output channel configure register - 0xdc - 32 - 0x00000000 - 0xFFFF0003 - - - RESERVED - read as 0 - 29 - 3 - read-write - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - RESERVED - read as 0 - 21 - 3 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - RESERVED - read as 0 - 0 - 1 - read-write - - - - - GCR - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFE7 - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - read-write - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - SHCR - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x00001FFF - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - CAPPOS_0 - Capture rising edge register - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_1 - Capture rising edge register - 0x104 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_2 - Capture rising edge register - 0x108 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_3 - Capture rising edge register - 0x10c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_4 - Capture rising edge register - 0x110 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_5 - Capture rising edge register - 0x114 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_6 - Capture rising edge register - 0x118 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_7 - Capture rising edge register - 0x11c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_8 - Capture rising edge register - 0x120 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_9 - Capture rising edge register - 0x124 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_10 - Capture rising edge register - 0x128 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_11 - Capture rising edge register - 0x12c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_12 - Capture rising edge register - 0x130 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_13 - Capture rising edge register - 0x134 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_14 - Capture rising edge register - 0x138 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_15 - Capture rising edge register - 0x13c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_16 - Capture rising edge register - 0x140 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_17 - Capture rising edge register - 0x144 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_18 - Capture rising edge register - 0x148 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_19 - Capture rising edge register - 0x14c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_20 - Capture rising edge register - 0x150 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_21 - Capture rising edge register - 0x154 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_22 - Capture rising edge register - 0x158 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CAPPOS_23 - Capture rising edge register - 0x15c - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - CNT - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - RESERVED - read-only as 0 - 0 - 4 - read-only - - - - - CAPNEG_0 - Capture falling edge register - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_1 - Capture falling edge register - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_2 - Capture falling edge register - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_3 - Capture falling edge register - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_4 - Capture falling edge register - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_5 - Capture falling edge register - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_6 - Capture falling edge register - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_7 - Capture falling edge register - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_8 - Capture falling edge register - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_9 - Capture falling edge register - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_10 - Capture falling edge register - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_11 - Capture falling edge register - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_12 - Capture falling edge register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_13 - Capture falling edge register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_14 - Capture falling edge register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_15 - Capture falling edge register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_16 - Capture falling edge register - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_17 - Capture falling edge register - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_18 - Capture falling edge register - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_19 - Capture falling edge register - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_20 - Capture falling edge register - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_21 - Capture falling edge register - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_22 - Capture falling edge register - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPNEG_23 - Capture falling edge register - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CNTCOPY - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - RESERVED - read-only as 0 - 0 - 4 - read-only - - - - - PWMCFG_0 - PWM channel configure register - 0x200 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_1 - PWM channel configure register - 0x204 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_2 - PWM channel configure register - 0x208 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_3 - PWM channel configure register - 0x20c - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_4 - PWM channel configure register - 0x210 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_5 - PWM channel configure register - 0x214 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_6 - PWM channel configure register - 0x218 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - PWMCFG_7 - PWM channel configure register - 0x21c - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - SR - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - read-write - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - read-write - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - read-write - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - read-write - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - read-write - - - - - IRQEN - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - DMAEN - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - CMPCFG_CMPCFG0 - Comparator configure register - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_1 - Comparator configure register - 0x234 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_2 - Comparator configure register - 0x238 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_3 - Comparator configure register - 0x23c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_4 - Comparator configure register - 0x240 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_5 - Comparator configure register - 0x244 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_6 - Comparator configure register - 0x248 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_7 - Comparator configure register - 0x24c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_8 - Comparator configure register - 0x250 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_9 - Comparator configure register - 0x254 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_10 - Comparator configure register - 0x258 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_11 - Comparator configure register - 0x25c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_12 - Comparator configure register - 0x260 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_13 - Comparator configure register - 0x264 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_14 - Comparator configure register - 0x268 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_15 - Comparator configure register - 0x26c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_16 - Comparator configure register - 0x270 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_17 - Comparator configure register - 0x274 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_18 - Comparator configure register - 0x278 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_19 - Comparator configure register - 0x27c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_20 - Comparator configure register - 0x280 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_21 - Comparator configure register - 0x284 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_22 - Comparator configure register - 0x288 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - CMPCFG_23 - Comparator configure register - 0x28c - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - RESERVED - No description avaiable - 0 - 1 - read-only - - - - - - - PWM1 - PWM1 - PWM - 0xf0210000 - - - PWM2 - PWM2 - PWM - 0xf0220000 - - - PWM3 - PWM3 - PWM - 0xf0230000 - - - HALL0 - HALL0 - HALL - 0xf0204000 - - 0x0 - 0x8c - registers - - - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x8001083F - - - READ - 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - RESERVED - reserved - 16 - 1 - read-write - - - SNAPEN - 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - 11 - 1 - read-write - - - RESERVED - reserved - 5 - 1 - read-write - - - RSTCNT - set to reset all counter and related snapshots - 4 - 1 - read-write - - - RESERVED - reserved - 2 - 2 - read-write - - - RESERVED - reserved - 0 - 2 - read-write - - - - - PHCFG - Phase configure register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLYSEL - This bit select delay start time: -1- start counting delay after pre-trigger -0- start counting delay after u,v,w toggle - 31 - 1 - read-write - - - RESERVED - reserved - 24 - 7 - read-write - - - DLYCNT - delay clock cycles number - 0 - 24 - read-write - - - - - WDGCFG - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - UVWCFG - U,V,W configure register - 0xc - 32 - 0x00000000 - 0x07FFFFFF - - - RESERVED - reserved - 24 - 3 - read-write - - - PRECNT - the clock cycle number which the pre flag will set before the next uvw transition - 0 - 24 - read-write - - - - - TRGOEN - Trigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- enable trigger output when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- enable trigger output when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- enable trigger output when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFEN - 1- enable trigger output when u flag set - 23 - 1 - read-write - - - VFEN - 1- enable trigger output when v flag set - 22 - 1 - read-write - - - WFEN - 1- enable trigger output when w flag set - 21 - 1 - read-write - - - - - READEN - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- load counters to their read registers when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- load counters to their read registers when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- load counters to their read registers when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFEN - 1- load counters to their read registers when u flag set - 23 - 1 - read-write - - - VFEN - 1- load counters to their read registers when v flag set - 22 - 1 - read-write - - - WFEN - 1- load counters to their read registers when w flag set - 21 - 1 - read-write - - - - - DMAEN - DMA enable register - 0x24 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- generate dma request when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- generate dma request when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- generate dma request when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFEN - 1- generate dma request when u flag set - 23 - 1 - read-write - - - VFEN - 1- generate dma request when v flag set - 22 - 1 - read-write - - - WFEN - 1- generate dma request when w flag set - 21 - 1 - read-write - - - - - SR - Status register - 0x28 - 32 - 0x00000000 - 0xFFE00000 - - - WDGF - watchdog count timeout flag - 31 - 1 - read-write - - - PHUPTF - phase update flag, will set when any of u, v, w signal toggle - 30 - 1 - read-write - - - PHPREF - phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - 29 - 1 - read-write - - - PHDLYF - phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UF - u flag, will set when u signal toggle - 23 - 1 - read-write - - - VF - v flag, will set when v signal toggle - 22 - 1 - read-write - - - WF - w flag, will set when w signal toggle - 21 - 1 - read-write - - - - - IRQEN - Interrupt request enable register - 0x2c - 32 - 0x00000000 - 0xFFE00000 - - - WDGIE - 1- generate interrupt request when wdg flag set - 31 - 1 - read-write - - - PHUPTIE - 1- generate interrupt request when phupt flag set - 30 - 1 - read-write - - - PHPREIE - 1- generate interrupt request when phpre flag set - 29 - 1 - read-write - - - PHDLYIE - 1- generate interrupt request when phdly flag set - 28 - 1 - read-write - - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - - - UFIE - 1- generate interrupt request when u flag set - 23 - 1 - read-write - - - VFIE - 1- generate interrupt request when v flag set - 22 - 1 - read-write - - - WFIE - 1- generate interrupt request when w flag set - 21 - 1 - read-write - - - - - COUNT_CURRENT_W - W counter - 0x30 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_CURRENT_V - V counter - 0x34 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_CURRENT_U - U counter - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_CURRENT_TMR - Timer counter - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_READ_W - W read register - 0x40 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_READ_V - V read register - 0x44 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_READ_U - U read register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_READ_TMR - Timer read register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP0_W - W snap register 0 - 0x50 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP0_V - V snap register 0 - 0x54 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP0_U - Usnap register 0 - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP0_TMR - Timer snap register 0 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP1_W - W snap register 1 - 0x60 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP1_V - V snap register 1 - 0x64 - 32 - 0x00000000 - 0xCFFFFFFF - - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP1_U - U snap register 1 - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - COUNT_SNAP1_TMR - Timer snap register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - HIS_U_HIS0 - history register 0 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - HIS_U_HIS1 - history register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - HIS_V_HIS0 - V histroy register 0 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - HIS_V_HIS1 - V histroy register 1 - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - HIS_W_HIS0 - W histroy register 0 - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - HIS_W_HIS1 - W histroy register 1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - - - HALL1 - HALL1 - HALL - 0xf0214000 - - - HALL2 - HALL2 - HALL - 0xf0224000 - - - HALL3 - HALL3 - HALL - 0xf0234000 - - - QEI0 - QEI0 - QEI - 0xf0208000 - - 0x0 - 0x80 - registers - - - - CR - Control register - 0x0 - 32 - 0x00000000 - 0x80077F3F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - HRSTSPD - 1- reset spdcnt when H assert - 18 - 1 - read-write - - - HRSTPH - 1- reset phcnt when H assert - 17 - 1 - read-write - - - HRSTZ - 1- reset zcnt when H assert - 16 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - RESERVED - 00-x1, phase_cnt will increase at each A posedge -01-x2, phase_cnt will increase at each A/B posedge -10-x4, phase_cnt will increase at each edge(A/B, pos/neg) - 2 - 2 - read-write - - - ENCTYP - 00-abz; 01-pd; 10-ud; 11-reserved - 0 - 2 - read-write - - - - - PHCFG - Phase configure register - 0x4 - 32 - 0x00000000 - 0x007FFFFF - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert - 21 - 1 - read-write - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 21 - read-write - - - - - WDGCFG - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - PHIDX - Phase index register - 0xc - 32 - 0x00000000 - 0x001FFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 21 - read-write - - - - - TRGOEN - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - - - READEN - Read event enable register - 0x14 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - - - ZCMP - Z comparator - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - PHCMP - Phase comparator - 0x1c - 32 - 0x00000000 - 0xE01FFFFF - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - PHCMP - phcnt position compare value - 0 - 21 - read-write - - - - - SPDCMP - Speed comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - DMAEN - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - - - SR - Status register - 0x28 - 32 - 0x00000000 - 0xF0000000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - - - IRQEN - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xF0000000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - - - COUNT_CURRENT_Z - Z counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_CURRENT_PH - Phase counter - 0x34 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_CURRENT_SPD - Speed counter - 0x38 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_CURRENT_TMR - Timer counter - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_READ_Z - Z counter - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_READ_PH - Phase counter - 0x44 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_READ_SPD - Speed counter - 0x48 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_READ_TMR - Timer counter - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP0_Z - Z snap register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_SNAP0_PH - Phase snap register - 0x54 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_SNAP0_SPD - Speed snap register - 0x58 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_SNAP0_TMR - Timer snap register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - COUNT_SNAP1_Z - Z snap register 1 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - COUNT_SNAP1_PH - Phase snap register 1 - 0x64 - 32 - 0x00000000 - 0xC61FFFFF - - - RESERVE - reversed - 31 - 1 - read-only - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - COUNT_SNAP1_SPD - Speed snap register 1 - 0x68 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - COUNT_SNAP1_TMR - Timer snap register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS0 - Speed history - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS1 - Speed history 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS2 - Speed history 2 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - SPDHIS_SPDHIS3 - Speed history 3 - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - - - QEI1 - QEI1 - QEI - 0xf0218000 - - - QEI2 - QEI2 - QEI - 0xf0228000 - - - QEI3 - QEI3 - QEI - 0xf0238000 - - - TRGM0 - TRGM0 - TRGM - 0xf020c000 - - 0x0 - 0x404 - registers - - - - FILTCFG_PWM_IN0 - Filter configure register - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN1 - Filter configure register - 0x4 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN2 - Filter configure register - 0x8 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN3 - Filter configure register - 0xc - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN4 - Filter configure register - 0x10 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN5 - Filter configure register - 0x14 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN6 - Filter configure register - 0x18 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_PWM_IN7 - Filter configure register - 0x1c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN0 - Filter configure register - 0x20 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN1 - Filter configure register - 0x24 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN2 - Filter configure register - 0x28 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN3 - Filter configure register - 0x2c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN4 - Filter configure register - 0x30 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN5 - Filter configure register - 0x34 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN6 - Filter configure register - 0x38 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN7 - Filter configure register - 0x3c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN8 - Filter configure register - 0x40 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN9 - Filter configure register - 0x44 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN10 - Filter configure register - 0x48 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - FILTCFG_TRGM_IN11 - Filter configure register - 0x4c - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - TRGOCFG_TRGM_OUT0 - Trigger manager output configure register - 0x100 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT1 - Trigger manager output configure register - 0x104 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT2 - Trigger manager output configure register - 0x108 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT3 - Trigger manager output configure register - 0x10c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT4 - Trigger manager output configure register - 0x110 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT5 - Trigger manager output configure register - 0x114 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT6 - Trigger manager output configure register - 0x118 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT7 - Trigger manager output configure register - 0x11c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT8 - Trigger manager output configure register - 0x120 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT9 - Trigger manager output configure register - 0x124 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT10 - Trigger manager output configure register - 0x128 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUT11 - Trigger manager output configure register - 0x12c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUTX0 - Trigger manager output configure register - 0x130 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_TRGM_OUTX1 - Trigger manager output configure register - 0x134 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_SYNCI - Trigger manager output configure register - 0x138 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FRCI - Trigger manager output configure register - 0x13c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FRCSYNCI - Trigger manager output configure register - 0x140 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_SHRLDSYNCI - Trigger manager output configure register - 0x144 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI0 - Trigger manager output configure register - 0x148 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI1 - Trigger manager output configure register - 0x14c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI2 - Trigger manager output configure register - 0x150 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_FAULTI3 - Trigger manager output configure register - 0x154 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN8 - Trigger manager output configure register - 0x158 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN9 - Trigger manager output configure register - 0x15c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN10 - Trigger manager output configure register - 0x160 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN11 - Trigger manager output configure register - 0x164 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN12 - Trigger manager output configure register - 0x168 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN13 - Trigger manager output configure register - 0x16c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN14 - Trigger manager output configure register - 0x170 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN15 - Trigger manager output configure register - 0x174 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN16 - Trigger manager output configure register - 0x178 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN17 - Trigger manager output configure register - 0x17c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN18 - Trigger manager output configure register - 0x180 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN19 - Trigger manager output configure register - 0x184 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN20 - Trigger manager output configure register - 0x188 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN21 - Trigger manager output configure register - 0x18c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN22 - Trigger manager output configure register - 0x190 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_PWM_IN23 - Trigger manager output configure register - 0x194 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_A - Trigger manager output configure register - 0x198 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_B - Trigger manager output configure register - 0x19c - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_Z - Trigger manager output configure register - 0x1a0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_H - Trigger manager output configure register - 0x1a4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_PAUSE - Trigger manager output configure register - 0x1a8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_QEI_SNAPI - Trigger manager output configure register - 0x1ac - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_U - Trigger manager output configure register - 0x1b0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_V - Trigger manager output configure register - 0x1b4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_W - Trigger manager output configure register - 0x1b8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_HALL_SNAPI - Trigger manager output configure register - 0x1bc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC0_STRGI - Trigger manager output configure register - 0x1c0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC1_STRGI - Trigger manager output configure register - 0x1c4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC2_STRGI - Trigger manager output configure register - 0x1c8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADC3_STRGI - Trigger manager output configure register - 0x1cc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADCX_PTRGI0A - Trigger manager output configure register - 0x1d0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADCX_PTRGI0B - Trigger manager output configure register - 0x1d4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_ADCX_PTRGI0C - Trigger manager output configure register - 0x1d8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRA_SYNCI - Trigger manager output configure register - 0x1dc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRA_IN2 - Trigger manager output configure register - 0x1e0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRA_IN3 - Trigger manager output configure register - 0x1e4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRB_SYNCI - Trigger manager output configure register - 0x1e8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRB_IN2 - Trigger manager output configure register - 0x1ec - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_GPTMRB_IN3 - Trigger manager output configure register - 0x1f0 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_CMPX_WIN - Trigger manager output configure register - 0x1f4 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_CAN_PTPC0_CAP - Trigger manager output configure register - 0x1f8 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - TRGOCFG_CAN_PTPC1_CAP - Trigger manager output configure register - 0x1fc - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - DMACFG_0 - DMA request configure register - 0x200 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - DMACFG_1 - DMA request configure register - 0x204 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - DMACFG_2 - DMA request configure register - 0x208 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - DMACFG_3 - DMA request configure register - 0x20c - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - GCR - General Control Register - 0x400 - 32 - 0x00000000 - 0x00000FFF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 12 - read-write - - - - - - - TRGM1 - TRGM1 - TRGM - 0xf021c000 - - - TRGM2 - TRGM2 - TRGM - 0xf022c000 - - - TRGM3 - TRGM3 - TRGM - 0xf023c000 - - - SYNT - SYNT - SYNT - 0xf0240000 - - 0x0 - 0x30 - registers - - - - GCR - Global control register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - RLD - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - CNT - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - CMP_0 - Comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - CMP_1 - Comparator - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - CMP_2 - Comparator - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - CMP_3 - Comparator - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - LCDC - LCDC - LCDC - 0xf1000000 - - 0x0 - 0x404 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SW_RST - Software reset, high active. When write 1 ,all internal logical will be reset. -0b - No action -1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. - 31 - 1 - read-write - - - DISP_ON - Display panel On/Off mode. -0b - Display Off. -1b - Display On. -Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. -So a good procedure to stop and turn on the display is: -1) clr VS_BLANK status -2) assert software reset -3) de-assert software reset -4) set display off -5) check VS_BLANK status until it is asserted, -6)reset the module, change settings -7) set display on - 30 - 1 - read-write - - - LINE_PATTERN - LCDIF line output order. -000b - RGB. -001b - RBG. -010b - GBR. -011b - GRB. -100b - BRG. -101b - BGR. - 27 - 3 - read-write - - - DISP_MODE - LCDIF operating mode. -00b - Normal mode. Panel content controlled by layer configuration. -01b - Test Mode1.(BGND Color Display) -10b - Test Mode2.(Column Color Bar) -11b - Test Mode3.(Row Color Bar) - 25 - 2 - read-write - - - BGDCL4CLR - background color for clear mode when the alpha channel is 0 - 24 - 1 - read-write - - - ARQOS - ARQOS for bus fabric arbitration - 20 - 4 - read-write - - - RSV - Reserved - 5 - 15 - read-write - - - INV_PXDATA - Indicates if value at the output (pixel data output) needs to be negated. -0b - Output is to remain same as the data inside memory -1b - Output to be negated from the data inside memory - 4 - 1 - read-write - - - INV_PXCLK - Polarity change of Pixel Clock. -0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge -1b - LCDC outputs data on the falling edge, Display samples data on the rising edge - 3 - 1 - read-write - - - INV_HREF - Polarity of HREF -0b - HREF signal active HIGH, indicating active pixel data -1b - HREF signal active LOW - 2 - 1 - read-write - - - INV_VSYNC - Polarity of VSYNC -0b - VSYNC signal active HIGH -1b - VSYNC signal active LOW - 1 - 1 - read-write - - - INV_HSYNC - Polarity of HSYNC -0b - HSYNC signal active HIGH -1b - HSYNC signal active LOW - 0 - 1 - read-write - - - - - BGND_CL - Background Color Register - 0x4 - 32 - 0x00000000 - 0x00FFFFFF - - - R - Red component of the default color displayed in the sectors where no layer is active. - 16 - 8 - read-write - - - G - Green component of the default color displayed in the sectors where no layer is active. - 8 - 8 - read-write - - - B - Blue component of the default color displayed in the sectors where no layer is active. - 0 - 8 - read-write - - - - - DISP_WN_SIZE - Display Window Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - Y - Sets the display size vertical resolution in pixels. - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - X - Sets the display size horizontal resolution in pixels. - 0 - 12 - read-write - - - - - HSYNC_PARA - HSYNC Config Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 31 - 1 - read-write - - - FP - HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC - 22 - 9 - read-write - - - RSV - Reserved - 20 - 2 - read-write - - - BP - HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC - 11 - 9 - read-write - - - RSV - Reserved - 9 - 2 - read-write - - - PW - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - VSYNC_PARA - VSYNC Config Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 31 - 1 - read-write - - - FP - VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC - 22 - 9 - read-write - - - RSV - Reserved - 20 - 2 - read-write - - - BP - VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC - 11 - 9 - read-write - - - RSV - Reserved - 9 - 2 - read-write - - - PW - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - DMA_ST - DMA Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFF00 - - - DMA_ERR - plane n axi error. W1C. - 24 - 8 - read-write - - - DMA1_DONE - Plane n frame 1 dma done. W1C. - 16 - 8 - read-write - - - DMA0_DONE - Plane n frame 0 dma done. W1C. - 8 - 8 - read-write - - - - - ST - Status Register - 0x18 - 32 - 0x00000000 - 0x0000000F - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - read-write - - - VS_BLANK - Asserted when in vertical blanking period. At the start of VSYNC - 2 - 1 - read-write - - - UNDERRUN - Asserted when the output buffer underrun condition encountered - 1 - 1 - read-write - - - VSYNC - Asserted when in vertical blanking period. At the end of VSYNC - 0 - 1 - read-write - - - - - INT_EN - Interrupt Enable Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - DMA_ERR - Interrupt enable for DMA error - 24 - 8 - read-write - - - DMA_DONE - Interrupt enable for DMA done - 16 - 8 - read-write - - - RSV - Interrupt enable for DMA underflow - 8 - 8 - read-write - - - RSV - Reserved - 4 - 4 - read-write - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - read-only - - - VS_BLANK - Interrupt enable for start of sof - 2 - 1 - read-write - - - UNDERRUN - Interrupt enable for underrun - 1 - 1 - read-write - - - VSYNC - Interrupt enable for end of sof - 0 - 1 - read-write - - - - - TXFIFO - TX FIFO Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 8 - 24 - read-write - - - THRSH - Threshold to start the lcd raster (0--0x7F) - 0 - 8 - read-write - - - - - LAYER_0_LAYCTRL - Layer Control Register - 0x200 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_0_ALPHAS - Layer Alpha Register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_0_LAYSIZE - Layer Size Register - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_0_LAYPOS - Layer Position Register - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_0_START0 - Layer Buffer Pointer Register - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_0_LINECFG - Layer Bus Config Register - 0x218 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_0_BG_CL - Layer Background Color Register - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_0_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x220 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_0_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x224 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_0_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x228 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - LAYER_1_LAYCTRL - Layer Control Register - 0x240 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_1_ALPHAS - Layer Alpha Register - 0x244 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_1_LAYSIZE - Layer Size Register - 0x248 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_1_LAYPOS - Layer Position Register - 0x24c - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_1_START0 - Layer Buffer Pointer Register - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_1_LINECFG - Layer Bus Config Register - 0x258 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_1_BG_CL - Layer Background Color Register - 0x25c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_1_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x260 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_1_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x264 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_1_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x268 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - LAYER_2_LAYCTRL - Layer Control Register - 0x280 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_2_ALPHAS - Layer Alpha Register - 0x284 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_2_LAYSIZE - Layer Size Register - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_2_LAYPOS - Layer Position Register - 0x28c - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_2_START0 - Layer Buffer Pointer Register - 0x290 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_2_LINECFG - Layer Bus Config Register - 0x298 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_2_BG_CL - Layer Background Color Register - 0x29c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_2_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x2a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_2_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x2a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_2_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x2a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - LAYER_3_LAYCTRL - Layer Control Register - 0x2c0 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_3_ALPHAS - Layer Alpha Register - 0x2c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_3_LAYSIZE - Layer Size Register - 0x2c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_3_LAYPOS - Layer Position Register - 0x2cc - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_3_START0 - Layer Buffer Pointer Register - 0x2d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_3_LINECFG - Layer Bus Config Register - 0x2d8 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_3_BG_CL - Layer Background Color Register - 0x2dc - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_3_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x2e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_3_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x2e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_3_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x2e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - LAYER_4_LAYCTRL - Layer Control Register - 0x300 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_4_ALPHAS - Layer Alpha Register - 0x304 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_4_LAYSIZE - Layer Size Register - 0x308 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_4_LAYPOS - Layer Position Register - 0x30c - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_4_START0 - Layer Buffer Pointer Register - 0x310 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_4_LINECFG - Layer Bus Config Register - 0x318 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_4_BG_CL - Layer Background Color Register - 0x31c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_4_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x320 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_4_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x324 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_4_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x328 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - LAYER_5_LAYCTRL - Layer Control Register - 0x340 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_5_ALPHAS - Layer Alpha Register - 0x344 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_5_LAYSIZE - Layer Size Register - 0x348 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_5_LAYPOS - Layer Position Register - 0x34c - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_5_START0 - Layer Buffer Pointer Register - 0x350 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_5_LINECFG - Layer Bus Config Register - 0x358 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_5_BG_CL - Layer Background Color Register - 0x35c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_5_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x360 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_5_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x364 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_5_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x368 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - LAYER_6_LAYCTRL - Layer Control Register - 0x380 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_6_ALPHAS - Layer Alpha Register - 0x384 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_6_LAYSIZE - Layer Size Register - 0x388 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_6_LAYPOS - Layer Position Register - 0x38c - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_6_START0 - Layer Buffer Pointer Register - 0x390 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_6_LINECFG - Layer Bus Config Register - 0x398 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_6_BG_CL - Layer Background Color Register - 0x39c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_6_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x3a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_6_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x3a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_6_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x3a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - LAYER_7_LAYCTRL - Layer Control Register - 0x3c0 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - LAYER_7_ALPHAS - Layer Alpha Register - 0x3c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 16 - 16 - read-write - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYER_7_LAYSIZE - Layer Size Register - 0x3c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 28 - 4 - read-write - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - RSV - Reserved - 12 - 4 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYER_7_LAYPOS - Layer Position Register - 0x3cc - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - LAYER_7_START0 - Layer Buffer Pointer Register - 0x3d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LAYER_7_LINECFG - Layer Bus Config Register - 0x3d8 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - RSV - Reserved - 16 - 5 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. - 0 - 16 - read-write - - - - - LAYER_7_BG_CL - Layer Background Color Register - 0x3dc - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - LAYER_7_CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x3e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - LAYER_7_CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x3e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - LAYER_7_CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x3e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - CLUT_LOAD - Clut Load Control Register - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 7 - 25 - read-write - - - SEL_NUM - Selected CLUT Number -The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. -. 3'h0 - PLANE 0 -. 3'h1 - PLANE 1 -. ------ -. 3'h7 - PLANE 7 -CLUT 8 can be modified via APB even when display is on. -Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. - 4 - 3 - read-write - - - RSV - Reserved - 1 - 3 - read-write - - - UPDATE_EN - CLUT Update Enable -The bit is written to 1 when software want to update the Color Look Up Tables during display. -If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. -If set to 0, software can update CLUT8 directly according to the CLUT memory map. -Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. - 0 - 1 - read-write - - - - - - - CAM0 - CAM0 - CAM - 0xf1008000 - - 0x0 - 0x490 - registers - - - - CR1 - Control Register - 0x0 - 32 - 0x00000000 - 0x3F9A8C7F - - - COLOR_EXT - If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. -The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. - 29 - 1 - read-write - - - INV_PIXCLK - invert pixclk pad input before it is used - 28 - 1 - read-write - - - INV_HSYNC - invert hsync pad input before it is used - 27 - 1 - read-write - - - INV_VSYNC - invert vsync pad input before it is used - 26 - 1 - read-write - - - SWAP16_EN - SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. -NOTE: Example of swapping enabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x 33441122 -NOTE: Example of swapping disabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x11223344 -0 Disable swapping -1 Enable swapping - 25 - 1 - read-write - - - PACK_DIR - Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. -0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. -1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. - 24 - 1 - read-write - - - RESTART_BUSPTR - force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer - 23 - 1 - read-write - - - ASYNC_RXFIFO_CLR - ASynchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO immediately. -It will be auto-cleared. - 20 - 1 - read-write - - - SYNC_RXFIFO_CLR - Synchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO on every SOF. - 19 - 1 - read-write - - - SOF_INT_POL - SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. -0 SOF interrupt is generated on SOF falling edge -1 SOF interrupt is generated on SOF rising edge - 17 - 1 - read-write - - - INV_DATA - Invert Data Input. This bit enables or disables internal inverters on the data lines. -0 CAM_D data lines are directly applied to internal circuitry -1 CAM_D data lines are inverted before applied to internal circuitry - 15 - 1 - read-write - - - STORAGE_MODE - 00: Normal Mode (one plane mode) -01: Two Plane Mode (Y, UV plane) -10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 -11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 - 10 - 2 - read-write - - - COLOR_FORMATS - input color formats: -0010b: 24bit: RGB888 -0100b: 16bit: RGB565 -0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) -YUV -YCrCb -Note: YUV420 is not supported. -1000b: 24bit: YUV444 - 3 - 4 - read-write - - - SENSOR_BIT_WIDTH - the bit width of the sensor -0: 8 bits -1: 10 bits -Others: Undefined - 0 - 3 - read-write - - - - - INT_EN - Interrupt Enable Register - 0x4 - 32 - 0x00000000 - 0x00003A4D - - - ERR_CL_BWID_CFG_INT_EN - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable - 13 - 1 - read-write - - - HIST_DONE_INT_EN - Enable hist done int - 12 - 1 - read-write - - - HRESP_ERR_EN - Hresponse Error Enable. This bit enables the hresponse error interrupt. -0 Disable hresponse error interrupt -1 Enable hresponse error interrupt - 11 - 1 - read-write - - - EOF_INT_EN - End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. -0 EOF interrupt is disabled. -1 EOF interrupt is generated when RX count value is reached. - 9 - 1 - read-write - - - RF_OR_INTEN - RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. -0 RxFIFO overrun interrupt is disabled -1 RxFIFO overrun interrupt is enabled - 6 - 1 - read-write - - - FB2_DMA_DONE_INTEN - Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA -transfer done. -0 Frame Buffer2 DMA Transfer Done interrupt disable -1 Frame Buffer2 DMA Transfer Done interrupt enable - 3 - 1 - read-write - - - FB1_DMA_DONE_INTEN - Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA -transfer done. -0 Frame Buffer1 DMA Transfer Done interrupt disable -1 Frame Buffer1 DMA Transfer Done interrupt enable - 2 - 1 - read-write - - - SOF_INT_EN - Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. -0 SOF interrupt disable -1 SOF interrupt enable - 0 - 1 - read-write - - - - - CR2 - Control 2 Register - 0x10 - 32 - 0x00000000 - 0xFFFF8E2F - - - FRMCNT_15_0 - Frame Counter. This is a 16-bit Frame Counter -(Wraps around automatically after reaching the maximum) - 16 - 16 - read-only - - - FRMCNT_RST - Frame Count Reset. Resets the Frame Counter. -0 Do not reset -1 Reset frame counter immediately - 15 - 1 - read-write - - - RXFF_LEVEL - RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. -000 4 Double words -001 8 Double words -010 16 Double words -011 24 Double words -100 32 Double words -101 48 Double words -110 64 Double words -111 96 Double words - 9 - 3 - read-write - - - DMA_REQ_EN_RFF - DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. -0 Disable the dma request -1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. - 5 - 1 - read-write - - - CLRBITFORMAT - Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. - 0 - 4 - read-write - - - - - STA - Status Register - 0x24 - 32 - 0x00000000 - 0x000C26C4 - - - ERR_CL_BWID_CFG - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found - 19 - 1 - read-write - - - HIST_DONE - hist cal done - 18 - 1 - read-write - - - RF_OR_INT - RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing -1) -0 RXFIFO has not overflowed. -1 RXFIFO has overflowed. - 13 - 1 - read-write - - - DMA_TSF_DONE_FB2 - DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 10 - 1 - read-write - - - DMA_TSF_DONE_FB1 - DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 9 - 1 - read-write - - - EOF_INT - End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) -0 EOF is not detected. -1 EOF is detected. - 7 - 1 - read-write - - - SOF_INT - Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) -0 SOF is not detected. -1 SOF is detected. - 6 - 1 - read-write - - - HRESP_ERR_INT - Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing -1) -0 No hresponse error. -1 Hresponse error is detected. - 2 - 1 - read-write - - - - - DMASA_FB1 - Pixel DMA Frame Buffer 1 Address - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - PTR - DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer1 - 2 - 30 - read-write - - - - - DMASA_FB2 - Pixel DMA Frame Buffer 2 Address - 0x34 - 32 - 0x00000000 - 0xFFFFFFFC - - - PTR - DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer2 - 2 - 30 - read-write - - - - - BUF_PARA - Buffer Parameters Register - 0x38 - 32 - 0x00000000 - 0x0000FFFF - - - LINEBSP_STRIDE - Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. -The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. - 0 - 16 - read-write - - - - - IDEAL_WN_SIZE - Ideal Image Size Register - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Image Height. Indicates how many active pixels in a column of the image from the sensor. - 16 - 16 - read-write - - - WIDTH - Image Width. Indicates how many active pixels in a line of the image from the sensor. -The number of bytes to be transfered is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. -As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. - 0 - 16 - read-write - - - - - CR18 - Control CR18 Register - 0x4c - 32 - 0x00000000 - 0x80000780 - - - CAM_ENABLE - CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. - 31 - 1 - read-write - - - AWQOS - AWQOS for bus fabric arbitration - 7 - 4 - read-write - - - - - DMASA_UV1 - Pixel UV DMA Frame Buffer 1 Address - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 1 - 2 - 30 - read-write - - - RSV - Reserved - 0 - 2 - read-write - - - - - DMASA_UV2 - Pixel UV DMA Frame Buffer 2 Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 2 - 2 - 30 - read-write - - - RSV - Reserved - 0 - 2 - read-write - - - - - CR20 - Control CR20 Register - 0x58 - 32 - 0x00000000 - 0xC00001FF - - - BINARY_EN - binary picture output enable - 31 - 1 - read-write - - - HISTOGRAM_EN - histogarm enable - 30 - 1 - read-write - - - BIG_END - Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. - 8 - 1 - read-write - - - THRESHOLD - Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. - 0 - 8 - read-write - - - - - MAX_WN_CYCLE - Max Window Size Register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - ROW - Max Width-1 - 16 - 16 - read-write - - - COL - Max Height-1 - 0 - 16 - read-write - - - - - CSC_COEF0 - Color Space Conversion Config Register 0 - 0x70 - 32 - 0x00000000 - 0xDFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Color Space Conversion Config Register 1 - 0x74 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Color Space Conversion Config Register 2 - 0x78 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - CLRKEY_LOW - Low Color Key Register - 0x7c - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - High Color Key Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - HISTOGRAM_FIFO_DATA0 - Histogram Registers - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA1 - Histogram Registers - 0x94 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA2 - Histogram Registers - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA3 - Histogram Registers - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA4 - Histogram Registers - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA5 - Histogram Registers - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA6 - Histogram Registers - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA7 - Histogram Registers - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA8 - Histogram Registers - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA9 - Histogram Registers - 0xb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA10 - Histogram Registers - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA11 - Histogram Registers - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA12 - Histogram Registers - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA13 - Histogram Registers - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA14 - Histogram Registers - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA15 - Histogram Registers - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA16 - Histogram Registers - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA17 - Histogram Registers - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA18 - Histogram Registers - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA19 - Histogram Registers - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA20 - Histogram Registers - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA21 - Histogram Registers - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA22 - Histogram Registers - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA23 - Histogram Registers - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA24 - Histogram Registers - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA25 - Histogram Registers - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA26 - Histogram Registers - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA27 - Histogram Registers - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA28 - Histogram Registers - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA29 - Histogram Registers - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA30 - Histogram Registers - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA31 - Histogram Registers - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA32 - Histogram Registers - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA33 - Histogram Registers - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA34 - Histogram Registers - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA35 - Histogram Registers - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA36 - Histogram Registers - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA37 - Histogram Registers - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA38 - Histogram Registers - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA39 - Histogram Registers - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA40 - Histogram Registers - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA41 - Histogram Registers - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA42 - Histogram Registers - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA43 - Histogram Registers - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA44 - Histogram Registers - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA45 - Histogram Registers - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA46 - Histogram Registers - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA47 - Histogram Registers - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA48 - Histogram Registers - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA49 - Histogram Registers - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA50 - Histogram Registers - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA51 - Histogram Registers - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA52 - Histogram Registers - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA53 - Histogram Registers - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA54 - Histogram Registers - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA55 - Histogram Registers - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA56 - Histogram Registers - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA57 - Histogram Registers - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA58 - Histogram Registers - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA59 - Histogram Registers - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA60 - Histogram Registers - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA61 - Histogram Registers - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA62 - Histogram Registers - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA63 - Histogram Registers - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA64 - Histogram Registers - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA65 - Histogram Registers - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA66 - Histogram Registers - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA67 - Histogram Registers - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA68 - Histogram Registers - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA69 - Histogram Registers - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA70 - Histogram Registers - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA71 - Histogram Registers - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA72 - Histogram Registers - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA73 - Histogram Registers - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA74 - Histogram Registers - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA75 - Histogram Registers - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA76 - Histogram Registers - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA77 - Histogram Registers - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA78 - Histogram Registers - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA79 - Histogram Registers - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA80 - Histogram Registers - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA81 - Histogram Registers - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA82 - Histogram Registers - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA83 - Histogram Registers - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA84 - Histogram Registers - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA85 - Histogram Registers - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA86 - Histogram Registers - 0x1e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA87 - Histogram Registers - 0x1ec - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA88 - Histogram Registers - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA89 - Histogram Registers - 0x1f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA90 - Histogram Registers - 0x1f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA91 - Histogram Registers - 0x1fc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA92 - Histogram Registers - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA93 - Histogram Registers - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA94 - Histogram Registers - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA95 - Histogram Registers - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA96 - Histogram Registers - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA97 - Histogram Registers - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA98 - Histogram Registers - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA99 - Histogram Registers - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA100 - Histogram Registers - 0x220 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA101 - Histogram Registers - 0x224 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA102 - Histogram Registers - 0x228 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA103 - Histogram Registers - 0x22c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA104 - Histogram Registers - 0x230 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA105 - Histogram Registers - 0x234 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA106 - Histogram Registers - 0x238 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA107 - Histogram Registers - 0x23c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA108 - Histogram Registers - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA109 - Histogram Registers - 0x244 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA110 - Histogram Registers - 0x248 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA111 - Histogram Registers - 0x24c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA112 - Histogram Registers - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA113 - Histogram Registers - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA114 - Histogram Registers - 0x258 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA115 - Histogram Registers - 0x25c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA116 - Histogram Registers - 0x260 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA117 - Histogram Registers - 0x264 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA118 - Histogram Registers - 0x268 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA119 - Histogram Registers - 0x26c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA120 - Histogram Registers - 0x270 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA121 - Histogram Registers - 0x274 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA122 - Histogram Registers - 0x278 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA123 - Histogram Registers - 0x27c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA124 - Histogram Registers - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA125 - Histogram Registers - 0x284 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA126 - Histogram Registers - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA127 - Histogram Registers - 0x28c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA128 - Histogram Registers - 0x290 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA129 - Histogram Registers - 0x294 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA130 - Histogram Registers - 0x298 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA131 - Histogram Registers - 0x29c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA132 - Histogram Registers - 0x2a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA133 - Histogram Registers - 0x2a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA134 - Histogram Registers - 0x2a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA135 - Histogram Registers - 0x2ac - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA136 - Histogram Registers - 0x2b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA137 - Histogram Registers - 0x2b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA138 - Histogram Registers - 0x2b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA139 - Histogram Registers - 0x2bc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA140 - Histogram Registers - 0x2c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA141 - Histogram Registers - 0x2c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA142 - Histogram Registers - 0x2c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA143 - Histogram Registers - 0x2cc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA144 - Histogram Registers - 0x2d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA145 - Histogram Registers - 0x2d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA146 - Histogram Registers - 0x2d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA147 - Histogram Registers - 0x2dc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA148 - Histogram Registers - 0x2e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA149 - Histogram Registers - 0x2e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA150 - Histogram Registers - 0x2e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA151 - Histogram Registers - 0x2ec - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA152 - Histogram Registers - 0x2f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA153 - Histogram Registers - 0x2f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA154 - Histogram Registers - 0x2f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA155 - Histogram Registers - 0x2fc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA156 - Histogram Registers - 0x300 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA157 - Histogram Registers - 0x304 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA158 - Histogram Registers - 0x308 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA159 - Histogram Registers - 0x30c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA160 - Histogram Registers - 0x310 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA161 - Histogram Registers - 0x314 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA162 - Histogram Registers - 0x318 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA163 - Histogram Registers - 0x31c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA164 - Histogram Registers - 0x320 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA165 - Histogram Registers - 0x324 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA166 - Histogram Registers - 0x328 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA167 - Histogram Registers - 0x32c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA168 - Histogram Registers - 0x330 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA169 - Histogram Registers - 0x334 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA170 - Histogram Registers - 0x338 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA171 - Histogram Registers - 0x33c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA172 - Histogram Registers - 0x340 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA173 - Histogram Registers - 0x344 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA174 - Histogram Registers - 0x348 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA175 - Histogram Registers - 0x34c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA176 - Histogram Registers - 0x350 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA177 - Histogram Registers - 0x354 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA178 - Histogram Registers - 0x358 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA179 - Histogram Registers - 0x35c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA180 - Histogram Registers - 0x360 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA181 - Histogram Registers - 0x364 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA182 - Histogram Registers - 0x368 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA183 - Histogram Registers - 0x36c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA184 - Histogram Registers - 0x370 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA185 - Histogram Registers - 0x374 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA186 - Histogram Registers - 0x378 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA187 - Histogram Registers - 0x37c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA188 - Histogram Registers - 0x380 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA189 - Histogram Registers - 0x384 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA190 - Histogram Registers - 0x388 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA191 - Histogram Registers - 0x38c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA192 - Histogram Registers - 0x390 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA193 - Histogram Registers - 0x394 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA194 - Histogram Registers - 0x398 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA195 - Histogram Registers - 0x39c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA196 - Histogram Registers - 0x3a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA197 - Histogram Registers - 0x3a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA198 - Histogram Registers - 0x3a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA199 - Histogram Registers - 0x3ac - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA200 - Histogram Registers - 0x3b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA201 - Histogram Registers - 0x3b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA202 - Histogram Registers - 0x3b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA203 - Histogram Registers - 0x3bc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA204 - Histogram Registers - 0x3c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA205 - Histogram Registers - 0x3c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA206 - Histogram Registers - 0x3c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA207 - Histogram Registers - 0x3cc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA208 - Histogram Registers - 0x3d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA209 - Histogram Registers - 0x3d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA210 - Histogram Registers - 0x3d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA211 - Histogram Registers - 0x3dc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA212 - Histogram Registers - 0x3e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA213 - Histogram Registers - 0x3e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA214 - Histogram Registers - 0x3e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA215 - Histogram Registers - 0x3ec - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA216 - Histogram Registers - 0x3f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA217 - Histogram Registers - 0x3f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA218 - Histogram Registers - 0x3f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA219 - Histogram Registers - 0x3fc - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA220 - Histogram Registers - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA221 - Histogram Registers - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA222 - Histogram Registers - 0x408 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA223 - Histogram Registers - 0x40c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA224 - Histogram Registers - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA225 - Histogram Registers - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA226 - Histogram Registers - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA227 - Histogram Registers - 0x41c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA228 - Histogram Registers - 0x420 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA229 - Histogram Registers - 0x424 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA230 - Histogram Registers - 0x428 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA231 - Histogram Registers - 0x42c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA232 - Histogram Registers - 0x430 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA233 - Histogram Registers - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA234 - Histogram Registers - 0x438 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA235 - Histogram Registers - 0x43c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA236 - Histogram Registers - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA237 - Histogram Registers - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA238 - Histogram Registers - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA239 - Histogram Registers - 0x44c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA240 - Histogram Registers - 0x450 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA241 - Histogram Registers - 0x454 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA242 - Histogram Registers - 0x458 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA243 - Histogram Registers - 0x45c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA244 - Histogram Registers - 0x460 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA245 - Histogram Registers - 0x464 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA246 - Histogram Registers - 0x468 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA247 - Histogram Registers - 0x46c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA248 - Histogram Registers - 0x470 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA249 - Histogram Registers - 0x474 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA250 - Histogram Registers - 0x478 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA251 - Histogram Registers - 0x47c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA252 - Histogram Registers - 0x480 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA253 - Histogram Registers - 0x484 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA254 - Histogram Registers - 0x488 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - HISTOGRAM_FIFO_DATA255 - Histogram Registers - 0x48c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - reserved - 24 - 8 - read-only - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - - - CAM1 - CAM1 - CAM - 0xf100c000 - - - PDMA - PDMA - PDMA - 0xf1010000 - - 0x0 - 0xc0 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 23 - 9 - read-write - - - ARQOS - QoS for AXI read bus - 19 - 4 - read-write - - - AWQOS - QoS for AXI write bus - 15 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 13 - 2 - read-write - - - AXIERR_IRQ_EN - Enable interrupt of AXI bus error - 12 - 1 - read-write - - - PDMA_DONE_IRQ_EN - Enable interrupt of PDMA_DONE - 11 - 1 - read-write - - - RSV - Asserted to re-shadow the registers to enable on-the-fly new display pattern generation. Auto clear to zero. - 10 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - RSV - Enable handshake with LCD0 controller. When this is set, the PDMA will not process an entire framebuffer, but will instead process rows of NxN blocks in a double-buffer handshake with the LCDIF. This enables the use of the onboard SRAM for a partial frame buffer. - 8 - 1 - read-write - - - RSV - Enable the next irq interrupt - 7 - 1 - read-write - - - IRQ_EN - Enable normal interrupt - 6 - 1 - read-write - - - BS16 - Asserted when the Block Size is 16x16, else 8x8 - 5 - 1 - read-write - - - P1_EN - Plane 1 Enable - 4 - 1 - read-write - - - P0_EN - Plane 0 Enable - 3 - 1 - read-write - - - RSV - Asserted to use repeat mode - 2 - 1 - read-write - - - PDMA_SFTRST - Software Reset. -Write 1 to clear PDMA internal logic. -Write 0 to exit software reset mode. - 1 - 1 - read-write - - - PDMA_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKY - Y block that is processing - 24 - 8 - read-only - - - BLOCKX - X block that is processing - 16 - 8 - read-only - - - RSV - Reserved - 10 - 6 - read-only - - - PDMA_DONE - PDMA one image done - 9 - 1 - read-only - - - AXI_ERR_ID - AXI error ID - 5 - 4 - read-only - - - AXI_0_WRITE_ERR - AXI0 write err - 4 - 1 - read-write - - - AXI_1_READ_ERR - AXI1 read err - 3 - 1 - read-write - - - AXI_0_READ_ERR - AXI0 read err - 2 - 1 - read-write - - - RSV - Asserted to indicate NEXT_CMD event triggering IRQ - 1 - 1 - read-write - - - IRQ - Asserted to indicate a IRQ event - 0 - 1 - read-write - - - - - OUT_CTRL - Out Layer Control Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTALPHA - The destination (P1) system ALPHA value. - 24 - 8 - read-write - - - SRCALPHA - The source (P0) system ALPHA value. - 16 - 8 - read-write - - - DSTALPHA_OP - The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) -2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 14 - 2 - read-write - - - SRCALPHA_OP - The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) -2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 12 - 2 - read-write - - - ABLEND_MODE - Alpha Blending Mode -0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional belding mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 8 - 4 - read-write - - - RSV - Not suppoted yet - 6 - 2 - read-write - - - FORMAT - Output buffer format. -0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) - 0 - 6 - read-write - - - - - OUT_BUF - Output buffer address - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. - 0 - 32 - read-write - - - - - OUT_PITCH - Outlayer Pitch Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - OUT_LRC - Output Lower Right Corner Register - 0x18 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. -The value is the height of the output image size. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. -Should be the width of the output image size. - 0 - 14 - read-write - - - - - OUT_PS_0_ULC - Layer Upper Left Corner Register - 0x1c - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - OUT_PS_0_LRC - Layer Lower Right Corner Register - 0x20 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - OUT_PS_1_ULC - Layer Upper Left Corner Register - 0x24 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - OUT_PS_1_LRC - Layer Lower Right Corner Register - 0x28 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - PS_0_CTRL - Layer Control Register - 0x30 - 32 - 0x00000000 - 0x001FFFFF - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack_dir operation. - 20 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 18 - 2 - read-write - - - BKGCL4CLR - Enable to use background color for clear area - 17 - 1 - read-write - - - YCBCR_MODE - YCbCr mode or YUV mode - 16 - 1 - read-write - - - BYPASS - Asserted to bypass the CSC stage - 15 - 1 - read-write - - - VFLIP - Indicates that the input should be flipped vertically (effect applied before rotation). - 14 - 1 - read-write - - - HFLIP - Indicates that the input should be flipped horizontally (effect applied before rotation). - 13 - 1 - read-write - - - ROTATE - Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring -after the FLIP_X and FLIP_Y permutation. -0x0 ROT_0 -0x1 ROT_90 -0x2 ROT_180 -0x3 ROT_270 - 11 - 2 - read-write - - - DECY - Verticle pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECY2 - Decimate PS by 2. -0x2 DECY4 - Decimate PS by 4. -0x3 DECY8 - Decimate PS by 8. - 9 - 2 - read-write - - - DECX - Horizontal pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECX2 - Decimate PS by 2. -0x2 DECX4 - Decimate PS by 4. -0x3 DECX8 - Decimate PS by 8. - 7 - 2 - read-write - - - HW_BYTE_SWAP - Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - 6 - 1 - read-write - - - FORMAT - PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. -0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - 0 - 6 - read-write - - - - - PS_0_BUF - Layer data buffer address - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Address pointer for the PS RGB or Y (luma) input buffer. - 0 - 32 - read-write - - - - - PS_0_PITCH - Layer data pitch register - 0x40 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - PS_0_BKGD - Layer background color register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - COLOR - Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - 0 - 32 - read-write - - - - - PS_0_SCALE - Layer scale register - 0x48 - 32 - 0x00000000 - 0x7FFF7FFF - - - Y - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 16 - 15 - read-write - - - X - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 0 - 15 - read-write - - - - - PS_0_OFFSET - Layer offset register - 0x4c - 32 - 0x00000000 - 0x0FFF0FFF - - - Y - This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 16 - 12 - read-write - - - X - This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 0 - 12 - read-write - - - - - PS_0_CLRKEY_LOW - Layer low color key register - 0x50 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - PS_0_CLRKEY_HIGH - Layer high color key register - 0x54 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - 0 - 24 - read-write - - - - - PS_0_ORG - Layer original size register - 0x58 - 32 - 0x00000000 - 0x3FFF3FFF - - - HIGHT - The number of vertical pixels of the original frame (not -1) - 16 - 14 - read-write - - - WIDTH - The number of horizontal pixels of the original frame (not -1) - 0 - 14 - read-write - - - - - PS_1_CTRL - layer control register - 0x60 - 32 - 0x00000000 - 0x001FFFFF - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack_dir operation. - 20 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 18 - 2 - read-write - - - BKGCL4CLR - Enable to use background color for clear area - 17 - 1 - read-write - - - YCBCR_MODE - YCbCr mode or YUV mode - 16 - 1 - read-write - - - BYPASS - Asserted to bypass the CSC stage - 15 - 1 - read-write - - - VFLIP - Indicates that the input should be flipped vertically (effect applied before rotation). - 14 - 1 - read-write - - - HFLIP - Indicates that the input should be flipped horizontally (effect applied before rotation). - 13 - 1 - read-write - - - ROTATE - Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring -after the FLIP_X and FLIP_Y permutation. -0x0 ROT_0 -0x1 ROT_90 -0x2 ROT_180 -0x3 ROT_270 - 11 - 2 - read-write - - - DECY - Verticle pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECY2 - Decimate PS by 2. -0x2 DECY4 - Decimate PS by 4. -0x3 DECY8 - Decimate PS by 8. - 9 - 2 - read-write - - - DECX - Horizontal pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECX2 - Decimate PS by 2. -0x2 DECX4 - Decimate PS by 4. -0x3 DECX8 - Decimate PS by 8. - 7 - 2 - read-write - - - HW_BYTE_SWAP - Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - 6 - 1 - read-write - - - FORMAT - PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. -0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - 0 - 6 - read-write - - - - - PS_1_BUF - Layer data buffer address - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Address pointer for the PS RGB or Y (luma) input buffer. - 0 - 32 - read-write - - - - - PS_1_PITCH - Layer data pitch register - 0x70 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - PS_1_BKGD - Layer background color register - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - COLOR - Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - 0 - 32 - read-write - - - - - PS_1_SCALE - Layer scale register - 0x78 - 32 - 0x00000000 - 0x7FFF7FFF - - - Y - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 16 - 15 - read-write - - - X - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 0 - 15 - read-write - - - - - PS_1_OFFSET - Layer offset register - 0x7c - 32 - 0x00000000 - 0x0FFF0FFF - - - Y - This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 16 - 12 - read-write - - - X - This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 0 - 12 - read-write - - - - - PS_1_CLRKEY_LOW - Layer low color key register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - PS_1_CLRKEY_HIGH - Layer high color key register - 0x84 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - 0 - 24 - read-write - - - - - PS_1_ORG - Layer original size register - 0x88 - 32 - 0x00000000 - 0x3FFF3FFF - - - HIGHT - The number of vertical pixels of the original frame (not -1) - 16 - 14 - read-write - - - WIDTH - The number of horizontal pixels of the original frame (not -1) - 0 - 14 - read-write - - - - - YUV2RGB_COEF0 - YUV2RGB coefficients register 0 - 0xa0 - 32 - 0x00000000 - 0x1FFFFFFF - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - YUV2RGB_COEF1 - YUV2RGB coefficients register 1 - 0xa4 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - YUV2RGB_COEF2 - YUV2RGB coefficients register 2 - 0xa8 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients register 0 - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YUV CSC stage - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients register 1 - 0xb0 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients register 2 - 0xb4 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients register 3 - 0xb8 - 32 - 0x00000000 - 0x07FF07FF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients register 4 - 0xbc - 32 - 0x00000000 - 0x07FF07FF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - - - JPEG - JPEG - JPEG - 0xf1014000 - - 0x0 - 0xa0 - registers - - - - INDMA_MISC - In DMA Misc Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFC - - - RSV - Reserved - 23 - 9 - read-write - - - ARQOS - QoS for AXI read channel - 19 - 4 - read-write - - - MAX_OT - max_ot when input are RGB pixels. -For 16 bits per pixel, it can be set as 4. -For 32 bits per pixel, it will be set as 2. - 15 - 4 - read-write - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. - 14 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - INDMA_RENEW - Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. - 11 - 1 - read-write - - - NXT_IRQ_EN - In DMA Next Interrupt Enable - 10 - 1 - read-write - - - IN_DMA_DONE_IRQ_EN - In DMA Done enable - 9 - 1 - read-write - - - AXI_ERR_IRQ_EN - In DMA axi bus error inetrrupt enable - 8 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of In DMA module - 7 - 1 - read-write - - - IN_DMA_ID - 0: Pixel (In) -1: ECS (In) -2: Qmem -3: HuffEnc -4: HuffMin -5: HuffBase -6: HuffSymb - 4 - 3 - read-write - - - IN_DMA_REQ - Asserted to request DMA. Automatically clear after DMA is done. - 3 - 1 - read-write - - - INDMA2D - Asserted if In_DMA_ID=Pixel. - 2 - 1 - read-write - - - - - INDMABASE - In DMA Buf Address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - INDMA_CTRL0 - In DMA Buf Control 0 Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. - 0 - 16 - read-write - - - - - INDMA_CTRL1 - In DMA Buf Control 1 Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - INXT_CMD - In DMA Next Command Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - OUTDMA_MISC - Out DMA Misc Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFC - - - RSV - Reserved - 18 - 14 - read-write - - - AWQOS - No description avaiable - 14 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. -2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - EN_OUTCNT - Enable output counter (unit as bytes) - 11 - 1 - read-write - - - INI_OUTCNT - Asserted to ini output counter - 10 - 1 - read-write - - - ADD_ODMA_ENDINGS - Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. - 9 - 1 - read-write - - - NXT_IRQ_EN - Out DMA Next Interrupt Enable - 8 - 1 - read-write - - - OUT_DMA_DONE_IRQ_EN - Out DMA Done interrupt Enable - 7 - 1 - read-write - - - AXI_ERR_IRQ_EN - Out DMA axi bus error inetrrupt enable - 6 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of Out DMA module - 5 - 1 - read-write - - - OUT_DMA_ID - 0: Pixel (Out) -1: ECS (Out) - 4 - 1 - read-write - - - OUT_DMA_REQ - Asserted to enable Out DMA request - 3 - 1 - read-write - - - OUTDMA2D - Asserted if Out_DMA_ID==Pixel - 2 - 1 - read-write - - - - - OUTDMABASE - Out DMA Buf Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - OUTDMA_CTRL0 - Out DMA Buf Control 0 Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows when Out_DMA_ID==Pixel - 0 - 16 - read-write - - - - - OUTDMA_CTRL1 - Out DMA Buf Control 1 Register - 0x30 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - ONXT_CMD - Out DMA Next Command Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - CFG - Configuration Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 23 - 9 - read-write - - - JD_UVSWAP - Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. - 22 - 1 - read-write - - - CFG_IPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as B,R -2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 - 20 - 2 - read-write - - - CODEC_OVER_IRQ_EN - The jpg endec process done interrupt enable - 19 - 1 - read-write - - - CODEC_RESTART_ERR_IRQ_EN - The jpg endec restart error interrupt enable - 18 - 1 - read-write - - - MEM_DEBUG_CLK_SEL - asserted to use APB clock, so that the memory contents could be read out through APB interface - 17 - 1 - read-write - - - RSV - memory power down - 16 - 1 - read-write - - - RSV - No description avaiable - 10 - 6 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - CFG_OPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as R,B -2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 - 7 - 2 - read-write - - - JDATA_FORMAT - 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU -3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU -3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU -3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU -3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU -Others: Undefined - 4 - 3 - read-write - - - JPEG_SFTRST - Software Reset - 3 - 1 - read-write - - - START - Asserted if to start a new encoder/decoder conversion. -It will at first stop the inner JPEG module, then reset it, and then re-run it. -It is a different mode from DMA phase mode. -It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. -Auto clear. - 2 - 1 - read-write - - - MODE - 1: decoder, 0:encoder - 1 - 1 - read-write - - - JPEG_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x44 - 32 - 0x00000000 - 0xFFFFBFFE - - - BUSY - When 1 means that the module is busy doing conversion and data transfer. - 31 - 1 - read-only - - - RSV - Reserved - 15 - 16 - read-only - - - AXI_ERR_ID - the axi err id - 10 - 4 - read-only - - - AXI_READ_ERR - in-dma axi bus error - 9 - 1 - read-only - - - AXI_WRITE_ERR - out-dma axi bus error - 8 - 1 - read-only - - - AXI_ERR - axi bus error - 7 - 1 - read-write - - - ONXT_IRQ - OutDMA next interrupt - 6 - 1 - read-write - - - INXT_IRQ - InDMA next interrupt - 5 - 1 - read-write - - - OUT_DMA_TRANSFER_DONE - OutDMA process done - 4 - 1 - read-write - - - IN_DMA_TRANSFER_DONE - InDMA process done - 3 - 1 - read-write - - - CODEC_OVER - Coding or decoding process is over. DMA is not included. -The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. - 2 - 1 - read-write - - - RESTART_MARKER_ERROR - codec restart marker error interrupt - 1 - 1 - read-write - - - - - WIDTH - Image width register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 16 - 16 - read-write - - - IMG - Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - HEIGHT - Image height register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 16 - 16 - read-write - - - IMG - Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - BUFADDR - Buf Access Addr - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - ADDR[31:28] denotes the buffer type: -0x2: Qmem -0x3: HuffEnc -0x4: HuffMin -0x5: HuffBase -0x6: HuffSymb -ADDR[27:0] is the address inside the buffer - 0 - 32 - read-write - - - - - BUFDATA - Buf Access Data - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer. -The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. - 0 - 32 - read-write - - - - - OUTDMACNT - Out DMA Bytes Counter - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The out DMA counter - 0 - 32 - read-only - - - - - CSC_COEF0 - YUV2RGB coefficients Register 0 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit. -0b - The CSC is bypassed -1b - The CSC is enabled - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - YUV2RGB coefficients Register 1 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - YUV2RGB coefficients Register 2 - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients Register 0 - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode. Must be assigned as 1. - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YCbCr CSC stage - 30 - 1 - read-write - - - RSV - Reserved - 29 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients Register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients Register 2 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients Register 3 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients Register 4 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - Reserved - 27 - 5 - read-write - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - RSV - Reserved - 11 - 5 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - IMGREG1 - Image Control Register 1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFF7 - - - RSV - No description avaiable - 4 - 28 - read-write - - - RE - Encoder Use only. -Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs - 2 - 1 - read-write - - - NCOL - Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 - 0 - 2 - read-write - - - - - IMGREG2 - Image Control Register 2 - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 26 - 6 - read-write - - - NMCU - Encoder Use only. -The number of NMCU to be generated in encoder mode - 0 - 26 - read-write - - - - - IMGREG3 - Image Control Register 3 - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 16 - 16 - read-write - - - NRST - Encoder use only. -It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. - 0 - 16 - read-write - - - - - IMGREG_REG40 - Image Control Register 40 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 8 - 24 - read-write - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - IMGREG_REG41 - Image Control Register 41 - 0x94 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 8 - 24 - read-write - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - IMGREG_REG42 - Image Control Register 42 - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 8 - 24 - read-write - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - IMGREG_REG43 - Image Control Register 43 - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - RSV - No description avaiable - 8 - 24 - read-write - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - - - ENET0 - ENET0 - ENET - 0xf2000000 - - 0x0 - 0x3028 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configuration. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - VERSION - Version Register - 0x20 - 32 - 0x00000000 - 0x0000FFFF - - - USERVER - User-defined Version - 8 - 8 - read-only - - - SNPSVER - Synopsys-defined Version (3.7) - 0 - 8 - read-only - - - - - DEBUGGING - Debug Register - 0x24 - 32 - 0x00000000 - 0x037F0377 - - - TXSTSFSTS - MTL TxStatus FIFO Full Status - When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. - 25 - 1 - read-only - - - TXFSTS - MTL Tx FIFO Not Empty Status -When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. - 24 - 1 - read-only - - - TWCSTS - MTL Tx FIFO Write Controller Status -When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. - 22 - 1 - read-only - - - TRCSTS - MTL Tx FIFO Read Controller Status -This field indicates the state of the Tx FIFO Read Controller: -- 00: IDLE state -- 01: READ state (transferring data to the MAC transmitter) -- 10: Waiting for TxStatus from the MAC transmitter -- 11: Writing the received TxStatus or flushing the Tx FIFO - 20 - 2 - read-only - - - TXPAUSED - MAC Transmitter in Pause -When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. - 19 - 1 - read-only - - - TFCSTS - MAC Transmit Frame Controller Status -This field indicates the state of the MAC Transmit Frame Controller module: -- 00: IDLE state -- 01: Waiting for status of previous frame or IFG or backoff period to be over -- 10: Generating and transmitting a Pause frame (in the full-duplex mode) -- 11: Transferring input frame for transmission - 17 - 2 - read-only - - - TPESTS - MAC GMII or MII Transmit Protocol Engine Status - When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. - 16 - 1 - read-only - - - RXFSTS - MTL RxFIFO Fill-Level Status -This field gives the status of the fill-level of the Rx FIFO: -- 00: Rx FIFO Empty -- 01: Rx FIFO fill-level below flow-control deactivate threshold -- 10: Rx FIFO fill-level above flow-control activate threshold -- 11: Rx FIFO Full - 8 - 2 - read-only - - - RRCSTS - MTL RxFIFO Read Controller State -This field gives the state of the Rx FIFO read Controller: -- 00: IDLE state -- 01: Reading frame data -- 10: Reading frame status (or timestamp) -- 11: Flushing the frame data and status - 5 - 2 - read-only - - - RWCSTS - MTL Rx FIFO Write Controller Active Status - When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. - 4 - 1 - read-only - - - RFCFCSTS - MAC Receive Frame FIFO Controller Status - When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. - 1 - 2 - read-only - - - RPESTS - MAC GMII or MII Receive Protocol Engine Status -When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. - 0 - 1 - read-only - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Regsiter - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is always set to 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - MAC_ADDR_1_HIGH - MAC Address High Register - 0x48 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_1_LOW - MAC Address Low Register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - MAC_ADDR_2_HIGH - MAC Address2 High Register - 0x50 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_2_LOW - MAC Address2 Low Register - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - MAC_ADDR_3_HIGH - MAC Address3 High Register - 0x58 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_3_LOW - MAC Address3 Low Register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - MAC_ADDR_4_HIGH - MAC Address4 High Register - 0x60 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - MAC_ADDR_4_LOW - MAC Address4 Low Register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0001003F - - - SMIDRXS - Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). - 16 - 1 - read-only - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - GPIO - General Purpose IO Register - 0xe0 - 32 - 0x00000000 - 0x0F0F0F0F - - - GPIT - No description avaiable - 24 - 4 - read-write - - - GPIE - No description avaiable - 16 - 4 - read-write - - - GPO - No description avaiable - 8 - 4 - read-write - - - GPIS - No description avaiable - 0 - 4 - read-write - - - - - MMC_CNTRL - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - MMC_INTR_RX - MMC Receive Interrupt maintains the interrupt generated from all -of the receive statistic counters. - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - MMC_INTR_TX - MMC Transmit Interrupt maintains the interrupt generated from all -of the transmit statistic counters - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - MMC_INTR_MASK_RX - MMC Receive Interrupt mask maintains the mask for the interrupt -generated from all of the receive statistic counters - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - MMC_INTR_MASK_TX - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - TXOCTETCOUNT_GB - Number of bytes transmitted, exclusive of preamble and retried -bytes, in good and bad frames. - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. - 0 - 32 - read-write - - - - - TXFRAMECOUNT_GB - Number of good and bad frames transmitted, exclusive of retried -frames. - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted, exclusive of retried frames. - 0 - 32 - read-write - - - - - TXBROADCASTFRAMES_G - Number of good broadcast frames transmitted - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good broadcast frames transmitted. - 0 - 32 - read-write - - - - - TXMLTICASTFRAMES_G - Number of good multicast frames transmitted - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good multicast frames transmitted. - 0 - 32 - read-write - - - - - TX64OCTETS_GB - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX65TO127OCTETS_GB - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX128TO255OCTETS_GB - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX256TO511OCTETS_GB - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX512TO1023OCTETS_GB - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TX1024TOMAXOCTETS_GB - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - TXUNICASTFRAMES_GB - Number of good and bad unicast frames transmitted. - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad unicast frames transmitted. - 0 - 32 - read-write - - - - - TXMULTICASTFRAMES_GB - Number of good and bad multicast frames transmitted. - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad multicast frames transmitted. - 0 - 32 - read-write - - - - - TXBROADCASTFRAMES_GB - Number of good and bad broadcast frames transmitted. - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad broadcast frames transmitted. - 0 - 32 - read-write - - - - - TXUNDERFLOWERROR - Number of frames aborted because of frame underflow error. - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of frame underflow error. - 0 - 32 - read-write - - - - - TXSINGLECOL_G - Number of successfully transmitted frames after a single collision -in the half-duplex mode. - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after a single collision in the half-duplex mode. - 0 - 32 - read-write - - - - - TXMULTICOL_G - Number of successfully transmitted frames after multiple collisions -in the half-duplex mode. - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after multiple collisions in the half-duplex mode. - 0 - 32 - read-write - - - - - TXDEFERRED - Number of successfully transmitted frames after a deferral in the -half-duplex mode. - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after a deferral in the half-duplex mode. - 0 - 32 - read-write - - - - - TXLATECOL - Number of frames aborted because of late collision error - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of late collision error. - 0 - 32 - read-write - - - - - TXEXESSCOL - Number of frames aborted because of excessive (16) collision -errors - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of excessive (16) collision errors. - 0 - 32 - read-write - - - - - TXCARRIERERROR - Number of frames aborted because of carrier sense error (no -carrier or loss of carrier). - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of carrier sense error (no carrier or loss of carrier). - 0 - 32 - read-write - - - - - TXOCTETCOUNT_G - Number of bytes transmitted, exclusive of preamble, only in good -frames. - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes transmitted, exclusive of preamble, only in good frames. - 0 - 32 - read-write - - - - - TXFRAMECOUNT_G - Number of good frames transmitted - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good frames transmitted. - 0 - 32 - read-write - - - - - TXEXCESSDEF - Number of frames aborted because of excessive deferral error -(deferred for more than two max-sized frame times). - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). - 0 - 32 - read-write - - - - - TXPAUSEFRAMES - Number of good Pause frames transmitted - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good Pause frames transmitted. - 0 - 32 - read-write - - - - - TXVLANFRAMES_G - Number of good VLAN frames transmitted, exclusive of retried -frames. - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good VLAN frames transmitted, exclusive of retried frames. - 0 - 32 - read-write - - - - - TXOVERSIZE_G - Number of frames transmitted without errors and with length -greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged -frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC -Configuration Register)). - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 - read-write - - - - - RXFRAMECOUNT_GB - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - RXOCTETCOUNT_G - Number of bytes received, exclusive of preamble, only in good -frames. - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received, exclusive of preamble, in good and bad frames. - 0 - 32 - read-write - - - - - RXOCTETCOUNT_GB - Number of bytes received, exclusive of preamble, in good and bad -frames. - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received, exclusive of preamble, only in good frames. - 0 - 32 - read-write - - - - - RXBROADCASTFRAMES_G - Number of good broadcast frames received - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good broadcast frames received. - 0 - 32 - read-write - - - - - RXMULTICASTFRAMES_G - Number of good multicast frames received - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good multicast frames received. - 0 - 32 - read-write - - - - - RXCRCERROR - Number of frames received with CRC error - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with CRC error. - 0 - 32 - read-write - - - - - RXALIGNMENTERROR - Number of frames received with alignment (dribble) error. Valid -only in 10/100 mode - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. - 0 - 32 - read-write - - - - - RXRUNTERROR - Number of frames received with runt (<64 bytes and CRC error) -error. - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with runt (<64 bytes and CRC error) error. - 0 - 32 - read-write - - - - - RXJABBERERROR - Number of giant frames received with length (including CRC) -greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with -CRC error. If Jumbo Frame mode is enabled, then frames of -length greater than 9,018 bytes (9,022 for VLAN tagged) are -considered as giant frames. - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - 0 - 32 - read-write - - - - - RXUNDERSIZE_G - Number of frames received with length less than 64 bytes, without -any errors. - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length less than 64 bytes, without any errors. - 0 - 32 - read-write - - - - - RXOVERSIZE_G - Number of frames received without errors, with length greater -than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 -bytes if enabled in Bit 27 of Register 0 (MAC Configuration -Register)) - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 - read-write - - - - - RX64OCTETS_GB - Number of good and bad frames received with length 64 bytes, -exclusive of preamble. - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length 64 bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX65TO127OCTETS_GB - No description avaiable - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX128TO255OCTETS_GB - No description avaiable - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX256TO511OCTETS_GB - Number of good and bad frames received with length between -256 and 511 (inclusive) bytes, exclusive of preamble. - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX512TO1023OCTETS_GB - Number of good and bad frames received with length between -512 and 1023 (inclusive) bytes, exclusive of preamble. - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX1024TOMAXOCTETS_GB - Number of good and bad frames received with length between -1024 and maxsize (inclusive) bytes, exclusive of preamble. - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - RXUNICASTFRAMES_G - Number of received good unicast frames. - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good unicast frames. - 0 - 32 - read-write - - - - - RXLENGTHERROR - Number of frames received with length error (Length type field ≠ -frame size), for all frames with valid length field. - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. - 0 - 32 - read-write - - - - - RXOUTOFRANGETYPE - Number of frames received with length field not equal to the valid -frame size (greater than 1,500 but less than 1,536). - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - 0 - 32 - read-write - - - - - RXPAUSEFRAMES - Number of good and valid Pause frames received. - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and valid Pause frames received. - 0 - 32 - read-write - - - - - RXFIFOOVERFLOW - Number of missed received frames because of FIFO overflow. -This counter is not present in the GMAC-CORE configuration. - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. - 0 - 32 - read-write - - - - - RXVLANFRAMES_GB - Number of good and bad VLAN frames received. - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad VLAN frames received. - 0 - 32 - read-write - - - - - RXWATCHDOGERROR - Number of frames received with error because of watchdog -timeout error (frames with a data load larger than 2,048 bytes or -the value programmed in Register 55 (Watchdog Timeout -Register)). - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). - 0 - 32 - read-write - - - - - RXRCVERROR - Number of frames received with Receive error or Frame Extension -error on the GMII or MII interface. - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. - 0 - 32 - read-write - - - - - RXCTRLFRAMES_G - Number of received good control frames - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good control frames. - 0 - 32 - read-write - - - - - MMC_IPC_INTR_MASK_RX - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - MMC_IPC_INTR_RX - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - RXIPV4_GD_FMS - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - RXIPV4_HDRERR_FRMS - Number of IPv4 datagrams received with header (checksum, -length, or version mismatch) errors - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors - 0 - 32 - read-write - - - - - RXIPV4_NOPAY_FRMS - Number of IPv4 datagram frames received that did not have a -TCP, UDP, or ICMP payload processed by the Checksum engine - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine - 0 - 32 - read-write - - - - - RXIPV4_FRAG_FRMS - Number of good IPv4 datagrams with fragmentation - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams with fragmentation - 0 - 32 - read-write - - - - - RXIPV4_UDSBL_FRMS - Number of good IPv4 datagrams received that had a UDP -payload with checksum disabled - 0x220 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received that had a UDP payload with checksum disabled - 0 - 32 - read-write - - - - - RXIPV6_GD_FRMS - Number of good IPv6 datagrams received with TCP, UDP, or -ICMP payloads - 0x224 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads - 0 - 32 - read-write - - - - - RXIPV6_HDRERR_FRMS - Number of IPv6 datagrams received with header errors (length or -version mismatch) - 0x228 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv6 datagrams received with header errors (length or version mismatch) - 0 - 32 - read-write - - - - - RXIPV6_NOPAY_FRMS - Number of IPv6 datagram frames received that did not have a -TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with -fragmentation or security extension headers - 0x22c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers - 0 - 32 - read-write - - - - - RXUDP_GD_FRMS - Number of good IP datagrams with a good UDP payload. This -counter is not updated when the rxipv4_udsbl_frms counter is -incremented. - 0x230 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. - 0 - 32 - read-write - - - - - RXUDP_ERR_FRMS - Number of good IP datagrams whose UDP payload has a -checksum error - 0x234 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose UDP payload has a checksum error - 0 - 32 - read-write - - - - - RXTCP_GD_FRMS - Number of good IP datagrams with a good TCP payload - 0x238 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good TCP payload - 0 - 32 - read-write - - - - - RXTCP_ERR_FRMS - Number of good IP datagrams whose TCP payload has a -checksum error - 0x23c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose TCP payload has a checksum error - 0 - 32 - read-write - - - - - RXICMP_GD_FRMS - Number of good IP datagrams with a good ICMP payload - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good ICMP payload - 0 - 32 - read-write - - - - - RXICMP_ERR_FRMS - Number of good IP datagrams whose ICMP payload has a -checksum error - 0x244 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose ICMP payload has a checksum error - 0 - 32 - read-write - - - - - RXIPV4_GD_OCTETS - Number of bytes received in good IPv4 datagrams encapsulating -TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad -bytes are not included in this counter or in the octet counters listed -below). - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). - 0 - 32 - read-write - - - - - RXIPV4_HDRERR_OCTETS - Number of bytes received in IPv4 datagrams with header errors -(checksum, length, version mismatch). The value in the Length -field of IPv4 header is used to update this counter. - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_NOPAY_OCTETS - Number of bytes received in IPv4 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv4 header’s -Length field is used to update this counter. - 0x258 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_FRAG_OCTETS - Number of bytes received in fragmented IPv4 datagrams. The -value in the IPv4 header’s Length field is used to update this -counter - 0x25c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_UDSBL_OCTETS - Number of bytes received in a UDP segment that had the UDP -checksum disabled. This counter does not count IP Header bytes. - 0x260 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. - 0 - 32 - read-write - - - - - RXIPV6_GD_OCTETS - Number of bytes received in good IPv6 datagrams encapsulating -TCP, UDP or ICMPv6 data - 0x264 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data - 0 - 32 - read-write - - - - - RXIPV6_HDRERR_OCTETS - Number of bytes received in IPv6 datagrams with header errors -(length, version mismatch). The value in the IPv6 header’s Length -field is used to update this counter. - 0x268 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV6_NOPAY_OCTETS - Number of bytes received in IPv6 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv6 header’s -Length field is used to update this counter. - 0x26c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXUDP_GD_OCTETS - Number of bytes received in a good UDP segment. This counter -(and the counters below) does not count IP header bytes. - 0x270 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. - 0 - 32 - read-write - - - - - RXUDP_ERR_OCTETS - Number of bytes received in a UDP segment that had checksum -errors - 0x274 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a UDP segment that had checksum errors - 0 - 32 - read-write - - - - - RXTCP_GD_OCTETS - Number of bytes received in a good TCP segment - 0x278 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good TCP segment - 0 - 32 - read-write - - - - - RXTCP_ERR_OCTETS - Number of bytes received in a TCP segment with checksum -errors - 0x27c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a TCP segment with checksum errors - 0 - 32 - read-write - - - - - RXICMP_GD_OCTETS - Number of bytes received in a good ICMP segment - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good ICMP segment - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x400 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_0_L4_ADDR - Layer 4 Address Register - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_0 - Layer 3 Address 0 Register - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_1 - Layer 3 Address 1 Register - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_2 - Layer 3 Address 2 Register - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_3 - Layer 3 Address 3 Register - 0x41c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x430 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_1_L4_ADDR - Layer 4 Address Register - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_0 - Layer 3 Address 0 Register - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_1 - Layer 3 Address 1 Register - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_2 - Layer 3 Address 2 Register - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_1_L3_ADDR_3 - Layer 3 Address 3 Register - 0x44c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x460 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_2_L4_ADDR - Layer 4 Address Register - 0x464 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_0 - Layer 3 Address 0 Register - 0x470 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_1 - Layer 3 Address 1 Register - 0x474 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_2 - Layer 3 Address 2 Register - 0x478 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_2_L3_ADDR_3 - Layer 3 Address 3 Register - 0x47c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x490 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_3_L4_ADDR - Layer 4 Address Register - 0x494 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_0 - Layer 3 Address 0 Register - 0x4a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_1 - Layer 3 Address 1 Register - 0x4a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_2 - Layer 3 Address 2 Register - 0x4a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_3_L3_ADDR_3 - Layer 3 Address 3 Register - 0x4ac - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER0 - Hash Table Register 0 - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER1 - Hash Table Register 1 - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER2 - Hash Table Register 2 - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER3 - Hash Table Register 3 - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER4 - Hash Table Register 4 - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER5 - Hash Table Register 5 - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER6 - Hash Table Register 6 - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER7 - Hash Table Register 7 - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-write - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-write - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description avaiable - 7 - 1 - read-only - - - TSTARGT2 - No description avaiable - 6 - 1 - read-only - - - TSTRGTERR1 - No description avaiable - 5 - 1 - read-only - - - TSTARGT1 - No description avaiable - 4 - 1 - read-only - - - TSTRGTERR - No description avaiable - 3 - 1 - read-only - - - AUXTSTRIG - No description avaiable - 2 - 1 - read-only - - - TSTARGT - No description avaiable - 1 - 1 - read-only - - - TSSOVF - No description avaiable - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - read-write - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - read-write - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - read-write - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRL0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-write - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-write - - - - - PPS0_INTERVAL - PPS0 Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS0 Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_1_TGTTM_SEC - PPS Target Time Seconds Register - 0x780 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - PPS_1_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x784 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - PPS_1_INTERVAL - PPS Interval Register - 0x788 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_1_WIDTH - PPS Width Register - 0x78c - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_2_TGTTM_SEC - PPS2 Target Time Seconds Register - 0x7a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - PPS_2_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x7a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - PPS_2_INTERVAL - PPS Interval Register - 0x7a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_2_WIDTH - PPS Width Register - 0x7ac - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_3_TGTTM_SEC - PPS3 Target Time Seconds Register - 0x7c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - PPS_3_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x7c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - PPS_3_INTERVAL - PPS Interval Register - 0x7c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS_3_WIDTH - PPS Width Register - 0x7cc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_HW_FEATURE - HW Feature Register - 0x1058 - 32 - 0x00000000 - 0x7FFFFFFF - - - ACTPHYIF - Active or selected PHY interface -When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. -- 000: GMII or MII -- 001: RGMII -- 010: SGMII -- 011: TBI -- 100: RMII -- 101: RTBI -- 110: SMII -- 111: RevMII - All Others: Reserved - 28 - 3 - read-write - - - SAVLANINS - Source Address or VLAN Insertion - 27 - 1 - read-write - - - FLEXIPPSEN - Flexible Pulse-Per-Second Output - 26 - 1 - read-write - - - INTTSEN - Timestamping with Internal System Time - 25 - 1 - read-write - - - ENHDESSEL - Alternate (Enhanced Descriptor) - 24 - 1 - read-write - - - TXCHCNT - Number of additional Tx Channels - 22 - 2 - read-write - - - RXCHCNT - Number of additional Rx Channels - 20 - 2 - read-write - - - RXFIFOSIZE - Rx FIFO > 2,048 Bytes - 19 - 1 - read-write - - - RXTYP2COE - IP Checksum Offload (Type 2) in Rx - 18 - 1 - read-write - - - RXTYP1COE - IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. - 17 - 1 - read-write - - - TXCOESEL - Checksum Offload in Tx - 16 - 1 - read-write - - - AVSEL - AV feature - 15 - 1 - read-write - - - EEESEL - Energy Efficient Ethernet - 14 - 1 - read-write - - - TSVER2SEL - IEEE 1588-2008 Advanced timestamp - 13 - 1 - read-write - - - TSVER1SEL - Only IEEE 1588-2002 timestamp - 12 - 1 - read-write - - - MMCSEL - RMON module - 11 - 1 - read-write - - - MGKSEL - PMT magic packet - 10 - 1 - read-write - - - RWKSEL - PMT remote wake-up frame - 9 - 1 - read-write - - - SMASEL - SMA (MDIO) Interface - 8 - 1 - read-write - - - L3L4FLTREN - Layer 3 and Layer 4 feature - 7 - 1 - read-write - - - PCSSEL - PCS registers (TBI, SGMII, or RTBI PHY interface) - 6 - 1 - read-write - - - ADDMACADRSEL - Multiple MAC Address registers - 5 - 1 - read-write - - - HASHSEL - HASH filter - 4 - 1 - read-write - - - EXTHASHEN - Expanded DA Hash filter - 3 - 1 - read-write - - - HDSEL - Half-duplex support - 2 - 1 - read-write - - - GMIISEL - 1000 Mbps support - 1 - 1 - read-write - - - MIISEL - 10 or 100 Mbps support - 0 - 1 - read-write - - - - - CTRL0 - Control Register 0 - 0x3000 - 32 - 0x00000000 - 0x000003FF - - - ENET0_RXCLK_DLY_SEL - No description avaiable - 5 - 5 - read-write - - - ENET0_TXCLK_DLY_SEL - No description avaiable - 0 - 5 - read-write - - - - - CTRL2 - Control Register 1 - 0x3008 - 32 - 0x00000000 - 0xF808F400 - - - ENET0_IRQ_EN - No description avaiable - 27 - 5 - read-write - - - ENET0_REFCLK_OE - No description avaiable - 19 - 1 - read-write - - - ENET0_PHY_INF_SEL - No description avaiable - 13 - 3 - read-write - - - ENET0_FLOWCTRL - No description avaiable - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - No description avaiable - 10 - 1 - read-write - - - - - - - ENET1 - ENET1 - ENET - 0xf2004000 - - - NTMR0 - NTMR0 - TMR - 0xf2010000 - - 0x0 - 0x20c - registers - - - - CHANNEL_CH0_CR - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH0_CMP0 - Comparator register 0 - 0x4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH0_CMP1 - Comparator register 1 - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH0_RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH0_CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH0_CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH0_CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH0_CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH0_CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH0_CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - CHANNEL_CH1_CR - Control Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH1_CMP0 - Comparator register 0 - 0x44 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH1_CMP1 - Comparator register 1 - 0x48 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH1_RLD - Reload register - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH1_CNTUPTVAL - Counter update value register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH1_CAPPOS - Capture rising edge register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH1_CAPNEG - Capture falling edge register - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH1_CAPPRD - PWM period measure register - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH1_CAPDTY - PWM duty cycle measure register - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH1_CNT - Counter - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - CHANNEL_CH2_CR - Control Register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH2_CMP0 - Comparator register 0 - 0x84 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH2_CMP1 - Comparator register 1 - 0x88 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH2_RLD - Reload register - 0x8c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH2_CNTUPTVAL - Counter update value register - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH2_CAPPOS - Capture rising edge register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPNEG - Capture falling edge register - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPPRD - PWM period measure register - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPDTY - PWM duty cycle measure register - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH2_CNT - Counter - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - CHANNEL_CH3_CR - Control Register - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - RESERVED - not exist - 15 - 16 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- RLD flag, counter reload; -01- Input signal toggle captured -10- CMP0 flag -11- CMP1 flag - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - CHANNEL_CH3_CMP0 - Comparator register 0 - 0xc4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH3_CMP1 - Comparator register 1 - 0xc8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - CHANNEL_CH3_RLD - Reload register - 0xcc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CHANNEL_CH3_CNTUPTVAL - Counter update value register - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CHANNEL_CH3_CAPPOS - Capture rising edge register - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CHANNEL_CH3_CAPNEG - Capture falling edge register - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH3_CAPPRD - PWM period measure register - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH3_CAPDTY - PWM duty cycle measure register - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH3_CNT - Counter - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 16 - 16 - read-write - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - read-write - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - read-write - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - read-write - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - read-write - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - read-write - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - read-write - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - read-write - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - read-write - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - read-write - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - read-write - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - read-write - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - read-write - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - read-write - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - read-write - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - read-write - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - read-write - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 16 - 16 - read-write - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software coutner sync event - 0 - 4 - read-write - - - - - - - NTMR1 - NTMR1 - TMR - 0xf2014000 - - - GPTMR0 - GPTMR0 - TMR - 0xf3000000 - - - GPTMR1 - GPTMR1 - TMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - TMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - TMR - 0xf300c000 - - - GPTMR4 - GPTMR4 - TMR - 0xf3010000 - - - GPTMR5 - GPTMR5 - TMR - 0xf3014000 - - - GPTMR6 - GPTMR6 - TMR - 0xf3018000 - - - GPTMR7 - GPTMR7 - TMR - 0xf301c000 - - - PTMR - PTMR - TMR - 0xf40e0000 - - - USB0 - USB0 - USB - 0xf2020000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00000000 - 0x00FFEB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0x00FF00FF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 8 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 8 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0x00FF00FF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 8 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 8 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x000000FF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 8 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0x00FF00FF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0x00FF00FF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0x00FF00FF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0x00FF00FF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTCTRL_ENDPTCTRL0 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL1 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c4 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL2 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c8 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL3 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1cc - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL4 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL5 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d4 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL6 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d8 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL7 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1dc - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - read-write - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - read-write - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description avaiable - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description avaiable - 25 - 1 - read-write - - - AUTORESUME_EN - No description avaiable - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description avaiable - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description avaiable - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description avaiable - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description avaiable - 10 - 1 - read-write - - - OTG_POWER_MASK - No description avaiable - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description avaiable - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description avaiable - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description avaiable - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description avaiable - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description avaiable - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description avaiable - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description avaiable - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description avaiable - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description avaiable - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description avaiable - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description avaiable - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description avaiable - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description avaiable - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description avaiable - 31 - 1 - read-write - - - - - PHY_STATUS - No description avaiable - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description avaiable - 31 - 1 - read-write - - - LINE_STATE - No description avaiable - 6 - 2 - read-write - - - HOST_DISCONNECT - No description avaiable - 5 - 1 - read-write - - - ID_DIG - No description avaiable - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description avaiable - 2 - 1 - read-write - - - VBUS_VALID - No description avaiable - 0 - 1 - read-write - - - - - - - USB1 - USB1 - USB - 0xf2024000 - - - SDXC0 - SDXC0 - SDXC - 0xf2030000 - - 0x0 - 0x548 - registers - - - - SDMASA - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description avaiable - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description avaiable - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description avaiable - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - RESP_RESP01 - No description avaiable - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP23 - No description avaiable - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP45 - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP67 - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - BUF_DATA - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description avaiable - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description avaiable - 0x28 - 32 - 0x00000000 - 0x070F0E3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description avaiable - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description avaiable - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgement Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description avaiable - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description avaiable - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description avaiable - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description avaiable - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description avaiable - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description avaiable - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description avaiable - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description avaiable - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description avaiable - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description avaiable - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - PRESET_INIT - No description avaiable - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_DS - No description avaiable - 0x62 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_HS - No description avaiable - 0x64 - 16 - 0x0001 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR12 - No description avaiable - 0x66 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR25 - No description avaiable - 0x68 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR50 - No description avaiable - 0x6a - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR104 - No description avaiable - 0x6c - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_DDR50 - No description avaiable - 0x6e - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_UHS2 - No description avaiable - 0x74 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description avaiable - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description avaiable - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description avaiable - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description avaiable - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description avaiable - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description avaiable - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description avaiable - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description avaiable - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description avaiable - 0 - 1 - read-write - - - - - CQCTL - No description avaiable - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description avaiable - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description avaiable - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description avaiable - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description avaiable - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description avaiable - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description avaiable - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description avaiable - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description avaiable - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description avaiable - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description avaiable - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description avaiable - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description avaiable - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description avaiable - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description avaiable - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description avaiable - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description avaiable - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description avaiable - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description avaiable - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description avaiable - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description avaiable - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description avaiable - 0 - 32 - read-only - - - - - MBIU_CTRL - Y - 0x510 - 32 - 0x00000000 - 0x0000000F - - - BURST_INCR16_EN - No description avaiable - 3 - 1 - read-write - - - BURST_INCR8_EN - No description avaiable - 2 - 1 - read-write - - - BUSRT_INCR4_EN - No description avaiable - 1 - 1 - read-write - - - UNDEFL_INCR_EN - No description avaiable - 0 - 1 - read-write - - - - - EMMC_BOOT_CTRL - No description avaiable - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description avaiable - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description avaiable - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - - - SDXC1 - SDXC1 - SDXC - 0xf2034000 - - - CONCTL - CONCTL - CONCTL - 0xf2040000 - - 0x0 - 0x18 - registers - - - - CTRL0 - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFF0FFFFF - - - RESERVED - No description avaiable - 24 - 8 - read-write - - - ENET1_RXCLK_DLY_SEL - No description avaiable - 15 - 5 - read-write - - - ENET1_TXCLK_DLY_SEL - No description avaiable - 10 - 5 - read-write - - - ENET0_RXCLK_DLY_SEL - No description avaiable - 5 - 5 - read-write - - - ENET0_TXCLK_DLY_SEL - No description avaiable - 0 - 5 - read-write - - - - - CTRL2 - No description avaiable - 0x8 - 32 - 0x00000000 - 0x0008F400 - - - ENET0_REFCLK_OE - No description avaiable - 19 - 1 - read-write - - - ENET0_PHY_INTF_SEL - 000:Reserved -001:RGMII -100:RMII -111:Reserved - 13 - 3 - read-write - - - ENET0_FLOWCTRL - No description avaiable - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - default to use internal clk. -set from pad， two option here: - internal 50MHz clock out to pad then in; - use external clock; - 10 - 1 - read-write - - - - - CTRL3 - No description avaiable - 0xc - 32 - 0x00000000 - 0x0008F400 - - - ENET1_REFCLK_OE - No description avaiable - 19 - 1 - read-write - - - ENET1_PHY_INTF_SEL - No description avaiable - 13 - 3 - read-write - - - ENET1_FLOWCTRL - No description avaiable - 12 - 1 - read-write - - - ENET1_RMII_TXCLK_SEL - No description avaiable - 10 - 1 - read-write - - - - - CTRL4 - No description avaiable - 0x10 - 32 - 0x00000000 - 0xDFFE0000 - - - SDXC0_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC0_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC0_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC0_GPR_TUNING_CARD_CLK_SEL - for card clock DLL, default 0 - 23 - 5 - read-write - - - SDXC0_GPR_TUNING_STROBE_SEL - for strobe DLL, default 7taps(1ns) - 18 - 5 - read-write - - - SDXC0_GPR_STROBE_IN_ENABLE - enable strobe clock, maybe used when update strobe DLL - 17 - 1 - read-write - - - - - CTRL5 - No description avaiable - 0x14 - 32 - 0x00000000 - 0xDFFE0000 - - - SDXC1_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC1_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC1_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC1_GPR_TUNING_CARD_CLK_SEL - No description avaiable - 23 - 5 - read-write - - - SDXC1_GPR_TUNING_STROBE_SEL - No description avaiable - 18 - 5 - read-write - - - SDXC1_GPR_STROBE_IN_ENABLE - No description avaiable - 17 - 1 - read-write - - - - - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x4 - 0x30 - registers - - - - CFG - Configuration Register - 0x10 - 32 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 2 - 30 - read-write - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - INTEN - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 10 - 22 - read-write - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - STATUS - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 15 - 17 - read-write - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - read-write - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - read-write - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - read-write - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - read-write - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - read-write - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - read-write - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - read-write - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - ADDR - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 10 - 22 - read-write - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - DATA - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 8 - 24 - read-write - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - CTRL - Control Register - 0x24 - 32 - 0x00001E00 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 13 - 19 - read-write - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - CMD - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 3 - 29 - read-write - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - SETUP - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 29 - 3 - read-write - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - RESERVED - No description avaiable - 14 - 2 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 5 - 27 - read-write - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - RESERVED - Not used - 24 - 4 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - RESERVED - Reserved - 18 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - RESERVED - Not used - 17 - 1 - read-only - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - CRCEN - CRC enable. -1x1, CRC is enabled. -1x0, CRC is disabled. - 11 - 1 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - RESERVED - Not used - 8 - 1 - read-only - - - RESERVED - Not used - 6 - 2 - read-only - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 31 - 1 - read-write - - - RESERVED - Not used - 30 - 1 - read-write - - - RESERVED - Not used - 24 - 6 - read-only - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - read-write - - - RESERVED - Not used - 21 - 2 - read-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - read-write - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - read-write - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - read-write - - - RESERVED - Not used - 6 - 10 - read-only - - - ERRSET - Working mode setup error. - 5 - 1 - read-write - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - read-write - - - ERRSRC - Source Buffer Access Error - 3 - 1 - read-write - - - ERRDST - Destination Buffer Error - 2 - 1 - read-write - - - ERRHAS - Hashing Check Error - 1 - 1 - read-write - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - read-write - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - RESERVED - Not used - 24 - 8 - read-only - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - RESERVED - Not used - 2 - 14 - read-only - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV0 - Cipher Initializtion Vector 0 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV1 - Cipher Initializtion Vector 1 - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV2 - Cipher Initializtion Vector 2 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV3 - Cipher Initializtion Vector 3 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - HASWRD_HASWRD0 - Hash Data Word 0 - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD1 - Hash Data Word 1 - 0x2c - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD2 - Hash Data Word 2 - 0x30 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD3 - Hash Data Word 3 - 0x34 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD4 - Hash Data Word 4 - 0x38 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD5 - Hash Data Word 5 - 0x3c - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD6 - Hash Data Word 6 - 0x40 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD7 - Hash Data Word 7 - 0x44 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - RESERVED - Not used - 7 - 17 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - RESERVED - Not used - 0 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description avaiable - 0 - 32 - read-write - - - - - - - DRAM - DRAM - DRAM - 0xf3050000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 - read-write - - - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 - read-write - - - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 - 1 - read-write - - - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 - 1 - read-write - - - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 - 1 - read-write - - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 - read-write - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BR_BASE0 - Base Register 0 (for SDRAM CS0 device) - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - BR_BASE1 - Base Register 1 (for SDRAM CS1 device) - 0x14 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - INTEN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 - 1 - read-write - - - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 - 1 - read-write - - - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 - 1 - read-write - - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 - 1 - read-write - - - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 - 1 - read-write - - - IPCMDDONE - IP command normal done interrupt - 0 - 1 - read-write - - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 - 1 - read-write - - - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 - read-write - - - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 - read-write - - - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 - 1 - read-write - - - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 - read-write - - - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 - 1 - read-write - - - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 - read-write - - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 - read-write - - - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 - read-write - - - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 - read-write - - - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 - read-write - - - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 - read-write - - - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 - read-write - - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 - read-write - - - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 - read-write - - - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 - read-write - - - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - 0 - 8 - read-write - - - - - SDRCTRL3 - SDRAM Control Register 3 - 0x4c - 32 - 0x00000000 - 0xFFFFFF0F - - - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 - read-write - - - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 - read-write - - - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 - read-write - - - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 - read-write - - - REN - Refresh enable - 0 - 1 - read-write - - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SA - Slave address - 0 - 32 - read-write - - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 - read-write - - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked - 3 - 1 - read-write - - - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked - 2 - 1 - read-write - - - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked - 1 - 1 - read-write - - - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked - 0 - 1 - read-write - - - - - IPCMD - IP Command Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. - 16 - 16 - write-only - - - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write - - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 - 1 - read-only - - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 - 1 - read-write - - - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells - 1 - 5 - read-write - - - DLYEN - delay line enable - 0 - 1 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x3000 - registers - - - - RESOURCE_CPU0_CORE - Resource control register for cpu0 - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CPU0_SUBSYS - Resource control register for cpx0 - 0x4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CPU1_CORE - Resource control register for cpu1 - 0x20 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CPX1_SUBSYS - Resource control register for cpx1 - 0x24 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_POW_CON - Resource control register for pow_con - 0x54 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_POW_VIS - Resource control register for pow_vis - 0x58 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_POW_CPU0 - Resource control register for pow_cpu0 - 0x5c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_POW_CPU1 - Resource control register for pow_cpu1 - 0x60 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RST_SOC - Resource control register for rst_soc - 0x64 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RST_CON - Resource control register for rst_con - 0x68 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RST_VIS - Resource control register for rst_vis - 0x6c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RST_CPU0 - Resource control register for rst_cpu0 - 0x70 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RST_CPU1 - Resource control register for rst_cpu1 - 0x74 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_XTAL - Resource control register for xtal - 0x80 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL0 - Resource control register for pll0 - 0x84 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL0CLK0 - Resource control register for clk0_pll0 - 0x88 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL1 - Resource control register for pll1 - 0x8c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL1CLK0 - Resource control register for clk0_pll1 - 0x90 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL1CLK1 - Resource control register for clk1_pll1 - 0x94 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL2 - Resource control register for pll2 - 0x98 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL2CLK0 - Resource control register for clk0_pll2 - 0x9c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL2CLK1 - Resource control register for clk1_pll2 - 0xa0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL3 - Resource control register for pll3 - 0xa4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL3CLK0 - Resource control register for clk0_pll3 - 0xa8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL4 - Resource control register for pll4 - 0xac - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_SRC_PLL4CLK0 - Resource control register for clk0_pll4 - 0xb0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CPU0 - Resource control register for clk_top_cpu0 - 0x100 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_MCHTMR0 - Resource control register for clk_top_mct0 - 0x104 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CPU1 - Resource control register for clk_top_cpu1 - 0x108 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_MCHTMR1 - Resource control register for clk_top_mct1 - 0x10c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_AXI - Resource control register for clk_top_axi0 - 0x110 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CONN - Resource control register for clk_top_axi1 - 0x114 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_VIS - Resource control register for clk_top_axi2 - 0x118 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_AHB - Resource control register for clk_top_ahb0 - 0x11c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_DRAM - Resource control register for clk_top_dram - 0x120 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_XPI0 - Resource control register for clk_top_xpi0 - 0x124 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_XPI1 - Resource control register for clk_top_xpi1 - 0x128 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR0 - Resource control register for clk_top_tmr0 - 0x12c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR1 - Resource control register for clk_top_tmr1 - 0x130 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR2 - Resource control register for clk_top_tmr2 - 0x134 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR3 - Resource control register for clk_top_tmr3 - 0x138 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR4 - Resource control register for clk_top_tmr4 - 0x13c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR5 - Resource control register for clk_top_tmr5 - 0x140 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR6 - Resource control register for clk_top_tmr6 - 0x144 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_GPTMR7 - Resource control register for clk_top_tmr7 - 0x148 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART0 - Resource control register for clk_top_urt0 - 0x14c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART1 - Resource control register for clk_top_urt1 - 0x150 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART2 - Resource control register for clk_top_urt2 - 0x154 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART3 - Resource control register for clk_top_urt3 - 0x158 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART4 - Resource control register for clk_top_urt4 - 0x15c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART5 - Resource control register for clk_top_urt5 - 0x160 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART6 - Resource control register for clk_top_urt6 - 0x164 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART7 - Resource control register for clk_top_urt7 - 0x168 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART8 - Resource control register for clk_top_urt8 - 0x16c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART9 - Resource control register for clk_top_urt9 - 0x170 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART10 - Resource control register for clk_top_urta - 0x174 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART11 - Resource control register for clk_top_urtb - 0x178 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART12 - Resource control register for clk_top_urtc - 0x17c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART13 - Resource control register for clk_top_urtd - 0x180 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART14 - Resource control register for clk_top_urte - 0x184 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_UART15 - Resource control register for clk_top_urtf - 0x188 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C0 - Resource control register for clk_top_i2c0 - 0x18c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C1 - Resource control register for clk_top_i2c1 - 0x190 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C2 - Resource control register for clk_top_i2c2 - 0x194 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2C3 - Resource control register for clk_top_i2c3 - 0x198 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI0 - Resource control register for clk_top_spi0 - 0x19c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI1 - Resource control register for clk_top_spi1 - 0x1a0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI2 - Resource control register for clk_top_spi2 - 0x1a4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SPI3 - Resource control register for clk_top_spi3 - 0x1a8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAN0 - Resource control register for clk_top_can0 - 0x1ac - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAN1 - Resource control register for clk_top_can1 - 0x1b0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAN2 - Resource control register for clk_top_can2 - 0x1b4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAN3 - Resource control register for clk_top_can3 - 0x1b8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_PTPC - Resource control register for clk_top_ptpc - 0x1bc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ANA0 - Resource control register for clk_top_ana0 - 0x1c0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ANA1 - Resource control register for clk_top_ana1 - 0x1c4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ANA2 - Resource control register for clk_top_ana2 - 0x1c8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_AUD0 - Resource control register for clk_top_aud0 - 0x1cc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_AUD1 - Resource control register for clk_top_aud1 - 0x1d0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_AUD2 - Resource control register for clk_top_aud2 - 0x1d4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_LCDC - Resource control register for clk_top_dis0 - 0x1d8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAM0 - Resource control register for clk_top_cam0 - 0x1dc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_CAM1 - Resource control register for clk_top_cam1 - 0x1e0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ENET0 - Resource control register for clk_top_eth0 - 0x1e4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ENET1 - Resource control register for clk_top_eth1 - 0x1e8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_PTP0 - Resource control register for clk_top_ptp0 - 0x1ec - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_PTP1 - Resource control register for clk_top_ptp1 - 0x1f0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_REF0 - Resource control register for clk_top_ref0 - 0x1f4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_REF1 - Resource control register for clk_top_ref1 - 0x1f8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_NTMR0 - Resource control register for clk_top_ntm0 - 0x1fc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_NTMR1 - Resource control register for clk_top_ntm1 - 0x200 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SDXC0 - Resource control register for clk_top_sdc0 - 0x204 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_SDXC1 - Resource control register for clk_top_sdc1 - 0x208 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ADC0 - Resource control register for clk_top_adc0 - 0x300 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ADC1 - Resource control register for clk_top_adc1 - 0x304 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ADC2 - Resource control register for clk_top_adc2 - 0x308 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_ADC3 - Resource control register for clk_top_adc3 - 0x30c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2S0 - Resource control register for clk_top_i2s0 - 0x310 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2S1 - Resource control register for clk_top_i2s1 - 0x314 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2S2 - Resource control register for clk_top_i2s2 - 0x318 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CLK_TOP_I2S3 - Resource control register for clk_top_i2s3 - 0x31c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_AHBAPB_BUS - Resource control register for ahbp - 0x400 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_AXI_BUS - Resource control register for axis - 0x404 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CONN_BUS - Resource control register for axic - 0x408 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_VIS_BUS - Resource control register for axiv - 0x40c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_DRAM - Resource control register for dram - 0x410 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ROM - Resource control register for rom0 - 0x414 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_LMM0 - Resource control register for lmm0 - 0x418 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_LMM1 - Resource control register for lmm1 - 0x41c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MCHTMR0 - Resource control register for mct0 - 0x420 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MCHTMR1 - Resource control register for mct1 - 0x424 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_AXI_SRAM0 - Resource control register for ram0 - 0x428 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_AXI_SRAM1 - Resource control register for ram1 - 0x42c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_XPI0 - Resource control register for xpi0 - 0x430 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_XPI1 - Resource control register for xpi1 - 0x434 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SDP - Resource control register for sdp0 - 0x438 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_RNG - Resource control register for rng0 - 0x43c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_KEYM - Resource control register for kman - 0x440 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_HDMA - Resource control register for dma0 - 0x444 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_XDMA - Resource control register for dma1 - 0x448 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPIO - Resource control register for gpio - 0x44c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MBX0 - Resource control register for mbx0 - 0x450 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MBX1 - Resource control register for mbx1 - 0x454 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_WDG0 - Resource control register for wdg0 - 0x458 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_WDG1 - Resource control register for wdg1 - 0x45c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_WDG2 - Resource control register for wdg2 - 0x460 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_WDG3 - Resource control register for wdg3 - 0x464 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR0 - Resource control register for tmr0 - 0x468 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR1 - Resource control register for tmr1 - 0x46c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR2 - Resource control register for tmr2 - 0x470 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR3 - Resource control register for tmr3 - 0x474 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR4 - Resource control register for tmr4 - 0x478 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR5 - Resource control register for tmr5 - 0x47c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR6 - Resource control register for tmr6 - 0x480 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_GPTMR7 - Resource control register for tmr7 - 0x484 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART0 - Resource control register for urt0 - 0x488 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART1 - Resource control register for urt1 - 0x48c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART2 - Resource control register for urt2 - 0x490 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART3 - Resource control register for urt3 - 0x494 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART4 - Resource control register for urt4 - 0x498 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART5 - Resource control register for urt5 - 0x49c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART6 - Resource control register for urt6 - 0x4a0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART7 - Resource control register for urt7 - 0x4a4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART8 - Resource control register for urt8 - 0x4a8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART9 - Resource control register for urt9 - 0x4ac - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART10 - Resource control register for urta - 0x4b0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART11 - Resource control register for urtb - 0x4b4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART12 - Resource control register for urtc - 0x4b8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART13 - Resource control register for urtd - 0x4bc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART14 - Resource control register for urte - 0x4c0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_UART15 - Resource control register for urtf - 0x4c4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C0 - Resource control register for i2c0 - 0x4c8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C1 - Resource control register for i2c1 - 0x4cc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C2 - Resource control register for i2c2 - 0x4d0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2C3 - Resource control register for i2c3 - 0x4d4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI0 - Resource control register for spi0 - 0x4d8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI1 - Resource control register for spi1 - 0x4dc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI2 - Resource control register for spi2 - 0x4e0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SPI3 - Resource control register for spi3 - 0x4e4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAN0 - Resource control register for can0 - 0x4e8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAN1 - Resource control register for can1 - 0x4ec - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAN2 - Resource control register for can2 - 0x4f0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAN3 - Resource control register for can3 - 0x4f4 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_PTPC - Resource control register for ptpc - 0x4f8 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ADC0 - Resource control register for adc0 - 0x4fc - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ADC1 - Resource control register for adc1 - 0x500 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ADC2 - Resource control register for adc2 - 0x504 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ADC3 - Resource control register for adc3 - 0x508 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ACMP - Resource control register for acmp - 0x50c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2S0 - Resource control register for i2s0 - 0x510 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2S1 - Resource control register for i2s1 - 0x514 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2S2 - Resource control register for i2s2 - 0x518 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_I2S3 - Resource control register for i2s3 - 0x51c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_PDM - Resource control register for pdm0 - 0x520 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_DAO - Resource control register for clsd - 0x524 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SYNT - Resource control register for msyn - 0x528 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MOT0 - Resource control register for mot0 - 0x52c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MOT1 - Resource control register for mot1 - 0x530 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MOT2 - Resource control register for mot2 - 0x534 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_MOT3 - Resource control register for mot3 - 0x538 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_LCDC - Resource control register for dis0 - 0x53c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAM0 - Resource control register for cam0 - 0x540 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_CAM1 - Resource control register for cam1 - 0x544 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_JPEG - Resource control register for jpeg - 0x548 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_PDMA - Resource control register for pdma - 0x54c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ENET0 - Resource control register for eth0 - 0x550 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_ENET1 - Resource control register for eth1 - 0x554 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_NTMR0 - Resource control register for ntm0 - 0x558 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_NTMR1 - Resource control register for ntm1 - 0x55c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SDXC0 - Resource control register for sdc0 - 0x560 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_SDXC1 - Resource control register for sdc1 - 0x564 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_USB0 - Resource control register for usb0 - 0x568 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_USB1 - Resource control register for usb1 - 0x56c - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_REF0 - Resource control register for ref0 - 0x570 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - RESOURCE_REF1 - Resource control register for ref1 - 0x574 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - GROUP0_0_VALUE - Goup setting - 0x800 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_0_SET - Goup setting - 0x804 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_0_CLEAR - Goup setting - 0x808 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_0_TOGGLE - Goup setting - 0x80c - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_1_VALUE - Goup setting - 0x810 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_1_SET - Goup setting - 0x814 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_1_CLEAR - Goup setting - 0x818 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_1_TOGGLE - Goup setting - 0x81c - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_2_VALUE - Goup setting - 0x820 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_2_SET - Goup setting - 0x824 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_2_CLEAR - Goup setting - 0x828 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP0_2_TOGGLE - Goup setting - 0x82c - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_0_VALUE - Goup setting - 0x840 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_0_SET - Goup setting - 0x844 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_0_CLEAR - Goup setting - 0x848 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_0_TOGGLE - Goup setting - 0x84c - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_1_VALUE - Goup setting - 0x850 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_1_SET - Goup setting - 0x854 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_1_CLEAR - Goup setting - 0x858 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_1_TOGGLE - Goup setting - 0x85c - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_2_VALUE - Goup setting - 0x860 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_2_SET - Goup setting - 0x864 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_2_CLEAR - Goup setting - 0x868 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - GROUP1_2_TOGGLE - Goup setting - 0x86c - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - AFFILIATE_CPU0_VALUE - Affiliate of Group - 0x900 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU0_SET - Affiliate of Group - 0x904 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU0_CLEAR - Affiliate of Group - 0x908 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU0_TOGGLE - Affiliate of Group - 0x90c - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU1_VALUE - Affiliate of Group - 0x910 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU1_SET - Affiliate of Group - 0x914 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU1_CLEAR - Affiliate of Group - 0x918 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - AFFILIATE_CPU1_TOGGLE - Affiliate of Group - 0x91c - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - RETENTION_CPU0_VALUE - Retention Contol - 0x920 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep, each bit represents a resource -bit0: soc_pow -bit1: soc_rst -bit2: cpu0_pow -bit3: cpu0_rst -bit4: cpu1_pow -bit5: cpu1_rst -bit6: con_pow -bit7: con_rst -bit8: vis_pow -bit9: vis_rst -bit10: xtal -bit11: pll0 -bit12: pll1 -bit13: pll2 -bit14: pll3 -bit15: pll4 - 0 - 18 - read-write - - - - - RETENTION_CPU0_SET - Retention Contol - 0x924 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - RETENTION_CPU0_CLEAR - Retention Contol - 0x928 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - RETENTION_CPU0_TOGGLE - Retention Contol - 0x92c - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - RETENTION_CPU1_VALUE - Retention Contol - 0x930 - 32 - 0x00000000 - 0x0003FFFF - - - LINK - retention setting while system sleep, each bit represents a resource -bit0: soc_pow -bit1: soc_rst -bit2: cpu0_pow -bit3: cpu0_rst -bit4: cpu1_pow -bit5: cpu1_rst -bit6: con_pow -bit7: con_rst -bit8: vis_pow -bit9: vis_rst -bit10: xtal -bit11: pll0 -bit12: pll1 -bit13: pll2 -bit14: pll3 -bit15: pll4 - 0 - 18 - read-write - - - - - RETENTION_CPU1_SET - Retention Contol - 0x934 - 32 - 0x00000000 - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - RETENTION_CPU1_CLEAR - Retention Contol - 0x938 - 32 - 0x00000000 - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - RETENTION_CPU1_TOGGLE - Retention Contol - 0x93c - 32 - 0x00000000 - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - POWER_CPU0_STATUS - Power Setting - 0x1000 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - POWER_CPU0_LF_WAIT - Power Setting - 0x1004 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_CPU0_OFF_WAIT - Power Setting - 0x100c - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_CPU1_STATUS - Power Setting - 0x1010 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - POWER_CPU1_LF_WAIT - Power Setting - 0x1014 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_CPU1_OFF_WAIT - Power Setting - 0x101c - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_CON_STATUS - Power Setting - 0x1020 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - POWER_CON_LF_WAIT - Power Setting - 0x1024 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_CON_OFF_WAIT - Power Setting - 0x102c - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_VIS_STATUS - Power Setting - 0x1030 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - POWER_VIS_LF_WAIT - Power Setting - 0x1034 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - POWER_VIS_OFF_WAIT - Power Setting - 0x103c - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - RESET_SOC_CONTROL - Reset Setting - 0x1400 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - RESET_SOC_CONFIG - Reset Setting - 0x1404 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - RESET_SOC_COUNTER - Reset Setting - 0x140c - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - RESET_CON_CONTROL - Reset Setting - 0x1410 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - RESET_CON_CONFIG - Reset Setting - 0x1414 - 32 - 0x00000064 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - RESET_CON_COUNTER - Reset Setting - 0x141c - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - RESET_VIS_CONTROL - Reset Setting - 0x1420 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - RESET_VIS_CONFIG - Reset Setting - 0x1424 - 32 - 0x00000064 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - RESET_VIS_COUNTER - Reset Setting - 0x142c - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - RESET_CPU0_CONTROL - Reset Setting - 0x1430 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - RESET_CPU0_CONFIG - Reset Setting - 0x1434 - 32 - 0x00000064 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - RESET_CPU0_COUNTER - Reset Setting - 0x143c - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - RESET_CPU1_CONTROL - Reset Setting - 0x1440 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - RESET_CPU1_CONFIG - Reset Setting - 0x1444 - 32 - 0x00000064 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - RESET_CPU1_COUNTER - Reset Setting - 0x144c - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - CLOCK_CLK_TOP_CPU0 - Clock setting - 0x1800 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_MCHTMR0 - Clock setting - 0x1804 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CPU1 - Clock setting - 0x1808 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_MCHTMR - Clock setting - 0x180c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_AXI - Clock setting - 0x1810 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CONN - Clock setting - 0x1814 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_VIS - Clock setting - 0x1818 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_AHB - Clock setting - 0x181c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_DRAM - Clock setting - 0x1820 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_XPI0 - Clock setting - 0x1824 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_XPI1 - Clock setting - 0x1828 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR0 - Clock setting - 0x182c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR1 - Clock setting - 0x1830 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR2 - Clock setting - 0x1834 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR3 - Clock setting - 0x1838 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR4 - Clock setting - 0x183c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR5 - Clock setting - 0x1840 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR6 - Clock setting - 0x1844 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_GPTMR7 - Clock setting - 0x1848 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART0 - Clock setting - 0x184c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART1 - Clock setting - 0x1850 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART2 - Clock setting - 0x1854 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART3 - Clock setting - 0x1858 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART4 - Clock setting - 0x185c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART5 - Clock setting - 0x1860 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART6 - Clock setting - 0x1864 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART7 - Clock setting - 0x1868 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART8 - Clock setting - 0x186c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART9 - Clock setting - 0x1870 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART10 - Clock setting - 0x1874 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART11 - Clock setting - 0x1878 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART12 - Clock setting - 0x187c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART13 - Clock setting - 0x1880 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART14 - Clock setting - 0x1884 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_UART15 - Clock setting - 0x1888 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C0 - Clock setting - 0x188c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C1 - Clock setting - 0x1890 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C2 - Clock setting - 0x1894 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_I2C3 - Clock setting - 0x1898 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI0 - Clock setting - 0x189c - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI1 - Clock setting - 0x18a0 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI2 - Clock setting - 0x18a4 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SPI3 - Clock setting - 0x18a8 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAN0 - Clock setting - 0x18ac - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAN1 - Clock setting - 0x18b0 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAN2 - Clock setting - 0x18b4 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAN3 - Clock setting - 0x18b8 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_PTPC - Clock setting - 0x18bc - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ANA0 - Clock setting - 0x18c0 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ANA1 - Clock setting - 0x18c4 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ANA2 - Clock setting - 0x18c8 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_AUD0 - Clock setting - 0x18cc - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_AUD1 - Clock setting - 0x18d0 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_AUD2 - Clock setting - 0x18d4 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_LCDC - Clock setting - 0x18d8 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAM0 - Clock setting - 0x18dc - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_CAM1 - Clock setting - 0x18e0 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ENET0 - Clock setting - 0x18e4 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_ENET1 - Clock setting - 0x18e8 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_PTP0 - Clock setting - 0x18ec - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_PTP1 - Clock setting - 0x18f0 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_REF0 - Clock setting - 0x18f4 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_REF1 - Clock setting - 0x18f8 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_NTMR0 - Clock setting - 0x18fc - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_NTMR1 - Clock setting - 0x1900 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SDXC0 - Clock setting - 0x1904 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - CLOCK_CLK_TOP_SDXC1 - Clock setting - 0x1908 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - ADCCLK_CLK_TOP_ADC0 - Clock setting - 0x1c00 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: adc clock 0 -2: adc clock 1 -3: adc clock 2 - 8 - 3 - read-write - - - - - ADCCLK_CLK_TOP_ADC1 - Clock setting - 0x1c04 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: adc clock 0 -2: adc clock 1 -3: adc clock 2 - 8 - 3 - read-write - - - - - ADCCLK_CLK_TOP_ADC2 - Clock setting - 0x1c08 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: adc clock 0 -2: adc clock 1 -3: adc clock 2 - 8 - 3 - read-write - - - - - ADCCLK_CLK_TOP_ADC3 - Clock setting - 0x1c0c - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: adc clock 0 -2: adc clock 1 -3: adc clock 2 - 8 - 3 - read-write - - - - - I2SCLK_CLK_TOP_I2S0 - Clock setting - 0x1c10 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: i2s clock 0 -2: i2s clock 1 -3: i2s clock 2 - 8 - 3 - read-write - - - - - I2SCLK_CLK_TOP_I2S1 - Clock setting - 0x1c14 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: i2s clock 0 -2: i2s clock 1 -3: i2s clock 2 - 8 - 3 - read-write - - - - - I2SCLK_CLK_TOP_I2S2 - Clock setting - 0x1c18 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: i2s clock 0 -2: i2s clock 1 -3: i2s clock 2 - 8 - 3 - read-write - - - - - I2SCLK_CLK_TOP_I2S3 - Clock setting - 0x1c1c - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: i2s clock 0 -2: i2s clock 1 -3: i2s clock 2 - 8 - 3 - read-write - - - - - GLOBAL00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - PRESET - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 - 0 - 4 - read-write - - - - - MONITOR_SLICE0_CONTROL - Clock measure and monitor control - 0x2400 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE0_CURRENT - Clock measure result - 0x2404 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE0_LOW_LIMIT - Clock lower limit - 0x2408 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE0_HIGH_LIMIT - Clock upper limit - 0x240c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE1_CONTROL - Clock measure and monitor control - 0x2420 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE1_CURRENT - Clock measure result - 0x2424 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE1_LOW_LIMIT - Clock lower limit - 0x2428 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE1_HIGH_LIMIT - Clock upper limit - 0x242c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE2_CONTROL - Clock measure and monitor control - 0x2440 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE2_CURRENT - Clock measure result - 0x2444 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE2_LOW_LIMIT - Clock lower limit - 0x2448 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE2_HIGH_LIMIT - Clock upper limit - 0x244c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE3_CONTROL - Clock measure and monitor control - 0x2460 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - MONITOR_SLICE3_CURRENT - Clock measure result - 0x2464 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - MONITOR_SLICE3_LOW_LIMIT - Clock lower limit - 0x2468 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - MONITOR_SLICE3_HIGH_LIMIT - Clock upper limit - 0x246c - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - CPU_CPU0_LP - No description avaiable - 0x2800 - 32 - 0x00001200 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter saturated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wakeup happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - CPU_CPU0_LOCK - No description avaiable - 0x2804 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - CPU_CPU0_GPR0 - No description avaiable - 0x2808 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR1 - No description avaiable - 0x280c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR2 - No description avaiable - 0x2810 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR3 - No description avaiable - 0x2814 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR4 - No description avaiable - 0x2818 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR5 - No description avaiable - 0x281c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR6 - No description avaiable - 0x2820 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR7 - No description avaiable - 0x2824 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR8 - No description avaiable - 0x2828 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR9 - No description avaiable - 0x282c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR10 - No description avaiable - 0x2830 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR11 - No description avaiable - 0x2834 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR12 - No description avaiable - 0x2838 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_GPR13 - No description avaiable - 0x283c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU0_STATUS0 - No description avaiable - 0x2840 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS1 - No description avaiable - 0x2844 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS2 - No description avaiable - 0x2848 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS3 - No description avaiable - 0x284c - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS4 - No description avaiable - 0x2850 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS5 - No description avaiable - 0x2854 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS6 - No description avaiable - 0x2858 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_STATUS7 - No description avaiable - 0x285c - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU0_ENABLE0 - No description avaiable - 0x2880 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE1 - No description avaiable - 0x2884 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE2 - No description avaiable - 0x2888 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE3 - No description avaiable - 0x288c - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE4 - No description avaiable - 0x2890 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE5 - No description avaiable - 0x2894 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE6 - No description avaiable - 0x2898 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU0_ENABLE7 - No description avaiable - 0x289c - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_LP - No description avaiable - 0x2c00 - 32 - 0x00001200 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter saturated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wakeup happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - CPU_CPU1_LOCK - No description avaiable - 0x2c04 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - CPU_CPU1_GPR0 - No description avaiable - 0x2c08 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR1 - No description avaiable - 0x2c0c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR2 - No description avaiable - 0x2c10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR3 - No description avaiable - 0x2c14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR4 - No description avaiable - 0x2c18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR5 - No description avaiable - 0x2c1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR6 - No description avaiable - 0x2c20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR7 - No description avaiable - 0x2c24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR8 - No description avaiable - 0x2c28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR9 - No description avaiable - 0x2c2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR10 - No description avaiable - 0x2c30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR11 - No description avaiable - 0x2c34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR12 - No description avaiable - 0x2c38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_GPR13 - No description avaiable - 0x2c3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - CPU_CPU1_STATUS0 - No description avaiable - 0x2c40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_STATUS1 - No description avaiable - 0x2c44 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_STATUS2 - No description avaiable - 0x2c48 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_STATUS3 - No description avaiable - 0x2c4c - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_STATUS4 - No description avaiable - 0x2c50 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_STATUS5 - No description avaiable - 0x2c54 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_STATUS6 - No description avaiable - 0x2c58 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_STATUS7 - No description avaiable - 0x2c5c - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - CPU_CPU1_ENABLE0 - No description avaiable - 0x2c80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_ENABLE1 - No description avaiable - 0x2c84 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_ENABLE2 - No description avaiable - 0x2c88 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_ENABLE3 - No description avaiable - 0x2c8c - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_ENABLE4 - No description avaiable - 0x2c90 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_ENABLE5 - No description avaiable - 0x2c94 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_ENABLE6 - No description avaiable - 0x2c98 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - CPU_CPU1_ENABLE7 - No description avaiable - 0x2c9c - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf64 - registers - - - - PAD_PA00_FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA00_PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA01_FUNC_CTL - ALT SELECT - 0x8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA01_PAD_CTL - PAD SETTINGS - 0xc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA02_FUNC_CTL - ALT SELECT - 0x10 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA02_PAD_CTL - PAD SETTINGS - 0x14 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA03_FUNC_CTL - ALT SELECT - 0x18 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA03_PAD_CTL - PAD SETTINGS - 0x1c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA04_FUNC_CTL - ALT SELECT - 0x20 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA04_PAD_CTL - PAD SETTINGS - 0x24 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA05_FUNC_CTL - ALT SELECT - 0x28 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA05_PAD_CTL - PAD SETTINGS - 0x2c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA06_FUNC_CTL - ALT SELECT - 0x30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA06_PAD_CTL - PAD SETTINGS - 0x34 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA07_FUNC_CTL - ALT SELECT - 0x38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA07_PAD_CTL - PAD SETTINGS - 0x3c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA08_FUNC_CTL - ALT SELECT - 0x40 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA08_PAD_CTL - PAD SETTINGS - 0x44 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA09_FUNC_CTL - ALT SELECT - 0x48 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA09_PAD_CTL - PAD SETTINGS - 0x4c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA10_FUNC_CTL - ALT SELECT - 0x50 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA10_PAD_CTL - PAD SETTINGS - 0x54 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA11_FUNC_CTL - ALT SELECT - 0x58 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA11_PAD_CTL - PAD SETTINGS - 0x5c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA12_FUNC_CTL - ALT SELECT - 0x60 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA12_PAD_CTL - PAD SETTINGS - 0x64 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA13_FUNC_CTL - ALT SELECT - 0x68 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA13_PAD_CTL - PAD SETTINGS - 0x6c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA14_FUNC_CTL - ALT SELECT - 0x70 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA14_PAD_CTL - PAD SETTINGS - 0x74 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA15_FUNC_CTL - ALT SELECT - 0x78 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA15_PAD_CTL - PAD SETTINGS - 0x7c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA16_FUNC_CTL - ALT SELECT - 0x80 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA16_PAD_CTL - PAD SETTINGS - 0x84 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA17_FUNC_CTL - ALT SELECT - 0x88 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA17_PAD_CTL - PAD SETTINGS - 0x8c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA18_FUNC_CTL - ALT SELECT - 0x90 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA18_PAD_CTL - PAD SETTINGS - 0x94 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA19_FUNC_CTL - ALT SELECT - 0x98 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA19_PAD_CTL - PAD SETTINGS - 0x9c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA20_FUNC_CTL - ALT SELECT - 0xa0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA20_PAD_CTL - PAD SETTINGS - 0xa4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA21_FUNC_CTL - ALT SELECT - 0xa8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA21_PAD_CTL - PAD SETTINGS - 0xac - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA22_FUNC_CTL - ALT SELECT - 0xb0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA22_PAD_CTL - PAD SETTINGS - 0xb4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA23_FUNC_CTL - ALT SELECT - 0xb8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA23_PAD_CTL - PAD SETTINGS - 0xbc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA24_FUNC_CTL - ALT SELECT - 0xc0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA24_PAD_CTL - PAD SETTINGS - 0xc4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA25_FUNC_CTL - ALT SELECT - 0xc8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA25_PAD_CTL - PAD SETTINGS - 0xcc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA26_FUNC_CTL - ALT SELECT - 0xd0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA26_PAD_CTL - PAD SETTINGS - 0xd4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA27_FUNC_CTL - ALT SELECT - 0xd8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA27_PAD_CTL - PAD SETTINGS - 0xdc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA28_FUNC_CTL - ALT SELECT - 0xe0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA28_PAD_CTL - PAD SETTINGS - 0xe4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA29_FUNC_CTL - ALT SELECT - 0xe8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA29_PAD_CTL - PAD SETTINGS - 0xec - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA30_FUNC_CTL - ALT SELECT - 0xf0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA30_PAD_CTL - PAD SETTINGS - 0xf4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PA31_FUNC_CTL - ALT SELECT - 0xf8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PA31_PAD_CTL - PAD SETTINGS - 0xfc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB00_FUNC_CTL - ALT SELECT - 0x100 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB00_PAD_CTL - PAD SETTINGS - 0x104 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB01_FUNC_CTL - ALT SELECT - 0x108 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB01_PAD_CTL - PAD SETTINGS - 0x10c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB02_FUNC_CTL - ALT SELECT - 0x110 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB02_PAD_CTL - PAD SETTINGS - 0x114 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB03_FUNC_CTL - ALT SELECT - 0x118 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB03_PAD_CTL - PAD SETTINGS - 0x11c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB04_FUNC_CTL - ALT SELECT - 0x120 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB04_PAD_CTL - PAD SETTINGS - 0x124 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB05_FUNC_CTL - ALT SELECT - 0x128 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB05_PAD_CTL - PAD SETTINGS - 0x12c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB06_FUNC_CTL - ALT SELECT - 0x130 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB06_PAD_CTL - PAD SETTINGS - 0x134 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB07_FUNC_CTL - ALT SELECT - 0x138 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB07_PAD_CTL - PAD SETTINGS - 0x13c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB08_FUNC_CTL - ALT SELECT - 0x140 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB08_PAD_CTL - PAD SETTINGS - 0x144 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB09_FUNC_CTL - ALT SELECT - 0x148 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB09_PAD_CTL - PAD SETTINGS - 0x14c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB10_FUNC_CTL - ALT SELECT - 0x150 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB10_PAD_CTL - PAD SETTINGS - 0x154 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB11_FUNC_CTL - ALT SELECT - 0x158 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB11_PAD_CTL - PAD SETTINGS - 0x15c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB12_FUNC_CTL - ALT SELECT - 0x160 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB12_PAD_CTL - PAD SETTINGS - 0x164 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB13_FUNC_CTL - ALT SELECT - 0x168 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB13_PAD_CTL - PAD SETTINGS - 0x16c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB14_FUNC_CTL - ALT SELECT - 0x170 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB14_PAD_CTL - PAD SETTINGS - 0x174 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB15_FUNC_CTL - ALT SELECT - 0x178 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB15_PAD_CTL - PAD SETTINGS - 0x17c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB16_FUNC_CTL - ALT SELECT - 0x180 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB16_PAD_CTL - PAD SETTINGS - 0x184 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB17_FUNC_CTL - ALT SELECT - 0x188 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB17_PAD_CTL - PAD SETTINGS - 0x18c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB18_FUNC_CTL - ALT SELECT - 0x190 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB18_PAD_CTL - PAD SETTINGS - 0x194 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB19_FUNC_CTL - ALT SELECT - 0x198 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB19_PAD_CTL - PAD SETTINGS - 0x19c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB20_FUNC_CTL - ALT SELECT - 0x1a0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB20_PAD_CTL - PAD SETTINGS - 0x1a4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB21_FUNC_CTL - ALT SELECT - 0x1a8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB21_PAD_CTL - PAD SETTINGS - 0x1ac - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB22_FUNC_CTL - ALT SELECT - 0x1b0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB22_PAD_CTL - PAD SETTINGS - 0x1b4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB23_FUNC_CTL - ALT SELECT - 0x1b8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB23_PAD_CTL - PAD SETTINGS - 0x1bc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB24_FUNC_CTL - ALT SELECT - 0x1c0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB24_PAD_CTL - PAD SETTINGS - 0x1c4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB25_FUNC_CTL - ALT SELECT - 0x1c8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB25_PAD_CTL - PAD SETTINGS - 0x1cc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB26_FUNC_CTL - ALT SELECT - 0x1d0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB26_PAD_CTL - PAD SETTINGS - 0x1d4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB27_FUNC_CTL - ALT SELECT - 0x1d8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB27_PAD_CTL - PAD SETTINGS - 0x1dc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB28_FUNC_CTL - ALT SELECT - 0x1e0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB28_PAD_CTL - PAD SETTINGS - 0x1e4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB29_FUNC_CTL - ALT SELECT - 0x1e8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB29_PAD_CTL - PAD SETTINGS - 0x1ec - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB30_FUNC_CTL - ALT SELECT - 0x1f0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB30_PAD_CTL - PAD SETTINGS - 0x1f4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PB31_FUNC_CTL - ALT SELECT - 0x1f8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PB31_PAD_CTL - PAD SETTINGS - 0x1fc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC00_FUNC_CTL - ALT SELECT - 0x200 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC00_PAD_CTL - PAD SETTINGS - 0x204 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC01_FUNC_CTL - ALT SELECT - 0x208 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC01_PAD_CTL - PAD SETTINGS - 0x20c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC02_FUNC_CTL - ALT SELECT - 0x210 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC02_PAD_CTL - PAD SETTINGS - 0x214 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC03_FUNC_CTL - ALT SELECT - 0x218 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC03_PAD_CTL - PAD SETTINGS - 0x21c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC04_FUNC_CTL - ALT SELECT - 0x220 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC04_PAD_CTL - PAD SETTINGS - 0x224 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC05_FUNC_CTL - ALT SELECT - 0x228 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC05_PAD_CTL - PAD SETTINGS - 0x22c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC06_FUNC_CTL - ALT SELECT - 0x230 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC06_PAD_CTL - PAD SETTINGS - 0x234 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC07_FUNC_CTL - ALT SELECT - 0x238 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC07_PAD_CTL - PAD SETTINGS - 0x23c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC08_FUNC_CTL - ALT SELECT - 0x240 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC08_PAD_CTL - PAD SETTINGS - 0x244 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC09_FUNC_CTL - ALT SELECT - 0x248 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC09_PAD_CTL - PAD SETTINGS - 0x24c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC10_FUNC_CTL - ALT SELECT - 0x250 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC10_PAD_CTL - PAD SETTINGS - 0x254 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC11_FUNC_CTL - ALT SELECT - 0x258 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC11_PAD_CTL - PAD SETTINGS - 0x25c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC12_FUNC_CTL - ALT SELECT - 0x260 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC12_PAD_CTL - PAD SETTINGS - 0x264 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC13_FUNC_CTL - ALT SELECT - 0x268 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC13_PAD_CTL - PAD SETTINGS - 0x26c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC14_FUNC_CTL - ALT SELECT - 0x270 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC14_PAD_CTL - PAD SETTINGS - 0x274 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC15_FUNC_CTL - ALT SELECT - 0x278 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC15_PAD_CTL - PAD SETTINGS - 0x27c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC16_FUNC_CTL - ALT SELECT - 0x280 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC16_PAD_CTL - PAD SETTINGS - 0x284 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC17_FUNC_CTL - ALT SELECT - 0x288 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC17_PAD_CTL - PAD SETTINGS - 0x28c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC18_FUNC_CTL - ALT SELECT - 0x290 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC18_PAD_CTL - PAD SETTINGS - 0x294 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC19_FUNC_CTL - ALT SELECT - 0x298 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC19_PAD_CTL - PAD SETTINGS - 0x29c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC20_FUNC_CTL - ALT SELECT - 0x2a0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC20_PAD_CTL - PAD SETTINGS - 0x2a4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC21_FUNC_CTL - ALT SELECT - 0x2a8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC21_PAD_CTL - PAD SETTINGS - 0x2ac - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC22_FUNC_CTL - ALT SELECT - 0x2b0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC22_PAD_CTL - PAD SETTINGS - 0x2b4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC23_FUNC_CTL - ALT SELECT - 0x2b8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC23_PAD_CTL - PAD SETTINGS - 0x2bc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC24_FUNC_CTL - ALT SELECT - 0x2c0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC24_PAD_CTL - PAD SETTINGS - 0x2c4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC25_FUNC_CTL - ALT SELECT - 0x2c8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC25_PAD_CTL - PAD SETTINGS - 0x2cc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC26_FUNC_CTL - ALT SELECT - 0x2d0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC26_PAD_CTL - PAD SETTINGS - 0x2d4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC27_FUNC_CTL - ALT SELECT - 0x2d8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC27_PAD_CTL - PAD SETTINGS - 0x2dc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC28_FUNC_CTL - ALT SELECT - 0x2e0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC28_PAD_CTL - PAD SETTINGS - 0x2e4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC29_FUNC_CTL - ALT SELECT - 0x2e8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC29_PAD_CTL - PAD SETTINGS - 0x2ec - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC30_FUNC_CTL - ALT SELECT - 0x2f0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC30_PAD_CTL - PAD SETTINGS - 0x2f4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PC31_FUNC_CTL - ALT SELECT - 0x2f8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PC31_PAD_CTL - PAD SETTINGS - 0x2fc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD00_FUNC_CTL - ALT SELECT - 0x300 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD00_PAD_CTL - PAD SETTINGS - 0x304 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD01_FUNC_CTL - ALT SELECT - 0x308 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD01_PAD_CTL - PAD SETTINGS - 0x30c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD02_FUNC_CTL - ALT SELECT - 0x310 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD02_PAD_CTL - PAD SETTINGS - 0x314 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD03_FUNC_CTL - ALT SELECT - 0x318 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD03_PAD_CTL - PAD SETTINGS - 0x31c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD04_FUNC_CTL - ALT SELECT - 0x320 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD04_PAD_CTL - PAD SETTINGS - 0x324 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD05_FUNC_CTL - ALT SELECT - 0x328 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD05_PAD_CTL - PAD SETTINGS - 0x32c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD06_FUNC_CTL - ALT SELECT - 0x330 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD06_PAD_CTL - PAD SETTINGS - 0x334 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD07_FUNC_CTL - ALT SELECT - 0x338 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD07_PAD_CTL - PAD SETTINGS - 0x33c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD08_FUNC_CTL - ALT SELECT - 0x340 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD08_PAD_CTL - PAD SETTINGS - 0x344 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD09_FUNC_CTL - ALT SELECT - 0x348 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD09_PAD_CTL - PAD SETTINGS - 0x34c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD10_FUNC_CTL - ALT SELECT - 0x350 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD10_PAD_CTL - PAD SETTINGS - 0x354 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD11_FUNC_CTL - ALT SELECT - 0x358 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD11_PAD_CTL - PAD SETTINGS - 0x35c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD12_FUNC_CTL - ALT SELECT - 0x360 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD12_PAD_CTL - PAD SETTINGS - 0x364 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD13_FUNC_CTL - ALT SELECT - 0x368 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD13_PAD_CTL - PAD SETTINGS - 0x36c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD14_FUNC_CTL - ALT SELECT - 0x370 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD14_PAD_CTL - PAD SETTINGS - 0x374 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD15_FUNC_CTL - ALT SELECT - 0x378 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD15_PAD_CTL - PAD SETTINGS - 0x37c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD16_FUNC_CTL - ALT SELECT - 0x380 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD16_PAD_CTL - PAD SETTINGS - 0x384 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD17_FUNC_CTL - ALT SELECT - 0x388 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD17_PAD_CTL - PAD SETTINGS - 0x38c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD18_FUNC_CTL - ALT SELECT - 0x390 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD18_PAD_CTL - PAD SETTINGS - 0x394 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD19_FUNC_CTL - ALT SELECT - 0x398 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD19_PAD_CTL - PAD SETTINGS - 0x39c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD20_FUNC_CTL - ALT SELECT - 0x3a0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD20_PAD_CTL - PAD SETTINGS - 0x3a4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD21_FUNC_CTL - ALT SELECT - 0x3a8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD21_PAD_CTL - PAD SETTINGS - 0x3ac - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD22_FUNC_CTL - ALT SELECT - 0x3b0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD22_PAD_CTL - PAD SETTINGS - 0x3b4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD23_FUNC_CTL - ALT SELECT - 0x3b8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD23_PAD_CTL - PAD SETTINGS - 0x3bc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD24_FUNC_CTL - ALT SELECT - 0x3c0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD24_PAD_CTL - PAD SETTINGS - 0x3c4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD25_FUNC_CTL - ALT SELECT - 0x3c8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD25_PAD_CTL - PAD SETTINGS - 0x3cc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD26_FUNC_CTL - ALT SELECT - 0x3d0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD26_PAD_CTL - PAD SETTINGS - 0x3d4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD27_FUNC_CTL - ALT SELECT - 0x3d8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD27_PAD_CTL - PAD SETTINGS - 0x3dc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD28_FUNC_CTL - ALT SELECT - 0x3e0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD28_PAD_CTL - PAD SETTINGS - 0x3e4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD29_FUNC_CTL - ALT SELECT - 0x3e8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD29_PAD_CTL - PAD SETTINGS - 0x3ec - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD30_FUNC_CTL - ALT SELECT - 0x3f0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD30_PAD_CTL - PAD SETTINGS - 0x3f4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PD31_FUNC_CTL - ALT SELECT - 0x3f8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PD31_PAD_CTL - PAD SETTINGS - 0x3fc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE00_FUNC_CTL - ALT SELECT - 0x400 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE00_PAD_CTL - PAD SETTINGS - 0x404 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE01_FUNC_CTL - ALT SELECT - 0x408 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE01_PAD_CTL - PAD SETTINGS - 0x40c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE02_FUNC_CTL - ALT SELECT - 0x410 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE02_PAD_CTL - PAD SETTINGS - 0x414 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE03_FUNC_CTL - ALT SELECT - 0x418 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE03_PAD_CTL - PAD SETTINGS - 0x41c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE04_FUNC_CTL - ALT SELECT - 0x420 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE04_PAD_CTL - PAD SETTINGS - 0x424 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE05_FUNC_CTL - ALT SELECT - 0x428 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE05_PAD_CTL - PAD SETTINGS - 0x42c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE06_FUNC_CTL - ALT SELECT - 0x430 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE06_PAD_CTL - PAD SETTINGS - 0x434 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE07_FUNC_CTL - ALT SELECT - 0x438 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE07_PAD_CTL - PAD SETTINGS - 0x43c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE08_FUNC_CTL - ALT SELECT - 0x440 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE08_PAD_CTL - PAD SETTINGS - 0x444 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE09_FUNC_CTL - ALT SELECT - 0x448 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE09_PAD_CTL - PAD SETTINGS - 0x44c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE10_FUNC_CTL - ALT SELECT - 0x450 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE10_PAD_CTL - PAD SETTINGS - 0x454 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE11_FUNC_CTL - ALT SELECT - 0x458 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE11_PAD_CTL - PAD SETTINGS - 0x45c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE12_FUNC_CTL - ALT SELECT - 0x460 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE12_PAD_CTL - PAD SETTINGS - 0x464 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE13_FUNC_CTL - ALT SELECT - 0x468 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE13_PAD_CTL - PAD SETTINGS - 0x46c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE14_FUNC_CTL - ALT SELECT - 0x470 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE14_PAD_CTL - PAD SETTINGS - 0x474 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE15_FUNC_CTL - ALT SELECT - 0x478 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE15_PAD_CTL - PAD SETTINGS - 0x47c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE16_FUNC_CTL - ALT SELECT - 0x480 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE16_PAD_CTL - PAD SETTINGS - 0x484 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE17_FUNC_CTL - ALT SELECT - 0x488 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE17_PAD_CTL - PAD SETTINGS - 0x48c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE18_FUNC_CTL - ALT SELECT - 0x490 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE18_PAD_CTL - PAD SETTINGS - 0x494 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE19_FUNC_CTL - ALT SELECT - 0x498 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE19_PAD_CTL - PAD SETTINGS - 0x49c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE20_FUNC_CTL - ALT SELECT - 0x4a0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE20_PAD_CTL - PAD SETTINGS - 0x4a4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE21_FUNC_CTL - ALT SELECT - 0x4a8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE21_PAD_CTL - PAD SETTINGS - 0x4ac - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE22_FUNC_CTL - ALT SELECT - 0x4b0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE22_PAD_CTL - PAD SETTINGS - 0x4b4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE23_FUNC_CTL - ALT SELECT - 0x4b8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE23_PAD_CTL - PAD SETTINGS - 0x4bc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE24_FUNC_CTL - ALT SELECT - 0x4c0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE24_PAD_CTL - PAD SETTINGS - 0x4c4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE25_FUNC_CTL - ALT SELECT - 0x4c8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE25_PAD_CTL - PAD SETTINGS - 0x4cc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE26_FUNC_CTL - ALT SELECT - 0x4d0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE26_PAD_CTL - PAD SETTINGS - 0x4d4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE27_FUNC_CTL - ALT SELECT - 0x4d8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE27_PAD_CTL - PAD SETTINGS - 0x4dc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE28_FUNC_CTL - ALT SELECT - 0x4e0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE28_PAD_CTL - PAD SETTINGS - 0x4e4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE29_FUNC_CTL - ALT SELECT - 0x4e8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE29_PAD_CTL - PAD SETTINGS - 0x4ec - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE30_FUNC_CTL - ALT SELECT - 0x4f0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE30_PAD_CTL - PAD SETTINGS - 0x4f4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PE31_FUNC_CTL - ALT SELECT - 0x4f8 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PE31_PAD_CTL - PAD SETTINGS - 0x4fc - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF00_FUNC_CTL - ALT SELECT - 0x500 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF00_PAD_CTL - PAD SETTINGS - 0x504 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF01_FUNC_CTL - ALT SELECT - 0x508 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF01_PAD_CTL - PAD SETTINGS - 0x50c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF02_FUNC_CTL - ALT SELECT - 0x510 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF02_PAD_CTL - PAD SETTINGS - 0x514 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF03_FUNC_CTL - ALT SELECT - 0x518 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF03_PAD_CTL - PAD SETTINGS - 0x51c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF04_FUNC_CTL - ALT SELECT - 0x520 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF04_PAD_CTL - PAD SETTINGS - 0x524 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF05_FUNC_CTL - ALT SELECT - 0x528 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF05_PAD_CTL - PAD SETTINGS - 0x52c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF06_FUNC_CTL - ALT SELECT - 0x530 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF06_PAD_CTL - PAD SETTINGS - 0x534 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF07_FUNC_CTL - ALT SELECT - 0x538 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF07_PAD_CTL - PAD SETTINGS - 0x53c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF08_FUNC_CTL - ALT SELECT - 0x540 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF08_PAD_CTL - PAD SETTINGS - 0x544 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF09_FUNC_CTL - ALT SELECT - 0x548 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF09_PAD_CTL - PAD SETTINGS - 0x54c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PF10_FUNC_CTL - ALT SELECT - 0x550 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PF10_PAD_CTL - PAD SETTINGS - 0x554 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX00_FUNC_CTL - ALT SELECT - 0xd00 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX00_PAD_CTL - PAD SETTINGS - 0xd04 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX01_FUNC_CTL - ALT SELECT - 0xd08 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX01_PAD_CTL - PAD SETTINGS - 0xd0c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX02_FUNC_CTL - ALT SELECT - 0xd10 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX02_PAD_CTL - PAD SETTINGS - 0xd14 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX03_FUNC_CTL - ALT SELECT - 0xd18 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX03_PAD_CTL - PAD SETTINGS - 0xd1c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX04_FUNC_CTL - ALT SELECT - 0xd20 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX04_PAD_CTL - PAD SETTINGS - 0xd24 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX05_FUNC_CTL - ALT SELECT - 0xd28 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX05_PAD_CTL - PAD SETTINGS - 0xd2c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX06_FUNC_CTL - ALT SELECT - 0xd30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX06_PAD_CTL - PAD SETTINGS - 0xd34 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX07_FUNC_CTL - ALT SELECT - 0xd38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX07_PAD_CTL - PAD SETTINGS - 0xd3c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX08_FUNC_CTL - ALT SELECT - 0xd40 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX08_PAD_CTL - PAD SETTINGS - 0xd44 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX09_FUNC_CTL - ALT SELECT - 0xd48 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX09_PAD_CTL - PAD SETTINGS - 0xd4c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX10_FUNC_CTL - ALT SELECT - 0xd50 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX10_PAD_CTL - PAD SETTINGS - 0xd54 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PX11_FUNC_CTL - ALT SELECT - 0xd58 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PX11_PAD_CTL - PAD SETTINGS - 0xd5c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY00_FUNC_CTL - ALT SELECT - 0xe00 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY00_PAD_CTL - PAD SETTINGS - 0xe04 - 32 - 0x00001110 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY01_FUNC_CTL - ALT SELECT - 0xe08 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY01_PAD_CTL - PAD SETTINGS - 0xe0c - 32 - 0x00001110 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY02_FUNC_CTL - ALT SELECT - 0xe10 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY02_PAD_CTL - PAD SETTINGS - 0xe14 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY03_FUNC_CTL - ALT SELECT - 0xe18 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY03_PAD_CTL - PAD SETTINGS - 0xe1c - 32 - 0x00001110 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY04_FUNC_CTL - ALT SELECT - 0xe20 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY04_PAD_CTL - PAD SETTINGS - 0xe24 - 32 - 0x00001110 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY05_FUNC_CTL - ALT SELECT - 0xe28 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY05_PAD_CTL - PAD SETTINGS - 0xe2c - 32 - 0x00001000 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY06_FUNC_CTL - ALT SELECT - 0xe30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY06_PAD_CTL - PAD SETTINGS - 0xe34 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY07_FUNC_CTL - ALT SELECT - 0xe38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY07_PAD_CTL - PAD SETTINGS - 0xe3c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY08_FUNC_CTL - ALT SELECT - 0xe40 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY08_PAD_CTL - PAD SETTINGS - 0xe44 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY09_FUNC_CTL - ALT SELECT - 0xe48 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY09_PAD_CTL - PAD SETTINGS - 0xe4c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY10_FUNC_CTL - ALT SELECT - 0xe50 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY10_PAD_CTL - PAD SETTINGS - 0xe54 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PY11_FUNC_CTL - ALT SELECT - 0xe58 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PY11_PAD_CTL - PAD SETTINGS - 0xe5c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ00_FUNC_CTL - ALT SELECT - 0xf00 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ00_PAD_CTL - PAD SETTINGS - 0xf04 - 32 - 0x00001100 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ01_FUNC_CTL - ALT SELECT - 0xf08 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ01_PAD_CTL - PAD SETTINGS - 0xf0c - 32 - 0x00001110 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ02_FUNC_CTL - ALT SELECT - 0xf10 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ02_PAD_CTL - PAD SETTINGS - 0xf14 - 32 - 0x00001110 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ03_FUNC_CTL - ALT SELECT - 0xf18 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ03_PAD_CTL - PAD SETTINGS - 0xf1c - 32 - 0x00001110 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ04_FUNC_CTL - ALT SELECT - 0xf20 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ04_PAD_CTL - PAD SETTINGS - 0xf24 - 32 - 0x00003000 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ05_FUNC_CTL - ALT SELECT - 0xf28 - 32 - 0x00000001 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ05_PAD_CTL - PAD SETTINGS - 0xf2c - 32 - 0x00003000 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ06_FUNC_CTL - ALT SELECT - 0xf30 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ06_PAD_CTL - PAD SETTINGS - 0xf34 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ07_FUNC_CTL - ALT SELECT - 0xf38 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ07_PAD_CTL - PAD SETTINGS - 0xf3c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ08_FUNC_CTL - ALT SELECT - 0xf40 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ08_PAD_CTL - PAD SETTINGS - 0xf44 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ09_FUNC_CTL - ALT SELECT - 0xf48 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ09_PAD_CTL - PAD SETTINGS - 0xf4c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ10_FUNC_CTL - ALT SELECT - 0xf50 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ10_PAD_CTL - PAD SETTINGS - 0xf54 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - PAD_PZ11_FUNC_CTL - ALT SELECT - 0xf58 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_PZ11_PAD_CTL - PAD SETTINGS - 0xf5c - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only avaiable in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - - - PIOC - PIOC - IOC - 0xf40d8000 - - - BIOC - BIOC - IOC - 0xf5010000 - - - OTPSHW - OTPSHW - OTP - 0xf4080000 - - 0x0 - 0xc08 - registers - - - - SHADOW_SHADOW000 - Fuse shadow registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW001 - Fuse shadow registers - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW002 - Fuse shadow registers - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW003 - Fuse shadow registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW004 - Fuse shadow registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW005 - Fuse shadow registers - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW006 - Fuse shadow registers - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW007 - Fuse shadow registers - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW008 - Fuse shadow registers - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW009 - Fuse shadow registers - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW010 - Fuse shadow registers - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW011 - Fuse shadow registers - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW012 - Fuse shadow registers - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW013 - Fuse shadow registers - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW014 - Fuse shadow registers - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW015 - Fuse shadow registers - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW016 - Fuse shadow registers - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW017 - Fuse shadow registers - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW018 - Fuse shadow registers - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW019 - Fuse shadow registers - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW020 - Fuse shadow registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW021 - Fuse shadow registers - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW022 - Fuse shadow registers - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW023 - Fuse shadow registers - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW024 - Fuse shadow registers - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW025 - Fuse shadow registers - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW026 - Fuse shadow registers - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW027 - Fuse shadow registers - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW028 - Fuse shadow registers - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW029 - Fuse shadow registers - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW030 - Fuse shadow registers - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW031 - Fuse shadow registers - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW032 - Fuse shadow registers - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW033 - Fuse shadow registers - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW034 - Fuse shadow registers - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW035 - Fuse shadow registers - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW036 - Fuse shadow registers - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW037 - Fuse shadow registers - 0x94 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW038 - Fuse shadow registers - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW039 - Fuse shadow registers - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW040 - Fuse shadow registers - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW041 - Fuse shadow registers - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW042 - Fuse shadow registers - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW043 - Fuse shadow registers - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW044 - Fuse shadow registers - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW045 - Fuse shadow registers - 0xb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW046 - Fuse shadow registers - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW047 - Fuse shadow registers - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW048 - Fuse shadow registers - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW049 - Fuse shadow registers - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW050 - Fuse shadow registers - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW051 - Fuse shadow registers - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW052 - Fuse shadow registers - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW053 - Fuse shadow registers - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW054 - Fuse shadow registers - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW055 - Fuse shadow registers - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW056 - Fuse shadow registers - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW057 - Fuse shadow registers - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW058 - Fuse shadow registers - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW059 - Fuse shadow registers - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW060 - Fuse shadow registers - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW061 - Fuse shadow registers - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW062 - Fuse shadow registers - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW063 - Fuse shadow registers - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW064 - Fuse shadow registers - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW065 - Fuse shadow registers - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW066 - Fuse shadow registers - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW067 - Fuse shadow registers - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW068 - Fuse shadow registers - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW069 - Fuse shadow registers - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW070 - Fuse shadow registers - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW071 - Fuse shadow registers - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW072 - Fuse shadow registers - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW073 - Fuse shadow registers - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW074 - Fuse shadow registers - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW075 - Fuse shadow registers - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW076 - Fuse shadow registers - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW077 - Fuse shadow registers - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW078 - Fuse shadow registers - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW079 - Fuse shadow registers - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW080 - Fuse shadow registers - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW081 - Fuse shadow registers - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW082 - Fuse shadow registers - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW083 - Fuse shadow registers - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW084 - Fuse shadow registers - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW085 - Fuse shadow registers - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW086 - Fuse shadow registers - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW087 - Fuse shadow registers - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW088 - Fuse shadow registers - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW089 - Fuse shadow registers - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW090 - Fuse shadow registers - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW091 - Fuse shadow registers - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW092 - Fuse shadow registers - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW093 - Fuse shadow registers - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW094 - Fuse shadow registers - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW095 - Fuse shadow registers - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW096 - Fuse shadow registers - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW097 - Fuse shadow registers - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW098 - Fuse shadow registers - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW099 - Fuse shadow registers - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW100 - Fuse shadow registers - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW101 - Fuse shadow registers - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW102 - Fuse shadow registers - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW103 - Fuse shadow registers - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW104 - Fuse shadow registers - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW105 - Fuse shadow registers - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW106 - Fuse shadow registers - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW107 - Fuse shadow registers - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW108 - Fuse shadow registers - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW109 - Fuse shadow registers - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW110 - Fuse shadow registers - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW111 - Fuse shadow registers - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW112 - Fuse shadow registers - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW113 - Fuse shadow registers - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW114 - Fuse shadow registers - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW115 - Fuse shadow registers - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW116 - Fuse shadow registers - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW117 - Fuse shadow registers - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW118 - Fuse shadow registers - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW119 - Fuse shadow registers - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW120 - Fuse shadow registers - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW121 - Fuse shadow registers - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW122 - Fuse shadow registers - 0x1e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW123 - Fuse shadow registers - 0x1ec - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW124 - Fuse shadow registers - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW125 - Fuse shadow registers - 0x1f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW126 - Fuse shadow registers - 0x1f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_SHADOW127 - Fuse shadow registers - 0x1fc - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK00 - Fuse shadow lock - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK01 - Fuse shadow lock - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK02 - Fuse shadow lock - 0x208 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK03 - Fuse shadow lock - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK04 - Fuse shadow lock - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK05 - Fuse shadow lock - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK06 - Fuse shadow lock - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - SHADOW_LOCK_LOCK07 - Fuse shadow lock - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_FUSE000 - Fuse Array - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE001 - Fuse Array - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE002 - Fuse Array - 0x408 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE003 - Fuse Array - 0x40c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE004 - Fuse Array - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE005 - Fuse Array - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE006 - Fuse Array - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE007 - Fuse Array - 0x41c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE008 - Fuse Array - 0x420 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE009 - Fuse Array - 0x424 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE010 - Fuse Array - 0x428 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE011 - Fuse Array - 0x42c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE012 - Fuse Array - 0x430 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE013 - Fuse Array - 0x434 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE014 - Fuse Array - 0x438 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE015 - Fuse Array - 0x43c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE016 - Fuse Array - 0x440 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE017 - Fuse Array - 0x444 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE018 - Fuse Array - 0x448 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE019 - Fuse Array - 0x44c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE020 - Fuse Array - 0x450 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE021 - Fuse Array - 0x454 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE022 - Fuse Array - 0x458 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE023 - Fuse Array - 0x45c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE024 - Fuse Array - 0x460 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE025 - Fuse Array - 0x464 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE026 - Fuse Array - 0x468 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE027 - Fuse Array - 0x46c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE028 - Fuse Array - 0x470 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE029 - Fuse Array - 0x474 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE030 - Fuse Array - 0x478 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE031 - Fuse Array - 0x47c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE032 - Fuse Array - 0x480 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE033 - Fuse Array - 0x484 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE034 - Fuse Array - 0x488 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE035 - Fuse Array - 0x48c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE036 - Fuse Array - 0x490 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE037 - Fuse Array - 0x494 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE038 - Fuse Array - 0x498 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE039 - Fuse Array - 0x49c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE040 - Fuse Array - 0x4a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE041 - Fuse Array - 0x4a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE042 - Fuse Array - 0x4a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE043 - Fuse Array - 0x4ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE044 - Fuse Array - 0x4b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE045 - Fuse Array - 0x4b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE046 - Fuse Array - 0x4b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE047 - Fuse Array - 0x4bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE048 - Fuse Array - 0x4c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE049 - Fuse Array - 0x4c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE050 - Fuse Array - 0x4c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE051 - Fuse Array - 0x4cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE052 - Fuse Array - 0x4d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE053 - Fuse Array - 0x4d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE054 - Fuse Array - 0x4d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE055 - Fuse Array - 0x4dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE056 - Fuse Array - 0x4e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE057 - Fuse Array - 0x4e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE058 - Fuse Array - 0x4e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE059 - Fuse Array - 0x4ec - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE060 - Fuse Array - 0x4f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE061 - Fuse Array - 0x4f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE062 - Fuse Array - 0x4f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE063 - Fuse Array - 0x4fc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE064 - Fuse Array - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE065 - Fuse Array - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE066 - Fuse Array - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE067 - Fuse Array - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE068 - Fuse Array - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE069 - Fuse Array - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE070 - Fuse Array - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE071 - Fuse Array - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE072 - Fuse Array - 0x520 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE073 - Fuse Array - 0x524 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE074 - Fuse Array - 0x528 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE075 - Fuse Array - 0x52c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE076 - Fuse Array - 0x530 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE077 - Fuse Array - 0x534 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE078 - Fuse Array - 0x538 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE079 - Fuse Array - 0x53c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE080 - Fuse Array - 0x540 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE081 - Fuse Array - 0x544 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE082 - Fuse Array - 0x548 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE083 - Fuse Array - 0x54c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE084 - Fuse Array - 0x550 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE085 - Fuse Array - 0x554 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE086 - Fuse Array - 0x558 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE087 - Fuse Array - 0x55c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE088 - Fuse Array - 0x560 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE089 - Fuse Array - 0x564 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE090 - Fuse Array - 0x568 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE091 - Fuse Array - 0x56c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE092 - Fuse Array - 0x570 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE093 - Fuse Array - 0x574 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE094 - Fuse Array - 0x578 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE095 - Fuse Array - 0x57c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE096 - Fuse Array - 0x580 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE097 - Fuse Array - 0x584 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE098 - Fuse Array - 0x588 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE099 - Fuse Array - 0x58c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE100 - Fuse Array - 0x590 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE101 - Fuse Array - 0x594 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE102 - Fuse Array - 0x598 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE103 - Fuse Array - 0x59c - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE104 - Fuse Array - 0x5a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE105 - Fuse Array - 0x5a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE106 - Fuse Array - 0x5a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE107 - Fuse Array - 0x5ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE108 - Fuse Array - 0x5b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE109 - Fuse Array - 0x5b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE110 - Fuse Array - 0x5b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE111 - Fuse Array - 0x5bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE112 - Fuse Array - 0x5c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE113 - Fuse Array - 0x5c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE114 - Fuse Array - 0x5c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE115 - Fuse Array - 0x5cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE116 - Fuse Array - 0x5d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE117 - Fuse Array - 0x5d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE118 - Fuse Array - 0x5d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE119 - Fuse Array - 0x5dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE120 - Fuse Array - 0x5e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE121 - Fuse Array - 0x5e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE122 - Fuse Array - 0x5e8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE123 - Fuse Array - 0x5ec - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE124 - Fuse Array - 0x5f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE125 - Fuse Array - 0x5f4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE126 - Fuse Array - 0x5f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_FUSE127 - Fuse Array - 0x5fc - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK00 - Fuse lock - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK01 - Fuse lock - 0x604 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK02 - Fuse lock - 0x608 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK03 - Fuse lock - 0x60c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK04 - Fuse lock - 0x610 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK05 - Fuse lock - 0x614 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK06 - Fuse lock - 0x618 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - FUSE_LOCK_LOCK07 - Fuse lock - 0x61c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - REGION_LOAD_REGION0 - LOAD region - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - REGION_LOAD_REGION1 - LOAD region - 0xa24 - 32 - 0x00001008 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - REGION_LOAD_REGION2 - LOAD region - 0xa28 - 32 - 0x00000010 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - REGION_LOAD_REGION3 - LOAD region - 0xa2c - 32 - 0x00000000 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf40c8000 - - - PPOR - PPOR - PPOR - 0xf40c0000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOT - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_COLD - reset type attribute - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PMU - 0xf40c4000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0001044C - 0x00010FFF - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x00B010B0 - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: trun off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00B010B0 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000000 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-write - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - ouput over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x00EF1C6E - 0x073F007F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_AUTOLP - enable auto enter low power mode -0: do not enter low power mode -1: enter low power mode if current is detected low - 4 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00EF1C6E - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: clock gated according to low power flow -10: clock is always off -11: clock is always on -bit0-1: fuse -bit2-3: sram -bit4-5: vad -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:debug - 0 - 32 - read-write - - - - - DEBUG_STOP - Debug stop config - 0x50 - 32 - 0x00000001 - 0x00000003 - - - CPU1 - Stop peripheral when CPU1 enter debug mode -0: peripheral keep running when CPU1 in debug mode -1: peripheral enter debug mode when CPU1 enter debug - 1 - 1 - read-write - - - CPU0 - Stop peripheral when CPU0 enter debug mode -0: peripheral keep running when CPU0 in debug mode -1: peripheral enter debug mode when CPU0 enter debug - 0 - 1 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000316 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PSEC - PSEC - PSEC - 0xf40cc000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf40d0000 - - 0x0 - 0x48 - registers - - - - MONITOR_GLITCH0_CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_GLITCH0_STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_GLITCH1_CONTROL - Glitch and clock monitor control - 0x8 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_GLITCH1_STATUS - Glitch and clock monitor status - 0xc - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_CONTROL - Glitch and clock monitor control - 0x10 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_STATUS - Glitch and clock monitor status - 0x14 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_CLOCK1_CONTROL - Glitch and clock monitor control - 0x18 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_CLOCK1_STATUS - Glitch and clock monitor status - 0x1c - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - IRQ_FLAG - No description avaiable - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description avaiable - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - PGPR - PGPR - PGPR - 0xf40d4000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - VAD - VAD - VAD - 0xf40ec000 - - 0x0 - 0xa4 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x0FF7FBFF - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 24 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 20 - 4 - read-write - - - VAD_IE - VAD event interrupt enable - 18 - 1 - read-write - - - OFIFO_AV_IE - OFIFO data available interrupt enable - 17 - 1 - read-write - - - MEMBUF_EMPTY_IE - Buf empty interrupt enable - 16 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - OFIFO overflow error interrupt enable - 15 - 1 - read-write - - - IIR_OVLD_ERR_IE - IIR overload error interrupt enable - 14 - 1 - read-write - - - IIR_OVFL_ERR_IE - IIR overflow error interrupt enable - 13 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload Interrupt Enable - 12 - 1 - read-write - - - CIC_SAT_ERR_IE - CIC saturation Interrupt Enable - 11 - 1 - read-write - - - MEMBUF_DISABLE - asserted to disable membuf - 9 - 1 - read-write - - - FIFO_THRSH - OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) - 5 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 4 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 3 - 1 - read-write - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 1 - 2 - read-write - - - CHNUM - the number of channels to be stored in buffer. Asserted to enable 2 channels. - 0 - 1 - read-write - - - - - FILTCTRL - Filter Control Register - 0x4 - 32 - 0x00000000 - 0x000007FF - - - DECRATIO - the decimation ratio of iir after CIC -1 -2: means dec-by-3 - 8 - 3 - read-write - - - IIR_SLOT_EN - IIR slot enable - 0 - 8 - read-write - - - - - DEC_CTRL0 - Decision Control Register 0 - 0x8 - 32 - 0x00000000 - 0xFFFF03FF - - - NOISE_TOL - the value of amplitude for noise determination when calculationg ZCR - 16 - 16 - read-write - - - BLK_CFG - asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks - 9 - 1 - read-write - - - SUBBLK_LEN - length of sub-block - 0 - 9 - read-write - - - - - DEC_CTRL1 - Decision Control Register 1 - 0xc - 32 - 0x00000000 - 0x003FFFFF - - - ZCR_HIGH - ZCR high limit - 11 - 11 - read-write - - - ZCR_LOW - ZCR low limit - 0 - 11 - read-write - - - - - DEC_CTRL2 - Decision Control Register 2 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - AMP_HIGH - amplitude high limit - 16 - 16 - read-write - - - AMP_LOW - amplitude low limit - 0 - 16 - read-write - - - - - ST - Status - 0x18 - 32 - 0x00000000 - 0x000000FF - - - VAD - VAD event found - 7 - 1 - read-write - - - OFIFO_AV - OFIFO data available - 6 - 1 - read-only - - - MEMBUF_EMPTY - Buf empty - 5 - 1 - read-write - - - OFIFO_OVFL - OFIFO overflow - 4 - 1 - read-write - - - IIR_OVLD - IIR overloading - 3 - 1 - read-write - - - IIR_OVFL - IIR oberflow - 2 - 1 - read-write - - - CIC_OVLD_ERR - CIC overload - 1 - 1 - read-write - - - CIC_SAT_ERR - CIC saturation - 0 - 1 - read-write - - - - - OFIFO - Out FIFO - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - The PCM data. -When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). -When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). - 0 - 32 - read-write - - - - - RUN - Run Command Register - 0x20 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - software reset. Self-clear - 1 - 1 - read-write - - - VAD_EN - module enable - 0 - 1 - read-write - - - - - OFIFO_CTRL - Out FIFO Control Register - 0x24 - 32 - 0x00000000 - 0x00000001 - - - EN - Asserted to enable OFIFO - 0 - 1 - read-write - - - - - CIC_CFG - CIC Configuration Register - 0x28 - 32 - 0x00000000 - 0x0000FC00 - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - - - COEF_STE_ACT - Short Time Energy Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The current detected short time energy - 0 - 32 - read-only - - - - - - - PLLCTL - PLLCTL - PLLCTL - 0xf4100000 - - 0x0 - 0x344 - registers - - - - XTAL - Crystal control and status - 0x0 - 32 - 0x00000000 - 0x300FFFFF - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of IRC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - PLL_PLL0_CFG0 - PLLx config0 - 0x80 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description avaiable - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description avaiable - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - PLL_PLL0_CFG1 - PLLx config1 - 0x84 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - PLL_PLL0_CFG2 - PLLx config2 - 0x88 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - PLL_PLL0_FREQ - PLLx frac mode frequency adjust - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - PLL_PLL0_LOCK - PLLx lock control - 0x90 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - PLL_PLL0_STATUS - PLLx status - 0xa0 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description avaiable - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description avaiable - 0 - 1 - read-only - - - - - PLL_PLL0_DIV0 - PLLx divider0 control - 0xc0 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL0_DIV1 - PLLx divider1 control - 0xc4 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL1_CFG0 - PLLx config0 - 0x100 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description avaiable - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description avaiable - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - PLL_PLL1_CFG1 - PLLx config1 - 0x104 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - PLL_PLL1_CFG2 - PLLx config2 - 0x108 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - PLL_PLL1_FREQ - PLLx frac mode frequency adjust - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - PLL_PLL1_LOCK - PLLx lock control - 0x110 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - PLL_PLL1_STATUS - PLLx status - 0x120 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description avaiable - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description avaiable - 0 - 1 - read-only - - - - - PLL_PLL1_DIV0 - PLLx divider0 control - 0x140 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL1_DIV1 - PLLx divider1 control - 0x144 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL2_CFG0 - PLLx config0 - 0x180 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description avaiable - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description avaiable - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - PLL_PLL2_CFG1 - PLLx config1 - 0x184 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - PLL_PLL2_CFG2 - PLLx config2 - 0x188 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - PLL_PLL2_FREQ - PLLx frac mode frequency adjust - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - PLL_PLL2_LOCK - PLLx lock control - 0x190 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - PLL_PLL2_STATUS - PLLx status - 0x1a0 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description avaiable - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description avaiable - 0 - 1 - read-only - - - - - PLL_PLL2_DIV0 - PLLx divider0 control - 0x1c0 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL2_DIV1 - PLLx divider1 control - 0x1c4 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL3_CFG0 - PLLx config0 - 0x200 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description avaiable - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description avaiable - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - PLL_PLL3_CFG1 - PLLx config1 - 0x204 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - PLL_PLL3_CFG2 - PLLx config2 - 0x208 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - PLL_PLL3_FREQ - PLLx frac mode frequency adjust - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - PLL_PLL3_LOCK - PLLx lock control - 0x210 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - PLL_PLL3_STATUS - PLLx status - 0x220 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description avaiable - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description avaiable - 0 - 1 - read-only - - - - - PLL_PLL3_DIV0 - PLLx divider0 control - 0x240 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL3_DIV1 - PLLx divider1 control - 0x244 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL4_CFG0 - PLLx config0 - 0x280 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description avaiable - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description avaiable - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - PLL_PLL4_CFG1 - PLLx config1 - 0x284 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - PLL_PLL4_CFG2 - PLLx config2 - 0x288 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - PLL_PLL4_FREQ - PLLx frac mode frequency adjust - 0x28c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - PLL_PLL4_LOCK - PLLx lock control - 0x290 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - PLL_PLL4_STATUS - PLLx status - 0x2a0 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description avaiable - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description avaiable - 0 - 1 - read-only - - - - - PLL_PLL4_DIV0 - PLLx divider0 control - 0x2c0 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - PLL_PLL4_DIV1 - PLLx divider1 control - 0x2c4 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - - - BPOR - BPOR - BPOR - 0xf5004000 - - 0x0 - 0x10 - registers - - - - POR_CAUSE - Power on cause - 0x0 - 32 - 0x00000000 - 0x0000001F - - - CAUSE - Power on cause, each bit represnts one cause, write 1 to clear each bit -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_SELECT - Power on select - 0x4 - 32 - 0x00000000 - 0x0000001F - - - SELECT - Power on cause select, each bit represnts one cause, value 1 enables corresponding cause -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_CONFIG - Power on reset config - 0x8 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - POR_CONTROL - Power down control - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - COUNTER - Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - 0 - 16 - read-write - - - - - - - BCFG - BCFG - TRIM - 0xf5008000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LP_MODE - Bandgap works in low power mode -0: not in low power mode -1: bandgap work in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - LDO_CFG - LDO config - 0x4 - 32 - 0x00010000 - 0x03370FFF - - - RES_TRIM - Resistor trim - 24 - 2 - read-write - - - CP_TRIM - Capacitor trim - 20 - 2 - read-write - - - EN_SL - enable selfload, this bit helps improve LDO performance when current less than 200nA -0: self load disabled -1: selfload enabled - 18 - 1 - read-write - - - DIS_PD - disable pull down resistor, enable pull down may lead to more power but better response -0: pulldown resistor enabled -1: pulldown resistor disabled - 17 - 1 - read-write - - - ENABLE - LDO enable -0: LDO is disabled -1: LDO is enabled - 16 - 1 - read-write - - - VOLT - LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. -600: 600mV -620: 620mV -. . . -1100:1100mV - 0 - 12 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf500c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf5018000 - - 0x0 - 0x20 - registers - - - - BATT_GPR0 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR1 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR2 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR3 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR4 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR5 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR6 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR7 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - RTCSHW - RTCSHW - RTC - 0xf501c000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - RTC - RTC - RTC - 0xf5044000 - - - BSEC - BSEC - BSEC - 0xf5040000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - BKEY - BKEY - BKEY - 0xf5048000 - - 0x0 - 0x4c - registers - - - - KEY_0_DATA_0 - Key data - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_1 - Key data - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_2 - Key data - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_3 - Key data - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_4 - Key data - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_5 - Key data - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_6 - Key data - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_0_DATA_7 - Key data - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_0 - Key data - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_1 - Key data - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_2 - Key data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_3 - Key data - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_4 - Key data - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_5 - Key data - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_6 - Key data - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - KEY_1_DATA_7 - Key data - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - ECC_KEY0 - Key ECC and access control - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - ECC_KEY1 - Key 1 ECC and access control - 0x44 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf504c000 - - 0x0 - 0x1c - registers - - - - MONITOR_GLITCH0_CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_GLITCH0_STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_CONTROL - Glitch and clock monitor control - 0x10 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destory DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - MONITOR_CLOCK0_STATUS - Glitch and clock monitor status - 0x14 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - TAMP - TAMP - TAMP - 0xf5050000 - - 0x0 - 0x88 - registers - - - - TAMP_TAMP0_CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP0_POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP0_LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP1_CONTROL - Tamper1 control - 0x10 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP1_POLY - Tamper1 Polynomial of LFSR - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP1_LFSR - Tamper1 LFSR shift register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP2_CONTROL - Tamper2 control - 0x20 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP2_POLY - Tamper2 Polynomial of LFSR - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP2_LFSR - Tamper2 LFSR shift register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP3_CONTROL - Tamper3 control - 0x30 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP3_POLY - Tamper3 Polynomial of LFSR - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP3_LFSR - Tamper3 LFSR shift register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP4_CONTROL - Tamper4 control - 0x40 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP4_POLY - Tamper4 Polynomial of LFSR - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP4_LFSR - Tamper4 LFSR shift register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_TAMP5_CONTROL - Tamper5 control - 0x50 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - TAMP_TAMP5_POLY - Tamper5 Polynomial of LFSR - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - TAMP_TAMP5_LFSR - Tamper5 LFSR shift register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disapeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf5054000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/SConscript index 985fd5d7e6..5717c3e631 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/SConscript +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/SConscript @@ -15,6 +15,7 @@ src = Split(''' hpm_l1c_drv.c hpm_sysctl_drv.c hpm_clock_drv.c + hpm_otp_drv.c boot/hpm_bootheader.c ''') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c index 30c2edc202..57cdf5aa2e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h index c2bf30d0b0..d7f22fd824 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h new file mode 100644 index 0000000000..4b8d483194 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ACMP_SOC_DRV_H +#define HPM_ACMP_SOC_DRV_H + +#include "hpm_soc.h" + +static inline void acmp_enable_bandgap(void) +{ + uint32_t clk_div_temp; + + clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(HPM_ADC3->CONV_CFG1); + + /* Set input clock divider temporarily */ + HPM_ADC3->CONV_CFG1 = (HPM_ADC3->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Enable ADC config clock */ + HPM_ADC3->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Enable bandgap_en */ + HPM_ADC3->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK; + + /* Recover input clock divider */ + HPM_ADC3->CONV_CFG1 = (HPM_ADC3->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); + + /* Disable ADC config clock */ + HPM_ADC3->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; +} + +#endif /* HPM_ACMP_SOC_DRV_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h index 8d6e337a35..1d3c6eb0c4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -78,4 +78,4 @@ #define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#endif /* HPM_BATT_IOMUX_H */ \ No newline at end of file +#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_drv.h new file mode 100644 index 0000000000..7f5a005ef6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_drv.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BCFG_DRV_H +#define HPM_BCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_bcfg_regs.h" + +/** + * + * @brief BCFG driver APIs + * @defgroup bcfg_interface BCFG driver APIs + * @ingroup io_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief disable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief enable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +/** + * @brief disable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +/** + * @brief set ldo voltage + * + * @param[in] ptr base address + * @param[in] voltage target voltage + */ +static inline void bcfg_ldo_set_voltage(BCFG_Type *ptr, uint16_t voltage) +{ + ptr->LDO_CFG = (ptr->LDO_CFG & ~(BCFG_LDO_CFG_VOLT_MASK)) | BCFG_LDO_CFG_VOLT_SET(voltage); +} + +/** + * @brief enable ldo + * + * @param[in] ptr base address + */ +static inline void bcfg_ldo_enable(BCFG_Type *ptr) +{ + ptr->LDO_CFG |= BCFG_LDO_CFG_ENABLE_MASK; +} + +/** + * @brief disable ldo + * + * @param[in] ptr base address + */ +static inline void bcfg_ldo_disable(BCFG_Type *ptr) +{ + ptr->LDO_CFG &= ~BCFG_LDO_CFG_ENABLE_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BCFG_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h similarity index 99% rename from bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h rename to bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h index 69b89729ec..07e8001cd0 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -273,4 +273,4 @@ typedef struct { -#endif /* HPM_BCFG_H */ \ No newline at end of file +#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h new file mode 100644 index 0000000000..46bb7beb07 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BGPR_H +#define HPM_BGPR_H + +typedef struct { + __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ + __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ + __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ + __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ + __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ + __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ + __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ + __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ +} BGPR_Type; + + +/* Bitfield definition for register: BATT_GPR0 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR0_GPR_SHIFT (0U) +#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) +#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR1 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR1_GPR_SHIFT (0U) +#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) +#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR2 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR2_GPR_SHIFT (0U) +#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) +#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR3 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR3_GPR_SHIFT (0U) +#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) +#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR4 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR4_GPR_SHIFT (0U) +#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) +#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR5 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR5_GPR_SHIFT (0U) +#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) +#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR6 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR6_GPR_SHIFT (0U) +#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) +#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR7 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR7_GPR_SHIFT (0U) +#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) +#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) + + + + +#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_drv.h new file mode 100644 index 0000000000..e37bac24b1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_drv.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BPOR_DRV_H +#define HPM_BPOR_DRV_H + +#include "hpm_common.h" +#include "hpm_bpor_regs.h" + +/** + * + * @brief BPOR driver APIs + * @defgroup bpor_interface BPOR driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +/** @brief Define BPOR power on cause */ +typedef enum { + bpor_power_on_cause_wbutn = 1 << 0, + bpor_power_on_cause_safety_violation = 1 << 1, + bpor_power_on_cause_rtc_0 = 1 << 2, + bpor_power_on_cause_rtc_1 = 1 << 3, + bpor_power_on_cause_gpio = 1 << 4 +} bpor_power_on_cause_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get power on cause + * + * @param[in] ptr BPOR base address + * @retval POR_CAUSE register value + */ +static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) +{ + return ptr->POR_CAUSE; +} + +/** + * @brief Clear power on cause + * + * @param[in] ptr BPOR base address + * @param[in] mask cause status to be cleared + */ +static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) +{ + ptr->POR_CAUSE |= mask; +} + +/** + * @brief enable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be enabled + */ +static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT |= cause; +} + +/** + * @brief disable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be disabled + */ +static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT &= ~cause; +} + +/** + * @brief Set power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be used + */ +static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) +{ + ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; +} + +/** + * @brief Enable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Disable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Set power down counter + * + * @param[in] ptr BPOR base address + * @param[in] counter counter value + */ +static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) +{ + ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h new file mode 100644 index 0000000000..32147d05a2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BPOR_H +#define HPM_BPOR_H + +typedef struct { + __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ + __RW uint32_t POR_SELECT; /* 0x4: Power on select */ + __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ + __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ +} BPOR_Type; + + +/* Bitfield definition for register: POR_CAUSE */ +/* + * CAUSE (RW) + * + * Power on cause, each bit represnts one cause, write 1 to clear each bit + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) +#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) +#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) +#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: POR_SELECT */ +/* + * SELECT (RW) + * + * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) +#define BPOR_POR_SELECT_SELECT_SHIFT (0U) +#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) +#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) + +/* Bitfield definition for register: POR_CONFIG */ +/* + * RETENTION (RW) + * + * retention battery domain setting + * 0: battery reset on reset pin reset happen + * 1: battery domain retention when reset pin reset happen + */ +#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) +#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) +#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) +#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) + +/* Bitfield definition for register: POR_CONTROL */ +/* + * COUNTER (RW) + * + * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + */ +#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) +#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) +#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) +#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) + + + + +#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c index 0c4736ff5d..9e897fef0e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,8 +9,7 @@ #include "hpm_clock_drv.h" #include "hpm_sysctl_drv.h" #include "hpm_pllctl_drv.h" -#include "hpm_csr_regs.h" -#include "riscv/riscv_core.h" + /*********************************************************************************************************************** * Definitions **********************************************************************************************************************/ @@ -64,7 +63,7 @@ static uint32_t get_frequency_for_wdg(uint32_t instance); */ static void switch_ip_clock(clock_name_t clock_name, bool on); -static uint64_t get_core_mcycle(void); +static uint64_t hpm_csr_get_core_cycle(void); /*********************************************************************************************************************** * Variables @@ -330,7 +329,7 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); return status_success; } @@ -350,7 +349,7 @@ hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); HPM_SYSCTL->I2SCLK[node_or_instance] = - (HPM_SYSCTL->I2SCLK[node_or_instance] & SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); + (HPM_SYSCTL->I2SCLK[node_or_instance] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); return status_success; } @@ -472,35 +471,19 @@ void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) } } - -static uint64_t get_core_mcycle(void) -{ - uint64_t result; - uint32_t resultl_first = read_csr(CSR_CYCLE); - uint32_t resulth = read_csr(CSR_CYCLEH); - uint32_t resultl_second = read_csr(CSR_CYCLE); - if (resultl_first < resultl_second) { - result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ - } else { - resulth = read_csr(CSR_CYCLEH); - result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ - } - return result; - } - void clock_cpu_delay_us(uint32_t us) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } void clock_cpu_delay_ms(uint32_t ms) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } @@ -509,4 +492,4 @@ void clock_update_core_clock(void) uint32_t hart_id = read_csr(CSR_MHARTID); clock_name_t cpu_clk_name = (hart_id == 1U) ? clock_cpu1 : clock_cpu0; hpm_core_clock = clock_get_frequency(cpu_clk_name); -} \ No newline at end of file +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h index 4da5b1f1c5..23a46a75c4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #include "hpm_common.h" #include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" /** * @brief CLOCK driver APIs @@ -108,7 +109,7 @@ typedef enum _clock_name { clock_axi1 = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_COMMON, clock_node_axi1), clock_axi2 = MAKE_CLOCK_NAME(sysctl_resource_axiv, CLK_SRC_GROUP_COMMON, clock_node_axi2), clock_ahb = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_COMMON, clock_node_ahb0), - clock_dram = MAKE_CLOCK_NAME(sysctl_resource_dram, CLK_SRC_GROUP_COMMON, clock_node_dram), + clock_femc = MAKE_CLOCK_NAME(sysctl_resource_femc, CLK_SRC_GROUP_COMMON, clock_node_femc), clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), clock_xpi1 = MAKE_CLOCK_NAME(sysctl_resource_xpi1, CLK_SRC_GROUP_COMMON, clock_node_xpi1), clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h index 72f6fb746f..cc29018e11 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -6509,4 +6509,4 @@ #define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) -#endif /* HPM_CSR_H */ \ No newline at end of file +#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h new file mode 100644 index 0000000000..640355344e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_H +#define HPM_DMAMUX_H + +typedef struct { + __RW uint32_t MUXCFG[16]; /* 0x0 - 0x3C: HDMA MUX0 Configuration */ +} DMAMUX_Type; + + +/* Bitfield definition for register array: MUXCFG */ +/* + * ENABLE (RW) + * + * DMA Mux Channel Enable + * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be + * used to disable or reconfigure a DMA channel. + * 0b - DMA Mux channel is disabled + * 1b - DMA Mux channel is enabled + */ +#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) +#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) +#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) +#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) + +/* + * SOURCE (RW) + * + * DMA Channel Source + * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + */ +#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) +#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) +#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) + + + +/* MUXCFG register group index macro definition */ +#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) +#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) +#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) +#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) +#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) +#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) +#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) +#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) +#define DMAMUX_MUXCFG_XDMA_MUX0 (8UL) +#define DMAMUX_MUXCFG_XDMA_MUX1 (9UL) +#define DMAMUX_MUXCFG_XDMA_MUX2 (10UL) +#define DMAMUX_MUXCFG_XDMA_MUX3 (11UL) +#define DMAMUX_MUXCFG_XDMA_MUX4 (12UL) +#define DMAMUX_MUXCFG_XDMA_MUX5 (13UL) +#define DMAMUX_MUXCFG_XDMA_MUX6 (14UL) +#define DMAMUX_MUXCFG_XDMA_MUX7 (15UL) + + +#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h index 612b4d6e75..6f36ba007c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -129,4 +129,4 @@ -#endif /* HPM_DMAMUX_SRC_H */ \ No newline at end of file +#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h index 846a796630..18b35d6eb4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,16 +13,63 @@ extern "C" { #endif +static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK; + HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(inf_type); + } else if (ptr == HPM_ENET1) { + HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK; + HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(inf_type); + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK; + } else if (ptr == HPM_ENET1) { + HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK; + } else if (ptr == HPM_ENET1) { + HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) { hpm_stat_t stat = status_success; if (ptr == HPM_ENET0) { HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); - HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); + HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); } else if (ptr == HPM_ENET1) { HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK); - HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(rx_delay); + HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(rx_delay); } else { return status_invalid_argument; } @@ -75,24 +122,8 @@ static inline hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr) return stat; } -static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK; - HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(inf_type); - } else if (ptr == HPM_ENET1) { - HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK; - HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(inf_type); - } else { - return status_invalid_argument; - } - - return stat; -} #if defined __cplusplus } /* __cplusplus */ #endif -#endif /* HPM_ENET_SOC_DRV_H */ \ No newline at end of file +#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h index 4f4197eedf..1ec106d8af 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,10 +24,10 @@ typedef struct { * 0: fields can be changed * 1: fields locked to current value, not changeable */ -#define GPIOM_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_PIN_LOCK_SHIFT (31U) -#define GPIOM_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_PIN_LOCK_SHIFT) & GPIOM_PIN_LOCK_MASK) -#define GPIOM_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_PIN_LOCK_MASK) >> GPIOM_PIN_LOCK_SHIFT) +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) /* * HIDE (RW) @@ -38,10 +38,10 @@ typedef struct { * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio */ -#define GPIOM_PIN_HIDE_MASK (0xF00U) -#define GPIOM_PIN_HIDE_SHIFT (8U) -#define GPIOM_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_PIN_HIDE_SHIFT) & GPIOM_PIN_HIDE_MASK) -#define GPIOM_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_PIN_HIDE_MASK) >> GPIOM_PIN_HIDE_SHIFT) +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) /* * SELECT (RW) @@ -52,10 +52,10 @@ typedef struct { * 2: cpu0 fastgpio * 3: cpu1 fast gpio */ -#define GPIOM_PIN_SELECT_MASK (0x3U) -#define GPIOM_PIN_SELECT_SHIFT (0U) -#define GPIOM_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_PIN_SELECT_SHIFT) & GPIOM_PIN_SELECT_MASK) -#define GPIOM_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_PIN_SELECT_MASK) >> GPIOM_PIN_SELECT_SHIFT) +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) @@ -105,4 +105,4 @@ typedef struct { #define GPIOM_ASSIGN_GPIOZ (15UL) -#endif /* HPM_GPIOM_H */ \ No newline at end of file +#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h index 23e5140883..2d44d44cbb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h index e361b87730..a4271a4d94 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,6 +24,8 @@ extern "C" { #endif +/* Machine mode API: these APIs are supposed to be called at machine mode */ + /** * @brief Enable global IRQ with mask * @@ -35,13 +37,24 @@ ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) } /** - * @brief Disable global IRQ with mask + * @brief Disable global IRQ with mask and return mstatus * * @param[in] mask interrupt mask to be disabled + * @retval current mstatus value before irq mask is disabled */ -ATTR_ALWAYS_INLINE static inline void disable_global_irq(uint32_t mask) +ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) { - clear_csr(CSR_MSTATUS, mask); + return read_clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); } /** @@ -125,7 +138,6 @@ ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); } - /** * @brief Claim software interrupt * @@ -187,7 +199,7 @@ ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) do { \ intc_set_irq_priority(irq, priority); \ intc_m_enable_irq(irq); \ - } while(0); + } while (0) /* * @brief Enable specific interrupt @@ -259,7 +271,9 @@ ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_ /* * Vectored based irq install and uninstall */ +/* Machine mode */ extern int __vector_table[]; + extern void default_irq_entry(void); /** @@ -282,7 +296,7 @@ ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) */ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) { - __vector_table[irq] = (int)default_irq_entry; + __vector_table[irq] = (int) default_irq_entry; } /* @@ -301,7 +315,7 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) */ #define RESTORE_CSR(r) write_csr(r, __##r); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) #else @@ -326,71 +340,129 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) #endif #ifdef __riscv_flen -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP) + 21 FPU caller registers */ -#define CONTEXT_REG_NUM (4*(16 + 4 + 1 + 21)) +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */ +#define CONTEXT_REG_NUM (4*(16 + 4 + 20*2)) +#endif + #else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ -#define CONTEXT_REG_NUM (4*(16 + 4 + 1)) +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS */ +#define CONTEXT_REG_NUM (4 * (16 + 4)) #endif #ifdef __riscv_flen /* * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack */ +#if __riscv_flen == 32 #define SAVE_FPU_CONTEXT() { \ - __asm volatile("fsw ft0, 21*4(sp) \n\ - fsw ft1, 22*4(sp) \n\ - fsw ft2, 23*4(sp) \n\ - fsw ft3, 24*4(sp) \n\ - fsw ft4, 25*4(sp) \n\ - fsw ft5, 26*4(sp) \n\ - fsw ft6, 27*4(sp) \n\ - fsw ft7, 28*4(sp) \n\ - fsw fa0, 29*4(sp) \n\ - fsw fa1, 30*4(sp) \n\ - fsw fa2, 31*4(sp) \n\ - fsw fa3, 32*4(sp) \n\ - fsw fa4, 33*4(sp) \n\ - fsw fa5, 34*4(sp) \n\ - fsw fa6, 35*4(sp) \n\ - fsw fa7, 36*4(sp) \n\ - fsw ft8, 37*4(sp) \n\ - fsw ft9, 38*4(sp) \n\ - fsw ft10, 39*4(sp) \n\ - fsw ft11, 40*4(sp) \n\ - frsr t6 \n\ - sw t6, 41*4(sp) \n");\ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ } /* * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack */ #define RESTORE_FPU_CONTEXT() { \ - __asm volatile("flw ft0, 21*4(sp) \n\ - flw ft1, 22*4(sp) \n\ - flw ft2, 23*4(sp) \n\ - flw ft3, 24*4(sp) \n\ - flw ft4, 25*4(sp) \n\ - flw ft5, 26*4(sp) \n\ - flw ft6, 27*4(sp) \n\ - flw ft7, 28*4(sp) \n\ - flw fa0, 29*4(sp) \n\ - flw fa1, 30*4(sp) \n\ - flw fa2, 31*4(sp) \n\ - flw fa3, 32*4(sp) \n\ - flw fa4, 33*4(sp) \n\ - flw fa5, 34*4(sp) \n\ - flw fa6, 35*4(sp) \n\ - flw fa7, 36*4(sp) \n\ - flw ft8, 37*4(sp) \n\ - flw ft9, 38*4(sp) \n\ - flw ft10, 39*4(sp) \n\ - flw ft11, 40*4(sp) \n\ - lw t6, 41*4(sp) \n\ - fssr t6, t6 \n");\ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ } +#else /*__riscv_flen == 64*/ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif #else #define SAVE_FPU_CONTEXT() #define RESTORE_FPU_CONTEXT() @@ -401,66 +473,88 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) */ #define SAVE_CALLER_CONTEXT() { \ __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("sw ra, 0*4(sp) \n\ - sw t0, 1*4(sp) \n\ - sw t1, 2*4(sp) \n\ - sw t2, 3*4(sp) \n\ - sw a0, 4*4(sp) \n\ - sw a1, 5*4(sp) \n\ - sw a2, 6*4(sp) \n\ - sw a3, 7*4(sp) \n\ - sw a4, 8*4(sp) \n\ - sw a5, 9*4(sp) \n\ - sw a6, 10*4(sp) \n\ - sw a7, 11*4(sp) \n\ - sw t3, 12*4(sp) \n\ - sw t4, 13*4(sp) \n\ - sw t5, 14*4(sp) \n\ - sw t6, 15*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ } /** * @brief Restore the caller registers based on the RISC-V ABI specification */ #define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("lw ra, 0*4(sp) \n\ - lw t0, 1*4(sp) \n\ - lw t1, 2*4(sp) \n\ - lw t2, 3*4(sp) \n\ - lw a0, 4*4(sp) \n\ - lw a1, 5*4(sp) \n\ - lw a2, 6*4(sp) \n\ - lw a3, 7*4(sp) \n\ - lw a4, 8*4(sp) \n\ - lw a5, 9*4(sp) \n\ - lw a6, 10*4(sp) \n\ - lw a7, 11*4(sp) \n\ - lw t3, 12*4(sp) \n\ - lw t4, 13*4(sp) \n\ - lw t5, 14*4(sp) \n\ - lw t6, 15*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ } +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fssr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + #ifdef __riscv_dsp /* * Save DSP context - * NOTE: To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + * NOTE: DSP context registers are stored at word offset 41 in the stack */ #define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrr t6, ucode\n\ - sw t6, 20*4(sp)\n"); \ + __asm volatile("rdov s0\n"); \ } /* * @brief Restore DSP context - * @note To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + * @note DSP context registers are stored at word offset 41 in the stack */ #define RESTORE_DSP_CONTEXT() {\ - __asm volatile("lw t6, 20*4(sp)\n\ - csrw ucode, t6 \n"); \ + __asm volatile("csrw ucode, s0\n"); \ } + #else #define SAVE_DSP_CONTEXT() #define RESTORE_DSP_CONTEXT() @@ -474,31 +568,31 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) * MSTATUS = word offset 18 * MXSTATUS = word offset 19 */ -#define ENTER_NESTED_IRQ_HANDLING_M() {\ - __asm volatile("csrr t6, mepc \n\ - sw t6, 17*4(sp) \n\ - csrr t6, mstatus \n\ - sw t6, 18*4(sp) \n\ - csrr t6, %0\n\ - sw t6, 19*4(sp) \n\ - " : : "i" CSR_MSTATUS);\ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile("li t6, %0\n" : : "i" (CSR_MSTATUS_MIE_MASK)); \ - __asm volatile("csrrs t6, mstatus, t6\n"); \ + __asm volatile ("\n\ + c.li a5, 8\n\ + csrs mstatus, a5\n"); \ } -#define COMPLETE_IRQ_HANDLING_M(irq_num) {\ - __asm volatile("li t0, 0xe4000000 \n\ - li t1, 0x200004 \n\ - add t0, t0, t1 \n\ - lui t1, 0 \n\ - slli t2, t1, 0xc \n\ - add t0, t0, t2 \n");\ - __asm volatile("li t1, %0" : : "i" (irq_num) :); \ - __asm volatile("sw t1, 0(t0) \n\ - fence io, io \n\ - li t6, 1\n\ - addi t6, t6, -0x800\n\ - csrrs t6, mie, t6 \n"); \ + +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("\n\ + lui a5, 0x1\n\ + addi a5, a5, -2048\n\ + csrc mie, a5\n"); \ + __asm volatile("\n\ + lui a4, 0xe4200\n");\ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)\n\ + fence io, io\n"); \ + __asm volatile("csrs mie, a5"); \ } /* @@ -510,13 +604,10 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) * MXSTATUS = word offset 19 */ #define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("csrrci t6, mstatus, 8 \n\ - lw t6, 18*4(sp) \n\ - csrw mstatus, t6 \n\ - lw t6, 17*4(sp) \n\ - csrw mepc, t6 \n\ - lw t6, 19*4(sp) \n\ - csrw %0, t6 \n" : : "i" CSR_MSTATUS);\ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ RESTORE_DSP_CONTEXT(); \ } @@ -532,7 +623,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) /* @brief Nested IRQ exit macro : Restore CSRs */ #define NESTED_IRQ_EXIT() \ - clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); \ RESTORE_CSR(CSR_MSTATUS) \ RESTORE_CSR(CSR_MEPC) \ RESTORE_MXSTATUS() \ @@ -549,7 +639,7 @@ do { \ __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ __asm volatile("fence io, io"); \ set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ -} while(0) +} while (0) #ifdef __cplusplus #define HPM_EXTERN_C extern "C" @@ -568,13 +658,14 @@ do { \ #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ void isr(void) __attribute__((section(".isr_vector")));\ HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) {\ +void ISR_NAME_M(irq_num)(void) \ +{ \ SAVE_CALLER_CONTEXT(); \ ENTER_NESTED_IRQ_HANDLING_M();\ __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ __asm volatile("jalr t1\n");\ - EXIT_NESTED_IRQ_HANDLING_M();\ COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ __asm volatile("mret\n");\ } @@ -582,8 +673,9 @@ void ISR_NAME_M(irq_num)(void) {\ #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ void isr(void) __attribute__((section(".isr_vector")));\ HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) { \ - isr(); \ +void ISR_NAME_M(irq_num)(void) \ +{ \ + isr(); \ } #endif @@ -596,7 +688,8 @@ void ISR_NAME_M(irq_num)(void) { \ #define SDK_DECLARE_MCHTMR_ISR(isr) \ void isr(void) __attribute__((section(".isr_vector")));\ HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) {\ +void mchtmr_isr(void) \ +{ \ isr();\ } @@ -608,7 +701,8 @@ void mchtmr_isr(void) {\ #define SDK_DECLARE_SWI_ISR(isr)\ void isr(void) __attribute__((section(".isr_vector")));\ HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) {\ +void swi_isr(void) \ +{ \ isr();\ } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h index a8d2aec494..91dbb44da0 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -355,4 +355,4 @@ typedef struct { #define IOC_PAD_PZ11 (491UL) -#endif /* HPM_IOC_H */ \ No newline at end of file +#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h index 5c123a6372..6e13e8b131 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -460,7 +460,6 @@ #define IOC_PB16_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB16_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) #define IOC_PB16_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB16_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PB17_FUNC_CTL function mux definitions */ #define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -474,472 +473,398 @@ #define IOC_PB18_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB18_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PB18_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB18_FUNC_CTL_DRAM_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB18_FUNC_CTL_FEMC_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB18_FUNC_CTL_XPI_SLV_ADQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB19_FUNC_CTL function mux definitions */ #define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB19_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB19_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB19_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB19_FUNC_CTL_DRAM_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB19_FUNC_CTL_FEMC_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB19_FUNC_CTL_XPI_SLV_ADQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB20_FUNC_CTL function mux definitions */ #define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB20_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PB20_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PB20_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB20_FUNC_CTL_DRAM_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB20_FUNC_CTL_FEMC_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB20_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB20_FUNC_CTL_XPI_SLV_ADQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB21_FUNC_CTL function mux definitions */ #define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB21_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB21_FUNC_CTL_DRAM_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB21_FUNC_CTL_FEMC_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB21_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB21_FUNC_CTL_XPI_SLV_ADQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB22_FUNC_CTL function mux definitions */ #define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB22_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB22_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB22_FUNC_CTL_DRAM_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB22_FUNC_CTL_FEMC_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB22_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB22_FUNC_CTL_XPI_SLV_ADQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB23_FUNC_CTL function mux definitions */ #define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB23_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB23_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB23_FUNC_CTL_DRAM_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB23_FUNC_CTL_FEMC_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB23_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB23_FUNC_CTL_XPI_SLV_ADQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB24_FUNC_CTL function mux definitions */ #define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB24_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB24_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB24_FUNC_CTL_DRAM_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB24_FUNC_CTL_FEMC_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB24_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB24_FUNC_CTL_XPI_SLV_ADQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB25_FUNC_CTL function mux definitions */ #define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB25_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB25_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB25_FUNC_CTL_DRAM_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB25_FUNC_CTL_FEMC_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB25_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB25_FUNC_CTL_XPI_SLV_ADQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB26_FUNC_CTL function mux definitions */ #define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB26_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB26_FUNC_CTL_DRAM_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB26_FUNC_CTL_FEMC_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB26_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB26_FUNC_CTL_XPI_SLV_ADQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB27_FUNC_CTL function mux definitions */ #define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB27_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB27_FUNC_CTL_DRAM_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB27_FUNC_CTL_FEMC_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB27_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB27_FUNC_CTL_XPI_SLV_ADQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB28_FUNC_CTL function mux definitions */ #define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB28_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB28_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB28_FUNC_CTL_DRAM_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB28_FUNC_CTL_FEMC_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB28_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB28_FUNC_CTL_XPI_SLV_ADQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB29_FUNC_CTL function mux definitions */ #define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB29_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB29_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB29_FUNC_CTL_DRAM_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB29_FUNC_CTL_FEMC_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB29_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB29_FUNC_CTL_XPI_SLV_ADQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PB30_FUNC_CTL function mux definitions */ #define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB30_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PB30_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB30_FUNC_CTL_DRAM_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB30_FUNC_CTL_FEMC_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB30_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) /* IOC_PB31_FUNC_CTL function mux definitions */ #define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PB31_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB31_FUNC_CTL_DRAM_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB31_FUNC_CTL_FEMC_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PB31_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB31_FUNC_CTL_XPI_SLV_ADQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC00_FUNC_CTL function mux definitions */ #define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC00_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC00_FUNC_CTL_DRAM_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC00_FUNC_CTL_FEMC_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC00_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC00_FUNC_CTL_XPI_SLV_ADQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC01_FUNC_CTL function mux definitions */ #define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC01_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC01_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC01_FUNC_CTL_DRAM_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC01_FUNC_CTL_FEMC_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC01_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC01_FUNC_CTL_XPI_SLV_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC02_FUNC_CTL function mux definitions */ #define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC02_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC02_FUNC_CTL_DRAM_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC02_FUNC_CTL_FEMC_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC02_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC02_FUNC_CTL_XPI_SLV_ADQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC03_FUNC_CTL function mux definitions */ #define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC03_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC03_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC03_FUNC_CTL_DRAM_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC03_FUNC_CTL_FEMC_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC03_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC03_FUNC_CTL_XPI_SLV_ADQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC04_FUNC_CTL function mux definitions */ #define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC04_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC04_FUNC_CTL_DRAM_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC04_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC04_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC04_FUNC_CTL_XPI_SLV_ADQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC04_FUNC_CTL_UTMI_CFG_ADDR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC05_FUNC_CTL function mux definitions */ #define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC05_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC05_FUNC_CTL_DRAM_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC05_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC05_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC05_FUNC_CTL_XPI_SLV_ADQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC05_FUNC_CTL_UTMI_CFG_DDIR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC06_FUNC_CTL function mux definitions */ #define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC06_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC06_FUNC_CTL_DRAM_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC06_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC06_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC06_FUNC_CTL_XPI_SLV_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC06_FUNC_CTL_UTMI_CFG_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC07_FUNC_CTL function mux definitions */ #define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC07_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC07_FUNC_CTL_DRAM_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC07_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC07_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC07_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC07_FUNC_CTL_XPI_SLV_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC08_FUNC_CTL function mux definitions */ #define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC08_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC08_FUNC_CTL_DRAM_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC08_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC08_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC08_FUNC_CTL_ETH1_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC08_FUNC_CTL_XPI_SLV_ADQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC08_FUNC_CTL_UTMI_CFG_ADDR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC09_FUNC_CTL function mux definitions */ #define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC09_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC09_FUNC_CTL_DRAM_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC09_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC09_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC09_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC09_FUNC_CTL_ETH1_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC09_FUNC_CTL_UTMI_CFG_REN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC10_FUNC_CTL function mux definitions */ #define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC10_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC10_FUNC_CTL_DRAM_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC10_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC10_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC10_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC10_FUNC_CTL_XPI_SLV_ADQ_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC10_FUNC_CTL_UTMI_CFG_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC11_FUNC_CTL function mux definitions */ #define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC11_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC11_FUNC_CTL_DRAM_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC11_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC11_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC11_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC11_FUNC_CTL_XPI_SLV_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC11_FUNC_CTL_UTMI_CFG_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC12_FUNC_CTL function mux definitions */ #define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC12_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC12_FUNC_CTL_DRAM_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC12_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC12_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC12_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC12_FUNC_CTL_XPI_SLV_ADQ_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC13_FUNC_CTL function mux definitions */ #define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC13_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC13_FUNC_CTL_DRAM_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC13_FUNC_CTL_ETH1_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC13_FUNC_CTL_XPI_SLV_ADQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC13_FUNC_CTL_UTMI_CFG_ADDR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) +#define IOC_PC13_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) /* IOC_PC14_FUNC_CTL function mux definitions */ #define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC14_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC14_FUNC_CTL_DRAM_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC14_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC14_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC14_FUNC_CTL_TRGM3_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC14_FUNC_CTL_ETH1_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC14_FUNC_CTL_UTMI_CFG_WEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC15_FUNC_CTL function mux definitions */ #define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC15_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC15_FUNC_CTL_DRAM_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC15_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC15_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC15_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC15_FUNC_CTL_XPI_SLV_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC15_FUNC_CTL_UTMI_CFG_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC16_FUNC_CTL function mux definitions */ #define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC16_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC16_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC16_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC16_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC16_FUNC_CTL_TRGM2_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC16_FUNC_CTL_XPI_SLV_ADQ_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC16_FUNC_CTL_UTMI_CFG_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC17_FUNC_CTL function mux definitions */ #define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC17_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC17_FUNC_CTL_DRAM_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC17_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC17_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC17_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC17_FUNC_CTL_XPI_SLV_ADQ_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC18_FUNC_CTL function mux definitions */ #define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC18_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC18_FUNC_CTL_DRAM_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC18_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC18_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC18_FUNC_CTL_ETH1_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC18_FUNC_CTL_XPI_SLV_ADQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC18_FUNC_CTL_UTMI_CFG_ADDR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC19_FUNC_CTL function mux definitions */ #define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC19_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC19_FUNC_CTL_DRAM_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC19_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC19_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC19_FUNC_CTL_TRGM3_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC19_FUNC_CTL_ETH1_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC19_FUNC_CTL_UTMI_CFG_RST_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC20_FUNC_CTL function mux definitions */ #define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC20_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC20_FUNC_CTL_DRAM_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC20_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC20_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC20_FUNC_CTL_TRGM3_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC20_FUNC_CTL_XPI_SLV_ADQ_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC20_FUNC_CTL_UTMI_CFG_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC21_FUNC_CTL function mux definitions */ #define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC21_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC21_FUNC_CTL_DRAM_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC21_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC21_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC21_FUNC_CTL_TRGM2_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC21_FUNC_CTL_XPI_SLV_ADQ_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC21_FUNC_CTL_UTMI_CFG_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC22_FUNC_CTL function mux definitions */ #define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC22_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC22_FUNC_CTL_DRAM_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC22_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC22_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC22_FUNC_CTL_TRGM2_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC22_FUNC_CTL_XPI_SLV_ADQ_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC23_FUNC_CTL function mux definitions */ #define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC23_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC23_FUNC_CTL_DRAM_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC23_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC23_FUNC_CTL_TRGM3_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC23_FUNC_CTL_ETH1_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC23_FUNC_CTL_XPI_SLV_ADQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC23_FUNC_CTL_UTMI_CFG_ADDR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC24_FUNC_CTL function mux definitions */ #define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC24_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC24_FUNC_CTL_DRAM_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC24_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC24_FUNC_CTL_TRGM3_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC24_FUNC_CTL_ETH1_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC24_FUNC_CTL_XPI_SLV_ADQ_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC24_FUNC_CTL_UTMI_CFG_ADDR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC25_FUNC_CTL function mux definitions */ #define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC25_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC25_FUNC_CTL_DRAM_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC25_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC25_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC25_FUNC_CTL_TRGM2_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC25_FUNC_CTL_XPI_SLV_ADQ_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) -#define IOC_PC25_FUNC_CTL_UTMI_CFG_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC26_FUNC_CTL function mux definitions */ #define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC26_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC26_FUNC_CTL_DRAM_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC26_FUNC_CTL_FEMC_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC26_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC26_FUNC_CTL_TRGM2_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC26_FUNC_CTL_XPI_SLV_ADQ_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) /* IOC_PC27_FUNC_CTL function mux definitions */ #define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC27_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC27_FUNC_CTL_DRAM_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC27_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC27_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC27_FUNC_CTL_ETH1_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC27_FUNC_CTL_UTMI_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC28_FUNC_CTL function mux definitions */ #define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC28_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC28_FUNC_CTL_DRAM_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC28_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC28_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC28_FUNC_CTL_ETH1_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC28_FUNC_CTL_UTMI_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC29_FUNC_CTL function mux definitions */ #define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC29_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC29_FUNC_CTL_DRAM_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC29_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC29_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC29_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PC29_FUNC_CTL_ETH1_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC29_FUNC_CTL_UTMI_DM_PULLDOWN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC30_FUNC_CTL function mux definitions */ #define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC30_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC30_FUNC_CTL_DRAM_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC30_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC30_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC30_FUNC_CTL_TRGM2_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC30_FUNC_CTL_UTMI_OP_MOD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PC31_FUNC_CTL function mux definitions */ #define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC31_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC31_FUNC_CTL_DRAM_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC31_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC31_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PC31_FUNC_CTL_PWM2_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC31_FUNC_CTL_UTMI_LINE_STAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD00_FUNC_CTL function mux definitions */ #define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD00_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD00_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD00_FUNC_CTL_DRAM_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD00_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD00_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD00_FUNC_CTL_ETH1_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD00_FUNC_CTL_UTMI_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD01_FUNC_CTL function mux definitions */ #define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD01_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PD01_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD01_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD01_FUNC_CTL_DRAM_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD01_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD01_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD01_FUNC_CTL_ETH1_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD01_FUNC_CTL_UTMI_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD02_FUNC_CTL function mux definitions */ #define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD02_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD02_FUNC_CTL_DRAM_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD02_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD02_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD02_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD02_FUNC_CTL_ETH1_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD02_FUNC_CTL_UTMI_DP_PULLDOWN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD03_FUNC_CTL function mux definitions */ #define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD03_FUNC_CTL_DRAM_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD03_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD03_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD03_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD03_FUNC_CTL_UTMI_OP_MOD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD04_FUNC_CTL function mux definitions */ #define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD04_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD04_FUNC_CTL_DRAM_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD04_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD04_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD04_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD04_FUNC_CTL_UTMI_LINE_STAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD05_FUNC_CTL function mux definitions */ #define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PD05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD05_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD05_FUNC_CTL_DRAM_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD05_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD05_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD05_FUNC_CTL_ETH1_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD05_FUNC_CTL_UTMI_FSS_MOD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD06_FUNC_CTL function mux definitions */ #define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD06_FUNC_CTL_DRAM_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD06_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD06_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD06_FUNC_CTL_UTMI_SESS_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD07_FUNC_CTL function mux definitions */ #define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD07_FUNC_CTL_DRAM_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD07_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD07_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD07_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD07_FUNC_CTL_UTMI_SUSPDM IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD08_FUNC_CTL function mux definitions */ #define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD08_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD08_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD08_FUNC_CTL_DRAM_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD08_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD08_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD08_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD08_FUNC_CTL_ETH1_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD08_FUNC_CTL_UTMI_H_DISCNT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD09_FUNC_CTL function mux definitions */ #define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD09_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PD09_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD09_FUNC_CTL_DRAM_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD09_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD09_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD09_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD09_FUNC_CTL_UTMI_VBUS_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD10_FUNC_CTL function mux definitions */ #define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -947,10 +872,9 @@ #define IOC_PD10_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD10_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PD10_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD10_FUNC_CTL_DRAM_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD10_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD10_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD10_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD10_FUNC_CTL_UTMI_TERM_SEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD11_FUNC_CTL function mux definitions */ #define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -959,18 +883,16 @@ #define IOC_PD11_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD11_FUNC_CTL_PWM3_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD11_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD11_FUNC_CTL_UTMI_TXBST_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD12_FUNC_CTL function mux definitions */ #define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PD12_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PD12_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD12_FUNC_CTL_DRAM_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD12_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD12_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD12_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD12_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD12_FUNC_CTL_UTMI_TEST_BIST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD13_FUNC_CTL function mux definitions */ #define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -978,10 +900,9 @@ #define IOC_PD13_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PD13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PD13_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD13_FUNC_CTL_DRAM_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD13_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD13_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD13_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD13_FUNC_CTL_UTMI_SELF_TEST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD14_FUNC_CTL function mux definitions */ #define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -991,7 +912,6 @@ #define IOC_PD14_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD14_FUNC_CTL_PWM3_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD14_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD14_FUNC_CTL_UTMI_PLL_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD15_FUNC_CTL function mux definitions */ #define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -999,8 +919,6 @@ #define IOC_PD15_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD15_FUNC_CTL_PWM2_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD15_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD15_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PD15_FUNC_CTL_UTMI_RESET IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD16_FUNC_CTL function mux definitions */ #define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1010,7 +928,6 @@ #define IOC_PD16_FUNC_CTL_TRGM2_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD16_FUNC_CTL_SDC1_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD16_FUNC_CTL_ETH1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD16_FUNC_CTL_UTMI_DDIR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD17_FUNC_CTL function mux definitions */ #define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1019,7 +936,6 @@ #define IOC_PD17_FUNC_CTL_TRGM3_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD17_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD17_FUNC_CTL_ETH1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD17_FUNC_CTL_UTMI_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD18_FUNC_CTL function mux definitions */ #define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1029,7 +945,6 @@ #define IOC_PD18_FUNC_CTL_TRGM3_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD18_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD18_FUNC_CTL_ETH1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD18_FUNC_CTL_UTMI_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD19_FUNC_CTL function mux definitions */ #define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1039,7 +954,6 @@ #define IOC_PD19_FUNC_CTL_TRGM2_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD19_FUNC_CTL_SDC1_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD19_FUNC_CTL_ETH1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD19_FUNC_CTL_UTMI_RX_ACTIVE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD20_FUNC_CTL function mux definitions */ #define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1049,7 +963,6 @@ #define IOC_PD20_FUNC_CTL_TRGM2_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD20_FUNC_CTL_SDC1_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD20_FUNC_CTL_ETH1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD20_FUNC_CTL_UTMI_RX_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD21_FUNC_CTL function mux definitions */ #define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1058,7 +971,6 @@ #define IOC_PD21_FUNC_CTL_TRGM3_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD21_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD21_FUNC_CTL_ETH1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD21_FUNC_CTL_UTMI_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD22_FUNC_CTL function mux definitions */ #define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1067,7 +979,6 @@ #define IOC_PD22_FUNC_CTL_TRGM3_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD22_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD22_FUNC_CTL_ETH1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD22_FUNC_CTL_UTMI_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD23_FUNC_CTL function mux definitions */ #define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1075,7 +986,6 @@ #define IOC_PD23_FUNC_CTL_TRGM2_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD23_FUNC_CTL_SDC1_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD23_FUNC_CTL_ETH1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD23_FUNC_CTL_UTMI_XCVR_SEL_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD24_FUNC_CTL function mux definitions */ #define IOC_PD24_FUNC_CTL_GPIO_D_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1084,7 +994,6 @@ #define IOC_PD24_FUNC_CTL_TRGM2_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD24_FUNC_CTL_SDC1_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD24_FUNC_CTL_ETH1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD24_FUNC_CTL_UTMI_XCVR_SEL_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD25_FUNC_CTL function mux definitions */ #define IOC_PD25_FUNC_CTL_GPIO_D_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1093,7 +1002,6 @@ #define IOC_PD25_FUNC_CTL_TRGM2_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD25_FUNC_CTL_SDC1_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD25_FUNC_CTL_ETH1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD25_FUNC_CTL_UTMI_RX_VLDH IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD26_FUNC_CTL function mux definitions */ #define IOC_PD26_FUNC_CTL_GPIO_D_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1102,7 +1010,6 @@ #define IOC_PD26_FUNC_CTL_TRGM3_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD26_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD26_FUNC_CTL_ETH1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD26_FUNC_CTL_UTMI_TX_VLDH IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD27_FUNC_CTL function mux definitions */ #define IOC_PD27_FUNC_CTL_GPIO_D_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1111,7 +1018,6 @@ #define IOC_PD27_FUNC_CTL_TRGM3_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD27_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD27_FUNC_CTL_ETH1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD27_FUNC_CTL_UTMI_TX_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD28_FUNC_CTL function mux definitions */ #define IOC_PD28_FUNC_CTL_GPIO_D_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1120,7 +1026,6 @@ #define IOC_PD28_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD28_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD28_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD28_FUNC_CTL_UTMI_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD29_FUNC_CTL function mux definitions */ #define IOC_PD29_FUNC_CTL_GPIO_D_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1129,7 +1034,6 @@ #define IOC_PD29_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD29_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PD29_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD29_FUNC_CTL_UTMI_CLK60_TO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD30_FUNC_CTL function mux definitions */ #define IOC_PD30_FUNC_CTL_GPIO_D_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1139,7 +1043,6 @@ #define IOC_PD30_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD30_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD30_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD30_FUNC_CTL_UTMI_TX_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PD31_FUNC_CTL function mux definitions */ #define IOC_PD31_FUNC_CTL_GPIO_D_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1149,7 +1052,6 @@ #define IOC_PD31_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PD31_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PD31_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD31_FUNC_CTL_UTMI_RX_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE00_FUNC_CTL function mux definitions */ #define IOC_PE00_FUNC_CTL_GPIO_E_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1158,7 +1060,6 @@ #define IOC_PE00_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE00_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE00_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE00_FUNC_CTL_UTMI_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE01_FUNC_CTL function mux definitions */ #define IOC_PE01_FUNC_CTL_GPIO_E_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1167,7 +1068,6 @@ #define IOC_PE01_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE01_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE01_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE01_FUNC_CTL_UTMI_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE02_FUNC_CTL function mux definitions */ #define IOC_PE02_FUNC_CTL_GPIO_E_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1176,7 +1076,6 @@ #define IOC_PE02_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE02_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE02_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE02_FUNC_CTL_UTMI_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE03_FUNC_CTL function mux definitions */ #define IOC_PE03_FUNC_CTL_GPIO_E_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1186,7 +1085,6 @@ #define IOC_PE03_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE03_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE03_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE03_FUNC_CTL_UTMI_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE04_FUNC_CTL function mux definitions */ #define IOC_PE04_FUNC_CTL_GPIO_E_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1196,7 +1094,6 @@ #define IOC_PE04_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE04_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE04_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE04_FUNC_CTL_UTMI_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE05_FUNC_CTL function mux definitions */ #define IOC_PE05_FUNC_CTL_GPIO_E_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1205,7 +1102,6 @@ #define IOC_PE05_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE05_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE05_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE05_FUNC_CTL_UTMI_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE06_FUNC_CTL function mux definitions */ #define IOC_PE06_FUNC_CTL_GPIO_E_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1215,7 +1111,6 @@ #define IOC_PE06_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE06_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE06_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE06_FUNC_CTL_UTMI_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE07_FUNC_CTL function mux definitions */ #define IOC_PE07_FUNC_CTL_GPIO_E_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1224,7 +1119,6 @@ #define IOC_PE07_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE07_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE07_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE07_FUNC_CTL_UTMI_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE08_FUNC_CTL function mux definitions */ #define IOC_PE08_FUNC_CTL_GPIO_E_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1233,7 +1127,6 @@ #define IOC_PE08_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE08_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE08_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE08_FUNC_CTL_UTMI_RX_DM IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE09_FUNC_CTL function mux definitions */ #define IOC_PE09_FUNC_CTL_GPIO_E_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1243,7 +1136,6 @@ #define IOC_PE09_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE09_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE09_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE09_FUNC_CTL_UTMI_RX_DP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE10_FUNC_CTL function mux definitions */ #define IOC_PE10_FUNC_CTL_GPIO_E_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1253,7 +1145,6 @@ #define IOC_PE10_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE10_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE10_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE10_FUNC_CTL_UTMI_RX_RCV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE11_FUNC_CTL function mux definitions */ #define IOC_PE11_FUNC_CTL_GPIO_E_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1264,7 +1155,6 @@ #define IOC_PE11_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE11_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE11_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE11_FUNC_CTL_UTMI_TX_SE0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE12_FUNC_CTL function mux definitions */ #define IOC_PE12_FUNC_CTL_GPIO_E_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1273,7 +1163,6 @@ #define IOC_PE12_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PE12_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE12_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE12_FUNC_CTL_UTMI_TXEN_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE13_FUNC_CTL function mux definitions */ #define IOC_PE13_FUNC_CTL_GPIO_E_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1282,7 +1171,6 @@ #define IOC_PE13_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) #define IOC_PE13_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PE13_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE13_FUNC_CTL_UTMI_TX_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE14_FUNC_CTL function mux definitions */ #define IOC_PE14_FUNC_CTL_GPIO_E_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1293,7 +1181,6 @@ #define IOC_PE14_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE14_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE14_FUNC_CTL_ETH1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE14_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PE15_FUNC_CTL function mux definitions */ #define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1313,7 +1200,6 @@ #define IOC_PE16_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE16_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE16_FUNC_CTL_ETH1_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE16_FUNC_CTL_UTMI_D16_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) /* IOC_PE17_FUNC_CTL function mux definitions */ #define IOC_PE17_FUNC_CTL_GPIO_E_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1352,7 +1238,6 @@ #define IOC_PE20_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE20_FUNC_CTL_ETH1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) #define IOC_PE20_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE20_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PE21_FUNC_CTL function mux definitions */ #define IOC_PE21_FUNC_CTL_GPIO_E_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1389,7 +1274,6 @@ #define IOC_PE24_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PE24_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) #define IOC_PE24_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE24_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) #define IOC_PE24_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PE25_FUNC_CTL function mux definitions */ @@ -1399,7 +1283,6 @@ #define IOC_PE25_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) #define IOC_PE25_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE25_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE25_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PE26_FUNC_CTL function mux definitions */ #define IOC_PE26_FUNC_CTL_GPIO_E_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1488,7 +1371,6 @@ #define IOC_PF03_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PF03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PF03_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF03_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PF04_FUNC_CTL function mux definitions */ #define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1531,7 +1413,6 @@ #define IOC_PF08_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PF08_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PF08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF08_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) #define IOC_PF08_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PF09_FUNC_CTL function mux definitions */ @@ -1559,7 +1440,7 @@ /* IOC_PX01_FUNC_CTL function mux definitions */ #define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PX01_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PX01_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) #define IOC_PX01_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) @@ -1586,7 +1467,7 @@ /* IOC_PX06_FUNC_CTL function mux definitions */ #define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PX06_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PX06_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) /* IOC_PX07_FUNC_CTL function mux definitions */ @@ -1680,7 +1561,6 @@ #define IOC_PY08_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PY08_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) #define IOC_PY08_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY08_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PY09_FUNC_CTL function mux definitions */ #define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1689,7 +1569,6 @@ #define IOC_PY09_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PY09_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) #define IOC_PY09_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY09_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PY10_FUNC_CTL function mux definitions */ #define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1761,14 +1640,12 @@ #define IOC_PZ08_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) #define IOC_PZ08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PZ08_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PZ09_FUNC_CTL function mux definitions */ #define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ09_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ09_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) #define IOC_PZ09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PZ09_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PZ10_FUNC_CTL function mux definitions */ #define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1786,4 +1663,4 @@ #define IOC_PZ11_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#endif /* HPM_IOMUX_H */ \ No newline at end of file +#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.c index 51b368fa22..c55600dcdc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.c @@ -1,12 +1,10 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#include "hpm_common.h" -#include "hpm_soc.h" #include "hpm_l1c_drv.h" #include @@ -19,14 +17,18 @@ static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) { register uint32_t i; - register uint32_t next_address = 0; + register uint32_t next_address; register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); #define CCTL_VERSION (3U << 18) if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { l1c_cctl_address(address); - while (next_address < (address + size)) { + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { l1c_cctl_cmd(opcode); next_address = l1c_cctl_get_address(); } @@ -36,6 +38,8 @@ static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) tmp += HPM_L1C_CACHELINE_SIZE; } } + + write_csr(CSR_MSTATUS, csr); } void l1c_dc_enable(void) @@ -62,6 +66,7 @@ void l1c_ic_enable(void) { if (!l1c_ic_is_enabled()) { set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK | HPM_MCACHE_CTL_IC_EN_MASK); } } @@ -73,7 +78,7 @@ void l1c_ic_disable(void) } } -void l1c_fence_i() +void l1c_fence_i(void) { __asm("fence.i"); } @@ -88,6 +93,11 @@ void l1c_dc_writeback_all(void) l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); } +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + void l1c_dc_fill_lock(uint32_t address, uint32_t size) { ASSERT_ADDR_SIZE(address, size); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h index d64cd4791f..e328193a07 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #define _HPM_L1_CACHE_H #include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_soc.h" /** * @@ -468,6 +469,11 @@ void l1c_dc_invalidate_all(void); */ void l1c_dc_writeback_all(void); +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_misc.h index 85cd427d9b..0197bf37f8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_misc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_misc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,28 +18,24 @@ #define CORE1_DLM_SYSTEM_BASE (0x11C0000U) #define ADDRESS_IN_ILM(address) \ - ((ILM_LOCAL_BASE) <= (address)) && \ ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) #define ADDRESS_IN_DLM(address) \ - ((DLM_LOCAL_BASE) <= (address)) && \ - ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ - ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + (((DLM_LOCAL_BASE) <= (address)) && \ + ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address))) #define ADDRESS_IN_CORE0_ILM_SYSTEM(address) \ - ((CORE0_ILM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address)) + (((CORE0_ILM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address))) #define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ - ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + (((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address))) #define ADDRESS_IN_CORE1_ILM_SYSTEM(address) \ - ((CORE1_ILM_SYSTEM_BASE) <= (address)) && \ - ((CORE1_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address)) + (((CORE1_ILM_SYSTEM_BASE) <= (address)) && \ + ((CORE1_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address))) #define ADDRESS_IN_CORE1_DLM_SYSTEM(address) \ - ((CORE1_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE1_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + (((CORE1_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE1_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address))) #define DLM_TO_SYSTEM(address) \ (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) @@ -74,15 +70,15 @@ static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t a { if (core_id == HPM_CORE1) { if (ADDRESS_IN_CORE1_DLM_SYSTEM(addr)) { - addr = addr - CORE1_DLM_SYSTEM_BASE + DLM_LOCAL_BASE; + addr = (addr - CORE1_DLM_SYSTEM_BASE) + DLM_LOCAL_BASE; } else if (ADDRESS_IN_CORE1_ILM_SYSTEM(addr)) { - addr = addr - CORE1_ILM_SYSTEM_BASE + ILM_LOCAL_BASE; + addr = (addr - CORE1_ILM_SYSTEM_BASE) + ILM_LOCAL_BASE; } } else { if (ADDRESS_IN_CORE0_DLM_SYSTEM(addr)) { - addr = addr - CORE0_DLM_SYSTEM_BASE + DLM_LOCAL_BASE; + addr = (addr - CORE0_DLM_SYSTEM_BASE) + DLM_LOCAL_BASE; } else if (ADDRESS_IN_CORE0_ILM_SYSTEM(addr)) { - addr = addr - CORE0_ILM_SYSTEM_BASE + ILM_LOCAL_BASE; + addr = (addr - CORE0_ILM_SYSTEM_BASE) + ILM_LOCAL_BASE; } } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c index 986bfe88d7..b9d9297b31 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2021 hpmicro +* Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -48,7 +48,7 @@ uint32_t otp_read_from_ip(uint32_t addr) HPM_OTP->ADDR = addr; HPM_OTP->INT_FLAG = OTP_INT_FLAG_READ_MASK; /* Write-1-Clear */ HPM_OTP->CMD = OTP_CMD_READ; - while(!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_READ_MASK)) { + while (!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_READ_MASK)) { } ret_val = HPM_OTP->DATA; } @@ -60,14 +60,14 @@ hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words hpm_stat_t status = status_invalid_argument; do { uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >=fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); /* Enable 2.5V LDO for FUSE programming */ uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); HPM_PCFG->LDO2P5 = reg_val; - //TODO: delay 1ms, wait for design team's update to get a steady bit (bit28 in this reg) + /* TODO: delay 1ms, wait for design team's update to get a steady bit (bit28 in this reg) */ - for (uint32_t i=0; iUNLOCK = OTP_UNLOCK_MAGIC_NUM; HPM_OTP->FUSE[addr++] = *src++; @@ -80,7 +80,7 @@ hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words ++src; ++addr; - while(!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_WRITE_MASK)) { + while (!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_WRITE_MASK)) { } @@ -88,7 +88,7 @@ hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words /* Disable 2.5V LDO after FUSE programming for saving power */ HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; status = status_success; - }while(false); + } while (false); return status; } @@ -99,7 +99,7 @@ hpm_stat_t otp_reload(otp_region_t region) if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { HPM_OTP->LOAD_REQ = (uint32_t)region; HPM_OTP->LOAD_COMP = (uint32_t)region; - while(!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { } status = status_success; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h index bedd300b95..1b36b87450 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -26,7 +26,7 @@ typedef enum { otp_region1_mask = 2U, /*!< Address range: [8, 15] */ otp_region2_mask = 4U, /*!< Address range: [16, 127] */ otp_region3_mask = 8U, /*!< Address range: user defined */ -}otp_region_t; +} otp_region_t; /** * @brief OTP lock options @@ -37,11 +37,10 @@ typedef enum { otp_permanent_no_lock = 2, otp_disable_access = 3, otp_lock_option_max = otp_disable_access, -}otp_lock_option_t; +} otp_lock_option_t; -enum -{ +enum { otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h new file mode 100644 index 0000000000..e99e0837a5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h @@ -0,0 +1,639 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) +#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_fuse = 0, + pcfg_pmc_periph_ram = 2, + pcfg_pmc_periph_vad = 4, + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, + pcfg_pmc_periph_debug = 16, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap enable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief bandgap enable low power mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) +{ + ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn of LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) +{ + ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + * @param[in] over_limit set to true means current is greater than limit + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); +} + +/** + * @brief disable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief enable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/** + * @brief Disable CPU0 debug stop notficiation to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Enable CPU0 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Disable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Enable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Configure CPU core debug stop notification to peripherals + * + * @param[in] ptr + * @param[in] mask + */ +static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) +{ + ptr->DEBUG_STOP = mask; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h new file mode 100644 index 0000000000..b05080feac --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h @@ -0,0 +1,927 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ + __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * LOWPOWER_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) +#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) +#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) +#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) +#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) +#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) +#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) +#define PCFG_LDO1P1_ENABLE_SHIFT (16U) +#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) +#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: trun off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RW) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * DISABLE_POWER_LOSS (RW) + * + * disable power loss protection + * 0: power loss protection enabled, DCDC shuts down when power loss + * 1: power loss protection disabled, DCDC try working after power voltage drop + */ +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * ouput over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit0-1: fuse + * bit2-3: sram + * bit4-5: vad + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + * bit16-17:debug + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: DEBUG_STOP */ +/* + * CPU1 (RW) + * + * Stop peripheral when CPU1 enter debug mode + * 0: peripheral keep running when CPU1 in debug mode + * 1: peripheral enter debug mode when CPU1 enter debug + */ +#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) +#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) +#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) + +/* + * CPU0 (RW) + * + * Stop peripheral when CPU0 enter debug mode + * 0: peripheral keep running when CPU0 in debug mode + * 1: peripheral enter debug mode when CPU0 enter debug + */ +#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) +#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) +#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h new file mode 100644 index 0000000000..0369149bdd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_plic_drv.h index dc0b95e00e..9595051f90 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_plic_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_plic_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h index 960ac3207e..7a8737a43a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -82,4 +82,4 @@ #define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#endif /* HPM_PMIC_IOMUX_H */ \ No newline at end of file +#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h new file mode 100644 index 0000000000..b1eb6e6ac5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_temperature = 1 << 1, + ppor_reset_pin = 1 << 2, + ppor_reset_debug = 1 << 4, + ppor_reset_security_violation = 1 << 5, + ppor_reset_jtag = 1 << 6, + ppor_reset_cpu0_lockup = 1 << 8, + ppor_reset_cpu1_lockup = 1 << 9, + ppor_reset_cpu0_request = 1 << 10, + ppor_reset_cpu1_request = 1 << 11, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_wdog2 = 1 << 18, + ppor_reset_wdog3 = 1 << 19, + ppor_reset_pmic_wdog = 1 << 20, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG |= mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD = mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD &= ~mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT = mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT &= ~mask; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h new file mode 100644 index 0000000000..21cb6fc237 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ + __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ + __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RW) + * + * current status of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * STATUS (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) +#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) +#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_HOT */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOT_TYPE_SHIFT (0U) +#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) +#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) + +/* Bitfield definition for register: RESET_COLD */ +/* + * FLAG (RW) + * + * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_COLD_FLAG_SHIFT (0U) +#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) +#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h index 10b6c359af..0dab53b250 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h @@ -1,9 +1,9 @@ /* -* Copyright (c) 2021 hpmicro -* -* SPDX-License-Identifier: BSD-3-Clause -* -*/ + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ #ifndef HPM_ROMAPI_H #define HPM_ROMAPI_H @@ -52,6 +52,14 @@ typedef union { }; } api_boot_arg_t; +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + #define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ #define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ #define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ @@ -61,6 +69,18 @@ typedef union { #define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ #define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ +typedef struct { + uint32_t _internal[138]; +} sm3_context_t; + +#define SM4_ENCRYPT 1 +#define SM4_DECRYPT 0 + +typedef struct { + uint32_t mode; + uint32_t _internal[116]; +} sm4_context_t; + /** * @brief OTP driver interface */ @@ -117,7 +137,8 @@ typedef struct { void (*update_dllcr)(XPI_Type *base, uint32_t serial_root_clk_freq, uint32_t data_valid_time, xpi_channel_t channel, uint32_t dly_target); /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); + hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, + uint32_t *out_addr); } xpi_driver_interface_t; /** @@ -131,38 +152,48 @@ typedef struct { /**< XPI NOR driver interface: initialize FLASH */ hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr, + hpm_stat_t (*get_status)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr, uint16_t *out_status); /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: erase a specified FLASH region */ hpm_stat_t (*erase)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start, uint32_t length); /**< XPI NOR driver interface: Erase the whole FLASH */ hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, const uint32_t *src, + hpm_stat_t (*program)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + const uint32_t *src, uint32_t dst_addr, uint32_t length); /**< XPI NOR driver interface: read data from specified FLASH address */ hpm_stat_t (*read)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t *dst, uint32_t start, uint32_t length); /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, const uint32_t *src, uint32_t dst_addr, uint32_t length); /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t addr); /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t addr); /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config); uint32_t reserved0[3]; @@ -228,6 +259,42 @@ typedef struct { hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); } sdp_driver_interface_t; +typedef struct { + /**< SM3 API version*/ + uint32_t version; + /**< SM3 API itnerface: HASH Initialization */ + hpm_stat_t (*init)(sm3_context_t *ctx); + /**< SM3 API interface: HASH update */ + hpm_stat_t (*update)(sm3_context_t *ctx, const void *input, uint32_t len); + /**< SM3 API interface: HASH finish */ + hpm_stat_t (*finalize)(sm3_context_t *ctx, uint8_t output[32]); +} sm3_api_interface_t; + +typedef struct { + /**< SM4 API interface: Version */ + uint32_t version; + /**< SM4 API interface: Set encryption key */ + void (*setkey_enc)(sm4_context_t *ctx, const uint8_t key[16]); + /**< SM4 API interface: Set decryption key */ + void (*setkey_dec)(sm4_context_t *ctx, const uint8_t key[16]); + /**< SM4 API interface: SM4 ECB operation */ + hpm_stat_t (*crypt_ecb)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output); + /**< SM4 API interface: SM4 CBC operation */ + hpm_stat_t (*crypt_cbc)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], + const uint8_t *input, uint8_t *output); + /**< SM4 API interface: SM4 CTR operation */ + hpm_stat_t (*crypt_ctr)(sm4_context_t *ctx, uint8_t *nonce_counter, const uint8_t *input, + uint8_t *output, uint32_t length); + /**< SM4 API interface: SM4 CCB encryption */ + hpm_stat_t (*ccm_gen_enc)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, uint8_t *tag, uint32_t tag_len); + /**< SM4 API interface: SM4 CCM Decryption and verifying */ + hpm_stat_t (*ccm_dec_verify)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, const uint8_t *tag, uint32_t tag_len); +} sm4_api_interface_t; + /** * @brief Bootloader API table */ @@ -248,11 +315,13 @@ typedef struct { const xpi_ram_driver_interface_t *xpi_ram_driver_if; /**< Bootloader API table: sdp driver interface address */ const sdp_driver_interface_t *sdp_driver_if; + const uint32_t reserved0; + const sm3_api_interface_t *sm3_api_if; /* SM3 driver interface address */ + const sm4_api_interface_t *sm4_api_if; /* SM4 driver itnerface address */ } bootloader_api_table_t; /**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t*)0x2001FF00U) - +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) #ifdef __cplusplus extern "C" { @@ -317,10 +386,13 @@ static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_ * @param[in] length Region size to be erased * @return API execution status */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t start, uint32_t length) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + fencei(); + return status; } /** @@ -335,7 +407,9 @@ static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, xpi_xfer_chann const xpi_nor_config_t *nor_config, uint32_t start) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + fencei(); + return status; } /** @@ -365,7 +439,9 @@ static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, xpi_xfer_channe const xpi_nor_config_t *nor_config, uint32_t start) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + fencei(); + return status; } /** @@ -383,7 +459,6 @@ static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, xpi return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); } - /** * @brief Erase the whole FLASH in blocking way * @param[in] base XPI base address @@ -407,10 +482,11 @@ static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + fencei(); + return status; } - /** * @brief Program data to specified FLASH address in blocking way * @param[in] base XPI base address @@ -421,10 +497,14 @@ static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_ * @param[in] length length of data to be programmed * @return API execution status */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, const uint32_t *src, uint32_t dst_addr, uint32_t length) { - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + hpm_stat_t + status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + fencei(); + return status; } /** @@ -455,7 +535,8 @@ static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, xp * @param [in] length length of data to be read out * @return API exection address */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t *dst, uint32_t start, uint32_t length) { return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); @@ -488,6 +569,175 @@ static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); } +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + if (((base != HPM_XPI0) && (base != HPM_XPI1)) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) + || ((offset & 0xFFF) != 0)) { + return false; + } + static const uint8_t k_mc_xpi_remap_config[] = { + 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, + 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, + 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, + }; + typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); + remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; + bool result = cb(base, start, len, offset); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_disable[] = { + 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, + 0xf5, 0x42, 0x82, 0x80, + }; + typedef void (*remap_disable_cb_t)(XPI_Type *); + remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; + cb(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_enabled[] = { + 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, + }; + typedef bool (*remap_chk_cb_t)(XPI_Type *); + remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; + return chk_cb(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + if ((base != HPM_XPI0) && (base != HPM_XPI1)) { + return false; + } + static const uint8_t k_mc_exip_region_config[] = { + 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, + 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, + 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, + 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, + 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, + 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, + 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, + 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, + 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, + }; + typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); + exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; + cb(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return true; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @@param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + static const uint8_t k_mc_exip_region_disable[] = { + 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, + 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, + 0xe7, 0xd0, 0x82, 0x80 + }; + typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); + exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; + cb(base, index); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_enable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, + 0xf5, 0xc0, 0x82, 0x80 + }; + typedef void (*exip_enable_cb_t)(XPI_Type *); + exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; + cb(base); +} + +/** + * @brief Disable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_disable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, + 0x82, 0x80 + }; + typedef void (*exip_disable_cb_t)(XPI_Type *); + exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; + cb(base); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} /*********************************************************************************************************************** * @@ -648,6 +898,111 @@ static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8 return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); } + +/*********************************************************************************************************************** + * + * + * SM3 Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief SM4 initialization + * + * @param [in] ctx SM3 context + * @return API execution status + */ +static inline hpm_stat_t rom_sm3_init(sm3_context_t *ctx) +{ + return ROM_API_TABLE_ROOT->sm3_api_if->init(ctx); +} + +/** + * @brief SM3 update operation + * + * @param [in,out] ctx SM3 context + * @param [in] input Data for SM3 calculation + * @param [in] len length of the data for SM3 calculation + * @return API execution status + */ +static inline hpm_stat_t rom_sm3_update(sm3_context_t *ctx, const void *input, uint32_t len) +{ + return ROM_API_TABLE_ROOT->sm3_api_if->update(ctx, input, len); +} + +/** + * @brief SM3 finalize + * Return the computing SM3 digest + * + * @param [in] ctx SM3 context + * @param [out] output SM3 digest calculated by the above API + * @return API execution status + */ +static inline hpm_stat_t rom_sm3_finalize(sm3_context_t *ctx, uint8_t output[32]) +{ + return ROM_API_TABLE_ROOT->sm3_api_if->finalize(ctx, output); +} + +/*********************************************************************************************************************** + * + * + * SM4 Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Set SM4 encryption key + * + * @param [in] ctx SM4 context + * @param [in] key SM4 encryption key + */ +static inline void rom_sm4_setkey_enc(sm4_context_t *ctx, const uint8_t key[16]) +{ + ROM_API_TABLE_ROOT->sm4_api_if->setkey_enc(ctx, key); +} + +/** + * @brief Set SM4 decryption key + * + * @param [in] ctx SM4 context + * @param [in] key SM4 decryption key + */ +static inline void rom_sm4_setkey_dec(sm4_context_t *ctx, const uint8_t key[16]) +{ + ROM_API_TABLE_ROOT->sm4_api_if->setkey_dec(ctx, key); +} + +/** + * @brief SM4 ECB crypto operation(Encrypt or Decrypt) + * @param [in] ctx SM4 context + * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] input Input data + * @param [out] output Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, + uint8_t *output) +{ + return ROM_API_TABLE_ROOT->sm4_api_if->crypt_ecb(ctx, mode, length, input, output); +} + +/** + * @brief SM4 CBC crypto operation(Encrypt or Decrypt) + * @param [in] ctx SM4 context + * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] input Input data + * @param [out] output Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sm4_crypt_cbc(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], + const uint8_t *input, uint8_t *output) +{ + return ROM_API_TABLE_ROOT->sm4_api_if->crypt_cbc(ctx, mode, length, iv, input, output); +} + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi_xpi_soc_def.h index 13edd92e2c..ea3ba9e8f9 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi_xpi_soc_def.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi_xpi_soc_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -61,8 +61,7 @@ typedef enum { } xpi_clk_src_t; -typedef union -{ +typedef union { struct { uint8_t freq; bool enable_ddr; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h index 3c737107a6..6fffe29309 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -23,7 +23,8 @@ static inline void sdxc_wait_card_active(SDXC_Type *base) { base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; - while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) {} + while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) { + } /* * Assume that the BUS clock is 200MHz, while in the identification state, the SD clock is 400KHz. * - Reading the register costs about 5ns in best case, hence the loop should be (74 / 400KHz) * 1000000000 / 5 @@ -44,6 +45,22 @@ static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) } } +static inline bool sdxc_is_inverse_clock_enabled(SDXC_Type *base) +{ + volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; + return ((*reg) & (1UL << 28)) != 0U; +} + +static inline void sdxc_select_cardclk_delay_source(SDXC_Type *base, bool delay_from_pad) +{ + +} + +static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t delay_chain) +{ + +} + #if defined(__cplusplus) } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml index 5756e2ccce..8cb241610e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml @@ -4,111 +4,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -328,111 +247,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -870,111 +708,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1194,111 +951,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1736,111 +1412,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -2060,111 +1655,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -2602,111 +2116,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -2926,111 +2359,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -3468,111 +2820,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -3792,111 +3063,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -4748,28 +3938,28 @@ - + - + - + - + - + - + - + - + @@ -4811,1442 +4001,1037 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -6388,81 +5173,85 @@ + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -6561,7 +5350,7 @@ - + @@ -6572,7 +5361,7 @@ - + @@ -6583,7 +5372,7 @@ - + @@ -6594,7 +5383,7 @@ - + @@ -6605,7 +5394,7 @@ - + @@ -6616,7 +5405,7 @@ - + @@ -6627,7 +5416,7 @@ - + @@ -6638,7 +5427,7 @@ - + @@ -6649,7 +5438,7 @@ - + @@ -6660,7 +5449,7 @@ - + @@ -6671,7 +5460,7 @@ - + @@ -6682,7 +5471,7 @@ - + @@ -6693,7 +5482,7 @@ - + @@ -6704,7 +5493,7 @@ - + @@ -6715,7 +5504,7 @@ - + @@ -6726,7 +5515,7 @@ - + @@ -6737,7 +5526,7 @@ - + @@ -6748,7 +5537,7 @@ - + @@ -6759,7 +5548,7 @@ - + @@ -7048,81 +5837,85 @@ + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -7221,7 +6014,7 @@ - + @@ -7232,7 +6025,7 @@ - + @@ -7243,7 +6036,7 @@ - + @@ -7254,7 +6047,7 @@ - + @@ -7265,7 +6058,7 @@ - + @@ -7276,7 +6069,7 @@ - + @@ -7287,7 +6080,7 @@ - + @@ -7298,7 +6091,7 @@ - + @@ -7309,7 +6102,7 @@ - + @@ -7320,7 +6113,7 @@ - + @@ -7331,7 +6124,7 @@ - + @@ -7342,7 +6135,7 @@ - + @@ -7353,7 +6146,7 @@ - + @@ -7364,7 +6157,7 @@ - + @@ -7375,7 +6168,7 @@ - + @@ -7386,7 +6179,7 @@ - + @@ -7397,7 +6190,7 @@ - + @@ -7408,7 +6201,7 @@ - + @@ -7419,7 +6212,7 @@ - + @@ -7708,81 +6501,85 @@ + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -7881,7 +6678,7 @@ - + @@ -7892,7 +6689,7 @@ - + @@ -7903,7 +6700,7 @@ - + @@ -7914,7 +6711,7 @@ - + @@ -7925,7 +6722,7 @@ - + @@ -7936,7 +6733,7 @@ - + @@ -7947,7 +6744,7 @@ - + @@ -7958,7 +6755,7 @@ - + @@ -7969,7 +6766,7 @@ - + @@ -7980,7 +6777,7 @@ - + @@ -7991,7 +6788,7 @@ - + @@ -8002,7 +6799,7 @@ - + @@ -8013,7 +6810,7 @@ - + @@ -8024,7 +6821,7 @@ - + @@ -8035,7 +6832,7 @@ - + @@ -8046,7 +6843,7 @@ - + @@ -8057,7 +6854,7 @@ - + @@ -8068,7 +6865,7 @@ - + @@ -8079,7 +6876,7 @@ - + @@ -8368,6 +7165,10 @@ + + + + @@ -8416,7 +7217,7 @@ - + @@ -8901,27 +7702,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -8997,7 +7777,6 @@ - @@ -9016,27 +7795,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -9112,7 +7870,6 @@ - @@ -9131,27 +7888,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -9227,7 +7963,6 @@ - @@ -9246,27 +7981,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -9342,7 +8056,6 @@ - @@ -12920,28 +11633,28 @@ - + - + - + - + - + - + - + - + @@ -13038,28 +11751,28 @@ - + - + - + - + - + - + - + - + @@ -13156,28 +11869,28 @@ - + - + - + - + - + - + - + - + @@ -13274,34 +11987,33 @@ - + - + - + - + - + - + - + - + - @@ -17291,7 +16003,6 @@ - @@ -17310,7 +16021,6 @@ - @@ -17329,7 +16039,6 @@ - @@ -17348,7 +16057,6 @@ - @@ -17452,7 +16160,6 @@ - @@ -17471,7 +16178,6 @@ - @@ -17490,7 +16196,6 @@ - @@ -17509,7 +16214,6 @@ - @@ -17613,7 +16317,6 @@ - @@ -17632,7 +16335,6 @@ - @@ -17651,7 +16353,6 @@ - @@ -17670,7 +16371,6 @@ - @@ -17774,7 +16474,6 @@ - @@ -17793,7 +16492,6 @@ - @@ -17812,7 +16510,6 @@ - @@ -17831,7 +16528,6 @@ - @@ -19975,7 +18671,6 @@ - @@ -20024,7 +18719,6 @@ - @@ -20507,7 +19201,6 @@ - @@ -20515,6 +19208,7 @@ + @@ -20526,44 +19220,59 @@ + + + + + + + + + + + + + + + @@ -20572,7 +19281,9 @@ + + @@ -20585,6 +19296,7 @@ + @@ -20595,22 +19307,29 @@ + + + + + + + @@ -21640,6 +20359,7 @@ + @@ -21651,44 +20371,59 @@ + + + + + + + + + + + + + + + @@ -21697,7 +20432,9 @@ + + @@ -21710,6 +20447,7 @@ + @@ -21720,22 +20458,29 @@ + + + + + + + @@ -22798,10 +21543,7 @@ - - - @@ -23229,24 +21971,6 @@ - - - - - - - - - - - - - - - - - - @@ -23341,7 +22065,6 @@ - @@ -23352,12 +22075,6 @@ - - - - - - @@ -23508,132 +22225,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23697,86 +22291,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23807,20 +22321,6 @@ - - - - - - - - - - - - - - @@ -23837,20 +22337,6 @@ - - - - - - - - - - - - - - @@ -23867,20 +22353,6 @@ - - - - - - - - - - - - - - @@ -23897,30 +22369,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -24003,10 +22451,11 @@ + - + @@ -24191,50 +22640,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -24312,24 +22717,6 @@ - - - - - - - - - - - - - - - - - - @@ -24424,7 +22811,6 @@ - @@ -24435,12 +22821,6 @@ - - - - - - @@ -24591,132 +22971,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -24780,86 +23037,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -24890,20 +23067,6 @@ - - - - - - - - - - - - - - @@ -24920,20 +23083,6 @@ - - - - - - - - - - - - - - @@ -24950,20 +23099,6 @@ - - - - - - - - - - - - - - @@ -24980,30 +23115,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -25086,10 +23197,11 @@ + - + @@ -25274,55 +23386,11 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -25336,10 +23404,10 @@ - + - + @@ -25365,7 +23433,7 @@ - + @@ -25379,10 +23447,10 @@ - + - + @@ -25408,7 +23476,7 @@ - + @@ -25422,10 +23490,10 @@ - + - + @@ -25451,7 +23519,7 @@ - + @@ -25465,10 +23533,10 @@ - + - + @@ -25537,7 +23605,7 @@ - + @@ -25551,10 +23619,10 @@ - + - + @@ -25580,7 +23648,7 @@ - + @@ -25594,10 +23662,10 @@ - + - + @@ -25623,7 +23691,7 @@ - + @@ -25637,10 +23705,10 @@ - + - + @@ -25666,7 +23734,7 @@ - + @@ -25680,10 +23748,10 @@ - + - + @@ -25752,7 +23820,7 @@ - + @@ -25766,10 +23834,10 @@ - + - + @@ -25795,7 +23863,7 @@ - + @@ -25809,10 +23877,10 @@ - + - + @@ -25838,7 +23906,7 @@ - + @@ -25852,10 +23920,10 @@ - + - + @@ -25881,7 +23949,7 @@ - + @@ -25895,10 +23963,10 @@ - + - + @@ -25967,7 +24035,7 @@ - + @@ -25981,10 +24049,10 @@ - + - + @@ -26010,7 +24078,7 @@ - + @@ -26024,10 +24092,10 @@ - + - + @@ -26053,7 +24121,7 @@ - + @@ -26067,10 +24135,10 @@ - + - + @@ -26096,7 +24164,7 @@ - + @@ -26110,10 +24178,10 @@ - + - + @@ -26182,7 +24250,7 @@ - + @@ -26196,10 +24264,10 @@ - + - + @@ -26225,7 +24293,7 @@ - + @@ -26239,10 +24307,10 @@ - + - + @@ -26268,7 +24336,7 @@ - + @@ -26282,10 +24350,10 @@ - + - + @@ -26311,7 +24379,7 @@ - + @@ -26325,10 +24393,10 @@ - + - + @@ -26397,7 +24465,7 @@ - + @@ -26411,10 +24479,10 @@ - + - + @@ -26440,7 +24508,7 @@ - + @@ -26454,10 +24522,10 @@ - + - + @@ -26483,7 +24551,7 @@ - + @@ -26497,10 +24565,10 @@ - + - + @@ -26526,7 +24594,7 @@ - + @@ -26540,10 +24608,10 @@ - + - + @@ -26612,7 +24680,7 @@ - + @@ -26626,10 +24694,10 @@ - + - + @@ -26655,7 +24723,7 @@ - + @@ -26669,10 +24737,10 @@ - + - + @@ -26698,7 +24766,7 @@ - + @@ -26712,10 +24780,10 @@ - + - + @@ -26741,7 +24809,7 @@ - + @@ -26755,10 +24823,10 @@ - + - + @@ -26827,7 +24895,7 @@ - + @@ -26841,10 +24909,10 @@ - + - + @@ -26870,7 +24938,7 @@ - + @@ -26884,10 +24952,10 @@ - + - + @@ -26913,7 +24981,7 @@ - + @@ -26927,10 +24995,10 @@ - + - + @@ -26956,7 +25024,7 @@ - + @@ -26970,10 +25038,10 @@ - + - + @@ -27042,7 +25110,7 @@ - + @@ -27056,10 +25124,10 @@ - + - + @@ -27085,7 +25153,7 @@ - + @@ -27099,10 +25167,10 @@ - + - + @@ -27128,7 +25196,7 @@ - + @@ -27142,10 +25210,10 @@ - + - + @@ -27171,7 +25239,7 @@ - + @@ -27185,10 +25253,10 @@ - + - + @@ -27257,7 +25325,7 @@ - + @@ -27271,10 +25339,10 @@ - + - + @@ -27300,7 +25368,7 @@ - + @@ -27314,10 +25382,10 @@ - + - + @@ -27343,7 +25411,7 @@ - + @@ -27357,10 +25425,10 @@ - + - + @@ -27386,7 +25454,7 @@ - + @@ -27400,10 +25468,10 @@ - + - + @@ -27472,7 +25540,7 @@ - + @@ -27486,10 +25554,10 @@ - + - + @@ -27515,7 +25583,7 @@ - + @@ -27529,10 +25597,10 @@ - + - + @@ -27558,7 +25626,7 @@ - + @@ -27572,10 +25640,10 @@ - + - + @@ -27601,7 +25669,7 @@ - + @@ -27615,10 +25683,10 @@ - + - + @@ -27789,8 +25857,6 @@ - - @@ -27947,8 +26013,6 @@ - - @@ -28079,8 +26143,6 @@ - - @@ -28237,8 +26299,6 @@ - - @@ -28336,6 +26396,7 @@ + @@ -28573,8 +26634,6 @@ - - @@ -28780,6 +26839,7 @@ + @@ -29017,8 +27077,6 @@ - - @@ -29161,12 +27219,14 @@ + + @@ -29179,6 +27239,8 @@ + + @@ -29187,6 +27249,8 @@ + + @@ -29234,7 +27298,7 @@ - + @@ -29309,7 +27373,7 @@ - + @@ -29384,7 +27448,7 @@ - + @@ -29459,7 +27523,7 @@ - + @@ -29503,7 +27567,6 @@ - @@ -29619,7 +27682,7 @@ - + @@ -29627,6 +27690,9 @@ + + + @@ -29650,6 +27716,11 @@ + + + + + @@ -29692,6 +27763,22 @@ + + + + + + + + + + + + + + + + @@ -29894,7 +27981,7 @@ - + @@ -30249,7 +28336,7 @@ - + @@ -30985,7 +29072,7 @@ - + @@ -31382,12 +29469,6 @@ - - - - - - @@ -31490,94 +29571,94 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -31594,94 +29675,94 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -42264,52 +40345,52 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h index 067c709029..7c5e148244 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -99,7 +99,7 @@ #define IRQn_XPI1 86 /* XPI1 IRQ */ #define IRQn_XDMA 87 /* XDMA IRQ */ #define IRQn_HDMA 88 /* HDMA IRQ */ -#define IRQn_DRAM 89 /* DRAM IRQ */ +#define IRQn_FEMC 89 /* FEMC IRQ */ #define IRQn_RNG 90 /* RNG IRQ */ #define IRQn_I2S0 91 /* I2S0 IRQ */ #define IRQn_I2S1 92 /* I2S1 IRQ */ @@ -676,12 +676,12 @@ /* SDP base pointer */ #define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) -#include "hpm_dram_regs.h" -/* Address of DRAM instances */ -/* DRAM base address */ -#define HPM_DRAM_BASE (0xF3050000UL) -/* DRAM base pointer */ -#define HPM_DRAM ((DRAM_Type *) HPM_DRAM_BASE) +#include "hpm_femc_regs.h" +/* Address of FEMC instances */ +/* FEMC base address */ +#define HPM_FEMC_BASE (0xF3050000UL) +/* FEMC base pointer */ +#define HPM_FEMC ((FEMC_Type *) HPM_FEMC_BASE) #include "hpm_sysctl_regs.h" /* Address of SYSCTL instances */ @@ -849,8 +849,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#include "hpm_ioc_regs.h" -#include "hpm_gpiom_regs.h" -#include "hpm_sysctl_regs.h" -#include "hpm_trgm_regs.h" #endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h index 08ed7da2b4..f554062f28 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,6 +14,7 @@ * I2C Section */ #define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (256U) /* * PMIC Section @@ -30,6 +31,7 @@ */ #define I2S_SOC_MAX_CHANNEL_NUM (16U) #define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) +#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) #define PDM_I2S HPM_I2S0 #define DAO_I2S HPM_I2S1 #define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) @@ -55,7 +57,6 @@ #define PWM_SOC_PWM_MAX_COUNT (8U) #define PWM_SOC_CMP_MAX_COUNT (24U) #define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) -#define PWM_SOC_OUTPUT_MAX_COUNT (24U) /* * DMA Section @@ -81,8 +82,8 @@ #define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) /* -* USB Section -*/ + * USB Section + */ #define USB_SOC_MAX_COUNT (2U) #define USB_SOC_DCD_QTD_NEXT_INVALID (1U) @@ -97,41 +98,56 @@ #define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) #define USB_SOC_HCD_QTD_ALIGNMENT (32U) #define USB_SOC_HCD_QHD_ALIGNMENT (32U) -#define USB_SOC_HCD_MAX_ENDPOINT_COUNT (8U) -#define USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT (USB_SOC_HCD_MAX_ENDPOINT_COUNT * 2U) #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) #define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) /* -* ENET Section -*/ -#define ENET_SOC_DESC_ADDR_ALIGNMENT (16U) + * ENET Section + */ +#define ENET_SOC_RGMII_EN (1U) +#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) #define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) #define ENET_SOC_ADDR_MAX_COUNT (5U) #define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) #define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) #define ENET_SOC_ALT_EHD_DES_LEN (8U) +#define ENET_SOC_PPS_MAX_COUNT (4L) +#define ENET_SOC_PPS1_EN (0U) /* -* ADC Section -*/ + * ACMP Section + */ +#define ACMP_SOC_BANDGAP (1U) + +/* + * ADC Section + */ #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_MAX_TRIG_CH_NUM (11U) #define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) #define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) #define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (0U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (1024U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (4096U) #define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) +#define ADC_SOC_OTP_TSNS_REF25_MASK (0xffffUL) +#define ADC_SOC_OTP_TSNS_REF25_SHIFT (21U) +#define ADC_SOC_REF_TEMP (25U) +#define ADC_SOC_REF_SLOPE (1.0f/6) +#define ADC_SOC_TEMPSENS_REF25_VOL (3300U) +#define ADC_SOC_VOUT25C_MAX_SAMPLE_VALUE (65535U) #define ADC12_SOC_CLOCK_CLK_DIV (2U) #define ADC12_SOC_CALIBRATION_WAITING_LOOP_CNT (10) #define ADC12_SOC_MAX_CH_NUM (17U) -#define ADC12_SOC_TEMP_CH_NUM (18U) -#define ADC12_SOC_INVALID_TEMP_BASE (0xF0010000UL) +#define ADC12_SOC_MAX_SAMPLE_VALUE (4095U) #define ADC16_SOC_PARAMS_LEN (34U) #define ADC16_SOC_MAX_CH_NUM (7U) #define ADC16_SOC_TEMP_CH_NUM (14U) +#define ADC16_SOC_TEMP_CH_EN (1U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) /* * SYSCTL Section @@ -148,6 +164,7 @@ * CAN Section */ #define CAN_SOC_MAX_COUNT (4U) +#define CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND (1) /* Refer to E00016 in HPM6700/6400 Errata */ /* * UART Section @@ -158,19 +175,40 @@ * SPI Section */ #define SPI_SOC_TRANSFER_COUNT_MAX (512U) +#define SPI_SOC_FIFO_DEPTH (4U) /* * SDXC Section */ #define SDXC_SOC_MAX_COUNT (2) + + /* - * JPEG Section + * ROM API section */ -/*jpg file sampling factor*/ -#define JPEG_SOC_SAMPLING_FORMAT_420 (0x2211U) -#define JPEG_SOC_SAMPLING_FORMAT_422H (0x2111U) -#define JPEG_SOC_SAMPLING_FORMAT_422V (0x1211U) -#define JPEG_SOC_SAMPLING_FORMAT_444 (0x1111U) -#define JPEG_SOC_SAMPLING_FORMAT_400 (0x2200U) +#define ROMAPI_HAS_SW_SM3 (1) +#define ROMAPI_HAS_SW_SM4 (1) + +/* + * OTP Section + */ +#define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ + +/** + * PWM Section + * + */ +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (0U) + + +/** + * IOC Section + * + */ +#define IOC_SOC_PAD_MAX (491) + #endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c index 38fafa6a14..203258cd10 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,7 +11,7 @@ #define SYSCTL_RESOURCE_GROUP0 0 #define SYSCTL_RESOURCE_GROUP1 1 -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24 )) +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) static inline bool sysctl_valid_cpu_index(uint8_t cpu) { @@ -30,7 +30,7 @@ hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, return status_invalid_argument; } for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[cpu].GPR[i] ; + *(data + i) = ptr->CPU[cpu].GPR[i]; } return status_success; } @@ -180,7 +180,7 @@ uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, return frequency; } -static hpm_stat_t _sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) { if (!sysctl_valid_cpu_index(cpu)) { return status_invalid_argument; @@ -192,31 +192,12 @@ static hpm_stat_t _sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) { - return _sysctl_set_cpu_entry(ptr, 1, entry); + return sysctl_set_cpu_entry(ptr, 1, entry); } hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) { - return _sysctl_set_cpu_entry(ptr, 0, entry); -} - -void sysctl_release_cpu1(SYSCTL_Type *ptr) -{ - ptr->CPU[1].LP &= ~SYSCTL_CPU_LP_HALT_MASK; -} - -bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) -{ - return ((ptr->CPU[1].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); -} - -hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu, cpu_lp_mode_t mode) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].LP = (ptr->CPU[cpu].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); - return status_success; + return sysctl_set_cpu_entry(ptr, 0, entry); } hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, @@ -277,7 +258,7 @@ hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, return status_invalid_argument; } - switch(node) { + switch (node) { case clock_node_adc3: case clock_node_adc2: case clock_node_adc1: @@ -311,7 +292,8 @@ hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint } ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while(sysctl_clock_target_is_busy(ptr, node)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } return status_success; } @@ -330,6 +312,7 @@ hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while(sysctl_clock_target_is_busy(ptr, node)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } return status_success; } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h index 9a8f72674d..042227459b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -111,7 +111,7 @@ typedef enum { sysctl_resource_clk_top_axi1 = 69, sysctl_resource_clk_top_axi2 = 70, sysctl_resource_clk_top_ahb0 = 71, - sysctl_resource_clk_top_dram = 72, + sysctl_resource_clk_top_femc = 72, sysctl_resource_clk_top_xpi0 = 73, sysctl_resource_clk_top_xpi1 = 74, sysctl_resource_clk_top_gptmr0 = 75, @@ -184,7 +184,7 @@ typedef enum { sysctl_resource_axis = 257, sysctl_resource_axic = 258, sysctl_resource_axiv = 259, - sysctl_resource_dram = 260, + sysctl_resource_femc = 260, sysctl_resource_rom0 = 261, sysctl_resource_lmm0 = 262, sysctl_resource_lmm1 = 263, @@ -299,7 +299,7 @@ typedef enum { clock_node_axi1 = 5, clock_node_axi2 = 6, clock_node_ahb0 = 7, - clock_node_dram = 8, + clock_node_femc = 8, clock_node_xpi0 = 9, clock_node_xpi1 = 10, clock_node_gptmr0 = 11, @@ -435,7 +435,7 @@ typedef enum { monitor_target_clk_top_axi1 = 133, monitor_target_clk_top_axi2 = 134, monitor_target_clk_top_ahb0 = 135, - monitor_target_clk_top_dram = 136, + monitor_target_clk_top_femc = 136, monitor_target_clk_top_xpi0 = 137, monitor_target_clk_top_xpi1 = 138, monitor_target_clk_top_gptmr0 = 139, @@ -520,6 +520,13 @@ typedef enum { monitor_reference_24mhz = 1, } monitor_reference_t; +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + /** * @brief Monitor config */ @@ -562,7 +569,8 @@ static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t moni static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) { - while(!sysctl_monitor_result_is_valid(ptr, monitor_index)); + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } return ptr->MONITOR[monitor_index].CURRENT; } @@ -747,13 +755,37 @@ static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, * @param[in] cpu_index cpu index * @param[in] mask bit mask to clear */ -static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, +static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) { ptr->RETENTION[cpu_index].CLEAR = mask; } +/** + * @brief Disable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, + uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Disable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, + uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask); +} + /** * @brief Enable resource retention when specific CPU enters stop mode * @@ -761,13 +793,73 @@ static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, * @param[in] cpu_index cpu index * @param[in] mask bit mask to set */ -static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, +static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) { ptr->RETENTION[cpu_index].SET = mask; } +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, + uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, + uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 1, value); +} + /** * @brief Retain target domain for specific CPU * @@ -776,7 +868,7 @@ static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, * @param[in] domain target domain power to be retained * @param[in] retain_mem set true to retain memory/register of target domain */ -static inline void sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, +static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, uint8_t cpu_index, sysctl_retention_domain_t domain, bool retain_mem) @@ -788,6 +880,34 @@ static inline void sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, ptr->RETENTION[cpu_index].SET = (set_mask << domain); } +/** + * @brief Retain target domain for specific CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem); +} + /** * @brief Check if any clock is busy * @@ -902,6 +1022,32 @@ static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; } +/** + * @brief Get target CPU0 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, + uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 0, status_index); +} + +/** + * @brief Get target CPU1 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, + uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 1, status_index); +} + /** * @brief Check wakeup source status with mask * @@ -920,6 +1066,38 @@ static inline return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; } +/** + * @brief Check CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline + uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); +} + +/** + * @brief Check CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline + uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask); +} + /** * @brief Enable wakeup source status with mask * @@ -937,6 +1115,34 @@ static inline ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; } +/** + * @brief Enable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask; +} + /** * @brief Disable wakeup source status with mask * @@ -954,12 +1160,41 @@ static inline ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; } +/** + * @brief Disable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); +} + + +/** + * @brief Disable CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask); +} + /** * @brief Disable wakeup source status with irq * * @param[in] ptr SYSCTL_Type base address * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source + * @param[in] irq_num irq number to be disabled as wakeup source */ static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, @@ -968,6 +1203,31 @@ static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); } +/** + * @brief Disable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); +} + + +/** + * @brief Disable CPU1 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num); +} + /** * @brief Enable wakeup source status with irq * @@ -979,9 +1239,48 @@ static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) { - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num % 32); + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); } +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Enable CPU1 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num); +} + +/** + * @brief Lock CPU gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint16_t gpr_mask) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + + /** * @brief Lock CPU0 gpr with mask * @@ -991,7 +1290,7 @@ static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) { - ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); + sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); } /** @@ -1003,7 +1302,18 @@ static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) { - ptr->CPU[1].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); + sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask); +} + +/** + * @brief Lock CPU lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; } /** @@ -1013,7 +1323,7 @@ static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, */ static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) { - ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; + sysctl_cpu_lock(ptr, 0); } /** @@ -1023,7 +1333,155 @@ static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) */ static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr) { - ptr->CPU[1].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; + sysctl_cpu_lock(ptr, 1); +} + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) +{ + ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); +} + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 0, mode); +} + +/** + * @brief Set CPU1 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 1, mode); +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Clear CPU1 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 1, flags); +} + +/** + * @brief Get CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); +} + +/** + * @brief Get CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 0); +} + +/** + * @brief Get CPU1 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 1); +} + +/** + * @brief Release cpu + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK; +} + +/** + * @brief Release cpu1 + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) +{ + sysctl_release_cpu(ptr, 1); +} + +/** + * @brief Check whether CPU is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval true CPU is released + * @retval false CPU is on-hold + */ +static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); +} + +/** + * @brief Check whether CPU1 is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @retval true CPU1 is released + * @retval false CPU1 is on-hold + */ +static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) +{ + return sysctl_is_cpu_released(ptr, 1); } /** @@ -1052,18 +1510,6 @@ hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_i2s_t source); -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mode target mode to set - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, - uint8_t cpu_index, - cpu_lp_mode_t mode); - /** * @brief Enable group resource * @@ -1191,21 +1637,16 @@ hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); -/** - * @brief Release cpu1 - * - * @param[in] ptr SYSCTL_Type base address - */ -void sysctl_release_cpu1(SYSCTL_Type *ptr); /** - * @brief Check whether CPU1 is released or not + * @brief Set entry point on CPU boot or wakeup * - * @param [in] ptr SYSCTL_Type base address - * @retval true CPU1 is released - * @retval false CPU1 is on-hold + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu CPU index + * @param[in] entry Entry address for CPU + * @return status_success if everything is okay */ -bool sysctl_is_cpu1_released(SYSCTL_Type *ptr); +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry); /** * @brief Set entry point on CPU0 wakeup diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h index 48e2316b6c..20847100f4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -944,10 +944,10 @@ typedef struct { * * register for software to handle resume, can save resume address or status */ -#define SYSCTL_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_GPR_GPR_SHIFT (0U) -#define SYSCTL_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_GPR_GPR_SHIFT) & SYSCTL_GPR_GPR_MASK) -#define SYSCTL_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_GPR_GPR_MASK) >> SYSCTL_GPR_GPR_SHIFT) +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) /* Bitfield definition for register of struct array CPU: STATUS0 */ /* @@ -955,9 +955,9 @@ typedef struct { * * IRQ values */ -#define SYSCTL_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_WAKEUP_STATUS_STATUS_SHIFT) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) /* Bitfield definition for register of struct array CPU: ENABLE0 */ /* @@ -965,10 +965,10 @@ typedef struct { * * IRQ wakeup enable */ -#define SYSCTL_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) @@ -1007,7 +1007,7 @@ typedef struct { #define SYSCTL_RESOURCE_CLK_TOP_CONN (69UL) #define SYSCTL_RESOURCE_CLK_TOP_VIS (70UL) #define SYSCTL_RESOURCE_CLK_TOP_AHB (71UL) -#define SYSCTL_RESOURCE_CLK_TOP_DRAM (72UL) +#define SYSCTL_RESOURCE_CLK_TOP_FEMC (72UL) #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (73UL) #define SYSCTL_RESOURCE_CLK_TOP_XPI1 (74UL) #define SYSCTL_RESOURCE_CLK_TOP_GPTMR0 (75UL) @@ -1078,7 +1078,7 @@ typedef struct { #define SYSCTL_RESOURCE_AXI_BUS (257UL) #define SYSCTL_RESOURCE_CONN_BUS (258UL) #define SYSCTL_RESOURCE_VIS_BUS (259UL) -#define SYSCTL_RESOURCE_DRAM (260UL) +#define SYSCTL_RESOURCE_FEMC (260UL) #define SYSCTL_RESOURCE_ROM (261UL) #define SYSCTL_RESOURCE_LMM0 (262UL) #define SYSCTL_RESOURCE_LMM1 (263UL) @@ -1209,7 +1209,7 @@ typedef struct { #define SYSCTL_CLOCK_CLK_TOP_CONN (5UL) #define SYSCTL_CLOCK_CLK_TOP_VIS (6UL) #define SYSCTL_CLOCK_CLK_TOP_AHB (7UL) -#define SYSCTL_CLOCK_CLK_TOP_DRAM (8UL) +#define SYSCTL_CLOCK_CLK_TOP_FEMC (8UL) #define SYSCTL_CLOCK_CLK_TOP_XPI0 (9UL) #define SYSCTL_CLOCK_CLK_TOP_XPI1 (10UL) #define SYSCTL_CLOCK_CLK_TOP_GPTMR0 (11UL) @@ -1328,4 +1328,4 @@ typedef struct { #define SYSCTL_CPU_CPU1 (1UL) -#endif /* HPM_SYSCTL_H */ \ No newline at end of file +#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h index e34cb1bd5e..e737a08c7b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -226,4 +226,4 @@ typedef struct { #define TRGM_DMACFG_3 (3UL) -#endif /* HPM_TRGM_H */ \ No newline at end of file +#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h index feedbbf098..6b10ecd513 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,18 +12,18 @@ /* trgm0_input mux definitions */ #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN0 (0x2UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN1 (0x3UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN2 (0x4UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN3 (0x5UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN4 (0x6UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN5 (0x7UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN6 (0x8UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN7 (0x9UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN8 (0xAUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN9 (0xBUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN10 (0xCUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_IN11 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) @@ -723,4 +723,4 @@ -#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file +#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list index e422ffcce5..01bdca78b7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list @@ -1,10 +1,10 @@ -# Copyright 2022 hpmicro +# Copyright (c) 2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # In this file, all modules available on this part are listed CONFIG_HAS_HPMSDK_UART=y -CONFIG_HAS_HPMSDK_DRAM=y +CONFIG_HAS_HPMSDK_FEMC=y CONFIG_HAS_HPMSDK_SDP=y CONFIG_HAS_HPMSDK_LCDC=y CONFIG_HAS_HPMSDK_I2C=y diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c index d5c3a0e86e..2c0c81f64f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,6 +10,10 @@ #include "hpm_soc.h" #include "hpm_l1c_drv.h" +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + void enable_plic_feature(void) { uint32_t plic_feature = 0; @@ -17,7 +21,7 @@ void enable_plic_feature(void) /* enabled vector mode and preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; #endif -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) /* enabled preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; #endif @@ -30,7 +34,9 @@ __attribute__((weak)) void system_init(void) disable_irq_from_intc(); enable_plic_feature(); enable_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif #ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld index 1089782cf8..e169e802e7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,13 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (wx) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ + NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } SECTIONS @@ -50,6 +53,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -118,13 +130,13 @@ SECTIONS .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; - } > AXI_SRAM + PROVIDE(__ramfunc_end__ = .); + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -139,13 +151,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > DLM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > AXI_SRAM .framebuffer (NOLOAD) : { @@ -154,19 +159,47 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .stack : { + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; @@ -175,6 +208,10 @@ SECTIONS PROVIDE (_stack_safe = .); } > DLM - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld index 383517c877..4753a5ee88 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,14 @@ UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20 MEMORY { XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 768K /* AXI SRAM */ + SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M - AXI_SRAM (wx) : ORIGIN = 0x1000000, LENGTH = 2M + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M } SECTIONS @@ -50,20 +55,28 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(AXI_SRAM) : AT(__vector_load_addr__) { + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { . = ALIGN(8); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) . = ALIGN(8); __vector_ram_end__ = .; - } > AXI_SRAM - + } > ILM .data : AT(etext) { . = ALIGN(8); @@ -120,13 +133,13 @@ SECTIONS .fast : AT(etext + __data_end__ - __data_start__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; - } > AXI_SRAM + PROVIDE(__ramfunc_end__ = .); + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -141,13 +154,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > AXI_SRAM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > SDRAM .framebuffer (NOLOAD) : { @@ -156,33 +162,57 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > SDRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .stack : { + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; . = ALIGN(8); PROVIDE (_stack = .); - } > SDRAM - - .stack_safe : { - . = ALIGN(8); - . += 0x1000; - . = ALIGN(8); PROVIDE (_stack_safe = .); - } > AXI_SRAM + } > DLM - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld index 3606a3f9d8..96e99bf444 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,9 +11,14 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 768K /* AXI SRAM */ + SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M - AXI_SRAM (wx) : ORIGIN = 0x1000000, LENGTH = 2M + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -43,12 +48,12 @@ SECTIONS .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) + *(EXCLUDE_FILE (nx*.o*) .text) + *(EXCLUDE_FILE (nx*.o*) .text*) + *(EXCLUDE_FILE (nx*.o*) .rodata) + *(EXCLUDE_FILE (nx*.o*) .rodata*) + *(EXCLUDE_FILE (nx*.o*) .srodata) + *(EXCLUDE_FILE (nx*.o*) .srodata*) *(.hash) *(.dyn*) @@ -67,20 +72,28 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(AXI_SRAM) : AT(__vector_load_addr__) { + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { . = ALIGN(8); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) . = ALIGN(8); __vector_ram_end__ = .; - } > AXI_SRAM - + } > ILM .data : AT(etext) { . = ALIGN(8); @@ -137,14 +150,20 @@ SECTIONS .fast : AT(etext + __data_end__ - __data_start__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + nx*.o*(.text) + nx*.o*(.text*) + nx*.o*(.rodata) + nx*.o*(.rodata*) + nx*.o*(.srodata) + nx*.o*(.srodata*) . = ALIGN(8); - __ramfunc_end__ = .; - } > AXI_SRAM + PROVIDE(__ramfunc_end__ = .); + } > ILM __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -159,13 +178,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > AXI_SRAM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > SDRAM .framebuffer (NOLOAD) : { @@ -174,27 +186,57 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > SDRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .stack : { + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_safe = .); - } > AXI_SRAM + } > DLM - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld index e6eb786cdf..6a87b2842b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,10 +12,13 @@ UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20 MEMORY { XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (wx) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ + NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } SECTIONS @@ -51,6 +54,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -120,13 +132,13 @@ SECTIONS .fast : AT(etext + __data_end__ - __data_start__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; - } > AXI_SRAM + PROVIDE(__ramfunc_end__ = .); + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -141,13 +153,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > DLM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > AXI_SRAM .framebuffer (NOLOAD) : { @@ -156,19 +161,47 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; @@ -177,6 +210,10 @@ SECTIONS PROVIDE (_stack_safe = .); } > DLM - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld index 99846a3361..7bff4c76bd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,13 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (wx) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ + NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -23,6 +26,7 @@ __app_load_addr__ = ORIGIN(XPI0) + 0x3000; __boot_header_length__ = __boot_header_end__ - __boot_header_start__; __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + SECTIONS { .nor_cfg_option __nor_cfg_option_load_addr__ : { @@ -42,14 +46,14 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) + *(EXCLUDE_FILE (nx*.o*) .text) + *(EXCLUDE_FILE (nx*.o*) .text*) + *(EXCLUDE_FILE (nx*.o*) .rodata) + *(EXCLUDE_FILE (nx*.o*) .rodata*) + *(EXCLUDE_FILE (nx*.o*) .srodata) + *(EXCLUDE_FILE (nx*.o*) .srodata*) *(.hash) *(.dyn*) @@ -68,6 +72,15 @@ SECTIONS KEEP(*(.rel*)) } > XPI0 + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -137,14 +150,20 @@ SECTIONS .fast : AT(etext + __data_end__ - __data_start__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) + nx*.o*(.text) + nx*.o*(.text*) + nx*.o*(.rodata) + nx*.o*(.rodata*) + nx*.o*(.srodata) + nx*.o*(.srodata*) . = ALIGN(8); - __ramfunc_end__ = .; - } > AXI_SRAM + PROVIDE(__ramfunc_end__ = .); + } > ILM __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -159,13 +178,6 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > DLM - - .heap : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; } > AXI_SRAM .framebuffer (NOLOAD) : { @@ -174,19 +186,47 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .stack : { + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; @@ -195,6 +235,10 @@ SECTIONS PROVIDE (_stack_safe = .); } > DLM - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/initfini.c new file mode 100644 index 0000000000..7d2b85799c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld index d054978073..261dde48ad 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,16 +10,13 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - /* It's alias address of core0 ILM+DLM, but accessing via system bus */ - CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K - /* It's alias address of core1 ILM+DLM, but accessing via system bus */ - CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = 32M - - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ + NONCACHEABLE_RAM (w) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ + SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } SECTIONS @@ -27,18 +24,18 @@ SECTIONS .start : { . = ALIGN(8); KEEP(*(.start)) - } > CORE0_LM_SLV + } > ILM .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) KEEP(*(.vector_table)) . = ALIGN(8); - } > CORE0_LM_SLV + } > ILM .rel : { KEEP(*(.rel*)) - } > CORE0_LM_SLV + } > ILM .text : { . = ALIGN(8); @@ -59,12 +56,18 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(8); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - } > CORE0_LM_SLV + } > ILM .data : AT(etext) { . = ALIGN(8); @@ -126,9 +129,9 @@ SECTIONS *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -146,43 +149,64 @@ SECTIONS } > AXI_SRAM .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > AXI_SRAM - - .dual_core_share (NOLOAD) : { - KEEP(*(.dual_core_share)) - } > AXI_SRAM - - .heap : { . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - + KEEP(*(.framebuffer)) + . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .stack : { + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; + . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_safe = .); - } > AXI_SRAM + } > DLM - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT(__stack_base__ >= __heap_end__, "stack overlapped with heap") + ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld index d333beac88..d7bba310a0 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,16 +10,11 @@ HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - /* It's alias address of core0 ILM+DLM, but accessing via system bus */ - CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K - /* It's alias address of core1 ILM+DLM, but accessing via system bus */ - CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = 32M - - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + NONCACHEABLE_RAM (w) : ORIGIN = 0x01140000, LENGTH = 64K /* AXI SRAM1 */ + AXI_SRAM (wx) : ORIGIN = 0x01150000, LENGTH = 176K + SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K } SECTIONS @@ -27,18 +22,18 @@ SECTIONS .start : { . = ALIGN(8); KEEP(*(.start)) - } > CORE1_LM_SLV + } > ILM .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) KEEP(*(.vector_table)) . = ALIGN(8); - } > CORE1_LM_SLV + } > ILM .rel : { KEEP(*(.rel*)) - } > CORE1_LM_SLV + } > ILM .text : { . = ALIGN(8); @@ -59,12 +54,18 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(8); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - } > CORE1_LM_SLV + } > ILM .data : AT(etext) { . = ALIGN(8); @@ -126,9 +127,9 @@ SECTIONS *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM + } > ILM - .bss : { + .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) @@ -146,43 +147,56 @@ SECTIONS } > AXI_SRAM .framebuffer (NOLOAD) : { - KEEP(*(.framebuffer)) - } > AXI_SRAM - - .dual_core_share (NOLOAD) : { - KEEP(*(.dual_core_share)) - } > AXI_SRAM - - .heap : { . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - + KEEP(*(.framebuffer)) + . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE + } > NONCACHEABLE_RAM - .stack : { + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; + . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_safe = .); - } > AXI_SRAM + } > DLM - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT(__stack_base__ >= __heap_end__, "stack overlapped with heap") + ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S index 4f95d2294c..f5e1b28a4f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -40,6 +40,24 @@ _start: la t0, _stack mv sp, t0 + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + #ifndef NO_CLEANUP_AT_START /* clean up */ call _clean_up @@ -51,10 +69,24 @@ _start: csrw uitb, t0 #endif -#ifndef CONFIG_FREERTOS - #define HANDLER_TRAP SW_handler -#else +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS #define HANDLER_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap #endif #ifndef USE_NONVECTOR_MODE @@ -76,7 +108,7 @@ _start: /* System reset handler */ call reset_handler - /* Infinite loop, if returned accidently */ + /* Infinite loop, if returned accidentally */ 1: j 1b .weak exit diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c index 1d44f2e153..ed38e338a7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,25 +9,19 @@ #include "hpm_l1c_drv.h" #include "hpm_interrupt.h" -#ifdef __cplusplus -extern "C" { -#endif + extern void system_init(void); -extern void __libc_init_array(void); -extern void __libc_fini_array(void); -#ifdef __cplusplus -} -#endif + __attribute__((weak)) void _clean_up(void) { - /* clean up plic, it will help while debuging */ + /* clean up plic, it will help while debugging */ disable_irq_from_intc(); intc_m_set_threshold(0); for (uint32_t irq = 0; irq < 128; irq++) { intc_m_complete_irq(irq); } - /* clear any bits left in plic enable regster */ + /* clear any bits left in plic enable register */ for (uint32_t i = 0; i < 4; i++) { *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; } @@ -84,29 +78,19 @@ __attribute__((weak)) void c_startup(void) __attribute__((weak)) int main(void) { - while(1); + while (1) { + ; + } } __attribute__((weak)) void reset_handler(void) { l1c_dc_disable(); l1c_dc_invalidate_all(); -#if !defined(__SEGGER_RTL_VERSION) || defined(__GNU_LINKER) - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); -#endif /* Call platform specific hardware initialization */ system_init(); -#ifdef __cplusplus - /* Do global constructors */ - __libc_init_array(); -#endif - /* Entry function */ main(); } @@ -116,14 +100,14 @@ __attribute__((weak)) void reset_handler(void) * a call to __cxa_atexit() with __dso_handle as one of the arguments. * The dummy versions of these symbols should be provided. */ -void __cxa_atexit(void (*arg1)(void*), void* arg2, void* arg3) +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) { } -#ifndef __SEGGER_RTL_VERSION -void* __dso_handle = (void*) &__dso_handle; +#if !defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes) +void *__dso_handle = (void *) &__dso_handle; #endif -__attribute__((weak)) void _init() +__attribute__((weak)) void _init(void) { } diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf index 7e28e152c6..934bafc305 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf @@ -1,89 +1,111 @@ -/* - * Copyright 2021-2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ -define region DLM = [from 0x80000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 768k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM_SLV { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00080000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ +define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ +define region SHARE_RAM = [from 0x0117C000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; +define region APB_SRAM = [from 0xF40F0000 size 8k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; + +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { section .backup_sram}; + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM with fixed order { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; + +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in APB_SRAM { section .backup_sram}; // Backup SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf index 854e22e207..c8a224459d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf @@ -1,85 +1,113 @@ -/* - * Copyright 2021-2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region AXI_SRAM = [from 0x1000000 size 2M]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of AXI_SRAM with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of SDRAM { block stack }; // Stack reserved block at the end -place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00080000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 768k]; /* AXI SRAM */ +define region SHARE_RAM = [from 0x0117C000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; +define region APB_SRAM = [from 0xF40F0000 size 8k]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; + +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { section .backup_sram}; + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order { symbol _start }; + + +place at start of ILM with fixed order { block vectors }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in SDRAM { block cherryusb_usbh_class_info }; +place in SDRAM { block framebuffer }; + +place in AXI_SRAM then SDRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in APB_SRAM { section .backup_sram}; // Backup SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in SDRAM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .uf2_signature }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf index 23f6c2d968..13fc9264f4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf @@ -1,96 +1,120 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region AXI_SRAM = [from 0x1000000 size 2M]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of AXI_SRAM with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in SDRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SDRAM { block heap }; // Heap reserved block -place at end of SDRAM { block stack }; // Stack reserved block at the end -place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x0C00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region XPI0 = [from 0x80003000 size (_flash_size - 0x3000) ]; /* XPI0 */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00080000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 768k]; /* AXI SRAM */ +define region SHARE_RAM = [from 0x0117C000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; +define region APB_SRAM = [from 0xF40F0000 size 8k]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; + +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { section .backup_sram}; + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; +place at start of ILM with fixed order { block vectors }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.*, section .text.*nx*, // "ramfunc" section + }; + +place in SDRAM { block cherryusb_usbh_class_info }; +place in SDRAM { block framebuffer }; + +place in AXI_SRAM then SDRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in APB_SRAM { section .backup_sram}; // Backup SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in SDRAM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf index fe190a9225..258d55b101 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf @@ -1,92 +1,113 @@ -/* - * Copyright 2021-2022 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ -define region DLM = [from 0x80000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 768k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order {symbol _start}; -keep { section .uf2_signature }; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM_SLV { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00080000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ +define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ +define region SHARE_RAM = [from 0x0117C000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; +define region APB_SRAM = [from 0xF40F0000 size 8k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; + +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { section .backup_sram}; + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +initialize by copy { block vectors }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order { symbol _start }; + +place at start of ILM with fixed order { block vectors }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; + +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in APB_SRAM { section .backup_sram}; // Backup SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .uf2_signature }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf index 273c6b0a38..48c4804fef 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf @@ -1,103 +1,121 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ -define region DLM = [from 0x80000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x1080000 size 768k]; -define region SDRAM = [from 0x40000000 size _extram_size]; -define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; - -define block framebuffer with alignment = 8 { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block safe_stack + 1; -define exported symbol _stack = end of block stack + 1; - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM_SLV with fixed order { block vectors }; -initialize by copy { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM_SLV { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in DLM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in AXI_SRAM { block framebuffer }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack }; // Stack reserved block at the end -place at end of DLM { block safe_stack }; // Safe stack reserved block at the end +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x0C00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region XPI0 = [from 0x80003000 size (_flash_size - 0x3000) ]; /* XPI0 */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00080000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ +define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ +define region SHARE_RAM = [from 0x0117C000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; +define region APB_SRAM = [from 0xF40F0000 size 8k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; + +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { section .backup_sram}; + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; +place at start of ILM with fixed order { block vectors }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.*, section .text.*nx*, // "ramfunc" section + }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; + +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in APB_SRAM { section .backup_sram}; // Backup SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf index 28076234d2..4476af4ceb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf @@ -1,79 +1,98 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ -define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ -define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ -define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block framebuffer { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; -define exported symbol _stack_safe = end of block safe_stack + 1; - - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of CORE0_LM_SLV { symbol _start }; -place in CORE0_LM_SLV { block vectors }; // Vector table section -place in CORE0_LM_SLV with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec, // Catch-all for (readonly) executable code (e.g. .text) - section .fast, section .fast.*, // "ramfunc" section - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -/* Explicit placement in AXI_SRAM */ -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00080000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ +define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ +define region SHARE_RAM = [from 0x0117C000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; +define region APB_SRAM = [from 0xF40F0000 size 8k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block cherryusb_usbh_class_info { section .usbh_class_info }; +define block framebuffer { section .framebuffer }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { section .backup_sram}; + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in APB_SRAM { section .backup_sram}; // Backup SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf index e7617c78e7..1c778b0389 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf @@ -1,79 +1,94 @@ -/* - * Copyright 2021 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ -define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ -define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ -define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; - -/* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; -define block framebuffer { section .framebuffer }; -define block safe_stack with size = 512, readwrite access {}; -define exported symbol _stack_safe = end of block safe_stack + 1; - - -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -place at start of CORE1_LM_SLV { symbol _start }; -place in CORE1_LM_SLV { block vectors }; // Vector table section -place in CORE1_LM_SLV with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec, // Catch-all for (readonly) executable code (e.g. .text) - section .fast, section .fast.*, // "ramfunc" section - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -/* Explicit placement in AXI_SRAM */ -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM with auto order { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AXI_SRAM { block heap }; // Heap reserved block -place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end +/* + * Copyright (c) 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00080000 size 256k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01140000 size 64k]; /* AXI SRAM1 */ +define region AXI_SRAM = [from 0x01150000 size 176k]; +define region SHARE_RAM = [from 0x0117C000 size 16k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block cherryusb_usbh_class_info { section .usbh_class_info }; +define block framebuffer { section .framebuffer }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s index 75872e000f..3b6c089188 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s @@ -38,20 +38,20 @@ File : SEGGER_RISCV_crt0.s Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce + Designed to work with the SEGGER linker to produce smallest possible executables. - + This file does not normally require any customization. Additional information: Preprocessor Definitions FULL_LIBRARY - If defined then + If defined then - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - the exit symbol is defined and executes on return from main. - the exit symbol calls destructors, atexit functions and then calls SEGGER_SEMIHOST_Exit(). - + If not defined then - argc and argv are not valid (main is assumed to not take parameters) - the exit symbol is defined, executes on return from main and @@ -147,16 +147,16 @@ Additional information: * _start * * Function description -* Entry point for the startup code. +* Entry point for the startup code. * Usually called by the reset handler. -* Performs all initialisation, based on the entries in the +* Performs all initialisation, based on the entries in the * linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an +* It is device independent, so there should not be any need for an * end-user to modify it. * * Additional information -* At this point, the stack pointer should already have been -* initialized +* At this point, the stack pointer should already have been +* initialized * - by hardware (such as on Cortex-M), * - by the device-specific reset handler, * - or by the debugger (such as for RAM Code). @@ -171,7 +171,7 @@ START_FUNC _start addi gp, gp, %lo(__global_pointer$) lui tp, %hi(__thread_pointer$) addi tp, tp, %lo(__thread_pointer$) - .option pop + .option pop csrw mstatus, zero csrw mcause, zero @@ -207,7 +207,7 @@ START_FUNC _start // * Call constructors of global Objects (if any exist) // la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): +L(RunInit): lw a0, (s0) // Get next initialization function from table add s0, s0, 4 // Increment table pointer to point to function arguments jalr a0 // Call initialization function @@ -223,10 +223,27 @@ MARK_FUNC __SEGGER_init_done call _clean_up #endif -#ifndef CONFIG_FREERTOS - #define HANDLER_TRAP SW_handler -#else +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap #endif #ifndef USE_NONVECTOR_MODE @@ -248,7 +265,7 @@ MARK_FUNC __SEGGER_init_done MARK_FUNC start #ifndef FULL_LIBRARY // - // In a real embedded application ("Free-standing environment"), + // In a real embedded application ("Free-standing environment"), // main() does not get any arguments, // which means it is not necessary to init a0 and a1. // @@ -269,10 +286,10 @@ MARK_FUNC exit .size exit,.-exit #else // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle + // In a hosted environment, + // we need to load a0 and a1 with argc and argv, in order to handle // the command line arguments. - // This is required for some programs running under control of a + // This is required for some programs running under control of a // debugger, such as automated tests. // li a0, ARGSSPACE @@ -296,14 +313,14 @@ END_FUNC _start #else li a0, 0 li a1, 0 -#endif +#endif call APP_ENTRY_POINT tail exit - + END_FUNC _start - // + // #ifdef FULL_LIBRARY /********************************************************************* * @@ -311,14 +328,14 @@ END_FUNC _start * * Function description * Exit of the system. -* Called on return from application entry point or explicit call +* Called on return from application entry point or explicit call * to exit. * * Additional information * In a hosted environment exit gracefully, by * saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, +* calling destructurs of global objects, +* calling registered atexit functions, * and notifying the host/debugger. */ #undef L @@ -334,8 +351,8 @@ L(Loop): la t0, __dtors_end__ beq s0, t0, L(End) lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 + addi s0, s0, 4 + jalr t1 j L(Loop) L(End): // @@ -369,5 +386,5 @@ nmi_handler: 1: j 1b #include "../vectors.h" - + /*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c index de883dce02..ae000f4005 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -88,17 +88,17 @@ __attribute__((weak)) long exception_handler(long cause, long epc) return epc; } -#ifndef CONFIG_FREERTOS -void SW_handler(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); #else -void SW_handler(void) __attribute__ ((section(".isr_vector"))); +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); #endif -void SW_handler(void) +void irq_handler_trap(void) { long mcause = read_csr(CSR_MCAUSE); long mepc = read_csr(CSR_MEPC); long mstatus = read_csr(CSR_MSTATUS); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH long mxstatus = read_csr(CSR_MXSTATUS); #endif #ifdef __riscv_dsp @@ -129,7 +129,7 @@ void SW_handler(void) uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); if (irq_index) { /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif ((isr_func_t)__vector_table[irq_index])(); @@ -167,7 +167,7 @@ void SW_handler(void) /* Restore CSR */ write_csr(CSR_MSTATUS, mstatus); write_csr(CSR_MEPC, mepc); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH write_csr(CSR_MXSTATUS, mxstatus); #endif #ifdef __riscv_dsp diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h index c64c586819..c1ab56467b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -112,7 +112,7 @@ __vector_table: IRQ_HANDLER 86 /* XPI1 IRQ handler */ IRQ_HANDLER 87 /* XDMA IRQ handler */ IRQ_HANDLER 88 /* HDMA IRQ handler */ - IRQ_HANDLER 89 /* DRAM IRQ handler */ + IRQ_HANDLER 89 /* FEMC IRQ handler */ IRQ_HANDLER 90 /* RNG IRQ handler */ IRQ_HANDLER 91 /* I2S0 IRQ handler */ IRQ_HANDLER 92 /* I2S1 IRQ handler */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h index 9b7f6a5149..c898ee71fa 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -261,4 +261,4 @@ typedef struct { #define ACMP_CHANNEL_CHN3 (3UL) -#endif /* HPM_ACMP_H */ \ No newline at end of file +#endif /* HPM_ACMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h index 4a1ff204b0..0e319e5b75 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,7 +12,8 @@ typedef struct { __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __R uint8_t RESERVED0[972]; /* 0x34 - 0x3FF: Reserved */ + __RW uint32_t TRG_SW_STA; /* 0x34: */ + __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ __R uint32_t BUS_RESULT[19]; /* 0x400 - 0x448: */ __R uint8_t RESERVED1[180]; /* 0x44C - 0x4FF: Reserved */ __RW uint32_t BUF_CFG0; /* 0x500: */ @@ -147,6 +148,29 @@ typedef struct { #define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) #define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) +/* Bitfield definition for register: TRG_SW_STA */ +/* + * TRG_SW_STA (RW) + * + * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + */ +#define ADC12_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) +#define ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) +#define ADC12_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC12_TRG_SW_STA_TRG_SW_STA_MASK) +#define ADC12_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC12_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT) + +/* + * TRIG_SW_INDEX (RW) + * + * which trigger for the SW trigger + * 0 for trig0a, 1 for trig0b… + * 3 for trig1a, …11 for trig3c + */ +#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) +#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) +#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK) +#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) + /* Bitfield definition for register array: BUS_RESULT */ /* * VALID (RO) @@ -167,8 +191,8 @@ typedef struct { * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long */ -#define ADC12_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC12_BUS_RESULT_CHAN_RESULT_SHIFT (0U) +#define ADC12_BUS_RESULT_CHAN_RESULT_MASK (0xFFF0U) +#define ADC12_BUS_RESULT_CHAN_RESULT_SHIFT (4U) #define ADC12_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_BUS_RESULT_CHAN_RESULT_MASK) >> ADC12_BUS_RESULT_CHAN_RESULT_SHIFT) /* Bitfield definition for register: BUF_CFG0 */ @@ -390,8 +414,8 @@ typedef struct { * adc convert result, update after each valid conversion. * it may be updated period according to config, also may be updated due to other queue convert the same channel */ -#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) +#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFF0U) +#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (4U) #define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) /* Bitfield definition for register array: SAMPLE_CFG */ @@ -442,8 +466,12 @@ typedef struct { * CLOCK_DIVIDER (RW) * * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. - * set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + * 0 for same adc_clk and bus_clk, + * 1 for 1:2, + * 2 for 1:3, + * ... + * 15 for 1:16 + * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk */ #define ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) #define ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) @@ -942,4 +970,4 @@ typedef struct { #define ADC12_SAMPLE_CFG_CHN18 (18UL) -#endif /* HPM_ADC12_H */ \ No newline at end of file +#endif /* HPM_ADC12_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h index c12798389c..865d0d475c 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,7 +12,8 @@ typedef struct { __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __R uint8_t RESERVED0[972]; /* 0x34 - 0x3FF: Reserved */ + __RW uint32_t TRG_SW_STA; /* 0x34: */ + __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */ __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */ __RW uint32_t BUF_CFG0; /* 0x500: */ @@ -161,6 +162,29 @@ typedef struct { #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) #define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) +/* Bitfield definition for register: TRG_SW_STA */ +/* + * TRG_SW_STA (RW) + * + * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + */ +#define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) +#define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) +#define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) +#define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) + +/* + * TRIG_SW_INDEX (RW) + * + * which trigger for the SW trigger + * 0 for trig0a, 1 for trig0b… + * 3 for trig1a, …11 for trig3c + */ +#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) +#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) +#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) +#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) + /* Bitfield definition for register array: BUS_RESULT */ /* * VALID (RO) @@ -186,6 +210,16 @@ typedef struct { #define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) /* Bitfield definition for register: BUF_CFG0 */ +/* + * BUS_MODE_EN (RW) + * + * bus mode enable + */ +#define ADC16_BUF_CFG0_BUS_MODE_EN_MASK (0x2U) +#define ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT (1U) +#define ADC16_BUF_CFG0_BUS_MODE_EN_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK) +#define ADC16_BUF_CFG0_BUS_MODE_EN_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK) >> ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT) + /* * WAIT_DIS (RW) * @@ -285,7 +319,7 @@ typedef struct { * HW update this field after each dma write, it indicate the next dma write pointer. * dma write address is (tar_addr+seq_wr_pointer)*4 */ -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFU) +#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFFFFUL) #define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U) #define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT) @@ -446,8 +480,12 @@ typedef struct { * CLOCK_DIVIDER (RW) * * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. - * set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. + * 0 for same adc_clk and bus_clk, + * 1 for 1:2, + * 2 for 1:3, + * ... + * 15 for 1:16 + * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk */ #define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) #define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) @@ -843,7 +881,7 @@ typedef struct { * COV_END_CNT (RW) * * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number). + * should set to (21-convert_clock_number+1). */ #define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) #define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) @@ -975,4 +1013,4 @@ typedef struct { #define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) -#endif /* HPM_ADC16_H */ \ No newline at end of file +#endif /* HPM_ADC16_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h index e9ee8e040f..54dc15aef6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -109,4 +109,4 @@ typedef struct { -#endif /* HPM_BACC_H */ \ No newline at end of file +#endif /* HPM_BACC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h index 1a2fa3b072..9bac0efb10 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,10 +24,10 @@ typedef struct { * * security key data */ -#define BKEY_DATA_DATA_MASK (0xFFFFFFFFUL) -#define BKEY_DATA_DATA_SHIFT (0U) -#define BKEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_DATA_DATA_SHIFT) & BKEY_DATA_DATA_MASK) -#define BKEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_DATA_DATA_MASK) >> BKEY_DATA_DATA_SHIFT) +#define BKEY_KEY_DATA_DATA_MASK (0xFFFFFFFFUL) +#define BKEY_KEY_DATA_DATA_SHIFT (0U) +#define BKEY_KEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_KEY_DATA_DATA_SHIFT) & BKEY_KEY_DATA_DATA_MASK) +#define BKEY_KEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_KEY_DATA_DATA_MASK) >> BKEY_KEY_DATA_DATA_SHIFT) /* Bitfield definition for register array: ECC */ /* @@ -98,4 +98,4 @@ typedef struct { #define BKEY_ECC_KEY1 (1UL) -#endif /* HPM_BKEY_H */ \ No newline at end of file +#endif /* HPM_BKEY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h index 22df7ec6d8..1df7b1c81e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,7 +13,8 @@ typedef struct { struct { __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - } MONITOR[3]; + __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ + } MONITOR[2]; } BMON_Type; @@ -59,7 +60,7 @@ typedef struct { /* MONITOR register group index macro definition */ #define BMON_MONITOR_GLITCH0 (0UL) -#define BMON_MONITOR_CLOCK0 (2UL) +#define BMON_MONITOR_CLOCK0 (1UL) -#endif /* HPM_BMON_H */ \ No newline at end of file +#endif /* HPM_BMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h index c7af45067b..8453ab18a4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -242,4 +242,4 @@ typedef struct { -#endif /* HPM_BSEC_H */ \ No newline at end of file +#endif /* HPM_BSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h index 0eeb899ec9..96fc00c580 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -230,4 +230,4 @@ typedef struct { -#endif /* HPM_BUTN_H */ \ No newline at end of file +#endif /* HPM_BUTN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h index 0a3a034d98..b0db9cc101 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,7 +15,7 @@ typedef struct { __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ __RW uint32_t CR2; /* 0x10: Control 2 Register */ __R uint8_t RESERVED1[16]; /* 0x14 - 0x23: Reserved */ - __W uint32_t STA; /* 0x24: Status Register */ + __RW uint32_t STA; /* 0x24: Status Register */ __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ __RW uint32_t DMASA_FB1; /* 0x30: Pixel DMA Frame Buffer 1 Address */ __RW uint32_t DMASA_FB2; /* 0x34: Pixel DMA Frame Buffer 2 Address */ @@ -35,10 +35,28 @@ typedef struct { __RW uint32_t CLRKEY_HIGH; /* 0x80: High Color Key Register */ __R uint8_t RESERVED5[12]; /* 0x84 - 0x8F: Reserved */ __R uint32_t HISTOGRAM_FIFO[256]; /* 0x90 - 0x48C: Histogram Registers */ + __RW uint32_t ROI_WIDTH; /* 0x490: Roi Width Config Register */ + __RW uint32_t ROI_HEIGHT; /* 0x494: Roi Width Config Register */ + __RW uint32_t PRO_CTRL; /* 0x498: Pro Config Register */ + __RW uint32_t ACT_SIZE; /* 0x49C: actual size */ + __RW uint32_t VSYNC_VALID_CNT; /* 0x4A0: vsync valid counter */ + __RW uint32_t HSYNC_VALID_CNT; /* 0x4A4: hsync valid counter */ + __RW uint32_t VALID_MARGIN; /* 0x4A8: valid margin */ + __RW uint32_t ALARM_SET; /* 0x4AC: alarm set */ } CAM_Type; /* Bitfield definition for register: CR1 */ +/* + * INV_DEN (RW) + * + * invert den pad input before it is used + */ +#define CAM_CR1_INV_DEN_MASK (0x40000000UL) +#define CAM_CR1_INV_DEN_SHIFT (30U) +#define CAM_CR1_INV_DEN_SET(x) (((uint32_t)(x) << CAM_CR1_INV_DEN_SHIFT) & CAM_CR1_INV_DEN_MASK) +#define CAM_CR1_INV_DEN_GET(x) (((uint32_t)(x) & CAM_CR1_INV_DEN_MASK) >> CAM_CR1_INV_DEN_SHIFT) + /* * COLOR_EXT (RW) * @@ -184,8 +202,11 @@ typedef struct { * COLOR_FORMATS (RW) * * input color formats: - * 0010b: 24bit: RGB888 - * 0100b: 16bit: RGB565 + * 0010b:24bit:RGB888 + * 0011b:24bit:RGB666 + * 0100b:16bit:RGB565 + * 0101b:16bit:RGB444 + * 0110b:16bit:RGB555 * 0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) * YUV * YCrCb @@ -203,6 +224,7 @@ typedef struct { * the bit width of the sensor * 0: 8 bits * 1: 10 bits + * 3:24bits * Others: Undefined */ #define CAM_CR1_SENSOR_BIT_WIDTH_MASK (0x7U) @@ -307,7 +329,7 @@ typedef struct { /* Bitfield definition for register: CR2 */ /* - * FRMCNT_15_0 (ROI) + * FRMCNT_15_0 (RO) * * Frame Counter. This is a 16-bit Frame Counter * (Wraps around automatically after reaching the maximum) @@ -750,7 +772,7 @@ typedef struct { /* Bitfield definition for register array: HISTOGRAM_FIFO */ /* - * HIST_Y (ROI) + * HIST_Y (RO) * * the appearance of bin x (x=(address-DATA0)/4) */ @@ -758,6 +780,283 @@ typedef struct { #define CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT (0U) #define CAM_HISTOGRAM_FIFO_HIST_Y_GET(x) (((uint32_t)(x) & CAM_HISTOGRAM_FIFO_HIST_Y_MASK) >> CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT) +/* Bitfield definition for register: ROI_WIDTH */ +/* + * ROI_WIDTH_END (RW) + * + * end address of width for roi + */ +#define CAM_ROI_WIDTH_ROI_WIDTH_END_MASK (0xFFFF0000UL) +#define CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT (16U) +#define CAM_ROI_WIDTH_ROI_WIDTH_END_SET(x) (((uint32_t)(x) << CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT) & CAM_ROI_WIDTH_ROI_WIDTH_END_MASK) +#define CAM_ROI_WIDTH_ROI_WIDTH_END_GET(x) (((uint32_t)(x) & CAM_ROI_WIDTH_ROI_WIDTH_END_MASK) >> CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT) + +/* + * ROI_WIDTH_START (RW) + * + * start address of width for roi + */ +#define CAM_ROI_WIDTH_ROI_WIDTH_START_MASK (0xFFFFU) +#define CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT (0U) +#define CAM_ROI_WIDTH_ROI_WIDTH_START_SET(x) (((uint32_t)(x) << CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT) & CAM_ROI_WIDTH_ROI_WIDTH_START_MASK) +#define CAM_ROI_WIDTH_ROI_WIDTH_START_GET(x) (((uint32_t)(x) & CAM_ROI_WIDTH_ROI_WIDTH_START_MASK) >> CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT) + +/* Bitfield definition for register: ROI_HEIGHT */ +/* + * ROI_HEIGHT_END (RW) + * + * end address of height for roi + */ +#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK (0xFFFF0000UL) +#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT (16U) +#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_SET(x) (((uint32_t)(x) << CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT) & CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK) +#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_GET(x) (((uint32_t)(x) & CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK) >> CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT) + +/* + * ROI_HEIGHT_START (RW) + * + * start address of height for roi + */ +#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK (0xFFFFU) +#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT (0U) +#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_SET(x) (((uint32_t)(x) << CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT) & CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK) +#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_GET(x) (((uint32_t)(x) & CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK) >> CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT) + +/* Bitfield definition for register: PRO_CTRL */ +/* + * ASYNC_FIFO_SEL (RW) + * + * 0 use fifo for sync + * 1 use flipflop for sync + */ +#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_MASK (0x8000U) +#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_SHIFT (15U) +#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ASYNC_FIFO_SEL_SHIFT) & CAM_PRO_CTRL_ASYNC_FIFO_SEL_MASK) +#define CAM_PRO_CTRL_ASYNC_FIFO_SEL_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ASYNC_FIFO_SEL_MASK) >> CAM_PRO_CTRL_ASYNC_FIFO_SEL_SHIFT) + +/* + * ERR_INJECT (RW) + * + * 0 generate alarm in normal mode + * 1 force to generate fatal alarm + */ +#define CAM_PRO_CTRL_ERR_INJECT_MASK (0x4000U) +#define CAM_PRO_CTRL_ERR_INJECT_SHIFT (14U) +#define CAM_PRO_CTRL_ERR_INJECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ERR_INJECT_SHIFT) & CAM_PRO_CTRL_ERR_INJECT_MASK) +#define CAM_PRO_CTRL_ERR_INJECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ERR_INJECT_MASK) >> CAM_PRO_CTRL_ERR_INJECT_SHIFT) + +/* + * BAYER_BIG_ENDIAN (RW) + * + * 0 bayer data is little-endian + * 1 bayer data is big-endian + */ +#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_MASK (0x2000U) +#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SHIFT (13U) +#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SHIFT) & CAM_PRO_CTRL_BAYER_BIG_ENDIAN_MASK) +#define CAM_PRO_CTRL_BAYER_BIG_ENDIAN_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_BAYER_BIG_ENDIAN_MASK) >> CAM_PRO_CTRL_BAYER_BIG_ENDIAN_SHIFT) + +/* + * READY_ERROR (W1C) + * + * indicate cam_te_b0_ready and cam_te_b1_ready assert at the same time + * clear by writing 1 + */ +#define CAM_PRO_CTRL_READY_ERROR_MASK (0x1000U) +#define CAM_PRO_CTRL_READY_ERROR_SHIFT (12U) +#define CAM_PRO_CTRL_READY_ERROR_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_READY_ERROR_SHIFT) & CAM_PRO_CTRL_READY_ERROR_MASK) +#define CAM_PRO_CTRL_READY_ERROR_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_READY_ERROR_MASK) >> CAM_PRO_CTRL_READY_ERROR_SHIFT) + +/* + * READY_ENABLE (RO) + * + * indicate cam_in_init assert + */ +#define CAM_PRO_CTRL_READY_ENABLE_MASK (0x800U) +#define CAM_PRO_CTRL_READY_ENABLE_SHIFT (11U) +#define CAM_PRO_CTRL_READY_ENABLE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_READY_ENABLE_MASK) >> CAM_PRO_CTRL_READY_ENABLE_SHIFT) + +/* + * READY_DISABLE (RW) + * + * indicate cam_out_init de-assert + */ +#define CAM_PRO_CTRL_READY_DISABLE_MASK (0x400U) +#define CAM_PRO_CTRL_READY_DISABLE_SHIFT (10U) +#define CAM_PRO_CTRL_READY_DISABLE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_READY_DISABLE_SHIFT) & CAM_PRO_CTRL_READY_DISABLE_MASK) +#define CAM_PRO_CTRL_READY_DISABLE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_READY_DISABLE_MASK) >> CAM_PRO_CTRL_READY_DISABLE_SHIFT) + +/* + * BUFFER_SWITCH (RW) + * + * 00 switch buffer every frame + * 01 switch buffer every 8 lines + * 10 switch buffer every 16 lines + */ +#define CAM_PRO_CTRL_BUFFER_SWITCH_MASK (0x300U) +#define CAM_PRO_CTRL_BUFFER_SWITCH_SHIFT (8U) +#define CAM_PRO_CTRL_BUFFER_SWITCH_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_BUFFER_SWITCH_SHIFT) & CAM_PRO_CTRL_BUFFER_SWITCH_MASK) +#define CAM_PRO_CTRL_BUFFER_SWITCH_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_BUFFER_SWITCH_MASK) >> CAM_PRO_CTRL_BUFFER_SWITCH_SHIFT) + +/* + * ROI_UPDATE (RW) + * + * roi configration update + */ +#define CAM_PRO_CTRL_ROI_UPDATE_MASK (0x80U) +#define CAM_PRO_CTRL_ROI_UPDATE_SHIFT (7U) +#define CAM_PRO_CTRL_ROI_UPDATE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ROI_UPDATE_SHIFT) & CAM_PRO_CTRL_ROI_UPDATE_MASK) +#define CAM_PRO_CTRL_ROI_UPDATE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ROI_UPDATE_MASK) >> CAM_PRO_CTRL_ROI_UPDATE_SHIFT) + +/* + * SCALE_UPDATE (RW) + * + * scale configration update + */ +#define CAM_PRO_CTRL_SCALE_UPDATE_MASK (0x40U) +#define CAM_PRO_CTRL_SCALE_UPDATE_SHIFT (6U) +#define CAM_PRO_CTRL_SCALE_UPDATE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_UPDATE_SHIFT) & CAM_PRO_CTRL_SCALE_UPDATE_MASK) +#define CAM_PRO_CTRL_SCALE_UPDATE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_UPDATE_MASK) >> CAM_PRO_CTRL_SCALE_UPDATE_SHIFT) + +/* + * SCALE_HEIGHT_SELECT (RW) + * + * 000 keep all pixel for height + * 001 keep 1 for every 2 pixel for height + * 010 keep 1 for every 3 pixel for height + * 011 keep 1 for every 4 pixel for height + * 100 keep 1 for every 5 pixel for height + * 101 keep 1 for every 6 pixel for height + * 110 keep 1 for every 7 pixel for height + * 111 keep 1 for every 8 pixel for height + */ +#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK (0x38U) +#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT (3U) +#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT) & CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK) +#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK) >> CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT) + +/* + * SCALE_WIDTH_SELECT (RW) + * + * 000 keep all pixel for width + * 001 keep 1 for every 2 pixel for width + * 010 keep 1 for every 3 pixel for width + * 011 keep 1 for every 4 pixel for width + * 100 keep 1 for every 5 pixel for width + * 101 keep 1 for every 6 pixel for width + * 110 keep 1 for every 7 pixel for width + * 111 keep 1 for every 8 pixel for width + */ +#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK (0x7U) +#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT (0U) +#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT) & CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK) +#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK) >> CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT) + +/* Bitfield definition for register: ACT_SIZE */ +/* + * ACT_HEIGHT (RW) + * + * actual height after scale and/or roi + */ +#define CAM_ACT_SIZE_ACT_HEIGHT_MASK (0xFFFF0000UL) +#define CAM_ACT_SIZE_ACT_HEIGHT_SHIFT (16U) +#define CAM_ACT_SIZE_ACT_HEIGHT_SET(x) (((uint32_t)(x) << CAM_ACT_SIZE_ACT_HEIGHT_SHIFT) & CAM_ACT_SIZE_ACT_HEIGHT_MASK) +#define CAM_ACT_SIZE_ACT_HEIGHT_GET(x) (((uint32_t)(x) & CAM_ACT_SIZE_ACT_HEIGHT_MASK) >> CAM_ACT_SIZE_ACT_HEIGHT_SHIFT) + +/* + * ACT_WIDTH (RW) + * + * actual width after scale and/or roi + */ +#define CAM_ACT_SIZE_ACT_WIDTH_MASK (0xFFFFU) +#define CAM_ACT_SIZE_ACT_WIDTH_SHIFT (0U) +#define CAM_ACT_SIZE_ACT_WIDTH_SET(x) (((uint32_t)(x) << CAM_ACT_SIZE_ACT_WIDTH_SHIFT) & CAM_ACT_SIZE_ACT_WIDTH_MASK) +#define CAM_ACT_SIZE_ACT_WIDTH_GET(x) (((uint32_t)(x) & CAM_ACT_SIZE_ACT_WIDTH_MASK) >> CAM_ACT_SIZE_ACT_WIDTH_SHIFT) + +/* Bitfield definition for register: VSYNC_VALID_CNT */ +/* + * VSYNC_VALID_CNT (RW) + * + * vsync valid counter + */ +#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK (0xFFFFFFFFUL) +#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT (0U) +#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SET(x) (((uint32_t)(x) << CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT) & CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK) +#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_GET(x) (((uint32_t)(x) & CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK) >> CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT) + +/* Bitfield definition for register: HSYNC_VALID_CNT */ +/* + * HSYNC_VALID_CNT (RW) + * + * hsync valid counter + */ +#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK (0xFFFFFFFFUL) +#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT (0U) +#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SET(x) (((uint32_t)(x) << CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT) & CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK) +#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_GET(x) (((uint32_t)(x) & CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK) >> CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT) + +/* Bitfield definition for register: VALID_MARGIN */ +/* + * HSYNC_VALID_MARGIN (RW) + * + * hsync valid margin + */ +#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK (0xFFFF0000UL) +#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT (16U) +#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SET(x) (((uint32_t)(x) << CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT) & CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK) +#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_GET(x) (((uint32_t)(x) & CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK) >> CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT) + +/* + * VSYNC_VALID_MARGIN (RW) + * + * vsync valid margin + */ +#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK (0xFFFFU) +#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT (0U) +#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SET(x) (((uint32_t)(x) << CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT) & CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK) +#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_GET(x) (((uint32_t)(x) & CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK) >> CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT) + +/* Bitfield definition for register: ALARM_SET */ +/* + * SIG_NORMAL (RW) + * + * define signal duty cycles(base clock) + * 0x0: disable signal + * 0x1: high 1, low 15 + * 0x2: high 2, low 14 + * …... + * 0xF: high 15, low 1 + */ +#define CAM_ALARM_SET_SIG_NORMAL_MASK (0xF00000UL) +#define CAM_ALARM_SET_SIG_NORMAL_SHIFT (20U) +#define CAM_ALARM_SET_SIG_NORMAL_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_SIG_NORMAL_SHIFT) & CAM_ALARM_SET_SIG_NORMAL_MASK) +#define CAM_ALARM_SET_SIG_NORMAL_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_SIG_NORMAL_MASK) >> CAM_ALARM_SET_SIG_NORMAL_SHIFT) + +/* + * FATAL_NORMAL (RW) + * + * define signal duty cycles(base clock) + * 0x0: disable signal + * 0x1: high 1, low 15 + * 0x2: high 2, low 14 + * …... + * 0xF: high 15, low 1 + */ +#define CAM_ALARM_SET_FATAL_NORMAL_MASK (0xF0000UL) +#define CAM_ALARM_SET_FATAL_NORMAL_SHIFT (16U) +#define CAM_ALARM_SET_FATAL_NORMAL_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_FATAL_NORMAL_SHIFT) & CAM_ALARM_SET_FATAL_NORMAL_MASK) +#define CAM_ALARM_SET_FATAL_NORMAL_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_FATAL_NORMAL_MASK) >> CAM_ALARM_SET_FATAL_NORMAL_SHIFT) + +/* + * PRE_DIV (RW) + * + * frequency division + */ +#define CAM_ALARM_SET_PRE_DIV_MASK (0xFFFFU) +#define CAM_ALARM_SET_PRE_DIV_SHIFT (0U) +#define CAM_ALARM_SET_PRE_DIV_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_PRE_DIV_SHIFT) & CAM_ALARM_SET_PRE_DIV_MASK) +#define CAM_ALARM_SET_PRE_DIV_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_PRE_DIV_MASK) >> CAM_ALARM_SET_PRE_DIV_SHIFT) + /* HISTOGRAM_FIFO register group index macro definition */ @@ -1019,4 +1318,4 @@ typedef struct { #define CAM_HISTOGRAM_FIFO_DATA255 (255UL) -#endif /* HPM_CAM_H */ \ No newline at end of file +#endif /* HPM_CAM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h index 7395c8d908..d5afee8552 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -1399,4 +1399,4 @@ typedef struct { #define CAN_TTS_WRD1 (1UL) -#endif /* HPM_CAN_H */ \ No newline at end of file +#endif /* HPM_CAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h index d3ab74834e..9dcca793ef 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -57,6 +57,16 @@ typedef struct { #define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) /* Bitfield definition for register: CTRL2 */ +/* + * ENET0_LPI_IRQ_EN (RW) + * + * ENET0 LPI IRQ Enable + */ +#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL) +#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U) +#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) +#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) + /* * ENET0_REFCLK_OE (RW) * @@ -102,6 +112,16 @@ typedef struct { #define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) /* Bitfield definition for register: CTRL3 */ +/* + * ENET1_LPI_IRQ_EN (RW) + * + * ENET1 LPI Interrupt Enable + */ +#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK (0x20000000UL) +#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT (29U) +#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) +#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) >> CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) + /* * ENET1_REFCLK_OE (RW) * @@ -199,6 +219,25 @@ typedef struct { #define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) #define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) +/* + * SDXC0_GPR_CCLK_RX_DLY_SW_SEL (RW) + * + */ +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL) +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U) +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) + +/* + * SDXC0_GPR_CCLK_RX_DLY_SW_FORCE (RW) + * + * force use sw DLL config + */ +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U) +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U) +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) +#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) + /* Bitfield definition for register: CTRL5 */ /* * SDXC1_SYS_IRQ_EN (RW) @@ -257,7 +296,25 @@ typedef struct { #define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) #define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) +/* + * SDXC1_GPR_CCLK_RX_DLY_SW_SEL (RW) + * + */ +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL) +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U) +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) + +/* + * SDXC1_GPR_CCLK_RX_DLY_SW_FORCE (RW) + * + */ +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U) +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U) +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) +#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) -#endif /* HPM_CONCTL_H */ \ No newline at end of file + +#endif /* HPM_CONCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_crc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_crc_regs.h new file mode 100644 index 0000000000..0a24a3e824 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_crc_regs.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CRC_H +#define HPM_CRC_H + +typedef struct { + struct { + __RW uint32_t PRE_SET; /* 0x0: pre set for crc setting */ + __RW uint32_t CLR; /* 0x4: chn clear crc result and setting */ + __RW uint32_t POLY; /* 0x8: chn poly */ + __RW uint32_t INIT_DATA; /* 0xC: chn init_data */ + __RW uint32_t XOROUT; /* 0x10: chn xorout */ + __RW uint32_t MISC_SETTING; /* 0x14: chn misc_setting */ + __RW uint32_t DATA; /* 0x18: chn data */ + __RW uint32_t RESULT; /* 0x1C: chn result */ + __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ + } CHN[8]; +} CRC_Type; + + +/* Bitfield definition for register of struct array CHN: PRE_SET */ +/* + * PRE_SET (RW) + * + * 0: no pre set + * 1: CRC32 + * 2: CRC32-AUTOSAR + * 3: CRC16-CCITT + * 4: CRC16-XMODEM + * 5: CRC16-MODBUS + * 1: CRC32 + * 2: CRC32-autosar + * 3: CRC16-ccitt + * 4: CRC16-xmodem + * 5: CRC16-modbus + * 6: crc16_dnp + * 7: crc16_x25 + * 8: crc16_usb + * 9: crc16_maxim + * 10: crc16_ibm + * 11: crc8_maxim + * 12: crc8_rohc + * 13: crc8_itu + * 14: crc8 + * 15: crc5_usb + */ +#define CRC_CHN_PRE_SET_PRE_SET_MASK (0xFFU) +#define CRC_CHN_PRE_SET_PRE_SET_SHIFT (0U) +#define CRC_CHN_PRE_SET_PRE_SET_SET(x) (((uint32_t)(x) << CRC_CHN_PRE_SET_PRE_SET_SHIFT) & CRC_CHN_PRE_SET_PRE_SET_MASK) +#define CRC_CHN_PRE_SET_PRE_SET_GET(x) (((uint32_t)(x) & CRC_CHN_PRE_SET_PRE_SET_MASK) >> CRC_CHN_PRE_SET_PRE_SET_SHIFT) + +/* Bitfield definition for register of struct array CHN: CLR */ +/* + * CLR (RW) + * + * write 1 to clr crc setting and result for its channel. + * always read 0. + */ +#define CRC_CHN_CLR_CLR_MASK (0x1U) +#define CRC_CHN_CLR_CLR_SHIFT (0U) +#define CRC_CHN_CLR_CLR_SET(x) (((uint32_t)(x) << CRC_CHN_CLR_CLR_SHIFT) & CRC_CHN_CLR_CLR_MASK) +#define CRC_CHN_CLR_CLR_GET(x) (((uint32_t)(x) & CRC_CHN_CLR_CLR_MASK) >> CRC_CHN_CLR_CLR_SHIFT) + +/* Bitfield definition for register of struct array CHN: POLY */ +/* + * POLY (RW) + * + * poly setting + */ +#define CRC_CHN_POLY_POLY_MASK (0xFFFFFFFFUL) +#define CRC_CHN_POLY_POLY_SHIFT (0U) +#define CRC_CHN_POLY_POLY_SET(x) (((uint32_t)(x) << CRC_CHN_POLY_POLY_SHIFT) & CRC_CHN_POLY_POLY_MASK) +#define CRC_CHN_POLY_POLY_GET(x) (((uint32_t)(x) & CRC_CHN_POLY_POLY_MASK) >> CRC_CHN_POLY_POLY_SHIFT) + +/* Bitfield definition for register of struct array CHN: INIT_DATA */ +/* + * INIT_DATA (RW) + * + * initial data of CRC + */ +#define CRC_CHN_INIT_DATA_INIT_DATA_MASK (0xFFFFFFFFUL) +#define CRC_CHN_INIT_DATA_INIT_DATA_SHIFT (0U) +#define CRC_CHN_INIT_DATA_INIT_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) +#define CRC_CHN_INIT_DATA_INIT_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) >> CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) + +/* Bitfield definition for register of struct array CHN: XOROUT */ +/* + * XOROUT (RW) + * + * XOR for CRC result + */ +#define CRC_CHN_XOROUT_XOROUT_MASK (0xFFFFFFFFUL) +#define CRC_CHN_XOROUT_XOROUT_SHIFT (0U) +#define CRC_CHN_XOROUT_XOROUT_SET(x) (((uint32_t)(x) << CRC_CHN_XOROUT_XOROUT_SHIFT) & CRC_CHN_XOROUT_XOROUT_MASK) +#define CRC_CHN_XOROUT_XOROUT_GET(x) (((uint32_t)(x) & CRC_CHN_XOROUT_XOROUT_MASK) >> CRC_CHN_XOROUT_XOROUT_SHIFT) + +/* Bitfield definition for register of struct array CHN: MISC_SETTING */ +/* + * BYTE_REV (RW) + * + * 0: no wrap input byte order + * 1: wrap input byte order + */ +#define CRC_CHN_MISC_SETTING_BYTE_REV_MASK (0x1000000UL) +#define CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT (24U) +#define CRC_CHN_MISC_SETTING_BYTE_REV_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) +#define CRC_CHN_MISC_SETTING_BYTE_REV_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) >> CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) + +/* + * REV_OUT (RW) + * + * 0: no wrap output bit order + * 1: wrap output bit order + */ +#define CRC_CHN_MISC_SETTING_REV_OUT_MASK (0x10000UL) +#define CRC_CHN_MISC_SETTING_REV_OUT_SHIFT (16U) +#define CRC_CHN_MISC_SETTING_REV_OUT_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) +#define CRC_CHN_MISC_SETTING_REV_OUT_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) >> CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) + +/* + * REV_IN (RW) + * + * 0: no wrap input bit order + * 1: wrap input bit order + */ +#define CRC_CHN_MISC_SETTING_REV_IN_MASK (0x100U) +#define CRC_CHN_MISC_SETTING_REV_IN_SHIFT (8U) +#define CRC_CHN_MISC_SETTING_REV_IN_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_IN_SHIFT) & CRC_CHN_MISC_SETTING_REV_IN_MASK) +#define CRC_CHN_MISC_SETTING_REV_IN_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_IN_MASK) >> CRC_CHN_MISC_SETTING_REV_IN_SHIFT) + +/* + * POLY_WIDTH (RW) + * + * crc data length + */ +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK (0x3FU) +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT (0U) +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) >> CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) + +/* Bitfield definition for register of struct array CHN: DATA */ +/* + * DATA (RW) + * + * data for crc + */ +#define CRC_CHN_DATA_DATA_MASK (0xFFFFFFFFUL) +#define CRC_CHN_DATA_DATA_SHIFT (0U) +#define CRC_CHN_DATA_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_DATA_DATA_SHIFT) & CRC_CHN_DATA_DATA_MASK) +#define CRC_CHN_DATA_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_DATA_DATA_MASK) >> CRC_CHN_DATA_DATA_SHIFT) + +/* Bitfield definition for register of struct array CHN: RESULT */ +/* + * RESULT (RW) + * + * crc result + */ +#define CRC_CHN_RESULT_RESULT_MASK (0xFFFFFFFFUL) +#define CRC_CHN_RESULT_RESULT_SHIFT (0U) +#define CRC_CHN_RESULT_RESULT_SET(x) (((uint32_t)(x) << CRC_CHN_RESULT_RESULT_SHIFT) & CRC_CHN_RESULT_RESULT_MASK) +#define CRC_CHN_RESULT_RESULT_GET(x) (((uint32_t)(x) & CRC_CHN_RESULT_RESULT_MASK) >> CRC_CHN_RESULT_RESULT_SHIFT) + + + +/* CHN register group index macro definition */ +#define CRC_CHN_0 (0UL) +#define CRC_CHN_1 (1UL) +#define CRC_CHN_2 (2UL) +#define CRC_CHN_3 (3UL) +#define CRC_CHN_4 (4UL) +#define CRC_CHN_5 (5UL) +#define CRC_CHN_6 (6UL) +#define CRC_CHN_7 (7UL) + + +#endif /* HPM_CRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h index ffab52c9fa..70c2d44144 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -23,7 +23,7 @@ typedef struct { __RW uint32_t DMA_EN; /* 0x38: */ __R uint8_t RESERVED2[4]; /* 0x3C - 0x3F: Reserved */ __RW uint32_t ANA_CFG0; /* 0x40: */ - __R uint8_t RESERVED3[4]; /* 0x44 - 0x47: Reserved */ + __RW uint32_t CFG0_BAK; /* 0x44: */ __RW uint32_t STATUS0; /* 0x48: */ } DAC_Type; @@ -336,6 +336,15 @@ typedef struct { #define DAC_BUF_LENGTH_BUF0_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF0_LEN_MASK) >> DAC_BUF_LENGTH_BUF0_LEN_SHIFT) /* Bitfield definition for register: IRQ_STS */ +/* + * STEP_CMPT (W1C) + * + */ +#define DAC_IRQ_STS_STEP_CMPT_MASK (0x10U) +#define DAC_IRQ_STS_STEP_CMPT_SHIFT (4U) +#define DAC_IRQ_STS_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_STEP_CMPT_SHIFT) & DAC_IRQ_STS_STEP_CMPT_MASK) +#define DAC_IRQ_STS_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_STEP_CMPT_MASK) >> DAC_IRQ_STS_STEP_CMPT_SHIFT) + /* * AHB_ERROR (W1C) * @@ -374,6 +383,15 @@ typedef struct { #define DAC_IRQ_STS_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF0_CMPT_MASK) >> DAC_IRQ_STS_BUF0_CMPT_SHIFT) /* Bitfield definition for register: IRQ_EN */ +/* + * STEP_CMPT (RW) + * + */ +#define DAC_IRQ_EN_STEP_CMPT_MASK (0x10U) +#define DAC_IRQ_EN_STEP_CMPT_SHIFT (4U) +#define DAC_IRQ_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_STEP_CMPT_SHIFT) & DAC_IRQ_EN_STEP_CMPT_MASK) +#define DAC_IRQ_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_STEP_CMPT_MASK) >> DAC_IRQ_EN_STEP_CMPT_SHIFT) + /* * AHB_ERROR (RW) * @@ -411,6 +429,15 @@ typedef struct { #define DAC_IRQ_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF0_CMPT_MASK) >> DAC_IRQ_EN_BUF0_CMPT_SHIFT) /* Bitfield definition for register: DMA_EN */ +/* + * STEP_CMPT (RW) + * + */ +#define DAC_DMA_EN_STEP_CMPT_MASK (0x10U) +#define DAC_DMA_EN_STEP_CMPT_SHIFT (4U) +#define DAC_DMA_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_STEP_CMPT_SHIFT) & DAC_DMA_EN_STEP_CMPT_MASK) +#define DAC_DMA_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_STEP_CMPT_MASK) >> DAC_DMA_EN_STEP_CMPT_SHIFT) + /* * BUF1_CMPT (RW) * @@ -475,6 +502,98 @@ typedef struct { #define DAC_ANA_CFG0_DAC12BIT_EN_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) #define DAC_ANA_CFG0_DAC12BIT_EN_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) >> DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) +/* Bitfield definition for register: CFG0_BAK */ +/* + * SW_DAC_DATA (RW) + * + * dac data used in direct mode(dac_mode==2'b10) + */ +#define DAC_CFG0_BAK_SW_DAC_DATA_MASK (0xFFF0000UL) +#define DAC_CFG0_BAK_SW_DAC_DATA_SHIFT (16U) +#define DAC_CFG0_BAK_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) +#define DAC_CFG0_BAK_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) >> DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) + +/* + * DMA_AHB_EN (RW) + * + * set to enable internal DMA, it will read one burst if enough space in FIFO. + * Should only be used in buffer mode. + */ +#define DAC_CFG0_BAK_DMA_AHB_EN_MASK (0x200U) +#define DAC_CFG0_BAK_DMA_AHB_EN_SHIFT (9U) +#define DAC_CFG0_BAK_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) +#define DAC_CFG0_BAK_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) >> DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) + +/* + * SYNC_MODE (RW) + * + * 1: sync dac clock and ahb clock. + * all HW trigger signals are pulse in sync mode, can get faster response; + * 0: async dac clock and ahb_clock + * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + */ +#define DAC_CFG0_BAK_SYNC_MODE_MASK (0x100U) +#define DAC_CFG0_BAK_SYNC_MODE_SHIFT (8U) +#define DAC_CFG0_BAK_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SYNC_MODE_SHIFT) & DAC_CFG0_BAK_SYNC_MODE_MASK) +#define DAC_CFG0_BAK_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SYNC_MODE_MASK) >> DAC_CFG0_BAK_SYNC_MODE_SHIFT) + +/* + * TRIG_MODE (RW) + * + * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; + * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + */ +#define DAC_CFG0_BAK_TRIG_MODE_MASK (0x80U) +#define DAC_CFG0_BAK_TRIG_MODE_SHIFT (7U) +#define DAC_CFG0_BAK_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_TRIG_MODE_SHIFT) & DAC_CFG0_BAK_TRIG_MODE_MASK) +#define DAC_CFG0_BAK_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_TRIG_MODE_MASK) >> DAC_CFG0_BAK_TRIG_MODE_SHIFT) + +/* + * HW_TRIG_EN (RW) + * + * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + */ +#define DAC_CFG0_BAK_HW_TRIG_EN_MASK (0x40U) +#define DAC_CFG0_BAK_HW_TRIG_EN_SHIFT (6U) +#define DAC_CFG0_BAK_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) +#define DAC_CFG0_BAK_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) >> DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) + +/* + * DAC_MODE (RW) + * + * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) + * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down + * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + */ +#define DAC_CFG0_BAK_DAC_MODE_MASK (0x30U) +#define DAC_CFG0_BAK_DAC_MODE_SHIFT (4U) +#define DAC_CFG0_BAK_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DAC_MODE_SHIFT) & DAC_CFG0_BAK_DAC_MODE_MASK) +#define DAC_CFG0_BAK_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DAC_MODE_MASK) >> DAC_CFG0_BAK_DAC_MODE_SHIFT) + +/* + * BUF_DATA_MODE (RW) + * + * data structure for buffer mode, + * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. + * 1: each 32-bit data contains 1 point, b11:0 for first + */ +#define DAC_CFG0_BAK_BUF_DATA_MODE_MASK (0x8U) +#define DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT (3U) +#define DAC_CFG0_BAK_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) +#define DAC_CFG0_BAK_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) >> DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) + +/* + * HBURST_CFG (RW) + * + * DAC support following fixed burst only + * 000-SINGLE; 011-INCR4; 101: INCR8 + * others are reserved + */ +#define DAC_CFG0_BAK_HBURST_CFG_MASK (0x7U) +#define DAC_CFG0_BAK_HBURST_CFG_SHIFT (0U) +#define DAC_CFG0_BAK_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HBURST_CFG_SHIFT) & DAC_CFG0_BAK_HBURST_CFG_MASK) +#define DAC_CFG0_BAK_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HBURST_CFG_MASK) >> DAC_CFG0_BAK_HBURST_CFG_SHIFT) + /* Bitfield definition for register: STATUS0 */ /* * CUR_BUF_OFFSET (RW) @@ -507,4 +626,4 @@ typedef struct { #define DAC_BUF_ADDR_BUF1 (1UL) -#endif /* HPM_DAC_H */ \ No newline at end of file +#endif /* HPM_DAC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h index 321b839983..1162cb3a59 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -31,19 +31,6 @@ typedef struct { #define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) #define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) -/* - * SAT_ERR_IE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (saturation) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define DAO_CTRL_SAT_ERR_IE_MASK (0x10000UL) -#define DAO_CTRL_SAT_ERR_IE_SHIFT (16U) -#define DAO_CTRL_SAT_ERR_IE_SET(x) (((uint32_t)(x) << DAO_CTRL_SAT_ERR_IE_SHIFT) & DAO_CTRL_SAT_ERR_IE_MASK) -#define DAO_CTRL_SAT_ERR_IE_GET(x) (((uint32_t)(x) & DAO_CTRL_SAT_ERR_IE_MASK) >> DAO_CTRL_SAT_ERR_IE_SHIFT) - /* * MONO (RW) * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h index 9ddbd9c766..c8ffe93e04 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,15 +10,17 @@ #define HPM_DMA_H typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __R uint32_t IDMISC; /* 0x4: ID Misc */ + __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ + __R uint8_t RESERVED2[12]; /* 0x14 - 0x1F: Reserved */ __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ - __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ + __R uint8_t RESERVED3[8]; /* 0x28 - 0x2F: Reserved */ __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ + __R uint8_t RESERVED4[8]; /* 0x38 - 0x3F: Reserved */ struct { __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ @@ -32,6 +34,18 @@ typedef struct { } DMA_Type; +/* Bitfield definition for register: IDMISC */ +/* + * IDLE_FLAG (RO) + * + * DMA Idle Flag + * 0 - DMA is busy + * 1 - DMA is dile + */ +#define DMA_IDMISC_IDLE_FLAG_MASK (0x8000U) +#define DMA_IDMISC_IDLE_FLAG_SHIFT (15U) +#define DMA_IDMISC_IDLE_FLAG_GET(x) (((uint32_t)(x) & DMA_IDMISC_IDLE_FLAG_MASK) >> DMA_IDMISC_IDLE_FLAG_SHIFT) + /* Bitfield definition for register: DMACFG */ /* * CHAINXFR (RO) @@ -273,7 +287,8 @@ typedef struct { * 0x8: 256 transfers * 0x9:512 transfers * 0xa: 1024 transfers - * 0xb -0xf: Reserved, setting this field with a reserved value triggers the error exception + * 0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception + * for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 */ #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) @@ -291,6 +306,7 @@ typedef struct { * 0x4: Quad word transfer * 0x5: Eight word transfer * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception + * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 */ #define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) #define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) @@ -310,6 +326,7 @@ typedef struct { * 0x4: Quad word transfer * 0x5: Eight word transfer * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception + * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 */ #define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) #define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) @@ -544,4 +561,4 @@ typedef struct { #define DMA_CHCTRL_CH7 (7UL) -#endif /* HPM_DMA_H */ \ No newline at end of file +#endif /* HPM_DMA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h deleted file mode 100644 index 1adf537812..0000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h +++ /dev/null @@ -1,834 +0,0 @@ -/* - * Copyright (c) 2021-2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DRAM_H -#define HPM_DRAM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ - __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ - __RW uint32_t BR[2]; /* 0x10 - 0x14: Base Register 0 (for SDRAM CS0 device) */ - __R uint8_t RESERVED1[32]; /* 0x18 - 0x37: Reserved */ - __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ - __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ - __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ - __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ - __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ - __R uint8_t RESERVED2[64]; /* 0x50 - 0x8F: Reserved */ - __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ - __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ - __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ - __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ - __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ - __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ - __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ - __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ - __R uint32_t STAT0; /* 0xC0: Status Register 0 */ - __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ - __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ -} DRAM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * BTO (RW) - * - * Bus timeout cycles - * AXI Bus timeout cycle is as following (255*(2^BTO)): - * 00000b - 255*1 - * 00001-11110b - 255*2 - 255*2^30 - * 11111b - 255*2^31 - */ -#define DRAM_CTRL_BTO_MASK (0x1F000000UL) -#define DRAM_CTRL_BTO_SHIFT (24U) -#define DRAM_CTRL_BTO_SET(x) (((uint32_t)(x) << DRAM_CTRL_BTO_SHIFT) & DRAM_CTRL_BTO_MASK) -#define DRAM_CTRL_BTO_GET(x) (((uint32_t)(x) & DRAM_CTRL_BTO_MASK) >> DRAM_CTRL_BTO_SHIFT) - -/* - * CTO (RW) - * - * Command Execution timeout cycles - * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is - * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is - * CTO*1024 cycle. - */ -#define DRAM_CTRL_CTO_MASK (0xFF0000UL) -#define DRAM_CTRL_CTO_SHIFT (16U) -#define DRAM_CTRL_CTO_SET(x) (((uint32_t)(x) << DRAM_CTRL_CTO_SHIFT) & DRAM_CTRL_CTO_MASK) -#define DRAM_CTRL_CTO_GET(x) (((uint32_t)(x) & DRAM_CTRL_CTO_MASK) >> DRAM_CTRL_CTO_SHIFT) - -/* - * DQS (RW) - * - * DQS (read strobe) mode - * 0b - Dummy read strobe loopbacked internally - * 1b - Dummy read strobe loopbacked from DQS pad - */ -#define DRAM_CTRL_DQS_MASK (0x4U) -#define DRAM_CTRL_DQS_SHIFT (2U) -#define DRAM_CTRL_DQS_SET(x) (((uint32_t)(x) << DRAM_CTRL_DQS_SHIFT) & DRAM_CTRL_DQS_MASK) -#define DRAM_CTRL_DQS_GET(x) (((uint32_t)(x) & DRAM_CTRL_DQS_MASK) >> DRAM_CTRL_DQS_SHIFT) - -/* - * DIS (RW) - * - * Module Disable - * 0b - Module enabled - * 1b - Module disabled - */ -#define DRAM_CTRL_DIS_MASK (0x2U) -#define DRAM_CTRL_DIS_SHIFT (1U) -#define DRAM_CTRL_DIS_SET(x) (((uint32_t)(x) << DRAM_CTRL_DIS_SHIFT) & DRAM_CTRL_DIS_MASK) -#define DRAM_CTRL_DIS_GET(x) (((uint32_t)(x) & DRAM_CTRL_DIS_MASK) >> DRAM_CTRL_DIS_SHIFT) - -/* - * RST (RW) - * - * Software Reset - * Reset all internal logic in SEMC except configuration register - */ -#define DRAM_CTRL_RST_MASK (0x1U) -#define DRAM_CTRL_RST_SHIFT (0U) -#define DRAM_CTRL_RST_SET(x) (((uint32_t)(x) << DRAM_CTRL_RST_SHIFT) & DRAM_CTRL_RST_MASK) -#define DRAM_CTRL_RST_GET(x) (((uint32_t)(x) & DRAM_CTRL_RST_MASK) >> DRAM_CTRL_RST_SHIFT) - -/* Bitfield definition for register: BMW0 */ -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define DRAM_BMW0_RWS_MASK (0xFF0000UL) -#define DRAM_BMW0_RWS_SHIFT (16U) -#define DRAM_BMW0_RWS_SET(x) (((uint32_t)(x) << DRAM_BMW0_RWS_SHIFT) & DRAM_BMW0_RWS_MASK) -#define DRAM_BMW0_RWS_GET(x) (((uint32_t)(x) & DRAM_BMW0_RWS_MASK) >> DRAM_BMW0_RWS_SHIFT) - -/* - * SH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define DRAM_BMW0_SH_MASK (0xFF00U) -#define DRAM_BMW0_SH_SHIFT (8U) -#define DRAM_BMW0_SH_SET(x) (((uint32_t)(x) << DRAM_BMW0_SH_SHIFT) & DRAM_BMW0_SH_MASK) -#define DRAM_BMW0_SH_GET(x) (((uint32_t)(x) & DRAM_BMW0_SH_MASK) >> DRAM_BMW0_SH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define DRAM_BMW0_AGE_MASK (0xF0U) -#define DRAM_BMW0_AGE_SHIFT (4U) -#define DRAM_BMW0_AGE_SET(x) (((uint32_t)(x) << DRAM_BMW0_AGE_SHIFT) & DRAM_BMW0_AGE_MASK) -#define DRAM_BMW0_AGE_GET(x) (((uint32_t)(x) & DRAM_BMW0_AGE_MASK) >> DRAM_BMW0_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define DRAM_BMW0_QOS_MASK (0xFU) -#define DRAM_BMW0_QOS_SHIFT (0U) -#define DRAM_BMW0_QOS_SET(x) (((uint32_t)(x) << DRAM_BMW0_QOS_SHIFT) & DRAM_BMW0_QOS_MASK) -#define DRAM_BMW0_QOS_GET(x) (((uint32_t)(x) & DRAM_BMW0_QOS_MASK) >> DRAM_BMW0_QOS_SHIFT) - -/* Bitfield definition for register: BMW1 */ -/* - * BR (RW) - * - * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current - * executing command. - */ -#define DRAM_BMW1_BR_MASK (0xFF000000UL) -#define DRAM_BMW1_BR_SHIFT (24U) -#define DRAM_BMW1_BR_SET(x) (((uint32_t)(x) << DRAM_BMW1_BR_SHIFT) & DRAM_BMW1_BR_MASK) -#define DRAM_BMW1_BR_GET(x) (((uint32_t)(x) & DRAM_BMW1_BR_MASK) >> DRAM_BMW1_BR_SHIFT) - -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define DRAM_BMW1_RWS_MASK (0xFF0000UL) -#define DRAM_BMW1_RWS_SHIFT (16U) -#define DRAM_BMW1_RWS_SET(x) (((uint32_t)(x) << DRAM_BMW1_RWS_SHIFT) & DRAM_BMW1_RWS_MASK) -#define DRAM_BMW1_RWS_GET(x) (((uint32_t)(x) & DRAM_BMW1_RWS_MASK) >> DRAM_BMW1_RWS_SHIFT) - -/* - * PH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define DRAM_BMW1_PH_MASK (0xFF00U) -#define DRAM_BMW1_PH_SHIFT (8U) -#define DRAM_BMW1_PH_SET(x) (((uint32_t)(x) << DRAM_BMW1_PH_SHIFT) & DRAM_BMW1_PH_MASK) -#define DRAM_BMW1_PH_GET(x) (((uint32_t)(x) & DRAM_BMW1_PH_MASK) >> DRAM_BMW1_PH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define DRAM_BMW1_AGE_MASK (0xF0U) -#define DRAM_BMW1_AGE_SHIFT (4U) -#define DRAM_BMW1_AGE_SET(x) (((uint32_t)(x) << DRAM_BMW1_AGE_SHIFT) & DRAM_BMW1_AGE_MASK) -#define DRAM_BMW1_AGE_GET(x) (((uint32_t)(x) & DRAM_BMW1_AGE_MASK) >> DRAM_BMW1_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define DRAM_BMW1_QOS_MASK (0xFU) -#define DRAM_BMW1_QOS_SHIFT (0U) -#define DRAM_BMW1_QOS_SET(x) (((uint32_t)(x) << DRAM_BMW1_QOS_SHIFT) & DRAM_BMW1_QOS_MASK) -#define DRAM_BMW1_QOS_GET(x) (((uint32_t)(x) & DRAM_BMW1_QOS_MASK) >> DRAM_BMW1_QOS_SHIFT) - -/* Bitfield definition for register array: BR */ -/* - * BASE (RW) - * - * Base Address - * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low - * position 12 bits are all zero. - */ -#define DRAM_BR_BASE_MASK (0xFFFFF000UL) -#define DRAM_BR_BASE_SHIFT (12U) -#define DRAM_BR_BASE_SET(x) (((uint32_t)(x) << DRAM_BR_BASE_SHIFT) & DRAM_BR_BASE_MASK) -#define DRAM_BR_BASE_GET(x) (((uint32_t)(x) & DRAM_BR_BASE_MASK) >> DRAM_BR_BASE_SHIFT) - -/* - * SIZE (RW) - * - * Memory size - * 00000b - 4KB - * 00001b - 8KB - * 00010b - 16KB - * 00011b - 32KB - * 00100b - 64KB - * 00101b - 128KB - * 00110b - 256KB - * 00111b - 512KB - * 01000b - 1MB - * 01001b - 2MB - * 01010b - 4MB - * 01011b - 8MB - * 01100b - 16MB - * 01101b - 32MB - * 01110b - 64MB - * 01111b - 128MB - * 10000b - 256MB - * 10001b - 512MB - * 10010b - 1GB - * 10011b - 2GB - * 10100-11111b - 4GB - */ -#define DRAM_BR_SIZE_MASK (0x3EU) -#define DRAM_BR_SIZE_SHIFT (1U) -#define DRAM_BR_SIZE_SET(x) (((uint32_t)(x) << DRAM_BR_SIZE_SHIFT) & DRAM_BR_SIZE_MASK) -#define DRAM_BR_SIZE_GET(x) (((uint32_t)(x) & DRAM_BR_SIZE_MASK) >> DRAM_BR_SIZE_SHIFT) - -/* - * VLD (RW) - * - * Valid - */ -#define DRAM_BR_VLD_MASK (0x1U) -#define DRAM_BR_VLD_SHIFT (0U) -#define DRAM_BR_VLD_SET(x) (((uint32_t)(x) << DRAM_BR_VLD_SHIFT) & DRAM_BR_VLD_MASK) -#define DRAM_BR_VLD_GET(x) (((uint32_t)(x) & DRAM_BR_VLD_MASK) >> DRAM_BR_VLD_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * AXIBUSERR (RW) - * - * AXI BUS error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_AXIBUSERR_MASK (0x8U) -#define DRAM_INTEN_AXIBUSERR_SHIFT (3U) -#define DRAM_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_AXIBUSERR_SHIFT) & DRAM_INTEN_AXIBUSERR_MASK) -#define DRAM_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_AXIBUSERR_MASK) >> DRAM_INTEN_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (RW) - * - * AXI command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_AXICMDERR_MASK (0x4U) -#define DRAM_INTEN_AXICMDERR_SHIFT (2U) -#define DRAM_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_AXICMDERR_SHIFT) & DRAM_INTEN_AXICMDERR_MASK) -#define DRAM_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_AXICMDERR_MASK) >> DRAM_INTEN_AXICMDERR_SHIFT) - -/* - * IPCMDERR (RW) - * - * IP command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_IPCMDERR_MASK (0x2U) -#define DRAM_INTEN_IPCMDERR_SHIFT (1U) -#define DRAM_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_IPCMDERR_SHIFT) & DRAM_INTEN_IPCMDERR_MASK) -#define DRAM_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_IPCMDERR_MASK) >> DRAM_INTEN_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (RW) - * - * IP command done interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_IPCMDDONE_MASK (0x1U) -#define DRAM_INTEN_IPCMDDONE_SHIFT (0U) -#define DRAM_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << DRAM_INTEN_IPCMDDONE_SHIFT) & DRAM_INTEN_IPCMDDONE_MASK) -#define DRAM_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & DRAM_INTEN_IPCMDDONE_MASK) >> DRAM_INTEN_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: INTR */ -/* - * AXIBUSERR (W1C) - * - * AXI bus error interrupt - * AXI Bus error interrupt is generated in following cases: - * • AXI address is invalid - * • AXI 8-bit or 16-bit WRAP write/read - */ -#define DRAM_INTR_AXIBUSERR_MASK (0x8U) -#define DRAM_INTR_AXIBUSERR_SHIFT (3U) -#define DRAM_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << DRAM_INTR_AXIBUSERR_SHIFT) & DRAM_INTR_AXIBUSERR_MASK) -#define DRAM_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & DRAM_INTR_AXIBUSERR_MASK) >> DRAM_INTR_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (W1C) - * - * AXI command error interrupt - * AXI command error interrupt is generated when AXI command execution timeout. - */ -#define DRAM_INTR_AXICMDERR_MASK (0x4U) -#define DRAM_INTR_AXICMDERR_SHIFT (2U) -#define DRAM_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << DRAM_INTR_AXICMDERR_SHIFT) & DRAM_INTR_AXICMDERR_MASK) -#define DRAM_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & DRAM_INTR_AXICMDERR_MASK) >> DRAM_INTR_AXICMDERR_SHIFT) - -/* - * IPCMDERR (W1C) - * - * IP command error done interrupt - * IP command error interrupt is generated in following case: - * • IP Command Address target invalid device space - * • IP Command Code unsupported - * • IP Command triggered when previous command - */ -#define DRAM_INTR_IPCMDERR_MASK (0x2U) -#define DRAM_INTR_IPCMDERR_SHIFT (1U) -#define DRAM_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << DRAM_INTR_IPCMDERR_SHIFT) & DRAM_INTR_IPCMDERR_MASK) -#define DRAM_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & DRAM_INTR_IPCMDERR_MASK) >> DRAM_INTR_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (W1C) - * - * IP command normal done interrupt - */ -#define DRAM_INTR_IPCMDDONE_MASK (0x1U) -#define DRAM_INTR_IPCMDDONE_SHIFT (0U) -#define DRAM_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << DRAM_INTR_IPCMDDONE_SHIFT) & DRAM_INTR_IPCMDDONE_MASK) -#define DRAM_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & DRAM_INTR_IPCMDDONE_MASK) >> DRAM_INTR_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: SDRCTRL0 */ -/* - * BANK2 (RW) - * - * 2 Bank selection bit - * 0b - SDRAM device has 4 banks. - * 1b - SDRAM device has 2 banks. - */ -#define DRAM_SDRCTRL0_BANK2_MASK (0x4000U) -#define DRAM_SDRCTRL0_BANK2_SHIFT (14U) -#define DRAM_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_BANK2_SHIFT) & DRAM_SDRCTRL0_BANK2_MASK) -#define DRAM_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_BANK2_MASK) >> DRAM_SDRCTRL0_BANK2_SHIFT) - -/* - * CAS (RW) - * - * CAS Latency - * 00b - 1 - * 01b - 1 - * 10b - 2 - * 11b - 3 - */ -#define DRAM_SDRCTRL0_CAS_MASK (0xC00U) -#define DRAM_SDRCTRL0_CAS_SHIFT (10U) -#define DRAM_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_CAS_SHIFT) & DRAM_SDRCTRL0_CAS_MASK) -#define DRAM_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_CAS_MASK) >> DRAM_SDRCTRL0_CAS_SHIFT) - -/* - * COL (RW) - * - * Column address bit number - * 00b - 12 bit - * 01b - 11 bit - * 10b - 10 bit - * 11b - 9 bit - */ -#define DRAM_SDRCTRL0_COL_MASK (0x300U) -#define DRAM_SDRCTRL0_COL_SHIFT (8U) -#define DRAM_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_COL_SHIFT) & DRAM_SDRCTRL0_COL_MASK) -#define DRAM_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_COL_MASK) >> DRAM_SDRCTRL0_COL_SHIFT) - -/* - * COL8 (RW) - * - * Column 8 selection bit - * 0b - Column address bit number is decided by COL field. - * 1b - Column address bit number is 8. COL field is ignored. - */ -#define DRAM_SDRCTRL0_COL8_MASK (0x80U) -#define DRAM_SDRCTRL0_COL8_SHIFT (7U) -#define DRAM_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_COL8_SHIFT) & DRAM_SDRCTRL0_COL8_MASK) -#define DRAM_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_COL8_MASK) >> DRAM_SDRCTRL0_COL8_SHIFT) - -/* - * BURSTLEN (RW) - * - * Burst Length - * 000b - 1 - * 001b - 2 - * 010b - 4 - * 011b - 8 - * 100b - 8 - * 101b - 8 - * 110b - 8 - * 111b - 8 - */ -#define DRAM_SDRCTRL0_BURSTLEN_MASK (0x70U) -#define DRAM_SDRCTRL0_BURSTLEN_SHIFT (4U) -#define DRAM_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_BURSTLEN_SHIFT) & DRAM_SDRCTRL0_BURSTLEN_MASK) -#define DRAM_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_BURSTLEN_MASK) >> DRAM_SDRCTRL0_BURSTLEN_SHIFT) - -/* - * HIGHBAND (RW) - * - * high band select - * 0: use data[15:0] for 16bit SDRAM; - * 1: use data[31:16] for 16bit SDRAM; - * only used when Port Size is 16bit(PORTSZ=01b) - */ -#define DRAM_SDRCTRL0_HIGHBAND_MASK (0x8U) -#define DRAM_SDRCTRL0_HIGHBAND_SHIFT (3U) -#define DRAM_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_HIGHBAND_SHIFT) & DRAM_SDRCTRL0_HIGHBAND_MASK) -#define DRAM_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_HIGHBAND_MASK) >> DRAM_SDRCTRL0_HIGHBAND_SHIFT) - -/* - * PORTSZ (RW) - * - * Port Size - * 00b - 8bit - * 01b - 16bit - * 10b - 32bit - */ -#define DRAM_SDRCTRL0_PORTSZ_MASK (0x3U) -#define DRAM_SDRCTRL0_PORTSZ_SHIFT (0U) -#define DRAM_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_PORTSZ_SHIFT) & DRAM_SDRCTRL0_PORTSZ_MASK) -#define DRAM_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_PORTSZ_MASK) >> DRAM_SDRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SDRCTRL1 */ -/* - * ACT2PRE (RW) - * - * ACT to Precharge minimum time - * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - */ -#define DRAM_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) -#define DRAM_SDRCTRL1_ACT2PRE_SHIFT (20U) -#define DRAM_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_ACT2PRE_SHIFT) & DRAM_SDRCTRL1_ACT2PRE_MASK) -#define DRAM_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_ACT2PRE_MASK) >> DRAM_SDRCTRL1_ACT2PRE_SHIFT) - -/* - * CKEOFF (RW) - * - * CKE OFF minimum time - * It is promised clock suspend last at leat CKEOFF+1 clock cycles. - */ -#define DRAM_SDRCTRL1_CKEOFF_MASK (0xF0000UL) -#define DRAM_SDRCTRL1_CKEOFF_SHIFT (16U) -#define DRAM_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_CKEOFF_SHIFT) & DRAM_SDRCTRL1_CKEOFF_MASK) -#define DRAM_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_CKEOFF_MASK) >> DRAM_SDRCTRL1_CKEOFF_SHIFT) - -/* - * WRC (RW) - * - * Write recovery time - * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_WRC_MASK (0xE000U) -#define DRAM_SDRCTRL1_WRC_SHIFT (13U) -#define DRAM_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_WRC_SHIFT) & DRAM_SDRCTRL1_WRC_MASK) -#define DRAM_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_WRC_MASK) >> DRAM_SDRCTRL1_WRC_SHIFT) - -/* - * RFRC (RW) - * - * Refresh recovery time - * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_RFRC_MASK (0x1F00U) -#define DRAM_SDRCTRL1_RFRC_SHIFT (8U) -#define DRAM_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_RFRC_SHIFT) & DRAM_SDRCTRL1_RFRC_MASK) -#define DRAM_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_RFRC_MASK) >> DRAM_SDRCTRL1_RFRC_SHIFT) - -/* - * ACT2RW (RW) - * - * ACT to Read/Write wait time - * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_ACT2RW_MASK (0xF0U) -#define DRAM_SDRCTRL1_ACT2RW_SHIFT (4U) -#define DRAM_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_ACT2RW_SHIFT) & DRAM_SDRCTRL1_ACT2RW_MASK) -#define DRAM_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_ACT2RW_MASK) >> DRAM_SDRCTRL1_ACT2RW_SHIFT) - -/* - * PRE2ACT (RW) - * - * PRECHARGE to ACT/Refresh wait time - * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_PRE2ACT_MASK (0xFU) -#define DRAM_SDRCTRL1_PRE2ACT_SHIFT (0U) -#define DRAM_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_PRE2ACT_SHIFT) & DRAM_SDRCTRL1_PRE2ACT_MASK) -#define DRAM_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_PRE2ACT_MASK) >> DRAM_SDRCTRL1_PRE2ACT_SHIFT) - -/* Bitfield definition for register: SDRCTRL2 */ -/* - * ITO (RW) - * - * SDRAM Idle timeout - * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is - * considered idle when there is no AXI Bus transfer and no SDRAM command pending. - * 00000000b - IDLE timeout period is 256*Prescale period. - * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. - */ -#define DRAM_SDRCTRL2_ITO_MASK (0xFF000000UL) -#define DRAM_SDRCTRL2_ITO_SHIFT (24U) -#define DRAM_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_ITO_SHIFT) & DRAM_SDRCTRL2_ITO_MASK) -#define DRAM_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_ITO_MASK) >> DRAM_SDRCTRL2_ITO_SHIFT) - -/* - * ACT2ACT (RW) - * - * ACT to ACT wait time - * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This - * could help to meet tRRD timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) -#define DRAM_SDRCTRL2_ACT2ACT_SHIFT (16U) -#define DRAM_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_ACT2ACT_SHIFT) & DRAM_SDRCTRL2_ACT2ACT_MASK) -#define DRAM_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_ACT2ACT_MASK) >> DRAM_SDRCTRL2_ACT2ACT_SHIFT) - -/* - * REF2REF (RW) - * - * Refresh to Refresh wait time - * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. - * This could help to meet tRFC timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL2_REF2REF_MASK (0xFF00U) -#define DRAM_SDRCTRL2_REF2REF_SHIFT (8U) -#define DRAM_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_REF2REF_SHIFT) & DRAM_SDRCTRL2_REF2REF_MASK) -#define DRAM_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_REF2REF_MASK) >> DRAM_SDRCTRL2_REF2REF_SHIFT) - -/* - * SRRC (RW) - * - * Self Refresh Recovery time - * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - */ -#define DRAM_SDRCTRL2_SRRC_MASK (0xFFU) -#define DRAM_SDRCTRL2_SRRC_SHIFT (0U) -#define DRAM_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_SRRC_SHIFT) & DRAM_SDRCTRL2_SRRC_MASK) -#define DRAM_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_SRRC_MASK) >> DRAM_SDRCTRL2_SRRC_SHIFT) - -/* Bitfield definition for register: SDRCTRL3 */ -/* - * UT (RW) - * - * Refresh urgent threshold - * Internal refresh request is generated on every Refresh period. Before internal request timer count up to - * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh - * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. - * When internal request timer count up to this urgent threshold, refresh request is considered as urgent - * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP - * command to SDRAM device. - * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as - * urgent refresh request. - * Refresh urgent threshold is as follwoing: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - UT*Prescaler period - */ -#define DRAM_SDRCTRL3_UT_MASK (0xFF000000UL) -#define DRAM_SDRCTRL3_UT_SHIFT (24U) -#define DRAM_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_UT_SHIFT) & DRAM_SDRCTRL3_UT_MASK) -#define DRAM_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_UT_MASK) >> DRAM_SDRCTRL3_UT_SHIFT) - -/* - * RT (RW) - * - * Refresh timer period - * Refresh timer period is as following: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - RT*Prescaler period - */ -#define DRAM_SDRCTRL3_RT_MASK (0xFF0000UL) -#define DRAM_SDRCTRL3_RT_SHIFT (16U) -#define DRAM_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_RT_SHIFT) & DRAM_SDRCTRL3_RT_MASK) -#define DRAM_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_RT_MASK) >> DRAM_SDRCTRL3_RT_SHIFT) - -/* - * PRESCALE (RW) - * - * Prescaler timer period - * Prescaler timer period is as following: - * 00000000b - 256*16 clock cycles - * 00000001-11111111b - PRESCALE*16 clock cycles - */ -#define DRAM_SDRCTRL3_PRESCALE_MASK (0xFF00U) -#define DRAM_SDRCTRL3_PRESCALE_SHIFT (8U) -#define DRAM_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_PRESCALE_SHIFT) & DRAM_SDRCTRL3_PRESCALE_MASK) -#define DRAM_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_PRESCALE_MASK) >> DRAM_SDRCTRL3_PRESCALE_SHIFT) - -/* - * REBL (RW) - * - * Refresh burst length - * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The - * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. - * 000b - 1 - * 001b - 2 - * 010b - 3 - * 011b - 4 - * 100b - 5 - * 101b - 6 - * 110b - 7 - * 111b - 8 - */ -#define DRAM_SDRCTRL3_REBL_MASK (0xEU) -#define DRAM_SDRCTRL3_REBL_SHIFT (1U) -#define DRAM_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_REBL_SHIFT) & DRAM_SDRCTRL3_REBL_MASK) -#define DRAM_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_REBL_MASK) >> DRAM_SDRCTRL3_REBL_SHIFT) - -/* - * REN (RW) - * - * Refresh enable - */ -#define DRAM_SDRCTRL3_REN_MASK (0x1U) -#define DRAM_SDRCTRL3_REN_SHIFT (0U) -#define DRAM_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_REN_SHIFT) & DRAM_SDRCTRL3_REN_MASK) -#define DRAM_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_REN_MASK) >> DRAM_SDRCTRL3_REN_SHIFT) - -/* Bitfield definition for register: SADDR */ -/* - * SA (RW) - * - * Slave address - */ -#define DRAM_SADDR_SA_MASK (0xFFFFFFFFUL) -#define DRAM_SADDR_SA_SHIFT (0U) -#define DRAM_SADDR_SA_SET(x) (((uint32_t)(x) << DRAM_SADDR_SA_SHIFT) & DRAM_SADDR_SA_MASK) -#define DRAM_SADDR_SA_GET(x) (((uint32_t)(x) & DRAM_SADDR_SA_MASK) >> DRAM_SADDR_SA_SHIFT) - -/* Bitfield definition for register: DATSZ */ -/* - * DATSZ (RW) - * - * Data Size in Byte - * When IP command is not a write/read operation, DATSZ field would be ignored. - * 000b - 4 - * 001b - 1 - * 010b - 2 - * 011b - 3 - * 100b - 4 - * 101b - 4 - * 110b - 4 - * 111b - 4 - */ -#define DRAM_DATSZ_DATSZ_MASK (0x7U) -#define DRAM_DATSZ_DATSZ_SHIFT (0U) -#define DRAM_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << DRAM_DATSZ_DATSZ_SHIFT) & DRAM_DATSZ_DATSZ_MASK) -#define DRAM_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & DRAM_DATSZ_DATSZ_MASK) >> DRAM_DATSZ_DATSZ_SHIFT) - -/* Bitfield definition for register: BYTEMSK */ -/* - * BM3 (RW) - * - * Byte Mask for Byte 3 (IPTXD bit 31:24) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM3_MASK (0x8U) -#define DRAM_BYTEMSK_BM3_SHIFT (3U) -#define DRAM_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM3_SHIFT) & DRAM_BYTEMSK_BM3_MASK) -#define DRAM_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM3_MASK) >> DRAM_BYTEMSK_BM3_SHIFT) - -/* - * BM2 (RW) - * - * Byte Mask for Byte 2 (IPTXD bit 23:16) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM2_MASK (0x4U) -#define DRAM_BYTEMSK_BM2_SHIFT (2U) -#define DRAM_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM2_SHIFT) & DRAM_BYTEMSK_BM2_MASK) -#define DRAM_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM2_MASK) >> DRAM_BYTEMSK_BM2_SHIFT) - -/* - * BM1 (RW) - * - * Byte Mask for Byte 1 (IPTXD bit 15:8) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM1_MASK (0x2U) -#define DRAM_BYTEMSK_BM1_SHIFT (1U) -#define DRAM_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM1_SHIFT) & DRAM_BYTEMSK_BM1_MASK) -#define DRAM_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM1_MASK) >> DRAM_BYTEMSK_BM1_SHIFT) - -/* - * BM0 (RW) - * - * Byte Mask for Byte 0 (IPTXD bit 7:0) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM0_MASK (0x1U) -#define DRAM_BYTEMSK_BM0_SHIFT (0U) -#define DRAM_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM0_SHIFT) & DRAM_BYTEMSK_BM0_MASK) -#define DRAM_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM0_MASK) >> DRAM_BYTEMSK_BM0_SHIFT) - -/* Bitfield definition for register: IPCMD */ -/* - * KEY (WO) - * - * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory - * device is selected by BRx settings and IPCR0 registers. - */ -#define DRAM_IPCMD_KEY_MASK (0xFFFF0000UL) -#define DRAM_IPCMD_KEY_SHIFT (16U) -#define DRAM_IPCMD_KEY_SET(x) (((uint32_t)(x) << DRAM_IPCMD_KEY_SHIFT) & DRAM_IPCMD_KEY_MASK) -#define DRAM_IPCMD_KEY_GET(x) (((uint32_t)(x) & DRAM_IPCMD_KEY_MASK) >> DRAM_IPCMD_KEY_SHIFT) - -/* - * CMD (RW) - * - * SDRAM Commands: - * • 0x8: READ - * • 0x9: WRITE - * • 0xA: MODESET - * • 0xB: ACTIVE - * • 0xC: AUTO REFRESH - * • 0xD: SELF REFRESH - * • 0xE: PRECHARGE - * • 0xF: PRECHARGE ALL - * • Others: RSVD - * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - */ -#define DRAM_IPCMD_CMD_MASK (0xFFFFU) -#define DRAM_IPCMD_CMD_SHIFT (0U) -#define DRAM_IPCMD_CMD_SET(x) (((uint32_t)(x) << DRAM_IPCMD_CMD_SHIFT) & DRAM_IPCMD_CMD_MASK) -#define DRAM_IPCMD_CMD_GET(x) (((uint32_t)(x) & DRAM_IPCMD_CMD_MASK) >> DRAM_IPCMD_CMD_SHIFT) - -/* Bitfield definition for register: IPTX */ -/* - * DAT (RW) - * - * Data - */ -#define DRAM_IPTX_DAT_MASK (0xFFFFFFFFUL) -#define DRAM_IPTX_DAT_SHIFT (0U) -#define DRAM_IPTX_DAT_SET(x) (((uint32_t)(x) << DRAM_IPTX_DAT_SHIFT) & DRAM_IPTX_DAT_MASK) -#define DRAM_IPTX_DAT_GET(x) (((uint32_t)(x) & DRAM_IPTX_DAT_MASK) >> DRAM_IPTX_DAT_SHIFT) - -/* Bitfield definition for register: IPRX */ -/* - * DAT (RW) - * - * Data - */ -#define DRAM_IPRX_DAT_MASK (0xFFFFFFFFUL) -#define DRAM_IPRX_DAT_SHIFT (0U) -#define DRAM_IPRX_DAT_SET(x) (((uint32_t)(x) << DRAM_IPRX_DAT_SHIFT) & DRAM_IPRX_DAT_MASK) -#define DRAM_IPRX_DAT_GET(x) (((uint32_t)(x) & DRAM_IPRX_DAT_MASK) >> DRAM_IPRX_DAT_SHIFT) - -/* Bitfield definition for register: STAT0 */ -/* - * IDLE (RO) - * - * Indicating whether it is in IDLE state. - * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no - * pending device access. - */ -#define DRAM_STAT0_IDLE_MASK (0x1U) -#define DRAM_STAT0_IDLE_SHIFT (0U) -#define DRAM_STAT0_IDLE_GET(x) (((uint32_t)(x) & DRAM_STAT0_IDLE_MASK) >> DRAM_STAT0_IDLE_SHIFT) - -/* Bitfield definition for register: DLYCFG */ -/* - * OE (RW) - * - * delay clock output enable, should be set after setting DLYEN and DLYSEL - */ -#define DRAM_DLYCFG_OE_MASK (0x2000U) -#define DRAM_DLYCFG_OE_SHIFT (13U) -#define DRAM_DLYCFG_OE_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_OE_SHIFT) & DRAM_DLYCFG_OE_MASK) -#define DRAM_DLYCFG_OE_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_OE_MASK) >> DRAM_DLYCFG_OE_SHIFT) - -/* - * DLYSEL (RW) - * - * delay line select, 0 for 1 cell, 31 for all 32 cells - */ -#define DRAM_DLYCFG_DLYSEL_MASK (0x3EU) -#define DRAM_DLYCFG_DLYSEL_SHIFT (1U) -#define DRAM_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_DLYSEL_SHIFT) & DRAM_DLYCFG_DLYSEL_MASK) -#define DRAM_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_DLYSEL_MASK) >> DRAM_DLYCFG_DLYSEL_SHIFT) - -/* - * DLYEN (RW) - * - * delay line enable - */ -#define DRAM_DLYCFG_DLYEN_MASK (0x1U) -#define DRAM_DLYCFG_DLYEN_SHIFT (0U) -#define DRAM_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_DLYEN_SHIFT) & DRAM_DLYCFG_DLYEN_MASK) -#define DRAM_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_DLYEN_MASK) >> DRAM_DLYCFG_DLYEN_SHIFT) - - - -/* BR register group index macro definition */ -#define DRAM_BR_BASE0 (0UL) -#define DRAM_BR_BASE1 (1UL) - - -#endif /* HPM_DRAM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h index 82508381de..9deab13543 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,8 +18,7 @@ typedef struct { __RW uint32_t GMII_DATA; /* 0x14: GMII Data Register */ __RW uint32_t FLOWCTRL; /* 0x18: Flow Control Register */ __RW uint32_t VLAN_TAG; /* 0x1C: VLAN Tag Register */ - __R uint32_t VERSION; /* 0x20: Version Register */ - __R uint32_t DEBUGGING; /* 0x24: Debug Register */ + __R uint8_t RESERVED0[8]; /* 0x20 - 0x27: Reserved */ __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Regsiter */ @@ -32,11 +31,10 @@ typedef struct { __RW uint32_t HIGH; /* 0x48: MAC Address High Register */ __RW uint32_t LOW; /* 0x4C: MAC Address Low Register */ } MAC_ADDR[4]; - __R uint8_t RESERVED0[112]; /* 0x68 - 0xD7: Reserved */ + __R uint8_t RESERVED1[112]; /* 0x68 - 0xD7: Reserved */ __RW uint32_t XMII_CSR; /* 0xD8: SGMII/RGMII/SMII Control and Status Register */ __RW uint32_t WDOG_WTO; /* 0xDC: Watchdog Timeout Register */ - __RW uint32_t GPIO; /* 0xE0: General Purpose IO Register */ - __R uint8_t RESERVED1[28]; /* 0xE4 - 0xFF: Reserved */ + __R uint8_t RESERVED2[32]; /* 0xE0 - 0xFF: Reserved */ __RW uint32_t MMC_CNTRL; /* 0x100: MMC Control establishes the operating mode of MMC. */ __RW uint32_t MMC_INTR_RX; /* 0x104: MMC Receive Interrupt maintains the interrupt generated from all of the receive statistic counters. */ @@ -68,152 +66,20 @@ frames. */ __RW uint32_t TX1024TOMAXOCTETS_GB; /* 0x138: Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. */ - __RW uint32_t TXUNICASTFRAMES_GB; /* 0x13C: Number of good and bad unicast frames transmitted. */ - __RW uint32_t TXMULTICASTFRAMES_GB; /* 0x140: Number of good and bad multicast frames transmitted. */ - __RW uint32_t TXBROADCASTFRAMES_GB; /* 0x144: Number of good and bad broadcast frames transmitted. */ - __RW uint32_t TXUNDERFLOWERROR; /* 0x148: Number of frames aborted because of frame underflow error. */ - __RW uint32_t TXSINGLECOL_G; /* 0x14C: Number of successfully transmitted frames after a single collision -in the half-duplex mode. */ - __RW uint32_t TXMULTICOL_G; /* 0x150: Number of successfully transmitted frames after multiple collisions -in the half-duplex mode. */ - __RW uint32_t TXDEFERRED; /* 0x154: Number of successfully transmitted frames after a deferral in the -half-duplex mode. */ - __RW uint32_t TXLATECOL; /* 0x158: Number of frames aborted because of late collision error */ - __RW uint32_t TXEXESSCOL; /* 0x15C: Number of frames aborted because of excessive (16) collision -errors */ - __RW uint32_t TXCARRIERERROR; /* 0x160: Number of frames aborted because of carrier sense error (no -carrier or loss of carrier). */ - __RW uint32_t TXOCTETCOUNT_G; /* 0x164: Number of bytes transmitted, exclusive of preamble, only in good -frames. */ - __RW uint32_t TXFRAMECOUNT_G; /* 0x168: Number of good frames transmitted */ - __RW uint32_t TXEXCESSDEF; /* 0x16C: Number of frames aborted because of excessive deferral error -(deferred for more than two max-sized frame times). */ - __RW uint32_t TXPAUSEFRAMES; /* 0x170: Number of good Pause frames transmitted */ - __RW uint32_t TXVLANFRAMES_G; /* 0x174: Number of good VLAN frames transmitted, exclusive of retried -frames. */ - __RW uint32_t TXOVERSIZE_G; /* 0x178: Number of frames transmitted without errors and with length -greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged -frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC -Configuration Register)). */ - __R uint8_t RESERVED2[4]; /* 0x17C - 0x17F: Reserved */ + __R uint8_t RESERVED3[68]; /* 0x13C - 0x17F: Reserved */ __RW uint32_t RXFRAMECOUNT_GB; /* 0x180: Number of good and bad frames received */ - __RW uint32_t RXOCTETCOUNT_G; /* 0x184: Number of bytes received, exclusive of preamble, only in good -frames. */ - __RW uint32_t RXOCTETCOUNT_GB; /* 0x188: Number of bytes received, exclusive of preamble, in good and bad -frames. */ - __RW uint32_t RXBROADCASTFRAMES_G; /* 0x18C: Number of good broadcast frames received */ - __RW uint32_t RXMULTICASTFRAMES_G; /* 0x190: Number of good multicast frames received */ - __RW uint32_t RXCRCERROR; /* 0x194: Number of frames received with CRC error */ - __RW uint32_t RXALIGNMENTERROR; /* 0x198: Number of frames received with alignment (dribble) error. Valid -only in 10/100 mode */ - __RW uint32_t RXRUNTERROR; /* 0x19C: Number of frames received with runt (<64 bytes and CRC error) -error. */ - __RW uint32_t RXJABBERERROR; /* 0x1A0: Number of giant frames received with length (including CRC) -greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with -CRC error. If Jumbo Frame mode is enabled, then frames of -length greater than 9,018 bytes (9,022 for VLAN tagged) are -considered as giant frames. */ - __RW uint32_t RXUNDERSIZE_G; /* 0x1A4: Number of frames received with length less than 64 bytes, without -any errors. */ - __RW uint32_t RXOVERSIZE_G; /* 0x1A8: Number of frames received without errors, with length greater -than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 -bytes if enabled in Bit 27 of Register 0 (MAC Configuration -Register)) */ - __RW uint32_t RX64OCTETS_GB; /* 0x1AC: Number of good and bad frames received with length 64 bytes, -exclusive of preamble. */ - __RW uint32_t RX65TO127OCTETS_GB; /* 0x1B0: */ - __RW uint32_t RX128TO255OCTETS_GB; /* 0x1B4: */ - __RW uint32_t RX256TO511OCTETS_GB; /* 0x1B8: Number of good and bad frames received with length between -256 and 511 (inclusive) bytes, exclusive of preamble. */ - __RW uint32_t RX512TO1023OCTETS_GB; /* 0x1BC: Number of good and bad frames received with length between -512 and 1023 (inclusive) bytes, exclusive of preamble. */ - __RW uint32_t RX1024TOMAXOCTETS_GB; /* 0x1C0: Number of good and bad frames received with length between -1024 and maxsize (inclusive) bytes, exclusive of preamble. */ - __RW uint32_t RXUNICASTFRAMES_G; /* 0x1C4: Number of received good unicast frames. */ - __RW uint32_t RXLENGTHERROR; /* 0x1C8: Number of frames received with length error (Length type field ≠ -frame size), for all frames with valid length field. */ - __RW uint32_t RXOUTOFRANGETYPE; /* 0x1CC: Number of frames received with length field not equal to the valid -frame size (greater than 1,500 but less than 1,536). */ - __RW uint32_t RXPAUSEFRAMES; /* 0x1D0: Number of good and valid Pause frames received. */ - __RW uint32_t RXFIFOOVERFLOW; /* 0x1D4: Number of missed received frames because of FIFO overflow. -This counter is not present in the GMAC-CORE configuration. */ - __RW uint32_t RXVLANFRAMES_GB; /* 0x1D8: Number of good and bad VLAN frames received. */ - __RW uint32_t RXWATCHDOGERROR; /* 0x1DC: Number of frames received with error because of watchdog -timeout error (frames with a data load larger than 2,048 bytes or -the value programmed in Register 55 (Watchdog Timeout -Register)). */ - __RW uint32_t RXRCVERROR; /* 0x1E0: Number of frames received with Receive error or Frame Extension -error on the GMII or MII interface. */ - __RW uint32_t RXCTRLFRAMES_G; /* 0x1E4: Number of received good control frames */ - __R uint8_t RESERVED3[24]; /* 0x1E8 - 0x1FF: Reserved */ + __R uint8_t RESERVED4[124]; /* 0x184 - 0x1FF: Reserved */ __RW uint32_t MMC_IPC_INTR_MASK_RX; /* 0x200: MMC IPC Receive Checksum Offload Interrupt Mask maintains the mask for the interrupt generated from the receive IPC statistic counters. */ - __R uint8_t RESERVED4[4]; /* 0x204 - 0x207: Reserved */ + __R uint8_t RESERVED5[4]; /* 0x204 - 0x207: Reserved */ __RW uint32_t MMC_IPC_INTR_RX; /* 0x208: MMC Receive Checksum Offload Interrupt maintains the interrupt that the receive IPC statistic counters generate. See Table 4-25 for further detail. */ - __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */ + __R uint8_t RESERVED6[4]; /* 0x20C - 0x20F: Reserved */ __RW uint32_t RXIPV4_GD_FMS; /* 0x210: Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload */ - __RW uint32_t RXIPV4_HDRERR_FRMS; /* 0x214: Number of IPv4 datagrams received with header (checksum, -length, or version mismatch) errors */ - __RW uint32_t RXIPV4_NOPAY_FRMS; /* 0x218: Number of IPv4 datagram frames received that did not have a -TCP, UDP, or ICMP payload processed by the Checksum engine */ - __RW uint32_t RXIPV4_FRAG_FRMS; /* 0x21C: Number of good IPv4 datagrams with fragmentation */ - __RW uint32_t RXIPV4_UDSBL_FRMS; /* 0x220: Number of good IPv4 datagrams received that had a UDP -payload with checksum disabled */ - __RW uint32_t RXIPV6_GD_FRMS; /* 0x224: Number of good IPv6 datagrams received with TCP, UDP, or -ICMP payloads */ - __RW uint32_t RXIPV6_HDRERR_FRMS; /* 0x228: Number of IPv6 datagrams received with header errors (length or -version mismatch) */ - __RW uint32_t RXIPV6_NOPAY_FRMS; /* 0x22C: Number of IPv6 datagram frames received that did not have a -TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with -fragmentation or security extension headers */ - __RW uint32_t RXUDP_GD_FRMS; /* 0x230: Number of good IP datagrams with a good UDP payload. This -counter is not updated when the rxipv4_udsbl_frms counter is -incremented. */ - __RW uint32_t RXUDP_ERR_FRMS; /* 0x234: Number of good IP datagrams whose UDP payload has a -checksum error */ - __RW uint32_t RXTCP_GD_FRMS; /* 0x238: Number of good IP datagrams with a good TCP payload */ - __RW uint32_t RXTCP_ERR_FRMS; /* 0x23C: Number of good IP datagrams whose TCP payload has a -checksum error */ - __RW uint32_t RXICMP_GD_FRMS; /* 0x240: Number of good IP datagrams with a good ICMP payload */ - __RW uint32_t RXICMP_ERR_FRMS; /* 0x244: Number of good IP datagrams whose ICMP payload has a -checksum error */ - __R uint8_t RESERVED6[8]; /* 0x248 - 0x24F: Reserved */ - __RW uint32_t RXIPV4_GD_OCTETS; /* 0x250: Number of bytes received in good IPv4 datagrams encapsulating -TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad -bytes are not included in this counter or in the octet counters listed -below). */ - __RW uint32_t RXIPV4_HDRERR_OCTETS; /* 0x254: Number of bytes received in IPv4 datagrams with header errors -(checksum, length, version mismatch). The value in the Length -field of IPv4 header is used to update this counter. */ - __RW uint32_t RXIPV4_NOPAY_OCTETS; /* 0x258: Number of bytes received in IPv4 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv4 header’s -Length field is used to update this counter. */ - __RW uint32_t RXIPV4_FRAG_OCTETS; /* 0x25C: Number of bytes received in fragmented IPv4 datagrams. The -value in the IPv4 header’s Length field is used to update this -counter */ - __RW uint32_t RXIPV4_UDSBL_OCTETS; /* 0x260: Number of bytes received in a UDP segment that had the UDP -checksum disabled. This counter does not count IP Header bytes. */ - __RW uint32_t RXIPV6_GD_OCTETS; /* 0x264: Number of bytes received in good IPv6 datagrams encapsulating -TCP, UDP or ICMPv6 data */ - __RW uint32_t RXIPV6_HDRERR_OCTETS; /* 0x268: Number of bytes received in IPv6 datagrams with header errors -(length, version mismatch). The value in the IPv6 header’s Length -field is used to update this counter. */ - __RW uint32_t RXIPV6_NOPAY_OCTETS; /* 0x26C: Number of bytes received in IPv6 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv6 header’s -Length field is used to update this counter. */ - __RW uint32_t RXUDP_GD_OCTETS; /* 0x270: Number of bytes received in a good UDP segment. This counter -(and the counters below) does not count IP header bytes. */ - __RW uint32_t RXUDP_ERR_OCTETS; /* 0x274: Number of bytes received in a UDP segment that had checksum -errors */ - __RW uint32_t RXTCP_GD_OCTETS; /* 0x278: Number of bytes received in a good TCP segment */ - __RW uint32_t RXTCP_ERR_OCTETS; /* 0x27C: Number of bytes received in a TCP segment with checksum -errors */ - __RW uint32_t RXICMP_GD_OCTETS; /* 0x280: Number of bytes received in a good ICMP segment */ - __R uint8_t RESERVED7[380]; /* 0x284 - 0x3FF: Reserved */ + __R uint8_t RESERVED7[492]; /* 0x214 - 0x3FF: Reserved */ struct { __RW uint32_t L3_L4_CTRL; /* 0x400: Layer 3 and Layer 4 Control Register */ __RW uint32_t L4_ADDR; /* 0x404: Layer 4 Address Register */ @@ -222,18 +88,15 @@ errors */ __RW uint32_t L3_ADDR_1; /* 0x414: Layer 3 Address 1 Register */ __RW uint32_t L3_ADDR_2; /* 0x418: Layer 3 Address 2 Register */ __RW uint32_t L3_ADDR_3; /* 0x41C: Layer 3 Address 3 Register */ - __R uint8_t RESERVED1[16]; /* 0x420 - 0x42F: Reserved */ - } L3_L4_CFG[4]; - __R uint8_t RESERVED8[64]; /* 0x4C0 - 0x4FF: Reserved */ - __RW uint32_t HASH_TABLE[8]; /* 0x500 - 0x51C: Hash Table Register 0 */ - __R uint8_t RESERVED9[100]; /* 0x520 - 0x583: Reserved */ + } L3_L4_CFG[1]; + __R uint8_t RESERVED8[356]; /* 0x420 - 0x583: Reserved */ __RW uint32_t VLAN_TAG_INC_RPL; /* 0x584: VLAN Tag Inclusion or Replacement Register */ __RW uint32_t VLAN_HASH; /* 0x588: VLAN Hash Table Register */ - __R uint8_t RESERVED10[372]; /* 0x58C - 0x6FF: Reserved */ + __R uint8_t RESERVED9[372]; /* 0x58C - 0x6FF: Reserved */ __RW uint32_t TS_CTRL; /* 0x700: Timestamp Control Register */ __RW uint32_t SUB_SEC_INCR; /* 0x704: Sub-Second Increment Register */ - __RW uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ - __RW uint32_t SYST_NSEC; /* 0x70C: System Time - Nanoseconds Register */ + __R uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ + __R uint32_t SYST_NSEC; /* 0x70C: System Time - Nanoseconds Register */ __RW uint32_t SYST_SEC_UPD; /* 0x710: System Time - Seconds Update Register */ __RW uint32_t SYST_NSEC_UPD; /* 0x714: System Time - Nanoseconds Update Register */ __RW uint32_t TS_ADDEND; /* 0x718: Timestamp Addend Register */ @@ -242,12 +105,12 @@ errors */ __RW uint32_t SYSTM_H_SEC; /* 0x724: System Time - Higher Word Seconds Register */ __R uint32_t TS_STATUS; /* 0x728: Timestamp Status Register */ __RW uint32_t PPS_CTRL; /* 0x72C: PPS Control Register */ - __RW uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ - __RW uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ - __R uint8_t RESERVED11[40]; /* 0x738 - 0x75F: Reserved */ + __R uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ + __R uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ + __R uint8_t RESERVED10[40]; /* 0x738 - 0x75F: Reserved */ __RW uint32_t PPS0_INTERVAL; /* 0x760: PPS0 Interval Register */ __RW uint32_t PPS0_WIDTH; /* 0x764: PPS0 Width Register */ - __R uint8_t RESERVED12[24]; /* 0x768 - 0x77F: Reserved */ + __R uint8_t RESERVED11[24]; /* 0x768 - 0x77F: Reserved */ struct { __RW uint32_t TGTTM_SEC; /* 0x780: PPS Target Time Seconds Register */ __RW uint32_t TGTTM_NSEC; /* 0x784: PPS Target Time Nanoseconds Register */ @@ -255,7 +118,7 @@ errors */ __RW uint32_t WIDTH; /* 0x78C: PPS Width Register */ __R uint8_t RESERVED0[16]; /* 0x790 - 0x79F: Reserved */ } PPS[3]; - __R uint8_t RESERVED13[2080]; /* 0x7E0 - 0xFFF: Reserved */ + __R uint8_t RESERVED12[2080]; /* 0x7E0 - 0xFFF: Reserved */ __RW uint32_t DMA_BUS_MODE; /* 0x1000: Bus Mode Register */ __RW uint32_t DMA_TX_POLL_DEMAND; /* 0x1004: Transmit Poll Demand Register */ __RW uint32_t DMA_RX_POLL_DEMAND; /* 0x1008: Receive Poll Demand Register */ @@ -268,17 +131,16 @@ errors */ __RW uint32_t DMA_RX_INTR_WDOG; /* 0x1024: Receive Interrupt Watchdog Timer Register */ __RW uint32_t DMA_AXI_MODE; /* 0x1028: AXI Bus Mode Register */ __RW uint32_t DMA_BUS_STATUS; /* 0x102C: AHB or AXI Status Register */ - __R uint8_t RESERVED14[24]; /* 0x1030 - 0x1047: Reserved */ + __R uint8_t RESERVED13[24]; /* 0x1030 - 0x1047: Reserved */ __RW uint32_t DMA_CURR_HOST_TX_DESC; /* 0x1048: Current Host Transmit Descriptor Register */ __RW uint32_t DMA_CURR_HOST_RX_DESC; /* 0x104C: Current Host Receive Descriptor Register */ __RW uint32_t DMA_CURR_HOST_TX_BUF; /* 0x1050: Current Host Transmit Buffer Address Register */ __RW uint32_t DMA_CURR_HOST_RX_BUF; /* 0x1054: Current Host Receive Buffer Address Register */ - __RW uint32_t DMA_HW_FEATURE; /* 0x1058: HW Feature Register */ - __R uint8_t RESERVED15[8100]; /* 0x105C - 0x2FFF: Reserved */ + __R uint8_t RESERVED14[8104]; /* 0x1058 - 0x2FFF: Reserved */ __RW uint32_t CTRL0; /* 0x3000: Control Register 0 */ - __R uint8_t RESERVED16[4]; /* 0x3004 - 0x3007: Reserved */ + __R uint8_t RESERVED15[4]; /* 0x3004 - 0x3007: Reserved */ __RW uint32_t CTRL2; /* 0x3008: Control Register 1 */ - __R uint8_t RESERVED17[28]; /* 0x300C - 0x3027: Reserved */ + __R uint8_t RESERVED16[28]; /* 0x300C - 0x3027: Reserved */ } ENET_Type; @@ -982,162 +844,6 @@ errors */ #define ENET_VLAN_TAG_VL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VL_SHIFT) & ENET_VLAN_TAG_VL_MASK) #define ENET_VLAN_TAG_VL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VL_MASK) >> ENET_VLAN_TAG_VL_SHIFT) -/* Bitfield definition for register: VERSION */ -/* - * USERVER (RO) - * - * User-defined Version - */ -#define ENET_VERSION_USERVER_MASK (0xFF00U) -#define ENET_VERSION_USERVER_SHIFT (8U) -#define ENET_VERSION_USERVER_GET(x) (((uint32_t)(x) & ENET_VERSION_USERVER_MASK) >> ENET_VERSION_USERVER_SHIFT) - -/* - * SNPSVER (RO) - * - * Synopsys-defined Version (3.7) - */ -#define ENET_VERSION_SNPSVER_MASK (0xFFU) -#define ENET_VERSION_SNPSVER_SHIFT (0U) -#define ENET_VERSION_SNPSVER_GET(x) (((uint32_t)(x) & ENET_VERSION_SNPSVER_MASK) >> ENET_VERSION_SNPSVER_SHIFT) - -/* Bitfield definition for register: DEBUGGING */ -/* - * TXSTSFSTS (RO) - * - * MTL TxStatus FIFO Full Status - * When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. - */ -#define ENET_DEBUGGING_TXSTSFSTS_MASK (0x2000000UL) -#define ENET_DEBUGGING_TXSTSFSTS_SHIFT (25U) -#define ENET_DEBUGGING_TXSTSFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXSTSFSTS_MASK) >> ENET_DEBUGGING_TXSTSFSTS_SHIFT) - -/* - * TXFSTS (RO) - * - * MTL Tx FIFO Not Empty Status - * When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. - */ -#define ENET_DEBUGGING_TXFSTS_MASK (0x1000000UL) -#define ENET_DEBUGGING_TXFSTS_SHIFT (24U) -#define ENET_DEBUGGING_TXFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXFSTS_MASK) >> ENET_DEBUGGING_TXFSTS_SHIFT) - -/* - * TWCSTS (RO) - * - * MTL Tx FIFO Write Controller Status - * When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. - */ -#define ENET_DEBUGGING_TWCSTS_MASK (0x400000UL) -#define ENET_DEBUGGING_TWCSTS_SHIFT (22U) -#define ENET_DEBUGGING_TWCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TWCSTS_MASK) >> ENET_DEBUGGING_TWCSTS_SHIFT) - -/* - * TRCSTS (RO) - * - * MTL Tx FIFO Read Controller Status - * This field indicates the state of the Tx FIFO Read Controller: - * - 00: IDLE state - * - 01: READ state (transferring data to the MAC transmitter) - * - 10: Waiting for TxStatus from the MAC transmitter - * - 11: Writing the received TxStatus or flushing the Tx FIFO - */ -#define ENET_DEBUGGING_TRCSTS_MASK (0x300000UL) -#define ENET_DEBUGGING_TRCSTS_SHIFT (20U) -#define ENET_DEBUGGING_TRCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TRCSTS_MASK) >> ENET_DEBUGGING_TRCSTS_SHIFT) - -/* - * TXPAUSED (RO) - * - * MAC Transmitter in Pause - * When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. - */ -#define ENET_DEBUGGING_TXPAUSED_MASK (0x80000UL) -#define ENET_DEBUGGING_TXPAUSED_SHIFT (19U) -#define ENET_DEBUGGING_TXPAUSED_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXPAUSED_MASK) >> ENET_DEBUGGING_TXPAUSED_SHIFT) - -/* - * TFCSTS (RO) - * - * MAC Transmit Frame Controller Status - * This field indicates the state of the MAC Transmit Frame Controller module: - * - 00: IDLE state - * - 01: Waiting for status of previous frame or IFG or backoff period to be over - * - 10: Generating and transmitting a Pause frame (in the full-duplex mode) - * - 11: Transferring input frame for transmission - */ -#define ENET_DEBUGGING_TFCSTS_MASK (0x60000UL) -#define ENET_DEBUGGING_TFCSTS_SHIFT (17U) -#define ENET_DEBUGGING_TFCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TFCSTS_MASK) >> ENET_DEBUGGING_TFCSTS_SHIFT) - -/* - * TPESTS (RO) - * - * MAC GMII or MII Transmit Protocol Engine Status - * When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. - */ -#define ENET_DEBUGGING_TPESTS_MASK (0x10000UL) -#define ENET_DEBUGGING_TPESTS_SHIFT (16U) -#define ENET_DEBUGGING_TPESTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TPESTS_MASK) >> ENET_DEBUGGING_TPESTS_SHIFT) - -/* - * RXFSTS (RO) - * - * MTL RxFIFO Fill-Level Status - * This field gives the status of the fill-level of the Rx FIFO: - * - 00: Rx FIFO Empty - * - 01: Rx FIFO fill-level below flow-control deactivate threshold - * - 10: Rx FIFO fill-level above flow-control activate threshold - * - 11: Rx FIFO Full - */ -#define ENET_DEBUGGING_RXFSTS_MASK (0x300U) -#define ENET_DEBUGGING_RXFSTS_SHIFT (8U) -#define ENET_DEBUGGING_RXFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RXFSTS_MASK) >> ENET_DEBUGGING_RXFSTS_SHIFT) - -/* - * RRCSTS (RO) - * - * MTL RxFIFO Read Controller State - * This field gives the state of the Rx FIFO read Controller: - * - 00: IDLE state - * - 01: Reading frame data - * - 10: Reading frame status (or timestamp) - * - 11: Flushing the frame data and status - */ -#define ENET_DEBUGGING_RRCSTS_MASK (0x60U) -#define ENET_DEBUGGING_RRCSTS_SHIFT (5U) -#define ENET_DEBUGGING_RRCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RRCSTS_MASK) >> ENET_DEBUGGING_RRCSTS_SHIFT) - -/* - * RWCSTS (RO) - * - * MTL Rx FIFO Write Controller Active Status - * When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. - */ -#define ENET_DEBUGGING_RWCSTS_MASK (0x10U) -#define ENET_DEBUGGING_RWCSTS_SHIFT (4U) -#define ENET_DEBUGGING_RWCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RWCSTS_MASK) >> ENET_DEBUGGING_RWCSTS_SHIFT) - -/* - * RFCFCSTS (RO) - * - * MAC Receive Frame FIFO Controller Status - * When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. - */ -#define ENET_DEBUGGING_RFCFCSTS_MASK (0x6U) -#define ENET_DEBUGGING_RFCFCSTS_SHIFT (1U) -#define ENET_DEBUGGING_RFCFCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RFCFCSTS_MASK) >> ENET_DEBUGGING_RFCFCSTS_SHIFT) - -/* - * RPESTS (RO) - * - * MAC GMII or MII Receive Protocol Engine Status - * When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. - */ -#define ENET_DEBUGGING_RPESTS_MASK (0x1U) -#define ENET_DEBUGGING_RPESTS_SHIFT (0U) -#define ENET_DEBUGGING_RPESTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RPESTS_MASK) >> ENET_DEBUGGING_RPESTS_SHIFT) - /* Bitfield definition for register: RWKFRMFILT */ /* * WKUPFRMFILT (RW) @@ -1552,14 +1258,13 @@ errors */ /* Bitfield definition for register: MAC_ADDR_0_HIGH */ /* - * AE (RW) + * AE (RO) * * Address Enable - * This bit is always set to 1. + * This bit is RO. The bit value is fixed at 1. */ #define ENET_MAC_ADDR_0_HIGH_AE_MASK (0x80000000UL) #define ENET_MAC_ADDR_0_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_0_HIGH_AE_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_HIGH_AE_SHIFT) & ENET_MAC_ADDR_0_HIGH_AE_MASK) #define ENET_MAC_ADDR_0_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_AE_MASK) >> ENET_MAC_ADDR_0_HIGH_AE_SHIFT) /* @@ -1643,15 +1348,6 @@ errors */ #define ENET_MAC_ADDR_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) /* Bitfield definition for register: XMII_CSR */ -/* - * SMIDRXS (RO) - * - * Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). - */ -#define ENET_XMII_CSR_SMIDRXS_MASK (0x10000UL) -#define ENET_XMII_CSR_SMIDRXS_SHIFT (16U) -#define ENET_XMII_CSR_SMIDRXS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_SMIDRXS_MASK) >> ENET_XMII_CSR_SMIDRXS_SHIFT) - /* * FALSCARDET (RW) * @@ -1735,43 +1431,6 @@ errors */ #define ENET_WDOG_WTO_WTO_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_WTO_SHIFT) & ENET_WDOG_WTO_WTO_MASK) #define ENET_WDOG_WTO_WTO_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_WTO_MASK) >> ENET_WDOG_WTO_WTO_SHIFT) -/* Bitfield definition for register: GPIO */ -/* - * GPIT (RW) - * - */ -#define ENET_GPIO_GPIT_MASK (0xF000000UL) -#define ENET_GPIO_GPIT_SHIFT (24U) -#define ENET_GPIO_GPIT_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIT_SHIFT) & ENET_GPIO_GPIT_MASK) -#define ENET_GPIO_GPIT_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIT_MASK) >> ENET_GPIO_GPIT_SHIFT) - -/* - * GPIE (RW) - * - */ -#define ENET_GPIO_GPIE_MASK (0xF0000UL) -#define ENET_GPIO_GPIE_SHIFT (16U) -#define ENET_GPIO_GPIE_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIE_SHIFT) & ENET_GPIO_GPIE_MASK) -#define ENET_GPIO_GPIE_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIE_MASK) >> ENET_GPIO_GPIE_SHIFT) - -/* - * GPO (RW) - * - */ -#define ENET_GPIO_GPO_MASK (0xF00U) -#define ENET_GPIO_GPO_SHIFT (8U) -#define ENET_GPIO_GPO_SET(x) (((uint32_t)(x) << ENET_GPIO_GPO_SHIFT) & ENET_GPIO_GPO_MASK) -#define ENET_GPIO_GPO_GET(x) (((uint32_t)(x) & ENET_GPIO_GPO_MASK) >> ENET_GPIO_GPO_SHIFT) - -/* - * GPIS (RW) - * - */ -#define ENET_GPIO_GPIS_MASK (0xFU) -#define ENET_GPIO_GPIS_SHIFT (0U) -#define ENET_GPIO_GPIS_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIS_SHIFT) & ENET_GPIO_GPIS_MASK) -#define ENET_GPIO_GPIS_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIS_MASK) >> ENET_GPIO_GPIS_SHIFT) - /* Bitfield definition for register: MMC_CNTRL */ /* * UCDBC (RW) @@ -3101,182 +2760,6 @@ errors */ #define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) #define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) -/* Bitfield definition for register: TXUNICASTFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad unicast frames transmitted. - */ -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK) -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXMULTICASTFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad multicast frames transmitted. - */ -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK) -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXBROADCASTFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad broadcast frames transmitted. - */ -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK) -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXUNDERFLOWERROR */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of frame underflow error. - */ -#define ENET_TXUNDERFLOWERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT (0U) -#define ENET_TXUNDERFLOWERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT) & ENET_TXUNDERFLOWERROR_FRMCNT_MASK) -#define ENET_TXUNDERFLOWERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXUNDERFLOWERROR_FRMCNT_MASK) >> ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXSINGLECOL_G */ -/* - * FRMCNT (RW) - * - * Number of successfully transmitted frames after a single collision in the half-duplex mode. - */ -#define ENET_TXSINGLECOL_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXSINGLECOL_G_FRMCNT_SHIFT (0U) -#define ENET_TXSINGLECOL_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXSINGLECOL_G_FRMCNT_SHIFT) & ENET_TXSINGLECOL_G_FRMCNT_MASK) -#define ENET_TXSINGLECOL_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXSINGLECOL_G_FRMCNT_MASK) >> ENET_TXSINGLECOL_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXMULTICOL_G */ -/* - * FRMCNT (RW) - * - * Number of successfully transmitted frames after multiple collisions in the half-duplex mode. - */ -#define ENET_TXMULTICOL_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXMULTICOL_G_FRMCNT_SHIFT (0U) -#define ENET_TXMULTICOL_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXMULTICOL_G_FRMCNT_SHIFT) & ENET_TXMULTICOL_G_FRMCNT_MASK) -#define ENET_TXMULTICOL_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXMULTICOL_G_FRMCNT_MASK) >> ENET_TXMULTICOL_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXDEFERRED */ -/* - * FRMCNT (RW) - * - * Number of successfully transmitted frames after a deferral in the half-duplex mode. - */ -#define ENET_TXDEFERRED_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXDEFERRED_FRMCNT_SHIFT (0U) -#define ENET_TXDEFERRED_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXDEFERRED_FRMCNT_SHIFT) & ENET_TXDEFERRED_FRMCNT_MASK) -#define ENET_TXDEFERRED_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXDEFERRED_FRMCNT_MASK) >> ENET_TXDEFERRED_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXLATECOL */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of late collision error. - */ -#define ENET_TXLATECOL_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXLATECOL_FRMCNT_SHIFT (0U) -#define ENET_TXLATECOL_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXLATECOL_FRMCNT_SHIFT) & ENET_TXLATECOL_FRMCNT_MASK) -#define ENET_TXLATECOL_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXLATECOL_FRMCNT_MASK) >> ENET_TXLATECOL_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXEXESSCOL */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of excessive (16) collision errors. - */ -#define ENET_TXEXESSCOL_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXEXESSCOL_FRMCNT_SHIFT (0U) -#define ENET_TXEXESSCOL_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXEXESSCOL_FRMCNT_SHIFT) & ENET_TXEXESSCOL_FRMCNT_MASK) -#define ENET_TXEXESSCOL_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXEXESSCOL_FRMCNT_MASK) >> ENET_TXEXESSCOL_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXCARRIERERROR */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of carrier sense error (no carrier or loss of carrier). - */ -#define ENET_TXCARRIERERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXCARRIERERROR_FRMCNT_SHIFT (0U) -#define ENET_TXCARRIERERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXCARRIERERROR_FRMCNT_SHIFT) & ENET_TXCARRIERERROR_FRMCNT_MASK) -#define ENET_TXCARRIERERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXCARRIERERROR_FRMCNT_MASK) >> ENET_TXCARRIERERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXOCTETCOUNT_G */ -/* - * BYTECNT (RW) - * - * Number of bytes transmitted, exclusive of preamble, only in good frames. - */ -#define ENET_TXOCTETCOUNT_G_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT (0U) -#define ENET_TXOCTETCOUNT_G_BYTECNT_SET(x) (((uint32_t)(x) << ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT) & ENET_TXOCTETCOUNT_G_BYTECNT_MASK) -#define ENET_TXOCTETCOUNT_G_BYTECNT_GET(x) (((uint32_t)(x) & ENET_TXOCTETCOUNT_G_BYTECNT_MASK) >> ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT) - -/* Bitfield definition for register: TXFRAMECOUNT_G */ -/* - * FRMCNT (RW) - * - * Number of good frames transmitted. - */ -#define ENET_TXFRAMECOUNT_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT (0U) -#define ENET_TXFRAMECOUNT_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT) & ENET_TXFRAMECOUNT_G_FRMCNT_MASK) -#define ENET_TXFRAMECOUNT_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXFRAMECOUNT_G_FRMCNT_MASK) >> ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXEXCESSDEF */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). - */ -#define ENET_TXEXCESSDEF_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXEXCESSDEF_FRMCNT_SHIFT (0U) -#define ENET_TXEXCESSDEF_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXEXCESSDEF_FRMCNT_SHIFT) & ENET_TXEXCESSDEF_FRMCNT_MASK) -#define ENET_TXEXCESSDEF_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXEXCESSDEF_FRMCNT_MASK) >> ENET_TXEXCESSDEF_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXPAUSEFRAMES */ -/* - * FRMCNT (RW) - * - * Number of good Pause frames transmitted. - */ -#define ENET_TXPAUSEFRAMES_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXPAUSEFRAMES_FRMCNT_SHIFT (0U) -#define ENET_TXPAUSEFRAMES_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXPAUSEFRAMES_FRMCNT_SHIFT) & ENET_TXPAUSEFRAMES_FRMCNT_MASK) -#define ENET_TXPAUSEFRAMES_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXPAUSEFRAMES_FRMCNT_MASK) >> ENET_TXPAUSEFRAMES_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXVLANFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of good VLAN frames transmitted, exclusive of retried frames. - */ -#define ENET_TXVLANFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXVLANFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_TXVLANFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXVLANFRAMES_G_FRMCNT_SHIFT) & ENET_TXVLANFRAMES_G_FRMCNT_MASK) -#define ENET_TXVLANFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXVLANFRAMES_G_FRMCNT_MASK) >> ENET_TXVLANFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXOVERSIZE_G */ -/* - * FRMCNT (RW) - * - * Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - */ -#define ENET_TXOVERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXOVERSIZE_G_FRMCNT_SHIFT (0U) -#define ENET_TXOVERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXOVERSIZE_G_FRMCNT_SHIFT) & ENET_TXOVERSIZE_G_FRMCNT_MASK) -#define ENET_TXOVERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXOVERSIZE_G_FRMCNT_MASK) >> ENET_TXOVERSIZE_G_FRMCNT_SHIFT) - /* Bitfield definition for register: RXFRAMECOUNT_GB */ /* * FRMCNT (RW) @@ -3288,281 +2771,6 @@ errors */ #define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) #define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) -/* Bitfield definition for register: RXOCTETCOUNT_G */ -/* - * BYTECNT (RW) - * - * Number of bytes received, exclusive of preamble, in good and bad frames. - */ -#define ENET_RXOCTETCOUNT_G_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT (0U) -#define ENET_RXOCTETCOUNT_G_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT) & ENET_RXOCTETCOUNT_G_BYTECNT_MASK) -#define ENET_RXOCTETCOUNT_G_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXOCTETCOUNT_G_BYTECNT_MASK) >> ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXOCTETCOUNT_GB */ -/* - * BYTECNT (RW) - * - * Number of bytes received, exclusive of preamble, only in good frames. - */ -#define ENET_RXOCTETCOUNT_GB_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT (0U) -#define ENET_RXOCTETCOUNT_GB_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT) & ENET_RXOCTETCOUNT_GB_BYTECNT_MASK) -#define ENET_RXOCTETCOUNT_GB_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXOCTETCOUNT_GB_BYTECNT_MASK) >> ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXBROADCASTFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of good broadcast frames received. - */ -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK) -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK) >> ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXMULTICASTFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of good multicast frames received. - */ -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK) -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK) >> ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXCRCERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with CRC error. - */ -#define ENET_RXCRCERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXCRCERROR_FRMCNT_SHIFT (0U) -#define ENET_RXCRCERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXCRCERROR_FRMCNT_SHIFT) & ENET_RXCRCERROR_FRMCNT_MASK) -#define ENET_RXCRCERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXCRCERROR_FRMCNT_MASK) >> ENET_RXCRCERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXALIGNMENTERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. - */ -#define ENET_RXALIGNMENTERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXALIGNMENTERROR_FRMCNT_SHIFT (0U) -#define ENET_RXALIGNMENTERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXALIGNMENTERROR_FRMCNT_SHIFT) & ENET_RXALIGNMENTERROR_FRMCNT_MASK) -#define ENET_RXALIGNMENTERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXALIGNMENTERROR_FRMCNT_MASK) >> ENET_RXALIGNMENTERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXRUNTERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with runt (<64 bytes and CRC error) error. - */ -#define ENET_RXRUNTERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXRUNTERROR_FRMCNT_SHIFT (0U) -#define ENET_RXRUNTERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXRUNTERROR_FRMCNT_SHIFT) & ENET_RXRUNTERROR_FRMCNT_MASK) -#define ENET_RXRUNTERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXRUNTERROR_FRMCNT_MASK) >> ENET_RXRUNTERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXJABBERERROR */ -/* - * FRMCNT (RW) - * - * Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - */ -#define ENET_RXJABBERERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXJABBERERROR_FRMCNT_SHIFT (0U) -#define ENET_RXJABBERERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXJABBERERROR_FRMCNT_SHIFT) & ENET_RXJABBERERROR_FRMCNT_MASK) -#define ENET_RXJABBERERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXJABBERERROR_FRMCNT_MASK) >> ENET_RXJABBERERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUNDERSIZE_G */ -/* - * FRMCNT (RW) - * - * Number of frames received with length less than 64 bytes, without any errors. - */ -#define ENET_RXUNDERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUNDERSIZE_G_FRMCNT_SHIFT (0U) -#define ENET_RXUNDERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUNDERSIZE_G_FRMCNT_SHIFT) & ENET_RXUNDERSIZE_G_FRMCNT_MASK) -#define ENET_RXUNDERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUNDERSIZE_G_FRMCNT_MASK) >> ENET_RXUNDERSIZE_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXOVERSIZE_G */ -/* - * FRMCNT (RW) - * - * Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - */ -#define ENET_RXOVERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOVERSIZE_G_FRMCNT_SHIFT (0U) -#define ENET_RXOVERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXOVERSIZE_G_FRMCNT_SHIFT) & ENET_RXOVERSIZE_G_FRMCNT_MASK) -#define ENET_RXOVERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXOVERSIZE_G_FRMCNT_MASK) >> ENET_RXOVERSIZE_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX64OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length 64 bytes, exclusive of preamble. - */ -#define ENET_RX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX64OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX64OCTETS_GB_FRMCNT_SHIFT) & ENET_RX64OCTETS_GB_FRMCNT_MASK) -#define ENET_RX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX64OCTETS_GB_FRMCNT_MASK) >> ENET_RX64OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX65TO127OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_RX65TO127OCTETS_GB_FRMCNT_MASK) -#define ENET_RX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX128TO255OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_RX128TO255OCTETS_GB_FRMCNT_MASK) -#define ENET_RX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX256TO511OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_RX256TO511OCTETS_GB_FRMCNT_MASK) -#define ENET_RX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX512TO1023OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK) -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX1024TOMAXOCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK) -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUNICASTFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of received good unicast frames. - */ -#define ENET_RXUNICASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXUNICASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXUNICASTFRAMES_G_FRMCNT_MASK) -#define ENET_RXUNICASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUNICASTFRAMES_G_FRMCNT_MASK) >> ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXLENGTHERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. - */ -#define ENET_RXLENGTHERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXLENGTHERROR_FRMCNT_SHIFT (0U) -#define ENET_RXLENGTHERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXLENGTHERROR_FRMCNT_SHIFT) & ENET_RXLENGTHERROR_FRMCNT_MASK) -#define ENET_RXLENGTHERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXLENGTHERROR_FRMCNT_MASK) >> ENET_RXLENGTHERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXOUTOFRANGETYPE */ -/* - * FRMCNT (RW) - * - * Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - */ -#define ENET_RXOUTOFRANGETYPE_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT (0U) -#define ENET_RXOUTOFRANGETYPE_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT) & ENET_RXOUTOFRANGETYPE_FRMCNT_MASK) -#define ENET_RXOUTOFRANGETYPE_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXOUTOFRANGETYPE_FRMCNT_MASK) >> ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXPAUSEFRAMES */ -/* - * FRMCNT (RW) - * - * Number of good and valid Pause frames received. - */ -#define ENET_RXPAUSEFRAMES_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXPAUSEFRAMES_FRMCNT_SHIFT (0U) -#define ENET_RXPAUSEFRAMES_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXPAUSEFRAMES_FRMCNT_SHIFT) & ENET_RXPAUSEFRAMES_FRMCNT_MASK) -#define ENET_RXPAUSEFRAMES_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXPAUSEFRAMES_FRMCNT_MASK) >> ENET_RXPAUSEFRAMES_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXFIFOOVERFLOW */ -/* - * FRMCNT (RW) - * - * Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. - */ -#define ENET_RXFIFOOVERFLOW_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT (0U) -#define ENET_RXFIFOOVERFLOW_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT) & ENET_RXFIFOOVERFLOW_FRMCNT_MASK) -#define ENET_RXFIFOOVERFLOW_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFIFOOVERFLOW_FRMCNT_MASK) >> ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXVLANFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad VLAN frames received. - */ -#define ENET_RXVLANFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_RXVLANFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT) & ENET_RXVLANFRAMES_GB_FRMCNT_MASK) -#define ENET_RXVLANFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXVLANFRAMES_GB_FRMCNT_MASK) >> ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXWATCHDOGERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). - */ -#define ENET_RXWATCHDOGERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXWATCHDOGERROR_FRMCNT_SHIFT (0U) -#define ENET_RXWATCHDOGERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXWATCHDOGERROR_FRMCNT_SHIFT) & ENET_RXWATCHDOGERROR_FRMCNT_MASK) -#define ENET_RXWATCHDOGERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXWATCHDOGERROR_FRMCNT_MASK) >> ENET_RXWATCHDOGERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXRCVERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. - */ -#define ENET_RXRCVERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXRCVERROR_FRMCNT_SHIFT (0U) -#define ENET_RXRCVERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXRCVERROR_FRMCNT_SHIFT) & ENET_RXRCVERROR_FRMCNT_MASK) -#define ENET_RXRCVERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXRCVERROR_FRMCNT_MASK) >> ENET_RXRCVERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXCTRLFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of received good control frames. - */ -#define ENET_RXCTRLFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXCTRLFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT) & ENET_RXCTRLFRAMES_G_FRMCNT_MASK) -#define ENET_RXCTRLFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXCTRLFRAMES_G_FRMCNT_MASK) >> ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT) - /* Bitfield definition for register: MMC_IPC_INTR_MASK_RX */ /* * RXICMPEROIM (RW) @@ -4192,292 +3400,6 @@ errors */ #define ENET_RXIPV4_GD_FMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) #define ENET_RXIPV4_GD_FMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) >> ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) -/* Bitfield definition for register: RXIPV4_HDRERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors - */ -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_NOPAY_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine - */ -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_FRAG_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams with fragmentation - */ -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_UDSBL_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams received that had a UDP payload with checksum disabled - */ -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads - */ -#define ENET_RXIPV6_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV6_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_GD_FRMS_FRMCNT_MASK) -#define ENET_RXIPV6_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_GD_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_HDRERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv6 datagrams received with header errors (length or version mismatch) - */ -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK) -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_NOPAY_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers - */ -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK) -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUDP_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. - */ -#define ENET_RXUDP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXUDP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXUDP_GD_FRMS_FRMCNT_MASK) -#define ENET_RXUDP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_GD_FRMS_FRMCNT_MASK) >> ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUDP_ERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams whose UDP payload has a checksum error - */ -#define ENET_RXUDP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXUDP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXUDP_ERR_FRMS_FRMCNT_MASK) -#define ENET_RXUDP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXTCP_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams with a good TCP payload - */ -#define ENET_RXTCP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXTCP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXTCP_GD_FRMS_FRMCNT_MASK) -#define ENET_RXTCP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_GD_FRMS_FRMCNT_MASK) >> ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXTCP_ERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams whose TCP payload has a checksum error - */ -#define ENET_RXTCP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXTCP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXTCP_ERR_FRMS_FRMCNT_MASK) -#define ENET_RXTCP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXICMP_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams with a good ICMP payload - */ -#define ENET_RXICMP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXICMP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXICMP_GD_FRMS_FRMCNT_MASK) -#define ENET_RXICMP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_GD_FRMS_FRMCNT_MASK) >> ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXICMP_ERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams whose ICMP payload has a checksum error - */ -#define ENET_RXICMP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXICMP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXICMP_ERR_FRMS_FRMCNT_MASK) -#define ENET_RXICMP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). - */ -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_HDRERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. - */ -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_NOPAY_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_FRAG_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_UDSBL_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. - */ -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data - */ -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_HDRERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_NOPAY_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXUDP_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. - */ -#define ENET_RXUDP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXUDP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXUDP_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXUDP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXUDP_ERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a UDP segment that had checksum errors - */ -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT) & ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK) -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK) >> ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXTCP_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a good TCP segment - */ -#define ENET_RXTCP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXTCP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXTCP_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXTCP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXTCP_ERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a TCP segment with checksum errors - */ -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT) & ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK) -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK) >> ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXICMP_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a good ICMP segment - */ -#define ENET_RXICMP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXICMP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXICMP_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXICMP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT) - /* Bitfield definition for register of struct array L3_L4_CFG: L3_L4_CTRL */ /* * L4DPIM0 (RW) @@ -4693,18 +3615,6 @@ errors */ #define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) #define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) >> ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) -/* Bitfield definition for register array: HASH_TABLE */ -/* - * HT31T0 (RW) - * - * First 32 bits of Hash Table - * This field contains the first 32 Bits (31:0) of the Hash table. - */ -#define ENET_HASH_TABLE_HT31T0_MASK (0xFFFFFFFFUL) -#define ENET_HASH_TABLE_HT31T0_SHIFT (0U) -#define ENET_HASH_TABLE_HT31T0_SET(x) (((uint32_t)(x) << ENET_HASH_TABLE_HT31T0_SHIFT) & ENET_HASH_TABLE_HT31T0_MASK) -#define ENET_HASH_TABLE_HT31T0_GET(x) (((uint32_t)(x) & ENET_HASH_TABLE_HT31T0_MASK) >> ENET_HASH_TABLE_HT31T0_SHIFT) - /* Bitfield definition for register: VLAN_TAG_INC_RPL */ /* * CSVL (RW) @@ -5011,26 +3921,24 @@ errors */ /* Bitfield definition for register: SYST_SEC */ /* - * TSS (RW) + * TSS (RO) * * Timestamp Second * The value in this field indicates the current value in seconds of the System Time maintained by the MAC. */ #define ENET_SYST_SEC_TSS_MASK (0xFFFFFFFFUL) #define ENET_SYST_SEC_TSS_SHIFT (0U) -#define ENET_SYST_SEC_TSS_SET(x) (((uint32_t)(x) << ENET_SYST_SEC_TSS_SHIFT) & ENET_SYST_SEC_TSS_MASK) #define ENET_SYST_SEC_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_TSS_MASK) >> ENET_SYST_SEC_TSS_SHIFT) /* Bitfield definition for register: SYST_NSEC */ /* - * TSSS (RW) + * TSSS (RO) * * Timestamp Sub Seconds * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. */ #define ENET_SYST_NSEC_TSSS_MASK (0x7FFFFFFFUL) #define ENET_SYST_NSEC_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_TSSS_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_TSSS_SHIFT) & ENET_SYST_NSEC_TSSS_MASK) #define ENET_SYST_NSEC_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_TSSS_MASK) >> ENET_SYST_NSEC_TSSS_SHIFT) /* Bitfield definition for register: SYST_SEC_UPD */ @@ -5298,6 +4206,17 @@ errors */ #define ENET_PPS_CTRL_TRGTMODSEL1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) #define ENET_PPS_CTRL_TRGTMODSEL1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) >> ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) +/* + * PPSEN1 (RW) + * + * Flexible PPS1 Output Mode Enable + * When set high, Bits[10:8] function as PPSCMD. + */ +#define ENET_PPS_CTRL_PPSEN1_MASK (0x1000U) +#define ENET_PPS_CTRL_PPSEN1_SHIFT (12U) +#define ENET_PPS_CTRL_PPSEN1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSEN1_SHIFT) & ENET_PPS_CTRL_PPSEN1_MASK) +#define ENET_PPS_CTRL_PPSEN1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN1_MASK) >> ENET_PPS_CTRL_PPSEN1_SHIFT) + /* * PPSCMD1 (RW) * @@ -5336,7 +4255,7 @@ errors */ #define ENET_PPS_CTRL_PPSEN0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN0_MASK) >> ENET_PPS_CTRL_PPSEN0_SHIFT) /* - * PPSCTRL0 (RW) + * PPSCTRLCMD0 (RW) * * PPSCTRL0: PPS0 Output Frequency Control * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: @@ -5345,32 +4264,60 @@ errors */ * - 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. * - 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... * - 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) + * PPSCMD0: Flexible PPS0 Output Control + * 0000: No Command + * 0001: START Single Pulse + * This command generates single pulse rising at the start point defined in + * Target Time Registers and of a duration defined + * in the PPS0 Width Register. + * 0010: START Pulse Train + * This command generates the train of pulses rising at the start point + * defined in the Target Time Registers and of a duration defined in the + * PPS0 Width Register and repeated at interval defined in the PPS + * Interval Register. By default, the PPS pulse train is free-running unless + * stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train + * immediately’ commands. + * 0011: Cancel START + * This command cancels the START Single Pulse and START Pulse Train + * commands if the system time has not crossed the programmed start + * time. + * 0100: STOP Pulse train at time + * This command stops the train of pulses initiated by the START Pulse + * Train command (PPSCMD = 0010) after the time programmed in the + * Target Time registers elapses. + * 0101: STOP Pulse Train immediately + * This command immediately stops the train of pulses initiated by the + * START Pulse Train command (PPSCMD = 0010). + * 0110: Cancel STOP Pulse train + * This command cancels the STOP pulse train at time command if the + * programmed stop time has not elapsed. The PPS pulse train becomes + * free-running on the successful execution of this command. + * 0111-1111: Reserved + * Note: These bits get cleared automatically */ -#define ENET_PPS_CTRL_PPSCTRL0_MASK (0xFU) -#define ENET_PPS_CTRL_PPSCTRL0_SHIFT (0U) -#define ENET_PPS_CTRL_PPSCTRL0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCTRL0_SHIFT) & ENET_PPS_CTRL_PPSCTRL0_MASK) -#define ENET_PPS_CTRL_PPSCTRL0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCTRL0_MASK) >> ENET_PPS_CTRL_PPSCTRL0_SHIFT) +#define ENET_PPS_CTRL_PPSCTRLCMD0_MASK (0xFU) +#define ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT (0U) +#define ENET_PPS_CTRL_PPSCTRLCMD0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) +#define ENET_PPS_CTRL_PPSCTRLCMD0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) >> ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) /* Bitfield definition for register: AUX_TS_NSEC */ /* - * AUXTSLO (RW) + * AUXTSLO (RO) * * Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. */ #define ENET_AUX_TS_NSEC_AUXTSLO_MASK (0x7FFFFFFFUL) #define ENET_AUX_TS_NSEC_AUXTSLO_SHIFT (0U) -#define ENET_AUX_TS_NSEC_AUXTSLO_SET(x) (((uint32_t)(x) << ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) #define ENET_AUX_TS_NSEC_AUXTSLO_GET(x) (((uint32_t)(x) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) >> ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) /* Bitfield definition for register: AUX_TS_SEC */ /* - * AUXTSHI (RW) + * AUXTSHI (RO) * * Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */ #define ENET_AUX_TS_SEC_AUXTSHI_MASK (0xFFFFFFFFUL) #define ENET_AUX_TS_SEC_AUXTSHI_SHIFT (0U) -#define ENET_AUX_TS_SEC_AUXTSHI_SET(x) (((uint32_t)(x) << ENET_AUX_TS_SEC_AUXTSHI_SHIFT) & ENET_AUX_TS_SEC_AUXTSHI_MASK) #define ENET_AUX_TS_SEC_AUXTSHI_GET(x) (((uint32_t)(x) & ENET_AUX_TS_SEC_AUXTSHI_MASK) >> ENET_AUX_TS_SEC_AUXTSHI_SHIFT) /* Bitfield definition for register: PPS0_INTERVAL */ @@ -6630,293 +5577,13 @@ errors */ #define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) #define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) -/* Bitfield definition for register: DMA_HW_FEATURE */ -/* - * ACTPHYIF (RW) - * - * Active or selected PHY interface - * When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. - * - 000: GMII or MII - * - 001: RGMII - * - 010: SGMII - * - 011: TBI - * - 100: RMII - * - 101: RTBI - * - 110: SMII - * - 111: RevMII - All Others: Reserved - */ -#define ENET_DMA_HW_FEATURE_ACTPHYIF_MASK (0x70000000UL) -#define ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT (28U) -#define ENET_DMA_HW_FEATURE_ACTPHYIF_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT) & ENET_DMA_HW_FEATURE_ACTPHYIF_MASK) -#define ENET_DMA_HW_FEATURE_ACTPHYIF_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ACTPHYIF_MASK) >> ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT) - -/* - * SAVLANINS (RW) - * - * Source Address or VLAN Insertion - */ -#define ENET_DMA_HW_FEATURE_SAVLANINS_MASK (0x8000000UL) -#define ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT (27U) -#define ENET_DMA_HW_FEATURE_SAVLANINS_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT) & ENET_DMA_HW_FEATURE_SAVLANINS_MASK) -#define ENET_DMA_HW_FEATURE_SAVLANINS_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_SAVLANINS_MASK) >> ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT) - -/* - * FLEXIPPSEN (RW) - * - * Flexible Pulse-Per-Second Output - */ -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK (0x4000000UL) -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT (26U) -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT) & ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK) -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK) >> ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT) - -/* - * INTTSEN (RW) - * - * Timestamping with Internal System Time - */ -#define ENET_DMA_HW_FEATURE_INTTSEN_MASK (0x2000000UL) -#define ENET_DMA_HW_FEATURE_INTTSEN_SHIFT (25U) -#define ENET_DMA_HW_FEATURE_INTTSEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_INTTSEN_SHIFT) & ENET_DMA_HW_FEATURE_INTTSEN_MASK) -#define ENET_DMA_HW_FEATURE_INTTSEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_INTTSEN_MASK) >> ENET_DMA_HW_FEATURE_INTTSEN_SHIFT) - -/* - * ENHDESSEL (RW) - * - * Alternate (Enhanced Descriptor) - */ -#define ENET_DMA_HW_FEATURE_ENHDESSEL_MASK (0x1000000UL) -#define ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT (24U) -#define ENET_DMA_HW_FEATURE_ENHDESSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT) & ENET_DMA_HW_FEATURE_ENHDESSEL_MASK) -#define ENET_DMA_HW_FEATURE_ENHDESSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ENHDESSEL_MASK) >> ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT) - -/* - * TXCHCNT (RW) - * - * Number of additional Tx Channels - */ -#define ENET_DMA_HW_FEATURE_TXCHCNT_MASK (0xC00000UL) -#define ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT (22U) -#define ENET_DMA_HW_FEATURE_TXCHCNT_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT) & ENET_DMA_HW_FEATURE_TXCHCNT_MASK) -#define ENET_DMA_HW_FEATURE_TXCHCNT_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TXCHCNT_MASK) >> ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT) - -/* - * RXCHCNT (RW) - * - * Number of additional Rx Channels - */ -#define ENET_DMA_HW_FEATURE_RXCHCNT_MASK (0x300000UL) -#define ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT (20U) -#define ENET_DMA_HW_FEATURE_RXCHCNT_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT) & ENET_DMA_HW_FEATURE_RXCHCNT_MASK) -#define ENET_DMA_HW_FEATURE_RXCHCNT_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXCHCNT_MASK) >> ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT) - -/* - * RXFIFOSIZE (RW) - * - * Rx FIFO > 2,048 Bytes - */ -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK (0x80000UL) -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT (19U) -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT) & ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK) -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK) >> ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT) - -/* - * RXTYP2COE (RW) - * - * IP Checksum Offload (Type 2) in Rx - */ -#define ENET_DMA_HW_FEATURE_RXTYP2COE_MASK (0x40000UL) -#define ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT (18U) -#define ENET_DMA_HW_FEATURE_RXTYP2COE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT) & ENET_DMA_HW_FEATURE_RXTYP2COE_MASK) -#define ENET_DMA_HW_FEATURE_RXTYP2COE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXTYP2COE_MASK) >> ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT) - -/* - * RXTYP1COE (RW) - * - * IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. - */ -#define ENET_DMA_HW_FEATURE_RXTYP1COE_MASK (0x20000UL) -#define ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT (17U) -#define ENET_DMA_HW_FEATURE_RXTYP1COE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT) & ENET_DMA_HW_FEATURE_RXTYP1COE_MASK) -#define ENET_DMA_HW_FEATURE_RXTYP1COE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXTYP1COE_MASK) >> ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT) - -/* - * TXCOESEL (RW) - * - * Checksum Offload in Tx - */ -#define ENET_DMA_HW_FEATURE_TXCOESEL_MASK (0x10000UL) -#define ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT (16U) -#define ENET_DMA_HW_FEATURE_TXCOESEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT) & ENET_DMA_HW_FEATURE_TXCOESEL_MASK) -#define ENET_DMA_HW_FEATURE_TXCOESEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TXCOESEL_MASK) >> ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT) - -/* - * AVSEL (RW) - * - * AV feature - */ -#define ENET_DMA_HW_FEATURE_AVSEL_MASK (0x8000U) -#define ENET_DMA_HW_FEATURE_AVSEL_SHIFT (15U) -#define ENET_DMA_HW_FEATURE_AVSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_AVSEL_SHIFT) & ENET_DMA_HW_FEATURE_AVSEL_MASK) -#define ENET_DMA_HW_FEATURE_AVSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_AVSEL_MASK) >> ENET_DMA_HW_FEATURE_AVSEL_SHIFT) - -/* - * EEESEL (RW) - * - * Energy Efficient Ethernet - */ -#define ENET_DMA_HW_FEATURE_EEESEL_MASK (0x4000U) -#define ENET_DMA_HW_FEATURE_EEESEL_SHIFT (14U) -#define ENET_DMA_HW_FEATURE_EEESEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_EEESEL_SHIFT) & ENET_DMA_HW_FEATURE_EEESEL_MASK) -#define ENET_DMA_HW_FEATURE_EEESEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_EEESEL_MASK) >> ENET_DMA_HW_FEATURE_EEESEL_SHIFT) - -/* - * TSVER2SEL (RW) - * - * IEEE 1588-2008 Advanced timestamp - */ -#define ENET_DMA_HW_FEATURE_TSVER2SEL_MASK (0x2000U) -#define ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT (13U) -#define ENET_DMA_HW_FEATURE_TSVER2SEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT) & ENET_DMA_HW_FEATURE_TSVER2SEL_MASK) -#define ENET_DMA_HW_FEATURE_TSVER2SEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TSVER2SEL_MASK) >> ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT) - -/* - * TSVER1SEL (RW) - * - * Only IEEE 1588-2002 timestamp - */ -#define ENET_DMA_HW_FEATURE_TSVER1SEL_MASK (0x1000U) -#define ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT (12U) -#define ENET_DMA_HW_FEATURE_TSVER1SEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT) & ENET_DMA_HW_FEATURE_TSVER1SEL_MASK) -#define ENET_DMA_HW_FEATURE_TSVER1SEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TSVER1SEL_MASK) >> ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT) - -/* - * MMCSEL (RW) - * - * RMON module - */ -#define ENET_DMA_HW_FEATURE_MMCSEL_MASK (0x800U) -#define ENET_DMA_HW_FEATURE_MMCSEL_SHIFT (11U) -#define ENET_DMA_HW_FEATURE_MMCSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MMCSEL_SHIFT) & ENET_DMA_HW_FEATURE_MMCSEL_MASK) -#define ENET_DMA_HW_FEATURE_MMCSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MMCSEL_MASK) >> ENET_DMA_HW_FEATURE_MMCSEL_SHIFT) - -/* - * MGKSEL (RW) - * - * PMT magic packet - */ -#define ENET_DMA_HW_FEATURE_MGKSEL_MASK (0x400U) -#define ENET_DMA_HW_FEATURE_MGKSEL_SHIFT (10U) -#define ENET_DMA_HW_FEATURE_MGKSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MGKSEL_SHIFT) & ENET_DMA_HW_FEATURE_MGKSEL_MASK) -#define ENET_DMA_HW_FEATURE_MGKSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MGKSEL_MASK) >> ENET_DMA_HW_FEATURE_MGKSEL_SHIFT) - -/* - * RWKSEL (RW) - * - * PMT remote wake-up frame - */ -#define ENET_DMA_HW_FEATURE_RWKSEL_MASK (0x200U) -#define ENET_DMA_HW_FEATURE_RWKSEL_SHIFT (9U) -#define ENET_DMA_HW_FEATURE_RWKSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RWKSEL_SHIFT) & ENET_DMA_HW_FEATURE_RWKSEL_MASK) -#define ENET_DMA_HW_FEATURE_RWKSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RWKSEL_MASK) >> ENET_DMA_HW_FEATURE_RWKSEL_SHIFT) - -/* - * SMASEL (RW) - * - * SMA (MDIO) Interface - */ -#define ENET_DMA_HW_FEATURE_SMASEL_MASK (0x100U) -#define ENET_DMA_HW_FEATURE_SMASEL_SHIFT (8U) -#define ENET_DMA_HW_FEATURE_SMASEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_SMASEL_SHIFT) & ENET_DMA_HW_FEATURE_SMASEL_MASK) -#define ENET_DMA_HW_FEATURE_SMASEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_SMASEL_MASK) >> ENET_DMA_HW_FEATURE_SMASEL_SHIFT) - -/* - * L3L4FLTREN (RW) - * - * Layer 3 and Layer 4 feature - */ -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK (0x80U) -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT (7U) -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT) & ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK) -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK) >> ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT) - -/* - * PCSSEL (RW) - * - * PCS registers (TBI, SGMII, or RTBI PHY interface) - */ -#define ENET_DMA_HW_FEATURE_PCSSEL_MASK (0x40U) -#define ENET_DMA_HW_FEATURE_PCSSEL_SHIFT (6U) -#define ENET_DMA_HW_FEATURE_PCSSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_PCSSEL_SHIFT) & ENET_DMA_HW_FEATURE_PCSSEL_MASK) -#define ENET_DMA_HW_FEATURE_PCSSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_PCSSEL_MASK) >> ENET_DMA_HW_FEATURE_PCSSEL_SHIFT) - -/* - * ADDMACADRSEL (RW) - * - * Multiple MAC Address registers - */ -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK (0x20U) -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT (5U) -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT) & ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK) -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK) >> ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT) - -/* - * HASHSEL (RW) - * - * HASH filter - */ -#define ENET_DMA_HW_FEATURE_HASHSEL_MASK (0x10U) -#define ENET_DMA_HW_FEATURE_HASHSEL_SHIFT (4U) -#define ENET_DMA_HW_FEATURE_HASHSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_HASHSEL_SHIFT) & ENET_DMA_HW_FEATURE_HASHSEL_MASK) -#define ENET_DMA_HW_FEATURE_HASHSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_HASHSEL_MASK) >> ENET_DMA_HW_FEATURE_HASHSEL_SHIFT) - -/* - * EXTHASHEN (RW) - * - * Expanded DA Hash filter - */ -#define ENET_DMA_HW_FEATURE_EXTHASHEN_MASK (0x8U) -#define ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT (3U) -#define ENET_DMA_HW_FEATURE_EXTHASHEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT) & ENET_DMA_HW_FEATURE_EXTHASHEN_MASK) -#define ENET_DMA_HW_FEATURE_EXTHASHEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_EXTHASHEN_MASK) >> ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT) - -/* - * HDSEL (RW) - * - * Half-duplex support - */ -#define ENET_DMA_HW_FEATURE_HDSEL_MASK (0x4U) -#define ENET_DMA_HW_FEATURE_HDSEL_SHIFT (2U) -#define ENET_DMA_HW_FEATURE_HDSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_HDSEL_SHIFT) & ENET_DMA_HW_FEATURE_HDSEL_MASK) -#define ENET_DMA_HW_FEATURE_HDSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_HDSEL_MASK) >> ENET_DMA_HW_FEATURE_HDSEL_SHIFT) - -/* - * GMIISEL (RW) - * - * 1000 Mbps support - */ -#define ENET_DMA_HW_FEATURE_GMIISEL_MASK (0x2U) -#define ENET_DMA_HW_FEATURE_GMIISEL_SHIFT (1U) -#define ENET_DMA_HW_FEATURE_GMIISEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_GMIISEL_SHIFT) & ENET_DMA_HW_FEATURE_GMIISEL_MASK) -#define ENET_DMA_HW_FEATURE_GMIISEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_GMIISEL_MASK) >> ENET_DMA_HW_FEATURE_GMIISEL_SHIFT) - -/* - * MIISEL (RW) - * - * 10 or 100 Mbps support - */ -#define ENET_DMA_HW_FEATURE_MIISEL_MASK (0x1U) -#define ENET_DMA_HW_FEATURE_MIISEL_SHIFT (0U) -#define ENET_DMA_HW_FEATURE_MIISEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MIISEL_SHIFT) & ENET_DMA_HW_FEATURE_MIISEL_MASK) -#define ENET_DMA_HW_FEATURE_MIISEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MIISEL_MASK) >> ENET_DMA_HW_FEATURE_MIISEL_SHIFT) - /* Bitfield definition for register: CTRL0 */ /* * ENET0_RXCLK_DLY_SEL (RW) * */ -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3E0U) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (5U) +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3F00U) +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (8U) #define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) #define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) @@ -6924,24 +5591,27 @@ errors */ * ENET0_TXCLK_DLY_SEL (RW) * */ -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x1FU) +#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x3FU) #define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U) #define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) #define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) /* Bitfield definition for register: CTRL2 */ /* - * ENET0_IRQ_EN (RW) + * ENET0_LPI_IRQ_EN (RW) * + * lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt */ -#define ENET_CTRL2_ENET0_IRQ_EN_MASK (0xF8000000UL) -#define ENET_CTRL2_ENET0_IRQ_EN_SHIFT (27U) -#define ENET_CTRL2_ENET0_IRQ_EN_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_IRQ_EN_SHIFT) & ENET_CTRL2_ENET0_IRQ_EN_MASK) -#define ENET_CTRL2_ENET0_IRQ_EN_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_IRQ_EN_MASK) >> ENET_CTRL2_ENET0_IRQ_EN_SHIFT) +#define ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL) +#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U) +#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) +#define ENET_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) /* * ENET0_REFCLK_OE (RW) * + * set to enable output 50MHz clock to rmii phy. + * User should set it if use soc internal clock as refclk */ #define ENET_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) #define ENET_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) @@ -6951,6 +5621,9 @@ errors */ /* * ENET0_PHY_INF_SEL (RW) * + * PHY mode select + * 000MII; 001RGMII; 100RMII; + * should be set before config IOMUX, otherwise may cause glitch for RGMII */ #define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK (0xE000U) #define ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT (13U) @@ -6960,6 +5633,7 @@ errors */ /* * ENET0_FLOWCTRL (RW) * + * flow control request */ #define ENET_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) #define ENET_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) @@ -6969,6 +5643,10 @@ errors */ /* * ENET0_RMII_TXCLK_SEL (RW) * + * RMII mode output clock pad select + * set to use txck as RMII refclk; + * clr to use rxck as RMII refclk; default 0(rxck) + * refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. */ #define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) #define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) @@ -6985,19 +5663,6 @@ errors */ /* L3_L4_CFG register group index macro definition */ #define ENET_L3_L4_CFG_0 (0UL) -#define ENET_L3_L4_CFG_1 (1UL) -#define ENET_L3_L4_CFG_2 (2UL) -#define ENET_L3_L4_CFG_3 (3UL) - -/* HASH_TABLE register group index macro definition */ -#define ENET_HASH_TABLE_REGISTER0 (0UL) -#define ENET_HASH_TABLE_REGISTER1 (1UL) -#define ENET_HASH_TABLE_REGISTER2 (2UL) -#define ENET_HASH_TABLE_REGISTER3 (3UL) -#define ENET_HASH_TABLE_REGISTER4 (4UL) -#define ENET_HASH_TABLE_REGISTER5 (5UL) -#define ENET_HASH_TABLE_REGISTER6 (6UL) -#define ENET_HASH_TABLE_REGISTER7 (7UL) /* PPS register group index macro definition */ #define ENET_PPS_1 (0UL) @@ -7005,4 +5670,4 @@ errors */ #define ENET_PPS_3 (2UL) -#endif /* HPM_ENET_H */ \ No newline at end of file +#endif /* HPM_ENET_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h index 024cffc5c0..e598888422 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -308,4 +308,4 @@ typedef struct { #define EXIP_RGN_3 (3UL) -#endif /* HPM_EXIP_H */ \ No newline at end of file +#endif /* HPM_EXIP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_femc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_femc_regs.h new file mode 100644 index 0000000000..01e193c4c4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_femc_regs.h @@ -0,0 +1,981 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_FEMC_H +#define HPM_FEMC_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __RW uint32_t IOCTRL; /* 0x4: IO Mux Control Register */ + __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ + __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ + __RW uint32_t BR[7]; /* 0x10 - 0x28: Base Register 0 (for SDRAM CS0 device) */ + __R uint8_t RESERVED0[12]; /* 0x2C - 0x37: Reserved */ + __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ + __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ + __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ + __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ + __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ + __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ + __R uint8_t RESERVED1[32]; /* 0x50 - 0x6F: Reserved */ + __RW uint32_t SRCTRL0; /* 0x70: SRAM control register 0 */ + __RW uint32_t SRCTRL1; /* 0x74: SRAM control register 1 */ + __R uint8_t RESERVED2[24]; /* 0x78 - 0x8F: Reserved */ + __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ + __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ + __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ + __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ + __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ + __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ + __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ + __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ + __R uint32_t STAT0; /* 0xC0: Status Register 0 */ + __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ + __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ +} FEMC_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * BTO (RW) + * + * Bus timeout cycles + * AXI Bus timeout cycle is as following (255*(2^BTO)): + * 00000b - 255*1 + * 00001-11110b - 255*2 - 255*2^30 + * 11111b - 255*2^31 + */ +#define FEMC_CTRL_BTO_MASK (0x1F000000UL) +#define FEMC_CTRL_BTO_SHIFT (24U) +#define FEMC_CTRL_BTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_BTO_SHIFT) & FEMC_CTRL_BTO_MASK) +#define FEMC_CTRL_BTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_BTO_MASK) >> FEMC_CTRL_BTO_SHIFT) + +/* + * CTO (RW) + * + * Command Execution timeout cycles + * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is + * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is + * CTO*1024 cycle. + */ +#define FEMC_CTRL_CTO_MASK (0xFF0000UL) +#define FEMC_CTRL_CTO_SHIFT (16U) +#define FEMC_CTRL_CTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_CTO_SHIFT) & FEMC_CTRL_CTO_MASK) +#define FEMC_CTRL_CTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_CTO_MASK) >> FEMC_CTRL_CTO_SHIFT) + +/* + * DQS (RW) + * + * DQS (read strobe) mode + * 0b - Dummy read strobe loopbacked internally + * 1b - Dummy read strobe loopbacked from DQS pad + */ +#define FEMC_CTRL_DQS_MASK (0x4U) +#define FEMC_CTRL_DQS_SHIFT (2U) +#define FEMC_CTRL_DQS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DQS_SHIFT) & FEMC_CTRL_DQS_MASK) +#define FEMC_CTRL_DQS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DQS_MASK) >> FEMC_CTRL_DQS_SHIFT) + +/* + * DIS (RW) + * + * Module Disable + * 0b - Module enabled + * 1b - Module disabled + */ +#define FEMC_CTRL_DIS_MASK (0x2U) +#define FEMC_CTRL_DIS_SHIFT (1U) +#define FEMC_CTRL_DIS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DIS_SHIFT) & FEMC_CTRL_DIS_MASK) +#define FEMC_CTRL_DIS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DIS_MASK) >> FEMC_CTRL_DIS_SHIFT) + +/* + * RST (RW) + * + * Software Reset + * Reset all internal logic in SEMC except configuration register + */ +#define FEMC_CTRL_RST_MASK (0x1U) +#define FEMC_CTRL_RST_SHIFT (0U) +#define FEMC_CTRL_RST_SET(x) (((uint32_t)(x) << FEMC_CTRL_RST_SHIFT) & FEMC_CTRL_RST_MASK) +#define FEMC_CTRL_RST_GET(x) (((uint32_t)(x) & FEMC_CTRL_RST_MASK) >> FEMC_CTRL_RST_SHIFT) + +/* Bitfield definition for register: IOCTRL */ +/* + * IO_CSX (RW) + * + * IO_CSX output selection + * 0001b - SDRAM CS1 + * 0110b - SRAM CE# + */ +#define FEMC_IOCTRL_IO_CSX_MASK (0xF0U) +#define FEMC_IOCTRL_IO_CSX_SHIFT (4U) +#define FEMC_IOCTRL_IO_CSX_SET(x) (((uint32_t)(x) << FEMC_IOCTRL_IO_CSX_SHIFT) & FEMC_IOCTRL_IO_CSX_MASK) +#define FEMC_IOCTRL_IO_CSX_GET(x) (((uint32_t)(x) & FEMC_IOCTRL_IO_CSX_MASK) >> FEMC_IOCTRL_IO_CSX_SHIFT) + +/* Bitfield definition for register: BMW0 */ +/* + * RWS (RW) + * + * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is + * same as current executing command with read/write operation switch. + */ +#define FEMC_BMW0_RWS_MASK (0xFF0000UL) +#define FEMC_BMW0_RWS_SHIFT (16U) +#define FEMC_BMW0_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW0_RWS_SHIFT) & FEMC_BMW0_RWS_MASK) +#define FEMC_BMW0_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW0_RWS_MASK) >> FEMC_BMW0_RWS_SHIFT) + +/* + * SH (RW) + * + * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is + * same as current executing command without read/write operation switch. + */ +#define FEMC_BMW0_SH_MASK (0xFF00U) +#define FEMC_BMW0_SH_SHIFT (8U) +#define FEMC_BMW0_SH_SET(x) (((uint32_t)(x) << FEMC_BMW0_SH_SHIFT) & FEMC_BMW0_SH_MASK) +#define FEMC_BMW0_SH_GET(x) (((uint32_t)(x) & FEMC_BMW0_SH_MASK) >> FEMC_BMW0_SH_SHIFT) + +/* + * AGE (RW) + * + * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is + * multiplied by WAGE to get weight score. + */ +#define FEMC_BMW0_AGE_MASK (0xF0U) +#define FEMC_BMW0_AGE_SHIFT (4U) +#define FEMC_BMW0_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW0_AGE_SHIFT) & FEMC_BMW0_AGE_MASK) +#define FEMC_BMW0_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW0_AGE_MASK) >> FEMC_BMW0_AGE_SHIFT) + +/* + * QOS (RW) + * + * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator + * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS + * is multiplied by WQOS to get weight score. + */ +#define FEMC_BMW0_QOS_MASK (0xFU) +#define FEMC_BMW0_QOS_SHIFT (0U) +#define FEMC_BMW0_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW0_QOS_SHIFT) & FEMC_BMW0_QOS_MASK) +#define FEMC_BMW0_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW0_QOS_MASK) >> FEMC_BMW0_QOS_SHIFT) + +/* Bitfield definition for register: BMW1 */ +/* + * BR (RW) + * + * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current + * executing command. + */ +#define FEMC_BMW1_BR_MASK (0xFF000000UL) +#define FEMC_BMW1_BR_SHIFT (24U) +#define FEMC_BMW1_BR_SET(x) (((uint32_t)(x) << FEMC_BMW1_BR_SHIFT) & FEMC_BMW1_BR_MASK) +#define FEMC_BMW1_BR_GET(x) (((uint32_t)(x) & FEMC_BMW1_BR_MASK) >> FEMC_BMW1_BR_SHIFT) + +/* + * RWS (RW) + * + * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is + * same as current executing command with read/write operation switch. + */ +#define FEMC_BMW1_RWS_MASK (0xFF0000UL) +#define FEMC_BMW1_RWS_SHIFT (16U) +#define FEMC_BMW1_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW1_RWS_SHIFT) & FEMC_BMW1_RWS_MASK) +#define FEMC_BMW1_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW1_RWS_MASK) >> FEMC_BMW1_RWS_SHIFT) + +/* + * PH (RW) + * + * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is + * same as current executing command without read/write operation switch. + */ +#define FEMC_BMW1_PH_MASK (0xFF00U) +#define FEMC_BMW1_PH_SHIFT (8U) +#define FEMC_BMW1_PH_SET(x) (((uint32_t)(x) << FEMC_BMW1_PH_SHIFT) & FEMC_BMW1_PH_MASK) +#define FEMC_BMW1_PH_GET(x) (((uint32_t)(x) & FEMC_BMW1_PH_MASK) >> FEMC_BMW1_PH_SHIFT) + +/* + * AGE (RW) + * + * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is + * multiplied by WAGE to get weight score. + */ +#define FEMC_BMW1_AGE_MASK (0xF0U) +#define FEMC_BMW1_AGE_SHIFT (4U) +#define FEMC_BMW1_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW1_AGE_SHIFT) & FEMC_BMW1_AGE_MASK) +#define FEMC_BMW1_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW1_AGE_MASK) >> FEMC_BMW1_AGE_SHIFT) + +/* + * QOS (RW) + * + * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator + * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS + * is multiplied by WQOS to get weight score. + */ +#define FEMC_BMW1_QOS_MASK (0xFU) +#define FEMC_BMW1_QOS_SHIFT (0U) +#define FEMC_BMW1_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW1_QOS_SHIFT) & FEMC_BMW1_QOS_MASK) +#define FEMC_BMW1_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW1_QOS_MASK) >> FEMC_BMW1_QOS_SHIFT) + +/* Bitfield definition for register array: BR */ +/* + * BASE (RW) + * + * Base Address + * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low + * position 12 bits are all zero. + */ +#define FEMC_BR_BASE_MASK (0xFFFFF000UL) +#define FEMC_BR_BASE_SHIFT (12U) +#define FEMC_BR_BASE_SET(x) (((uint32_t)(x) << FEMC_BR_BASE_SHIFT) & FEMC_BR_BASE_MASK) +#define FEMC_BR_BASE_GET(x) (((uint32_t)(x) & FEMC_BR_BASE_MASK) >> FEMC_BR_BASE_SHIFT) + +/* + * SIZE (RW) + * + * Memory size + * 00000b - 4KB + * 00001b - 8KB + * 00010b - 16KB + * 00011b - 32KB + * 00100b - 64KB + * 00101b - 128KB + * 00110b - 256KB + * 00111b - 512KB + * 01000b - 1MB + * 01001b - 2MB + * 01010b - 4MB + * 01011b - 8MB + * 01100b - 16MB + * 01101b - 32MB + * 01110b - 64MB + * 01111b - 128MB + * 10000b - 256MB + * 10001b - 512MB + * 10010b - 1GB + * 10011b - 2GB + * 10100-11111b - 4GB + */ +#define FEMC_BR_SIZE_MASK (0x3EU) +#define FEMC_BR_SIZE_SHIFT (1U) +#define FEMC_BR_SIZE_SET(x) (((uint32_t)(x) << FEMC_BR_SIZE_SHIFT) & FEMC_BR_SIZE_MASK) +#define FEMC_BR_SIZE_GET(x) (((uint32_t)(x) & FEMC_BR_SIZE_MASK) >> FEMC_BR_SIZE_SHIFT) + +/* + * VLD (RW) + * + * Valid + */ +#define FEMC_BR_VLD_MASK (0x1U) +#define FEMC_BR_VLD_SHIFT (0U) +#define FEMC_BR_VLD_SET(x) (((uint32_t)(x) << FEMC_BR_VLD_SHIFT) & FEMC_BR_VLD_MASK) +#define FEMC_BR_VLD_GET(x) (((uint32_t)(x) & FEMC_BR_VLD_MASK) >> FEMC_BR_VLD_SHIFT) + +/* Bitfield definition for register: INTEN */ +/* + * AXIBUSERR (RW) + * + * AXI BUS error interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define FEMC_INTEN_AXIBUSERR_MASK (0x8U) +#define FEMC_INTEN_AXIBUSERR_SHIFT (3U) +#define FEMC_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXIBUSERR_SHIFT) & FEMC_INTEN_AXIBUSERR_MASK) +#define FEMC_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXIBUSERR_MASK) >> FEMC_INTEN_AXIBUSERR_SHIFT) + +/* + * AXICMDERR (RW) + * + * AXI command error interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define FEMC_INTEN_AXICMDERR_MASK (0x4U) +#define FEMC_INTEN_AXICMDERR_SHIFT (2U) +#define FEMC_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXICMDERR_SHIFT) & FEMC_INTEN_AXICMDERR_MASK) +#define FEMC_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXICMDERR_MASK) >> FEMC_INTEN_AXICMDERR_SHIFT) + +/* + * IPCMDERR (RW) + * + * IP command error interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define FEMC_INTEN_IPCMDERR_MASK (0x2U) +#define FEMC_INTEN_IPCMDERR_SHIFT (1U) +#define FEMC_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDERR_SHIFT) & FEMC_INTEN_IPCMDERR_MASK) +#define FEMC_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDERR_MASK) >> FEMC_INTEN_IPCMDERR_SHIFT) + +/* + * IPCMDDONE (RW) + * + * IP command done interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define FEMC_INTEN_IPCMDDONE_MASK (0x1U) +#define FEMC_INTEN_IPCMDDONE_SHIFT (0U) +#define FEMC_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDDONE_SHIFT) & FEMC_INTEN_IPCMDDONE_MASK) +#define FEMC_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDDONE_MASK) >> FEMC_INTEN_IPCMDDONE_SHIFT) + +/* Bitfield definition for register: INTR */ +/* + * AXIBUSERR (W1C) + * + * AXI bus error interrupt + * AXI Bus error interrupt is generated in following cases: + * • AXI address is invalid + * • AXI 8-bit or 16-bit WRAP write/read + */ +#define FEMC_INTR_AXIBUSERR_MASK (0x8U) +#define FEMC_INTR_AXIBUSERR_SHIFT (3U) +#define FEMC_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXIBUSERR_SHIFT) & FEMC_INTR_AXIBUSERR_MASK) +#define FEMC_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXIBUSERR_MASK) >> FEMC_INTR_AXIBUSERR_SHIFT) + +/* + * AXICMDERR (W1C) + * + * AXI command error interrupt + * AXI command error interrupt is generated when AXI command execution timeout. + */ +#define FEMC_INTR_AXICMDERR_MASK (0x4U) +#define FEMC_INTR_AXICMDERR_SHIFT (2U) +#define FEMC_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXICMDERR_SHIFT) & FEMC_INTR_AXICMDERR_MASK) +#define FEMC_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXICMDERR_MASK) >> FEMC_INTR_AXICMDERR_SHIFT) + +/* + * IPCMDERR (W1C) + * + * IP command error done interrupt + * IP command error interrupt is generated in following case: + * • IP Command Address target invalid device space + * • IP Command Code unsupported + * • IP Command triggered when previous command + */ +#define FEMC_INTR_IPCMDERR_MASK (0x2U) +#define FEMC_INTR_IPCMDERR_SHIFT (1U) +#define FEMC_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDERR_SHIFT) & FEMC_INTR_IPCMDERR_MASK) +#define FEMC_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDERR_MASK) >> FEMC_INTR_IPCMDERR_SHIFT) + +/* + * IPCMDDONE (W1C) + * + * IP command normal done interrupt + */ +#define FEMC_INTR_IPCMDDONE_MASK (0x1U) +#define FEMC_INTR_IPCMDDONE_SHIFT (0U) +#define FEMC_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDDONE_SHIFT) & FEMC_INTR_IPCMDDONE_MASK) +#define FEMC_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDDONE_MASK) >> FEMC_INTR_IPCMDDONE_SHIFT) + +/* Bitfield definition for register: SDRCTRL0 */ +/* + * BANK2 (RW) + * + * 2 Bank selection bit + * 0b - SDRAM device has 4 banks. + * 1b - SDRAM device has 2 banks. + */ +#define FEMC_SDRCTRL0_BANK2_MASK (0x4000U) +#define FEMC_SDRCTRL0_BANK2_SHIFT (14U) +#define FEMC_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BANK2_SHIFT) & FEMC_SDRCTRL0_BANK2_MASK) +#define FEMC_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BANK2_MASK) >> FEMC_SDRCTRL0_BANK2_SHIFT) + +/* + * CAS (RW) + * + * CAS Latency + * 00b - 1 + * 01b - 1 + * 10b - 2 + * 11b - 3 + */ +#define FEMC_SDRCTRL0_CAS_MASK (0xC00U) +#define FEMC_SDRCTRL0_CAS_SHIFT (10U) +#define FEMC_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_CAS_SHIFT) & FEMC_SDRCTRL0_CAS_MASK) +#define FEMC_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_CAS_MASK) >> FEMC_SDRCTRL0_CAS_SHIFT) + +/* + * COL (RW) + * + * Column address bit number + * 00b - 12 bit + * 01b - 11 bit + * 10b - 10 bit + * 11b - 9 bit + */ +#define FEMC_SDRCTRL0_COL_MASK (0x300U) +#define FEMC_SDRCTRL0_COL_SHIFT (8U) +#define FEMC_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL_SHIFT) & FEMC_SDRCTRL0_COL_MASK) +#define FEMC_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL_MASK) >> FEMC_SDRCTRL0_COL_SHIFT) + +/* + * COL8 (RW) + * + * Column 8 selection bit + * 0b - Column address bit number is decided by COL field. + * 1b - Column address bit number is 8. COL field is ignored. + */ +#define FEMC_SDRCTRL0_COL8_MASK (0x80U) +#define FEMC_SDRCTRL0_COL8_SHIFT (7U) +#define FEMC_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL8_SHIFT) & FEMC_SDRCTRL0_COL8_MASK) +#define FEMC_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL8_MASK) >> FEMC_SDRCTRL0_COL8_SHIFT) + +/* + * BURSTLEN (RW) + * + * Burst Length + * 000b - 1 + * 001b - 2 + * 010b - 4 + * 011b - 8 + * 100b - 8 + * 101b - 8 + * 110b - 8 + * 111b - 8 + */ +#define FEMC_SDRCTRL0_BURSTLEN_MASK (0x70U) +#define FEMC_SDRCTRL0_BURSTLEN_SHIFT (4U) +#define FEMC_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BURSTLEN_SHIFT) & FEMC_SDRCTRL0_BURSTLEN_MASK) +#define FEMC_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BURSTLEN_MASK) >> FEMC_SDRCTRL0_BURSTLEN_SHIFT) + +/* + * HIGHBAND (RW) + * + * high band select + * 0: use data[15:0] for 16bit SDRAM; + * 1: use data[31:16] for 16bit SDRAM; + * only used when Port Size is 16bit(PORTSZ=01b) + */ +#define FEMC_SDRCTRL0_HIGHBAND_MASK (0x8U) +#define FEMC_SDRCTRL0_HIGHBAND_SHIFT (3U) +#define FEMC_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_HIGHBAND_SHIFT) & FEMC_SDRCTRL0_HIGHBAND_MASK) +#define FEMC_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_HIGHBAND_MASK) >> FEMC_SDRCTRL0_HIGHBAND_SHIFT) + +/* + * PORTSZ (RW) + * + * Port Size + * 00b - 8bit + * 01b - 16bit + * 10b - 32bit + */ +#define FEMC_SDRCTRL0_PORTSZ_MASK (0x3U) +#define FEMC_SDRCTRL0_PORTSZ_SHIFT (0U) +#define FEMC_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_PORTSZ_SHIFT) & FEMC_SDRCTRL0_PORTSZ_MASK) +#define FEMC_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_PORTSZ_MASK) >> FEMC_SDRCTRL0_PORTSZ_SHIFT) + +/* Bitfield definition for register: SDRCTRL1 */ +/* + * ACT2PRE (RW) + * + * ACT to Precharge minimum time + * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. + */ +#define FEMC_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) +#define FEMC_SDRCTRL1_ACT2PRE_SHIFT (20U) +#define FEMC_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2PRE_SHIFT) & FEMC_SDRCTRL1_ACT2PRE_MASK) +#define FEMC_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2PRE_MASK) >> FEMC_SDRCTRL1_ACT2PRE_SHIFT) + +/* + * CKEOFF (RW) + * + * CKE OFF minimum time + * It is promised clock suspend last at leat CKEOFF+1 clock cycles. + */ +#define FEMC_SDRCTRL1_CKEOFF_MASK (0xF0000UL) +#define FEMC_SDRCTRL1_CKEOFF_SHIFT (16U) +#define FEMC_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_CKEOFF_SHIFT) & FEMC_SDRCTRL1_CKEOFF_MASK) +#define FEMC_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_CKEOFF_MASK) >> FEMC_SDRCTRL1_CKEOFF_SHIFT) + +/* + * WRC (RW) + * + * Write recovery time + * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. + */ +#define FEMC_SDRCTRL1_WRC_MASK (0xE000U) +#define FEMC_SDRCTRL1_WRC_SHIFT (13U) +#define FEMC_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_WRC_SHIFT) & FEMC_SDRCTRL1_WRC_MASK) +#define FEMC_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_WRC_MASK) >> FEMC_SDRCTRL1_WRC_SHIFT) + +/* + * RFRC (RW) + * + * Refresh recovery time + * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. + */ +#define FEMC_SDRCTRL1_RFRC_MASK (0x1F00U) +#define FEMC_SDRCTRL1_RFRC_SHIFT (8U) +#define FEMC_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_RFRC_SHIFT) & FEMC_SDRCTRL1_RFRC_MASK) +#define FEMC_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_RFRC_MASK) >> FEMC_SDRCTRL1_RFRC_SHIFT) + +/* + * ACT2RW (RW) + * + * ACT to Read/Write wait time + * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. + */ +#define FEMC_SDRCTRL1_ACT2RW_MASK (0xF0U) +#define FEMC_SDRCTRL1_ACT2RW_SHIFT (4U) +#define FEMC_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2RW_SHIFT) & FEMC_SDRCTRL1_ACT2RW_MASK) +#define FEMC_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2RW_MASK) >> FEMC_SDRCTRL1_ACT2RW_SHIFT) + +/* + * PRE2ACT (RW) + * + * PRECHARGE to ACT/Refresh wait time + * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. + */ +#define FEMC_SDRCTRL1_PRE2ACT_MASK (0xFU) +#define FEMC_SDRCTRL1_PRE2ACT_SHIFT (0U) +#define FEMC_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_PRE2ACT_SHIFT) & FEMC_SDRCTRL1_PRE2ACT_MASK) +#define FEMC_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_PRE2ACT_MASK) >> FEMC_SDRCTRL1_PRE2ACT_SHIFT) + +/* Bitfield definition for register: SDRCTRL2 */ +/* + * ITO (RW) + * + * SDRAM Idle timeout + * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is + * considered idle when there is no AXI Bus transfer and no SDRAM command pending. + * 00000000b - IDLE timeout period is 256*Prescale period. + * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. + */ +#define FEMC_SDRCTRL2_ITO_MASK (0xFF000000UL) +#define FEMC_SDRCTRL2_ITO_SHIFT (24U) +#define FEMC_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ITO_SHIFT) & FEMC_SDRCTRL2_ITO_MASK) +#define FEMC_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ITO_MASK) >> FEMC_SDRCTRL2_ITO_SHIFT) + +/* + * ACT2ACT (RW) + * + * ACT to ACT wait time + * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This + * could help to meet tRRD timing requirement by SDRAM device. + */ +#define FEMC_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) +#define FEMC_SDRCTRL2_ACT2ACT_SHIFT (16U) +#define FEMC_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ACT2ACT_SHIFT) & FEMC_SDRCTRL2_ACT2ACT_MASK) +#define FEMC_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ACT2ACT_MASK) >> FEMC_SDRCTRL2_ACT2ACT_SHIFT) + +/* + * REF2REF (RW) + * + * Refresh to Refresh wait time + * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. + * This could help to meet tRFC timing requirement by SDRAM device. + */ +#define FEMC_SDRCTRL2_REF2REF_MASK (0xFF00U) +#define FEMC_SDRCTRL2_REF2REF_SHIFT (8U) +#define FEMC_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_REF2REF_SHIFT) & FEMC_SDRCTRL2_REF2REF_MASK) +#define FEMC_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_REF2REF_MASK) >> FEMC_SDRCTRL2_REF2REF_SHIFT) + +/* + * SRRC (RW) + * + * Self Refresh Recovery time + * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. + */ +#define FEMC_SDRCTRL2_SRRC_MASK (0xFFU) +#define FEMC_SDRCTRL2_SRRC_SHIFT (0U) +#define FEMC_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_SRRC_SHIFT) & FEMC_SDRCTRL2_SRRC_MASK) +#define FEMC_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_SRRC_MASK) >> FEMC_SDRCTRL2_SRRC_SHIFT) + +/* Bitfield definition for register: SDRCTRL3 */ +/* + * UT (RW) + * + * Refresh urgent threshold + * Internal refresh request is generated on every Refresh period. Before internal request timer count up to + * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh + * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. + * When internal request timer count up to this urgent threshold, refresh request is considered as urgent + * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP + * command to SDRAM device. + * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as + * urgent refresh request. + * Refresh urgent threshold is as follwoing: + * 00000000b - 256*Prescaler period + * 00000001-11111111b - UT*Prescaler period + */ +#define FEMC_SDRCTRL3_UT_MASK (0xFF000000UL) +#define FEMC_SDRCTRL3_UT_SHIFT (24U) +#define FEMC_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_UT_SHIFT) & FEMC_SDRCTRL3_UT_MASK) +#define FEMC_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_UT_MASK) >> FEMC_SDRCTRL3_UT_SHIFT) + +/* + * RT (RW) + * + * Refresh timer period + * Refresh timer period is as following: + * 00000000b - 256*Prescaler period + * 00000001-11111111b - RT*Prescaler period + */ +#define FEMC_SDRCTRL3_RT_MASK (0xFF0000UL) +#define FEMC_SDRCTRL3_RT_SHIFT (16U) +#define FEMC_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_RT_SHIFT) & FEMC_SDRCTRL3_RT_MASK) +#define FEMC_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_RT_MASK) >> FEMC_SDRCTRL3_RT_SHIFT) + +/* + * PRESCALE (RW) + * + * Prescaler timer period + * Prescaler timer period is as following: + * 00000000b - 256*16 clock cycles + * 00000001-11111111b - PRESCALE*16 clock cycles + */ +#define FEMC_SDRCTRL3_PRESCALE_MASK (0xFF00U) +#define FEMC_SDRCTRL3_PRESCALE_SHIFT (8U) +#define FEMC_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_PRESCALE_SHIFT) & FEMC_SDRCTRL3_PRESCALE_MASK) +#define FEMC_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_PRESCALE_MASK) >> FEMC_SDRCTRL3_PRESCALE_SHIFT) + +/* + * REBL (RW) + * + * Refresh burst length + * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The + * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. + * 000b - 1 + * 001b - 2 + * 010b - 3 + * 011b - 4 + * 100b - 5 + * 101b - 6 + * 110b - 7 + * 111b - 8 + */ +#define FEMC_SDRCTRL3_REBL_MASK (0xEU) +#define FEMC_SDRCTRL3_REBL_SHIFT (1U) +#define FEMC_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REBL_SHIFT) & FEMC_SDRCTRL3_REBL_MASK) +#define FEMC_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REBL_MASK) >> FEMC_SDRCTRL3_REBL_SHIFT) + +/* + * REN (RW) + * + * Refresh enable + */ +#define FEMC_SDRCTRL3_REN_MASK (0x1U) +#define FEMC_SDRCTRL3_REN_SHIFT (0U) +#define FEMC_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REN_SHIFT) & FEMC_SDRCTRL3_REN_MASK) +#define FEMC_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REN_MASK) >> FEMC_SDRCTRL3_REN_SHIFT) + +/* Bitfield definition for register: SRCTRL0 */ +/* + * ADVH (RW) + * + * ADV hold state + * 0b - ADV is high during address hold state + * 1b - ADV is low during address hold state + */ +#define FEMC_SRCTRL0_ADVH_MASK (0x800U) +#define FEMC_SRCTRL0_ADVH_SHIFT (11U) +#define FEMC_SRCTRL0_ADVH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVH_SHIFT) & FEMC_SRCTRL0_ADVH_MASK) +#define FEMC_SRCTRL0_ADVH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVH_MASK) >> FEMC_SRCTRL0_ADVH_SHIFT) + +/* + * ADVP (RW) + * + * ADV polarity + * 0b - ADV is active low + * 1b - ADV is active high + */ +#define FEMC_SRCTRL0_ADVP_MASK (0x400U) +#define FEMC_SRCTRL0_ADVP_SHIFT (10U) +#define FEMC_SRCTRL0_ADVP_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVP_SHIFT) & FEMC_SRCTRL0_ADVP_MASK) +#define FEMC_SRCTRL0_ADVP_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVP_MASK) >> FEMC_SRCTRL0_ADVP_SHIFT) + +/* + * ADM (RW) + * + * address data mode + * 00b - address and data MUX mode + * 11b - address and data non-MUX mode + */ +#define FEMC_SRCTRL0_ADM_MASK (0x300U) +#define FEMC_SRCTRL0_ADM_SHIFT (8U) +#define FEMC_SRCTRL0_ADM_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADM_SHIFT) & FEMC_SRCTRL0_ADM_MASK) +#define FEMC_SRCTRL0_ADM_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADM_MASK) >> FEMC_SRCTRL0_ADM_SHIFT) + +/* + * PORTSZ (RW) + * + * port size + * 0b - 8bit + * 1b - 16bit + */ +#define FEMC_SRCTRL0_PORTSZ_MASK (0x1U) +#define FEMC_SRCTRL0_PORTSZ_SHIFT (0U) +#define FEMC_SRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_PORTSZ_SHIFT) & FEMC_SRCTRL0_PORTSZ_MASK) +#define FEMC_SRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_PORTSZ_MASK) >> FEMC_SRCTRL0_PORTSZ_SHIFT) + +/* Bitfield definition for register: SRCTRL1 */ +/* + * OEH (RW) + * + * OE high time, is OEH+1 clock cycles + */ +#define FEMC_SRCTRL1_OEH_MASK (0xF0000000UL) +#define FEMC_SRCTRL1_OEH_SHIFT (28U) +#define FEMC_SRCTRL1_OEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEH_SHIFT) & FEMC_SRCTRL1_OEH_MASK) +#define FEMC_SRCTRL1_OEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEH_MASK) >> FEMC_SRCTRL1_OEH_SHIFT) + +/* + * OEL (RW) + * + * OE low time, is OEL+1 clock cycles + */ +#define FEMC_SRCTRL1_OEL_MASK (0xF000000UL) +#define FEMC_SRCTRL1_OEL_SHIFT (24U) +#define FEMC_SRCTRL1_OEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEL_SHIFT) & FEMC_SRCTRL1_OEL_MASK) +#define FEMC_SRCTRL1_OEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEL_MASK) >> FEMC_SRCTRL1_OEL_SHIFT) + +/* + * WEH (RW) + * + * WE high time, is WEH+1 clock cycles + */ +#define FEMC_SRCTRL1_WEH_MASK (0xF00000UL) +#define FEMC_SRCTRL1_WEH_SHIFT (20U) +#define FEMC_SRCTRL1_WEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEH_SHIFT) & FEMC_SRCTRL1_WEH_MASK) +#define FEMC_SRCTRL1_WEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEH_MASK) >> FEMC_SRCTRL1_WEH_SHIFT) + +/* + * WEL (RW) + * + * WE low time, is WEL+1 clock cycles + */ +#define FEMC_SRCTRL1_WEL_MASK (0xF0000UL) +#define FEMC_SRCTRL1_WEL_SHIFT (16U) +#define FEMC_SRCTRL1_WEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEL_SHIFT) & FEMC_SRCTRL1_WEL_MASK) +#define FEMC_SRCTRL1_WEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEL_MASK) >> FEMC_SRCTRL1_WEL_SHIFT) + +/* + * AH (RW) + * + * Address hold time, is AH+1 clock cycles + */ +#define FEMC_SRCTRL1_AH_MASK (0xF000U) +#define FEMC_SRCTRL1_AH_SHIFT (12U) +#define FEMC_SRCTRL1_AH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AH_SHIFT) & FEMC_SRCTRL1_AH_MASK) +#define FEMC_SRCTRL1_AH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AH_MASK) >> FEMC_SRCTRL1_AH_SHIFT) + +/* + * AS (RW) + * + * Address setup time, is AS+1 clock cycles + */ +#define FEMC_SRCTRL1_AS_MASK (0xF00U) +#define FEMC_SRCTRL1_AS_SHIFT (8U) +#define FEMC_SRCTRL1_AS_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AS_SHIFT) & FEMC_SRCTRL1_AS_MASK) +#define FEMC_SRCTRL1_AS_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AS_MASK) >> FEMC_SRCTRL1_AS_SHIFT) + +/* + * CEH (RW) + * + * Chip enable hold time, is CEH+1 clock cycles + */ +#define FEMC_SRCTRL1_CEH_MASK (0xF0U) +#define FEMC_SRCTRL1_CEH_SHIFT (4U) +#define FEMC_SRCTRL1_CEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CEH_SHIFT) & FEMC_SRCTRL1_CEH_MASK) +#define FEMC_SRCTRL1_CEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CEH_MASK) >> FEMC_SRCTRL1_CEH_SHIFT) + +/* + * CES (RW) + * + * Chip enable setup time, is CES+1 clock cycles + */ +#define FEMC_SRCTRL1_CES_MASK (0xFU) +#define FEMC_SRCTRL1_CES_SHIFT (0U) +#define FEMC_SRCTRL1_CES_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CES_SHIFT) & FEMC_SRCTRL1_CES_MASK) +#define FEMC_SRCTRL1_CES_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CES_MASK) >> FEMC_SRCTRL1_CES_SHIFT) + +/* Bitfield definition for register: SADDR */ +/* + * SA (RW) + * + * Slave address + */ +#define FEMC_SADDR_SA_MASK (0xFFFFFFFFUL) +#define FEMC_SADDR_SA_SHIFT (0U) +#define FEMC_SADDR_SA_SET(x) (((uint32_t)(x) << FEMC_SADDR_SA_SHIFT) & FEMC_SADDR_SA_MASK) +#define FEMC_SADDR_SA_GET(x) (((uint32_t)(x) & FEMC_SADDR_SA_MASK) >> FEMC_SADDR_SA_SHIFT) + +/* Bitfield definition for register: DATSZ */ +/* + * DATSZ (RW) + * + * Data Size in Byte + * When IP command is not a write/read operation, DATSZ field would be ignored. + * 000b - 4 + * 001b - 1 + * 010b - 2 + * 011b - 3 + * 100b - 4 + * 101b - 4 + * 110b - 4 + * 111b - 4 + */ +#define FEMC_DATSZ_DATSZ_MASK (0x7U) +#define FEMC_DATSZ_DATSZ_SHIFT (0U) +#define FEMC_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << FEMC_DATSZ_DATSZ_SHIFT) & FEMC_DATSZ_DATSZ_MASK) +#define FEMC_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & FEMC_DATSZ_DATSZ_MASK) >> FEMC_DATSZ_DATSZ_SHIFT) + +/* Bitfield definition for register: BYTEMSK */ +/* + * BM3 (RW) + * + * Byte Mask for Byte 3 (IPTXD bit 31:24) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define FEMC_BYTEMSK_BM3_MASK (0x8U) +#define FEMC_BYTEMSK_BM3_SHIFT (3U) +#define FEMC_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM3_SHIFT) & FEMC_BYTEMSK_BM3_MASK) +#define FEMC_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM3_MASK) >> FEMC_BYTEMSK_BM3_SHIFT) + +/* + * BM2 (RW) + * + * Byte Mask for Byte 2 (IPTXD bit 23:16) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define FEMC_BYTEMSK_BM2_MASK (0x4U) +#define FEMC_BYTEMSK_BM2_SHIFT (2U) +#define FEMC_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM2_SHIFT) & FEMC_BYTEMSK_BM2_MASK) +#define FEMC_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM2_MASK) >> FEMC_BYTEMSK_BM2_SHIFT) + +/* + * BM1 (RW) + * + * Byte Mask for Byte 1 (IPTXD bit 15:8) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define FEMC_BYTEMSK_BM1_MASK (0x2U) +#define FEMC_BYTEMSK_BM1_SHIFT (1U) +#define FEMC_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM1_SHIFT) & FEMC_BYTEMSK_BM1_MASK) +#define FEMC_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM1_MASK) >> FEMC_BYTEMSK_BM1_SHIFT) + +/* + * BM0 (RW) + * + * Byte Mask for Byte 0 (IPTXD bit 7:0) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define FEMC_BYTEMSK_BM0_MASK (0x1U) +#define FEMC_BYTEMSK_BM0_SHIFT (0U) +#define FEMC_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM0_SHIFT) & FEMC_BYTEMSK_BM0_MASK) +#define FEMC_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM0_MASK) >> FEMC_BYTEMSK_BM0_SHIFT) + +/* Bitfield definition for register: IPCMD */ +/* + * KEY (WO) + * + * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory + * device is selected by BRx settings and IPCR0 registers. + */ +#define FEMC_IPCMD_KEY_MASK (0xFFFF0000UL) +#define FEMC_IPCMD_KEY_SHIFT (16U) +#define FEMC_IPCMD_KEY_SET(x) (((uint32_t)(x) << FEMC_IPCMD_KEY_SHIFT) & FEMC_IPCMD_KEY_MASK) +#define FEMC_IPCMD_KEY_GET(x) (((uint32_t)(x) & FEMC_IPCMD_KEY_MASK) >> FEMC_IPCMD_KEY_SHIFT) + +/* + * CMD (RW) + * + * SDRAM Commands: + * • 0x8: READ + * • 0x9: WRITE + * • 0xA: MODESET + * • 0xB: ACTIVE + * • 0xC: AUTO REFRESH + * • 0xD: SELF REFRESH + * • 0xE: PRECHARGE + * • 0xF: PRECHARGE ALL + * • Others: RSVD + * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. + */ +#define FEMC_IPCMD_CMD_MASK (0xFFFFU) +#define FEMC_IPCMD_CMD_SHIFT (0U) +#define FEMC_IPCMD_CMD_SET(x) (((uint32_t)(x) << FEMC_IPCMD_CMD_SHIFT) & FEMC_IPCMD_CMD_MASK) +#define FEMC_IPCMD_CMD_GET(x) (((uint32_t)(x) & FEMC_IPCMD_CMD_MASK) >> FEMC_IPCMD_CMD_SHIFT) + +/* Bitfield definition for register: IPTX */ +/* + * DAT (RW) + * + * Data + */ +#define FEMC_IPTX_DAT_MASK (0xFFFFFFFFUL) +#define FEMC_IPTX_DAT_SHIFT (0U) +#define FEMC_IPTX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPTX_DAT_SHIFT) & FEMC_IPTX_DAT_MASK) +#define FEMC_IPTX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPTX_DAT_MASK) >> FEMC_IPTX_DAT_SHIFT) + +/* Bitfield definition for register: IPRX */ +/* + * DAT (RW) + * + * Data + */ +#define FEMC_IPRX_DAT_MASK (0xFFFFFFFFUL) +#define FEMC_IPRX_DAT_SHIFT (0U) +#define FEMC_IPRX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPRX_DAT_SHIFT) & FEMC_IPRX_DAT_MASK) +#define FEMC_IPRX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPRX_DAT_MASK) >> FEMC_IPRX_DAT_SHIFT) + +/* Bitfield definition for register: STAT0 */ +/* + * IDLE (RO) + * + * Indicating whether it is in IDLE state. + * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no + * pending device access. + */ +#define FEMC_STAT0_IDLE_MASK (0x1U) +#define FEMC_STAT0_IDLE_SHIFT (0U) +#define FEMC_STAT0_IDLE_GET(x) (((uint32_t)(x) & FEMC_STAT0_IDLE_MASK) >> FEMC_STAT0_IDLE_SHIFT) + +/* Bitfield definition for register: DLYCFG */ +/* + * OE (RW) + * + * delay clock output enable, should be set after setting DLYEN and DLYSEL + */ +#define FEMC_DLYCFG_OE_MASK (0x2000U) +#define FEMC_DLYCFG_OE_SHIFT (13U) +#define FEMC_DLYCFG_OE_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_OE_SHIFT) & FEMC_DLYCFG_OE_MASK) +#define FEMC_DLYCFG_OE_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_OE_MASK) >> FEMC_DLYCFG_OE_SHIFT) + +/* + * DLYSEL (RW) + * + * delay line select, 0 for 1 cell, 31 for all 32 cells + */ +#define FEMC_DLYCFG_DLYSEL_MASK (0x3EU) +#define FEMC_DLYCFG_DLYSEL_SHIFT (1U) +#define FEMC_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYSEL_SHIFT) & FEMC_DLYCFG_DLYSEL_MASK) +#define FEMC_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYSEL_MASK) >> FEMC_DLYCFG_DLYSEL_SHIFT) + +/* + * DLYEN (RW) + * + * delay line enable + */ +#define FEMC_DLYCFG_DLYEN_MASK (0x1U) +#define FEMC_DLYCFG_DLYEN_SHIFT (0U) +#define FEMC_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYEN_SHIFT) & FEMC_DLYCFG_DLYEN_MASK) +#define FEMC_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYEN_MASK) >> FEMC_DLYCFG_DLYEN_SHIFT) + + + +/* BR register group index macro definition */ +#define FEMC_BR_BASE0 (0UL) +#define FEMC_BR_BASE1 (1UL) +#define FEMC_BR_BASE6 (6UL) + + +#endif /* HPM_FEMC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h index 8c7bca3438..29781c6641 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -71,7 +71,7 @@ typedef struct { /* Bitfield definition for register: STATUS */ /* - * FIR_OV (ROI) + * FIR_OV (RO) * * FIR Overflow err */ @@ -80,7 +80,7 @@ typedef struct { #define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) /* - * FFT_OV (ROI) + * FFT_OV (RO) * * FFT Overflow Err */ @@ -89,7 +89,7 @@ typedef struct { #define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) /* - * WR_ERR (ROI) + * WR_ERR (RO) * * AXI Data Write Error */ @@ -98,7 +98,7 @@ typedef struct { #define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) /* - * RD_NXT_ERR (ROI) + * RD_NXT_ERR (RO) * * AXI Read Bus Error for NXT DATA */ @@ -107,7 +107,7 @@ typedef struct { #define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) /* - * RD_ERR (ROI) + * RD_ERR (RO) * * AXI Data Read Error */ @@ -116,7 +116,7 @@ typedef struct { #define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) /* - * NXT_CMD_RD_DONE (ROI) + * NXT_CMD_RD_DONE (RO) * * Indicate that next command sequence is already read into the module. */ @@ -125,7 +125,7 @@ typedef struct { #define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) /* - * OP_CMD_DONE (ROI) + * OP_CMD_DONE (RO) * * Indicate that operation cmd is done, and data are available in system memory. */ @@ -330,7 +330,7 @@ typedef struct { /* * FIR_COEF_TAPS (RW) * - * Length of FIR coefs + * Length of FIR coefs （max 256） */ #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK (0x3FFFU) #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT (0U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h index 59783d253b..a6ac8a1756 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,10 +11,8 @@ typedef struct { struct { - __RW uint32_t VALUE; /* 0x0: GPIO input value */ - __RW uint32_t SET; /* 0x4: GPIO input set */ - __RW uint32_t CLEAR; /* 0x8: GPIO input clear */ - __RW uint32_t TOGGLE; /* 0xC: GPIO input toggle */ + __R uint32_t VALUE; /* 0x0: GPIO input value */ + __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ } DI[16]; struct { __RW uint32_t VALUE; /* 0x100: GPIO output value */ @@ -30,9 +28,7 @@ typedef struct { } OE[16]; struct { __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ - __RW uint32_t SET; /* 0x304: GPIO interrupt flag set */ - __RW uint32_t CLEAR; /* 0x308: GPIO interrupt flag clear */ - __RW uint32_t TOGGLE; /* 0x30C: GPIO interrupt flag toggle */ + __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ } IF[16]; struct { __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ @@ -63,7 +59,7 @@ typedef struct { /* Bitfield definition for register of struct array DI: VALUE */ /* - * INPUT (RW) + * INPUT (RO) * * GPIO input bus value, each bit represents a bus bit * 0: low level presents on chip pin @@ -71,48 +67,8 @@ typedef struct { */ #define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) #define GPIO_DI_VALUE_INPUT_SHIFT (0U) -#define GPIO_DI_VALUE_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_VALUE_INPUT_SHIFT) & GPIO_DI_VALUE_INPUT_MASK) #define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) -/* Bitfield definition for register of struct array DI: SET */ -/* - * INPUT (RW) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_SET_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_SET_INPUT_SHIFT (0U) -#define GPIO_DI_SET_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_SET_INPUT_SHIFT) & GPIO_DI_SET_INPUT_MASK) -#define GPIO_DI_SET_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_SET_INPUT_MASK) >> GPIO_DI_SET_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DI: CLEAR */ -/* - * INPUT (RW) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_CLEAR_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_CLEAR_INPUT_SHIFT (0U) -#define GPIO_DI_CLEAR_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_CLEAR_INPUT_SHIFT) & GPIO_DI_CLEAR_INPUT_MASK) -#define GPIO_DI_CLEAR_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_CLEAR_INPUT_MASK) >> GPIO_DI_CLEAR_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DI: TOGGLE */ -/* - * INPUT (RW) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_TOGGLE_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_TOGGLE_INPUT_SHIFT (0U) -#define GPIO_DI_TOGGLE_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_TOGGLE_INPUT_SHIFT) & GPIO_DI_TOGGLE_INPUT_MASK) -#define GPIO_DI_TOGGLE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_TOGGLE_INPUT_MASK) >> GPIO_DI_TOGGLE_INPUT_SHIFT) - /* Bitfield definition for register of struct array DO: VALUE */ /* * OUTPUT (RW) @@ -230,45 +186,6 @@ typedef struct { #define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) #define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) -/* Bitfield definition for register of struct array IF: SET */ -/* - * IRQ_FLAG (RW) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_SET_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_SET_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_SET_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_SET_IRQ_FLAG_SHIFT) & GPIO_IF_SET_IRQ_FLAG_MASK) -#define GPIO_IF_SET_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_SET_IRQ_FLAG_MASK) >> GPIO_IF_SET_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IF: CLEAR */ -/* - * IRQ_FLAG (RW) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_CLEAR_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_CLEAR_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_CLEAR_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_CLEAR_IRQ_FLAG_SHIFT) & GPIO_IF_CLEAR_IRQ_FLAG_MASK) -#define GPIO_IF_CLEAR_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_CLEAR_IRQ_FLAG_MASK) >> GPIO_IF_CLEAR_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IF: TOGGLE */ -/* - * IRQ_FLAG (RW) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_TOGGLE_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_TOGGLE_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_TOGGLE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_TOGGLE_IRQ_FLAG_SHIFT) & GPIO_IF_TOGGLE_IRQ_FLAG_MASK) -#define GPIO_IF_TOGGLE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_TOGGLE_IRQ_FLAG_MASK) >> GPIO_IF_TOGGLE_IRQ_FLAG_SHIFT) - /* Bitfield definition for register of struct array IE: VALUE */ /* * IRQ_EN (RW) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h index 52f5c93478..366b24ec64 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -42,6 +42,43 @@ typedef struct { #define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) #define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) +/* + * OPMODE (RW) + * + * 0: round mode + * 1: one-shot mode, timer will stopped at reload point. + * NOTE: reload irq will be always set at one-shot mode at end + */ +#define GPTMR_CHANNEL_CR_OPMODE_MASK (0x20000UL) +#define GPTMR_CHANNEL_CR_OPMODE_SHIFT (17U) +#define GPTMR_CHANNEL_CR_OPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_OPMODE_SHIFT) & GPTMR_CHANNEL_CR_OPMODE_MASK) +#define GPTMR_CHANNEL_CR_OPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_OPMODE_MASK) >> GPTMR_CHANNEL_CR_OPMODE_SHIFT) + +/* + * MONITOR_SEL (RW) + * + * set to monitor input signal high level time(chan_meas_high) + * clr to monitor input signal period(chan_meas_prd) + */ +#define GPTMR_CHANNEL_CR_MONITOR_SEL_MASK (0x10000UL) +#define GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT (16U) +#define GPTMR_CHANNEL_CR_MONITOR_SEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) +#define GPTMR_CHANNEL_CR_MONITOR_SEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) >> GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) + +/* + * MONITOR_EN (RW) + * + * set to monitor input signal period or high level time. + * When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts + * * only can be used when trig_mode is selected as measure mode(100) + * * the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. + * if no posedge after reload for more than val_1, will also assert irq_capt + */ +#define GPTMR_CHANNEL_CR_MONITOR_EN_MASK (0x8000U) +#define GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT (15U) +#define GPTMR_CHANNEL_CR_MONITOR_EN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) +#define GPTMR_CHANNEL_CR_MONITOR_EN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) >> GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) + /* * CNTRST (RW) * @@ -120,10 +157,10 @@ typedef struct { * DMASEL (RW) * * select one of DMA request: - * 00- RLD flag, counter reload; - * 01- Input signal toggle captured - * 10- CMP0 flag - * 11- CMP1 flag + * 00- CMP0 flag + * 01- CMP1 flag + * 10- Input signal toggle captured + * 11- RLD flag, counter reload; */ #define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) #define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) @@ -181,10 +218,10 @@ typedef struct { * * compare value 0 */ -#define GPTMR_CMP_CMP_MASK (0xFFFFFFFFUL) -#define GPTMR_CMP_CMP_SHIFT (0U) -#define GPTMR_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CMP_CMP_SHIFT) & GPTMR_CMP_CMP_MASK) -#define GPTMR_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CMP_CMP_MASK) >> GPTMR_CMP_CMP_SHIFT) +#define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) +#define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) +#define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) /* Bitfield definition for register of struct array CHANNEL: RLD */ /* @@ -604,4 +641,4 @@ typedef struct { #define GPTMR_CHANNEL_CH3 (3UL) -#endif /* HPM_GPTMR_H */ \ No newline at end of file +#endif /* HPM_GPTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h index 52dae76c15..bf7d13dcc7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -585,4 +585,4 @@ typedef struct { #define HALL_HIS_W (2UL) -#endif /* HPM_HALL_H */ \ No newline at end of file +#endif /* HPM_HALL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h index 639abf4261..f351b91b36 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -336,6 +336,51 @@ typedef struct { #define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) /* Bitfield definition for register: CTRL */ +/* + * DATACNT_HIGH (RW) + * + * Data counts in bytes. + * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. + * Slave: the meaning of DataCnt depends on the DMA mode: + * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. + * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + */ +#define I2C_CTRL_DATACNT_HIGH_MASK (0xFF000000UL) +#define I2C_CTRL_DATACNT_HIGH_SHIFT (24U) +#define I2C_CTRL_DATACNT_HIGH_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_HIGH_SHIFT) & I2C_CTRL_DATACNT_HIGH_MASK) +#define I2C_CTRL_DATACNT_HIGH_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_HIGH_MASK) >> I2C_CTRL_DATACNT_HIGH_SHIFT) + +/* + * RESET_LEN (RW) + * + * reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. + */ +#define I2C_CTRL_RESET_LEN_MASK (0xF00000UL) +#define I2C_CTRL_RESET_LEN_SHIFT (20U) +#define I2C_CTRL_RESET_LEN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_LEN_SHIFT) & I2C_CTRL_RESET_LEN_MASK) +#define I2C_CTRL_RESET_LEN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_LEN_MASK) >> I2C_CTRL_RESET_LEN_SHIFT) + +/* + * RESET_HOLD_SCKIN (RW) + * + * set to hold input clock to high when reset is active + */ +#define I2C_CTRL_RESET_HOLD_SCKIN_MASK (0x4000U) +#define I2C_CTRL_RESET_HOLD_SCKIN_SHIFT (14U) +#define I2C_CTRL_RESET_HOLD_SCKIN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) +#define I2C_CTRL_RESET_HOLD_SCKIN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) >> I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) + +/* + * RESET_ON (RW) + * + * set to send reset signals(just toggle clock bus defined by reset_len). + * this register is clered when reset is end, can't be cleared by software + */ +#define I2C_CTRL_RESET_ON_MASK (0x2000U) +#define I2C_CTRL_RESET_ON_SHIFT (13U) +#define I2C_CTRL_RESET_ON_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_ON_SHIFT) & I2C_CTRL_RESET_ON_MASK) +#define I2C_CTRL_RESET_ON_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_ON_MASK) >> I2C_CTRL_RESET_ON_SHIFT) + /* * PHASE_START (RW) * @@ -400,7 +445,7 @@ typedef struct { * DATACNT (RW) * * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. + * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. * Slave: the meaning of DataCnt depends on the DMA mode: * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. @@ -554,4 +599,4 @@ typedef struct { -#endif /* HPM_I2C_H */ \ No newline at end of file +#endif /* HPM_I2C_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h index 7a64f7857a..51414306bc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -449,11 +449,12 @@ typedef struct { /* * CH_MAX (RW) * - * CH_MAX[3:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. + * CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. * It must be an even number, so CH_MAX[0] is always 0. - * 4'h2: 2 channels - * 4'h4: 4 channels + * 5'h2: 2 channels + * 5'h4: 4 channels * ... + * 5‘h10: 16 channels (max) */ #define I2S_CFGR_CH_MAX_MASK (0x7C0U) #define I2S_CFGR_CH_MAX_SHIFT (6U) diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h index b7bf305c6f..223ab85e1d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -591,7 +591,7 @@ typedef struct { /* Bitfield definition for register: STAT */ /* - * BUSY (ROI) + * BUSY (RO) * * When 1 means that the module is busy doing conversion and data transfer. */ @@ -600,7 +600,7 @@ typedef struct { #define JPEG_STAT_BUSY_GET(x) (((uint32_t)(x) & JPEG_STAT_BUSY_MASK) >> JPEG_STAT_BUSY_SHIFT) /* - * AXI_ERR_ID (ROI) + * AXI_ERR_ID (RO) * * the axi err id */ @@ -609,7 +609,7 @@ typedef struct { #define JPEG_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_ID_MASK) >> JPEG_STAT_AXI_ERR_ID_SHIFT) /* - * AXI_READ_ERR (ROI) + * AXI_READ_ERR (RO) * * in-dma axi bus error */ @@ -618,7 +618,7 @@ typedef struct { #define JPEG_STAT_AXI_READ_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_READ_ERR_MASK) >> JPEG_STAT_AXI_READ_ERR_SHIFT) /* - * AXI_WRITE_ERR (ROI) + * AXI_WRITE_ERR (RO) * * out-dma axi bus error */ @@ -750,7 +750,7 @@ typedef struct { /* Bitfield definition for register: OUTDMACNT */ /* - * VAL (ROI) + * VAL (RO) * * The out DMA counter */ @@ -1092,4 +1092,4 @@ typedef struct { #define JPEG_IMGREG_REG43 (3UL) -#endif /* HPM_JPEG_H */ \ No newline at end of file +#endif /* HPM_JPEG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h index c935fdb66f..94369e6c42 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -261,4 +261,4 @@ typedef struct { #define KEYM_SOFTPKEY_SPK7 (7UL) -#endif /* HPM_KEYM_H */ \ No newline at end of file +#endif /* HPM_KEYM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h index a257d2cf53..f700ed7eaa 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -261,4 +261,4 @@ typedef struct { #define KEYMAN_SOFTPKEY_SPK7 (7UL) -#endif /* HPM_KEYMAN_H */ \ No newline at end of file +#endif /* HPM_KEYMAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h index d6c0a4ea1d..f1bc84ab10 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -16,10 +16,19 @@ typedef struct { __RW uint32_t HSYNC_PARA; /* 0xC: HSYNC Config Register */ __RW uint32_t VSYNC_PARA; /* 0x10: VSYNC Config Register */ __W uint32_t DMA_ST; /* 0x14: DMA Status Register */ - __W uint32_t ST; /* 0x18: Status Register */ + __RW uint32_t ST; /* 0x18: Status Register */ __RW uint32_t INT_EN; /* 0x1C: Interrupt Enable Register */ __RW uint32_t TXFIFO; /* 0x20: TX FIFO Register */ - __R uint8_t RESERVED0[476]; /* 0x24 - 0x1FF: Reserved */ + __RW uint32_t CTRL_BP_V_RANGE; /* 0x24: BP_V range for CAMSYNC mode */ + __RW uint32_t CTRL_PW_V_RANGE; /* 0x28: PW_V range for CAMSYNC mode */ + __RW uint32_t CTRL_FP_V_RANGE; /* 0x2C: FP_V range for CAMSYNC mode */ + __RW uint32_t CAM_SYNC_HCNT_MIN; /* 0x30: min HCNT value for CAMSYNC mode */ + __RW uint32_t CAM_SYNC_HCNT_BEST; /* 0x34: best HCNT value for CAMSYNC mode */ + __RW uint32_t CAM_SYNC_HCNT_MAX; /* 0x38: max HCNT value for CAMSYNC mode */ + __R uint32_t CAM_SYNC_HCNT_ST; /* 0x3C: current HCNT value for CAMSYNC mode */ + __R uint32_t SHADOW_DONE_ST; /* 0x40: Shadow done status */ + __RW uint32_t SHADOW_DONE_INT_EN; /* 0x44: Shadow done interrupt enable */ + __R uint8_t RESERVED0[440]; /* 0x48 - 0x1FF: Reserved */ struct { __RW uint32_t LAYCTRL; /* 0x200: Layer Control Register */ __RW uint32_t ALPHAS; /* 0x204: Layer Alpha Register */ @@ -122,6 +131,64 @@ typedef struct { #define LCDC_CTRL_ARQOS_SET(x) (((uint32_t)(x) << LCDC_CTRL_ARQOS_SHIFT) & LCDC_CTRL_ARQOS_MASK) #define LCDC_CTRL_ARQOS_GET(x) (((uint32_t)(x) & LCDC_CTRL_ARQOS_MASK) >> LCDC_CTRL_ARQOS_SHIFT) +/* + * SHADOW_OP (RW) + * + * Shadow Option + * 1: Use physical VSYNC (ST[VS_BLANK]) as shadow time. + * 0: Use layer internal logic VSYNC as shadow time. In general, this type of shadow control will have longer memory read time, so less underflow risk. + */ +#define LCDC_CTRL_SHADOW_OP_MASK (0x20000UL) +#define LCDC_CTRL_SHADOW_OP_SHIFT (17U) +#define LCDC_CTRL_SHADOW_OP_SET(x) (((uint32_t)(x) << LCDC_CTRL_SHADOW_OP_SHIFT) & LCDC_CTRL_SHADOW_OP_MASK) +#define LCDC_CTRL_SHADOW_OP_GET(x) (((uint32_t)(x) & LCDC_CTRL_SHADOW_OP_MASK) >> LCDC_CTRL_SHADOW_OP_SHIFT) + +/* + * B_LE_MODE (RW) + * + * Endianess mode for Blue Color Pads + * 1: Little endian. Pad 0 --> Color LSB 0 + * 0: Big Endian. Pad 0--> Color MSB 7 + */ +#define LCDC_CTRL_B_LE_MODE_MASK (0x10000UL) +#define LCDC_CTRL_B_LE_MODE_SHIFT (16U) +#define LCDC_CTRL_B_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_B_LE_MODE_SHIFT) & LCDC_CTRL_B_LE_MODE_MASK) +#define LCDC_CTRL_B_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_B_LE_MODE_MASK) >> LCDC_CTRL_B_LE_MODE_SHIFT) + +/* + * G_LE_MODE (RW) + * + * Endianess mode for Green Color Pads + * 1: Little endian. Pad 0 --> Color LSB 0 + * 0: Big Endian. Pad 0--> Color MSB 7 + */ +#define LCDC_CTRL_G_LE_MODE_MASK (0x8000U) +#define LCDC_CTRL_G_LE_MODE_SHIFT (15U) +#define LCDC_CTRL_G_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_G_LE_MODE_SHIFT) & LCDC_CTRL_G_LE_MODE_MASK) +#define LCDC_CTRL_G_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_G_LE_MODE_MASK) >> LCDC_CTRL_G_LE_MODE_SHIFT) + +/* + * R_LE_MODE (RW) + * + * Endianess mode for Red Color Pads + * 1: Little endian. Pad 0 --> Color LSB 0 + * 0: Big Endian. Pad 0--> Color MSB 7 + */ +#define LCDC_CTRL_R_LE_MODE_MASK (0x4000U) +#define LCDC_CTRL_R_LE_MODE_SHIFT (14U) +#define LCDC_CTRL_R_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_R_LE_MODE_SHIFT) & LCDC_CTRL_R_LE_MODE_MASK) +#define LCDC_CTRL_R_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_R_LE_MODE_MASK) >> LCDC_CTRL_R_LE_MODE_SHIFT) + +/* + * CAM_SYNC_EN (RW) + * + * Enable the VSYNC synchronization of CAM and LCDC + */ +#define LCDC_CTRL_CAM_SYNC_EN_MASK (0x2000U) +#define LCDC_CTRL_CAM_SYNC_EN_SHIFT (13U) +#define LCDC_CTRL_CAM_SYNC_EN_SET(x) (((uint32_t)(x) << LCDC_CTRL_CAM_SYNC_EN_SHIFT) & LCDC_CTRL_CAM_SYNC_EN_MASK) +#define LCDC_CTRL_CAM_SYNC_EN_GET(x) (((uint32_t)(x) & LCDC_CTRL_CAM_SYNC_EN_MASK) >> LCDC_CTRL_CAM_SYNC_EN_SHIFT) + /* * INV_PXDATA (RW) * @@ -328,6 +395,55 @@ typedef struct { #define LCDC_DMA_ST_DMA0_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA0_DONE_MASK) >> LCDC_DMA_ST_DMA0_DONE_SHIFT) /* Bitfield definition for register: ST */ +/* + * P1_HANDSHAKE_ABORT (W1C) + * + * Plane 1 handshake abort error. W1C + */ +#define LCDC_ST_P1_HANDSHAKE_ABORT_MASK (0x100U) +#define LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT (8U) +#define LCDC_ST_P1_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT) & LCDC_ST_P1_HANDSHAKE_ABORT_MASK) +#define LCDC_ST_P1_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_ST_P1_HANDSHAKE_ABORT_MASK) >> LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT) + +/* + * P0_HANDSHAKE_ABORT (W1C) + * + * Plane 0 handshake abort error. W1C + */ +#define LCDC_ST_P0_HANDSHAKE_ABORT_MASK (0x80U) +#define LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT (7U) +#define LCDC_ST_P0_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT) & LCDC_ST_P0_HANDSHAKE_ABORT_MASK) +#define LCDC_ST_P0_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_ST_P0_HANDSHAKE_ABORT_MASK) >> LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT) + +/* + * CAM_HCNT_FAIL (W1C) + * + * During cam_vsync mode, sync fail due to hcnt out of acceptable ranges. W1C + */ +#define LCDC_ST_CAM_HCNT_FAIL_MASK (0x40U) +#define LCDC_ST_CAM_HCNT_FAIL_SHIFT (6U) +#define LCDC_ST_CAM_HCNT_FAIL_SET(x) (((uint32_t)(x) << LCDC_ST_CAM_HCNT_FAIL_SHIFT) & LCDC_ST_CAM_HCNT_FAIL_MASK) +#define LCDC_ST_CAM_HCNT_FAIL_GET(x) (((uint32_t)(x) & LCDC_ST_CAM_HCNT_FAIL_MASK) >> LCDC_ST_CAM_HCNT_FAIL_SHIFT) + +/* + * CAM_VSYNC_FAIL (W1C) + * + * During cam_vsync mode, sync fail due to out of vsync parameters. W1C + */ +#define LCDC_ST_CAM_VSYNC_FAIL_MASK (0x20U) +#define LCDC_ST_CAM_VSYNC_FAIL_SHIFT (5U) +#define LCDC_ST_CAM_VSYNC_FAIL_SET(x) (((uint32_t)(x) << LCDC_ST_CAM_VSYNC_FAIL_SHIFT) & LCDC_ST_CAM_VSYNC_FAIL_MASK) +#define LCDC_ST_CAM_VSYNC_FAIL_GET(x) (((uint32_t)(x) & LCDC_ST_CAM_VSYNC_FAIL_MASK) >> LCDC_ST_CAM_VSYNC_FAIL_SHIFT) + +/* + * SHADOW_DONE (RO) + * + * Shadow done status. This is an OR-ed signals of all shadow_done signals of all planes, and it can only be cleared by writing 1 for all asserted bits in SHADOW_DONE_ST register. + */ +#define LCDC_ST_SHADOW_DONE_MASK (0x10U) +#define LCDC_ST_SHADOW_DONE_SHIFT (4U) +#define LCDC_ST_SHADOW_DONE_GET(x) (((uint32_t)(x) & LCDC_ST_SHADOW_DONE_MASK) >> LCDC_ST_SHADOW_DONE_SHIFT) + /* * URGENT_UNDERRUN (W1C) * @@ -390,12 +506,53 @@ typedef struct { #define LCDC_INT_EN_DMA_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_DONE_MASK) >> LCDC_INT_EN_DMA_DONE_SHIFT) /* - * URGENT_UNDERRUN (ROI) + * HANDSHAKE_ABORT (RW) + * + * Handshake abort error int enable + */ +#define LCDC_INT_EN_HANDSHAKE_ABORT_MASK (0x80U) +#define LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT (7U) +#define LCDC_INT_EN_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT) & LCDC_INT_EN_HANDSHAKE_ABORT_MASK) +#define LCDC_INT_EN_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_INT_EN_HANDSHAKE_ABORT_MASK) >> LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT) + +/* + * CAM_HCNT_FAIL (RW) + * + * hcnt out of acceptable ranges interrupt enable + */ +#define LCDC_INT_EN_CAM_HCNT_FAIL_MASK (0x40U) +#define LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT (6U) +#define LCDC_INT_EN_CAM_HCNT_FAIL_SET(x) (((uint32_t)(x) << LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT) & LCDC_INT_EN_CAM_HCNT_FAIL_MASK) +#define LCDC_INT_EN_CAM_HCNT_FAIL_GET(x) (((uint32_t)(x) & LCDC_INT_EN_CAM_HCNT_FAIL_MASK) >> LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT) + +/* + * CAM_VSYNC_FAIL (RW) + * + * cam_vsync fail interrupt enable + */ +#define LCDC_INT_EN_CAM_VSYNC_FAIL_MASK (0x20U) +#define LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT (5U) +#define LCDC_INT_EN_CAM_VSYNC_FAIL_SET(x) (((uint32_t)(x) << LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT) & LCDC_INT_EN_CAM_VSYNC_FAIL_MASK) +#define LCDC_INT_EN_CAM_VSYNC_FAIL_GET(x) (((uint32_t)(x) & LCDC_INT_EN_CAM_VSYNC_FAIL_MASK) >> LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT) + +/* + * SHADOW_DONE (RW) + * + * Shadow done interrupt enable + */ +#define LCDC_INT_EN_SHADOW_DONE_MASK (0x10U) +#define LCDC_INT_EN_SHADOW_DONE_SHIFT (4U) +#define LCDC_INT_EN_SHADOW_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_SHADOW_DONE_SHIFT) & LCDC_INT_EN_SHADOW_DONE_MASK) +#define LCDC_INT_EN_SHADOW_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_SHADOW_DONE_MASK) >> LCDC_INT_EN_SHADOW_DONE_SHIFT) + +/* + * URGENT_UNDERRUN (RW) * * Asserted when the output buffer urgent underrun condition encountered */ #define LCDC_INT_EN_URGENT_UNDERRUN_MASK (0x8U) #define LCDC_INT_EN_URGENT_UNDERRUN_SHIFT (3U) +#define LCDC_INT_EN_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) #define LCDC_INT_EN_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) >> LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) /* @@ -439,7 +596,250 @@ typedef struct { #define LCDC_TXFIFO_THRSH_SET(x) (((uint32_t)(x) << LCDC_TXFIFO_THRSH_SHIFT) & LCDC_TXFIFO_THRSH_MASK) #define LCDC_TXFIFO_THRSH_GET(x) (((uint32_t)(x) & LCDC_TXFIFO_THRSH_MASK) >> LCDC_TXFIFO_THRSH_SHIFT) +/* Bitfield definition for register: CTRL_BP_V_RANGE */ +/* + * MAX (RW) + * + * Maximal BP_V values + */ +#define LCDC_CTRL_BP_V_RANGE_MAX_MASK (0x7FC0000UL) +#define LCDC_CTRL_BP_V_RANGE_MAX_SHIFT (18U) +#define LCDC_CTRL_BP_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_MAX_SHIFT) & LCDC_CTRL_BP_V_RANGE_MAX_MASK) +#define LCDC_CTRL_BP_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_MAX_MASK) >> LCDC_CTRL_BP_V_RANGE_MAX_SHIFT) + +/* + * BEST (RW) + * + * Best BP_V values + */ +#define LCDC_CTRL_BP_V_RANGE_BEST_MASK (0x3FE00UL) +#define LCDC_CTRL_BP_V_RANGE_BEST_SHIFT (9U) +#define LCDC_CTRL_BP_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_BEST_SHIFT) & LCDC_CTRL_BP_V_RANGE_BEST_MASK) +#define LCDC_CTRL_BP_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_BEST_MASK) >> LCDC_CTRL_BP_V_RANGE_BEST_SHIFT) + +/* + * MIN (RW) + * + * Minimal BP_V values + */ +#define LCDC_CTRL_BP_V_RANGE_MIN_MASK (0x1FFU) +#define LCDC_CTRL_BP_V_RANGE_MIN_SHIFT (0U) +#define LCDC_CTRL_BP_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_MIN_SHIFT) & LCDC_CTRL_BP_V_RANGE_MIN_MASK) +#define LCDC_CTRL_BP_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_MIN_MASK) >> LCDC_CTRL_BP_V_RANGE_MIN_SHIFT) + +/* Bitfield definition for register: CTRL_PW_V_RANGE */ +/* + * MAX (RW) + * + * Maximal PW_V values + */ +#define LCDC_CTRL_PW_V_RANGE_MAX_MASK (0x7FC0000UL) +#define LCDC_CTRL_PW_V_RANGE_MAX_SHIFT (18U) +#define LCDC_CTRL_PW_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_MAX_SHIFT) & LCDC_CTRL_PW_V_RANGE_MAX_MASK) +#define LCDC_CTRL_PW_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_MAX_MASK) >> LCDC_CTRL_PW_V_RANGE_MAX_SHIFT) + +/* + * BEST (RW) + * + * Best PW_V values + */ +#define LCDC_CTRL_PW_V_RANGE_BEST_MASK (0x3FE00UL) +#define LCDC_CTRL_PW_V_RANGE_BEST_SHIFT (9U) +#define LCDC_CTRL_PW_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_BEST_SHIFT) & LCDC_CTRL_PW_V_RANGE_BEST_MASK) +#define LCDC_CTRL_PW_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_BEST_MASK) >> LCDC_CTRL_PW_V_RANGE_BEST_SHIFT) + +/* + * MIN (RW) + * + * Minimal PW_V values + */ +#define LCDC_CTRL_PW_V_RANGE_MIN_MASK (0x1FFU) +#define LCDC_CTRL_PW_V_RANGE_MIN_SHIFT (0U) +#define LCDC_CTRL_PW_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_MIN_SHIFT) & LCDC_CTRL_PW_V_RANGE_MIN_MASK) +#define LCDC_CTRL_PW_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_MIN_MASK) >> LCDC_CTRL_PW_V_RANGE_MIN_SHIFT) + +/* Bitfield definition for register: CTRL_FP_V_RANGE */ +/* + * MAX (RW) + * + * Maximal FP_V values + */ +#define LCDC_CTRL_FP_V_RANGE_MAX_MASK (0x7FC0000UL) +#define LCDC_CTRL_FP_V_RANGE_MAX_SHIFT (18U) +#define LCDC_CTRL_FP_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_MAX_SHIFT) & LCDC_CTRL_FP_V_RANGE_MAX_MASK) +#define LCDC_CTRL_FP_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_MAX_MASK) >> LCDC_CTRL_FP_V_RANGE_MAX_SHIFT) + +/* + * BEST (RW) + * + * Best FP_V values + */ +#define LCDC_CTRL_FP_V_RANGE_BEST_MASK (0x3FE00UL) +#define LCDC_CTRL_FP_V_RANGE_BEST_SHIFT (9U) +#define LCDC_CTRL_FP_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_BEST_SHIFT) & LCDC_CTRL_FP_V_RANGE_BEST_MASK) +#define LCDC_CTRL_FP_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_BEST_MASK) >> LCDC_CTRL_FP_V_RANGE_BEST_SHIFT) + +/* + * MIN (RW) + * + * Minimal FP_V values + */ +#define LCDC_CTRL_FP_V_RANGE_MIN_MASK (0x1FFU) +#define LCDC_CTRL_FP_V_RANGE_MIN_SHIFT (0U) +#define LCDC_CTRL_FP_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_MIN_SHIFT) & LCDC_CTRL_FP_V_RANGE_MIN_MASK) +#define LCDC_CTRL_FP_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_MIN_MASK) >> LCDC_CTRL_FP_V_RANGE_MIN_SHIFT) + +/* Bitfield definition for register: CAM_SYNC_HCNT_MIN */ +/* + * VAL (RW) + * + * minimal acceptable HCNT Value + */ +#define LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK (0xFFFFU) +#define LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT (0U) +#define LCDC_CAM_SYNC_HCNT_MIN_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK) +#define LCDC_CAM_SYNC_HCNT_MIN_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT) + +/* Bitfield definition for register: CAM_SYNC_HCNT_BEST */ +/* + * HYST (RW) + * + * hysteresys of acceptable HCNT Value + */ +#define LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK (0xFF0000UL) +#define LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT (16U) +#define LCDC_CAM_SYNC_HCNT_BEST_HYST_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT) & LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK) +#define LCDC_CAM_SYNC_HCNT_BEST_HYST_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK) >> LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT) + +/* + * VAL (RW) + * + * best acceptable HCNT Value + */ +#define LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK (0xFFFFU) +#define LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT (0U) +#define LCDC_CAM_SYNC_HCNT_BEST_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK) +#define LCDC_CAM_SYNC_HCNT_BEST_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT) + +/* Bitfield definition for register: CAM_SYNC_HCNT_MAX */ +/* + * VAL (RW) + * + * maximal acceptable HCNT Value + */ +#define LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK (0xFFFFU) +#define LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT (0U) +#define LCDC_CAM_SYNC_HCNT_MAX_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK) +#define LCDC_CAM_SYNC_HCNT_MAX_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT) + +/* Bitfield definition for register: CAM_SYNC_HCNT_ST */ +/* + * VAL (RO) + * + * current HCNT value + */ +#define LCDC_CAM_SYNC_HCNT_ST_VAL_MASK (0xFFFFU) +#define LCDC_CAM_SYNC_HCNT_ST_VAL_SHIFT (0U) +#define LCDC_CAM_SYNC_HCNT_ST_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_ST_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_ST_VAL_SHIFT) + +/* Bitfield definition for register: SHADOW_DONE_ST */ +/* + * VAL (RO) + * + * current shadow_done value for plane 7,...,0 respectively + */ +#define LCDC_SHADOW_DONE_ST_VAL_MASK (0xFFU) +#define LCDC_SHADOW_DONE_ST_VAL_SHIFT (0U) +#define LCDC_SHADOW_DONE_ST_VAL_GET(x) (((uint32_t)(x) & LCDC_SHADOW_DONE_ST_VAL_MASK) >> LCDC_SHADOW_DONE_ST_VAL_SHIFT) + +/* Bitfield definition for register: SHADOW_DONE_INT_EN */ +/* + * VAL (RW) + * + * shadow_done interrupt enable for plane 7,...,0 respectively + */ +#define LCDC_SHADOW_DONE_INT_EN_VAL_MASK (0xFFU) +#define LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT (0U) +#define LCDC_SHADOW_DONE_INT_EN_VAL_SET(x) (((uint32_t)(x) << LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT) & LCDC_SHADOW_DONE_INT_EN_VAL_MASK) +#define LCDC_SHADOW_DONE_INT_EN_VAL_GET(x) (((uint32_t)(x) & LCDC_SHADOW_DONE_INT_EN_VAL_MASK) >> LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT) + /* Bitfield definition for register of struct array LAYER: LAYCTRL */ +/* + * RESAMPLE_VRATIO (RW) + * + * Resample the input data stream in the verticle direction + * 0: don't resample + * positive n: upsample-by-n+1 (2 to 8) + * negtive n: downsample-by-n+1 (2 to 8) + */ +#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK (0xF0000000UL) +#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT (28U) +#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT) & LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK) +#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK) >> LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT) + +/* + * RESAMPLE_HRATIO (RW) + * + * Resample the input data stream in the horizontal direction + * 0: don't resample + * positive n: upsample-by-n+1 (2 to 8) + * negtive n: downsample-by-n+1 (2 to 8) + */ +#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK (0xF000000UL) +#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT (24U) +#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT) & LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK) +#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK) >> LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT) + +/* + * NORMLZ_OUT (RW) + * + * Normalize the pixel out for the not-overlapped pixels + */ +#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK (0x800000UL) +#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT (23U) +#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT) & LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK) +#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK) >> LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT) + +/* + * HANDSHAKE_ABORT_INT_EN (RW) + * + * 1: Enable the handshake abort error interrupt. + * 0: don't Enable the handshake abort error interrupt. + * Abort is generated when the LCDC is going to switch bank to a new bank, and the new bank data is not ready yet. + * Abort is only useful when communicating with the offline calculator (such as PDMA as the active pixel generator mode). + * PDMA as the active generator mode, means it is the first pixel generator with data sources from offline memory, and not from on-the-fly streaming data (such as camera captured data). + * While with on-the-fly streaming data, error condition is indicated by display buffer underflow. + */ +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK (0x400000UL) +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT (22U) +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT) & LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK) +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK) >> LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT) + +/* + * HANDSHAKE_BUFSIZE (RW) + * + * 1: handshake buffer is 16 rows hight per ping or pang buf. + * 0: handshake buffer is 8 rows hight per ping or pang buf. + */ +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK (0x200000UL) +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT (21U) +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT) & LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK) +#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK) >> LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT) + +/* + * ENABLE_HANDSHAKE (RW) + * + * Enable handshake with input pixel controller. When this is set, the LCDC will not process an entire framebuffer, + * but will instead process rows of NxN blocks in a double-buffer handshake with the input pixel controlller. This enables + * the use of the onboard SRAM for a partial frame buffer. Only valid for Plane 0 & 1. + * 1: handshake enabled + * 0: handshake disabled + */ +#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK (0x100000UL) +#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT (20U) +#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT) & LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK) +#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK) >> LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT) + /* * PACK_DIR (RW) * @@ -787,6 +1187,17 @@ typedef struct { #define LCDC_LAYER_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C3_MASK) >> LCDC_LAYER_CSC_COEF2_C3_SHIFT) /* Bitfield definition for register: CLUT_LOAD */ +/* + * STR_HIGH (RW) + * + * 1'b1: Store 8+ CLUT tables through APB + * 1'b0: Store 0-7 CLUT tables through APB + */ +#define LCDC_CLUT_LOAD_STR_HIGH_MASK (0x80000000UL) +#define LCDC_CLUT_LOAD_STR_HIGH_SHIFT (31U) +#define LCDC_CLUT_LOAD_STR_HIGH_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_STR_HIGH_SHIFT) & LCDC_CLUT_LOAD_STR_HIGH_MASK) +#define LCDC_CLUT_LOAD_STR_HIGH_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_STR_HIGH_MASK) >> LCDC_CLUT_LOAD_STR_HIGH_SHIFT) + /* * SEL_NUM (RW) * @@ -831,4 +1242,4 @@ typedef struct { #define LCDC_LAYER_7 (7UL) -#endif /* HPM_LCDC_H */ \ No newline at end of file +#endif /* HPM_LCDC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lin_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lin_regs.h new file mode 100644 index 0000000000..b1c314ac70 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lin_regs.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LIN_H +#define HPM_LIN_H + +typedef struct { + __RW uint32_t DATABYTE[8]; /* 0x0 - 0x1C: data byte */ + __RW uint32_t CONTROL; /* 0x20: control register */ + __R uint32_t STATE; /* 0x24: state register */ + __R uint32_t ERROR; /* 0x28: error register */ + __RW uint32_t DATA_LEN; /* 0x2C: data lenth register */ + __RW uint32_t BAUDRATE_CTL_LOW; /* 0x30: baudrate control low register */ + __RW uint32_t BARDRATE_CTL_HIGH; /* 0x34: baudrate control high register */ + __RW uint32_t ID; /* 0x38: id register */ + __RW uint32_t TV; /* 0x3C: timeout control register */ +} LIN_Type; + + +/* Bitfield definition for register array: DATABYTE */ +/* + * DATA_BYTE (RW) + * + * data byte + */ +#define LIN_DATABYTE_DATA_BYTE_MASK (0xFFU) +#define LIN_DATABYTE_DATA_BYTE_SHIFT (0U) +#define LIN_DATABYTE_DATA_BYTE_SET(x) (((uint32_t)(x) << LIN_DATABYTE_DATA_BYTE_SHIFT) & LIN_DATABYTE_DATA_BYTE_MASK) +#define LIN_DATABYTE_DATA_BYTE_GET(x) (((uint32_t)(x) & LIN_DATABYTE_DATA_BYTE_MASK) >> LIN_DATABYTE_DATA_BYTE_SHIFT) + +/* Bitfield definition for register: CONTROL */ +/* + * STOP (WO) + * + * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID + */ +#define LIN_CONTROL_STOP_MASK (0x80U) +#define LIN_CONTROL_STOP_SHIFT (7U) +#define LIN_CONTROL_STOP_SET(x) (((uint32_t)(x) << LIN_CONTROL_STOP_SHIFT) & LIN_CONTROL_STOP_MASK) +#define LIN_CONTROL_STOP_GET(x) (((uint32_t)(x) & LIN_CONTROL_STOP_MASK) >> LIN_CONTROL_STOP_SHIFT) + +/* + * SLEEP (RW) + * + * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. + */ +#define LIN_CONTROL_SLEEP_MASK (0x40U) +#define LIN_CONTROL_SLEEP_SHIFT (6U) +#define LIN_CONTROL_SLEEP_SET(x) (((uint32_t)(x) << LIN_CONTROL_SLEEP_SHIFT) & LIN_CONTROL_SLEEP_MASK) +#define LIN_CONTROL_SLEEP_GET(x) (((uint32_t)(x) & LIN_CONTROL_SLEEP_MASK) >> LIN_CONTROL_SLEEP_SHIFT) + +/* + * TRANSMIT (RW) + * + * 1: transmit operation 0: receive operation + */ +#define LIN_CONTROL_TRANSMIT_MASK (0x20U) +#define LIN_CONTROL_TRANSMIT_SHIFT (5U) +#define LIN_CONTROL_TRANSMIT_SET(x) (((uint32_t)(x) << LIN_CONTROL_TRANSMIT_SHIFT) & LIN_CONTROL_TRANSMIT_MASK) +#define LIN_CONTROL_TRANSMIT_GET(x) (((uint32_t)(x) & LIN_CONTROL_TRANSMIT_MASK) >> LIN_CONTROL_TRANSMIT_SHIFT) + +/* + * DATA_ACK (RW) + * + * slave only. Write 1 after handling a data request interrupt + */ +#define LIN_CONTROL_DATA_ACK_MASK (0x10U) +#define LIN_CONTROL_DATA_ACK_SHIFT (4U) +#define LIN_CONTROL_DATA_ACK_SET(x) (((uint32_t)(x) << LIN_CONTROL_DATA_ACK_SHIFT) & LIN_CONTROL_DATA_ACK_MASK) +#define LIN_CONTROL_DATA_ACK_GET(x) (((uint32_t)(x) & LIN_CONTROL_DATA_ACK_MASK) >> LIN_CONTROL_DATA_ACK_SHIFT) + +/* + * RESET_INT (WO) + * + * write 1 to reset the int bit in the status register and the interrupt request output of LIN + */ +#define LIN_CONTROL_RESET_INT_MASK (0x8U) +#define LIN_CONTROL_RESET_INT_SHIFT (3U) +#define LIN_CONTROL_RESET_INT_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_INT_SHIFT) & LIN_CONTROL_RESET_INT_MASK) +#define LIN_CONTROL_RESET_INT_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_INT_MASK) >> LIN_CONTROL_RESET_INT_SHIFT) + +/* + * RESET_ERROR (WO) + * + * assert 1 to reset the error bits in status register and error register. A read access to this bit delivers always the value 0 + */ +#define LIN_CONTROL_RESET_ERROR_MASK (0x4U) +#define LIN_CONTROL_RESET_ERROR_SHIFT (2U) +#define LIN_CONTROL_RESET_ERROR_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_ERROR_SHIFT) & LIN_CONTROL_RESET_ERROR_MASK) +#define LIN_CONTROL_RESET_ERROR_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_ERROR_MASK) >> LIN_CONTROL_RESET_ERROR_SHIFT) + +/* + * WAKEUP_REQ (RW) + * + * wakeup request. Assert to terminate the Sleep mode of the LIN bus. The bit will be reset by core + */ +#define LIN_CONTROL_WAKEUP_REQ_MASK (0x2U) +#define LIN_CONTROL_WAKEUP_REQ_SHIFT (1U) +#define LIN_CONTROL_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_WAKEUP_REQ_SHIFT) & LIN_CONTROL_WAKEUP_REQ_MASK) +#define LIN_CONTROL_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_WAKEUP_REQ_MASK) >> LIN_CONTROL_WAKEUP_REQ_SHIFT) + +/* + * START_REQ (RW) + * + * master only. Set by host controller of a LIN master to start the LIN transmission. The core will reset the bit after the transmission is finished or an error is occurred + */ +#define LIN_CONTROL_START_REQ_MASK (0x1U) +#define LIN_CONTROL_START_REQ_SHIFT (0U) +#define LIN_CONTROL_START_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_START_REQ_SHIFT) & LIN_CONTROL_START_REQ_MASK) +#define LIN_CONTROL_START_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_START_REQ_MASK) >> LIN_CONTROL_START_REQ_SHIFT) + +/* Bitfield definition for register: STATE */ +/* + * LIN_ACTIVE (RO) + * + * The bit indicates whether the LIN bus is active or not + */ +#define LIN_STATE_LIN_ACTIVE_MASK (0x80U) +#define LIN_STATE_LIN_ACTIVE_SHIFT (7U) +#define LIN_STATE_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LIN_STATE_LIN_ACTIVE_MASK) >> LIN_STATE_LIN_ACTIVE_SHIFT) + +/* + * BUS_IDLE_TV (RO) + * + * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s + */ +#define LIN_STATE_BUS_IDLE_TV_MASK (0x40U) +#define LIN_STATE_BUS_IDLE_TV_SHIFT (6U) +#define LIN_STATE_BUS_IDLE_TV_GET(x) (((uint32_t)(x) & LIN_STATE_BUS_IDLE_TV_MASK) >> LIN_STATE_BUS_IDLE_TV_SHIFT) + +/* + * ABORTED (RO) + * + * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. + */ +#define LIN_STATE_ABORTED_MASK (0x20U) +#define LIN_STATE_ABORTED_SHIFT (5U) +#define LIN_STATE_ABORTED_GET(x) (((uint32_t)(x) & LIN_STATE_ABORTED_MASK) >> LIN_STATE_ABORTED_SHIFT) + +/* + * DATA_REQ (RO) + * + * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. + */ +#define LIN_STATE_DATA_REQ_MASK (0x10U) +#define LIN_STATE_DATA_REQ_SHIFT (4U) +#define LIN_STATE_DATA_REQ_GET(x) (((uint32_t)(x) & LIN_STATE_DATA_REQ_MASK) >> LIN_STATE_DATA_REQ_SHIFT) + +/* + * INT (RO) + * + * set when request an interrupt. Reset by reset_int + */ +#define LIN_STATE_INT_MASK (0x8U) +#define LIN_STATE_INT_SHIFT (3U) +#define LIN_STATE_INT_GET(x) (((uint32_t)(x) & LIN_STATE_INT_MASK) >> LIN_STATE_INT_SHIFT) + +/* + * ERROR (RO) + * + * set when detecte an error, clear by reset_error + */ +#define LIN_STATE_ERROR_MASK (0x4U) +#define LIN_STATE_ERROR_SHIFT (2U) +#define LIN_STATE_ERROR_GET(x) (((uint32_t)(x) & LIN_STATE_ERROR_MASK) >> LIN_STATE_ERROR_SHIFT) + +/* + * WAKEUP (RO) + * + * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 + */ +#define LIN_STATE_WAKEUP_MASK (0x2U) +#define LIN_STATE_WAKEUP_SHIFT (1U) +#define LIN_STATE_WAKEUP_GET(x) (((uint32_t)(x) & LIN_STATE_WAKEUP_MASK) >> LIN_STATE_WAKEUP_SHIFT) + +/* + * COMPLETE (RO) + * + * set after a transmission has been successful finished and it will reset at the start of a transmission. + */ +#define LIN_STATE_COMPLETE_MASK (0x1U) +#define LIN_STATE_COMPLETE_SHIFT (0U) +#define LIN_STATE_COMPLETE_GET(x) (((uint32_t)(x) & LIN_STATE_COMPLETE_MASK) >> LIN_STATE_COMPLETE_SHIFT) + +/* Bitfield definition for register: ERROR */ +/* + * PARITY_ERROR (RO) + * + * slave only. identifier parity error + */ +#define LIN_ERROR_PARITY_ERROR_MASK (0x8U) +#define LIN_ERROR_PARITY_ERROR_SHIFT (3U) +#define LIN_ERROR_PARITY_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_PARITY_ERROR_MASK) >> LIN_ERROR_PARITY_ERROR_SHIFT) + +/* + * TIMEOUT (RO) + * + * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms + */ +#define LIN_ERROR_TIMEOUT_MASK (0x4U) +#define LIN_ERROR_TIMEOUT_SHIFT (2U) +#define LIN_ERROR_TIMEOUT_GET(x) (((uint32_t)(x) & LIN_ERROR_TIMEOUT_MASK) >> LIN_ERROR_TIMEOUT_SHIFT) + +/* + * CHK_ERROR (RO) + * + * checksum error + */ +#define LIN_ERROR_CHK_ERROR_MASK (0x2U) +#define LIN_ERROR_CHK_ERROR_SHIFT (1U) +#define LIN_ERROR_CHK_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_CHK_ERROR_MASK) >> LIN_ERROR_CHK_ERROR_SHIFT) + +/* + * BIT_ERROR (RO) + * + * bit error + */ +#define LIN_ERROR_BIT_ERROR_MASK (0x1U) +#define LIN_ERROR_BIT_ERROR_SHIFT (0U) +#define LIN_ERROR_BIT_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_BIT_ERROR_MASK) >> LIN_ERROR_BIT_ERROR_SHIFT) + +/* Bitfield definition for register: DATA_LEN */ +/* + * ENH_CHECK (RW) + * + * 1:enhence check mode + */ +#define LIN_DATA_LEN_ENH_CHECK_MASK (0x80U) +#define LIN_DATA_LEN_ENH_CHECK_SHIFT (7U) +#define LIN_DATA_LEN_ENH_CHECK_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_ENH_CHECK_SHIFT) & LIN_DATA_LEN_ENH_CHECK_MASK) +#define LIN_DATA_LEN_ENH_CHECK_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_ENH_CHECK_MASK) >> LIN_DATA_LEN_ENH_CHECK_SHIFT) + +/* + * DATA_LENGTH (RW) + * + * data length + */ +#define LIN_DATA_LEN_DATA_LENGTH_MASK (0xFU) +#define LIN_DATA_LEN_DATA_LENGTH_SHIFT (0U) +#define LIN_DATA_LEN_DATA_LENGTH_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_DATA_LENGTH_SHIFT) & LIN_DATA_LEN_DATA_LENGTH_MASK) +#define LIN_DATA_LEN_DATA_LENGTH_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_DATA_LENGTH_MASK) >> LIN_DATA_LEN_DATA_LENGTH_SHIFT) + +/* Bitfield definition for register: BAUDRATE_CTL_LOW */ +/* + * BT_DIV_LOW (RW) + * + * bit div register 7:0 + */ +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK (0xFFU) +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT (0U) +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SET(x) (((uint32_t)(x) << LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_GET(x) (((uint32_t)(x) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) >> LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) + +/* Bitfield definition for register: BARDRATE_CTL_HIGH */ +/* + * PRESCL (RW) + * + * prescl register + */ +#define LIN_BARDRATE_CTL_HIGH_PRESCL_MASK (0xC0U) +#define LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT (6U) +#define LIN_BARDRATE_CTL_HIGH_PRESCL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) +#define LIN_BARDRATE_CTL_HIGH_PRESCL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) >> LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) + +/* + * BT_MUL (RW) + * + * bt_mul register + */ +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK (0x3EU) +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT (1U) +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) + +/* + * BT_DIV_HIGH (RW) + * + * bit div register 8 + */ +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK (0x1U) +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT (0U) +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) + +/* Bitfield definition for register: ID */ +/* + * ID (RW) + * + * id register + */ +#define LIN_ID_ID_MASK (0x3FU) +#define LIN_ID_ID_SHIFT (0U) +#define LIN_ID_ID_SET(x) (((uint32_t)(x) << LIN_ID_ID_SHIFT) & LIN_ID_ID_MASK) +#define LIN_ID_ID_GET(x) (((uint32_t)(x) & LIN_ID_ID_MASK) >> LIN_ID_ID_SHIFT) + +/* Bitfield definition for register: TV */ +/* + * INITIAL_MODE (RW) + * + * initial_mode + */ +#define LIN_TV_INITIAL_MODE_MASK (0x80U) +#define LIN_TV_INITIAL_MODE_SHIFT (7U) +#define LIN_TV_INITIAL_MODE_SET(x) (((uint32_t)(x) << LIN_TV_INITIAL_MODE_SHIFT) & LIN_TV_INITIAL_MODE_MASK) +#define LIN_TV_INITIAL_MODE_GET(x) (((uint32_t)(x) & LIN_TV_INITIAL_MODE_MASK) >> LIN_TV_INITIAL_MODE_SHIFT) + +/* + * MASTER_MODE (RW) + * + * master_mode + */ +#define LIN_TV_MASTER_MODE_MASK (0x40U) +#define LIN_TV_MASTER_MODE_SHIFT (6U) +#define LIN_TV_MASTER_MODE_SET(x) (((uint32_t)(x) << LIN_TV_MASTER_MODE_SHIFT) & LIN_TV_MASTER_MODE_MASK) +#define LIN_TV_MASTER_MODE_GET(x) (((uint32_t)(x) & LIN_TV_MASTER_MODE_MASK) >> LIN_TV_MASTER_MODE_SHIFT) + +/* + * BUS_INACTIVITY_TIME (RW) + * + * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s + */ +#define LIN_TV_BUS_INACTIVITY_TIME_MASK (0xCU) +#define LIN_TV_BUS_INACTIVITY_TIME_SHIFT (2U) +#define LIN_TV_BUS_INACTIVITY_TIME_SET(x) (((uint32_t)(x) << LIN_TV_BUS_INACTIVITY_TIME_SHIFT) & LIN_TV_BUS_INACTIVITY_TIME_MASK) +#define LIN_TV_BUS_INACTIVITY_TIME_GET(x) (((uint32_t)(x) & LIN_TV_BUS_INACTIVITY_TIME_MASK) >> LIN_TV_BUS_INACTIVITY_TIME_SHIFT) + +/* + * WUP_REPEAT_TIME (RW) + * + * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms + */ +#define LIN_TV_WUP_REPEAT_TIME_MASK (0x3U) +#define LIN_TV_WUP_REPEAT_TIME_SHIFT (0U) +#define LIN_TV_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LIN_TV_WUP_REPEAT_TIME_SHIFT) & LIN_TV_WUP_REPEAT_TIME_MASK) +#define LIN_TV_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LIN_TV_WUP_REPEAT_TIME_MASK) >> LIN_TV_WUP_REPEAT_TIME_SHIFT) + + + +/* DATABYTE register group index macro definition */ +#define LIN_DATABYTE_DATA_BYTE0 (0UL) +#define LIN_DATABYTE_DATA_BYTE1 (1UL) +#define LIN_DATABYTE_DATA_BYTE2 (2UL) +#define LIN_DATABYTE_DATA_BYTE3 (3UL) +#define LIN_DATABYTE_DATA_BYTE4 (4UL) +#define LIN_DATABYTE_DATA_BYTE5 (5UL) +#define LIN_DATABYTE_DATA_BYTE6 (6UL) +#define LIN_DATABYTE_DATA_BYTE7 (7UL) + + +#endif /* HPM_LIN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h index f75d851c47..63e3cf9703 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -343,4 +343,4 @@ typedef struct { #define MBX_RXWRD_RXFIFO0 (0UL) -#endif /* HPM_MBX_H */ \ No newline at end of file +#endif /* HPM_MBX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h new file mode 100644 index 0000000000..e2cfd0f8f7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h @@ -0,0 +1,3583 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MCAN_H +#define HPM_MCAN_H + +typedef struct { + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __R uint32_t ENDN; /* 0x4: endian register */ + __R uint8_t RESERVED1[4]; /* 0x8 - 0xB: Reserved */ + __RW uint32_t DBTP; /* 0xC: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set */ + __RW uint32_t TEST; /* 0x10: test register */ + __RW uint32_t RWD; /* 0x14: ram watchdog */ + __RW uint32_t CCCR; /* 0x18: CC control register */ + __RW uint32_t NBTP; /* 0x1C: nominal bit timing and prescaler register */ + __RW uint32_t TSCC; /* 0x20: timestamp counter configuration */ + __R uint32_t TSCV; /* 0x24: timestamp counter value */ + __RW uint32_t TOCC; /* 0x28: timeout counter configuration */ + __R uint32_t TOCV; /* 0x2C: timeout counter value */ + __R uint8_t RESERVED2[16]; /* 0x30 - 0x3F: Reserved */ + __R uint32_t ECR; /* 0x40: error counter register */ + __R uint32_t PSR; /* 0x44: protocol status register */ + __RW uint32_t TDCR; /* 0x48: transmitter delay compensation */ + __R uint8_t RESERVED3[4]; /* 0x4C - 0x4F: Reserved */ + __RW uint32_t IR; /* 0x50: interrupt register */ + __RW uint32_t IE; /* 0x54: interrupt enable */ + __RW uint32_t ILS; /* 0x58: interrupt line select */ + __RW uint32_t ILE; /* 0x5C: interrupt line enable */ + __R uint8_t RESERVED4[32]; /* 0x60 - 0x7F: Reserved */ + __RW uint32_t GFC; /* 0x80: global filter configuration */ + __RW uint32_t SIDFC; /* 0x84: standard ID filter configuration */ + __RW uint32_t XIDFC; /* 0x88: extended ID filter configuration */ + __R uint8_t RESERVED5[4]; /* 0x8C - 0x8F: Reserved */ + __RW uint32_t XIDAM; /* 0x90: extended id and mask */ + __R uint32_t HPMS; /* 0x94: high priority message status */ + __RW uint32_t NDAT1; /* 0x98: new data1 */ + __RW uint32_t NDAT2; /* 0x9C: new data2 */ + __RW uint32_t RXF0C; /* 0xA0: rx fifo 0 configuration */ + __R uint32_t RXF0S; /* 0xA4: rx fifo 0 status */ + __RW uint32_t RXF0A; /* 0xA8: rx fifo0 acknowledge */ + __RW uint32_t RXBC; /* 0xAC: rx buffer configuration */ + __RW uint32_t RXF1C; /* 0xB0: rx fifo1 configuration */ + __R uint32_t RXF1S; /* 0xB4: rx fifo1 status */ + __RW uint32_t RXF1A; /* 0xB8: rx fifo 1 acknowledge */ + __RW uint32_t RXESC; /* 0xBC: rx buffer/fifo element size configuration */ + __RW uint32_t TXBC; /* 0xC0: tx buffer configuration */ + __R uint32_t TXFQS; /* 0xC4: tx fifo/queue status */ + __RW uint32_t TXESC; /* 0xC8: tx buffer element size configuration */ + __R uint32_t TXBRP; /* 0xCC: tx buffer request pending */ + __RW uint32_t TXBAR; /* 0xD0: tx buffer add request */ + __RW uint32_t TXBCR; /* 0xD4: tx buffer cancellation request */ + __R uint32_t TXBTO; /* 0xD8: tx buffer transmission occurred */ + __R uint32_t TXBCF; /* 0xDC: tx buffer cancellation finished */ + __RW uint32_t TXBTIE; /* 0xE0: tx buffer transmission interrupt enable */ + __RW uint32_t TXBCIE; /* 0xE4: tx buffer cancellation finished interrupt enable */ + __R uint8_t RESERVED6[8]; /* 0xE8 - 0xEF: Reserved */ + __RW uint32_t TXEFC; /* 0xF0: tx event fifo configuration */ + __R uint32_t TXEFS; /* 0xF4: tx event fifo status */ + __RW uint32_t TXEFA; /* 0xF8: tx event fifo acknowledge */ + __R uint8_t RESERVED7[260]; /* 0xFC - 0x1FF: Reserved */ + __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0-15 */ + __R uint32_t CREL; /* 0x240: core release register */ + __RW uint32_t TSCFG; /* 0x244: timestamp configuration */ + __R uint32_t TSS1; /* 0x248: timestamp status1 */ + __R uint32_t TSS2; /* 0x24C: timestamp status2 */ + __R uint32_t ATB; /* 0x250: actual timebase */ + __R uint32_t ATBH; /* 0x254: actual timebase high */ + __R uint8_t RESERVED8[424]; /* 0x258 - 0x3FF: Reserved */ + __RW uint32_t GLB_CTL; /* 0x400: global control */ + __R uint32_t GLB_STATUS; /* 0x404: global status */ + __R uint8_t RESERVED9[7160]; /* 0x408 - 0x1FFF: Reserved */ + __RW uint32_t MESSAGE_BUFF[640]; /* 0x2000 - 0x29FC: message buff */ +} MCAN_Type; + + +/* Bitfield definition for register: ENDN */ +/* + * EVT (R) + * + * Endianness Test Value + * The endianness test value is 0x87654321. + */ +#define MCAN_ENDN_EVT_MASK (0xFFFFFFFFUL) +#define MCAN_ENDN_EVT_SHIFT (0U) +#define MCAN_ENDN_EVT_GET(x) (((uint32_t)(x) & MCAN_ENDN_EVT_MASK) >> MCAN_ENDN_EVT_SHIFT) + +/* Bitfield definition for register: DBTP */ +/* + * TDC (RW) + * + * transmitter delay compensation enable + * 0= Transmitter Delay Compensation disabled + * 1= Transmitter Delay Compensation enabled + */ +#define MCAN_DBTP_TDC_MASK (0x800000UL) +#define MCAN_DBTP_TDC_SHIFT (23U) +#define MCAN_DBTP_TDC_SET(x) (((uint32_t)(x) << MCAN_DBTP_TDC_SHIFT) & MCAN_DBTP_TDC_MASK) +#define MCAN_DBTP_TDC_GET(x) (((uint32_t)(x) & MCAN_DBTP_TDC_MASK) >> MCAN_DBTP_TDC_SHIFT) + +/* + * DBRP (RW) + * + * Data Bit Rate Prescaler + * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_DBTP_DBRP_MASK (0x1F0000UL) +#define MCAN_DBTP_DBRP_SHIFT (16U) +#define MCAN_DBTP_DBRP_SET(x) (((uint32_t)(x) << MCAN_DBTP_DBRP_SHIFT) & MCAN_DBTP_DBRP_MASK) +#define MCAN_DBTP_DBRP_GET(x) (((uint32_t)(x) & MCAN_DBTP_DBRP_MASK) >> MCAN_DBTP_DBRP_SHIFT) + +/* + * DTSEG1 (RW) + * + * Data time segment before sample point + * Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_DBTP_DTSEG1_MASK (0x1F00U) +#define MCAN_DBTP_DTSEG1_SHIFT (8U) +#define MCAN_DBTP_DTSEG1_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG1_SHIFT) & MCAN_DBTP_DTSEG1_MASK) +#define MCAN_DBTP_DTSEG1_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG1_MASK) >> MCAN_DBTP_DTSEG1_SHIFT) + +/* + * DTSEG2 (RW) + * + * Data time segment after sample point + * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_DBTP_DTSEG2_MASK (0xF0U) +#define MCAN_DBTP_DTSEG2_SHIFT (4U) +#define MCAN_DBTP_DTSEG2_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG2_SHIFT) & MCAN_DBTP_DTSEG2_MASK) +#define MCAN_DBTP_DTSEG2_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG2_MASK) >> MCAN_DBTP_DTSEG2_SHIFT) + +/* + * DSJW (RW) + * + * Data (Re)Synchronization Jump Width + * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_DBTP_DSJW_MASK (0xFU) +#define MCAN_DBTP_DSJW_SHIFT (0U) +#define MCAN_DBTP_DSJW_SET(x) (((uint32_t)(x) << MCAN_DBTP_DSJW_SHIFT) & MCAN_DBTP_DSJW_MASK) +#define MCAN_DBTP_DSJW_GET(x) (((uint32_t)(x) & MCAN_DBTP_DSJW_MASK) >> MCAN_DBTP_DSJW_SHIFT) + +/* Bitfield definition for register: TEST */ +/* + * SVAL (R) + * + * Started Valid + * 0= Value of TXBNS not valid + * 1= Value of TXBNS valid + */ +#define MCAN_TEST_SVAL_MASK (0x200000UL) +#define MCAN_TEST_SVAL_SHIFT (21U) +#define MCAN_TEST_SVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_SVAL_MASK) >> MCAN_TEST_SVAL_SHIFT) + +/* + * TXBNS (R) + * + * Tx Buffer Number Started + * Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. + */ +#define MCAN_TEST_TXBNS_MASK (0x1F0000UL) +#define MCAN_TEST_TXBNS_SHIFT (16U) +#define MCAN_TEST_TXBNS_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNS_MASK) >> MCAN_TEST_TXBNS_SHIFT) + +/* + * PVAL (R) + * + * Prepared Valid + * 0= Value of TXBNP not valid + * 1= Value of TXBNP valid + */ +#define MCAN_TEST_PVAL_MASK (0x2000U) +#define MCAN_TEST_PVAL_SHIFT (13U) +#define MCAN_TEST_PVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_PVAL_MASK) >> MCAN_TEST_PVAL_SHIFT) + +/* + * TXBNP (R) + * + * Tx Buffer Number Prepared + * Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. + */ +#define MCAN_TEST_TXBNP_MASK (0x1F00U) +#define MCAN_TEST_TXBNP_SHIFT (8U) +#define MCAN_TEST_TXBNP_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNP_MASK) >> MCAN_TEST_TXBNP_SHIFT) + +/* + * RX (R) + * + * Receive Pin + * Monitors the actual value of pin m_can_rx + * 0= The CAN bus is dominant (m_can_rx = ‘0’) + * 1= The CAN bus is recessive (m_can_rx = ‘1’) + */ +#define MCAN_TEST_RX_MASK (0x80U) +#define MCAN_TEST_RX_SHIFT (7U) +#define MCAN_TEST_RX_GET(x) (((uint32_t)(x) & MCAN_TEST_RX_MASK) >> MCAN_TEST_RX_SHIFT) + +/* + * TX (RW) + * + * Control of Transmit Pin + * 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time + * 01 Sample Point can be monitored at pin m_can_tx + * 10 Dominant (‘0’) level at pin m_can_tx + * 11 Recessive (‘1’) at pin m_can_tx + */ +#define MCAN_TEST_TX_MASK (0x60U) +#define MCAN_TEST_TX_SHIFT (5U) +#define MCAN_TEST_TX_SET(x) (((uint32_t)(x) << MCAN_TEST_TX_SHIFT) & MCAN_TEST_TX_MASK) +#define MCAN_TEST_TX_GET(x) (((uint32_t)(x) & MCAN_TEST_TX_MASK) >> MCAN_TEST_TX_SHIFT) + +/* + * LBCK (RW) + * + * Loop Back Mode + * 0= Reset value, Loop Back Mode is disabled + * 1= Loop Back Mode is enabled + */ +#define MCAN_TEST_LBCK_MASK (0x10U) +#define MCAN_TEST_LBCK_SHIFT (4U) +#define MCAN_TEST_LBCK_SET(x) (((uint32_t)(x) << MCAN_TEST_LBCK_SHIFT) & MCAN_TEST_LBCK_MASK) +#define MCAN_TEST_LBCK_GET(x) (((uint32_t)(x) & MCAN_TEST_LBCK_MASK) >> MCAN_TEST_LBCK_SHIFT) + +/* Bitfield definition for register: RWD */ +/* + * WDV (R) + * + * Watchdog Value + * Actual Message RAM Watchdog Counter Value. + */ +#define MCAN_RWD_WDV_MASK (0xFF00U) +#define MCAN_RWD_WDV_SHIFT (8U) +#define MCAN_RWD_WDV_GET(x) (((uint32_t)(x) & MCAN_RWD_WDV_MASK) >> MCAN_RWD_WDV_SHIFT) + +/* + * WDC (RW) + * + * Watchdog Configuration + * Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. + */ +#define MCAN_RWD_WDC_MASK (0xFFU) +#define MCAN_RWD_WDC_SHIFT (0U) +#define MCAN_RWD_WDC_SET(x) (((uint32_t)(x) << MCAN_RWD_WDC_SHIFT) & MCAN_RWD_WDC_MASK) +#define MCAN_RWD_WDC_GET(x) (((uint32_t)(x) & MCAN_RWD_WDC_MASK) >> MCAN_RWD_WDC_SHIFT) + +/* Bitfield definition for register: CCCR */ +/* + * NISO (RW) + * + * Non ISO Operation + * If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD + * Specification V1.0. + * 0= CAN FD frame format according to ISO 11898-1:2015 + * 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 + * Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. + */ +#define MCAN_CCCR_NISO_MASK (0x8000U) +#define MCAN_CCCR_NISO_SHIFT (15U) +#define MCAN_CCCR_NISO_SET(x) (((uint32_t)(x) << MCAN_CCCR_NISO_SHIFT) & MCAN_CCCR_NISO_MASK) +#define MCAN_CCCR_NISO_GET(x) (((uint32_t)(x) & MCAN_CCCR_NISO_MASK) >> MCAN_CCCR_NISO_SHIFT) + +/* + * TXP (RW) + * + * Transmit Pause + * If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after + * itself has successfully transmitted a frame (see Section 3.5). + * 0= Transmit pause disabled + * 1= Transmit pause enabled + */ +#define MCAN_CCCR_TXP_MASK (0x4000U) +#define MCAN_CCCR_TXP_SHIFT (14U) +#define MCAN_CCCR_TXP_SET(x) (((uint32_t)(x) << MCAN_CCCR_TXP_SHIFT) & MCAN_CCCR_TXP_MASK) +#define MCAN_CCCR_TXP_GET(x) (((uint32_t)(x) & MCAN_CCCR_TXP_MASK) >> MCAN_CCCR_TXP_SHIFT) + +/* + * EFBI (RW) + * + * Edge Filtering during Bus Integration + * 0= Edge filtering disabled + * 1= Two consecutive dominant tq required to detect an edge for hard synchronization + */ +#define MCAN_CCCR_EFBI_MASK (0x2000U) +#define MCAN_CCCR_EFBI_SHIFT (13U) +#define MCAN_CCCR_EFBI_SET(x) (((uint32_t)(x) << MCAN_CCCR_EFBI_SHIFT) & MCAN_CCCR_EFBI_MASK) +#define MCAN_CCCR_EFBI_GET(x) (((uint32_t)(x) & MCAN_CCCR_EFBI_MASK) >> MCAN_CCCR_EFBI_SHIFT) + +/* + * PXHD (RW) + * + * Protocol Exception Handling Disable + * 0= Protocol exception handling enabled + * 1= Protocol exception handling disabled + * Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. + */ +#define MCAN_CCCR_PXHD_MASK (0x1000U) +#define MCAN_CCCR_PXHD_SHIFT (12U) +#define MCAN_CCCR_PXHD_SET(x) (((uint32_t)(x) << MCAN_CCCR_PXHD_SHIFT) & MCAN_CCCR_PXHD_MASK) +#define MCAN_CCCR_PXHD_GET(x) (((uint32_t)(x) & MCAN_CCCR_PXHD_MASK) >> MCAN_CCCR_PXHD_SHIFT) + +/* + * WMM (RW) + * + * Wide Message Marker + * Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. + * 0= 8-bit Message Marker used + * 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + */ +#define MCAN_CCCR_WMM_MASK (0x800U) +#define MCAN_CCCR_WMM_SHIFT (11U) +#define MCAN_CCCR_WMM_SET(x) (((uint32_t)(x) << MCAN_CCCR_WMM_SHIFT) & MCAN_CCCR_WMM_MASK) +#define MCAN_CCCR_WMM_GET(x) (((uint32_t)(x) & MCAN_CCCR_WMM_MASK) >> MCAN_CCCR_WMM_SHIFT) + +/* + * UTSU (RW) + * + * Use Timestamping Unit + * When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. + * 0= Internal time stamping + * 1= External time stamping by TSU + * Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. + * In this case bit UTSU is fixed to zero by synthesis. + */ +#define MCAN_CCCR_UTSU_MASK (0x400U) +#define MCAN_CCCR_UTSU_SHIFT (10U) +#define MCAN_CCCR_UTSU_SET(x) (((uint32_t)(x) << MCAN_CCCR_UTSU_SHIFT) & MCAN_CCCR_UTSU_MASK) +#define MCAN_CCCR_UTSU_GET(x) (((uint32_t)(x) & MCAN_CCCR_UTSU_MASK) >> MCAN_CCCR_UTSU_SHIFT) + +/* + * BRSE (RW) + * + * Bit Rate Switch Enable + * 0= Bit rate switching for transmissions disabled + * 1= Bit rate switching for transmissions enabled + * Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. + */ +#define MCAN_CCCR_BRSE_MASK (0x200U) +#define MCAN_CCCR_BRSE_SHIFT (9U) +#define MCAN_CCCR_BRSE_SET(x) (((uint32_t)(x) << MCAN_CCCR_BRSE_SHIFT) & MCAN_CCCR_BRSE_MASK) +#define MCAN_CCCR_BRSE_GET(x) (((uint32_t)(x) & MCAN_CCCR_BRSE_MASK) >> MCAN_CCCR_BRSE_SHIFT) + +/* + * FDOE (RW) + * + * FD Operation Enable + * 0= FD operation disabled + * 1= FD operation enabled + */ +#define MCAN_CCCR_FDOE_MASK (0x100U) +#define MCAN_CCCR_FDOE_SHIFT (8U) +#define MCAN_CCCR_FDOE_SET(x) (((uint32_t)(x) << MCAN_CCCR_FDOE_SHIFT) & MCAN_CCCR_FDOE_MASK) +#define MCAN_CCCR_FDOE_GET(x) (((uint32_t)(x) & MCAN_CCCR_FDOE_MASK) >> MCAN_CCCR_FDOE_SHIFT) + +/* + * TEST (RW) + * + * Test Mode Enable + * 0= Normal operation, register TEST holds reset values + * 1= Test Mode, write access to register TEST enabled + */ +#define MCAN_CCCR_TEST_MASK (0x80U) +#define MCAN_CCCR_TEST_SHIFT (7U) +#define MCAN_CCCR_TEST_SET(x) (((uint32_t)(x) << MCAN_CCCR_TEST_SHIFT) & MCAN_CCCR_TEST_MASK) +#define MCAN_CCCR_TEST_GET(x) (((uint32_t)(x) & MCAN_CCCR_TEST_MASK) >> MCAN_CCCR_TEST_SHIFT) + +/* + * DAR (RW) + * + * Disable Automatic Retransmission + * 0= Automatic retransmission of messages not transmitted successfully enabled + * 1= Automatic retransmission disabled + */ +#define MCAN_CCCR_DAR_MASK (0x40U) +#define MCAN_CCCR_DAR_SHIFT (6U) +#define MCAN_CCCR_DAR_SET(x) (((uint32_t)(x) << MCAN_CCCR_DAR_SHIFT) & MCAN_CCCR_DAR_MASK) +#define MCAN_CCCR_DAR_GET(x) (((uint32_t)(x) & MCAN_CCCR_DAR_MASK) >> MCAN_CCCR_DAR_SHIFT) + +/* + * MON (RW) + * + * Bus Monitoring Mode + * Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. + * 0= Bus Monitoring Mode is disabled + * 1= Bus Monitoring Mode is enabled + */ +#define MCAN_CCCR_MON_MASK (0x20U) +#define MCAN_CCCR_MON_SHIFT (5U) +#define MCAN_CCCR_MON_SET(x) (((uint32_t)(x) << MCAN_CCCR_MON_SHIFT) & MCAN_CCCR_MON_MASK) +#define MCAN_CCCR_MON_GET(x) (((uint32_t)(x) & MCAN_CCCR_MON_MASK) >> MCAN_CCCR_MON_SHIFT) + +/* + * CSR (RW) + * + * Clock Stop Request + * 0= No clock stop is requested + * 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + */ +#define MCAN_CCCR_CSR_MASK (0x10U) +#define MCAN_CCCR_CSR_SHIFT (4U) +#define MCAN_CCCR_CSR_SET(x) (((uint32_t)(x) << MCAN_CCCR_CSR_SHIFT) & MCAN_CCCR_CSR_MASK) +#define MCAN_CCCR_CSR_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSR_MASK) >> MCAN_CCCR_CSR_SHIFT) + +/* + * CSA (R) + * + * Clock Stop Acknowledge + * 0= No clock stop acknowledged + * 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk + */ +#define MCAN_CCCR_CSA_MASK (0x8U) +#define MCAN_CCCR_CSA_SHIFT (3U) +#define MCAN_CCCR_CSA_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSA_MASK) >> MCAN_CCCR_CSA_SHIFT) + +/* + * ASM (RW) + * + * Restricted Operation Mode + * Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. + * 0= Normal CAN operation + * 1= Restricted Operation Mode active + */ +#define MCAN_CCCR_ASM_MASK (0x4U) +#define MCAN_CCCR_ASM_SHIFT (2U) +#define MCAN_CCCR_ASM_SET(x) (((uint32_t)(x) << MCAN_CCCR_ASM_SHIFT) & MCAN_CCCR_ASM_MASK) +#define MCAN_CCCR_ASM_GET(x) (((uint32_t)(x) & MCAN_CCCR_ASM_MASK) >> MCAN_CCCR_ASM_SHIFT) + +/* + * CCE (RW) + * + * Configuration Change Enable + * 0= The CPU has no write access to the protected configuration registers + * 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) + */ +#define MCAN_CCCR_CCE_MASK (0x2U) +#define MCAN_CCCR_CCE_SHIFT (1U) +#define MCAN_CCCR_CCE_SET(x) (((uint32_t)(x) << MCAN_CCCR_CCE_SHIFT) & MCAN_CCCR_CCE_MASK) +#define MCAN_CCCR_CCE_GET(x) (((uint32_t)(x) & MCAN_CCCR_CCE_MASK) >> MCAN_CCCR_CCE_SHIFT) + +/* + * INIT (RW) + * + * Initialization + * 0= Normal Operation + * 1= Initialization is started + */ +#define MCAN_CCCR_INIT_MASK (0x1U) +#define MCAN_CCCR_INIT_SHIFT (0U) +#define MCAN_CCCR_INIT_SET(x) (((uint32_t)(x) << MCAN_CCCR_INIT_SHIFT) & MCAN_CCCR_INIT_MASK) +#define MCAN_CCCR_INIT_GET(x) (((uint32_t)(x) & MCAN_CCCR_INIT_MASK) >> MCAN_CCCR_INIT_SHIFT) + +/* Bitfield definition for register: NBTP */ +/* + * NSJW (RW) + * + * Nominal (Re)Synchronization Jump Width + * Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_NBTP_NSJW_MASK (0xFE000000UL) +#define MCAN_NBTP_NSJW_SHIFT (25U) +#define MCAN_NBTP_NSJW_SET(x) (((uint32_t)(x) << MCAN_NBTP_NSJW_SHIFT) & MCAN_NBTP_NSJW_MASK) +#define MCAN_NBTP_NSJW_GET(x) (((uint32_t)(x) & MCAN_NBTP_NSJW_MASK) >> MCAN_NBTP_NSJW_SHIFT) + +/* + * NBRP (RW) + * + * Nominal Bit Rate Prescaler + * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is + * such that one more than the value programmed here is used. + */ +#define MCAN_NBTP_NBRP_MASK (0x1FF0000UL) +#define MCAN_NBTP_NBRP_SHIFT (16U) +#define MCAN_NBTP_NBRP_SET(x) (((uint32_t)(x) << MCAN_NBTP_NBRP_SHIFT) & MCAN_NBTP_NBRP_MASK) +#define MCAN_NBTP_NBRP_GET(x) (((uint32_t)(x) & MCAN_NBTP_NBRP_MASK) >> MCAN_NBTP_NBRP_SHIFT) + +/* + * NTSEG1 (RW) + * + * Nominal Time segment before sample point + * Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_NBTP_NTSEG1_MASK (0xFF00U) +#define MCAN_NBTP_NTSEG1_SHIFT (8U) +#define MCAN_NBTP_NTSEG1_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG1_SHIFT) & MCAN_NBTP_NTSEG1_MASK) +#define MCAN_NBTP_NTSEG1_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG1_MASK) >> MCAN_NBTP_NTSEG1_SHIFT) + +/* + * NTSEG2 (RW) + * + * Nominal Time segment after sample point + * Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_NBTP_NTSEG2_MASK (0x7FU) +#define MCAN_NBTP_NTSEG2_SHIFT (0U) +#define MCAN_NBTP_NTSEG2_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG2_SHIFT) & MCAN_NBTP_NTSEG2_MASK) +#define MCAN_NBTP_NTSEG2_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG2_MASK) >> MCAN_NBTP_NTSEG2_SHIFT) + +/* Bitfield definition for register: TSCC */ +/* + * TCP (RW) + * + * Timestamp Counter Prescaler + * Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_TSCC_TCP_MASK (0xF0000UL) +#define MCAN_TSCC_TCP_SHIFT (16U) +#define MCAN_TSCC_TCP_SET(x) (((uint32_t)(x) << MCAN_TSCC_TCP_SHIFT) & MCAN_TSCC_TCP_MASK) +#define MCAN_TSCC_TCP_GET(x) (((uint32_t)(x) & MCAN_TSCC_TCP_MASK) >> MCAN_TSCC_TCP_SHIFT) + +/* + * TSS (RW) + * + * timestamp Select + * 00= Timestamp counter value always 0x0000 + * 01= Timestamp counter value incremented according to TCP + * 10= External timestamp counter value used + * 11= Same as “00” + */ +#define MCAN_TSCC_TSS_MASK (0x3U) +#define MCAN_TSCC_TSS_SHIFT (0U) +#define MCAN_TSCC_TSS_SET(x) (((uint32_t)(x) << MCAN_TSCC_TSS_SHIFT) & MCAN_TSCC_TSS_MASK) +#define MCAN_TSCC_TSS_GET(x) (((uint32_t)(x) & MCAN_TSCC_TSS_MASK) >> MCAN_TSCC_TSS_SHIFT) + +/* Bitfield definition for register: TSCV */ +/* + * TSC (RC) + * + * Timestamp Counter + * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + */ +#define MCAN_TSCV_TSC_MASK (0xFFFFU) +#define MCAN_TSCV_TSC_SHIFT (0U) +#define MCAN_TSCV_TSC_GET(x) (((uint32_t)(x) & MCAN_TSCV_TSC_MASK) >> MCAN_TSCV_TSC_SHIFT) + +/* Bitfield definition for register: TOCC */ +/* + * TOP (RW) + * + * Timeout Period + * Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + */ +#define MCAN_TOCC_TOP_MASK (0xFFFF0000UL) +#define MCAN_TOCC_TOP_SHIFT (16U) +#define MCAN_TOCC_TOP_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOP_SHIFT) & MCAN_TOCC_TOP_MASK) +#define MCAN_TOCC_TOP_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOP_MASK) >> MCAN_TOCC_TOP_SHIFT) + +/* + * TOS (RW) + * + * Timeout Select + * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. + * 00= Continuous operation + * 01= Timeout controlled by Tx Event FIFO + * 10= Timeout controlled by Rx FIFO 0 + * 11= Timeout controlled by Rx FIFO 1 + */ +#define MCAN_TOCC_TOS_MASK (0x6U) +#define MCAN_TOCC_TOS_SHIFT (1U) +#define MCAN_TOCC_TOS_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOS_SHIFT) & MCAN_TOCC_TOS_MASK) +#define MCAN_TOCC_TOS_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOS_MASK) >> MCAN_TOCC_TOS_SHIFT) + +/* + * RP (RW) + * + * Enable Timeout Counter + * 0= Timeout Counter disabled + * 1= Timeout Counter enabled + */ +#define MCAN_TOCC_RP_MASK (0x1U) +#define MCAN_TOCC_RP_SHIFT (0U) +#define MCAN_TOCC_RP_SET(x) (((uint32_t)(x) << MCAN_TOCC_RP_SHIFT) & MCAN_TOCC_RP_MASK) +#define MCAN_TOCC_RP_GET(x) (((uint32_t)(x) & MCAN_TOCC_RP_MASK) >> MCAN_TOCC_RP_SHIFT) + +/* Bitfield definition for register: TOCV */ +/* + * TOC (RC) + * + * Timeout Counter + * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. + */ +#define MCAN_TOCV_TOC_MASK (0xFFFFU) +#define MCAN_TOCV_TOC_SHIFT (0U) +#define MCAN_TOCV_TOC_GET(x) (((uint32_t)(x) & MCAN_TOCV_TOC_MASK) >> MCAN_TOCV_TOC_SHIFT) + +/* Bitfield definition for register: ECR */ +/* + * CEL (X) + * + * CAN Error Logging + * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. + * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. + * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. + */ +#define MCAN_ECR_CEL_MASK (0xFF0000UL) +#define MCAN_ECR_CEL_SHIFT (16U) +#define MCAN_ECR_CEL_GET(x) (((uint32_t)(x) & MCAN_ECR_CEL_MASK) >> MCAN_ECR_CEL_SHIFT) + +/* + * RP (R) + * + * Receive Error Passive + * 0= The Receive Error Counter is below the error passive level of 128 + * 1= The Receive Error Counter has reached the error passive level of 128 + */ +#define MCAN_ECR_RP_MASK (0x8000U) +#define MCAN_ECR_RP_SHIFT (15U) +#define MCAN_ECR_RP_GET(x) (((uint32_t)(x) & MCAN_ECR_RP_MASK) >> MCAN_ECR_RP_SHIFT) + +/* + * REC (R) + * + * Receive Error Counter + * Actual state of the Receive Error Counter, values between 0 and 127 + */ +#define MCAN_ECR_REC_MASK (0x7F00U) +#define MCAN_ECR_REC_SHIFT (8U) +#define MCAN_ECR_REC_GET(x) (((uint32_t)(x) & MCAN_ECR_REC_MASK) >> MCAN_ECR_REC_SHIFT) + +/* + * TEC (R) + * + * Transmit Error Counter + * Actual state of the Transmit Error Counter, values between 0 and 255 + * Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + */ +#define MCAN_ECR_TEC_MASK (0xFFU) +#define MCAN_ECR_TEC_SHIFT (0U) +#define MCAN_ECR_TEC_GET(x) (((uint32_t)(x) & MCAN_ECR_TEC_MASK) >> MCAN_ECR_TEC_SHIFT) + +/* Bitfield definition for register: PSR */ +/* + * TDCV (R) + * + * Transmitter Delay Compensation Value + * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + */ +#define MCAN_PSR_TDCV_MASK (0x7F0000UL) +#define MCAN_PSR_TDCV_SHIFT (16U) +#define MCAN_PSR_TDCV_GET(x) (((uint32_t)(x) & MCAN_PSR_TDCV_MASK) >> MCAN_PSR_TDCV_SHIFT) + +/* + * PXE (X) + * + * Protocol Exception Event + * 0= No protocol exception event occurred since last read access + * 1= Protocol exception event occurred + * Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_PXE_MASK (0x4000U) +#define MCAN_PSR_PXE_SHIFT (14U) +#define MCAN_PSR_PXE_GET(x) (((uint32_t)(x) & MCAN_PSR_PXE_MASK) >> MCAN_PSR_PXE_SHIFT) + +/* + * RFDF (X) + * + * Received a CAN FD Message + * This bit is set independent of acceptance filtering. + * 0= Since this bit was reset by the CPU, no CAN FD message has been received + * 1= Message in CAN FD format with FDF flag set has been received + * Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_RFDF_MASK (0x2000U) +#define MCAN_PSR_RFDF_SHIFT (13U) +#define MCAN_PSR_RFDF_GET(x) (((uint32_t)(x) & MCAN_PSR_RFDF_MASK) >> MCAN_PSR_RFDF_SHIFT) + +/* + * RBRS (X) + * + * BRS flag of last received CAN FD Message + * This bit is set together with RFDF, independent of acceptance filtering. + * 0= Last received CAN FD message did not have its BRS flag set + * 1= Last received CAN FD message had its BRS flag set + * Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_RBRS_MASK (0x1000U) +#define MCAN_PSR_RBRS_SHIFT (12U) +#define MCAN_PSR_RBRS_GET(x) (((uint32_t)(x) & MCAN_PSR_RBRS_MASK) >> MCAN_PSR_RBRS_SHIFT) + +/* + * RESI (X) + * + * ESI flag of last received CAN FD Message + * This bit is set together with RFDF, independent of acceptance filtering. + * 0= Last received CAN FD message did not have its ESI flag set + * 1= Last received CAN FD message had its ESI flag set + * Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_RESI_MASK (0x800U) +#define MCAN_PSR_RESI_SHIFT (11U) +#define MCAN_PSR_RESI_GET(x) (((uint32_t)(x) & MCAN_PSR_RESI_MASK) >> MCAN_PSR_RESI_SHIFT) + +/* + * DLEC (S) + * + * Data Phase Last Error Code + * Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with + * its BRS flag set has been transferred (reception or transmission) without error. + * Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_DLEC_MASK (0x700U) +#define MCAN_PSR_DLEC_SHIFT (8U) +#define MCAN_PSR_DLEC_GET(x) (((uint32_t)(x) & MCAN_PSR_DLEC_MASK) >> MCAN_PSR_DLEC_SHIFT) + +/* + * BO (R) + * + * Bus_Off Status + * 0= The M_CAN is not Bus_Off + * 1= The M_CAN is in Bus_Off state + */ +#define MCAN_PSR_BO_MASK (0x80U) +#define MCAN_PSR_BO_SHIFT (7U) +#define MCAN_PSR_BO_GET(x) (((uint32_t)(x) & MCAN_PSR_BO_MASK) >> MCAN_PSR_BO_SHIFT) + +/* + * EW (R) + * + * Warning Status + * 0= Both error counters are below the Error_Warning limit of 96 + * 1= At least one of error counter has reached the Error_Warning limit of 96 + */ +#define MCAN_PSR_EW_MASK (0x40U) +#define MCAN_PSR_EW_SHIFT (6U) +#define MCAN_PSR_EW_GET(x) (((uint32_t)(x) & MCAN_PSR_EW_MASK) >> MCAN_PSR_EW_SHIFT) + +/* + * EP (R) + * + * Error Passive + * 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected + * 1= The M_CAN is in the Error_Passive state + */ +#define MCAN_PSR_EP_MASK (0x20U) +#define MCAN_PSR_EP_SHIFT (5U) +#define MCAN_PSR_EP_GET(x) (((uint32_t)(x) & MCAN_PSR_EP_MASK) >> MCAN_PSR_EP_SHIFT) + +/* + * ACT (R) + * + * Activity + * Monitors the module’s CAN communication state. + * 00= Synchronizing - node is synchronizing on CAN communication + * 01= Idle - node is neither receiver nor transmitter + * 10= Receiver - node is operating as receiver + * 11= Transmitter - node is operating as transmitter + * Note: ACT is set to “00” by a Protocol Exception Event. + */ +#define MCAN_PSR_ACT_MASK (0x18U) +#define MCAN_PSR_ACT_SHIFT (3U) +#define MCAN_PSR_ACT_GET(x) (((uint32_t)(x) & MCAN_PSR_ACT_MASK) >> MCAN_PSR_ACT_SHIFT) + +/* + * LEC (S) + * + * Last Error Code + * The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. + * 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. + * 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + * 2= Form Error: A fixed format part of a received frame has the wrong format. + * 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. + * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), + * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus + * value was dominant. + * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + * dominant or continuously disturbed). + * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. + * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. + * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. + * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. + * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_LEC_MASK (0x7U) +#define MCAN_PSR_LEC_SHIFT (0U) +#define MCAN_PSR_LEC_GET(x) (((uint32_t)(x) & MCAN_PSR_LEC_MASK) >> MCAN_PSR_LEC_SHIFT) + +/* Bitfield definition for register: TDCR */ +/* + * TDCO (RW) + * + * Transmitter Delay Compensation SSP Offset + * Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. + */ +#define MCAN_TDCR_TDCO_MASK (0x7F00U) +#define MCAN_TDCR_TDCO_SHIFT (8U) +#define MCAN_TDCR_TDCO_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCO_SHIFT) & MCAN_TDCR_TDCO_MASK) +#define MCAN_TDCR_TDCO_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCO_MASK) >> MCAN_TDCR_TDCO_SHIFT) + +/* + * TDCF (RW) + * + * Transmitter Delay Compensation Filter Window Length + * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + */ +#define MCAN_TDCR_TDCF_MASK (0x7FU) +#define MCAN_TDCR_TDCF_SHIFT (0U) +#define MCAN_TDCR_TDCF_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCF_SHIFT) & MCAN_TDCR_TDCF_MASK) +#define MCAN_TDCR_TDCF_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCF_MASK) >> MCAN_TDCR_TDCF_SHIFT) + +/* Bitfield definition for register: IR */ +/* + * ARA (RW) + * + * Access to Reserved Address + * 0= No access to reserved address occurred + * 1= Access to reserved address occurred + */ +#define MCAN_IR_ARA_MASK (0x20000000UL) +#define MCAN_IR_ARA_SHIFT (29U) +#define MCAN_IR_ARA_SET(x) (((uint32_t)(x) << MCAN_IR_ARA_SHIFT) & MCAN_IR_ARA_MASK) +#define MCAN_IR_ARA_GET(x) (((uint32_t)(x) & MCAN_IR_ARA_MASK) >> MCAN_IR_ARA_SHIFT) + +/* + * PED (RW) + * + * Protocol Error in Data Phase (Data Bit Time is used) + * 0= No protocol error in data phase + * 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + */ +#define MCAN_IR_PED_MASK (0x10000000UL) +#define MCAN_IR_PED_SHIFT (28U) +#define MCAN_IR_PED_SET(x) (((uint32_t)(x) << MCAN_IR_PED_SHIFT) & MCAN_IR_PED_MASK) +#define MCAN_IR_PED_GET(x) (((uint32_t)(x) & MCAN_IR_PED_MASK) >> MCAN_IR_PED_SHIFT) + +/* + * PEA (RW) + * + * Protocol Error in Arbitration Phase (Nominal Bit Time is used) + * 0= No protocol error in arbitration phase + * 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + */ +#define MCAN_IR_PEA_MASK (0x8000000UL) +#define MCAN_IR_PEA_SHIFT (27U) +#define MCAN_IR_PEA_SET(x) (((uint32_t)(x) << MCAN_IR_PEA_SHIFT) & MCAN_IR_PEA_MASK) +#define MCAN_IR_PEA_GET(x) (((uint32_t)(x) & MCAN_IR_PEA_MASK) >> MCAN_IR_PEA_SHIFT) + +/* + * WDI (RW) + * + * Watchdog Interrupt + * 0= No Message RAM Watchdog event occurred + * 1= Message RAM Watchdog event due to missing READY + */ +#define MCAN_IR_WDI_MASK (0x4000000UL) +#define MCAN_IR_WDI_SHIFT (26U) +#define MCAN_IR_WDI_SET(x) (((uint32_t)(x) << MCAN_IR_WDI_SHIFT) & MCAN_IR_WDI_MASK) +#define MCAN_IR_WDI_GET(x) (((uint32_t)(x) & MCAN_IR_WDI_MASK) >> MCAN_IR_WDI_SHIFT) + +/* + * BO (RW) + * + * Bus_Off Status + * 0= Bus_Off status unchanged + * 1= Bus_Off status changed + */ +#define MCAN_IR_BO_MASK (0x2000000UL) +#define MCAN_IR_BO_SHIFT (25U) +#define MCAN_IR_BO_SET(x) (((uint32_t)(x) << MCAN_IR_BO_SHIFT) & MCAN_IR_BO_MASK) +#define MCAN_IR_BO_GET(x) (((uint32_t)(x) & MCAN_IR_BO_MASK) >> MCAN_IR_BO_SHIFT) + +/* + * EW (RW) + * + * Warning Status + * 0= Error_Warning status unchanged + * 1= Error_Warning status changed + */ +#define MCAN_IR_EW_MASK (0x1000000UL) +#define MCAN_IR_EW_SHIFT (24U) +#define MCAN_IR_EW_SET(x) (((uint32_t)(x) << MCAN_IR_EW_SHIFT) & MCAN_IR_EW_MASK) +#define MCAN_IR_EW_GET(x) (((uint32_t)(x) & MCAN_IR_EW_MASK) >> MCAN_IR_EW_SHIFT) + +/* + * EP (RW) + * + * Error Passive + * 0= Error_Passive status unchanged + * 1= Error_Passive status changed + */ +#define MCAN_IR_EP_MASK (0x800000UL) +#define MCAN_IR_EP_SHIFT (23U) +#define MCAN_IR_EP_SET(x) (((uint32_t)(x) << MCAN_IR_EP_SHIFT) & MCAN_IR_EP_MASK) +#define MCAN_IR_EP_GET(x) (((uint32_t)(x) & MCAN_IR_EP_MASK) >> MCAN_IR_EP_SHIFT) + +/* + * ELO (RW) + * + * Error Logging Overflow + * 0= CAN Error Logging Counter did not overflow + * 1= Overflow of CAN Error Logging Counter occurred + */ +#define MCAN_IR_ELO_MASK (0x400000UL) +#define MCAN_IR_ELO_SHIFT (22U) +#define MCAN_IR_ELO_SET(x) (((uint32_t)(x) << MCAN_IR_ELO_SHIFT) & MCAN_IR_ELO_MASK) +#define MCAN_IR_ELO_GET(x) (((uint32_t)(x) & MCAN_IR_ELO_MASK) >> MCAN_IR_ELO_SHIFT) + +/* + * BEU (RW) + * + * Bit Error Uncorrected + * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. + * 0= No bit error detected when reading from Message RAM + * 1= Bit error detected, uncorrected (e.g. parity logic) + */ +#define MCAN_IR_BEU_MASK (0x200000UL) +#define MCAN_IR_BEU_SHIFT (21U) +#define MCAN_IR_BEU_SET(x) (((uint32_t)(x) << MCAN_IR_BEU_SHIFT) & MCAN_IR_BEU_MASK) +#define MCAN_IR_BEU_GET(x) (((uint32_t)(x) & MCAN_IR_BEU_MASK) >> MCAN_IR_BEU_SHIFT) + +/* + * BEC (RW) + * + * Bit Error Corrected + * Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. + * 0= No bit error detected when reading from Message RAM + * 1= Bit error detected and corrected (e.g. ECC) + */ +#define MCAN_IR_BEC_MASK (0x100000UL) +#define MCAN_IR_BEC_SHIFT (20U) +#define MCAN_IR_BEC_SET(x) (((uint32_t)(x) << MCAN_IR_BEC_SHIFT) & MCAN_IR_BEC_MASK) +#define MCAN_IR_BEC_GET(x) (((uint32_t)(x) & MCAN_IR_BEC_MASK) >> MCAN_IR_BEC_SHIFT) + +/* + * DRX (RW) + * + * Message stored to Dedicated Rx Buffer + * The flag is set whenever a received message has been stored into a dedicated Rx Buffer. + * 0= No Rx Buffer updated + * 1= At least one received message stored into an Rx Buffer + */ +#define MCAN_IR_DRX_MASK (0x80000UL) +#define MCAN_IR_DRX_SHIFT (19U) +#define MCAN_IR_DRX_SET(x) (((uint32_t)(x) << MCAN_IR_DRX_SHIFT) & MCAN_IR_DRX_MASK) +#define MCAN_IR_DRX_GET(x) (((uint32_t)(x) & MCAN_IR_DRX_MASK) >> MCAN_IR_DRX_SHIFT) + +/* + * TOO (RW) + * + * Timeout Occurred + * 0= No timeout + * 1= Timeout reached + */ +#define MCAN_IR_TOO_MASK (0x40000UL) +#define MCAN_IR_TOO_SHIFT (18U) +#define MCAN_IR_TOO_SET(x) (((uint32_t)(x) << MCAN_IR_TOO_SHIFT) & MCAN_IR_TOO_MASK) +#define MCAN_IR_TOO_GET(x) (((uint32_t)(x) & MCAN_IR_TOO_MASK) >> MCAN_IR_TOO_SHIFT) + +/* + * MRAF (RW) + * + * Message RAM Access Failure + * The flag is set, when the Rx Handler + * .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message + * storage is aborted and the Rx Handler starts processing of the following message. + * .was not able to write a message to the Message RAM. In this case message storage is aborted. + * In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. + * The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the + * M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. + * 0= No Message RAM access failure occurred + * 1= Message RAM access failure occurred + */ +#define MCAN_IR_MRAF_MASK (0x20000UL) +#define MCAN_IR_MRAF_SHIFT (17U) +#define MCAN_IR_MRAF_SET(x) (((uint32_t)(x) << MCAN_IR_MRAF_SHIFT) & MCAN_IR_MRAF_MASK) +#define MCAN_IR_MRAF_GET(x) (((uint32_t)(x) & MCAN_IR_MRAF_MASK) >> MCAN_IR_MRAF_SHIFT) + +/* + * TSW (RW) + * + * Timestamp Wraparound + * 0= No timestamp counter wrap-around + * 1= Timestamp counter wrapped around + */ +#define MCAN_IR_TSW_MASK (0x10000UL) +#define MCAN_IR_TSW_SHIFT (16U) +#define MCAN_IR_TSW_SET(x) (((uint32_t)(x) << MCAN_IR_TSW_SHIFT) & MCAN_IR_TSW_MASK) +#define MCAN_IR_TSW_GET(x) (((uint32_t)(x) & MCAN_IR_TSW_MASK) >> MCAN_IR_TSW_SHIFT) + +/* + * TEFL (RW) + * + * Tx Event FIFO Element Lost + * 0= No Tx Event FIFO element lost + * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + */ +#define MCAN_IR_TEFL_MASK (0x8000U) +#define MCAN_IR_TEFL_SHIFT (15U) +#define MCAN_IR_TEFL_SET(x) (((uint32_t)(x) << MCAN_IR_TEFL_SHIFT) & MCAN_IR_TEFL_MASK) +#define MCAN_IR_TEFL_GET(x) (((uint32_t)(x) & MCAN_IR_TEFL_MASK) >> MCAN_IR_TEFL_SHIFT) + +/* + * TEFF (RW) + * + * Tx Event FIFO Full + * 0= Tx Event FIFO not full + * 1= Tx Event FIFO full + */ +#define MCAN_IR_TEFF_MASK (0x4000U) +#define MCAN_IR_TEFF_SHIFT (14U) +#define MCAN_IR_TEFF_SET(x) (((uint32_t)(x) << MCAN_IR_TEFF_SHIFT) & MCAN_IR_TEFF_MASK) +#define MCAN_IR_TEFF_GET(x) (((uint32_t)(x) & MCAN_IR_TEFF_MASK) >> MCAN_IR_TEFF_SHIFT) + +/* + * TEFW (RW) + * + * Tx Event FIFO Watermark Reached + * 0= Tx Event FIFO fill level below watermark + * 1= Tx Event FIFO fill level reached watermark + */ +#define MCAN_IR_TEFW_MASK (0x2000U) +#define MCAN_IR_TEFW_SHIFT (13U) +#define MCAN_IR_TEFW_SET(x) (((uint32_t)(x) << MCAN_IR_TEFW_SHIFT) & MCAN_IR_TEFW_MASK) +#define MCAN_IR_TEFW_GET(x) (((uint32_t)(x) & MCAN_IR_TEFW_MASK) >> MCAN_IR_TEFW_SHIFT) + +/* + * TEFN (RW) + * + * Tx Event FIFO New Entry + * 0= Tx Event FIFO unchanged + * 1= Tx Handler wrote Tx Event FIFO element + */ +#define MCAN_IR_TEFN_MASK (0x1000U) +#define MCAN_IR_TEFN_SHIFT (12U) +#define MCAN_IR_TEFN_SET(x) (((uint32_t)(x) << MCAN_IR_TEFN_SHIFT) & MCAN_IR_TEFN_MASK) +#define MCAN_IR_TEFN_GET(x) (((uint32_t)(x) & MCAN_IR_TEFN_MASK) >> MCAN_IR_TEFN_SHIFT) + +/* + * TFE (RW) + * + * Tx FIFO Empty + * 0= Tx FIFO non-empty + * 1= Tx FIFO empty + */ +#define MCAN_IR_TFE_MASK (0x800U) +#define MCAN_IR_TFE_SHIFT (11U) +#define MCAN_IR_TFE_SET(x) (((uint32_t)(x) << MCAN_IR_TFE_SHIFT) & MCAN_IR_TFE_MASK) +#define MCAN_IR_TFE_GET(x) (((uint32_t)(x) & MCAN_IR_TFE_MASK) >> MCAN_IR_TFE_SHIFT) + +/* + * TCF (RW) + * + * Transmission Cancellation Finished + * 0= No transmission cancellation finished + * 1= Transmission cancellation finished + */ +#define MCAN_IR_TCF_MASK (0x400U) +#define MCAN_IR_TCF_SHIFT (10U) +#define MCAN_IR_TCF_SET(x) (((uint32_t)(x) << MCAN_IR_TCF_SHIFT) & MCAN_IR_TCF_MASK) +#define MCAN_IR_TCF_GET(x) (((uint32_t)(x) & MCAN_IR_TCF_MASK) >> MCAN_IR_TCF_SHIFT) + +/* + * TC (RW) + * + * Transmission Completed + * 0= No transmission completed + * 1= Transmission completed + */ +#define MCAN_IR_TC_MASK (0x200U) +#define MCAN_IR_TC_SHIFT (9U) +#define MCAN_IR_TC_SET(x) (((uint32_t)(x) << MCAN_IR_TC_SHIFT) & MCAN_IR_TC_MASK) +#define MCAN_IR_TC_GET(x) (((uint32_t)(x) & MCAN_IR_TC_MASK) >> MCAN_IR_TC_SHIFT) + +/* + * HPM (RW) + * + * High Priority Message + * 0= No high priority message received + * 1= High priority message received + */ +#define MCAN_IR_HPM_MASK (0x100U) +#define MCAN_IR_HPM_SHIFT (8U) +#define MCAN_IR_HPM_SET(x) (((uint32_t)(x) << MCAN_IR_HPM_SHIFT) & MCAN_IR_HPM_MASK) +#define MCAN_IR_HPM_GET(x) (((uint32_t)(x) & MCAN_IR_HPM_MASK) >> MCAN_IR_HPM_SHIFT) + +/* + * RF1L (RW) + * + * Rx FIFO 1 Message Lost + * 0= No Rx FIFO 1 message lost + * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + */ +#define MCAN_IR_RF1L_MASK (0x80U) +#define MCAN_IR_RF1L_SHIFT (7U) +#define MCAN_IR_RF1L_SET(x) (((uint32_t)(x) << MCAN_IR_RF1L_SHIFT) & MCAN_IR_RF1L_MASK) +#define MCAN_IR_RF1L_GET(x) (((uint32_t)(x) & MCAN_IR_RF1L_MASK) >> MCAN_IR_RF1L_SHIFT) + +/* + * RF1F (RW) + * + * Rx FIFO 1 Full + * 0= Rx FIFO 1 not full + * 1= Rx FIFO 1 full + */ +#define MCAN_IR_RF1F_MASK (0x40U) +#define MCAN_IR_RF1F_SHIFT (6U) +#define MCAN_IR_RF1F_SET(x) (((uint32_t)(x) << MCAN_IR_RF1F_SHIFT) & MCAN_IR_RF1F_MASK) +#define MCAN_IR_RF1F_GET(x) (((uint32_t)(x) & MCAN_IR_RF1F_MASK) >> MCAN_IR_RF1F_SHIFT) + +/* + * RF1W (RW) + * + * Rx FIFO 1 Watermark Reached + * 0= Rx FIFO 1 fill level below watermark + * 1= Rx FIFO 1 fill level reached watermark + */ +#define MCAN_IR_RF1W_MASK (0x20U) +#define MCAN_IR_RF1W_SHIFT (5U) +#define MCAN_IR_RF1W_SET(x) (((uint32_t)(x) << MCAN_IR_RF1W_SHIFT) & MCAN_IR_RF1W_MASK) +#define MCAN_IR_RF1W_GET(x) (((uint32_t)(x) & MCAN_IR_RF1W_MASK) >> MCAN_IR_RF1W_SHIFT) + +/* + * RF1N (RW) + * + * Rx FIFO 1 New Message + * 0= No new message written to Rx FIFO 1 + * 1= New message written to Rx FIFO 1 + */ +#define MCAN_IR_RF1N_MASK (0x10U) +#define MCAN_IR_RF1N_SHIFT (4U) +#define MCAN_IR_RF1N_SET(x) (((uint32_t)(x) << MCAN_IR_RF1N_SHIFT) & MCAN_IR_RF1N_MASK) +#define MCAN_IR_RF1N_GET(x) (((uint32_t)(x) & MCAN_IR_RF1N_MASK) >> MCAN_IR_RF1N_SHIFT) + +/* + * RF0L (RW) + * + * Rx FIFO 0 Message Lost + * 0= No Rx FIFO 0 message lost + * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + */ +#define MCAN_IR_RF0L_MASK (0x8U) +#define MCAN_IR_RF0L_SHIFT (3U) +#define MCAN_IR_RF0L_SET(x) (((uint32_t)(x) << MCAN_IR_RF0L_SHIFT) & MCAN_IR_RF0L_MASK) +#define MCAN_IR_RF0L_GET(x) (((uint32_t)(x) & MCAN_IR_RF0L_MASK) >> MCAN_IR_RF0L_SHIFT) + +/* + * RF0F (RW) + * + * Rx FIFO 0 Full + * 0= Rx FIFO 0 not full + * 1= Rx FIFO 0 full + */ +#define MCAN_IR_RF0F_MASK (0x4U) +#define MCAN_IR_RF0F_SHIFT (2U) +#define MCAN_IR_RF0F_SET(x) (((uint32_t)(x) << MCAN_IR_RF0F_SHIFT) & MCAN_IR_RF0F_MASK) +#define MCAN_IR_RF0F_GET(x) (((uint32_t)(x) & MCAN_IR_RF0F_MASK) >> MCAN_IR_RF0F_SHIFT) + +/* + * RF0W (RW) + * + * Rx FIFO 0 Watermark Reached + * 0= Rx FIFO 0 fill level below watermark + * 1= Rx FIFO 0 fill level reached watermark + */ +#define MCAN_IR_RF0W_MASK (0x2U) +#define MCAN_IR_RF0W_SHIFT (1U) +#define MCAN_IR_RF0W_SET(x) (((uint32_t)(x) << MCAN_IR_RF0W_SHIFT) & MCAN_IR_RF0W_MASK) +#define MCAN_IR_RF0W_GET(x) (((uint32_t)(x) & MCAN_IR_RF0W_MASK) >> MCAN_IR_RF0W_SHIFT) + +/* + * RF0N (RW) + * + * Rx FIFO 0 New Message + * 0= No new message written to Rx FIFO 0 + * 1= New message written to Rx FIFO 0 + */ +#define MCAN_IR_RF0N_MASK (0x1U) +#define MCAN_IR_RF0N_SHIFT (0U) +#define MCAN_IR_RF0N_SET(x) (((uint32_t)(x) << MCAN_IR_RF0N_SHIFT) & MCAN_IR_RF0N_MASK) +#define MCAN_IR_RF0N_GET(x) (((uint32_t)(x) & MCAN_IR_RF0N_MASK) >> MCAN_IR_RF0N_SHIFT) + +/* Bitfield definition for register: IE */ +/* + * ARAE (RW) + * + * Access to Reserved Address Enable + */ +#define MCAN_IE_ARAE_MASK (0x20000000UL) +#define MCAN_IE_ARAE_SHIFT (29U) +#define MCAN_IE_ARAE_SET(x) (((uint32_t)(x) << MCAN_IE_ARAE_SHIFT) & MCAN_IE_ARAE_MASK) +#define MCAN_IE_ARAE_GET(x) (((uint32_t)(x) & MCAN_IE_ARAE_MASK) >> MCAN_IE_ARAE_SHIFT) + +/* + * PEDE (RW) + * + * Protocol Error in Data Phase Enable + */ +#define MCAN_IE_PEDE_MASK (0x10000000UL) +#define MCAN_IE_PEDE_SHIFT (28U) +#define MCAN_IE_PEDE_SET(x) (((uint32_t)(x) << MCAN_IE_PEDE_SHIFT) & MCAN_IE_PEDE_MASK) +#define MCAN_IE_PEDE_GET(x) (((uint32_t)(x) & MCAN_IE_PEDE_MASK) >> MCAN_IE_PEDE_SHIFT) + +/* + * PEAE (RW) + * + * Protocol Error in Arbitration Phase Enable + */ +#define MCAN_IE_PEAE_MASK (0x8000000UL) +#define MCAN_IE_PEAE_SHIFT (27U) +#define MCAN_IE_PEAE_SET(x) (((uint32_t)(x) << MCAN_IE_PEAE_SHIFT) & MCAN_IE_PEAE_MASK) +#define MCAN_IE_PEAE_GET(x) (((uint32_t)(x) & MCAN_IE_PEAE_MASK) >> MCAN_IE_PEAE_SHIFT) + +/* + * WDIE (RW) + * + * Watchdog Interrupt Enable + */ +#define MCAN_IE_WDIE_MASK (0x4000000UL) +#define MCAN_IE_WDIE_SHIFT (26U) +#define MCAN_IE_WDIE_SET(x) (((uint32_t)(x) << MCAN_IE_WDIE_SHIFT) & MCAN_IE_WDIE_MASK) +#define MCAN_IE_WDIE_GET(x) (((uint32_t)(x) & MCAN_IE_WDIE_MASK) >> MCAN_IE_WDIE_SHIFT) + +/* + * BOE (RW) + * + * Bus_Off Status Interrupt Enable + */ +#define MCAN_IE_BOE_MASK (0x2000000UL) +#define MCAN_IE_BOE_SHIFT (25U) +#define MCAN_IE_BOE_SET(x) (((uint32_t)(x) << MCAN_IE_BOE_SHIFT) & MCAN_IE_BOE_MASK) +#define MCAN_IE_BOE_GET(x) (((uint32_t)(x) & MCAN_IE_BOE_MASK) >> MCAN_IE_BOE_SHIFT) + +/* + * EWE (RW) + * + * Warning Status Interrupt Enable + */ +#define MCAN_IE_EWE_MASK (0x1000000UL) +#define MCAN_IE_EWE_SHIFT (24U) +#define MCAN_IE_EWE_SET(x) (((uint32_t)(x) << MCAN_IE_EWE_SHIFT) & MCAN_IE_EWE_MASK) +#define MCAN_IE_EWE_GET(x) (((uint32_t)(x) & MCAN_IE_EWE_MASK) >> MCAN_IE_EWE_SHIFT) + +/* + * EPE (RW) + * + * Error Passive Interrupt Enable + */ +#define MCAN_IE_EPE_MASK (0x800000UL) +#define MCAN_IE_EPE_SHIFT (23U) +#define MCAN_IE_EPE_SET(x) (((uint32_t)(x) << MCAN_IE_EPE_SHIFT) & MCAN_IE_EPE_MASK) +#define MCAN_IE_EPE_GET(x) (((uint32_t)(x) & MCAN_IE_EPE_MASK) >> MCAN_IE_EPE_SHIFT) + +/* + * ELOE (RW) + * + * Error Logging Overflow Interrupt Enable + */ +#define MCAN_IE_ELOE_MASK (0x400000UL) +#define MCAN_IE_ELOE_SHIFT (22U) +#define MCAN_IE_ELOE_SET(x) (((uint32_t)(x) << MCAN_IE_ELOE_SHIFT) & MCAN_IE_ELOE_MASK) +#define MCAN_IE_ELOE_GET(x) (((uint32_t)(x) & MCAN_IE_ELOE_MASK) >> MCAN_IE_ELOE_SHIFT) + +/* + * BEUE (RW) + * + * Bit Error Uncorrected Interrupt Enable + */ +#define MCAN_IE_BEUE_MASK (0x200000UL) +#define MCAN_IE_BEUE_SHIFT (21U) +#define MCAN_IE_BEUE_SET(x) (((uint32_t)(x) << MCAN_IE_BEUE_SHIFT) & MCAN_IE_BEUE_MASK) +#define MCAN_IE_BEUE_GET(x) (((uint32_t)(x) & MCAN_IE_BEUE_MASK) >> MCAN_IE_BEUE_SHIFT) + +/* + * BECE (RW) + * + * Bit Error Corrected Interrupt Enable + */ +#define MCAN_IE_BECE_MASK (0x100000UL) +#define MCAN_IE_BECE_SHIFT (20U) +#define MCAN_IE_BECE_SET(x) (((uint32_t)(x) << MCAN_IE_BECE_SHIFT) & MCAN_IE_BECE_MASK) +#define MCAN_IE_BECE_GET(x) (((uint32_t)(x) & MCAN_IE_BECE_MASK) >> MCAN_IE_BECE_SHIFT) + +/* + * DRXE (RW) + * + * Message stored to Dedicated Rx Buffer Interrupt Enable + */ +#define MCAN_IE_DRXE_MASK (0x80000UL) +#define MCAN_IE_DRXE_SHIFT (19U) +#define MCAN_IE_DRXE_SET(x) (((uint32_t)(x) << MCAN_IE_DRXE_SHIFT) & MCAN_IE_DRXE_MASK) +#define MCAN_IE_DRXE_GET(x) (((uint32_t)(x) & MCAN_IE_DRXE_MASK) >> MCAN_IE_DRXE_SHIFT) + +/* + * TOOE (RW) + * + * Timeout Occurred Interrupt Enable + */ +#define MCAN_IE_TOOE_MASK (0x40000UL) +#define MCAN_IE_TOOE_SHIFT (18U) +#define MCAN_IE_TOOE_SET(x) (((uint32_t)(x) << MCAN_IE_TOOE_SHIFT) & MCAN_IE_TOOE_MASK) +#define MCAN_IE_TOOE_GET(x) (((uint32_t)(x) & MCAN_IE_TOOE_MASK) >> MCAN_IE_TOOE_SHIFT) + +/* + * MRAFE (RW) + * + * Message RAM Access Failure Interrupt Enable + */ +#define MCAN_IE_MRAFE_MASK (0x20000UL) +#define MCAN_IE_MRAFE_SHIFT (17U) +#define MCAN_IE_MRAFE_SET(x) (((uint32_t)(x) << MCAN_IE_MRAFE_SHIFT) & MCAN_IE_MRAFE_MASK) +#define MCAN_IE_MRAFE_GET(x) (((uint32_t)(x) & MCAN_IE_MRAFE_MASK) >> MCAN_IE_MRAFE_SHIFT) + +/* + * TSWE (RW) + * + * Timestamp Wraparound Interrupt Enable + */ +#define MCAN_IE_TSWE_MASK (0x10000UL) +#define MCAN_IE_TSWE_SHIFT (16U) +#define MCAN_IE_TSWE_SET(x) (((uint32_t)(x) << MCAN_IE_TSWE_SHIFT) & MCAN_IE_TSWE_MASK) +#define MCAN_IE_TSWE_GET(x) (((uint32_t)(x) & MCAN_IE_TSWE_MASK) >> MCAN_IE_TSWE_SHIFT) + +/* + * TEFLE (RW) + * + * Tx Event FIFO Event Lost Interrupt Enable + */ +#define MCAN_IE_TEFLE_MASK (0x8000U) +#define MCAN_IE_TEFLE_SHIFT (15U) +#define MCAN_IE_TEFLE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFLE_SHIFT) & MCAN_IE_TEFLE_MASK) +#define MCAN_IE_TEFLE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFLE_MASK) >> MCAN_IE_TEFLE_SHIFT) + +/* + * TEFFE (RW) + * + * Tx Event FIFO Full Interrupt Enable + */ +#define MCAN_IE_TEFFE_MASK (0x4000U) +#define MCAN_IE_TEFFE_SHIFT (14U) +#define MCAN_IE_TEFFE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFFE_SHIFT) & MCAN_IE_TEFFE_MASK) +#define MCAN_IE_TEFFE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFFE_MASK) >> MCAN_IE_TEFFE_SHIFT) + +/* + * TEFWE (RW) + * + * Tx Event FIFO Watermark Reached Interrupt Enable + */ +#define MCAN_IE_TEFWE_MASK (0x2000U) +#define MCAN_IE_TEFWE_SHIFT (13U) +#define MCAN_IE_TEFWE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFWE_SHIFT) & MCAN_IE_TEFWE_MASK) +#define MCAN_IE_TEFWE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFWE_MASK) >> MCAN_IE_TEFWE_SHIFT) + +/* + * TEFNE (RW) + * + * Tx Event FIFO New Entry Interrupt Enable + */ +#define MCAN_IE_TEFNE_MASK (0x1000U) +#define MCAN_IE_TEFNE_SHIFT (12U) +#define MCAN_IE_TEFNE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFNE_SHIFT) & MCAN_IE_TEFNE_MASK) +#define MCAN_IE_TEFNE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFNE_MASK) >> MCAN_IE_TEFNE_SHIFT) + +/* + * TFEE (RW) + * + * Tx FIFO Empty Interrupt Enable + */ +#define MCAN_IE_TFEE_MASK (0x800U) +#define MCAN_IE_TFEE_SHIFT (11U) +#define MCAN_IE_TFEE_SET(x) (((uint32_t)(x) << MCAN_IE_TFEE_SHIFT) & MCAN_IE_TFEE_MASK) +#define MCAN_IE_TFEE_GET(x) (((uint32_t)(x) & MCAN_IE_TFEE_MASK) >> MCAN_IE_TFEE_SHIFT) + +/* + * TCFE (RW) + * + * Transmission Cancellation Finished Interrupt Enable + */ +#define MCAN_IE_TCFE_MASK (0x400U) +#define MCAN_IE_TCFE_SHIFT (10U) +#define MCAN_IE_TCFE_SET(x) (((uint32_t)(x) << MCAN_IE_TCFE_SHIFT) & MCAN_IE_TCFE_MASK) +#define MCAN_IE_TCFE_GET(x) (((uint32_t)(x) & MCAN_IE_TCFE_MASK) >> MCAN_IE_TCFE_SHIFT) + +/* + * TCE (RW) + * + * Transmission Completed Interrupt Enable + */ +#define MCAN_IE_TCE_MASK (0x200U) +#define MCAN_IE_TCE_SHIFT (9U) +#define MCAN_IE_TCE_SET(x) (((uint32_t)(x) << MCAN_IE_TCE_SHIFT) & MCAN_IE_TCE_MASK) +#define MCAN_IE_TCE_GET(x) (((uint32_t)(x) & MCAN_IE_TCE_MASK) >> MCAN_IE_TCE_SHIFT) + +/* + * HPME (RW) + * + * High Priority Message Interrupt Enable + */ +#define MCAN_IE_HPME_MASK (0x100U) +#define MCAN_IE_HPME_SHIFT (8U) +#define MCAN_IE_HPME_SET(x) (((uint32_t)(x) << MCAN_IE_HPME_SHIFT) & MCAN_IE_HPME_MASK) +#define MCAN_IE_HPME_GET(x) (((uint32_t)(x) & MCAN_IE_HPME_MASK) >> MCAN_IE_HPME_SHIFT) + +/* + * RF1LE (RW) + * + * Rx FIFO 1 Message Lost Interrupt Enable + */ +#define MCAN_IE_RF1LE_MASK (0x80U) +#define MCAN_IE_RF1LE_SHIFT (7U) +#define MCAN_IE_RF1LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1LE_SHIFT) & MCAN_IE_RF1LE_MASK) +#define MCAN_IE_RF1LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1LE_MASK) >> MCAN_IE_RF1LE_SHIFT) + +/* + * RF1FE (RW) + * + * Rx FIFO 1 Full Interrupt Enable + */ +#define MCAN_IE_RF1FE_MASK (0x40U) +#define MCAN_IE_RF1FE_SHIFT (6U) +#define MCAN_IE_RF1FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1FE_SHIFT) & MCAN_IE_RF1FE_MASK) +#define MCAN_IE_RF1FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1FE_MASK) >> MCAN_IE_RF1FE_SHIFT) + +/* + * RF1WE (RW) + * + * Rx FIFO 1 Watermark Reached Interrupt Enable + */ +#define MCAN_IE_RF1WE_MASK (0x20U) +#define MCAN_IE_RF1WE_SHIFT (5U) +#define MCAN_IE_RF1WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1WE_SHIFT) & MCAN_IE_RF1WE_MASK) +#define MCAN_IE_RF1WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1WE_MASK) >> MCAN_IE_RF1WE_SHIFT) + +/* + * RF1NE (RW) + * + * Rx FIFO 1 New Message Interrupt Enable + */ +#define MCAN_IE_RF1NE_MASK (0x10U) +#define MCAN_IE_RF1NE_SHIFT (4U) +#define MCAN_IE_RF1NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1NE_SHIFT) & MCAN_IE_RF1NE_MASK) +#define MCAN_IE_RF1NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1NE_MASK) >> MCAN_IE_RF1NE_SHIFT) + +/* + * RF0LE (RW) + * + * Rx FIFO 0 Message Lost Interrupt Enable + */ +#define MCAN_IE_RF0LE_MASK (0x8U) +#define MCAN_IE_RF0LE_SHIFT (3U) +#define MCAN_IE_RF0LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0LE_SHIFT) & MCAN_IE_RF0LE_MASK) +#define MCAN_IE_RF0LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0LE_MASK) >> MCAN_IE_RF0LE_SHIFT) + +/* + * RF0FE (RW) + * + * Rx FIFO 0 Full Interrupt Enable + */ +#define MCAN_IE_RF0FE_MASK (0x4U) +#define MCAN_IE_RF0FE_SHIFT (2U) +#define MCAN_IE_RF0FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0FE_SHIFT) & MCAN_IE_RF0FE_MASK) +#define MCAN_IE_RF0FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0FE_MASK) >> MCAN_IE_RF0FE_SHIFT) + +/* + * RF0WE (RW) + * + * Rx FIFO 0 Watermark Reached Interrupt Enable + */ +#define MCAN_IE_RF0WE_MASK (0x2U) +#define MCAN_IE_RF0WE_SHIFT (1U) +#define MCAN_IE_RF0WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0WE_SHIFT) & MCAN_IE_RF0WE_MASK) +#define MCAN_IE_RF0WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0WE_MASK) >> MCAN_IE_RF0WE_SHIFT) + +/* + * RF0NE (RW) + * + * Rx FIFO 0 New Message Interrupt Enable + */ +#define MCAN_IE_RF0NE_MASK (0x1U) +#define MCAN_IE_RF0NE_SHIFT (0U) +#define MCAN_IE_RF0NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0NE_SHIFT) & MCAN_IE_RF0NE_MASK) +#define MCAN_IE_RF0NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0NE_MASK) >> MCAN_IE_RF0NE_SHIFT) + +/* Bitfield definition for register: ILS */ +/* + * ARAL (RW) + * + * Access to Reserved Address Line + */ +#define MCAN_ILS_ARAL_MASK (0x20000000UL) +#define MCAN_ILS_ARAL_SHIFT (29U) +#define MCAN_ILS_ARAL_SET(x) (((uint32_t)(x) << MCAN_ILS_ARAL_SHIFT) & MCAN_ILS_ARAL_MASK) +#define MCAN_ILS_ARAL_GET(x) (((uint32_t)(x) & MCAN_ILS_ARAL_MASK) >> MCAN_ILS_ARAL_SHIFT) + +/* + * PEDL (RW) + * + * Protocol Error in Data Phase Line + */ +#define MCAN_ILS_PEDL_MASK (0x10000000UL) +#define MCAN_ILS_PEDL_SHIFT (28U) +#define MCAN_ILS_PEDL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEDL_SHIFT) & MCAN_ILS_PEDL_MASK) +#define MCAN_ILS_PEDL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEDL_MASK) >> MCAN_ILS_PEDL_SHIFT) + +/* + * PEAL (RW) + * + * Protocol Error in Arbitration Phase Line + */ +#define MCAN_ILS_PEAL_MASK (0x8000000UL) +#define MCAN_ILS_PEAL_SHIFT (27U) +#define MCAN_ILS_PEAL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEAL_SHIFT) & MCAN_ILS_PEAL_MASK) +#define MCAN_ILS_PEAL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEAL_MASK) >> MCAN_ILS_PEAL_SHIFT) + +/* + * WDIL (RW) + * + * Watchdog Interrupt Line + */ +#define MCAN_ILS_WDIL_MASK (0x4000000UL) +#define MCAN_ILS_WDIL_SHIFT (26U) +#define MCAN_ILS_WDIL_SET(x) (((uint32_t)(x) << MCAN_ILS_WDIL_SHIFT) & MCAN_ILS_WDIL_MASK) +#define MCAN_ILS_WDIL_GET(x) (((uint32_t)(x) & MCAN_ILS_WDIL_MASK) >> MCAN_ILS_WDIL_SHIFT) + +/* + * BOL (RW) + * + * Bus_Off Status Interrupt Line + */ +#define MCAN_ILS_BOL_MASK (0x2000000UL) +#define MCAN_ILS_BOL_SHIFT (25U) +#define MCAN_ILS_BOL_SET(x) (((uint32_t)(x) << MCAN_ILS_BOL_SHIFT) & MCAN_ILS_BOL_MASK) +#define MCAN_ILS_BOL_GET(x) (((uint32_t)(x) & MCAN_ILS_BOL_MASK) >> MCAN_ILS_BOL_SHIFT) + +/* + * EWL (RW) + * + * Warning Status Interrupt Line + */ +#define MCAN_ILS_EWL_MASK (0x1000000UL) +#define MCAN_ILS_EWL_SHIFT (24U) +#define MCAN_ILS_EWL_SET(x) (((uint32_t)(x) << MCAN_ILS_EWL_SHIFT) & MCAN_ILS_EWL_MASK) +#define MCAN_ILS_EWL_GET(x) (((uint32_t)(x) & MCAN_ILS_EWL_MASK) >> MCAN_ILS_EWL_SHIFT) + +/* + * EPL (RW) + * + * Error Passive Interrupt Line + */ +#define MCAN_ILS_EPL_MASK (0x800000UL) +#define MCAN_ILS_EPL_SHIFT (23U) +#define MCAN_ILS_EPL_SET(x) (((uint32_t)(x) << MCAN_ILS_EPL_SHIFT) & MCAN_ILS_EPL_MASK) +#define MCAN_ILS_EPL_GET(x) (((uint32_t)(x) & MCAN_ILS_EPL_MASK) >> MCAN_ILS_EPL_SHIFT) + +/* + * ELOL (RW) + * + * Error Logging Overflow Interrupt Line + */ +#define MCAN_ILS_ELOL_MASK (0x400000UL) +#define MCAN_ILS_ELOL_SHIFT (22U) +#define MCAN_ILS_ELOL_SET(x) (((uint32_t)(x) << MCAN_ILS_ELOL_SHIFT) & MCAN_ILS_ELOL_MASK) +#define MCAN_ILS_ELOL_GET(x) (((uint32_t)(x) & MCAN_ILS_ELOL_MASK) >> MCAN_ILS_ELOL_SHIFT) + +/* + * BEUL (RW) + * + * Bit Error Uncorrected Interrupt Line + */ +#define MCAN_ILS_BEUL_MASK (0x200000UL) +#define MCAN_ILS_BEUL_SHIFT (21U) +#define MCAN_ILS_BEUL_SET(x) (((uint32_t)(x) << MCAN_ILS_BEUL_SHIFT) & MCAN_ILS_BEUL_MASK) +#define MCAN_ILS_BEUL_GET(x) (((uint32_t)(x) & MCAN_ILS_BEUL_MASK) >> MCAN_ILS_BEUL_SHIFT) + +/* + * BECL (RW) + * + * Bit Error Corrected Interrupt Line + */ +#define MCAN_ILS_BECL_MASK (0x100000UL) +#define MCAN_ILS_BECL_SHIFT (20U) +#define MCAN_ILS_BECL_SET(x) (((uint32_t)(x) << MCAN_ILS_BECL_SHIFT) & MCAN_ILS_BECL_MASK) +#define MCAN_ILS_BECL_GET(x) (((uint32_t)(x) & MCAN_ILS_BECL_MASK) >> MCAN_ILS_BECL_SHIFT) + +/* + * DRXL (RW) + * + * Message stored to Dedicated Rx Buffer Interrupt Line + */ +#define MCAN_ILS_DRXL_MASK (0x80000UL) +#define MCAN_ILS_DRXL_SHIFT (19U) +#define MCAN_ILS_DRXL_SET(x) (((uint32_t)(x) << MCAN_ILS_DRXL_SHIFT) & MCAN_ILS_DRXL_MASK) +#define MCAN_ILS_DRXL_GET(x) (((uint32_t)(x) & MCAN_ILS_DRXL_MASK) >> MCAN_ILS_DRXL_SHIFT) + +/* + * TOOL (RW) + * + * Timeout Occurred Interrupt Line + */ +#define MCAN_ILS_TOOL_MASK (0x40000UL) +#define MCAN_ILS_TOOL_SHIFT (18U) +#define MCAN_ILS_TOOL_SET(x) (((uint32_t)(x) << MCAN_ILS_TOOL_SHIFT) & MCAN_ILS_TOOL_MASK) +#define MCAN_ILS_TOOL_GET(x) (((uint32_t)(x) & MCAN_ILS_TOOL_MASK) >> MCAN_ILS_TOOL_SHIFT) + +/* + * MRAFL (RW) + * + * Message RAM Access Failure Interrupt Line + */ +#define MCAN_ILS_MRAFL_MASK (0x20000UL) +#define MCAN_ILS_MRAFL_SHIFT (17U) +#define MCAN_ILS_MRAFL_SET(x) (((uint32_t)(x) << MCAN_ILS_MRAFL_SHIFT) & MCAN_ILS_MRAFL_MASK) +#define MCAN_ILS_MRAFL_GET(x) (((uint32_t)(x) & MCAN_ILS_MRAFL_MASK) >> MCAN_ILS_MRAFL_SHIFT) + +/* + * TSWL (RW) + * + * Timestamp Wraparound Interrupt Line + */ +#define MCAN_ILS_TSWL_MASK (0x10000UL) +#define MCAN_ILS_TSWL_SHIFT (16U) +#define MCAN_ILS_TSWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TSWL_SHIFT) & MCAN_ILS_TSWL_MASK) +#define MCAN_ILS_TSWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TSWL_MASK) >> MCAN_ILS_TSWL_SHIFT) + +/* + * TEFLL (RW) + * + * Tx Event FIFO Event Lost Interrupt Line + */ +#define MCAN_ILS_TEFLL_MASK (0x8000U) +#define MCAN_ILS_TEFLL_SHIFT (15U) +#define MCAN_ILS_TEFLL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFLL_SHIFT) & MCAN_ILS_TEFLL_MASK) +#define MCAN_ILS_TEFLL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFLL_MASK) >> MCAN_ILS_TEFLL_SHIFT) + +/* + * TEFFL (RW) + * + * Tx Event FIFO Full Interrupt Line + */ +#define MCAN_ILS_TEFFL_MASK (0x4000U) +#define MCAN_ILS_TEFFL_SHIFT (14U) +#define MCAN_ILS_TEFFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFFL_SHIFT) & MCAN_ILS_TEFFL_MASK) +#define MCAN_ILS_TEFFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFFL_MASK) >> MCAN_ILS_TEFFL_SHIFT) + +/* + * TEFWL (RW) + * + * Tx Event FIFO Watermark Reached Interrupt Line + */ +#define MCAN_ILS_TEFWL_MASK (0x2000U) +#define MCAN_ILS_TEFWL_SHIFT (13U) +#define MCAN_ILS_TEFWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFWL_SHIFT) & MCAN_ILS_TEFWL_MASK) +#define MCAN_ILS_TEFWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFWL_MASK) >> MCAN_ILS_TEFWL_SHIFT) + +/* + * TEFNL (RW) + * + * Tx Event FIFO New Entry Interrupt Line + */ +#define MCAN_ILS_TEFNL_MASK (0x1000U) +#define MCAN_ILS_TEFNL_SHIFT (12U) +#define MCAN_ILS_TEFNL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFNL_SHIFT) & MCAN_ILS_TEFNL_MASK) +#define MCAN_ILS_TEFNL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFNL_MASK) >> MCAN_ILS_TEFNL_SHIFT) + +/* + * TFEL (RW) + * + * Tx FIFO Empty Interrupt Line + */ +#define MCAN_ILS_TFEL_MASK (0x800U) +#define MCAN_ILS_TFEL_SHIFT (11U) +#define MCAN_ILS_TFEL_SET(x) (((uint32_t)(x) << MCAN_ILS_TFEL_SHIFT) & MCAN_ILS_TFEL_MASK) +#define MCAN_ILS_TFEL_GET(x) (((uint32_t)(x) & MCAN_ILS_TFEL_MASK) >> MCAN_ILS_TFEL_SHIFT) + +/* + * TCFL (RW) + * + * Transmission Cancellation Finished Interrupt Line + */ +#define MCAN_ILS_TCFL_MASK (0x400U) +#define MCAN_ILS_TCFL_SHIFT (10U) +#define MCAN_ILS_TCFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCFL_SHIFT) & MCAN_ILS_TCFL_MASK) +#define MCAN_ILS_TCFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCFL_MASK) >> MCAN_ILS_TCFL_SHIFT) + +/* + * TCL (RW) + * + * Transmission Completed Interrupt Line + */ +#define MCAN_ILS_TCL_MASK (0x200U) +#define MCAN_ILS_TCL_SHIFT (9U) +#define MCAN_ILS_TCL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCL_SHIFT) & MCAN_ILS_TCL_MASK) +#define MCAN_ILS_TCL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCL_MASK) >> MCAN_ILS_TCL_SHIFT) + +/* + * HPML (RW) + * + * High Priority Message Interrupt Line + */ +#define MCAN_ILS_HPML_MASK (0x100U) +#define MCAN_ILS_HPML_SHIFT (8U) +#define MCAN_ILS_HPML_SET(x) (((uint32_t)(x) << MCAN_ILS_HPML_SHIFT) & MCAN_ILS_HPML_MASK) +#define MCAN_ILS_HPML_GET(x) (((uint32_t)(x) & MCAN_ILS_HPML_MASK) >> MCAN_ILS_HPML_SHIFT) + +/* + * RF1LL (RW) + * + * Rx FIFO 1 Message Lost Interrupt Line + */ +#define MCAN_ILS_RF1LL_MASK (0x80U) +#define MCAN_ILS_RF1LL_SHIFT (7U) +#define MCAN_ILS_RF1LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1LL_SHIFT) & MCAN_ILS_RF1LL_MASK) +#define MCAN_ILS_RF1LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1LL_MASK) >> MCAN_ILS_RF1LL_SHIFT) + +/* + * RF1FL (RW) + * + * Rx FIFO 1 Full Interrupt Line + */ +#define MCAN_ILS_RF1FL_MASK (0x40U) +#define MCAN_ILS_RF1FL_SHIFT (6U) +#define MCAN_ILS_RF1FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1FL_SHIFT) & MCAN_ILS_RF1FL_MASK) +#define MCAN_ILS_RF1FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1FL_MASK) >> MCAN_ILS_RF1FL_SHIFT) + +/* + * RF1WL (RW) + * + * Rx FIFO 1 Watermark Reached Interrupt Line + */ +#define MCAN_ILS_RF1WL_MASK (0x20U) +#define MCAN_ILS_RF1WL_SHIFT (5U) +#define MCAN_ILS_RF1WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1WL_SHIFT) & MCAN_ILS_RF1WL_MASK) +#define MCAN_ILS_RF1WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1WL_MASK) >> MCAN_ILS_RF1WL_SHIFT) + +/* + * RF1NL (RW) + * + * Rx FIFO 1 New Message Interrupt Line + */ +#define MCAN_ILS_RF1NL_MASK (0x10U) +#define MCAN_ILS_RF1NL_SHIFT (4U) +#define MCAN_ILS_RF1NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1NL_SHIFT) & MCAN_ILS_RF1NL_MASK) +#define MCAN_ILS_RF1NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1NL_MASK) >> MCAN_ILS_RF1NL_SHIFT) + +/* + * RF0LL (RW) + * + * Rx FIFO 0 Message Lost Interrupt Line + */ +#define MCAN_ILS_RF0LL_MASK (0x8U) +#define MCAN_ILS_RF0LL_SHIFT (3U) +#define MCAN_ILS_RF0LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0LL_SHIFT) & MCAN_ILS_RF0LL_MASK) +#define MCAN_ILS_RF0LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0LL_MASK) >> MCAN_ILS_RF0LL_SHIFT) + +/* + * RF0FL (RW) + * + * Rx FIFO 0 Full Interrupt Line + */ +#define MCAN_ILS_RF0FL_MASK (0x4U) +#define MCAN_ILS_RF0FL_SHIFT (2U) +#define MCAN_ILS_RF0FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0FL_SHIFT) & MCAN_ILS_RF0FL_MASK) +#define MCAN_ILS_RF0FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0FL_MASK) >> MCAN_ILS_RF0FL_SHIFT) + +/* + * RF0WL (RW) + * + * Rx FIFO 0 Watermark Reached Interrupt Line + */ +#define MCAN_ILS_RF0WL_MASK (0x2U) +#define MCAN_ILS_RF0WL_SHIFT (1U) +#define MCAN_ILS_RF0WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0WL_SHIFT) & MCAN_ILS_RF0WL_MASK) +#define MCAN_ILS_RF0WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0WL_MASK) >> MCAN_ILS_RF0WL_SHIFT) + +/* + * RF0NL (RW) + * + * Rx FIFO 0 New Message Interrupt Line + */ +#define MCAN_ILS_RF0NL_MASK (0x1U) +#define MCAN_ILS_RF0NL_SHIFT (0U) +#define MCAN_ILS_RF0NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0NL_SHIFT) & MCAN_ILS_RF0NL_MASK) +#define MCAN_ILS_RF0NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0NL_MASK) >> MCAN_ILS_RF0NL_SHIFT) + +/* Bitfield definition for register: ILE */ +/* + * EINT1 (RW) + * + * Enable Interrupt Line 1 + * 0= Interrupt line m_can_int1 disabled + * 1= Interrupt line m_can_int1 enabled + */ +#define MCAN_ILE_EINT1_MASK (0x2U) +#define MCAN_ILE_EINT1_SHIFT (1U) +#define MCAN_ILE_EINT1_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT1_SHIFT) & MCAN_ILE_EINT1_MASK) +#define MCAN_ILE_EINT1_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT1_MASK) >> MCAN_ILE_EINT1_SHIFT) + +/* + * EINT0 (RW) + * + * Enable Interrupt Line 0 + * 0= Interrupt line m_can_int0 disabled + * 1= Interrupt line m_can_int0 enabled + */ +#define MCAN_ILE_EINT0_MASK (0x1U) +#define MCAN_ILE_EINT0_SHIFT (0U) +#define MCAN_ILE_EINT0_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT0_SHIFT) & MCAN_ILE_EINT0_MASK) +#define MCAN_ILE_EINT0_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT0_MASK) >> MCAN_ILE_EINT0_SHIFT) + +/* Bitfield definition for register: GFC */ +/* + * ANFS (RW) + * + * Accept Non-matching Frames Standard + * Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. + * 00= Accept in Rx FIFO 0 + * 01= Accept in Rx FIFO 1 + * 10= Reject + * 11= Reject + */ +#define MCAN_GFC_ANFS_MASK (0x30U) +#define MCAN_GFC_ANFS_SHIFT (4U) +#define MCAN_GFC_ANFS_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFS_SHIFT) & MCAN_GFC_ANFS_MASK) +#define MCAN_GFC_ANFS_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFS_MASK) >> MCAN_GFC_ANFS_SHIFT) + +/* + * ANFE (RW) + * + * Accept Non-matching Frames Extended + * Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. + * 00= Accept in Rx FIFO 0 + * 01= Accept in Rx FIFO 1 + * 10= Reject + * 11= Reject + */ +#define MCAN_GFC_ANFE_MASK (0xCU) +#define MCAN_GFC_ANFE_SHIFT (2U) +#define MCAN_GFC_ANFE_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFE_SHIFT) & MCAN_GFC_ANFE_MASK) +#define MCAN_GFC_ANFE_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFE_MASK) >> MCAN_GFC_ANFE_SHIFT) + +/* + * RRFS (RW) + * + * Reject Remote Frames Standard + * 0= Filter remote frames with 11-bit standard IDs + * 1= Reject all remote frames with 11-bit standard IDs + */ +#define MCAN_GFC_RRFS_MASK (0x2U) +#define MCAN_GFC_RRFS_SHIFT (1U) +#define MCAN_GFC_RRFS_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFS_SHIFT) & MCAN_GFC_RRFS_MASK) +#define MCAN_GFC_RRFS_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFS_MASK) >> MCAN_GFC_RRFS_SHIFT) + +/* + * RRFE (RW) + * + * Reject Remote Frames Extended + * 0= Filter remote frames with 29-bit extended IDs + * 1= Reject all remote frames with 29-bit extended IDs + */ +#define MCAN_GFC_RRFE_MASK (0x1U) +#define MCAN_GFC_RRFE_SHIFT (0U) +#define MCAN_GFC_RRFE_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFE_SHIFT) & MCAN_GFC_RRFE_MASK) +#define MCAN_GFC_RRFE_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFE_MASK) >> MCAN_GFC_RRFE_SHIFT) + +/* Bitfield definition for register: SIDFC */ +/* + * LSS (RW) + * + * List Size Standard + * 0= No standard Message ID filter + * 1-128= Number of standard Message ID filter elements + * >128= Values greater than 128 are interpreted as 128 + */ +#define MCAN_SIDFC_LSS_MASK (0xFF0000UL) +#define MCAN_SIDFC_LSS_SHIFT (16U) +#define MCAN_SIDFC_LSS_SET(x) (((uint32_t)(x) << MCAN_SIDFC_LSS_SHIFT) & MCAN_SIDFC_LSS_MASK) +#define MCAN_SIDFC_LSS_GET(x) (((uint32_t)(x) & MCAN_SIDFC_LSS_MASK) >> MCAN_SIDFC_LSS_SHIFT) + +/* + * FLSSA (RW) + * + * Filter List Standard Start Address + * Start address of standard Message ID filter list (32-bit word address) + */ +#define MCAN_SIDFC_FLSSA_MASK (0xFFFCU) +#define MCAN_SIDFC_FLSSA_SHIFT (2U) +#define MCAN_SIDFC_FLSSA_SET(x) (((uint32_t)(x) << MCAN_SIDFC_FLSSA_SHIFT) & MCAN_SIDFC_FLSSA_MASK) +#define MCAN_SIDFC_FLSSA_GET(x) (((uint32_t)(x) & MCAN_SIDFC_FLSSA_MASK) >> MCAN_SIDFC_FLSSA_SHIFT) + +/* Bitfield definition for register: XIDFC */ +/* + * LSE (RW) + * + * List Size Extended + * 0= No extended Message ID filter + * 1-64= Number of extended Message ID filter elements + * >64= Values greater than 64 are interpreted as 64 + */ +#define MCAN_XIDFC_LSE_MASK (0x7F0000UL) +#define MCAN_XIDFC_LSE_SHIFT (16U) +#define MCAN_XIDFC_LSE_SET(x) (((uint32_t)(x) << MCAN_XIDFC_LSE_SHIFT) & MCAN_XIDFC_LSE_MASK) +#define MCAN_XIDFC_LSE_GET(x) (((uint32_t)(x) & MCAN_XIDFC_LSE_MASK) >> MCAN_XIDFC_LSE_SHIFT) + +/* + * FLESA (RW) + * + * Filter List Extended Start Address + * Start address of extended Message ID filter list (32-bit word address). + */ +#define MCAN_XIDFC_FLESA_MASK (0xFFFCU) +#define MCAN_XIDFC_FLESA_SHIFT (2U) +#define MCAN_XIDFC_FLESA_SET(x) (((uint32_t)(x) << MCAN_XIDFC_FLESA_SHIFT) & MCAN_XIDFC_FLESA_MASK) +#define MCAN_XIDFC_FLESA_GET(x) (((uint32_t)(x) & MCAN_XIDFC_FLESA_MASK) >> MCAN_XIDFC_FLESA_SHIFT) + +/* Bitfield definition for register: XIDAM */ +/* + * EIDM (RW) + * + * Extended ID Mask + * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + */ +#define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) +#define MCAN_XIDAM_EIDM_SHIFT (0U) +#define MCAN_XIDAM_EIDM_SET(x) (((uint32_t)(x) << MCAN_XIDAM_EIDM_SHIFT) & MCAN_XIDAM_EIDM_MASK) +#define MCAN_XIDAM_EIDM_GET(x) (((uint32_t)(x) & MCAN_XIDAM_EIDM_MASK) >> MCAN_XIDAM_EIDM_SHIFT) + +/* Bitfield definition for register: HPMS */ +/* + * FLST (R) + * + * Filter List + * Indicates the filter list of the matching filter element. + * 0= Standard Filter List + * 1= Extended Filter List + */ +#define MCAN_HPMS_FLST_MASK (0x8000U) +#define MCAN_HPMS_FLST_SHIFT (15U) +#define MCAN_HPMS_FLST_GET(x) (((uint32_t)(x) & MCAN_HPMS_FLST_MASK) >> MCAN_HPMS_FLST_SHIFT) + +/* + * FIDX (R) + * + * Filter Index + * Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + */ +#define MCAN_HPMS_FIDX_MASK (0x7F00U) +#define MCAN_HPMS_FIDX_SHIFT (8U) +#define MCAN_HPMS_FIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_FIDX_MASK) >> MCAN_HPMS_FIDX_SHIFT) + +/* + * MSI (R) + * + * Message Storage Indicator + * 00= No FIFO selected + * 01= FIFO message lost + * 10= Message stored in FIFO 0 + * 11= Message stored in FIFO 1 + */ +#define MCAN_HPMS_MSI_MASK (0xC0U) +#define MCAN_HPMS_MSI_SHIFT (6U) +#define MCAN_HPMS_MSI_GET(x) (((uint32_t)(x) & MCAN_HPMS_MSI_MASK) >> MCAN_HPMS_MSI_SHIFT) + +/* + * BIDX (R) + * + * Buffer Index + * Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. + */ +#define MCAN_HPMS_BIDX_MASK (0x3FU) +#define MCAN_HPMS_BIDX_SHIFT (0U) +#define MCAN_HPMS_BIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_BIDX_MASK) >> MCAN_HPMS_BIDX_SHIFT) + +/* Bitfield definition for register: NDAT1 */ +/* + * ND1 (RW) + * + * New Data[31:0] + * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * 0= Rx Buffer not updated + * 1= Rx Buffer updated from new message + */ +#define MCAN_NDAT1_ND1_MASK (0xFFFFFFFFUL) +#define MCAN_NDAT1_ND1_SHIFT (0U) +#define MCAN_NDAT1_ND1_SET(x) (((uint32_t)(x) << MCAN_NDAT1_ND1_SHIFT) & MCAN_NDAT1_ND1_MASK) +#define MCAN_NDAT1_ND1_GET(x) (((uint32_t)(x) & MCAN_NDAT1_ND1_MASK) >> MCAN_NDAT1_ND1_SHIFT) + +/* Bitfield definition for register: NDAT2 */ +/* + * ND2 (RW) + * + * New Data[63:32] + * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * 0= Rx Buffer not updated + * 1= Rx Buffer updated from new message + */ +#define MCAN_NDAT2_ND2_MASK (0xFFFFFFFFUL) +#define MCAN_NDAT2_ND2_SHIFT (0U) +#define MCAN_NDAT2_ND2_SET(x) (((uint32_t)(x) << MCAN_NDAT2_ND2_SHIFT) & MCAN_NDAT2_ND2_MASK) +#define MCAN_NDAT2_ND2_GET(x) (((uint32_t)(x) & MCAN_NDAT2_ND2_MASK) >> MCAN_NDAT2_ND2_SHIFT) + +/* Bitfield definition for register: RXF0C */ +/* + * F0OM (RW) + * + * FIFO 0 Operation Mode + * FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). + * 0= FIFO 0 blocking mode + * 1= FIFO 0 overwrite mode + */ +#define MCAN_RXF0C_F0OM_MASK (0x80000000UL) +#define MCAN_RXF0C_F0OM_SHIFT (31U) +#define MCAN_RXF0C_F0OM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0OM_SHIFT) & MCAN_RXF0C_F0OM_MASK) +#define MCAN_RXF0C_F0OM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0OM_MASK) >> MCAN_RXF0C_F0OM_SHIFT) + +/* + * F0WM (RW) + * + * Rx FIFO 0 Watermark + * 0= Watermark interrupt disabled + * 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) + * >64= Watermark interrupt disabled + */ +#define MCAN_RXF0C_F0WM_MASK (0x7F000000UL) +#define MCAN_RXF0C_F0WM_SHIFT (24U) +#define MCAN_RXF0C_F0WM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0WM_SHIFT) & MCAN_RXF0C_F0WM_MASK) +#define MCAN_RXF0C_F0WM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0WM_MASK) >> MCAN_RXF0C_F0WM_SHIFT) + +/* + * F0S (RW) + * + * Rx FIFO 0 Size + * 0= No Rx FIFO 0 + * 1-64= Number of Rx FIFO 0 elements + * >64= Values greater than 64 are interpreted as 64 + * The Rx FIFO 0 elements are indexed from 0 to F0S-1 + */ +#define MCAN_RXF0C_F0S_MASK (0x7F0000UL) +#define MCAN_RXF0C_F0S_SHIFT (16U) +#define MCAN_RXF0C_F0S_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0S_SHIFT) & MCAN_RXF0C_F0S_MASK) +#define MCAN_RXF0C_F0S_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0S_MASK) >> MCAN_RXF0C_F0S_SHIFT) + +/* + * F0SA (RW) + * + * Rx FIFO 0 Start Address + * Start address of Rx FIFO 0 in Message RAM (32-bit word address) + */ +#define MCAN_RXF0C_F0SA_MASK (0xFFFCU) +#define MCAN_RXF0C_F0SA_SHIFT (2U) +#define MCAN_RXF0C_F0SA_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0SA_SHIFT) & MCAN_RXF0C_F0SA_MASK) +#define MCAN_RXF0C_F0SA_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0SA_MASK) >> MCAN_RXF0C_F0SA_SHIFT) + +/* Bitfield definition for register: RXF0S */ +/* + * RF0L (R) + * + * Rx FIFO 0 Message Lost + * This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. + * 0= No Rx FIFO 0 message lost + * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + * Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. + */ +#define MCAN_RXF0S_RF0L_MASK (0x2000000UL) +#define MCAN_RXF0S_RF0L_SHIFT (25U) +#define MCAN_RXF0S_RF0L_GET(x) (((uint32_t)(x) & MCAN_RXF0S_RF0L_MASK) >> MCAN_RXF0S_RF0L_SHIFT) + +/* + * F0F (R) + * + * Rx FIFO 0 Full + * 0= Rx FIFO 0 not full + * 1= Rx FIFO 0 full + */ +#define MCAN_RXF0S_F0F_MASK (0x1000000UL) +#define MCAN_RXF0S_F0F_SHIFT (24U) +#define MCAN_RXF0S_F0F_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0F_MASK) >> MCAN_RXF0S_F0F_SHIFT) + +/* + * F0PI (R) + * + * Rx FIFO 0 Put Index + * Rx FIFO 0 write index pointer, range 0 to 63. + */ +#define MCAN_RXF0S_F0PI_MASK (0x3F0000UL) +#define MCAN_RXF0S_F0PI_SHIFT (16U) +#define MCAN_RXF0S_F0PI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0PI_MASK) >> MCAN_RXF0S_F0PI_SHIFT) + +/* + * F0GI (R) + * + * Rx FIFO 0 Get Index + * Rx FIFO 0 read index pointer, range 0 to 63. + */ +#define MCAN_RXF0S_F0GI_MASK (0x3F00U) +#define MCAN_RXF0S_F0GI_SHIFT (8U) +#define MCAN_RXF0S_F0GI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0GI_MASK) >> MCAN_RXF0S_F0GI_SHIFT) + +/* + * F0FL (R) + * + * Rx FIFO 0 Fill Level + * Number of elements stored in Rx FIFO 0, range 0 to 64. + */ +#define MCAN_RXF0S_F0FL_MASK (0x7FU) +#define MCAN_RXF0S_F0FL_SHIFT (0U) +#define MCAN_RXF0S_F0FL_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0FL_MASK) >> MCAN_RXF0S_F0FL_SHIFT) + +/* Bitfield definition for register: RXF0A */ +/* + * F0AI (RW) + * + * Rx FIFO 0 Acknowledge Index + * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + */ +#define MCAN_RXF0A_F0AI_MASK (0x3FU) +#define MCAN_RXF0A_F0AI_SHIFT (0U) +#define MCAN_RXF0A_F0AI_SET(x) (((uint32_t)(x) << MCAN_RXF0A_F0AI_SHIFT) & MCAN_RXF0A_F0AI_MASK) +#define MCAN_RXF0A_F0AI_GET(x) (((uint32_t)(x) & MCAN_RXF0A_F0AI_MASK) >> MCAN_RXF0A_F0AI_SHIFT) + +/* Bitfield definition for register: RXBC */ +/* + * RBSA (RW) + * + * Rx Buffer Start Address + * Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. + */ +#define MCAN_RXBC_RBSA_MASK (0xFFFCU) +#define MCAN_RXBC_RBSA_SHIFT (2U) +#define MCAN_RXBC_RBSA_SET(x) (((uint32_t)(x) << MCAN_RXBC_RBSA_SHIFT) & MCAN_RXBC_RBSA_MASK) +#define MCAN_RXBC_RBSA_GET(x) (((uint32_t)(x) & MCAN_RXBC_RBSA_MASK) >> MCAN_RXBC_RBSA_SHIFT) + +/* Bitfield definition for register: RXF1C */ +/* + * F1OM (RW) + * + * FIFO 1 Operation Mode + * FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). + * 0= FIFO 1 blocking mode + * 1= FIFO 1 overwrite mode + */ +#define MCAN_RXF1C_F1OM_MASK (0x80000000UL) +#define MCAN_RXF1C_F1OM_SHIFT (31U) +#define MCAN_RXF1C_F1OM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1OM_SHIFT) & MCAN_RXF1C_F1OM_MASK) +#define MCAN_RXF1C_F1OM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1OM_MASK) >> MCAN_RXF1C_F1OM_SHIFT) + +/* + * F1WM (RW) + * + * Rx FIFO 1 Watermark + * 0= Watermark interrupt disabled + * 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) + * >64= Watermark interrupt disabled + */ +#define MCAN_RXF1C_F1WM_MASK (0x7F000000UL) +#define MCAN_RXF1C_F1WM_SHIFT (24U) +#define MCAN_RXF1C_F1WM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1WM_SHIFT) & MCAN_RXF1C_F1WM_MASK) +#define MCAN_RXF1C_F1WM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1WM_MASK) >> MCAN_RXF1C_F1WM_SHIFT) + +/* + * F1S (RW) + * + * Rx FIFO 1 Size + * 0= No Rx FIFO 1 + * 1-64= Number of Rx FIFO 1 elements + * >64= Values greater than 64 are interpreted as 64 + * The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + */ +#define MCAN_RXF1C_F1S_MASK (0x7F0000UL) +#define MCAN_RXF1C_F1S_SHIFT (16U) +#define MCAN_RXF1C_F1S_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1S_SHIFT) & MCAN_RXF1C_F1S_MASK) +#define MCAN_RXF1C_F1S_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1S_MASK) >> MCAN_RXF1C_F1S_SHIFT) + +/* + * F1SA (RW) + * + * Rx FIFO 1 Start Address + * Start address of Rx FIFO 1 in Message RAM (32-bit word address) + */ +#define MCAN_RXF1C_F1SA_MASK (0xFFFCU) +#define MCAN_RXF1C_F1SA_SHIFT (2U) +#define MCAN_RXF1C_F1SA_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1SA_SHIFT) & MCAN_RXF1C_F1SA_MASK) +#define MCAN_RXF1C_F1SA_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1SA_MASK) >> MCAN_RXF1C_F1SA_SHIFT) + +/* Bitfield definition for register: RXF1S */ +/* + * DMS (R) + * + * Debug Message Status + * 00= Idle state, wait for reception of debug messages, DMA request is cleared + * 01= Debug message A received + * 10= Debug messages A, B received + * 11= Debug messages A, B, C received, DMA request is set + */ +#define MCAN_RXF1S_DMS_MASK (0xC0000000UL) +#define MCAN_RXF1S_DMS_SHIFT (30U) +#define MCAN_RXF1S_DMS_GET(x) (((uint32_t)(x) & MCAN_RXF1S_DMS_MASK) >> MCAN_RXF1S_DMS_SHIFT) + +/* + * RF1L (R) + * + * Rx FIFO 1 Message Lost + * This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. + * 0= No Rx FIFO 1 message lost + * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + * Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. + */ +#define MCAN_RXF1S_RF1L_MASK (0x2000000UL) +#define MCAN_RXF1S_RF1L_SHIFT (25U) +#define MCAN_RXF1S_RF1L_GET(x) (((uint32_t)(x) & MCAN_RXF1S_RF1L_MASK) >> MCAN_RXF1S_RF1L_SHIFT) + +/* + * F1F (R) + * + * Rx FIFO 1 Full + * 0= Rx FIFO 1 not full + * 1= Rx FIFO 1 full + */ +#define MCAN_RXF1S_F1F_MASK (0x1000000UL) +#define MCAN_RXF1S_F1F_SHIFT (24U) +#define MCAN_RXF1S_F1F_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1F_MASK) >> MCAN_RXF1S_F1F_SHIFT) + +/* + * F1PI (R) + * + * Rx FIFO 1 Put Index + * Rx FIFO 1 write index pointer, range 0 to 63. + */ +#define MCAN_RXF1S_F1PI_MASK (0x3F0000UL) +#define MCAN_RXF1S_F1PI_SHIFT (16U) +#define MCAN_RXF1S_F1PI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1PI_MASK) >> MCAN_RXF1S_F1PI_SHIFT) + +/* + * F1GI (R) + * + * Rx FIFO 1 Get Index + * Rx FIFO 1 read index pointer, range 0 to 63. + */ +#define MCAN_RXF1S_F1GI_MASK (0x3F00U) +#define MCAN_RXF1S_F1GI_SHIFT (8U) +#define MCAN_RXF1S_F1GI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT) + +/* + * F1FL (R) + * + * Rx FIFO 1 Fill Level + * Number of elements stored in Rx FIFO 1, range 0 to 64. + */ +#define MCAN_RXF1S_F1FL_MASK (0x7FU) +#define MCAN_RXF1S_F1FL_SHIFT (0U) +#define MCAN_RXF1S_F1FL_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1FL_MASK) >> MCAN_RXF1S_F1FL_SHIFT) + +/* Bitfield definition for register: RXF1A */ +/* + * F1AI (RW) + * + * Rx FIFO 1 Acknowledge Index + * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + */ +#define MCAN_RXF1A_F1AI_MASK (0x3FU) +#define MCAN_RXF1A_F1AI_SHIFT (0U) +#define MCAN_RXF1A_F1AI_SET(x) (((uint32_t)(x) << MCAN_RXF1A_F1AI_SHIFT) & MCAN_RXF1A_F1AI_MASK) +#define MCAN_RXF1A_F1AI_GET(x) (((uint32_t)(x) & MCAN_RXF1A_F1AI_MASK) >> MCAN_RXF1A_F1AI_SHIFT) + +/* Bitfield definition for register: RXESC */ +/* + * RBDS (RW) + * + * Rx Buffer Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + */ +#define MCAN_RXESC_RBDS_MASK (0x700U) +#define MCAN_RXESC_RBDS_SHIFT (8U) +#define MCAN_RXESC_RBDS_SET(x) (((uint32_t)(x) << MCAN_RXESC_RBDS_SHIFT) & MCAN_RXESC_RBDS_MASK) +#define MCAN_RXESC_RBDS_GET(x) (((uint32_t)(x) & MCAN_RXESC_RBDS_MASK) >> MCAN_RXESC_RBDS_SHIFT) + +/* + * F1DS (RW) + * + * Rx FIFO 1 Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + */ +#define MCAN_RXESC_F1DS_MASK (0x70U) +#define MCAN_RXESC_F1DS_SHIFT (4U) +#define MCAN_RXESC_F1DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F1DS_SHIFT) & MCAN_RXESC_F1DS_MASK) +#define MCAN_RXESC_F1DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F1DS_MASK) >> MCAN_RXESC_F1DS_SHIFT) + +/* + * F0DS (RW) + * + * Rx FIFO 0 Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + */ +#define MCAN_RXESC_F0DS_MASK (0x7U) +#define MCAN_RXESC_F0DS_SHIFT (0U) +#define MCAN_RXESC_F0DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F0DS_SHIFT) & MCAN_RXESC_F0DS_MASK) +#define MCAN_RXESC_F0DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F0DS_MASK) >> MCAN_RXESC_F0DS_SHIFT) + +/* Bitfield definition for register: TXBC */ +/* + * TFQM (RW) + * + * Tx FIFO/Queue Mode + * 0= Tx FIFO operation + * 1= Tx Queue operation + */ +#define MCAN_TXBC_TFQM_MASK (0x40000000UL) +#define MCAN_TXBC_TFQM_SHIFT (30U) +#define MCAN_TXBC_TFQM_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQM_SHIFT) & MCAN_TXBC_TFQM_MASK) +#define MCAN_TXBC_TFQM_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQM_MASK) >> MCAN_TXBC_TFQM_SHIFT) + +/* + * TFQS (RW) + * + * Transmit FIFO/Queue Size + * 0= No Tx FIFO/Queue + * 1-32= Number of Tx Buffers used for Tx FIFO/Queue + * >32= Values greater than 32 are interpreted as 32 + */ +#define MCAN_TXBC_TFQS_MASK (0x3F000000UL) +#define MCAN_TXBC_TFQS_SHIFT (24U) +#define MCAN_TXBC_TFQS_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQS_SHIFT) & MCAN_TXBC_TFQS_MASK) +#define MCAN_TXBC_TFQS_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQS_MASK) >> MCAN_TXBC_TFQS_SHIFT) + +/* + * NDTB (RW) + * + * Number of Dedicated Transmit Buffers + * 0= No Dedicated Tx Buffers + * 1-32= Number of Dedicated Tx Buffers + * >32= Values greater than 32 are interpreted as 32 + */ +#define MCAN_TXBC_NDTB_MASK (0x3F0000UL) +#define MCAN_TXBC_NDTB_SHIFT (16U) +#define MCAN_TXBC_NDTB_SET(x) (((uint32_t)(x) << MCAN_TXBC_NDTB_SHIFT) & MCAN_TXBC_NDTB_MASK) +#define MCAN_TXBC_NDTB_GET(x) (((uint32_t)(x) & MCAN_TXBC_NDTB_MASK) >> MCAN_TXBC_NDTB_SHIFT) + +/* + * TBSA (RW) + * + * Tx Buffers Start Address + * Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). + * Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + */ +#define MCAN_TXBC_TBSA_MASK (0xFFFCU) +#define MCAN_TXBC_TBSA_SHIFT (2U) +#define MCAN_TXBC_TBSA_SET(x) (((uint32_t)(x) << MCAN_TXBC_TBSA_SHIFT) & MCAN_TXBC_TBSA_MASK) +#define MCAN_TXBC_TBSA_GET(x) (((uint32_t)(x) & MCAN_TXBC_TBSA_MASK) >> MCAN_TXBC_TBSA_SHIFT) + +/* Bitfield definition for register: TXFQS */ +/* + * TFQF (R) + * + * Tx FIFO/Queue Full + * 0= Tx FIFO/Queue not full + * 1= Tx FIFO/Queue full + */ +#define MCAN_TXFQS_TFQF_MASK (0x200000UL) +#define MCAN_TXFQS_TFQF_SHIFT (21U) +#define MCAN_TXFQS_TFQF_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQF_MASK) >> MCAN_TXFQS_TFQF_SHIFT) + +/* + * TFQPI (R) + * + * Tx FIFO/Queue Put Index + * Tx FIFO/Queue write index pointer, range 0 to 31. + */ +#define MCAN_TXFQS_TFQPI_MASK (0x1F0000UL) +#define MCAN_TXFQS_TFQPI_SHIFT (16U) +#define MCAN_TXFQS_TFQPI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQPI_MASK) >> MCAN_TXFQS_TFQPI_SHIFT) + +/* + * TFGI (R) + * + * Tx FIFO Get Index + * Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured + * (TXBC.TFQM = ‘1’). + */ +#define MCAN_TXFQS_TFGI_MASK (0x1F00U) +#define MCAN_TXFQS_TFGI_SHIFT (8U) +#define MCAN_TXFQS_TFGI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFGI_MASK) >> MCAN_TXFQS_TFGI_SHIFT) + +/* + * TFFL (R) + * + * Tx FIFO Free Level + * Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) + * Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with + * the first dedicated Tx Buffers. + * Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + */ +#define MCAN_TXFQS_TFFL_MASK (0x3FU) +#define MCAN_TXFQS_TFFL_SHIFT (0U) +#define MCAN_TXFQS_TFFL_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFFL_MASK) >> MCAN_TXFQS_TFFL_SHIFT) + +/* Bitfield definition for register: TXESC */ +/* + * TBDS (RW) + * + * Tx Buffer Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + * Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). + */ +#define MCAN_TXESC_TBDS_MASK (0x7U) +#define MCAN_TXESC_TBDS_SHIFT (0U) +#define MCAN_TXESC_TBDS_SET(x) (((uint32_t)(x) << MCAN_TXESC_TBDS_SHIFT) & MCAN_TXESC_TBDS_MASK) +#define MCAN_TXESC_TBDS_GET(x) (((uint32_t)(x) & MCAN_TXESC_TBDS_MASK) >> MCAN_TXESC_TBDS_SHIFT) + +/* Bitfield definition for register: TXBRP */ +/* + * TRP (R) + * + * Transmission Request Pending + * Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register + * TXBCR. + * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the + * highest priority (Tx Buffer with lowest Message ID). + * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. + * After a cancellation has been requested, a finished cancellation is signalled via TXBCF + * ? after successful transmission together with the corresponding TXBTO bit + * ? when the transmission has not yet been started at the point of cancellation + * ? when the transmission has been aborted due to lost arbitration + * ? when an error occurred during frame transmission + * In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. + * 0= No transmission request pending + * 1= Transmission request pending + * Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. + */ +#define MCAN_TXBRP_TRP_MASK (0xFFFFFFFFUL) +#define MCAN_TXBRP_TRP_SHIFT (0U) +#define MCAN_TXBRP_TRP_GET(x) (((uint32_t)(x) & MCAN_TXBRP_TRP_MASK) >> MCAN_TXBRP_TRP_SHIFT) + +/* Bitfield definition for register: TXBAR */ +/* + * AR (RW) + * + * Add Request + * Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx + * Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. + * When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. + * 0= No transmission request added + * 1= Transmission requested added + * Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. + */ +#define MCAN_TXBAR_AR_MASK (0xFFFFFFFFUL) +#define MCAN_TXBAR_AR_SHIFT (0U) +#define MCAN_TXBAR_AR_SET(x) (((uint32_t)(x) << MCAN_TXBAR_AR_SHIFT) & MCAN_TXBAR_AR_MASK) +#define MCAN_TXBAR_AR_GET(x) (((uint32_t)(x) & MCAN_TXBAR_AR_MASK) >> MCAN_TXBAR_AR_SHIFT) + +/* Bitfield definition for register: TXBCR */ +/* + * CR (RW) + * + * Cancellation Request + * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. + * 0= No cancellation pending + * 1= Cancellation pending + */ +#define MCAN_TXBCR_CR_MASK (0xFFFFFFFFUL) +#define MCAN_TXBCR_CR_SHIFT (0U) +#define MCAN_TXBCR_CR_SET(x) (((uint32_t)(x) << MCAN_TXBCR_CR_SHIFT) & MCAN_TXBCR_CR_MASK) +#define MCAN_TXBCR_CR_GET(x) (((uint32_t)(x) & MCAN_TXBCR_CR_MASK) >> MCAN_TXBCR_CR_SHIFT) + +/* Bitfield definition for register: TXBTO */ +/* + * TO (R) + * + * Transmission Occurred + * Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. + * 0= No transmission occurred + * 1= Transmission occurred + */ +#define MCAN_TXBTO_TO_MASK (0xFFFFFFFFUL) +#define MCAN_TXBTO_TO_SHIFT (0U) +#define MCAN_TXBTO_TO_GET(x) (((uint32_t)(x) & MCAN_TXBTO_TO_MASK) >> MCAN_TXBTO_TO_SHIFT) + +/* Bitfield definition for register: TXBCF */ +/* + * CF (R) + * + * Cancellation Finished + * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. + * 0= No transmit buffer cancellation + * 1= Transmit buffer cancellation finished + */ +#define MCAN_TXBCF_CF_MASK (0xFFFFFFFFUL) +#define MCAN_TXBCF_CF_SHIFT (0U) +#define MCAN_TXBCF_CF_GET(x) (((uint32_t)(x) & MCAN_TXBCF_CF_MASK) >> MCAN_TXBCF_CF_SHIFT) + +/* Bitfield definition for register: TXBTIE */ +/* + * TIE (RW) + * + * Transmission Interrupt Enable + * Each Tx Buffer has its own Transmission Interrupt Enable bit. + * 0= Transmission interrupt disabled + * 1= Transmission interrupt enable + */ +#define MCAN_TXBTIE_TIE_MASK (0xFFFFFFFFUL) +#define MCAN_TXBTIE_TIE_SHIFT (0U) +#define MCAN_TXBTIE_TIE_SET(x) (((uint32_t)(x) << MCAN_TXBTIE_TIE_SHIFT) & MCAN_TXBTIE_TIE_MASK) +#define MCAN_TXBTIE_TIE_GET(x) (((uint32_t)(x) & MCAN_TXBTIE_TIE_MASK) >> MCAN_TXBTIE_TIE_SHIFT) + +/* Bitfield definition for register: TXBCIE */ +/* + * CFIE (RW) + * + * Cancellation Finished Interrupt Enable + * Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. + * 0= Cancellation finished interrupt disabled + * 1= Cancellation finished interrupt enabled + */ +#define MCAN_TXBCIE_CFIE_MASK (0xFFFFFFFFUL) +#define MCAN_TXBCIE_CFIE_SHIFT (0U) +#define MCAN_TXBCIE_CFIE_SET(x) (((uint32_t)(x) << MCAN_TXBCIE_CFIE_SHIFT) & MCAN_TXBCIE_CFIE_MASK) +#define MCAN_TXBCIE_CFIE_GET(x) (((uint32_t)(x) & MCAN_TXBCIE_CFIE_MASK) >> MCAN_TXBCIE_CFIE_SHIFT) + +/* Bitfield definition for register: TXEFC */ +/* + * EFWM (RW) + * + * Event FIFO Watermark + * 0= Watermark interrupt disabled + * 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) + * >32= Watermark interrupt disabled + */ +#define MCAN_TXEFC_EFWM_MASK (0x3F000000UL) +#define MCAN_TXEFC_EFWM_SHIFT (24U) +#define MCAN_TXEFC_EFWM_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFWM_SHIFT) & MCAN_TXEFC_EFWM_MASK) +#define MCAN_TXEFC_EFWM_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFWM_MASK) >> MCAN_TXEFC_EFWM_SHIFT) + +/* + * EFS (RW) + * + * Event FIFO Size + * 0= Tx Event FIFO disabled + * 1-32= Number of Tx Event FIFO elements + * >32= Values greater than 32 are interpreted as 32 + * The Tx Event FIFO elements are indexed from 0 to EFS - 1 + */ +#define MCAN_TXEFC_EFS_MASK (0x3F0000UL) +#define MCAN_TXEFC_EFS_SHIFT (16U) +#define MCAN_TXEFC_EFS_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFS_SHIFT) & MCAN_TXEFC_EFS_MASK) +#define MCAN_TXEFC_EFS_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFS_MASK) >> MCAN_TXEFC_EFS_SHIFT) + +/* + * EFSA (RW) + * + * Event FIFO Start Address + * Start address of Tx Event FIFO in Message RAM (32-bit word address) + */ +#define MCAN_TXEFC_EFSA_MASK (0xFFFCU) +#define MCAN_TXEFC_EFSA_SHIFT (2U) +#define MCAN_TXEFC_EFSA_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFSA_SHIFT) & MCAN_TXEFC_EFSA_MASK) +#define MCAN_TXEFC_EFSA_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFSA_MASK) >> MCAN_TXEFC_EFSA_SHIFT) + +/* Bitfield definition for register: TXEFS */ +/* + * TEFL (R) + * + * Tx Event FIFO Element Lost + * This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. + * 0= No Tx Event FIFO element lost + * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + */ +#define MCAN_TXEFS_TEFL_MASK (0x2000000UL) +#define MCAN_TXEFS_TEFL_SHIFT (25U) +#define MCAN_TXEFS_TEFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_TEFL_MASK) >> MCAN_TXEFS_TEFL_SHIFT) + +/* + * EFF (R) + * + * Event FIFO Full + * 0= Tx Event FIFO not full + * 1= Tx Event FIFO full + */ +#define MCAN_TXEFS_EFF_MASK (0x1000000UL) +#define MCAN_TXEFS_EFF_SHIFT (24U) +#define MCAN_TXEFS_EFF_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFF_MASK) >> MCAN_TXEFS_EFF_SHIFT) + +/* + * EFPI (R) + * + * Event FIFO Put Index + * Tx Event FIFO write index pointer, range 0 to 31. + */ +#define MCAN_TXEFS_EFPI_MASK (0x1F0000UL) +#define MCAN_TXEFS_EFPI_SHIFT (16U) +#define MCAN_TXEFS_EFPI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFPI_MASK) >> MCAN_TXEFS_EFPI_SHIFT) + +/* + * EFGI (R) + * + * Event FIFO Get Index + * Tx Event FIFO read index pointer, range 0 to 31. + */ +#define MCAN_TXEFS_EFGI_MASK (0x1F00U) +#define MCAN_TXEFS_EFGI_SHIFT (8U) +#define MCAN_TXEFS_EFGI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFGI_MASK) >> MCAN_TXEFS_EFGI_SHIFT) + +/* + * EFFL (R) + * + * Event FIFO Fill Level + * Number of elements stored in Tx Event FIFO, range 0 to 32. + */ +#define MCAN_TXEFS_EFFL_MASK (0x3FU) +#define MCAN_TXEFS_EFFL_SHIFT (0U) +#define MCAN_TXEFS_EFFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFFL_MASK) >> MCAN_TXEFS_EFFL_SHIFT) + +/* Bitfield definition for register: TXEFA */ +/* + * EFAI (RW) + * + * Event FIFO Acknowledge Index + * After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get + * Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + */ +#define MCAN_TXEFA_EFAI_MASK (0x1FU) +#define MCAN_TXEFA_EFAI_SHIFT (0U) +#define MCAN_TXEFA_EFAI_SET(x) (((uint32_t)(x) << MCAN_TXEFA_EFAI_SHIFT) & MCAN_TXEFA_EFAI_MASK) +#define MCAN_TXEFA_EFAI_GET(x) (((uint32_t)(x) & MCAN_TXEFA_EFAI_MASK) >> MCAN_TXEFA_EFAI_SHIFT) + +/* Bitfield definition for register array: TS_SEL */ +/* + * TS (R) + * + * Timestamp Word TS + * default can save 16 timestamps with 32bit; + * if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + */ +#define MCAN_TS_SEL_TS_MASK (0xFFFFFFFFUL) +#define MCAN_TS_SEL_TS_SHIFT (0U) +#define MCAN_TS_SEL_TS_GET(x) (((uint32_t)(x) & MCAN_TS_SEL_TS_MASK) >> MCAN_TS_SEL_TS_SHIFT) + +/* Bitfield definition for register: CREL */ +/* + * REL (R) + * + * Core Release + * One digit, BCD-coded + */ +#define MCAN_CREL_REL_MASK (0xF0000000UL) +#define MCAN_CREL_REL_SHIFT (28U) +#define MCAN_CREL_REL_GET(x) (((uint32_t)(x) & MCAN_CREL_REL_MASK) >> MCAN_CREL_REL_SHIFT) + +/* + * STEP (R) + * + * Step of Core Release + * One digit, BCD-coded. + */ +#define MCAN_CREL_STEP_MASK (0xF000000UL) +#define MCAN_CREL_STEP_SHIFT (24U) +#define MCAN_CREL_STEP_GET(x) (((uint32_t)(x) & MCAN_CREL_STEP_MASK) >> MCAN_CREL_STEP_SHIFT) + +/* + * SUBSTEP (R) + * + * Sub-step of Core Release + * One digit, BCD-coded + */ +#define MCAN_CREL_SUBSTEP_MASK (0xF00000UL) +#define MCAN_CREL_SUBSTEP_SHIFT (20U) +#define MCAN_CREL_SUBSTEP_GET(x) (((uint32_t)(x) & MCAN_CREL_SUBSTEP_MASK) >> MCAN_CREL_SUBSTEP_SHIFT) + +/* + * YEAR (R) + * + * Timestamp Year + * One digit, BCD-coded. This field is set by generic parameter on + * synthesis. + */ +#define MCAN_CREL_YEAR_MASK (0xF0000UL) +#define MCAN_CREL_YEAR_SHIFT (16U) +#define MCAN_CREL_YEAR_GET(x) (((uint32_t)(x) & MCAN_CREL_YEAR_MASK) >> MCAN_CREL_YEAR_SHIFT) + +/* + * MON (R) + * + * Timestamp Month + * Two digits, BCD-coded. This field is set by generic parameter + * on synthesis. + */ +#define MCAN_CREL_MON_MASK (0xFF00U) +#define MCAN_CREL_MON_SHIFT (8U) +#define MCAN_CREL_MON_GET(x) (((uint32_t)(x) & MCAN_CREL_MON_MASK) >> MCAN_CREL_MON_SHIFT) + +/* + * DAY (R) + * + * Timestamp Day + * Two digits, BCD-coded. This field is set by generic parameter + * on synthesis. + */ +#define MCAN_CREL_DAY_MASK (0xFFU) +#define MCAN_CREL_DAY_SHIFT (0U) +#define MCAN_CREL_DAY_GET(x) (((uint32_t)(x) & MCAN_CREL_DAY_MASK) >> MCAN_CREL_DAY_SHIFT) + +/* Bitfield definition for register: TSCFG */ +/* + * TBPRE (RW) + * + * Timebase Prescaler + * 0x00 to 0xFF + * The value by which the oscillator frequency is divided for + * generating the timebase counter clock. Valid values for the + * Timebase Prescaler are 0 to 255. The actual interpretation by + * the hardware of this value is such that one more than the value + * programmed here is used. Affects only the TSU internal + * timebase. When the internal timebase is excluded by synthesis, + * TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not + * used. + */ +#define MCAN_TSCFG_TBPRE_MASK (0xFF00U) +#define MCAN_TSCFG_TBPRE_SHIFT (8U) +#define MCAN_TSCFG_TBPRE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBPRE_SHIFT) & MCAN_TSCFG_TBPRE_MASK) +#define MCAN_TSCFG_TBPRE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBPRE_MASK) >> MCAN_TSCFG_TBPRE_SHIFT) + +/* + * EN64 (RW) + * + * set to use 64bit timestamp. + * when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. + * TSP can be used to select different one + */ +#define MCAN_TSCFG_EN64_MASK (0x8U) +#define MCAN_TSCFG_EN64_SHIFT (3U) +#define MCAN_TSCFG_EN64_SET(x) (((uint32_t)(x) << MCAN_TSCFG_EN64_SHIFT) & MCAN_TSCFG_EN64_MASK) +#define MCAN_TSCFG_EN64_GET(x) (((uint32_t)(x) & MCAN_TSCFG_EN64_MASK) >> MCAN_TSCFG_EN64_SHIFT) + +/* + * SCP (RW) + * + * Select Capturing Position + * 0: Capture Timestamp at EOF + * 1: Capture Timestamp at SOF + */ +#define MCAN_TSCFG_SCP_MASK (0x4U) +#define MCAN_TSCFG_SCP_SHIFT (2U) +#define MCAN_TSCFG_SCP_SET(x) (((uint32_t)(x) << MCAN_TSCFG_SCP_SHIFT) & MCAN_TSCFG_SCP_MASK) +#define MCAN_TSCFG_SCP_GET(x) (((uint32_t)(x) & MCAN_TSCFG_SCP_MASK) >> MCAN_TSCFG_SCP_SHIFT) + +/* + * TBCS (RW) + * + * Timebase Counter Select + * When the internal timebase is excluded by synthesis, TBCS is + * fixed to ‘1’. + * 0: Timestamp value captured from internal timebase counter, + * ATB.TB[31:0] is the internal timbase counter + * 1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] + */ +#define MCAN_TSCFG_TBCS_MASK (0x2U) +#define MCAN_TSCFG_TBCS_SHIFT (1U) +#define MCAN_TSCFG_TBCS_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBCS_SHIFT) & MCAN_TSCFG_TBCS_MASK) +#define MCAN_TSCFG_TBCS_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBCS_MASK) >> MCAN_TSCFG_TBCS_SHIFT) + +/* + * TSUE (RW) + * + * Timestamp Unit Enable + * 0: TSU disabled + * 1: TSU enabled + */ +#define MCAN_TSCFG_TSUE_MASK (0x1U) +#define MCAN_TSCFG_TSUE_SHIFT (0U) +#define MCAN_TSCFG_TSUE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TSUE_SHIFT) & MCAN_TSCFG_TSUE_MASK) +#define MCAN_TSCFG_TSUE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TSUE_MASK) >> MCAN_TSCFG_TSUE_SHIFT) + +/* Bitfield definition for register: TSS1 */ +/* + * TSL (R) + * + * Timestamp Lost + * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. + * Reading a Timestamp register resets the related bit. + */ +#define MCAN_TSS1_TSL_MASK (0xFFFF0000UL) +#define MCAN_TSS1_TSL_SHIFT (16U) +#define MCAN_TSS1_TSL_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSL_MASK) >> MCAN_TSS1_TSL_SHIFT) + +/* + * TSN (R) + * + * Timestamp New + * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related + * Timestamp register. Reading a Timestamp register resets the related bit. + */ +#define MCAN_TSS1_TSN_MASK (0xFFFFU) +#define MCAN_TSS1_TSN_SHIFT (0U) +#define MCAN_TSS1_TSN_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSN_MASK) >> MCAN_TSS1_TSN_SHIFT) + +/* Bitfield definition for register: TSS2 */ +/* + * TSP (R) + * + * Timestamp Pointer + * The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 + * depending on number_ts_g), it is incremented to 0. + * Value also signalled on output m_can_tsp[3:0]. + */ +#define MCAN_TSS2_TSP_MASK (0xFU) +#define MCAN_TSS2_TSP_SHIFT (0U) +#define MCAN_TSS2_TSP_GET(x) (((uint32_t)(x) & MCAN_TSS2_TSP_MASK) >> MCAN_TSS2_TSP_SHIFT) + +/* Bitfield definition for register: ATB */ +/* + * TB (RC) + * + * timebase for timestamp generation 31-0 + */ +#define MCAN_ATB_TB_MASK (0xFFFFFFFFUL) +#define MCAN_ATB_TB_SHIFT (0U) +#define MCAN_ATB_TB_GET(x) (((uint32_t)(x) & MCAN_ATB_TB_MASK) >> MCAN_ATB_TB_SHIFT) + +/* Bitfield definition for register: ATBH */ +/* + * TBH (RC) + * + * timebase for timestamp generation 63-32 + */ +#define MCAN_ATBH_TBH_MASK (0xFFFFFFFFUL) +#define MCAN_ATBH_TBH_SHIFT (0U) +#define MCAN_ATBH_TBH_GET(x) (((uint32_t)(x) & MCAN_ATBH_TBH_MASK) >> MCAN_ATBH_TBH_SHIFT) + +/* Bitfield definition for register: GLB_CTL */ +/* + * M_CAN_STBY (RW) + * + * m_can standby control + */ +#define MCAN_GLB_CTL_M_CAN_STBY_MASK (0x80000000UL) +#define MCAN_GLB_CTL_M_CAN_STBY_SHIFT (31U) +#define MCAN_GLB_CTL_M_CAN_STBY_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_M_CAN_STBY_SHIFT) & MCAN_GLB_CTL_M_CAN_STBY_MASK) +#define MCAN_GLB_CTL_M_CAN_STBY_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_M_CAN_STBY_MASK) >> MCAN_GLB_CTL_M_CAN_STBY_SHIFT) + +/* + * STBY_CLR_EN (RW) + * + * m_can standby clear control + * 0:controlled by software by standby bit[bit31] + * 1:auto clear standby by hardware when rx data is 0 + */ +#define MCAN_GLB_CTL_STBY_CLR_EN_MASK (0x40000000UL) +#define MCAN_GLB_CTL_STBY_CLR_EN_SHIFT (30U) +#define MCAN_GLB_CTL_STBY_CLR_EN_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) +#define MCAN_GLB_CTL_STBY_CLR_EN_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) >> MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) + +/* + * STBY_POL (RW) + * + * standby polarity selection + */ +#define MCAN_GLB_CTL_STBY_POL_MASK (0x20000000UL) +#define MCAN_GLB_CTL_STBY_POL_SHIFT (29U) +#define MCAN_GLB_CTL_STBY_POL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_POL_SHIFT) & MCAN_GLB_CTL_STBY_POL_MASK) +#define MCAN_GLB_CTL_STBY_POL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_POL_MASK) >> MCAN_GLB_CTL_STBY_POL_SHIFT) + +/* + * TSU_TBIN_SEL (RW) + * + */ +#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x7U) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) + +/* Bitfield definition for register: GLB_STATUS */ +/* + * M_CAN_INT1 (R) + * + * m_can interrupt status1 + */ +#define MCAN_GLB_STATUS_M_CAN_INT1_MASK (0x8U) +#define MCAN_GLB_STATUS_M_CAN_INT1_SHIFT (3U) +#define MCAN_GLB_STATUS_M_CAN_INT1_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT1_MASK) >> MCAN_GLB_STATUS_M_CAN_INT1_SHIFT) + +/* + * M_CAN_INT0 (R) + * + * m_can interrupt status0 + */ +#define MCAN_GLB_STATUS_M_CAN_INT0_MASK (0x4U) +#define MCAN_GLB_STATUS_M_CAN_INT0_SHIFT (2U) +#define MCAN_GLB_STATUS_M_CAN_INT0_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT0_MASK) >> MCAN_GLB_STATUS_M_CAN_INT0_SHIFT) + +/* Bitfield definition for register array: MESSAGE_BUFF */ +/* + * DATA (RW) + * + * m_can message buffer + */ +#define MCAN_MESSAGE_BUFF_DATA_MASK (0xFFFFFFFFUL) +#define MCAN_MESSAGE_BUFF_DATA_SHIFT (0U) +#define MCAN_MESSAGE_BUFF_DATA_SET(x) (((uint32_t)(x) << MCAN_MESSAGE_BUFF_DATA_SHIFT) & MCAN_MESSAGE_BUFF_DATA_MASK) +#define MCAN_MESSAGE_BUFF_DATA_GET(x) (((uint32_t)(x) & MCAN_MESSAGE_BUFF_DATA_MASK) >> MCAN_MESSAGE_BUFF_DATA_SHIFT) + + + +/* TS_SEL register group index macro definition */ +#define MCAN_TS_SEL_TS_SEL0 (0UL) +#define MCAN_TS_SEL_TS_SEL1 (1UL) +#define MCAN_TS_SEL_TS_SEL2 (2UL) +#define MCAN_TS_SEL_TS_SEL3 (3UL) +#define MCAN_TS_SEL_TS_SEL4 (4UL) +#define MCAN_TS_SEL_TS_SEL5 (5UL) +#define MCAN_TS_SEL_TS_SEL6 (6UL) +#define MCAN_TS_SEL_TS_SEL7 (7UL) +#define MCAN_TS_SEL_TS_SEL8 (8UL) +#define MCAN_TS_SEL_TS_SEL9 (9UL) +#define MCAN_TS_SEL_TS_SEL10 (10UL) +#define MCAN_TS_SEL_TS_SEL11 (11UL) +#define MCAN_TS_SEL_TS_SEL12 (12UL) +#define MCAN_TS_SEL_TS_SEL13 (13UL) +#define MCAN_TS_SEL_TS_SEL14 (14UL) +#define MCAN_TS_SEL_TS_SEL15 (15UL) + +/* MESSAGE_BUFF register group index macro definition */ +#define MCAN_MESSAGE_BUFF_0 (0UL) +#define MCAN_MESSAGE_BUFF_1 (1UL) +#define MCAN_MESSAGE_BUFF_2 (2UL) +#define MCAN_MESSAGE_BUFF_3 (3UL) +#define MCAN_MESSAGE_BUFF_4 (4UL) +#define MCAN_MESSAGE_BUFF_5 (5UL) +#define MCAN_MESSAGE_BUFF_6 (6UL) +#define MCAN_MESSAGE_BUFF_7 (7UL) +#define MCAN_MESSAGE_BUFF_8 (8UL) +#define MCAN_MESSAGE_BUFF_9 (9UL) +#define MCAN_MESSAGE_BUFF_10 (10UL) +#define MCAN_MESSAGE_BUFF_11 (11UL) +#define MCAN_MESSAGE_BUFF_12 (12UL) +#define MCAN_MESSAGE_BUFF_13 (13UL) +#define MCAN_MESSAGE_BUFF_14 (14UL) +#define MCAN_MESSAGE_BUFF_15 (15UL) +#define MCAN_MESSAGE_BUFF_16 (16UL) +#define MCAN_MESSAGE_BUFF_17 (17UL) +#define MCAN_MESSAGE_BUFF_18 (18UL) +#define MCAN_MESSAGE_BUFF_19 (19UL) +#define MCAN_MESSAGE_BUFF_20 (20UL) +#define MCAN_MESSAGE_BUFF_21 (21UL) +#define MCAN_MESSAGE_BUFF_22 (22UL) +#define MCAN_MESSAGE_BUFF_23 (23UL) +#define MCAN_MESSAGE_BUFF_24 (24UL) +#define MCAN_MESSAGE_BUFF_25 (25UL) +#define MCAN_MESSAGE_BUFF_26 (26UL) +#define MCAN_MESSAGE_BUFF_27 (27UL) +#define MCAN_MESSAGE_BUFF_28 (28UL) +#define MCAN_MESSAGE_BUFF_29 (29UL) +#define MCAN_MESSAGE_BUFF_30 (30UL) +#define MCAN_MESSAGE_BUFF_31 (31UL) +#define MCAN_MESSAGE_BUFF_32 (32UL) +#define MCAN_MESSAGE_BUFF_33 (33UL) +#define MCAN_MESSAGE_BUFF_34 (34UL) +#define MCAN_MESSAGE_BUFF_35 (35UL) +#define MCAN_MESSAGE_BUFF_36 (36UL) +#define MCAN_MESSAGE_BUFF_37 (37UL) +#define MCAN_MESSAGE_BUFF_38 (38UL) +#define MCAN_MESSAGE_BUFF_39 (39UL) +#define MCAN_MESSAGE_BUFF_40 (40UL) +#define MCAN_MESSAGE_BUFF_41 (41UL) +#define MCAN_MESSAGE_BUFF_42 (42UL) +#define MCAN_MESSAGE_BUFF_43 (43UL) +#define MCAN_MESSAGE_BUFF_44 (44UL) +#define MCAN_MESSAGE_BUFF_45 (45UL) +#define MCAN_MESSAGE_BUFF_46 (46UL) +#define MCAN_MESSAGE_BUFF_47 (47UL) +#define MCAN_MESSAGE_BUFF_48 (48UL) +#define MCAN_MESSAGE_BUFF_49 (49UL) +#define MCAN_MESSAGE_BUFF_50 (50UL) +#define MCAN_MESSAGE_BUFF_51 (51UL) +#define MCAN_MESSAGE_BUFF_52 (52UL) +#define MCAN_MESSAGE_BUFF_53 (53UL) +#define MCAN_MESSAGE_BUFF_54 (54UL) +#define MCAN_MESSAGE_BUFF_55 (55UL) +#define MCAN_MESSAGE_BUFF_56 (56UL) +#define MCAN_MESSAGE_BUFF_57 (57UL) +#define MCAN_MESSAGE_BUFF_58 (58UL) +#define MCAN_MESSAGE_BUFF_59 (59UL) +#define MCAN_MESSAGE_BUFF_60 (60UL) +#define MCAN_MESSAGE_BUFF_61 (61UL) +#define MCAN_MESSAGE_BUFF_62 (62UL) +#define MCAN_MESSAGE_BUFF_63 (63UL) +#define MCAN_MESSAGE_BUFF_64 (64UL) +#define MCAN_MESSAGE_BUFF_65 (65UL) +#define MCAN_MESSAGE_BUFF_66 (66UL) +#define MCAN_MESSAGE_BUFF_67 (67UL) +#define MCAN_MESSAGE_BUFF_68 (68UL) +#define MCAN_MESSAGE_BUFF_69 (69UL) +#define MCAN_MESSAGE_BUFF_70 (70UL) +#define MCAN_MESSAGE_BUFF_71 (71UL) +#define MCAN_MESSAGE_BUFF_72 (72UL) +#define MCAN_MESSAGE_BUFF_73 (73UL) +#define MCAN_MESSAGE_BUFF_74 (74UL) +#define MCAN_MESSAGE_BUFF_75 (75UL) +#define MCAN_MESSAGE_BUFF_76 (76UL) +#define MCAN_MESSAGE_BUFF_77 (77UL) +#define MCAN_MESSAGE_BUFF_78 (78UL) +#define MCAN_MESSAGE_BUFF_79 (79UL) +#define MCAN_MESSAGE_BUFF_80 (80UL) +#define MCAN_MESSAGE_BUFF_81 (81UL) +#define MCAN_MESSAGE_BUFF_82 (82UL) +#define MCAN_MESSAGE_BUFF_83 (83UL) +#define MCAN_MESSAGE_BUFF_84 (84UL) +#define MCAN_MESSAGE_BUFF_85 (85UL) +#define MCAN_MESSAGE_BUFF_86 (86UL) +#define MCAN_MESSAGE_BUFF_87 (87UL) +#define MCAN_MESSAGE_BUFF_88 (88UL) +#define MCAN_MESSAGE_BUFF_89 (89UL) +#define MCAN_MESSAGE_BUFF_90 (90UL) +#define MCAN_MESSAGE_BUFF_91 (91UL) +#define MCAN_MESSAGE_BUFF_92 (92UL) +#define MCAN_MESSAGE_BUFF_93 (93UL) +#define MCAN_MESSAGE_BUFF_94 (94UL) +#define MCAN_MESSAGE_BUFF_95 (95UL) +#define MCAN_MESSAGE_BUFF_96 (96UL) +#define MCAN_MESSAGE_BUFF_97 (97UL) +#define MCAN_MESSAGE_BUFF_98 (98UL) +#define MCAN_MESSAGE_BUFF_99 (99UL) +#define MCAN_MESSAGE_BUFF_100 (100UL) +#define MCAN_MESSAGE_BUFF_101 (101UL) +#define MCAN_MESSAGE_BUFF_102 (102UL) +#define MCAN_MESSAGE_BUFF_103 (103UL) +#define MCAN_MESSAGE_BUFF_104 (104UL) +#define MCAN_MESSAGE_BUFF_105 (105UL) +#define MCAN_MESSAGE_BUFF_106 (106UL) +#define MCAN_MESSAGE_BUFF_107 (107UL) +#define MCAN_MESSAGE_BUFF_108 (108UL) +#define MCAN_MESSAGE_BUFF_109 (109UL) +#define MCAN_MESSAGE_BUFF_110 (110UL) +#define MCAN_MESSAGE_BUFF_111 (111UL) +#define MCAN_MESSAGE_BUFF_112 (112UL) +#define MCAN_MESSAGE_BUFF_113 (113UL) +#define MCAN_MESSAGE_BUFF_114 (114UL) +#define MCAN_MESSAGE_BUFF_115 (115UL) +#define MCAN_MESSAGE_BUFF_116 (116UL) +#define MCAN_MESSAGE_BUFF_117 (117UL) +#define MCAN_MESSAGE_BUFF_118 (118UL) +#define MCAN_MESSAGE_BUFF_119 (119UL) +#define MCAN_MESSAGE_BUFF_120 (120UL) +#define MCAN_MESSAGE_BUFF_121 (121UL) +#define MCAN_MESSAGE_BUFF_122 (122UL) +#define MCAN_MESSAGE_BUFF_123 (123UL) +#define MCAN_MESSAGE_BUFF_124 (124UL) +#define MCAN_MESSAGE_BUFF_125 (125UL) +#define MCAN_MESSAGE_BUFF_126 (126UL) +#define MCAN_MESSAGE_BUFF_127 (127UL) +#define MCAN_MESSAGE_BUFF_128 (128UL) +#define MCAN_MESSAGE_BUFF_129 (129UL) +#define MCAN_MESSAGE_BUFF_130 (130UL) +#define MCAN_MESSAGE_BUFF_131 (131UL) +#define MCAN_MESSAGE_BUFF_132 (132UL) +#define MCAN_MESSAGE_BUFF_133 (133UL) +#define MCAN_MESSAGE_BUFF_134 (134UL) +#define MCAN_MESSAGE_BUFF_135 (135UL) +#define MCAN_MESSAGE_BUFF_136 (136UL) +#define MCAN_MESSAGE_BUFF_137 (137UL) +#define MCAN_MESSAGE_BUFF_138 (138UL) +#define MCAN_MESSAGE_BUFF_139 (139UL) +#define MCAN_MESSAGE_BUFF_140 (140UL) +#define MCAN_MESSAGE_BUFF_141 (141UL) +#define MCAN_MESSAGE_BUFF_142 (142UL) +#define MCAN_MESSAGE_BUFF_143 (143UL) +#define MCAN_MESSAGE_BUFF_144 (144UL) +#define MCAN_MESSAGE_BUFF_145 (145UL) +#define MCAN_MESSAGE_BUFF_146 (146UL) +#define MCAN_MESSAGE_BUFF_147 (147UL) +#define MCAN_MESSAGE_BUFF_148 (148UL) +#define MCAN_MESSAGE_BUFF_149 (149UL) +#define MCAN_MESSAGE_BUFF_150 (150UL) +#define MCAN_MESSAGE_BUFF_151 (151UL) +#define MCAN_MESSAGE_BUFF_152 (152UL) +#define MCAN_MESSAGE_BUFF_153 (153UL) +#define MCAN_MESSAGE_BUFF_154 (154UL) +#define MCAN_MESSAGE_BUFF_155 (155UL) +#define MCAN_MESSAGE_BUFF_156 (156UL) +#define MCAN_MESSAGE_BUFF_157 (157UL) +#define MCAN_MESSAGE_BUFF_158 (158UL) +#define MCAN_MESSAGE_BUFF_159 (159UL) +#define MCAN_MESSAGE_BUFF_160 (160UL) +#define MCAN_MESSAGE_BUFF_161 (161UL) +#define MCAN_MESSAGE_BUFF_162 (162UL) +#define MCAN_MESSAGE_BUFF_163 (163UL) +#define MCAN_MESSAGE_BUFF_164 (164UL) +#define MCAN_MESSAGE_BUFF_165 (165UL) +#define MCAN_MESSAGE_BUFF_166 (166UL) +#define MCAN_MESSAGE_BUFF_167 (167UL) +#define MCAN_MESSAGE_BUFF_168 (168UL) +#define MCAN_MESSAGE_BUFF_169 (169UL) +#define MCAN_MESSAGE_BUFF_170 (170UL) +#define MCAN_MESSAGE_BUFF_171 (171UL) +#define MCAN_MESSAGE_BUFF_172 (172UL) +#define MCAN_MESSAGE_BUFF_173 (173UL) +#define MCAN_MESSAGE_BUFF_174 (174UL) +#define MCAN_MESSAGE_BUFF_175 (175UL) +#define MCAN_MESSAGE_BUFF_176 (176UL) +#define MCAN_MESSAGE_BUFF_177 (177UL) +#define MCAN_MESSAGE_BUFF_178 (178UL) +#define MCAN_MESSAGE_BUFF_179 (179UL) +#define MCAN_MESSAGE_BUFF_180 (180UL) +#define MCAN_MESSAGE_BUFF_181 (181UL) +#define MCAN_MESSAGE_BUFF_182 (182UL) +#define MCAN_MESSAGE_BUFF_183 (183UL) +#define MCAN_MESSAGE_BUFF_184 (184UL) +#define MCAN_MESSAGE_BUFF_185 (185UL) +#define MCAN_MESSAGE_BUFF_186 (186UL) +#define MCAN_MESSAGE_BUFF_187 (187UL) +#define MCAN_MESSAGE_BUFF_188 (188UL) +#define MCAN_MESSAGE_BUFF_189 (189UL) +#define MCAN_MESSAGE_BUFF_190 (190UL) +#define MCAN_MESSAGE_BUFF_191 (191UL) +#define MCAN_MESSAGE_BUFF_192 (192UL) +#define MCAN_MESSAGE_BUFF_193 (193UL) +#define MCAN_MESSAGE_BUFF_194 (194UL) +#define MCAN_MESSAGE_BUFF_195 (195UL) +#define MCAN_MESSAGE_BUFF_196 (196UL) +#define MCAN_MESSAGE_BUFF_197 (197UL) +#define MCAN_MESSAGE_BUFF_198 (198UL) +#define MCAN_MESSAGE_BUFF_199 (199UL) +#define MCAN_MESSAGE_BUFF_200 (200UL) +#define MCAN_MESSAGE_BUFF_201 (201UL) +#define MCAN_MESSAGE_BUFF_202 (202UL) +#define MCAN_MESSAGE_BUFF_203 (203UL) +#define MCAN_MESSAGE_BUFF_204 (204UL) +#define MCAN_MESSAGE_BUFF_205 (205UL) +#define MCAN_MESSAGE_BUFF_206 (206UL) +#define MCAN_MESSAGE_BUFF_207 (207UL) +#define MCAN_MESSAGE_BUFF_208 (208UL) +#define MCAN_MESSAGE_BUFF_209 (209UL) +#define MCAN_MESSAGE_BUFF_210 (210UL) +#define MCAN_MESSAGE_BUFF_211 (211UL) +#define MCAN_MESSAGE_BUFF_212 (212UL) +#define MCAN_MESSAGE_BUFF_213 (213UL) +#define MCAN_MESSAGE_BUFF_214 (214UL) +#define MCAN_MESSAGE_BUFF_215 (215UL) +#define MCAN_MESSAGE_BUFF_216 (216UL) +#define MCAN_MESSAGE_BUFF_217 (217UL) +#define MCAN_MESSAGE_BUFF_218 (218UL) +#define MCAN_MESSAGE_BUFF_219 (219UL) +#define MCAN_MESSAGE_BUFF_220 (220UL) +#define MCAN_MESSAGE_BUFF_221 (221UL) +#define MCAN_MESSAGE_BUFF_222 (222UL) +#define MCAN_MESSAGE_BUFF_223 (223UL) +#define MCAN_MESSAGE_BUFF_224 (224UL) +#define MCAN_MESSAGE_BUFF_225 (225UL) +#define MCAN_MESSAGE_BUFF_226 (226UL) +#define MCAN_MESSAGE_BUFF_227 (227UL) +#define MCAN_MESSAGE_BUFF_228 (228UL) +#define MCAN_MESSAGE_BUFF_229 (229UL) +#define MCAN_MESSAGE_BUFF_230 (230UL) +#define MCAN_MESSAGE_BUFF_231 (231UL) +#define MCAN_MESSAGE_BUFF_232 (232UL) +#define MCAN_MESSAGE_BUFF_233 (233UL) +#define MCAN_MESSAGE_BUFF_234 (234UL) +#define MCAN_MESSAGE_BUFF_235 (235UL) +#define MCAN_MESSAGE_BUFF_236 (236UL) +#define MCAN_MESSAGE_BUFF_237 (237UL) +#define MCAN_MESSAGE_BUFF_238 (238UL) +#define MCAN_MESSAGE_BUFF_239 (239UL) +#define MCAN_MESSAGE_BUFF_240 (240UL) +#define MCAN_MESSAGE_BUFF_241 (241UL) +#define MCAN_MESSAGE_BUFF_242 (242UL) +#define MCAN_MESSAGE_BUFF_243 (243UL) +#define MCAN_MESSAGE_BUFF_244 (244UL) +#define MCAN_MESSAGE_BUFF_245 (245UL) +#define MCAN_MESSAGE_BUFF_246 (246UL) +#define MCAN_MESSAGE_BUFF_247 (247UL) +#define MCAN_MESSAGE_BUFF_248 (248UL) +#define MCAN_MESSAGE_BUFF_249 (249UL) +#define MCAN_MESSAGE_BUFF_250 (250UL) +#define MCAN_MESSAGE_BUFF_251 (251UL) +#define MCAN_MESSAGE_BUFF_252 (252UL) +#define MCAN_MESSAGE_BUFF_253 (253UL) +#define MCAN_MESSAGE_BUFF_254 (254UL) +#define MCAN_MESSAGE_BUFF_255 (255UL) +#define MCAN_MESSAGE_BUFF_256 (256UL) +#define MCAN_MESSAGE_BUFF_257 (257UL) +#define MCAN_MESSAGE_BUFF_258 (258UL) +#define MCAN_MESSAGE_BUFF_259 (259UL) +#define MCAN_MESSAGE_BUFF_260 (260UL) +#define MCAN_MESSAGE_BUFF_261 (261UL) +#define MCAN_MESSAGE_BUFF_262 (262UL) +#define MCAN_MESSAGE_BUFF_263 (263UL) +#define MCAN_MESSAGE_BUFF_264 (264UL) +#define MCAN_MESSAGE_BUFF_265 (265UL) +#define MCAN_MESSAGE_BUFF_266 (266UL) +#define MCAN_MESSAGE_BUFF_267 (267UL) +#define MCAN_MESSAGE_BUFF_268 (268UL) +#define MCAN_MESSAGE_BUFF_269 (269UL) +#define MCAN_MESSAGE_BUFF_270 (270UL) +#define MCAN_MESSAGE_BUFF_271 (271UL) +#define MCAN_MESSAGE_BUFF_272 (272UL) +#define MCAN_MESSAGE_BUFF_273 (273UL) +#define MCAN_MESSAGE_BUFF_274 (274UL) +#define MCAN_MESSAGE_BUFF_275 (275UL) +#define MCAN_MESSAGE_BUFF_276 (276UL) +#define MCAN_MESSAGE_BUFF_277 (277UL) +#define MCAN_MESSAGE_BUFF_278 (278UL) +#define MCAN_MESSAGE_BUFF_279 (279UL) +#define MCAN_MESSAGE_BUFF_280 (280UL) +#define MCAN_MESSAGE_BUFF_281 (281UL) +#define MCAN_MESSAGE_BUFF_282 (282UL) +#define MCAN_MESSAGE_BUFF_283 (283UL) +#define MCAN_MESSAGE_BUFF_284 (284UL) +#define MCAN_MESSAGE_BUFF_285 (285UL) +#define MCAN_MESSAGE_BUFF_286 (286UL) +#define MCAN_MESSAGE_BUFF_287 (287UL) +#define MCAN_MESSAGE_BUFF_288 (288UL) +#define MCAN_MESSAGE_BUFF_289 (289UL) +#define MCAN_MESSAGE_BUFF_290 (290UL) +#define MCAN_MESSAGE_BUFF_291 (291UL) +#define MCAN_MESSAGE_BUFF_292 (292UL) +#define MCAN_MESSAGE_BUFF_293 (293UL) +#define MCAN_MESSAGE_BUFF_294 (294UL) +#define MCAN_MESSAGE_BUFF_295 (295UL) +#define MCAN_MESSAGE_BUFF_296 (296UL) +#define MCAN_MESSAGE_BUFF_297 (297UL) +#define MCAN_MESSAGE_BUFF_298 (298UL) +#define MCAN_MESSAGE_BUFF_299 (299UL) +#define MCAN_MESSAGE_BUFF_300 (300UL) +#define MCAN_MESSAGE_BUFF_301 (301UL) +#define MCAN_MESSAGE_BUFF_302 (302UL) +#define MCAN_MESSAGE_BUFF_303 (303UL) +#define MCAN_MESSAGE_BUFF_304 (304UL) +#define MCAN_MESSAGE_BUFF_305 (305UL) +#define MCAN_MESSAGE_BUFF_306 (306UL) +#define MCAN_MESSAGE_BUFF_307 (307UL) +#define MCAN_MESSAGE_BUFF_308 (308UL) +#define MCAN_MESSAGE_BUFF_309 (309UL) +#define MCAN_MESSAGE_BUFF_310 (310UL) +#define MCAN_MESSAGE_BUFF_311 (311UL) +#define MCAN_MESSAGE_BUFF_312 (312UL) +#define MCAN_MESSAGE_BUFF_313 (313UL) +#define MCAN_MESSAGE_BUFF_314 (314UL) +#define MCAN_MESSAGE_BUFF_315 (315UL) +#define MCAN_MESSAGE_BUFF_316 (316UL) +#define MCAN_MESSAGE_BUFF_317 (317UL) +#define MCAN_MESSAGE_BUFF_318 (318UL) +#define MCAN_MESSAGE_BUFF_319 (319UL) +#define MCAN_MESSAGE_BUFF_320 (320UL) +#define MCAN_MESSAGE_BUFF_321 (321UL) +#define MCAN_MESSAGE_BUFF_322 (322UL) +#define MCAN_MESSAGE_BUFF_323 (323UL) +#define MCAN_MESSAGE_BUFF_324 (324UL) +#define MCAN_MESSAGE_BUFF_325 (325UL) +#define MCAN_MESSAGE_BUFF_326 (326UL) +#define MCAN_MESSAGE_BUFF_327 (327UL) +#define MCAN_MESSAGE_BUFF_328 (328UL) +#define MCAN_MESSAGE_BUFF_329 (329UL) +#define MCAN_MESSAGE_BUFF_330 (330UL) +#define MCAN_MESSAGE_BUFF_331 (331UL) +#define MCAN_MESSAGE_BUFF_332 (332UL) +#define MCAN_MESSAGE_BUFF_333 (333UL) +#define MCAN_MESSAGE_BUFF_334 (334UL) +#define MCAN_MESSAGE_BUFF_335 (335UL) +#define MCAN_MESSAGE_BUFF_336 (336UL) +#define MCAN_MESSAGE_BUFF_337 (337UL) +#define MCAN_MESSAGE_BUFF_338 (338UL) +#define MCAN_MESSAGE_BUFF_339 (339UL) +#define MCAN_MESSAGE_BUFF_340 (340UL) +#define MCAN_MESSAGE_BUFF_341 (341UL) +#define MCAN_MESSAGE_BUFF_342 (342UL) +#define MCAN_MESSAGE_BUFF_343 (343UL) +#define MCAN_MESSAGE_BUFF_344 (344UL) +#define MCAN_MESSAGE_BUFF_345 (345UL) +#define MCAN_MESSAGE_BUFF_346 (346UL) +#define MCAN_MESSAGE_BUFF_347 (347UL) +#define MCAN_MESSAGE_BUFF_348 (348UL) +#define MCAN_MESSAGE_BUFF_349 (349UL) +#define MCAN_MESSAGE_BUFF_350 (350UL) +#define MCAN_MESSAGE_BUFF_351 (351UL) +#define MCAN_MESSAGE_BUFF_352 (352UL) +#define MCAN_MESSAGE_BUFF_353 (353UL) +#define MCAN_MESSAGE_BUFF_354 (354UL) +#define MCAN_MESSAGE_BUFF_355 (355UL) +#define MCAN_MESSAGE_BUFF_356 (356UL) +#define MCAN_MESSAGE_BUFF_357 (357UL) +#define MCAN_MESSAGE_BUFF_358 (358UL) +#define MCAN_MESSAGE_BUFF_359 (359UL) +#define MCAN_MESSAGE_BUFF_360 (360UL) +#define MCAN_MESSAGE_BUFF_361 (361UL) +#define MCAN_MESSAGE_BUFF_362 (362UL) +#define MCAN_MESSAGE_BUFF_363 (363UL) +#define MCAN_MESSAGE_BUFF_364 (364UL) +#define MCAN_MESSAGE_BUFF_365 (365UL) +#define MCAN_MESSAGE_BUFF_366 (366UL) +#define MCAN_MESSAGE_BUFF_367 (367UL) +#define MCAN_MESSAGE_BUFF_368 (368UL) +#define MCAN_MESSAGE_BUFF_369 (369UL) +#define MCAN_MESSAGE_BUFF_370 (370UL) +#define MCAN_MESSAGE_BUFF_371 (371UL) +#define MCAN_MESSAGE_BUFF_372 (372UL) +#define MCAN_MESSAGE_BUFF_373 (373UL) +#define MCAN_MESSAGE_BUFF_374 (374UL) +#define MCAN_MESSAGE_BUFF_375 (375UL) +#define MCAN_MESSAGE_BUFF_376 (376UL) +#define MCAN_MESSAGE_BUFF_377 (377UL) +#define MCAN_MESSAGE_BUFF_378 (378UL) +#define MCAN_MESSAGE_BUFF_379 (379UL) +#define MCAN_MESSAGE_BUFF_380 (380UL) +#define MCAN_MESSAGE_BUFF_381 (381UL) +#define MCAN_MESSAGE_BUFF_382 (382UL) +#define MCAN_MESSAGE_BUFF_383 (383UL) +#define MCAN_MESSAGE_BUFF_384 (384UL) +#define MCAN_MESSAGE_BUFF_385 (385UL) +#define MCAN_MESSAGE_BUFF_386 (386UL) +#define MCAN_MESSAGE_BUFF_387 (387UL) +#define MCAN_MESSAGE_BUFF_388 (388UL) +#define MCAN_MESSAGE_BUFF_389 (389UL) +#define MCAN_MESSAGE_BUFF_390 (390UL) +#define MCAN_MESSAGE_BUFF_391 (391UL) +#define MCAN_MESSAGE_BUFF_392 (392UL) +#define MCAN_MESSAGE_BUFF_393 (393UL) +#define MCAN_MESSAGE_BUFF_394 (394UL) +#define MCAN_MESSAGE_BUFF_395 (395UL) +#define MCAN_MESSAGE_BUFF_396 (396UL) +#define MCAN_MESSAGE_BUFF_397 (397UL) +#define MCAN_MESSAGE_BUFF_398 (398UL) +#define MCAN_MESSAGE_BUFF_399 (399UL) +#define MCAN_MESSAGE_BUFF_400 (400UL) +#define MCAN_MESSAGE_BUFF_401 (401UL) +#define MCAN_MESSAGE_BUFF_402 (402UL) +#define MCAN_MESSAGE_BUFF_403 (403UL) +#define MCAN_MESSAGE_BUFF_404 (404UL) +#define MCAN_MESSAGE_BUFF_405 (405UL) +#define MCAN_MESSAGE_BUFF_406 (406UL) +#define MCAN_MESSAGE_BUFF_407 (407UL) +#define MCAN_MESSAGE_BUFF_408 (408UL) +#define MCAN_MESSAGE_BUFF_409 (409UL) +#define MCAN_MESSAGE_BUFF_410 (410UL) +#define MCAN_MESSAGE_BUFF_411 (411UL) +#define MCAN_MESSAGE_BUFF_412 (412UL) +#define MCAN_MESSAGE_BUFF_413 (413UL) +#define MCAN_MESSAGE_BUFF_414 (414UL) +#define MCAN_MESSAGE_BUFF_415 (415UL) +#define MCAN_MESSAGE_BUFF_416 (416UL) +#define MCAN_MESSAGE_BUFF_417 (417UL) +#define MCAN_MESSAGE_BUFF_418 (418UL) +#define MCAN_MESSAGE_BUFF_419 (419UL) +#define MCAN_MESSAGE_BUFF_420 (420UL) +#define MCAN_MESSAGE_BUFF_421 (421UL) +#define MCAN_MESSAGE_BUFF_422 (422UL) +#define MCAN_MESSAGE_BUFF_423 (423UL) +#define MCAN_MESSAGE_BUFF_424 (424UL) +#define MCAN_MESSAGE_BUFF_425 (425UL) +#define MCAN_MESSAGE_BUFF_426 (426UL) +#define MCAN_MESSAGE_BUFF_427 (427UL) +#define MCAN_MESSAGE_BUFF_428 (428UL) +#define MCAN_MESSAGE_BUFF_429 (429UL) +#define MCAN_MESSAGE_BUFF_430 (430UL) +#define MCAN_MESSAGE_BUFF_431 (431UL) +#define MCAN_MESSAGE_BUFF_432 (432UL) +#define MCAN_MESSAGE_BUFF_433 (433UL) +#define MCAN_MESSAGE_BUFF_434 (434UL) +#define MCAN_MESSAGE_BUFF_435 (435UL) +#define MCAN_MESSAGE_BUFF_436 (436UL) +#define MCAN_MESSAGE_BUFF_437 (437UL) +#define MCAN_MESSAGE_BUFF_438 (438UL) +#define MCAN_MESSAGE_BUFF_439 (439UL) +#define MCAN_MESSAGE_BUFF_440 (440UL) +#define MCAN_MESSAGE_BUFF_441 (441UL) +#define MCAN_MESSAGE_BUFF_442 (442UL) +#define MCAN_MESSAGE_BUFF_443 (443UL) +#define MCAN_MESSAGE_BUFF_444 (444UL) +#define MCAN_MESSAGE_BUFF_445 (445UL) +#define MCAN_MESSAGE_BUFF_446 (446UL) +#define MCAN_MESSAGE_BUFF_447 (447UL) +#define MCAN_MESSAGE_BUFF_448 (448UL) +#define MCAN_MESSAGE_BUFF_449 (449UL) +#define MCAN_MESSAGE_BUFF_450 (450UL) +#define MCAN_MESSAGE_BUFF_451 (451UL) +#define MCAN_MESSAGE_BUFF_452 (452UL) +#define MCAN_MESSAGE_BUFF_453 (453UL) +#define MCAN_MESSAGE_BUFF_454 (454UL) +#define MCAN_MESSAGE_BUFF_455 (455UL) +#define MCAN_MESSAGE_BUFF_456 (456UL) +#define MCAN_MESSAGE_BUFF_457 (457UL) +#define MCAN_MESSAGE_BUFF_458 (458UL) +#define MCAN_MESSAGE_BUFF_459 (459UL) +#define MCAN_MESSAGE_BUFF_460 (460UL) +#define MCAN_MESSAGE_BUFF_461 (461UL) +#define MCAN_MESSAGE_BUFF_462 (462UL) +#define MCAN_MESSAGE_BUFF_463 (463UL) +#define MCAN_MESSAGE_BUFF_464 (464UL) +#define MCAN_MESSAGE_BUFF_465 (465UL) +#define MCAN_MESSAGE_BUFF_466 (466UL) +#define MCAN_MESSAGE_BUFF_467 (467UL) +#define MCAN_MESSAGE_BUFF_468 (468UL) +#define MCAN_MESSAGE_BUFF_469 (469UL) +#define MCAN_MESSAGE_BUFF_470 (470UL) +#define MCAN_MESSAGE_BUFF_471 (471UL) +#define MCAN_MESSAGE_BUFF_472 (472UL) +#define MCAN_MESSAGE_BUFF_473 (473UL) +#define MCAN_MESSAGE_BUFF_474 (474UL) +#define MCAN_MESSAGE_BUFF_475 (475UL) +#define MCAN_MESSAGE_BUFF_476 (476UL) +#define MCAN_MESSAGE_BUFF_477 (477UL) +#define MCAN_MESSAGE_BUFF_478 (478UL) +#define MCAN_MESSAGE_BUFF_479 (479UL) +#define MCAN_MESSAGE_BUFF_480 (480UL) +#define MCAN_MESSAGE_BUFF_481 (481UL) +#define MCAN_MESSAGE_BUFF_482 (482UL) +#define MCAN_MESSAGE_BUFF_483 (483UL) +#define MCAN_MESSAGE_BUFF_484 (484UL) +#define MCAN_MESSAGE_BUFF_485 (485UL) +#define MCAN_MESSAGE_BUFF_486 (486UL) +#define MCAN_MESSAGE_BUFF_487 (487UL) +#define MCAN_MESSAGE_BUFF_488 (488UL) +#define MCAN_MESSAGE_BUFF_489 (489UL) +#define MCAN_MESSAGE_BUFF_490 (490UL) +#define MCAN_MESSAGE_BUFF_491 (491UL) +#define MCAN_MESSAGE_BUFF_492 (492UL) +#define MCAN_MESSAGE_BUFF_493 (493UL) +#define MCAN_MESSAGE_BUFF_494 (494UL) +#define MCAN_MESSAGE_BUFF_495 (495UL) +#define MCAN_MESSAGE_BUFF_496 (496UL) +#define MCAN_MESSAGE_BUFF_497 (497UL) +#define MCAN_MESSAGE_BUFF_498 (498UL) +#define MCAN_MESSAGE_BUFF_499 (499UL) +#define MCAN_MESSAGE_BUFF_500 (500UL) +#define MCAN_MESSAGE_BUFF_501 (501UL) +#define MCAN_MESSAGE_BUFF_502 (502UL) +#define MCAN_MESSAGE_BUFF_503 (503UL) +#define MCAN_MESSAGE_BUFF_504 (504UL) +#define MCAN_MESSAGE_BUFF_505 (505UL) +#define MCAN_MESSAGE_BUFF_506 (506UL) +#define MCAN_MESSAGE_BUFF_507 (507UL) +#define MCAN_MESSAGE_BUFF_508 (508UL) +#define MCAN_MESSAGE_BUFF_509 (509UL) +#define MCAN_MESSAGE_BUFF_510 (510UL) +#define MCAN_MESSAGE_BUFF_511 (511UL) +#define MCAN_MESSAGE_BUFF_512 (512UL) +#define MCAN_MESSAGE_BUFF_513 (513UL) +#define MCAN_MESSAGE_BUFF_514 (514UL) +#define MCAN_MESSAGE_BUFF_515 (515UL) +#define MCAN_MESSAGE_BUFF_516 (516UL) +#define MCAN_MESSAGE_BUFF_517 (517UL) +#define MCAN_MESSAGE_BUFF_518 (518UL) +#define MCAN_MESSAGE_BUFF_519 (519UL) +#define MCAN_MESSAGE_BUFF_520 (520UL) +#define MCAN_MESSAGE_BUFF_521 (521UL) +#define MCAN_MESSAGE_BUFF_522 (522UL) +#define MCAN_MESSAGE_BUFF_523 (523UL) +#define MCAN_MESSAGE_BUFF_524 (524UL) +#define MCAN_MESSAGE_BUFF_525 (525UL) +#define MCAN_MESSAGE_BUFF_526 (526UL) +#define MCAN_MESSAGE_BUFF_527 (527UL) +#define MCAN_MESSAGE_BUFF_528 (528UL) +#define MCAN_MESSAGE_BUFF_529 (529UL) +#define MCAN_MESSAGE_BUFF_530 (530UL) +#define MCAN_MESSAGE_BUFF_531 (531UL) +#define MCAN_MESSAGE_BUFF_532 (532UL) +#define MCAN_MESSAGE_BUFF_533 (533UL) +#define MCAN_MESSAGE_BUFF_534 (534UL) +#define MCAN_MESSAGE_BUFF_535 (535UL) +#define MCAN_MESSAGE_BUFF_536 (536UL) +#define MCAN_MESSAGE_BUFF_537 (537UL) +#define MCAN_MESSAGE_BUFF_538 (538UL) +#define MCAN_MESSAGE_BUFF_539 (539UL) +#define MCAN_MESSAGE_BUFF_540 (540UL) +#define MCAN_MESSAGE_BUFF_541 (541UL) +#define MCAN_MESSAGE_BUFF_542 (542UL) +#define MCAN_MESSAGE_BUFF_543 (543UL) +#define MCAN_MESSAGE_BUFF_544 (544UL) +#define MCAN_MESSAGE_BUFF_545 (545UL) +#define MCAN_MESSAGE_BUFF_546 (546UL) +#define MCAN_MESSAGE_BUFF_547 (547UL) +#define MCAN_MESSAGE_BUFF_548 (548UL) +#define MCAN_MESSAGE_BUFF_549 (549UL) +#define MCAN_MESSAGE_BUFF_550 (550UL) +#define MCAN_MESSAGE_BUFF_551 (551UL) +#define MCAN_MESSAGE_BUFF_552 (552UL) +#define MCAN_MESSAGE_BUFF_553 (553UL) +#define MCAN_MESSAGE_BUFF_554 (554UL) +#define MCAN_MESSAGE_BUFF_555 (555UL) +#define MCAN_MESSAGE_BUFF_556 (556UL) +#define MCAN_MESSAGE_BUFF_557 (557UL) +#define MCAN_MESSAGE_BUFF_558 (558UL) +#define MCAN_MESSAGE_BUFF_559 (559UL) +#define MCAN_MESSAGE_BUFF_560 (560UL) +#define MCAN_MESSAGE_BUFF_561 (561UL) +#define MCAN_MESSAGE_BUFF_562 (562UL) +#define MCAN_MESSAGE_BUFF_563 (563UL) +#define MCAN_MESSAGE_BUFF_564 (564UL) +#define MCAN_MESSAGE_BUFF_565 (565UL) +#define MCAN_MESSAGE_BUFF_566 (566UL) +#define MCAN_MESSAGE_BUFF_567 (567UL) +#define MCAN_MESSAGE_BUFF_568 (568UL) +#define MCAN_MESSAGE_BUFF_569 (569UL) +#define MCAN_MESSAGE_BUFF_570 (570UL) +#define MCAN_MESSAGE_BUFF_571 (571UL) +#define MCAN_MESSAGE_BUFF_572 (572UL) +#define MCAN_MESSAGE_BUFF_573 (573UL) +#define MCAN_MESSAGE_BUFF_574 (574UL) +#define MCAN_MESSAGE_BUFF_575 (575UL) +#define MCAN_MESSAGE_BUFF_576 (576UL) +#define MCAN_MESSAGE_BUFF_577 (577UL) +#define MCAN_MESSAGE_BUFF_578 (578UL) +#define MCAN_MESSAGE_BUFF_579 (579UL) +#define MCAN_MESSAGE_BUFF_580 (580UL) +#define MCAN_MESSAGE_BUFF_581 (581UL) +#define MCAN_MESSAGE_BUFF_582 (582UL) +#define MCAN_MESSAGE_BUFF_583 (583UL) +#define MCAN_MESSAGE_BUFF_584 (584UL) +#define MCAN_MESSAGE_BUFF_585 (585UL) +#define MCAN_MESSAGE_BUFF_586 (586UL) +#define MCAN_MESSAGE_BUFF_587 (587UL) +#define MCAN_MESSAGE_BUFF_588 (588UL) +#define MCAN_MESSAGE_BUFF_589 (589UL) +#define MCAN_MESSAGE_BUFF_590 (590UL) +#define MCAN_MESSAGE_BUFF_591 (591UL) +#define MCAN_MESSAGE_BUFF_592 (592UL) +#define MCAN_MESSAGE_BUFF_593 (593UL) +#define MCAN_MESSAGE_BUFF_594 (594UL) +#define MCAN_MESSAGE_BUFF_595 (595UL) +#define MCAN_MESSAGE_BUFF_596 (596UL) +#define MCAN_MESSAGE_BUFF_597 (597UL) +#define MCAN_MESSAGE_BUFF_598 (598UL) +#define MCAN_MESSAGE_BUFF_599 (599UL) +#define MCAN_MESSAGE_BUFF_600 (600UL) +#define MCAN_MESSAGE_BUFF_601 (601UL) +#define MCAN_MESSAGE_BUFF_602 (602UL) +#define MCAN_MESSAGE_BUFF_603 (603UL) +#define MCAN_MESSAGE_BUFF_604 (604UL) +#define MCAN_MESSAGE_BUFF_605 (605UL) +#define MCAN_MESSAGE_BUFF_606 (606UL) +#define MCAN_MESSAGE_BUFF_607 (607UL) +#define MCAN_MESSAGE_BUFF_608 (608UL) +#define MCAN_MESSAGE_BUFF_609 (609UL) +#define MCAN_MESSAGE_BUFF_610 (610UL) +#define MCAN_MESSAGE_BUFF_611 (611UL) +#define MCAN_MESSAGE_BUFF_612 (612UL) +#define MCAN_MESSAGE_BUFF_613 (613UL) +#define MCAN_MESSAGE_BUFF_614 (614UL) +#define MCAN_MESSAGE_BUFF_615 (615UL) +#define MCAN_MESSAGE_BUFF_616 (616UL) +#define MCAN_MESSAGE_BUFF_617 (617UL) +#define MCAN_MESSAGE_BUFF_618 (618UL) +#define MCAN_MESSAGE_BUFF_619 (619UL) +#define MCAN_MESSAGE_BUFF_620 (620UL) +#define MCAN_MESSAGE_BUFF_621 (621UL) +#define MCAN_MESSAGE_BUFF_622 (622UL) +#define MCAN_MESSAGE_BUFF_623 (623UL) +#define MCAN_MESSAGE_BUFF_624 (624UL) +#define MCAN_MESSAGE_BUFF_625 (625UL) +#define MCAN_MESSAGE_BUFF_626 (626UL) +#define MCAN_MESSAGE_BUFF_627 (627UL) +#define MCAN_MESSAGE_BUFF_628 (628UL) +#define MCAN_MESSAGE_BUFF_629 (629UL) +#define MCAN_MESSAGE_BUFF_630 (630UL) +#define MCAN_MESSAGE_BUFF_631 (631UL) +#define MCAN_MESSAGE_BUFF_632 (632UL) +#define MCAN_MESSAGE_BUFF_633 (633UL) +#define MCAN_MESSAGE_BUFF_634 (634UL) +#define MCAN_MESSAGE_BUFF_635 (635UL) +#define MCAN_MESSAGE_BUFF_636 (636UL) +#define MCAN_MESSAGE_BUFF_637 (637UL) +#define MCAN_MESSAGE_BUFF_638 (638UL) +#define MCAN_MESSAGE_BUFF_639 (639UL) + + +#endif /* HPM_MCAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h index e54a80d7e2..9183123142 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -40,4 +40,4 @@ typedef struct { -#endif /* HPM_MCHTMR_H */ \ No newline at end of file +#endif /* HPM_MCHTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h index 9b39012b95..694060dbcc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -78,7 +78,7 @@ typedef struct { * FLAG (RW) * * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt + * 0: no monitor interrupt * 1: monitor interrupt happened * Note: This register only available in PMIC domain */ @@ -110,4 +110,4 @@ typedef struct { #define MON_MONITOR_CLOCK1 (3UL) -#endif /* HPM_MON_H */ \ No newline at end of file +#endif /* HPM_MON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h index 0db009eabf..12b9a5c9fb 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -50,4 +50,4 @@ typedef struct { -#endif /* HPM_MONO_H */ \ No newline at end of file +#endif /* HPM_MONO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h index 821405f19b..41e11712e7 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -557,4 +557,4 @@ typedef struct { #define OTP_REGION_LOAD_REGION3 (3UL) -#endif /* HPM_OTP_H */ \ No newline at end of file +#endif /* HPM_OTP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h index 015a8c1d3e..f591980906 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -489,4 +489,4 @@ typedef struct { -#endif /* HPM_PDM_H */ \ No newline at end of file +#endif /* HPM_PDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h index aca242a62a..32de012adc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -176,7 +176,7 @@ typedef struct { /* Bitfield definition for register: STAT */ /* - * BLOCKY (ROI) + * BLOCKY (RO) * * Y block that is processing */ @@ -185,7 +185,7 @@ typedef struct { #define PDMA_STAT_BLOCKY_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKY_MASK) >> PDMA_STAT_BLOCKY_SHIFT) /* - * BLOCKX (ROI) + * BLOCKX (RO) * * X block that is processing */ @@ -194,7 +194,7 @@ typedef struct { #define PDMA_STAT_BLOCKX_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKX_MASK) >> PDMA_STAT_BLOCKX_SHIFT) /* - * PDMA_DONE (ROI) + * PDMA_DONE (RO) * * PDMA one image done */ @@ -203,7 +203,7 @@ typedef struct { #define PDMA_STAT_PDMA_DONE_GET(x) (((uint32_t)(x) & PDMA_STAT_PDMA_DONE_MASK) >> PDMA_STAT_PDMA_DONE_SHIFT) /* - * AXI_ERR_ID (ROI) + * AXI_ERR_ID (RO) * * AXI error ID */ @@ -279,7 +279,7 @@ typedef struct { * 0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream * 1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) * 2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream - * Others: Reserved + * 3: don't multiply the color data with any alpha values for blender inputs. */ #define PDMA_OUT_CTRL_DSTALPHA_OP_MASK (0xC000U) #define PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT (14U) @@ -293,7 +293,7 @@ typedef struct { * 0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream * 1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) * 2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream - * Others: Reserved + * 3: don't multiply the color data with any alpha values for blender inputs. */ #define PDMA_OUT_CTRL_SRCALPHA_OP_MASK (0x3000U) #define PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT (12U) @@ -327,6 +327,16 @@ typedef struct { #define PDMA_OUT_CTRL_ABLEND_MODE_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) #define PDMA_OUT_CTRL_ABLEND_MODE_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) >> PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) +/* + * NORM_OUT (RW) + * + * Asserted to normalize the output color channels with alpha channels + */ +#define PDMA_OUT_CTRL_NORM_OUT_MASK (0x80U) +#define PDMA_OUT_CTRL_NORM_OUT_SHIFT (7U) +#define PDMA_OUT_CTRL_NORM_OUT_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_NORM_OUT_SHIFT) & PDMA_OUT_CTRL_NORM_OUT_MASK) +#define PDMA_OUT_CTRL_NORM_OUT_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_NORM_OUT_MASK) >> PDMA_OUT_CTRL_NORM_OUT_SHIFT) + /* * FORMAT (RW) * @@ -428,6 +438,17 @@ typedef struct { #define PDMA_OUT_PS_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_X_MASK) >> PDMA_OUT_PS_LRC_X_SHIFT) /* Bitfield definition for register of struct array PS: CTRL */ +/* + * PL_ONLY_BLENDOP (RW) + * + * 1: For those pixels that are this plane-only, use the colcor values and alpha values directly as blender output for un-normalized outputs configurations. + * 0: For those pixels that are this plane-only, the operations are determined by other operation configurations. + */ +#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK (0x1000000UL) +#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT (24U) +#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT) & PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK) +#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK) >> PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT) + /* * INB13_SWAP (RW) * @@ -909,4 +930,4 @@ typedef struct { #define PDMA_PS_1 (1UL) -#endif /* HPM_PDMA_H */ \ No newline at end of file +#endif /* HPM_PDMA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pla_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pla_regs.h new file mode 100644 index 0000000000..7527e041a4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pla_regs.h @@ -0,0 +1,1708 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLA_H +#define HPM_PLA_H + +typedef struct { + struct { + __RW uint32_t AOI_16TO8[8]; /* 0x0 - 0x1C: CHN AOI_16to8 AND logic cfg */ + __RW uint32_t AOI_8TO7_00_01; /* 0x20: CHN AOI_16to8_00_01 OR logic cfg */ + __RW uint32_t AOI_8TO7_02_03; /* 0x24: CHN AOI_16to8_02_03 OR logic cfg */ + __RW uint32_t AOI_8TO7_04_05; /* 0x28: CHN AOI_16to8_04_05 OR logic cfg */ + __RW uint32_t AOI_8TO7_06; /* 0x2C: CHN AOI_16to8_06 OR logic cfg */ + __RW uint32_t FILTER_2ND[8]; /* 0x30 - 0x4C: CHN SECOND_FILTER cfg */ + __RW uint32_t FILTER_3RD[7]; /* 0x50 - 0x68: CHN THIRD_FILTER cfg */ + __RW uint32_t CFG_FF; /* 0x6C: CHN cfg ff */ + } CHN[8]; + __R uint8_t RESERVED0[64]; /* 0x380 - 0x3BF: Reserved */ + __RW uint32_t FILTER_1ST_PLA_IN[8]; /* 0x3C0 - 0x3DC: FRIST_FILTER_PLA_IN setting */ + __RW uint32_t FILTER_1ST_PLA_OUT[8]; /* 0x3E0 - 0x3FC: FRIST_FILTER_PLA_OUT setting */ + __RW uint32_t CHN_CFG_ACTIVE[8]; /* 0x400 - 0x41C: CHN cfg active */ +} PLA_Type; + + +/* Bitfield definition for register of struct array CHN: AOI_16TO8_00 */ +/* + * AOI_16TO8_15 (RW) + * + * select value for AOI_16to8_15. + * 0: 0. + * 1: 1st_filter_out[15]. + * 2: ~1st_filter_out[15]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK (0xC0000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT (30U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) + +/* + * AOI_16TO8_14 (RW) + * + * select value for AOI_16to8_14. + * 0: 0. + * 1: 1st_filter_out[14]. + * 2: ~1st_filter_out[14]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK (0x30000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT (28U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) + +/* + * AOI_16TO8_13 (RW) + * + * select value for AOI_16to8_13. + * 0: 0. + * 1: 1st_filter_out[13]. + * 2: ~1st_filter_out[13]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK (0xC000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT (26U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) + +/* + * AOI_16TO8_12 (RW) + * + * select value for AOI_16to8_12. + * 0: 0. + * 1: 1st_filter_out[12]. + * 2: ~1st_filter_out[12]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK (0x3000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT (24U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) + +/* + * AOI_16TO8_11 (RW) + * + * select value for AOI_16to8_11. + * 0: 0. + * 1: 1st_filter_out[11]. + * 2: ~1st_filter_out[11]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK (0xC00000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT (22U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) + +/* + * AOI_16TO8_10 (RW) + * + * select value for AOI_16to8_10. + * 0: 0. + * 1: 1st_filter_out[10]. + * 2: ~1st_filter_out[10]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK (0x300000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT (20U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) + +/* + * AOI_16TO8_9 (RW) + * + * select value for AOI_16to8_9. + * 0: 0. + * 1: 1st_filter_out[9]. + * 2: ~1st_filter_out[9]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK (0xC0000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT (18U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) + +/* + * AOI_16TO8_8 (RW) + * + * select value for AOI_16to8_8. + * 0: 0. + * 1: 1st_filter_out[8]. + * 2: ~1st_filter_out[8]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK (0x30000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT (16U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) + +/* + * AOI_16TO8_7 (RW) + * + * select value for AOI_16to8_7. + * 0: 0. + * 1: 1st_filter_out[7]. + * 2: ~1st_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK (0xC000U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT (14U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) + +/* + * AOI_16TO8_6 (RW) + * + * select value for AOI_16to8_6. + * 0: 0. + * 1: 1st_filter_out[6]. + * 2: ~1st_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK (0x3000U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT (12U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) + +/* + * AOI_16TO8_5 (RW) + * + * select value for AOI_16to8_5. + * 0: 0. + * 1: 1st_filter_out[5]. + * 2: ~1st_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK (0xC00U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT (10U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) + +/* + * AOI_16TO8_4 (RW) + * + * select value for AOI_16to8_4. + * 0: 0. + * 1: 1st_filter_out[4]. + * 2: ~1st_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK (0x300U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT (8U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) + +/* + * AOI_16TO8_3 (RW) + * + * select value for AOI_16to8_3. + * 0: 0. + * 1: 1st_filter_out[3]. + * 2: ~1st_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK (0xC0U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT (6U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) + +/* + * AOI_16TO8_2 (RW) + * + * select value for AOI_16to8_2. + * 0: 0. + * 1: 1st_filter_out[2]. + * 2: ~1st_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK (0x30U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT (4U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) + +/* + * AOI_16TO8_1 (RW) + * + * select value for AOI_16to8_1. + * 0: 0. + * 1: 1st_filter_out[1]. + * 2: ~1st_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK (0xCU) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT (2U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) + +/* + * AOI_16TO8_0 (RW) + * + * select value for AOI_16to8_0. + * 0: 0. + * 1: 1st_filter_out[0]. + * 2: ~1st_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK (0x3U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT (0U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_00_01 */ +/* + * AOI_8TO7_01_7 (RW) + * + * select value for AOI_8to7_01_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK (0xC0000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT (30U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) + +/* + * AOI_8TO7_01_6 (RW) + * + * select value for AOI_8to7_01_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK (0x30000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT (28U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) + +/* + * AOI_8TO7_01_5 (RW) + * + * select value for AOI_8to7_01_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK (0xC000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT (26U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) + +/* + * AOI_8TO7_01_4 (RW) + * + * select value for AOI_8to7_01_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK (0x3000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT (24U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) + +/* + * AOI_8TO7_01_3 (RW) + * + * select value for AOI_8to7_01_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK (0xC00000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT (22U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) + +/* + * AOI_8TO7_01_2 (RW) + * + * select value for AOI_8to7_01_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK (0x300000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT (20U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) + +/* + * AOI_8TO7_01_1 (RW) + * + * select value for AOI_8to7_01_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK (0xC0000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT (18U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) + +/* + * AOI_8TO7_01_0 (RW) + * + * select value for AOI_8to7_01_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK (0x30000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT (16U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) + +/* + * AOI_8TO7_00_7 (RW) + * + * select value for AOI_8to7_00_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) + +/* + * AOI_8TO7_00_6 (RW) + * + * select value for AOI_8to7_00_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) + +/* + * AOI_8TO7_00_5 (RW) + * + * select value for AOI_8to7_00_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) + +/* + * AOI_8TO7_00_4 (RW) + * + * select value for AOI_8to7_00_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) + +/* + * AOI_8TO7_00_3 (RW) + * + * select value for AOI_8to7_00_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) + +/* + * AOI_8TO7_00_2 (RW) + * + * select value for AOI_8to7_00_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) + +/* + * AOI_8TO7_00_1 (RW) + * + * select value for AOI_8to7_00_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) + +/* + * AOI_8TO7_00_0 (RW) + * + * select value for AOI_8to7_00_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_02_03 */ +/* + * AOI_8TO7_03_7 (RW) + * + * select value for AOI_8to7_03_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK (0xC0000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT (30U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) + +/* + * AOI_8TO7_03_6 (RW) + * + * select value for AOI_8to7_03_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK (0x30000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT (28U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) + +/* + * AOI_8TO7_03_5 (RW) + * + * select value for AOI_8to7_03_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK (0xC000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT (26U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) + +/* + * AOI_8TO7_03_4 (RW) + * + * select value for AOI_8to7_03_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK (0x3000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT (24U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) + +/* + * AOI_8TO7_03_3 (RW) + * + * select value for AOI_8to7_03_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK (0xC00000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT (22U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) + +/* + * AOI_8TO7_03_2 (RW) + * + * select value for AOI_8to7_03_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK (0x300000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT (20U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) + +/* + * AOI_8TO7_03_1 (RW) + * + * select value for AOI_8to7_03_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK (0xC0000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT (18U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) + +/* + * AOI_8TO7_03_0 (RW) + * + * select value for AOI_8to7_03_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK (0x30000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT (16U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) + +/* + * AOI_8TO7_02_7 (RW) + * + * select value for AOI_8to7_02_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) + +/* + * AOI_8TO7_02_6 (RW) + * + * select value for AOI_8to7_02_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) + +/* + * AOI_8TO7_02_5 (RW) + * + * select value for AOI_8to7_02_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) + +/* + * AOI_8TO7_02_4 (RW) + * + * select value for AOI_8to7_02_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) + +/* + * AOI_8TO7_02_3 (RW) + * + * select value for AOI_8to7_02_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) + +/* + * AOI_8TO7_02_2 (RW) + * + * select value for AOI_8to7_02_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) + +/* + * AOI_8TO7_02_1 (RW) + * + * select value for AOI_8to7_02_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) + +/* + * AOI_8TO7_02_0 (RW) + * + * select value for AOI_8to7_02_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_04_05 */ +/* + * AOI_8TO7_05_7 (RW) + * + * select value for AOI_8to7_05_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK (0xC0000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT (30U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) + +/* + * AOI_8TO7_05_6 (RW) + * + * select value for AOI_8to7_05_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK (0x30000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT (28U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) + +/* + * AOI_8TO7_05_5 (RW) + * + * select value for AOI_8to7_05_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK (0xC000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT (26U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) + +/* + * AOI_8TO7_05_4 (RW) + * + * select value for AOI_8to7_05_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK (0x3000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT (24U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) + +/* + * AOI_8TO7_05_3 (RW) + * + * select value for AOI_8to7_05_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK (0xC00000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT (22U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) + +/* + * AOI_8TO7_05_2 (RW) + * + * select value for AOI_8to7_05_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK (0x300000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT (20U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) + +/* + * AOI_8TO7_05_1 (RW) + * + * select value for AOI_8to7_05_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK (0xC0000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT (18U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) + +/* + * AOI_8TO7_05_0 (RW) + * + * select value for AOI_8to7_05_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK (0x30000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT (16U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) + +/* + * AOI_8TO7_04_7 (RW) + * + * select value for AOI_8to7_04_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) + +/* + * AOI_8TO7_04_6 (RW) + * + * select value for AOI_8to7_04_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) + +/* + * AOI_8TO7_04_5 (RW) + * + * select value for AOI_8to7_04_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) + +/* + * AOI_8TO7_04_4 (RW) + * + * select value for AOI_8to7_04_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) + +/* + * AOI_8TO7_04_3 (RW) + * + * select value for AOI_8to7_04_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) + +/* + * AOI_8TO7_04_2 (RW) + * + * select value for AOI_8to7_04_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) + +/* + * AOI_8TO7_04_1 (RW) + * + * select value for AOI_8to7_04_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) + +/* + * AOI_8TO7_04_0 (RW) + * + * select value for AOI_8to7_04_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_06 */ +/* + * AOI_8TO7_06_7 (RW) + * + * select value for AOI_8to7_06_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) + +/* + * AOI_8TO7_06_6 (RW) + * + * select value for AOI_8to7_06_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) + +/* + * AOI_8TO7_06_5 (RW) + * + * select value for AOI_8to7_06_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) + +/* + * AOI_8TO7_06_4 (RW) + * + * select value for AOI_8to7_06_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) + +/* + * AOI_8TO7_06_3 (RW) + * + * select value for AOI_8to7_06_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) + +/* + * AOI_8TO7_06_2 (RW) + * + * select value for AOI_8to7_06_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) + +/* + * AOI_8TO7_06_1 (RW) + * + * select value for AOI_8to7_06_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) + +/* + * AOI_8TO7_06_0 (RW) + * + * select value for AOI_8to7_06_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: SECOND_FILTER_0 */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK (0x8U) +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT (3U) +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CHN: THIRD_FILTER_0 */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK (0x8U) +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT (3U) +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CHN: CFG_FF */ +/* + * OSC_LOOP_CLAMP_VALUE (RW) + * + * osc loop clamp value when osc ring active. + * 0: clamp 0. + * 1: clamp 1. + */ +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK (0x20000UL) +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT (17U) +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) >> PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) + +/* + * DIS_OSC_LOOP_CLAMP (RW) + * + * disable osc loop clamp. + * 0: enable osc loop clamp when osc ring active. + * 1: disable or clean current osc loop clamp. + */ +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK (0x10000UL) +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT (16U) +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) >> PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) + +/* + * SEL_ADDER_MINUS (RW) + * + * 0: select adder when cfg_adder_minus active. + * 1: select minus when cfg_adder_minus active. + */ +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK (0x10U) +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT (4U) +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) >> PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) + +/* + * SEL_CLK_SOURCE (RW) + * + * cfg_ff clock source. + * 0: system clock. + * 1: use 3rd_filter_2 as clock. + */ +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK (0x8U) +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT (3U) +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) >> PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) + +/* + * SEL_CFG_FF_TYPE (RW) + * + * cfg_ff type. + * 0: DFF. + * 1: 3rd_filter_0. + * 2: dual-edge DFF. + * 3: Trigger FF. + * 4: JK FF. + * 5. latch. + * 6: full adder/minus. + */ +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK (0x7U) +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT (0U) +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) >> PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) + +/* Bitfield definition for register array: FILTER_1ST_PLA_IN */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK (0x8U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT (3U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register array: FILTER_1ST_PLA_OUT */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK (0x8U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT (3U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register array: CHN_CFG_ACTIVE */ +/* + * CFG_ACTIVE (RW) + * + * write 0xF00D to enable all setting. Otherwire, all setting inactive. + */ +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK (0xFFFFU) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT (0U) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) >> PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) + + + +/* AOI_16TO8 register group index macro definition */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_00 (0UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_01 (1UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_02 (2UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_03 (3UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_04 (4UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_05 (5UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_06 (6UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_07 (7UL) + +/* FILTER_2ND register group index macro definition */ +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_0 (0UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_1 (1UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_2 (2UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_3 (3UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_4 (4UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_5 (5UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_6 (6UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_7 (7UL) + +/* FILTER_3RD register group index macro definition */ +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_0 (0UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_1 (1UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_2 (2UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_3 (3UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_4 (4UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_5 (5UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_6 (6UL) + +/* CHN register group index macro definition */ +#define PLA_CHN_0 (0UL) +#define PLA_CHN_1 (1UL) +#define PLA_CHN_2 (2UL) +#define PLA_CHN_3 (3UL) +#define PLA_CHN_4 (4UL) +#define PLA_CHN_5 (5UL) +#define PLA_CHN_6 (6UL) +#define PLA_CHN_7 (7UL) + +/* FILTER_1ST_PLA_IN register group index macro definition */ +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0 (0UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1 (1UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2 (2UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3 (3UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4 (4UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5 (5UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6 (6UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7 (7UL) + +/* FILTER_1ST_PLA_OUT register group index macro definition */ +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0 (0UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0 (0UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1 (1UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2 (2UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3 (3UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4 (4UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5 (5UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6 (6UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7 (7UL) + +/* CHN_CFG_ACTIVE register group index macro definition */ +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0 (0UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1 (1UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2 (2UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3 (3UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4 (4UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5 (5UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6 (6UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7 (7UL) + + +#endif /* HPM_PLA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h index 48c410378e..c7dd01a027 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -140,10 +140,10 @@ typedef struct { * * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. */ -#define PLIC_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_INTEN_INTERRUPT_SHIFT) & PLIC_INTEN_INTERRUPT_MASK) -#define PLIC_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_INTEN_INTERRUPT_MASK) >> PLIC_INTEN_INTERRUPT_SHIFT) +#define PLIC_TARGETINT_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) +#define PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT (0U) +#define PLIC_TARGETINT_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) +#define PLIC_TARGETINT_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) >> PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) /* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ /* @@ -336,4 +336,4 @@ typedef struct { #define PLIC_TARGETCONFIG_TARGET1 (1UL) -#endif /* HPM_PLIC_H */ \ No newline at end of file +#endif /* HPM_PLIC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h index dd6d68646c..c9eea94496 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -55,4 +55,4 @@ typedef struct { -#endif /* HPM_PLIC_SW_H */ \ No newline at end of file +#endif /* HPM_PLIC_SW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h index c3bf35c7d4..166e54c0fd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -443,4 +443,4 @@ typedef struct { #define PLLCTL_PLL_PLL4 (4UL) -#endif /* HPM_PLLCTL_H */ \ No newline at end of file +#endif /* HPM_PLLCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h index 17de80ac8f..1345f6f9d4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -249,9 +249,9 @@ typedef struct { * 0: divider is working * 1: divider is changing status */ -#define PLLCTLV2_DIV_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_DIV_BUSY_SHIFT (31U) -#define PLLCTLV2_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_BUSY_MASK) >> PLLCTLV2_DIV_BUSY_SHIFT) +#define PLLCTLV2_PLL_DIV_BUSY_MASK (0x80000000UL) +#define PLLCTLV2_PLL_DIV_BUSY_SHIFT (31U) +#define PLLCTLV2_PLL_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT) /* * RESPONSE (RO) @@ -260,9 +260,9 @@ typedef struct { * 0: Divider is not stable * 1: Divider is stable for use */ -#define PLLCTLV2_DIV_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_DIV_RESPONSE_SHIFT (29U) -#define PLLCTLV2_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_RESPONSE_MASK) >> PLLCTLV2_DIV_RESPONSE_SHIFT) +#define PLLCTLV2_PLL_DIV_RESPONSE_MASK (0x20000000UL) +#define PLLCTLV2_PLL_DIV_RESPONSE_SHIFT (29U) +#define PLLCTLV2_PLL_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT) /* * ENABLE (RO) @@ -271,9 +271,9 @@ typedef struct { * 0: Divider is off * 1: Divider is on */ -#define PLLCTLV2_DIV_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_DIV_ENABLE_SHIFT (28U) -#define PLLCTLV2_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_ENABLE_MASK) >> PLLCTLV2_DIV_ENABLE_SHIFT) +#define PLLCTLV2_PLL_DIV_ENABLE_MASK (0x10000000UL) +#define PLLCTLV2_PLL_DIV_ENABLE_SHIFT (28U) +#define PLLCTLV2_PLL_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT) /* * DIV (RW) @@ -285,10 +285,10 @@ typedef struct { * . . . * 63: divide by 13.6 */ -#define PLLCTLV2_DIV_DIV_MASK (0x3FU) -#define PLLCTLV2_DIV_DIV_SHIFT (0U) -#define PLLCTLV2_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_DIV_DIV_SHIFT) & PLLCTLV2_DIV_DIV_MASK) -#define PLLCTLV2_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_DIV_MASK) >> PLLCTLV2_DIV_DIV_SHIFT) +#define PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU) +#define PLLCTLV2_PLL_DIV_DIV_SHIFT (0U) +#define PLLCTLV2_PLL_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK) +#define PLLCTLV2_PLL_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT) @@ -303,4 +303,4 @@ typedef struct { #define PLLCTLV2_PLL_PLL2 (2UL) -#endif /* HPM_PLLCTLV2_H */ \ No newline at end of file +#endif /* HPM_PLLCTLV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h index 055225a6db..be2007e514 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -93,4 +93,4 @@ typedef struct { #define PMON_MONITOR_CLOCK1 (3UL) -#endif /* HPM_PMON_H */ \ No newline at end of file +#endif /* HPM_PMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h index 249a9c544d..9f5b33eb8d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -262,4 +262,4 @@ typedef struct { -#endif /* HPM_PSEC_H */ \ No newline at end of file +#endif /* HPM_PSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h index 3fe0c72dd2..48f5be63d6 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -406,4 +406,4 @@ typedef struct { #define PTPC_PTPC_1 (1UL) -#endif /* HPM_PTPC_H */ \ No newline at end of file +#endif /* HPM_PTPC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h index 3790ae929a..5865f0cd95 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,9 +11,18 @@ typedef struct { __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ - __RW uint32_t STA; /* 0x4: Counter start register */ - __RW uint32_t RLD; /* 0x8: Counter reload register */ - __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ + union { + __RW uint32_t STA; /* 0x4: Counter start register */ + __RW uint32_t STA_HRPWM; /* 0x4: Counter start register */ + }; + union { + __RW uint32_t RLD; /* 0x8: Counter reload register */ + __RW uint32_t RLD_HRPWM; /* 0x8: Counter reload register */ + }; + union { + __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ + __RW uint32_t CMP_HRPWM[24]; /* 0xC - 0x68: Comparator register */ + }; __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ __RW uint32_t FRCMD; /* 0x78: Force output mode register */ __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ @@ -36,6 +45,9 @@ typedef struct { __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ + __R uint8_t RESERVED8[368]; /* 0x290 - 0x3FF: Reserved */ + __R uint32_t ANASTS[8]; /* 0x400 - 0x41C: analog status register */ + __W uint32_t HRPWM_CFG; /* 0x420: hrpwm config register */ } PWM_Type; @@ -43,7 +55,8 @@ typedef struct { /* * SHUNLK (RW) * - * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written. + * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, + * otherwise the shadow registers can not be written. */ #define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) #define PWM_UNLK_SHUNLK_SHIFT (0U) @@ -72,6 +85,16 @@ typedef struct { #define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) #define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) +/* Bitfield definition for register: STA_HRPWM */ +/* + * STA (RW) + * + */ +#define PWM_STA_HRPWM_STA_MASK (0xFFFFFF00UL) +#define PWM_STA_HRPWM_STA_SHIFT (8U) +#define PWM_STA_HRPWM_STA_SET(x) (((uint32_t)(x) << PWM_STA_HRPWM_STA_SHIFT) & PWM_STA_HRPWM_STA_MASK) +#define PWM_STA_HRPWM_STA_GET(x) (((uint32_t)(x) & PWM_STA_HRPWM_STA_MASK) >> PWM_STA_HRPWM_STA_SHIFT) + /* Bitfield definition for register: RLD */ /* * XRLD (RW) @@ -93,7 +116,27 @@ typedef struct { #define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) #define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) -/* Bitfield definition for register array: CMP */ +/* Bitfield definition for register: RLD_HRPWM */ +/* + * RLD (RW) + * + */ +#define PWM_RLD_HRPWM_RLD_MASK (0xFFFFFF00UL) +#define PWM_RLD_HRPWM_RLD_SHIFT (8U) +#define PWM_RLD_HRPWM_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_SHIFT) & PWM_RLD_HRPWM_RLD_MASK) +#define PWM_RLD_HRPWM_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_MASK) >> PWM_RLD_HRPWM_RLD_SHIFT) + +/* + * RLD_HR (RW) + * + * pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. + */ +#define PWM_RLD_HRPWM_RLD_HR_MASK (0xFFU) +#define PWM_RLD_HRPWM_RLD_HR_SHIFT (0U) +#define PWM_RLD_HRPWM_RLD_HR_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_HR_SHIFT) & PWM_RLD_HRPWM_RLD_HR_MASK) +#define PWM_RLD_HRPWM_RLD_HR_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_HR_MASK) >> PWM_RLD_HRPWM_RLD_HR_SHIFT) + +/* Bitfield definition for register: 0 */ /* * XCMP (RW) * @@ -107,7 +150,8 @@ typedef struct { /* * CMP (RW) * - * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, + * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. */ #define PWM_CMP_CMP_MASK (0xFFFFFF0UL) #define PWM_CMP_CMP_SHIFT (4U) @@ -134,11 +178,31 @@ typedef struct { #define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) #define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) +/* Bitfield definition for register: 0 */ +/* + * CMP (RW) + * + */ +#define PWM_CMP_HRPWM_CMP_MASK (0xFFFFFF00UL) +#define PWM_CMP_HRPWM_CMP_SHIFT (8U) +#define PWM_CMP_HRPWM_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_SHIFT) & PWM_CMP_HRPWM_CMP_MASK) +#define PWM_CMP_HRPWM_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_MASK) >> PWM_CMP_HRPWM_CMP_SHIFT) + +/* + * CMP_HR (RW) + * + * high resolution compare value + */ +#define PWM_CMP_HRPWM_CMP_HR_MASK (0xFFU) +#define PWM_CMP_HRPWM_CMP_HR_SHIFT (0U) +#define PWM_CMP_HRPWM_CMP_HR_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_HR_SHIFT) & PWM_CMP_HRPWM_CMP_HR_MASK) +#define PWM_CMP_HRPWM_CMP_HR_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_HR_MASK) >> PWM_CMP_HRPWM_CMP_HR_SHIFT) + /* Bitfield definition for register: FRCMD */ /* * FRCMD (RW) * - * 2bit for each PWM output channel (0~7); + * 2bit for each PWM output channel (0-7); * 00: force output 0 * 01: force output 1 * 10: output highz @@ -257,7 +321,8 @@ typedef struct { /* * HWSHDWEDG (RW) * - * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as shadow register hardware load event. + * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. + * This bit assign its which edge is used as compare shadow register hardware load event. * 1- Falling edge * 0- Rising edge */ @@ -279,7 +344,8 @@ typedef struct { /* * FAULTRECEDG (RW) * - * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. + * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. + * This bit assign its effective edge of fault recover trigger. * 1- Falling edge * 0- Rising edge */ @@ -354,7 +420,8 @@ typedef struct { /* * FAULTCLR (RW) * - * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. + * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. */ #define PWM_GCR_FAULTCLR_MASK (0x40U) #define PWM_GCR_FAULTCLR_SHIFT (6U) @@ -372,7 +439,27 @@ typedef struct { #define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) /* - * FRCTIME (RW) + * HR_PWM_EN (RW) + * + * set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. + */ +#define PWM_GCR_HR_PWM_EN_MASK (0x10U) +#define PWM_GCR_HR_PWM_EN_SHIFT (4U) +#define PWM_GCR_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWM_GCR_HR_PWM_EN_SHIFT) & PWM_GCR_HR_PWM_EN_MASK) +#define PWM_GCR_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWM_GCR_HR_PWM_EN_MASK) >> PWM_GCR_HR_PWM_EN_SHIFT) + +/* + * TIMERRESET (RW) + * + * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + */ +#define PWM_GCR_TIMERRESET_MASK (0x8U) +#define PWM_GCR_TIMERRESET_SHIFT (3U) +#define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) +#define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) + +/* + * FRCTIME (WO) * * This bit field select the force effective time * 00: force immediately @@ -396,6 +483,36 @@ typedef struct { #define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) /* Bitfield definition for register: SHCR */ +/* + * CNT_UPDATE_RELOAD (RW) + * + * set to update counter working register at reload point, clear to use cnt_update_time as old version. + */ +#define PWM_SHCR_CNT_UPDATE_RELOAD_MASK (0x8000U) +#define PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT (15U) +#define PWM_SHCR_CNT_UPDATE_RELOAD_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) +#define PWM_SHCR_CNT_UPDATE_RELOAD_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) >> PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) + +/* + * CNT_UPDATE_EDGE (RW) + * + * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers + */ +#define PWM_SHCR_CNT_UPDATE_EDGE_MASK (0x4000U) +#define PWM_SHCR_CNT_UPDATE_EDGE_SHIFT (14U) +#define PWM_SHCR_CNT_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) +#define PWM_SHCR_CNT_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) >> PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) + +/* + * FORCE_UPDATE_EDGE (RW) + * + * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers + */ +#define PWM_SHCR_FORCE_UPDATE_EDGE_MASK (0x2000U) +#define PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT (13U) +#define PWM_SHCR_FORCE_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) +#define PWM_SHCR_FORCE_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) >> PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) + /* * FRCSHDWSEL (RW) * @@ -422,7 +539,8 @@ typedef struct { * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register * 00: after software set shlk bit of shlk register * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. + * The comparator can be either output compare mode or input capture mode. * 11: after SHSYNCI assert */ #define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) @@ -500,6 +618,19 @@ typedef struct { #define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) /* Bitfield definition for register array: PWMCFG */ +/* + * HR_UPDATE_MODE (RW) + * + * 0: update the hr value for the first edge at reload point; + * 1: update the hr value for the first edge at the last edge; + * all others will be updated at previous edge + * for pair mode, only pwm_cfg 0/2/4/6 are used + */ +#define PWM_PWMCFG_HR_UPDATE_MODE_MASK (0x20000000UL) +#define PWM_PWMCFG_HR_UPDATE_MODE_SHIFT (29U) +#define PWM_PWMCFG_HR_UPDATE_MODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) +#define PWM_PWMCFG_HR_UPDATE_MODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) >> PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) + /* * OEN (RW) * @@ -518,7 +649,8 @@ typedef struct { * This bitfield select when the FRCMD shadow register will be loaded to its work register * 00: after software set shlk bit of shlk register * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. + * The comparator can be either output compare mode or input capture mode. * 11: after SHSYNCI assert */ #define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) @@ -545,7 +677,8 @@ typedef struct { * This bitfield select when to recover PWM output after fault condition removed. * 00: immediately * 01: after pwm timer counter reload time - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. + * The comparator can be either output compare mode or input capture mode. * 11: after software write faultclr bit in GCR register */ #define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) @@ -757,7 +890,8 @@ typedef struct { * This bitfield select when the comparator shadow register will be loaded to its work register * 00: after software set shlk bit of shlk register * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. + * The comparator can be either output compare mode or input capture mode. * 11: after SHSYNCI assert */ #define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) @@ -777,6 +911,31 @@ typedef struct { #define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) #define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) +/* Bitfield definition for register array: ANASTS */ +/* + * CALON (RO) + * + * calibration status. + * will be set by hardware after setting cal_start. + * cleared after calibration finished + */ +#define PWM_ANASTS_CALON_MASK (0x80000000UL) +#define PWM_ANASTS_CALON_SHIFT (31U) +#define PWM_ANASTS_CALON_GET(x) (((uint32_t)(x) & PWM_ANASTS_CALON_MASK) >> PWM_ANASTS_CALON_SHIFT) + +/* Bitfield definition for register: HRPWM_CFG */ +/* + * CAL_START (WO) + * + * calibration start. + * software setting this bit to start calibration process. + * each bit for one channel. + */ +#define PWM_HRPWM_CFG_CAL_START_MASK (0xFFU) +#define PWM_HRPWM_CFG_CAL_START_SHIFT (0U) +#define PWM_HRPWM_CFG_CAL_START_SET(x) (((uint32_t)(x) << PWM_HRPWM_CFG_CAL_START_SHIFT) & PWM_HRPWM_CFG_CAL_START_MASK) +#define PWM_HRPWM_CFG_CAL_START_GET(x) (((uint32_t)(x) & PWM_HRPWM_CFG_CAL_START_MASK) >> PWM_HRPWM_CFG_CAL_START_SHIFT) + /* CMP register group index macro definition */ @@ -805,6 +964,32 @@ typedef struct { #define PWM_CMP_22 (22UL) #define PWM_CMP_23 (23UL) +/* CMP_HRPWM register group index macro definition */ +#define PWM_CMP_HRPWM_0 (0UL) +#define PWM_CMP_HRPWM_1 (1UL) +#define PWM_CMP_HRPWM_2 (2UL) +#define PWM_CMP_HRPWM_3 (3UL) +#define PWM_CMP_HRPWM_4 (4UL) +#define PWM_CMP_HRPWM_5 (5UL) +#define PWM_CMP_HRPWM_6 (6UL) +#define PWM_CMP_HRPWM_7 (7UL) +#define PWM_CMP_HRPWM_8 (8UL) +#define PWM_CMP_HRPWM_9 (9UL) +#define PWM_CMP_HRPWM_10 (10UL) +#define PWM_CMP_HRPWM_11 (11UL) +#define PWM_CMP_HRPWM_12 (12UL) +#define PWM_CMP_HRPWM_13 (13UL) +#define PWM_CMP_HRPWM_14 (14UL) +#define PWM_CMP_HRPWM_15 (15UL) +#define PWM_CMP_HRPWM_16 (16UL) +#define PWM_CMP_HRPWM_17 (17UL) +#define PWM_CMP_HRPWM_18 (18UL) +#define PWM_CMP_HRPWM_19 (19UL) +#define PWM_CMP_HRPWM_20 (20UL) +#define PWM_CMP_HRPWM_21 (21UL) +#define PWM_CMP_HRPWM_22 (22UL) +#define PWM_CMP_HRPWM_23 (23UL) + /* CHCFG register group index macro definition */ #define PWM_CHCFG_0 (0UL) #define PWM_CHCFG_1 (1UL) @@ -919,5 +1104,15 @@ typedef struct { #define PWM_CMPCFG_22 (22UL) #define PWM_CMPCFG_23 (23UL) +/* ANASTS register group index macro definition */ +#define PWM_ANASTS_0 (0UL) +#define PWM_ANASTS_1 (1UL) +#define PWM_ANASTS_2 (2UL) +#define PWM_ANASTS_3 (3UL) +#define PWM_ANASTS_4 (4UL) +#define PWM_ANASTS_5 (5UL) +#define PWM_ANASTS_6 (6UL) +#define PWM_ANASTS_7 (7UL) -#endif /* HPM_PWM_H */ \ No newline at end of file + +#endif /* HPM_PWM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h index 64a3076195..f8d1956602 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -633,4 +633,4 @@ typedef struct { #define QEI_SPDHIS_SPDHIS3 (3UL) -#endif /* HPM_QEI_H */ \ No newline at end of file +#endif /* HPM_QEI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h index c58a7ecd9f..eb2914de30 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -276,4 +276,4 @@ typedef struct { #define RNG_R2SK_FO2S7 (7UL) -#endif /* HPM_RNG_H */ \ No newline at end of file +#endif /* HPM_RNG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h index e796e9c761..99cad8ef43 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -159,4 +159,4 @@ typedef struct { -#endif /* HPM_RTC_H */ \ No newline at end of file +#endif /* HPM_RTC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h new file mode 100644 index 0000000000..ac8b741984 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h @@ -0,0 +1,753 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDM_H +#define HPM_SDM_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: SDM control register */ + __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ + __R uint32_t STATUS; /* 0x8: Status Registers */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + struct { + __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ + __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ + __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ + __RW uint32_t SDST; /* 0x1C: Data Path Status */ + __R uint32_t SDATA; /* 0x20: Data */ + __R uint32_t SDFIFO; /* 0x24: FIFO Data */ + __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ + __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ + __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ + __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ + __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ + __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ + __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ + } CH[4]; +} SDM_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SFTRST (RW) + * + * software reset the module if asserted to be1’b1. + */ +#define SDM_CTRL_SFTRST_MASK (0x80000000UL) +#define SDM_CTRL_SFTRST_SHIFT (31U) +#define SDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDM_CTRL_SFTRST_SHIFT) & SDM_CTRL_SFTRST_MASK) +#define SDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDM_CTRL_SFTRST_MASK) >> SDM_CTRL_SFTRST_SHIFT) + +/* + * CHMD (RW) + * + * Channel Rcv mode + * Bits[2:0] for Ch0. + * Bits[5:3] for Ch1 + * Bits[8:6] for Ch2 + * Bits[11:9] for Ch3 + * 3'b000: Capture at posedge of MCLK + * 3'b001: Capture at both posedge and negedge of MCLK + * 3'b010: Manchestor Mode + * 3'b011: Capture at negedge of MCLK + * 3'b100: Capture at every other posedge of MCLK + * 3'b101: Capture at every other negedge of MCLK + * Others: Undefined + */ +#define SDM_CTRL_CHMD_MASK (0x3FFC000UL) +#define SDM_CTRL_CHMD_SHIFT (14U) +#define SDM_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDM_CTRL_CHMD_SHIFT) & SDM_CTRL_CHMD_MASK) +#define SDM_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDM_CTRL_CHMD_MASK) >> SDM_CTRL_CHMD_SHIFT) + +/* + * SYNC_MCLK (RW) + * + * Asserted to double sync the mclk input pin before its usage inside the module + */ +#define SDM_CTRL_SYNC_MCLK_MASK (0x3C00U) +#define SDM_CTRL_SYNC_MCLK_SHIFT (10U) +#define SDM_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MCLK_SHIFT) & SDM_CTRL_SYNC_MCLK_MASK) +#define SDM_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MCLK_MASK) >> SDM_CTRL_SYNC_MCLK_SHIFT) + +/* + * SYNC_MDAT (RW) + * + * Asserted to double sync the mdat input pin before its usage inside the module + */ +#define SDM_CTRL_SYNC_MDAT_MASK (0x3C0U) +#define SDM_CTRL_SYNC_MDAT_SHIFT (6U) +#define SDM_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MDAT_SHIFT) & SDM_CTRL_SYNC_MDAT_MASK) +#define SDM_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MDAT_MASK) >> SDM_CTRL_SYNC_MDAT_SHIFT) + +/* + * CH_EN (RW) + * + * Channel Enable + */ +#define SDM_CTRL_CH_EN_MASK (0x3CU) +#define SDM_CTRL_CH_EN_SHIFT (2U) +#define SDM_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDM_CTRL_CH_EN_SHIFT) & SDM_CTRL_CH_EN_MASK) +#define SDM_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDM_CTRL_CH_EN_MASK) >> SDM_CTRL_CH_EN_SHIFT) + +/* + * IE (RW) + * + * Interrupt Enable + */ +#define SDM_CTRL_IE_MASK (0x2U) +#define SDM_CTRL_IE_SHIFT (1U) +#define SDM_CTRL_IE_SET(x) (((uint32_t)(x) << SDM_CTRL_IE_SHIFT) & SDM_CTRL_IE_MASK) +#define SDM_CTRL_IE_GET(x) (((uint32_t)(x) & SDM_CTRL_IE_MASK) >> SDM_CTRL_IE_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * CH3DRY (RW) + * + * Ch3 Data Ready interrupt enable. + */ +#define SDM_INT_EN_CH3DRY_MASK (0x80U) +#define SDM_INT_EN_CH3DRY_SHIFT (7U) +#define SDM_INT_EN_CH3DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3DRY_SHIFT) & SDM_INT_EN_CH3DRY_MASK) +#define SDM_INT_EN_CH3DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3DRY_MASK) >> SDM_INT_EN_CH3DRY_SHIFT) + +/* + * CH2DRY (RW) + * + * Ch2 Data Ready interrupt enable + */ +#define SDM_INT_EN_CH2DRY_MASK (0x40U) +#define SDM_INT_EN_CH2DRY_SHIFT (6U) +#define SDM_INT_EN_CH2DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2DRY_SHIFT) & SDM_INT_EN_CH2DRY_MASK) +#define SDM_INT_EN_CH2DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2DRY_MASK) >> SDM_INT_EN_CH2DRY_SHIFT) + +/* + * CH1DRY (RW) + * + * Ch1 Data Ready interrupt enable + */ +#define SDM_INT_EN_CH1DRY_MASK (0x20U) +#define SDM_INT_EN_CH1DRY_SHIFT (5U) +#define SDM_INT_EN_CH1DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1DRY_SHIFT) & SDM_INT_EN_CH1DRY_MASK) +#define SDM_INT_EN_CH1DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1DRY_MASK) >> SDM_INT_EN_CH1DRY_SHIFT) + +/* + * CH0DRY (RW) + * + * Ch0 Data Ready interrupt enable + */ +#define SDM_INT_EN_CH0DRY_MASK (0x10U) +#define SDM_INT_EN_CH0DRY_SHIFT (4U) +#define SDM_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0DRY_SHIFT) & SDM_INT_EN_CH0DRY_MASK) +#define SDM_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0DRY_MASK) >> SDM_INT_EN_CH0DRY_SHIFT) + +/* + * CH3ERR (RW) + * + * Ch3 Error interrupt enable. + */ +#define SDM_INT_EN_CH3ERR_MASK (0x8U) +#define SDM_INT_EN_CH3ERR_SHIFT (3U) +#define SDM_INT_EN_CH3ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3ERR_SHIFT) & SDM_INT_EN_CH3ERR_MASK) +#define SDM_INT_EN_CH3ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3ERR_MASK) >> SDM_INT_EN_CH3ERR_SHIFT) + +/* + * CH2ERR (RW) + * + * Ch2 Error interrupt enable + */ +#define SDM_INT_EN_CH2ERR_MASK (0x4U) +#define SDM_INT_EN_CH2ERR_SHIFT (2U) +#define SDM_INT_EN_CH2ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2ERR_SHIFT) & SDM_INT_EN_CH2ERR_MASK) +#define SDM_INT_EN_CH2ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2ERR_MASK) >> SDM_INT_EN_CH2ERR_SHIFT) + +/* + * CH1ERR (RW) + * + * Ch1 Error interrupt enable + */ +#define SDM_INT_EN_CH1ERR_MASK (0x2U) +#define SDM_INT_EN_CH1ERR_SHIFT (1U) +#define SDM_INT_EN_CH1ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1ERR_SHIFT) & SDM_INT_EN_CH1ERR_MASK) +#define SDM_INT_EN_CH1ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1ERR_MASK) >> SDM_INT_EN_CH1ERR_SHIFT) + +/* + * CH0ERR (RW) + * + * Ch0 Error interrupt enable + */ +#define SDM_INT_EN_CH0ERR_MASK (0x1U) +#define SDM_INT_EN_CH0ERR_SHIFT (0U) +#define SDM_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0ERR_SHIFT) & SDM_INT_EN_CH0ERR_MASK) +#define SDM_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0ERR_MASK) >> SDM_INT_EN_CH0ERR_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * CH3DRY (RO) + * + * Ch3 Data Ready. + * De-assert this bit by reading the data (or data fifo) registers. + */ +#define SDM_STATUS_CH3DRY_MASK (0x80U) +#define SDM_STATUS_CH3DRY_SHIFT (7U) +#define SDM_STATUS_CH3DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3DRY_MASK) >> SDM_STATUS_CH3DRY_SHIFT) + +/* + * CH2DRY (RO) + * + * Ch2 Data Ready + */ +#define SDM_STATUS_CH2DRY_MASK (0x40U) +#define SDM_STATUS_CH2DRY_SHIFT (6U) +#define SDM_STATUS_CH2DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2DRY_MASK) >> SDM_STATUS_CH2DRY_SHIFT) + +/* + * CH1DRY (RO) + * + * Ch1 Data Ready + */ +#define SDM_STATUS_CH1DRY_MASK (0x20U) +#define SDM_STATUS_CH1DRY_SHIFT (5U) +#define SDM_STATUS_CH1DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1DRY_MASK) >> SDM_STATUS_CH1DRY_SHIFT) + +/* + * CH0DRY (RO) + * + * Ch0 Data Ready + */ +#define SDM_STATUS_CH0DRY_MASK (0x10U) +#define SDM_STATUS_CH0DRY_SHIFT (4U) +#define SDM_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0DRY_MASK) >> SDM_STATUS_CH0DRY_SHIFT) + +/* + * CH3ERR (RO) + * + * Ch3 Error. + * ORed together by channel related error signals and corresponding error interrupt enable signals. + * De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. + */ +#define SDM_STATUS_CH3ERR_MASK (0x8U) +#define SDM_STATUS_CH3ERR_SHIFT (3U) +#define SDM_STATUS_CH3ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3ERR_MASK) >> SDM_STATUS_CH3ERR_SHIFT) + +/* + * CH2ERR (RO) + * + * Ch2 Error + */ +#define SDM_STATUS_CH2ERR_MASK (0x4U) +#define SDM_STATUS_CH2ERR_SHIFT (2U) +#define SDM_STATUS_CH2ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2ERR_MASK) >> SDM_STATUS_CH2ERR_SHIFT) + +/* + * CH1ERR (RO) + * + * Ch1 Error + */ +#define SDM_STATUS_CH1ERR_MASK (0x2U) +#define SDM_STATUS_CH1ERR_SHIFT (1U) +#define SDM_STATUS_CH1ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1ERR_MASK) >> SDM_STATUS_CH1ERR_SHIFT) + +/* + * CH0ERR (RO) + * + * Ch0 Error + */ +#define SDM_STATUS_CH0ERR_MASK (0x1U) +#define SDM_STATUS_CH0ERR_SHIFT (0U) +#define SDM_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0ERR_MASK) >> SDM_STATUS_CH0ERR_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFOCTRL */ +/* + * THRSH (RW) + * + * FIFO threshold (0,..,16) (fillings > threshold, then gen int) + */ +#define SDM_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) +#define SDM_CH_SDFIFOCTRL_THRSH_SHIFT (4U) +#define SDM_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_THRSH_SHIFT) & SDM_CH_SDFIFOCTRL_THRSH_MASK) +#define SDM_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_THRSH_MASK) >> SDM_CH_SDFIFOCTRL_THRSH_SHIFT) + +/* + * D_RDY_INT_EN (RW) + * + * FIFO data ready interrupt enable + */ +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLP */ +/* + * MANCH_THR (RW) + * + * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + */ +#define SDM_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) +#define SDM_CH_SDCTRLP_MANCH_THR_SHIFT (25U) +#define SDM_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_MANCH_THR_SHIFT) & SDM_CH_SDCTRLP_MANCH_THR_MASK) +#define SDM_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_MANCH_THR_MASK) >> SDM_CH_SDCTRLP_MANCH_THR_SHIFT) + +/* + * WDOG_THR (RW) + * + * Watch dog threshold for channel failure of CLK halting + */ +#define SDM_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) +#define SDM_CH_SDCTRLP_WDOG_THR_SHIFT (17U) +#define SDM_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WDOG_THR_SHIFT) & SDM_CH_SDCTRLP_WDOG_THR_MASK) +#define SDM_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WDOG_THR_MASK) >> SDM_CH_SDCTRLP_WDOG_THR_SHIFT) + +/* + * AF_IE (RW) + * + * Acknowledge feedback interrupt enable + */ +#define SDM_CH_SDCTRLP_AF_IE_MASK (0x10000UL) +#define SDM_CH_SDCTRLP_AF_IE_SHIFT (16U) +#define SDM_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_AF_IE_SHIFT) & SDM_CH_SDCTRLP_AF_IE_MASK) +#define SDM_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_AF_IE_MASK) >> SDM_CH_SDCTRLP_AF_IE_SHIFT) + +/* + * DFFOVIE (RW) + * + * Ch Data FIFO overflow interrupt enable + */ +#define SDM_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) +#define SDM_CH_SDCTRLP_DFFOVIE_SHIFT (15U) +#define SDM_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DFFOVIE_SHIFT) & SDM_CH_SDCTRLP_DFFOVIE_MASK) +#define SDM_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DFFOVIE_MASK) >> SDM_CH_SDCTRLP_DFFOVIE_SHIFT) + +/* + * DSATIE (RW) + * + * Ch CIC Data Saturation Interrupt Enable + */ +#define SDM_CH_SDCTRLP_DSATIE_MASK (0x4000U) +#define SDM_CH_SDCTRLP_DSATIE_SHIFT (14U) +#define SDM_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DSATIE_SHIFT) & SDM_CH_SDCTRLP_DSATIE_MASK) +#define SDM_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DSATIE_MASK) >> SDM_CH_SDCTRLP_DSATIE_SHIFT) + +/* + * DRIE (RW) + * + * Ch Data Ready Interrupt Enable + */ +#define SDM_CH_SDCTRLP_DRIE_MASK (0x2000U) +#define SDM_CH_SDCTRLP_DRIE_SHIFT (13U) +#define SDM_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DRIE_SHIFT) & SDM_CH_SDCTRLP_DRIE_MASK) +#define SDM_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DRIE_MASK) >> SDM_CH_SDCTRLP_DRIE_SHIFT) + +/* + * SYNCSEL (RW) + * + * Select the PWM SYNC Source + */ +#define SDM_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) +#define SDM_CH_SDCTRLP_SYNCSEL_SHIFT (7U) +#define SDM_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_SYNCSEL_SHIFT) & SDM_CH_SDCTRLP_SYNCSEL_MASK) +#define SDM_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_SYNCSEL_MASK) >> SDM_CH_SDCTRLP_SYNCSEL_SHIFT) + +/* + * FFSYNCCLREN (RW) + * + * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + */ +#define SDM_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) +#define SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) +#define SDM_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) +#define SDM_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) + +/* + * WTSYNACLR (RW) + * + * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen + * 0: WTSYNFLG should be cleared manually by WTSYNMCLR + */ +#define SDM_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) +#define SDM_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) +#define SDM_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) +#define SDM_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) >> SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) + +/* + * WTSYNMCLR (RW) + * + * 1: Manually clear WTSYNFLG. Auto-clear. + */ +#define SDM_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) +#define SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) +#define SDM_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) +#define SDM_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) + +/* + * WTSYNCEN (RW) + * + * 1: Start to store data only after PWM SYNC event + * 0: Start to store data whenever enabled + */ +#define SDM_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) +#define SDM_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) +#define SDM_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) +#define SDM_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) >> SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) + +/* + * D32 (RW) + * + * 1:32 bit data + * 0:16 bit data + */ +#define SDM_CH_SDCTRLP_D32_MASK (0x4U) +#define SDM_CH_SDCTRLP_D32_SHIFT (2U) +#define SDM_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_D32_SHIFT) & SDM_CH_SDCTRLP_D32_MASK) +#define SDM_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_D32_MASK) >> SDM_CH_SDCTRLP_D32_SHIFT) + +/* + * DR_OPT (RW) + * + * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold + * 0: Use Data Reg Ready as data ready + */ +#define SDM_CH_SDCTRLP_DR_OPT_MASK (0x2U) +#define SDM_CH_SDCTRLP_DR_OPT_SHIFT (1U) +#define SDM_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DR_OPT_SHIFT) & SDM_CH_SDCTRLP_DR_OPT_MASK) +#define SDM_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DR_OPT_MASK) >> SDM_CH_SDCTRLP_DR_OPT_SHIFT) + +/* + * EN (RW) + * + * Data Path Enable + */ +#define SDM_CH_SDCTRLP_EN_MASK (0x1U) +#define SDM_CH_SDCTRLP_EN_SHIFT (0U) +#define SDM_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_EN_SHIFT) & SDM_CH_SDCTRLP_EN_MASK) +#define SDM_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_EN_MASK) >> SDM_CH_SDCTRLP_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLE */ +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDM_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) +#define SDM_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) +#define SDM_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) +#define SDM_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) >> SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) + +/* + * PWMSYNC (RW) + * + * Asserted to double sync the PWM trigger signal + */ +#define SDM_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) +#define SDM_CH_SDCTRLE_PWMSYNC_SHIFT (16U) +#define SDM_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_PWMSYNC_SHIFT) & SDM_CH_SDCTRLE_PWMSYNC_MASK) +#define SDM_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_PWMSYNC_MASK) >> SDM_CH_SDCTRLE_PWMSYNC_SHIFT) + +/* + * CIC_SCL (RW) + * + * CIC shift control + */ +#define SDM_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) +#define SDM_CH_SDCTRLE_CIC_SCL_SHIFT (11U) +#define SDM_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_SCL_SHIFT) & SDM_CH_SDCTRLE_CIC_SCL_MASK) +#define SDM_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_SCL_MASK) >> SDM_CH_SDCTRLE_CIC_SCL_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-256 + */ +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Don't store the first samples that are not accurate + * Zero: Store all samples + */ +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) + +/* Bitfield definition for register of struct array CH: SDST */ +/* + * PERIOD_MCLK (RO) + * + * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + */ +#define SDM_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) +#define SDM_CH_SDST_PERIOD_MCLK_SHIFT (23U) +#define SDM_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDM_CH_SDST_PERIOD_MCLK_MASK) >> SDM_CH_SDST_PERIOD_MCLK_SHIFT) + +/* + * FIFO_DR (W1C) + * + * FIFO data ready + */ +#define SDM_CH_SDST_FIFO_DR_MASK (0x200U) +#define SDM_CH_SDST_FIFO_DR_SHIFT (9U) +#define SDM_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_FIFO_DR_SHIFT) & SDM_CH_SDST_FIFO_DR_MASK) +#define SDM_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FIFO_DR_MASK) >> SDM_CH_SDST_FIFO_DR_SHIFT) + +/* + * AF (W1C) + * + * Achnowledge flag + */ +#define SDM_CH_SDST_AF_MASK (0x100U) +#define SDM_CH_SDST_AF_SHIFT (8U) +#define SDM_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDM_CH_SDST_AF_SHIFT) & SDM_CH_SDST_AF_MASK) +#define SDM_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDM_CH_SDST_AF_MASK) >> SDM_CH_SDST_AF_SHIFT) + +/* + * DOV_ERR (W1C) + * + * Data FIFO Overflow Error. Error flag. + */ +#define SDM_CH_SDST_DOV_ERR_MASK (0x80U) +#define SDM_CH_SDST_DOV_ERR_SHIFT (7U) +#define SDM_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DOV_ERR_SHIFT) & SDM_CH_SDST_DOV_ERR_MASK) +#define SDM_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DOV_ERR_MASK) >> SDM_CH_SDST_DOV_ERR_SHIFT) + +/* + * DSAT_ERR (W1C) + * + * CIC out Data saturation err. Error flag. + */ +#define SDM_CH_SDST_DSAT_ERR_MASK (0x40U) +#define SDM_CH_SDST_DSAT_ERR_SHIFT (6U) +#define SDM_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DSAT_ERR_SHIFT) & SDM_CH_SDST_DSAT_ERR_MASK) +#define SDM_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DSAT_ERR_MASK) >> SDM_CH_SDST_DSAT_ERR_SHIFT) + +/* + * WTSYNFLG (RO) + * + * Wait-for-sync event found + */ +#define SDM_CH_SDST_WTSYNFLG_MASK (0x20U) +#define SDM_CH_SDST_WTSYNFLG_SHIFT (5U) +#define SDM_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDM_CH_SDST_WTSYNFLG_MASK) >> SDM_CH_SDST_WTSYNFLG_SHIFT) + +/* + * FILL (RO) + * + * Data FIFO Fillings + */ +#define SDM_CH_SDST_FILL_MASK (0x1FU) +#define SDM_CH_SDST_FILL_SHIFT (0U) +#define SDM_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FILL_MASK) >> SDM_CH_SDST_FILL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDATA */ +/* + * VAL (RO) + * + * Data + */ +#define SDM_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) +#define SDM_CH_SDATA_VAL_SHIFT (0U) +#define SDM_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDATA_VAL_MASK) >> SDM_CH_SDATA_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFO */ +/* + * VAL (RO) + * + * FIFO Data + */ +#define SDM_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) +#define SDM_CH_SDFIFO_VAL_SHIFT (0U) +#define SDM_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFO_VAL_MASK) >> SDM_CH_SDFIFO_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCAMP */ +/* + * VAL (RO) + * + * instant Amplitude Results + */ +#define SDM_CH_SCAMP_VAL_MASK (0xFFFFU) +#define SDM_CH_SCAMP_VAL_SHIFT (0U) +#define SDM_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCAMP_VAL_MASK) >> SDM_CH_SCAMP_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTL */ +/* + * VAL (RW) + * + * Amplitude Threshold for High Limit + */ +#define SDM_CH_SCHTL_VAL_MASK (0xFFFFU) +#define SDM_CH_SCHTL_VAL_SHIFT (0U) +#define SDM_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTL_VAL_SHIFT) & SDM_CH_SCHTL_VAL_MASK) +#define SDM_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTL_VAL_MASK) >> SDM_CH_SCHTL_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTLZ */ +/* + * VAL (RW) + * + * Amplitude Threshold for zero crossing + */ +#define SDM_CH_SCHTLZ_VAL_MASK (0xFFFFU) +#define SDM_CH_SCHTLZ_VAL_SHIFT (0U) +#define SDM_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTLZ_VAL_SHIFT) & SDM_CH_SCHTLZ_VAL_MASK) +#define SDM_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTLZ_VAL_MASK) >> SDM_CH_SCHTLZ_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCLLT */ +/* + * VAL (RW) + * + * Amplitude Threshold for low limit + */ +#define SDM_CH_SCLLT_VAL_MASK (0xFFFFU) +#define SDM_CH_SCLLT_VAL_SHIFT (0U) +#define SDM_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCLLT_VAL_SHIFT) & SDM_CH_SCLLT_VAL_MASK) +#define SDM_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCLLT_VAL_MASK) >> SDM_CH_SCLLT_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCCTRL */ +/* + * HZ_EN (RW) + * + * Zero Crossing Enable + */ +#define SDM_CH_SCCTRL_HZ_EN_MASK (0x800000UL) +#define SDM_CH_SCCTRL_HZ_EN_SHIFT (23U) +#define SDM_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HZ_EN_SHIFT) & SDM_CH_SCCTRL_HZ_EN_MASK) +#define SDM_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HZ_EN_MASK) >> SDM_CH_SCCTRL_HZ_EN_SHIFT) + +/* + * MF_IE (RW) + * + * Module failure Interrupt enable + */ +#define SDM_CH_SCCTRL_MF_IE_MASK (0x400000UL) +#define SDM_CH_SCCTRL_MF_IE_SHIFT (22U) +#define SDM_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_MF_IE_SHIFT) & SDM_CH_SCCTRL_MF_IE_MASK) +#define SDM_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_MF_IE_MASK) >> SDM_CH_SCCTRL_MF_IE_SHIFT) + +/* + * HL_IE (RW) + * + * HLT Interrupt Enable + */ +#define SDM_CH_SCCTRL_HL_IE_MASK (0x200000UL) +#define SDM_CH_SCCTRL_HL_IE_SHIFT (21U) +#define SDM_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HL_IE_SHIFT) & SDM_CH_SCCTRL_HL_IE_MASK) +#define SDM_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HL_IE_MASK) >> SDM_CH_SCCTRL_HL_IE_SHIFT) + +/* + * LL_IE (RW) + * + * LLT interrupt Enable + */ +#define SDM_CH_SCCTRL_LL_IE_MASK (0x100000UL) +#define SDM_CH_SCCTRL_LL_IE_SHIFT (20U) +#define SDM_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_LL_IE_SHIFT) & SDM_CH_SCCTRL_LL_IE_MASK) +#define SDM_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_LL_IE_MASK) >> SDM_CH_SCCTRL_LL_IE_SHIFT) + +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDM_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) +#define SDM_CH_SCCTRL_SGD_ORDR_SHIFT (18U) +#define SDM_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_SGD_ORDR_SHIFT) & SDM_CH_SCCTRL_SGD_ORDR_MASK) +#define SDM_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_SGD_ORDR_MASK) >> SDM_CH_SCCTRL_SGD_ORDR_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-32 + */ +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Ignore the first samples that are not accurate + * Zero: Use all samples + */ +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) + +/* + * EN (RW) + * + * Amplitude Path Enable + */ +#define SDM_CH_SCCTRL_EN_MASK (0x1U) +#define SDM_CH_SCCTRL_EN_SHIFT (0U) +#define SDM_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_EN_SHIFT) & SDM_CH_SCCTRL_EN_MASK) +#define SDM_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_EN_MASK) >> SDM_CH_SCCTRL_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SCST */ +/* + * HZ (W1C) + * + * Amplitude rising above HZ event found. + */ +#define SDM_CH_SCST_HZ_MASK (0x8U) +#define SDM_CH_SCST_HZ_SHIFT (3U) +#define SDM_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDM_CH_SCST_HZ_SHIFT) & SDM_CH_SCST_HZ_MASK) +#define SDM_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDM_CH_SCST_HZ_MASK) >> SDM_CH_SCST_HZ_SHIFT) + +/* + * MF (W1C) + * + * power modulator Failure found. MCLK not found. Error flag. + */ +#define SDM_CH_SCST_MF_MASK (0x4U) +#define SDM_CH_SCST_MF_SHIFT (2U) +#define SDM_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDM_CH_SCST_MF_SHIFT) & SDM_CH_SCST_MF_MASK) +#define SDM_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDM_CH_SCST_MF_MASK) >> SDM_CH_SCST_MF_SHIFT) + +/* + * CMPH (W1C) + * + * HLT out of range. Error flag. + */ +#define SDM_CH_SCST_CMPH_MASK (0x2U) +#define SDM_CH_SCST_CMPH_SHIFT (1U) +#define SDM_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPH_SHIFT) & SDM_CH_SCST_CMPH_MASK) +#define SDM_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPH_MASK) >> SDM_CH_SCST_CMPH_SHIFT) + +/* + * CMPL (W1C) + * + * LLT out of range. Error flag. + */ +#define SDM_CH_SCST_CMPL_MASK (0x1U) +#define SDM_CH_SCST_CMPL_SHIFT (0U) +#define SDM_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPL_SHIFT) & SDM_CH_SCST_CMPL_MASK) +#define SDM_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPL_MASK) >> SDM_CH_SCST_CMPL_SHIFT) + + + +/* CH register group index macro definition */ +#define SDM_CH_0 (0UL) +#define SDM_CH_1 (1UL) +#define SDM_CH_2 (2UL) +#define SDM_CH_3 (3UL) + + +#endif /* HPM_SDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h index d2548d27e0..d81aba4fec 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -170,6 +170,7 @@ typedef struct { * AES algorithem selection. * 0x0 = AES 128; * 0x1 = AES 256; + * 0x8 = SM4； * Others, reserved. */ #define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) @@ -669,4 +670,4 @@ typedef struct { #define SDP_HASWRD_HASWRD7 (7UL) -#endif /* HPM_SDP_H */ \ No newline at end of file +#endif /* HPM_SDP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h index 2404466293..1f3bbcadcd 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -27,7 +27,7 @@ typedef struct { __R uint32_t CAPABILITIES2; /* 0x44: */ __R uint32_t CURR_CAPABILITIES1; /* 0x48: */ __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */ - __RW uint32_t FORCE_EVENT; /* 0x50: */ + __W uint32_t FORCE_EVENT; /* 0x50: */ __R uint32_t ADMA_ERR_STAT; /* 0x54: */ __RW uint32_t ADMA_SYS_ADDR; /* 0x58: */ __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */ @@ -319,7 +319,8 @@ typedef struct { * RESP_ERR_CHK_ENABLE (RW) * * Response Error Check Enable - * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. + * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. + * If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. * Note: * - Response error check must not be enabled for any response type other than R1 and R5. * - Response check must not be enabled for the tuning command. @@ -440,7 +441,7 @@ typedef struct { /* Bitfield definition for register array: RESP */ /* - * RESP01 (R) + * RESP01 (RO) * * Command Response * These bits reflect 39-8 bits of SD/eMMC Response Field. @@ -464,7 +465,7 @@ typedef struct { /* Bitfield definition for register: PSTATE */ /* - * SUB_CMD_STAT (R) + * SUB_CMD_STAT (RO) * * Sub Command Status * This bit is used to distinguish between a main command and a sub command status. @@ -477,7 +478,7 @@ typedef struct { #define SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT) /* - * CMD_ISSUE_ERR (R) + * CMD_ISSUE_ERR (RO) * * Command Not Issued by Error * This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. @@ -490,7 +491,7 @@ typedef struct { #define SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT) /* - * CMD_LINE_LVL (R) + * CMD_LINE_LVL (RO) * * Command-Line Signal Level * This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. @@ -500,7 +501,7 @@ typedef struct { #define SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT) /* - * DAT_3_0 (R) + * DAT_3_0 (RO) * * DAT[3:0] Line Signal Level * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. @@ -510,7 +511,7 @@ typedef struct { #define SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT) /* - * WR_PROTECT_SW_LVL (R) + * WR_PROTECT_SW_LVL (RO) * * Write Protect Switch Pin Level * This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. @@ -523,7 +524,7 @@ typedef struct { #define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT) /* - * CARD_DETECT_PIN_LEVEL (R) + * CARD_DETECT_PIN_LEVEL (RO) * * Card Detect Pin Level * This bit reflects the inverse synchronized value of the card_detect_n signal. @@ -536,7 +537,7 @@ typedef struct { #define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT) /* - * CARD_STABLE (R) + * CARD_STABLE (RO) * * Card Stable * This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. @@ -549,7 +550,7 @@ typedef struct { #define SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT) /* - * CARD_INSERTED (R) + * CARD_INSERTED (RO) * * Card Inserted * This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. @@ -562,7 +563,7 @@ typedef struct { #define SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT) /* - * BUF_RD_ENABLE (R) + * BUF_RD_ENABLE (RO) * * Buffer Read Enable * This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. @@ -575,7 +576,7 @@ typedef struct { #define SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT) /* - * BUF_WR_ENABLE (R) + * BUF_WR_ENABLE (RO) * * Buffer Write Enable * This bit is used for non-DMA transfers. This bit is set if space is available for writing data. @@ -588,7 +589,7 @@ typedef struct { #define SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT) /* - * RD_XFER_ACTIVE (R) + * RD_XFER_ACTIVE (RO) * * Read Transfer Active * This bit indicates whether a read transfer is active for SD/eMMC mode. @@ -601,7 +602,7 @@ typedef struct { #define SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT) /* - * WR_XFER_ACTIVE (R) + * WR_XFER_ACTIVE (RO) * * Write Transfer Active * This status indicates whether a write transfer is active for SD/eMMC mode. @@ -614,7 +615,7 @@ typedef struct { #define SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT) /* - * DAT_7_4 (R) + * DAT_7_4 (RO) * * DAT[7:4] Line Signal Level * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. @@ -624,7 +625,7 @@ typedef struct { #define SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT) /* - * RE_TUNE_REQ (R) + * RE_TUNE_REQ (RO) * * Re-Tuning Request * SDXC does not generate retuning request. The software must maintain the Retuning timer. @@ -634,7 +635,7 @@ typedef struct { #define SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT) /* - * DAT_LINE_ACTIVE (R) + * DAT_LINE_ACTIVE (RO) * * DAT Line Active ( * This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. @@ -650,7 +651,7 @@ typedef struct { #define SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT) /* - * DAT_INHIBIT (R) + * DAT_INHIBIT (RO) * * Command Inhibit (DAT) * This bit is generated if either DAT line active or Read transfer active is set to 1. @@ -664,7 +665,7 @@ typedef struct { #define SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT) /* - * CMD_INHIBIT (R) + * CMD_INHIBIT (RO) * * Command Inhibit (CMD) * This bit indicates the following : @@ -818,6 +819,23 @@ typedef struct { #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) #define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) +/* + * SD_BUS_PWR_VDD1 (RW) + * + * SD Bus Power for VDD1 + * This bit enables VDD1 power of the card. + * This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. + * Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. + * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_IN bit in the CLK_CTRL_R register. + * Values: + * 0x0 (OFF): Power off + * 0x1 (ON): Power on + */ +#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U) +#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U) +#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) +#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) + /* * EXT_DAT_XFER (RW) * @@ -1123,7 +1141,8 @@ typedef struct { * RESP_ERR (R/W1C) * * Response Error - * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. + * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. + * If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. * Values: * 0x0 (FALSE): No error * 0x1 (TRUE): Error @@ -1320,7 +1339,7 @@ typedef struct { #define SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) /* - * ERR_INTERRUPT (R) + * ERR_INTERRUPT (RO) * * Error Interrupt * If any of the bits in the Error Interrupt Status register are set, then this bit is set. @@ -1347,7 +1366,7 @@ typedef struct { #define SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT) /* - * FX_EVENT (R) + * FX_EVENT (RO) * * FX Event * This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. @@ -1360,7 +1379,7 @@ typedef struct { #define SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT) /* - * RE_TUNE_EVENT (R) + * RE_TUNE_EVENT (RO) * * Re-tuning Event * This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. @@ -1370,7 +1389,7 @@ typedef struct { #define SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT) /* - * CARD_INTERRUPT (R) + * CARD_INTERRUPT (RO) * * Card Interrupt * This bit reflects the synchronized value of: @@ -2317,7 +2336,7 @@ typedef struct { #define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) /* - * CMD_NOT_ISSUED_AUTO_CMD12 (R) + * CMD_NOT_ISSUED_AUTO_CMD12 (RO) * * Command Not Issued By Auto CMD12 Error * If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. @@ -2331,7 +2350,7 @@ typedef struct { #define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) /* - * AUTO_CMD_RESP_ERR (R) + * AUTO_CMD_RESP_ERR (RO) * * Auto CMD Response Error * This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. @@ -2345,7 +2364,7 @@ typedef struct { #define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT) /* - * AUTO_CMD_IDX_ERR (R) + * AUTO_CMD_IDX_ERR (RO) * * Auto CMD Index Error * This bit is set if the command index error occurs in response to a command. @@ -2358,7 +2377,7 @@ typedef struct { #define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT) /* - * AUTO_CMD_EBIT_ERR (R) + * AUTO_CMD_EBIT_ERR (RO) * * Auto CMD End Bit Error * This bit is set when detecting that the end bit of command response is 0. @@ -2371,7 +2390,7 @@ typedef struct { #define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT) /* - * AUTO_CMD_CRC_ERR (R) + * AUTO_CMD_CRC_ERR (RO) * * Auto CMD CRC Error * This bit is set when detecting a CRC error in the command response. @@ -2384,7 +2403,7 @@ typedef struct { #define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT) /* - * AUTO_CMD_TOUT_ERR (R) + * AUTO_CMD_TOUT_ERR (RO) * * Auto CMD Timeout Error * This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. @@ -2398,7 +2417,7 @@ typedef struct { #define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT) /* - * AUTO_CMD12_NOT_EXEC (R) + * AUTO_CMD12_NOT_EXEC (RO) * * Auto CMD12 Not Executed * If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. @@ -2415,7 +2434,7 @@ typedef struct { /* Bitfield definition for register: CAPABILITIES1 */ /* - * SLOT_TYPE_R (R) + * SLOT_TYPE_R (RO) * * Slot Type * These bits indicate usage of a slot by a specific Host System. @@ -2430,7 +2449,7 @@ typedef struct { #define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT) /* - * ASYNC_INT_SUPPORT (R) + * ASYNC_INT_SUPPORT (RO) * * Asynchronous Interrupt Support (SD Mode only) * Values: @@ -2442,7 +2461,7 @@ typedef struct { #define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT) /* - * VOLT_18 (R) + * VOLT_18 (RO) * * Voltage Support for 1.8V * Values: @@ -2454,7 +2473,7 @@ typedef struct { #define SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT) /* - * VOLT_30 (R) + * VOLT_30 (RO) * * Voltage Support for SD 3.0V or Embedded 1.2V * Values: @@ -2466,7 +2485,7 @@ typedef struct { #define SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT) /* - * VOLT_33 (R) + * VOLT_33 (RO) * * Voltage Support for 3.3V * Values: @@ -2478,7 +2497,7 @@ typedef struct { #define SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT) /* - * SUS_RES_SUPPORT (R) + * SUS_RES_SUPPORT (RO) * * Suspense/Resume Support * This bit indicates whether the Host Controller supports Suspend/Resume functionality. @@ -2492,7 +2511,7 @@ typedef struct { #define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT) /* - * SDMA_SUPPORT (R) + * SDMA_SUPPORT (RO) * * SDMA Support * This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. @@ -2505,7 +2524,7 @@ typedef struct { #define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT) /* - * HIGH_SPEED_SUPPORT (R) + * HIGH_SPEED_SUPPORT (RO) * * High Speed Support * This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. @@ -2518,7 +2537,7 @@ typedef struct { #define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT) /* - * ADMA2_SUPPORT (R) + * ADMA2_SUPPORT (RO) * * ADMA2 Support * This bit indicates whether the Host Controller is capable of using ADMA2. @@ -2531,7 +2550,7 @@ typedef struct { #define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT) /* - * EMBEDDED_8_BIT (R) + * EMBEDDED_8_BIT (RO) * * 8-bit Support for Embedded Device * This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. @@ -2544,7 +2563,7 @@ typedef struct { #define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT) /* - * MAX_BLK_LEN (R) + * MAX_BLK_LEN (RO) * * Maximum Block Length * This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. @@ -2560,7 +2579,7 @@ typedef struct { #define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT) /* - * BASE_CLK_FREQ (R) + * BASE_CLK_FREQ (RO) * * Base Clock Frequency for SD clock * These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. @@ -2586,7 +2605,7 @@ typedef struct { #define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT) /* - * TOUT_CLK_UNIT (R) + * TOUT_CLK_UNIT (RO) * * Timeout Clock Unit * This bit shows the unit of base clock frequency used to detect Data TImeout Error. @@ -2599,7 +2618,7 @@ typedef struct { #define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT) /* - * TOUT_CLK_FREQ (R) + * TOUT_CLK_FREQ (RO) * * Timeout Clock Frequency * This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. @@ -2616,7 +2635,7 @@ typedef struct { /* Bitfield definition for register: CAPABILITIES2 */ /* - * VDD2_18V_SUPPORT (R) + * VDD2_18V_SUPPORT (RO) * * 1.8V VDD2 Support * This bit indicates support of VDD2 for the Host System. @@ -2628,7 +2647,7 @@ typedef struct { #define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT) /* - * ADMA3_SUPPORT (R) + * ADMA3_SUPPORT (RO) * * ADMA3 Support * This bit indicates whether the Host Controller is capable of using ADMA3. @@ -2641,7 +2660,7 @@ typedef struct { #define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT) /* - * CLK_MUL (R) + * CLK_MUL (RO) * * Clock Multiplier * These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. @@ -2656,7 +2675,7 @@ typedef struct { #define SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT) /* - * RE_TUNING_MODES (R) + * RE_TUNING_MODES (RO) * * Re-Tuning Modes (UHS-I only) * These bits select the re-tuning method and limit the maximum data length. @@ -2671,7 +2690,7 @@ typedef struct { #define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT) /* - * USE_TUNING_SDR50 (R) + * USE_TUNING_SDR50 (RO) * * Use Tuning for SDR50 (UHS-I only) * Values: @@ -2683,7 +2702,7 @@ typedef struct { #define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT) /* - * RETUNE_CNT (R) + * RETUNE_CNT (RO) * * Timer Count for Re-Tuning (UHS-I only) * 0x0: Re-Tuning Timer disabled @@ -2702,7 +2721,7 @@ typedef struct { #define SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT) /* - * DRV_TYPED (R) + * DRV_TYPED (RO) * * Driver Type D Support (UHS-I only) * This bit indicates support of Driver Type D for 1.8 Signaling. @@ -2715,7 +2734,7 @@ typedef struct { #define SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT) /* - * DRV_TYPEC (R) + * DRV_TYPEC (RO) * * Driver Type C Support (UHS-I only) * This bit indicates support of Driver Type C for 1.8 Signaling. @@ -2728,7 +2747,7 @@ typedef struct { #define SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT) /* - * DRV_TYPEA (R) + * DRV_TYPEA (RO) * * Driver Type A Support (UHS-I only) * This bit indicates support of Driver Type A for 1.8 Signaling. @@ -2741,7 +2760,7 @@ typedef struct { #define SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT) /* - * UHS2_SUPPORT (R) + * UHS2_SUPPORT (RO) * * UHS-II Support (UHS-II only) * This bit indicates whether Host Controller supports UHS-II. @@ -2754,7 +2773,7 @@ typedef struct { #define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT) /* - * DDR50_SUPPORT (R) + * DDR50_SUPPORT (RO) * * DDR50 Support (UHS-I only) * Values: @@ -2766,7 +2785,7 @@ typedef struct { #define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT) /* - * SDR104_SUPPORT (R) + * SDR104_SUPPORT (RO) * * SDR104 Support (UHS-I only) * This bit mentions that SDR104 requires tuning. @@ -2779,7 +2798,7 @@ typedef struct { #define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT) /* - * SDR50_SUPPORT (R) + * SDR50_SUPPORT (RO) * * SDR50 Support (UHS-I only) * This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. @@ -2793,7 +2812,7 @@ typedef struct { /* Bitfield definition for register: CURR_CAPABILITIES1 */ /* - * MAX_CUR_18V (R) + * MAX_CUR_18V (RO) * * Maximum Current for 1.8V * This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. @@ -2809,7 +2828,7 @@ typedef struct { #define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT) /* - * MAX_CUR_30V (R) + * MAX_CUR_30V (RO) * * Maximum Current for 3.0V * This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. @@ -2825,7 +2844,7 @@ typedef struct { #define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT) /* - * MAX_CUR_33V (R) + * MAX_CUR_33V (RO) * * Maximum Current for 3.3V * This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. @@ -2842,7 +2861,7 @@ typedef struct { /* Bitfield definition for register: CURR_CAPABILITIES2 */ /* - * MAX_CUR_VDD2_18V (R) + * MAX_CUR_VDD2_18V (RO) * * Maximum Current for 1.8V VDD2 * This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. @@ -2859,7 +2878,7 @@ typedef struct { /* Bitfield definition for register: FORCE_EVENT */ /* - * FORCE_BOOT_ACK_ERR (W) + * FORCE_BOOT_ACK_ERR (WO) * * Force Event for Boot Ack error * Values: @@ -2872,7 +2891,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) /* - * FORCE_RESP_ERR (W) + * FORCE_RESP_ERR (WO) * * Force Event for Response Error (SD Mode only) * Values: @@ -2885,7 +2904,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) /* - * FORCE_TUNING_ERR (W) + * FORCE_TUNING_ERR (WO) * * Force Event for Tuning Error (UHS-I Mode only) * Values: @@ -2898,7 +2917,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) /* - * FORCE_ADMA_ERR (W) + * FORCE_ADMA_ERR (WO) * * Force Event for ADMA Error * Values: @@ -2911,7 +2930,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) /* - * FORCE_AUTO_CMD_ERR (W) + * FORCE_AUTO_CMD_ERR (WO) * * Force Event for Auto CMD Error (SD/eMMC Mode only) * Values: @@ -2924,7 +2943,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) /* - * FORCE_CUR_LMT_ERR (W) + * FORCE_CUR_LMT_ERR (WO) * * Force Event for Current Limit Error * Values: @@ -2937,7 +2956,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) /* - * FORCE_DATA_END_BIT_ERR (W) + * FORCE_DATA_END_BIT_ERR (WO) * * Force Event for Data End Bit Error (SD/eMMC Mode only) * Values: @@ -2950,7 +2969,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) /* - * FORCE_DATA_CRC_ERR (W) + * FORCE_DATA_CRC_ERR (WO) * * Force Event for Data CRC Error (SD/eMMC Mode only) * Values: @@ -2963,7 +2982,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) /* - * FORCE_DATA_TOUT_ERR (W) + * FORCE_DATA_TOUT_ERR (WO) * * Force Event for Data Timeout Error (SD/eMMC Mode only) * Values: @@ -2976,7 +2995,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) /* - * FORCE_CMD_IDX_ERR (W) + * FORCE_CMD_IDX_ERR (WO) * * Force Event for Command Index Error (SD/eMMC Mode only) * Values: @@ -2989,7 +3008,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) /* - * FORCE_CMD_END_BIT_ERR (W) + * FORCE_CMD_END_BIT_ERR (WO) * * Force Event for Command End Bit Error (SD/eMMC Mode only) * Values: @@ -3002,7 +3021,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) /* - * FORCE_CMD_CRC_ERR (W) + * FORCE_CMD_CRC_ERR (WO) * * Force Event for Command CRC Error (SD/eMMC Mode only) * Values: @@ -3015,7 +3034,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) /* - * FORCE_CMD_TOUT_ERR (W) + * FORCE_CMD_TOUT_ERR (WO) * * Force Event for Command Timeout Error (SD/eMMC Mode only) * Values: @@ -3028,7 +3047,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) /* - * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (W) + * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (WO) * * Force Event for Command Not Issued By Auto CMD12 Error * Values: @@ -3041,7 +3060,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) /* - * FORCE_AUTO_CMD_RESP_ERR (W) + * FORCE_AUTO_CMD_RESP_ERR (WO) * * Force Event for Auto CMD Response Error * Values: @@ -3054,7 +3073,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) /* - * FORCE_AUTO_CMD_IDX_ERR (W) + * FORCE_AUTO_CMD_IDX_ERR (WO) * * Force Event for Auto CMD Index Error * Values: @@ -3067,7 +3086,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) /* - * FORCE_AUTO_CMD_EBIT_ERR (W) + * FORCE_AUTO_CMD_EBIT_ERR (WO) * * Force Event for Auto CMD End Bit Error * Values: @@ -3080,7 +3099,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) /* - * FORCE_AUTO_CMD_CRC_ERR (W) + * FORCE_AUTO_CMD_CRC_ERR (WO) * * Force Event for Auto CMD CRC Error * Values: @@ -3093,7 +3112,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) /* - * FORCE_AUTO_CMD_TOUT_ERR (W) + * FORCE_AUTO_CMD_TOUT_ERR (WO) * * Force Event for Auto CMD Timeout Error * Values: @@ -3106,7 +3125,7 @@ typedef struct { #define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) /* - * FORCE_AUTO_CMD12_NOT_EXEC (W) + * FORCE_AUTO_CMD12_NOT_EXEC (WO) * * Force Event for Auto CMD12 Not Executed * Values: @@ -3120,7 +3139,7 @@ typedef struct { /* Bitfield definition for register: ADMA_ERR_STAT */ /* - * ADMA_LEN_ERR (R) + * ADMA_LEN_ERR (RO) * * ADMA Length Mismatch Error States * This error occurs in the following instances: @@ -3135,7 +3154,7 @@ typedef struct { #define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT) /* - * ADMA_ERR_STATES (R) + * ADMA_ERR_STATES (RO) * * ADMA Error States * These bits indicate the state of ADMA when an error occurs during ADMA data transfer. @@ -3166,7 +3185,7 @@ typedef struct { /* Bitfield definition for register array: PRESET */ /* - * CLK_GEN_SEL_VAL (R) + * CLK_GEN_SEL_VAL (RO) * * Clock Generator Select Value * This bit is effective when the Host Controller supports a programmable clock generator. @@ -3179,7 +3198,7 @@ typedef struct { #define SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT) /* - * FREQ_SEL_VAL (R) + * FREQ_SEL_VAL (RO) * * SDCLK/RCLK Frequency Select Value * 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. @@ -3204,7 +3223,7 @@ typedef struct { /* Bitfield definition for register: P_EMBEDDED_CNTRL */ /* - * REG_OFFSET_ADDR (R) + * REG_OFFSET_ADDR (RO) * * Offset Address of Embedded Control register. */ @@ -3214,7 +3233,7 @@ typedef struct { /* Bitfield definition for register: P_VENDOR_SPECIFIC_AREA */ /* - * REG_OFFSET_ADDR (R) + * REG_OFFSET_ADDR (RO) * * Base offset Address for Vendor-Specific registers. */ @@ -3224,7 +3243,7 @@ typedef struct { /* Bitfield definition for register: P_VENDOR2_SPECIFIC_AREA */ /* - * REG_OFFSET_ADDR (R) + * REG_OFFSET_ADDR (RO) * * Base offset Address for Command Queuing registers. */ @@ -3234,7 +3253,7 @@ typedef struct { /* Bitfield definition for register: SLOT_INTR_STATUS */ /* - * INTR_SLOT (R) + * INTR_SLOT (RO) * * Interrupt signal for each Slot * These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. @@ -3254,7 +3273,7 @@ typedef struct { /* Bitfield definition for register: CQVER */ /* - * EMMC_VER_MAHOR (R) + * EMMC_VER_MAHOR (RO) * * This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. */ @@ -3263,7 +3282,7 @@ typedef struct { #define SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT) /* - * EMMC_VER_MINOR (R) + * EMMC_VER_MINOR (RO) * * This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. */ @@ -3272,7 +3291,7 @@ typedef struct { #define SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT) /* - * EMMC_VER_SUFFIX (R) + * EMMC_VER_SUFFIX (RO) * * This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. */ @@ -3282,7 +3301,7 @@ typedef struct { /* Bitfield definition for register: CQCAP */ /* - * CRYPTO_SUPPORT (R) + * CRYPTO_SUPPORT (RO) * * Crypto Support * This bit indicates whether the Host Controller supports cryptographic operations. @@ -3295,7 +3314,7 @@ typedef struct { #define SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT) /* - * ITCFMUL (R) + * ITCFMUL (RO) * * Internal Timer Clock Frequency Multiplier (ITCFMUL) * This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS @@ -3312,7 +3331,7 @@ typedef struct { #define SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT) /* - * ITCFVAL (R) + * ITCFVAL (RO) * * Internal Timer Clock Frequency Value (ITCFVAL) * This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. @@ -3575,7 +3594,7 @@ typedef struct { #define SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT) /* - * INTC_STAT (R) + * INTC_STAT (RO) * * Interrupt Coalescing Status Bit * This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt @@ -3589,7 +3608,7 @@ typedef struct { #define SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT) /* - * INTC_RST (W) + * INTC_RST (WO) * * Counter and Timer Reset * When host driver writes 1, the interrupt coalescing timer and counter are reset. @@ -3603,7 +3622,7 @@ typedef struct { #define SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT) /* - * INTC_TH_WEN (W) + * INTC_TH_WEN (WO) * * Interrupt Coalescing Counter Threshold Write Enable * When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. @@ -3617,7 +3636,7 @@ typedef struct { #define SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT) /* - * INTC_TH (W) + * INTC_TH (WO) * * Interrupt Coalescing Counter Threshold filed * Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. @@ -3637,7 +3656,7 @@ typedef struct { #define SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT) /* - * TOUT_VAL_WEN (W) + * TOUT_VAL_WEN (WO) * * When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. * Values: @@ -3822,7 +3841,7 @@ typedef struct { /* Bitfield definition for register: CQCRDCT */ /* - * DCMD_RESP (R) + * DCMD_RESP (RO) * * This register contains the response of the command generated by the last direct command (DCMD) task that was sent. * Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. @@ -3849,7 +3868,7 @@ typedef struct { /* Bitfield definition for register: CQTERRI */ /* - * TRANS_ERR_TASKID (R) + * TRANS_ERR_TASKID (RO) * * This field captures the ID of the task that was executed and whose data transfer has errors. */ @@ -3858,7 +3877,7 @@ typedef struct { #define SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT) /* - * TRANS_ERR_CMD_INDX (R) + * TRANS_ERR_CMD_INDX (RO) * * This field captures the index of the command that was executed and whose data transfer has errors. */ @@ -3867,7 +3886,7 @@ typedef struct { #define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT) /* - * RESP_ERR_FIELDS_VALID (R) + * RESP_ERR_FIELDS_VALID (RO) * * This bit is updated when an error is detected while a command transaction was in progress. * Values: @@ -3879,7 +3898,7 @@ typedef struct { #define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT) /* - * RESP_ERR_TASKID (R) + * RESP_ERR_TASKID (RO) * * This field captures the ID of the task which was executed on the command line when the error occurred. */ @@ -3888,7 +3907,7 @@ typedef struct { #define SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT) /* - * RESP_ERR_CMD_INDX (R) + * RESP_ERR_CMD_INDX (RO) * * This field captures the index of the command that was executed on the command line when the error occurred */ @@ -3898,7 +3917,7 @@ typedef struct { /* Bitfield definition for register: CQCRI */ /* - * CMD_RESP_INDX (R) + * CMD_RESP_INDX (RO) * * Last Command Response index * This field stores the index of the last received command response. Controller updates the value every time a command response is received @@ -3909,7 +3928,7 @@ typedef struct { /* Bitfield definition for register: CQCRA */ /* - * CMD_RESP_ARG (R) + * CMD_RESP_ARG (RO) * * Last Command Response argument * This field stores the argument of the last received command response. Controller updates the value every time a command response is received. @@ -3920,7 +3939,7 @@ typedef struct { /* Bitfield definition for register: MSHC_VER_ID */ /* - * VER_ID (R) + * VER_ID (RO) * */ #define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL) @@ -3929,7 +3948,7 @@ typedef struct { /* Bitfield definition for register: MSHC_VER_TYPE */ /* - * VER_TYPE (R) + * VER_TYPE (RO) * */ #define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL) @@ -4005,7 +4024,7 @@ typedef struct { #define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) /* - * VALIDATE_BOOT (W) + * VALIDATE_BOOT (WO) * * Validate Mandatory Boot Enable bit * This bit is used to validate the MAN_BOOT_EN bit. @@ -4288,7 +4307,7 @@ typedef struct { /* Bitfield definition for register: AUTO_TUNING_STAT */ /* - * L_EDGE_PH_CODE (R) + * L_EDGE_PH_CODE (RO) * * Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. */ @@ -4297,7 +4316,7 @@ typedef struct { #define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT) /* - * R_EDGE_PH_CODE (R) + * R_EDGE_PH_CODE (RO) * * Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. */ @@ -4316,18 +4335,11 @@ typedef struct { #define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) /* Bitfield definition for register: MISC_CTRL0 */ -/* - * IRQ_EN (RW) - * - */ -#define SDXC_MISC_CTRL0_IRQ_EN_MASK (0xC0000000UL) -#define SDXC_MISC_CTRL0_IRQ_EN_SHIFT (30U) -#define SDXC_MISC_CTRL0_IRQ_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_IRQ_EN_SHIFT) & SDXC_MISC_CTRL0_IRQ_EN_MASK) -#define SDXC_MISC_CTRL0_IRQ_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_IRQ_EN_MASK) >> SDXC_MISC_CTRL0_IRQ_EN_SHIFT) - /* * CARDCLK_INV_EN (RW) * + * set to invert card_clk, for slow speed card to meet 5ns setup timing. + * May cause glitch on clock, should be set before enable clk(in core cfg) */ #define SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK (0x10000000UL) #define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT (28U) @@ -4337,24 +4349,19 @@ typedef struct { /* * PAD_CLK_SEL_B (RW) * + * set to use internal clock directly, may have timing issue; + * clr to use clock loopback from pad. */ #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK (0x20000UL) #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT (17U) #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) #define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) >> SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) -/* - * CARDCLK_EN_SW (RW) - * - */ -#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_MASK (0x1000U) -#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_SHIFT (12U) -#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_EN_SW_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_EN_SW_MASK) -#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_EN_SW_MASK) >> SDXC_MISC_CTRL0_CARDCLK_EN_SW_SHIFT) - /* * FREQ_SEL_SW_EN (RW) * + * set to use FREQ_SEL_SW as card clock divider; + * clear to use core logic as clock divider. */ #define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK (0x800U) #define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT (11U) @@ -4364,6 +4371,8 @@ typedef struct { /* * TMCLK_EN (RW) * + * set to force enable tmclk; + * clear to use core signal intclk_en to control it */ #define SDXC_MISC_CTRL0_TMCLK_EN_MASK (0x400U) #define SDXC_MISC_CTRL0_TMCLK_EN_SHIFT (10U) @@ -4373,6 +4382,7 @@ typedef struct { /* * FREQ_SEL_SW (RW) * + * software card clock divider, it will be used only when FREQ_SEL_SW_EN is set */ #define SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK (0x3FFU) #define SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT (0U) @@ -4383,6 +4393,9 @@ typedef struct { /* * CARD_ACTIVE (RW) * + * SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). + * When counter finished, this bit will be cleared by hardware. + * Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) */ #define SDXC_MISC_CTRL1_CARD_ACTIVE_MASK (0x80000000UL) #define SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT (31U) @@ -4392,12 +4405,34 @@ typedef struct { /* * CARD_ACTIVE_PERIOD_SEL (RW) * + * card clock delay config. + * 00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle */ #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK (0x30000000UL) #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT (28U) #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) #define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) +/* + * CARDCLK_DLYSEL (RW) + * + * for card clock DLL, default 0 + */ +#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK (0x3F00000UL) +#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT (20U) +#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) +#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) >> SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT) + +/* + * STROBE_DLYSEL (RW) + * + * for strobe DLL, default 7taps(1ns) + */ +#define SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK (0x3F000UL) +#define SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT (12U) +#define SDXC_MISC_CTRL1_STROBE_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) +#define SDXC_MISC_CTRL1_STROBE_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) >> SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT) + /* RESP register group index macro definition */ @@ -4418,4 +4453,4 @@ typedef struct { #define SDXC_PRESET_UHS2 (10UL) -#endif /* HPM_SDXC_H */ \ No newline at end of file +#endif /* HPM_SDXC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h index 444df301a0..5a386bec92 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -246,13 +246,13 @@ typedef struct { * LIFECYCLE (RO) * * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, + * bit7: lifecycle_debate, + * bit6: lifecycle_scribe, + * bit5: lifecycle_no_ret, + * bit4: lifecycle_return, + * bit3: lifecycle_secure, + * bit2: lifecycle_nonsec, + * bit1: lifecycle_create, * bit0: lifecycle_unknow */ #define SEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) @@ -262,4 +262,4 @@ typedef struct { -#endif /* HPM_SEC_H */ \ No newline at end of file +#endif /* HPM_SEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h index 182b415f3e..392c0b8a0b 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,8 +12,7 @@ typedef struct { __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ + __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ __RW uint32_t CMD; /* 0x24: Command Register */ __RW uint32_t ADDR; /* 0x28: Address Register */ @@ -129,193 +128,6 @@ typedef struct { #define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) #define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) -/* Bitfield definition for register: DIRECTIO */ -/* - * DIRECTIOEN (RW) - * - * Enable Direct IO - * 0x0: Disable - * 0x1: Enable - */ -#define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) -#define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) -#define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) -#define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) - -/* - * HOLD_OE (RW) - * - * Output enable for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) -#define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) -#define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) -#define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) - -/* - * WP_OE (RW) - * - * Output enable for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) -#define SPI_DIRECTIO_WP_OE_SHIFT (20U) -#define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) -#define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) - -/* - * MISO_OE (RW) - * - * Output enable fo the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) -#define SPI_DIRECTIO_MISO_OE_SHIFT (19U) -#define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) -#define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) - -/* - * MOSI_OE (RW) - * - * Output enable for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) -#define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) -#define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) -#define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) - -/* - * SCLK_OE (RW) - * - * Output enable for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) -#define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) -#define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) -#define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) - -/* - * CS_OE (RW) - * - * Output enable for SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) -#define SPI_DIRECTIO_CS_OE_SHIFT (16U) -#define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) -#define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) - -/* - * HOLD_O (RW) - * - * Output value for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) -#define SPI_DIRECTIO_HOLD_O_SHIFT (13U) -#define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) -#define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) - -/* - * WP_O (RW) - * - * Output value for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_O_MASK (0x1000U) -#define SPI_DIRECTIO_WP_O_SHIFT (12U) -#define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) -#define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) - -/* - * MISO_O (RW) - * - * Output value for the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_O_MASK (0x800U) -#define SPI_DIRECTIO_MISO_O_SHIFT (11U) -#define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) -#define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) - -/* - * MOSI_O (RW) - * - * Output value for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_O_MASK (0x400U) -#define SPI_DIRECTIO_MOSI_O_SHIFT (10U) -#define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) -#define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) - -/* - * SCLK_O (RW) - * - * Output value for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_O_MASK (0x200U) -#define SPI_DIRECTIO_SCLK_O_SHIFT (9U) -#define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) -#define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) - -/* - * CS_O (RW) - * - * Output value for the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_O_MASK (0x100U) -#define SPI_DIRECTIO_CS_O_SHIFT (8U) -#define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) -#define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) - -/* - * HOLD_I (RO) - * - * Status of the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_I_MASK (0x20U) -#define SPI_DIRECTIO_HOLD_I_SHIFT (5U) -#define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) - -/* - * WP_I (RO) - * - * Status of the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_I_MASK (0x10U) -#define SPI_DIRECTIO_WP_I_SHIFT (4U) -#define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) - -/* - * MISO_I (RO) - * - * Status of the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_I_MASK (0x8U) -#define SPI_DIRECTIO_MISO_I_SHIFT (3U) -#define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) - -/* - * MOSI_I (RO) - * - * Status of the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_I_MASK (0x4U) -#define SPI_DIRECTIO_MOSI_I_SHIFT (2U) -#define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) - -/* - * SCLK_I (RO) - * - * Status of the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_I_MASK (0x2U) -#define SPI_DIRECTIO_SCLK_I_SHIFT (1U) -#define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) - -/* - * CS_I (RO) - * - * Status of the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_I_MASK (0x1U) -#define SPI_DIRECTIO_CS_I_SHIFT (0U) -#define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) - /* Bitfield definition for register: TRANSCTRL */ /* * SLVDATAONLY (RW) @@ -847,12 +659,13 @@ typedef struct { /* Bitfield definition for register: SLVST */ /* - * UNDERRUN (R1C) + * UNDERRUN (W1C) * * Data underrun occurs in the last transaction */ #define SPI_SLVST_UNDERRUN_MASK (0x40000UL) #define SPI_SLVST_UNDERRUN_SHIFT (18U) +#define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) #define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) /* @@ -915,15 +728,6 @@ typedef struct { #define SPI_CONFIG_SLAVE_SHIFT (14U) #define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) -/* - * DIRECTIO (RO) - * - * Support for Direct SPI IO - */ -#define SPI_CONFIG_DIRECTIO_MASK (0x800U) -#define SPI_CONFIG_DIRECTIO_SHIFT (11U) -#define SPI_CONFIG_DIRECTIO_GET(x) (((uint32_t)(x) & SPI_CONFIG_DIRECTIO_MASK) >> SPI_CONFIG_DIRECTIO_SHIFT) - /* * QUADSPI (RO) * diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h index 08eef5ce87..936d2bda0a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,14 +12,86 @@ typedef struct { __RW uint32_t GCR; /* 0x0: Global control register */ __RW uint32_t RLD; /* 0x4: Counter reload register */ - __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ + __RW uint32_t SYNT_NEW; /* 0x8: sync timer new value register */ __R uint32_t CNT; /* 0xC: Counter */ - __R uint8_t RESERVED1[16]; /* 0x10 - 0x1F: Reserved */ + __R uint32_t SYNT_SAVE; /* 0x10: sync timer trig save value */ + __R uint32_t SYNT_READ; /* 0x14: sync timer read value */ + __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */ __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ } SYNT_Type; /* Bitfield definition for register: GCR */ +/* + * SYNC_TIMER_INC (WO) + * + * set to increase the sync timer with new_value, auto clr + */ +#define SYNT_GCR_SYNC_TIMER_INC_MASK (0x80000000UL) +#define SYNT_GCR_SYNC_TIMER_INC_SHIFT (31U) +#define SYNT_GCR_SYNC_TIMER_INC_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_INC_SHIFT) & SYNT_GCR_SYNC_TIMER_INC_MASK) +#define SYNT_GCR_SYNC_TIMER_INC_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_INC_MASK) >> SYNT_GCR_SYNC_TIMER_INC_SHIFT) + +/* + * SYNC_TIMER_DEC (WO) + * + * set to decrease the sync timer with new_value, auto clr + */ +#define SYNT_GCR_SYNC_TIMER_DEC_MASK (0x40000000UL) +#define SYNT_GCR_SYNC_TIMER_DEC_SHIFT (30U) +#define SYNT_GCR_SYNC_TIMER_DEC_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_DEC_SHIFT) & SYNT_GCR_SYNC_TIMER_DEC_MASK) +#define SYNT_GCR_SYNC_TIMER_DEC_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_DEC_MASK) >> SYNT_GCR_SYNC_TIMER_DEC_SHIFT) + +/* + * SYNC_TIMER_NEW (WO) + * + * set the sync timer to new_value, auto clr + */ +#define SYNT_GCR_SYNC_TIMER_NEW_MASK (0x20000000UL) +#define SYNT_GCR_SYNC_TIMER_NEW_SHIFT (29U) +#define SYNT_GCR_SYNC_TIMER_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_NEW_SHIFT) & SYNT_GCR_SYNC_TIMER_NEW_MASK) +#define SYNT_GCR_SYNC_TIMER_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_NEW_MASK) >> SYNT_GCR_SYNC_TIMER_NEW_SHIFT) + +/* + * SYNC_TIMER_RESET (WO) + * + * reset sync timer to 0, auto clr + */ +#define SYNT_GCR_SYNC_TIMER_RESET_MASK (0x10000000UL) +#define SYNT_GCR_SYNC_TIMER_RESET_SHIFT (28U) +#define SYNT_GCR_SYNC_TIMER_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_RESET_SHIFT) & SYNT_GCR_SYNC_TIMER_RESET_MASK) +#define SYNT_GCR_SYNC_TIMER_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_RESET_MASK) >> SYNT_GCR_SYNC_TIMER_RESET_SHIFT) + +/* + * SYNC_TIMER_STOPEN (RW) + * + * set to enable cpu_debug_mode to stop the sync timer + */ +#define SYNT_GCR_SYNC_TIMER_STOPEN_MASK (0x20U) +#define SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT (5U) +#define SYNT_GCR_SYNC_TIMER_STOPEN_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT) & SYNT_GCR_SYNC_TIMER_STOPEN_MASK) +#define SYNT_GCR_SYNC_TIMER_STOPEN_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_STOPEN_MASK) >> SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT) + +/* + * SYNC_TIMER_ENABLE (RW) + * + * set to enable the sync timer, clr to stop + */ +#define SYNT_GCR_SYNC_TIMER_ENABLE_MASK (0x10U) +#define SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT (4U) +#define SYNT_GCR_SYNC_TIMER_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT) & SYNT_GCR_SYNC_TIMER_ENABLE_MASK) +#define SYNT_GCR_SYNC_TIMER_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_ENABLE_MASK) >> SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT) + +/* + * STOPEN (RW) + * + * set to enable cpu_debug_mode to stop the counter + */ +#define SYNT_GCR_STOPEN_MASK (0x4U) +#define SYNT_GCR_STOPEN_SHIFT (2U) +#define SYNT_GCR_STOPEN_SET(x) (((uint32_t)(x) << SYNT_GCR_STOPEN_SHIFT) & SYNT_GCR_STOPEN_MASK) +#define SYNT_GCR_STOPEN_GET(x) (((uint32_t)(x) & SYNT_GCR_STOPEN_MASK) >> SYNT_GCR_STOPEN_SHIFT) + /* * CRST (RW) * @@ -51,6 +123,17 @@ typedef struct { #define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) #define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) +/* Bitfield definition for register: SYNT_NEW */ +/* + * NEW_VALUE (RW) + * + * new value for sync timer, can be used as update/inc/dec + */ +#define SYNT_SYNT_NEW_NEW_VALUE_MASK (0xFFFFFFFFUL) +#define SYNT_SYNT_NEW_NEW_VALUE_SHIFT (0U) +#define SYNT_SYNT_NEW_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_SYNT_NEW_NEW_VALUE_SHIFT) & SYNT_SYNT_NEW_NEW_VALUE_MASK) +#define SYNT_SYNT_NEW_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_SYNT_NEW_NEW_VALUE_MASK) >> SYNT_SYNT_NEW_NEW_VALUE_SHIFT) + /* Bitfield definition for register: CNT */ /* * CNT (RO) @@ -61,6 +144,26 @@ typedef struct { #define SYNT_CNT_CNT_SHIFT (0U) #define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) +/* Bitfield definition for register: SYNT_SAVE */ +/* + * TIME_SAVE (RO) + * + * use the trigger to save sync timer here + */ +#define SYNT_SYNT_SAVE_TIME_SAVE_MASK (0xFFFFFFFFUL) +#define SYNT_SYNT_SAVE_TIME_SAVE_SHIFT (0U) +#define SYNT_SYNT_SAVE_TIME_SAVE_GET(x) (((uint32_t)(x) & SYNT_SYNT_SAVE_TIME_SAVE_MASK) >> SYNT_SYNT_SAVE_TIME_SAVE_SHIFT) + +/* Bitfield definition for register: SYNT_READ */ +/* + * SYNC_TIME (RO) + * + * current sync timer value + */ +#define SYNT_SYNT_READ_SYNC_TIME_MASK (0xFFFFFFFFUL) +#define SYNT_SYNT_READ_SYNC_TIME_SHIFT (0U) +#define SYNT_SYNT_READ_SYNC_TIME_GET(x) (((uint32_t)(x) & SYNT_SYNT_READ_SYNC_TIME_MASK) >> SYNT_SYNT_READ_SYNC_TIME_SHIFT) + /* Bitfield definition for register array: CMP */ /* * CMP (RW) @@ -81,4 +184,4 @@ typedef struct { #define SYNT_CMP_3 (3UL) -#endif /* HPM_SYNT_H */ \ No newline at end of file +#endif /* HPM_SYNT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h index 38204bbaf4..207713d433 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -190,4 +190,4 @@ typedef struct { #define TAMP_TAMP_TAMP5 (5UL) -#endif /* HPM_TAMP_H */ \ No newline at end of file +#endif /* HPM_TAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h index d92ee0dc19..2b6dddcaac 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,21 +10,21 @@ #define HPM_TSNS_H typedef struct { - __R uint32_t T; /* 0x0: */ - __R uint32_t TMAX; /* 0x4: */ - __R uint32_t TMIN; /* 0x8: */ - __R uint32_t AGE; /* 0xC: */ - __RW uint32_t STATUS; /* 0x10: */ - __RW uint32_t CONFIG; /* 0x14: */ - __RW uint32_t VALIDITY; /* 0x18: */ - __RW uint32_t FLAG; /* 0x1C: */ - __RW uint32_t UPPER_LIM_IRQ; /* 0x20: */ - __RW uint32_t LOWER_LIM_IRQ; /* 0x24: */ - __RW uint32_t UPPER_LIM_RST; /* 0x28: */ - __RW uint32_t LOWER_LIM_RST; /* 0x2C: */ - __RW uint32_t ASYNC; /* 0x30: */ + __R uint32_t T; /* 0x0: Temperature */ + __R uint32_t TMAX; /* 0x4: Maximum Temperature */ + __R uint32_t TMIN; /* 0x8: Minimum Temperature */ + __R uint32_t AGE; /* 0xC: Sample age */ + __RW uint32_t STATUS; /* 0x10: Status */ + __RW uint32_t CONFIG; /* 0x14: Configuration */ + __RW uint32_t VALIDITY; /* 0x18: Sample validity */ + __RW uint32_t FLAG; /* 0x1C: Temperature flag */ + __RW uint32_t UPPER_LIM_IRQ; /* 0x20: Maximum temperature to interrupt */ + __RW uint32_t LOWER_LIM_IRQ; /* 0x24: Minimum temperature to interrupt */ + __RW uint32_t UPPER_LIM_RST; /* 0x28: Maximum temperature to reset */ + __RW uint32_t LOWER_LIM_RST; /* 0x2C: Minimum temperature to reset */ + __RW uint32_t ASYNC; /* 0x30: Configuration in asynchronous mode */ __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __RW uint32_t ADVAN; /* 0x38: */ + __RW uint32_t ADVAN; /* 0x38: Advance configuration */ } TSNS_Type; @@ -134,7 +134,7 @@ typedef struct { /* * SPEED (RW) * - * cycles of a progressive step in 24M clock, valide from 24-255, default 63 + * cycles of a progressive step in 24M clock, valide from 24-255, default 96 * 24: 24 cycle for a step * 25: 25 cycle for a step * 26: 26 cycle for a step @@ -149,10 +149,10 @@ typedef struct { /* * AVERAGE (RW) * - * Average time, defaul tin 2 + * Average time, default in 3 * 0: measure and return * 1: twice and average - * 2: 4 times and average(default) + * 2: 4 times and average * . . . * 7: 128 times and average */ @@ -319,6 +319,7 @@ typedef struct { /* * POLARITY (RW) * + * Polarity of internal comparator */ #define TSNS_ASYNC_POLARITY_MASK (0x10000UL) #define TSNS_ASYNC_POLARITY_SHIFT (16U) @@ -386,4 +387,4 @@ typedef struct { -#endif /* HPM_TSNS_H */ \ No newline at end of file +#endif /* HPM_TSNS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h index cf1c0c6787..aafd95775f 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,10 +10,14 @@ #define HPM_UART_H typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __RW uint32_t IDLE_CFG; /* 0x4: Idle Configuration Register */ + __RW uint32_t ADDR_CFG; /* 0x8: address match config register */ + __RW uint32_t IIR2; /* 0xC: Interrupt Identification Register2 */ __RW uint32_t CFG; /* 0x10: Configuration Register */ __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ + __RW uint32_t FCRR; /* 0x18: FIFO Control Register config */ + __RW uint32_t MOTO_CFG; /* 0x1C: moto system control register */ union { __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ @@ -24,7 +28,7 @@ typedef struct { __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ }; union { - __R uint32_t IIR; /* 0x28: Interrupt Identification Register */ + __RW uint32_t IIR; /* 0x28: Interrupt Identification Register */ __W uint32_t FCR; /* 0x28: FIFO Control Register */ }; __RW uint32_t LCR; /* 0x2C: Line Control Register */ @@ -34,6 +38,248 @@ typedef struct { } UART_Type; +/* Bitfield definition for register: IDLE_CFG */ +/* + * TX_IDLE_COND (RW) + * + * IDLE Detection Condition + * 0 - Treat as idle if TX pin is logic one + * 1 - Treat as idle if UART state machine state is idle + */ +#define UART_IDLE_CFG_TX_IDLE_COND_MASK (0x2000000UL) +#define UART_IDLE_CFG_TX_IDLE_COND_SHIFT (25U) +#define UART_IDLE_CFG_TX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_COND_SHIFT) & UART_IDLE_CFG_TX_IDLE_COND_MASK) +#define UART_IDLE_CFG_TX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_COND_MASK) >> UART_IDLE_CFG_TX_IDLE_COND_SHIFT) + +/* + * TX_IDLE_EN (RW) + * + * UART TX Idle Detect Enable + * 0 - Disable + * 1 - Enable + */ +#define UART_IDLE_CFG_TX_IDLE_EN_MASK (0x1000000UL) +#define UART_IDLE_CFG_TX_IDLE_EN_SHIFT (24U) +#define UART_IDLE_CFG_TX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_EN_SHIFT) & UART_IDLE_CFG_TX_IDLE_EN_MASK) +#define UART_IDLE_CFG_TX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_EN_MASK) >> UART_IDLE_CFG_TX_IDLE_EN_SHIFT) + +/* + * TX_IDLE_THR (RW) + * + * Threshold for UART transmit Idle detection (in terms of bits) + */ +#define UART_IDLE_CFG_TX_IDLE_THR_MASK (0xFF0000UL) +#define UART_IDLE_CFG_TX_IDLE_THR_SHIFT (16U) +#define UART_IDLE_CFG_TX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_THR_SHIFT) & UART_IDLE_CFG_TX_IDLE_THR_MASK) +#define UART_IDLE_CFG_TX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_THR_MASK) >> UART_IDLE_CFG_TX_IDLE_THR_SHIFT) + +/* + * RXEN (RW) + * + * UART receive enable. + * 0 - hold RX input to high, avoide wrong data input when config pinmux + * 1 - bypass RX input from PIN + * software should set it after config pinmux + */ +#define UART_IDLE_CFG_RXEN_MASK (0x800U) +#define UART_IDLE_CFG_RXEN_SHIFT (11U) +#define UART_IDLE_CFG_RXEN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RXEN_SHIFT) & UART_IDLE_CFG_RXEN_MASK) +#define UART_IDLE_CFG_RXEN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RXEN_MASK) >> UART_IDLE_CFG_RXEN_SHIFT) + +/* + * RX_IDLE_COND (RW) + * + * IDLE Detection Condition + * 0 - Treat as idle if RX pin is logic one + * 1 - Treat as idle if UART state machine state is idle + */ +#define UART_IDLE_CFG_RX_IDLE_COND_MASK (0x200U) +#define UART_IDLE_CFG_RX_IDLE_COND_SHIFT (9U) +#define UART_IDLE_CFG_RX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_COND_SHIFT) & UART_IDLE_CFG_RX_IDLE_COND_MASK) +#define UART_IDLE_CFG_RX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_COND_MASK) >> UART_IDLE_CFG_RX_IDLE_COND_SHIFT) + +/* + * RX_IDLE_EN (RW) + * + * UART Idle Detect Enable + * 0 - Disable + * 1 - Enable + * it should be enabled if enable address match feature + */ +#define UART_IDLE_CFG_RX_IDLE_EN_MASK (0x100U) +#define UART_IDLE_CFG_RX_IDLE_EN_SHIFT (8U) +#define UART_IDLE_CFG_RX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_EN_SHIFT) & UART_IDLE_CFG_RX_IDLE_EN_MASK) +#define UART_IDLE_CFG_RX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_EN_MASK) >> UART_IDLE_CFG_RX_IDLE_EN_SHIFT) + +/* + * RX_IDLE_THR (RW) + * + * Threshold for UART Receive Idle detection (in terms of bits) + */ +#define UART_IDLE_CFG_RX_IDLE_THR_MASK (0xFFU) +#define UART_IDLE_CFG_RX_IDLE_THR_SHIFT (0U) +#define UART_IDLE_CFG_RX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_THR_SHIFT) & UART_IDLE_CFG_RX_IDLE_THR_MASK) +#define UART_IDLE_CFG_RX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_THR_MASK) >> UART_IDLE_CFG_RX_IDLE_THR_SHIFT) + +/* Bitfield definition for register: ADDR_CFG */ +/* + * TXEN_9BIT (RW) + * + * set to use 9bit mode for transmitter, + * will set the MSB for the first character as address flag, keep 0 for others. + */ +#define UART_ADDR_CFG_TXEN_9BIT_MASK (0x100000UL) +#define UART_ADDR_CFG_TXEN_9BIT_SHIFT (20U) +#define UART_ADDR_CFG_TXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_TXEN_9BIT_SHIFT) & UART_ADDR_CFG_TXEN_9BIT_MASK) +#define UART_ADDR_CFG_TXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_TXEN_9BIT_MASK) >> UART_ADDR_CFG_TXEN_9BIT_SHIFT) + +/* + * RXEN_ADDR_MSB (RW) + * + * set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). + * Clr to use first character as address. + * Only needed if enable address match feature + */ +#define UART_ADDR_CFG_RXEN_ADDR_MSB_MASK (0x80000UL) +#define UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT (19U) +#define UART_ADDR_CFG_RXEN_ADDR_MSB_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) +#define UART_ADDR_CFG_RXEN_ADDR_MSB_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) >> UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) + +/* + * RXEN_9BIT (RW) + * + * set to use 9bit mode for receiver, only valid if rxen_addr_msb is set + */ +#define UART_ADDR_CFG_RXEN_9BIT_MASK (0x40000UL) +#define UART_ADDR_CFG_RXEN_9BIT_SHIFT (18U) +#define UART_ADDR_CFG_RXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_9BIT_SHIFT) & UART_ADDR_CFG_RXEN_9BIT_MASK) +#define UART_ADDR_CFG_RXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_9BIT_MASK) >> UART_ADDR_CFG_RXEN_9BIT_SHIFT) + +/* + * A1_EN (RW) + * + * enable addr1 compare for the first character. + * If a1_en OR a0_en, then do not receive data if address not match. + * If ~a1_en AND ~a0_en, the receive all data like before. + * NOTE: should set idle_tmout_en if enable address match feature + */ +#define UART_ADDR_CFG_A1_EN_MASK (0x20000UL) +#define UART_ADDR_CFG_A1_EN_SHIFT (17U) +#define UART_ADDR_CFG_A1_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A1_EN_SHIFT) & UART_ADDR_CFG_A1_EN_MASK) +#define UART_ADDR_CFG_A1_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A1_EN_MASK) >> UART_ADDR_CFG_A1_EN_SHIFT) + +/* + * A0_EN (RW) + * + * enable addr0 compare for the first character + */ +#define UART_ADDR_CFG_A0_EN_MASK (0x10000UL) +#define UART_ADDR_CFG_A0_EN_SHIFT (16U) +#define UART_ADDR_CFG_A0_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A0_EN_SHIFT) & UART_ADDR_CFG_A0_EN_MASK) +#define UART_ADDR_CFG_A0_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A0_EN_MASK) >> UART_ADDR_CFG_A0_EN_SHIFT) + +/* + * ADDR1 (RW) + * + * address 1 fileld. + * in 9bit mode, this is the full address byte. + * For other mode(8/7/6/5bit), MSB should be set for address flag. + * If want address==0 to be matched at 8bit mode, should set addr1=0x80 + */ +#define UART_ADDR_CFG_ADDR1_MASK (0xFF00U) +#define UART_ADDR_CFG_ADDR1_SHIFT (8U) +#define UART_ADDR_CFG_ADDR1_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR1_SHIFT) & UART_ADDR_CFG_ADDR1_MASK) +#define UART_ADDR_CFG_ADDR1_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR1_MASK) >> UART_ADDR_CFG_ADDR1_SHIFT) + +/* + * ADDR0 (RW) + * + * address 0 field. + */ +#define UART_ADDR_CFG_ADDR0_MASK (0xFFU) +#define UART_ADDR_CFG_ADDR0_SHIFT (0U) +#define UART_ADDR_CFG_ADDR0_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR0_SHIFT) & UART_ADDR_CFG_ADDR0_MASK) +#define UART_ADDR_CFG_ADDR0_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR0_MASK) >> UART_ADDR_CFG_ADDR0_SHIFT) + +/* Bitfield definition for register: IIR2 */ +/* + * RXIDLE_FLAG (W1C) + * + * UART RX IDLE Flag, assert after rxd low and then rx idle timeout, write one clear + * 0 - UART RX is busy + * 1 - UART RX is idle + */ +#define UART_IIR2_RXIDLE_FLAG_MASK (0x80000000UL) +#define UART_IIR2_RXIDLE_FLAG_SHIFT (31U) +#define UART_IIR2_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_RXIDLE_FLAG_SHIFT) & UART_IIR2_RXIDLE_FLAG_MASK) +#define UART_IIR2_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_RXIDLE_FLAG_MASK) >> UART_IIR2_RXIDLE_FLAG_SHIFT) + +/* + * TXIDLE_FLAG (W1C) + * + * UART TX IDLE Flag, assert after txd low and then tx idle timeout, write one clear + * 0 - UART TX is busy + * 1 - UART TX is idle + */ +#define UART_IIR2_TXIDLE_FLAG_MASK (0x40000000UL) +#define UART_IIR2_TXIDLE_FLAG_SHIFT (30U) +#define UART_IIR2_TXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_TXIDLE_FLAG_SHIFT) & UART_IIR2_TXIDLE_FLAG_MASK) +#define UART_IIR2_TXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_TXIDLE_FLAG_MASK) >> UART_IIR2_TXIDLE_FLAG_SHIFT) + +/* + * ADDR_MATCH (W1C) + * + * address match irq status, assert if either address match(and enabled). Write one clear + * NOTE: the address byte may not moved by DMA at this point. + * User can wait next addr_match_idle irq for the whole data include address + */ +#define UART_IIR2_ADDR_MATCH_MASK (0x20000000UL) +#define UART_IIR2_ADDR_MATCH_SHIFT (29U) +#define UART_IIR2_ADDR_MATCH_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_SHIFT) & UART_IIR2_ADDR_MATCH_MASK) +#define UART_IIR2_ADDR_MATCH_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_MASK) >> UART_IIR2_ADDR_MATCH_SHIFT) + +/* + * ADDR_MATCH_IDLE (W1C) + * + * address match and idle irq status, assert at rx bus idle if address match event triggered. + * Write one clear; + */ +#define UART_IIR2_ADDR_MATCH_IDLE_MASK (0x10000000UL) +#define UART_IIR2_ADDR_MATCH_IDLE_SHIFT (28U) +#define UART_IIR2_ADDR_MATCH_IDLE_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_IDLE_SHIFT) & UART_IIR2_ADDR_MATCH_IDLE_MASK) +#define UART_IIR2_ADDR_MATCH_IDLE_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_IDLE_MASK) >> UART_IIR2_ADDR_MATCH_IDLE_SHIFT) + +/* + * DATA_LOST (W1C) + * + * assert if data lost before address match status, write one clear; + * It will not assert if no address match occurs + */ +#define UART_IIR2_DATA_LOST_MASK (0x8000000UL) +#define UART_IIR2_DATA_LOST_SHIFT (27U) +#define UART_IIR2_DATA_LOST_SET(x) (((uint32_t)(x) << UART_IIR2_DATA_LOST_SHIFT) & UART_IIR2_DATA_LOST_MASK) +#define UART_IIR2_DATA_LOST_GET(x) (((uint32_t)(x) & UART_IIR2_DATA_LOST_MASK) >> UART_IIR2_DATA_LOST_SHIFT) + +/* + * FIFOED (RO) + * + * FIFOs enabled + * These two bits are 1 when bit 0 of the FIFO Control + * Register (FIFOE) is set to 1. + */ +#define UART_IIR2_FIFOED_MASK (0xC0U) +#define UART_IIR2_FIFOED_SHIFT (6U) +#define UART_IIR2_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR2_FIFOED_MASK) >> UART_IIR2_FIFOED_SHIFT) + +/* + * INTRID (RO) + * + * Interrupt ID, see IIR2 for detail decoding + */ +#define UART_IIR2_INTRID_MASK (0xFU) +#define UART_IIR2_INTRID_SHIFT (0U) +#define UART_IIR2_INTRID_GET(x) (((uint32_t)(x) & UART_IIR2_INTRID_MASK) >> UART_IIR2_INTRID_SHIFT) + /* Bitfield definition for register: CFG */ /* * FIFOSIZE (RO) @@ -64,6 +310,176 @@ typedef struct { #define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) #define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) +/* Bitfield definition for register: FCRR */ +/* + * FIFOT4EN (RW) + * + * set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) + * clr to use 2bit(TFIFOT and RFIFOT) + */ +#define UART_FCRR_FIFOT4EN_MASK (0x800000UL) +#define UART_FCRR_FIFOT4EN_SHIFT (23U) +#define UART_FCRR_FIFOT4EN_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOT4EN_SHIFT) & UART_FCRR_FIFOT4EN_MASK) +#define UART_FCRR_FIFOT4EN_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOT4EN_MASK) >> UART_FCRR_FIFOT4EN_SHIFT) + +/* + * TFIFOT4 (RW) + * + * txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. + */ +#define UART_FCRR_TFIFOT4_MASK (0xF0000UL) +#define UART_FCRR_TFIFOT4_SHIFT (16U) +#define UART_FCRR_TFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT4_SHIFT) & UART_FCRR_TFIFOT4_MASK) +#define UART_FCRR_TFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT4_MASK) >> UART_FCRR_TFIFOT4_SHIFT) + +/* + * RFIFOT4 (RW) + * + * rxfifo threshold(0 for 1byte, 0xF for 16bytes). + * Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled + */ +#define UART_FCRR_RFIFOT4_MASK (0xF00U) +#define UART_FCRR_RFIFOT4_SHIFT (8U) +#define UART_FCRR_RFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT4_SHIFT) & UART_FCRR_RFIFOT4_MASK) +#define UART_FCRR_RFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT4_MASK) >> UART_FCRR_RFIFOT4_SHIFT) + +/* + * RFIFOT (RW) + * + * Receiver FIFO trigger level + */ +#define UART_FCRR_RFIFOT_MASK (0xC0U) +#define UART_FCRR_RFIFOT_SHIFT (6U) +#define UART_FCRR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT_SHIFT) & UART_FCRR_RFIFOT_MASK) +#define UART_FCRR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT_MASK) >> UART_FCRR_RFIFOT_SHIFT) + +/* + * TFIFOT (RW) + * + * Transmitter FIFO trigger level + */ +#define UART_FCRR_TFIFOT_MASK (0x30U) +#define UART_FCRR_TFIFOT_SHIFT (4U) +#define UART_FCRR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT_SHIFT) & UART_FCRR_TFIFOT_MASK) +#define UART_FCRR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT_MASK) >> UART_FCRR_TFIFOT_SHIFT) + +/* + * DMAE (RW) + * + * DMA enable + * 0: Disable + * 1: Enable + */ +#define UART_FCRR_DMAE_MASK (0x8U) +#define UART_FCRR_DMAE_SHIFT (3U) +#define UART_FCRR_DMAE_SET(x) (((uint32_t)(x) << UART_FCRR_DMAE_SHIFT) & UART_FCRR_DMAE_MASK) +#define UART_FCRR_DMAE_GET(x) (((uint32_t)(x) & UART_FCRR_DMAE_MASK) >> UART_FCRR_DMAE_SHIFT) + +/* + * TFIFORST (WO) + * + * Transmitter FIFO reset + * Write 1 to clear all bytes in the TXFIFO and resets its + * counter. The Transmitter Shift Register is not cleared. + * This bit will automatically be cleared. + */ +#define UART_FCRR_TFIFORST_MASK (0x4U) +#define UART_FCRR_TFIFORST_SHIFT (2U) +#define UART_FCRR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFORST_SHIFT) & UART_FCRR_TFIFORST_MASK) +#define UART_FCRR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFORST_MASK) >> UART_FCRR_TFIFORST_SHIFT) + +/* + * RFIFORST (WO) + * + * Receiver FIFO reset + * Write 1 to clear all bytes in the RXFIFO and resets its + * counter. The Receiver Shift Register is not cleared. + * This bit will automatically be cleared. + */ +#define UART_FCRR_RFIFORST_MASK (0x2U) +#define UART_FCRR_RFIFORST_SHIFT (1U) +#define UART_FCRR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFORST_SHIFT) & UART_FCRR_RFIFORST_MASK) +#define UART_FCRR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFORST_MASK) >> UART_FCRR_RFIFORST_SHIFT) + +/* + * FIFOE (RW) + * + * FIFO enable + * Write 1 to enable both the transmitter and receiver + * FIFOs. + * The FIFOs are reset when the value of this bit toggles. + */ +#define UART_FCRR_FIFOE_MASK (0x1U) +#define UART_FCRR_FIFOE_SHIFT (0U) +#define UART_FCRR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOE_SHIFT) & UART_FCRR_FIFOE_MASK) +#define UART_FCRR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOE_MASK) >> UART_FCRR_FIFOE_SHIFT) + +/* Bitfield definition for register: MOTO_CFG */ +/* + * SWTRG (WO) + * + * software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. + * Hardware auto reset. + */ +#define UART_MOTO_CFG_SWTRG_MASK (0x80000000UL) +#define UART_MOTO_CFG_SWTRG_SHIFT (31U) +#define UART_MOTO_CFG_SWTRG_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_SWTRG_SHIFT) & UART_MOTO_CFG_SWTRG_MASK) +#define UART_MOTO_CFG_SWTRG_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_SWTRG_MASK) >> UART_MOTO_CFG_SWTRG_SHIFT) + +/* + * TXSTP_BITS (RW) + * + * if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits + */ +#define UART_MOTO_CFG_TXSTP_BITS_MASK (0xFF00U) +#define UART_MOTO_CFG_TXSTP_BITS_SHIFT (8U) +#define UART_MOTO_CFG_TXSTP_BITS_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTP_BITS_SHIFT) & UART_MOTO_CFG_TXSTP_BITS_MASK) +#define UART_MOTO_CFG_TXSTP_BITS_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTP_BITS_MASK) >> UART_MOTO_CFG_TXSTP_BITS_SHIFT) + +/* + * HWTRG_EN (RW) + * + * set to enable hardware trigger(trigger from moto is shared by other UART) + */ +#define UART_MOTO_CFG_HWTRG_EN_MASK (0x80U) +#define UART_MOTO_CFG_HWTRG_EN_SHIFT (7U) +#define UART_MOTO_CFG_HWTRG_EN_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_HWTRG_EN_SHIFT) & UART_MOTO_CFG_HWTRG_EN_MASK) +#define UART_MOTO_CFG_HWTRG_EN_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_HWTRG_EN_MASK) >> UART_MOTO_CFG_HWTRG_EN_SHIFT) + +/* + * TRG_MODE (RW) + * + * set to enable trigger mode. + * software should push needed data into txbuffer frist, uart will not start transmission at this time. + * User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty + * NOTE: the hw_trigger should be pulse signal from trig mux. + */ +#define UART_MOTO_CFG_TRG_MODE_MASK (0x40U) +#define UART_MOTO_CFG_TRG_MODE_SHIFT (6U) +#define UART_MOTO_CFG_TRG_MODE_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_MODE_SHIFT) & UART_MOTO_CFG_TRG_MODE_MASK) +#define UART_MOTO_CFG_TRG_MODE_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_MODE_MASK) >> UART_MOTO_CFG_TRG_MODE_SHIFT) + +/* + * TRG_CLR_RFIFO (RW) + * + * set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. + */ +#define UART_MOTO_CFG_TRG_CLR_RFIFO_MASK (0x20U) +#define UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT (5U) +#define UART_MOTO_CFG_TRG_CLR_RFIFO_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) +#define UART_MOTO_CFG_TRG_CLR_RFIFO_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) >> UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) + +/* + * TXSTOP_INSERT (RW) + * + * set to insert STOP bits between each tx byte till tx fifo empty. + * NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set + */ +#define UART_MOTO_CFG_TXSTOP_INSERT_MASK (0x10U) +#define UART_MOTO_CFG_TXSTOP_INSERT_SHIFT (4U) +#define UART_MOTO_CFG_TXSTOP_INSERT_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) +#define UART_MOTO_CFG_TXSTOP_INSERT_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) >> UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) + /* Bitfield definition for register: RBR */ /* * RBR (RO) @@ -97,6 +513,58 @@ typedef struct { #define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) /* Bitfield definition for register: IER */ +/* + * ERXIDLE (RW) + * + * Enable Receive Idle interrupt + * 0 - Disable Idle interrupt + * 1 - Enable Idle interrupt + */ +#define UART_IER_ERXIDLE_MASK (0x80000000UL) +#define UART_IER_ERXIDLE_SHIFT (31U) +#define UART_IER_ERXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ERXIDLE_SHIFT) & UART_IER_ERXIDLE_MASK) +#define UART_IER_ERXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ERXIDLE_MASK) >> UART_IER_ERXIDLE_SHIFT) + +/* + * ETXIDLE (RW) + * + * enable transmit idle interrupt + */ +#define UART_IER_ETXIDLE_MASK (0x40000000UL) +#define UART_IER_ETXIDLE_SHIFT (30U) +#define UART_IER_ETXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ETXIDLE_SHIFT) & UART_IER_ETXIDLE_MASK) +#define UART_IER_ETXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ETXIDLE_MASK) >> UART_IER_ETXIDLE_SHIFT) + +/* + * EADDRM (RW) + * + * enable ADDR_MATCH interrupt + */ +#define UART_IER_EADDRM_MASK (0x20000000UL) +#define UART_IER_EADDRM_SHIFT (29U) +#define UART_IER_EADDRM_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_SHIFT) & UART_IER_EADDRM_MASK) +#define UART_IER_EADDRM_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_MASK) >> UART_IER_EADDRM_SHIFT) + +/* + * EADDRM_IDLE (RW) + * + * enable ADDR_MATCH_IDLE interrupt + */ +#define UART_IER_EADDRM_IDLE_MASK (0x10000000UL) +#define UART_IER_EADDRM_IDLE_SHIFT (28U) +#define UART_IER_EADDRM_IDLE_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_IDLE_SHIFT) & UART_IER_EADDRM_IDLE_MASK) +#define UART_IER_EADDRM_IDLE_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_IDLE_MASK) >> UART_IER_EADDRM_IDLE_SHIFT) + +/* + * EDATLOST (RW) + * + * enable DATA_LOST interrupt + */ +#define UART_IER_EDATLOST_MASK (0x8000000UL) +#define UART_IER_EDATLOST_SHIFT (27U) +#define UART_IER_EDATLOST_SET(x) (((uint32_t)(x) << UART_IER_EDATLOST_SHIFT) & UART_IER_EDATLOST_MASK) +#define UART_IER_EDATLOST_GET(x) (((uint32_t)(x) & UART_IER_EDATLOST_MASK) >> UART_IER_EDATLOST_SHIFT) + /* * EMSI (RW) * @@ -159,6 +627,19 @@ typedef struct { #define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) /* Bitfield definition for register: IIR */ +/* + * RXIDLE_FLAG (W1C) + * + * UART IDLE Flag + * 0 - UART is busy + * 1 - UART is idle + * NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR + */ +#define UART_IIR_RXIDLE_FLAG_MASK (0x80000000UL) +#define UART_IIR_RXIDLE_FLAG_SHIFT (31U) +#define UART_IIR_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR_RXIDLE_FLAG_SHIFT) & UART_IIR_RXIDLE_FLAG_MASK) +#define UART_IIR_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR_RXIDLE_FLAG_MASK) >> UART_IIR_RXIDLE_FLAG_SHIFT) + /* * FIFOED (RO) * @@ -173,7 +654,7 @@ typedef struct { /* * INTRID (RO) * - * Interrupt ID + * Interrupt ID, see IIR2 for detail decoding */ #define UART_IIR_INTRID_MASK (0xFU) #define UART_IIR_INTRID_SHIFT (0U) @@ -380,6 +861,42 @@ typedef struct { #define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) /* Bitfield definition for register: LSR */ +/* + * RXIDLE (RO) + * + * rxidle after timeout, clear after rx idle condition not match + */ +#define UART_LSR_RXIDLE_MASK (0x80000000UL) +#define UART_LSR_RXIDLE_SHIFT (31U) +#define UART_LSR_RXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_RXIDLE_MASK) >> UART_LSR_RXIDLE_SHIFT) + +/* + * TXIDLE (RO) + * + * txidle after timeout, clear after tx idle condition not match + */ +#define UART_LSR_TXIDLE_MASK (0x40000000UL) +#define UART_LSR_TXIDLE_SHIFT (30U) +#define UART_LSR_TXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_TXIDLE_MASK) >> UART_LSR_TXIDLE_SHIFT) + +/* + * RFIFO_NUM (RO) + * + * data bytes in rxfifo not read + */ +#define UART_LSR_RFIFO_NUM_MASK (0x1F0000UL) +#define UART_LSR_RFIFO_NUM_SHIFT (16U) +#define UART_LSR_RFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_RFIFO_NUM_MASK) >> UART_LSR_RFIFO_NUM_SHIFT) + +/* + * TFIFO_NUM (RO) + * + * data bytes in txfifo not sent + */ +#define UART_LSR_TFIFO_NUM_MASK (0x1F00U) +#define UART_LSR_TFIFO_NUM_SHIFT (8U) +#define UART_LSR_TFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_TFIFO_NUM_MASK) >> UART_LSR_TFIFO_NUM_SHIFT) + /* * ERRF (RO) * @@ -512,4 +1029,4 @@ typedef struct { -#endif /* HPM_UART_H */ \ No newline at end of file +#endif /* HPM_UART_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h index 72fdc9dcd2..8f18e72f3d 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -2194,4 +2194,4 @@ typedef struct { #define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) -#endif /* HPM_USB_H */ \ No newline at end of file +#endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h index 624f748fd7..2211664822 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -298,7 +298,7 @@ typedef struct { #define VAD_ST_VAD_GET(x) (((uint32_t)(x) & VAD_ST_VAD_MASK) >> VAD_ST_VAD_SHIFT) /* - * OFIFO_AV (ROI) + * OFIFO_AV (RO) * * OFIFO data available */ @@ -424,7 +424,7 @@ typedef struct { /* Bitfield definition for register array: COEF */ /* - * VAL (ROI) + * VAL (RO) * * The current detected short time energy */ @@ -438,4 +438,4 @@ typedef struct { #define VAD_COEF_STE_ACT (0UL) -#endif /* HPM_VAD_H */ \ No newline at end of file +#endif /* HPM_VAD_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h index 5f99205e46..5322d5c1a1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -153,4 +153,4 @@ typedef struct { -#endif /* HPM_WDG_H */ \ No newline at end of file +#endif /* HPM_WDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c index 3db7cd3651..75ca411ff1 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c index 8c4a9590fb..027d8c660e 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c index b728f257ae..57dd6471dc 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,7 @@ #include "hpm_common.h" +#ifndef __riscv_xandes uint32_t __bswapsi2 (uint32_t u) { return ((((u) & 0xff000000) >> 24) @@ -26,3 +27,4 @@ uint64_t __bswapdi2 (uint64_t u) | (((u) & 0x000000000000ff00ull) << 40) | (((u) & 0x00000000000000ffull) << 56)); } +#endif

    >Mx6{V=eY8+$D`-hYzklv*{RQMjMw+B}Qi1Q27X?Y05=4e9F91uDrldCH zC~tCSFSUdGp*T4>pg$PlEo@lhTC3NUXl>khSF)r>A)S*|6+D#dV__^i2YtdgV4S+f z#X{%EVrt38^iPereCsmG_epZc=MXlvP=0BvV#t%W+ukA81pqbJgqzRk>T4Dn_f; z;*!QCXJDlQX_X*-CZ3<|UDbY8uZ1NjuW9(Aas;eYGxKZluU)WyVI;!r( zRhiSmtP`+sV&?kaO~nXxRgmnghdw(-NiN!V_H6^_pIL?G;rSrT>r0ak-`jy_dYSHzP7_v(03(>MEk{fhfwi8{n=gZWhD zrJBIPlUS?qiWC_}6m_oa$)uPSf;=rqh7)Wv#*2dTSl{J;<=}mNW~?7G0f;TJR*HgfBJ~nj1fvY8b$d4geaW5igDKAl{1x)WzefU zJmrEUQ+I8AV&K-a1NX{|E{7~R%{nVBF&#hKWi+WBblkVoR24I0EECgU;mT*(eC9RO9#=PCrxk|r4F9`6XkT~}F zWT($K)x7cc13K*{?d%k5puMz!>MXLAwb6qnfA+%967a2%S#uM^sf$~EV~wV}uuK>?PzZG4?07AfG|yRH zzrxL%H*N3uh(G(zPwA%tHe5m~QIC~sAFqSqN(^DFqr|#_>I^5OYc@De4dZlL1A%nd zqc}Yf>9|iJ7m4HrY+(8F=Wg-ye9ZR4`)=-M2__9N&BzfrwLw~!STV*WBeX61Zhfli zUDiIT+o95ERiLDHtt(P=WMp++}`lZ z7Q0o2eO@wOH79+d8eM+O&IJY4xtzALPEP;I9=`@4^M~tZ2S`kwK&J767}aQD@DWns zDMt$ci%>p67$UJKVO-O)Upm|Zpgd1RVPNCPvy0srYXh|Bi{9AMZMPYvmNd&Lv}I#` z2_Y1>@8q299Mg;(?W-AjTwQO`pJY^ZRUrjgVL0oLnPz|zpj;<(X>BR5mLOCWbCq$K zDT78Qf|}2)Rl;ASAYNG`L6V;z<7YY9$swv!AfhIs>ZM^cFW+2aBhoxN9Pre7m(Sn2 z#hrVHEOjC*aCSCeJRI^{&#iGquG2f#B%=Yj7^9>j?zF5QwZ+9tU0(UjMLyUWV0BK^ z?m*xK__okw=V!<)!DbVtlRhFJF^(ZpDamjMQlf-p?b`Fm_By-0A-PQmn{9$Pa9-#} zW2{HRw_INg`NH!Tco6o9LZ9ZsGNVG;GgXLW*k?o=6+~QE>$nW}RI|{IXg5NR`%^TA z?qUOMY1>QTp1qPK-~lN;WXb&$NNka#l^|+FjErJ@I-n5;Sg%1|Xo^XnBIpuCT@)Hg z0SJr+4}no0x(u9zwFo6CjN!c36WRD2GmV){VE6F@l4-)x;UUTJ9G#~ep7-c>I&3U= z*qs`@px}4DbdCG_Bcz3K;sT@f^#!K6W;n^qMt>!*zXVoR2)w}cm-+PJssmMyN4Q3o zt;Q_Cs@^vjoY&ift@q24njosOo%?(_?(22F1Sg+%l&UBoPr98{e>iYnchapg_jXn> zkXTTP!b&_{ke;0q1|eP$Q&UUAX@j6D4#>+8IO?Y zLemI+p1QcqSti)nRJ`!q1@;fmh#m~M_|z&_mIK}un&k8Vge^DH`kUY>52XaE?DB2P z`P^x?SY27>@N~d!im=q{l}@E32qRRJv5#azu%_#)GpU z##)Qca+1-QMz=-aD>sj4@licet*xw?%W-Yzsw8DE9$&dRxzzAE>KU4m$4k#`u(;IZ z_Jd6c$yx)KzY4uEL|sIVGhV5W1qA7+t&6RR#vtSXat9F%@}EJ{^;e`j~VK zc$}a0X(-EcPhVlYu|gvb@TDf|9OE^+1l<*)M$FOqly~kPvboe?Fi03BnrxbJdN$$h zkM;Q?a)EkD5zG+?6@aiLNzUTp8cVGUJihk?V3{1viJ0|cH(bAQN5?b9sH8-+cZzc=cy@IL|V)@72Cm zRW;65YbNC$1ZB@3mpqb{&8?Dd4>bj8?-1SZxuh9_ey_(Tw{N3t4#uD-XJCu+ytDHg zqtQiCR|BlJLTl|PF77Qwf_{xZ*8Tjk-yZIZJdI_dIgug7;^ zeV@@J2kDh!b7nLXDN9ODdEq)h6D5bZG2`f^J%QCBBC~-@3Gnmc=gq{=#4dh^t&$;=$y81d2oM^#l;2-?TF>TqbsKN z%5uaX{mvhW-r*McbcjH(e)$@wqr(3E_g)o&9^1BW#5BwCT5WXMA3;wie0C$?U;f@# zDU9ZwcW(3A_y3OJ;X@KqL@CakBq`H|Pk5zEp5_$RqC!mwb$~g^44>>y*+~z0@8fMo z;|T&w)E&`UxytEuho@g?uzG2QZ@heoJkL2gn~-Zu?{q{q8gp_wW_oz$Gz|!x6u!&^ z<0=5UqScgQTnB&*CQZ0>d6Ap1e2I5nAMx$qe2JGo_c{CKJMZ)T@BctN`_EMSZk2h&}u~7Kb!I&{_=->{VOk$WSZ~&{2t??!QJfquFY5)KAC?%T8}Xkr(V7kC`MHhbQBig>044p#rjQ zq}7169CpkZuQF4f@4a7Psn9IP=vSKbMnr$>S z=&3$aZ6u%CJZ8dqfeb=ar%Ta4MdlgF@e$G522ur2Y(lOlif|1geOD!QSi{jCO;te< zCD1ST;Tn8Y=P2)6O3B$o^XEUl&x_ZW`S1VnEe7L+?LA8zD8`c%|5BIV_{KMxjwj?< zj?Qz8HW*>?lyVfXAaLNy7>ss-aJSi@(~fALjnEdSRjVF@nE|khlP=3lejr4tRYV_M$-u@^oiSzI^!CxZ;~825Ykw`08sj7c(g zaf9S!nA%4NeKAg)fLsWP)&-gzB~=M~-5gZ1)Errh@42c6B_LB$)>&mYk3IK{lt*ur z^LT5Qq&G!)5l52&um2#$4?_xTX|~!(&8mxbxoI+vH^235-hclNXQ!up_|a{K!=YQA%Ah(7L*ho0Fp5dj)HM>!9i>M}F;|t8ctJ>B zIO|%Z%jz3z38R=!yo8d9AP6wV(mOsPolX%_(P_01!m_c{;dg%L+vHhp7uHwBn{Orz zGAV)}peP$-VnIq#S2-Gu28A(9lbp&`(6Jz#1-BFeUqX6zOn!ds?pY|5R7@rl-g^5Z zbe>?XMoEeE9DsH`&S0C8a=ow0xmi|Sjjb3O zB@mYtaG!ye>a((*J7qvKmtbOkK3ZxKewARGX*gyyVNv;;&o1`_@Q}=$uIl8NrM7^t zjcV-7^g;lI*22_C{a5e!H2^7(0PR^Tr7iiK0J*jZVaT!+D*~dxBa#9SiznTr1i|3! zkO1~T3BQAFLlA~E+ubKmYyk{W+z?l;UAJHT;>27z=*!GTB(}*1$3D|wf#cIYSm)Ut z1RnPu?6JRh;+&Ai0}dWOq8OafKiH=z1f?w4S?=N{xx!XPsk1n+oH(jvkF z7?pi&Z7_#Hkqif@Mw3RnNm{hg;|W2i$dZ(NG)9I^tbsJsJbmLLw|tMQ>s_|?Pf?zS zk&-mi_)-!nOO_X+cXrO`{0LEu5Jd{YqLYEhCpn|hkil>)JQP9Tp`S$ z{H57~nlVB^k!$iS#Vc~WFhZ)3F!W1$h(TD*XKp-2 z?0tiSy?vxkSqUPL5g-vle@K{-C^ZmDXXg7V7Qasr0v)E}c7>v2U-{bP-6*iZf z9Gp!MrPX5v2CH!-khN{C1dLD!PofKt#icI)^&ftLMytg_v*70CC2@4T!RNpBZT_o& z`CssF{`^gjiUU;Kz*2gwTSGD!ptF6#wGFK2Q)C6*X3Vu0zr;Jcha?XqSyrGIpXRBK z8y{nx@WXp!PD4R&l8BM*upGqfpA8rv=Y)Z(BOM_GcXkG4hE)NwW-UR({q{@xDjqE;{tbCRbk3aSC!6WLOQxk=u46`r_i8{AlGgX7&Ap!M+2=A_AcvPRYOW0T9%Uj z|LncVuWiY7=J$(;-JkCE&Ff!w%!Xu=$wpGCE7OovQpo~b1$!pgfKi@!{5lQDxYM;ZjMZj%vs(l1Va|efKh7d;5Fty{F$@M0gOf_c<>m`42D|zH<6L7pYp5U~ z*x4f&Fh4t`vmcPHuMuFF4~NucPIrBs5aWV>izgWv=jbZg_Ah!0wX`()*?!8HCGW)} zz|B$j}Q6e z>Jp^_;y9ux3WuZzVasU=gAl0{MV?cX1wjyCt)Z@(vK8TOvGz)F#?Z+!?%v$v*7Y4m zs9w0;K{1pW#vhvVI>zr`8pE2RG?tI3muI zm@nL1ke;8Q6mbx6eQ%RnJ3U6@3AL^<<&>?#1|o4BlWC!;w03>Kgdj~5LQ}D^*5z`d z7)=)rI9RcRp@jPCg!25D(64W+HC6_wtVg5*s(cPsFM|iG9k7NYwhO78GNP2OPnNXS zVuX}}Bnm7@@pN-P$FXp0(6ow*jpHs6ZRXGT4YpOnY7ViQlxWs(6TRaCKa1mjEHf@o zXEPd3Ov5XAs)S80-_r&wERWGL6onv)q9v$hSN4`h^~WwjJ7cUAf{>rm@v{KLkGd*_ zP)b&1fsG|my5{PgRY(|w2w{l=2$U;rQc;YkG~-z<-u>Vq?rkYJxaJ z2+8oW;OycAWP}VFRU1Go%N;Z{LPb8)DBH;{<#NIMJrxI!_?lw1M5r4C)YWi8etAhf zpV962m{<#y##jkBg^kJ>-ud*5*Y5PmYr~H}KB5~d4$g*jIw>Mbc>nPw@r{hHzkG*_ z%OP+4Xvn8fvF-kFvS=fn}k>#Gu@HC6@7 zOooT?jn?f((4f!le$Y65E5B>Oe`{Ohtwp7ptVFXQKbI!gSgfuw2rr?zM6FtssW}hY zlUN=LsLPsiUJyhfN!OKxNS4R)D}sj94mb__{yM@~%=ijXEXdDJoGM%pwS7SZPO^J8 znj(PCS`Q_I<#o4#h-@8Ae>2+aZWO+hl3dPeK0cgMI>kR-*1Y`8CgW*NnuPRwDgACtp4Ytb?h&<> z2yY`q5Vpr{_iyR1$2)}9f=EIbKsg?R3dwdi(6cFeGDaGW9$gY|Zu8Flb4qO(n+RJd zqze6XCvp72@+q;H|QivitJG(4SkC-1HlkV&x6URGSSq&{H z)POvzf;i1i;pTyx8x4Zn*fS}Gv)NWO{T^LM^iuQOjddO#UUGgu=E-S?;W)=2*_zcn zIxl!~mUD9uaCCIeFMa(Pl*u{x>@$=pnV*d?BE-&nsP#35lbjb{e4cqwad7w$69~+F z!h<7Cv6yjidWn>ZAaIh)QK(qtg)h6&BuVT7SyQ8w1Y>=cO;DLe*3}Ky+ae$c6vN9a z9zH&_RauI%ERn>nqkU~LMi2y&IEn}&OBe;DX+%Nb6d`@~)B62PTZPK9_TCGtn@tTT zRVe}O=Rh;h98xZjoL^k=@x6QE!*_nn;o$*4e)BCp{^V0W{9v1R-v5}RgC|^#r(8`- zROlp#!zf~~wt=>mvy&r?F>LSb(jTmGF+4{b!(=w+{P+-KJwPF#_UcSQ7@$jcKeBF* zd_Lvk?97#@DS=XMUaKf%KAUnmyx^^OKcp^mzV_Nzgfe5w`3y2kCyuC*h|=JzfZU~P zP1JEsl&vwXnXp(?5D-U->hg^F=@FsNIA~)a%81vylvN3{F)Ey4>$i`;g4+rUDX7-bR598S)gA5!h;qoAl7PGs`YEP={?ohQn?Z+e10ss7#@K2^4rZi zqdoF6)$B!=V)4lNwzxf-#!n8CT3}@KhI#D=4 zg<;z>A*5Xc;5%P83q>@g8~DlII29I`9r4b%5KD=;rfHtEjWfJ-h=fNVq<3_Mu2`I% z5L!!|BvhU}A9Q-mCo@!(BD+1R(sczsy{hpU}DCN!1 z9`IlO{{IC*#G}(Gj~_ooj2@B3Awozm54k{?0zExP&qvfjhoY#l)}XA#ZbUph9P;D0 zJ|HbmdH&jf@#!OyB*PSaW~Jh=N~waFmu~O#=w!lQyzv>o@bWJGNKvh4T;ClKhLTPa z5QU0b2$WC=Cp_p<($*P0;|(buT^2$R1rbN1l7I1+AMp>rvd=&K)>pY2p4hLvyv`2~ zEdTp=J|*c7h(hHgU_A%iU=c}1x_gbq*%6b&Ltc3CF4wkuoF1LH?#Wq3piA`R5@|G2 zHImB$Sq&iRQP0MtR`acwcX{{Wi0}O9A!#oq$}%b|2tq}EH6}m5Alujg8B#80XswB) zYBLNp&NEBLy_uVh8WOG3z2s}On^2QIuyz^Dd@dLOrz)4M_1o`Phwy*j1|NR&dMcY? zT|=^l0pk5vP>aQs#yraGWhGgj2$B`jailE_|+ISy$z+L@w`5 zvms+$$SnN1uMaY`G4!&S`MgA6`RWUMeDvs&%Xx*Afv<&j^SRmn+i1!=$yPL-z!l-f zHqpkG<3#BaeRYXcu6(B+kEzO|A4UcEa@Jn9jx)fs~ji z!s?p3s#_G)m>?kAyT;=5g!#!a-Mu|T6r;6W9>YI(*F&dq%tZUVMeE2kiarf5>FKgP znrCkf63dOvjLnWB+V2w7IcwdJeirbBn*(AAFWeX~nwI>+tJfG#7R<|cM1KmQ}X_M5-K&%O9O|NQ^{W6B#_$V$L;gpnGmIbVM1C4TWM&+;$-)q;24 ze#bQ^6a`5X5``h!Xp~Z}5ur8IRf#s1FmOsv(i770Yf&kQRDoASg4;KC`Qmdo#rNL2 zPY}i+LjtAP-s!WxKH%zV%EiSM(pc)nocYNy@%Ao81k{G7Y=seRCmZLU`if(#T}cnZ zcr?A)Uz^fAflNER{_Z2rE-#r)M%;h!fZ@p*CRdzHPI>3!M_8kgVN4tb^rHk@kSm(!&3LcC2)Co2>HoqE+(l~CDiV}o$+=jd;(H1TzxeI)h6RZ(Z z`pm~U#n}N0FGy@bh6&O7Hl>9mjEIG0QZBIG$+lh|T8IFx4ca=cMN#Wk;mjgHxD0z$ zl>*S?!h=|)K#5K_OJ8|zYjgL{ z;Aa8IPwSYMT7$NMa*9zZaK_XTunb`sP>TQ=#Y9mD6$I!icZwfDfC?j^!s*I;+^UU3 zEEXlC3hAUNac971MunY#Ujcb!=ZtGGiwkxv2=n~gd~6l4fgR&7@|5o7Q=Jb$SsP|aYnS3pw>5CS&Xr+ zECxxp7gN=SNGN0&QfZ460jLla!J;%&BH{awF3`q`BwpvvYk!Yhul+JgD(bT21ak}AyA6ETCmqs$ms=Tu2E7U&cv1eAQOLT^0FQhNY5XfrI;^YWb6&O>wdUF+Gssg50 zq@50h5l=mf23fRPgU^H%r!YMmB7~xk;WP$<19e*0!Y}ZKlmyw3H+}yX2?G%#Myp_x6xUhE@T|&JOdF6VDadMTY58 zYS%6iS9jQD2}x5X)|6;861*!F8!ppk+-th1kU$hFq5yXK36sf!vvJP$yku*TqHE3D z4^H`|S8uU1NZIJ6T))1BF6Inm#4GzTdwt1AYXO-m*vw#m5F@IB*?3GSd)TUgz=>b{ z@SV?i_{oPHKDvie%B=}4n9diDCmDuhX-cIvwbn?foCA*W84)*6j4>#sTxpx{M*;BR zN1rmPQXU+g^Np{3i3i6s)(0Kd*SlQXTj%0xz_-79>7I)e=*gIcHpIKT7^xh`32%3r z(m+cKOjvEbytjGENp%%HUWCC~f;i!PC^>%X5b6cR!lF%z)pKlJyQaQM5(J6}R}y7> zADGeTit%_v7z7|Ze=i7I@MAK*0^ztIZv8lWXtbs>E}#sAz|^kCSCYh73uRuo#*WGd z%s9SA5Jn6qIp;Hpj5_E@A%tR4R*wG^xIR%0QZKBaC@SwCFO~Bm1!jE4;_T2l`wibB zjL0_jF;XF`ob8Q19OhbK(+v zrVSRH+atZ2r}2-rNwqfS{psvQQ*zpT-xzT#KBs8qZADWG)~LB5nrt!%)LoWUx?U?wX=EuwjIEGD$i-r@mKTeZpThC80K^Xwr7pl0ia1Kp zLXcM#i4p`!iU>hzSNAOaqAO<;hx8OV(i#M%y*htPkw(@SE0Ep^5dkuAn@W;qM4djf zh2hPIV`PvZq6j4e>e{-#G}g(|il)o6X$)$!Xf?%jMlqQY4|>E|;v6bZN*7J1QR6mL z2j+Qa$RjVzzXF)$2T2v z>E)2aQOO_u_z+_ZWo?j536=DuMEAZ*WYlrO@Y5kb`uG&n*}_H<%37#2^VyuJ6BBP; zM?@LL=_A6$h(KtX@T@2b>Z<0MTf6-BKl=BHlZ-FF^ekWf(o1~*?R)&kZ@fWSB^U%x z4lg;le8RntKf-8Dk|aRDsF0Z6f)~Ddiw_{~xwF4U6o)J>PC2;$F~9w5KgTy-y~F9z z3D2xc&hGAVFxD+;4?kb554Ichx%oXbIQh~jx1?)UG9AWv30Ki(M^+_voB7-H4`>`} z_uBGPTZDD>*vg23yMz1GkyASxS&AN-nG7j?KL_c3CRamRcHvu4-Id8u*5%jnWe|S*OOy z5UW85_~wcJ`lLV$#pClC-*|DCi>nz$S#kIJIv*X37|kkV5W41l_%c0HQ_mJyDN#v= zwW@Wj8xTW!lB%pris2cm%%Q3Awic@^q>>bu7t}>fxV3{yyRCC*nv9TlV6_lL8`~He zLRk`bdc^B}Y&FMBCarzc7LslXrbf@rvb(bIjtn?O9%I~GYv-$NV&bRgr~h7f*xUw+ zWM>a^a?1SVn9j}~GV7paKxcQ4*|96f%69h#vELg{Ih@cCIdC&@uLe&w$JxJJmau>i$!`19j;;PiZBWYLq%OlUU=?Ve)+X$ z`SzdwA@9BW4uJ|=H8|zvb@L)eNrl>~9b3a8!x4^)ADUF{Z9Sg%m|ax0^ZwIR-r)QwU4Axdk#pdwzg5o-g5@&t|?? zMUJg2l0nA-hcpi2(jL^)F<*LSldrz?8t=dV0T*Y-T%FgP9h?$o5!bKXVV;-dc|l!Q z;6V_fKpEFp#?WvLjPDWRIA>tz%wo*`?H9QF+%vrJg%|l3fA}4SRf&qb?KQbIBw9dJdE4!R zTSFj0k1r^Ohu+~2u-an7m}Fxgq7+>$(7Hki%jQOx%i)>RdTeb!w3%*iyTTyClrA8W zO^cz18)X}S!hLT%n6dWAi^P1a_Jb`$fJCvK%i4Yq7>BN#}H=&zWT*tFBk>!Jk{-!41`!v8t>TzPT0=RVQO$)$WF3+?B$1YjlOc;z5QQO|gNWC^d&JsW zkF|{fPi9vuPW^I@VWBEY5D}@YOR@H&9K&z4LYu)`fBju=lg1= zW9iV_B^iDtU($f|D;QgwEoq$oHgK^G^0qv-6rT9lY$7X&d|exYwGE6h=+PCjtXw8! zXAc{uE%$3#__%To)=*ttQBNlj#l-8I5QRQ4^ViYrpZ;@KFTz)@1E4F-{9=TuHJz;u zq9pX2c!Lny22pTa2)RTDtyng0Ypo4)6|-FP$hgp>%86)U^i?1yxl$8PoZk;`E4YXAhBN)KaYw z$lV89W68^kd0rERF`dmdR2oxVdQ=f1mMW#y7w53cvKtSNPX|Ip@5HU?8Dev3ct`qRkt;db7(5&)ndzUw;c@ zUF|-`^4b0S)T1Xnxc|VR#m)Ni=O~1vs%xS!z#2_aRv2TcwLxpwoD&~-I|ta=^tyKH zO!q#0z+mHTY?(7JYO%fTx|xs0bFyBSk3KnQmqV096pP#e2h*u@+;{gVRgAVS^W1U( z1TAMqMG+!&Wcg-!Eti_hX6RzU*Pp#@|D%8JTjJrtOLovn#UK9bKjPh={D{51J$~ok z`5hkI|BQpf1N&Fs{l0kk_^4f?);f_3Z7ujRRViFfyxZ-vxw*|^F{3|NqbMt`E-w*& zFIP&UaT2yzOB^Qz>l?&r<}yryB26<+j*dvv3@H`Y_qX{E|AT+b#c+sBG+6{wLV*g< z)&WJX8p6$`EQ<-06P75enotSM^n(22%$HvKOj3}LZe2$tnd=}P22e>J9h@SooXS|F z5}rfmZMu+-2ydP2e3Hb}g+kW~DXlBh%RNWaOENbLy8%8wKXhY5RQFFZypA|IP3I`usmVzyCiSpIrXo)qFa>)WPf*Z})%q z)fcY+=lxE&-lUF&bfsC26zJvMj6ntgPd3-Y@bDf{XG_GLb)TqC#k zqndzZsqWAcXYKOyS2rLFE->>5sjE?L&?r|9F}oZQb-F~o)Gc!SMr@3);dhQrAf=NL z6~^JxKD{l1knZ+2K_H+m0ZW=jnEn8BCVlCKLtUdV8?@n8Jczelf|are$Gwzs!A zpDTzG&KB^OZy%7xJ^Hs^0t98Hv1xz^Bnp@r!C!pmJuP%s`pq^KlARyS-^zxLpz3{dK$*<)GId9IXC6CGg5z41F zRlm)7p#b5X58A-1DNk7qxM+d~A-G!9-WUX&PD_+bxNK{Z7n$4!u4O z1#kd_^b(o6HV73Wl8kDcqddwlq@vaq6~s;yBT`@tv*Tk#6ccrO$Zj9wZIbl{%9$bQ z_%FgjRU?~biXMp-7V4r#TGxBP**>pI*EpNtJE1pr(>TJdFN@JD^Q$RMZSI=!XtF_& z?d*`Bow7JRCfnUcq+K+wPsrlzl-cPqot=GDl(ZetrCS8wF+hf}%6hOT!` z&3rzisvY^?HAEJaMUJtCvdBr3h+=xddM{&I3v9Ju(A%RVK$wtH>(;(SaY!c#i2^|w z1zZfrnCXaoc;f7abUYRtW~93}uuE>?dOf>E(w9aaYL-dH?kB6>*VpJ4E!Evu=vUsUAOkt;Ufwu zLzI$aSxTC9SQG_m9P~Dm_-7?pKg~n9biZL+V`x@RRHv}x;X^eQqaiigph_>6h@Yd9N zL;(RpDP$D6U~7etEU+k`C@QM5CP^cdaQ#h;0j!e>)dEx~iDZnvJi(ed^U0WMIz*3- zQKo>zIVV+BQk4~SHW~L`Tnh7uWloe)6&1Otg6Z zwk43-I(JU{nt8VgD>=v7!p;^(9G{Q5C(iA&uk5pR^M-hEHf5pV?7@httSJ^b1Od`m zY!H#`U8guXWO{G}K|sD1FsUj&yY~q<*OfTGnlQaQWnKro^U0AIUVKQmlk&A!U*O{6 zg7N5r-Q69AR|Tdnh$LJbo$$T;bHXHMyNrp1<^9uBE~Ys*pMQqS0xl*cQZ4n)mt2ho zO?Qn6-JW1ubt;E~DT{G0Bv*`Nc$lgq6Oc$@jVS~9d+LPYa>+c>8F{a$-sG_+s; zTC*nFpnN4re~N$dx%JeZ$LjSOLoEf-`Z^_odUQ!pRph6R7#l<#>e{dv&oNa^w$>%e zVt;PZp_0bg2Wy?8TpT(lt*rIaDkBf!^ZxwY6_ z<4R!FTpQ5#G_lsH7cK9tcjN%+OKQMU)iptqA(cW~Cv%O*A1oGO+_A&WZA_@BN0-E* zlOvT%VN^uAyG>cw6c?8SVL)A0)E5_IQ3P??BAM1&R20zL8X%QmG0m|>NhB&%;CdJ} z-1}m_Kp0KfJVPI~S>ILJ@ey2LBZY7!wAM9~Gse2oF}1X{&3~W6Y|uiIZ12L^3G-t| zKv!uOZ4~j=F8TQhle1GgyZgu>a&WxQKxu6mq#<{9yS#UQ$fMIKU%I`(BFNKl}h`4ZWm8mZpSZ z09qj97*k8mujYL8$nfg(*ZBLdJ;S|sUgxo@xVtyt_RS7QW5HX8XOvbsWj|j+R7@{9 zd6;u`aptex*?hFc_&q0-5-9_Oumsvr*AnG<0b1)eTk347@TG5VLS9~t#QPt7#Od)d z2P4g&fA4)3Buq#dJ)WVnHH4UBi#c@#)>gz(L|zt1si+q@v*SbJ?LCx?JptOG=s}b1 z#APX(Mtq<>pUJkFPZ7ktd;duM!JmDH58r*0_uhS*$Bz$qa(F_o*Wr6Ve208KBiCSM zM6W+UNtgXG+7Kr(QRLL|jL!rC%;&RKJYzDxB3~@rdvHN`%RvbOI^8bg@q}(CC5jWO zV!`O@lCmt3LXsCbc~Mb`gn#qaCtSOJi^;s;;%ZLPk*Fx3o)#3-ak4 z<|7tY=U&jl0S6{b=HJY^W0FjMpLZpO;3X;vVGnGN(PRz z>C4_*aLX%aS*x8-Vs+biliFfTMP1ic8!b#-V{~O}T~n1M#bSoFRtOdOxi1kaaMuGw zam2=;2WUb`RteeVr*Ql%0Qoz{@BjV}!|(j~|J)fL4borvx!33qHqb^RtmW$J0!&4k zb;+v=YYd%EVh@Ie`198vQFDe7AzB2~NLQL5+yvaa`#k-v9dT5Q9YNd^%!ANv_EO5F zw5Js=-1p8G4ab8Ow6}T9kL6~`Q@_)7gM_+;>o$RAxmvXFy+p*a7E^28rih!-IMK^v zyUp4f*ZI^rKJK5<4jmIwK)SKkTuQqgw9Z~tQY~Bu*-jQxDT%QTiEt=`Ga^-)^VQpZ ze)l(jm3xm)IXyXHG8*&oTi@m6(Z>W)=9zjk}b6L0)Jo6%quJd0DW9=DF(w zs#?>1^*Z|-9oE;n92}f56cS{BN&-4N+sG`%pb^?II~`)Gn$GSvB8)L*)iU`{jxYGy zmv^|^U2tJDapT&Wr5f3~xB!H8hPW-r2P{%rbA9WY*jrO#GpR)s&w1t68lT;N!o~Rn z8DuCSo$6E=(FCGaNaEdns_B$sJV8kaqJ)3`XK(Q*-}}%tjLR2D0m05I3O`H4MX}GvfY$EL-QZgGHGW!ctbvr<3nCv7vso1kMgkZwjkT~HMjQ4$k( z9AUk!-CxO${B0S+&lBI<;ASY+N>I{PY3 zspFJIo+E;gFw5MU$H~ApDF5frqqz^#ck?z)W+d=eVLul{3E_ec(PD2;^LAK*3`=NX z2|hIU$o=e}2g`e)LPZdVh`c0W5!Gx) zv>u^#<1D$qjY8*?o{w@01E-^cK|euBcziNpb1miz*ZW*sOOQYuDU7bTJ+S=x*YDau zPsL~NpR=*K!QEG0< zpS;8QaL85NVUb)XO1l(i69SRD`z$kTvgPE`g$szKk_ch3we?__CC_t|6x6;GcF?RX zr4YU}Dh#}0l6IUqYc)GNyX@V#!}`5b&SsY!9iBsP8?}9dLIwm%5Y{ELqeJX$iY;p= zTbqRBh2z$kZDR|ApYV=Rs?6jCGA?mFpPp{U9H( zc)-(W(}D{?OYpbgfv8nWA|(nkAyh8Q5=DufFBT$- zL%OOU4QrCk+az)Pw6x<-$@p0S@^_4X@=soqzxO-;G(8MKSX_ zU@;rnZf~8e>+r)U3K^Gyef`r)Ou{t?5=0QY=5#prl#+s9xznN77s#WT<41_4GQw)+ zL3s4iddEbp1SYEv8I2>>MD5TTiN^5?By_XblfvD?wGCVdSX}wRY*ACxE^R9X6lF~q zx+YS_xN``DrSg$O30(PtX?AljfVj+^c;~A@6B~yRsB6PUC*(K2{spc^b3S@>#j7vw zvYuY&M;{(@FfJSD+1G1VeBs76|M*+4a(*%5>f)T^vmyWe>AM`<*TgHv$06`w<1SG@ zMFfIC36vFddl8cgK7Dk_x4wCoonFG_WWn|8o1E7nM#XN^5*Cd`)P}{`1*WR$Zf_%k z$e|@3aWNKjt=Z~IP9EQ*8w=a*#I{@nb~Y-k_0gTROO+sjwo)3iwwp?!GC7*$eERSa z&%StJRXG(0_aBnn`l8dk?*PtLHP|qq zv%Q6=YnKgF(i4$gPZjGOyLNpw`+s}x?v+3|Bv9Li)VW-H!k>3TKyQ?|lvn!Ez98NT z<+)gmC)PZaX8rgw2fMnO{cFNIl@@GWlV4t9;|!5?y*%gg7_FB(^UOj303ZNKL_t&! zR7Ri%8(1sQ+7J!a5Q$T4lF~Wt`S9Ek*wYN+WchqnTnX2I!12%GG)7hn>U@F_%M4oF z$&j|9o?Us)i=VTiksfx=b0a#?-rFFc_IAn*pS}5YJ9gL97&MxQ$ zp;N1q0YRKBgPhiTbI#JmBqz^n{?RW#%a1=jqs%L|`YD|xpx24m?4|tmCl3*I$qP3I z*sZP%4MOR0*QwO-6lKjNMjig0Bv zk|2ptb=j5?BebuNcdePMHF$CNc5kyj_-eYMV{6R(ih4Sv%nQn*B8Xx{wP3FUve)%C zGb7sWAg5OdW2owyFbX-kn6tCiVUUKr{o!LeK}``_YAsk>%Q!h7v)+x_S?loN;F7Y? zNa;$Fr2sRZQj9LB11E*6f|Sw-uC7ig7gIv1Df1b+$_b+wp&Xf>AaG4@tC}EC4A$0I zr)$8%%)5xszX6+ZZ0F$zs7wvf(-AVXK}AZu3+>{aK&z^Q9#;Q&@^ zELvAI*1QoL!P52(YJikxJv!wmfwm3jV?Cv4M$SETT zXrvyMu=Khaa^WI>ZH0HxSI}O&RI9SSoC0Vap|(S`f3L1;%K4liNeSc7`x3$jFP6G0 zdFjpuFYRX>9-m>#0!dAhWLT*%LQ#o`?acvC&S%^|nUSV3m!k#SgOsAugn?kQpKv)X zxtJ6!YS^F5UTT4M#yz=Z8M<*km`QkoAG>0Bn^9W3WsdVYmjax4UbFc6fJ z3DeV4g6@EHdz-qdnI4}J#wqFUHX2uA(FDXxgxw#=&jW`{$z|ZT;?TEla}!Lg?h-8h z-X^G6S%2>M%c)LVUbqr00ImFP+=)?9KoA9O%3ZD;v(1)#Zl{t`w2D>9TEr*h!7w}BVD^%@@QR|!wTroC}pxr%d)WMpXbgYMkJcrK(dKw`tah4FIiR-=NC#Gqt z`8@B>Y74@6{fyQ?qlF;b*hH5nl=C@ZlwfHPTG7gbHbY8DUDqtinyqex)XwINXC-xQ zh$F@E#hf6FNV1eC!#SNm@ceF{zr4!%r~mB#;ki54c=gLK^5%P=@Z?Y5A?ok)8((^n zduNuSHbg2w1~s7qV?t(m&EqEr+}dB~`d6Oi$-~b$U7WIi>m{yTf6j)TzL@0|Vb-O) zv4O1?ET%K=KRQNP!)Tg20K?m3tu>{Wc6Fs|j+m=_nO>uCXtbuy10^o>f(aK z;n*g}6EQ0R5ipz2dG)!QeBla^UKACWS ze8RP@gcn}i;|Cucu+h!<>I++ZcQNCOch|YO-9wm~5AL5k)ZQv6bBfC$StKx4Gd(%w zH-F`e{MxsEp4b1)_Xz7Lj~;%;2XEJ`Z*1_jZ~h{qSu#(wy>KhU|VFvGsqmAW!IAqWt5JnMYm6I=K%x7~~ zvLysr)ev$w2|M)hC9~=_+z?~o_4^l^nx0(uzE*7o;&1W5K z;8i7)4%T-Ici@Yc3o%W9Ces3rE@h-V0B1pju5qn&K~e)i2rNoij4*Cbt=u}7ZBL@5 zscACc4baq#MrF$SJ|YgJvVdu{a2m_teJ#JEG+FW$zKO7KbbQE%_Z~2(PquU2uC4W% zPp9JI;Ug|j4^YCgv%AB!>o-s;=I%4ku(7@&5Ry(eqpl4_XjV+5@_&`@wRRyL-(6_a=)JEGljAUL`0+Ig>jPIvm{44*moQ@_-DB3z?pZZ(|=kE7S z>4Gr`soF)^yw)1<2E7%I$5BpZAQWK|Eu9W)Tcw*$tSCoAI^zSIsY*QhFYHuGK%@${WCuL zy+20RhEAtL+U*kD{(1Jgx0zoJ$+|suk}msqo@ZEu=;;;IB{m4!0B$_DeEOj#3?v_X zc1Eugv$fXYqbHY+-|o-X0Of3ssV&`|ZA28ItD35;(7Gn-Sfaoga_!wCiw`!#3{;3+ z(F_#AwW@ByOlzzaLLe0==_Wy48=@rU>#sfoQt;X771Kq&bAl)$+1Wwk)MT3D zHPf^yhilZ7mZdt&K%O1Er0xf*?Y4e+mh_O?-vn!I&;pMcOL5As#{}sHM`k^*d&{j zIBEb4NHzh&HekT^gWZlhXl2UL8z%5&o*08^W@%^sfAM^3}{=$MHg7GvTs4NxrkQPHf#x~8rQd_$O@E{#4_;!O4gsT zR=adhix7qc5IH1)Cd3HQvwG%U(Wa!c`PYXgR(ZZ#_%+i9ZTWxff^5BzCc=Oep zq}SGYcK=;|^7dOKNzBW4UL*^8JnNrxI(7TUY&J)gIgLh0qnU7?8b17Vz^gYe@*6+* z8vn;Xea2%u<7aMd@#QyPV5UR<^vQ&ob|4~~78qlA`NlTC_~jS)!`U<5|M0{`JFIo& zl5civtfAD-!YQd-DxA>>tH{d|DV*AxwN6@C>qS&(Yo*B-Zme+c@jfz62&Ewk;L}G> z>^tB4p19C1`I*=6kj~GTKAJI&8tfjOvw8I;zWB;b{^|GMV9z(2Q__o4Sh}lglzGAQ^pFd^kYE17W&6tZH@S3STm1gF zzhf`0#^Ux1*ZJl*e}N}YpRu>Q&F_8tk9hFt(>hB)U@5bdZnx*;oy(H>Jay68vS2hi zM=FJq0bvvnNJ%9j9L9ZG&I_7-Q))LRQ*M z1}B!&Y)v-0O2CZr4h{1+;vp1?15JwtAURvCEPyZ zYhG=2KTExhtf*~6McO*C15a7{G_P8~!khi`(S%PPe9GB4BW|=rUxgeV?DF{G15O9W zY_9kC$`}6uufBSlcB^A=+_)}QS5}4F^E6s(vb+#wSpu62a*QQgZ45>i7;9{r#sVQk zp3a!f!Prn#@7DMTO`2z-$crVW?61%9IRN=f4xyCkACJuU-+GVJ%N>j^gtdku0Lef$ zzb`0?93d20UQk-a!C6XY{Q_@ZxQz{>Iz(^%B9T%ONLX8Ga`5n%mmyyvfg)oGh7dWO(|Kylro>3N+!{!X*+`=Cpj~sI)D=EDr zWS|I?svChJ14J0pSnoj?QfjB_l&o~I#^u6SjviK{g21-BDDuKs2T#IW=|!sYvyS~DMxFZ8sGEr2mollRx?+e&uid5`XjO-efS153Q`Wlro3bc@!qs|M*EAX*i7N{y<`M*|cFvlp^!1k+5Bdy_kC~McS%zG>b&Wz>5CNC3UM36_ zSZF07=O;sA52!<>xVp2-D9!!46RweO6rqw9hX;oafGUA81;f*0vHR(L-u>~9`2P35 zFYe#FOaJKu_Mbf9_~?k?`I!BKvjv;)?MR_DK^VH8Cm2K=5(J7M3`mlM(pZW-C(jD9 zyday;>wOgK`gE+WtS(rOi^S^W;^`5AH2h>FW<4&7;$iP zhH7+Bam$etDuyUQMhP(`*<^$8Q0(tL;cRfiJe_gn;!C{v;%$GvQWQmQ%Tl|g zZ!~35_>2xiSsJwVJIL}L27nf2kqd2%Fc!3N>TRY6&G9(^ z`Ad!{3ON{J|Cir=kI1^zBiE$QpG&bCxMyZ$>0hh!U{gOL%ZFrnC^&PQ`-FUP#?l zjE3=kq(vD=NX)Z>>G^~>2??TrhSE$=4*1}m6VApn_D*v)w>NouK6U9Do&l{04PymD zg#;=>MX}q&jt@CHJRw3Rs?vkR~a=-Rm5K@Y6$NkF3Y?E zMqs6LJ{Q{Z0u_he8F9MrRYB=IH)4H#owL0k+rwvuP(spd3PFGnxi_q#v^KyZgj50Z z*_e~V6MO&ThoarR#mefcIQ{4V+t}cXw>DW@X>xcvW~H5Q_h`sLsCcEfkR=f>HmNAP8w}Y%m_rDCRkFr$v;+b^dVGJg$nW z)nmRCA%I2Uc_pt{G0ZivSa$4%cs`ou=lsG^boZ~~2w@gc68G!p2_w7olRA=Etr74j zVBz%J>Ri=xR8H~oyYycd?D+zSm>NR(&r6B04)CaU7uoLAK%mN+tjB5j8@mJy7LWcM zz*@Xl?KXC~eDBqLx;b2L+_riy{}58t1)fS;vg2dyJSFgHKsql71(bf*mI_RkqNg*2 zH3(s_^Eu^w?!b&Lh~p5-0wWbkr;TbhDXO|MKTm20O}Y1ubk0dFqOo*~21_=}D6@jN zX(WVj-R{e(!E4>CL-=mrww~9nO_QvzZI{Q@)6JFXIh$nU^BD-}G$Sr=bZ8|3 ztt8;WYLoPGkK31feDE+MY;`y~KI5PLo43S;)dnXsNo(g0gS^Ri|MaIEk1{UY{sJqT z*BA|kB&`N37dAQDKcbvY$Y(QNxY*_Npv&+5@FAVnCZbnzm_{6a(5JPs!WXWtKz2Y` zl&-6{N;sZEAuh17wa#qXCz8(js`^1hVMtNt7%d5WuMLc()DR#k2z*y;r&5>Y1-Lo| zw~usha2(x0wAWDN%#RN#v}J2&OB`lH9)0vN|L}kNmxPTrSzaQd7VXQo8H*<4-0%zE ze2tTnF+Y0m5o;?go=8Ef8L`n#c>nG*0xXxWZ1K*$g9VVc&cTgV*U*i`6@hm;y#4W~ z1pgvqe}A73Kf24&!5;J3n7g0$`O~*Qc1`)DLWUuYrfX^_rDQ&zlVwokIVuQ=qp0o! zW{jmMN*b*eHjrdRK%?Dtb61z-c}AXPs30H;BPOFEAdyOvG!mjfk*6-bNozx?I*i0R z4+e(ePd*lh#{&+>mT2ROl`0lmN>rR6gTzH>#wRX9XC;D&WNio4>^gtKJLsYkys74_ zgz+?|3xa=c~bC|N)RNa^-qsT8s*Dz~PN2m_1k z3BQH}UNNn*Z=SHN%(Yx5NGdyD1Arx|8&Q36Yg=ng5QHeDob)!%u1lr3a`^(CPMb-Z zd$TEp1BmXq-8vVpM@jV_mXXfFVuLlcrLSbk>p$@k6+{U_7#ph30m$da^M_D@)IluA zx(UG=vbBN{5@Edrp?6fJFQz-x(7!uybF9iMX9>yU*QDQhj9MsE)Ts!S^I)irb;a=g zg()kQx8WU(nyFI?y!2rskZf&j@dqD16Hh)Fv9r=*=km+qhfn$pr&F#CkL+*#y*px_ zYc6he*xv5ZA53_5GGQ{yIUT3;hjaR8sV8a{8+>(b>o;X>O!jyD0F$uv)u!0Wg>p< z*I%&j-P`4OlwyN`liee%3K@DJ5$l5~#&I z6u8utY&u651#z>1io-=Mg`bNM6mDcsqFtbc$k z3o0oIAr;ML!?oYY+}}oV=p3jlCou-6m2Vdh<0%w9n^BC;K?=g&3L;M2I`X#Bjf0>_ zbBbAt3<6XXENqPTBd`#L0YR?~!lg{vxl>aTxZ0P}N{n!l-^Q(EH*16k2i5}+V=z+s zbXb?3S>~29&xx9eca9g%kmDp&H6YIUwhO>31a%~(nk$vFwA@R!dJthPd8zry<1*875Mudv!IHQqwSh?{A^H9?2#ay}d zBE!tmSYKl_7$Smz?xjnN_xIS_8}hGy_XjSGjV6;UB2eCHj8qXHGg z7-L8}Ey6|%+e~=*);j%%?{n6F$~S-ROWeD6kL`>-{MkDJVIq0q z$_9V<-9O^N{WF?L!0TUrmBNNR9hUU;CTlX`;#!lBpA0yk%;+{lx{a8@*@PFa?@(kp zyHESP^1=>BrxQ-cnRg-$h=ubVL@`PVg2p=c_Rjh6cRoPq8QG-7>J>00rkGM@DMGl& zK;#K1SDOKyR)a7In5G#rP&DF*yl_soF@``1gwYsao=%ZjNT=InV{?l%O&Ok^qIFqE zKB6cf2qVU$bIPJbD1|At2jL;d=QExi`~*>^kgQ`G7YJ0077`<*4V4mMASg!1%ubHo z#0z4gwH;)$OX*ePWW^&bMO6hLlw@8Q(&-#i6rN-eAQVDYAkL@N8bPToc~M&7oEDeH ziv*PG`C_z>iYzY(ySylTG)TCOS%I_?gRVQeyV^Lp)JtkXcm+x=)mc@d5pLgi089D0 ztDK@N5CW&xR%$QC;r`y)LAQ9TD2r<{Y25wQc9-XD)6$lMt06^5VbS(8QJlpeRZlI; z^7BsUpC8X1AJPnziUKL;0z?=hgRpjgmUF9(kVwy+THi%eNQn%eSFS<;r6C(n5h@^T z#EZg47EYLyf^0e?8%-S(-ApQEQE!CHg<5W*2oPRgS1*`3shm7zBZQy1bAe>uryL!U zpFW`%lw7)biJ1+BwH^Nc&%eUSaLNbwpYicWAMwt=eaLjQPwbVovZDiz^C6vUUqO^D zOrf2hcEkZgbH4}woYDZ?mauF9S2A$IUi@--04sn%i&;xnWfB+k7;z8BA(`@Nj>`)vY$G?Szk?o?$&$J35fguQr%hx2g~5Xe{WqFY_V2Z z+6wK`8gn;+l#ASlOCTCt*?79@7}po0*ZosaDtvq*e*n{001BWNkl0A;AuPTQV=*|@yHJ6spA8{h1S6=37$1f8UV<9}mkJ`RtL+e2gwY7A zU3ArhnIw$Sjo9}ySVYJSP6oM}e|C{H@5rLc#(R5gsYM2z<5tfTKYy){YFW$CdFJi6 zlat*&ofAsP&*w~I#q9Wq-+%j0K<8|%gxuI!U@sqs*epIcLKO zPj>svvz)K}?3)DT5Ig>qIO+0*?JY+60g+xo0L?g{)P{7PG8#`Pik#`ZV3KBJX^Jg! zLMaGMiLKI=ty>qx_?-D@L?9swEtl8YTz>T$j~_l{be@n+hMbT0P_|(E(nV*(=Myg_ z?)FzD9q`h+WS(W{SxKrCaifJ0l5{rX=%|lGGEHaXdB*1EHqB;2I-6mE?#e2sgANldZOM>to0Vr+y07tlERa%Ui8LTm%8TGq609s1aIYw;P(44 ziV1=kYzhdZ3JAgwC0xzalTRNrIX$4!Td!?LO+cu?r;X}5f@zJdeFUK^OJ=Fs#ES}< zSnJl@a;dpj3=0BDGb%&=8XlhmkiXbxkKPey$8 zTEpJy+!Wvb_9MRg?eFrHFMpZe`h}lI$E)J;IOS|=xqfktUNgRc7a(|@W!Qt-IrGQhlBgP z^@AhgxDxwUXd}te6pS-g;Fx$K=&jM2z2@C+&xy1--^>2OTkYN0x9PLb?A%~%U3v>%TcMk~lh0}vG2r861f zzPg~9(@|e(guHRJOI8|8skyS%#%j&`_Ye8n%bQH+IsfkTgx!OEy1fpKl`h$A#`Nfv zKm{~6*Dyk$b&2bw?!xLu8@kPiJC}QuWl1ZP91TWXy1K&oDB{+|9(%)#gOe$NQVV)V z2%>g^2m@3cRf~ms$Pm~vcZ?d=h2+CU+M-Yn2nhj!T*%7SGDo#j?+Xu?A_xn%{P{w7 zQD0gt)}`MR>h9-D>%Q8YMZNKT=KL&gnErS5s(qdus5f$-dQ`n5TP^tNyw&G~c&@JI zvqufIYT9k_n_6(7ioCF3=Z&?XjgPpxYlfW;s@<;H#4wPU+1NEy)CE?TuGh`d6B?~a z8V!OVAj@)!vLxyBC^h7>DdGAGrBLX6PBEE6pol_=FplB30&HF&jK&7C-rR+MA4xOD z5GrsxqHox|@+x)Zt z>s@~E^v~$F5{4(Gc|lRvaz{AX`#_<@!-<|ajQX@ zukh3NK4EL?3Y#s&@BGQT_Wu4p%M@ zCr5qme*8Z79`CyXa5T~ivZBO_geZwo12u{ zP-??$Hs$<$NReku#^-gBye_q01C}U?Sy_?Xym5{H__u$X!;=%jMu!Ja4#M$Y>5m4Tm(jf zFesxa5eVtPl}kypJ|({dqo7ns2~ui|wBY*>E!%!;1xgCLzS8;kSp2`*$L9d#FFA^= zP}+vF+T5#@4YxN55EkXb@ZdDB{hD&eQpBSEUP97pEWDMaqwcpMoT5(-*6zwgN zxJ9QK(`&{|<|W^Fb%z%&^?0&BB#9NxP;g;2;e$^NR*Twk(ZUk=`&Pa=l@NHK<=BVQ z^D%peCmavXc<-n0b9~h2d~o2H+FA+7>F|d^0GUSOm|~?|F09biy7i8wu?Pi53xduH zu@KCU4lx#z&25@n7nvUQnH?X~*xDv5HItJwR27sGyQg## zg)xdi%ICVHTWblEm@tVK4jfg{pl}^_2M2WQlu!vWkuVLrtZi=+28z@3l=W7G0j6_Z zM=0>?NcdU{*T=>@2l#=7M66#=bxidzK8LYR zmB`FzWJiZYro`xyGA~@Ts(LQ#3WlRNrYLfXbcT##%Az1EG%`%kD5TM(CnqqUQz(~s z2q40cywD`A7AlIp9o6-FH@NvH{XJD1wWX35uE6A?u0smpny!hegK-4{sK=xpouvo` zLb^`umBS^L!KAJHq1vWa@5R!d7n7+#Qu7}Oq1rV+r5P!AG_DQA41_P4m zA$XKIQ{^!0D$S(GCjM+ieQ1FgEg?nGM};cj;^}naxNKAJSG4J2!6AP8u{e zSJ@4^^!o#h>5;6hk_*Ak_6iT~J|Lfu>4cW?!6!@y1NQEYNQXP@9ZmT9H^0FzeEl{> zS)xmgGIL&j@iLDeJ>#SOQ&A*W>E|7uP3I^KH@CL9d;f&H{avym=J?|QWf5@t&LOjD zN}1;yQ*?>2$t#Le06yL3AZu5EWv`5DKZgoY>1gme*=Je$*OBt%h* zcDsed&_6t?*I^RJL~)Fe(xtlQIe9vxnQTEAfG8FbT;l{?T(d`Klggr~8@q;4#HCA@ z>9s-v6Jw$#wwNPDj4~zpZ=l`b}o3@D)*o?7R~t zL>(ddtmA@5_0=Y5t>s&<@9^TK9^d<5pASDB*0QPPh1Xj58#Fp&esY9e7sQvZ z^XNPmX*TDu^9JI@S12#7aL~4;QjioFy=92+J zZ8DwZq_Y{!#w6V?LE?($bWt)N&yZn2qnRL-p){acD@2=u`AHukCCT~*jg2j4g8?F+ zqhyE(l#470?_Bz45k9mm1;mZW+hOmFE;*-I=PWe3ZLEbL@;UE5I$}Lb)r=ZkyRb?S z2+F)b7a0;K&leN{!A_faeVf7DMHXJXvcip>F1rU!!X)OUYnwbhnWA;cjhz*K{BXdB zPtJ$}Sy^F(bp?sj(FB{Pl#?^!Y(}C&x^_ln70POCthw033NsX@n6S}w$R1uveRBo)zSi8DS$K>9*<*3yDiFu#59m!Y12+Y!Ts_yZ%ZCQS9;Zm+Ji_a~;k17So1yq;P zIQ`!Q%0fC}etbk^3UpDRiySEwLV7!8jc>{oQ|1NPEG38{tPId)Nz!Z(_STS*lfG6( zM%0MWW#JmNDMe`ot*ve1RziAyickubG@UHy()0cK5v{KHgrI5Zk zt3g=3urrGg%+g%;^I>+*mu_wFo8S5}QibSz#^iiREWgG7`+x5{M@_l97Go{3&v~yv zjMkcNr^Da=#b4%yJFju!@)cgYbp?s#zxkj41?RIC(`iPt8Pn)>nPi$yx5HQ7yu@k) z<_ACJ?CBoYHg59r?M*&O6uKEe>Ug5RJ{A)r`&(EM>fy- z;kyrOfNHap+2D|5^P=m6GhgB0=nNT1!qzJNvy_h?Jmt~d_ryovcIgK0*coNzx$Ci|5jkDiC7uMau}X`J6eHz5XG;|Ghus*7eK8k!CtRCl8xU%$V8a z9BTz-*d$!rA!v799R{M#jHuMu9B7tQlDKum+BzE=_%vE8s2dIo;beDFE)}?n?BL80 zS*bClD_l25iag7?bA6p|yJ4-h!ZjwW)Fwr3nwOURbCy8*eWfyRRZ43e{h%V3aD>v5 z>Vs46blf)Z)oM@dMcfH(>XqR5dK z!qRCbG#d%+R$_%zB8VC!ae&c2>LM(mQpBN)x&%Q$7)Gd2Ayq^a1oT#Vqgr4ErvQvb6)D#?o9qozPR5xlumYdMF4*2^&`d&qK8q|0(xzo?bA{Vi z*LmT}8nY6v?w@mXGUfK=9+x&+SOmjK%G*DALKsI((}GqKGB}&k>o!P|kXQ*eR+@bH zbcmI%K-*dtsSZ92X{*k0fHVecH9|?A%|o7iFu|Gt(YQj{&Je?0tewwbc&46 zxOL|?7hc+-(`s@9t#ca9uFzqJwYK5fr8V9yXWZCm^59{gyO*)yA=5wO;O)_ox>BB>Y=M%yt!5YiQj}Ad+92}k?R7_xV zidpX1vR2}pZ(pdcqJU{`D78fjOCSvSbVw`8dE?qD7q`~<@!N0n+LZ>A(Tu14Q@-}* z4J4Y2D+#?uz%VWAh=W@fOOb#jU}$QVS@;dj|6RrSLmjcRfG#w}JVypj1xbpkpqP3c zR&1MCE~0lc!8I8364ODTp6?gp@3YJb($UP_cc)31M785z0f%aHtx^GNx7$DSbJsPd zmZz+G%v$4(IF7?3G<^qq1BkO#1v&6@vGKE5C=q2NLl2hX^IL% zj8dpLrrl{XJ0Fpqo{$tNdNLufnj&*~){#e?XbKy!U8z1Jzln!9qwCUS%K@dfb}X%1)X+}U;O$P>=)j6O*9)VI;|$!3ObP> zY{azUn91=mtym(JpePCso;>7Cq@0~k(Ls;Vc*bNr0V^m=O)C!h^jRNWXo67Dh(p4l z!_n!8H||_!o|oLdagljpcycrb5n#~n{*X*(bBq<}()Dh!BJiY*@=9b96C~U{E&2H5 z3=t?o8T065&ZIb@5%*idFIj%OK< z4(6`+Wy|lMcb^4q3)ZJ6RkqJo4M^?cdt(KXMg2!5EKv)|R92&Uca_cb z_PZy znC6Bc2)wbX=*GoclfIz022fV`Txfxco1jZAi(VQAM|^z64hLrhOhvRmw*0X)EW}7qC}_%tBCRrE6Sh1)=OQo6LCf z$w&PBopp9Lx;(!3R3zo2{`_ka2+&mNXsf2B#1kBP)46Rju}taTEy!tlwxJvLUF zjMI{RUu)s6ZBYWsbWAfp&SHJVSeDJ|f2&CZrpv{+FxWLc;{l8&v-hN5Ed-s6<>7V{Fk(6xRx`fEa z1k+Q@q=d2rLe`3mAN|ooGA#&%rq^w;v$aaEp-Honuo;o&n$Fr9hiS4-$!gBxqT}akZVZ_x-TO?t~4}bcE7jJHJdA-5elOZAusJP?WG50^I#>HsE ze42uGsy#AP&!;0*;KO^jVG@Gq5=Ma=N0uDLC8xf2@RtFGbz1)E={Z6Qnj34V@H6M} z5zk7VSE}m1S)9lJ+b*4VIn7FVG+d{*!NR8ae^P{6|A_zi79LJPp!F-ycq8K9;GD+xctTH`4$KI6T<3j~`6Mqx*L`Iyqv$e?mG>iQou z8%>oAFAxMlz>r+S_0l%4+`f)d3i2u1_7LqJBAqiGozrP0nAJ5tczQ;e z=9r6L<@TL5#`%!94lB?IR(OPLz(wi4FjnDI2jq?zlZVhlC(7CxecMTP+i2Tp{Nq}p)rU`h}y>V9OP z7|ksw=jY^;89FcMZf`inGP7XBjZ`ETE;E+`F*^q|)@YQHltw#g{MnGq7#i!Fm@+4w z%#hY#(t?i$1M=w^r9~ZVw8SM9P@h_ii%ADG?UFKz)02 zol;u{g8{R_fV07XmDM%OY{uE?z(*it9dWHDNfZW@K1w0-oXKd&lV{I3I-4U1xOD3d zL7Fo?JNEr;Lc-oAL3_ogt5VBUKTmYHd2F-+B^NcOwcrZa(lstMQn`Ik_=pHDr5s(j zI#}FT20=urL8=59#0X>f${5ayz$Cab`Ou44WKME{evObuBLqB&8s}=j~Gre z4o|0?k1{sbyX*~Sq*+x5%@ppdXm)PBX%3*)c-nxB96b9}++~?`;5mIPgdFeVYT-_p{O*k2x^4jaK zb8tH2U;o)h98WcNI>XG)C=MvP^A)upL5I347-1w001BWNklB$iR*0HNb6Gnjp+@|(ziJ}l)YSQVHAc(M1A(94- zl^&C`A^BuNs3f{92$ZDE=U@#<95YL&BaUcw-V*SDbE zVRu+?`_eY8UXLgaxvElN{+bg+o?Fz5nx=Me4pQlGBT-fOH#n*0=PRD%u_$gr& z@zRYgUc9o-alg+`KK_IoH?M;X_#0oi%49O*-4AALZLYGuvBr}zy!XjI#p$sVbrueU z>7wM)g@{{MRyjDGv41jUd$q~oFvS|UwX?#*gArFYn%ub1<-;dK2BVB9iU?MH^inO8 z1XZn>LCAn;V~6Zuj>;wkfr~6CX)s+S<;|Ba@N-}O8u#wrr5h`b z4)^%!k0&U(&h_gzn2paEPbXyaIa!|7JRHDyJYje~q9_Wibv-^R(TK7rDZ|*?4o5Q1 z^NfT3fuDPhtv9$-W+9#2eV_MgIBkzr{~aju0{= z>24#Nt4?9i_y~uo1B45kumplZIE654!IqvI6*L+VW-`MFiwYEFsXMZB5S~b_@tMUKD=j`E>btpXZJcPQ zGtyXG6tUEr>gSF)ut*GfI_5_o-Bp3of59&FSO54Nfc$%pS9PnEjFr*`sgS~<6h-OP9E9s=n`;Z+=|xFGDahvqlk*8eN#bTg5QTn^wHV`= zfw{I68Ym44NuZn}R+*>a60xTp>S_FbsJ7WS9T$fBeVXeCZB1UVf8yw}VhI zqSuzh+jC25OY$7W4qytCKx`5xP{d9J_(l~eKI9V=q$(ev>`(<%s1S%NK&nD8HnH83 zY{`;ZYN@5$eYoyT_`&w0(ubI?>}Tlb~)NRq89Yn?SGpO9}S4x7dhK(665flo14rZCG=uL zoNAsS@MdP&>1z(6V@vfaj8~PX#HYsup2tk9hU*9%%QY1y&sklX<8S_rzs4J{UK8Wd zz^Zx`hY*5u8%z90zxmhM+uh-l+xKuBt2gg^K5LB@3-j|F4v!i2dIYl}t8K;3gA-F1 z32SY|t&cz9;K6M?>0&T^@SS@&!yY#3nA?29?{3&B%H&$M)@qyuJGbqa4QLl)1Cl5i76KF*T&?VN4FjsSNvS{!CecN=d?2 z9ki7YE<3fHbJpvxCv+||QNY5Oi4-N%-uKBd@y*$vmFrTQpDRGHs-g}ssbeCgMEXUf z%zWxvQ}cEbF`0nd=b|IU#;Qw$Wa?g&*P4pZO#Oi}f;WAx6b6!r(cuw}F}S`*I*!n3 zMirGTp5Jj@@?0|-46H(w^LvG+r-r+&b4NVotWlXb*A zcTIyvwinrso8-ejP*<6;U)W$6aI|M-*}w|6ml&icwM7uzxY?Rzvr*PLuW z7GHUIkL8xj^^50u_rph|=VrNo=OK?DK4NZhk?q|hE-Z!|@9!`?+{P?~92_3gKb+@u z5aSIFaM)pUKOkCo1su=P-UOI}z9>x2nfZW~mdAX}A&{EO8#BCfYm6ft-ncZ+v;7`X zoN;zOBu{g`(HWy$h0ukAtLP8g&1HKUjLwjbi@&%^w6}@O(<*nzQEox$5+q4PqtT{4 zH;YLIytvxpul$A2(fh)STs*hN4}S0--@d#|qt)i+YcDb!ba?pi5#Rdu_xb4d-O4$+ zySrP>QK=-J>mjAGHC{Z=MzDn4V_nZjIaV35l8!aPQmh;?DGDg8@sO2jSVbY?`T05C zdhG@NWlap75ju65YPpnQW z*VM_nT&=kGXnoiFr}u!S1lw{HKyv z3*b`?Vo{QR0AWLbLdYt~TKOJ+p@Q++`B`RK0k@uZ=nmr|@y$$V9>Ng1l7=tMN%vG7 z9vxBhU}JTO`MCvi;o>>r`!25T({2QKt`z-VpO&iQfN+&WnG|Jmq;Lp*$=O8<=yC(2 zIHxyAm~FT$)td-M;RilBg7w7)I?MUs^axkM@SReuk{cH0o4oYqYjlneI2pDu^Q#=k zV-AlTTIVk@w|*AoIp8Q#Z8+>DwqmfdUTC*oBg=AhK8XNGK&J`P7=lKNt!G>8Z9XAT zptHo7Jmt;TUlFgqe4RKNKWBV^eg0@XW_@*uU;4$L<;jz$)@#@8;)@4tA4eSQ@1hBC zYjr$VG932J&hCx~g8-!*v$cCjKSnfX+tlWk81C(HFi6ccrOfW`p16DOzIo%#&xwtV zHBMv0?d*s=>*5HB9(GVk!XLl=W#0MLJM;!4T$7UZ578#aBpGJ3jGOiuce*&OMcihS z(o=<~kjCUw*bUncJxU~E3a^xqvI^o`o6}U+m`?UIQ0d@T5lWsnc&x{*02l)Nn*Us0 z$#beJ)$>hw%;mN8rws-%QIx9yv#??irJ-DU|4MpL>pcE#f7J#u3W(z;Q|3fcnZRxiGfar0bE!G0KtlchAT5 z9LA#vH>l&+Tf}ip9!D0~I}UE(qQ?TQ6w-0XOx09XKS()UnFS^WS7}sDzO&M}g^?x- zu@6&5uBReRWg8c`Mi+n;ZE0S{Oi{3=#s#11FC%QuS=pnyxL5i2QuV5g&spU*TR=4{ z`(*lkOF$(RqShd&*U@Rp{=orzTQyW;iMdyPnJ59*XhM}jGC~_eq5{&>A!-!i*Fx&+ z>m;&{7-@v>Be2q?#u)M}C5vJl*FicSQaZ%KBX?k|1>J6s%PVc(dg(mxfAWw&`u{UBp?|bXp2SF{SYK+G7uOr)y)ALrIpVY*aki0}wyVXH z&0~haWh($uh(eSOHnBIhzIu0nZ|JxS!QsQN1A4w9PTsjcSzzTWFFBw+T`0$ zZt?yHA8`Bj1LkL%=>9fB=Vp8NKpY+JVe&FB%g!%Vr~*#B=GH^6jYcXvr}HeIL|=^o zBPQ#+Dr+Q(N~y2Bj>$8mkSM80)0DxW&y5@3PmA<68GrO*PQ0mnuMv|XP{1H*QruJS!JpeP&&rEx{cekj_ln2Xl1(vx+u z8WCk%OD1w3lXb_CQ&KKPA;MwlnG@$#p6A6do2TgyM#q!~v`n@tGYheU*-q@j!>%>g)|#hH-p-4mAPLteeIM!z@U z@T5<6X@M~Gxqfw-dv(KGuWaz$`$yaz4*7+v^ZY0O&d+do+~t$I_t0s~cfR$f-2V7O zTv76&1-|DIwi+Df0V-^eL(VQ;co6bo%hVUt24l*9}D0^m*Y>5G~xjjL*V+@iY zaM8(#=wyKJHE|kE%7nx6`Ja=gr3Bi=2}OTZuUmXpa;gQuEdk4?BOc}a{Gm|>Atw1- zQ}g(_J##YaD=;+u{d8ZH_o~jHx=wjzgPAfs#B&DJb9p5dAlF4@_o;gTjx^-s0r8PF zJ{->iggnpDCbPWw!WkeawEFW5*K;vSk-Gum$~yQVQrl|b`JjiChG;Obxguf6a4)t0+A;~*^yS)CQq4eA z#R$vGR0;37K`TLRb&b0_Pr3Vh?^#*#_6)Cm_Eq9I<>Q-o2$ccXV`Lnb&R-)+Qu?Eu zosmLIUC>D=V4J;fo@R`Xj_|?&XL%Wo2c$RaTxj3+cSLoop18^ z)_3UW7PFT>Lw^*rb^8O-qXy%F=6IN~+ljdM(I>)>wi(8P+WPC9jt@Aq(iHOzmy<_=e z&dxTs?%e0#@R;H02`Z0KA|;9n3JMc);&dzLh_&hzNJAVaXe}`)bZ%IhpXI{YC7y2WGwhFW z8$QG1eH_mv8iA5ZEG#dP=Q+`M0LI{X3IrlaGlAAd`ckVxNoVS{t)#UmRzhRIIL}3f zD}O*?L`^$)o-;V6oDZduP_6XBRFR=FpAb>Dvq7LSvTUnT9ZXo^1T$G@rVY(<9h1Tk zCn=-xSesmD1?Z5)vt+{Hgtb5=NtWy#b?^S*?t{~%cHr}4c>Kfw`Ij8I(P$*D@AGu8 z&$FEql4y)0G+Voeq`Bta;~gGu9+POn`=4xKq>B@Vc#a|~JkVwe@IbN9Jm>YCig?uHg^TON+T-5i10rgq_&k2L!^YJ)Tq#jHXSlmdveDo`r7ZZGFT8w-e|~(x z=FMA-W;L(8_$C_xy!YUc@cJ4-JLI%KW?{C@%U4!0QWA}ZeEi8%&aAI+X2IvooXZzq zJ;P|cz_~@2Zhye-557f~Cb+J$ITLwKnx;57IQ2G;fH)eW0UU}oQX7}ks5v(tGmVZ1vIYBxOwV8I6 zcqfa5HM^n73N(OS*t{@A`x@6R7e>mJ5TQXxMVjY4J+fY3M-_d9z+@103}Kd$4kL7~ zar_V?6`8hSV7vHPZ%!pmpIcg&>j;pNEYqZ!LHSMgV?#2E2%HRq!uM3=>6(rfm}yUu zeHjFhW*M3G8Mzy{jdOT;NUU?DPMKd^U}kQf+4)5?91cX9Yt!%d_{x{Rg5PL~R-<8t z{f@Z)!WGV~Ef}FZTJ2epYt6~w9!WGtYwK0gd5$SI<}eH~rZCACo+=tUJ3DgXZ5A1B5IqD-fqTxYsc`?Obf zdP6iYQM8)6cLkiFstGjNi=S8IGG!Y~-J=5RrF~X3m#Yj6`y>bZI6~lfer4FAOMqPz z`a)px@*W10=V)#4>kei-BpnVxXk?xul~sCDj=~EWq9iz?>eV zvy{BwLnD!XV3T?g#7RQb?cs$r!ghTMIFt?>D$8uTD@!0UvD$P+EfHd>ootxW=IoSS z)3RX;up)(Inu$F|#85_Jrmj3?V18<76+=-= zhhXhIvEz{(9J4c4j{v8%qH+bQE1HUmMjeD5DWv1QaL^&+ZHmNr@*nP4| z7=R(4Iz?1zR z*Urx3`!1h6>##f%aym{q>_n9jQqKJxjr4u|l?|f(ZNzv`?K!^hk)|;Uh1;6v(Mifb z_=69T!VpCvI-4cY8PT8vS&qR+Itot-99P<6d{g7a7`sN7z_yI$^@l?oY3Ep0h?m&9 zT?QRz)=-dEEevDx)Qm1@SEitL8cnWqyxDWavoG)@gU9cmBIE$VGx)~E48|mB#&Dcq zR8iDZnrgfoz*WjtDbMZp<~XvVGYKG0vWm)@YCEQdqma2m2*nGR)>)XXF;jC8Qn9_g z&)t(l9M7@2ippXA%o?ZNF5}SvZ3Ld@5)^e%(mW?O!j4aD1X9W}l1ViuryVY3MA6u- z5ivD`N~eQBkej?>nbR`>UdR+nrI6C8Xxe4H zBm|7d5htDQc$CCXq!As!6`-_~na;J4MsFlpx@-)`jw5D4}Qp!@UQgo z69eQ&9BHb_QzKr#evVhKU0`$Xn9V28NX?KuPsoLjQ&TuHXFNLM;4~$YEo4wfdXAk) zWyMcr5XOc&s{(38K|yj;2tb$$*hr}=-Ft!HG}3f2FpLmb!c z&s}Qs=igj6n-ALJo8LJhNc;TkrKV{%R>dev$kUwt!!F02K0*kdZ5^_{HczYBXhx*_a z&z?OacjhWytQ1yF!{i2vygOOcNw8kiGO?2iY-pnqN)Xij=iJp6$cf_IoKOkgdT|wF za_&DpM4F6^g(jY>NaHcinI&Q)If)Hn*komPm7`w52Twa(T4~X$`F4LJ*pWzx_A=5@%NzdGGu0ng9JC{SRV)ZQaSI>zbe6q=Z^S^$DF)`xO9DW$Gx;V?lil_Lt8KoRs zJI2^Zl*u#8Cw4u&Rvi_D_Sp;30|V$hpLqMr{`yoDqx##F2MkQLxmi&Js=OL2C0%&4 z@(Be<7ge#X%x0myB9#sAm(;xC27-yiZOK6fs=7bVIUtw3_QDr4fhWU&a}XIA>RCgtpTE~jCD4SkdBKkWKAnc zVJWL5b=#g(bB`kbV+!aOCKS@Tdy6)k7&K-6t3V@kUI4pdZkS0PPL)(n**ql|Ts$|I zz#8#NNLy*1DWlScM2hE_7#^i*R3_LySM1Q3!Wkk77FS8)49EAm`)H3mj=8Wl$1t*m z|3seAJv>Aw${Ki{Yn2kqz(+Yxw9Q7504e07vKEr{zSjbeR?TJM%8R^peS=Pcp$`*so3OQ~mB}%Cx|4*Wn zV+#i|5iYPrb)ACJli4|_HB#AeV{+?(N83@C6?vd}mK71(Vl$Ew>D38Z3uKuUe5us! zgki27;`<)HBMIsabfsEl7#9@0y-vizagVk6Ixk&V;?CxgrA7%s=XAuGr6#At1S#P9 zwG|$3ci7xMMo5KJildW0o7;N?((u~Lm$^4ikgkv8_$b#WO2_p3eKU>{VGsnKL-%Np z&cPOEFI{6~uo$OQizo_%N}(%PU+G88H&pWEu{K$!UMMIf~;`ZM5`U*94wtk~pP58urF< z+MS=Db(N6wCf5>4>PW{(^2IDo^zLEjTWOYejmcJ)=UYi~7#;Crc>Kfw`4LByMo6J~ z$%p-v? ziWupfe3((Mg_u-YWf0eTZicBOlRiPa#qGx(4o`YuG>vwX#%vqE=5XifA%FL`{}DHC zKOtB=%g|rs_rCdwNRybIk;n4J3P-(&lg^OGn+Nn0!KKS1<{B=adG$Oe{gi{)8wJ98+d|X8-^o07*naRE=;}-#|8E9`rL2EHCqD+~CRmg!gu~2yb-h zM=3A8ae>~L0t^V0tEex`Q_?`R76rI5)#7L4v=(qwRiVqjSD=LwEuu3`z3#Evl;r&` zYiA`-A8!#o>M-b?kmm`m>yb&H>n~j6XFmUV_D;v#mnq7bXKAj+QFlZ)%W!eHexc1; z+vVcf1@1iS@XpOGQVn1D>{UK{b(#A&Z}9pH8|3kbg{DF&%m*LbWP5W{oV#$5QTDvL zpV1mO2pEk=yz|aGWLk6Wg)3&R>9IZ|&HPWlEdKesk9l%xaN2V`?IgVY&WGH*b%&F~ z1NOR!I2pq!^BfFp6ln3%Id*!6gZJ(uMb4kR`w@d-EMno}HydQRKqo0md5oh0#u(x> zDK_S`Y*8H7Bg17JYidR!m184-lUO-01=6R0{j0 z8Sy9qq^aaE#T3}AIKr}wP82jNIoTYiLod2W9IcK5%$9VpX$SuF&y=9F1me?UuK2w? z&s5JKrzl+pB@JdcV03hZk_yLlt<8f~+9?xFMbR#ZNrXUCBu;__?NZ>1QY9v@5^jSa zU_2UOv?i?A&|2Fh&panhGlc6`&Jv?F#`Opmmk^#`fChsbc+{2_Q3ZgPRRn=aLBJ}i zGm*xvsFcPUT^69|YR#Msosu3k0fSOd6)=RUXtbU(@~}}fzvknIK2j;$wo?E%%~D2P zn|$AxZCFZ}DJWgo=tJp^*F`^7#*HqbT9e^gMcoXb9hYEv4cRcPuFj+5h^?({=4To# zv>FKIB7+)w&?h-PMz~I~UTG*2o+%^j6tpD-0!3-(q*_yJ*O^^wvhu=JUVHfrKlu1Q z<6f8RFTcjiSI%&Mf5h5_WgfZ-!Qxwd{`v|(czDeE3rlQwM(mj@eD>l3{o#<^tj=*f zV5c`i>n@Kw0T-?`dGd6h559Mk<(UBA6?mRQ97PDNsf8|Q=ISiZ*Vtcc^Yl0>X92Sf z56_kS>8&GyUD+T=aNII_%maus|-Pjdql4P%(==&%@+7Q5>U`V-@p? zXrh#=a3Wf8n`c%jOBcBXrL?Th^U3~FeilY-o@dlN7pVm~R_a%0ISUI-Ub(zP9!J#D z4okBJ&-Kji{($pT?j&Qw7i(E7scXCL!X}ZbT{sIPEX94pMPcP@0?j|eMXo>rM6C( zbi5jSr}1|_-aP&7UcbNP2V$kuIo)~OZQtU@@c4-V@*@scx(FiTC}z9c<8XHimy}%F zisALZ!xb9kI@ElZmDzxcFD$XLx{mAF3aNEp86^c-vDgS>a6F&I#RVb}ihuIeTO15? zym}KMe4EfX#VIuil!E1%kZwOFGn!v~ZH=XN$RJLTQu3`^yX+hd`QH5#iv1h%oJ%VW zu58S+wR6Ia_aCz~S0|_i#KS%pFP-C~N5}LAV~lX{XXkNe=W*i^LI`|M@%r`ieC->@ z-2Sj5=2x%MqE2(J#n|(kh0S3 zuP|r@gzPU?K3L-@2cZ->l82iI{LFBn0 z;nAL*<>1*C(rxhh&%9)2W}3YHC+~={I|FXR^0x&f!vU)^9zXroE9TDALvb*280Zk` z7BnGbRmgKXT2LivmP5WMidm_biAh!V3ZPF#B6IoGUte|1=d=$f2(3zK>`l;ucHe9rr7&p`J3{+}e)wgC69Wd3stbs)|Bsw}o zVNkA*MO6h&OiC1n%-D*(S(c(RjTc(lhN=KuiDyf1z5z9P?(t|$mgUsyA-T~gN8&gR zqy7LTU9$18lBG?(8sYLXc!332#d|2FP&H>_z*R=SrGu5p;bjvGCJ{?xO5;hQv%J7+ z#>$zN1{7rum7UiXFbXJ?>}(`LRF2naV}RoMObGy|?aLxcR{ldlp)xk5ek`nTz!6)ZH5HP%?Wa;3ThO$ncii)N28w)PUFIG|oBdj0tNYdk0-k`y(2zB#mP_ z2S>Dh7vFR2d{&B+K}@RQ^RJ#`_hg93GG4wgk8)0U?eZcwA05++49$8-rVDCa`OZcA z3Sld6OJkMEaD0O04U+vGOgtz+ZZT#GV*yi)nc}~5SFSQX?eO$|4(~t~I8pL1HjusV=ZSqu-+0=f{|_^rCS*7PH2k~CSyBya?OML`=@{W(b0{s z{=?t7%?~+#<8S|0bEEF=63wBjT%X=3&5n*c+eiKU>v#9M|I7dQ?z`XM&;IPkvi8UH z@e>2&Uvii%BaLGMa^nZS$VM?)meFp{;QBtwQ7Gl$c^*Ii#h18#?V1TfUtlzj5O}T< z1`1^e0XoBASegrrj~*PNq{s4X$XCAi znC>v)i?6Qp`RgnEi|;%k(H00%Bu$-Lo8j`AITqR>>7dUW*U!=G_qcQW5pTVIg~NC5 zbKFl6%0u}c!~TG5I3|q~?%&(wr3(wp)*Y^%TjJ#48N0Xd&^)=s#)TIN)|b#}#{N-{ zTHuju*jQWO^0@_;=Ue>g*ZPd3l%=&5`lA#a*DkJF7r@4$(;G6_*+ojIHD-unL3DgX zIvUYjUPd&Uq}DxYJ(fyx_gRNWTV2bgbu3M-7FZr?Z_vee!1p~y;}p+TNGTb_2|_5c ztiveI$#RV}0;!4+Zz(}2CffWJ#U|I*2r1k!7Jp5=(Aq#Uib(oHyk>)-S!0}PkS?q9 zZS(B#5$D(DxqN<&?omJ%bxERuSw4S7{Mq+D;p5w%u()=Cet*ExNslwjEqYPLL1)bJ zT!WLtV**dHv){!J1DXwwcnDwp)`xum#vSI(5hglCW;uH&N4)*^m-*wjzs9fr#lLKR^KbkI#8D)6cXkP+77w0mvw7z>qqM=T z-Vs|3pP)4Zt$AXt=&PJ;X#r0v8v@6W`qmoiY8bE*H*U<;}O= z5IT*SS>8l7E-_Rs3K)rqMx0rJpZ((N;-$~I{QkEe@zHjS@-5ZM@e8ZE0-N^dl6obC zAc+&=!3a0-2^zHtkO#Ywe_AOj(~LSj@;s+D+d}!O0{d080c_;sQwD&&qv3M z)#v^_Rq&>YT2w|*5d|sAeOEG}{~v{}GRh$Yvh>tXeOH0(;!{b1h(|<6hd2}o=Y?lj z7vNV3&`C-fMMwc*J;WG6mZro>TFnb8uucVJC#o+Q#z0uF*}{TJOjr*|lN1bOX;jqy z@JL*rV0jti1?ZxxcWHn;_gN(o7Xe74EnmNApDfKWd5&@&!ouTHD*xN40vIF64HOK^ z0_d5-_|TO>P{soUAWflqCnq^DlVsB}XQzxP6y1r%bKYEG?j|i65`0kTFX$tkTm+Vj~*0QoD3c?n{ z)I~I@N|@FLiNVo^Fi>2%y2i7IIp4hdn8oF@{KYT5!TrrczWsE>^1R2(vo-ckTio3~ z<>s+VcNEiH&@9e1A#CxK`-)SY^Ww%lv%cX=udVS5FD`O;++ls8 z$s#8Q5rQ%kPgU?>y;J6>*xRPe*Aq2Rtq}2#`vUQB_IgG{$(Ksy_91h2wAwRga$!Twd z>p7&ECKC$Jb@{n3zQ$>hT|wsjt_Zs|6}vkwPk+#tryI#558v}JU*n=Zkc+cZ5vBS z78d7t?bT&*vcJs_KHkHhS;G;zh=zTZ78h_`S9H2PhU1a!_xea@jN?dj5}_Oy5JYiQ z1V63w%k?~wWrlH_5PFiZIqQD@v!C(4`VW~pe%|@dfBUblE!D#>t+j(+Z>sT&M<>U} z{@mQ{z6{>oNyIllJnX&qPyXKD+vO(*@Dl^%M;@I)&m?JLwAMtKVHjn&d5-6KXrsx} z6wmXBlZ5NnuJYIa^1sE>{ESF5ZIw`jAgp~cNK$i%3e1n$ugeq^!VKMRXn9gi{eEka%1~L7O&3m zt3P#?_QERPdK`1-pwG2)i=3Q}Xf*>GflID6?N*)kOoRQ?F@q?x>Jf$71_)bu_T&WD zb7?FsVwB6MdrFpOG?!NpjTV_H63C`D=_Jt{9iG^T$!wdNulU@xWrUJE-RpDO9kSSR zNE<#<3f32!+pPEZei7`7~cfFK!-iAND(tAQ7K#cnn^PZR(c zAwfA6Zyg};9oo$XwdNdqM;%&0&Zu{Q$wx+~F`c7rjt};z&n%cs8;tbC2haLkKOb;q ztx2aJ^XzCqr;{?*fHlYE_R|ihg9PQe>>p_c+Tl2n{MY~eKP62fk>?tJW|^7DfX?~- zufNaTXM4Q%(lwgx8T!3G_a8pu<2w)enV~?bG@RZQhiG>G7;CL=tThBQHq~l<;WRzqKdt-E*(U2aVQW!^Z`NBFs_4vnH)d#`zm3+qGVX3ARR^IS%y~+ zQI1oMX;BywRRm-D{mOe+KTiyS>YWO&dqp{-kn&6-qQgU5E5q{uYwVP{4N5{9ME%4yH!NeJp5WsMcj3ou&XD3{@2fam+*c%+VxzqA6L zUx54P-?_^7D2<)M8(rr1RJ1Z}NMkD}t2_t47E}}_ix_P3c^UbzINTIbOPg?=m((aq z1Hme`k>}{lkY*{yfa6To;)*LiZPXThpoCSho6x8PB_Cas5e{P`5~bxcy{>6(kWTU3 zWv)x{ec9GJ*L0GMpw`Bj(T4fy*$?aAm}$jd{L(Ym1`~?&D-bvouo|zKQ4_A8_(4V0Lbf&%XXLfBMZE?C;iXd$8_+gDktHs>%67SyL z=XjVG;vhw{7sjFilxM+pR?bZ=5MD^Qa+W+TsW>*;QOf$}afBET(Y+qt%rd!KN6Z|9 zi69vfMT#tnkP?hg*xD8nfdrEk-94d`VzOc`<{%to?p8_DAP|;?g*MU(1!Or|I0)Cp z^+T4I7HKw?>8UwHkuT*34&*s;6ctKV0^`qc6gm9acRv($PjPT^iW|<*jU7_oFuSnE z>Bmp_@WTiEYrphU+}?yF%Se(8&yl2QPMYSp1>ShP+a))qsBNYgL>awdV&_E^+qFmf zyz}8EfhQnOQ930{V<;-n=eZUp&rswfIm9^#t?}<{;h@QixUMP+FbYQ*fGih63Q4XF zy<;H`jvn&oe(o*#vw!~Ilz;Z!r$na4xhpRS&-G27j#yt%BJeOb-v7vaJUlDaz_9ad zi>)V5dHvNF+1Oa)s1MTkjK_wZqXGN-2Ml|sBxy!!j1_|^FdRsvR5;2ZiiRxB`25N* zyis2Wk~z5U{np?457*BwwLdf0uDxDY@=e#3FMAUDvHZqRFaOcrX7t^|;o#2i{HMRw z{UKY(kM;2r1LQ{>u2SR(hNFn4S13mts0SfRS%s@SxBScX)g_h}<_TOu!xt#eBh58Q z6yv(K>T*0Dl52w>1o-Y8qc~yfIKr1XSv&@#Q3`ZErC4Mj*P8C>h^re-9H}@Sq_}~H ziQ&a_a}38RqhbNIV%oMKP@JTEeD@hzLlzBqeE$*TnuWOrXV>PqzuUJJSCxa27DUJK zm^_bZhAv7dzOsr@4#SfU>1a%SVFBt5G9wFbrmiSbWgT_pdB{RX z-Eky~O`lre;$V3D{uVE;tg^H+%QtUs^0_MuYsS zvAVvE>xRrOZ;0FXpR&Auo?9J5vsYu zw|0+7N1D~yfR&B&$n-H%C%BCn?k0vuAI2zoK&~~K6}*e*c#^jHZ~yU^Ma_5E?Q0%# ziI_T}TSs|{*R`;ERQ&Wu6@yq~li#FSXF;@};xXd`HYQ6la$jDE9<|i*lSo(dhX|fSdyUWe$O% ziR-&l6qJc|S%SLqd?6rg)-f2A>r{Oz%6pXO70HVwo8!6b73WrY8b!r*Q~k}Jsk5AM ze}qm`l<%Rcs@cy!BT&?gm@;X~YfpVvk%IDlz#1_IloF6cjE@cxM&o*3;qfoWtpz%H zo{?uMuIFMQsx>N&0M{>yk0K|YbfZzC^eh)v3A$JZ6VfCl2y4V~f>eSuO$mYk;rJwO zXpIlwui6Mvw$qd`Qi6J66U)nfF7IfxO-^?_2VF!!Od*>o4M`KycL~8m6E*NpcPMx4K+hZSixjog+?SPKPnQ-iR}EHCmy|t;dHf&DPmD>Juj^Z(Nus zPEtO3a>%ehWMQspomtwje>x`Bf@aO9W{$aXW>(C!Y9=4|an>($^Ufo2aB#wnTMr05 z#TVbWYIe7tiD!3iU_6&=U%19NmvmFO|74qsD{Yt+)WT)l+6aLTju_Dmy?J4xJ8|c;W#011YsD^tk-zs@&fxu9(%plaF+uvtTu@s?XWX61T#%u zzp%#LtuC$ECC;2%;N-Z=X{SfCRcA1Yp)kNshcQvA8AS=_S7$lsj5s{*GaQT&QlZL8 zAqt9YA$rmqXEvIo0WGUN+-Qw3uFbtt0^vxM5{$B(JWne+ni9&+32n2{N;6zafj57a z8`~fA<*&WRzyDW$MR>I~ol#(3xb`MVJQl}$_gHFc^U;m(>92h6nT(g$sbxd%?~XVg z`W)SO%Hop_tyYtj*#-zfrytQB2}Zh3riy_h3KxYj7-^-J9Vtm2L1Yw-_WbJQ)y2Q{ z-~CVj*}tA=+4ZH_#%JoGH#-<*pF~OayZuytf3I)ue|>-L!JqvXzZmh8x;|SmP@I0Tu>$roP;g@!8cBrZN>Z>zx>lI2A2OiQ}=oN$krBV*8*BI4OUm@h=q&i zNs`z;lhPTZ!$V~L|FZXHKaw3;n%~dN?&@2(M|f#=obOPbgQQ|Gnn4Hc6O1)VsT66zGp1%5gy_D-Oco1 z_j-6%j|!vKqi6)l%m{bC*YCA!cFy^}^L>RyJ{*tP;D~e*QD0j_)SDDlqEZGI3-$+A z3b58$Ss*=Gnlq16E}d%e{BTOM)d1zt2weitp+A_?2z?x7gO8vd;sze7RO49$jK&5Z zqCAci;MW5j-?e6gi-2i~+EBhvxyniwNOcL%s8xS~xt7ldS{D7cVLpUx!xqHY6@RTY8Nr90Llj)4{ za43>^hBO+Xe5=%xTl!9|UIWKx=WuLBlex$=c+D2R<5B7|oCM%-5Swt;b6bY3jfdR}OxH?}86 zEhQVaF0e$ogN2ZX7kD_XTUKLFPzS9~dUAv)sYnaMF%~FIbst43a9~j$3CbcK%5%Xu zWfEaOzbFcl@dP&vaBJZSI#pi3YMl~FAZ(|1nVg>}?VM2M?A$Q=1SJ#Nl=PeGJCuEA z6+KKzyqZO9wUGF08^p#?jE0CbCGPDJZfv8ai}E~tWqWSYtTJRYRFuRb&d_O!8(2Bn zA}`Q+K{A{1$;~IMzV#Bmf(OSD{ZYhvr_Sls2Jhb7;oNq?acubPS)XTzGroRfn~&}v zkm%3BrvLyT07*naRBHil%Hb%+Rg!kYVY}PnrHvY^6U=L8Yogt*i8vDYeu#<>cyKHk zMLCz&8@zTV5G$s^`)+|L63(wGq*vp?P_jEoS=(rm^q#Qlt)!Hw4l%w zX@;W|Nt#g+DV7{wlNSjAD977(FK%`0VEaCYmwn zjW`lM>nk3UaYQI{w%1qq?)N_=lRjVn>Z`cEi;@CY3c|qU$?h?a_lBI?Ucqw(&AQKg z8d07RlquV zW|eY?YUlZ1{^jSaGz0Ui-}J0-p};^_RoJLZp}`K$>Rx_5kfks zT9eEep7$bTf6im4N0H9S3XSptl!T(NNx9YrM_Q4K!W4MQ;K~BWg;q_m-tyYp?chJ{ z1l=M|;&E=|gGrqI;r=}R=l|;IxgUS;_kZ>O_x&CJF5`;?0c);hgr$j0 zl7itZ1MFs`1QY^3dpg7v*0jhTw5oz8?CkFm1|G%1gwbG5kqf4Agrgju^={GL+_Z9m z+QPO@;GtxLbgaqpg2C}IS1xXG{n9_?&i%*aQL}`vH3T6ifh@zmmwGNI)G&m-oPHA+z$XWw!M9Et| z3F<0Nvo28-<=UW6YlD%7oufI2qbE2@@y#!76ZkIA`p3L^bsZrUcX!8&YPJm;ORldj z>s>FJE>mWHILbjOE9s}PRaSdntDs^zG_}KV6w@f@&&f=wChl{uyT{zX9^C4Bk%2Cuxd&i$QLvLxb57rWel z)MxK-#74KtTBpU}u+NjvKcQJnh$a#7Tw+8IGj~ah;-tHJSj zPM&M7o?GK^u*%W#n6KVA#f9xQfBY9eVc6@@syVEYL0TXV4(W{|Ci9eU|N6IBU-22u z)AHVF1QPAk_;h#5AOGz=Yf9K&W5a8*J4v~6s?A0xL`ir$OnCR^p_t55#)XGh3#+H; zh3fy`pg}jTJf4wHX9VpPf@W>;oL8?C z6-rSCsZt8UW?+w7N%B?!tg+IlFQ{En_Hr!Gucd%}`FmGG34zS!%nuF_I>+<96K?`+ zU~IHS`J|NOX<`$kiWaF2R?4n>Wo|ndQ;4GQ>Ww}KtTqSXoy?$w4 z*#3?@r_dUcTZi(BH>R~A$u+7dsG85Ste_}^i?p!cC(bmkGg?SwJk(Fw3T>MrHSQ}WV1^OZIj0JPK|GU`3!r5 zDbM!C9HcS#cSmF&JfTtdNpOhp`SHDDZa$mX zbR2v~(`W>A>OP;{>GApDTzvBI6FN0PEpUnF5j%VPxb4$?)>a-P>uu(~W__#l6v}ea*&Mgo z#8KW!0ZULSA=_)L%cRgICs;W&%wjJvLM+UIrQ_fPHG0F8!;ha@kC8M+Pp7!e26ShZ+<=k?AS6a9l;cpZ z)sV^|GtR=xr6}opg^+YM*KvK9ol(x@U_iX{Ip@#4Y1Y?5(QP^?9rNx-5Bc10;IEy* z3tWo4!1zrZzs6u3acbSVtk06lC{a)gefr09rg6?JN}yCyqZD%y7+lYKhUDcMWA{*r z(H41AhR1`Iuk+%2nQYTe!_Tt$y?^;n|LKG;#=rCUA_4gYLrR4#)mu#2QRw+@xgjgG*0vu6 zYocalEf=M7l(G+>-85|Q>^dh7u0@d}r71VmD!6ti3LC)aqA2|jEO%Kti*oRyDp2WL zTY7>)84yXt^zeW%2&ji1(?K6&lwGs{Asma=P*xeS-03`uhz}1aqKLUKc-o)v>tB6^ zfBze=nm_pCzY+h_Kl>vZ({29S|Lp51$K}8NgLip4n$oU$6lp@E?jyCvcLc61=ncjM zu1lxkFd9vWkB>2VPIG$;>AOt(M-`DS4kuFf3Iy+$^0-`QD{~ zP+%!iiPn7ZaEK5EN(hp{1U(&ENkBB&bcpZ!2)9OlG~sdYKEd``v>Resbe1+^gPf{) z_9Wq{2MWhzytGy4dmkRqS*a1M)cM-^O}Z-qNu2QT&OO#@4sTpI&(MVIWOX*32tS?h z@!jX_K72s1dYQm?S!)KY)LnGu^1;m=HdbovJ@51J&8OVB(52TKup$$_{k3yky>yn3 zMhRW(~A_?-NFQ7Nxb19Rf}v1rt;0{rD5p3;M% ztVUA?hPH$*7oSz$^hGtbD6DUZUVeRfE%;KDW?}&MnV~QL<@VRp76w!Ff{_{QZTyyT+CWl8;CUMSo-Q&jfvrL99KEJz5 zURZTQ<;VpVq!5*^NMg*ai zKSnGR#3XjV@H`iRpxq2<2a3oSY+c{r(TY#E6|k{dXMY&6z1AQv_UW_&HdaFBNycj3 zYC%p;l?U2AzOy?QndBplkjp1m{XgFrG+a_tZn8z_=3QXvdG!kU} z8mpZaBB-%?@j6Mpix)*mc4*XGg7X*fG1O`yZcwAKeUWZ`lR_5=$HVqY7Oby#Xw>UG z+#eAoR^ryH1qi1ylP!yV1!WJWE%YhrU`j8dMc<@RHcge4VqRI97aE}qs_YTTjX}B+ zwc?W*ftD#&`q|#&0uU>kE* z!9*k+&N6=Qx8CIQM~5_gMZ4zVE6G~JqZvBv9r|dkd9r)Vet%+xDU_wG>cS@T%|^iL zYJ<^mf{8L@i6rPEM=9ub*NCHpJeu(fuH_R0Hn{EQ^Y=$yVJnl9oIpF;dZ-LRQc3S-EH?AS0Bib{~Z~e!=#^tkXHmS^x^r>&ZCJN(= zG}Cy#k1kR|PvN?XFsPBlW6&9U$HU{F+&=zi|NVdUU;ba50BK*0|Ci&71mqWtdKend znHXsbwALcebA<5l{eZ$43!6HIB1?%UW7|(5N-lMYkl5-*j@HJqjfD;Q3$2+>Cq&cP zq9RtwNy??b0XTvCDS76~IpOve)>TVLE1N0Ph945Y}k6THJZOPrP@JpMCH-L3J0{mBa)+Iio(#^-a`5wv%>+|bVhA`9Z_pw6%1ur z8DtU2R`eTVELT|(qm9Ij4m7c!3l@E+~lM<308%$joJdMN$&(T(s^VX9hIVf>JsTZB8wvnS=U+! zFIaH17m7{h#Xbj#K>8km@6l-0x$|VeJkc1TI3A8UwGuKK%~+{9gl5jy-nhU!*H7_i zs#wjMytV04PY;o<%ii2!0w8Tt+HE>K+_5HAf$#9NKcl_6g73RLIT$lO+-IO4G4iLx z;~IrFjHVGHn$v05kb#d#r8R5RHqfae?IhFe505C~8SASaclYm*?LK2V-lBcxw{aS4 z934*(ML|BDQlu$CvyNOeYqO|I!ix#VB6eS*WxYVxf&~SpqP)D25D2ko&R%?2mE?nM zp42Bnzc2>BQO5~vHNT>oRp(`A42wibR+7(4XhwAo%gNC4@0OLf<#?4q~)H3v+V*y1FLzyXuk(bmPVueBb3q@7*N~ z1YdgPEaUN<3un9dj$oeTTsgnSlcxt*=aFkr2Oob6RWwlk8pQTH51OY{^IoGYR(Qx?5?L%6PkZ-=c$=`gs$Kg1!w7!yp zwQzA>+7BvRLt=wkue)L8W5+{el9I-Kr0)}~Z(@9F3R%$>rLg`-QcA{g#*c3GIGQAc zzQbgeFq-E)?9VwECp2nf=5b1^<`BmTy}^XZ#3f1#?(U2^NOtLsVtiM!-turwLBDs5 z>$+&=FdEHhv>Nz9KxPbRFnVs)xP;5o(S-N!^iiIV>nh^j0E9$@Z9cpA-1==G`Jr@i zOLuJ{U2+4?N|#*vtgcEVhL7(LND9Dl5stI)KRH1<4MkQq=hrGnA1IL3J+bkEHSH71_D<=Nx+$PQU`mAD@*?g1Eu_M0 zb|{J*Yr6+1#}*2tW6_Wb6o@G^c{m{*2Ky$638V zx4Vj~Byn1BZ)e2OIOb>)qr{)8pop#Q~d>h*w}^BkIjeinpy2eS@1jbLNLJ$MZeHR+HoX0YzbGY;7Psk9crQI+_!# zucI1G@${(lLkv$vGg--N`($e$XCjW(v8kFrVNUuv`*I* zt;z=cV$su4qV)@;MIbNSKxy+E1?0Ny1eA#U`}XIV`_; z8NH+Q`N(3DgMEalkdG?ZEKL{1(seLaO)1ZFYgi|h^&1gZDz>z0#8&eytz@mcg6}%y zj!Ujw8m$J6Mvbr@@}r;JW&d!@fATwD;TvDM$kns!9M1~=`qO>7Yb$*H${HU(Ea*12 z&{@u(fBY2T`A8*rbTH@6(}a~!a{b~4`v)UjG)fxoJe%^#lOgk5(C{6;dTpHt&xd?` zZ;#*n+GSq5V1u*|?j7;T(_?}nA?odOC6#>Z>(}|&XHPM}nbkV|y#riFaq-+Hzw-4P z{N!hM85|sQvDM`Bhkb6|?<2E_fASB1iSA0wac^d2Tq}B>u?fRR_Ye8Or~ABhCFU#F zH}PG`G%nccgan>s|0qTmns&nlPZ6aBZC`;S8CEE>WPzw^t$B7hfxLV+b!C4 zkArctxc3!`S1CEk#dIjqEMxl}jF9+i>&&wZl9<5c#7ROC#khX3Sm#VRXDWJUl;m7J z)#Tf+Y|&}>eDCHycXuZEo}k$Z>9zt6j%R%KY>e;P#kAoW-1aI4L23k@R!F<)F`A|v z4O8;mW4#&Tc^>f`qC`TRV2q&|C@ya|Py(19;TKajw%fR_i|s|8cRAf%;fEt1N`ypW)+ ze@&7VM9$&g;Z7*t11{&Yn-%-TSgd!QxN5_(GEG&IfW6YEj80|C%@cBM zsD%M{?>}eM>k*zi%fTdLo=W0eBjypl>#{#hh;_z#r^aLwkxvu59t#D9#+bsY?MaB^ zlwN;S7F8q~jn%ZVUM~B+0gjURuI;m0U0WqX5k+%GQNm~*;YdYRCVD8ByfCZ4tL_{n45I9KB+^7!LF{s`5*#OB!!#|I7{4_Z8VKBInpjox$k z>$@3QQgG?DFl^Vkcy%Lbehve^7=N$vMFR2*Ms9Lb7$c03Hp>s2n0(6da0o);xIR&u z5=9Y{C}B366Zk&U+0;4%F9i(?-w3Ul&F7|3Z{T?W{o@h3$Z;HjD*=j<{h<~TiDi@w z2$J#0HkoRT9|U;yI%&0jwT6z@;5gzQZn<;;7W(lY{F-E_6eH-t_Ycay2G>GA+yBt!ku;pXQc&2 zzHlHO_KwI3Lvw2b$9I_>9FdG?G}hOU^#-}A8e31OGUWv;uiptzzfu6IstO_JV`k)mG(*b*X3iBs7v*`>Kv<4o#P^4F1g-9fN@;B)ioTg zky4aRy9r_4!)-Rn9hX9z$z?NvTlfNbGx(e^??2@B=NY?`fO&9{XR`)>`r$6Rp=oVw(`V)<1g&=?VMpT_2R?X%`^k8|8Nm(`-m%m&1BP`w5yjYUSEm4FQc;!pg z<)wox0*@-WSg1Kw^L&YVwJa0N5=E;*VeC2CL&`FEQbHh;IniJMrmz*_(rbW)G2RJ* zPf94Vf;7!>nk)F7RkW~)w^eA@FICJ?WT;IiOG)Uu^LMrmc8c`H5 zE);d;FpM*9T-oORM?+rPYLFE<7|q%B29tTlSFWGp-tLsWquA15d^mr41#JY6dQ+sM zXapW_U*F>VsSck#88Vs1NZ{7mpFP~+>u+A=Km4sX@qLHe5BG7rfWh&UgV}TZ)pcGzbA~iYiDom3I3Y8}HfWbZ z5Uzx+Zi@@263%b8nM4^;l$Ji&$rn*7}IHn{U5Xi;+(Q9Qsh+1T#m@fG ziq1&opocOSt949`h(Fnm=@|JF;S(u6iSvo7ll>3t4vNQ7dRtuU6;W) z;a~mmF1`bvGMrs+;R#KWBsi{18cj)4O;Bs{&W+P(&%o1XiX16~ozF;w5qOT`m6tZTu+c#4!n9Xf;(I^6N1kiD-Z_qy+ExNn6m&XG-ulXQ zZr|S_N(%d3;{vTEoz4oUx4YD90io}b6q1Rv#lQY^!mHO4R$C!cR`|pBkHphKz?<7G zTJ04c?;LXF+C{cbZ4u|t8_iI)Hrh#vjT5h+p< z-aF#Y{`_xv_F#{26K2vN-2j{rr{2P8bSO%Qw&I+hS*@{g_6kxu^!ms2#tA}7;?amk z%_R&xM*Ra!n&LX%qIz7Ea=Yz~4K#*9|A4U3qSjp}a{{zKRpNK=r_6AB|}ZLcFepZVa3bULTD-i1bk+-3_W zJm(V0SWsmQi@>dl6c>hKi%OIYw5ovZ1t>zWXgt(qCF_Mmr>qnksvW*ky{V{LRVY~A zzeO}_-XGar*;2(k=kZL0+D?YUY+Mw6vh zn$W9U*|D4BEGgB7a*Z&Cxh@dWW2QZh1~c@nKL63LbvgIaMTDbhUx=tRLi$f1^V?rO z!$1C=uQ8gX=AZrHcg3II99XA$1Vv`eu5`6Y3K&Hhx1Ju+Z3i@J9$rx6bVKsy*(+RZ z!EgW4mzhT?zyCk?dGIVkv>Fsy&iwEgDIMzFHnTY6>u+7>+PMuzlL`Lw5vOi`8`J;* zAOJ~3K~!f6=T3E~w;EhLvq6F6(MQkmYu4P;EZy^R3X`Qdd6MAd;Rz~IAr=OUkmR=V zsFcK5ZPt_E9*Zhg^TaHYOtIKls|28Y@#3>juz?p7hRUJ+=leL8U$>lWu!O|?eDbuA z|D`P6mfUfR3Z4W=N@7h05BgB#cww-(9s;p2%d|OCi5?b)G%IZKv9?YwY@?--RZmr^ zx>r(v3RC(e2*oQGx;D6Q6x;0@Hy_Tag#mBg*yj4hoV8ZKvx5;yVelNq*I(Xbtrc*8 zcZg7u)rQZ((UkEx=B=w;_J?yu^BhMB&a5}sAI_QPQ1cwVdvl-JB%%>|yncC|r~NUr zI3-GRgs}+pX4|9Yx}4ppk)#>Z;gFFKOy&tYdqd8j+dz2^$K!~jamty^4*UB(gzIwg z!Zsg&_LMx=taSr^`&*ZokB0o^cRpf3gFJy`HbZt-k&bT@Pz0}>Yq8#PXg6y7;rH(2 zyMk|A-@xPt)|PV z)f&A~LWO?oLN6GIqMV0DK$c{rlPN*7j$aE)Hjcrm*Kt-lByogW50SOHRfZ~&7s@$> zu*ze{lY}_ctgY1f>BB>mBRM>pvsRbf`RqP>>#Gb>#pdQJdrETm=`n*z%4iakWI6Rv zve%oif1FTncpOhs4u*41uQwP+1r_yCN|3rBk7LMviYTVm5L|fe1}|N@Xwd_))X!Kw zlcfNHF$T|b=)QH0z5X$O@}2jYWigKOER}4QEdz)YSz4OZE}M^*MTx~TdGdVPMt^m( zPMDLPF(|3j#x_(#fpYA@@+`Ngx}z{gmag-b5?0KoNYAtK_U5FBp&SpBXQdB|W7h&H zFh-)3vi(y%o&tJNM6`Q&SuhdS?ALPwk|ahN!{Knw_wPMt=it~D357%pg(ZEKeYZ%m!tl}E zU2fifOrB=q%dcES2#n(>fp93QwHq57t+s0TuEWtNLJ2E2<2Vk5vFO$2Mu#l5@ksl^ z8@%_)L(ckZsGv@`aT(p&=F!e0@I8Whom?9Z4o95YlDz%;CI03|A9H%EOAyv5@(i74 zxyj|>Pyg4SW_&UJ-s6h|ih0axtH!T={dHQc7HMYZpV0+bnxe5) z4J-3nVZh>r0H`Q3w9d^uih29ZFN@b-f0NbjCd%_D3XK=kc<=LF9?ZswMw>z#6!1&0 zp5n^7PdpqjpU2!df10Fl_^Th@Vwx+$Fksy8LzNSnHx14GLqcLfV*<&5>%;(IhiVX$TrMl%qhF8+VBm$kKdlnL?w>V6RfI(PgzU zOA?~V48Kvs3;dHL;pc{sf;3J@=Mi2Q;`*))2+fHru06OlzMCJ9P@YF^rHLcT4GdFK z<^;OXMB^F8Xu?(lB^?_eXDPntQvh+4(I}G+VYIEWX^nCfwU*T>SB^SCcVMYW)}RYv z>tzl{bM6gi4AAIwYCNGuHtC^&yh;MGN?Xxz zgfWKNY8zoRTk9=)#}V(}+~N95o7{PFM0mSv$)?mE|BFo_cW_SS@-JQzWi;YdMIXdXW9@yp+Q zg=VA1dmlX_%{9+^L;mW!AJJ-t{K~iAVYfFSN-}=)YuA__9rLgM@~1?Zpnj%}TXR54 zYeHC}uu)cU>(K$9KJ4+eFP*0rdQ6jyqR@QjR*$>ShvbE!vD)V0-k5W1A^+YtuhE~R z9FEgPGOtU+OUu{S-0Mwv_ui0MoN^Sy)pM)d-WijXbLj;AD%G*XiB_8~tPnzV&nr_+ zwX%xSwsSHm@3Ro4u!gqDOSQh#L&sLih2i3MlY37GytLh-TUT7ze1}KR4tVnU6Rw_L zXQLC+ZP%F36ZZQQ-28@n0vSG{j+v1R$296KjvpT(;-M*8XT)mQVf%6itqpx2 zZrnISZ~uTt51(_f-J)@BooU?0brid+HGcZ}E@@gU)=%reW7kGqXj~y_Gy)WcBF~w{ zDgANG;W)$h6iQlpbCzrJLgNP>S_<;iO7|W|IrCY@EY&odO(CTqNppPPB@BFq<2g!6 z&YfQ4!P7o_y(8PuFRVfsjzSy3)BcFrWP)%!UViy9`$rKM&#jXRhX)4*-@e-A%~u7J z@q}i*#^88N5c)iL+yfN5{gF9$W>fgS!+dP;J(pToI=p@{{@&w@1mqWt@pLYeG*elU zQ42hT6X2*Zp=&pSBFoT4UIDkbu2)qj!~#aIwvno8Q3l#sp#>O1PttG{-G*c~8#AAc zsC#Sp#RLbBTtJZ*ynSPv8)w`6^^foJ^wCpH8nLnB@$GkR@VmeIDu4dN+Z^`~F=>Y5 zItvV`JRg|%$u*Qk0-QeB4un9;R6dD0& zZ38|fPR>lc7(_14%aq#VX@*-=u(~My5K45Ts*Gtvk!B?G1f;_8tqEQwnYjpfOOXLx zXhi9gp!E`bZ>)T&)|xC%DDna~3~^k?Li5rgisl$0@m89)nQ=jzF^j6FANrLP)}m@@ zXO%65p3r~noI*)FW%>Jgu6gy^8MfPXX49Bto^bX2I!|tX$dBIpkm+p3r=NaG(Rc+@ z*!wD^qDVFIXlN;Z%_dSnJdfD!bh&cj6rGyGskIteGT}!bf57Wk&za|Yha4RAkSiN# zZG&XL*+3YLqXgq9<-z`h)0-`fvE1{pu2^Y!42Bth_*WnE=9ez9wc;_H%n-)Kwoco7 zRbCeB$@25w9aT_P&YMDOYvfs7o5f=&$l{b_Hplfm{HCRFEvKPX;#vjoC$tE|A{<<* zkd}vCAT?=}l8mP~zDLliBOF;iF`W34ETJ(kpmm0Yd-sWI*U7ot>Y#uuA?o)~MTX;h z_M^(ziUpJ?7IVmGZKXDKNe8sEeSx(6{8+45W%85dn&WxS<3Wr7uAEJ&`!3Tc;iE^# zeExilHiGR=fO1`)9nQJ`{Fq0($IRjkgCR}|E}vZ`&LH$%(#!^9q3__ig2Qo4Q5eo_ z1Z=O?x&7prnk!ge3Ayw1kW*`Q-oCy`zdz#iR-2vvn2mNw5CmjmiV&()xij>Sri6~< z()J2}`rR4ESftV*xOIP*ue}rTjkhoJbbmyr)8xIIPmzAeN-LmHj-|DR{z)QQ&cs;5 zlR?T$$8+Agvd+Kw(S+Tj8Rxb;4CaQ-)sTn#V-AjH>>tng&9}~R@7;$)xhaDoP2E#u zLK3Grc~-Ew60+3}nZ*vL*BazmVNnmtN^*HmWLbPE%4AYFE?%dDQj)CDI7;F<3a1SG zjF1cZnAV0=8?xMx6$Q~eA)n7_bXwFpA)Q8m5QdeSN0Do~EsvHbsW)ou^oG}*R!vGQQIM?@b&+T6JbTE|VIQ-;vhd+CC0Z>ow&}T1vq30}w_Ek7s%mad z1Q(W{=aa;vI+wD46Dy5uw;Ne%9tr%gQSRru48Aq8l!#WX6-(PKGy;c;;%ES^9E4+# zWuKd+8f#0ra$OwPMP(KRG1C5P*RpbDS|ALv3OA?K_v&XHnx3 z0>NhwMw~vgPNU{=7^hZrp}L;sek_H+btPfo((pav>6De4&+mNW6-Lv9Tx%Zf9xyl> zf_CtfvWc6cNDUUTl?vCFBt?OlCm<9T&u;L>)l)=qO7CFEO0$6<2Hd&*oKzRMjzVig zPz!nO+Bsf2yTQ$ed-R8M?mRtUb90s7{pD8}P7^-){0WnJ!6%P`afEU`+Uu+2dBM@afLhZcAH)8DY#!l- zHB4!oB}$nuBrR=HuJ2M`Ya>J{wOrj;sy0)5R$ilKO^qCjkO;@YU0oxe z_z0zN+bvs>E~6c>sAid^P3I&au7V2N?0E7W4U$T}IL&hIJnZw%wKbxnKHvFxpN(#t zhqrGse0GP!S5AxG{vNx}pJ2AS7){wY=pwup;p!S7EdLmI{CvQwnsZ@2;NB-Y3`P;V z(;mgqGcu!izSpC_^AKU0=xBt&pd1(Bub};grRGV&U>u=@4MGQ#Id$Kq7W%w=?L4|D zIDGPiVlV|)QAh`8WewqnwvtutZ!87L3xonN+Il!NYiMI|J=e}teS$I+c|n$DWpD$&jaqbH4T3Y5vLYyiD(S#=Ey3 z^Y(S0FI{P)JQr6A4tgy<{`3*^X~gXZd!$A%NehI~j3zVk0<;$V_@}qHbYYvbT_2+p zzW(|J-n?;|QIzq)<0+%8QXynf)EGuNU~v3^d;2qlatK0~AK&itORsG6>tEjH;r@tu zVz2e?{)q2>_?QR#);lBD0-bBVbg{!YHN1Db&+#;&=1P9!^)35+8^iZL>yZ}PqA%rh zT^PuVik>0}Jw>~&SYHX*?gZ3*#ac7qR68Jatw&0sHIB5E=q%Tal7iz|#$cM!JDSlO zOc})mgK5eSZ|>teptGDjqT=Qf(mCu1&dHF&Vwq<1*t%}ZSZAHH^d15e~U?oH{> z3UqD@MMtyTdL%Ryj~?!EcUYkdrIMQ}lLe{x(;wgAjDE_i*RHTEvkp+?DQOxZrCl!# z;5Y$FIT&5=-S7X9cW(~(*6+OqiKH-#Iut?(97my-Xqooe5hssvRj{en+XXraNEWYM zD2J8q+A)5T^x5 zRhs=REjXe=S<3U4Cu@WdWxhn|IVK?2Hu-MVJkFgxL(|Pf%}FseD|0S|p;-e@6$Gwg zjwX#0RyVtR>B=dF;|YN%SYPY#+8Z~x^wMcQ`uHwE=yUn}I+>7UX+|UTXf|t1rx9_Q zA%!B(GOnFlJoYI?EcUJ&~;PR<9X{Hfbg3txU`4;U!;t5SQn}Ex}7#jn$z1mq~31fHdpBF9+F29&DAwTdkv%fQnkWXlkzOLw6D@V+*JZ4O<9?f zB^SPIoD*P-z!(doyOfQ9Ky+|KJe?6%4(Ix$w_=fZaDp0$>dzQF-z(`@FIN49VBwUy zeED@%VJ?IA>gr32hg<4ORY9_vzxMql#iuBPQP;B-C%jtIuM8HwS`DvWw@3+;Qod&KzU5hE__;Y&&7-AYcG-KQ&;?S$&R(B? z_4(f-Cp%>SH+ygPW7&13`Th2AhC9W*F=phPOitn;k`h&-rjk_EE~`pq*xf+GK(`I} z#gBgTU*LbhK-(~21Gdq&AIc3>19n%dYf@ENER`fmq(pH@lF4Mwkr|m0aU<@0roFcx z_CDv{V7Ul))hiD`W=3ShJ?HFU?X|wO*7s!#w3aMJhjdiVy^qf`8jUF?2jue~qoY>i zw4QtUJIwo6J+(0=jFI8ZAN`Ow9$lj_z5%hyCOmt2mj`z~68CO?z~b;WVseBF!kkiT zu72e|;6z+z;xtF2jJH2Nq{wqN1|7Pcl=))D@o37`^@#UAxyRo9BcxP_!jE@Zmc-k; z$fy;7%0OouGE&Wa2bx@^r02{JPK7;HX5@&|7}OeCt0kd8J*IUjSN*-3I` z0T@G`7rqg;4!RIjiv=o5|CZ39l>T#s5Lio-%?f_>?gO&Y5hsdA*Q2K$fBeUPfh{tOG0Yzv z@!rWT4nNXZD-dy;*S__2_J4JUU%d4(w#ZOY(i#jn7$&@%l{g)dto3}RSp>ToG_f3l z+jky;K5X`(tAgzh&bhO0sj$7WD;yS=Zo-*eOu9yOIK~7Fb#*Dbt?4xMDFH~So#36)2ID6yy zazJSU)1&fb&z?%#lSI^+{(4mWyVi*s(ewhB7q1hxmnep^?%rEclV>UD-ZL}85PmbB#7;t0nkc&yet%p;l zvx1F{F6~ZCSytqw31!um^IKhJqZ4j?c+F+|ABnS@Ydnl&eq}Onj>=Tb7A2(>EGlSk zT;S|8FVl%54u%tUHrCkQ8gMwAFkPH9{aAPQkD28Ko86dxufxNGDTl)eLf7QQp#;oU z+`RV~>jYYLQ3IAt_1v93UAP30u_A07td=!F!E%3=`?;e;>F zT*TX);6-!^`c63P05Pm zRv$18N>$hB`hRZFsn7vJO^fTZGp-3W8Yi+z0f$m3T=N;rM$quHLi%zQ>zlbnNUeG! zUOS8a)9Yt);qx0k5#tZW=0z-xn6wLM`s%6({&FZITO#gts8j#f{N75G_=7+28ue?67NrA8=2 zUy$(nJInp(4{jA{T9I0=zf(c)GON-2)=I!p*U~pN<*RcV<|uB(=rr=R`r*TBhPL{5 z>Y$^c>|KeZn{^U`aByDRr_7ii9wI73-15rGzPq^ILvFc7op-)WSrK*C5J^IDa)PJ| zv{sn;9Np_TweLa%;;i|MY&s=MQ{rA1hs4>Ed~TRa-6)ce7N&t*J+Fe_TgEzu)5;6^ zDGkmt94*MkQ`)^Q_s0fzQX+#R;P-)GvZxwHAE_dy2Ht%*N8oGXmGt|4UOGNGSfG_c zYt6WHynAm#qy=Izp*T9ElO`x7DXNmZH0U^J1I-F-9mMiDRrW(w2mS(Xem))&3PBnt3n9jODCli98F6M z3LW%}juwt;S_YCM-{)2sFJ5|fqs4O<`h4-i8dta5T-a#Qj|ED=JTEw&%(y!&nPvq= zmg9iJIvyU+DUAm~2ECL)uSF-4thY7m-I%p@%2ukmx<26RR|g!=OYRPHetKib{v_w_ z;}KNu zLU0@49w9tMtn=BN`6A-R!*G!6jYdT!Dk}V0J=cE^%tVt+p%1cq7 zE8(4*>^Kgeah0L0R)n(5)iN)+G7@#)kiqMctORpng}G}blLIa&c!SoGR-`aO@$36z zt~~uLdsE9hxAy61i!Bx$9+Wugc=nkqj5ER9Y0h6f%a7i?$=^JBfCWxO55$<``?nZ9 z+~Dk`%iKMfb7OCUkb?7P1}w6it7rS%1%{)A?}rhNEX%00qN^=7g75wIZ_ZZS`vjg2d)z_3)oC%_Fz?OXmHQS2++Jt93W%$C}*TKiCGYh`ttv)oN>XiThAOJ~3K~zASwY9pQ znk5vFx#r+=4Px6Ij#gmG5?2*|%?gJK+A2ws;v!#fYYB9b&QX>X4#8qJ#jbnQ&RFa9 zAS!=2$8mzv5m6M8#xb@k$nu;xj_I@&RwxjXMONS(Jl@~O=}WkHE!3s^W_lUuq@)S~ zMYm6@H}J=<5J+LkhKE$+F{&uYA3q}9IRkMU^Xb%ApiXW|^8)$>jZe@x9!ocW>6Dx* z<62!IHG@ta2!2W*q#5&Y-+EqZ*0%Z)Pc^v{0ur|j!W+@SQ;O;$lu=k@QIH)TLRF$u zAAHn7dX4PXX2m;smNKuv2;}9j6?#?AY8a_DEC2xY?q+vPx9p}ntVRTI_b-MS{;aEtTCte zpbH{(!n?z+cC1}p3hL=d!I$yX&Z~63UxUySu+(#^_b=#Bt6x?Y>nxo_^WvpVUVUPN zS1p8D~uutMF`FKWa;067brK(|Z}W`c(v|OShHeuy7$Z5m0)u`r4~Y{ z5Xkx$tHq5QQjNwW`8Tr&`t2C41&b`Fs$fz{-hH&d^e^!2moBlp) zk7sOe_Bk0%m^|92a+?16^HfqWeRz+>G$UQ#W^J>N)CY*lq9r_W!Q1WKjSdHgUL{;9 zuMj_76ufj{gY64__Ut+@Jo5y-mgc6I5XBnn488siXD>fbo)_GHc!;ni&p&&P3)_7j z9!@zvnef!*E%qKAqNU(>zWE%7$1|{oZYO2X?{IK3@qHhm*RA#u+{%Qm0!HBV(EQmi z5LV**W*ovwY$&1g<<;JP2`NKRA{@>MCk2+z^#}i<*XIGqXIyz+Vr=Pos!_PAz?3=E zSp16PamvB{yMhn@7ypNY>2%6lZ@noN^NcfRcF1kaIICFe_jqt@iMvlwVsOsz;*|}U zjWBsZ+U^35qAd9M#vb4O<}2L2f544T?vl1zbl3VAYgvmGXLtIX-RzO&1xiY8+&kj@ zlb0BtjF|N!E_4MO=TfS9#f_ibr8wT_Qs+gkKC{E^Zp6va5reiOjxyxQWS<*d#AH9#+MreblHZ?f*=_1ddyaX zJZKII83LZ#@UGVGH!N2xB`*!)U9)My>8wU=)LC(G>-qJT-5V)9lTtnZtMtnLKA{K1 zxl^o0wWC{~bE5uVK;f6=e7Dk~^ zt#RU=!s{F7yt?!HHcn{l$qquMux-VS@rQIs&N! zHFS8p=J_4gl(?!wYlYI1>Cq4=1g$utEOW|}A?-7}lv$3Q&k=EqPJLNiwJ5w=a}=G* zFghS=CCE7PrJSeMxW8=e8R8nps|m_zLd6E%UbUb?fEJeg@G)XKM%aqVROmDT9Hy+i zdUTD#TkD+;6=9GV6wU>QC2kRKZsSBv2C=jWwSyYR5lSmhh*3WfA>gdv!Fi8R1Wky# zcSk7M;QUKl19@3tt!1m1@Rg^x`Nq>*ym-D#Pa7T&r~K&MN8ETY;`ZYykEbQG3Ua3? zs^vcSVzqHo-YH}#Hx+`+I%ZWZZVI@{^lf-0tzk-7cv; z$N%}^NBj@JdXxEd%53cg9_y4J{^}l?RpQ=6^V-$t>C6?jb;9BC6e%Q8e*lqQ2~266 z_?o`NSc|PJ-56TRcv^cr8tsI4^0iKoD)Bb0s+P9jmPlbK%gkwKgmfjQEGhGXv(DMOgIEDEYQ{O?8LzO$f3{c_%ZfVaG=MOG^i{t# zlx8eKSgLG6+;02jWNRk9Iyw zP)h2srs|$ag^n~zdG@d@_rw`W*I-FFJ42bPcT;?MoR+HK^XngUeI9^(#$}AbS|@M@ zgrYPyQ1|)6{*)78?Glw1OJ&u@O=*x(zZtYrtPj@3SHJd6gihGl*ubDUnat>PV)qw6 zzaxKXV3zWilF5mA>R*I6NkaH0Lj! zVY1jn2zYeo9-{;jAFVfjq=l0_X>%EwBn;q^xoYL>a zSS;^+^pN4<0dcE^j8hEqbUN94B8_vF%@*JsNjnYovc4Z@73B~@;EVx01#XcSNF|Bm zC@>t=2UIxpg5%Q!Hq^d_XcU8+sZ)Zw$-9|V2X)JE6O67pPb-e92uPZ6{*-Vmm2(}- zgUwpUd^pCI746Ldaa*n2FE~dlh#}532)qj=NK#mT(nufp<%Jid)KNrPmQ>DSjAs^; zN>P?RlOdH42&Ggw;n8DYthE$njwA9)?UnVxhcHdRRaTzG#$jo7yUe2wwv^~F zr#7rrKYZa}2({3z4hW4GzDfq`RDc~FA&P?h;1TK8F6hw15WIt?kJT=Nie~=A=}d;# z)>t~b)ImZRN36vPRvZ?81v1Ukdp^wbsQ|HdYF08bs~M72C#k08Z5-?1%xd8fRl)q= z0Lqf2ot_dk1%a`qepBkey~s;cyGOjWjSZQHW~tP-Hx^%~5wcNIpwa}BrWCUook)3# zSL@3rRHSi5jvb$n4M&(PN2M`qXSSG47c53IM5JkNZ6RANjByQtg;Wx$eeJrfneSGE z5K#x~%duRBMXQ%beVe@{1zK2&!$&YaK?}!XJ|k(hg99d6%rf*M3!f)3F6a{=QArzw z#^JDOi*$Pzr=x&)LrqT503m?V3h8QXAU_#R>CehLt&&xEAY>UZDe2MfqBNAHVZE2| z+SA*7|CL>y+if$M&Up8uyIi|}%scm|+&*#Sfn852uQeo<7k~53&;hU!K5#GQ3(R~< zdvg=w2%K9sXe&kSuV%m^ckJJp@%G&bKYaHQ-+X$V-+Jjhmv+|qr{DiJZ@hn*y_152 z3pt}n#$=~Mss-OZzfIC=arE(stIu3!I$f|RDpZvCV15M@u+BA^<+`C>NJSjSEaqd% z$z3+qG*Q~8j>;4kV=An1-gkEnV@f23@xc+3St0D;Di%T1ZqeD^2#VOgtg6flFqWv3 z)=&@#hbeNb1D(dFz@D%S5kgR83xBqDLkVICsC8f^C@bUpysYu;cvAVbmF1qjDUQ4l zVE_@FDJd5@X|Lyher5j(;g!PcUPQmYeY3vrGhGHh^3!%l_rLp9-gqZyNzx4XtiUu*IH-+ zMP4x-&nf2%Hrf#VnZOH`&}^zbq7c3M3d8MeILm?HxGGu<9(s32?u!x zBV&H}v+Ml$-8~+TO0GWtGK;)mqZhN$mfZYc59Y@VZ(V2c;30PH3lzr*kB_GeHa2-; z_dM6HP3U(t8*4GHjClXrO`iD5)1>8y;|Dn}Jb#6wuH@l|2av?Hc6M=Tr>S49Pwd)( zx5iM+Jpv!4F`s6?Yf4H2+Gd@j$P4DPoFt8ik|;PZG{!n8ZY&)JYn$N5VQ_VdVI{-S zB->r>Ktf%YyPWD}fYLCnNa>LuVV7AJ{{t+u7XDr$c#5tW16aL*GyZ_{b*Z)~GeFk- z>k@}Tx4M|P3q{P8r!I0bJmz?Kh)^-82r7xdf-M=Wud{Ks&))q9h@^uN$~!DlA(cTy z5lBTVBx5Q_Ak zzn||c!#U{o)<9UQ(J?B^$sRu>+1^D&t(9`7dbf#{%#dSc4DJb)jGRsksCQ6gPm6`L|rlq6Ztg+R55Q49j=OiH7N;u!Yb9jiXN}^WcGaqKz zxL$>|DuqBg(TG;cc9(c_$Fl%g+kCupF7#)~5PW-0AF?^cVouy{(K)k2HXLFWGfw~^ zC6)1+$yh-)IzdU$?HFq;<#>$E3X(`*$_!=`L@PmvpgmH*)2Cp9dYvq@Nt{Bh-OBu| z&P!A7B?MX+%Hbp2=!94~@qNJ$Huhy>gD1&b2ui z9`i>(zQY^0$9!^-F)lqBh>{X5>s~j%*YZUG&pI&S3gGRi^B(6(k|DZ zF_wHfCyryHmX|IF)k7>6h7StIo#8&eym`R)zjU5&f9Xk{{N9(CmGG16Lv9{SxclIc zN7ET!-R$vTIOp=29#_xyx%p_ykKew}Vm_s{)#9D?>}Pq?0HJ-=y%&rV1?ERX?u;Ex9`&H4G_hUMQ#vM zHFmh37h4&Gvp(2sN)$a?leHF|#4DhnUtl(nokWp__%w-y5Wcv}YyC(cFo>`|!a9(F z<-(`_o_C!d01= z4i8vc8<9j2!;>N1^*uh`o6z2Qn%3GTpL~3mtwD?JRFX|{iYzBD4S)H@b*|lbgp-nP zE8_8R%I*6HO&KRrU@G5xA_E(o!)M!_^&oLom9)Dp%w+BfPw>?Oi`){~lC`xConD)h z;|WDsB3w=8(DVd3=d8yQKeOrg^Xvc5^?3mD8J97Y@WHdM$<*O+t;!0IVl3-`mriUz zyzA8b3gQVgh`X<;kJ#L~z@oJD`x^+EAR^6kPhS%0e$K65?o(Jxq$K+X6MpvQ2fX&x z7kU1vGwdIZNg_!;pYw12_*Z0=r+Uri8FAWWRBH0cjKfEd+1%M+c7H}zLNz*~I66cr zZy3My%5&_VKg%M|IZ2=7#z!~kUwM&dUwD=mRK!}h%@6+cr`RBr^zAQQr6)4}@X<%y zpWf#i&wbmy`n8wXKgq>gA3tW1l|)LRoaNkli(A+4aJ0A2?3r`izw?muyPF(5JmU7P zeUhN#Q{@G!)x(IDAi&l734W~7UK?2Un0Rv@lG?!$UPYOeRzCQMbx5}YPEb}A&Ki`~ zL{ShLteruih7^mu0315<^~E*Ku>W{RRaBUwLdE`bsL@bDrlVd5;T;gdH!ccK*=Q;g znsEa&N=FJ-c9k?Z8D!3v`(9V%38}}G^WZ6 zI-48BwL|3ULMTU78M1kfF%~HW?ZKv>r;{P%8O7l~@#Yz1(xxgc)x1Dz9rR+{ieP;h zo0UMa3HIu_T;1^XUS_!*n(x>1UREqdQ*<1o;@CS}E5QeKz-X6s#PU-mNOg&tQbAxW ztP~+EvMR`iN4TmWPQAjp2%NC8MoRJ2qS6IqHp>uchh%fB2|nrozD9=Yw{jDsO`4TG_3}ej@4zfER(4nP@HXSl(m+{ zqM#)lUwwLq-+lQUU%s@)#Ic#~&YaZ!XBJM#vZyg|!q)Q=5FDa}FDo2Wfv<1fY=yhU7 zi+!ddWmJl$574hILEK8vS`uqXQF>cookh3OQzf^e=CG~jSb&fbumry9{=@p6bfkkp z_x%Djo1IA0kl{9sfT^D}pYd|mB9vbv9t;4a@D&vzWVFJZU{}_asMncmK(D&ImRfzh z*)<_+;#_mCIBPHh;zWBPKonJOns-W)h)DYP9?cEt*k_QeWv$=mWL~kpyTfRIpXsBA zP*ofp3eIhJdH%{4631FQWlY$gAThZZN)w~ zw6$G@qv4R_W4YWrb~#3)(U{3(7J_!)c-~9>UUE2!`4r(St<-1G7C`{h`aSKW%du7k zA?4L{?&sIv=lVPV`HZXEPOa2)W36{6goHRreIsEVSiq^net9@8>r3maLG+!as*EsY z>6Dq$#n2NGi+qSE6{^~#SQJfJmkZM5^L*WO@2 zl%~A$%o#S;Qtmvuz*@hI2HMLYR`o6*vl7vY-_^+KEJ0 z3ny(Zq}3?tYr}0-Qj8Cr?g$YpfiQ+@F&49fyV!+AOF^Y$(sqZeFueESU6M$0`N9_2 ze2#V%Uw+{-pFBA6Kx1VPkw$6V)Z{}5(pDg2AtgyGSq5^v@dgQ9kD-@+W0S;69XMB4A6da6NMYIOG$ zW0G@Cn%@E0bU{A$h+(?c4WC_?3y2`L7tmm1n>urWqbv>CXc8RrHD4kV4&P?YNr8x4 zsO|>Oec>vbJ7?HAf0^B9CF9OjGLb@1q1U}3=dYgQOE0}ZXY)M&^PgX5VFXd48!d!N zCdl3{UwQ2^Uwr9{+`K>J`eGA#<_lz%^EL0TqGhIBxcU^Yz4(OKzVaOZ%b&c@Y?c$Z zBb06}5q}{A15Q10%K%;A%Uz;Gql_2!vJT?)EsPM9!$Zh&vV(on?K7BCFulJ=yw;<& zv(p^jwhkmdg{<4kVDb_jYjl{`CP)c?x`3SdOcM|sy4ndzx?OaneDb7el3tcfIP32- zpDe&xT5Fw^d4gh|QB3E=-8QYYPRL4tDl-;`2Ve|wr;Rm%OGyTHFYBF2iO+;!y~4Td z^oTchutGJ|!(zog$q?8&69fqtGn4~k98sKLOhq{v(e8FAYIIi6WK67uRyV~Oi>(Yc zQlx_}c~xPv1z=fBrpU^m*EexdvUEVhI6{+b@_VG2C>xxnzz(zm*sNj#4$uOsqsO@8 z17d||e`*}IkmI^=XmX@Ek?s*{^&<<^EcOzxHE=ACFm$3 zlA#x-$()KNQ&F?2#qAVlW0Y1jJpg#{Lo3xhtkN|;)s`HO*>KyV#!yYKEwNaBdpNiVDD(cljk?d3jUWmV9gAquL$U?u%$RR`o z%J)CXpfc|ntONq(%Vt*gqHuUx+hA1xRz9)@4_0hZ9Y00x08(LvL^$g~2pl+zQi^u0ndb%* z&LE^Gh^U?;XxETa*meQmV4@+DY9WWwYmmy!}GokLiRg{&xvt74fI{d54_ zIEsW?|7A~z|L1^-34v15X|2U*n!CxuFgCeBcqMi7$phZ`@Q|wLqX!-G@bNlI$gJeX zgE9HZ3DPPPku4TP_B_2-%$18<{LS09>BSN|A9Jw3&u@MG zS)ROn2CX%3zyAsMKE6g<0G_9$pm#{~;uR;>`u-D-T)F13YXT-w_mL2uyLkm_chMg(&FwAJ3?aq?@!*N??_wwbsR2M-*$ETh=`Lv9c)Tm6&~#wJ$9*R-gtOI0WVJ08vx) z_SZ@JYltNE%tI{q*ryr95Q4HOnI9h09(0MCdhpu$aHq1G^?oMLC>Jxdj%c;o=s^d3 zoY&|LAl!0I1!vTh71kKy%Ag`oP3ymJsEQI*R^WVZfGihehX;tdk=psdE_heinzmVn zeiZ9`!+EPqvb~E5b6$fWb%xA^^{3;A%vzL$#nF)Vpodb5qR2^-2s@vXSEUbJoMV1G z@+Az$U~8IODY1CbKr5tIdKVsXb;eT7=2(@WH&Z_cwM}%(UYFIt&REN0Jfm7QRgP?yS5`<8moo$iR?R9X@*T4&@uw{vjTeNo0 zVB-X1tk1AYL7YTL-3u8{w`57G_x3U+vPAjoF%Dyn3(t#pJoBOgA^5$oKgB=&+GVsY z`IDc1!0Xrc*_(h-2_jNxDMAqMmdmxVXCbqX(_7R403ZNKL_t()yki@uacyE)NjWqC zhix+Kg!cfP2xJ!iJzOAjl3F2A%{xc|owXi%J>k#af6UvTJmMdJ?McpWcKPj>FQAf` zNp5&}G~?#|69%0Y@7x};FrF=FiO2<88_KbKm1bkmkWs4v3Zf|Gc#)ArF;AZF^Kbw9 zBZ|DB6-y?M_OXQ|8g#r-v=-rfHb){+I&4a1lW}ttGcY# zA(rnO0xJ)WI1frlL7GO)3b&$^ZmFzgJP&|?4Es+=7J0?u@f4vYLiwPky?c&1j>G#8 zxp3t?No^N{$qae*FR`e zfh*@oXF}$`B8n4|Ry*|AS~f2}&sV=+0KYI^rE8(QVIpd@dHHEuC7;I@+U+eKiXU4^N z!bT;KCxU)n^4fVxXJ^}eaBm{szIFpjfs|1|h$ObiuqLCeRrkW~*?;ms{vZEJJ$!ud zZ~mMA`oFrt=hwgY^?3mD8P{Y!r!qz=rI1>X#1XEl(NvZPeto#EI6TWn;nP`>+A%Jw zilQprg|nL^aU`}j)+x)1;b=0p6bB(=^9xy#TW-%LZ>;8~MUUBgFh_z0N5{~m{`+V*4D=rl!cdor5WIpHn z-+774SDxU}6n=f@glS%o6^8y`jW2!mHOi_YJ%7Z}&)%hbd7GEN@d`#L+G)&tAKd5U zWWxG-m;U;I{ry9tNU*iD!)RLY(|7k+zX+y-BSvPrxN(kn)PUb%|E1(`tUd30znrn$|gwB&~I+5pUnzz9MXeSK9U*ugW+sFXC?QEgnTJ*~WO{0r7XK{9SkHnbgX2&KKX{?C&PLxKB7srtG*=VB znSpK^@!XXi&Tq8EE6-fwkN^5Trp1i7+o3{$E7@3U@xtY8)>MXUY1X?PZcj3lvrTVD zWegi@ZJs>0!OmJDzVh5H7mZJohJ?S|eM7wWnttOg-M z2$a?&y*5M<#)f{J+Ig$TFQ9}%SVWPL9Xv)>1%-9U&24ml-B&qLJ3WChr?L$XwA7N; zTHBW^#Su*p1CCZF^*tm>gi->^e93l|ra|;BFeruKqjun>1&5`|edaUX+Mz@=!Ea-W ztZf>XIc{KhH{*%YTf+7}sQNYNt@vr6j_a*hETD96rXLgy19hOgs&nm~$XC zQpdj6CDyd!Chnm8sjFxQK!zD=dIUi zpeq+O0J35m36855HCS=P8}uxU+tN0HFV{KAEWfxphGKyfg8%HdzQB4X<;zz#_+S6> zIzPL9h!vWK(lalkg9vsfd%ZfNjc=@?YeDKLb z_J$d{I|${O!JdoIW3*zs>vV_L0P?pk%Fu6DYdx)=(|5#6~!xnRseXc zMG{Kw>TH-32qnY%Hohr6l*xJ^Nr5o|n6Salhq1Aad@?3kA9!6KTZ1j3pGe?)K|(f( zKw9EL31n>tEkXQ?X7{@n+p zPhP}oM>~!9FaP=Pu-%I&<|EXjKJSmF96!G2CHb^O14%nZ3PHJ;Bb8#U72%Rjhz#o< zMKDzb7;IJ2QFC^Bi0^*$>wNFGzRn;1$xr#{!;jEun`C_(<2<#qnT>hrg)N@wF6bs1 zYlBU0-oDH6WXy@MeBs%r-S542RUGWy=I8I;fwYUTl|cAXS7ALt3brE49ztgu)#-8Y zU`SD9lx0Dy(_?FMo85HA^uaY2bP!P&t6~u)v5?gQCoQg+CF|Yf+sVbVui%Jy_0|8D zx8C|Z6Y}qQeI9^(#xhAT5x2KG1*AuWrcB$li@MlG~)0$ zqskH%xuVrdFnPwq+c&AooYA8r-0T4-4<_v0NT{r0b9aY!JEqlX^Np`P$HwM>oA(Y` zYenqtZt|~x@FwTB*Z9uYuJXq9V;)a(Tvm`B4bhzrX}^yQ6o#v8IZhA`5gQI=k95~% zM|Dsj8idF-2TeAefe^&4v{5B)90zLD&{E9iID8GUl#(b8>{ImtD*ORo79~PRqF6WR zf6YBEg~D3HY&64`6|H`oC|OlY_p3rmiHzl`L%MOwgrJG!1*=YPENyOAJJCCTdnIDZ^X`gilI=T|t?h13lP4;3$VjjaXr8X9pLzF+l}Q)Q)Mr zM}xznBaPnZ`(UJ@PNqSCU0GuD!V6O+nkp}#GN>rRmKFITBkg&Z)z*%o5af%@Gv0LD zM5%9dt(`2w=VP5`F={8MH1ZBjnUfzr!j)wcd^8{iwRgJs93Eyh|3^GOGkP17BYlmDq z^MK#~jVG|yXTu6K#tLTB(mTM$P~;^#i9O}AZI;rh%Q=S$&ERn>rLG82QZOkj)5kLu zf;`I^47!|u`biGQMH4R(GI}yJiq|oew~awu5FeD)Wvi?6X&W1|ESV#W6Atpxh$vF% z&25Y`%~>Obpvp_6bG`&FtUIr~?Z{4!QE@`l?P4nf4NH}8gjSKp$GaiCuztNI-L7Bf zwQ^&486lJpXr=#qGq1s3`btGf8Y@x_i`-!FEMvwx)>1*g6R{{A@*n{@je4!^!k zW!PBn^W_(xq&&G#DYW~`AO0EFKE5rscQ3M-j`(-~?%&bwbQsMF;zfq7T1c!fp^}6% zNFcCei^ARb_(0saUXo>b$QDV2(ERMzw}p-s$}MQQ0#VJ0WJ-&eZZBrgOE|joHa{)* z#FZz%&~LZW7k>XM-`@GbTW{_C?N$Hz^;y^F0mx@uYn_%6s65>8hy9^9W~GI}T8n@5 zo6n=ucBAQ0RhG3>lPJmY(FwEZjMiEYTUmbj(LVF>7;Q34W%$wGyi1kOp~%UKg5l8# zzyG~&FxM$>U!RLAFPV0qC$oqAuH((eop0X&4@lC}(3jvf%K>TTJhM z!j=AubnGQ^mvH~q9nL)QG~G^0nnd*4F&EAbI6R&sY{m0ew|VOFHWx2#@y^ZT!004# zDhi@uwG&RGrBIKh3&q|`rY8alN+?aL8$kn_C!i`TvU!FO5?$*N*w7SM7o#soE=X&O3_Enia4y1Tw*4T{@P_%LeU$ z;8s9jxM2nT7QuO_>)uyO3F?RSS|t*sVXAuk%OCF(Ip0t}&lTu|>|{h7wTa@C$C=@O zdi^o6vc%Co<5D4Y(xA}3d?(@2VvGO%jYmw64v9MxhC}j{+kAktjD|-f(y@32Ov@kY+jHb>_buDltyiC_-6<~s&TR*PH2WbthutNC>A*? zj?t}Txpv)3DUu9a|JM27r&usQJV2U~IOtc@$ZV}S;{p?pt18O*3}G!Q?otTNcv6t4 zg0$DhSxXu#A}Od$po?~v;n9?AJYjuf4Yj#VF`JV{irtMCgKo-nmVx$)<9F{oATKIU zDJlh}b=a~BrE+zEFR@k5bXZ`WrPXO6oo}d@N~4lwNdnL~ddooY6c{4}QLLAXI5_e) zWIv>E2#1$j9Cu44=R+TDk@4Hk#6rooHPQG%Rr)b z*8O*F2sC^K$FoV**{j+~7X(UOx3v303Kok3S5|!g8_)9lUpdEzw;uCnzrN3%`wL3Z zp&KX7nrnK7R@PAsq%866Q#%`Qo(<4gl5V@95+|(XGB3eePhL>3bLYP=q#%l;2B@it zFq{q4vSHk;F_c-3NFtI}!YI@H+h0E9ne&@;TM=Kpw9dE?y!FWuQ4rTN#&{>M*~_k3 z`_1!*zsB9xaxV&et)LV;U@!rF>FCFBtbT06O>4iA}`51pLy=NySlsP%Br09 z-ZA(gB6emS5f`GK&j$MR>8z~Gy<=FhzHhDdtw16uDM_WH5wVlHK%&Sqg)oLenK7vh zjgB_1ZTIQ#NeG(8aC5W658mG8i@gz#_Rsm&%NtDRhWYI^)=R<9e*Ot|a*C)Yy!(@1 z@X!9~KjYEePq{cBQCCw2{h?P7YdgS;u-zA=lQr7cRY{+!CqnIxQi@;y?yvGU|JL8( z7w`Uz&p!K%(dj8G8+WLLBEhh|JwVr*v#0l&o}F-gdz*t7&&A#QkH8u-WjURVIXpT> zot#kQDI2)}F+<=m!jURTl4d?yCj^O-!rBR-7z|49BP5C}jY1}d&7D4JB2iM&>vbuM zoHCVUN?;~u-2d_vmE;Vs+!?G5R|mk?0OYTEeGNc<>7_ga;qZ;N0_&z^WLB2cj=plh zUSj-!*h#r{NI;yOU+_nN{3l$D&cy24IzlSuE~U4AgU81eY5yh$OClw+i<+PP{2rZ^ zK6R~`jmPM^CQTHx#&L9XLAkm{v9pVD0&>aD`Z_P}-KW1&u(8r%@A(NATCuve%Gm@a zvxdL@{cmyWrJGpi(7*p99^JjmcYgZ^+9?eaH&<283@qZG5_ z`#kybJ-++;E`RTLzv<>S761CZN6d^tH#Lbfl+q%U;^Fa}N?U&OSMRV|CiHpY@N7=4y(ocTDSZyF(=UW1$-OfaJ41)fK|Prk@}*W=s$EkxfHhmJ7wKkTT)$ zX$ndJ)?nr}WnjF{=-9N)0{V7-Q~;u zDPQi5c;)(#-+Xz<{@yd@>wQknE_nO3TijhM`Q*VNTN^9f++E?r&mQya*$K|dHoE9d znIcUU#xw}4!D)oc+I6@n0=}Hy6AP(ZllYa$)^eJo6c%%K0>=j=Smt#oIFEMJ;v*lO zE@Va9P1+jM0!m#Qnj|CN+CgNwucKiBg5#e{;HdpOL<9mviM3xYxcu4%g`Kd8tJ;v@ z_`UDn;`Qy4|MySc=f_WG%v1-L7D%mq%9ULH&P7^~SL}(kTnmRia1I`P2Q@2GYto|d zLhdPZD{LL z5Euay1DNpHVa!FaCAdXYBZ6D2eNl@whWdO;R^-SsZ-JK68a!^{5b*# zD)9|NBN2dTNiP``$6~FQ3sH0@BqA*^QXp(RQT&h^W3e`VUI3ASkaGBEjDj4_Xu_ej zWHUs2et1y?8SIw->8#e^6j~^>iS=ua@yt-H6oky?_VNMkD3-8DSYGR89G+aT*-xnE zDZ*%OZx%Fl!p>@k`=3gZ`6)+xkKHF9zb`teBTX|dE+!bQ7hBp{FY^xV8NsFTq>aKj zV?auZEaT?&tGxcw4gT;C{}m6OykJsEj2$DBhV{)=hMA>yf)k_E$ZgkOsONjzW&~Tr*t>td#2K!~o+!s$ea=(xI-;ZXecZ~qQTNmf@^P*QL{HRQb^|MD+C;k~1p z6pJx)s;c7tlS6uwhRJA*)eX)xSZ$C=f=CjQULOrOtNF&wEp~?)&({n3MZ!xrHu*>Y z^pE+$_ugQ8XOsW^AO9h z{N}6c92_1qpN@HUFyYJnF}=RwPS+o#J3H$_a4LQ?ocTL`Lo!{mI5N)oz> zM5eK@QnZZ#gYSVhOF72L)r1p4e4(bUWi56CwKGVl5B!{M-9-kXa^ zh@YdDca{=uy~Hv&(p-@w0+S_}nU7$I#23!vf-@<+pg~q-BrbyAh12a|Ar#;oN(q#y zm>=vTv?ePHtTVpXfLk=nbk+lTnIvA`6JKcRgu_}xUPy|5$xI||&A{R5jOnytKAW@F z&*>(D@4meY4sPxYnAR`&;?Xe@$BXCteDTTW4A)lp=)+IxxQd&vzQ#Lm-DW{al(ZzHD;3XjiMPiLcq?sQ-XZ`EeCzD6$>Xz2_B}&FEa`{^)6Hgi_0s8C& z&WOm1St*ol{G2 z&cl$zbll}SG!YwTvZw`VNi8Wz%Yv*UyZ`{6xtI8K!Yog*sk#(B_UkzF>s%~^JY*nK zq>}B#cmhMAT1VM$6D<;ccJGMad3&38uCMa;wLW*YI=uh*oHS7=6`VKcg`r^4#L?ju z#{Amx-M3@J$vb?m?V}M*ZoK!lek+niV)>~YP2<}8_Dv7%(t|A7Ugx`Hr$o@Q5EzJs z=55_lsHq9vN!y>bdpexop5*blX2v?Cb5VJ>J?~>phaUvjMqL(-W0!7MN{k8hBcX1m zm3WZw6&dC-%x}LP?yH zEwNylDu6x_(#let@I(O;8e^O`TGX{>Je?zDkNW(C#z`iLqnB?mYYaN=^5w~td%yn^ zQOsXZO^y)=-gx76UVq~)ntJYPZ3QwVO?+2#Ya3rTSr#P9ktI24mSRkU(*_~Dy->=h zyBV!xhBN7FlfBuwAL0P1X&Sy;L za~?c9_4O(u@jB@t0-%Btk_`-9(&^#^%xBtb-)9*(>D7+r75e;~G<1$_PL4>eMRW!s z7d##s5s(Bn&3VO<$Z$I0Jj01EDD(`ZxXe_>X_YZ8XsOVaQ0xpXDsaJ3ZW&eQnXY9H z9%yBj37}{hSS*}mh$mH`RwUAhle9Fm9p$?AqCDrktaOg+vDKzLu5VT=_emiPb#s%CXKV19B!y1GWuE!w>xgg_=KDwRvBSIZ;f8%+w~<%Qe5)Pk->ZhLhx zp&m~t*H`Hb*QfwP$H)KVMOhS?IGQ})o7iB}z?O>+`dOoF- zrzq2K_T(w1X?(hgpjF|SPv)c{O{MiZLNujKxr}qVobuOHOb+)Ebroz$-Hw6Qjc4AJ zcP@psp^t_P&XB}cgGj89{?KfTQlV)Kv$|n)G3VM^mtimC{@yV=>ph+wjw!N)Ou@yZ z!j_ufczc&y*LINO7wBrj(ThW>>6BTe`QqMlUU}t)SC^8IBobr1nvcRFqzw&O!{Y}> zE;8RDFxsAlx2;p$MnqcYYauk?>vBM!9%E0AD5RyTYg#8TjDQi4mR&?vhG%z}5M@(R zVCtHNl+Ml$WHD#oQO|4Y>7356OOmQEMGK(V+6l+PR>!p>B6z(FrfO~I<%+-at2Zc8 z$N&AKhde#2$%+z{_#$u{$3`r;;Mk8N;_7ABIz~P1((C@c5|yc?cLLS}IUxmU=-m?y ziNgcB7)@4lNs;cKjEdVKHL3_Z(JYn$&)j%s_nnx zm-v!%-;SxH8c$JaLecHSZS5K8=^T}$WZl9y_zMQmT8q^cQmNJ!IO|iytg&9fYpI8h zL_m^|3+5W+^?CZ}F}0J} zv_o2W+3-BiTN2MLtyAX=QYw`2X`M~gpq*>`Z}HjB|J>bu?}x(FJ({NB8*jbAfA*jJ9#TkQ5eSu$ zX9>0TDufUus>3;Ato7sKygFMFNEM}20LFfLq*8#OZVbj6yppr`zf_V?76p%=?oIy9 z&p$YV|87y#_4W1de0>c-e#w=oObV&2PzfNgx+cpq$`Iadt^BfE*&bNp-~PbJzT=Hr zmgii5={2kqY;JBKWWua!SQ!qP{_HcJKRaO7B-q9~FxhYwlVuoj?i=J-OWy5~u5VDM z3052G!vi|a1=4Etd`6}OkM|D2Xny6*+x+~4`$#2u`OYr0s^RUIcUZMKlk+Y=`!mDY zY{omUT;;ppd6l=vjvsw_%>G%0wy?D^VCTv@)x3i20sBW|cCKIJwRhg6v4T9$dGz=I zQ_Xne)f-&9y2;%K`#5XaUhnehXO9@H^trOT&i#9POvlpzsC?wW2<02}CH|0&O~yzI zRFdJ-k76B&XQQmu-Vtjw_0b`eQ?kt+WU}N$yT}lE5V?dCX_d)jEPiLnpauZbl3|Ow z2q&Ybwe(?b(V5)E*N8_(%-0jQRML?Mg^sjw?xI$ws`t*=QYnsD-^7SorEt!tSh?PENFJ<|Z`06~VM3LnQ zwg#sg=A$`6c_pYgmIz;4R86K>Q+TIOv2ZAf)8^WH7LHKRFKEusanmVzkz$+5Gjzee zgx1}jc}8NEKGDyyZ$P$4PR?iKnPNWkj*I`kSS0N(gIpJjxjkO?nQ7iR zsV7tPY(_p9kQ5;zxulmW2(qLS^w}}y_<%w}J)e8f6P37}!wFw-u1c>k7JK(N=SZYP zSDIR;WSiTNmzTsDRGN^Mxlj3tDCsL#Bpu>*@=<^Qtd_yD6liVf7YW~gYn#)_oZtWC z1v3q4QD7TG49&C(YmtbG`%^%cDW5(SA_x&sEvDFiXDpJB7Q?yre=n_PZ}XPOFR|!@ zbZIZSC1*RHVZq)we8bIZIwQ+-@@`2(!uyX-`0clMxVoC~+La+Ios^TA^I`=o-EaFj zv^F!zGr#BM@|Oxk;u-U3i=#k@wT9WzkzX^}u$@PvE!A{N*6onxDy&I}LCF|!b4!C0 zqXTy7wYWBgY7s}crAS;YY;o)N6TV0gG8zab*OIgm6i+xfDZx6D@NA6@QJT2s!~Z*H zk;bPgJ1LfC*cXdO;1Lz!e33nihKDhl67E%n@s8cW7qxIcQKhzR6OOaACzqlajcc_kzk&_W3gO5Ic#B4HSW4+5uH#XT=8}RAp59oJuI%UaU{P=yY z-@L-Ty%VYzcbSb2xzHVIY5B9Ce!|1&=Nyj>`Q}Ze>X2uGv(s}PK72$y8S&umedhaL z@;p06)+5fR4V$}HxpnInY2vtZZI#uv4y*ketPe_xGUM5cQ~ty6zX?k5eJtYgJLg znc@F<9mgdmRxBJT;q$56nhz24zG)>tms0_paF-4zCxSYSa|D^11%nyc&!vMImd-W4 z;!oIEyzGBh0@GUaV1G=bU1<8X#5WURMf9bnCd3wa3 z-<$IB**%WkfM5BQYp8ix&n`Zre{Lxy7Z+3Bee@w6Ip<_Fr%Bd1nZTF#o}i04l_^OcY#(nr5P@-j@;xJr#?&Zi~#P~72AUH}wK;A1!%iObl{!Qd-YX~K2jt@z- zp*lVw@2%i^rB73Igy`4e&~Eo`bUMS>&Fcm!C3%@5oI`8fI?73wl6E>|d63s_>vCk9 z^A0c{Pce~)c8im=}KOhVrbYy;LHQsvci{888T{}Azz4$ThZdJ@jFdNykQhI#~x z;Dh@o0Ng*AFmEi@2!8s-2`jyflZy%`C8JrxCkN;JJ-chIuj^^f&QN9PJ5nz@VgN#- zq@@|1wvmsz4h_J>B8^1|i7HA&RF-S^r$Z$PrfH~TLb1I|QkH0ATK3urNQ;y-O9M0P zF73&fnzURD9Ep*3U9hn0)>t~3pqTt#w!^V9}081XTiB<+&*3 z>tB)q`1m@FM@JK$old#3+F^TGvewHvp3TEN`e$mhQKN&53n?y18)@)>!S@akAv$Ah z?BMNT8q9oc_5~bRDKIg*RCJIwk*rp-vb}>O7UIMPE5I|OxOsmjC>{5D_Y;AUo z5+;G%GAyD=ag1fCON1b3!9uiQfr%DXCre1yN7R;l7AHWegwq)uJvj5qXU_5B{H)yr z@_ddF31_1b!)})=yH~mU`A6dT_$2ftioISuXjC|iP)Oy;M6Gp*jD>oTsI-TV6q$O; zd+&cJZ`{63r`P9qfA@F!=YRMM9vx0ey92Vaq?$}{(+g%tdyLLbdG`1&AAj&3liJ~A zD(15pRW&2eqqMV(oyq}2OriEmL$=Yt<(^z|kHzP1=O%y@zl@}BBpLQ1&PR}3)Y1O> z`fFcb1CU>GHO@J+RP>f63aq?zI4rYN@oIBdp{)_||L_hSII=7iMNv@nR!~}_IxF=0 zDQUl9Wp%*zyvLLA0Y*5w!vR()n(;Y_v$(4AiX6gHPbP?}LeDOc(=kdos(HzIU(`e1rwJym}xTl|jXx7cGuU}DQwxNC|7)4h!8=&#vu_{;T@QC zWsS5bX-22aXH%4|vG|mMSjW+JxL%r<1v|YsgghhUyF*8i;ethXMCo38=@3VVORQDv z(BN7|xIF*@s3AHv!6;rTsI%~pK!F=;l1+#qRO~^a|4+qUba?5wlFS#cS(h)O%3?U{^2Wg=ComcatcCFtPH(G ztn#%ov5$%aj1y!lYo07PIV5ci?&6gG`X;vUYFtq%?JM+eaIEob(Ltx*MQej;8gy0p zln<5Quq0VVf2i6Tkd~p0qDz?eGoEe8V%jNXrlsDWI_qZ5(U;f?K-2r>cj=6PxlTNo_Hmkg2CnW+C98J-7?2eL}Q7+jM@72$vl#mblBt=P{ z=ZLVzMVMQG&mPog$Jmo&a^Yy^RSQ1+=JMbyEjzxLTrN55)*+O{Xie=D#l{w@D8ifs zr`*K?e}N4uNs*9f_c51kxnp^WEb18`bWPWmGL<|z9J6;c#W+Y*1lqBtU@->9`5HG7 zzBsO%d1XQ^$^rl_7w*SB;DM-Z?Td4cYFc5Nnl#V7GwM7OT~BA;X-)?V;>22-szD}- zEYDgyXlji$nl#UR&!musB@;#7@3hk8QVPbihQqTN&N|k58S4XIppIA&I&oYh`yAJN z>_qQvKpYntJ>pAy(VISrEKC1MF4k6oL?M$Pksc-~+BjiG8Dijt~c9~Y1G);UHP-D<;>8uDtr<9>V7lrWJ41ihG}bgw{1l zlF}IM*MQMfGoSwCjDet#hfGl6S+z0HRA}9>e{{yIvi#oP{ac7M=TF~zz(LbR_WI1v zjzn{QA<#2E|MDUK=l}CZy!YpS#z&t%L}eYiy*{6Q{uv*>_Y+oERsblw1J>5J$cv6w zqm0UsB1kkxAiP9&EuY14{l&c>uS3Z$%&!m}Al zWi)n-HQK)+S{IfMuQt@TaB!9vZtL(EO(HBCD;=c34OjYNQajG(69%cKD{Ca0q_e{O zVoZH9LIAaO2$i6MKEG`mWK%)qP#CoFDh^k!Y_PGh#*2dsYVFwG>T!I0$}6|F8T9+S z|H*xnfa_a*a&;YH9WRb%OlJ*mzWo-rZtl`FhCDBr&3)u2NfK^ucU*3qc(<@5!g77v z7bV`@R)};=?HpN=A*JHzctn<`7?n^N*vcg*qcNRMPPa@jMw8?{ij{TFCJpsuib_+` z!78;#Tj1eBKI2pTYhKowH9ibO2sbFvKh#S2P{=t9#cX3Ye^9Lu4E6eRG1D-rTVNfJ|=hYql z*$?kwtRu-(8(AVev$HPrVGyL*BErh5zwNM0V5$9<@@&6z zkglvEl|UaKqC#q3z9n(xAodC4-#Rg(GoZYOlIIykS8;Iw$v`&0dhQu8tH4>L(Y{ex zqS`eTnexRx7YJd=It42AH7}91ltTEmDSe)OoJU6}N)-!+&dYZCLP=tNzKiR5;l#&W zcM}-$+gm-pcO&8a`F$qSiZ@?-gAevg?mZhJu&fOVUfS%lvHR=X+UoND7ta}IUFcn5 zIPCJxH?MO(p7P+~3#OBqcSxfn@1HK*j|Cf=h+2!4CI*leAOpxdIfU-+QA~kw?@B>) zc7i@Wq>x@E%@`Y&j0NW%qogPx%YE*;5MKF6iqOryrXiu&+94@Qv^Kt9k0k7!#kEWv zMFb)jW_j_x#ggz_a_M!W4b8mfOgBtx>wCMj(GdVl%y#lT@vt!;18eDHdTTK5z-F{fKpNWA?-ng;Kk3QdLYfy4)r_U#k zPI&FgkWw0E(<$9ffk-oa;k@652FKxf%@@zkIiG3YTgvkwv}wyiF`G@@y)Qo#JF6YO z^Tti8JG=Z@Gv1%VnIrNH3|}K`d5GMeFYy4TeLL& z`ugi$UjvX|a%E|Xazbcr(ApqW>XesDU_qoVQ1m56EiTyjx?8aE{w=~ajTUzw>@gZw zqPIGRq`(Q7xhYTfM;NU!^C`~AKokYWP||iDcHy9~dXB@ORDv-L@4R`Fo$W17&Mpwn za_i1j{;z-jL+;&s!teanH(4DN%;q)kesGt==X>b!DNjEAoQtz_-v5gk&mU}aF`o1G zJ8!YG*5lsA1xKf2-uvmNLRM$o-LKK*b$wHM@(Pr(dm`sdB$2#^2W^p0?FsonqenpG?}w^aPFI3MPL@@ zLI7G@CTAB29NpC+Dx@)8is*zfkq(^porKG+9e-j<(e8tGpT&EPV~JPCat@lK0}`#7 z9~_WxNo3hWo6u=Iqz|}Q?HlfqpjZ?$d!s!c9AL|_Ttj1YOR^~n; z6IppFDB4DZ!6R=SQbVId^FSxj4OnZ?&Y_YNqy=HXX}^4<SpF-sPy?Kym7pX<~)G-mGgu&sCsYBrHpKu{NMt~9) zeRhgDKBN$ix|-v3sQGBqBR~}$M4q=11gnh)gGlOGMI#a~wOf>E=g`(N8;!s^x*Kb4 zO<8NBqdjSNQ){;UoGeASTZ!!O+cBCTL*%E;wU7T5cr`U7#sD&;X|j~^Njw`w=Gc9tRyQjiuoF$FEYUnUZ%isi3q`voO=?t$_W=uxRcB?U4K02>zP)Y8C6 z3ED}HCl$4^bh3mZQJ&G30%u|kP#_h;n6>I+EXG!cz9g>97f@Fm=+|8kUA@bKR=d;4Cj3Mm?+9ncLo~QO42TqEDrp8g+ghs#`x3Eo^gG%&*m^^ zI;+SM=`*^7m&0we<(1t&zwy>CfAG_X9F6KrMc~?afdp@x48n@gk7F^%3xzO&HI~{b zv=i;?1REeEymozsRKoqk3%Z5mTenv^Jig%N-9B&KSmC1whn!wa`QED=tiHC1Y^Hqt z(Pz}B&&jD+-P!?_VO7pt^=V|um1`Ruj#4hBl?P{HQFA2(WQpS0vkURx|1bZ9tLrJ9 z^<6%{_n5=y&zYDZ*alIjKH{Y%$doM4=yZD|Y3}QJ#^*HCF}j&yT}Dylq*B4KED+` z8=TK9`1<I3dV;-4G^KNHa%Q zbA+&Tij1w*E{8|QJh=ae*<`}?t6O~b#f<6PaB@1P+bLNacDdHwBGp|Ue)N}|kDu}F zJKy2eH(ue%(S+mi6d`krv0S^dL8tc}FJZU&2IHT6NPcC5oo~L$w1NK0fbp#1^yHiu zFODh84tsk?Bw0q0XG|t@_710fe*Xv|Qlw01j6oT{5Jl!21;w5bqGj%u7&SzDkh=)# z!k^{dfdU`FSfoBJ9lY@hwxw-4h`XfZBBUhgcH0AS!JNA#iA8tmup=IrN}|dl0LG<) z>Uhved_HMd6Y+E6qslZTSzAM9X&ZrvwHU!m_rDtejZlK5*Yn@6mIfl+q7s6&UQRA7 zN5?g3A`s4U^Xdkt<2m1c{VHcO!M*)S3kG}&jBAUiW!XXGDT8iKQRbXJKVv$XBZcHQ z-nxR2&=^aer`Xyoa^3?O>t{7cj1b625sGG)0Q<6&hX9pGihig4y}$Ch)Oy)r3?zdU z9AJ(Pkd0=3@Ph8v79#8TR3+`xpj4W)Y_$kZk2Myj{Ih3?^2M@A;v3tIMwHzSb8VQ8 z#$XLHRj5QQ)|d~MxqaqmHzjUA5t&h$(1@?KcE`4ga$=^R*;xgd?uy@ZCZtjJqO&=TvQ7SZVTERBG0$>vMx z^ZrFh8C$-RqQI3U#sQ%Nef%8xmAQ^&hOvfB39ejS1?w1(&$+eLqmu?j%rx=Jc@nN| zc6syq3ST_#aeRL4)#04OA$|JMlE1KoEd83X%fM2SB!0aZ8=YJifQ%)Ria|HyqX)-) z`E11YO2N_jj7-7jkB`A>-oCZLpS<^&gVPDuS97FF`2L$$n7+7Rdu5yb!(*@9)?4Aw zDIV%BlgfZnSR}FLN`&Z(bcWezgi1P`af5nh_^nsJ%TE7w)RkjWOi=Rk%AQUrRFZi+ zU^P-Hq;Qy~Vs>(fZ7TBq8i^9r^EqqRZy@tNySu9#pUpVEc*@RjNLeO~Ca2&mOXIzlBw5C5FW=<(nLrG8 zP)UjG^igGr6~4qXQIc9WBx#CFQm@A^C5nW~7>0u`x-oot_Ynw%%evIsGVB%XYz)wK z!;9xHxVk+gaW!kn%yl|a6sn<21-t7#c6*w7YMAPjsu48WQYM1k)sm(bjJk?c8G4H8F#xmy2$CFkY(-zmIN#Y%V@NbI`YfB+PDaw_hFMbqW#U`d= zMWrVHjb6GiNfSD&gW#~Z_5f{*2*tvAh$<}-S`bk7x_Gc6+K{x*{a&;~i}}2f)r`5! zS+^wVmaVFZ4Xj=C44k-JG$(|h9CTYS)cy&>S2u>AfA)-eI%AM4Foxr-X3#HKU+ePt zV9dqbD~h!dg>X6H0Zw;qh2AjZix(GIJz_8@Ii6{xgOj}xXBSgmy1s#N5+P!t`GN&^ z0#ugL8Fm4IN>y9b7gd5soX7ZjV@ zh_u7>WQ22$?%FCUPdyldR-p^La*j&U))7szlt$N3%}7;_%6%G2R9Eu~Du!x4rU5m-pFwc7#%XeHVEVqF<_o5UuKzFWK_@GI*dKM+QcI8H9v&8>co? zV9!r!PL9ZwpspKiV^K*?Ru(jMgRX0myg=mTLfpYxtZ@N+Xfz4M_BNs@TS;Ic1S%28 zUI!70g4U_OT&KhG`U$>w1QjjQX&p_Ysm>=PS?VLF!Dhqlx_5d#a;?I>;VHT1SdioPD~f_ z|6C9~5f~?Gk#;6qFc3gc*r+WT7x!CdTxU^&0@+rijkF_&# zoK(AK+W~5y(-9+EEbLME`LZoXI8tHBlwo!;Vsm?&_Z}Rxe>UURbPn~Lo-$NbgRq9J zVaaN4`S_FjZ1)oiX_z-&rqyDxA<7PTaP(EeY6(=u2$I*p^Y;?deyxLft$B8E!FONX z;`(Nf!?Ot+gOb&LL8_og6Ut2RTW{~uD^o_(iW{pr8=2tnWXkSppN=eP8cnyGaJB3) zKS?>B)trrMEP_mlwvnhON-a%Qv$MTPr`O@}y$2j0obl$JtBkf+iKTVJ8q^Mufsr{`p4&S-SO;iCuGIy6-657DNF z>UQZ2x7gUJ*xtI!Xgp&!oie#NLt$N}tQe2SR8@`DHO?BErg2T9>Gyi#`i)!6XLFuE zf5LP+T>y!tE85(6o-dOTu3b;EJ+GxwD5?1R`uDrO1|YxWQi*U%O4~FBYlKMCoJOSq z)qA77I3!%l7JZfNzI3$*gd&yv@yJT>k98bnQ-@qdz@SUea84E zU$&W1otz=Hq1FaxCRnRUg~LfpS`;`WKm5`AOeRx?y^Qs>A-W@Z|HCh+wPXL;GiKu{ zS)TL7-UWYp_pVT8%HvUoMy&JufBrdt_Q5j_Ch(2#d>h+nQYCqQbiva{k7>q7-2ePj z&L2JGL9++*Q}$1%>|WXB)wjM$QKW2b3>XeNxN^xW($A*0uM%>^OpV{1YiSn`(Y`?+j}kd3r&SDV!4=oK3;Oy`!3W6Fw(A zFL;Hf=tB5{?1h6N!{0Xaa?nkKRMO|ABQEvrSdg_}@kpGbIv-=^75Q*L5+X+iOFCQu zVbLci2;DF{+9z4vLMEw?f`pri^&}3^P9XCV%>~l>C`?mLA#}K}4i6}{wiv8-&}K2$ zemVGNhRtk_lp?U@GGtb1toGe|1wIXFI-W9_R-6n|{>4Es^B_l?bNuiu=c!j@JC;`+J;EYU<7|&&QJeqjOTF(Ax6nKl=hbn~^GowVJ$0 z8BZ$GqVP3HP2DQ}i0BbIzyx-*b+$v@RA?Y7oVi50xcGZPeJoXAMknZ#BND)=l%zQCB0OfJeUv6Tyuq@B2tmAoxaO@-EenDM5kR-S zNJM}LZaJc0G1lRvAWalPxJ$nSzBZw046dnZrgJZ++gtSDSjhAG+gTLC$C`_vtQ21L z)9mPEiZYet3NJnDTno11^NDtEE}^T|;SRPhkSLc}ocMYqE#jbs_s9U~mg~wqAYZbN z5oE*<6-$#C23{=R%MvDY)-uT9+qYJ*buy@G$k!14T$Ef}Wd3Q*^ zlwl;% z&S1WHM*CwuQC=p)wx7e4Bd*4Rtj@=0!+# zut@39b%UvDvN8i>(7Hz9CGeyaD5*G~Oqnz}MON_m`8j(>4P|#iT^X#k=z5M7IZ7(N z|Gl?)@yc!LMsv~mfW3#0c>O>4Rc_wA!PLN@SMtYy{9~k&6h*=hzHyx^D=+a+s~0@_ z)+t-{>Q)Rj;BJr|KON$W5_x^vLt1#m-5lmIUj#{fNUoG;MZTp8pDgjGx~!r z*`Nn9X%B-1D-|L~*7=%_c6i;=xC)v^^U`jQ-+XhMr+Y_ST`k$a=4dWR=giI9k>4f^= zm|PgNN;nzUWF3J`6qB)6FOkVYF=zR6+Zm98##pMx8|QiDIGxr0chd|3T-0un_r2uM ziExmLuSQl}7^&cARFgUL(FJK)&|T?!)-aCK@_1h!RIrwMGDFu5Y0n@?+d*rzMfO%n zoT527L^cij^oZWdI(FE{DcL$eBJ5QIxUxsNrI@~WK_MJPSyD~TamJ#s)CVuuL8o7-ru*;pTvBnj_+@Fizw=f2^Uvp8dLi2!U6 z_KA(l@Xa>0^8lr(5v4@|+QMIcdBV|F$wucEd1=`{JmbB)U%=`PQu%0#t{dj_8ZCSt zv&#HYAc7Yi8TF_@)ix*zb6}kXXRx*bs{w;^YC*6BCpIohfiDuaqhl`)Aid)*2?}l9 z4j`D%YowB-c@|jM5G}OU_X%k{_{g_*q3kXkP66l|dof0+1W|T<9|hfz+S&`sA(3g0 zMG@;Je1?)(-iG1+{epBt`pC!H5Tz7|*pSi%6*P%Zc>5e#(XvDuuL5Um=+P312r0k> z2go@(MMAg8m^RjTT#jQVgPd^$p20Zjs>aMKwl)V01|80(4d>Gut2MfA$cr3MbcE*n z?`&{wnDFCYe8H!O6A;~Y4#9;pEJUp2lFf}|hIO>vT7_qMGbwpA zaoliuvgo)}ByqY+!`+!1a=?XCeK(JYLbZvjCz5B0x!nv6hdXoO?hf zB?phsD2j~3@j0J9e?qq?*gqa)AD;2fJGZ&9yG}DXXJ%n*<0_k*8|-Whc(8ZGXj=0t zH!|ib8$jzQZSj!{8NZf9~Q<`Vws=qM zIB1Qe!SqYZ0rRL={SDHaUIama00ARGkkDvJ5Hx@WqhYhjZn`2_#q#FX^(MVN{%jW! zdWhKPFL^PW7pPwa?qt#7UMeaP6#yH|7f{pn@cY4x? za^H4MTV#_lN=j;hWp=tNj`sRwYH32n)AJRzM-DTU%*l@+?jiNUoo6vwJk=bdZvk zC11X=!ks6lltt-S&MF+8d3iNItlSVH<^aSM%V$7l)%9Y*pe?!-UOs~>v@28MQvkI> z3>CVlIw=0{BgH%|#YG8L9X0XP%ec2F=EaL+59NFUH5P21xd{zA2Pu(J9Tg@Zq?-gg zkB9QQ`DZug>h*&_pk9es^V||0^-VSjHQN2Mv9lK<_vS7BiO|o$g8`UYwY845hBp`^@9FPcbZ3_Wm zAo=|EeO5XzQkI(g5Bi+n=+W!ec^oT7Q`b2$wm?|NX3J{2A0@^VKNZiwJ2i<>|*waze^7EQ~=yM7SsW5??bT?V++4L zDldpen*wW<_gyU_EiDdYhJk?L5ykNl5-3Ye9L1#Rj4+H)D!^z<6jw2#)&pXal6IWHVj|C*0D;$$++OJJ{yY1WqZChM73}G z&WSdLS|s_ymp3`zt24{X`JPmTI=Ie{lO;OYkz_9W6oSyd?&+*x`!walPg8bBBNF54 zH8;div($+A({De=tLHmxpHBJnpFiZ$;e=p5WX^-2s!lhCGR^qf%^v^B_g`eWS>u2H z>0N&E(Z1^rlp0+cgx37=>s|hffA0#tX2^S2;J^MCpYZ-9N2th2*^Hsg3qX+6V^4^< z#JqGgA+9HGXd~65EFcJY_tA)tAD$wOVVV`pGDFx<$RKbME(7^^jKC7Nn!affW*&ICHubRekG+5LUB2=6jysM*Y8A44s6t+r~Vh%YSWtKmC6~ zr4V__@aTX>C*q|GUEX|tg_FIBy$~uf8SgT9Frb-T(D22q7nkyH3 z91dpejY@)6Orw@C-rYeQ?$KCXB_}|$ko#7^PoCLh=MvmA@4x!pgmAy#rCyyEFLt@V zKW6uI%F1e!gVQNV9P;|tUPOj54<7E(NCKK6JbJv%Cm(-GGtl<1e<&V)lyPyb%li3? z9G_4@cq zBrHx@sdC#KM)K?t-F zVBCXOW&Xp0#hw?+XOZ-?9g%ra=gyXNHsj8Naz+MQ+6LNH1TTFYyq-_MAWbL7>A zv&4+lZ_UdQ^#Hj z97`*F(GAb|YJBl2gkbMv!s}O-`6u7I$#3r+^W<=X3=~>xo?C0M)QtJryN}rHHMzGt zKni&C<#m4Z*`A-Wj0ZH#K@C-Hi>Be68|WoFP8__gms5aa{v%_&qCPTofK2Ao?Fw zMRUfD+Wf`r+4W+p-$S4}Z4jFB=m1e_vV#MXHK5UUK5<)3G1ipB0eY6wzHov1`Ucbe zU7|peG+LzNk(&T*EwlYy>b*5Y+$1-yz*tB=z?K?gG(s9|K1J(-(Wu~ufAtnxYorQ^ z0@ty#D1-_qt#LC*a2*0+1$mhh$q*|t!axx>yHIaa8jH=+xlB=D!3qYW0)0A#vP2p~ zo@baW!=zJ$EzvqhASkV&%uDh-165!V6nRdm1bI=+6QA6?gOVc8Ku6@W8B$2{yl|hi zwAeJGw1JluNmL+-1B)4)k{=%;g`hB&dMzQHrG8*uhNdZyCQ@r*g2f?*@FX~3>%+qj`|9RfLy2SR$ zl)-S~I%YzWG#f~%pqTO8Qb@062t>-|)rj+rf{(@;E0vRuS&f3Z!F^7X*(zF@Iq4$3 zFANKrRm`+NXyeI}g36~Lq#vYN77OB}dQQRnYb?ST^1LLhxdDm-gV2B}C}txf(Lf|E zj0~J_OsRRN0^B{3Pd(puakl#XcCkG@?Uk!KHFHwST9hqG`=>}DX)bp$WllCap%LYx zxtfr+Ek-AVp(IO(6zNO|lOup6ki@a1T?;W*)2%CV113nQZ*Gw8Y%$y4Cs|v^NEbly zly8kQwS)g1DtV*z4F;^+Z>=?)Td8w?IiVH`B58R3Vwb;pf5MlZzrc-+27mdpk6CHQ zeE$z#5>0hkWC;=MW}i$Mz_MqTZ;J<%TG75y);C z_#hGO>nNT(K|n;)m~z^pMWt46%x0XoQJZ^n4BDto*pt(b$;>QZMJTI!0w|5A}dQ8?IkW; zILFt&@)Z#$3D>S(=hfH0%+2R65-Ld)NY<9x)M_=F^_uH?!0*iccuG3|xBUO7FTclI z?=Ah}`nSHm03iQ{OIVjRA5<}U(vlasKY;u$cSaU6XT#4j$$rB*yPT^-rP1mVH&$%3 zy-ZsrtO`MAZNu(n+hS+vWde?Occ~83lzccu6dD=2L%J*qB!(~y$+H=GmST*dmV^{p z!Q1bC#-;PCy!`xCM$?>Lr^Z%2Cd~>~+Yv9XUbOkB$-|F+DJI2$fAp=Jyz$2CoTMS| zKOC@gGC^z0r3>qPSD*xNaz zX+oBI9hyDG$OvR=$qPZGEg}Sr@TNO=1Kojkrg-$5^BKrTC5ziWN%_&ckGQ;A=i4u? z@}Sq?*PkB}V0isnkKNNL{b|94z{SwMdwZ8Zcdhw8@dUI%+Jf|8k7R8V8`VjR(#dXwM4Ey~Y677Nti_NcMUD)duR$XSL$Aj-+IN?7 zEQTO3D3KE=4=95YB`l$|C>3H!(K*P%Qp~2vFhWHMrpPIZf~ej?1R5I}uqk0VqDUuL zW<+s7ZY{53vdFo_N_~N#-NTn$Ag3?Hm-YTNj zK>Ml22B6f`O+owoDw(J;JRM+4Ls+jn#?lnzMTVeo-D1o<3b@*5q%XMe-A!dJMi-Q2 zi7vft)qnjg=s3IoyT`3UA(|*qZk9|0U%$G<+ESh3M|XMm?h(>JJG6ZHa+`)Sq_dnL zP<-!&9&g{-=k5EaE=R9*BCqxWjg*imiJXow711#7h&lPOLcp{D;k#(sBFhYWbdUV;F5${$MDH3# zMOAYSfyQ`JN*aSkqOnL@Im`soSWpV;O@s>PQbH*OT0hNfyY2_%gFe&Ih@{)0MA4t* z%<_zG5)cSO914`G5k_rJ$0^xlV9~kQ=+ybRDN~&pz`~<)Mv~_gJ4VZdG>4so5g*?@;Fy9NuPu|OIg{~>G*AoK znsFUaX*EuksX=T1usHHg7X^(*!oT~?uk+cxZQlK0pL{Z+orJ`p;(z+{|AX82AMq#u z_&*@eXXqkFmxiTA$m&v?&u`u0U;gM<^ampjr;#|!d)StCNq{;-XDLNC6LG!Cg$w8T z?ss3}=t7;hf1a^>GR261Jj;lqfL60kZ)KSmZeGP2&2%~<3I$OV5yfs_(`UM5^XJ$u z{2$N$v$~%4hZsMgb0JIp;`+C{z5pP<=W-*qgtf*En~I{C$=H(4Qp$4Cng^ImRG#U2 z%s1aN3)?Xo2!ymrq(B#<8B8&xOlJktqY~0nq+MpdZ3`#e%7!Dz-GNmUC8l%-NgN2Q zDbS^+*=cfkGUUONeY#6+u3f*xxz#R52gelJGMl!!cmENa>ph-q?Q@*%iAYb#vK%Wy zMx&vgNg%_`hSlN2cPvjWr9P=H)(%I@|%?AP^u7dNgnco>ab& zk_+ig)wwwfK#T(xM!0}f_qqxrtYbqfAYd)VbE_CbB{Zook#0rK|(q3Wi1E~${gTvM&n8{H}9>uipYbND)rx>g&@F7W~?DF1?m1i&Gj_` zrN~Oh=$j%(NJTmrAZs<^P6rI6$9vQRs5R@PlPPHDDwrMYBD+17nk}we=yB)XF5}67 z8<$#a)C_r^leJ>9l^#MkteRz-qAb1n(=70tG1eF(u$Dk6tII+t<A|%wDUDwM6J7w7AX=# z9DqO)3g*K?=fK^b>F(hed@C%uw&bOgncUgw^RGYHA=CJWwvy0zz~Pr$h^Cy5_84UL z001BWNkllZrw=AApBON8$h zymdGu&ofq9k~>>N9-Ibb`pBJY+M+@i6w+I662$?!G;Hl2b9g+$TFX*9rnlU}A~_z; zm`qY`Tv?}4i}?J`7N^4*G6*=g*5Tr2i#SkdYdINA+1i=VA5Dov_xu^_?yN(8I1o{# zec56jeJ+GRCS7zsCLat?;@HisFdjtsZk5A)ZeKAK8*j{ghT3UYpA5|2cIsE zXdzqxNFW5|Xu$O3l-kk~vR=mu#hpjnWIKI+@a@-F?zXVfl9ifL#N2-HkOz;qL_TUV zJUzf%UE=dkAM?Y9Tc8sD;9D=z>~`E)ih{UKZR0$%-7W0?9<}vz6f&r`XDY7k4A0}a zH!)wBQaUe@RD!%TeDGkOab`%ufYo-5?PSF9a7J^jMR%o3VJ)LcMziIHC>}Oexi>!H zw00eH<#~pB#;AUoYp>trT9hzDk{f7joPetChR%%U_O~t#v z{WbUR-?dk+J}`@GjEc=+kBd3f&$xpsp_ zm2zF!T?FPu=IU*VztP_5bH*;hC?W{ih2|F_iiX1Nz_R`T~Ib zo=c%X2;uaNZXshFyC?kFgK+HaQ?YGlR=Rj*)%zL@A+SZM+1l@uW6Oom#|n1b1#f=E8axYc$K5J?bb~>XZ)!$?yW0!1Y$mCpaQCeHKYfjn~3g12#lStoq4wi z09#4D{QVN(%)=fNi$$-d>daYV7xz=Zd|H{Q4D#L*UjZKc>sUi+-S<16i|^7^i9d6B zR3&wQDmJ;q0k;Z#2w!cxuFay5E3lqj@;}!aw=Tp&n=G(sp*#~_Nonjnk;s1(3w}yg z9Uk|lGV7kLK!sQ=N^52ZhcuTvkVItD6l{snC1Dtn?e7tpoaZvbF(@7Dee2wxo0h<{O(ezPgsti*kgD?Prg+ z#h0F2qX@3BGty{d_+YQ3@vCj5(434)wk9FD5g4Prk^W40gp}l^W>yGtZO~nVYS7rtv-ML<69gLGPJQ=>ec!F8y9%v z+6wEPgis0c(z10j<8MCR<*z?@%y(Yi;GcfyCQ1ly?+!Q}rF`eb4boimU;Ran8sz-o ztC#rh%Nv|ut~)Q4wM;X^XHWY4@4tG)-GdR4R4%=-qK=G3`)9F=0ru;j#nbshML+p- z&dGmVe7fIz&JH;BfV7JA7Dl^$eQ$^6`UXM0;SBe_1MOm+Ep{?ycG4&5E)jRy6h%ob z4%yw?;r_$-`J->VMi4b9ttL<)f;zj$BW5NbZgn`_8S!9$#OAp*?(9ry)fC-E#D}-H z5yAz+SYr^iIJ^KRI#sr-GMK_2d3EMlPDZIHq}YrCfzPY%aKN)P~p z;S>RU{J77gfCqbh`lF0qCqY`x`IRP1D;Ej7=aHj~bazY=2~JguhMA#^=HPI^@bH-0 zMnY7tQHb6hmmj~y{=p&5R)-JY+Z9KH5osxeu$KF_C-MXE~)v#L}fE$x?@d zU2Tb;;+6W`C9w2utZ-OIShD zX;b+2_io zb-JtP$n%2MMnD<&G0h8U0dZJ z|Iy1fHL>{By%FQm5UK#B1f?z*k7ul|^{6+S{PNcy^OZMl@Y2Q#Z-25yI+~IMiYo8C z@=LgOw7a)fREFzCettC<#2CYH`w?IJ(hY8Y|0M>42|xYo4`_t0HTuy<4=83C7|nP% z;o$HTV>HuA!TSNuyK_vua)X%}BHI5Vs9#k$)p1+!E;jj8a7IHH=MyNKD9Qo2LkuQB66NX2Ah z9k7wo8KUQ28nsxO)w`s+*S^4YjRQIVMBLAIzyKlVQYa_oIy>O20^m+J2;Ro1*`pQUwdpj#9ER!BLQut}u%-&9Qy_oqq{Cg%VPbe1}a zffATfGd=CoUTOnSrYS}{=06aY^kA3TrXcDr0gxW;5GhFNb<)WgE1(t%?tXHM|8qFt z@bHwtW~7rL)BXS@O?9WSNMEG*L4(>lS)Wi??LNC|fLZmKm3}=1fpTk6S4FfVL6rAg zXzjukq_sp*fE3ad74uC^5GsMu1=1RC0M{t1og~l8U95G)i?FWqB}CwI609XuG1gl5 z{&C$nDHT$Jv;mp`ooDDW!w^xcHArVEAgQ+-Xh0e$vJ53%U3Y4-dvHwG!TZ^%DQlA6%vrd-i$ICkaC~n|02=vdZdmo&WZSce#HsCRBmz^caf> z4@Rs2}!#{ywpY;jV&`oR#2-)j+3j)`0EG+%IC)n09 zaYOJVH|%_Jf~j>0YgOGZoNUMnHwsEDdM?t(hAvosXF69xV6>f^$17$Z>A-;lO=7-g ztZ|H=>r^r<=dY6W-jD#!894`8sq$yP<&`o$=!Y0=d|K6isSkRuiczV%va z!r4%A?Yu*Ymk0SQlbM+RO8$QL^Bqip?Johv0LU`sL6!)I086n>MZaipL z9tfH=C!bDHaZFfCTr8<)-yM*5z)w}bOLa(>CE0k2Qi{0Qq^c~fT^Meq^&m}3bT*?n z*hiUiK4W5Z(x!psg!{$>RnU8F}t{XV6{QY0Hp#-Z5$x;_oF%l5yGd`;Pv}17S;ukRcxK_ zN=fFi%36a8s;%Dom}cQTDniWHxb?u-VlkzYooZv;{wMsfI4@M6cK}?q=z;|-E=|fh zM!L`fv?Z#A6j_E90nKL1$M0I_9gvbB2uWut#%SVZgCZ{|3@&Q7*_pG~N#uY-Ru}?d zY1KkjmzqS%B5g*erl|*(k#xUJQEIMT>G5aZy-7WAL)E0TR6RP0BygF>jMJQY6cQ=d zjco)jJ~vRl6K5Adx-^#D%X%c1tUqLWbVS@;Mu&9{ca8}{#oAhz7q4xilyq{zTr)Tw zu-b}w@j{12=m?10j}OErPfoeCxk57udF6bIuU=i^hac{vtw5NPuUuc}`g)TfkUZQv z<>PyMeChfImzQJWFyNI7P44auDYbiEGi{h<1!d{<^u}oF5&V;HUgTR>yM&Z%?GO0T zyARnqo$3%7rD26%KpJAOO181LZfiu15fr&xU+r2t(_59H(LDrU*4n}35Me- zKYI58zx-^MP9xz5U%SeyS9-j@+2B9?(mMackH^dkyI3dlvk<7dzA*2~nrauZm1k^0 zq+mrgR%ku}-3MeLD?(7k42*%(`;-7rEam6K5V z5RwHbaNso40&OK_St6wrF810AV+Do)6$D(q@dEYGFr7^qj>b%LL#_?8=?pIdMx&6z z?VbMgeyZE?EWmiyj9!6^vl6Vc-jMlwxA3$p?2GH~dVK*ve($Am4~}rAyRyU@OX;=2 zRe4txb*?t`Rr6Ue@;kyqixfh1T5Z1dt#49`LwYMctkImDp3v-cY2Q9#_pSS6`#ad+ z1Q~=VDJja_58jeY2SZGmA%$f!$WYQT>}i_$4o$%6a7q*gph3^3C>5Yf&tuDo(R7NO zOEqwZf(S6)z~_>gG72p?x3S8sfV7yBJl91`dW@Uv3|coyW6N_JJ&FP{6Y$BML*k`n zf+A-&&dDARNm?D=emupPF*4~8)tBZGcG3#6@su*piR%eL61&387mlKmX3Y;E*F_Kl zPV<7}z9wpRXt&*T){(Jv;U^gT zgRe+xq|*$6rQWC^1L*;XV+m!& z^q)P56_`RZ?hgs$h+3;LFC?ML@i*1E?>9?<3MBO;@ZiJ20d2g$r6^EFy8|tby==)9 z2}U?DbvE;(^6VI2;0Hm)7}@z|JP=XapM?~*UuBRJ6LO&9q$nVNu$YZJi?+0r68LO2_oSlE9C-&RbC-q z)gllm6@b^YOC`{S`{pVUt?HJ6W8t(m9^^WyM+G{ykHbVPSb8@lT={Mg3(#+we^ynI zLLgAeCtf|n3d-s^vX)Zo`M^Y7n)%So(#QA)QqW8S;z%*gQ)E=5-fCd2>tyEM$EE^j zBE?wZM%@i?)PiJV6WMIL-v^7ePXAtc!e&Lu-NTfgm@yq35=i*XtwX}~S9r2LcDEM8 zQX;sy5>l5MVU3g|T?y?RJlT4q_kC`_cn827%FgmX)E8gbyB6Eu3D zF&iCf%S+^00kepU8y()bzRK6Gw6R(vgOI(`A&>V?xpZ-zbKMAQEyv@O&z_v{;o}h> zJUC(Hl?_^v;(ITy@!q{7_6Hf8orpJY_GmBp8<)w%(U2YRg!%=_A|N2*-@{0!}CN|=?k00~l!#+pD8M~(`H!hZx z+7Koo4|e-SH+(L57x}B`+i@j6#I5=%C6F)st&ZZ)qYkTuRf$jDr6MllBNwx zNos4G%ntUL?C;V&=k}VxNuQ|Mrm@sTV^PA8jfUid5psErSz01xXbY{;Iu~&y5K^PF zlEafz-uv(lv*tBgwUFLY6RqJZ*VZVDlAWUoFTQ$%`=38xxVufmXjHw8_Rp=VH>hu3 zV6wZ-bZ?j1+6Gc8AA;cbRp0%oyr;qkn<(W;xwCt4_1sF=Wvjj>E8=2)pWGj+(nLxZ zb6sddF-QpmHQ#4I`0idvUpF`!hFppu&ojy*BTxdX4P~m)nd>&|vT(_7*8SWl@G24C z#d5WT@n?bd&y<KHIh{wV^*6^OK*x#b7vMX?cZ0I~I6-eT|3P z$LN_LX(j}5$Z$Ayz(QK;trkHPpoOKhAdK5Iv@R&J6d5RP+8-D03v8*rEdFjd$Y3U0y<~Q8yi~Y~> zorww%Dq&f!he#=$xz<{gXOQ}%8AV>Q)UFeRPV!O><;wHIrOs6CUFE$9M)3LLBceE9 zz1Joyjc1hIU#yB|>CNp}XEL?G-tm}H8_un^sah3oN^->x8vpOy<`*i7E=ryRhGrvS zWu-}3RzE3J8#6DwjjcK`*8jPZdpW>z{rocb_NM&i)`8QA2Z5Vt9x7i{FXAfa zEU5rtoyoO2V5E}7&4%+m$VHdI`ay_i2TTf_JR+#qiPttLj`k7Sr860A821OR?XC@R z9Q&?|BO=oMJ!GfA$Pm?9CL5k0tcwwzjHVPOha$(?0;$~O>L6GgYElS{aAtBh%uafS z-ur=+LP_EMKcJ+GfwjhZR^9{AIk551$Q;-(e-@;V(48Ng#&^Ly+ZO~1C7qAMTF|At zmr7P06kiWbFcMRt05IWE8r9phlE5-5dv5Qe?RUPb#3uQjCGPUZd28 z(g?>^H{0G1W~(X`ZJ@LjkPY}`dqOv9bN?`7G8&VtyvW`_vUS);1%WHVvz$E72m{Ep zCC^LpvYZ32>iz}VFzjcH2Y^yEqKMcH$RQ3DGLV#+r4~v4={GL&=Jge(Sw3gv4W4ne zjvT5-ihAUdt3svNJ|6KG|N0#c4o>;Ow_czbxgls>P}Q{K3;M6VU| z;`t6Qt|vUc`-HE){xUb$n+PFzyf@+}zy6%#og?l)TqS#HlK^=BT$_zp^WOa(gfYyP z>;Cg{9mZL|&-qJhbZY^DRD8a5$}c{6$ng|Hr8qU3pKR?Rq@>I!+<3TI`r z^F3is?VGa_)-zJhXJszc8lRJUXMBOy?XPjWO}N~1Y?`%bA*gL^k{=2tyL%`lY1A6j zR+pK~a>7_qj7LmQ2h@A3kTf{Ay3F^!_af^ZEtKw))LdHJdJu>kOYmVR7+WXJTW*Fl zlYo3OBg-;cfyNq1b9I$MTgC_bG{43LMM)6XX>M#X+TBJD`b5h;a^v2=>%99? z+4~?JFspnaXHvW>Qcf}_#m?LU1pRwo6()3pJM&c@mK9#3~>s(o%D!Fsx5@&)?%`(9rFkl%AjZ3?YR z8Axa~VuC2b=yG1vSx37pXa#>+&VUW!nake+C)T!_4e_1t{SiSBvb@|ysDSA#qh5-b|v|3!b zyh)noZV=&b@9^Bk6*r4RSvswR-cpT64^D|iNzs2qcDfIf2F1`aD+M=iUgyOdYuvlH z&EDQI_wGGF=Q9qrACd0gW9!y2Z)L{}Q_IC`H)yt&h*inu^Ieu#o3v^HuV3lXZ72NI zukLcA7gBE~JbJVX%9)y_um~BDG;7GDMiBWya#lQb;8;=RNVxJQQ+7%7EFB= zmFof*bXEWU4tr^h0eNO3Hc(BKb_rI__={&Xg@7{8XeWU$j$F|Y#F3kZ?HTXtIa+X7 z&lV}}ISgWfibMC_g@67$XtnI z4k9TOW$C7=+ggjD)gg!?W(Qj&(vT!|(n(H{XC$V;#@>J7yAq`?kxEjl#b~W5io(xw zuvnvAB&n_cN>1G~+%W z<^PWLMWYk~?bDy;z7Gp?L$?3)W47;L@IeaVq%9tv>6^9hB-a*vdH^j6pbd)neHJJpce807*na zRBAt+951&h4gc!5k9hCF5mp9{%)kLB>DO*ilq|Jt{MjEq&&~Cgizp5tmX;A9t)?5n zW=oPqF5E!{YCdoj>-H;cG}>53X~F%y0Y7}_0YCa^pL6Rgyl|=KhVf~*vwgzBL_^Zx z^W6y_Jv`=*UOi7M6ny9T4IXcu@XZ%CXoju>^!EK@cE%P{?{Ig2%IP$x7A5rR0WY2J z^2wb&qzsAU2yHE;HYh1c;+QxJ=7sF25R`F?sCurYK>26d<|$zuyWh!Lj8p{m4pB3v z(TQ1V#)J~m!ZOeyQFj#;geYC20!YjG5l57S#H|i8O2E1Xh_Kdm+LfHIXOND#z@FuZ zs5C_tu&oqXi)X^6h$(=gVA?-+G043&v*0?OplIeNC+EU;xKSCd7_BM@(Ss6M(AUug{T-!w{Hf@onxhSGlHsCvJ{q3NpijD zK35%k>pSe#eXBYQbI?|irP6`sBv5qPHHL#Bve72$I-nF685}=gyn7olxX)xX!ju}U z=8@`Sgd`HBo0hIZ*HH|bq+vvTWs_!VS-<)^Nu1K{G+ozoHs*9NCM^V^&@3%4QxrL^ zdW}5KDTJZDw2EppQAxuQdrBj*3E0O@1Cf42j2)^Pr;EbITvjPASrU!ah`$MppO`8}7x6vpaONJStW)^J6o z&n>UOg;=n&z`W4=-Qt1y_eiNkI-BzO$M2D)Dcx>|+(<^LrrBz-wcAI^2w^m<&4A72 zCI=133eDlcA%kq@Cb$Yg7>7i0OdQ9|repGKMki66TWfJIO<7y3qfEvtH#f0m!F%s~ z!bY!+ln_eGYnNA8YX|In^fUUyN4$9M8?0Sir=Nvv9}Li0K@=)$(c*>nO%}}t>44L*%smBr0lypPQ{?;DXp4&j29C}HG zrL-2pfM|JzX0wAvVLjXGGW+cr8PVC>D8N{zS!W*%*&$5J3P~vZ9@bv+=VLlmeLqE_uZleby{wS9Y!waLk;nOrlu4Wdy6h3XSw8 z$*O=NL&tc84*V)KHqyFxiQMdwa-6@($WaDxB=(%F1QptW|Naj;#+3+rnvpWmWvEVHR5ixn$_oZ-0S!fH-Y`XP#uoFkq0 z4@=(Lt{@VjcnkM;INw@3)+QytIrB{-&iT16whdAc80VQ*<2)OB_x>J}q9%@Gf9`RV zjp5-=fi1oEa1l|W!H5RqF0&#}KV=q=4Kh@nBq9pDbTG=A|?Y`PB_+hPU*($n! zbz%CvUjqb=G|eb?w{iQsr0ZKa>6s>tAX(qSA(&2QFl$heWV(Mse`SSub(LCMoRIXg z4Cmm-AAH8)?jy=#N>Nq3^wMjrUU-ql?PHDM#-$bddCG@3pYYPP4JM7kMj0}g?u8I! z>su%xnC|V9Z$P@afkL8nU}Oow7)m1Xa$FbIEM*Plct*0c=*8g9HzmxbG)+ykyh81l zZybK66$l#B?vEkTB`oz)wli-W+6m&NC5nTRyASuUNk+c00ZE214uz)HCI9RPk12+5 z{>FDWKAmuUc+C0du8YZ*ZZxK>i6Tjw z^oSxAh z;koC~#>>HQ9$D2|<6MEYhO(HkypSP)?I%0brQx`)SY2Kqj|`24=dWDg@OX%jj!TzU zxRS@@G31FOR)(#mh?mZ#oK}LJ{SzvkVVn@wST3(7oF522$|KMPYkkS{o2f`e!+2IW zXRV0CjFMaTwkfq`I4U^5wMHbM*H2kp>JvpVRaGD(g%b{G4E50=IgkuiXq3V^8_dbR zx_!nJ)^W?wG#;7lnv4SGTP7S_jAhKU0;B- zFlfu9go4xw)fF2p3)61c;>_<`lF6Hzl~_GPAO#I6S1kx=Me2 zlXCwlPS;rHy$;1}MifV+SxQ}2-g^-#T+`4D_edllBjjKWJ=`G{mN?CcoF&4z+cHt%gSIRz?QD#eRhrBE+VmS|=ZsLh z{cRLYp_eZ_)1Y?JIH?fIg~{yxF)SNPV|*($9qWz%pnE*VWL*7As#wifu+FQ4OgezM2Gu;Bbk#^8HWs47P?{WXMWO2~rt(U!7UI^G5PI$CG zLOX%7rUMCD52dvRYvyt1Er{33ZTVawh?CFmyZ+L7fG508WjWc_1;}w!t`lqqO0smMyCtr^H(qXsQMk zC4NX^=uNxDwHoO9!~tMm^h9Nc_L zk|rD$kVX}++;|S9M@)yiqzbpPwkf`SR$k5!Ve#hO)}VB@p=cLNFSU4<-fNGJ5piC7ZgoXH9inwZ#e~xu zPNoHeLC$nM?vTf=%@u~DlH-#Zzwzr=IXX4`=)K!0QDd6MBl+I7O0U;LNXcKl`w6F$ z8EKZW*w3iWE%W|Ix45vi&bh61KK}SqUjEVxeDv89-r2uT;tC!f8p>#sKmNf@-oJm! zq={KrKSz=!AYj@^{^-Zs^zA91J}S|@i~Q*3KD*6398W+lY>4X{J&MZkqmLg^#eK4V zABp3jJmJBq<-$hFr#lnG${OjSH`eL0z>H6ctfn|TL>2|2w}9&P0U0DzhH^Yb#)>S@ z{b_8qqf#K1K%toq_mQ&^v4p1b6YEtpXA^`Vn0O5;iv5CO4dw9=D^76M$Km?s;Y{vR zD2AmFDBB=}hnej71U(*kNsD!)614XJrs5dqET*afh@%)+6zGYMb9TXS2exBNobWOQ zC4EYjaBb|QXG+=`7=Fl~3~w)=57o5zlOhcD_MiH$;dT zZqvbJn6=RsY|%5DrtBnAt>-4Z6VGZW<%{E1O4B|fEorD5nzBO23ae{cbGc{0{HEzs zp}@LU-w~dv@U!$?TtE~hEkz^+-FyHQ!kwiJ0ifDZ?(NXq5~RHZy}XJ`5^UBZJ$Hd> ze;3(QARJlVqbdrJia3cWr&E$%N}NQPs-oC`N?AEnf01L(8mijy;K?y-r7x~G2OFdjET)3f zNy)X%KF!R~7~ik}xU!%;9g!_9bup)1Y_V$F);R+2y0hRLTx~4VvI(rEM2m%K!LZex3Ipp0K=-@$*-gSkGf-WySCP;1+lHD`eaUJC}d9fgVwsoKX>g zvvaVH&@8*|PHeUKZOUGY?w>&+gg2i@d7u2kMP@tOxV@)jTjxN=UZNx0gk%y!7pCHDajXdq>@y%30^zE!)*{J zNCjCMqtXnKFEK1F=Zqui4_I1WU^uC`{d9zt34=W2)#o=jJ~(jWq7v7izv8NL3nd+| z<^xo|#GRe*v2ze(wC3X026>jcMnq!p!5u!n`(37$_OaP@O+A@VOoljTIAX%PA1e0l zd?cRSx#L+o5pjAt=F#JAjD@Es8qzfyc(>I1tE+;l9Ts)+fsTQGniR{9#6?uR*;J;I26`c>gf!X zBqUkpB}vdB!d7d_!+n^JP{PsFH3CVJCElcGLu6}*GYOn)5q&=sp;Z{EHX7D8zVr~x z{U?Fh5YnUCPS@ZRk(4-L(N%+UUb+)0i4cm$Ib1LSJA5-C!*D>~M2WTr4NS|N+i2m| zXXIC|UHY8Y^~-<`hSk*37VhHAXC=IMAGL}zzF-#wguFF>h8!B-sdXEB7{M{u=QzLd zOR4-M^Dt?>3w0HQc^`PsNc((r9+tM_g7!ZU(l-*)zYrW@io6XToVE~@AsW~>8bWk@ zO)zn`jblJ@yNA%Tg|*gRiWeuuv7k8EAzeSu(%KT*TCbardn6kds1BYYbcqv|IL&Cv z5{V?qVw$={h>R#osB4Wd8s!?|sE1q_Fge{tNJF9|g>W?5pUX)3=XKt|iEdi6ZoENS zMPXQ^vpxbiijd0tZ%okji|+PlJ5E8<_+f#q)Ixxt4Wh#|dEpx%KVu;@6WStM&xi98 zt~ieU`!Tv}Iy*wDyJvkv+Dd4;VVdFGTj!_A%eYURrqp$Xv4SjLq&9e|NSdJ=NK8mk zn@ymY5yufq3d(X!J*(^La z>~a5SND@gRDe0$zm9-Vp#nOWZXHB{RS+~LDpC^$wp$kc>LPRlwx@jmXO{^r5@ZXoL zN4}MLNgpBfqMH}sFOM;f>*tqwVRL~j7SxU5;r^J)NH1vHHm~xua+02J0L`jgZfr=DSFGE%!mEhrN#XtEs zH>vB2pTEAzmoF~x#?N1RM+?mQfcySs;6yLyhFyMB&WdNoceCbOEIy)nn9GhTgR zlZ$ITmNG>(8S$&HpXcFW!S>-8nZ(2^YefA8ALlP)M3NF(4<9OG=8U%pdsUm*)-ss$ z&)7bU1YenjDDuy6@Q}6pBf_UlW@tn?CGIaWF8n&vixsQ6kN6u2MNyd`n{9z5A3m~_ z$9(72a|q|?WfA9Ba&}j8zV+&J9G(_Pd4iLgx-k@G#UQqvTkdoD+^T4dA&w%J2Mg>T z4oRh#-+fPv z#s0|zZ6*0&(G_JSo;=xRIvLT+`-mv@jAzqOHH}NszPNJb8roR)o<3qS9c$rQ zbsmq;&jmTl#?4t~fwTV>3CtJAzw`K_0r?q6rE4pk(|!Tfq{2{P{XoJwd*A*PwE1V6 zk4`2rUo6@POb{Z^Qg?N086gF0t4ox%;qYX_a*~qAKC#GX!+Rfo#v5;bmB0PBexBpg zDcd`HRMS&mggAjyl6)}0;h0TMiL#9EeDkYpZmjd*@h;m>4|(Oq%RGLv%ko0X`3vXx zb7VQXc9OIyplfBT4=kA|pNq9TD>=p*Zf zW^_uLMu@t?%x1)cWg0y4nk_AP6JiU*2Vag7c<)6yLpV!a*S>J*WjJf7ikdD(B+TEK z%S{BWKf)vOvXf?X+h2ICFLT>#>4KKj7wN8*I0@NpthUh}mD66jqC$3im}VH72Z4}L zcMr82Y>T=Q8WqttK0+Xgx~9R$qvFx300??CyL-0?(H5kl?F{^9Qhu-;xR7WRm<&hv zd3{{7-;A6E7r-E2_lgje-0GG?u`k=-hvu#QbOJ98JNsOSb}@%Eju62UBg4PDkhbN& zm+Vek7tPr|h(d;zEu=h!N6@&I1@RkoukWXE+q%YSgOiFhg68lk$%ZA)m(bez;bBSQ z)3NrSB6WojmMqIC${7er9H&%eMVb<%Q(z~D6r%=-_SdgvHAI9IUf0x~FByiZY2%rh zNU2~3_DqqCB-X1$5FtKV2#HdjO%Xzdgf<__;H+;xM7U;Jd!{FfLaLed5xO=svr73* zRBPA8Ts!9(Mce z`QU^>FXC`ia_`9zR0U5C#*9W2%33q64RPM<*7&whZ;QTG=CU`O@?aOVG3*?UX&ZT4 zHyjTq+miiIFJ{ih5v!PY{;_ORklJ~^O~F;TnU2;cZkwc<}c-a~6kf@4@{@-$-B7~Z~p!1mq= zr?Z+-VMx=InG^hrAMJ2w+e^2uYz{~jjAtcx_on>Sogp9ZRy?;M_?;hbBc0*XCnFj| z82$-Sl5z8};(z(0+q`k-h#MDI$zz8Sj&Y&+;QkRmym!h>`UFAOvL9_D(w&&leA_uN z*B&jh--0f!l(~ybC3r@{;^NK(dpHM;HK?>l@7zTuJ5OkyY?E(ou{h{+dRiciH|QH0 zw1q_bro?JPWqh3U2S0hA{l|~V7jky)-{s`EvOlP__^zwtPE0iPf8*IMr%LHHA;|i;@@*yl3`e1>TxvjZ1L(s#;kCnDkf|UHmS7_v(Uwm(~~2bM$?of z#dt_hHrUDssEkgJsA_|sZ=~?6V1$Tstd%_2ITruypZ{|vM?2!~-N#f-#kq@D85LIi z@V!qsI@ssJ#Y^A}MOis*tnl@Lz*y&sVj`r|;2OUMp1Ie~`V2pBQ2%@iR%c2Nk72LZ zi}~XC_d334Kz_y%r&)!ZRVoxdwblWl^pb|IsG>#v=oX2yEJ!EKqV1*~&RI7r3UTxH zeNJYUrImG5l7osEn~LMn%oi!raQ*5zzW&-Z&TlO7!3Upmd^9AIZJL8TLlOESQUce` zFSER{M3O4Lbo~O$OMP~BcB$%$jn#}7E)FnF!-KmIIoN%QnVzuw$%hofeNG-&9=Zv4 zAMSDPxyvjqZBnl+aOdGu9^JW(DaYLZ>=vWP57`&Td>A#9E@x&EZoG7zSWj7Ai0DOv z8|yI}g8^w8^MjKU?i~+#IH^M1tt8D; zpw+T_n%dPRb~++jSU_T_%Zf-TvR)5k4NX-M#W6y~XAq`2vw%AraR^9%{;abBQx3&- z*Z|t0dW1W`dn&~IeYM{Y=NT&SMW_>mktf|oNhr`w?G5Ym+T1rpUjAfoVUVE^s$&*x z*g$X&V|`KBrKq?NdmG-X0B;!g;lZAn2+V+IL&A9>P;)JI7UV&yrDr5z;8$QbgqLy& z0Zxdn*zfN7Gm$mVU_{P!=~jNuh{ZTTZ5%==a01sNc%p3v!C^brv74^$g1iZb3JqlF zj=b@*O}i3aa%54Yd7sKzY@@MFgK*ZT${g$wZ78Dtq95MoEHcfAH_!WYtfsA&@EC>0txM3|t~>fJ-bXRS|b5%_c&8HIaYbcV;) z3~5YDANliP!(5I?`P}=ndG^*=g!15rY!i2aJg{l1;L`|m7Xl~KG<8=H+V;k6H{S4m zTXTEcY_-rVK8Ehh!d=_VUDHb>9At^xa`u+RFY5{`2HscXk$o~;2;0) zrzq*r2F8sbN)qPw-}$ra*&@NDar~1%e?VV(AInrrtW?AZ8Wr=e-r44RA8r$+FFp+L7rYlcM27#aCywXg}_e^l|_(TkR+JKpml?c5*njf7z}vjjT_{$MsL5z(f&ug@%43HdoE@o zdpvXrJHrwsL6NgjAWbAn`ouF&^n}?Qp~-Ne=$A@)Fsgl`twjZ3 z$^|yFUGLj_%yw(xnSG~aMa2B~BCvhq$`Qw2BHjA+%EoX!g(y~(b<;6+Qut@W`iswT z1+zvnt>JjAIhZu0k>uV{MItOy8=;~Yq~v6#8BQht$G`rFKYiy@KNz!aFxE1x6c0v{ z6PEa&{^_6be}DHKgfmE~*gl$3)PkhHM4T;v@}Nl;`v~%;7?Z3Ic= zf`ucF)IvXvuUxK$zV?+HynOvd z_pKYN=yEJZ+aFOJ4Ee^Z7kTTgH+k>o6Fz)=!mKQr%}V+Ueg4ibeT9`w@Y}zA%#)ix z_Ht+QQrxG#_eN_xpaakxvP`l!twx~h;u(93(ixGGEHBtysu|7 zz;A9&%5ITv8^qS6E~M}@y$G#@bG{(9b}pUrSGm*Kwhe&wf9+*d0sR+vseq4o_q(_V zO-ow{IcL!=Y8tfZ{v%5t(W)!z*~}x${T{K30$UNXy~2!$4*sV7)phen1k9sCTWON7 zD44&~(13JRPFrxcsG9c}*wA>l1%&_DF7z_~&#fHCyOd-%9IH*|ae#0ZktD>u9x{qa z7W#fZhE)E{oME4&^96nAFZ}=4BBLSBIec)>AP9jI3M(VDlUUtQO(tX_BJSlhuD~`m zx-L*bj#ckJCE4^|4sC*0D9PxZzd*IWkEjZa)x=3mUDY52X_`>ZN|MA&>6~#s-OE~{ z1k%XgtKJ0anFF81W)YGgt@6x>e@$owx|s-qGaott4xzAfb4e)Sd|793E~IJUFk$eb z4Dp=S8H90kj-0@tC>76}3J;PZ2y+O+@}_mWuKAQBA=~sGOKTz)LSU>w8;8*iMnwLZ zw0=5yyuOJTETXL=i3Ld>swP`pKu4ZE#28FbVvQkL>_e2cAIt+Q;aWy7><(Z%S z-BBKG$cAW_qn4cR_FI3A9SfP{tJl{s7C!jwfR#Z;ub22p@4lj{!fYZNvHH@>^kX;} z6`agU)>c>O<$aoBKrG7dA6x>fkhpg=*PEpgh%S&Ok6D+Ea#(IAmo=E0`0 zpWp zyN9Rz;OQ|pF0FDpt=O6Fprv48VG$=328~3pytYglD~=8=zy8Z_@{Jc3`Tc5#*p0FA zfH;nc(>|J*(X7GN6)H|ek|bDbNwPjxrd;0IpqKhkhkl-UM%Wr$s4t}Sd#ViVZo3}% z^ZM-6bT2m+^s+4L_xm?qee0FYJ9qx@F<%^iqvMMPG=u&sF%AsC*F+@Jp0_r-Kpvb4H^K`|>e3rov9-Y)=2n)XN**7*L1+r0h$ zebzVEiQ<^VDVnCiG^Lk0;GRqGbXgXi>aGL}959_b`(&@r4C2Ugnf$8P++fvLs1ToQNo$AYEP|?k}L7PkBN} zk2-bN$a$l!*N@DjXAxbK8J429Z}M+RFwa=GK0T)$`s82tY;ojKe~ZNW>EfJi1pIF6 z2@{D=Sd}Q(Q19&^V-w^qeu!K67_@0M*7#v@GQ_yH`eLtr5M5lQM-YSICCI^A=4E~h z&pl1f&0pth;Ly-G=MCQW4D##d=L~DZv}uVIfDMbd3?7Jf`mHtSS|j=ywrQ}U@l1LIEdqf z`e2XPIiiInAJgou`$TCTrTo-iuMO7-;iscJ=YpIqNY_Fm>YQ(s zVikGqxN|-hn$QF}hZKIcg-~rnVLa>5`J>tdH7~D_N+2T9G7guPsMJaIQjBhQg{i6wauIMER{XFH)_K>=0aA9ztKTY9Y zZP|Gz5J`rW2|~=Joj&zXc0hu&fwyl_pKwc9YlEFj%u#+f2PIlSqm>knOYQeGrM&!7 z3TCxoS~Y%dkN_bSM7|zMvOdczG3Dr#FMsJ0OPL~0BA)Dz=qEll`uNH^uUy;Ud+$Hy zcsOA+D;S+laJEJWi#3j7bV8)S>4M+={XgPudCZghH#rzi$p&kzOe+>wH+lWdU%;t^ zOgVn>8(*fE_prur>HL-uLek3;qDXbAf=$cpIv;N0<*UId>O$Ok0D=6>EMH^D;3bk0 zk~k4Ku`*TB0$&_|)J?nv#Ms0Cs-#bixO=e_jbqP@%>#gQFG9&pnHbD zym`WVyMjrh_|j_|I25y4fktw7A08eY^SD~Ut^FK7eq=aFrkpmC{>p$}-lK65@7>yG zIxARQsc?Y)?1)Avo=hWDI^|$glk`%a@momI>0f0)ctM2lcnG^V!ZnnKhsfC}ku=m* zNuxDMl2BC*Wl<0(DK<*caYnYbfk-lRi#mq_r1j%i=e6?Uj5N!fy@vi>gj6Uur^-Wt zhYQ+dcP4xap4FL#AGR#1hsR(W;=zDuaS10?KqoEWO)aggPDp_*YhV1t2~ixOn}TvW z>6(W2?sBe0%jYPfkY@@d8*oHV?9CHTT)2;f1LwUgGKkV!GqFGQZ8WkC2ww2OwBIur z`ke?`t;Eegd;Weg9joI# zEY5ip7o{-O3{zJ`t6S7gVq`*PYcdH*-lLjXY*S&H%KIB)N4dX8<{(~N!jvVmg9E5a zgz@tWRGMKeBx#SjDscFSZlmjV?VxECjkb(u1&#JH11tOtiCC!+ks8?4P}CW1P!f_j zrf%x)bt2pg&U!gd6lP9XAZ-oaEduJ7EkA@UAk|7KbnqlaQPc$nNEsr3g}_>GIG0Kh zIK9wJ&pCoP_I{A2(f$=KFo$hX@4|iK91e?$6OYzwjaom4TwJAYG|gm6stkHMCdFcP zO*Ng->-UM1grX?v4OaYn^Fs`%h)6fKka_Oe7svnS`8rdkfr|W;W=CK&pIw_fRGs#@ z743zfy(rE(l2qZG;QY!0)1u+&aE20+IF?<(Y>ef~=73qHDXNBiA%Or^%ql}s=}xA# zy1YPRAyI-GmzH?&^pvuJ^}!M+6R+Yh){(`67uE+PvFaLYAqAtN;px$gI7|H+YGI|H zu(_J^*`p!PKexula?X4Ay{0~n#F>xPN?6;m$rx_L9HFX_v1(0 zd{~jLt`a5jGc~M0AeBPp5h9YIO%Eu)6l8-ufFXn;uT5tX*hmq}xJz)GFSUOCYL|{q zekJDD$T&wN1WWyt_wF2WZ+pn!`^IH1Z!WOCZ)u8>UwPv?OKyzYDfo?F|9NiS{EXrL zBbJsWH!eQM*T3;)jMd~qxLKWu$;pUf|0&vlZfXux!B@WVB1^Bn!f-s}h^N%EU2L+7 z>@AU7P^RS5TMwA-jyz)$@(TP?fJdTTJPyF4s9)wQpCc89!?0HoUi9u zXpE<&?)DLf@QhQ4Wk36n2;r}*YLx?oXmRHIjkUI$fnuzsC^aI^sH&Pz_a>gfPhuv8 z#_SJSTk^_9?9AUx+?vY^*F{hHPvKH-BhIU0*{6b`;#%JPfwXl3*wpKS~L2k5pKvv8D+Piei2|>;0JDr*q$9 zmPEoiju{(RUYilI?e0xa16r{2m8k$6pgOYji1)srZMPpN}6T# z@&&50LZj%fY%(h~d!qsqMa;$pckkR~u(Ap&rK~J(ee*T0y>OLATbkZa8Q;Cnwb#GQ zmtKAzsT7e?eD`}l;ppguE9aMa@!B`28%?(Ll&6!JrHku)nI*w8$RrmUel2vNJj zQWW0gm!%0bU^BSL}-i1Yrk2zpd*$tWQxv%1KJ`#v=6lR z0@j73SHD7AYdVz4w!VZj4G4go%Ha?_ouQJLDDQ*vI&Ps9 zsw$Ap%rgo`pzEqbv)jTI=Ykw27{9{?5vurr z19Sl_kYS^DPLlO&NustOfF z2$>TJkN7tssx(P^G7S`r2iF_lFO-vbn$u z7nWEV#O$6_+}Rn?Xd8eL=dbMG#-e|Bxb2R9s^6uf+SnTxAE zPKF~sy#tH=lst*JvYxSb=QCFOl3#fJC3>RZrW+9fTNf|#ou7Y2+`e;%elBo}eSY-W zKK)+mpIwr(*{n+u}{wJ?4eJ{ws`f$=UH4H`1{A0(2UUqWcdB2 z4UPe44MIroi$Wk>JYToM-6+m{C?OnPcVRrs9PZ&r36}Eg+G{U9_X6+}zBv9y#}^IA z&pb2;FHI2Epqwwh(lqH7*e)vYa|>jrhyH86YiOM54;K0A>t82{BDc1_DV&QrK0Rfy zy279S)lYe_dk15jH-n#F=gqIb!mKdd-#KAAGdSl99%Bq5>7h{+qX|g(+u!&aTNk%D z7)}`ur(C_f&iDT0M`&I1pZ{mS#s?qW#yP{@-Vu);J;XKzN85L)Pxsk-7?UtT8_UH@ z&#}1BgUwZ@<0+rrx4=-}=bTP!HqT!~W&^Blc;nRzT)A?NdwWwV zV|n4yGJo;zUEccgMQSVf7k_aV>jaUYV-;F9E#z`j$@RzBT2{^ww0Fm_QoprWL5utrA&Ku2zoTp>8qVG?i(YAabEW2tfAFM z$8kb4J|XE1NLM#JgP{b)(LTLIlJxu3Q-RebPHQiHQjTJO-_NpxxgpK9kR zqNyPAvuUiUy*b@@2CGAV@qf0~q9Pg4LC-P?(aLOGKpb6{N)tyhaU7xR3g-k_uLm}G z&{{8&3&vR$1vSom+A%^Rh3)2n$TR6yu~MXIiqjrB%S zr6iG5G*0^zIu&(t1?T48kVrb5X%MTIh?dq6&Jkgek;B@GNcduGI-8Q^J)$(DC=0S) zMx*Bw+H31bH_st6&wR8DWVe=vHQ3(+p)-;KnMU31-#)4K%-6|wjTZBS>2~SyT%_X{ zU*6=c=a-p`$1E;nTpGk&-|BP!sNkRe`CW!HzdpS2!YXfEUGh>sf6kn-jyy@k$4fE3 zd5+P>a&$7`m%e$G8(TRGvEa=YH@Uhs;Q#r{+l)>MjD@r>$rNlZc*)M8E@_M)6{&me z;-dKS)ipkNFhpz1AXB_{X_@uR@gIG4osFeFy(D7ot*iXtvjcYaPC3;rK=8R8$w5J*XoG0lvsn7Y%`6H247HK1#zlc|@nDT#H0aVuHGufsAVz*%F14?`fs zvti8~RabJJ^oNW>!5df|V=&IqGzKLdr`mA;(GqXI{sK=APubnw=hYW4a`*lo$44jh zdMN^dHk$RdMgH!aS2!A;a4;NWE!;b?Ts*(X!m?vD8T0b>%Y67`Oh1dcc7BojPe-I` zfvcMXK6pIl_O_Q!8{=?^!r;dY__r<)!i9t_Ie)IsFgk7Y_I#+XADSrIhNPv)oDXvG zQSXw6`!n(^<>B5KYb>#l^cNPm^>Cj!Ib!>8O4XR|8P-OV2*^%47`t?w*2 zGY1tBUal%6b(PYTC-f4xwY9doMc0CTas2;1zGy&x#?h2gXk+rZaO!F6Tji^22^ zV$jY}fI0g7Y|%SsL4*)kCupjYhxhJKPKIJ-b%m<2oJ<D@${I~wVCpg;zrI*hE+&oyTWftTuI0?eV=i4^C+}sPyRgX{Uwer+ zzWhA*?%XFy6ONBh5XFeqxI!P?!W|#7#2ObCB-@8G9z1x$V6a9xjTlc0QUwbs>=%0! zPd{ey!dH22HD`D_T!+U<~iE^*J~ovbM|5FJ?1r-H>LIIO|arGved~m2JY(DoQAd<2^FvQ`hPl z7*holtszp1dO9ObQ)Cq5k`$JfsG^v7>m1eIKBg{_R-mN!^KLWF^6J}Ikh+La7LB&7`RyKM%2QDuciMItmf{ys3q&*jlpK)#Av-0+MJ zhDZvk;W4rPtIWk}a%g!o`T7eTag zp6)qhex9W4;%-|hki#3ul@ipoY47I1=vfwf5pTY@$@{mS@MrJc;UE3ho6O3ZzxeSz zj+z)H1xfhY!;=X`RU@sJT19apeDs3h++s{WkxUxP|I6N+Jy~{T=Y7Au_Zjbyb7f`C z1FBF!q0s<(0Gd6po20}+BB>B9(_t&Zc7**VNBD1Ggr6PZ2fv%LXxf}CQ=+I=Q#}I> zbYpCws!&7LT$S_9%sZWN@9l@Z&$$V*)fA;yoQUqO&b;^Lx%=#4t#7UG`_f3!NfQDI zC+9+xgsUg}SSdJjVu{t|U3Nwl1d^)O6lKLqFXr5eYuhR+&4rZ?U%kA{^?SRNWyN!6 zmw4{udNg#u)NR z!Lj+6|NfUQ^YYm~N(i=w1%L3vd)(YEkSca2kbZyq#O3FJ3)%#-l^OpT6{jP$j;87i zc**a-u@(FMOtct^z@>0U6|uCnynlBej3J79SYz24Rvce}^{uJ6(qFOl#-{l9-}yfG z*KcumeVr)o(0#H)B~l@UAnLBLyLSLW5%d>9DCd77X6>uGu3KqZCx`8mIeFx4_xv2! z3a#3zuLIVM-?JTOD-8mkJ+nZPD5_F3*NspTR^~hOub$)LiA9Q6p5fBP6Wn?_W@lJn ztYLmJ!4_lY>qBh4$BmCZWdHs>mhy|7dG2}2!zo*LM$FHjV1-WS?tycaXsX zXO4APe{zVGirQF4nL(;q3ud#Qz^sZt1Kr%$X%dkciQaXC7)#rl)hHn<;Y2_J0UP^M z9_@@;zm_{s@3f|-Z{FBKNoSJSaN?YCrJrke_pjP})XX(#X)2q63A|^(@;Lv%qTh##vDK zi6o@`ncvKXBJM5_b^0tUEzs%oDYT$Fx5U%YIy}j-BH;9iW&Zw`o?|dB*xozI!;J&7 zJj0ebTDvw1=@)NRD*k>~7|IZF$DUVi=*oj63Aiq(|`M$??NrI=?gKWlrT z;pY2qi0OXKt1n*St6zGay>ZQVuWhkCESXFuEY5d${?eR{^jOrpxA{Rm=E8{uzVU_2 zoI8Dt*FWB&t_?{N5Gok#?lB!_>>o^6S(#^Pp~sEePfs+;S+_X%_E+lCx|0VkzvL|C@WXV!j+7j ziJ5lKR505Fp$%}g)l^mG11aB1;uWuqzjxWxUhI(r9e+O)e8F~a^6cL3X*_U6#I--{$BSvx^J9HNU1p-ZF;N#Yn`46=^A;+Lgiy>KLv zZBX83e59NuC2l@ws!|Y!A%T=sRY_gf7^?_^MybVmgFa_u=0pe_!GETX<;>)o1XNf+ zDW5dRmNVnx4}Ok{&glmV30*Mrs<16$0(yK4fjTN0J<`-W&&tVDT#x`%> z+y!GRaDw$MNMU4a5xsWt`IUJ4i&vbar@yebDe-Irxw^cobX^TLkYor zFJNd~73#1symfoP^Cvn465>!X*GolSlx%Jf$aXfVwP0;-jfGUw>mS~DGv!CJbD zbDkgMgG7JURb>U%68BP?LA1;`W)7e6Z9K*+h0(s$t#@A?J*uSEo~u3p7JmLI-^NE4XLo0pPT41WB6#N9DITpKqE$f9 z=_AsTpxq;97?My*0ojvRw`5!pfRrXO+zRFT~XB)=avFqI2m*8 z<~sdO%!=&u!|(hADJ54fp5pquPr37Gi?!3|xq5bqH*ah(&I+&*)1u_rm4wsX9-ALe zxxRIWNvB}-vlm%7(Xl^X-w=jXR+r}J#*)EdjW(9OVZp}__g%GHIF6X{;upe2=zjct z#oF`sIPy%IXYOcxmZPm#&GQsE@S&H6%y%LtSUZmy}A0*6!SMgJ8haXc6&fXMFqG zlfgAUz5dSErwPcTtqcutjo5o7i zRY^caJ>6w88d2wC%83h-0;TA7JAC_%kJ#PaA>#a-xgh&vAv&D*pv^h zt+Tbg&0thfc26LB$B}_zcYnN z%8i?M86HkpSXn{z7SKV){rel7U+oY`!H0J?UC(C&fi*#^8z>ro2PvQ&>>>{Kh@>IQ z3Ivw4)4>=+mS;#6VuZj(F>!AR8AYwLG<*_Ov(W0Mx4&;>Hvh)6v!5(2f8rBG^H6;} zY5xW(w)wcDP`#B-l}Yuw)NxEb*hLiDJAS(!Rh0MfXytg_-Ras8MIm95AXQ10O?-96 zBZ+{;fDxER>ehM+dfQuKU2nhtnJe}*Bu6n50x-h2ZTVnA2!sfHwa1;qN(f|wDm6ig zY?3secsrRe_ot1UuT8M$aY01r#zhKA5Jhgo_fdxc&pYu6nZyS%?%owmlJEE*x>4lv z0d*8d2&u@&W2U1K$y}c#Ny!cm&<3KF6NK{%NG#c4i%ME+ zaCqqWFUqN6i6BHuLtR%`Q)5jH#vqMr%g~~71ZcD)(c@YZW<@gpJ*4yV(OT1FvBne5 zEs{!W*S4iXoa&d8xOHk*-v2?nHbAKyiMcj)n*=JKa9}OkSOOv2YKg171T<9QJ`m^VM&#%C40Q9;ebxqdqzXIRT8|`|N3u<8ojGVZ&54qTxRX%V1|=bm9FHOt zuy-&a7VwoXUtxED1XA(J!byy_bdr$qG$+@Fg)qucc`(u!HD+@h_lN_XA^-lIqbP-9nw3ZdaU9T1LyR?4we{z; zX)ANfi!Rw-Tkdk_;V%0JV}#L26;O_cTv(3z-Cz9@)8QVkzixT-SQ4c3+<)+xy2`1` zlA_3|irmEzQn@qL8jt}|7$L+=w%F9Ao8vO@t)$w4FcySVPQejp5*q}e<75UY#uyGq zQ#~ricQ!}azunRY5B}z4{`C6Wu1^z?pL1!zScSEYBcN-?xp0%(MU_8`Y}^K=qCrQ* z(JE$Ze=*HVaqq!XTi2yHT&d|q5v7qNae$T`!nks!$xyMrIpW6pfWNnVoL(n#&fAU8 z1J)UbNr8}-s;c<*58kDmW`uEvFo}8V?VDHxb(QgOV?Y`y&Ye3$5O>9`I|qbl%<9Y7 zXvE!dhhb+Pqe9NEUEpvy!59eB4jbcDQT65s&MlFSR~UEu9Cpqze>vvN!UEPpS;D(F z_pk`ell#n_K8xNg$tMB#cMmXfjOflGqsaTE;K$MpkPuFhDX^Amu!kM)6AD8AC z>gJ}gpG<5#!tYd}W&xdOe`iS-``Au|&RtR^tev$-96|d5gfZ0P1Io#mT5AGfNK+>> z>kSgUd0@i}@$(R$2siT+>(UbE=-!Nxna%6Q@KWGfei{<1ubv3c8nvF} zCrqQz<^oh91zOW460U^rPduqe;)pnnh|+ZCuHAfhAMiG6bk=%hBwP!P6fWSl)+HoT zNsJJbc}ZT@L{UiG?UGF=Oh#k6-7aaGl8p|jttC9RhFDxgC_%lufs&4xUQQiZ+Gr=! z8%8lo7>cUK6ozUvY!gXx}e{ParHPp=Q$4KEO71hT19V zk_qiq)2uaAb?xS$kQ9Yevl3pJ%^2;>I7Q>F;$CljAGAwgy}7D^K*_dE!OclGryA)= zA)Ms1#oe=z!h4SR-N?GO6yyId$gFfXf>Ky5;(Kc<>uX8@~m=+ zQEhp$Uot<}XLp$Ky^l6nSU$!iMvlH)OAf5#r)*X4p+}Cvarx+A(h0TqThkV zPRNTF*Z9`Q`|J)Y>RPiqI3O`O-Q$ZW6|lWOVPk8bN(3%Y3!F&CoyP+%bZWkM1!q<&?mgLKZMo0wB-5Vst=yU` zi;7;X_}#BP!*6~51oNS5$^7O|*7>uypE9EBRsCGmEA4hZ;rG)XZGNATO3iYUS;3+; z3vE1-ntjzT39q&^`@AOjwJjPXW}H0#oK&a~(z$+jBFUGp9;dEr)}J17e)Sl;2NQ%+ z?CuZQ+Mkd{l2|y?QH-S8KP0a#nVzQ%0`kL}qL&aUffSBxUgkN+RzjYCW)XBvS(GG! zpe$X2QfW)6U6P7+-eAfGP6#Ck&?@2f#+bpulwW%O0>Ar}3;fkw&a>xEqUwxqefv9h zXJ6J^|y?KMZttWIkDQJrxk3qmnH{|MPFQUSn-~Pof(qCNR&%gH}XIAIAb1UHb zgKg^YIM2NHqD{g;Jjyb%Xn`-i@-mMGB|F2MQ_FoG?u^JP!{yV9^g1znlPRHUKpR(a z*R}gDjsHgj05+Y){ceb=OM0my*Osa_1Onz#g~_J`X@^on!-Yt3jQNEH5r|;>2;foep=OZoRu(@V}J(wQv9H-}}8OpI(3G>(d0} zZ@nB@On_Ixk>o{5T^qu{6Pk{;Uok`3n%%VtG(>A|<6^dcC*`v*UL{E)jvZS;mj%0f zdn_!kkd>A@Pe+VLBer)2y!6sl&YU?$6h>?eGJ4C$5W2*a8A@0%1;r%8c;x@Wg>x*g z9^=vDT?Tstp8L#sHa7?4*@$PKy}<3;kJvrP_{uL_W_fMd^#hBaQdH}_^to5KaOo@t z*AM$w-+i0mI3w+Jc;UGP6oy{f;o-eUoH})!FT8w(%0j2xii zDCZV0d_vJ2|7{{<+91C{C)+zzqJ625jew^6`|d1~t??ONX~}8A3#@cL6w+5|npD9c zTrwh>gh#mdNC7&Cf+{hdaOr}6hy1x# zjV2LtfuutQUEtDirWy|tAzV-)Oa*0zt`xG?aCdXUy{G%wy5JW-Q?oGF=bP_6;X5~W5Mc}|^u6%#*7^ar zAMJAW#y00y`+Vi>&s z2$W@i?~qVbEQ^8*pkSWM^abn67)`N0GGU;YpOo%sIuzi0o&KmUCZg-*Rrg%NpP zaO%Vw|Ls5dHTDkGndVc|}nfW{*;MfdE5MYUg8AY7as< zFhV2f&i5JSrmcFpea9sX4>rfn9|S=laiEYfJl>hifLx`#Nv{XbtYMs$Ecav1AD`pn zd%G04YJ{=@NvNo_AP^y6{qh$%m`vE8)MPqF^iHxkm$0$5#oZ?Z;!dBrxenIUOo}P7 z>X03l=&GQf1S~GjGcG0D4<7Tvi)WZWd7Q~$$U?7!l7gG-_t7$;Fp?}UiDO0dbY$ml z55*T>xKPc_Exm1R@q<79z5i*Vm}eE~1_C;g zaQGniD01Xp>s~OKOvF##{XmQ+6PA}2u||{ElI7#4xcB6M>3B-oO*wgdg%3aYnDx64 z_jE96mQ)C$yygZ*Hpoeh>WQ3NAbZMC+iCs{yEmk&xhZ zZTpz;PstikfdpNVZ*4(7c1LGZvh~S>_B(5{$2R@SqS>fDROCQCcc5BtoYfx0?W1>x zsYJA&OY^=4kM#$=x8ma8U+Xt)7Q zHO6{Vxu&OI0G0nv#=8E0nCZV;kA61jWD`8Nz@n*~%mV8+kP!{f09XBx3MC+)PRXVj zoj9PHPCZA*MK`Y7+OInwWVh8N{~QZ{AU5qxMktCrr@Lb59baX;v^>Rq~zlX z`DjF^=PMzT5&2|@6xO%G8LA>DPP$G>r6DO=OI?;I0hO-FiX4IUPQ~tfJNaFWFg0L2 z*URbmhk^3k1C13v~MNM_p^ z($4?J2dAkNnzp~$jc*VrpIEqRi}3T(B~6}xW9^YOC0Z0Th~jpy6vC0mtFj_Z6I2*7 znNEq)n7XRaRuIJrg@$lt4cnQ+Xx;9u(l1;$*1m^p% zwcua<=pOsqyBt=6AWjj~;+r4sv$r?o$t!v=7FY0 z5rvM&Q`QwHmpc5@uU+IDSC;68PFDGwKe@xdc;g8>RpPipN6s+#brdiU|)IdWr2{SbMstZ?(yNh9qP$GEB%nw z4jhvQ_UefX_QdjnKuBAZ9Rek76vghV3TutAUQSq2)s+=OkS2*Rrsm}{eLB?kFFx27 z?_9qtURbR7jaQ$w8xjEJxADC;Ejz^#A%1MV$1H2b8$T@Imk-Z7COvzLPpb^z5Nl} z2NUwFB9_9NWV*pl6a;m_d^cfxKc}((Xt{(!GMZLorTJv?VJ-XPnn@|CYbRnM0xwho zPX5}TN=-G}`29?I1K@@~SsTlxQ}eudc9BV5usxXY;`tRGZEsMUnL~Mz!MESK&V}E4 zm3}{BWueDE`n6xNhm%|gEGtV3XaoPppZq0v_bf%ci0bt?b8?xjy)j$6`;>8wNF;}4 z#*61J@(aK5RqovQh_mO;*w4NEqNvM~Fc7@`(K^Gz!rTdVhc(&GK6#+Xj23&-1Fnj> z>e8{rI+XiIHl9zfzw7mB0`j+966fM%ahr{V&hDOFobL<6P3}AyI{oe{=fsI)hT^zy3aF0fecWQ z(`2v9l28g(7dr@Bkwjgz(OkT6g0rWVIXE11{>&vKBKMvi^5mdI!~u0xAu)XEh12vy!@oOx#LfMCTz=&YzxMT)8Py4I-`t|C4RI6^ z2a;3A=6L#Ki(4PBvvzEb{rxeoUOf-Spr%9W&4=!uMH3*;Hbx~aAvHywffc0P6l*Pc zRuCs0tcuV628`)2PSV}pQKy4CGj5E zh-&8XQO~Lgrrpe$MW(_Bt-=`y%J$VRfHguO3@9IvYNOrHWYfy!=BZ0193olU_M;u= z#(QZH>uxKt9|hi6fF;mvS;@GCHK&>k|h7MUi3AXq>s4z*6Q@ zgpf3Bq9{(>Gm{XC08E52H9;Vd*4-nfb}dUnQ%m=(E8RRpH)o8dO$OuHHk=T;B(!Z8q%g?a1qo%7{8jlHvc;K4S}KYN0A z?;W^30C?~I5Ni!V7$TMA!B}(mV2ls}ftN_N)?$R@gGVEDrHGOQMS!&-2fGGc#;Ey4 z=j}tI5@Z<`n*Ghvshml$R%4B5&lX`FC=f&ud%0!%QGrx~FmUs;p*v|L_xIehQc=Pn zH|$O;6cTAFin1q{r;-2wAOJ~3K~zE`xO#4p|N0j%@anlfiGp!f^36A{@yBmIVOPvM zPXxaox$zQMZK#X~Kzvf>Yf5fj8AFv72q_5@=i)9KJjvf*Q!1IIzRf@U`PH=Uh(|m@3FLYmXEh;zWJlu92T0B=bq#3H{XW+2V6LR zQrtO6Nz;UJFkySDkjLkl@5EHbaQpE9AqAJut~gGg0B1n!_jW&)K^&0RhQ@u~J;S4k zq@b$3_fAt8^IXBaaFw4%)S>zBPXH6*h&V`dZkpNIC6#1wkg+o#^I&U?t}4F!{$p-F z9ym#LpVS7uMb;pZB8(^|V?$Om47}C!JWxZN@%5RO=Fe;EnnrRa+dPRMDv~67L(?nc4ZDv%JnTZRwIP+ za)yo>a`Z$HzR}tp3<8Aml?~c4l7V#XAifX30py+f)Deet<*Q6}?LWN<_L`gZ!Gymz zDJ9ZBGmAy2geZy$;s}Ds-BTDk8QHpOrB+>wkevmWxO3GVm`xjiLu!?jL`gz67!V6Z z_xLIk4CVBYFbs%$Jx5F*k4ZYINBSK#M&J;>Cc$#@nvwTT(KOX0V+^&?{<|=Hy|GYh zs!F4US8|iWE2-F4F)i>(fY!R5L)P;wq!iSipy?!ZT|ct%NuE>r3O%amlSti2XFBpF zme#LEN~hlEP-I7XHwLE^Cu)RH2%K4=Q_=#9Y!l%yZ~_EUO1Gvw2S^33-J-6&%&%}7 z{=yi1riHQ6nX(yyu{BYWVsS~MiV_Ozk`K}8qx~9flJo{qZ#e|QB|$PyAW$?s5GS=O z+PWBk)S4>KKnTJ#K>@|^kZLqWMj^?CS^A6H&P>kz)PtpX^nar(_fKu2{VXbpUw|+ee+`5kAfUh0_BrQcXTIBAnDdH3ZilcqQ@b+HQA!b}u}>&wm5y1G>({HF zuWgmXpONl=>?|3toz$uDNP43?C4>WqOjUFJ{yvl3DO6=y!CWuq#@#8Oy|9E-t{PES zCE0jigiMiCAS_zvOvn4^VuTQa-Te`9+9gy0k8gg2KDfu%ul_@k#36@eVI+v!7<5_L zI1X)~LSzsKDTFAB8~~-HXt+s2NXpvSS{LZiHcST`d+q{fE`J7{okDB4b>kzhUi}RF zdwY~+juetOid>tw5a_Jp&Q6V#31S?gt>D=55@+TXxcd1oaP7toKE7=@tV&iE6Yd9n z5yS~!T0+Q$w5~0#2z3J7!wJ^G#fJqetKLy-O*Hlh}UY)z^d! z6OJt|poL;Mo-*GH`Qbb3Jo?ExN`(yeCw%Ao@4Mi@K%8`3zjRqp*M%#Ynwq+pP*oL5 zXkLH&2E)S<3yXbsh)gHkyZeA7fYoD5eE8uyFTe5`uB~tLldZd?a?0IZL8gxJtv7D) z=Jm&H4h^TCd7il2AqWBvGtD2pb&a^(QSrO%P#<%J~M^Ss>CVL-{?BC{3IkpAYz@1X-7qyE}+{ia`?h`-n<2ndT@}VXZ_a z{TUJ`oHXZ5igqTCD`cbGV%xR?yzho>+k=`OeZYEFi8VBGhPF*yXvxOHzgHcZOHxUc zpFbAc5|^7+2dmv!1WL89X|Tkm`X;2Dxs6NdIV!Vu3TUb@hN7ql;=n0@2uJRA+;Qs^ zsEnm9bEo&-4Si3#MOm+M<)5bu%AEUeRaPh^h$5$yR8KR4-W)RRAQxA#IG1s)HBo;K z8A`7TCTAi$ems?J2iyfYLZHinYclhh4E1+_s*r}m_cMi_xWA%e&euSMxNWU|?69YIq0iic9t zCsvMNEu}$9g$k6D+|{~84y6)=Mzr74RYPX(@Il~|tm>+E#*Wg>2PrH;5KtNI6x>045omMHC$Ihx7~g0id#!WgAu zN+XCCmk@F4D?RRcI;7i;f72q?C@qC?NDwW!>WugIuwFNF>97e6Ill5!5`Fw|vJC&;jG<480VU5Uw!@*Z@%*p=Z<}b zfB2>6IM~~?cK@C@coOo@{>Oi2-+lk5;`jg0{|j}b@}#XH?Q~f@ahib$sdR-zvGsJ9 zJNM@J!V726M)UaT77ME6{PC22ugm`4fZ>yS%*%+Nw?LT8kwg*y_U(s!=ff?cBzC5| z)(JTTfm01Ei`p6e`aQ*X`Q3(N)wD|qF-xvn?wV{O1RuXy=QY+orvbs5_5N`;=A1`BMw5F3<79_a356#It8ku(H_Y z`kf8F{JHZiBmw3`pJ`rj=J*^hTv%myFy!=VkN#YTAAj_Sq9}R!`ExAHrM&*p6AXe< zTgtj7FH0tsMaHQ!UG%)qFifm5LhNj3e+vTr>GkujPZN-zb16VrX{~W3dv~~3E^q|= z>C?7WHCO9@a0HRJM}98+CR*e<_dfn9(`m-y!W>yG*`HcgmU`TOGNFb1uuck7yEd@6 zlM+S=7DHoS;SP?PC=9T~tUuT%3I*GP4OF0bx^=+tU<9TjzQ03N6zHnt(zDO7y}XDq zH7nH#Cifo`oVvit%jZ~=5leGD-uvKV#*>W2r8%yA{x!-XM{JK6s2fBl7r6YTSGgR- z^tv6^?`@D(g1i>Q={y^QsZ$C;qml)LG3<^EK@gF2Qy*B^ndzP%C*6{eUF9Q=y9gCf z2Ql&SQ|K_p)HT9bPuy)158EDaO&gR@(#e-vua03#ioG4|G{Z_s(C-thtYC^7GdRF# zO)|eg&`llsuMI*;hgfr@kR=-b0MY)i*2Yy=8s~01YhlvHA)1Y9P;1)cH)~@Irmh{@ z9XNtslNdS!;ren-QP3Dzg7_h3T?p%m)sa%rNSqoQp#3|tl7u3aUu)Wx(aaH zN+H1deaRu)E|_p_bB-sXglUr!D1dC zz|KTH%q+@p_YYH+)RQrtG@`6DW;(^%1ObFmgtcxx27n9{v6ARo^TGNq|IODg^O>`Y zynSbnI9Bcb%mV%P4$*Z@l~)9zB8;Q970^i@i*~&=_tgw_ldROyhIakoE`RugyS)8yf{y#7 zUP-a}+-5&$E~Nyrle8;B9QmaXfOL|p?YeCCGynSr`0xvMws!rV(~hS&^4S94PJHBb zV#d2e2!bR<1-!82L!$n9K6>2|ns>7t$M%?WFbSm|!D*ir2757`?G7;HUdZ)b3A2C%Y5Z;&(*-YPO7gA}<^WW~|%GtOo}g4#@IHwnT3B`g=uguHp}2|xMhG3QRs@e41VXRZ@56_!a+l2kE= zBWjYTSJu*ih?9oBvF8^3WO+-#-U$I1tdz4NS935GDGSqLPym3 z2yLeXwsr`v5`6tDuW;hjD%Wm5<)H=mMUj&Y$Hd(ZX)gqcLx+9Pl20UhcOk z@6V7{ngpx)4%+>#cz%&e0Kz~$zbdlb9Vf+^#OP^;6gAz|HKyB^>|o!af@ud+W^K^h z1WWG!dt_Kx>bh=q>!ot!$skIay~6u{RFqz>8)K=ff~sng7|{mmO^>}x0JJ~+kCMV& zAg^TT_yO8^UAP`>Pwtii>A!EIsHL^L4{J0=yVp5H+qC`{y+EVKp zC7ctt(OzIdHdQR&if8dv8`~xWN=kw-Kv#a8qyiN{5JTW9n#hof0F}-m;||mo8w5zD zS|t1^@M4UmtZK^9l(;Vl<8X$!h}pdIbi0~6I77fwAneo=@Xw2d}sg`i%*`8CL;csS<4Z*Z_iQj zqt>{GH$Yxfb!#49^VqF*NqQJXZTY0-()nAIQler-!-vw^u-K2de0rX}g9#GDFMsX= zHy`iNTU_L;zjz#7Ypl^EaY$d5#HQe|FkF}mcxiEo@4kJ@KH1q9x9`8h?(RNCSs{dA zXK%opZ~cU4E}rM|rAusVJheN!yP`L@z~g0S;eY+#{&(`cU}<>;BU}YSDQ7BNOfn8fPg#56 z66u+Xlp(w3fuNg&)Y?#LNmaW&EK-s*4lr6Xsui`6 z)W&)d7sr{3BE`Wl z60kq1m`>e3YdlEw$kenrm^B7a!;-}@*ROOuXO?;A{hL%}K_J7nrJ)%z z(T<}aPEt?-RS=OJKY=sU&eHcEn9nl5cNAk-1is zewS!ziCU=EL=UgXVvSSbskNrAYJ#e6`{~g${iPMB?oKY2;Ao6IH5~Q6Ntnfrb$E|5f z*A6MRKFIL*XJ*Oq?DTPmk_rRTaE1WuBaY-pq95XJ(!RG12;mcz!3I55N|E-wY;c1t z`_EC{zrzAy5`qms5v(=7B{Wqh|G~DEjh#hz#zNSi!y?J|wn&wea4trNRB=RlY!zb! z#c&T5D1xNxROS3(CVZ7bSc|STwK0TBwbhF@q4M4+T5AV*O9jGU>Jn>egt92*0&FE| zm4t+Jt#;D;%rx@Z_#{tx31TT6Uqf4qFh0TXgmQ`Vy|9?p8$?R!Driz-t#0qr@mO37 zj{7W}1ZL%uC8I6UyQ@p#d$+Y~pKF2%sg(PnMaUJlQ_v-@LWXcdu=+Tc_B-`7E@F3|>V{HbJMLu4=5Y zgi&xrc}ln>Sc@6R(A-HY#&RU3@l#`#J{`##UFJO-dzz&!+C8%w>)9qT8>fb=Qfo^b zNIrXUi2%(I!(19r>6$0oL#)VYH-uwkpEuV>#4&m}C*t1Z44Okyj}<_f%N}lKbJKuSSpZ@gUi2Z{Dy!RX*AM-muc$>*+$c-B} z{N$N2(^=t1g%h;a&{>zX-KVMy6Fc&Q@l<%-Bk6STNTdo%PtH5Ap$dNS!VZ_WTfF_& zD&Ktdd4B)h+q`#cmyNZHJbGYBwDjk9HpKXBPwd`R;4R&D!nw^=P7d~&R#Sw_>GeW& z;DcL7RMxV0Jf_vkV+AqR9qMh9I&6s~O96Qz$+g2c&2VO8^SWTUt7&N{oZw_sJykga zfft^G(?s+EUEMeA&0NfO0iTs}R%<8NyzS?=c)rQvi`QMw92=n3k!H44Qn`W@Au zR62kdd6uw$I^m}u+~xIW*7=Rs&hdUO$x_YL^_*2XAxR6YOi0p%QbAV}-`YntYmN|BfK=>*L?|_&Ndk6^D?{E1_hqdZm&SSH@;f2ore0aT{n5 z(*Rq}(OD5u!bT?_?~9^jFgAW-QYbq@rb{F%l5AxO|M)K6orLqib7^adm6gEh{KG%` z8PnmAMB0X1?Y(0%8sMD8nkiVr#!8o)w@xW4!}4;Ek3RaG!D!02-g=quz4J1&S;^W` zn{WJsm+5DM|MA|ZjCS|=!MFc0-~G-zJUp84i!YDZJ)KgOB`e*Wm%n|@Z}u|r2jw1L zeDEW_`NG@$N5AzJMkM^j%@g*x^xUabt`<5K?1QPPVa)(<#35c-3yOSHSOhI69k4B z*~NrFkhU^(nnY^Lyebh3B!OC&rA>h1tijDf1xP7LF)PA?S(KEs64D%%rXYONRQ{Co z^8%U)b<7@vgoR+J4t_&i(2zN(5v@8H5H6tg4FRQgrSl67i!lkPWozq1p$=dc!iomL z4CrVBvWEK-4G!niDh9oB!OJ4fjV37bp4fpKDmB)Tbh`*=m>unrOHH0-Ob!lcc~5t9 zow4+EL`7LyMw22;T_x~^#S2NI6b5yP9Wxov8f|-Ddw}?02q?UX23RT96j&*# zEX;~Bs4od{)}fLRY?xUYt=z#H8v^&(lqrOus;W={OjEQ{n6jd*3~7?YK9umhthHEE zA)**SD3YikWg9_?P#v+&*tFI*$%K!=oQrBlATTDZaVq-5*jQ0ql;E|InnAqn-h(qX zB+^pQZsoY+0p+x!YIPAJ2D2W5uS#$-H*wyEJwB>#1%KjL)$pX=A!dr|G#X#};7{Y~ zwKcl+*jNE6MW_s9T7VA9LRLyhQqnAof&%U-8j$y%G}GKZnDPI-f1m&2`_FNBHsz0g z`4HoMpc*Zp^5GOj5HVN`qC^O^(r%ZKlgcKUaNZ%DjE%c>wIi&4wJOo#z@Jw-0(ju8 zqnOU{-jj85oC&>YtDS^zzp%l7_|`dI*lLqXC`-eKxAyqMpWWu8djrNcA?qd$+HI}H z6eZqy@@{+1=XVZg4drA8v`Mlw&P`7-o?**^_VN-kN#?nPt7rKF*tUSCLtPySm(ob= z#xW=t*Q^@gh-;dUm6ST6slPK&105S{9hTb(|LSKC@Xqn}^IM#a3cBqUGXu|G-o&QI zbj=RV6wHb)&t2SNRC@Mw*H4`iRpmH1IYNvFsA7z_4y6-TR#w>B+6V#?CM0>@c|k~$ zd=xf%EVG>e03ZNKL_t&$Wo59Y^4>d&vgB+y64n?tHa1upFR{A4&0DX(!fHqJE_a0$gg-kj=$y0GKnDE@r694(HKf{N&4_N7> z^m{p4$zb#u6N=i?$H!;q;@aBIG>NNFiDFy@uORO|-Ij)OM!(%+FfpM@5xKTCC9bp{ zQ3JJmb-g8{*nl&UiA#BN&b* ze17u_@o4vm-KtM_`zqdB_Vy3ieX`H`+A??UJYfIw4wZ#RyGOkG`YRZfLc5RE3K2M! zjaP*80jekmrqZse#8Gnp>rkq$(&1)iS6}0AgtZ?wW?8(-?q9C)s+(bP*vG(HyQ( z?W)22xcL$TG!x}!U6L{x4)D&Bv|1!9tC+%4l@&>+gHt+0UEW92zB)h(1Js8f4`VJ; zReVH_MICU|$wNr7og3X@XQYPX{DMxO_?1YV2T;9ym*<{ zuCB3rGUn4S_ULzVF6}Jwqo04lTQ6N;sgrQ;-Y##vc7-PgBi?=YGxC0qWNC@Y#YE8= zoH5Ah1Unn!%@n0HC`DBo%F2=IxcTCOZoaI0KpfWDka$FZLP~|LWiMqg0yN%)9wGoK zu{E#FIh+mDw=_vGv05WtNItv|=9Wr`*vDame0R;qma0jpL+?On{;rJ+>%>vXkmv{( zl&_qN(zb#ofY36iXicUwbSg*_i8Qk&dGs>DOC6E+c&#<+A88yx+SfKgrxy@~guxmb zoh$F~QB5uQPe?@cRgo%;Lratmu3)miM{8>v($-wzY+($|*JXi968`LyC!AYS{L_E% z44D%A-k;y3svJwJOUR_|-EowYA_VZAR)fIS&nU@aKTC|zJ)xm|Hky#;8CjPS7VZ*}75aa6OCvNE7GtNo0(pWEO!U)koh^F3Bt8j0h{@reKTz1#fB zrw2S50FFR1dX*MxOWIGk)#nwn9j2y3QNc<#q*EofC=D zjEjkvN{KAX#L4jqQfq|3mqihm)Idi>C!iFYYkiix31uTHwJ-R2BwBym?h~>2HrB22F^uPY^j7q`8W{gH-*4JB9 zy|1`_k6XCUqnV|hCd>*) zAOVCm`fOrYYUdn}DyrHv)YlTd%neba3GU)^)rpF#eKip1T-2veuA{S9KAyHD}@%;R~>lCws zRvviJXQLU#WX53TN$z}WjZt5d@w>K zEymM=+oRj)kHKtACsHffxWr^QeeF&Sz18|$?RZ{G}WYO%J}ezuHR&1 zxsCIlYZsPy<=T0?H9We|=QrQJ%E93ofA+86=cQ{qTs^nU&k6J@JDbFcn1v+t29>2j zxgh5(tO-UY4t#trHC?H8c~&w$uXs;vtX8=iEsw~sS*ZT#_`0)IXzW%hRD2v%RTUF? z85>%o5|uT0SNG6_zLZee($RP^Hay21&(@NaDp0uqtc%w*uPRvUDJzG}5-x7^_|^+s z{Mt+FyneCIS|>qz&)IOq2Vd^;uReal$GbD8K0{=oQm^B^TBOkFG@JKyi12$7iAWPN znS^^-S8$vpjjDw6HHRh%sn-=2DxJ-mLs*~ZKNZsZrnNG*^BGk-#z7bzj>9rkB)f%y*(yJPk7<#4okVVpqR>V^kffny6+F}b;RiOfLjmt>91`2fA-J+Kz#i1CkUNVx+3(H z$zV}C7)<#1=3Tz^jW_5o_4)Y2U-0>d@A2xlewU?Ob9>*3{QPSaqm0d+t8DIEWbb4| zubt3dZ!=CqbNAL-pO5Yjcyv;7I6c7&#qMy5V;ZWp656@O*r1wL%Ooousm4B3AV#AS zq2}~XDFwrE$z)nJz(JG1#K%;N!#L;BI;d|s>w;svhsuUV^}6z!MioB+&Dv8RHSN$v zlU3;*B%V>_IT}v+?n_&|@$5Q>r&Dg+KVhkp^5&I3mGAS_lT$waYM%@1UB3P5MZWdS z8rC^(JUr&cokRMqgg2jA=i+LIo%J5a!()&#u44`zE51o0@gxYPaejVoUmt(>zdmdLNaw0xH(+_4v+r-XYiCZ)|Le zvJ!rG{}7e8D2?ORy#p%axqE+~Yu7IG8^80Ll$GK0Pi_RHRR*;j2MC>@BekF`3c6W~ z^{s7opByo*3WQZyl{2xLR-R)s!^zn3+{+ipmzKeMX00zNzqrkF-+YxT&t3u!a;)E1IU*89ZW#>HGt8LzR zeiIYLfbd{Vg>r^!+CnRZ6N0SQ!xI)m>qCqyWbGCm5t%x8!9Nw?i)OP7i)Nlk+L?}h zr@jf$YIM1d)MOnbxp|?37|XdBBqB_ETP+UFtW2u)?8lWB4tBh{F6$hv$@M6K)p_cRG| z{fwOtbeMp+dCJN%m{vIFxPLH?V{Rc?f#w<)QR+I#sTG{&-6RXb4|P)M9F_N|-Vz!p z4);i;KxcVuZuAso#Y!h3rvxqe_ABQoW)spp;o9@(LnE_uq={fUJi|_gF$uF_&I^T% ze@=9Q6BcI@5CIUdHkd6orj0RKY8rmy_0);r;@``9>?jd>C7cc4<1Lo?JrPpHq)kM0 zu@2TmBas`ZfwAYPPCUdsXpmB%w5FCOXsCKZ&`90HF;1+MR8=%ejMPOXC6++rGR6=~ zDtHM3i?_ri%ZK|WRAX!@>jcBs3CjHNwQr29{Yh+C2dtRSGr&4SEhn0`^4O3c6!WG} z9+PkHptE+66|V37976&RX__)9;D7n^+Xw;w?GK*g^0{Sx|1a-z|8N`{rDf><@c0@9 zpQkl-)iDNSb+VnL339m~X?$~fk=Ba#+6r2SblG=sJR#FH4q3S3E$VA|0 z1=aCUpbU1GkeyyL=jJnwW(+mGWOZdpEId3vm)WHOLO?_sR;$;EW^=xw=+(>um8PgP zR9w7sPyJR+Pt#J+&67Z<6_VwpE~Rl;FX`o)N8^IqN0xLJ`_8=KWK`l3g?5UfG8D#e zer1{E)_LyVIKUW-KnR^^pQVWq-jSx7EXzpK3=nj?UCsuBD5;;5<(bz~i8M*Q6jChp zdTed1GkNbTp6n;$fA~NCGW22Pt8_(&>t`Db`)>r9?xe+RGDhi?q}{=lQ*KVz7~QpE zdgDHiA3tHG_q?B#PW;u+-sN;K#0W)ImdsA~Fx`~Z<#k%^9+g&n@WmdJ%HtTY)Jpi_ zJC`|~84?xfOShklxPLHWeK{kSo*AJ>uqfTr;A(tUDov<`7;3O7_)paalHrXtC6l;! zue5^#*WT%rqd`F{Q|zBj5eTkqb{WqMTgxp{A*RTg?%9Gg%YWQ`rij% z9r4A36Yzq)lNqIxj804b#gD&aZK=(qavTo~2ct9YAI(U05H=Z1OSR!GrWnCxF4f7j#d1mtfxgpgiIL0OheW}ze)JQ2iG zlcFArbM#u_T+I`oBSQ5g^&T-8j`{IV-eq`tBvw~fFr;E!Nx!syPTbv{Vy&mQ)aKmz zO^gjHDR=Mfa&T~p!bcB;uy89S$y@Efffk-`f9nk=XY3MT|(VD%6fQSq>sH&rOR!(#%Hw!;^@^!98gnWYv)>5W{gFkOnt%H9> zK#L}22%daIO~biGgg+)ME-vsQqE$lFe0&`n+w43LEi<8yIdHDh9- z3ec#q#P|97KGd((pQ)3r_+`#}RBsvYJ;l*s;B_N;?~{8N4@bKP+_-+5%a^wK__JGV zZmqJp*5}!C%cM&3S08+dN0Q|&s_6v0MJ2(k&N~w*V=g=kg~WO2_PX?YlD$JmTFWy# zkCQ=ts$LIj*K4Wf&s_N0DLp#D8y^x`6Os|7bnNR8ASBjQ%{^CAMPp78o5#T#4=OgJ zi$H~wu|nmni)MCleOhP`u1ygeg(FX_;M7&K@NBgX4%NmOWR@@-O>owt5<;@8f>CBj zjB82RAjw;+;NU#9xoZ7e^*9zH&@h^wBoR{2AhZya$wbWVoefR;<*XpfGQ2QYQ<5l6 zvHOs8a|fSyLgF4X^%{M3p3py(CY)99&wlh3qnY79`L%1jab<-+eD4uI`|60plL=la zw49H}`kt}a!sLlQ8R5Ev%n zDv++?@N~)tw-5R0^<8f4PB0242We-4)bmPLlxD)m!gFrLj0U#E*w4 zttd|_vLr?3L6&?`)vj4XV-nZIj5S!}7oZ6dKoVl_P*WL+4|84zsn@ajDzK*SI6LD%`<*wqwKt*Y z!muz@*0R0a$1MKDn9z)Jt1|%%E~%vns~esuU@;zAN}M*PWqR5)ZL^i4VTxty!qB8arvd!D5f)% zt0iJ&p*S=Qc^X#8hO%I1wD$=z) zgUWKYKS64R(g`JkN2dkCJ8WgyTI;aVNf=B@jz<;aG9>+421C_U2QbE1$8b_nRF-O1 zh5eDB*7$W3`rq&PIsy3=hs9#?q8n9Cre#I$3H||ffLtGQh<@Q4{6eW&EG)DFDTL2k zE%D8_-}c=+VPkzwNToSEIiu5G<0tRm;`YO1`n@*ad-FLS?wxRWe9FdZpH`=XvtiS% zsv=AVV_`C+tO~UBY_7CfU++^DQ-14vFZ1TBSGak1pKh+n62-L(%dGZNZ;F|?y3qzR z<<5I|ut!fg*S^G+3(Gt{8d1#(x~-Hf>(bVOE2}B}G-Y!4j2nkvkZ$K(+j+&`-W!WY zyGN{Vonv`*mCf}&>ut^EN{8K}5fzgE__to;iw8&Ce{{sPbIaVgdlIM@5#2&IWTkNT zyl)WszaEq}i3u<*EH@vX0YSGubtT2&0cJc38(epZY?kB1EON19^J)wkBqBI!$4xPo ztU|I8BHZ|hBNZXO&`9vQzyVY7t<&)osU)p#EBYaXV6uqlN#1Lt(}bFeBnS=D<#-C- zllD51jxrC7LUS&2WLVCrT3E|;G{rej-VGABb>%`5oA*YO=(&+MV{m?ihF+}0Ru$uu z0YVDeE6b=4-=&*J%trs`5BLtfShx~H7Xn4Anq+b!D5 z-B5v&YN6~N5|su?g%I4=PrMFpnyELxS2YS=_reg}!Rya>=Sg~f%&f$X&sbgSv%1{n z=EDIGrYV=VH@G$M9LiNLt?uy2?T2Kp;HBp;a{u8GMd|3YGn`Jqg~YWit6<`V2^A4% zP#BCeK}AQ~Fg}tb^#0f&vfyGxq@mx%#^lNvw9@D#NY0kU4C`FjT)jZ3d1E=$y%;t1 zENs}WZthp%-UdU+c`pGFs)99Q+03_E&riCZXEiv12-hck4Mau7G3L*!m1s7X zaxQOlc;oU4&+l}(y545Jt!xXW9=8=1$A3X^X>Dhv7h@^IU4VW zrUAX4xlbh$JacZD3!6QLMMXDPwEBv6Qh@`F zrKLT}m5hcH>~iS0`{e!i#c?*^;NXz5EWM2ih#OlM$lEP}Oj+tL39Tew-M+{A+6tF0 zULw(o3l}c1zn^-963fedytV8f9{Yd&^H0R1Gl$=52QiT(}6@e8Ildx8vkZ8r}sHAirZ=+mt15bfh2{ zTRD%?bHu*kt1qBw&9PWY^gbf!PE4m$KKSrsF&&+&>puSKh!aese^aUNMa zo{GBa;2UH!+`14zg}^Atbh3DF2?1HEHBt(+D=CkUpe)cjMRq!*8yk3?Gzfn~7eF9n zTxeswT65FAkTr}BJ}87=YL-DA2x%!WrKR*1=>uI!C7ROMAm=&_eEdW}p32x{ z4bnL(W2j7t$CKzDN^5GD>%e~&4Wci^)4Y7+L3xM7lPl0FR7^Y}rTRBu9}M#bFxOzSE@gVc+fc4TPh zigW8d(mdnJmZdZ+{P4Ti_{&cp(rKmq!|y!D|2dj)ZmrE*FP`Ir>kk?3ol=w)X_iqH z4qFyTDKP=sMF@j%7Viz-SD{BB(-DQX5p52EyD_1PP^%INqMWa@=se0~#?7$tx)Bnk zQ>K#%C_$Dc6tkd|RaI5+26CdI>;*UP*t_IhRB;RQ$J#iCRDhK0D%D&jHa3qFIob7C zCm`iOkf=^HQb@|83W! zGflLud=>7xQlYuER({i3k*A8aUdC!W;lg^G7tb$oWv$KjQp$23Xqe@!;OKbB z-Gedj-rVPxw@-OIa+GKgs`+00qOe5l&8pj`>Lp}h8IucpRlVE^rARtGrl-f?D(Ljd z@?diJ?UG;zJ#L>Hj*9qshxHrz%SKo}&TDZcyg(_$5?IZ-pgOY3K zB>%zN7xCWUj3r4DtTk+|bhv(J!0<4~j>oixVtk@$ojJ}u^9?q#4OB}}o*nV%!3ndS zWyYq%XlAh1`DdQWGJw2l@hOFm?eB%N( zZE-y9P!3Xl?@vCYl?IbtlXO8W(aOTSm#q$^aqJ#XxU${nAH8##EYm!*y~M|N4sk-p zH64c2D)x0WoqF-!LY67Y(o)%)_6ACaIZ>2B=)!tOt|gr;Wl~g_n4ruiGg?aW<_qT- zk0+!eC}&;T?6A>RtaTE^`DG^45-AktdI=B5LyGB?axfs<+(Bk-f?6Gm1ErZue(~@A zTI|&bzW8W{8^@S+pc75y1-mCDMQJh4gHm9^^RNz1hei0ldLNQuz48E)QjO#Q03ZNK zL_t(i_)eZ1M(NW?$=Ao<>i9YV`5O-5ofozF837$MrmBm|^D^^d1>~vO62AxL0ae)V zeU>Qk?6v3dD7H3M$Wz65TCudTgZs;y+}Zt-(WK(tU);o$Wem(6I+567LS=$XXDDS$ zbdo}nQyI(kn|BzGXRNO;^V2`S#j}@o7!@U3TN@ldddO#=+~nL3zQ^ZZKIF6G+v0_b zD;%DTnN^DSKmLNd4>Wx3b3Pj%cNq~>T?R*6b2PyvDOD9IO{F2R7I#)sjwLcmu-1H2T~$Hh z=y(syoYM}Czga|4BmF8O!2qfZJ|)(UVp1IbF+Kz!+8UV7m{pS~E+t|zSIeKq?hWTi zyu(|lP6}#-GvcGfbRw zdFR?X-AwZ0g=Ml-lWBP8mGeA%aWy3NoeZ6XU=JCnO|85YACLu^02*N=&Lya%LMAp= zq#}YQh?1AV{LgtGjRQl|s*n=pbyUI%P25^ZybsspokQy&38`Z+rj%*|xjIp(6KN%7 zlc*VE8`RSKIyoRx<`yW3vG>bZ*92X`(6UZG!sc)5WF(Ho02b8Jxeh5@lnAzXZHZ+P zbe7?Ps+h$&SEH=a7*Pql6<8-iaV}y2!h_b}jis1P&{;~JrC21L)g>~i866x!Wf&Zv z(cW02wYkk?Z;vF)n9T}OouIYG7>lxo+3pkaZ4Y^m%7&^^UCEnQ`yfdZT5Fp;s4V~U zk00`*>-)TOb&0pHZS#X?miXbztDF{|C#MCEPiLG?DvpN*!&w!miZN(Pm86pfs$whE ztoAb2x(OFnTCBAdokWr-fiV^1>5SWtCfwN_@cF}#;M_ko9E<^_kxHWLB_bw|P05iu zpcgf^^Ve!haV_yQ&#V@PFbLGzI$4(EoG0l950@aG(rjkU#@75abF6LNBLH&+jJUje zLd6*$05u;~?_%$Z5CW++b&6A0MVt)@ze)nIBSe`0C!>P*zC7g0Mw`KK-1z344rYAw z`7KsgdZhVtNdF8ehTdp^Omgy-K5Zd5I67l^HY8u#VC~WsmiswUX94s8j48o8?{w0e)xnd?dSRCM(Nu-QtYhvIUck)SzD$W9y1+{NYb3uooy8tcgLg4NQJ(n2kpW?*i>d1SBiTagH^3Y)Gc9!MZ3-DI}IyIZ(3coAA_?EQ$A~LHM1qF@XvX+E^QU7@WtMD#(R88(g!6 zz!*zeRk1fH^0s3JSod#OTT4FIm7s72HD$}$&_6*$LF=`vc0UJ#RIm?pi+WQQLXhYv zQSIXWaKRKY$o6^=Nucs*4KhLK94Uh8j*TjAvIZVpXy%qeQB@@fg>HASLL)?YuPLS^ z5|S*XDoO;Pl7y4}BRbnVv^O^yKG{V&%lP1s&gK@K?M)l2Y=gAMcXJ>ZrgY%#`W=F8R_5E#F#p%b7S$*~mcBhK_yJta8eA?pl))Tr12H9Vws2roh z28nthP^seaS;d{B!+0MDfFMZ}NmQd+tX>6q?D_iMZY3Bmp)jEb&ARBXqo`a^bE}*q z?_{*wnzNZhc#E-ywWSV6XCpqieh)L)qbnv{SZkww*z?Y;WjY=*98EZ$dU0lZyzu&K zWJ+Kh(eT+f=7n`tuTE^ewP-1W$B(V)ePK-tdwobgoU40A!dOx=NB|dwB~LY#4V81z z^cjic_>fc72zdruGkFOJuUvX4Ev|I(`FB)h0nu_x87w}ipAiJWjHmWbQ#(vIFXPpx7oRPk&zs7_w+%a7)XW6x}nk4xfr}DoGHK- z)ZA!eD(ql@H5G5Y{sPOZeXifQ$NE~It@S=1eEcQ7UYp8#4jw(BvYx9~H)(Y&Dqr&B?Si$ha4P_X|1gW zMUBxIYb@4*k_jrRCn>^0SJxKA!iFd!_uu&@PI?MKt2y&E(jlb?O?-z3xXCzBL)sm( zjSY07D2@-QPENvNhKMqQ^)at%HD*XkqL`}{Nl`a-iyF_zN3%m$S6?Erxn8tYtT0q@ zQ&u{lUcyBr1`!!u0+ei!r}`YE@QCQn9;#ab0u~aK_c-YnsA%CvHQe1e%4*7%Cj^!* zQUz4(v#1-~g`A)F(-pj!`9u$tkbFVy`LO_XMhRS+b8@j!wV4v}^HQpK4{fL}g{zI5 zj09(Kwu+yvWg9IoUOUHdJmoLm{g_0-@^`M$>t^ij@3Y)ZND|3xR&nLhCM*4npZxSw z#Ow?+Is{uHaL6P@{+hC8z5J%)?x|IVK|3)##vT9(EWjIwRX5xMiVSb%P-9gWgl z19bQ%*sl{X>*|y_{986vi8<~DF$t|vk{Gl#&yA<)SCTrph^tRr>(XwwQIBlCKPE~- z3X)bH=feW{C&C(>rz%$V=DkYB3ChZWC5URcoT*7LEqSoH};*MkF}# z%8NtR`zg*;BF$Uj+PxJZyfu}uCR7l-lN3dTk`9?mucTx!Dfz{XU2!l|$TR_^gHQ(& zFBR5%G_KhPjCHK^yKH^)4GxaZ(8(IPevYMnhYQcFl4p|E)R43~-1zJsGbicwbH=6S ztWq35Jfw5JMI{mfO*7EjBCbO#OJdc4CJ6D-T(kzzl<-(n;A~irCsT(cp{OdV%CXW( z*6li6sfmh=u?cCZl|WTc zI%ww^rHA3vG`aD3TClR*j^o5N0A(#R3=4^R1n|6d4ZzlIWz|&l`1<&}A73XRzv9p+ zyiA`Ogi7g!MO!?LD%NOCcrm<(r-9(`)&K{0+PQ!B(heTM>dF#D<=Hzt#Y_h%JI476 zx~o_ZRZ${^#>t?gt+8QxVtyP zoIa*3gBMDYXpV*_92naKBZ&@L;odt^XAzk|P#~w4I%W>RO4J#zD-JS9Upg1c@G@)R zq^73uxY+0&`U&cQy-q&%aFYoLjqG*ER@abPGCMk=I5{RuQ#^vItO7b1{RVu^ClH~T z$H&!L#%AfzRy;=-g{;xM`34sfk@$Ml`ZqoV_)bd@3Mm}U%edM2dM$(a8Cmm6<7ipb zkfI3yJtih!$a!Bwqhu8og2Lh`7LvC*(Fo@zW7Ve7)t6EDG?uD;eIKG%fvGBFqDite zo{b2}L-fUwcq-?qDjU28QXK-^8VzmkY525^=a`5fDeRhBxkISn$0B1=6Z$zSvTi4E zbeFdgN^m@NB%K~EUuI+kD$NlpMI|Yf6KwBn(wbWI=#1j*h;F}!ZuOYxKCatq`njIJ zvVpc^y4rB*(i$GY7oUB^ZJQgj3&xUg#m5!AxL6W9%*w`j0l~P7!GuJedhlD7uPIZ;TgvyGJJsM?MHIy!? z6cCKa>b@H(B`PAQb+sfYY8kw#Na6-=O@&t#PAYURG1g!_WGibpshe|h2+Gq_W@o3N z5~4K*(NG+{cj#7&?zxMUPwpeUAV^c-hF~{mhr&>t+iF! zYpYBT4nrkmHjTY2f~uUMlbqT99_fZhbyum3r8kHs}2`Wo* z&T~{bo{SA&9v7q!3bY)O=p%#+^G-#@Kj(sXQ5n_WoDbDVhs0YM?}xz`GnSS!e4+w< z&IKQZ*<^-JG`gKfhSR)K?7U|>7z2*>a=+=Hv&K@*3aqts`aPtQbLZ8GitDBpj>=Yuw2cx9ooIwkkV+$nXt~sgM3H0} z)+gMVIDY@<55!XDy{`(9r5X{Dd*_`{)D%SDRMc<|ClIBVes_|JdjrWt^$=Ooh=zzJ zAP^V}Ds6$16yEc*n}=+56WV#7x4(N0b?cCu_l}w7>rAa-*}R5E>^I^+Em&y?2&PA$(C0bx=vGF z>$f#8Twdk={(vV3LvWs}JAJmUu5f;}&4c|RMODRd9stn{%WFFwZtfZ`o!j4!pLinhSA2(bVe4>)YH!s3LVot&Gi+`@)N+@X$ zMq@tu>}GHjU0Oxz94jVSkvJO`S6xA6+ade0&O4203B9S@|d~5Gw zpa4pEE}dWH{SSBf@lQVIwbx$Yt=FF8{^JAIR{A75VOCk%?VMkGZQGOS3_3|UoVZb0s#s0`ETjCP*T?zC_=7^a<^6_}zVOTzUB z`Cv(5OgJwUVUhANFZyYLb(O%!AO7eJH7s72HdOoD9m>nFzY!(pxcAM7v zI#Nl><0FdWW3oJOdCRh*v%XH!ZehJ-Ivi6@3$kvPtkVj;7ylo7?-3+flHU3KTs#pv zQfF3GS7lXeF+J1Mqksi4n1unmz+y>|2N+;RGa7F^@yI)Gypk7QX_U59OCuKsz!t;7 z0Hde7S`1oLb?K_qI^xjlMag`g&y zVlUX;x?rnY2gWszxwx-2zdM+>FMdz$a)f_OQyQ%F{B!3V!c-Jl!TfAYl%%LZFQALi zi4{c^CRf27N6a%W_K#?_x^$NZO;KA9Q-F{y;qQ?Iuny&5HX4&pCO!wD+d^1x4j`RR z8NYil<;%~n^PS&#jVHUF(ie9v-L-Xy6O7d4PLf+etJ~$ZTO0Jo6S{7lliiUUuBK}1+bCuom zf(PeQN|j*a76mb#;j+IWvl->sp^^lmn99~pEP||blp*O@Gmxh^>wI`%Z9nacq}n(@ zhIQt}-%%8y5>1}vjjkn%G-Xv$m6gx9kOEWHZdRAX^N~jCv_Zh*&VbS?lEILu)$&u5 zGN+o1NxFRq>mo{fjpK|H-l|$u22)u~Uea!-Btm#QQy_^o^Sxc#n^)*vxx#dJ7ilVH zM<;Yvmq^#wm>-`KB`NuQMv^2%k-$_rN=4)cd!z_l)FzwG(OS_-;+lnsF@|hB!L?G- zIBup^2rt_G%B^KOY0M|j&Y9;1iwK&jT8Qo&ZYl6a5y3iGI!lb@`qqHcvk6Px4r~2o z`hyPdes;|Hyh16j%c)AQ4T^0Dq75b$^;AG;v$lC@NQq8U-)R`Tn9hh0W{C~P3lbeA#2wAVl>Bt3 z#F6t&q^WUmQYFLHC;;J>L6kiPI>BN zy~kVYyp~WZo}Cxm+qvM&HwiqVMq z$q8*|(7gf1TF%B9hZo*j``UV!Yb#w|eQwC0t$Fv(GoHV?#vgv;1|L5;<>BsypVV4Q zHW_hr@RVCuRzwnMOqpX%iL*`!sa;QLA}NH)CN5SH{eB1c_=wrQp|yDhsbZQo%Gyh7 z)p0&9fP~4s^i#C3=Qsp=hZC;6vdYaXeOg-5PBp!jVltkCfTcl;PCMpolr`>NHLF4^ z!E!gEEDh)5A~*wT9A3{=87I$1lazdyFRp+1^+f~nD=sBmX>Dblt$dni6yZui<##?& z3pat!&!WQy)BKgo|J0y6uG?<&jjz6m)G;f|OH>vPj!qa1I*ca+9_%V|i>DpMEl>*O z98pzaM(31eK{_0U;G&G_=_w9J+DXZ?Irr{8q}T7Vx^)GqV>+p$cVmlAyG3Qs-V6(mf8B1v; zg_9l;6Url0f#X?OM`nCMq1*x`cFr}_q8gfOdd`3v)l@7|k8PbV5=7YG91HqY-B_90 zhP1wd?4k}0^pz&f=oq|PRsA&)(ieSkX#zsy5y++}3A{fOC>a>rph~Ssa`V~}XOo~ZaJTpq>1Le zd&is%aU8MIP5AMrV~!pju%;($4!6XEhck9=e+t7JeDk+@tVG_CZB{yd{q5IT zO(yQa-M=I0EOBEc5?^`Y70xb3R7FWuOt|~$A+LVv%k;Lk`0(%^Ds5BFr%ZMxC~2uG zfmE7wb=gm%Yyl<&N}39%YH_$|Oap}Q+6)t#OA+S(He|3UshT}SO0QS&?s@n|)_LQC zx|Q&hD(@2K=|ip&lw0c>TU}!p(~8>9zFxmJtV5+k{)qIC<%>LvD=VV#JFTgFa&t&V zHW-ScLMu=Gu~LVri@+eg?QB(H3QO7_Vv5|;r;3as1kF+8n0ZFG*CWpgipmjLhfrWe zC{oLk>G27%)U^5u^XY^n(!{OAyKqTCss;0dU0NGkbhoZB+24brU~+UqcYT#~ZH3vv zF-h8@%I4@eLMusW3bc-yAMVmw-$X8TC`@e}5}bi_MAGXJMcNCeg{L`LYw1LiKY05Z z)4bx|-Z}Hol++pt5wr*h-?w57R!D?!NNY$WY_FzdqYJLBwfM^O8|06*OOr51WJVGA_PLmD15$;a;XnLbQV*T^!o`fzw#U> zlZr~tSlilQu+(So!n;8sRS2Zi9%PfwpWPw|prs7-Yd_(w!9t(O+y0lc)PcgCU*ub^mDl=0J_{795bFVXF9vA(&^ z;lT;Esz61J;fui2pse%L;;bmyIV#XvAVkOjF@|=mSXt}SOCwrZGMUbCQqhV1j80lu z8zw|rkwk4CAIvy7&*-F@cH+hIayCMyDP^IVO!MHf=+}di&PgdPd_lqbce%c3Kz_v) zr%I=Bj1-=B)$8@h%@}OeSZDr!h_Ju(cTtNv>n{ZAg%E=2bRvHK?rl!a=JW=W{mOGNslMg8N9+P$E%+eCo8Zxy7|KxYR&U#<7wm#tb zYb#9V8Ix(o3(pPMzP8Tok9K(fg9rZbw9py$F-e=*ct$ZDp{>OVj}%#{_+?U3Bn8SA z%#RLn^SMXQI$iH}C7?JtqC7wK%?FO6ENQK65OuuOrUS5!q?4l46deVTIKIGh)(hlY z1E2isgr^)yxzL`}Xtr~%L6~b>(E7mkmu)Bqz6f`r()0}i)W_@PhSgK)e8z}v5XuI4 zq!#>&I#$DPiq@anwHO!(I*Y|R6~S=^;gR!JEO`6HHHPh&NIKj`7h6=!vyz(|9h|B7 z{cqi%*NzyCW?WhA5+^Y~`)G&F)h??Y&5eyNt6j}XFXojSHy9O`pWQt{>RK_6e?6B9 zkQyl!_~IvNCnW8pY1-jwPm(e`uy3j7JkHCy9qko-Qc}S}Ve5)KWQ+PT^Ec;ViM% zBtlYTInr9eF{UR|NJx=MC(Oq8@J@)=R2{e+<`yhh^u zh;(%e)$TSno(PAGB#~}i3hwi3So;qgzqq^0a~nOjS6Y1d=oFzP8W(6Rp`jFx$oa(f zsw^l*XV^SP4+coqX{QmfQoQ%cGa?1AZx7i$98*?RW49~necA08`bOsg`#o-r7gwzP_sl!tH z07!w?V^sBfRy)Pj&&T&{&G{iERH17j$MmpNZONU7hfFUn zc<^kW&pvc~z@tKf~zM<6Fis&MklUB%|HE!H4(uDCEzG(uDEF zDf|0J=r{oxad4XR;Lz~q)dAy^GtN&=5NYad@9LZ*!dY8S>;jk)Hmz_r2YLz>uUuK7 zr3JS?xX;$s3e(bYay~%?()8)sgjOr2!n+T~!htbVl|^(k8=K2q%u1?q=I!dOA$VXS zkgk)a`Ee#L5g5O?{=U~24al#!v{EuwO6cH9Q{*$sJj2=`1qk0)Z z&6H`kJMNp`{HBmm%F1vE2oBH2tSq(p;fGJyxt|A-mG4u0t zq_enkjze&MTr!UZX=}j84^Bzb5#3(OER)=QI;KQX$sVN@y#2K=ar*o=MOktYUBf)v z=jxkZ;^xgQkcud2@#*8A(G4_-w_n=e+i%_Czq@$M!M%6*^;dt5@BGfMVP(ply)k8; z(~1P!%Mo^ROiRTK`fc`)Mr&9Z1^^ z(&oZJ;Y?0;a_9x;2y~}Syu1Pkvg0GFiwmMS!B|Ua49W5;s@msZjrT!;`o zVUf;yzNr)_sT;oT0y(pn_{TN!91dsy1~>1&Z%%3fYwebG8MU+x-Q_Y=SUYWrO9jgU zX}l~LufP8J0=7mYoA32c%>PK;aPegBFJ7?rpfQm`l3FCReO1m$FN;th3i-V(6D(iIz z&X)9geIljVKRg!Gb4f9tP!)#m`WB+)IrtLi9k8sW%1iR|b3`1Yao*+3K`q@iA^!nH zlTp&pM#B1Vp&(FNqm;MfRZ9E9U#UhLB4tSGEldAdkO~uAx#Bp+R8@E!h0jf>&^pEh zC!#7mXKP)U()eb@R0UEgKgBZM+E^&%3-iE-uAA7}(M;)(@E)j&zB^K&G@daZVTHol z8cqlkI1zGD@N`6sL$|v`y&)n={NzK>=(40z=vIf~{EWQJX$^*S`yHmohbUVRr7^`U z10anevV&dp<`sHdR~YZ^BFmiV(Gk7%b=s>dOpi~9(hg-dC5j><9Z?yBDN6F)Cy4d{ zD^=sz6>f&Nw|1r>4>@aT4>}xQwCJXqj+s&IKgLS0@sjxBuMBqC!c|^OZYoqTbvVB` zW^|*^uf1}Eqq8w{TN1Zg93P*OXTB+u#+N|0s<1`wsaTyZ$QU2V=%A_s?I^(t|K5yd z1@C;k!?m>@BG^zDWkHqYw1)jgpW+-;dEqB$-4>UscWT{ItzWx5)cCxhT{ihj)caHI z)yv{%F9R!nOSF`EfsSOOIa_=z9Nwlk(9a^>OkL{I)OSD&`g6nA51Wya0-+T`>hM0+ z&qYypxk3nJR8tu(DgsPNQI_OZ&~CN(^{>6i`*-#k4!aCHEuttU&k9tmy{<(2M#c$& z#CcFcN<#M6>Cy^>{32(#qWIkZFH;6lf5&puJ-8nQvUoef66N_J;&ASSNO?KKccKGXD3G- zAMAsv$VYofGiGvr#M6g!q!6rZU2Q~Vc~Nq<^ML)Og6U-9-Bzj@7yD1yKN)kFX}7wz zB9bU#Je~92hj-Y%zQs4+dWl#m-u>`CcOD($P!xF)iga&PS>jM>N^5N$R|Ti9rm*&7 zcWFzq<3m(7^W{jpO|rTHQc|28Q(l~rBnj3S3TsJM*U;_0=j7W!}^O+=W?IKa8u03bXsf{(kc??vE# zhpAI#9708`E_W%y!MoH;dF!QhjxXkX{P^4#;>JHDb6ji}8I89qVV<;4B zQcARr$gFLqVR4*Lm0=1I8Wc$={FOwban7K^M8OzKk|Y>YVJd^Q!68X560xPKCnwL~DxdV2`NGh|-iIpW~b%jS}+1 zJz5)A>1}Q>+TTZ;lG)KQ?bT)9gd84`BrVD!^Qp*6V#?AtT;tP_*>I`(ubas*84;rX zoX_c*4rhB~?tbzZF+E2q?P+xa-`F{bV}&yXP@;rDrERQ;sPdBgpWZ=LGxkr$PDT;c zu*;Lf3(;~KD`K#Ia%QL~%NasSI;xG+fRxPUIn(JBt-NuB7kXO`M;U+l{*+$llxg9! zqzWTZ(L%{shkR0F&6iO&763{;wX4x}U&jYjKdcQ=e}<{|9Gbr4avG1@;uDT$7~zS231 zM2645U$-(4i%n5bO=onsw$M>bX)TqJL`zGwF^u33p&<2zqvb90%U$4{7!$D}T$ z8c!+moMAP`89@@q*fIR*Z=aF4oU*j8az0$vT1Qn?qAX_I*nXb#NzTgpD#UHRd;19) zZQ7fC->euLv>jlp0yjP3>Sl`@n<I z*!a0C*S_^1{?kAFPhWoF%|H7u|L=eC0pI_A#TVD#>-wSr`Tx0$ah|KFYRgO&rV;-7 zH(Bl0U;jKR6pAv}pwuo-6W)6J>*%DzV7QDEis^L5V5!FsKX}aU!+P=~ah#rx8T4B8SC-khb&K7dW2)&46=`&Th!GND zE35;PmsEL46vwDow-CUeTXq}A^bx5LN6`QpAlBAxRo$)+?!Egwqf|FO36y)?D>{9;&$ zD#MrRL%bHE*M}(K_bg}xzESdFUEwE1jq>@wUv7ZwM{oKp>h%{UNiH-v)}fT-^;;`^ z?Zq`tFQ#Or<8hPnV(|mn0FrT^YpCtkA)H}zb4wIXg1{xp2~mu}6(NI1g#yWE21IF0du7GH zUYp@eg^)JrE<9pei)W=$-tEhJTj#PUaCku~aOwY&s_@hxEhSEh5GrWBVS`dw>oZ8S zQaB67luZ$6Ox5&*);X^~@MhCEJjFu*Rpk-=D2kc_P)fo?%hMS>N~=&(g>_mxmIZMy zK|dlO)e`FzuGPb}2cRQNC{SH^eSQhM28_1#VkOWJ%Yyv)2w7w}Cn%jGT3$u9JKh%E zdOeiTDe2}F^8HZ>}Z$K$ryn}DM4wcI3Ydz}gyl}s&~UZ(V%T|XP)gG7 zoH{9l81_2sU0D9^_?)ymK${F>3k3fA1d`EN2I2inlL(ili`^>hIZ+Z(Zy@!$x$Jn= zoN2DX*8KYw3jaEXqXyv|3(9J<7Y3?p-AwqiRW=i`#nxF*PD3usFHNAGb41FK&kJ0X z_}q>_IdaBRYOOIIMHk6pqE2|+X1#fRh7+|bSp7ZzHOV-_0Q=_|`{x;23UCHvOO#d! zEo(`h4_XZOz&M8yD&(HjMj;;h^3+G=pKI8g!JCgL?L+mP6BOa+Bm}q1`ri9{lAWKC zjiAZ+bFzyu$)HbXWf`P5QgPOQrm4*(LUZRFU`n!sea5>xbhoY`qZYuPP!U46g8s3@H%Ga4>{``&;?}paU#eg!Kv8qd6SWdBLceuHIgO&9SvdIor zS+LUC;^jBDxc|wJKl|aQU4T zT7xC=?65-X^G#mCqMS`g1_Ro|0aad5RV7L!$jGBTYlD=-lMCMY=rMU^ z`S!Qp=0`vKl=E>;yA@-d;my~!S$SjKNn3FI@B?wNbIR|0{dxE8Z+}ai6^aiYpL29_ z!7R(Td1Hg&%E0FxEInl}Yq9piE#Ca*m&hvU^gG;s{~@_|Tj4Lg*d(Uh&VPRR3AMIerXCO4P)gfA5$2iCj4=G0{ zL~)CvGMKU=UE9E=J&M8?b~UZJC@ZpwM-9_%J3PKeri#*18AoCqweyRtbsIH$@1U3$ zR7Hu3V?=z3QV>w+#*e>2@Itfjxyg%IpmEeFoVWk2DKXyVB?yw$CDg1L;5W;ySznj+ zAHTdb>mTs+r`n~-aWN@4KcA2nCDYt8&Pyui*gct|wBr8LGxiS0oL$VA7ZqQ5d6UQc zBR+e2#w<5{^!SvMQO?<^|~H;UF6A7ZK`Rppv#TJ1`-2*I)3sOiAN&j~=Mq+3_X4|Y+-oG6Yc@(hP1j-%j?wMl<#lZ(9r zM3FN-Jf^+2M!LFAc6``a^hS{;PGicvTztlAM<}cp#5xDT(Egh7PoN!@tad^Q*Dt#2(Ywb zjp%Ms6f2Zz4;_04!6<2=qJ(+jAcS6O9TE43=#>rML7S9wsx0>*e7bscHa&8v)dpK|tWhrzXLpc0(5lvTx7 z-guFl>m45+c;a~B`D;9W{~oj5eUeto>%7V;Oj#X5D&klpv6!;JR%O^{e|cF;X9vlXJ-WMUZZsbPd|O@ORqAtPdUma96bGupZ(}>L?+s- zZCvH{&)#7+z2IQ3&}38>Pe`H|tu;}ssVc{GIt6Et)`*#fKmYFc$@7w;D5y+DS(QX_ zM5o;nIO!B(5ZL9)I?c*jit0Z47(A`P%mO+rTdti{p#y-{$(F z0r?e|vC>%Qth1KVg$xiQh&-Ud!V-x^HR$T2noB5>YnqYTb34*X2%QkMhs04ze`OO? zM8BxGc5Rc%hmUyjBnum(Xy^zIfz1o@*^Da7vF-wmr{z%O6jed$Bu}62^64jc*u1jE z8!z9W+lhI2?*U(V*_h*lQ`}^aC->%*voi`Sc<#n^UVZTeDyMkw!_PoUZajaD$0sGr zgFZ|Blu2PplE_n?T%CsON2AtS?0T0x_grofX^a(!s({uyv0Nv&in!m$2!)x?C{-7? z)+LH!r0{`rs@)50XyNk&q)&afl_ksOsKAd_0r|Bdl*t*(`J~`%>Wx$VfwBnrlTr}1 z67T;X)uD2-e%lcuAfjBFj5(UZEG(3!;3FJV#@J9Ks>Us8v3zRLx}z#fY-P|%gj6*x zOHdi(IorxlQx+jg^#b*Le`h_~jq(Mgb&hxL9Po=zp3-SYw7YFiCneo>!j1JV{Z33a zD_I$&^jZ;H%WZ5`az4%(bYhl=9Y)iPTUVDUD$7zY<#asfqX(zxM2CRJOD;R1t_X7u zOy-M89Yvn&ENY>?So|5`5!*N=%PMkPQB^RX6eyE3vX>(;)U%iJpba0jHfv# zM~C!Un%yT4c=^>g+$%R<7XR`m&*)ycMp=5wUZOR{Jfob9DQ4b!6dm~hEkMR?qG+~w z-)o#gII7Y+Sw&HVbzU1#g|zcHO8k3XRbDKsyqnd0K1VBs(waIL)mlTGBq*gQa(}-s zXLDF%5z_k5G#8L&zZCuZP?=_}DlNfz6uL51(;O2X6X6?^JTDgOT(}S<7#>3kP!b~} zgl;!Y2em$Au|qCgn3`?WuM>$c@MWYZlx9Akd9=IRT1-x0vA*!4Zd6RNu|;vXPgKlk z>lU-g6d@prVrB;iw69*Hf9*L&J3ELX^En}_>$KN5nI9h#B`H;rqm&{}5(wpWJxQ(K zL|=$Iu!eRVAw&xmX`EC{&JU5!(d)FBogQ-a)=QM7<T_2;$D7g}^7HF_S7D1T2D3(N08=9les{nvFGd0kWe zJHov+jeWSF7O``wAu^@EFFJ|*^9;rsQp?7$p_$6m07qyfd}HjIrltXkLbvOj#a;qS zYRy3njMSe6S5;vn6OFyO6Kc^wI-k?y5I#rB)$Lh*Cw(I(1&GS$ELptkU2QiTMG;yn zsw%jDS%3c(22oaYI&H>hXN>m`NV`3{o12)jWVCyLkecqbHDr_o`tib*tiIQER+KT0 zUaGlzrN_?6jI6S}_T`t^zyFA{XHOYEcMTCI3_iW#ZCJamnlkPoUw7Fh$D}9mPJnO-r>YA{lG7wM&i=f7XK28LmY9W zXvfM?U6587+O$M@OeDEe#Pua(Xf5>uxb+Qw{>*W2GG$yW z@yg8`$k8tCR?5lw3}p>BR=aSq&%?uy>|4{2001BWNklsR`$t$mf1r7o4RMECc2Zl%M{v^cfL6iU@Av8no*S% z?Ln8M6*ooO8{5k)w=^f`V_v$s&g}=MoLuB2kzi-U1vd;@Q zH|Y<%Jl!9&wbbTYFRie1a7MSS$xdg?jt;#AWD-*g;e8@PIIyip-)Be1xICx(+_fgz zyQx!xpgE2N-*|bQ&0)$%k51WG?vQ0AcOO^0dTR@74DCd*w|`7eR`f+q+J{Ls#-(F$ z24q3n(ZnswjEeazV>+1;Dc@L6rl-!?imc3WRffn;Snu~~sa5*j4ttXc!j>X-Q>uJM zW>czpj;SirPTPmm85;^kL#x{+Nn<9bb4sVki!v1O^$rk%0U@MShv}D;IBOa!-g=qT zsI93?sDJ&m1m}oi?)_zFo1MiHn!QRvt|54=aa}flZ zmHQl3!-Ms{q);KVq!t595uA1cZNk@szSyXDLBV28`{qhsqUZRAsHTKCXE3wETbg!y zsHBDN_WYv+6x=tep#ZjiVp5h45qBxAw*^gFt!5Gu#R=1$9a>ke(cRo+ytjugGxDPY z(zSIu8$Q5L$KZ_hqTl-WU3yRILf4ihsmS<~fBuhn?WN~AyBISZ4mdkKVWk`M z@zJOJ_P2kN8#lH&+~4DW{h$9^e){7d(Q36D*Qut+m%eE?W&v8sKzH-^)VoM|;K5#M zzASO8%b)(~AM^Wv`0sK5@eV)v>Cag1rF`k-ZQ8v7FWkDti`!Q@JU-<=|F8Zx{-1Xr zlQ_G0LD0}V1q(O2#YopXtWow|XX)G)#t%7YdVY*DPr475Y2np;s zs`(6uBxi_WR5y=cH-UID9o!(U@j$32#k!FBTdWKT!qe1RsC&G4r#1j&`P~&|o|3 z&kf-mN@;F?`haCM=GL_(KE1!gcwTZbp3v)c`R(8SEs`VwlR4=s5yc5{?5UK_I@;YH z0!LBg&N?TIaW0CqNYfU1?kS!+(*7PPjgry_jVgr-CLG>$%L6$|`So;kdivzS+4MoZ zOuxAP?XNEykY922`z_T;lBz6AtgX=m*Br2)qrl)dpl0&H=l>1rO*nvo)-j&Wc(#8m zT$Q`CxkN=BgzAzcLsv*4Dywj{FtA211Rf1_K3vKg2RiZ}Vp}1Eq^umPYeSx2-R9o? z$4pPATz&2;X-`lJO)E_)PR1M_o$~fuudw~XHnY5BY;N=H@e^Kq`&(>3e;p&d3(mVA z+(Sx86UFa+g)k#c7_k|sv)jAgiB+M zN2G*Gd=VJ*Btk~$_9~s#>m=PJqBupx?NHn`j9p4&85N4{S6}4ySDz!%g3K;x1*WK& zo?am1n9fq)7an$@)2MS9n#qQMnhW2E!97djbH#=~3<4KAj>D-SaI!9RF6%-ZGV-Wj zO>^;I4{J=;1AYIR>O!v;KMSP-_#8?K;nB&gw9I9}(a||kq&;#v&3Je)BQFeRk5761 z)+%?Oo-*vU==9n=IhwMaB+T=Qvadh5|saWl%Y+o7D6(!p(&1SdD z&1-LRy!#NFj{@2z=&oENr^W8Uu~Vxz#D_am`fYEPQ1+BCWyQP{oQ@5D`MsZ0Sw|G7 z{N```8so{74?p?@H5jpy3XUJ`p@bt=iuvIM!{q_nU)tu*!voSzi?6)ANw?GD{o7+k zlN_CRjYbm1VO(|3Q4;b>!)1-DYVub8Yt14vz=#jHaF>QtTEX?M3x!TqeFV32^k+AAzX!2o^IP1 zKh&Cq@LY{_Byq({S9^Tz`JOvGoYRhHViJ{HOfHDC9j*-wUw>tT7q(Z}8_fA$PlwNh zZv?$8&3}+>utfIAeM8V`>{{zHKuJjyv_Kx*7Q|Zer5CR9k6ypVi&uwa=ewlL_|mNv ztcA6-pqmQjx}q&I1VQ9qf9{&m!Qxu%RhRmdrkS|x&bP>#!TIOcOjIrv-gTqY%iOcGBp3>ZwEh{;DMQ7QLdj2=;rN$#R5Js3dL-F6#ZqR0d}Zni!=Wt}5#%0%0vW zAp#Asw!C+^pi!%*PTnNLzX+-Qq^n-b3&7C_PkQ@kg%gWr?($u&r`ze$kXjd3Pp+-C zUe^?8V1gP1@Kcp+Hsf?>pQzKJx4DijOD^{J5ePb)8`vnqRi?SGm#vN)C?HTRrGPY& z+`hBVpp&rCk2yXWu{3D$Yu|X8uf2MO+aEunD@#O~^Uk~Pa_6(p_>({W6JCDpbw2*! z=RCguF+#`yrUbyQrUQ$bB3i$05%vi`wac=M?HkwmPyVAn=JBJ4eD8bTWoHsm6r0GT zM`a8apS>Ye#4O$5U%mT?;q8x^pY1ZfIOpnf6aL`$e%n32eVy5K!aUD$)_*EgF!8a@ z?|D*65rrmWUU*wwtyMkUa~@ch!dO4amH6qJl*$pTc#|Zlr)I)g#|NL@-}!9k@EKoR zfA8yy2IN;<)_X<@Av}c#Kxusm#amp9>GA^M4r{deJMI!MRY`{Z9$)^_YqTQA^70C% zEIB$pBJFDNr0sCyI#e$FhH&sD{Vte_YBC~jwTPCNsOEF>lOqI@ZokW~f9rM9M6dRvL>KezV=gcNke)P#lV!Geu&fN!;Hf8tVoPYgSeCCO8_df&C#N%x zPbzw;rkGpOBw=G?g-`D9Q3;KWJD6aHS9@#AfW|pfB20-Bg0h^0bF@2MtSPAHK(#>E zUv=T-({OPDp&~lnK6&N%qkr;s-u}v$k*-20Nl{kdEbVriPH)JwlPUkrzxZ3sY|3&= zqpJ*;TVy1WI>HEi+VCX`!a~ziyReAxXa8@tfDvenv zqeg}_Qe0o{Fz7C!mE@C0Cm0p;`pZ{X9d#H65 ziDD|eHls;tb}rZti)Jl2T=2A)UVs`akNz9u3)FfdU@gvi`c#^xSYt8P_=8o+Fs1XK zB@-xjj>_BQDoI&Z&GWEcbmI#}YjIK#X-{qPA#tAmqNJn@6A=Pps)9vtQF`|-ho|^O zk??sX(kEZ|X-%-}b>1yZsL+V8D5yP!O9fqr#g&Hn`3NN(-Ci4;&zT(^g4RUKYse@K zKN}j{Q1y6JRgtt)Y!c&=glK(>@?aP88ELCcp3QNt@|uvtJvtkk^sZiIw6}-MXH0@S z)?n)jRatngKtlrwQ;&eidO>i7J$u4`|9|{7-}~F2i?S@q<|9r{&N(_cV{&myJB`^t zp3;p=cAh@sDas*Kl69wAa=k~ua>C%yI-s|Q-w1TQAys1g* zH4DD~5g5GQP64Va7$2Qbp-9^824D)07QZtylo0wg&jZugHrM6)W=6u+&ZHwi9lDvcs*7E*<4qODxX~1h$;HPd|Gg zM&qdm{i>Wu3u<;o)6+R0Tq;8oD#U^oTCdl-;k3@8lqS}SEX$bXhS{`aT1-)`4QyHY zXKX68aQp|q`!=iTTYUd7{}p31V$g|MUm0?BYlD^LA;UpWXr&jRA0U;dTGuQFzknQ4 z`h%x7)3DZxx*-=*2XMe3gd^5k_$iJ-D@|E>z|mBO-p*lJW%(BlSpR_Qiw5LZT+^(w z)1rztBR?)yS|gMU0?I`J(abwOhi+dkQWp(My>(g#7o!P3{rPRClaUw>heX1FirIek zt1N9@r;`_qoeduHuGvVG(r7KIlt3pM9Y?q#_XTF8h%}^;U}ez8Im58q2KoQ8_g>GI z9od=RFEh72_IiKI!d3%l-_15;PqQTsIhx^cVmL!d6ACF5deGlOy(mI@(3@TqVvOj9 zL8-~6Z4%7}+M^pN00oqEpXI9j$V-gMAfZ(%r?0**IM8DzE7~T zy~5H$gLWcVU2I~s=Is1}G!$$swAg>I$Hm1{mZGb?aAlp7u@Sng=rj|~&IM_^&3?MW z56>$0Cab8eFLD;I@&0s;Y-yRRJ6HJN(HYm96e zi7PzXQI`kBWkoDpn*>%6$AY48RaC#&IdviC8(b7Bq<~RYA%rEY$=sG%Kw$km!y_SB zW?J$1jlAZxxZk^7O!?0e{(`wg2433j5-TW*ijBnvXZ?)vIHS`DXeEj?2^p789Vrk3 zlV{Fj!U_s)=nu!-y1s@CB#kuWVpI@>!Aw2KB|`3cL0wsNsL_lxS|>~Ors2<7Daqrb zAzMo+-}uZnPmcP&VyC$Cc*v(;*q|&+?(Ltm(Nstopmj-+4cxO3#Ivfr&c;-tq<41A zC^{4egOo={13J%dfo$=2?;g?)@3Gz}$;yhXl5~?c{m}(O(cxqQKlt%&_Rj`fOf@o2 zthTVevcyZzZ;Ab0=8|GlvbfM@?{vtM;~`cg8KHeI$*E& zb;swP6Xpd1tMJe0M-O-|mTvu&t@$)gns=T^&VmO|GPiZ2D?m?1OpXpo+ijX_t5~BM z9v*?Qbhoy!aYW_0LbLmJDKWHl5wkvaEJnaI*L>#Y5)byyIXane?d4srZglv&clLRI zuTLxuC+7nmK77pH(J7Oxz*u9;qM*z&VLeiNSvt5b*t+{6eH)tfPVkqOd?An+qqPy! zEEjoMf=b-$eES*Jabw!C;@7`$og2%7b^VIH^Dg4}=*TuAL>x-7vA%)!=++!%b8V<~ zL8azgg6B|)I>}b9m~#o?R6*boUFZEFl>iGt^uC%EKCN{;o$+{#!6bvxAm-!oj~*W< zAU|gaDXj#XO-r)0ausyMGxCw{h4YGZz3e=LeAIuhTMmRk3Sm2)HedfIza-KmW^tj7 zvYPQ^!p)mEIT#20c>f*xlgd}N>#vg(!yZ|$N1z1bivempL0OBi#u3!TgmHg>E^?;R zjOl2?(((dVw-*_Xr;G+8l#=9m&hA=^7q72!Wwpr%KY5+Ay@J=C+q9p3X+h*xar+1k z&xcH=87m7d7C!Y7(=3Oe!PEU7J6Csj=@Yl8tR!tU*xT|sY&ZUfU6X)3>Q%`36>LRJT>zSc3TuoRxml%zPHlGYwUt6ZqQas(;x3_NH5?}lLOZ?Ff_ZXFy*2*%|ti)s) z)o@CX76fV2-@;ltat<-q_a3cXaP3vA%BrH1MttgpRTf(@=lv-U4~MKTH@Nq-&)K+O zu@!N3y-PO<*jjFqm72rely@GSG0nB__r5eKFC#FQs%ACE#04dndiG(~qElDhu+H&1 zFAYC@|A^PFFS5COmHo33kB>)G8ovGZ0ZHuCQwCGRFc*CD2YW=yqJav9RsnB4>~lIO zSm-wS{(DE94syak&8vU7?YZW|xF%XLgM_S|tFee#0#~<Y$28Zka&$7_ z$CYMdDPix)W2*D}+`f2(sS28%1y1f+lmKMFgCoQJcfjZZT~(kWA)>YoUwT!Xo?Iab zW4`#>E(b?FHd~6LvkL-&lLiekjMW&AURZ19id5DG;qp>Zqtph0tA-2VjqFtI72t{< zy7FEj$~{9a>9uGBLR-Ljjkq3nHy<4bT+ZgLwiY~UQaiAlN;|aAx_^^OQI<}DdUO z0+(DmM(&L7;U-wU=FSmEp_GqsT#}|#M7*&}ezZ@RO^K6)d^*P3oFIyr9PH8D+F@a5 zhrz)ib~2>sU-*Df`ez8AJcGdTyNopi(jjl4K8KGtjcWr^E*?Q%({`(9&RyI&B7{`$;=|I5LyMNnwT=xmG{Seoq-VQYb{l^aYc zIXdlQwI*$(AVaJvvDOJ#2#=N;YaM3;G5Zdkml$ISqQDmqE)_ZeTa-=$I*yQmCv5v( z|6-DXlBguQ9FM#CRig){jz+z(M=e{(94V>SKqu4e+p|16>YgL%*JA6{{oFhZf&ghs zCI|bJm7%q}3sLOvsUVPo{Op*rsAw#A{CS&alKFbsy^LO8zW&m4TrO81t*wnKpG801 z2?^icWeEc51LB%nU}xt$|4fU`CX9}bNSjSs>#G=T=Kn6@gbid1mh&BZfT)TPtW=S1AE&UDYTEh?9sS z%PA&Pv~bXUSy-|H-n)OuXgp$})4^K9&N%1(;{#S#mgshx+G6d7Z-2mI zs(ElQVoHba{P-?+_s$t*6`MD2A*CWs15S=lx%2*Al%2Bw@E+s+2kgls7$0&rC|TdR z!ax7jf5Kub;ivCEWpyFp#z9~<1>tPNJ3|MHzTz@U}b=j&e7J??OyhBYn9K0{H9cAMD;zcw56RWe)aRaR-I!ZDZI+r5C%rN6-aX;7x3*dCB>dSA9{JwwFN(+iIq|;eub9pB_=kfKgs? zc+y9YP8ppZ(oRE%7->D0GGEt?CofD#-!GT)pn))U2LC}x}U?4AjM5{?6+yIY3?h<^ZKel%MEQgyZIb61Wl<2tF_Wi{Nj5g=Y;7?(IYE?# zH&ygiZ7=Pre3Yq-#Yh+Ms%*%oU)o@?B|w)15{}L<=%&{=J$S_4{sFIk`bCnjyvE7V zF?ZhmDf#f6+J|B$N$j~GrYyiCVM+>=myEThuI4gB8tS#6MixH#$yeEV{xdv!bin?@ z4`>U;^{!=Wca4peWkM;jLCiP5{UdJQd+LM&d@@*z7hK-IjCTGq`6S1hgs>4KeK1}p z_hnvC<%LT+m2!xe5Qsn#FLoWT!!o{Apa&7CW#H1)=iZk;N7XH3s~q|0llB=s`r-XYvy zml~0*kAC(X`1vtY)si(bR=48L0gd_tX1J1dt;af>B7(>(HrRSgxukXmR##-_J(5OB zdt)7~HU0fVu!8pH1||%tD*r5dkB?dF8*ZsJ7Ek1sXye7BjZ+9Kk(^EqQiKQ*GS0kw zy$swjDM3|M#9=6IJof^FL7(Y(jKB(4xNuzyo?1?!t66JWU7RaR?MdCPr4$)pC@@+h ztPw^RRNAt6^?CaH1#PL=SZFZJ6{jaT+2E9m{tjb}ce(3=gD;Ny=Tizbe@%VwYoyRXM8wDA zA3r`$Kz`0RKRy*CS*Bl6)XL2Chn%et*_mExe;q{t>rMiYcogxw`%=z^mw-IUGc28X9T z1|v<}5UegQF)9p;t83^m;?7CVNVVxMFVWmu=Rp*4F&QH^V?=n$qn2a%bhE{IV2}#N#8UO$w07*naRJ@!h)*!5=s4BFIu_|yzO}<(lgdtW} z#8FHbh2%v+mggP;anSi}#TSCKI0h8f5x-79OB95BuAD#2& zk8X2vFu}ZXlks_vEYFcaOt`Rsh!UVqKIXU5))~(%ADIU|))-#9v5wW6Z@qD!ab978 zjim+`qbV=#bhx(GB+D|2yrc*PPfy3Z_vnIArunD8aDyvrZSL(45P?LfIa*XNfHUQw zI#9Ya*XGGb?awfmf$Z{I8O&}%9?U*m$TH|7r^Y;4(eDRfaKHTqfbT;P8x7Ij04jBwaeC>1B z*jjEd9A&^Ysyrtv3WO9SQAlN6t6CgN;xy*=-4n9Bq$~}(C{WdqtJ@pcjb)T@?@5ye zjYgBoLQ#|mAqbAY;f=XJ$mQIOr`}-&Zk^VG*J?{&8|!-j3gQlsTyWp*}OE5 zD(%i&-~ueI4O-i0?xR$*Dx0gs;nb##bx51l#wRgu{z>8Hgi-<{0{>YOq$TjmHx4y< z7Oky35(0Ig>jN0$-tIt*c~Daad&U?_ZSd-`v*5`JSLMWHFgT$Y1(>oV3_?m7A{Uy7 zAizu~=;_!?a#lo1Ox$WySe%%FKer@|k#T|u!kITfF)hfmf}{}>t7KNls7cZFxw(p{ zK?I>QD?HjK$i~D;N z-}sf!^R+L&%=yW&O{0Kb|3WNwn%uelHt*bh%zyr${VLBr{~U+MXZ-g6^xO7t|N5_L z0N3pWDsV|&<)pR|0;v>{Z?&p>=!04EVP})-q>?ms=|TYvpJ zYu%X7z4{W;WV~?m8q3Qo^m{!H@89NUcPgI{&zCSE#AScbS#laBkwasB1>aZEP(l(! zk$3B~#8C%|%y~ z(~PK*B7$&6kQbI&Ya-TCl@(DO&05r+>a3P4+5m(|O zS>4*)y)_y6dd z;?2MLQ;g1StJx69kbm><{s*pKzv)y6{c(k1bg7MME&^dZXXP0aOh0!W+Gl33xm-;C zc>MnxA15F`XI%7pD$jHTE~_5*FHl8^QUP`QKt1f`$#|(EeHo6NzZk65qAW`u-M=S_ zqF`}(nW88ekH@TTKgVHTIj@701LEa%N)^p2D@h|FDw|}JDPg-y*lb`BC=8$bJW-;NgxtKk&i%b}`nf?wDNhc1 zEG>4(N=;l8{1;#U6jwJFz09hlmBtK*eW)@PIxWsd6@T#OKji7jkV-~`GA0NN%{2Da zTtiuw1WLKexvxe9K`@go43whM@F#!vmo!@~zVzjgjl}*>L%ZL`-y|br6LLyYb!0z22(DE85@f!_xAd3^R4tO$q<*SV*=)zCYOSV zy2WM2N2!sLdcJ~?map7e%qxBWYO`!F<~ zVp(IUN+-Y&1Zt+RreWVzWRDDV#h#DPakdj+Pyt0l+ zng}VVIK$)xDhNS1b-$q9L93X`3Y2B0MkEl<-MW6%1gOvjzShAtwMLd1JvMUy7w=b9-ok`t`ROQpuJE6 zIMIZ_3rt)tGS<(L5P~p?ow4pm_W3%im(sbXBLsCkf4NfvYthCMqzx~QI8Sow=dYe5 zQc4yVJE$b4D4n=OV|fXpm=H^)4QZ%oHzQ6Djv1czXf`5V`@}WUMvO6*NmlXjydVuF z&#$*ISQ<&h`MBWDejj7iOeL#!S$8<1nW^WU9UZdx@-pA}!iya2@AJl+Z*p{WimnQD zk)xDEi8>*37eZ^xjHd-4Btkjk&ieTrjVJWZPk8CMtF+~ajSh@@N8BEaF$VIypuMn6 zy0FCdT89^xTbw*vW$(#7N*&W&xk7Jhc=+^y@n|4+c6WLB!EHYEgIpGS4tYLFAoPy=Xe{5hUb4_OtuP%fX-(Qm}L7nh4@1?M@dX1Xfpk=G7M%n->4; z@BfGo9_?YwF^%<2D&-WOiouw2Fa#mU`hCh_-;uq9;doVY?Zq{I{fjqv=k|o#*<%Lh z`@~g=%pV;k}Cw9ooZ zgY`zl*})Tj?JF178crQ8QZ=69npE(x=%rj86+Xv>EW5Bb4Q-X(}q^1MP<+KM2gH!Q_)QrO|> zZE@D0aDIM4vUClE#Ht9HgrEYiOyjm9Q8cSZ<>2P&( zk^SQfzWd|*eCf4o{K6-8DRo7uouW`SEnJmO;IMtIU8T%NTrv=|4P4CHt>#8sHS9lI zD19Zn-dtwx?iQ-b^7Nq3ZZ|>#ldPmDDvF}wTR(cj@ll^v8gOG|dAQ$aI4{l zXLpZzx_8QSIADAAMSk_mH#q4}x%YJ6t2NEhnQSiu(~NTQU*R5?Z$4uL~3os2jdT+nDX>0k6%T3QAn84d=l zZEVtAjL7qxAc#;>yE)^LrT`yo7>$)7DsG}wK`l;D=~_7lPk41s%UD4Wxb`Wen8}dV zNrtTz!hEu;l;des-pET>ZvZG=&vIE+1X3UaMX9wk|*@1I)St?pnnJLMVicurhR^j0lKUH?VPvv6c{liesi)BXUD$ zb&<(%Oz+^3#>NK75Z8$>>Vo^MQjdTz2?=dD6Iif5Se?DbkC_*N`vHQ`wPPLa!E{8D zrsP?Ur6h_I@{?l%tqHqJ)CC5x7^{)701={Wi6|-pDk>rQgTMZ%__Oc6LusTaijvWA zKsGw3%%?~y-nsX`5ScM&XQx~Y#)NU=))6~LH3OwEx^f-_LEzevW?X{HRcS9vYYceF z>p&_-<%Iv^cYcr8-}oUxW106Jozoj@{^Z?)sM&%b#|lZ6O|g|lgw5HxxvDtxlDD59 z!lPNUxcM^q&L_Fj-}^c#u5Z?ir0v%xcmHNMg8!^Kq4Cc|6k>%V|JO-zy`MTVvzP^m zvwLi3nrkk3vxe;GfGW#rZEa(t#CvE+q=53GM|N~Vys|>Pu;_kwDaaI3VyMvr|Gd?L zAD(X_!eF-UU*=dup`@so%j(Yar}|Lc`AXqShV!ImrlwWjXDqtZ?5s6;`L%ThS;ga% zF~9KKE#BSh6NHK{y}Zs_AD*za(qd<&!5=?7*x2B@$Iq;kGoffVQ}qpCD{QBvg@b>X9trbJ1^`5@!p|381rciy`1 zNZsi=VP}o10;x5fMuTad+mpv1h(G$HoXxi8Z@>MQJbL(u#gz?SUb)6(JmCDIPoM&# z<`N=o%+{=n!GJ-(M>ZYXqRfRfB{!dYiS6B+v*bg1Bjn3T;zx_emw$ey1&fczf9m)+ z0r@#2Z8U5cmd5&OMHGifE2)ay>)^{-AN6HPO^*lzADP6~`f8oQT0|U0#7f&@d?X54 zaz3_X;|tc)oZi?XC|TOxW^jB;H69~d9jZ!`jV6Rr%p6C9pkBB%)2!fy-8IH%Pe}BT zfAdd2%kbvZ@RSd3zh(c$jqBq1wS?Zd&Ew-S4^KvX_0!jR?dB@WYs(~| zq>%&&8S!ZElxC~R)z>~lRhFp5ie@Lnv?b+gOhYQ-#SY(o_n7a0cnU#)wIL@To-sHd zG0Y#bz1HITf+SY%8tO`OF&@x6J+|#e!)D`=$O|o^M2LU;t6wHa8azHY;}3uT_j&7k zf8(SGee!38^Dc-Y=TvF|tsOe$T$~NZM@LL;!tZ_ieZKXxb3~XTqLv7v1Q`TC-FqsT zR1G%TP*oKOi9!1wP~nNM^D10@UuXB(Qn&BA;9givSuvev?5?$W>+UJvzkR@PFkySG zOQZy6XG7k6>jA&{YoF$Pm@}GWWLe31Z_JhT4vVdrpWZpdwWbB$SaII>U8{UpYbeH3 zj4?#b)Hx~pWMxiF*Gzi@tdummZ5PlA>z&_o9vzS9G$Zm-lNTCeE$a&{c9&ZeRmIw3 z17j^O>@M=*{(woAb7iB;dq4eiAJ9$M_<`}Ih zwIHzm+6oseSrH)W9%)|*bYyThs>;j*J?qtluo&&m-x0Z;;DOfe-h@FgTW9K?YT-9R z>)%(mK^SA}a3v(#bG8!~+I1R1C9d!;1mE)t|E8Zir8>tt;< z+kM1TUz^KS`nrZ)Cm}WnNjJ915BD(H7-vS7QAdOC)bi% zUvA?QzB*tM0)jA{aeaiZ#vWc&?A^-=yOyZ)0?mys$=WI=NEqi%lDQm>u>BJ%Z3v7& z`IVx+N}{f$)a#vBu0t?GU+XriS+Hy_ozLt~$8V}f9n4FA59*3dt@8M6pf~3|8lMHv zyijUz#?Rwft}G?WTBZkk=&Yc*wT+FFnQvDRNc3>P^yG|qX_;_g5$&bIE%n^t8I{XA zfvS&R_|6AiX>X?ZY=Ou4_sjsSkHi6WVsg113*pT{FTKvi6RxPS(2VFbBARK)#c;~T zN|XKGgco-fd1t&rtL$nMq>`^SCaNbz*?D&FmIHbA0?%KJ%4~Z=+^4=-Si;HN};qB8?(wAT5L{B-J91t&S z;$nib1=`d~v=Si|gb_L)P>s)#af7(h#8rm11|^}H#&o(}Dr4y^ufyUhKYjBj7&9Vn z2acy!OqfTxrM7lu zZI>`fIX>LyVlZMko6u~wXY)>8LbPUcAD*2HF!vnth~cxP=8wleW_+B0{G4%dey*}< z6-r#cwy}ah28_oOhW&He?FL1jQ>)K7xKSbGOs>s}8IR5_rEae_L{UIxg!t<>ekR_z zcffP6e3p1|lf6^H>raoVrc}oj zs-oRYXoQxLnGh&L6ewCrKoUg^#~DRg5-X^5#opP3tbj0(JlgL$)e5WGKN=B+ibp3? zjz@b$Nk~<}v=Z1jp^xI-o~!tp;~t}|LK`42KuEGtPF})ZuRsSmJDr$H8!GD-*xd>|uY#G> z?Ctx<{K^+^@a0!GIXD~f`Ik57k0uO;Q>NpL+h-$geYnqS&u>xYIcrNTUU_bfFTAwD z-MjnT`EZ}G-JP{Y2;m5CE{L?Vl`o%6(RqPN;+aZGy#YEPrLIiQD?G+Ps06RwT;|1{ z1s)$<5DClbV#=d~J}>Tei4;6M8nC&TaCR|v*I6mTAVf)tOd6!^HgTj-){rW}%1)QZ z`{%rOcb`t8=#>>;_~Z??U)$l2|NIBo-hho@z|!^thuv*9nuZ_z@F}gN$&Gf-_C~~? ze(wp9)#PQxQhJp;RjIuc zrR&X>z7;13lyel$b1(fXp4qguF|$qBB_nR;X>Bl}Mg<|Nv4Bz18IMZou8lY0mW?*e zG-Y~nNdIg=cd0{>7yh-1qA19Z_K@rA$h7U0kgQ)^?K4IDIr`xPWVqB8A1h- zGE7e%F*$rl-0IK~FCwEB9nUw2l9Ur=xc=M@W?_{(`y=0*&wOt9VSP1RAsy29k)Z5S zrb5j#m=E`v4mo4iFi>xY_4gT{c+WA7d6MhuIdkM^rkZtmTb0ZR=hMRjs_B&G<_;td zX|q00)q@MhM<>LKi$qIHz75jNN9Q{Pb(@&*#+#P~J>)Y&9&W8ywLOY(3QxM!GeodH z$Qd$yIWeiPlrLb-+bzv}-da1G%qy*caaM71HsXF15C(!qBsuSo*j{dO=g|q%X`4?x zx4}Da-=ifp%`1z%vK{klpIv8fWy^anI$#XtMPHO4P3qk+71#VqZw38o@MGpPg@!zuZ6iV~LP zRMBmxZe6Q#*E%W{?N);{4*Bu>PmwA{2tm7%(&%&;4h9TH0~%3G6hI>hiOFm`Ml>Qx zF&$y6DgX9g{ifa7*%oiS`6h3_^Ntgu@Dnr)W1=t=3!Mh5E6c>9WH1`dI8>L%<(8|< ze2{0jA0L^eACLd^@o@t3b4EplE=nn_MJnOi8W22udc^+u%<X zjX0tZ3L8ki`_3Wz=NS^q?&cz|-CX9;-YIXs^$6?HoY{6fOGL!HDv2d(H=&Wv3<~G4 zzdIJC6zO6Ia6Fk>mRB3g-MtF}3~3x9jAb+_Fc#i^a6-3{@a}_i9v)A;Gx&&?t}XLm z@0`0&&xt!-K0M0k|IG(1$C6lDmRB90q^&fcywc^}2Zxm7F?-_ya(KkQ`sG)+d-nl% z-y0LI-{j!njIX`2MJtW?&Kuw7XiyNCid*Y}eSBPqVXu!&nmm4b3Nj?uf;5dNrUhpQ zebQDFV+EtpgoSRKh><8J7ua%4AT+50BPD^&84phBG-A4~CjFvxVZCsC9Umd!ROt;x zo{4WyWK%+!)mv|mp^-jZ+`bK`;*ccrsXA~93mqp z-CZk2;crb{C9c~qYSEurHP$-0T_J>%fK&?W=e|(R+oLKgz^Q4~L13K_2rt1|w`U2Q z&y4nlYg#+SEh!9P7`pb75-E1FcthmKEzC`sE*qChY{I;6QF2+}5Hb;;-E zBW*6TnQ!Moe4UyIe{Hd@eJzMW(#;*RgFW|=rcYzBwAV`UR?5ulk?-0oMQH^Al?9Aqoz(0$Q2dXPO z+Y6*{NUHVpMTV!{S1l<;5nuYi;iC z^|`Zm!6$Dx1LKXA7GV{CS=D4Gt^L7gVmbTlXH~kcD?cA_qhG;2ZXkyG?qe3pDP&z znnn_!iwqH@tlxMM6DFJ=pYZg2A6rfl0?MMKwXn|G&MwVdkQF1&$J+UEP_ek!W@T%G z)6)=RE3#3a;d$RaeWJuLk(^v)7-JY`BeL;`mBp60vbDnG6EE8L-g{q+Clj>RLMr9f zwjko^-c!y_4#>-jZg+*)w?Te%{Kw|wL;K5L`7D3=z1w0b*7izAi1mgg2n^@<9B~ts>;=ED@Fr?dj~@v?;T_FA=$J*8;z+dtTqH`lfAtu5AWV3kcLRP_ZC{B z8eNih+b?u=$y2(Zl6mlkkVHx3Ln}Ko_nQYduF@Drp?5R3^J5f(N5>P+E^@l9m{uz$ zD-F#we_-`=%nKNNfT=fJ88~NI}+KT zq%sq+r zO|uc9LTOL>xj5~O0E-Gjq^-y*=D02p97j&09w1i-CxKDFq6O}Z41=IVZ_?E=W-*YMC15tYf&D$ps zPF_^0fMjEf$>AZ@XhfhQ6qd?mXGrS`64s;4L7Wn`+SoE7KP%~^f?xW~b$;=+Yn+}Q z*={Sv787BNWuaQ+Y$xTv`Ilei%FYIRdwZNc{GmN~dSA=}cWVixz@mK1rAJZy+9F)! z@7jfYW!7;sB*JRnnrVpQgs*?~i~PIa`sX}+^lAIeKmSXyy|K&}KJ^NN-U++g39G9s zoSk2=m|A{x_c1ryuG($Niag5*qlhR?=4-FD=*mg$CanfRSQF%(3RjU8n4%$k9$^IVs za7<%!2hm8;p3fzP^vTBoVRwOKWffhwEQ-2d_G}xqih^g9;_5a;*UDwR{|K|=tD!6@ zB#{z~OXuBH|K42>&w;s&^!N#?wV~3UN2BY)ft$rr3ho~a2`2^T#S|?g?mjx@sGnnm zA_)iFdwRx7H)U-}aA$vrPFvV0VQslh8Fu;UQ6JrV%*NIRt;H3doSrj{uduQC9Nl)p z+V(o1cyz@7{J;HQJbHS{ z#n}nM<{a)FG8tW9tI~#n5}$hcy4_idki&aCuFg5RkVJ8e))hsO+r_07o3@w5R4anG zX#*uivyqaOno>o?X+$CwYs<^Tar_LT@zGJMUd?uUJ1-U)FC1a*-$zkC9{=$1aRTyl zMx)g(h0HRitQ3<*ikKK3IhZhsV}dB8y|BcUYtIXpQELQ}$n_xFveGDFMW6yl7{!t< zEixKU#3UONu_YMZgFl2Xona4*X zWE8O4?s9ZCVsUekes9Rh(K%@&25Xu2`Xq4^5k&+>W3$W$ye=VA&fLRqF1|vkHE2a> z6K7Io=TdgF1O|L1Nm$_O0i?xL z8lj|D<&gvktS1|Xp`MFZ2hEF`V%4e@FaM+vBYBm^W6^F-t zioE1!`)8~#cUWIu;N5!%?4JzSJDae%(qe6~#m_!GMoCFC2{@G@7r9|DE*SLtTn$Hj z{@RKiADoE(FlB1mO!n^c?(2{2#nG4~y(PvK^v+Lt=ZzoGO@wWzuGm;?l3wibrRSEc zm}cVsG$T`rC{0{%vUII5VXKJ@Bj>k=WpTN~;hANmHaVY!3~Yo6N=#J=gdx0$SXx>n z?JQwaDX#9WVr0NzQcxUCX*L@e15#S9-MGod_6}v?Ob3O4AS_AKbS9T;jiJoOG^2kB^ zEs2uG9!Vn!HVnfsY(I@3{Lk1=2JA6B14zIKV^{->Ma&E>k|L=VB~eYX*L!dG-Iv;O zsoe9d5#fh8nN`h^+B1?LI~wSV%F4<-C(bz$zva6)3uspX^(0z)lt!ZB4sm-I6V_Zo zSc!ks;GzmHB9xMaQ}Jy*{XQX+Ioo~D%f0E9x-8sv7t zkAM8v^dEgdmdwO#Hl^3=(I3v(-#=h`bB(>tHR8bX$;bEj@V%dlC7)vjiR6@Y?Gi(Y z@`E!TKvj{$8t3*b1!mdd!p*BL7X0`}-=kd*Srmdl{lVMhi!pz8^Cpw&l%3r@)>|>7 zX~IXJ%sF@dDi=4Kgx-*Ou?%`yt!2ygTPo>-a(UJi^|TPP~1T*o#Q?k<4g)Ir=2YKi4x^0gsnP;O5zL4?C_9$HYYxJ5m|4n;8a3_nNOG> z9OBoT#GBidk>M%)&HZ?)7AS?Ryfj<^QLW~`>M&xF%YAM2x7Av2Eootqp65<)b&le6 zFI@hOwJS44V=RkIudbzBYFYzDVc1%W_~OggIGJU1hY4$~n5W%2Z{FVG;#Py_y%Ei3 z%=zsmqfGPO;}c3_xbx_USFWFDF)(aiyG#)H1VKP_?GkfujYYG;$z(w-kX*aA%fX8t zCns~fz;m!&3(`7~3uz4qgDsse5whY$8M~S*Cj$=IY({g<@~t;^?5*n;gsd)jIeNjL zzx|h-Omn0v*lQa0YMRwMZ{Ui$EC9c&$Ya^vcy?pZz#vGFhNJi9uBxfg$Z3Qzi>% zKvk8qme3MYxh@MUutpP?5x##O;RV&E1r~*rzN=iWf(7@m8|~WrQhHKKfhnB{RFW*5 z`I?2YEUKz6l%=L9^a@X`l;C%M>(}frefcd>WQ8!sB{zAIh&XIeYR!`;PsH}#B|KZA z@ZGhtX6c!?+yVdgo1{uYM5XDDbSf;B`vAVDxP5hg;} zzz=Ie=c!4P)Wo%#-0zq2kKXshom6oB$`;#eHJ%?&X*41%l1B$)I*kyG;OWtXPCa0E zv%$0OjI1=PYSeNUvlfcH#FQmo;IH)eg^+Yl=KR^=0mq}1b63tYoTSWi%ah)MI0$)q zFd_&%UJOz;+JZ~F9rDuf;Q4^V7kxH2+r0PWga^+?ynMC8EH_ByQO*ZU4#uSY2R2>b z6o+}8w}1F9|8Dq+*t~Fq)|X!9#5WZE1^0gbLtz$U-uUI;;^kPPdm|RZ7owOPVMXLB z(Mlq{$`b(xzf&qgV)*dMh^?0I+^BVl6g8w5kR>NzL%bknR+glTh-{YNDZ$anV=iuY zc;(6_AC2~j>P@sUn4&-msMl*ynVl&=1S_$oAWs)4zeZjPk~Cp5JE88ci@ZPO(FYmR zXFV1NLxi-{8y)8Jj76SPM3>0Z1h3x0t2I{&S1Txr*5uOxR+MnHa+Y!im3u{iRlh~yq zQuX+*prP(Nm2|>#pCVdU#C~+a+r`t4Hzm;MMM^QBBZGjT<>aKl_vC~h zJ((hf#grjsxl57f6wwBUqXqYV|3_pe&&j7<&?&7}YgIX425(EBpC!C!NdTuhc4G`$ zm+rk*Ry-EDs>+ty@W+4p4uASV7r(VDCS{YPsPW;$h_JDTdXSNyJf}=EL|DhJTkbqP zaUCP${mv*`1nD9tl*z30oLX9sCZ0%996tXy9(N=-iL7T zGV3YAhKE#V#5T?>!9oeVD6G`pTtYoRIwYM;sqdXfHk&IMX(>U^W-Jbm2OjSbf^ ztJV^igxFQ5X(bh0@dB6Ef2q#puDu}+70EnDc%Jj&SteYrrR=_cd0y4$YNH*4C@&F# zkL9$gE~>=*G$Uh`{2A-uS=V>!JbLhghrOKby$xE;8osaarJ&OY*y_|d8qB$Vu0s?$ zfeLFOEiGTYy2(U7FM5h(n*=G-nVyrASj`)MB6d);49WIIUhSmG_JWV3!eXtg{89wk8kmkK%%K<#M;!O+*doCXV}vR3sxH6LB}ZMCXbeXuq{)ml)7-v( z&VF>52Ts(h{APCT9 zPM)U(fkzZ6S6ESJU5h_^{30oR-SJvm$W8?f@CrypU$aot|L7sFC2P;8|T{m#ZQjd zKN|DamtJC?mE^hN>Tb)a_3Sly@BR@*skyY%q7i!3Ya##c?R$*+Cw%>l3wUvzr~4x= zY&N*K)8g@aL&91pn%g(XWuG+7h-)5~uUuvO3ztYrh$BO-9gwFj!nb~jMlB>*+ogXp zBr2e`eic>MOpfN5mIa|sWjm{g#N8i~aiTeyW>u78QNmCTPteJXTB}8Rcu1ZssI6@x zn=P!deDUTEX=(WBN6(-XC_f9&+j2 z>kRXNAAZn9N{?u5*U5=mD6^D8fvv}=^_Za5LRXzBMP=4!C2Ng2tf z<1zEu7_9`Yopm-g*D=DUzc7qPQ_95xsVtOpu3q2fi*MZG{@ptqA0DxF{xWN8P5h{a zXzlRcC&v|+N0FWM5Q`CC{Nhaz5i%5eTb3`|)1cH=(sHG>`0aIs zPz?G^Gn+;~iM>KXUUZX=<8Ne+o%`3@baVjLCjj4>{&ercwlN4Q5Gv%^NvxMGQ zq7Qy~P@#MvH#mW1H7SrOmGsUUuq|e?0 z*1F_Ed8=-g`}|WsjHL>p`#hI?EV@0C@r-!)9Ml?aE)XbBU}jU2<0DkPiMPH^GMys? zgliqQj>zSGwz?9h-&rLcPG!&?=(3qsY7iA%^HXD$hq!rM@?EU42mrl6Lci+_CX4Zi zXv3KauAsfu=gJCZhqb5O(MmAF_Z3q4D8CXw0GhRkyU&Ish33`k+X!PB%~Kw{7$Jou z3>2+K#Gn2A5qdb`qX&mH8DLK_QZ{#HtKyvPw8ZP+!|3U5xqbcYem5a=??j?=zWR-d z-)K-KbEd~#8hhucZEdg+Fdv*yYvdFf@~k9kwJEf#Qp_h)Vg;UZuEy5FdaKFJ8y&7} zH|^uQsgO3~_8VX2aW~`cQDU{RVv!YuamBVY!hmTjr;m=CUfd3V_el=vLhu<1nyFEjLbsm!7~}&>xl}^y=h!XlH4_ zLT;%t_JrpJ%<~kJV!hnR(eT7RIY^nWd6=@KJDPHScY}FSu-1qvjNxQB<3vc>&4{;d zZ15XzUSyh;)I-HQ*DR$XSyrpCctL<^P`QM;CDRx~rylUNFJ9%|lOF4>h-ck7QVM)u z5?2oFp68)N;Y!C=QI;j0wI=b_7W;#gw_aZ7*S>s_R?VkB7$Z!{G&SrG4O3l5MRjVm zm~VXJYy9SyF7my%f5Ll5ClK$jyB_n~zw+yBZFKB+e!ee`7XokYbLVl7!;=Mz%%|lE zq%aPes2oYwE-#93+-B){4%2Nl*=T|-4fXX+(%Fol*&$xvW_EIdNqTfTF|S|UWH4DU z8M`2Bu}GLK2FxZSydb90?x3|Z_;coh4jvT-J|`zfB+~(DRuI(JdG)oIN$XQy3}(E3 z>pW}C8t>mfAj@)YUfE$VoMWt^S@U`H?1({sj34-%+uLGiqse-!MlBA|Wx>g0LGL7C zXT3o^luU+Gj*gD$4@P|bYi}Tx&}r-f${cB2KGdm!yo zf_a_U*ymT?yv|hTP4o$zw^_I1gZ>fyR}gsi#sOQEZE?Nt6+NvcLFTjgh ztoc5@Ny5|af>ByYbT5^mghiA&`D{qOm{N}%FKRxYVWmR(J|;~m^Ne;qV0vJfOiS!A z<^1jjt!RUT{)GDJ-p9onqsk}S=*e7OM-l&`ag?&MPdb@I1n;9g^-bv!es*yXUBHZjvCF zFXj#|&}bsU7->NI3Q>e)Cx_T9L5XmM>8|-T+BGFYWiYy+5ek~2B#=V*N^;nnP;bQi zgV*-xo=maLCS{>{y5Fa9>pb_KpKvrz32HIYXvPP}*h14fw~Gox(te-hWQcH>5sVQS zq^ks4hch>(B+PxL(*?66r4uWJut@0(qaD`LiZiWEA>4+)B&17Gd31=%?5#3(D;?o4 z&kKCt$M=2mq5v#;p7U?N^BwC2zPNn#hJ3o;<+$6!6e-hL%KG{m*RJ10gf+Y%K<3W* zbxAfabtT7FaVwUUk0oqENrh6bp>8EkIKUdDa?a&KX9POIHy$!rClMVwJ1ueP#?`prcn>+&C5^0OO};OKlJe<=gezaZf@|S4-R?l${MfVKF=pFCOqrSF~ASsKcW#z zqR^wzg5j*>uRrM{r6kQY8VH*$9`$nuKYzhir^W{l`&`_r(OTQ)@xx=j`xke(|LlY} zE`AaGfc@T#$NNWiRtV}FyQ1&{l#O|?KcYLyNYae$t;^hh@q`Z_9& zDBoek;q+lD%PPV0QBsf$Cx{}a-f6Lz%#ePBs<%OSgd2){G9gI~KmOSRqR^{49sy5> zg8ec;Cjq|5=_F&&8Kx`=f)GCpK{zG1{y3!&bxOa*wHw#SN<&l3cm@q?_1y`?KAndHuY}M(VOen0N5qb=)W1^PyUE=V?AqV&GF~0Xh zdWE4CN(K|le0;)}-}(Zc@A2OI5137+tgkij>Pc*XJND7jeerw0`+Hovc#-_b zCcppyAOJ~3K~!h^NBnR9^q=z1U%tKaj98Y>9Tx;JPVN_5aSN(q)-sS1))`YSWt>5f zq&Z<2@=yNz|B_$*_21;qClC0`pS;7~W{cZ5ud}c}>|9&E|TrW=HH?~S7Tp%rlatRVkp3P~{el}=ZURM{SS4F0kTd4}L! zb+7ai5~U=*guH)5Hg?H}Y&4ybrvT4W73bpsuhAmf+6Dv?gNQ?vSQ=JVVjP?%ILlUw*=z$~1a znvCn1vVti}f$}6zkEfjMAJS;mSs2N`JsOZ(ixonpu&Uqot%{K4+>|O5u{B1&CFdWZ#{`48MG_NM3KhQjujTK@ee$CQB2HE~-t+REvm4P*$%StSQ|>r!~F7KsHtwlhfg!35@g7Lg?id(v5 z-t9tJ&^ot^j3VZ}0r_}Lys?3bYiP47umf(-bdUmwVwYeQd4jL%PI6Ee7C&?ar7HN~ zQ=6Bqu&1D{!50##JhCjqSXW6+lY}fyA&v=xkWy=ekc3gpdv_j)D_8Hbv%5#T5fga3 z6ot0d8sP^K$$ZA}@R-@Kj|_Jl7TJI&;VZXykrM7b8?o7rY1ae#ql7EFO)T)?qdwzV zhFW?W2nRtc^MdqbfHWyGj)>}Yg3w0@gVj0G<|rl6+E65hY>{A+f$&)nhzy?`UzSMa zGtElwJ?WDahW_G!-e8XBd5oqhX#t-c&UxHju)AL8cw9KR#%c~vyEjWEouxdo3vMi7 z;Bhoe=?)hR=dSCefQ@Fv-daef8B%D=c%JgrSI&`Z!?WWlCzFg>mJ!zi{6Ntgr?eU| zU;V-bB6j)x4<2y$@jlmXUgzsy`65Di{Ncm<{NazDiC1r3wLjYBm1y{kwRB`+VVijgLNo7fF-r?SckV9v>L| zu*M=6H0*+Q+2`S-cgYqr+G@e}%fG}&{VAW^eT=jvU;6T^%%*dM4jE5U1}7uldh-^w z(&zF1h(WiDE^}Ub{RZ_g=kN05c*w(N z2ds5E)90Mx;5((LV9+d5D@6+EOeM^6`*pZJnrI zUpW!Gb;EUxli7k|o)EVi1htq_8&s=9UBGnErM=Oi)oL<5+^4={kd2Nj9B>*JSOGfM z~2Ju8Fa#Y)irgHA1KO_qLTiVIByY&B}-j_YgwQXETK}%z(*j2 zLJEuTNiJ-}ym2vPBiOawCxO^(87?$3hEIRSo%DdsjSXy>GurKOk9^wlryRp!(&epz&^5}mW0lO@zjmli(?U5CXi%_r?@I+dq5JQ&l+1yQrXix+*G zYfWTknH~<cpdSi{Ry?on#``bNX@QLdkjF1TBg9!)&g)m@E!DO~zk_|A)1}Bq(AN{L8CK-3B z)oLiud3-hF2xAQp@?^hPT?@kp4-PO0yiP*4n1U@?mJoz3DU&&kR-2vkSJ;lGoOJgo zrEjORR0Kg#&8JiMD@sG)pD8*lyKq&}?-!Ho&ywB!n_gS~tJLS2$KQ8+o`8JDNVCjp ztA$XNxu6h)aSd%MC6%hZiuAbi@qI4tZP0EtorI*4D5)?;SDZIVX#iu0;+QNq%#++c zI2eh{Ya_!ZC2F-$i3*B@@`$$2lXVZ693Bxg8V)P04YJ4)T4MA9qZBfV@Y`*Ky+rcj z6B?n%oX{10Uaqd0LQ`h9t>(|K2{o^5!MJ z_Sz-QWg1{%w^Hl}W4+4T9Sap`PF&rHAND9dx zefK?n`2G=I6ypaG!mkTtK$)iqO7gtmaPD#8R=YBrg4mZ_*=Zo9GiN;RO?mao4)>lK z#*+oF-`wHpivi;@13x%jAo3Jd5mY~XI>Cw=Lixjh#9tla%voA>Vv;kH;_iv?9gj&6syT-lws($ITm;L0AT(1^Il6&8K|f)^)OE z%#()?$%>ed??0wf_i3%IbN9|YyeLF_0k6OL8k5PCJC6^UCpoXbw9ECI7aiOXR_E|e zk<#xLWRo${80xJiv+=}9RX022Qhp&C<3uqDWUN0bxW5&~j5AVI8(~NoP#yQ5*l%K!T*QH3 zG3nENa*up5W#{rujwk;DzZmlL=~Lc&_g%D=lto@atf~Omx^Fktg6KNI4&z~r3vPup zt2vSaTtCp_`-0hY!vFry{(w7o?^4Q|_|qT1$83>s`O-O(5{!z80w+`6OFYWv^(ql! z)zw%Qf818(0%_%W6&kKm{aGd#Sn@>*)+K3g#p2dyJDV^)*e7VN5o~Rpc1aNx z4EQwAwDvSGl|ohlag`)UiIuFnV#~n2N-Z#zH_NgLzUqqOiaUN3x`f13{J|BZPps~^ zvq7)xhFFTFoHSLEvrP7+^Ih>gh37lCo9}!0)tm)^M-T+Gnhj>-F^i)EcdXU-O6!tV zjUlWgkjv7+pd|t$1clL6b4`G8q8I2KQ=~k3He>Ppuf_c2h>N%0q_e(>HhOiALI`TL z8f9M4|L6|=?uc_&Um`Cpy^}dLB?;oX6Dp8P@d1~_=eduP3SB9?IazIsEeeb-KUEl* zk9yV?bK#d8R%J7h%*V`U3z6p~S)NnmIjS;%R%cYijL}ZiXC=9(J{9Br$HKAB-b1d# zBF?0?pO638@p%IB86%sfqSS>5ltg$T)(f!0pgf6Epp=iNJfb+{&i$u+^2sOm!iDo9 z3<83oSQ27LDiKc=y@%WwSpFZ1P> zzR3pX;o*CVRF`;uSS?HjqjR_6N#UHB<#M4nRtQ8<6i&+6 zRF2X{J7pg~Ao6{bQp{#Er#fO4MX5)J=*n<$NNKG9E~uycL*g67a4=WgrjE%q~nPbB3RqP^FkLmd4gzjld>q0jSfM> z(rFoPT!|U<5M7PmrNscuTM2;)7Twcqfbn=#71^+|hE2pCM;NC-o7qWeE7px$>J5AK@;ULp{J|rB{NYpD zvf%5tx9t4`As#(DBxvt)wOQxI@tA|b9N+gUsIs7xiZGBET@bgLWb+9@6d>CjwDkxY zbpmVgmFHj)*6>$%yKaX!&Wui&oZtG|71sQcr}yr1Z6jcNy}|ds|2^Kj^9i=h_)wR; z_Qo50^Ot`WFNi3zjDt~^*<{MzdPH0LY&I1)wga{Zshb6@SkjIxrAYDCTMVDg*xB&; z`l}bv+LBEAd~i6Vz6-Zsd5P<{QkLAP(`v0I90L z!GJ+iT9EZN;f7({KcchNqS-NIZvkB=Q*)Q|75g;7nGRib}4KZm<})mbfR}Nf@u_uFEdXGWc}~iVBf$DhI_YXX<>X>G}-Gjy6#-`>PZ1>)2L!{P$x zvM4a6#)|@^P<+aOk5lN9k-{Z%ORh!5p*dsYQbCv9-v;#v75ENzCoF0Am~=d$wtEiQ zY+*``72qie$&A^-0e-VXw7r87RHVYCvY0`q`6@wBRg$qxcwLTnDqtY&>0Y)BIG2f( zQi39P;xkIB)BUbmhtJ-`jx$rumNk@VzDlT;zZU{mtXp0;4?;293wF!JPLW z@3R&xIDb=6Xmf@K`zyRlIgA;dR&)L_f#+4?2&Y{}m-L*<>Yx4h?=nui zclQ7Dy`PW2eSDsPe8yN?Z`xLUW_-`17RQLN0mT%7Q-rY%b&_PCQ<|=(6$G`i8W}_x1MU3C7fghZ%-NN;Hm+CB5YsVMZ+`_YK$oZJ` zq;w0Q7Z7i55eXP~`%amwf)SjIW_W3z|MB;}iWLDrf9IzhK7Y>5O`rezH(%r1Z@^ zxiq(PN9&IJ%pxVMbrl`!)S-OeLt6pTqt$AQ*>q$_<$4&p*&GRMRbksVq!DbyoFXt<7Uf@qY zJm$$^fhe7c+jyjrICz76iQiu*Y6&j1X{?$7I%b@~1)|RDh>^vV4y4 zB4pSCtI#?}1u0f}!blIR>KGZ37M7jeCf6=+bN^|d{pVeN<*T6SknFhfgiXcKoFA8=U6Fd?(8t_^__1~UZA`HTNdQ$oFJ@W z)0E`+koxW(ajiw6PpQgF&ebxgQ=Z3?A0n0znCfS(4YJuGl!9URi1vD$X1l?pcSIeH zYIZQD@{9-^DHTg4dy9j_XlL+f4ftVzs(2PsO5%F#Na#|2N;cLQjnyTdA2?F03XruB zsX_|r(P+k$#uDvbqoLQybcr8r;pv>UD{Z{SI_aoKkuE5VL?{nW2-3wAgCtEBWNC)6 z)jcddf>2Rp3$zC11r<5o`M_A?q;Jh(B%Ct*?2~6=K@}{BAiR%*0=eT`Qaf!t3$lKLn-7c%w4MH z8SCJF%2W8YaMhKNm8<(oT~90_IhC|=mDp9c<|^6qd|9Db?P?x=QLfc!<9tS}!%+!i zp~z8jh^{8-EPrH`=v3e5kPt3`kyRhYTG!1H)+{#!SJU?bgzsa^WEB(}?YiAkE)~0+ zbnYqFM^aWO11HK>CBOoloNz&rqd0F1fq==ma=s2gT9hhN`iHVJ}|yo5pve68JkMOocncJ(Y7ZOC;F!Wn{UW5|s{%ZM;;xOo!Fd99Wufi&XW zR)T2 z?I}@uW21vkJ^tnY{e4D*KK*&Yr7wPi{Y3IV|MUOL_D3_ZbNyBR`tg9HQBFH9c=+gu zOBc47Pi8!MF`$$oSz)N3JC6)PX2*S(d~9ta8x2ZhDYKk1&G4cSFLW;FpQ=lZiyz^7$vnjJg^H=Zu93uqvI7Z;$57q{l zQX`dDNm07*3Br(~(tD5N7?bDRyuQWDufF2i)xHZDP@#i(V3=f`C-uN}!JD7%SSv3yzW+gRH~7@Be_0 ze(;BOPK)B&eJ|dfQ zyEfv>*BYQREKqMY@B&3Xjd}DU=jXElB3`eI<{;}mXDxZcmo9}|To(+}f}bDE>CU#1 z^$pMlt4rcgu+yoD!%@P<=7zm;VHaOPv)v&K1Je1FX1zv#aDvWLLS-2b$Cy0lrTQAp zPRNfx{zN>R3%+rq&Bo>iA9oKaOYl%kCsWpAO_pX=HC0h+&7y<{M+=?~o#AA-u|sWb zjiX+dr-#o8qL9{JhjgBD_hAnsptgG+>HChPDXXfdR79cAT;n^vfWb3( z`(^MXaEesRVAWLDRvUxYSR+O-=^fE(H|TVlOnO~ngiAu~DREk`gh{&Z&_7e z9v|&5i2Q8|TOf>wXl-Ft0E-D33a{3plqsUF@S{4Ws`6WFuxW-wpu))cy9hU@SXWD) zL@~2OA;W;Ym?5P{5Jl*$pv+7Bit8Z&6-7k5=Mh0b6_K8D8>H*SJ6Kg*O`5IdqI&Og zE(4zxG>$4kG)p*L6;xa6l;oB{`YL8S{j9SuFOwN1EP202I+_vh?BTUruIocZN?y#E z9vmQR4T7z0ie=Y;Q|Qz3Gs9NH?Vr}VfV8UWtPbVO`$ffLIyGLbK36zl6rtowm1}vg zF7J`$YfJL^5{hi3BIvYSvY}7k=iVY#hJ8$9M*JVV1`(B*GRjIL6Zp&ec*IGZW+91X(7eg{9P$ z9J#O+luP3K9$^%M7Z9#(vwq`isPSWh(3!Ym3(_F zG+JvUN$Q}~K}ZzUU4m%-|8OxEE5pXm$KP#yo`8JDC>8})3h}}H1A60}#47s!dD6Uv zwFPCez-AUNZlJ=L0!7fapgcT3LP&|u3yRqczuiVfF-!dHs_kf{TeO#Le&B3d?-Y^X zTBc=QV5KDNY&iK?W_Z4btcYZ8y%dy2v$xS?XY(At|9^gmA}`pw{wiKn=g;1`!^iLb zO#Iq^@)h3NYV+>HAz!<_&DvUnkN3wENyb}mzQo4v7Pl{S$Yj93`Nqc0N0F-58Q zgTK1NUw+&pO;Unn|Nmw0&0-`=vNOHU%WR%T_bnYDCP_1|S@zZlXDC=uKrPRAxqmd)#Z+-0YnHKj;6chYm@aB84D|A{#&pt2|<`2U1xtYtSg= z;3yZzQ+(y~ukgmFt}q((kmM+(@GEtE-)DWL!zh((Z6C1LKPC-Z2m=5BAOJ~3K~$MW zL~e{2^hz6IgHT#z(kBi#kZxG4fdx5CrEu$YOK(ey z_F2$MARR?e4`=JEJP@T6_!XaGX;_~bVHvi)-js*iN90+~B!%7X7^xKZ_lHcAjF0ae zad&S_stvV4%$Ht1MXqyh@ANTJa({QgAAb8LHQ$<3?haFQmXPa|T!u^&O)nY|$tGKe zQx4KpRN6jm>4K1?IHV>-x{4^(WXTA!Daxq`*VpKAZW+fMGA)pK#H&v!{-a;JL=;En zJKy|{nGEjng)eUE%YX7)&y)A==zDjs^VQd16TkAs zi{gL$<7?a=J4};|Xfh#a1h}4y6Vyx;O+_^B(K|k%f3%CE1VLEGJavJk)pe9ol5!T_R} z>HaR2HG>m0$jn^owJby_HxDbUAm=7=3yWFjIjY_y6foG|rqOQE?6l|~>=7c6b^G4M zmI2sCVIi%mnH%_kp80Lqw-)mfopJ-imggwf$Lp*hT({^0ERvZ5_}J;i_A{t#bGU{5 zL3uuDDw!BVnkmQ~Tmn!IIW9RK!mW_YihZr;&66?>%BvT0vDgHpM7NDimb8*+X^knJ z&=8HM2-kxoE!Yf+D7x<*&qD zXZ?LFh%e97#Y*p&@&X(*>CpjEZ-~FXiPLDz0!AeTGMX^l*+Et71gmT01)HIi1Ys4^ zG`9D|K4)jv2eNp|mS@IH-OH2}Pm7GsVo6r1UQhspC7Ql~gwM)ziZ7K)W?5b`FZ0x= zOa{vGvw|Zi6yWCwdm*Md>u0kP&59(`47&ryqX{Cc5v*;JB4$Ccm874mZ{_(MgevoJ z`>YIDV#%&u451(LNxt?%eLNvT>4FRv7h<2^}GpI}KbvU~9L}D0A5K z+f)MI{NC^VJ+ba596i3nnavfVXliahJ{Ipjip-rm_r-7ioi{jl_5{~IdY_e6)m*)C zTgdu4$|=|%<4~(Lska(T##6F*#Fb~ya;kBX_nkglkGAMdbMidrriE&$G441+88hI+Z(}=PCx1nE&mMzs*v`kfaf%guKxO+?b~fh6C;$B$(Dk zGWPJ|LySqtGELz7;5g(-g4UWSj;!-`o}rX8Ly?RD&v*ICSH8mQuU-aY$c->@l0iNa zq3`KvoXEXo$j0fX%-V8G+}?T2(O^O}91-=#gi^D0?-AQ~uCY>g7~Q(V;o&~ZPn{+> z^E3~4yNKi&PM>Hsy@%3UE%w8uHtzW{Mrg8 zSjNvQtT(EB{)=DW^=D7;U~j`Z~q1-)|dIw&3$ff4+vA2saz$NK9gvS zG8!dHqqZEAPH-H|*Z%aI=AZoYKN8a@X6JBd{^S4fw}qp$jn<4N&o%yJkKh00i}?E3 z{CEHK55(i`L*Bdki2v%p{4dOJetJ#(4}Wn$KdNF3B*x*LYmd47)Cu93nBC)uufKT% zon;7<^NYXyi&PqIQwuzP{K0i`JgKn0xyGeNg?l$7dkUU^ZH3Le%Kh7Sh_jeePoF@N zGtCWNy+hm6oPYKLX_7L2aLB>b20&K+RilwOT9XWi*7U0gtddDYo@59q$?}Y6*Xx|U zaFX}0KHx}ay!zVnwp=C7IseQF93=>ylyMx3YOP9Ry#wyc9PjTzyTL2ZZSwA|LvG$b zq*ifx_31S#s!o=s+`qTY-Fv${cVUChQjJ_F8cWNB)f%VUKKoL$e4)dcl@QV<)lQ4i zQIF6Mm`tZQo=-f9&=^|F9lHC+IMTtGj4VwE0w0}N+1SLucyEu&s<7yPUaa9_No(3O zxo6JHQA(ead70Gw44O%$Qv}Nh7CUi;ussu{R#tg#mG%Fn(8^4BVDWsD5=TOOaLDAi zN3gbmQ?C_017;?*JKWyJsWxWGM`>(ZN)zk6Y&tHaa0Lh>XUD5GmlU%SGrKOHWMu5k zmOo$2n|iVwZ+_2Z1AaNVGwPuL3lsF_alIy z8j{5=9_@5-e4n7RM2sZM^lVbgGrE*fwyd8utF^WtMPgVoI@s#zOlzF5PP+UQr#BjG zt~UA6yVqef;PMw<;$RT-_D6R)cXo{zpFYX^w+@Nu;wwd$8asPaUOBVEOQ%9Uoa~yK zn~JLAi1gG32h|D>x|({c#V>vKWh!FI&h}$Eoi;bO4j86G5LWm>IUdu|m{ISLJf860 z2iLjdCg#q2*BKAHA{QQMnsQ^a!&19Vt=VF$n{qTZ^!h_I*1P1Wdqg}PkwimuZa9D8 zIZmH>YVM5wbBt0^ONzhwXFnN#{rDsS`5B{D4~!cmIa6&BXU9bdWjA}r!}BVDMIvlT ziiE<2y4>hg;30!5vS{+AKp6A_4pfdOWC_bRSV&4V7PZ#KkWMF7);Eip?ClntpDN6c zY*w#@WT{!<@}@_>>u~MOuaS2j^4aIVz)LTlGsdlmcefL~ksxp#s*dIeXmy&5Mibht zD(~Gr=G1D9r%x}jb2P!N)~unTy-15zd9Fp&ezIA!KoQYa<;IZ$w^HLDN&r@N>MZ+idleTeN(^`;*nMzOxd!K;y|10@tYY?CWI=hpNlx7L@Pz{cQ8ia zIJU_&*P7?gEb-!*Hg|UWY%bO5jZ?n)&I59z`S8{*je5Yj%?>vo9x|QAyuW?Ka;wV4 z&1D{Lckz_q9iVLxpbOuedjH<-n>J-7EnL;Di>dt+_-g@mtTI7;KW(}Df)%4UhVjQ=~7PWMjR}dspvq zdTEX2jeu|c_=hNyvb?m+g$qxyr$Z8xvzJ#HjwSK_kmI8v(O|?{bp_Mgs!_!WK@gDVIj-+PWSH#l5w1y8Shr|!8NDy;hh;D| z3!*8Qkz%V%GL2hlQdx(=-VTj+gGRf-aQ}c%gQ~a4O(Do?ieOa~C^!Z!it;Y(o+X$E zaAl%nOTbF>zYuvaws%4KYL@n!#qd&K%YKSI9%)q-QH8pek_hQygllDxr8nzcu~}02 z8MmMWs<>rYvggGSVdhQEh@uxyNi>qYI6KN_e^GF!qC|jafpSqARGvj;>Dmk-w(q^j z7?h@Zb6#W4j+Ez_E>jU>3P#uNM>aVt0=c5+BRV={((B`|uHiHqGe>YG1Y$a3ymx>I zYWSTiB?~a+NlY@G5;U8*&1RuEW*gPZ zGa>XON?G5gQvSEROr7hQ6mt0uDTI}j&r*c2>mS#nUawNA2Bc06T??2R2iF& zSE-OIhs+76*L+@lYL)AE_k`y-Y_6@KU%ZUciSaz2OSQI$KiU`Xy!|n8s&O2LFMQ?= z#*-;q2Yvq6KlpR*U3-l5>Ie+uK_8|#v=uoIptlxX69QXo}^(}L{5I{8kjev7ie5O znc^skkP0QO(Vs9mlAPR_;!t$>@Y+3YO?K$i1F{^zWq<#e@4fk!*zZngKlL&uQQW%y zkejy!&31!lPPJ$?D(oH%Sg$EuquJ@jsIY1eGO)FOTw#(iA{mjV327XYM-xn*q0^Y*_<+abnDI2n2|FAg zb-8=vBOdOJ2{xa_sXG{<(5N}9H47dfO*Q8>8hrlBDTLMx#xaM(h#!BrMUoq&BMSto zOh#;?U=YMvp^_s7jw^};*B}a=#D<`>qbj+>Y1JP(UIkU3L zJ3sDmt1HCBv}tafu#%{8ipe!PH&!LZb5X86V6-+U&&Tm9Lb)2r#JZyk$g%bF)mjAs zL`g#6`_$?!(lkd4hoBnLX@pGs$2`1yoA$~&#x>me_yZo_{*biaoT51$YjcWW5|Su$ugqxgfTHMKYNZ#rYAZ@BWoo?mW+L{Kju{^X?Wq{fNDTE|KsVO(H_yW2vF>6-=TOud_rd!Sw{^PPBRF z?dwPZ>39r6&{|!lyMKs~4q28lohEp`L!M^%p$}2aWOs+kn!&BqNb<#qb^+8VMv3aW z%DPjVBC^VKj#Fz88tCus(rVXiWBTDfAqLfG+kO+ltOmZUhnG))JvMN(dvuAWo8mt) z_pF#*Udcih8~hAWHuGd*7WfufLje$2mAf)XEhXRWuUk~*G6mBxH~E|YKFcZ?jF1aS zh@>o!JR{8!0 z=90a|PfC-M9PKkX?%}O$;53?c{))g@Bojv4yWj?d>l+ByMd*U@EYH%?*F~5oo( z)_GZK=`SL%27JY}nt6g!vTdbdV0kyXWICA7!94L~#&igZghehUa0`=Cs(z_reH%S9 z+>|8~BJA3k?f1eaNTb6(vNt4XH1Jo}Z1Q2|NrvYMT%96vLnR0qOw#$@BE*96A}q>L zXOj`p;UPjm&}<^4OPXe^w<}z^bb?zCyM$qY>*icKzs?J1mx!{Q41wcFk|<&{7!k;n zs%LoW%qH!2QzX%pYUm+^B=~p-&w*w&V7c8Q@Esh-5gXkhU;FmEe0ci+<@wgsIZsi_ z1J{rx#=P^vHL-K=n)v9w582y!Os&1dsnZwfk0QSLS6^cirv$AH+w-4kvOKrmK}w0G zR+Wv76NH|iKNy)j*WwA#_is67f)qd3t3Mg=NdodS$0VH)XPGd<1)(rPA*8k`$pQ+Z z3xvg(V$Vl_bnM1f)>Y2TF2ob8#{2{Wlh3Ks+0R&xxXe627m8Tbign1P+*AxQ&u6Fw zVI4QD&{#de-j1Xnr^Jm*D6z@Iq(i;ZM6Ol|S5I-g^MIQ-A0d^4Tj|nXTOp_f>}~BK z;)vSHG6NYP95plhFNR-kp%D zDlfH{Nwk$YbgEUHFtm+=a_+TZ3d6+R!vTByJ?d4DR;zC7Fw9%%Sz`K#ZyH9)Icl0l4@0iY~rSqn0z`Sa1Q?X`=nEHxQSGd{Yr!>JQ>UVrfdAKu#|&2wAlZfrnz?(9kN`~TqA_$UAD zUof6T{Qckkce(J?21jq-o+Fm7OLtP^@lnk0{^nPCw0+1&*Y5GFf9Fel>g8wo<8NGL zAQ~uFk>#4l2P0m*uwhQN9nx&dz5WByu4pRKCmHUu7A9P*_05H6o8p7JDYx!FCKE2P zPMJ(obebc58_cHCM=HfQlL(`E?S&I~YC^@`FqJSAt```u)<)Et;>42R;|D`rU(HZq zra0poPSus>$d8?b(2-3ALZtgKeq z8ze+&%J}FAnM`f6Q>zm+YRIrkt|OKz%A9C>VoRnbi^fzv!FtQ%paQX|vp-1r@q;dL zlHsH=K{nxLt;T-pkO~J`YhfyuAr31c!^0kxFd!X|m}pIVxkK;p2+ws%vz#PJaU4k& zr?w9xPOM}4$|_E^L7JC)qh3g$7tntLS*~YnYYD?=xkgoLgllUI4)$m?s!IlUqg6;B(i{zw~85Kn`GD|>25o8Kc_yjFn@Ivss@TFN$rDwr( z@o!^h-!H!|7m^Dwvm`*5^ZJu)ep$k`5R^+{NRAF{+12VgZlhVqy$X~g5b>1J)?yk>&F*-nY0@ z$^y2<-XVk)HxT97E#}WlGxuV$Po)SPD7kCq{Wj&9SZLFfzAR|N###sEIPC8qgCC&7 z24DpXgs|p@PQ}M{B!ehN=LY32lp7WEQc5}7xyXo)k7)XmG|QMA9#Y#_W4Alz?pBv} z)uB>xc(^yjU^wiKxf^&K4W=CQr?`%SG$l(Cf-qn>O=wkI8exOMz}{_~WOf#e#xW7? z(4ZWHl$xoNqR5SLLQ!qDnT|&!iNLQl&_XeZry>bLHZN}AxE>$B_d}%XvwrdnlTn}d zZrvtJ6P~-WIRmDol=z-cnj{?V?=tLn8BZqoL0!16%g>vDe8PPEe=|NwKz_#1Q7&|r zNh4j0ffYfoty7gnW0|Fp%fQ>_7{a>bI*u*9g1Pf6#m0ho;_&*Z)x1#aJV&Hvp*mjZ zlO-u}8j(gRd76^y9FC7rOKZ?v;>Y*<)I*=d-ylv>vXfP0t~sbS896=@!NVI}4kHI| z^PEMRJcp5y9BdsC^~VIQ7P$z}qHItUB>fTTctX%_;#PtgwXTzt%oNRxWm08tf-)H~ z225VgL2-+-qg0?#2vKg{Ae6Aoh7criA**MYHQieoT|3e^vZYEw;CUWFSmVd#BioY_ z)GBzPDxxEa$uqL!14J|-7KWx?W9{q;{b5A2>M|T#^swqH>Yl`PC7vVE!eJEW1WAq& zDMEtdx;)w+vf2*$)z6(n3B%T2kAs6AAK!e)iIuv!d4E@gfy+kI=h_EXxwyK@{-Xzs z5{-76eCvnr6OD$fwU+qC*T2Eisf)aOW1qE}!`|*b-_cO1H>dgYD^8x>X+YtZo-}`kA4ti{EuJPyJy(<3f zW6iX>h7^WDl;Am#1 zE9{MP-nq5UdZ)_S<_WIf*uqtUILlaBsc`zl5`HXs@9q0y_vo1J(Nvsy@$)2pgTH+9 z8r^Be>5Jz$ablH`_Rw0B#|hDRf>#MSSq+IYxb^Ue;V8vm2z(FU3rOMw7^dNQ*tyn7?i>WY&vT&;bQA0a{9&dJ_=z z_P1%a8nl*dV|opPTW^u&MS0D_-m8n_vsa{#Sv`~s9W`NQ>e4MiqV&=APnQu8` zX_SOqn8I+-mKJG8k_&+p3MB-&n3Ks!S+Lrsq!WJnuqu)A;+nNK#Wk1LWPzemE`7$R z^CVF)FRd!?UCdu+=DYdgpC#E_f^o$rWcQod4_cYuGO3u&Vqr3v932sL2LvnYg?zG| zPe(~qGG(y+7#xr4<|bOHnF(;&^QTR2S@|-c6d+B>?3BqtQ4(9q4KE}_w&c#tleuC} ztyHg>84EtKHjJ5x&o8uI1<)YYQ$;A(IB#YK?b^`#0o%YGjr{pD|Ia_o#Hxls!=BA^yy88 zF3MKarrrg~f&l(0z0TMU876DK*! z@wpmp@ZbL5k9dA1rCoK{eg7eMCp9LGi=aGoIw8w6UPYml!`LV>jbq|yg6l}a&?R-1 z(Hh}+t`I`tDuE*fQl|(UJm0mfS5cl}gAp4vN~!qpUY9%D4#Oy893hl+sdOW1TYEfv zw!>FnJ;D9GA%Uw{ZHMgjVyc1lFuC!t%j?gq)7{^pyL*gsVm^5HJ;wb$?Fy`Jo@94t zo3rPirnS^2PZK`6xr66AR9(S|)duG_TfBH-o&B9d-hb~VF_QLji(mQlITRVG@>#v~ zDw8Ni)-zUHhg4)rUT?6rQ76G+_ugIVQA!#|c#ey%N`#2Xr$e4OdkUS@dHbE){CSp= zssPP^N*FSlj1dkb!x08UrBxpO6Nj5cGDpX|-##I&J#<`&0m@)*&+%m7bvmMc^pK{P#Se&{V9$ zMK-2PdJtmXlcLM4$qG2k#7;}boT98(O0>j^N(ie8m5F)ZmOUC4n3SJn6N+*gA?66Z zlweYgFqUQ3T4SWLKew2~F$cxU_nY}S74x`QT3iOxv!rkSF0(nYw{D7gViw4oS%_XF z4BDWi6;esNM?^=*1S@Me&1TU9WLa#LOc*|Xj8Q(-jT2}o(Rpsq(S>uM{5`YMG8UJI zm}N^w6wlcdWoxFKH|DQ1v&*!JM)7Wo^I?0G%fVn1zLKB>5AHr93_NP>HgCLimUg3p z);T+agb(f>lW2`Dn4hx8Wv0w!$|z)Bc_6ewc`n)yd3bM!L<>ZvLFR^*sZ&;QQW>lX zW5LKRG*ls^CeGo_>j#!W(uVi`>@I<{rJA36@dSeuZg=6zOV3jkF>h||a=G538hU)= z_8v!K1KA!i8TG+$-~@*5ppP@?BOHfoAMWu#{m<9wZ(Zm1-TO>(kM`7%YeCptp?&fh z+9x)6eR++SF29KHDw?$_uImXUB}=UaZsBjU*vB#ZoHH-aTO5C#Ur53Ck`DU2`5B{D4@?kbITITY3n9t1AdfQ+_KxwYHH2^|dDs#y1CXAw8` zre)%>u%N|!a|ULKNgk(6`vd%X9Z?C$3xp*#0%HoQJB#_;8=qonxx<}%J5>FYL4OZ7 zj%SpE1;`Xg2iH~9>ve_^tgfyi*DCy9U%QLW(&9jsgzYv?y->R{8D$e40xI+m zP`MJ|`hJm!slvI~A|oaTp+RD(1`f@-kDO+t(<#Y#M9^&Dg}yx;j6t9f+Mu;d;+(~V z5;J-X+RA)7YTkeis!$Lqsda-WBsNvGg9$W6xPR}E)9WpAopGvD8amS`ogDq z=_n@Zb_tqICSicdbMk2lj$xERW3|d^r^*jM+Gej8vC{Hcse4>HQDZc*XWGl>+sI_X z!|ONE(U9eu!1V5u^?HcO5;Cr{zc--KY;f_?CEmX`;r{-FQ)>;DTQ#&lS`SXZm zO8@A{BwC2o8$i-&;o3TWn1wVWkQk7}-9V7k9YXbeuZO;*fp>1;l8x-Rxg+cd2$KwJb6rGk^F)^V2CIoREz z-Dwgun~V=^V|rd`&H99(s7xtTtCXXx&_xl{X1SS(MwO`Ytl7F`3Kq6|D;ObW0k9BO zAOs9Xx(Jb%2Zv?QOR%Q6?s>0=`RPQU_+Poth_Xz#U=9=M+wkf@;8he zFv_*Tet~E>fls4WM;k#FXR|{9tWt_aG0KhD%>E5x)}!zQ`vE+Wd_d8aEf7lLh9L$) z;3?{1gTo}E7IS=Ssc$$(%G0&ZCThE6qCyNuR)c_&wVQ(-vLZFl&%`(zVi?e|e+oLZ?f==Hh1J0t^}pb3Z6 zanM-=#s;sG!H^TnRX+3lCO^8i&2p#4tCv=JwANil zw?cZO6t7mZ44@DUhA~N!@a!`iND1qm8sGci5m%mC!j*Hx* zLPpi#8HYSr;@pX4n)M1-ukR3~IgaB}-+YD-k3x{G0OMwTo;o_vfL15l4>>N#fxhk zk0QSN&TT&X(pfH@TIQqMyNr^AQ=7}Ye(@4bH{rqi-(>&c9%vNM_R z@ts{-jXGa>^)$=v3LC9}gWj0y4-T15#&}^B*<8W%a}wcj(4TTyC%SNO;8f1RCX*@C!I-cT z;u@G79^fNUl_nX?SXg7kEGQ_0gjq0Nd=6ESh&WR4)U&4vFRYMH$7D{x-8+x)M8>(3 zb)@GarDDG~VH&5LT&l5sJZ8TiQx6r6QXCH=It?EIthPf!&*ARwkijHHEd=tjAebTn z!ps}eMF~oX8OpDblu(K`!m^rWz+0f`i;RS28^AoV_fR1E7Jbk{Kw+pT3PVNP15&0e zWjSndJ&UXgptIZt@k%bp)fU0m%r$(TlFa@r0{vNEM)|#22^7Ual%ukgY&<0D4hcHT zxUD8xp)e&CsAR%u=P_D&RMt;eAgH*OS&zp;BJjjoDEMlGv@~#Wt*V@VT_zoN$c54} zlj~VBqs!O+MDQt!=T}~X4M+=yPRy^TWJAkx>+v)pPBKE@!5FJTsLZ?s(8dWlQfHiA zso}YbJBLF~uGV?#>?(KfJ!axLgv%>5PMu`1z0J;}T@KDHb8f9plo_@U`XpJ(%*|bt zq9(;X&wRPW6LU~3MzrG*EU(zl7Y0+PWhnu^$jQbNyr52!Ec8HWLnTz`EN5y!IkH$& z1|@(jC9Ek1<0-obeV#qPMx6NUcE{X&cu3V#+}}B-+Z}?=EhDI0JAWoehBaKrC!bDu z|LeQ|;vfGvBR(1b*5i`| zsf8(OdYCBKm>CrtU$Lca#KJrKUsUYK&dZ&&w6Vp zDxTsOu56%m$_>x(%+nhf0pIKG^5xggb8>Tuv&$i$xwyi6Z-1YE`0KBeMSYUtE{-aW zH@8k}?V>o?+oh51@}e^(4A0S+hpbBN#fk1h>nCuhZ9sG0Oq-CXwhoz-MX-p-{(gso1+zQBZ#s|Cj zj-rU*@pKBtw+2g3sOJ>TqsF3zs#eFT)ydMFMzg{z=bO}ghmUVQqPh}t>!Bc2 zaCx)J`}ev$KAy1L3ON{#dAQSK?`X)2l`3(eGO~9(kC zO){N|G<29`9#nD)!QiZD}SrkDu0T~FS2Wd>M4Y#&>v|3f3J?|o= zl@)b8m)j3hwvGqrxW)cpiXdmH?&2!J)w>70aB-b$cXm0mQs=d2R=IW~p&RjmtQI>P(<0IPbHLNj@PeBNpttORD9kWygvtm_zq(J9&vh_AXN(RS09^Sgg`Heci@X`j8 zX~fBv!+~@;cX9>ky2P2SrN3}`jcf1i^Ud$P#mSDsZLG8Y^eXocB98j+vfG{T%%^{m zowUMmnzB?67>{FaPZGN0j5|9Mc6tdHPAkryY?5V~<%Ul^^f>MvvbS}I5K)<7hJBR1KQz zC%JzZQuX2X&3jB!!^u-?)EX7WiADq!NK$h8fWf#Pm9-Xw?H!^h!t(E>AC8XT}ah&kN(*``vK8OeE2Nr}qZ-^Of4Gze)Bd4|bs z2^QL*GXq{3d@~nCDHDc;Alp$A-&3TyCY^aom|3<_rWa4}9%jxUl>c7rGm+TeqcFtB z$E2eX+JN6#!l~CubDQ+I3S=BJ+TFz{pUS%J`7lOXqusJTs$gjhK)JUUEQBl-$BOSu zQ8G5=W<5V+O>tc%g*|T$w@HOqU?+qqRU6GL83OAmQqKLnm7LkRA&WpfPBOAQry9CM zNyc!T6la4*7j=9NwohbtugjOOtefXfoE1_^-o3sxdr}4 zQBKu&P_D6MWyZd5nrTK_5KMDE)v2&l^GVW-PhD7J>u|(0(QK|X&_*I1g-kWt6s(OD zwy|BoC`~a!5RHd~BxYl|B`RUSU^KzxDfK|%2#BVUU7NE8ER8n#ECGY^IZE<8DTE9Z z)+K%}iDMPhtWhaO+g?*)U7}bi4 zr!rI4OwLLJHDpV-AS02ohNk-J(`HFQZy!f$bvgy|5?DzHTt&MssengRdlC z|KS~4zTspiz;hk$pIoKUY7~c@rrSNlSDI&@eu_NloBmE}{X#@$>g`SHt7pV*m2ub^jlv*xz-6fa2;x)O$ z^Uf_kdT_vM$7LAjv-`~#%)sh_!%C-0e;D)BsSXlDn&s500pEH5F*>oEg*`MpWTS&? z47m~o6EQcF(xN~xjIkQ}vQU6Awq(E&CG9L`*9f3|AFon{ECH!duEJzFvPh`P5(^+=h4BK$vCF@+!`-EcZ#qY z^62U=hl7MiM=_N~9W4ZtB{(yQdA#fz2uLyjXt^GqbmTUaV zmo71#W@I{HbE(eb{UK?V^V;(#>5XEP>(Q!Lc&N+8{ zL*~mlvodS!uAZs~bT`ldh=Bk|QKTu$BxTxO*df{0LRN$$9H9tryi$1Y@WK&_aM)o= zwrolqEKZ_G0u%-kjRv}bZuC%HU0rj|!<*lo&pBS4dtVk9Vc68V@1mkAGwbEM_uYHW z_kI6~Bp*_yIUhXeGpnGSPMDpX5_P-CRuAF%d~kG3G905T%iDMRl>I}tHkY}vxWt`< z5ylUA`Q@v$;}B0uzVWShI6XXLu@ms+*Dj%T#r~rMbdlow4uLaTBil9f+d{MMg+Osf_1b6@xp*PnZi z-}&7?;NJaRp1iWn&%}!3(*sVRmBRtmc!;euVcz4TkM6N|`wr_ppXuIhhBrSzoo({;;+Jfd zmfV}>;)TU!mI6tr1YKqL%oB?|xzV9ab1r;lho^TIdGqETd#6(l&Snh8S?w|>>h*rU zxVs|iF`XgIGM)zF2BXs2~b!(~qjT*7h+GeJ!pQe`PBZjV8m^;j-uL ziLBRVg&{pYrb<#;OG}6#M0>uYT?v8jdB|eQ;IE_fX4*qLe!cL z=7oQQhGcoc`eMY^V#vWLC(DZ(B{2;yg^=I}9`D{g0bTI?6Pw&W8gu7xLb$YyREp{G zA=ViD-U_YNRhOkR8xTlKl@?5oPu%*he1dKd8-#Pwe&g;{Uk0~d)_deU*Tptk9(Pa6 zI#OVinmGk=ekJM~AhqU96JNpyD zIG|`Wi&kQcC5{y9OD(FRAeqeY1D{)aL;mM~`E~OCL-vmbjK)K{?U?=jN1UAOQuu!V;%)A==;8!A`j!GfvMa%3t{JcV5>{ERy(}%>_w1nD%J8Ny3CkNoi(2| z&{m2N?3W_7wOS?NW*cH<(4(+fl8DNQ95&3XHF&MD8v<(-h76-!4e@o}DEOhnLX;RV5*VkV@Z zEK8D;KGO4Ott_GD8>zczJtgUMB3f~X6%a>maqV?Np1Qb1l9%+_A$h4WmEr2<0^fc6 z9@j3d^2BzJBrUmdb%iS%UGDFlQkE5qYZo}ZH{dVd`jA_X`Yc?139AB(3g|=vU6vG; zvy?2X&-TtL8;c?O_8BwLWj5{egZJ*ScQO@~Y~xv2?L~a;)his2QesciYX|HdPdFZB zbh;4__J&jjetfsj!60Ljp0cvk=HcO(>pMM+r})l~9&j{DkxHS{8Tn+2?JiLmO*Wp< zSy@F3kMVF!XK4u)287)O_o&7JCTKCvEZ=|oE?yWS!Zzd4goRM>`IoN{OIN5ZE_Ud8 zmhXM<4a#K5b5~Yv|KNcrvI)KA4f1lwesF(ZeEBP%WpihPyZa*^oMp~BIx{@#7o>Tg zy+_BW{EU^bDRWg zjqklB2!vSd^~{!Niw_T`+xImp~JB0?Z+h0Zg=FhqG8FAA{2^7&Vu zv^Oqx#gBhf@a`MmptY>{+DqG_(3ZO+g%JW>R7@tW>5Qz?9bLPy$nn{Tbe6Kc+yWsO zXBCsALe+NL^0B6%K@1w_FqW~#gFgZE~Bk(&t(mY2Rjpu_AvL2+k=eNN(8d{Mq zHAWk}prMk=$BN=+i4yZ+marO~<=CpKE!>?*tg+&4!s#BjkhK=_!nlNNT>gf&=Rc$B z>=bPpzcBYYQZ@zW`DfA`Qc8pX&L~Cz03ZNKL_t*1BuB?oX-aov0}(|SqtST*QWC`h z@k^ch3D6qWP?x z?QWUnNKX<((R^KO8Z2WCrZ9-`JVpI{+E_Op4SMw0*BhFcv2}Elv2@xI_xJm}^WKo& z^3vQ8##n{123g-LRaJ8J!UC^6cUe^0P~l;PBr8h%&H`bjnVudJ6$QP`4dR6^?>{(U zJQ}mHeSuKn1~N%PJ{%IQZ(%~Ghw%OLshErDautoWKY6d6530^JF!K+9#(KFym7H7I zc~jDWDUKp7eV@u&zH{r$-9rMt{z2b?eM(`C#UzO{@oAjg>Hx*zBqL9AY^|d_9uMrd zkNaX#X~tDVT1tw+gm-@YzJ2=oH6bw+MT!(o3#$C69s<{_lg5-m;FuCZA#HU&&;YFP z>r63$(FG0R+FD1KM!4J_bcz%ur4Gm|?jNPc2Yhn;wT@33ke_l`-#4B#r81R+%#r61 zcD>dZTcaHHLx-tzh2R_-0k`Nkk=5Aq$(@*g$^FjxFF%J-lv3=S&bYF*z%P8^36dn| zcv@idoc_@nS5{k8WkoNJhypjA@_i3emIym5J!zyxAdHs2=Lydb$nu;tO%YxN)>--G zmU`o9l3qFOGbt-vj2L5rLB`W)_`FdgK03yUl+bV<^RrIwEucpMJgCM%tA!%@!aRd+5X zY;p+d-Kp86;)M=MfS!&hCnJ_tdK6hoI?M2az%`#zVUS2`(3Qbd1zz07>vqs(K{XoU z3n;4+sodgcg<>$Aar6EOcMnE<`uT0N5loW;wO|<@-DmW0$fQ)T@&c*~2}MEVD`a(Fx;FG?oUj6vk4R=$KQJDYrT>ke<+d1&rETI8F1d;H(u{*Wk+_|&UU zah!Xsg&ki1@D^1zW_5j)FMR3-fAFu5`R==W$asNQzwipjh0kPq#P{CYV>ojY-Buh> z7)v(EdHchYd5+4v_Xa2>8D}MX!#-7IQ2Qg6x&iycjQ%ji=2OgcL{*k7wid8OipfS) zqM(!!QD+eu1PCPw;{c=!=qhJJjK9cWG$ZIN;&oz9M+J#2NVCe(F(s5m$z+zXv=DP? zC**H@@kR0en1MZMV}VEh_Py*WY4TSU!4i##5Kq?a~u1@wv~wW~(A6jw1Gt&bYgG#;Isg6cu@z zkxet_IHhwI_kaT!PS(a3JMi2+Q_0BDk43{`Q8exMT87+Q% z>pr`Or_8(+Uii!gcOD(Fx4X|mr_EWaxOL((4Q}2$;fb9QNme10VqDA|Vxt@`6Vb=$A9{tYj|oscBtSSkRhYC*<&?&yyPq zeCFCBd&dKY;~CQW_}v8%hS}jhy>>t=y2iB^o}#Eq-oJZFu(XU?a!tJ%^;vB}xY{AD zET^M%ejhZAd$Ye9bB+!*<%gQ*nArI_K3=FaZeKr1Kb&`OG<^vzTbEFQu3>0l zYmJAkKx@iMQ%#1HS%Il?q*O*%h3KE1(2fJqjeWG%c*-ZuQ}O=0?~sfW^0G}OgL;y7 zF5MPVp@TMHxqfAXrG<#WwBW_3F0j1V<_}-LOO}^N&%K|N*x0s$D zAj^c}(GkgX%vrjF+`htLKjVd$ZtyE#xW>C5M~p@(UKn!W@&>ma4v7QB&PIoKM9PP^ zb}42vOjTi|hnaVU^#UqHy@)n7k;U@_K@^e=1{C8lODjF{bViz$bho#WK}4mUMW7pR zxjYE0ah8Xk!sr=F%6cD?L~+LjHX4oRd!Q8i{gfZwI^y{!H;Ds9Ivo*KmcVaOW+i!& zP)$zBkB+f%n`mVf(OJR>f$|jXBY_1*)Yi3%tk&DV-2kN|dx1EhuIwx#y@Xz8^qw$^~=G^(z6LPMhUTpi&Gr zTNIVxLBFsMv=KJ&Yu>pbJ$}SOy2oo5W3E5BZg-DM@x$AXNJEcqZ-KTCoy8Wdb_-jb zV6~>(?b7OWDe^+9zHxErTNGe<^r zWe7aU(^nSpq@dJ>R^)N>exFopR$GeowKnTs&S0F7O`Mqv!n#Cv!0HO$RxGqU_WCp4 zy>r4-mseP51xRZ!y2NOK7qtm{tC+ID<_VLDMoLLKoiIMw$5=sod5N$7>PG!jW!WxRCbDgM@1o~PquyPtiDlfyl6 z97hl?@a7NS5&gpl7^7*oVuUr6b1QmxPF~=-p@4K-a+a59tqJ3nV?$J$qSREnL`g}f z)0#6eq!dJ9%<|F_-FA!9(JX&>Jo?V4kpJ7#PWWeha{RTAPa2S)a%4#&tFlnWdKhDn zr6vjkT9M~&(jrIcTIfeJIdGPBzBDM$=_JaAdZPs(9WYYabI4jqqE1%@f-i_|KPn3-{$3Cc$pVI{UWy> zo-wO(gw;fWM|-_PrycUdg)YNk!tK2QPi}SShLS4JnVk(>c$SJdFN@AmE9^OitO*{> z2Yrgsh{d%f@+2Y2D%x8+=pdrdj`A?~o|hgX@==Pq_?Uyc^))x>DhH`Bx+DtPJacJ< zgF!~O6%dOGkxoEWTzTRtE^Tjd>;3_6ACw3$B8)qLAfKg#twq<&3S6O7qd6E?pgD@0 z#8Xgc!NaqRZrifGy1=bl`&?XEW@oiUukCYjy^ALe!WgQ&q<=Q$`D<%vD>xY>y!Oln z(o~%FM_k_Mad^~cZ7Jf5UwF+vIGKo#9vs-|pfAd4pa1IDzsPr9f7AZSH(nQ=OV4ue z!+pN|+y*Z``y{{pN8jRiPp3qI;y?NKKFh}s4|(TUY@9W3 zk`apq!oOnuX{w5gD>1#c=NwTi2vhQCH~|cv2nkcYo~}J3YE(r~U8ocYpTFeE!Lf_}{;IpQHFXVZ1=8Ek$0` z)FsQ#MvuWsk8geBhupt+pN$0}q~GH8fAtrPy$iIrpXK6ukIw2caTU2dh`M<6gr!Kv zyz~A;%JC83eB)!Rl$1rzm8%!I_VUm3!i{Hm`q~AuG~vx3{D}YQx8A}JTu7i7wuo1D z#A{#J;i;7_&t2c5)e5=1)#jt!8D&y28V*G$4NEPbX=WK_xQ0Urs;a_R@I99~ptZo0 zQivd|X$bWls|$qZ3DLWRZml4t!1sMr)U`sMio7UUU+&S1Jzh@?@7?ROb77SrP)zfZ zWHdooLr~k<8eNf&CdBR76_gF&XiPoivGYQy5ePTUhpr21u#}}M-h?BYQgxBu#3D76BUju%PQ9s%Y}^22{&V)c z*>cvUt|?GTIsv_Oy0+}(2$N=XHZ~AZ?A*VM`^;^TlJ-xj@&XZcX|1hc8-Xvb@HKTK z*4W%SN5=C?xoJAio4rP)P+O%6T=4Bek}TT5Mz`V(&7J9N&I*5%t&#^ASFB(~!1_wUjTT^TZ*X^L4&mSos;M)~Xp z-+gDy>HYyPzi^f1w(l~^jME&s{goQ|s86dozq;vjf^>_IL-4Kg(Av(MS0O+YImKj* z>@I@x5H+w9bvtO~kPkU$5x7FX)s2z4V3sOKp}HJM8W5 zgEe#(dMqz3u@Fa?s^G)>hYV-OSQ$`hLllK9bUS$BnCq9;xwzT;=rH4d_!s}Z>fn6P^^AulR~=R3&O zHc>0}?pF)Ug;a!|AkuxY-d-W9HH3i&D(fSXBa3K@DDsKpfFv!@R&sBDKqvP2%(EAG za5Uw;dwnNLs|t)2c)iYJuyZ{LvW|I>V|7VY3BoW&Tg&n3h!5Yt&5aAIDVFYjI&8b+fG>y7P#2+`M958 zjixL$Ri*J;8fBcA9wAY_kKY36pKFX7i%VhQl^Z*BBS}9g=fzLkE9pkY{;$9JNA@>= z>yJg?EB;|=?JxcEFA>R9h+;-D8sP_mZobFg`_-q3bf16nfBl{~IzAKoM`QaB|G|I3 z(eV+#b@LcH-P&;o;&zL;-C~xc6nRd2WsAMTo0v4k4`WV8IaMoVDGC|Ra)Kbh56ij* z6?mS{{lhV>@gsiW)7S9SHKY`*tgdqF-aZd@A8~nmg;?esJiN=+qM{SQm%j9QUbyiL zgVB^Iib=DKv)LITC0~7chgq5tN`ufPt#*gywGAqJpJX~k4EKogQv@2%3n{g;u+^p( zO?y67r5#EuoW-U_l2-|>DCEN0653ksohC?QSO|sC#SoGV?V1ZW>Z8#n%qe8JHMl`XY+dEf zDMig1FT`W7>(HyJvD2Nux7z)wLGSAKq@e#cUd?^Xzk_+pLtS&E5WeHKI zOGg`y4|egj!P9kvqf2a6VHJ2nvA281^mM@L<|_C1&d4h8!m$2KG^WxBBe6DrQ#IDR#tuAvg!cvvG*Ucmcz_W8^AVxHUX(9Uvx{!5?bwbx)gok5ke)ccQl^SzJwC%^fp zRN*>HE9 ze{h$3Z~u^g^q>DCue|syd7dFH2(;rImpOSlvq@Iqc|PlFtD+Uhj>9NDw5@d_);)}O z9v<<%_wJEXB88?D-u$68+GS;k!bf_F*!RdP2e%5KEGrC_w{M@Y7_M>m{vMYvZnM^F z@%?ZA8R>Y46$%x0@H&fDg7~?we3?Wpa&vdaMdS11JI6%JtIqemDpBQ>4YAAfYZ|#G z`S{}j*HpuCV`oMVcC@Y^Awtneh(Q*OEz_%SWd z5RzkU$!S03V31*j;F&9{>}>Y<;Ng&}<`GjD(bfu=!fp*Fo3hki=ON2{`=bZEbMGzg zpK46|GJkoq&-;hBnU+F)>C4Y@GDvyz=02A$t>bAyl9rT}VRa#55c#y1mYF0aWiqAR z>k=;aNNWyn!>=xq98(mu7uxu~BOS|KacR4UsWxKf$G!o+P>VkPAU*yjCIhM}bJB zBrbCk;cxqCd~`o$$eU*YWF4N@3x-n_-{|M7Rla8?Ox z3V!SN{+yRyc?lsbRi0B;8Op-dWsjY;4!`jmzhfWm_k~a%fAZ(Ai!XiQWnO%8l|Ov{ zfV8%()>^x8y~UV^M?+ezh+qEfB^JaYMSqtp%eeB)iyV)0PDPg_*CgX9)3YJ%(|y z@7Z^6-V^`)Pj2(!or`R3t)ncoJVi1~7!6Bi(~%ubXJUMJpDPzu_}LeJg;u*mRaGc2 zrZSqU%mIt?V~o*YHD!?_l!xbs6lKBlPhT|u-Lu!lJEu|%6UpA#s*3i? zGBT7DMa4=d;PW>&$SOloYKo#n3W?`=ynFAA!Aui+9?JKe&{!ypbps5~_mE0bRgUk! z-1hm@6H6HFM67vU5eAad3hp1yPzp9zI~<&)+3D`j(CT$*atIpdsfMFZUF0Q$0XENRZ(ndi z>&FVcdEUWenhawsWnQAB#%qNxD`j4EH&4wuA0O&Q@UfwPGYFa!l+ZY(OTD5=oXVsnVp>AcNYnkRD`59@hBG5@VR|;p zFrJ4D<9VR2r$7mJy#wE)C@O}t%F%c&^9Hy%v{Vqa9Ys%9b97SA_tECsIyAzdNQ%m3 zb~PC<)-@hhd2<8|BiuE?pp=hU*yLaT=zzhf&5f&uvq^^ZBl2`c|9F=ujCte36DDGb zZg&;JmIEiObHbELPck0t9*Xzx9&u8{EN-o# zt-{YW)3hM33cR?33R?&jL}@@#-^|*jVjy_h8KGVn|+S4$h`Le`Sqnnsa-9z)Cyd zmtNW7{dfBuF2y$WGofsO^m6=;5lRYPy&!n$v#;{czIBJ2yT?p(i&3w|+3^9lZ~E5gqNZxNtPLTgl~R$ViK7jL0eMj{Jp9;3p>xYlgII*2CzMhs zDG6gkSpX)Z%2KA&k_m3=b==&4eyg7Cjy_>F;y8>vM6dN4C@=O{Ugg zH)0{4v2yuYHn+A=gFBYu001BWNklZIheH-tmdUe%G|g$RZ$cPhYSDg~7a%=6-3QXl3cTP`Fxwy5!FMjn^o`32J z50A%g^Ntp|Gq6bCL;1cF_m9S4A?kJK8;3<8Jg;^LGhAA0b7`Z)AKX2r7g(OZy2Gve zXFPLhk*jNMmanaF|1{z4+b2ACX^HKX7T33X><=>D{P37gXE?rO8hUMsMAP+DNo@LSJVy zYq7@tTShTKXBkmW@Px)wpp6t&Rl4bI4%f)p;SyW_6M%1m4VLf<2qm;y&imR8d;&}mD8=k(p!1GUC zHpUoXj1dT|5CW-`)y7a3mF>18mU@fg_D6RZjT44RMKDfza4_PztE)^)kFURRi*aVe zwDQ?n=+cV?H?H-F)y!SXI*?09UDHZkaqbe8!}{+T0)wZFSnYL0XPk3!Yn%SK;PsP) z?d@eQE-&-(qY3+c#h<->M627POsly|n{rq0JjJ^<5@>|nQYq&^WWiPjAuL`LVom5c z;>J)_6}?sqPf6bW@R-RguP5!2AoM7-Aq;(dos(HdmlZWt)>!A5q>a00e9z-(nDX_v z9?m)WNm8)Z@%Woxe2OP8^pMtaI!;F<&HRAh~%DoViOhXHeMu%=n6DMHQg z>ztz3EE6>y%UF=MX3CsXfv`~JCBl;~bIUephh;v4H@Hlyx`1w|YK`S@=t-_`EwH}a zVfT1~Eeobe#&_QMkp5tVDkd;HbJRLCT32XYIW3JJApABOAFVB-98;!4l<(pDA;M^a z`u?GCDx6rxMNoblFf$tW0*WCdAXQj~_mtRTA)!c$1=vQ;8K zM5HN2o?tzX($s06pB(?r$0rTQPdP4cZ0O_hN!CvbA}VW#CqfKD{{Am~)^`5(3oJy+ ziN<_i1iqpbMs(T>w#HY*a*M^Isw(^7;R8;N4u#rSW;w82zP7{d z-9F=4f${@X+~)d~Rjyv>@yy`qu1~MG$%zOJ z2mdL9qX$r>7+`Jt3GP2S;fFtXoln2~B7fth4R%k?>dndtBCXLFYe`ENLS^x|cKtb$ zO!LmWcSRKXNEsr-7$F2zmgD&WyZaBxW+R@svdyFWcLi(mbUh+2!n_q22EwH{W4 z2o;MYIU-GSOxIBygoNdVh{aCKtp{gN3lU8-*~U#}%w&k}pFpMg=3o2>A6&rRZtsvA<)Gn0Af?YFF+fe9Q_g>1*OtRgkz%cL=!v>5q>ZW4 z3Hf-)!s;?rQIaMpowW@_5Y)(r6VoRBAzs`@^}3I_#8{^bQi3d*;)fANSga{(*PjZl z6_wE_4ONvPeTl7R_%_E@hP~Yxdk-J-;`KG2S_`><=ZO80=EB8I;@Bsva2KnFowYS? zlBjTo2BD9wr=AAEEJ<1KEc4oP8-x-b?VnK;1t+7Fz2gx_rz6IhCQ^cf;}Po}pU78C z3PYzAa6Fjt!QB&HeR_?vQNp9+5xe^bbP=|<^`gx0+k zXm&E?z5s&tc`IZ0R7kU1`BWfYU1}3`JH$&BD)i5!CJLKMaBwTl^%(&*7Cw%7w9D740+&@#j>Tp);7 z**h9>FF)bcXLmq({OI;RNme>tM1#52MV2o#>FF^=n$h0cLPm~KDRe=4bcD6gy>J2R zd5+%GKnXPuKVIlKgu5 zb@5(bck$SC-!^Z_1%5V#VZ%9lJiO2fNB8t8DNau*r&HP+ThQt_{Yb41(z7Yk<1@T= zmuO|p(d+7a-e`lVG`_7fHX3?VjX;}9<45Pn$2{u;P=SXMipDy&L1&BSQ`uBMC3Ym^k>WY_nHOA7=x`eFF(D`3m3cWth6yV)_D8lBl?pW z>1;waJjD(k5||MSorpM$T-C2Cq%E-sOf@Dqis5)lIXT0Zn%?pvu?mr%qSb0SN@SIz zwI(wqr=ua+;0)jQSX$Vm6H3A$APjsr1ha-GuV3ZPgGU^X@8h>F5wsUbr!!39vXN{} zw{tR~hbFDXN{?YKIGAcWEuS!UrZH1*g{;-09eb?yS`?*bp&jtTwRQ4J zbMyWQ5_s|HRVpJW3eATPj?q=cNeY|G%RIBz<mQ#qAV2N!eT+u=RmoC}u-P%Q-HOZ0Ulbeb8zfoo9+YO<|=_I!saaWI-H%2*xp!S_u)e>@3eVv=fG{?R-n9q!1uUw=K;U{Z(is9yC<|)x9Kb` z)IxDhIU1v@k~j*%Z-eK#^}crEy1KQ%YA@z=IH4*sMx!ym{*|YAbUfzAw~u)K+6qUf zrzDdBJ6r1vQ_WzUbH6|4)<*}lmwQOhrxX%{;>}wp-27;dY&>E5(p7W<#SC%pV8qGL z;BPH}Qe3)niC_JhC%FG;-@f%|By>Jwq2=)lpM8m)m5^`!c%S{;W1PY}AKYa$D>+G8 zcuTlIv7*8ViSj+1qm3)V(picrOQKc_={t{hRgd1jf9r%hZOKd5*RfTBkD=3UqwLiF z+An`bT-;p3^WfE&t|D!LP(DUDUw9EjoJ3dom*2X}-~U_B@{j)OzsJeRDNkIx%y)nA zf%wL4NfK=m*`_Iy2@G1@jwU+T309~g*DCvEN(B*>2!sV%4%H-PYKGh;^VzO z`~8d;pW0$;waai;&<(mws)9~8BCVi5PPlP-o9T3)`*-dUMF%V_bnPrHI6gVX7$~&G z_k0$+U4$?~7YWuBEUi8vdJBvAUc${sXKZgQ^K&ol@JHW%pS6_^7uJ^e;Nj5aG+>+o zM?;~RSGumqu|{L-Cf-?LQ|BW%T8fa;iI5wcR0~4rxk%cR{||d_7GqhGpZEPD;%s-n zxo6hCbyaosGTl9EPY*dW+)YAbTLcW-6eSoo34h(%mz?RCiZbb#?8TS-IW3`@Lt42tUL*H){xU08+0V4^@d=?sD#l z<^O%(|NFow1+yXM;4Uw3z^gB;64fH!{p65OhBe~(j5Ny$Js+LS`QjOmU;oAnWbugk zq;IWGiK3eDqGi7O?nA!2(?hUA6a_TvArJNj2q{_VL_8fNE)cI|C0xj#Asdaz=LwCq zRb*Im{YbiCez1?#miopf*7IFsHIxobRiPkC%j~M{{+S#Ms=#h%%}zxII+u|}=G3B3 z!2qJ{r>JCEWe0oJUr`;VpWzNq4x3fcW2^6-6fDoWU`Z+Q&?LQM(#ed*#wk>zNv_KP zRHe|f3Dc+hc#S6E>bg608fU~|OO{3Xo;$Ht#Zvhi{4l@g*p5IOvb?l|mLN zdOk*v_6V{8t(vB-EFl?w7!m{_QUqvYDat&mV%TR8_h_xGQ1?KY4Bz(%g~s z$Pxs^s;a_3D(M=y%em=px3YQPI%5E-#NxVD#U@a)kYaJ)EIyNxsa92PNcoSo&h|F) zB*qwbO{y(RxaVxtBb1a(Ckbh$*&ilEalyuNgDa=I+`V@|GEX?SvC54r8+`Jp$MuVA zNOHP0kFC`vNm8)dt?}`LLz;odS6@EM_uhX(qZV-G+%oU5!;^UG&&FS4d{%(`lwq_Mn8LGYd3Qp+Pb4*IQ81bm91om3j4X}IrG&lXDKB4H<5#|V znReZyH;Iuz9A~`n+$o~Kl`~KQ?mXMo+-$( zjCwuf*MIGGum#iUjKhN?4tF0Tl;rH@d7?&*%u2rU`4`c`=Wvqo_-M*nw~p^AKHVO0 zX|v7#Fy_(01Wzfd21fTnoo-YJi!TNFctkoJ&|c|Mq#3j6oW{l`veux`rUZ9fAt#ii z)^044(2e7#!DKYNg4uirFMiDH7gxD!=6FidTB-5)(J|MyR_%v}PsPhyXGpdWINw?! zt;*nNB8bZEe_(Z{HUi^{Z^tCzz%L^DYgMFdh!cr(={5XwRdub&jl*516u9 z@Jr7v6U2wy+uLRy&-wJto6PUl7*3{4Q_EyLCC>%5bC+O{bLs4Pp6mxqGwT?H6nq3i zxdu&zVmQc1M;SK?LA$-o)4iws;rDKH@6irlJ^M0CD@%NohP?C1p3nxu?goCXj?8P^ zyz`iw*@%O@P4~W2-3o(_!{87`$N)XF7kYa5DJOq_U^}^>U`SsD7EpGR$z6(;c&)EE8xaUbvo(_`RFNodwcxi z7hYg&njCtHNm{r=kueDCLf4cK1im7lri8T?%J)G@VT~>=hC?hGUj?pkwqRv|R1sEq zNGXL7%2{SA!L(338W@thJyaO*_U%1}b7uv8x)bn~D;-9YjGdzyCiAH)Axu7FdCBA9 z_CCM&XCIJ7n`8#gt+n|(-?~mS@)@K9jI{!>YSm~ee5EKd&Gz;Yr`qzIMib_|6YZRCxT?|KS_*-@JDue*4=G2-j|)m9xP;zZUQ-U%AM9Hn4yAuRb(S z_jdV(pZmJJ@zMzjy1i(I=5 zCr>I&JY~MWPf)89uBf-A8?FRUno zgHN2(P8!S-36Llz=Sp6rnt95F$#cmP8Qv zk}PwDj47>?G0x;*eYt_>EAp&hKG&q$G94!PN+8d40ZVQHrSLpS;0aodfDi8tn8XFz z3O1K(>%j;zNL=#7m@H>w++dSnD>ZM?<$D;AqaBgNd{Gi+ny9&S*6P zOrhxyr>q7Boy>UYrOOO^bKbtaBl0xi=Eplcc{;>Ok6Oc`!agg@tGxcoRo?vch_`O< z@yX7Jc$yNn+W=Typs#NaHz6-S!FX z`s@&rJc}9kpIV#rL@|xIQg7qcmyor9me4fvDcesE@caN_wfhu`oDhT7hCIt?ZFC8J z_|cm;X@mlsr^v};Mw1EStq5=9EVpjoW3{fh@#-tEJD~10xOirXC=AJyg!3D9lqb0V zbcE+Ax1m>31KiVkN{~-R#DhMqQO=y7hN%Q((B z9?p5~+B%Q-M!fS$k1t+dCkj2j{mu?viGD_*M-=*G#v=_^d2rFoGc(7muCmb#iI0z&A5UqlucEc((wQZ0oN4jaAKj+Ni*iC16h&bJ zU$N9}3R`9mm?|Ga2&BYnlcRGjlnpV~(r(oF!j)wXCYm%a@RUON0lC&>^OS*3X|~Q_ zYi+*$-XjzmUs=!@QuN8Kq;vJ_=*Ak;IK%IRytikOBur*P6osXJJQUKOvbw&C$#d>K zI;7riQ>cJbTg!A?b@JJaWHP0*v0AB9F&5&{3@`NYm0YYlmDH+2tyP7#Ql5W}LF1TA zg{8o0$sJ>B$wzy9^K!u7_?heWpZxYew*Su`eNRYX#ozreu>bDQeuEEg-4k~NKd}GT?|obJhja00d&qzL-<%~7sl#NHV)tOg;n9etZWE;>H}Cg|bM2aF z%g;btO{H0PITaR93X;*3BFpJ)ZDN8Dqf3^8^7o!yBTG37WiHIK`4^N@r%E(sDipt5 ztFWchos)`vL)tqc9gS$LZz7v5 zCpVLhh19bNvx7tYdYx!>11+U11OWByzF@23qRQ5A@Bidy?wv0RrRp6n>Y_^C!y=2q zS?5xMgFjikltj{^_`_1}(PhK=;)YvX-0}}A=ESjd#=xe@8iZj;9M3RXlNUKk7jC}j0+7_3&9WIE z>a`m4`HZ~C%ATMMZ3-s^7J^!>?wDL_m>ut7W&>)CRl<4$o2S?`g-Bq9w_t{f`II8p zL@O(0@dmbVeN;iXxDu@H4jfIR+d`q4iXCK)0^a65|Vo8Gmmp;zili^x_Rh%9-$H_ z71(yOd4jHfHvY=vvjXI&j2wpyi9Dq!<|H z3eOKXc=8EnE?ncwZ#dbHYkaf|J)|yaNb5jK!l*&2A;~pKX8F;_yBzkXCtmW>>GdBU z&dP}(I2>glES~2xIG*Dbmd{5K&t1R5&fzhmyoPsajpv^8N^~Cz2aEB^R1wWBs=H3Q z9fNdDn@%29Hhq>~TT>vVWHuc$osQ{tmT0xwn8G1kS)P+5DNz)GO4wLm0V z3Tw=>^RsNk&Sq?_2Ig0P<~gx<6boY&-PNYB?RDP!^kc>c6GRdta=!$91fHkR+M&yo z8+=|Eu3lK@+KRDjD@&qx|84H}5BM8zT;pC}$u3qAG^drqE*U^1N}q@+I>qLfGPc!=jI;y4BYli6&6%;otM<%jh9 zBV3_qNRJOm1_j>I1w21sHXUQNA)AabSzf*`L+(kAGM}G&<1)3p$Hnu@{Ol{g%Ad3? z{ex}5@U?G#ldTKa?Yr;2FP?wyCGI^Pu(j1>rafkH%9pQi@@Q{Fk{5jb+A6!f8Tr{R zFJD?B^b~qFqR3`UXH(|GobP|TRvGj?mZZo2lYPGM{An&-yTWjsG9C5E z#|QR>3r#T@xdUZr=Bzd%zW$}lM1kVpy!C)tQt24amxKJppG{n+%U5{`IE?-t>@P_`+o&!X^Ir`|ps1n|$Rfg6Hc2MVgXk zIki%6U`U1-u|MlCG+D+n;th;%-(gE`{C zPLD5MTO-wmM+X!7(;OisS)6h-&v|eZvvu`4&C?f3jl3(SjWHkntH9#M-TG{W~DplKwbhG)=KWqJ=`2a>}YpxZZJYZA?diMJbO) zxa!Io001BWNkl}vqWijJ<5>E=3L!`%i?S&P4w7<=t z{qQ|BzL?JE;`jgX2YmUfKg+e#E$%)XVxwh@g(wPm{CL~^$)EnnP7)--6W@RHCU@?9 z>KbS*ctQ{c3g1&?S%xP=&aSmN9Q8@ke36||HRe_sLhfIS(H6haKmybN_>^c!QvW~=VmD!`d(<1bWQ#h>#;ZtmU6bL zKcY(emSq}vHKY_MtI7MvWaA0VjV)xWy1@RS0(qk3#C|uY?~84$Q88DNUus6R~5WS`F^C3ivqY}6Bfmt1yQ!}FBrB` zmMd&2-;#0x9NNmE4Z~{NXRRHue~=-YA)U}NFLG>=BT8wJRLV7U>x47`Kk!MD1f>+U zTI4<#T~Ot(Xj72q8S~kUJWZ+9>jZv4o+jv`Aj{M0ot4)^6UQ-eENHegOUtWxVV&`G ziculLD$;mH*jROQO-gF@h`AOeo93>h9|WMPs?IskAtiC9i3+c@&SlYOB&8rL3ZgJX z_zIKc3;AByZbR8uxo{Z6t;?#@Ep5@=HLgNDlL9Dox&O+=XCyq2;k;llN%54EAPNM? z;v}e3sWPNfA%r9?;7@PvaX{{8y|T*A(FBYpPv#uX3cR%rS1+y;MLvF@u~twR zHwUGxyy;xXB9wE>iwP!Yp&&FSMd{%(`l#!-Jq=gnP6}%u$X9Rvov%Tbe zr<0UsXANx(qgg^{<&>i<>n*&XhC`d|BE0G+z%E-g(F$g9Ous)utgJDd`n+{#ALaW< zKf+Xrx3)}{Rg_eJh4EOzb`wE^Kl}KIMxZFPAx?6ao8URD%W1D2%HW!D9f~uv0YTGa zu~|u%Rgo8l!1M7GjD`b}`II8dpu6PI245khV3umEgj&=fjt}gqtradk_o67WiIpNh zp~c;sMj|mrGdS*xAN=SO@o0A_q*8R3S1Ia8+&Qoqzm4bD5H`nks95s6a0{6bgi%PE zYI@^@$>A}wcO;IN+f3#;neljV|5JLs9v^)8fLGu6I@^b1?mz9by4*qt!8|R{7%pvg z$!!(JRSFo&m#d_pn2gDekLj*-(Rt2nmQY(;hcF`7W`PP;=%N<})KnMc%acQbl+FgX z(40NhAt@TfGpAh+!>~*ww)o|NSShF9^`*ZkI9wl5b+~YwN4wpoC<^AY8AV>us0BQK z`67F9gZ=(7S{wYJMmCvZr(@^pV+u?l2x{wi!r1+%J7R0;GLh#R%4eZRG8=4f>X&#C1a_Xcyme`kOv4fAtt0t$pOm^|mDb6q-(kl|>GknrKh5Ak%&OXoWf_t|^! z2{m7`v3`!QyG)+MJlGo%b(R?%kGS>zZKTb4(0fQSIuxF;AbrB_7RK*z;iXqt-8@Ba z7^D0Ur6tFcglN$z;Zrtrqs!W3vA#g*Ke&C~UWZu$G?LzkYGI56bSrU#2>wRSA2Nu z7VQS)^DzR$+*@Je{0$oQ2xBdy(UjXCeL$EUh^2;)@**-LIG!tUoNlmtcS5I?6Zjs3 zSwT|DmHc*_BG-K9qeH?#V3ByfEBJMhFDx;&o?`NXA}{cRm@x2NFMyDxOv2gKYOTq% zK(@OKQ-kLzKG_{(ti^A(Xf~S8)h;>N)We!{fJ#ShP4Ydrz8PzsR6_`?P*@=-k_1&0 zDCw0wtS4H2QxxT479`6)$G2_`@|2U^rPCQYj;XIK5!Hf{!6_L7;Up?9 zL7TGop;~87_J>6hwRP68T9<*eUgeC&PaN7SS1X<8=qyJC0e;|@4|{Uh6QYuIIaFF} zLo%8og{8LCMS0IOR+nIx3jhR+MHdA{oZ>~Hv%4-8Qi_~xaLjx-rLn$=YPBfJ;>A}A zJuhWfjV8gWGircR2~g^{sx<8)&q+oT#~e4xebX7zVT>Ue4iP}Kva)bYt61uan<&cH z8Pp;?-**x;>Ckv71QZ&LMg@Vp|Ln8qI%Lx+%JT^7^+oYfnIQO{BujIUYJs{7w+$ne z;s+l*;mJ;oQ!5SL`}hg7dBUk>_dYDbnWL1&N>LPL5e88dVPwE4lSmZSWD5s3A)Fgr zp6BSo^`v?24pRB$XAfcElcxz(Od2jaAf8PK0-t8P%lg&@QhP|8IJUxAx4xxCPT;E2 zQf}wY2*M8tB5&~=Ry#RVW-Pr?R$f=R0O{PW?tmOw6|!XkSy&c(YGq*Hwln9zNO`8g zy8F{HRH8hKNJN>ePFajfNx2?Kw6I9yToAR91im8lTrO0nQ^yY!%~peWoblra10L>; z__a5#vbj>{)4d`8@7vqV(t@9Pq2SuNWsEU|z9KFx7upflT4u3hol3*O1>+^8M0g%X z2+~ylq^|L^@mCt36(B!l%=0-}o|L+N4`U!rQ+!Y1DUVz@7nI65sn8kL7<5rA(3VA& z?^GVHkPsl13$rVXW&fzhlf53yTIl5qcvUlAi3&OEQBGD{%OcU*iZYQGIGPq5=^Rf& zIv$hG6KdVI^FX)G#l|^s2$J!HBFhPz4YvuI0=Ja71=d)nC(YvtI-e0mA%QROq&u)n ztDR=klO(w%D>ByP$#^`*8bhrXu>GXROIJ6^vy8ikeG09)d}fUxia530u$Pu{u~ggO zcJh$rr4GwmYmC#x>ejlrJNGfM$8er<{oE?6-pF=tToZ#`MVidmy7&S!)kTME+#6Z$ zJUXJ=s_`pdI>-BWp1QmmKf(&1=`7>T-ac=A_=M$VMAwJo{T{TsDCtue!=Jpf%?lSh zoLXtnjOx7o-aU-x@%ra3a%yGD4{z=BwUQ8aJN5#E%~IIJ@4V zH=Oa_-Ha@`gw59RV~2cOArW2x?PVIRCOLwmL4uSLzm)YXFFDWtX_C`!)d+o$?cR($ zw}if9Dmu*o-%}h7Vzj5Q1}?0%D74}3Q+LSG+LZUCa)r082o86+@yZrWPe_DyvI|wdHQPa-OUKP!%*5VQ_4;GI%9Y<$?uE$0BVP@~X;LLq)+N z#kyh=PSmnxg+cW-uHm}s#Sj*SCOhttOs3SLiXl^6KgpZ^u!`QdkX=SOcXERdD*2*U_#9mo^UV|+j0KmLv11R?onzw=MY^K8Kw zd452>0eP093(fx1r~KNl{G$EMzxB7oKm4b^&u{uO6?NJ(%arLDI81;gPC zDTE81#4*)M2}ZMwc$V_HOUtZu>Rh|9OqOSyT5E9Q!YcQ6hIAt7`pSxovs){?aB-d7 z2rivnX7^}FlBB$J?JS;@TwHIm)0;3$GQ`4Zw|wnFV5K|QNFi(^44=KDKO29=@mT@# zQ%0WW=u8`9A*?rP1P-mKCW;W2EK3nW64e_Ros-6MtSN|UHK25cC{ZX~Ixkh5l$3%Z zFBnc!66)l+prIt5C(*iefGG9ARxEZl^63nnylW7ax>T}9~D@H@(?AO zt^}?CDP=#RM66sL7!qg0;>_)`L*8~ zjFGc_WchbWIuu!2@T4Tm^HR?*o&9e0L0DICR3DC1lIe7^*aW16!Ei|OXrFP`B4~6e zjEC216V#d{vC9=vK}g^!&R;#vZvU94qaowtUB=@fy+KN0>lp2E@b)gz%|nC~tS4(+ zed!Ff`Ize~mU~)}q&cY;qHAJJhd1qfd^d>Y^%6MQ9`y*;k z9+0V~=xjCUT-?MCXJl3|czQr)_rxTGQNK@`#x~`#h`kB^Mw3FdIhtgAvU|uU+e40z zCrB(_(5FD~FW-8MF@nPQ^m`fcV1y8YMpfZi7{&#;cJiVABqmF9Ry$2TesIK6yT;Fd z{xmOLT;sd%&Y1Rk)LKohzq-XrCuF(lGnyoH8a_8JTqMo4Ly$wojq}S4CJ7&Zx=%8m z;2}^!M59(?G&$%%d(-GU3-0$Nl=ro*jPnPy^xjrRqu|Tw|Lo1XX8qXYVE9V;x)-ipR&Rhx{`>HG$>6(E{ z`Ar_rA!*m{yqDxU;HBf-GB9)!rH>Bpf3K8 zKe)*gbB0_+U<^WAk|bk)_a3jkcvh_b-M>SBFtX>*Z89Gn(mU9p&`MZi>9*^nxh5|x ztDQPa-8O%IbC-E$3F{F-y@pgJD^{(c7OXju`XtjiNnTJ}UM}r>OZK!Z#B2pF0bad^ z3d(#BP9#^=5ap6>mB5Q4WSK#70%FKT^SFHGZr z08dzwUXP?dqPBSouhmAE#gkGJo6MO$eTrXe5UsDHkqdd11K&zy-MGV}F^=^On~gFk z&{W5N%CjnAqrr)5TFDA84#@6x3IVbfx&wZB87s8iXydH1RaF4l^6#snL?DA;acx~8 zC`;zbqO11*@(f%rCrph6me+2q}p?#rD%fXJM^8$8v!)my6loe`t^4dwuQlzd%`LwDuN$H_G)U#) zc|OYb@$&!^)lfEn##DCc_Gsy--#3)rKIY zB+GKPw|B*4*hdxt{*i}HGqg}d%`PHplNVs6K=__>H_DxkS6~pvJz%*OFKilvdJWmA zmCxi@5_eEmU<_fsfggpgV6nKgVXfUJ;T{TYKm|3>2_|z0D#|C-Cn%Xf5O{(V%XB&? zPZKMo6~a2k=P&G=2n0n@*uin%fG2L;xJtcNqt#jEFz@pClNlygrEO=mxRr>N6j=?Cv)(g_ELNAxChOqTNP?G8&T>l_W|eDjxoiPtV|uv8z>pCm*!<>J|O zK7KOb%$YTYg9(5B=3TNvJ9(Qn6!RIKr4G6%m`>(I>zml9UV4C^=z}Z7R?lbHJjM$n z!e)bFHYXqSU4Kul2G+-q;Q0%u=s!$(GCp=iYZN)jl`c@ef~jLPYITQvrHQj_EOg<5 zluGK_^E`|$%5~cXJDuKG@hpvzQ?Ch=LlawPZ%pYIgbY z-CfdTh2`}tEMI7%tt9Xi$$ZX}r-#%V5zEUL`S{@xKX~f{W{E*9Z}Q30Hb@^M1bgr9 zf-&T&Wc$avymED&ufB8!S!*z#O^HVX)}MD_X|=$k+i4R7A;&XKnhn`p-(Y)mhWa1OM~{#Mb!W-hpJ@aZC7rfgDn+O6v3!1+{r;T2H z7E2=pUuQhHyTi4uHO{TK`0{frymfQR?ZXilHtMWL1!ra58YvDS_7q~w)LE5wCi?|4?qYf98#SWMxvNt7QfSUh7*iIi51 zpF6B)afZe^Vd+?N}_B5us>Eu^{^?lyD-{Zgk-~J3=B-ZysJkKZn?n8{u zIT#gUCeG7EV~ytKy&ijmInSS8=A{eEM7|&?guB-&j>0%AY$(sG)tWCY!c!>g7}Ba( zt5E(bbPt>%4Pgis5U1D#_IPf`&m)V5uPC;p8eg$8eOit zIEj%c3webmAM}Zb6QZ>(WV2I#uBD7Mo-y0o!;fmzHa5_ej>@ulzovX_@yv5B`c)P$ zKsw2&I6>U2S61~GEULBgu@?vC#rIBr#Wlox<+@#7)AHv=n=&KhnH@?%UR1zgc^KAa zae%K(TBHEalRVlT@GnMV4hBstDfkz^|F6W#a+iL8$apfxT8Qcm zl=8?`jwc26dYw*pnVYvh;eYra{~m|K8A7#@Ug*LAg@hud?!jDxmX)l`NuP=|#aMxg zBJz^a2z*IVn3Cml20Yd}8{V>Zq4J9ni{hqq2rch-Q?go~a?WXmb(Z6*yw`jssrzot zPOM!_9s&3gTD6dgwdAFQ(ai~g@;qi({^X-W-hDL02dqFYh1A}Md`k01@4sd83FQdGd?Ro z{*v)K)~b8|>u+6N4)yY($`Bd~T_DjIowd^ehHgy&{!SN3R1kV=Cq#Z zlIrvjLZLOFC=+<0$a0pNq5a0^pA*Y#rx;9AWV40|miXl9khu-0)dJ3*TIOhyF`Q+D zt)>g>Ql&+u70+xafOP13Wh}ceHnAlYYF$&D^vfp3qNGiQaz#usL6AAQl^@STW2t1HVJj;Akatu?VEJCgim;9e>8viHvz*x^p|N!eYIStk zbYBG%Iz6k!%x9#B`$&^xJc*pwonGDM_)#6JGxBK`g}tfo2OJ*u=uO@xR+}`=T!N)73M4A@XfAib z^DxG+wbEd@;j#O8ha@v}J1tJHcS~u2b6t9Hc#O0;t4r&&J53(%+-JG)F$&CW0-&r_a1yTtNJWWz8M-@LIxkry0K5`w_vc$`uX6}8ak zcob8Me2lfsl7h>pJ51x8!7RlZClmbYi(6P@x$|VmmtWXqzdvL9c+TrDo@V!O#1G$p z#FcZaj1xoD?YMlAtl(%cA=8#GJikd4_$8_5@uAEuncr;_LKj%UexPqkBCQl12 z1qb~h^T8o6oo$NiU-`Nq0BGQQB=$gIZZjz=+oXtdErySZlyvNWNHbBywco0s@7-Q>=0CWMm6 zAi}HFK&P%ivY@|aG(Wp)Z{Fgl#xW`)Lg;WXRJX462D6e%d0AFZ|!7=l}gxcCBe!J!5Tf#|eY%*uI zw}D(x|I@lXEX9jx+6 zMT7BdOg(gafy5n*{lEjOP=1}m!Gx!WeNrL@IY?`08J|wQh6FIcE5Ez%FEN_k(d1&2BR~#kfJDx zk{ZToYhSv4nG0vusD%N8(UhgtHDic*V8!~{3hmPu*j6E_ zX&}Q0l*B8M8KfkijL8NAcj)#MQV5Rr_NcXT;g#s8wvs$cnDut7DhlEIK5>#^O~G`Q zvbMR-G|3qZrz|Zs>9#`J?FN&1id3#hn~f*rxu&*$8XH8I+-XitY5Q$U;7niL=Kug8 z07*naRKr?>j^`*KYBbSVLee`%2#ZucMKXsXL+Kn$!P?p?g+FI^*dqviJYQk0D^P_5 zF9`61kTgxO)}Vp_V+;z{=$mF4TI;e|_+-=7dCsZRXINf8&CMq%Mg^ovx=8m$fG{~y z8!j$&@TW&a$%t3aM!fr@H`#vs0BH@L)Z|%8Vgs(d^m&%OF2@h=@~hu`gX`DMvUfOO zGMRDd{02vfrN|35+7UYUIrksjWisrsf9X6IuD>G230%JR9M?{*Q>!gg zSeT^+X;yG%waM<$jI~aU-Qy|8O}Tadh)M65 z$UDR5Ubw)U?|j1hw;plz@+p)MTt3w$lA4_-Pf3TzJa>ANAKiY+;V9wKR)hlc$E+WI}7XTSip42K6{j$nii}2dr3&ib700A&+M)HGD2?wds!%l;@Xv z{x*aD$gxt^Qp8g?UrcF-Zaue-dl4I3Ysg?s?P$vRjWxnB0x2kpf{kuKpoGhKG7zVR zdEz?nr1D(fO^Nb2m!uPL{`M)j1iXdVU@vMhJ{atM+q48^d|d^DxDwvKGJoHQ6` zGi>7-lc#$~Kcu$0MxixYyS@rrIUoT=UXaHLeiRWzZXd8EgJDXfJdb0FI3`+J!tbf~sqf=Q+|kmo=f};;>sKbX#jE(j19E1s*!j zxqf<$G}nwqGp=4}6HjAqoL%AL2ZuD2=K0f2w(mV)GMR7~dzju1MV9iyi_dZ9+8Rlk z^4g7ythBoba~(U`W_EZVU*?2ifEAKB)fCjwo{zSW%78rZnd*cfku;(ZBLsy}Xe1^T zSOVf)GNJ}+U5Y%XuMbZ=XXp_m& zK7N`JuAfGz%GJ+ceIM!jT-a>!+LcuX(~JiP6Rw|bkrz$g`Sg%iFE8`7Kj-a_4-iF$ zl0M4w(Itx)`jWs88K;I^SG^l^A);$4G4+!PF&XeLoRku84TeNo={ScGs3?E4?y;^v1RQ?J*_jpV|W8>F(ubTH$K zUwnaU{~vpA)?`PLUw8i8J=VMDz90c4fC5m3TDrQbt5bpI1Y{ z;n|GwWK7z6gLt#Sy+h4|lb6D;wb^{V!7m;jFc_y8&xPrYPNob;6LxklanhS{&`&5t zKxwPZfL|wGX`c6dRIJh*Z4`@ZDUhB=ZeTV|5!RrB20}rRr6_5UN>SzpTa+BUc#dE6 zE2LYHBsrqWHj!m@t;({Zt-)yREGVrdOHy=2k!N{U<*~?W!y!37Jm6%IlZz!Tg_@P^ zCWUcyz7&F2#{-TJjyY|XT)DNuZ@sl`ho{fQwLkbaUwrY<_75HlMG30O+aLU{l~Ge% zzkZ#^ulnf8fL2^1YenomKVa03iEDKp9Sx|d4sTvv;_0g%Km7OwW;EiTef=h{UuxR# zfA25Eqr=bG_{v-S&wubOwyxgbNB8zQ7)`6>;R2xxdXtn(yVrUBYuE8@ZvT(}{Zn!9 z@&Px#^De*lwb$)IKNY>gQWiOD>rIli;mgvx?0Y50(&1=rUb?4Qo) zjZ&19bVn&dI6LQ)e(HcwsTj;kC;9RHO5);>;6O<(uQ#YiKA%17@$z)y&|_^_X~!4? zC!>PWPPi5N3}?BMNk#!yTAHl}WxvIg-wQVHMgg0&5d6o{g5kMV!qezj`;__ch81>-Z9=(vS-@%RN(Bte*pxfh~p9-sR_g3e3w z=?v9rxoa&fr7_e)#e3J+dGhR-<8eaNs4u$lofOW3G2~g{>|vEN?2y7Dtp-yt7$x+F zQ%YTMayFz>4>&tIVRm|iFa>8b!SO+f&^f*@sRatFGuBo*+*nr_BGT3+z8H@fPX^4A zf}+SMjQgBId6Y(w6%y&kSVD#wOiNG-j44rJ9T9aXWrU7AN<1VUvMwpC=B!Lew8u`c zL49)r*SA`u#G~*Ol$ze*lt&Lfr}XO7H?E?5#d!ZE=IoewW7|n7tznkt7;W&C;HUQw zSZl`w((w87Q@(m@i_v(--r<0i<%a9yP&JBDlO-8ODoSHG8Kg+1$hF(^h-&PEAS((2 zPvQAhzs^Di2!*Y3W~#AgZDprijdL!Dp3WI9*ZVpzelCu$c@g0(%FmsV4*Uh7=As^t}1L=*#0Db9`BV{Dz~j)}oa4q#MHJyn?O@ z2q_g(N|H21O2PH(uc4G=ytzr>E1KbKAy!!y7HJ*S@E##-49Wt8b1fg@EX@?$nu5P%SN0;=*DSM|=mYY7;HyaMk z4ML8GDbM!%2&2hIL-NU(APfncEs%;5?WpvMvo4DQqpCnC>1^+u>xh#>724VKmd0~> zWo7V`&qNC`p3In2>+?eh@VyGBtA25GbSVDz?>>?*&q`@kh~Ln*w|B;1P*Caut&)W{ z*jAjm0Q_1F>H8!`(VLd+y#6+Mmf@!*y=EVs&WNvGCT!HHMIj%*oN(_jA#i4U7>#S4roE5QaGISD&xw{H;hUk3Fc9ItZvfd!nC1yIoi)zG6OU^;;_!wVG zl&45_hB66jn=7OPm`w)@WKP%;YeAQlpL-SJ>Gd2x_&>Czgd7xMAFeZKMLCA!0eyPqGh z)M*gKf@I=xwD*{8uO&n|1?y0?@!*V3tI2Y^#_`CenR!E@|5ZqggDvG=w$9S}Ou;c>DS?51yY9`I6s%?=t;SLTL=|-dyAA zMw7Kx#AnY=$jSn#EoPdqR@>pyo!9t3|F182`uM+abGspQS>ylx#g9npFKO?-%l1lx z`!7e7S%$EFh0cl#+C`ka@xsj{P_9ss3*io>)-s(rL!d zrBzC8k+DY}MVuty*^sT>t9bd8BuR+d9-l^fz0uGKxh{&%{ zSyO4_J%khtlahQeMU)wFgA1}NH>bEcRxCg&TOqo_Ua(phEc(vo5~MkMz8g2Do>ak9wEJe+SV3Y zRCcvU{7^0Aw-w=oREn_C_%$gO7Z@WcA*jVrt1UihDdJe8^wir)Sj;CGb_PeGk0*%(_(tz?nKwcWk(r|P(=I!gNEY*GL^^l$Q79ZYw z#`WzsJ8MlIK6py0!BYWJSf>=g=Zj~jE~g_)G5QM>PSz@ka2@lNPhC*3?p0tsr&$xkMumpluC*9 zm&p64D0N7%xPY6oq<4f#2 zAktVCvObr2Qvrr{?gM&0-mw)ESnVO^Zh7+{8M&~9K6eBY)?lrmK$54<(xV!pE`zA* zpGqeqWawV^%j2JRd|80}cMf5VDRr(3>wM!K=b#t9+)_#c-y;k>ili@coso_P*ucY- zE;)UXG|QY0*Vqd&tJWGmfABzj^vPXi(h#%+4X zryL(1VYOj*cb(g-8+`on1G3qWbUYzU4cT$Vpci44PiJL~JFng5?5N=Moe4qYrSMBmD}%^!<}&Xu8-qST8p z$ay%Hqlyit%+Y1;HV&r5Ie-+HvOpM1ktNt7brYr))arF4f}+R?0-r3)iQ~vQtw}|h z7cLJ*xrr|b0w&Wbp%A25PEk5m&htE`lPS-?cnI}v{2=6`Pan|`8NPy-vmtMP@NMFD z2jSOH)=m8NMoUPYVzLoJ7f1}!7MNlzX5+3MP7(^QZTr42p6~5Z_bhK+Ut^qGrdO7^ zvDG5-6%Swbs5K04U0>rlIe+)Sax^@lH(jQF=TGUz0srZvGnV&#RxV$q(ToxKKKa=x zYN^iVa+7ip@Zh+_=#t6udn|qJeTKD=PmfCq5%BKKRSw3MA3r!?ILX<)yh@`UQm=(< ztaaQXt3eAzf1L7{`$Jxy&F~lS6_o_VeJ?A`{+!8jdz$&rKo~>pOQOK%$$p>Zn$L8W z^TX#S+}>T|##V>Tc1#@kWQAcRg5zgL*diy8mT|vNnoPNQbqzJnKo2Np6E1CSQnt5= zH&;0BjY!jsS+9>DhSXM;-B_v$4pB*aM71e2^9`u$PIpX#5GW<+jZ*Sl^UpuH%*i0- z@&1tO>n&>QiefsX%%&7YNtx}Vf@PMswu!=+wZ;msUY$}JO)(oVIy+=}Wtq;>GBOOv z4Q#fWTwZVUe80~$GYk^LNk8GO-6gCw9CfF>I-O9jM;Cets&hR@?S;jrDa9tyG?X^g*=@x?Vd3m^!dAwp0NM&72@-LFO*6=%R z=XPZslP!yc>Cq8F1=Ke$p{0k_8qcdxeFR)^Npey;HxB0S&(6_oaV`^+)to<ysJ*$(XgH=5YWw?NzbQUjYVh%Ad(6@dPl7NSBLvouLBt4?V}(XoUDehG%D7^y z1QKUHVTCgyapnllkXs3b=P8UfKv`v(B#3l~S6d;I&VkMo5;GlQRRE2)YnT_#$RG*= ztW;>>fl^p0@aheu7clLfpc);#C`R}}wZCzNi>%J;V3KoftIf0hE@@VI&;8`?|FoQLShj{W33^{3d$_Q>VkT$#)GcMPd@MRtvf4( zlUUm`wJG&CA^A}Htby8 zwe{sqQIBKJ1`~Vb^0qK4;Y~CJ5!Rjagf$g<;Y=yJRQ7TF8MacNt+VapY5r1ByJMR;we1 zBZ@qCPET4>Z?@UG^&V%Y#U$6I;gnf2p|-q2u-fL{i!;LB)ONhF_^Em1p7c=N1MYv~6ECkZ^Xu%NPVkh+$tdH| z!I&re18#1&x%18MP?nnVETMmzu)I=Zy(962MXQj*SH~p%K5^iqh2qiuN9=B|(C#dA z)}IoX3>nney53=_=7E$P%p|{ja?IJ-dEY-d+b8fmlqbmw!{6LJ#26^F;jcd2r_hec zTJ#(&kTI(9QpqqxC4;Gq9PE4?2*FW*#%MHUW3|Q2%gekxopLfM*(oe1qm*BLwnrR= z+`PKNY%rpn&Sm;CDSDOa{yj3x=j8m8S7{@`nu+3aj_@3RMtW*K1^ zaO2uF-nez0U*3Pl)8{Yv-8;Lyefui+?%w5#Co`_^E_3t74Qh=JKe)Tc!6f6_S`DK$ zt*^xxD`?k!)|&yp`22_~8*R4Nn%sMG%-&gosCty<_mQ2W?Mh*gBuVCa1eAY{fLCmQ zHI}cxzRq{w-Dc1q^Z5A@dE4W(KVmu>WAhpH&=8aR<4Op*yo zXzI1lnM_onYX~O?QPMHld8s&h{0d!`v>QHwu#j1d(S$-S@+G7J#+fLjk8WPWni8W0 z)|BX^bPh-Ls46m?C-;1l|Cm|hM6zVaTqyvb*;My?o;&ecg}Y}Ybu0ZP-Ho!E(w$*=^xW+M$~I{jt}=KvI1Gz(-z5;dTWKikIC`^0|d((2&sr` zb@I|BsyAYv$#9BSYal((6<8Hp6f|1oqcK+Nswl5kN8=1ugoP*!*gF~V@?=b=ONzqq zaDV359BZjZBXp7DTSGHaeD?GZQRF1OecG|G>q|}HnUr)qq9}55ZJ8zoB5Y&B4q<1N z@4T@_J{@!K{u8wDXxbT9uWs|=`2dr}ymh&SlF+F6bYhQWmeFZ9NV0-Ssw<0UcRf8* zV22Y_qlJ;GV!7Nr8hYSmGlDQ?Jg;l#JzLrVt@T)urKNjLF-J}<*vjop2{M>0fHY7IhF8%VJTI7+jeFsj*WyO%|vEGz9go+pXp(D|^t zd}Z9QpBvm(lXZn^?Z14%$9L}|q=(j4Ob53qL_|6rF3 zD52@dF>h|K*~#(}e~}DW*Qw7O1d9Wv%R zUYwK8To+v#qF}1Rp-gkK@z^yy)@v1Idyak>bH3m$mVb*wYR~l$^S>M=E#c}$i;Ygm zlY;>b9|ANOja5D%T*JBqCB15)6$ms^d3L#76K1R!TLad)xcI*B-rHOoZE>55LgV{B z%5z9kS>z62OEd029da`2Q(8l#9jm<0H1ag`LF z<0%hoJsurQd3ro?vL*!D3h+Emr<#+)6I41w`HDQxkwOr)>LlY4Kl;ftK5n+KGN8~J z8ZCmgIzN5XbMh!5(6+j3JRe~p)0U)SfaVF&!n!8fOuLPc^R_=f1XNAJEQ-y!RjIZ1 zoUWIU6qa9p(PJ`AS?;E6E!PQrg+=l4<1W@3_PYt5DtK@>qt{Iq_Pw*w2=p4={*=+- z3BBVIPtO>ShCDyh6kdzIFS!2ZI&l;bHXB5dzeu4zzh5rgI~NKQ7Lra&sV$Az=lxr& zeE9h(Ke>NQAO(%s$F~_9HO-Qm@U>g(w$W@c9{0uSl4Lc`X^MoX=&{q>AxI7g@+fpbv&MiQI)Gp_LIxh9)^s8VYcYb#NlLSS*ymSXi4ul1%{V?fbdEVXN8}?yn-D00 z@N0O!UuE;S@HQbOp66kU5viFH1_7b3uwLwXrsjL&Du)A{rEj3eARv$~WL7G$&fgZH zJUriDSg_`^J~mjx6a{4=(0S=(qgjR*`R*Dy?^dkx7MtqQSn@PSh$_27&ZSgUsNGze zgvASd!dBB|fm8s9Q=2$6Rtm>LR|pBx^PD_Yy3b|oyud!sVYnz$k)CpHii_8DK#Y>O z;^VYSyu6CnS*lXeaXoEi#`NeIBYfhGEsXRW8&`dfc^1jsrD`sTnoC--IE(c~e~?{B zPJs&XcXPb0sP4TOjL+Xu~Pr5UXxwh( z@suP8J$L`+dcl^JrB=hqe|h|mA72(Azu^!Z!Xgt zOjurD!umCWhkc4nxJ9<|Q+N95qVfxe@igO?pFC&OKM|8@YDYzlgKolq{Qlpte>$X) z5&zSl-DLmZ6|?R>p0MP-mw4HfR}Xr`^%}`+!kb_D3R}$%PlrcBOnU^8#CdOM!oa66 zf|?iL`98BGbx4`=2t8-Xt96M$*yF=f?tSztq%7_3^_wE9HLF07YX5Hy%8%IC-W8wR zdu)Gt_bK~*iyt?Tjcwlg%2(OGev_Yl_?WZa6mWV}Ed*M~1#-Pe`kl*X+z%IfGgE4G zQ6fFFkjq`v8!sqW&Vjo5;#tkq3$zj3#@1N)(cJ^A(PV|@)2NGQG=5wo8IM6oT5B69 zB^jOe@T|ZKe2Qs`Dm4cOCy?|OSt6=JT1;8FY*qT|Jk1bNVoZrK2G3IzX~rzcoi(T) zk>yTnZLAB69E~P?a`yp+*W~)uO->I^?Z;;mQRX=_Tf2*6$y?B=!K-1Pz!RV(*7p#hkCYN6E3f{ls1(x2SmT`8<{O~u zylUs&~UW$WFn+N>eTX zEH@sUwdOo&x>~%%xmBm2g8eG@1}OxE5gZRQl#;wW%h)?j7mR07YPX5>eF_VwV~q_P z7&RkLGYEZJofbECRygbqDYJwupP^O^dEgV@#*t^6$odmK(_M& zWIomxVSm-ntaXXty3{BEzO<;KpqTVYeT!bw6h+F$r5b@UA_z2TQz2x6$%jlwU38g| zBr}?qYJByrOL$74q_fmD0(9wg_0n@= zOi6|3`GjGJ71B8^SpzCY`H^E_jfW7Rq8eTpBR#K@%+0wC;qpnUT#K+)L#Xqfi#d>j z5Q}14NQv|Xq3s#P?Xl>3p3}Z36q%2DO(1ild8|sZQ=%OH> z%m`ae@ZAPa%JZ>qjitmXbaYmNKBwk*l3Y$WA-_)_rZl@4NX!2aj=u_%lR z*uK2O#?>8O-)wPsHljBz2#buXQOff2620Riib)Sijf0a3HcOmLFHguP87HG2%2UJ= z$R|iC$V)+HA&w&eG9?*J3;gaep+4mL>g(7z;L7f6>>m&L>4&cneuNa7Jefh7AnK8m zWC`Jz2V9<0;7Pvu_6|!y$=S&%6I*gnmq_2|#*GbH%^HQ3NOgn3XvXGp0|Sg#8{B;D z5^)^ygI_#mmdsdLs`KE<5k;Z7wAtaoi$S$U+C>J5lxE?QIq!wBMiY91o%K48_D&fL zXP7KyV||O8Z)~%*T;uWKh`oa@T07h9u+?OmTXJpKU2Cx065RJP-q_vZ%J!P*on}^- zxv*Lj*J9CFTIIAmw2_oN>G?d|JK>G1Yiw_JxVjqC2t9he32)xq=JHyD{v=^*txX(y zyf~Y=b=_z*_FRBf0gIUtD8Gi)8f8u8^6i+itbl>=D9gh2-HLf(?)DBvkuynsyg0^W zPF|03g)%^449Yn9^_ z`z02?Y&Ib%~(AF>+jfmUxX4qX9pk6|Al-^UlpR zmg)}qJ2_k9?!7$(1{o&^I}^K?*O{Fej$e%tQj%r~B1_T6ElR>#l0;XD>UObNa1FdJ zEkqV2$;?t{*AXLdw11->(OFyNXpp;F`Kcm+~DQej3^3t>y0Zsw3?OmCA8-;OjGBeW-UfamvC*J?XfTxBUvQrn(F)s zVKCab&2c3=(?(O~Zi6hOLdcFQE&==iNU`}0JrWet8S&CGLA~J|pWNkHIHD{>C>NN4 z`A_E=1M@<2p55YmvXZn3=R73@r7@LexatY0{&x3(d%O(fV#rCL8GBVhI!B--WzZlC zJScOtv5Zp9wJU2(&t|AF;H^8av-k3V-lSxy)#k>|3O~BL$4aNh&RU(1pL7>FAg0nK z&n;Fj79Q^HNsQ54+h}rYyG<>S+}i07DHx6FJp6RT@zEJ+;M4DQVK+tyYxCKe`;?-| zS+CFOS&wmI_~hPwR-3Q0z0pFL3D}%cNAyM$jt>tgiwMt)@vY&sKciU-xVqlN^Ar|A zcW4P)HJZ&jQVI&+BNf$xU1+k(Y(q$aRo>$66UI4V6={aeb5syuf!}}kD%Z9eeD+|E z?X6{&+6_()4zapCS4nD%w%TC@#!!?ck&Ot0fLs@x+iYsevRFu6=GRx3rMtEl3sK?5 zOR39+eA5Po!1wV2-z946600oQSjw`*SSQc&g1|Y>EqcPLM%)V-8%jVB`HsyJE`Oua zkRUEHuk-VBL5Al-CeKsC=VNtVbT1Ob=Y{_T21E!J3^COhwqicc9gC_2=uw~9$uZ&5 z8h)pPu8I#OSTG;jN@|;%Smn8bZ80_lh>F3T->h>rRrS4)5-$oJm@xlL)jeb@CWp#K z7@cFw9O*mDT3y}Su4r;eFus(e$&BX@pY!guD|D7Rl)~fE_6AR1zM`8>i37=dudUEA zF@b6E{;f^+U&Kr&EA&Sb{O}SxJKyDd-~T?p{K?-E1^(jwpJ#*28>p-KRvUsK=Fk54 zpL6}@P40g5AzNz!tE($~`&&2o^ucrXpGrpdTST7aN1r_6=4-qB z;n%P6Xur?Xmp$hWWt@!56ggQ^VDbbhUG8$0CSqP}m1PdLBuSH9vzJ6j!S~T zG@;v5EL6=;dEL{UI4N{YN>GIc@Bz5+QP+7i=<<1ZUQ{t3sI z1;}qWcG;yY3q6^Rb?kfoJUq&v5C-RpB_(TXYXm{WFMsu^HAu1l@)@yb__zQ1kJ;MZ zLYGzg#)AETb2`9HX5D^Y9Q6z8?KNgL<7B3sm1{9iUMl4)iloUjwKuLvBAz15dI)!qZO~436Yk8d!FnwX1-C!xu8i%0c&}k_J ze$*gtbl8kmI3Ayp_Gg5FLK{P&VfVGm40Hg#PwvIoQXnvkJAcuqAq1h42sxKxS&Bk~ z1TR#74+)$v^!&Y_xp~UYzhBVfFkhtS*RUBX>b~IcWWpd)OlAd9J>qxY+oqkoLXOU` zM$=hYN8Z`u=Rd!X$tTFt@Z#AERCu=?-U{c1Qfn?|zjs%P1`bzRyp8dLPOHi>frT zf^0ma%yXhvgCKO$69tr&eXuSx<#d7xBSfjW-0}GB_ipg)=`)T`dwlzwy9@?Xp1nNb zD_?ty)1yNUpFiQw%_}@P9Mj%vv%I~<_kQ-Aq|kUuEmCtA?7)S4b{?o^^aZ;`+`anF zwH4=MUzEQemp`(W(c0 z@}$Sh(-~$qWi*-b^Usg?;oT$W@`B{a!)Hvj$M3Bz@vBD%eD>^&Z++zohesoHwJuhg zLO1f}1$Fg)7Zpim5jma}>>Ukxd$+@-PRN4?6F&R+b7s>7Pb%u|HU9SQE24Ux_usfI zLg4^}Y1!s)K6}jP#|f(&m-uhL`Z+d;?VtU@w`oX(6gjD`^Wn=Ao=qfPeTkx%VvL|D zN^V_VV>QglCu3%rCJQX}DB$*Pn=p>>>rKwGfM-V|uC6yY=_ed^r(EAzV*hkP;7Q)S zd5I?n10KH|kWUhdWJYay8L0%l(TvM$F`cCbMV>Pmjhu`JC&kMP$M^^V+Gqklzz-s{ zHI!N}Hr)uZaJ#X_lIIzI5I9C-!K{_8urQ{&=M6?%^4x{Z`o2%0HCCTX^uQo(?iz>j z=QBEsU(dmes$bAn5+qr@XSl&c3+!prm!h$LT3yX9d60q11D?M-XMk4!J zymdGF z!&dP0pvUaxF?)M^Jbv_0L`)fW&ukFag*BFbZ$Od>l9}eT5R9iDXv3oyC-|O|PCo6H zPC{*ciV@6CkLb=y{Lb=X9R?>;wYjD&6FkpH_z@O?=Sgf)Iy+q{T+63*MTIBb=QO$k zrA$?vE8!f&q;lY@HIzk;u$Cx@07;qYMRAOhi?v5$t>+2Nm&ZT)__6@`4ae21*5-vN zjJ2geVRVWvGL-V2(?zu~93368va-h8Z@o#Y)v}|>9Xz4M>e`0W=n7FSG?i3P%$xLN zl@2bsc4f!5>opNXO~%tHtE&xC9S}r{Sz-zOkgvY;I#;h>rawx#|LG%M?d`F)zQVh2 z-*$*fQE(h9j$b_`6mWgJ30_DT`Mhyshrj&m1HL#orZ-Nw_pDFpuk!pPVUUlYbB&<2 zMm|ZwmPqM2nz6FtLrAo-Btn4}M4rU=m6Jb6Fld4(L?Rq&C7k7=RK7q+TNJk16gmeL z<+&R;iUQ0aXKvcJwXs4i3J4-W?anq)Jw|IwJ5Ut5V3HNioy+rCX~u+c%rq;>^P-ZD z2m;?@l$3n(xJz2-3vC~^+FYJrW0$B~A@^Kd6WwE-4phz`j42HVXA^u+GEFsq{n0)p zmOEEhX_Z|r`vd;PAH8L*)#8_*?b&+R5_?Z$jt+Wwe!z`uuaR^mubzG3EGd1D)s`a9 z1CELmPYPO%m@G|+;}EcfzDF&NNRuhGT7)$Q-w%kwfLW3trK9mXD{I_%>l^m@SuTh= zJl;DIy}i$oHen`O_*ZVA^?-C%&{$VAYd$}@JK*?i%IlY#48|EBe)@vdr6!|MirjPy z*3GRYP7WTC_PT_Dhw*)adZUv67GwI9&Ov$aC z4*%=F`3@g_y3C_TPx#k=^d4WlIOOvuA%F7S+kE(mW^mcFfBJ{NEB?a|KH|@R`jlZQ z5p$OuJGbRLmzA6+Dm$@9o|WWDh97!_vD;`0E7)j# zC55V^{2F;W0$rlwnw3$D+EO8mXu{r@Fo;-g#`O0O_~<7;XQ?Kb4hIanXC%HyExk-q zTAHmkm)`n--Ss+G)*Gz0BN{c2H!gPwrKQshsHuWCcAA`=j_F4cG7McBytMq{!2yq7 zoY0CCCuaj<-*S7W?EnWPo>B-~R7kqZaM``KOS`kgs+Ih$7&xI5M zrE_M-Cuk$6Z*F1d8u|JBIcEuQO}gL^;`zsy^RWv^p{i>rE}XYHd+CsBDFxYdjIxGW zz0PzpK~Jan%??*DH5g2Crb$7);iF6A`WK{RmSreYkWR-W(<#2q34IqDcQ7n4XJh`C zZ(rfJ-oMS(&Mwp8DJLf4`{;BgCPd`DQ}X_l((|!e6SO;oE6Zr<5iGADr6B2cT@Z4!jZq%LTJq5ll_zw9 zf}qe`*}O`l-J-~6qakMaf=Ll@_B=q=marn^)}>XhUB5~Y*Xfo8lW>Z^91yI%#@dxFmaYqwAMnK& zFR(&c|Ikqeirld$`SOa0;iIamp8waHo zrgXAB*bpb@NeYP@@6mD{TxHlHv}G-*~K z0!1zMn3RSWea+L;oM*54!yi*zZngMUv2D+`hKVa?>EBvb*b{ID3)O2raTmu-4dT z&qqQfU57~F^sH7JqCgS`ipg|F7zN~cL8DP4OEbzmLHnSKl1`_^csgU2%zjN~WUZy& zJ>|2HenEWcO|D$O&PN|6{P3fPU~<0s+jn?veG~a;Mq_1(sh0Ex3BUD~%M7PEH+MQb z-|zD1#Tl2@Tim>|%*S`1bM49+-TshI?>#{&h4y3Ob+-vIS`#*Fc(n+noIJ1-dt6(M z8T9+SwppWH_nD?8NJ%;MIX&$%I6Jk>dh9>BE2hJDIN5*7!IKBr-+qVQ;U1&WKqTV{ zgF&Cqzj#6VVnls?8!w2Qz4LqluMpy2)4Ure`6_Z3Fc(B&wPDxH(wwJ9Qyv{9wDJHI zfYmc>Hgz8Fo`;HB2!W5F1*S;7p%EFI(5+W#MWZx&-|lAh;1 z5%F(lKPUICvi7B`yLz9c$>9t&Gh8G}6e$6MHWRXJz=X{U-{^)n@`XV_7lh~qkPO3u zNmBqRks?iUNQujkoZ-y$O!stGcUM=}o|#pdm3eYI`#Jv>5x$83WLDE0g1qklx~q^U zGwWYs`M&pizxPG>A;WP>JQ^|S^oat=_HKvglav=PE%4?C+l=B2jAcBD$*mKs(36Bp zPWQ1D}4euMhVqW$XEz9lv`1}>P90cIMY%2Q>h>0C4gT~MjQ zfK50r5i>=jpWTmefuT^6XI}1!^zJkng;RRoGe7ETGA9YiGrdkH)8v$zc#@_F;Y{v& z9me|y1oaldObcxtsx6hm%M(WJJ+u*&7FWRcPp|#-oJ9V)B!VeH@|h~Nv0!m)*Gw}M zo~=&1`7es9v^K{1(I}rp!z*ibK6Pc5y`wSrc6!V-OFY;*Mr%X8TBRHYOhyA63+!Y# z6cHnl#Y2>65&9l+Q0DIDE_H9h!-pH}Za=}~F^h8zN@l>gcjOFx3#8nWs;G#|qPJ#h zTxp93Xn6eaF2r4SA3dPGb(hxsl1Qz`oz1SzlT=t^(AE^<{qEcs)|m(!Gyx#3B}rn= zug=g`srWBnxyg6#?Gsd*MC+gB8+VTQXlEcyQ0IqUDlsoSLSI0hv9K`5#fxXTa(;o| z_}y=DbkOCMSFW-=U!xRwEVRn3E!KFr(=XKD1SU(#(~OzfCY4Hw@i?Z`Xkqf4r&~K5 z>>bi-HaK^2jYc)1tSpnsn7a>mC{-$a{>BR03i2$cQt}Br#cZ?8wbhnQ;(1K|oXEyQ zu-b;DvJld@7iKP@JSDnD(Cg}9IFBqRBAm3x$w^lg+ZmC@PQX@Pc>G^n4 zAf>`u%b?#SNhX{*djSNmOJbCcZ(#HS*AOJ~3K~%DbFwUTEl%!Psl-IA! zx)DTCp;-k$2w)guC`Y}=oa#h8v%(CCji0P1JnoJA!4#osg zRV0%>T5FV&_|nonK44@u7cQKmT8@flPl1r0Q(*D~5Qde-d2014zUOh~%o3gbEq1qa zQLi^qek7Fdky{YbQucky=V!Q3>ala{LpB~f zqSNak1k`F(78e#-yKt2iuf<+IA_@eX?Fq-Dgl4@=+Ut>}iZBd5{$i&mx0uo-`2V5J zqEOj5btx{)in5F>o*+Fzt)jTGQsHQ4hbMP?y!h#}cCXW=vE30_mhoVxPbZn-xHmxt zWo({`xw#g3KV^S(>>5+8z{&tC3{ey^nWT)zF~&j^g-9Vt(~RC=jOROJv?R?K4u^mX zt}M>baCQA0&4qPwd*d-rcXoLGc9+CLxmF^{a^8D*z~^6GC+Uv3 zw{^(;TphhL;MQh`vWa=;oqJTvA%}-ub`K|rs7`5N9>Rz;$q+)|1s=*6r(~1n>~1~f zE9sC&2V=Y-#Ckr$cT&_UEU~$>!OahDWAll)b@vflPqx|LKjiMc2Rz-|we7uKv9Yo%&c% zE(N6hef;AGtX48wwGx9=@#LUP-dx8ItB5kr+5YGu7b_Fy8$LE0J1Ry{asj4|`LI1= z7@T#~pg1NTju6!{=T>H^R6;hk9VKtB7V>BBwyDoF&{@XXe2wd8X9>$Cv^_fABc72l z71Bw!if88QbP^k5se~Tu^JU(BYlF@p=iLvsc1R)#xcjc`>fX_YJQpFQJ>Ck zkKyqlN-DI5UVEEKr-Lo8pp?&88}4l%Bc-HX4LQ5mpnW*txHsYZUp>$E!I17aLn?t3 z_GAsN%++}P@+^A?9egZU%~2{4ssM2eZZ8I8t{Lo|ZgIn4fKN?cBUAGvXVb6;9e)pwwx?5_vvT;k@M;pR1SW#M|EyWND1`T?It> zKE73_2|=NZXpJtC0&w!qMbcbILQiF6DTFP=G^u!&PiURL$0=XxGzkGdwqKq6NI@gZ zjRUuoI;Cq(QT!?OOGrsR>=W;|3F=M!xj70uD3m85PZ;j*q79UnmJvZfZuIHDUHn(r zxiOW|m567O4{?$l6)?QJ=7LE(HBg-P=VkV$axWMyg%T$_+%&lFe zy}OMdN7k1KE1M@(9U%n1?-x|746XA*!q;<6@z(WElm6M~ufWm0?&j(gnP2A9t*P>(!bczturS}`^(#ws#tB)Ho>c7I{^I`3b&ju~)hN*! zX9TSUtTtqwU2eQ_jUWnWKiy;OX>>AXe{Yv445-yBSgpylCRaY5lI-1?@K6~MdKPV* zs#azZLMWmr6w>CLIeV5P)8N}5J|(PH=^h-C7(u04a}6V+Iu9a!E4RqDT!CD zA^HRINsRCUYM$lGubpE)=wXJN_@OVhH;m2m)HWJ*(QJ&xQjl`7W!ZahK%C`nZ?TSs zITiZI^OTC|iT(ZG4h|e2?L8IeVJS7?gF0s`NtFXoy2Y9FnB)gk{n{ zAj@|-+Ivb?5~Sy6frVnT7ECEvc6tI79AvEFz4zbegZJO36qOifn#Hrvk$Fve-7e&U z5T)-sN%q^~PzwGh;JMUU+1YTGYSVK7w+}qy+74nmR|5d^;Bu!#e zffh+&3)I-Txf-3KlxOD_7R08=DTkJ*GAq2GTqwARlj91%go=Fpn!#5YnH3~i#;aEr z`02m(9NEr${D)ur4f|kgPsF)%9(Q{B8Ny^-y>OEs`k^oLg^QP%-Ounn#rEz1ti>yr zP$x~~Cy)GeScejdX%IU->`%V|osuXbCzoooq|vZ>C@>As8y>7=^=d>_9tXXN~2LG z(Uu@8qld?&S;90FkW$g_^$BMrF=f7U^C6%6{2VLGbKrU0+Bo97506~WLYg76l&fc! z$#X+zm{186D-zBx*J+k~_O_m|FyCNxsYQ}ytX(+E&Jbh}5vLhC*G10<#XNS|K&Llm zZl=uh7njjUg2?CI<`JVf!;^|kTXv5IVl+6W*X{7MeaLaQ&!FGu&c=?|*x6&ZeZalP zJ7RD93E42CHnUFms6)K>l+w~Fc##Y2ieP6N+)TOgQc1#6(HJZR7nYkG_a<23q)ojj zBpn>GG`hn-`0`o&WZ$Oa9#?O?D()XBe)-R~=y?~N40M(-<7fQSFP^oZe(9okc=xuw z_t7nT{>q}baOtw>cl-SBzy1#ICNTg}Iiggr5GcvZ*Vox>kNM6=ZJHII=htTtLUMF8 zq~DJ*#&FOXvg~>qS_#!5)EUqU;QEDG z{HTg3&tlRs*bxXz7zRv|jIaFh+bHRwJipjy6d69D9~7~_OYBOe3J)J2@UQ>vuLz7G zB?6H#jI#nrai*n02!bFW(T1=5;hWri?+yq12MDP!D6I65%10P+(o`-)(Tj$o5-BAx z)9S0>Yc5zft#7eI`Z0#B!m_V>|7y2L*SPAe~e0cGrC+vYRZc`}}%O^T0w4=48y zE@`qt;#JCcQ3;ZfOA39Dhr0u28jBqEV&1&9O|4oYH#vXAGWhQ?1vigv-pdX4%=^Avu168SXOMs4`#5sCilO>`&#qJqc-&7u9O; ztvC_euoy@?q9z-t?3hP)`gD%hXf^62!y~NDnWR2KIspdh`55JZyJ-)QEh<*ZYWBJl zW=kIb{XhHyX0XfV);3@Jvpbw!U*SjIc+NiB?TD0=$vEZqQO^O7l?s3KXYbRjg{&+s zFgIIc*UPzicY}B|rZzXr(V(C>7ezxAg!q*TgH8{>6d}VBX=X79vQiUeEQ3kTlSfik23PCpxqjc%~F5uvv2;=&;8sEpNzlq_#^@O zo?{auL@tChQhFzcinWD=opngLv6e}klFJgJ6k?(b6Ii4l6^PRmcA8QJE!MhZ#1u%> zwQEt95pcMkJY&A}oap&-2*ohy3A( zJ>tojo?OO@Ykc*+Z84Z+c%?F5zF6bkx9+lkaKJ*%x0Cimk?e1<_i#wunPY3G&2ull zY-`ndVUZ5u4NKfRFdUj58;3qOE-kwIF&gEU9RJhi!K3bh(8J#b7vK`(P|m zZL!_~R`||A-CFWoTP-}XKZMHC8PvfsV&bGT*O~!;`?WLH?A{W;^ozg5qo*ChN*xt= zR01C%CF9YAEKB+5@iE80{#$(UbFbM~U;Ba>Pcoz~lW9Xxju3H7nj4g-5Loiupp--v zD3HaTm>R;gwEhewp!k|YyDgO<;Nto`y;hYho z#S;MU#8lqx08Tt3Urhi&3f!gw@7g#m=#Y4BhLD)1>SFY)q= zX9<<&us5Mq_BgOZK67K8qfVdB$m6rGzs#L`cUfMTb1{s_fea@L7QuzzR0~NeeT@4N4&pFX>l3thfJA`QaC>OiGq-HGzV>*deIx#m$D8s)>@CO`GVmsp<>=HL7uzt6#8hrc}@+kf;={)y}j$Nb8B``DSY7~$NC=UWxB zc))M|=I`*%&0Ac#`jPz~f99Wy`Bnul>oM5f!CYBE=?pXMlUPGMUZ51!n4N22jb@w~ zN|DdYmsZe1@%7s~&d^c|mKT}?o@A0wX)FRg8jv6E<6+6heUz|xGmEZS-8vb{NC|YB z@qI6yq4l}T>>mxB%&~RqMCDNN<6r(PXBGnD!8SS_ScDK-Z*lR=8lU^jtGsu2lh?1U z@xs+LbbNrcW318m7HUyhEX~hyf2fgOfX+ue-Rp2>b(V84zD{BVX)ht#9nx$?%r2Cm z@B`Xx4>{C@Fcg)#m=jQ`cba*NEoUq28obFVh>l!1Z+BkS9QkIRP*z z?s3{kUepk*aUe*MJbz5O+Wo@mhBV!wPRFyo9JpXM&kfZ;^5dU9%V9s}ci-B^SVxhX zR#ZGGF@vsCyQ((vXXl*1l65{uN~etXcFB#Pva|x8e^RZd0FS2ht|^Fea*blDRA^5? ziD#wFPm+~qX@%2Dk1ZQX8IIYjAcpq#n%i!Cs$S5SSjhWuL13ip$FdwFp$NLj{Nxtn$jWAxsQFp}Vc3V7n(j}Pj7}^rMM=_&8 zpHAm7eruM=<`Lza516ev%IVYNF%P$osIHzT5dli^%=3lP%nZXg=4fY+`pPoG4`DLq zwF`4xU%yHuW6m@@X483l@7+6M(%q#}EjvLRDL@#Ea=*{LYiH=`VjAr#SvCU=d7Pqv zSI^Je7r$^#{LSyPJlN^*+rPI@tPN;`rxZ5NSZI}b`yX||VDe5x4F4x-@kcNgrQHW1#_!c$h-!l;Q&wh>^$A)7k}k<`Qb0VK_1lE zc(jcYmUuWs>XesXe~rO7VQ+g6I~(IKG%?Myv=&2JwGyMmFf&u*#@V`k>HLEDt*p&| zy!$4feg1R2`l;7>`~AB_b8BMrFh_(np@e0C_KNBzVeNGv~`0-)*N~(oNAC2LTD7NR*N4vS4U@i zsBBCq3_tSPd764p{Nlg=Wu6=isWxVW(V8?#$kK!$2&q;pq^Xa!g1ydw|L_~X$4}49 z@|klt$Qdz|5|d}F%vESKD(oJOP*N~IQ>J}9W<1G@1JXW2l|JQUpYWNPHYOJhtwQp_ zlOBhi5xudaStR8arL!|w3_E$wlgA?j22`Es%&bE&O^(z#8kh{*MAk#foH)%nQHl|# z!F)DJvBLQfIHc1xI=gF~I=nloNNy||LC~CsU=AT*m>4#9j(NUOr&cTTt=s!dv_q*> z7-B<7DGWHj+T_eii&rkTIC#3x{jCnK)Ea~y#PNhn7gkWE5;wPoSOIC4k)=5*3{HAb z0IaYD$|vYd5^5ey;+*$C+(t}>%vS{W-@QY6_=r|ym@NtNG^QE|d=hjvq7_){>#@k= zF=drA?6lducbDgHyug*!CQqJJNXHW@_YZ~>-Hyq;)g|0n}Ko-q=z4X7nR77eCNS2f9H$KTwZVS%@4L| z)k}ndMB0q?r3P2mXDF3?&MY)|@BSfiqEVi5MrG1Mp5h5-u9q8w))ud*+F9$oU*3Iq z#0L-enXdl%wPn z0jB?quSKy5I{Kb00?{J*+B+Q6>rap-=L;{N;Y{7BGJXDy7w8OPu!f}jGRdfqvKhm{ zkSC9~iN^yxPoaYbnb!nW!Wd1Q)R0LZDYTm|609odJ6?zl>PS^XBT2I{HakM<1SKV< zazw#Q!pMNt^Ore)<8_SkSedD?cmDvPlv@K*7R8QdgKxLjPlI=39Dp?q-ls}LAL~Jz zR#f0LfdBJDx=Q>>(jo*BxU$xyKNwL`l1oc9?(Yr}zN6kLA<%;Xqx}Pds-s<5;R0+a zrw!+AG9#!gu7dBKP*$ebHeGVlYn!qIEv|8Yx|dEX{U;6a#V5}uR$}@;V;xi3fW_h>?Y<8|Ump9>exaqZeQ{@{EX$KCCt5xpsaq zT62D-#fvwd<7?jLcbpQx5q7MB>dcNp&NQl49&BsBm0Z(QW_H`e+3H@?CB!4WV2&Cl|i z@hvYk|fki9$7r(n>RP?+{~<4ouA>Ju=I8Al0fM(q|9%B?E_xB(4c#K$Rx?> zb~=oEM||p~YxYNe@H1|1*<1(=I?Jr*c__~lC)9UiiloU2>MAKwo_o(y3Y6z)+frBz z2#d5~;1l{vAS7v)qVrsMo)0v!2qu$wFv-mLFODQX8Q*Jsl7M`#aSk$r$#P?&$O8i= zi;1GZDMJ+-W24bR=Na$c`Uq4&dwY{=BsjCW#?p#2!YYdLC%^iHmy27lt(jS_z3?K< zM$>lsBQdkIj)>;Cwb|vUH(`Ehp5?U_26@0-tHhN{XSjEFgQxplzVg*~XfCayg9-yv zrF7;BdE~R*vt)4xVGejcv&hV_ySXJUw{j#Ixpl@o+3*;$0hkO_hz)CG7F4Bzs?VbH z92Lbpj#KX4-XqBs{~#=p=9%!rh*nr5GYX`%)+!JPD}15+5(8VI=Pg=WZVKrISm_sm zYeAPO2lz^o4|)vRJItx8_R36+U;Fp}Sv=Z4M1?hyG$Bh2NaXJ!hdGFzo$bt~8LsG8vDlH(PW&9p>lfIPP>gckUb;n_E(UURh zWJ0Y`#pF3TlFjyznKK@fzUFazh*A=w03j8A=y8I*io(5HSS*HacZ`W7r9kn@^JjRx zbIilX``o?xHs#TMe&JvLJcGfI$D14cum8(0u-o2e=jkp#_jCWVxc6X#;c&>m{Ga|M zAKiPz!IKW}zjL1T=U-!Z+@Uo;$9Onm+}@=$zliZm#bF31kwa0)G8mM#lmm}UO5!9Z z^;|Wn90mBEViM;R7SX~A zl*`z};LpyX5L6o>#=>YE<0~i!id+UfIT&*8?3fFSRrY!@o)Qe=%psyhgS{1!pj2ku z?Gca0Naf*&CCmx!#vSg7hGD9)CZ;<|=uL7iuFr#z+<(#`M=(qU?Jjma%0)66VT~m! zS6E+HNTC^yCnQNu`)Ek#XoBYnGHq=dXJUS_WLxt~LLLoCh2_k}vwZpU*RXGI@y(C+ z@ollE6`nBDjsRy;dfJyG3RK*38cRh+SN zepsNqi1laC>5z2PM%LEJZ5I=kQ1v;)l)8aHmYWWpm+o3A=(9pPFD7eTRmsPKn8C7A z2p(ue;DhfWy#UXT=tULoJvl-f%bg96&cqOe0fi2DLFJSMeX4j<5@)1mw4?o(Q z-ybs^EY{V>(vD{+Pu5sOp~^G$s>roru^Dk?t;tv4+F-U8^4$3awvR@{+7NgWGwL&L zxAAKY!kM|EN5utWo=F++ACTpO($W$l3^2J%($rLf{@F^#)R6b|RQuT93!d2NyB4Bw zPjuB9VTK#De@iLYJC3=q+8~H3j8n_@!H_%$n`>Hr#((`&Kg|4m z6KyQbW`l)RiGxu_a5y9#jW8G#L?Z&XMtCU zYd9HOir!5<-4yun-X`0foZW*F3aUOKJj45 zw5w!VW4U?vDc9C#kj*uW24z;rj|YrZ!hT6s!U12UHhV81Ft|y#JJXE5y&o>~3%Jop1gri>vG6 z(=R{IqkA9P+wXr@C?yGfCpoRBRW4x>s!+rJ_p-9@#)q)2i*xqYi!{mV)G2YT<0j6=l9;c zjT&rWb%Gb}^Y{MlkJ>N(z#A5;$lo!C9N~3MVKk4S2%Wr zQc5W0Hn1$utuYqgb7iEdhMCTC0pJIL==KK5?s5ChpWJ)$luyQAYkZP`e6O(yNQvhu z0_BnE1gtFqEAF|axeotvu#@nsaI=6 z=jf1L=SZY!MypwM`;Z_pjZbcbU? zPcTU&)v{t`)+dfFwMvN>uAbrk#sQCZkKq1*N8=WyD_`Pvufphlk3rVtVs)O1=TTZY z3(Dzo=UStT#`+;L2q{@jxfbFpMO3&0OV7tsg5$$obmnySl^>AWfQgC7ypj+y!k_@} z6eY1R8IG6?2hR9U8_eK<#~U4Pe)I^x(!gkUAoxK*6h&lN&S*Tr+Oazr0Ofgvr819p z4%ym##PhFymaT(h^mu?YnzAQpl|A15@R;RR#Pet7c;}-w{Uk382RS+TDHKjln$Ay9 z9Tyf@Ak*$|QWe2Q8j~cDMl}EcAOJ~3K~x;>VJBlyie%UW&o8vz^(jJVHRud!1*SBQ zE@k9VgESeUqZ$JfGEst2xXRcMdD@d4Wlgld!bFCIei>^O{UoQXW-yI9k2^y~G_mCh z2_9JncolpcOQ@0+}L4f>yaG|hvM3`tDN7<*zLr$ zR?hO)yFd0}?(3LDo3bZ&q0jzay?NX`Jd*|fCXN*y&N5-kj*0fhm zP*9hqkK9_WpKbB{SG9SjGV{zC_ObJ9dXLZCn=S6+u2Y=^I!|F(m>Uh$&wg9h>$^4Br1 zWPiwZ+W`@NwSm`~C0br*X{O4##TNZIrQMy-pJc3EyF^PQWRnT^?>*-7*=2I;@$_(? z^6V_a3z(`wo7~CSR~Ax_?Mww^rUx$7^mzBI$y;vBx`oy^0jpNPbw zq{X;pSg`3#;h*H*Yo6yAW2jdveBskKKn48Dul_2T3|YJU27^p-?ffj`IAfCJu->3j zUZC;)muXc4{^aHpM&mI;NUD_zah@|<68ywJ{36|_=eYgWA9HxHN2OX}ZE1m-Mx89r zg#cl!wL&~oX)I`gg<#1EvN)Zu#_d~T3J7?fkCakq?dYu2UM<%Hqftr;-}h_~1Z4T+ zbTmnJ-~Z*G|3n4ruQ@(RK>o5}KuK$@PMn*rP^7tWsEiOuC7GXJzz-vP^S$@+gb|N6 zHYi5{Klu|s&ivvM#!iiEPN`T^c|~gsxi$>PiA{_Yl}ZyW4Fgj}nE;ee5Gfw-9P`yb z{Vt#R)N|CEb>9E*5tB*EY_rD7Y=uX6K1Ar8a55&ncZYqGF?a2%O^q+wso~sG9hpst z$|ZLDmaeH1wbr0oBMHisB9Hcdp9ed~=wXJD3ZZrkmyDVG}z`+dr-SuQTFyUiCkm5;O-E2xQ#&{xExA@QioaL^ME1_K6@ z4CVVLjiB))A&C=*Y@2CdF_p1()r)R#z=MZdTz&o}4))u`qY+t_ljfSYZ*SA6MIaQp zak97l*)mAgmx8Yb4_mT`5_)eiao291S(A=g(5A&2aDbT{iXy zRO(Ie>-a(v2oIqYLMb8(orxwlf|stJ<^4N5^m;?m;{!Zv@#-^Z2{@$^1d?1;u+3Fe zEkpPLItbibGR9SJC<5zec)ll1{KZppW=;~Je5B_w$#UL&e}_N`R;#wC7WqWw@<~!e5 zq|zXzMCS=>3k&?rfA^2XJ2zk9%9Tsv!g_;#zmFOB$=aaOW%A*eWN!yyGxVT_PMqYd z5gwySic%hzF03%q3i?V}}ZR%HvL7G3gJ*;3zd#FXN)}mRP zVMj`ay)HJHP#us#K|Z4Yqq3Vc=1TJihwY183e=Rcvk_p^e5Oi@CtbdU3(N zqZdvoSkuo00&AQR8`c&L;sCi@li&hzt+6^q;hf1Gwaa->7;O+nyM}ZxK!g=bJQ3-r zht)YJ9oIr};xcZHOF)VM&`g)M;Dk1Y6s~e9Tvfpeh4egx=ack>lhMU_4q*kkl4RyI zz{!LljWbkZ4r5Q9*FSEEO5x@`eI&(22@0jGXKEzRR6?eektrQ$`n4p@IX7RXSq=G< z_ja&Sk{ZjM#~nWR(kfez+dSE6Q))DcX6Mi@LqK>Er86e`ZL&;LUR*^)QE@%y^p$Z+ zEjvkkiw_N_-Hj(#E!?gki+eilADKSyLW16&{@iKR*%nH0(??^FLb7`}=J(!w$md^L zW0YtPJ0k+$M@R)y5+@nsNsQInYNbTGy^qOq(kx>z8sQ1cuYdJzzW!~&?*0*j(FBa9 zRSo&-pM8g?oA*d2F*?r+HeAsxZccqziWn6kC0Ua4>%aYn%q)J$=FTyhEKzN=SoqTq z>BkZqE@8Y9Dkv2N6StoT;d=P0C7(B5SSHO4-BH3M(FiG6o2xQg4S0XE%V3=H`e)Aa zWUs@w-uw_xI5}yPyS0DyY=irc4=DK&b2AG>p<=e|)9;N~U!7;RQO02T_S^T_*nLW4 zbqyVWxV=+P^!wN=(lxJqBS3_QS z;UYwJ*5^trHk~rZ@L-4U|I~HLtroco_~@ezhC?Sw?D`b)!i`vxCMj1huThD7hNGBl zJmH0_YYfK;4>#L1q(D`gV+vqF;0#He5=0>; z&yk)&rx{77gEzbAs2s|9X&7_rA`J#@3%VT6TR@l`QD5L|#|eA?;WjUvsS*Zr{NKO7 zDL!mV4oVlWegs9}(@TAR|E*o|;lq8>++tKi?A+YtkKW!uO2z%11dPNQORlwhMn>?# zy*97Ce38HTMuXcMN6ghr094BXORX{wn+@K-zsu#z>$H!DK;g`74N0$uO=6Uk#GPYG zVF_6Z99`*|UI77w%{sPG$7)Tj8u5)=JCvh<)x{Y;c+jRJ6GWVojRW#hgIooWTKCWg zn&fetQYpZvMLO1W3)Lu-R|!m=2RkWAmg7sspWfPMFdWk?Df;{SB*%R`&&LW?^x%k- zcPge-v1yaJE#5-Wpgp~QtVQGIge^i@r*7r~2Vpe2h*Yh0`-hdT)_{;$RY64_GO7^? zh0S8pBthpnLMag5X|+HU!E+HSNQxv!SSVyxkK3rJM8TD z@e3~~g!A~A_LRGzRpOOBM5T^40%hF3k|!}0okHk4#VM&y-=%T%Me*!cIGTS|Pio!56J4+}vQdla@St`o{ zs}vh)%A=9RYn_LdMdc|=D^+$MZ*yD@kojXK*%&V@A*4qTMtDKQu-`+Hqm*(zGctgZ zBD(N02dYj#i&5n|M_#~@1{rw>)ahP2O~Q+HV2mXSBy;u9&F4Jh;$oFB^cap}ws-cq zv{+|lZh>3x-C=F6$>MB{qlv~h4*YB%^tror$Ore@EHz8~(97%G-8x{qH{kx(0YCQn z>)g7%$$q=bg|qYAzrV?(4W-33GOJFigIK^Tp~_ACutX&ca7|KH7;VV%6tH;8yqf17WA`#YjDOqiKlBuNtMDJ6n1d?v~F97tJs zfFJ~(7oe2k#89+2+oYYEPAWX_wBjh`sehX){Dh`w*c1s>Qd&=`XG)fzjKAvmBmw!J z;~W4w*CHIAJ-WT07CTj2*kbCu4~F}FY3;L^EeN}-4Ec_;ys z-Vvk2A(;VbGD?1lxVy*3_8xmr$Kus5{0Q^2O&)D36q>vJr;Nr2G{Z8BOC{pWaN+zJ zx)a48{mDDUrjcQ@39g*_|FQRGPm(3)mEX_Z?-qMTMDCfjS9Nz4dIy?lfS>>n zLsAqq9HX`wnk2I^(}VsPJ;_Y6d6*Y!Of-qhh#V3afLIztZ`IXZ)z!6SW#yicv2S;A zcRl#Mk=5Wpn&ETbr?kqf%!nI)-M{ag^PL0W^vkC+#dkkCqVV-QKY~0^zY)y`PchH{3D9WiB$U-o!bFN>xgQJ)C*A629*tWAG+2c{eYF4kDZPgO=cXQ zjTjCUw=T80as2|HK0bEC^0UO7B(5LRFynb~FuOz`#iApP+%oXoGbn^=`mjPYdsPeU2n;ae-q1#LNwI(tMNhcMm zwFKa-59ZCkEC#qCP?B%GzDctZh~9Wky;0>SA3o;kvonGyaD|2t zq?#Ob$a8CKk=UIV%1VBYmB^BW*I&QHtxIjjlNp}xQ*O2S%fEd>hO^+c`L5xHltIX1 zklsB*uGloFa*cF2Vsd&)XzC!aF}ci zp#3&~_H~lFT|NjF`$67fk|i-N7btMG>w+aQ=s0z*YEfw+%{q6jvpJw6FiGa5El~)b zm&;<@=bgqe7cbYjwqB)H2|4b^jAxD&3j&|MRs8AqekQ!+1Yt66zIcPZ;~rV#BB^MQ zDc|jpB_E7M=MA#ahUHd^w{Kl$(0!Tx{XM3$m`W6Y$yi=lW^HwuPd?qj>Xcf&!ZgmX zNKzxI*Q-43rYJi@NI$1^ayUyBXNenc@q7W=V5K0#I(8X|0*_92$i`AcC?)&TlxN); zwQ58olpJ*?RBIJVfkMm*qYaY-ppqyGs8>U}XJ>>8!e*7NIOC`@qEacdzOFbrJ|a-s z&4)x~RAY5veqgQ3H;cU*-QkSpdf5dn`yLicmL?Ws7G1Do1~ncMB^4R&d^9^m~t(obIw89#LQ3;={*XTf1;Wym)zy)8h_aYo{=S*l}eSv?wq4X`*bH7Z53%|>G%6$JUk;RMXuoyl2WCH#epL_%TS)TXqwK? zvVzr8Jb#@xAaZf`x#4w*5Ng4A8f`EpUF=O?T>oL$7Y)e&&t*k!tEdeYf$u4dHu+GY zVK5jni&Js&+Dk|;q_z1XwUSSxz3yno#V!6kGgs8PN=aUM`AcH^;w3yUU^bud`mL9U zYHdC|oN|1s>C82~;gs$uVfT2<@##H=qY>Nd4XV`&16$>XkB1C;T?TRk6G!~XPaZLj z6Kd^kmYYl5`S?A?ol`d275vFQ>DdG9s-ksyo#WArNxx6My+&hmoj5UM^C>oS43ICK zn}wAU;u-189qeAYiuS`r;Fc!@)@XzhNEI+o45@US~F&5{W8-?_-Q6iF3)0@8(TJPVMR(E%!Wy&SGk{3Sr>W zXw;CZ?{YJIfyFUA@m%LjfjBRC@(*H>;w#S85DNe=AGowwlrM7R-(f#loRGySex-^p zELl8#PS2b(CFD{RTNLkZW6SUf+iQq=oA{(duh%C@5?;Tx$>8(^?S(YkEt(^ZF^2vm zaS{-zkSah1?vFS$v}hnSqfBx(HGKH-Gqg6WthL$OJ)~T#6Ezx)&d!J|_>C4?p9d~3 zR;Go5O)gxzfJM++-cpf^)e(z=;^!G?H!Pc_DWgG`l1_+1-_7j=J~sD%m&&2R#u&8m zDRLOJahV8VDZmROQUi$=hA1 z5%@VHxwOnIX)=j(SG0Ux6><>^h;j{6sS_766z#HcO1`sCl@fHC(rT1A?zs?2tqpIy zv`S_yfBK_GjLwF zYa0=joQZ=koPDJb7*WhtID-cvE!O4@po2{pGb0qieMKvqH+aU1d_9|mENbDpBiuR^ z2n?3Y7|up9{qc-vhdowTmWZ`**%d+}mFFDV$R#1dX$nPN2rvFLV3o?9m;}m)o#P?< zrz4I!L%wor+a*{F<+wpXF0pdI#}wO#aQ4`Rlb+EA>G?!!>&%W1(0luM7^37loJ zlQL>kbYQtWvaky`xyW8R1YTGt15Q&*Ir6#OUgqA%kLc_iqI~C4G`AThNdN^w`o2hl zh~3VFmoKhx+@CYcEYhURPmjpvbIR+R$f%4?GtxLgrx{Vb>h?&L&%zl?Jegy&luEmq zGXXhllNsXi1gxR5+(y{vKU2u&G1+v6TnQFUlYLJ6=Gah;)rM>~M|#Q~nZ^AxPI1ud zjYww=w6ug6RvRVG`cuNd=lToRxc}KBd~pFJoa}<9R@knuk&b2#pb~Dsu9SiW>a9v1 z$K5fV{bvj&F{)g{TAxP`b}`9}-??#}t?gAldUV2_$A^>}9$HAO%`jO;{HTX4RS?S0 z=ZXX-i7{D5Sg+^nz`Ykw;3Ug|kH|s2o#O$?JYj3I&3<=E6eeu8Yh2rCvVYR!osXXI z^|x+t+?&zqj#0uxVH}HPB?qTt5Q1*!j6Z*Pm-Y2^Ha3?jDaGG>xXb3+617nAWaku5 zDWvo{MXOVV`Z8Cg8le=USBjI zzwp|@XF^Z}aDiGgsUilyX@L zAAay5KYs5M{HTc#hO^!n6;{}}`xr}=?$GD99&q{k6@K~aukz9D&ro5N)9#4(Z{NoR zHMCb_p414|C0;2&H!si#eLT0hL;bPadBzoMv1pS2!6=x%2pxr-wtn_2w2*!sgZ%LFAZ_KuVG%ULX*qQiRqS zNgRU^q-mCi`Z*+Yb#;X-%TQ8U;rT)=gr2Ub_&Jaxr&8S~vdEFZH5}-I`LWM^?>t7) zA(IxJX>^*Rd&=jzXD3{^ zu*pGZ%-v6SFjA708a&u{gSZ8P=yv{`QZ{a*-E6nGzFy`1u*N}W#)~i3SzcY{aQ~Rr za*JA{&Zyg=BtTS~I1kJm(bVTW-RFj5u~=O=ow(vjG5&m%E!X< z*cvwnV)B98!W}2Cu#E+iI;P4xfSJG(thQTZ?JAw)GlcS3T3gQLFoLhVu*#*C3d32< zv(qW>e%4_;Pmwu_JQ&TnvR-Aq8KQ((G=cZ_hTMMK1tA@KBiv!E1bL=`Mtaf#55^@J z-`H5LjIeGjEPZa+AoH%>^k zpH zH{ZN$O+2QYoQM}!Lpt3OWOa8(m}$f}U%kjXcMs@w zdh87~PYy@?^e1>uZ7eCXD&@{meW@)T*BV##wi^3-sv z4I*bh$YqSig0zaGfm^r2EAhe8fpZTELi|E{K@MU_C>YcNSSlJ6V;v|XgOF%_o3!6W z=du`}Pc~ZKda0{e(O;Y7dm~t$UiMesHjZ%uoha*G~A#&?(D*}Sb5~@<+ z-r)ig~g8oAUJ1aM8V<D#H6s&jCf(IO0PF0nN2A9 zlC9+ir=ulm+YMT+I)jrAC;NxgR+iApGye9Y9m2*Erq-sj)5XSfl39kYoNc|;8D(E$ zb%qfVW1KYASJu9C?ILf!`XzBTPB}R~;nRoDc)0V-&G}>*S#Ce9LN`#Kq?waTE(&s) z&$rqI2p9Mvqw$>kk9O_X-hNyBGT~Q9VMu!P8`q0)^Y_~its#-dacCM z{SK;HB?>&|ahfxX#%A$|!O4yoo<5;>dT2+(zG!V;W|VmR_`@f34xfmv%?XJ$L@6huD_D@{8;{~^*W76P1p)H+ zyS`{Ze!+F9ln}xZ;c4d5Kc&j4JBkJ9sJ+p6N@_hDm8-%=GhqXT^h!3b6j?x)i_(r9 z`Ef=`>9E0pgevLe}5IK4$t-2mq&>G{VaoPNNS;`squ$S4+w zU7>$1q(ec74I<{_5wR!n%Vp;xvmg>&5hWo{jU$apZu=#;40#Pi+#$YtuxJExR=Xl`$DVWmo=8gTb% zmxJyMEV*nbFYXLvndPiE!3#zd&O+dVypp7lq?rZ71T2aa_t>~1EKO2wY}R<|)h#~V z?Q(ImiSK)qLd9y;r`@P>HW+jFvpwR>aOuJ_^^(tM<_<2YBp>bc*f}0K=N6scFJth+ zkmY)W=PO3D41wk4i%kwXW6C9;wWSiBVa)Ey*u5@e`1s)o4|aq@n}uYaSyF9C#DxW@a( zCYQCG>+RztrP15yr6srjRw}XtBUC2kv3XPjKtr8@Tm|(O4V<;0OZg@SJ=Q z+ci>-(ZOgihRhfc&hFMqg_aT}99UqCUTEK~b@DEkN-hDJ&wvYbzBco;Scds}bdR%J zm&N)7C+qT*>z0jiITl{IN>HnlS%J|O;Ri%(n>mB=`62Y8**DgLIiHoWxpv)c#d+wP zfh7L;bOujH@IUu6H}d*ySew;u$H=QUSoo+Hbiw_vPX^K8%e()=DQ*cK@lGav}? zl*_~sp2UcVVFp6Gyb)ntsO({H&a=}AD&NN~#ous1l2p!VO=Bqg7H>Y{n=ftP+Zd}; ztnzvJa+M34EtC@cUq3u${n7;nbIV_Uutz$d@%9_n*jR6}*BPU5uhVMxxh!&Sa$3*i zdzY}FrC3aVYU9j1JmG*CZ7kzih7f|&{@fM92===(o}EqzJ&@ApvqyVuY;VzO)#%ME zvrMAA!V(#h#1NHhY;LVG9!}^FM+h0>OO-!=3ZY!^q0LgP2@n{9&?7@K&m0Raq-1~R zJ||DBTyLgaZ!a^Nx&Xl0WP%b-fncpcV-cys8tvwsWN{9$VB^U_1)XKYNyh&EzL*Zr z@Ujs}?}W9b5~KDKZ@zlf4yIZRl+X1WD+rwtEpIT5Gv58^332a?csK@O5y_nU_ono^X%FhLDo?k_i;T}($52TyVea{$|t}dlO^TqY|xxQ#Xe!*4teHjQX<|adWo-3fN z<$P39pfk%n&M1{jY^*K`Pb$1LB2*A~RxARX?DJuS?s9;elO{ZSy2DR@_P+3fGD(tg zd}#}-Dt11d32g$(QNTC8_6nCStnu-KJ)S&0LTk&#OB?+5uYZ}ty#tOy$ zRGIbaDq6TC&(~kvAn;&!C*zYd%f8t{tb`20E8HJ9n3*copg}rH&}oXW0uPI}22k!W zmk^XH#0gBNu7i+Ki1a+95TtR8vfz1&G<8LuwPG=!;5^jx`(|9>aAUiL_{L2FU$TGD z;V7N4RafFSe(jq)dh(RfXhgME!x-mzpQb5U=88nAJUq{5I2=-r0)F!!{syH=ogaOC zmuY1i6$FqKhgm^&JjZeXg@bD`XkXX|3d?y=RDQY5)ip8s@#%h@=MgTiVk%X|Qsl52mDbtffykyQ&yGg&>C5S@mjXM1^m*e2I*6^2F7%B0z zK?;ax3GsA}41A(;n1?Fn(h*N_)SK~F@9uJWqs~DuX7}kSy}^`Ptwdv`#qjiuTC+j5 z* za@s@3F`FC9tSvPe4JU}1LV6)K1>g7Zg8-ezIXjqp?dPe}p7Jm_7Q$InYfPF_jzVVr z9^bjq;!CS&Mk-Qj>#L#LmHxD{EEOn-!iM4)Hv9m`}B28e62c2w@hcJ<^jz zOLai-cz?j9%?4}BRrZeuWSM4$&&goMwX5rFuU2@n*Fj!b;oxja64t0JTV~x3Sc|MQ zNt4XEi3M?j6?3>x3c|(kPxj{Dix^W1>sH zlv`fgd^pAsD1pv0KKt|mp`451pi3Bp93C8SJdtd_y3Ijnz`^N&Z@m2yK@@TK-~qxI zLSLfCJ;t50{Js_m&qXmU9IJqHta49Su~Nxp8o0gD#NGI14#k|de8qFJU=?+RMbFXEU zH-h<~EnreZDjb^u5}T#WMgvMV!K*Km=In;n+MOlh+=6!Thw^>K7W5(c5VHZPTv4u# zL(|jIh!)r`Vl9~61_RhN6m^D$yu}t0$Hncni@mv!={b2_?yOe40O4kX zq;P-HVqM}kjxn+rJU?(Uz+$v5iAfVn<^@;`(qxp3<~QHENUfyk^@r9EBB8Uyo*q0A zLSJ45%3M~GwibcJL=EvrfAbkX`sg9`lB9cjgcfB^PUa-x8vP`}&n(&q z(rgakf`=v8EJcb8ohDc-u`0kwCy7Nyq{8QWw-0zY{0XOLLu$a1>F;q>@`v)+)_@_!{Adbu$e6`;xuD(woB{s6E<%_cGkNJk^$JS;4p zP0>OUHQN~F=Ln@Pn6tAUuUuK?`|m&CKl|zxe(!hx z5r6c@f5vz`!jl3&@JUnWL=uGo)7hNiY{bg)6944)ew!Cxe1ZStFMr0z&nCS1Mg=L| zEQ<1EK7a9fgu@gbkTxeN7O1Fw?!Y~7TAm+RgL7GywIG84FDhYiPDp8%ae1}Q%U4HQ%59^dR0>&o?l&z()+-BH0qtd8RZq%4|yOe?u zFDMf&)$`3bXM=J&T?&X=ErvE=HlENMjOh&LELF?g+NwZ2X6r(U>tEld?0Y;p9&^&4 zu(8zSl-I7WQj0upTv_G&A0N8{Ag9lD9&+YOvA_YeaL-^Acno_3lF5WX z7~1uacRxAc#>F;5rzCOA?(ryp1cMV4w_y4<2x^7-hqQ>L+@ zS`L_NL2o?g;P8xQD0ylO*ESo>V$IzYN=t1*shD<-C}~5b+9bt2H$qB^;a-8oQ*iT| zlN?5Y$2VTPi04U8kEeXP+hOms54nD2i^fu$_wU?e=&f;M+XE?4IV>xL$1Jlvn|l2C zuRdh65_9pw7S+1P&)#{DrR^6OdXMN$EhDeNU~Y&<1CqpLmt?~})6))7y@6k?ImFRg zHw$L-ar1@KnR8Xk3g$2`wv5TqZ(|lNbW#*j9-JA1algyv!`@P|kbP31^f?pa9&XFV zTAk%)mB?3k>Kvs#e^Bx=Hb?)hkVrs^0-blwgtj;!!CA%;XO={t7nqrLg`O0O+mAX7 zbGv0_4cXv~S?7$%O2XC(nj+ZFI7@4pqxnKDK3i)|QPQ)p5LL<*KhhPG6CHD5tI5V{ zouAx0#P|0{)b<+)-E;oPpyZI|u&@5`T)MPMU&fmeJ6ICjTa118_oa`Pf<>~mgA?vmh& zbnVO(bP@v!;W?+GEY;}Ikd5UUrFNbD)3Iy*(h=kC5kU+Ir&2Fd4WL$z*jjBcNd%Kw#&A4eI0(A+x9H)V+gE>V`yBzL4Bh~J3mr`Mjww1^iSGHDZRy+<44;HER&kvdx zXME9Q{JUmB&VRO$cw6yv`0^LmzvuNu1M&;5L_f7wNNa@r7PykM2*i{ZsOkN!FqDFXOd5OoEQ;wpjZXk?F{-W5R*GS3Y0XkE;yiOF~b z+7M4Cj3;xJmTIi7HrzR&QznxM^Lfn6SC;wm^;M)4{Ou3^oQ+1E|KdM+8|ei+>&86j zq-1!6~G z=m$@&Sh*o&SORZ`6*@-+pF=bO5X?stbdnO*s`#P5kc|BNMwEY%|F6YS{JF~-&^aor zjiFKU__fzJ>2wG5hco`;H@BF?nk1QX)SEILPl!*CQ97Zyx=jDH142@7F460pVU@y< zLQ-8=2)e&s%zgNgkC2tc9Ma;o33s2BgtuSaWcPT?VQ=P8%OFCu);K#pVySGYx0?*Q zeVQxF#D2nTJR@w^kUmZq|J(*#G-=9{3}eIn{UO)ZmuNLI-nsLP$cHbjdi=&qO_s_j zfp2;H>IUDx+vWdx?=gBdC7zCv`7mIT#AvNC#-UDDyRfe?2uU-?a$&(_DXmsBw|Y%D zJn8Y*Pag2rE7yoB4eovRh%7j>saY14s!xA3<>9k4LJy+IV>ZbU){;!;q_c#mTE>rj zvdplu6mes-&RVm=?R#fj-74Xyg7GZnh0ARwvkWVpyyV%*NuK)v#W-|vUu0f1o>RoEXW_z1jSoJ4%Kb+NkO_oeVyV4MeQBAna>(A^gu(4c7(dEU zb%Vt6=*f^r@tEn{aBZzYv)v{rH_)=e?N4@TkE;CcZ+(lkjTJlv@7&#UmYS0ZlhZSz zr6yi$nM@SLY%ceJ#h`a_Ym9Jc^|>-NM-Z*0u<^y1e3vX(l;?l~N3%HRy5|ZjEV*5) zMp#W43T|HCU^<&qErpE635O>m7fR`Vi*uYZ2C0gSivn2}3vfaRaCa&HS_qOv6KAd{ z$x=z-z7$3dOwF$EF%tDr|0D1Eo#DQn)Zj`P^$LSRzv} zH@SI+(T0*IdF}cp4<83jv4tqTK?6y-kh>$QUeU8mooag_JIS(l%f2R>K8OEx= z18#nC{rg{EG$6m=+R$IKR{U>LdP+zk@jNe=h)Aq)dO#@zt@bLZg}-^{JrEwdPae<+ zE&t>n|06cHE@F&u&4x{J4Ty)!1}Ug(OQthnWniQFs>r4><)sapjdh}Xr%aMDvw2FU z4Y$7ZA`c(!ar@(sna!sJ!3vp%yAKaYho^X+$0QbXhckZivk&R@$MjQ=H^2T(=BZ`a zKf{xTxVO)|*CA_LbjgsUaO>uaY;UaafB*RrX(n<6JWrSQBXpL*u+KD2(D_C$t;S{= zWkGvBL9>mjx6u?j=o|qOf+Vw?^k>Y*W9)3gXgFgYACo01GV+*DMtGhgEY*4cfkl1q ziTJ&5-Ln6~KmC2N^X$Ox?j4EgXkdl%M7dh$h0E*Qx^ao#B;#NF$xr#=ol{JGn~kjv z!g5F+*X{1IJeN~A34ya<)S1)7+XV`j|JZXIk~2KhxOU7*E@Un}uohBdD6D0bax$~! zTEsj_`R;proQ>vetS+Imj6eIyBgS(>HX0Dj2Ugr$L5Njoavp#-9 z5-#NhV_w{WlK=!!uvn|-@-T>}F;W>WFPG^KW=?x=1l7oAd3}S@wN<*$_8BD^Dh!E} zjK)%x^{q7yCy*piDhCY437OVpaf0W2c%hHhhU?ocUcAs`K8x9GSGc;>;K@M`lg|0k z55AAE2|CNTw6#j>!YkNh>JD0*bI*J}Bc9LklqAzSmybz|H6%&m>W3T|)tMU}^t7c_ zD-)VI%mZ${bd4~O+_^L4M<0Dc>Bg^cZ|8s@@Hn}9g7zZDsndvq#bmku-`d=QS)w&m zDdlLkqJT8Zcy`!DCz`#TLrR+-M)+=sR~Up&sfvWoX+K9` z1t!Z_TB;IyhO_aM$;@Lm9b;9A>CE6)m#C~?;0N#T@U@o{*4CQr?srK?L#Ew6L466Y z*>***%%wEBoUt(9D5N5;n#{kW^Y>%L=VS~fcYAV&doF<#`C(t^SB%YbFvQ;h0zjaR zLnYHJ<7giZgVuq90rM(xg%0ddrr8a>dG4FN}(n7AJ=)7|min z!n&LzAtgvflBC?cxk;cT_Z}WIn`BNJNap5g#6pRN&OZkklqoeD2tVMHr(J&ajV)fh zxWt{E9?H13#~4Ev$4KFtZkgwW2wdo3mS$ia2q#owCUI^xykG!|#!$E>PbV=(Yy3(X ztInG!_p`E~IMAsfoy~|UWvu5dntN?@PP|xjW{`d%kICPgJZFB$2~KScL7=#}(WHAe z;B-9Z`lU6bj@kLB&;R-_|CoRN-~Fz=d~sc*`V?t|9nU?U9t@ZniSz{hUXQ_Oh1(B~ z>5pSD8DD*Mn@J)UL3PHuJ6vQ+Ae;;nEAwV3e^US&wT-6;fCN zWe7;Qu-?FABUYBHTwX2Phf^&gB?zUV7FupzUBmY*EA2AdO>ORs=R!&)vP>gQ-rVGc za$!p?#JStwf*}@~q<_kfe)xcDDL^3bq7v0+jL8!EXJ?d$8g-JQu;|H+dZ$i$`*7JY=`DR5bp8`MmLV@-7yS`{Z{y#1ugb@bgkXk{SCK%&6n%=r1 zJxybDJmsy|UJ~u)6-I-b_)@dFvWC$)<6)ooi7uKExtJwsx7%#4_k?I?dwPbhT_dU2xZe-Ss8DOys8%cN{P;E` zQ?6ZEk7B7ZSeSbLXsNFk;h;B>={{-kxXV#DdR=1DA_p}xB>6cjJY)YXR++Pi8DP znsu7>3O~Jn!f|hk?z-pWSK_Q8bo1)NzyzcC6~M4njd2=GgU(P9@j1{^JK3} zrP1WITUWRpN~-B0AKt!8qwF!4O>VyV1{>F|@cyUA#Ky5SX_9c|a*Ipt5I-4EQ5|}n zGb)MUwbyTwEL|mPt+Km&%%jsOy+jZynD%;j)dqgcfek_yu5jc{Ka0Hs>*Ps=4(D9* zBltV0BL(iCSJ4!%ap!Xfjx|~Qy7PyYLOvw1Qs5~?5QTj5_>58%@(;dtmG8a3%W#qr z1fByAGA9dLt_3uz0dKspN~!EKOB|vr47~s85eNO4ajYqYicDK(Nk-X|{PL@tq^aTY zexJAM>#ms==UNO=uqV|j<#Gj)rz$)9Ubmkj+zg2{cA-5dXI>U^J82O*C7s7CS4!Nx zb(zohdZe`$mA13pm5U{kS426Rf&e8I##&6K8O~Df@Ai55>N3wdQwEb1KX(BO%B98q zcDGvQD7hdgg`B&56^)^jA%&&Ty>`KQa(FIb3u@H`S!MKj$f3=1O;lmMESzK3Vu0S} zjFu192u$vlRs04a3!7difh%@!fxr`z*(~MGXNSCWsm1DYohJup%w{Rx@;0A*@R(`p z+o-f;BmauT8jNh%Qfrfy?TUEzc*x<&l)aMyYwIl@y#JKV)f(C_aqrR5V(kV|xY(E7 zn};kj2(#Xe(;|B>G-M?V#SR^G7~gUK@Hi9wWG{NP7Fq7o!@x*gk_CUoZ! z^E6{H)vT1OeE%o!^K0LDo!;>yGc*l*mR4n&j@;Rn745Fwur4Hkb-Kn#%MgHcX&i*4M{zKnI-KV6UBWtH@6s5BC5|Y@r+(~fT}f_&F6UY z5!FVEYO8_teX_}vez%KPZxTikdOl%tc8W0Rc|&J2;yB@zS6|}V^-EMjiL?f9a>{#8 z`{?E}C;b`6C&x^NeKanlI0yqQ#5N8l#(pf>ok`d zoRIGhw@ZNhLb9CD0{X36Hk`$9AjAMwJ>-gn} z&R7G6@#KV$?uC@=Rn~lu-}uT!I#2HK@WTOb-dN+?|Itg#<}qh6{Aj45yyWBw%DK&m z!Z9eHH?TRQBXaqJ!9!LWs9GsMG)->BC(#(Jc7xZMwWKM?N*$&XX44tk7^+q0Lg5Dy zcOUHY>4RqkjW(&Z+>aCfx_4-!Syz<3jKG7S)@GbYMw!A&4>KDhO-5Kg!fPy(h7D#Z zBvzguOvS)omSW};q!L6?nN)d;Lwixrl_oKs&@{>cCxaP-VT!N@J)h!B7horBuDe%0Mi^|Cpt20>1xV#kNvG?79))%V zoK%XSR&_HBh23zmP5?g&k-mo?6ya$O5nf-ZP%HZ!o=x26Tn-q{QYw{@Pzf%rFR{H` zqgf64+js9Xx%Z65rgF|incHJz7&#=ckSAHr!>}xLW}3UthNvK5I8F(okd0P_w}1cJ z$l)IMKlzX-@>$uwfo@#l_I@Ajm$11^On5$cKHJL`zWN8>A&9$nIOqzDVR>Vly`;`b zEV;Z^r&bNoY077x?hsUKc+F)O=(a#{bGhl_5O)Q*Lx@>GgwH$62qDe~r}ea6o4;2LUTfCEmQT%xjn1 zj3;jB*hq~)<7F9&3PO484`O^@vU@z{&f^Z>er*fL`0=MlBw3zEq*T5y=90YU znOCK-%3I7k6j$+M#ni_642UaAg;Zqmg!tr$bUfkBZ@f&FWjr|=A;JioJK|~FFOtG# zHWfqiSl7@N3)b@#4-STGtyFk%yTQ-ycNQ`*FYt5O)AOH4KL3*6+w%s(70a@)Fn;cH zbIZZ4S(&pL#b^H-R##Q;WV6X3#UU{gAqg`AqzC;05(MZE z(UaZ;=s^%b5E8^$C@wR-cU4z)*P2vVtg0LKr+qq8z!?2S;;<>79N+RZucHwN^7_9c!Z#jg(Mi5&!K! z`!?VE?mIYMKtA;N@Y9FjdQgV+biTp%8=T%1o@qOkwMKz0Shi44WI9_`YwJRyRbc;8UBOLn(`N zAlwU;y-B4GFyJ^Yw{G5KZl-3!&=;*vpM{krPWyuQe=SM0&+PIVZ++u6a-qv`9Md00 z2qdF%!ok^?z?C>cqNI<~f;36Ug&_(TAt5Z!&^>6gv-2D$?s8CXq4KLdc-3Y255M5$ zL4(a(Z&6sfMX(SdvJG$|Omn_rS$~j;@{9$7WJa5@7bJy2k9wFmLWTuokh2ZCS;@i4 z=b=0Vik&!snAi9Xq*yyb3zFhHwPBoJ!biPWvGM35^pB`fdT@VsetKrNnpm8&moeLw|fRr+vp7mLq$+3OdrBn#$ zNA_AgS901J@wXqo;Jq7*{(P8OMsh|8x&m7`rX0gkGbLV`8dv^E8i}_^zZ_ zEzv$bL*|P3b4!-nt}RkCZ34$O#_E2Dq;rNahM-hLjmHEz$;RaZuA@oggfvYMr2>Ab z#?$>4$7e%4&!Inx*=r67f*ePUHXQdDjT2mHO*M~BT5N8uaPMV{VSIqf?zxlE2C^^` zr46-G$PeCJp+AaAQbjZzF^&^_-$&?F^x9`=qe-JaBh#hV=_0(4t9Ra`_rm87zxx*T zlOtX}T;-3ybA$U21>K`%{^WZ%n9Ik)jgI(}cQ0{zxXX6SWqIogd-XPzK!Q&2T*vD0 z3l}3?gmei#hvS0*pFTRI90;y%EzmnY!7r3B7zU?JgiZ)66})1RUi}mk#kjc;e{KQg zhBz*ec{WT`+iU=25IH}4W+x$8c35HXd>0pQTIEesMc_*ATwCDr%O;;aJz=4i$0qR( zd-XmWOBK#KBN}IY?%Z6VI5&rI4jG;tQdnC@csVQlpcPYBudG7=V{8$`XuflEfh&sz za)C>4FedM4e5qN;D~xuiR*E2Ct|(1;!57<&3;gr!IxO`;QVAvfkrC}dg6q0mDiqi# zcnq7Gew3gFF{v`>d=YoHfEErDiX%p&w8$ta_BTr@>_KlPs!|pa)y9f=Xidhgo=DA3 z=GAacYsrkX3}&&O+BVbot<-;p*a^(j;{n~ z8KrI-jb|@eg{lc)l|4g7TjXOhEix16zJTCNf5==w3Z_Y^eFG!T@41yPwuOTUweJ42 zBZ@v;-<;>g?um(`M7*=Pj5x`0+U|(%XhFzvAERT&(&gl|jqVK~P0$)n>K(RU9rK+# z8}x=_K7DXV5^Fq9ocq~e!+IgDCyl+=V)BATHYU=|f+>Ahs|#uO1Pu|HCr*}3cVqbF zqb3^*Rq9Sidyw*IuT8A2XGK5O{PcdE%S%NbHw~>pEOyUEM9Nt2ldOM88;#K^(h&$1 zLmFF!I_&y!Fsv?=coqo8ojON*1uktavAABM-5xMoEpX%Yn>^S#%hs@_R`U77_ipmW zrCGu-pj^x`?zSkGi;NSy?&b%OyCFP14-xPXo~b2 z3zhNeq(@`#6^jejXRO{FGVHZEsyqDRvuzF@ZPRFWNVQc~EES9Ret=379N{5MidIRM zu-YV}QZC#1$OJ{EdkcI;iubpRB)|PN`}5B9Ig!HoI{)}bj;|At-!YCp+!F{RJjV!$ ztvbq#JFfJk!X}xiR!yy1rq}HVAq*!+2LukRugoJCm#ua^2J7(V*dQl6ETy#Wn_t|! z&o6)Vp$LMIaq4jW_BSZbZ{ZdfFk{2UrFCxKSmC3OpHj+syz|B;&z?SKWp0Ll`g^x| z^z;S&_8G(e2}!?BntFKYES?vT&lh=ZYXQd?o`oR?I$=l6} z##jX$lO!aaF4CGT64g)eJeQ$z`SH*15)He!UVxSkTDk;tt0X}oYc7omI~o*r~4t*kPxA2T>O zq_DV%405EY?GdmV^tSojDkr6c(r{zBNI7t*mP1;dK4(TVj1qqN$z#5KbBSxW-o*1P zKl;ljyCkuXFV7!pty2O=(Cm$=ADr^TcdoLywu#X⁣?HG^j@opWS_qNMp(~Gf2Nk z-ZzX?=BFYA#z=feP%8MAZek3BablaaU6*94a0P)U8AU0D&?6VPw0dJiCV@L;ZCyk& zm?+W6sanlfkdllJWaY7}Y_lPgbCpg;$C4z8;U{+w_@lSi`R9Ldh12ek#d5&C7af!V zCtqaiQaHV@77evXcPmLa?MJNF9M8Z+|7UwiIgrJ`o?(ep_w`0}PTvsBc z?W2)W5T%OyJFO`?C8b?g$|!_mk#U`-)=x)DPztRy+S<)$UOOp98{Ax;`oRIh^*HXP z96Wf!H{ZO(&9!-2_YRPbYYPtoOq!T+9EocUa26);}Nco5L#k%Y7UQ%#H)i7 zl5vlG=z;KIcuKc%Ku}vF^j-QVhY*i(r_iRA+h1K<=AG9s6UQ;tT7|Rjh#&v_Q#Lo& z_~G|&@g(f?*o$ejhXlC-LP*Br5yQa%DP8=)M*xoN;QL;-?rqUTYlW1~)Z4?DOf4}} zn*0wTACqxWidRY}OYqFsMuh*!@pS_7yT%$|jB!xfXopy7+)S=j2z&4dqZyAzqSa~} zDILnig6MU7c&;>_7hWt6Wwd~d%dag@S!-)__4@0toB8Dx5rlb88f`9ZuCjUQDto7W zK7H0?fB%?=k3v?LXD9?N4d_m&pVqSKio}Dy=Bs%gJlGg~ z3tV2vbJ7}6y|IYvN_Gy~7$I<6fvaP>jT2mz@Xb4yxO@Kvjx>~KXE+pqMK$Fe627@>YWjd zMw``z3blnipFix`3ZfK@#}N;oA0r)?cWp=74o6OCy$O< znp@=3a)n;IMW@vwU9KVA0*;$fnO&sS_E6f81_e^#K;HIV&LxcILzCMQ;rrg~=7Jcm_!Xkr% zJ>oRAzB*~bps+^a+AUr*I(+uB#mYj3ah$S$+Qs-qTBj}A?LOc6<}H%UhsKLrJlZ+H zsMJ0-0`jFC?_Rz^t{CF@Auk#ck9S*q>((4kcH8Wn^tiQAfx=tdQq>OQIAS zf#(P|mn+Owa%?RYd4AaA<*`)>BU}4MT*zi7j52w?H%@y#vP58lQcOAZS*1M7B&SAw z_MTaek~3M;+9DVel_rtR)x_V3te4PE>4bch-5NES>+=t541|H?_ukp0-Rki-zj(;% z$}9?v9E|vjKm8%4Ai+zUgkg&C3})Qn(wxVqt|OGz#72?Cijf|&vv)#gq&Vvi=?&HN z^C%S3ncTLFE@m{y>~#fBmJBDE?Cs<>JClZdV+(UKOC&AAY0zYn*3z2s%FGngXp4Xv zBSEXFA)`Qo&{Ootiol2r0ZT!rpdGBS@I-djJ{|FRM9G)@CqKBu-r+jeFE4R6NH}y{ zgi&-lJ#MX42*Qw$9v-5NWH=fN6(^jX*7^BQ{!VPJuameHoKXWKR!CDtshCHnG4Fry z3v@EZ^-DZ>@(K}F5st^%!5$_W+s{8m-|WYV;*?kmy2F@O=YYXDrBEtzu=|pq{P>8S z$Dh#v^gs*0JUJjWl2XMm7!DbY$HYmB;~3+5o+ZF(yRSG>WQoVckaxOc*i$Z31Dm*? zUra(SI-+0v8pcZbem(wiv2wk2$es1L|l_JrG<*LgM-&{50(VY0~SO1ooT*&v|S~s;yRW!zuCugv-vOp@D z;0O}w($i4MLD99~Tr|Gg&?;$Wa!k}GC1F}IbQ(o@m5GsTYwPJyGKPFC6W@pMY z;{i%)=H@Ci8y%KcX7NfDj?RXZLWg&*%<}Z%GfWaOYMqg^he*d|s5~OqM@ok)uivIU z$a8(A!sx6)XV_!VYA`%JLE~Xez{u&+@6WMuX`RcPiwIzOE>F3lIm$^~VR-N60x$PZ znF$T6?{44;K@z9rO9g)Q@E9c=E;GJW`|P68D&?KmR_L}mn4$G1IX;N^ zaNOdo+2!{26$Vbgpw&bhi4()H+e0Q1rP&!qaY~rWQLdJ0H_nh@fna`-6k9o*gdURy zPOTN`I00qIg+<&#f#}RS!53(>|utv$C14D;Y#7 zKfiZ`N)?X}`mE387!6~b%wOO)pFKzWIb^;-cdXFDodzyKOoBVRS;tArm6bAYT%KiR zHit2qmwTu9sUepy5EjdHyInT6t}v`?KG{3M4d+QT6iZcJyZt8Vs4F%uUFYhxn`U7! z63xz-E0?wiiWPc^!?kPI*=(U)5 z;?$5x2T@zZ%MVDS5g3CjZ6KnQ#`isx24xId1ZNi*hotA$A-RGLzr4LPj$D3{CDp*ZT( zX`j(}{DiRGrq^m_ZpblCxx}O4KFb@ISy)|1BtALUFq8MJ6Lq4{siGLVER;QF@-9VJ z@cKrTy^|isxSWUH=k$k3v3s%tIe${VLW|43m?0nX!tapN-y>azQIhbZ&-VC(w>Maw zFVh*ObYl=wPZ3BVGNmG6JsSd}Sghm-rKZ&%GgelT+J-J-8dy(58Dn4~<$EFO6xq6( zCMVOF`NI0jetv?&Bx#E4yS)C|D*LS=L%)LKd*{LZ6acy)o1F!=7~6P0p=sp;hmEB& zt8;lufx}U~L#x%{t*shIr+wm7<9SY&1e~if8L&?7!X_Tl$&!>Th}9V^A)KsFFr)og zw8PFz8Yf^hZV-TEO1aY73ON|9EG1W*q3lApc5F;+HtGR2c*lZ?WaJ%pqx!IKX2 z1($JOayEo=-ltj!@DjsHNtoGOBm&ts@z7SiL&p_MB}2it2DfqKu-6!(;}MJVRbCx+ z`Et8X5Qfvl$dR`9#P+CQgI!^m$n8rh5n3a)VtHkrIGLCY3fkQvQ4}GB#PwX##7g2O ziN^O`HkT?0B*&*+qBzd3Q~%a_SJPz9aBeneCUJ&V*?)S9MCoWum^vu5DA27p`1==k$$Nrpm)95&BD+JDmzF8z z7HGEH>~6neG>X}Nu|xf=YldgXqP8@Ha3e7q_PKxWGwR1jXyMZxwpqV=lU7ktKWj%z&C58svdQI(;nv*P~i1Ql6jZY-lM|Mk#Jzn&Hq70S&V=AGGYM)^o z!QpAl&a()WB<$`t`1ZGM*}pgX4Lm zMle5HW)wKQ$UGTzDy(vg8!%TbP%DKz+-XgbfJw6KNWu1Q3!N%%Y|hdf#@u~&gw&EN zm#%Vfa=>5z%?`>KUVH6zR+n;ouyc&@9dsJAzB0>eSJ&t?>%4d8HB&7W#N12;$=l4< zN=R3t^>yZJWwW+W5qYmp4~C9!1Br>g_&gzn;q8HmigrPkjBXn zka(+?@PYs(t-)Jvb=B(adp@x+_)9r_r7}uECaG=Z((K{)TZhs`6_g}OP;r76dN{6U z151%nL5wD9HZlD+LP9H=p)xqu)pcyeZ|eN5tBW0N9drCq(* zd3$YuFC~4g`Ne~Vr7#Oi4M{sKRIfvMc7`ZUSStIB27Uhd4_@Q+WRE)=c?$U=KmPd# zB&nv`X>s-P26yhfi7}9$o#EwYM+hwmT*+)XWG`?TM+uHF^!r14gAwoET%>dVz@l`H z!?_fMl?YZ!;bi8HlcE4vG$9_1a6Qj9PEUD0kS2=QXdEfv;^qm<_6m04!1IUc_{#z-H}^GMQ6!Ad3ecdH9j zybQHU(*zx9yuinC-E;ZX3y_(OpR@HfNu08TK?6ywcx}CkR0*Fw*hl#Vo6u#~HECei z+M1xo;{+AQgt>r9B~LBylM5ta;84l?)CwMl%|4$$>e3y?cn*9&pXcgonJ-_otS<AFb7l$Pc?Hu+4(5onF$TWXBfCNq76 zG)>WIisQK;GILdZ5#cciG)60uB(*{uj)Tr*e6_a0w#ev5QVLp)HoyGnF*7q|l34NU zFLnq#!$vNo-R+9c-v607+<6SbHK_sD54d*g9fTW-nOc#{b8~pU!~MsHv<3-@GMNFf zU87nlTq&$mrOXhY2^wT9yJ2xAWOboL^Q_OeZq2h$Esz+^%i|uOJRH;OCEU5b#M)wo zAAPh<6sMH)0pEXTlcF#29Km+k;gbgkOq7qO5Q?!LQ5utpzD!;RZPaWp;`|J$O4;5y5vRR`*ZAK~V#BXKz0b+^r|i6ZL7YOV zT(sU**$!falTiZg%9(i0I1?kr3;X&-RO6x?uhx3{Jr_MebVhp=!pRH{Et>o_1M43* zzD_`X$Jhc$G+HO%WC?^$r%ir#A!|;XXRNKQiOZKSn^LJL)>amA&{V2rk*YK^7IK*! zk`@ig__0|7X6y8r$6tOaT*qM)S$R>%FESWL_+g&2&Y1uGZ$IPryKwFD8i(}`!V4Hj zDZb;dc=ZiVx^4Qp3kz=}iaDD8Ce><*^_4~ZT!GWG77LX;cP?-8;YYtRKl${h;;rv| zlRx5u#ul(Y58Yds47A6Y|-k2B#)w zb*aYl-I#HrC=>!dzWa)D!Dloap;d}-999=fyt9=je|4S5zxj70X`4TMdxKlAU*VuR z;EP5|nrO5Rn5z|deST~fZ!FW^E%V~R8CRAHeE&w3@?yZ3XD$ajR!jb@)x~%o@4mJ| zDd+N|51(*lbAehV&(A)3%GUZU?_6Kz(mLoY|GLZ95j=S{G3)$E(TQc9;&a| zoXr!20YN@M2!U5FGCx-aA($!TxV$#clkH<-Es(B*kdkhz4F-;z1G=p?m0E@T(kiDX zEuwCR+}r|A7=YF!{Vp<>v&u12;OBfM>>DFMhPlkW73*g0*xnZ*1i|bai7WW<=_zNu z2rGnR7!8J~exJ9#vBlcT3`!gFGUf4M7i|<#lyYfffy*0nXz8+4&9isf2XWru30ae; z5RAtupWol->C2q0cnWy$<}z~76DLMo+FIrA{t!nx^tyfX^yxEN z?Ius2KNpM3i+HZbt5?q{6+&9A7LV`UWi}^C)0n8+Au(nAe2KT>V+KB=;@t3pUp42}U|GKC<=AxW+00ntmErG&H5?ham4V+HqmIv zgx4aagIb>_x3P@ph0JYUCLTv@E#|3rB2JnEuC5gM*3CJ7@=2e!FIBm^R>ej0tA}+Q zm-8M1k*N-e$x$q9fQF?wSQR^4Efraih_I?^6Z!{^L=9hXZ_RxzIu$FSCk!)E!{*p_M+KP!VIu@W( zO(pMfb*;kv$9tT%N7R;!mdKm^yfUDbA|E)+6hrd!c?vGnDtYqx0D!?Lq1_p>-RROD zDMpC_=^%rE!6@d7XAQpj`U;1qL)t@S3pyDBWNRanevWLR2`*Kv~dS(s_k$%JvHH96m5W3kNB=O_HbFYoim-@eA#AmPLN z2PBEc6Nc9}XSljni;_6wA16p)(V~0R*TW-gs8VjXEfrIfA@D3+?W@;$96rrA-*f=96bjiIc&p`bnN_V#b7k%Y-qUr z*6;J>qnG%B$6I$^H88VCF2!_e+cS`+J-lYh-H!d+j!5 zcStnq(;GwtVIJ3YjqiIx=@8!!@H{6gI@o?ADQ&{6(*)16OpD+4_c-tEkY7naetX#Y zwXbWXafA@w1tqwz$AA3zIsy5A8?F#qA+%$rkeh||T)Tj!Yn_@smoL7&FQns}m#U;MdPSzWP}F=LpzBs1AKkC|e z^9H42h?0_b-@U~z-~WPx<1_x|@82hvnbM6T2#XcGd`N!`<9e5~)_`85kU^P3T<7{~ zLA)$WMBL}{YK<$)dGYY^HhyKDM(Pod$E3>OW{sh)7a#(kZg)&C(&U#4knvg_VSNF{ zX~JSPPpw+w*Y|e0v^qmR7x1%>UlQg5Vg)Y`+ms3+g^V6joE1o#g%uzL*P3EfzR{p9`}EJPi!m}xxY8URB!OOm1pp)SHh``D6L%~pU?5| z@ecc)6u(qvW4T5?bjel93{%6&Nt=Q+H1_KJ?Y|xJsukf1pLEz~)NFz=gw-mtR7FoW zBfI&mFO=At^$;qD?|VGk-bW4lj0PjtHkP@*wO}_b0o%I`I_)k7xO{no{kav}3GD;zhw?Cigw9u1*15Hm}wB+)+O(<4et zYaI5B_@DpPJ(NmlwNv(;W4>`~1E;*juMZWEcOo7?gI_%Rg~*p@Si5wU&PdUW2D~~^ zw0k37zrM%J((ZO!-TsjI zYM#%Yow9#6!Vi2TiqUBUH5?ICXHbrZA10{w5yQq2iwk9zSF3#T=@(p|(bNxHpc9Y| zuAieKN~HZRw_aPNF&yEln7|>ctSegG5v|^coG&N@4!$ugmV7*6Y*OWjDaB_R)MiRd z=eo7o9|Fq_=d08LiNR!)CdUs*gu|%QAx=|9b0PhKrrGM!>vdt=5&6)i-K^7YcTs6f zIVU)+AEMHjTrMy{5Q;=6{N&y-Go?0zC}l8C`Rk8%8IGXY?{Lx@F^n`Oj=^=&THw0Y zd#4pks@3KvAtv8xH8YdahuPd9Wfl2`0!z!b_8J5kO_V zMrN8^O59wCaLyIXrt^N`nVQgA&yhA8q^GIk#+6xatd@E7+$UctlNxX{dBQkOsTMqL zZ!J(Q`J}046s7bA5%q3N?|8r^0g(b0cj!>jsvZGzpB!_N8%RlX};;62ud?a=RSuzUjJIa%rmr zTqN6>j6!6LLTj6_%dELt8HMi(Txl335M&M7QLG4k7a4j)aY`=m7>&mahGVY1c?D-Y zk5`#zHPRfnhU9&Zciz56u~??B3~nyR-hPYG*iv*x;}{`r9|0=G7~5Yo2|48j8s6k{ z3u8!9%_vet$}k#6)H@?iyJPyp2#H{}9FQb2PhOp{GG8J|5@yQ*zxa5YvtB~JP#_wl z*35V^uNn|0qsZA0VWxCHOVymx{jkWNn=b>JxOr?FQ-nsKkizin=_Ap5^)a3H84GLI z*w|c0Y1@N{u);fGA;hSZL4UweqrrR<*&=}!xIuwjxtyV0ZnnPdxuH^p<62ssN)t;_ zl~%yTt1K}RIUGkYUo8?if@Cz9=C~T$pXUay*m>~^m1;<0(`y`v#$Jy4(Gi_?mtkys z9Q%X52z-aYFIry^-y@15qG)W{B3dJ*v8Z*%5Sa9QO+-d6dVc)2H1A}HjN)ms1jKb* zj1flZuQ8B+%=kJ1`JLlcW*p=YC041z7J()Qo*+$A>h(HXTbsQ5?z`mkW%0)C*KnmW z3k&lmP1PhUfGMbcArTQ)NugW_nayhgXJisF#tdB%=?FFMVw3~vh@0~+rCOO6#~sSE zHQZta5e>P1ZOc}yR6?WPWbb7Q*DsmPzk`%6&ejZ$BgA*#o}oHd zh&v(lZ4CjEv_P1Tb`p*${{_US|!iXkspXhzKhF>U@LhV{KDC_S8#h+?`Iik`p}BK)mTIlU zy_aVkowUi7^JtTwCKxgZ2^N=Z1)GUV%7jau#ZXcpecPX*v|)KR$NFN4FSk$W3}ZZ3 za&x`PH*YKuCo#Wyc*NV+R~R%;8TE&lPJ|~UTUS=-4o3LYD3l5`n?0ib2$Mh|@VK;D z<#VOkZ4B`OZ(8jEf#ZAl#R6X7SsuKBPo6X==3Khe=#_8MGKSMfBdRZ+FcJYq3!>9w z9O=?XT#V5Sl7vy}P@A1&`}q#88}r7SH>m3pueM*|oVEDx|JiLi-4Xxm|M@<}xmmvd zy|<7?v3p$SJ8xg6=u3Y3i!Yg9oS{@M(r?tsqsfIuzW4eXPBP|T=YaXS8Oou{jpZWs zR-fH^k9Te@Gwc>YEBt~-B@q14+v~hK?ppP!42D{2FDbr|=aD;WTFXnvWRB_ZAFp5=na9#+&r@PI0Q}ado7{(B%mM-MG z4l1jpx?bk)o>j4xmQb0aQY=s@2CQCMAn(S!|HTX1Ck;$8=CkK#?9^jA13{}b=D4@R z%aakMnMG=&BXMnQjY7pRObn@zEC(L#LBfNVEtFDh%;x#VjRo4hn3-yctE)9Wd){Py zvB=f63eR@Vs1$wXsySZPhkW{^G4-R6QV{0zNJnIpNsC5<^<~NV1>C?#nE~ga19-lR z=a;Q7f>QJ&#px(wc-ZHiTg&X8botS*U!slX?dyvi9Jlz_?{5?4LMkrFt6dUkKzU!UpH0vB|BI86`_hgST4IXK6OaXO9ng^V&R@*5|nY zs>M-jgw~o%i$&hLI!AAu@WpnM(O5A~lwH3}8p-YY2=W1Pii>6ILV|n;f3BdGvUf z(I{fjXi#soNTo*cx4vnYP@%Ik%id;pFcX{q|pT<$l5)a$U`eB zakR2NJ(DKtOnP@hGgHQjnfRVHC-fYNn+4&^^F@YHO7pDC`eK#gXv|<3(`pYWh92L0 zd!41(G9P^Lil;B@R)QSc)-ee~L?%Ox(L{;D4Sa-jh@u!*8arocf}1blDMj2m0h401 zrTn&slB1V(LeXPpIb}2&ptV7#X_oA}R$f~`tOes#Ae6QqOO87so@MAu7T5zqXI^P4 z&8ScIp2vxzP^t2R>&xV1%EupmMxk8g`qd5YJ$ON}QpWXt60J~aic!jnU1%*_r6|l+ z@d~pjr-1ZBWI94%s2?BDINm3h^N2R+X=|z>oys&{Z?P6AOE=VbprA`$5z(Vm7-0y86$Dskje8TrDT3#5!^fcaMnah`75zBz!au@4ddo zTi2J^EqT_YZNVouT0<_b;jb<5jqBf~SSs;&zl}S)fS2()j8ddggoq-98{h;v($r*b z%`uOjpEA*!f4I}abtFo|tD`PL2!^ACBu&^{Eb;rV&++-kU+}A+K45EeiJ8SE#%X~Y zTQ2dij~dj;70ZOC4`b^+(P$4SUYq0L;SQBbnT?r{UgwmY^5~y5=?@0%rU_oI$WqyG zdiadZ+pp7Es&Mz|3G>xFQItYl#V4WP?o%umDb3dCL@BvK9+HH3G`0c1z7QA)!FyB>k{TOH(hBP>aQ*4 zS*@<|o5u}qY}8mSJ3M>(iYG^X+%O;-4XHROfANFs498<;Y8B2#2|xehlw2-{Gw$){ zca{l6itoAX)VqAK+az#2)Od^<4iQ0s7y7n>8hE(Ad%h71LoZUa#|cUsmgZ-9@8$yW zcuZbuq~q|Tkz#Om!g$c6P@TaqR~fY1j5=Lfoi6YH<`Id~{KbDd%X>E#I63XIc4?U~ za4^+8mJ4)F>dY(|R%b#UKkxF3 zM@_=Qm}1UloG6~|b$IZii4=m{n>7yVT}lOyKmX1ar|kjnf4++l664x?l%J{Mc`m2@ znE7(RH*T(Q+8xsywQz*7$j4|zd3gy@C=j2WLg$EN95GJHh>Z$~7Iaz-@?vBbXY!_; z_eCTXu44#&&H6&g^y)^8hC?GkD5ZG1eZ z^XkbXVkgC5D9$f4=(N~9J|QSodF_qYkflXBrzbpm_<;V4Z7wezv$FJp!$un?KZ{#i zL04*A-&|#9ugM@$yncC(o#P&NU!1W#lc!b*nJv4l&4oyva(Si9lbus$i$1djFH6X= z)n9D8ge98kuOOC=d!cHXB~+6krO4c%?VjaG$^2}IpMSDT;JLhaYl)wKzK7>IM6u>? z?;mm4Rotxlwy9e>$Vosl`NbEgiW6#;l;>P?+r40)6PckmN}VGgh6y5)(ReZxL2JWX zSLPUv5`Ouh&P*xb_Ewee-=62uUJoe+>k9?;>U|#Wc2IyjspPs&rX)3qQZEEn8D(qg zp#gZVL$eq2@~Fd&^(u`{#6-e;f~pBAvR;!32VPG76edCpQ;OL%V7oB;7y4e#d8OHB z6c*VM*?d}%L{EFqME19onGzHdqiugsG3QaqdvtpN^+uE1SC+WCQe>gzq9dQst8%b= zM6Q@;VXn-J-6N`I$hYs@c#?p@XhNKb3Py5-{-RjyC|h`g+e77 zkuTx74r)AtXh76xbL++xuK$y7nJ<6+V-b)0Bx9?*D1@>JR2-ol@PZtU&;-5#;}ae{dPp(n^6cqj{_-#Xia+_Y|APPS zfA}9s(v)7mXQJ^yl=1U-{+ibpLgj^WoBi0*FDwU z)0pn@g8?NDC4veNklB!HMd&ZkQVXpW!Hq%@B16yuq9lrd2uDJgo|$&jUDaK#%VuR| zW~F(V&%5i-(c<2hRWpo109g0gbXCX8dN1$0_nhDF`}>-7qLEqg0on4gS! z^V(HR%VA?}jhti9m|sjcnyIcpPhkrII!Qh1vyFXqc>#k2)3h0lC#)Iby##NCmd}JXkhL2}CZ3ohzh;u?C$eyulD# zYMe@uNTpP%Ad2Zv5^O8wKN~_}8NZ3}6z8CZP{cU!(_xPRnF6$T1AB*jK57^J;DVD2xGM->Lj%YOMY;3IQ zVKWrF&z@7A+2Fma^PFF)b9bvr^<16Vio?_GCi9IVrAmp%yB#){HW&{l{QJMYi?VWP z(`M>)B!xmH5mqu`!G`>BgaC4rA<0-#nwcl)pD@|mMN-BbO|bK2!s8xJ{tWKyGWYfa zRt~$od47?6&Y@T;P%Oa7aTia4Qz|fJh)l;EkslC@eeAr8Q*ciU0Ijnk$1aN2PGN@D zvwJ-EcPQixq>y^Q*%79*h$$PXDA$`{mnEiSpH5{`1A9}4xl;HOL9lm+<(CVjC zs!G8Dm1Y$QDPK(j$O`3YCW_9U)z@5yPAP5~6>f^)pIQiuw7@>)ooh`PB`j85=4v@U zynBG*xO4-}U)?_7(wQ3n$v4-SE4%#lgC-Alx`c_ww#`&Gku?d4(gdS1(vaBs9GsTL z>1PavV^k23Z`4sjVi}U|(C5OL8kLrKK$fKBdX|_k~>@|6| zWpe%UDrXj|{PNaGM%PP7lp=3y8b*gVR&BOEYjb$K#rikaxikZQ(#9y&IqrGv9&~Xm z6IrlOT9VpBPd}^5G)4j=GpI2P$;FLXdIO)m!!FCSMdBzTj+5*=PVbjE44G>bDdlax zc(BWh-9xTiS|ewhNR@E&>KQ(|wMDn*5i5-sL@5m|qZL9r97-i831Ki{W3|CQ|H+%Y zu~ySX6W&~_h<_3J+`7L@GSw?-fi?>%eK(g!dR@Z75j87MDJN-ndNdDGikngiDGgX+ zIS#gy$1%XMOoWvuSE)05<^q;~h?J>j)HF?mY2tgCTVt_=G)&^qr&2CctSz#GURCyMB>U(cz>!W)woXUS-hlqv8bHv0jB(s)Qto38RRYM_ul0wdlNT>*H2eBnska z#9%mLGVRp%6ob} zlhS5OPq}jK0;+q&AS@6pm#CCn&dypCat@aEsTWFIS}n7GctSgDGhbUKS2%~T zObj$*?*y-RL}6x`O5Pw)9_Qv}s9Esw#}5c?hr+@F+RkMbi&H@s#7a>syS#IC32c*g zcf#s?nOMQjUYm2Pbw0hf%lcxSvum^5etgJ&v%|O7>s+eEddKRBch0`e$>AYkoLa>e z^Eqm>ON@hrH{aY4zj%1emj@l(VueIo{P_Lr)Qr9`W=$^r_!~42UsA{$0?IUI7Z?T_ z&ufXFeD6(t`}r|O!x52|eEiF=c)oMO*^LF(7S6Mr0yo~i z#GUOv>NUNC)QbLa!tm%N_DE2>dR7ldBk{@SUox?0SZQp~X&!Uje8_U+o4ADhr{a|TPg}xDkJ;7HX-|!l@%^p zLn-gDRCj20$3$_&N~6TZbIYtO&l4oj>W|slIVRWbQz);qv^dYvaZ7)8_lX$TBkZoG z^K^@icg}F*+8d1hSbX{9r#$Yyz^}Mz@$ERs%pUXfBb?%u`jl=kg$Tn~6Ka959d1AG z5=9A#;WFs-C^cq5nsoLLsm#t%o1ejU9CC#sqwbJiyNiw@3L;{y?$RA79LwV3io@8C z82AZZyNzKQpkgM&HN4@F<>gtbXBP>_Jw~BMNy!HvKVtuQz{Sh!{LY*6e0Vn@Z%cmr ztyRvgl*yR}AKl$$W3kF);`8yB`)n@PSeUEO4HUK}vm#E=lOb2mEpdIh#Lmf(Le9dn z1d%tP)Tm+Q^LU*e{?SVkZ%nOH;;oyPD3uCSOAb57NA$Zkp2!!Z95h zMU&ZrO~W-gZuKb@a{TVMuClpY75}ok!^a;y=lz>k`TgJj3AgV&V5_Z(e4j7~I6GhB zOf^rfC{g_v%r>gLeSJ}EHz&M^BtxM=7=&@agXb;YzOqEQ=(5usQ7z?gb280kg9;e)7## zzS`-r-5la8jbmAvrbLlM2|7`b%bwZSf<;pixF8H;>eU?YTwFw`gx!M<7gtKWJQ?A| z3ezxNwH-RO+D#|2uXrb~i+EqX^cB@=di}EtknXS9bayJoe|>)udb%Hyc5JU%-cQGS zN`q+|Z0~p2dJ!_)D06PL!OQ&)-BO;Fxia1);N?Mw8&_6&dDP{k*KM?dBw}f<%t>#;hxhjx4#x=RnDylu?myb)TQ|?~kAHX_ zKZuZ~!S4P^D!A9F7(ESoOo2>P1Ulx8^NU@W_}driej zIz`fHc8yhAV&`O=y+8h$FoHIw<8s_TK}ic?TIpmUi7A#!EUe5jNd&%I#VFP>3q}6( z-~WAT$qC)#m&`V*+AvHpNhI6NF%O^Z^6rhZtS>Zp{MB8~o;ydNYzAITH!}G4d*7ga z(&GNzEw0?S!i9?)eEH>9*p5xPQ6cnw5*>m{jWsMMow~Sk!W-vi>AA~daP*Y!$j5bD zR#sM7n5ok5b@9Ckg;EjIFw^O9k`P9bHY}IM+=}S5n{-xF@`AusbG)gI@5@8ytvrZhP?j}iAc4^IIJj5H1u<~W{ zPL)a|sJf6ZRx+W|6!Fodk*HJFtH`Vy1=p@zqA@eCO{XZjy`ElMT@qHV%)RF)j8BI2 z1`{4Wdr4;)poGKyuU^pa_L(zM&i+AQ@!_2vCZj$b&qekW|K=}#&dy;UWtaKq->T4l zdce`{9;S#H9KOWy2K4rZ1g)3E!e;%#d8*Ypa;}RvnGg&{7&H0I;bUq|mmU;XFD;{_ z;MSd8q!g5L7V9&44*d?ZPL+xtuvDtC+9=YUEAYjgCi0A{TZh{$)$?4ubcv_71|1_! zK|WVx@ysSa`{+}K?E@;VqXRz>W-h^Ta#%*p?u+Mao|$E3d6`m9kt7iSt7jGol*3Pd z{xNflZA={s*9318(d>BGg%W30=Q!>R+1hP$ES5QO9Xc~#awIyrwC8SQc^X!u&DKFf zw|Pv#5(v3LwN~b&KW2S>5rJl=R$#u7a`i1MefE6MXK|rMZMMN=G-htLL8V%v{l#Nu zt2u67zQW0{#xK8kf?-GsjXCZQ0X5@vOSvI)6 z)#BfO{*vGQevu!(f02Lp$xd1*3J`IG?zOmgyU+8-FW5M{#IY|4f*8|~7?w$rr0!UT zG*EVq&CONbxV+4VKmUa7QJ1+!1=j{|IHcX~(e4ac+BnPG-~S$dnDF%eUA%sb6Z`Bx zzRhvFM>WEz$NQpWJ%Dt$U9sE?vfQ9Lh6ueEQkvJhKDJdCB1+JUbb%7jH2z z8&FJ`Teh%r4h3QIygBBu`y3$!aja?eycF$;6Sfa}c>O*`@SH-uj?NV`$F+>=qT^G< zJ$)Y1iJVfJU=pB4eI}#%Qv`lmOvF)w-y4#v6tVL;CVqrrNTMj=>~fVi&NcWy{{1~F zMVBAExyE0AxzCHEA(7Hd{D{B{uyRgn7n{lXG@xRI??;50_F~##D5VG|9#V?bhF7bU zPLy%Sr>~2Hkf7VgE*8LbxwKTGTy(ho^n@f%C(h@V%Di)Zf$gIKkN3Lxu_k|f%*Dkb zZ?0EaoyqZFw@%8Gqu?04dwHIb7jf_D2|*C>gPVD- zu2uQvlNNf4^k($3X;TKTrXN!a;$P7ly-vBBj+;_p1d=RdP^B(j;?+ONE7Dw+gicCZ z(n;#7HqBSjLf{24Up#6OhY`h`!Om_Il%~}iGB{~79{Y?V*m~J!GV$@oJ`*qIjd$Lm zyK$C&r$yu~V^0uxjm;*G}yKEO&G_-lL-V9;=m`4vOPPa&z%|pC=;sd zD65Ja4~futeu&0Em<9-m5C-ImoLKXyTn=3{I1F6$(U^@JOE{57sZwR8UK2t}%2o-# zXme{n(WA%`{$xn4R;AHs==LZQU){aSQ7_`RYgIN^Q#*BKShS9JkcNqy%h7M0klM>j z3>^~%KI1STc1FOR^m**LpNcj)m)fAmMRjt_9k3s`P}C0h?L8edO9{$A_r2IOy8T5BPt z79z{+NO_lv%+mx-+BuhsuC6(W2!jcc>|;a;Iu1aXnL|awuT*WRaX3O)XyD5)@9>LX zd?>73jWAYX^WtTk@&c{)2q6T+fyb@ePq}z`oj>@`zQxD49e#V=@~1_@U;)nL6i}YW(t}TkO2p<=Ta1@}|H-5sb&o z7Hx_Jhp`_C`a=q40aS!mA#vyBNuPn zBl3nw35GOC!ZBg!Vdzl%;{jo8(Cd2miR6dhy^0c&g?fSQ{T8!x73OA2>>dwj_dPD3 zox_VX&-PmxZDoqar3Fn8rgXcz51;e=*>j}juyfF4;#W{XjMQ-0Z1XSw@c$%9V!S}n z>&G}%%{Q;FQz_?Y4N}C$FbqC@*hFSUYs$Zt88SI-XjAmXJROwDUztF?c4J~m=yWIC zdlqwjqk$HZyE{Ez9QD$$E}iBSAOx*WpZiZ=ie_g_yL~LWy*|1;hcrw^lYl#qb{Gc{ zVHmQ#yAM$&I295hrQbF) zkR*y;yN!q=Y!$FvvH0f2c|QN*5wqnIkDl!CS3moLQmxAOzI6>l3i7tWH!jTc;Ndpk zdux-?aDpF89zARFXzPUB;tC^QU`8Q7c>g->&LXYj6DkFVM>}oiY6Y4DkG+i{pOHdF5v2wb;3bF7^g**N`sG)rbM_d zQW#ja#qL3e-eAl(&MuO-G=KQ7{#WXi9RKvc`ez)pC+u|tf+)uKJ?2Xm@BZ*QYjZjJ z$Gf~RhrIjVw{;>+UJf)J72#v1oNNWAWzro5v<5x}CoODGx+89^*U~g=oiJ0f*=mxy z<&X-@{TM!Z(!!hgEX))r7ad&3VrHg7pakPU@oayHY1*hHb+$Wq^%6(>2i!hM*zy)J zmy1M=iyXv7ti|iBU%tdiZ-U5GS$pG~1cNSN98fvG3K}Mb3YEqjl}eFj-^Ys*gk=${ zByEf|j0R&o%fhrBgrTuai_plEm?lvqF=cYf$<|t9mUuZzuji5IZmmuLNW*xpFZwz()YQ#UgNzBb@sa!;Wet`l3Bptp zWIG%kwJ|a$;ZMJOMx|h(l7u+X_~g-6!d`Psv+JW2gs~!sQ>z#i$EjZCb+d!1W+%$D zF4CJYly2Vv)lw8V97u3uW_>GlDkg2j!C*z0S|6{XHOHb$;W`0z-W zDir;3$Vs`%`o#H}*Z;>Guab-#r9ray~4uc0+s3vC+!}!**S{!6`t&m*lqT}a#&iKV{LVwR(H(qZW9$H42J=K@|U0E zx-NzkM4^v19Y&Gl?pB95iZP5P!YP1?u}6Dcs?AZrBk?E96b)*|h`+w|OGJGQ>8?SN zkk7j~u0b44Fts91lGJ%aN>C9mws*ODc8-7W)&jE?7gtX(OlZ{0kVJUnA-!%F+cvrX z)fThm3OoC4!h>IZr9Fw5M3O)G`7P>n zI3C3O;?`4+k57<>jcFJZ3(v3}3&$;r7q=ecEM7#JnqNM8$^3kSu^(ZY64Nm7!kGQm zHi?4n(C4tXPpn|*#TZhYI(R58Ql~E=NR%Rs6Joc3AuYThLC0y(lTw;V5RR-gp# z%q&4mG3fRw)T#un3E^bOx8J^q7X;k-@*#J=e8@N7zQ)eZ0mELOD1qI~w)Ts=kNM_1 z*I8eGk8u$5vyZ-_+Zj=5%+Tu&2#=1*&Ca5X3dj5VT-%((+`Pb}Cwn~DIw88e02@K% zzCm-CT0?45*4RPYLrRI|x*T)^K6!AEKHnlUC9rHnt_Wes$cy;p!y|Gtv$(EJs9qu3 zah#BhC&W=ilsVyCK2zcQH|7~ne54AQug~)1_b#!2GT<+N`3#lBxcMTTNDzA?5--5_ zeIg|Yqd-8&aHKHm3v~M-Cw-6iuP^fActn5fvo=@es5RoSJz=Ke@YVg7G&>$=mn*ae zDe``r=b#}}il+xd&~VV}a(BCjW1EC=LVG+wFeD1od=Y`7;kH?DBMhUAAI11)m3*zt zBq`AKOziR;&$^23{XGh<$+dIyRB{$c;DKQw$qF>fU>L+G1k3YPwh#MkE|z)w;w%Tv zKFz#fd9lXb=N+z{onfw?=d*`Rmgh>uN^|>ZI|I^F(XEgY%Mz)`Jfk}a(y4-7a4|@2 zIHjIs4Ssr`TDE~@8);Fi!4DJG=1XiYmHF`g5id_X3Y9WS!`zw z)~tz;Q}j~`EX%|)vjlO-3K%03#b*VxNQ>?ih0ef^Y`-xblfrC+I8m(47m-5nWUrH+ z5kjOHJxI0>2UwOxrDRgbnUwMl)q+jQkw_IY98RcOf*;;kV7ocu!ETQr)>xL2A>Qft zF&#N*t#ECF-q6SM0z?#J*d|9kkE8a8YwI;mdj6?41;~mmaVk0{{To6-7z79b)->}Y zvky;YVwn~v{eg7<%es&$z?DQHhLmV+OgG5%y`z}e^T05X!U3HiMdo@YVSS}WHDAFH zDP7KxG8L<9jS{IoLFm-V*D$OUt=4h+T}dO;n8az5XqX6*o)=n!uhI}tDFl|#7%~lf zv`vE~R`iA*j^ltSGxw+nl_>HB7pcJyLrkIZy#UYm(;O)~r4724fo-HsitXeX1rhaX z5yv)35{(xn_VCP)s>m?kak%pu<_VHs)!LnTt%rfCu<5js&MnRTt@2*PB77bN8E3Nv;> z%hkH%7~*%of0J&nkB&o8a2;~_0{3@X7(|>~U*aGB`1_bD)N4z1p@8MN8m472P;r;tY)29|5-*@_ew<{jL=!Nt`okCPBfg5fyi zixno5F>#`ZwLXhzGH?CsZ21yh$?)Uiei+yskz~!^&(9*(jEUsQ$=hhdG`26l32S-hI zcUmZSo?A~&#NqH3k9NA8zp+WZW;PYW1ONaa07*naRAYz;6~%Z*W0I`EN|G#1RcLgQ zu)D7b_VZYVCJaJ^VG?698jkpPfA%wiL@<~ns0YvKbO!wJyEmzxUF9op!dJZ`Y(rs} zuQ72oNQ)$nX&yFl9Y-j+z}sgpviGb<5{;RiU*qNSbq13G(l%)g`-C&+&?2>?JqSJA zL{K%0B#y(|=P$9_4jK50!G1qQ_5D=?$6Oo2w5=JQ^H8u5TdN!v;P9ik^WK3Mp z2x$-}3d77{XqP0(u8V+jrH;~yFw#_g6WbKTNlct5ia8r01$oz`QL^Zb6A~Z@Gn+$0 zq%?=@&7+A===(UO0;V;cpiNm$uci;-#AD-Z72l8f;}5qYp9FXS^iUz@Zjvj>kNG_8FB@fu3(L z9`t$mNMbh@C>LF{Rz$I6>#(09WYQop48GhQrH^ZtZVVE;G0WAftDvA%F5tKpy^NwU z1sDVZC!fP|>bQ*=?3~HZ?!V;d#Z$D_c*XM^MS1?!zy1pjTSMBa#5?OZSY4Xs%uJDw zKKKQ_mFq-q6(e8PXI2))JLenp z`(v(c)Ofbr=Kix2HkQiF)^g02O;%=epcR|*c^pTO=(IqTDx;ia4}%sNRZ_p2%%$6G z=8dKF>9Zq58kngv6k7-gqJ-6Yfwj3JKmB5d$Ga_DHrHG%(AhJS6$jla33lgEI6f7>T)_C}$&De|5 zW+|CI^XU&a3Kl7*tP#ZMIMvtW%!p|Jkdt^o zu{J|w=g`8ybscOo)%rx5)DBik?0h~$u(R(ePDoVNL`ex)fJEvPHMbQ+DoFz{bv9Iv zJPacZCrw6UMq`60Nr)AMen2$tQ?M0=NC=|@$8iWI6UM%WX_=IAc?<)FD#A|3EI6*i z#19xc4vuA_lZc5QVo8-|=;#94%yX2pA&C(J#z9OJr;`jzYTP%kk~e4Zya+!^#IuKw zc=CLgFiRL$Nt*v5kVFZo53-6#;(#a!((_(O&}jfMq(G}-nk3j5(ju2Hu(?>KVj&z6 zu~;v%RL^JBEs2UlWD??s32_wjy=%+3jxC}%qSNgWg+5B!+1&OH?4J0QJgv<mn({_Urf z>UG|^d4-exJ(4J3ZFPpPzIx20cLL#rsK3u}A{idp7^qn> zLnpO$;hx##?TZBpuEWDe&yh0Stb^eg0T`Bp5Sjg?N+3zdm5Us=hWNgh7H^3L!^A2S z@r?pbF;8pa;k8>>Bz*GG=hS8zgpt7aayYie$=337fnjl=^ZeNtha7ju zNGaKV*`{7AF*YEUnnKm2;ug`Ci?AG2HeS^zWE61k=@C1f2rJVs1hK-B62nXnUOW31 zw9=W|3a7>NDZrnhlSvFYx5&BkD=f`5v>zuT5jLIu04*JaX){}!;TzX4k_r05vDdufgs$=$6s_a7Y~4U>GOaOy6lHN;6m97dR7N;{dN zw^Pw78j>hs(&?hSGPYf3VWyPYElR=c$~@<9TuC(!V;|cxsMKn_d-E!1*H<`fwt4dS zF}r>VnaiOKlQS!G+;$^>I7v- zLZvaB9RKt?n{-D$KfUvkL?!9HljS!UBEhNEP)-3~N!B-(nf&O-Oojs{p`ze;C`Zt) zx;Qn-joCU*E=L&n)bfH@NO}{+!Tw7c-jKuAgo9S1tBVU9HBW?&Ba{~8^A2a`OKczZ zK?|y7mv-Od%wm;|CBa^^$AvQu`s0X)yWLaW7C`FslI}$*{X=Akcy<6Ar-A`A;N*+w zYMp4<1H+~;yFj8fj7PX`9$jgGOsO5VV{x?e0$WAsK^LpPhj+3^(8=S>tmDj|6XCc_ zVp>>9fNKhdUW~9TCUHu8@%)JHDB`^_Ym1a35Nvboc6>Yw8ahCSbWBX`?Atfq_QAt{u0E9xabL{aW+u)t^ zGi)F9NMeDorY=^10+plza8qJ#nx6q6&`AnZNhy(rOeaFqQGgKH`zn;uTwQMvL@_%j zBP`oQqDh%jnpkNv8zsCT=D~|DN8L$g>LrMRm}cjg-~GV_I>V5^y8V*#t99PK(BR@q znLFEE4mutp$)-gd@0k8vdK(HP>Qv7mrr#5(usgeQD4ifM5Ts3r5-~(^b}q;0V1UfS zDD-&o@HS4lg6Wn)SO_E4(wWjkp90!x=E+oKoFoZxoTB}PVPaSoLTHMGJc-iudV}=y z%XAu%c@mbx;Vk_x1b;zUFmv=V3)BXxwWCd`(N)FCU0(%-=_G29$cn8(WJ8IJl0 zEf@^CNRcua!Z5(L9sJ3Je!q`D8Dp9TR&9wmzf7X7R0}g5Jp*wZa^vzk^;(T`u|yb0 zm?|M>OPYs=_+dh-rg`OApU{O^DA0XfHFO#dzQ+CSBmT$#>3`<>l})OZGTrWw$f>b>=?#_^ zXXp*av;vcrr3NDMczCc&&b2AmOEfzsODl_5uEWXU0nubc6!?U89$j35!ZNjvaEtruVzQaX0tFfBVB`>F)XfFR1C5a8&j z$;R3m@BY^Nn5M<)mn)t3OT=ArLt`5V!;u64?jjK&42ORZOq54zW&@{+Q{2J#oiDMS$D$LeaxwKK>{kJYM@?stM6A_mr*762X z%b?+JbMwj>T`K1JVA!QzD~rYTHU9k57uZJ1Ub-D6%r}bEDn<5MBVHa)FibN=Tc@~5 z_PH$A!7!~9mFBcgNhw*=16vAAH^<2!;<{t<{`DoIL{TrKHo|XQT;ilVV(*~KnawJb zoe@FzP!G(m7`J*X&sA7ix_-A61~31%4`7@1+;r@;#gBFnS67z!i+JXR+5bBGhA3H^Z$MD zIgM(bvZF}?kIu<4e(MEJ+{Nz?(MiIjwMS(7^j{jx*GrgAfx4B)lmfRli>t=iQc*Tz za)!r~2frXX+$S9NIcYs1Uz^2{lBXZ-bMC?g=2ka|49F)F7H0FjwWLW-p5Ph^qdd#X zIS-mii7$4Gpeuu?sjk8x)1-Y2rqYfuSgXNhbZ=IiE z=V(9@CEUC?Pj?tlv?SlXI*UN?ubW*g0dHro>rbLIsXIffPYn&G1$27DpZ@oBSWBvz z$jvQ~R4Pc*!pzwiNX%Lz6X$BAO3*?RM2fsn{MMy9auP6CzQV~%TiZ@fRF^KYJ2L6p zCIdg@xHV+=XviDqXPKWVG8_lgN-okg82K?f$3q_PwppAhgZoTi{1GSJ*r3Fc|q1@-C|F5e_CKzDHrE zhBQpx*r>DE$kXhMxVl#1TNfLA@~Dlr41^)jNlGzF;+PCrq*=b1#Sp!Z;PrE3i!ym1uG~ zi+8WAFb)##JZ}+bgD@Lo7>T8WOED zjNCAJ(HyZdSLFOkl{;H)q-8MWkDl%YLLx~}8HGh;Vuk7S2~y?{r_EXF@+ZYKCnbaD zGA)S6rX{DnjZ(-YO5ZbeDL}^|T1BY914m-!Y=l)HNdz+XF=T`xY*ZwPF}2bfAvIcS zQ7AO1l=FnX&)AEY42Ni?aC3P?lCZH@<;`oG+baf}y4IBp)tPAzo9IL0v}Obd$jGU2evQTHX=O6a>UxTd^WAsP)9#IEx4YP;MLd}>w=&1?{p5QbT%OaFg5>4yj_3`B zy!+M-e*B%csg%pv`DvWy>DZ2e?Ys&}Op+v<$W0pzdAfhRKK&3vz6uA@r>mFaPzxDdM0r?FpTGKi)O(mtN(Wy;hx@3lqr`aHL zGc)9KIllbj7C{)ZyZZvifPeD4|A^VyM&@7sdJ{5*^RgRWYr6djM_r#%xy&$jD4TU8 z1%{ Yr*cdVKuJ12)gE)9H$-x5Tj0t#%e*VHAxh3`QiqRxmi{g>wNyj6Z)M2*Dqb>Ots2~ zcV7}=fyk1Hrxbu`g6(t!BC-Li6fDgYsYew$qY*#*-~*8)3AR&ZVZK6rxk6N2VEm%V zXP%OLFFt27Z8NUbt6{v~JA_X^t4c+1rI{Kp2MPbz&z@kLCUKGq2v_IJ2qAd5-NrH`GqnP7IK#*f`RKDP z8Z)z8x^$5fa>TYlb!mqAIhQ+MeI-mou)ev8m^cgusnw;Gb1`fu)3cwFNK#6hDRIli zG*nThji(<(oL??;`M1`%_4tUsuW(8Q3@Ny@Qf5XqS$D^LV`D|P`mxw@OB?!*Ali z{RM6^;>HULRHi4qd3(WJy}Zol2Sf2_(BtZIz(>!f_^zT+aror%3CE{HetGv8zY-!{ z>*_A0w7x#tiUTax113>Mo*V8zYvU-zN@%?<&<=;^W7>lWxfWzb;ou;%Dc3HCTw1=( z-ebkmQWN7gdD5HWItsMr(n^KVIN@g>?xU1Lz2Z>`94fwKG>lM=#B*Ktj{98OXi)JK z{Yg5XJD7K*nI((z;%g!1&$k>&LSvAQ!g1>q(Uh#)0VNPY1L69ZqD(xs!F42=6Y|&Z ze8Qsa;OU4gjq$>eu(!`{RHwSp zGnK1Z+*huLaBPR)a>r)f)>2sz!|m-B`|Sy5{lw0rm7lkK^T`WMmZap$CDWElDrTBd zy5JkPRtS{lrym{AkF-_NQ-UZr+}j`UwHq!!dUch&D46DgyL&zMPsg0~r%d7kw3RS+ z9Ct2?5oHAr_XfOnbA{cbKAqkK&yhI3YvZ;kWrVSNATLr&`;(%am6;W^_POM7gp>-` z_e(z%D-NKICX1&aghf&8rb5ax87!Chq~lq0K-WP^JDZUg zX-P>=guqg<1XiwCNeE0PLMkMaE+Z4;2O-g9%y7`BC55izffiH6IfA$IJg5jWNX=qCF^_Opw zq&Zod&}!6(;)p28a6J#laj4g7C`aK+sDuGQ5VC)8#QNqsVGuGJjff{Bq!2WkHCl^{ zJlj3s{=K`Tg^O^jjCF`c5zBygAGYb99f)hq+*FfG^z4Kzi8(m#vAwa#OSdm`(wp$R-@L}vtp&0qrBMkPPa~vqn8XRY&z=&s_eDA# zFpZ|facuXCfIN#Siqx_;WXX;&1x1!%j7BJllr9*J)&;uIR&ZpF?{>`gcM_X)P*}-uGv$Jzmc&=h`Y0c=O5a!?5isfdf?0zHI*xI7NnqswkL)Ml8 zoLXR%;|c9}XfNR4JY(62@X*10{<^Mb(j@nu4E_K3|FUZJzqWITzPjGiJ5WD|!;nzQuc%d{Ww zGiEDH2j)l{ak0P{bp9xC()gjyr_gTVNnb6DrE!WD_Rs3@@E>^7JX=+v{v!+T!Q^Q}9B(g%wh* zo};CdKhK_12}u}Xr59_BIt@n}R|_F>P1OVpVoTRhN>OPn;neH+Zj-uSVQ`+&XoOsD zF7T5N_o!C`zWdrXho=L6b^n-ey}rYnH&^*r?>@Df`X$71LCct3l$rf=@oSWdMrCKF z8o0c1bCn0XUD~|~zxVYkY%YdGnU%o3`_yW?$I@q<8?kovWfM&!F`33xmjfn7&`%7H zkNQ+=Tco<6+mG=VTIhl8IXjL*c%tNQo9C|4UYF;W1zpK~H(HaV8E2g#{ZT}v8Ze49 zjxsbtK{4p_yWhXcLPK$R*&)#p8*454QO@RSgUtnpeLps@zVec}_xPBjc3Vg(ALIrE+?sd|bmO?ma^27^rS=%7cT0c8^| zV=;Vt$N@{uklm9$QYns~J>u=R-eGZbhgZJ&4GJSUAH_II;fDd}2Jd~*XK#0xR?Q=h zA{=Lkak>ngb#5<05V#z*N4&7n;z!@T%I?{i)mBKe;&R*>5$B+^<{NibNYjF0lv?#3 z$-MZOujj-BW{Aj~;wNnK_xuZz_Rfj+9zxs)DGAnJAlP^TBh~!-jiZcLZeB(DF43@0 zT%`DZATlM$9G{j~V|{gr0teUkiL~LUJGF!A28PoV$MYx>>%c6%fRkyClsT?DYZ{b8 z+pddTQ03*$il}nGhCZ&pf**#+(Rlv((%jIh`~3blZZMpty!G*6X)Y&t{rU>E(4EWZ z=7r|QR)e$dm`3QbTyr@e#GIUu*<7q3)H3frII~01QlcD1=s9>!b}?Knuw8P`L8=NR zQ}1HH)d0efra3!nbyk`oKmFvmoI0ZHwAyQTm2H^hNk&+;h0ioD>>NT~@bU{S8iC?3 zes+&YRk*aZ#O88^rMgexDU!5cIEnZ_|K$gG6ukWEHCk1dr^klj)HaFGkVOeW)gmEa zO*)Tz5m!bDFTT*?Z%+H9sloGIq?kds7M+q(kj1H`VJc;XCj`vY^C$&3W^^bU=Ir}o zOo3GD;@;?T_+00f4yX+}%`tg4FG$D}1O<7Pkj8e%TnmZOl19D3Vns3@_Q=v0uqd6B z3N!5yO{~1Pt0YoEnr4<(l}%Z$UZH<}O84Y|y3$CcQJ%z6U`&RV2H{JxEXSA>gdxsj zq)~)nV7FTl;Y0(3)Hseuqq#!p2b`W9(CxHoEg6*4Bu_0{Ck!eCflX!&f;gJa8wA4G z*kTamX@aMxTy9D#HANV@C@Bf6H3Y_F$v}9n!$Qq7MS+Ooh{eSgj+AtJeO8vMOeT`^ zUYEcvNV0^ga*UKNSsIHZ9}}tt>TX6hYLks%G9IDx6xVZ^Z*k+>S45bn$n!^RuC}dgge%_jQ? zhong+dc6+Ha=`XL z6P{z0jD)1f3!3$Sm4zyow$?Z}?Gpwejin_vb}~|Y5Q3_wXtz(O`YxujNM`02#JsCt zX4aMwB`AzwN`=4pbWg0WHi(mg{$RkBn>U%J2BSTm_7y`V2!a-)lQGriB5^JViX7il zyncI=TIllUUoLSM*Z=?^07*naRJ1uA6-?ut)s~OKIssp}B9{q@ey*iEqsx?E+RCov z{bmKXudQ-zqsh;H^_1I}7rA|Tfj|4%eWq!_kG^-CB&u>Y%IGB(9^GxTwCISzU_!NC zrEYSPA|ux|K6%`yRr86H0;2?LQqmvCIIfy^H|J}{Z7;j(%XeGqw%jc_<|v8IQzO%n=$wo(P7P&JbZ+ShCY>-Hc11QF(CwTu8up1M zmPbFFBs}n@xqhX^ zV4QGzK4vgU8BTMeIAb)-kr*CFhg{!k@b#NZT-$1L_i2Z{lkpsV*7F94AuSB|o}Tl) z*EiX@yu@K=JfG_T?0`8X9nbY`bEH%d)a7TkdrzXgz$S&W2d(q+{@9p4cbGS}tFMa; zgNr~=WC?kiBZNlkv_u{aqkf-c(6@-TBT6cyO&W)TK7(EtVTw8G^d*%eW00jZtE&X|&t?TwEDBIM(3i2H(1zwh ziz`=e5$6uVu_7zB{+Bqu58)DLQ-?r;s;$zWCftAclu_=2sxeIA(eUn_TDZ_ts3p~5w0{e>J_3SqtI5OKF(9~;MqCbtxGgF1?llF(cqlp;}dpw zpHi(>$&#s^8PeLKr)5!Wiw*(CQmAH*_DWfFOY5xMuX0|He2H=>%J*40fNiMG_o(z8 zB^=+rxXkD>U#)-3`l=W^bkklC|=z>_#+zs^A?q-?-;MD4fpoa7Uq|r1Md|rETi|HidxHIC;wRJM(vE|oTTwmnjewV={N1zy= zo!~DS{6>phNQ$!i$8%|!5CYe+9Ox4VCQ*g6V@;78glf^6PamB!j0)D4>ReiD@Nl+!yU}6cZ zIE=hFr1Lz-cLbMKYV2$@dANVhv(qVI=u_mHEX(-#i*pS zPg&dE;$MFBkmax~r0dgjH@SZ{M%G#!^1_eA{kgD2EmOLRsV-FBNio|?ns zbD?!Xwb2k;S2E-Ht4Nt3q{aw|b}IbyUwk1LJjUdyD00n{r~A0o2GMvzp>}zCHm2X} zQhypDR<05U3w+Vdsch}=lP{i#`avJRzRbB;WUtdfYwNhY+NuyJ7!9UWeTTKC$FbIP zXJUa3ra5qTuTP$)h;g6Z=bw=rKgHE!+6RyM<@=u_M8M|XNw2o*PqTNxU_0!(0Fx#R&mV#lV7ue0^cKmGQZh|)9#2v`Y%PTK)j?BaIY~F7 zNK=Beit#)a8v#r8faCUv+-TNY0kIJ1T;nJ~nj1n_QK@+h#>t$IZJx_~^-QrxnYqxQ zkP@j4j-sSD+Cs*Y@V!^J(0RdIA03ekiQ`z5wI3CH__)jN*_cj0CMzYcb8Q$+3$AR` zG1~C)<8w}i8A%53-#_8E-?+>)Dfn!+SKi}`*Fgw*;ctPkwZ!xB#ZanrX|8WC;3>g_ zXWcK+mgb6g+Rz`TT)(tHs}a%}XI%Fb8w);rrz37`uh5;QJZne1bbEtWudnd--4k}( z7X7gdQ>*e;Y1R=!5MlUucgS8R=GOKCzxnby$D0u!KRKsA$#8{a2F`j)&>bZ_JsNWB zg+)4}m}1tQ$IJ)NXOhEn5N*~JC~1A7EDVJ(n4(lP6J@dX<&wChs$HCyrc|CRgn*(b zIljiabT=C;wi=8Ey^C3_EFnqltYZ{KP^1_$GXehc)-Nv}V+^r!_{ID8$n%`uaLnBJ z66WT87Z)i?l`rN^AuEI+N;)QJQ?RN1iK^V?R*koBsQDk)5XQXLHrBcE5 zd{h#X#0hC)jgPCfCjRn1wc}|+8BuUClW;wUEm$*)0pNpYX!PKQkk`<!|9^rTaD~*uOAVO-}d5VkyRW?0c zJ6sM1uM&_aV?sv}jT5?0AMy|X)8FTZKlmQQY05ax`S9)+>>r(S>xC^=7Mm1W^Ygdf z=AZu4|A8zTu)O5qr(F)d=%ck^ba={fyOc9ECEZF;dL)?gP?ZR6uVJ*%Bn*9e!V>|Iai> z)te-^JUN|^WjRG<0h1Q!JSOR!VunLhwSlTP(X%1L=a+;yw{oXRlu{(No1!DHAT z;(87hUy+Ur@~X#Vk`wp^neh1Fi!OU-6EKGJL5vZKXd3a;cOP*&%#h0YH#zywb>?)T zNlF)GH}EY_RnEHoRxb77VULZa3g3V83jJ}+FF!saD4Gr0 zu0vcD9CRW?W(S z?Zyhf`0R+$WQny_h5jI7tySTz&rYa@E-znQ=A8$pJUtoVc=l+YCHKOBDVqjLNQCFo zk8<9=cgE$V3a?&WpQ~&-eNyxwb>;C35h1zsGOCd6~;=4W1m2@Ma2v!dMZC z5+E>wxkr*^Z5o@Dm&5lns-i{n4aSJ)_M=VygfUhIx1_yX%qVF)ccir~;*hw0NPVG& zPzsZ0*t(`b2nWkDQ20U3QpD11mS&gn-p1dV^lF;re01-zy+>|nuX!Hiv_&lD&9t&_ zHGiK>Iltjp$zw;Mi;N^mI6TGVR2Z4_<0;L=r-$zLYqciHY zDx=|m@nl@iR@xk7mcs}Pd7hD#%}jJ*XKiLnNKigdJoje}MOIKKgK|CYKRcm_#elWji)?2nb<-|N&?>pT`)}xtGFetxt}gHj;oLgbWxy{LgxjG z%^JV^otLPqgqLq_Gwz*m-ag}KVED;9_h@(pjjD^Quu5xE+1VP$daumnm~F$tDqtnq zEElu0RTgov2$ka~#0&{@99+kt5(Lz16_hilibvxj`K!}G{}*MV_tpA4uCEG^U$b@~ zca`YIh)7At6BMAqQ6*Gd1})EXnM|gfbOs2=H{Gc#q{gI$BZN>0QOx%6C)Jz^G|r=dW+S~6`EB^6lH90wD`;SpR%$L@cPYl_Krgq zY5|ps&tJUrl<71tzrQZ26n4l@Vr3MORy8HbGlY;tamKS}&xj|lQ*m7?Rmu0?xIyv8 zEn2mZD2_Pm^w@j)h%_3ZgrIZY=k&Bgnq@*siR*f_s;b0w%1>$eQdaiUa*NPfSbpzx zz+`F&9Z67jHp|&eaLZyXA2T>jhzA(%Tr6YxVP7*5_C=5Su55Go;Ees#gi(|rl!LU*>XNW%THnW~;($H&)5=lu8)VAC74?7J2{OXN<-<#&!ApaEL0+ zMf0pomb4)rPeDk2{>d?cE14!42mPEZ&#hp$W8CFU zM7>2}?B3EwvluFV`1&S$PoJ>&_z^{t5||7VN?bExdiE5r+Tfcn-Qll4=%GBxcV53t zcaqQ>rR=QNIP1rpbf;WiYw+R2GhVy4#Kv-sw>~@J@Z3tQV)VSTejz6C6-^&FtjQThbLV&76TS)9w+A`nzb5NR;yfFukou-pV^4=92zjAi|HJU zQ}VG&w|A{I@g%}b1|&&l>0!dq8$~=i=+PNO6j6*&3eQm`VpNnf8-h4aD55D9&$r$a zQjq1=KcUc?B2IAq0Oh+pZAT1~6Oz32O3Jl0J}a9{vws&^K{guVcn&HI=k%I9&A4-Y zjnOpai~Sx&UXVm7Zs6PZX;uINlX1kmAMNo6fA1B3=WE;4DlP|SBTHQZiY(`qofe}g z0Hc~&EI1#l6-5VW)m!>6bHSSlV2UOvsUA^>nm)pRQceG4kx`S1p?2JOtPHM z_xs%0S>mJ@6Q>1^pqx>d3G`VsW9Bh}p+rcmX`v8Sme?Xg(n`CRG#5Feq8ej`4Zw;A zNL3CA3rnRUEj!VGkfmX&Rctd^#tcq&m5tqnHYmqsp;0GJ)4A;K40$%j;FPLK<4HuC z&${4pj^+pzd~k~o^; zx}GhfJ8hKXv9z|y&h?ud?(WiVpOY7mrllcio|6?ho6RQMTPtE~eVL`@MRcJFJ%?U@ zKom{ro}V)u_KBm2YOO}KT4!--nWfcLbWz}WK8~Y!c>gY(p5S_(6%ENUiXtxyMU6}q znyjoO6*|+UIv39sh;~m|;SF#-hg1m=4(G#^pSF)#t_JwNLt20ngdFx__Rf#&pK~0P zYyW;-Xadi{6;=sOKYs=aJB#FLO_W+c5XX_|e9GbB5#gF;JN?#geitg6B&N>96Fk~` zXk>aKL^=W|Brau(jn2t)i;8%jOOY3tA|>=Cz8BExoUyvR%;xqBfF$ocxKw|M#Xbu%0de)9R@@&Eka|JVQJW4>DdPV1`zRn@qX1y1?RMlfhDeC?;Z|=2#xH4W+a1dcn75 zW(pEHsIeobfb6lpKB`1W9h#I~${P z#@1Q`EnTYX+g!aAGVZnc)hADp%HzqCeeQksnAkYDfk#lOBK#^sDZ1mBqoXr)8nM0P zvFHmHoRn*;iwp)so;=>?+pphXeQl9@kI#7Wtb^+Zgw3kuf}3)n-LVBk8s}trfpP@n zG-sMiq);S@#w&UKYDOWEifl9{^ebrLkZW5Mnc4#0I6==B9FjVgoTlx85g zvJ_Bp1yABT}kJw9XY%2g_^%Szp+)0=QBDZf{rq~~FZ?|t}S;~Fqc#6tWljrKFIfvb?h8W+aUJrS>QRU#w zVHD@AE!9|EtUz8MlvAowF{hdV=)7SIamPgnXoenvZ<`4=aV}?1%4nBqjS>Ry)-ub@ zkdwP7W&E1w!8pE$SX;B|P-XB-l8p6Mz}8BYU*0=GNJ*txLpYK&*Er=swrx-df@YJU z(Y*iQgjcVxaMGEucRC`^3)$1r+3%ppo9 zkkY~N1jZChr&C9kKU#^9DB2afA#~T9L0DvDCeH+Gifa}d13n!^=1=CDLU;l9%2hCJLgf9EDY<( za>3NNFq+g>c9B_8Z4oa?n&qTvit9G5S!VeHSp_voDiwZEC65v`xt)`8RQVj#e9s7> z7)~O>&_g=P8s3(PfDn)s8s!D3s)xyQgi>Tw_}TqaJh5bUwwA@pQj7oWKYW3}^GMT( zX9t_S{oy_H(ZfSws_Q&C9n&2SW=uJQ05LJ>LW?|^a=Bjc@Bj9j#ud5nJjLa$O@ztt z!a5&)e#i%pd$jWqAv{E?2}OWNQbye_TQ@wuzqC9ZM$wP|yZ`FH_!VERf9Lg80rI!3 z<<;e*-MuHrnbw59L!q;aAZj#1Dt4}2V`=>oZ@v2=l1#k))4#&a2mF(N^51afg==JK zUVb-$lvaOxHl#Q6dN@5F^48rmWOIXX`3k;Rp)itKy@qrop|8+|W-ywf%_0kp3bnvR zYdgd^jZ-{Fu-pu3pHF!6&MJ=UaPMgcM_E&zqxOg!S6aAAa#Hu$S-D2PKjiH5Um4H$ zL^K|dOokY&`pML_9h>QNilbn8X@MtC1jw@c!9|~Mmdq4|?Xu0F`xybi%$!3J7iMSJ z!96+e{)_p6HG{{~BqE!}er zx*$(7l=3gGwKOPGVU=V$K_rnKigZ1+uz^`86LkB4RxPB_S|Xkd$c7yj8zEt9nRb7| z)My-O(S*EvLQNR1TwX>C!yrDTD#sY7LU-6hR~k6g1quT=l3FdG$O{&l0dbt6q{Q_c zdgF9P445C9N>b|X%lRQ{OgXRe92ZI|Vf_wD&XkalkA~!<4xTc2N?=A)Ofp5))-lP5 zUTsF;Za)tE;X{|ARcs(YeMXIliza zgnMUW{;!`tB1){vnmA1?q%R~I+ewxvYYbU}UAimi>4YfS;OdoC;yhz;a?D_G z!mUe-tgJ3m^)%nU>@%7~O!JJRZXdCkGrIq2ASieInuF%zIk5YI+psPT!*kxvqOx|g-VYll-PTbO(*!38bNEB z>De)+eTH^?3hA=3xy;S&Wn5*DLbH1wvwJ$?#zuonOCecSu(`Z|iaK0b4)~+rd7W0X z!IMwlqPu&@?|p5XYd5d)*Ivwk8G5C;+zLqIh=rQZ%2J*8@1M}?Pq?T>=^7da~JaC3Qy zYO%(@(g`)s@bdL_K7V$~vpfPRIU8m?J>I2S@wu|m!gVB-NR2^0vyLSHD*P`?1x|RF@?vYqcLlXA(e_he_v+zVKzW4%OtrlV2nVxC8A|) zGMi+!0JVRKEE`AmPU=#6R|-KS1xLLe=i|&8p3N>+TEu*od?5ryZW~Ci-&p0iJLRkw zq1=nP8_Lh7wIMHTaw{DVAq4y95r^HqIbwj6eE3D1c0XdAXwG`El`Gb|R8FFN#xttt z#XS)6qWdF^MZA>j5ak7TpY=FBpK@zwiSNI~-TgG}*o~Ht}z9|ILH!>G(uR3WCT*VrJrNTOfVP2%0}y1u02P^bWxxs zNUY3umSt4JkV>t}BzEA8uu|=aFgdj@c5>MKp zZ(~ghlU$Satwe_rHqOsb_F23U(lQ7NZ5WrcV`8><%Ck-wh|{uBrEDWi`c=}}BJUr? zVs|tkd^%<^lr%%Zcr;>~BF-kR3D#dEmOc#5FsUj{JQ1KN%6T9aE_0fW`OA-v#ntN=dxsOcY6TTm%KIQlrNR^v?bl7NJP{>H=X}uH<*UK-|6l8?0_1O5 zX%Nd)gq1AMs31``qLC&US)L=MLl{;u#&CSvMxu#Qn8b$3G@VP)f(u9t$_6>?0bq>5 z^ISGBZ{sgKq6ijonrq1BvJDEZ;?c>NdwX3PwZIzV)dQ-5!^&b6={UUg@d5RkPbKu( zJ?yYpb9nXI5?P_Cc=iD|Yd-(SUv+SW=8YSxOxCMhU9Iu{r;j<#bHX6t?x!D_csdk! zUilhHn(^$}6VBTwj3*JpX-bi0HfYQYc%D0qXaDVa91u{3$YcEj+G|AQZ}w%X!@Pwp}uxP0yPm#8l+^S}T3d;F`9 z4iVKRS{oMX0aq`z2pz#<-Q$CM`+Vp1ZT7n{Z+&!V=@icmSV%ET5^T+3yL;t9C+%QA z&vk%}v5v`wE|AHDAH8vz*Ke%zY4C@r8U~{QT)sw6=D?Hji=jl<*|Ew&j0wwKjt8b(9(r0;XnF=uklAec$1&J^)~074&VOf z4)xX&XT33}2M63gp77xO42)oPy#)fQ6`xU*vrzY0U951_nJ}CrNGb6G_aY!XHz;JJ zz-u&!+9wEU@LOx>m35-d8D==5$TMDkW0NZjntLCAg33oE=P_;(k|!`ZPAH^H7{1ER zm2H0YvoU}2&;Ej)?JdsE#}vlpm+!pCJMaC94-B?sS)@BWvTo2q%!@km3;A86 zO_}V^8cVi;V!;>Nb=SH?C=ga&S6a7tKL{z(2Dy+nHcN#chF0k+iAcurydeTs>Bv69 zi`j1fOBjJu^8f9bAj?5=J^wRWm+S^%8)rq4v$nCtn751&{`A4DOpx98V;CF$K-iNl4z2nLjvDpJQ~tzw*f<6 zNS2mYP>!8D)VaN0Ar(?XVe;~sSoJoo3k>#N*qc$JkIeR^pxIocGbu>Z6yZx|6wlf7 zFr|#XEk4BjYp@SRI;B_4thvUQ3s#Ga*=K|SQ|^l*FNh0C(Ol*@EzpTZjf_QciUwK; zT-Oyik~GZ_%CUYaWkY4gv?$8=TKNHcnc?Wu9(kUV8A)Lpn8KjkCA^x4<4F7bw6O1B zrg4-fvNSWp@#Krc)As(q{>Fc`{%-550_1O5K@4eOia09J*%TA?@LXj%pTY*}!1u}0 zl+)vVR#w-!cIysjhtEjz8FXxEN;7jRjGP~&)>KPT2|TJYK{YB&(+m^ap=F83=es>L z21iW^T*cnWgx)w|_jru!NG8)1*Hbu-WID}gtax}*5c(dECK1yl!}D68bIv*=vKN-n zY0TU29}swgt<{$BU5BvZiPO_#KKkebx`Q#p{s0#{2q*m-aT43%H6g44;04jZ270Zj zRVyqlw9KQYPfDB}vNS;|Wi`&r1JTkLBt{F2FwA_8&8%n<21iP+U4MbiwH1Ew-IvUZ zuYX-g<<_>6R+Nw zACiSJthK6yVZgHoXROy9Ucb7;-s12E#_n=UXps zFzmK@`Emof(=v^)5O;PK%*R`G@z)<^bp#1jVBF1`i+-(?fMFzEh?jnLR{HeXKQ<# z2U{z=_vs!_qa33P90@=C_DlSO@800SgU{JnxFi-9s_b05%2{unU*6s2teqnYLy_ey zH#}CFK8uZj^PWq-R^^A^y29bvh)*7!VuV6D4x*$qC~1)e{_3zwE%nW_>Cs2 zQXvQfUcS0ccQoaox5uT$3PsdsV`ULcK|JYm_1bl^G$wR4WR}P5D#7+@9VZ`gb9>c@ z7dC~^30sRb93^N34$ed&LLZ%GynJ&7UkP4VZ}N+~r$}LVdArUF>vjI>gME^0rW^lU zg8JN2wFXY1nRX5lM&mDTAXZk%1_N{&<2Z^h4$jfSVY%7l_~|32yHDvaF7VJW?;^kXcx%K8ZI6Xb(-as?1-X^?ugCl1LHwf7I&H{^DFTlwzM`t6>Pc%-LbH9Cv zqbz+b%?p0~;SrN4<+$G=2zm^s7TNjI(D|Hdg6)*g-s1AJ%@Xt(mE*!}&Y)ZecVPh; zIAyYC$fq$`6w&Tfx%J9re&Y}RK3O#8g9Oj$!DJ( zR`6i0eeNyVCP8{ydsN}xbNAU{t>5qWP1R^YtDPY`ErfG~dPrccrJOEMNu)xq3wTde zR=C=bv@_B~$KnR?BJ#csN~`!hMtj_dJesn`TZ?XGF^@<_dXB>xM_raASsKIgToj#$ z90^;Nc$p!T47nA~t;0FXu6n?}`P$`whg z6$QWnJqdIvfh{YxHadLsXKx^j1>?z#@uJ}F7cYFTqs9K^ZA7(XFu2BeGUuls{v;r? z&S8oYAth-$4THk<)IPXZI_m_~2)F=iPUC z`s^7mo5Nrg)9beJt_~D$1TMgGG`r(;e9GOscPYz?t<53tzxOuRF7I)C_=1+(T+U*xqn)Je3^m1a$yD~KOdPx< z;XC%aDZ+bJx zxkc8>cyT-rLR*=Df<ADL&fgnZ+Cgr2RqQCkrsvaA70kzxcav za^vDA|Ma(y5%~f0*^JpD=hn@e)B}p`*YR)&!+N_G2SBJ-3xUlQ9cAH0! zpD>;-A}_i|;kmTkI6ZpF)eGA~D&^xs1WXO@r*lFJ;F*laJbsch*x07q9r(k;1CcKmYvDaK!Id?c5>!RW@nnG%@ceMf zwY@e%1*3*FA{7`S>&YktB+mk>zlle%IDJLS9+GbEknC;;p{meit%Tdx2ma0d7Omo< z`1t$3$D5bl<6D2@b&e-1zBpX*@q?Fq@$e-{r_XerBZk*W)0E??LvOeZy2tZ-BTh_$ z9PUs9mGLa9YF$twU|CwEfXX@+wTYbU_+}}IH<8c1p8T`sTnFBTJktvVZWGN<3K0^p zh1PLi8K@f7GRNi%p1kTXFAPbwq&z*Msw^TMFfo#!J{nOi=XfueFDp#iqkZuTPGCKtXSvy?B$#%&rW#b z>L#yU+2P7wkBx4NZ-4hOt2*RQn5srJQBIzh zZ1wlp8g|I)DL?-3Bl^8IW-&$_-509U!PXhaFCTH5wYmDM|!y zLMBV2XKIG-L5C=!8*Q{z6%87rqHa<|cR&d)7>J~aW;q}8`6oYN|I#JC{#$>CKl|Z_ zj80E*J`ckvTZcx$)|9K9hhKb7xmxhr?c3D#>m0m%>klUX$>CRYl3m=TGVMhSb*6 z@3z_8+N4JCY*By`ELIhHnQ`;d z21Qk~T$boWQq-2RGH9h()sFG9qILqErLOT{_B6^ zU6FOWtZK)<{-e(s^aku-*x=dml02{JcT>ibC08yF*&cTI;>n0rRdeIwkkNF-G`D>3 z(*ss{fl3l~HaZ-PRxFE}MP9R96imlc_AXGLh^^0nSa&rMkIB!eMB2v#S@)Wu6g*20>K)}0M}S@3(` z`>8m*xy_4bQ*7rd2aAMn|Ne&@jB|16?XOeko}Yeph)zaGtts=8vaA^|3c9w9OV0$m z-aCqU4tQF<4l)XXy%0zR-iD$@M{7;tm(NH3q=7e=aB4ADP zX(q)pw$4>}Z?B&5RuDobM+AnWx-DuqarfB>9d<71PSblN2C z3>gLL&G{e%Qft~9gV0>ZDYYkLkR*vl4#WTR{>z^$m7vuNW)QuW<{Pi?vd9bGzPS~7 z?Qu%%{rY-06Jxoi#f9(hj0L-gN>hYV@!1zR?=dknYL#KxBO&05}$lp zG1%B<(C>u+V;83X)>szRl&6m#aQoH`+MO*9P9_XD252ELbr=!}5s{^+-OyUHySvBp zmj~Q`@Q}+_E(gP^=J~IKK~71~P4s#_v`#r0opN$|f>wb}s+5WvFCVFBVIP)Kqm*6G zC|uGd*|~*GTGYq)!*vr9W5VaBS;E?QMmB-EVy*ZLpAu-FVK4R!x*0dF?{WY6n7pXj z-|BPe!jO;eAMoCtJ>I>whcSjf{qzuHEx++Im#On5q-{QaIp@RA582!4@r`#bvNy&tHvsaX6vfZt>>rJqlx)%yZtjvBz7tF7W$5ct~Xm-g#}0Z@j+8_;iX> z+x+;^h*@58Yp=uA-2tsE;U|wycy+oUOA>zhXK&KgaC^VUAKiV$tXkn^Fe$K=X&p^p zo#W|#b^KM1uNsiQ;IPIBsZ}DSMM_V(swm5n+F0_^QdXA3<5Q%7$#_DqKSX#~EOYRY zhuciDBVAaEb7IK2x!Woi%3DrOr;LB{1z-Q!w>dakGMz5?wO_cy&Q_1DUc!7)aO2Vj z|K>Xn$TYlrYm-EJ#?uwQ{tGwxH-G$qr^icXxrs%p<9Jdc9J5bonbv6QqzfZEwc<4CpS=w!zK_&a~X z{#KXofBKwnzP;y1;}KO=iEg(?Ss8yi8c~#0^hXz9ESL(crdZ`@9U7ZeQHXq%Go4Rq zCmJm!h4p;+*%5a?KVrHl>GxYac(q_QFBp#=V;rn}5(@&>Q`b;41!T<_gNRAX4cC3m zxdwEW@#6Mf!BgbWw6Lulct>enpn3m_^Z~*~gQM%%wPA z4DSRWV!`O+#7z=}_g+Z;_>)7PAI(`VmrPCzmaB@zGWWaN8#w34i-P%LMk3Ns{M7`s z%X{Xl!aLvdG9*Xgob{_!L3c0|I_6|#3a;*Td3iYEbiClw-Voy)MeUd@YI@xk$K#UK zbOz3o4f?25ub)}qta0{1#H{-p2$@jNCty6L_RJRrcdqZVtUjPj6({Y4?gzIR?6#S9 z6Iy-EaQ8AtCv&{e_#`9S+QH~K#(7$UO=P=suJH-ec2fp3jI`xK5!?LVM&OB9KR=j~ zdUS|gEm7T#(1<%vIXT5SNCthRPVkmB>L%jv`erJ8{&_oxjz}d*JJ}i#6;dE{i}uAU zREs$>O;Piu^Hzxp%?A+ykaBJLDx@UILfU$Ra5R*~ zw4EYI*P_<5&-KUzQk4;<>+z%m=UoU$TLDpN8fNbs^je^mMCdd+n0;AGq7oHQ5#iU@ zuhAd~AxP46jq=@pKBk+(Rxe>?0{z4XfkJ37oeyqwLZF0LYZySFGYLKkR7~seQpDyU zigaao&zxZT0!FQXIW}!tn!xTP?vF zY*kXN=GeN#I)$;#9xAAe!Jv@+9c*!eQWb+ioAK!M?A`F^_7~1{I#MZ|3ym3GL?OBd zsl&SE98aGe|fmWZl3Be3MJLMvZlJ8*8p*rX?4* z2RuETvsjjNTZ${Y9VX*I@%!<;r(~(7lR<)_u1dat_X+)t0k>~n-_>yYO;uZf*(R-{Q%O5szL@xp8HaVJBsO z*rqNkUc5S`tU~bCvsY8zzP`!VU)wJSJV9LDXFgwG z9Tdf9%ti-zsk!s^*EoIx%d(A9f^xYEE*|SjI5Zv(z%=w4!E#yg?e8Cv^*dxDBrz}Y zLexb`zt<&StuR#;Xb#rltS2AOP}Pc}P~=4s9WuhcRhA`nRU@%zVG! zG!ti7%8cBB@si3ZZoTy;i>C`VE^n~6+u`xE6Aq^Zqv$$k zu|~Lq5ZSGD6=#E%khxJB&mVq#K(it_7bup^QrI+(o?vS$n~+P0#vDE(Bw?y71?y{u z56y&&;&mzHmp(77FM@{BBM44!=P#@GXW@Dc!b3c-rYUWPP2mv>_U=kWF}e5a>(adU zVQ&kCu4)D=fE1qPs^oijpHN#zZ5+m0?mazXxVO)b?>*+9|Iss1R~32xO=!*e;TNZ3 zS#Ps*a}U+(M0zhMm7tT1%1X%kv^y317xy?hI^x(Lg@(~OYU<#WB^vR2&?qhz3+k$h zx*Hh;%dtW7)>2dzfAg1qk$?1`{%3sjlOOZH{EL5yu@;>sxU$CkG&pqurmDDfVORX4 z|L7mmX(jxt-~C;*3eQNB|06}vKUPArT+F$;lkywCc!%$QSaJWJWOsL$`FtLl93>GV z0q4jU3vS=M!hii={g>Rm`&0g>|M|B$JUAfH3Tq{xv30OvHg!#!B>V^e;P3Il*WTlw z{L_EN=bzuBs#8{Z9-9296_QbqE{vhcG7=)#<_IYeDnW2YEtFEArD8Z3@cP9o+&}fq z^8yo{#zIh}Bg?{osICph1e%_+LEtXq(o)xf4&3Xcw6tJZc|LkR#TmnU*M^ix>Qt+l0oiM8xwi*xy!YIHe8}|+LmnK=sp^_;w@WhE z!s-@M1?SJ1NXd<4pi)W{n{CbZMw{>6eZ})p#ZMld@XqU(Ns@%h3%v6_%UX3$CufVy zSI1xJ_^JWI{&^MXZba9+?!HGA7V+F3$TJ5uGD&sOwX znqlO`{@h!a=(H0)dvZc6N$9r|K6!Y=8#i~!G#nmIxb((8ReqJDPrl1)KBkzB==M5c zicr>cbRXxTGLD18V;0jf636zi9Rda8-WsNBb(m5%+}eQ21}c^@!A?+0v`%nk5jL_! zBZZ8clMT&6EOLYhVz+!%AWF}&nDFw|iTLoNkLk5jk|af_1mh)j9XPz;9$~$w#$#%W zh*L&m46A&J5QsEQymOAasyyBaZz@`eV0UK#K4d-+3l{Gj)ozd9p+x6NNJ%Yfq{pZ7xpTo%1NEQA%Oz#!fSU{nF#B%B~x@sw{o2 zwGiH6jKh1u<()3QbU?A_q7zN4-^WQ6CW6-T;&{mbyW| zjc=uEx{AZo(tZNfSj`RruOKD+9a! z&@*~dEI6C`oJc!bS1G=k=$@e%5X0`8bx(lM39bE$;hl@0eV(t>Gz}sazYW6FxaW!W z&xkeU%-C~0|7H=!ueDO^VMe?zO{04LZ?DhSH{E~Cgb)oy)JNK=J3|Y+UH{cHjY$;y zuiF*Q4O#-dFs%8Zx%J*7R4np@2jE8wKyZQ2zhp`WYf5F)=YWtknh7L)j7zG+v<4lMM**~F?Y$##p*Y)Op_;?m!?{l)DTsBQ!^ZPE+T?1Mp;@=Q> zk}To=%Nb=E!bDrC;?>C#*KYE+{_by(7d1zxGe$rBlxlv;{tKZs5|l;=6B5r&O;y(GV9~Q2rLgWuEK-Fqx@Eo!A$VR!^eZ-=Q45l_TPOia7=~%h z{ze-mq1PV-q(RInOM~~0Gzpq3tre@;G1H?N)5!>H&bez5^rP)wm#v*WE?wN`BX?FHcy>6ao2C5P2iJIaUh$oe z52&2v*8T>=Op$0s+RFHTs#%mvT4~DP{iWMn*>3UOj~;XF(qNN@Gdlv zQscZoTYA1a{#wUZ4ai?|NGZH^-X9#D&=X7EymN!y%`Tl(QIu8SUdL&=Q)i3*+M@E@ zR4-Vq#%ZsQ;xB6{jTJKMu_zr+Pe;s_B_F(Zo%>IY`QG6(s@l@;cSw_jlUac=4v{)m zWzFyY@qG?X7F@lu!^wC_Czb4PwP~jkf4L9Nv$xUa(|b!MCyH;pdktR}Oh;4Rd2OHN zlQxfE9C3Vl%xsylS!|NE+Vp#UPDdjY0_O~6o`ZLkt3?pS6ACREOCPCIAQa7^SP8{` zT~#6cNGDhuoR`i|PQ#`cw!|P_kG|tVU`eUP210e?G^*x!AwjqBvV%uM(nT&>JpR!U z$-tlnTM-tQ>&ct9p8d@hyW5?p7dR^(nvksL$8%1f9aEH*aK4L>F&Vcu)V5wvhozFV zI(^71Ac*l6%iMeKg%m=B!VPb%qpl4bZOQw$Hc9ZYzBwzfw2~}q&ma8g8F>*Li(>s3 z%6Ko&&@<;jdbWBkIxV%f*=!Pol?=H7$EQ=Y@N92y38^Y?o$>jq5UW*AtJM}Fb!(bI zEUG--imI$AO-n3Sm6*@w6vawNf^mW}1vf9W+1}`4T%d}qRyFtTJ>%kbpF6kr`Rwrt zpFbI+B25e-0!<`dYg1KJ%LOXU(5)7oRP)yD9kf<48$@8O0X(Tzl*aJ+gG0P`w6ZkZ zE@y?%di|Z7h%9Rz);JPpX}2?xwURX=AOx635N|Ec!l0XRWv@?O4G=!$*0@+;-nh8I z{U>Ao;G-8LTCNKw=g#!b%{#5MA{`FUNw{ysh7lhE4YNeCwYkA+zT~G*4%pi2v)k`5 znio8HGUI38y@q#=UMFL7*x|F6bJ|iM)cImIJOFEeLx?rsTCA@_bVG~9WaG0B64~ux z=d<8&)b66X11dA6nk_I=BHBIB*;!-U{KckV7jgA!iqhu$i?hA=OgnORtY`mm!)|`= zOC|cb^)UV0qOLi2={RvSwBM&fAO$(*b67=<24qbVngerC98_}$-A>ZZNok$WI#di z7U?5s=0OUFSm!%LJ&|`TmKEEZJvN42ULMV;ouJe1F-gL^MW!UnGA>-$({PsWpZEB}U(u{7WL$S)~cDi`K#MCufNwR*QdtW@{zxi+f zJHGb82Nb@IagZb_#@cv2Ak8wiws!dDuYHT|&Nd%@c7)KHBx{poDO!gCim9ni9xtCf;Gg`{e}>kYdEsfbyR=(5iB^&HQ~yot+@V$tSRtpbQAW5U0%D`r=KY< zZuhvn9byw6y*S~;%VXZUbA{1tg|H#ts|gwvGOWQ8Pb-zQI~m<>izL8VYh+d6zG_1L ze;i*mAb;UeAce*&&8bn0t>OwjX7j1h6^@7gkMQCj^%U9^MgEuwk6yMsx>3$f_B`t*36wYF;Br}$@)kbHn zAPRK`?;P*mzDk-Zp1m3eSX+ik9X{AVVk?}h@vf%Z2@PCmKD?-{_ex2mw@4Shzs2K? z!PEuLT7ehd7z43Uv2~5dGny>TV zltoTo+7Jd9sN2+aErf7n8l1B{eKq05;S?8R(d)WqK3}mYj<|AhgBuqI+<$zG_i9Z| zi8nViRL0=S3W2~#MSqxb{X&<|9-pu(LW8%O&T&;mYuLvtMOBuxY)wmfly|~;;e}Mf zI_K-U7D;9iw!)hVr)!+8F=g(@lU$g(_Cg4uq(rNL#yMNzY>T@OPPlvj5P^yr15wEA z9Pi)B+3L5$!e~8S5<~jpG(8q_0!UI#A_$0`Zz`@hC61b%Rauj@Qhx1M-a)k5+EuBpR5Q<}<_h66bz@ z-P}Y@yok`2h#x5$icW)BG?U#1bsr&yB!a{QQRG)m+1-v2o#j zZt^pT>T*w@Hbvw~#CINo0fO^QW5pVk^3KstC13lQ%XB*_7dp`Eb=lhN(UOku{o((` zYCgplbKKE$(pACX>55EC4i66a#ozpUbUTXqJkW+^^Ng4pp&eCKVoWe6lF?PlyU+j# zDRI_Ol_k4-dki)0;}uDwBaKhu zoQ*cOHafWpqzq1-P5wp`TIj4pXBk3i@ZowYDaiAj)0ttKc0d~PRUJYkMR?bxR-BHP z%;&3!$SZsu=)Ub#(P|~EUe$D335gc;yBSt$9*KYx?0e#-HzjuUh(w#0o9F*yncCu z>8j%8wBkEojA;)yc<;_W^Tk8FQ0SO9B9&rU8RpB1TYCel+Vl3!9TuxH+nJ?R}IKtc(m|NNH3(Iw}a7LM(vCI&UYS)+0(oH{onXS-hAVA%Cf{dOPVB@ zx?r)GVe6V@zM#&h2rNpsf;DJ=h)@|Gi7`$jIzf5E>3GTgafR>hktoeG*`vaT!wBWy-_*pW>XOEOL@0V_EuOM=2F))?)Xe!>1ig z8E93)S#&!i>9nKOF=(aMQ+VM$7SCso4*C4y5lI%3g>e?=EY5ng5(sA~@+F;?rlk|I zOpC3JKK)KhSW_Wf3AO}hz}6J26~cQqhFw}&B31~}Rxk3vYm_TlRVB3%fJCU6rX3x^ zoL7{!ji^r`?+5_5_D>5kZ^eCu+g0>aKq!@4}UZ?q_(C!Im9mJ zpb}cU7f1&~T&In9p4xjvt4+3lIi^g|m#{uIivCO&aqe$e8z!U9 z6KsFu`K)n?rm1Sq>6{j=S!Wy3yN?Z$;Or6b@!EMG1~oofi8nfq=3brGq#y)J0OgX^ z=?H0SbP}Ajgb&R_6Q1Lo$BE$jW-G(~-jJ(TcKH0!5lTwBtu`-@rh&^Z8e}J~t&)hX zG!0YG!XVBj(C5+lX5F@yHF_1tO-O$>M8cg-&JjtlAa2}N;xi+J0_)amK|@Ox&XZ`* z#f>)oUWa^HvfIzt?uG>L{&16TedBf9;)p-}qeFi3@fQp?Ho12F8VAoGGCw`UECqEQ zoEfzaYh`U}YG1LaDypiCrxK`u4!3^vtPAwLEX&sKECRGtv|23+U*LT}MDn6wG?@vN zwb$0x-Z`{Z@%jaH%*O`3)9sVB+ANo=uy>Z_dg|Zkp1k+;dOeoQoY`!~*3K?gfUY0Y$5a&R=^>v#6KFlck<#tsi(j@f7{e&xL@JU?Bs-OrdT3Qi_D zKmX1(+y{brQFG@~pUY`jq$I*e9`?RW0x;!fSlAk<0;WvNoI`7`v z;dD{*XP=(NCBeS&;QbU zh_u5GKYht`ZaH0AUd=7tVVj-Z4g93!!gh~m2UE5;+T6G}F-lx2ZZ;+!S_m#3Ct*cXclPnaS*hcgCL zgvSBrLWkv}8%dI7w7PvrIyjLclLX!Ek_|SnWFf0ThJY{CZbwIxSQ+_9?TY7MjYW7% zFy(6K8ZM^ehK1J|OIcP_Rq2PNxUzU(<84J(|2AVoI~pHEI5C*0k2U@0{zOGKru;VvYzTUb@y6?4WX#i z66+jyA5Q?!tNDnZJer`Dih^5%X%QCi}Rqbv>1ds?Xm33*Ykor|3HwBk7#a~6}f4zTlny+$-zmPG3_%BT=) z9ZWMcX%1^b(celWtIC3q@jY(_G2t>GVlLEj&g$fdR;xwY?NK+`E>f)#sc@-$6z+!S z^@I0cV{^ODI;^0Ck5W$#4HryW@?x~IUI!HQV2h|9TjmJ70 z?l}(c!@J+zGuA!$55(NSyV(d~rEbirbolcfpM zMJUFvU*2Oj9`Wej0hyaI9*wA+B46fAMkhF@7%vQEEihG%uM4ycwAAH%&PJyq%R=yE z2z7*zwc^&utdbfjAkUX1X^M)}P7$fQjkeSIV84#ec=qy;L9b6)EGdfuDHPt9QCKZ; zE`0y0b`+)I)xjZK+uKO3vDT~|qQWy1_PwI4&}j=L6{n{o7K;VlUXM(0AWeZhzKp78b?m&vu}-osZoBx$Po#{0MV?C~kblbrsb!{eiz$}B0$P$11K818Jd zImr0gPKW15Q{KF>$F~nu@r8745+g@JmS(oRx@ z3S4&~0B54VM)>Ifa)hauu@-A(Rm^^%pL-F$EGw_bl=#=GRN~LGGG!|jjAXI2PrBZkk z?wz**QSn9v+f8GUTB8!Zo+Nr(gVS;I3h=+c2XFo|4^2$3sci2603ZNKL_t&{!B*H} zMzNUs)xwL!@qVu!Z^Z)&_vFjdITF=e1& zx#*Zr~|VoN75{In~%o!Ss;H3CuS<_rJJD zr?M-)*gbtbBff7Dea zc5;d@muPRGs;Qm9dWCGIp`l-Yu3w*>j7>sSn=>IY!9~v+x2APD=h2B;|Fe<-rE#$- z(s9BW1ioQUHXb~dEKPurUf$@!z9d5bbBMrNq)v1r^PW@-Ze1ACZ6_@Ail@g*s@igS ztIbwFAa7bpUW`_pObZePZ(rZQ8pqS)1qjJI*EboogLch&czU#8XV_wQ*rKW|N=s&| zn&ZieqO#a*sMy)wV9-tJWC`PC#kJeFna;+nmK|Qm*U0<(w0oY3 zOu7ESRrYV);qhnpLh)Z$P)w25khI$%E0lDxiS%olueD)%FI5m5r~fy5@AYh1cHj4X zR@mXBoA2#=JE!T1m;nX=L4<)ofD}};S(fOsOGT>6!#Iv#O@1!|CpG&fa^i-|zeThAijw z*~@b&ZgMVp@h&bYsy?{ z4i5GhkH<)F**Le#`3o2M^y3dhhLTVWheL{Df{>EQc+AQ1G1eNs@oR5_H-XOOEXD>m zs_|$@S(S9Vy?ACbV=SC0i$e43V5WO$whkdB#tEjADTl{3uHB+4>zI+{XCZ{m-!@Zu z#xuY6fn!~6I4X?1dXsbpe2x3`9T_G}bP8bq-0{gXd?$Xx1}CJQ_|DiK0*Z+FCl zz0X5tiUqGUPAE3}HJk5kBO<`(5Qrk`d0hB>yZ!Q)=+LFL?DfZCFVup5S#vVAB#8!R zQJLh~z_NLIgj8W~^tB+`7RSf)iwVeIcYV=-{1rJNMth#h^#W%nH8l$4(lSlhpy?maRZ*1`7aLV5Ch}W;J^VL_b@L+q0 zm4^P*ayUFesDw1tvrRwIf(t7>Za+R`XYZJe)j5>#?Dt3P9SrDYf}O(?SeQdPix-lG zUW!tZ{;0ya5b9;Dr=2ILJfYto(atndI41crADnuqQ@p-Rnn{MIN0{RZog_$^ps}QC zjIWEC%Y^4_qk%B0cd@_;;aH*h2n-ED0~Rzkvmp;fM7lsgn?gM#vEh3sP1A@!u)y-U3+(UjaC&k?|8#{ckz8G0#AYeB)na8%GZ^$mo@f>pSDB2*OvV$2qYE38ifU*8ynt8hkOtD3r~ka>&Lw}3!b63!qI z899YXf}>fg!PGTLwnTSsk?~|oS(O|gAB(lFUpGc-Z(2vRpDyO#0thX!_^h0 zuER9WiZ}^yAT?-BV|(i%Ivd6Q;JJx~k6lSIDZv<$Rt8D|Auz5Kt@!w%X7g~w_g~-ObU0x!t*M=0 z`zSO4mljj5ug~*%f5>N>1#i84jx5#ulb<}q7|V?-i?mvrpM0_#nyKffys@A}i2!Ce z#~asHS)WVz^xhV)zHouT#PI2pEu2(kEYBq&2?~i`1}( z($J#tQ8ySGpGu`56_>AHWNYVywbca{&#lp)))ACxT)c>GcOiUEM*D3)86cE`d_L^e z3K9gSGF)2g@zz%^^V5&Fc(mJ((*f|-k;cK6kHxB-HOk@tqVe_hE>3M+EdCoY``NXw zfhWf`0>SS16iu)eUR!K&d1D#d>oE}%l8arm+CsE7Hc@EhIXoG1I<82Q9B{azk2&d+ zwiI49sD5sPq-$}991RyaOB=4U_t_w4WPU`znKgb09! zv4*wPC6?y9>~24!*KM=0zQ%)x57~P9gu$RsbdqH}9J05w$?cCNkDff`!lmoH{*^a* zaPJ=d(*dK=2=6ROnoySoqroZfy!|$2!M>?C((&1>^AuJoFak$g?a4Glsp! z_&A*+OiLYrHOPj_Cz$0>nYs#KpHmI;a%R#&V}=nlu+B&FWCTrAwEgvwDyUmIZJlDK zHYAOUaEdzzh0f4<#%bYjLPW3wtXCL3sBotv6jF)Vv*NHJ{1Fk(6cMyonow^TXOSYf zz$q1$#NMn>T=my1XqyJ+4$E+_JkYBNudr6%rF%k$bgbb7bCBuVW zSytxTT)nWwJMTZ>{<9NQmWN4zPPlY&g~6l*9Ou`U7#B73-HeOtOC0tKUcIqFua!^- zBl8e+row~dMI4PwPgy%2Zl5qJYvy_#R_EI+Ep)iNu|Thzv3E3}*KM=3*g=ssat`?GK;v($y7Kmpbh3owCqPsj7-kZa-s^cMw7_mrHu8=22OrJ268; zBq%dPjvIW`&yZT4+i=237Y-sHX$&!~=L~tBQ9zg#Up@xNd22)apd`Y&FcBcw+mV!~uRrq}Io z{n|CIUc1R_UwQ>A5>%4=-NRF{b8w8(3FD#?KYs5%`vXN?T*TD{&Q$Sp*+5@#HQwrg zy1E)%pgxpkiJkPhy42;u@;ts&zNP0`=*1$!E!wbcDJjR=vb}IQ>Z@tM^-Y`B%GvS=`hvSN2<%HBJ zH+~MFR(74`-p&kg}TRpsUc24ro#bUMtuLvH(2at_`2Z2>O9Mf zbKY7nymKh&$(3j8@#j3-e2Ufylku1rZ{1>fd7l6N@BJ>7)6`)+MoU?Cx1Vx!bi{Bp zW;*V3<;qpoR_6Jy{_gKkT8&VONl}Q$J12}Qi%8r2;?5p#-`>O3bAc@%X%z?uD0G&E z1mQ-j5bnf?YI62W#A3`lhp#HCX^BoWi@g?E8Vn-FrQvj3BV|Arn@~GRNHbsT2P}LUe!ZVV@!?rRuG}+#h=#<)nUR);Y%~Ly~NH`Q3f!lpn%ed7|>&M))7{^3V#9gexM)S}Z)d3rEHI1!stH)}d(R=&-& zG}7M$p7}gs`*6s=e&-=ey%ss6=-{m7Cm(LIbzG3-8I^I|JU_?vjXD1LkMB~| zjy%`&63K8p<&WNd%JH}+O;e1AgX0N@hkeAGf_FaK;lb9Bo9pv@^VTvCwoiEb_5oUY z+MzqfnV^*j=xHdPgdmuKI7=_nY^-#6`}Q6meSVBjT3p+h=kC*EX7I5!fp&FtfKnQZ zqY*K$8L~9EAy59cL}WY0dWGm`9sOC?#p{_8CtK%F;fUavtfd z-r;?d8m>VIOkq$7NNM6!JLpkNU9;8^+*s0lkVFlg412S;E+(!!becpV$#Yb$Z~sX{V9He+uI1_S`q}HL}6&@?#*-63Ey(dT<(pF?Tq;Bu;A3|M(V$oK3ThdzS z2Jy4^m}10eYUnMu@tK~DA%i4M%!=rcePmEd)9LjnCR3`i2xcS!O~5%53TW?m^yo38 z@sy1VmwDyY*XYg7alE(1;o(6LwmXAV;rrO!e2TH2`Q=qEUAn}r7hhz5cbm~@K$AS~ ztV1}*?#>RANx}VxkGOIDDnIz%cUfHM#i^;q8cUOxwE6TY`+El*92~H@`HWxt=3D&6 zZ~P5@_EXKr?~fP_`&46tz+uf1{ao#n42LWD`AbhxIJmKDM8ryJBM)L@%kVyj0W9tgJgTU?jenX)9iKPOr#nL)*w)K#RRG`q>teZqr#cR?xyo|j*Gk(HGdE^e$6J}3wr-dXk! z_PKrc0mI=b#dN~0n>Scroo8chG4v45__DU*pkFaI5}BlYd~b_)f3izGTEli)*t(9_ zHwn`Zbl`-0j}jh_#rYcNDxA^SLU4H=e)zSker2KS>vAGY(HE`EiZo5*;NDVO!Q`aN zX@86bvMiz1%27&iZmAW<<&oxNjKx(;^iPh0WwiHna!n!)?YT4{kX1n;3og8}PTHRL zD(g^B3-Rtp52)&rx~_whT@)(|0`;lU>=5&LhzPTf2bGeZFI`{e=yb|pRPckhZt*AY zKIYQ-1^(_2USj`r$Z%Yul7ye%*{7}z7uV-``;%Ra4aM_vFU8druU%hZX}-h3py0vw z33-~*%2NLIFP<`)8s5CMLMzj}_xS;`)u9{>G2=0+-NUzfRJDr@ebW=gTQ<@ig%C(@ zVbbU5G809sNm7Z9!|v(Xix$2YYLO3~MwGQh0@Zj*?I*P6yMY=Rm-k?%B~@9n zxHg9bPA4^4r_IT*;_7)ts%6M@a)$Ew05cqrw{kYlucENnjYYCv9X-=C(O;Y5JIqjJZ3%S4auaL)Clq{BTod%2Rc=frO}%9T%>|YrlsTd z<|%`53BWHtddzZH2h)iLOp2(sGZtG_D6L}H;d9M+oNk2X!{KTZHAwA1je=Q-rMDJS zlpqAMtD2~wvqmA&U@b~&hNq|4%0x{I@tjPkib-%^R3YOA8bHf|(2=X(oI%a`5}I2Z zvyed0YPU(!1V5f)O`vKCSAmDgWP-KEE8)fMk3Xc-X|Xilq1A3ja}b61H8?|A6x8LE zPCMste~(lNE?>OB>gp;d$A=hG2MV#RDGJB-_LjeV`LcNJ)mJz$%XUhXt#2_voVy>6EbQ%D=R%NUAfM|;USw(AG3OH zjirS}jyeZqS&9@g2*!Op*TrmzJ3EtIU7^evQ=H@s$FVF5LFGR3>_73aA)I>%)YcT4XaW4=tv!rqD z3)E48ND>544f^Kg+)#} zDZNgD@PhsRm`6_!Se$F~!*9I6!|fBgos1-D+$ES%mTYN4Hi3{l*&W4ch(Sup=UYRR zgq@=))_Sr`b9;M)-5f+4KuNEau)f&l{=*%fY#k!5t&=5+G|Mp7(Mcp)fKC;)6-c2- zat%U>dz-sh-3}86twBnpOd{7e1S3VLAcV-xsG&2aCugG5X2TDwDTEM$MCp*dU>kd0 zfplW_V=p9mE2nbteKdcMbF)LS7z`m%taOFH*z@9Ezd)pE__v%3be5Pa;!VxQe8S6@ z7Fl1+DN4oo*l^lE45DD2gvLk+s>*Tm`c-t2vH9>eyE{)=TCuz#y z=nzql1XYDA3!JU7Ud652p(4WMo6)`x%?{S!jlo&Nay#Mb`aGRH5mhO~*5)oJ!vnHb zH$HI=Th~Zma^uETJc_NS_n8b2QKF&%vQ`@*WU#rcO6ut`>#GZ7-6f9pw<#wl3{Ps1 zA^g%*Q#^2SX_ekwE|N51xfOW&Hq!aLsWC!_Ku8rbS!6SMx4t=!!YwHRvMC&_&S$h0 z90${EI)m z!;{S=e*3#G^Uf#R+}}Fo`(M4vcVFLN_higZKH8y`NLJ>u;Fi>C)46aJV+|@vshwwX zaEQ+KPeM5SCDBS(34{x@E-xfmyGwgvk#4s`Z7g}Bc=gtKe3J5wm(MevRuoko z=~AA0TF^f_r8>6|1HdB9s~DrI3D!D3y1mKjLYG&sEm2oBTIOUbP&jcO;~dgC5)qmQ zCqqKCcMjtm)p*L}=!Ejx0=F*AlWEDye2e=}54rzjpX(PE_}Z-%E)HtmzH`7}TC;aD z;m03s^5vUr{3qYK$_ICLINCpCwU_bDSJwIT=_&8uKMF=>LVykXg9vygNuv1d$q@_f zj9-6wo!#S66rYD8tI-fNiQ?Whv_d;eA#aNDz{-mBPv>#dA$BwjDe+SB~IQ8vcmOrY5%y0KJtXg7f>Ol_2qh_VXP z3lT-rST3*4Q`8;a|9lc?Zz{*>3@N8HRt&StD6`@oJ3VeP^6@Vt;amL{58edM3Dwqy?SBD&;NXePG zd^v|ufs*FDjX#%BQy1LQur-Z#WilG^`DdSqPM)E3!oz!?Grzb(7Byv2(Cc+)^kN}h%uT7eclWMPc)s=RZ?SOo5>-`EmE|v49&W&?9%L`rdZijOE0;9oz2fGtKxwpl8_nz@!cNg2+An7e(n&&0cpqbGUc9oxldVHux^W(2ZyhEAG6c3wr?@Ob#bnhy z)6~`ngbWeF;FKoI71PR~r6kjeqO8$c@^o*&{ig@m+H(Hf0*k#i-CmnlUs$I$jvv4G zfaS#=m9gCad^0@0*3!)r(hKJ}CYNQD&*-8fn`gf%!kV0f2ImlQ+}^Yz z(Salg02Nu5Q25#>#C%jPUz0Bvb=td{>cG*n^Q*p(;#w8v%t0Yp+NP{3E><*(oX_Kp$^V9 zwgMyZq|JOe1}a55PaWtCzM9fi6`jPRgb_+WQB3Hc9@DOEKu@JactKqkT)23XH19Gv z+U4kA8?7B$XQIk;FNDI>C3Rhh>3GD-${KSEt2}ZgCr8_~v;mo*vzGAQW2=h!#WjRL zNa09?!BrEgVvI30zAi(k9Zi}+;DNh3y5Pk7L%2}j*OkF*3)Tql5}flC(}KyQ!1+K; z^43sRC1vGEvw-&MB&D2AP{JX#4hR|&Q%|WT!Gd~zd7a+;BBRq|hNB5dk|Jb{QYs+p z)=?WnRRya}W6BxL4et@&;B6In$5KSg=79PlTx>w%LG8mqX{}}VV93UD2X9k~vgGng zMkkjX^e5y=LYBAC@mU>DDk|dw4FITXi%xP#+YBqosB{#y#W)xghDX~+{Mrl4+<$z; zXjHJ+%cAY9#HSfbWTDwBYee2cY8`~(O2vr{gt&$P+<7U;<`=lUzQpy5t9M;VHN8 zJmk%M0K4fy!}A%{bQ_aY8m zML_bKpt=UBm6CTp+v0b=`!aK#1@=!Tv^t^5Z5;f3L~HRO)mtW-se!^cRu@`4**fO@ z${N$M#yE?pf>tZb^DvPe9OG@x-3Le9es~a)x8qq5sH}n7BfJTYOkTvoIh;*1xv(HK z0^WxP1dv*u(M5a+6m-$-KEOx~%!qOY5{d9kh3#G`f|cqX9;K~A(CxMa`|6ZKK+M2qmW=06!+7O}}13w$X1?QeKOo^Y%+M3O$Px;Ls z{06`MJAa#xKK_)Qy?wGYp|STxDx5bYt^sQR03ZNKL_t*GEW>f1Vm#tM`|ZDpZuNNY zy+6bIK==u6fD$KDaE7{?a_9DEeE)lI@vU!vllMOOh-W*8LBsPL`d-)Jo;}>%hZm;& zkAMHaWjdYm_S-+@cz>HT$w+h+8ejyrg2`~eXmHAZ_h0|d-dgMb$v^v-^0V7_qx33h zazdlr(58Yw-+344&CcTMF>bVn)*2(C3!aoX50lAMsE!F?tyW+>=y>ESB}sL7-Awc2 z{h5_7poKs>gP%;mhUvf18Kil13AM3&IJ0&(k*4bLIBDY~ELcK|IGIpMm|hfnPq~zh z`A@(50zdrL%e;Jbk-3%z5$%SZLC7{zuJawCm=GFs7kAwVju z2jx9qfB76QTw3Jb&Va4GAy+o$`Q-jS*Ury#?cxHDxBIkH#ll>RcRqQ>a9r}q!z0R~ zLJ3cnNFMJ^=uc}tzPAU?ada|dZf<}xhGJTy6|@tSAGhe15po?9X7gpq55TsHh*DI`@{aN*Kb z{Kbpp?H043Hk!gkBZNjKIYm*hxU|BpSHDcR(?W_fXBcM<#dN|zo*<=SaC(Bk0y-39 z*5GUnR>f~8jHZ2}!xv3Jw7tla2bCNViN45 zon__RMG_^>+*ycXZJi^N9;&@WtKB6@6V@(V#yLlxZC*IFa@cG16(;JU05c`vT&O@Pk&f)>(T;qtu7C?j>D9ytTCnG z>o2Wwex=2=^*Iju1!)p;6$0Al5yFw>DS0>0>5@bT_bDmK6U~#IQ}RUd^%s_SvVBZZ zwr54Fbxr78NN8`(_hwX1A^gliNeU0fV8=tM@rc%3o2sgK{P>WE`voUfb22Ef2p(;n za{KWqPYz0c_q#W^u-YRCi#<*#<`;TsDG6#>i>(aCd6G24)&^-Uk3N6Gt5;U}>KiZd z-p7w9j}K9iz@S7B*E?$i-9doEQ5QqfjjPaU;e;Yd6HZ4Z_cl-Hwll6@SmNP!pLV7h z)^IQ~Bnohj<%Kq_R*$E<15QRE3439#jZ~VWvE^i3ljk~oFF=|n%y;sTVI&|=6=jxk zG%~z@cZc8qo3AmP8k7>KL}R14Sww}flmf3L5-6vpw2lXSAvYau#@S7E=WsT9UVBIV)0lY#jpqgp>gcu#x@} zzh9{ozP8a=AvPT`__N7^3i|*E`CReuqP?^d*mxM65peZ{H+H-nx zGNbuQ83GA?)Oz5VX-|DKZg4f#=opox0qvI>>l{idI-M?AmT~&*m`W!Ip@YaC$#6JD zDS>f~HG1?>X6`*iBgWd*m?G~c9jBUWT_;!>K^jaxO35G?5 zb#6wD62#`NoM86u@f+9L{QckkEx!KRCGx~E8V@-gIJ8nIDFc}6tC@SJQi_*utn$Lu zzrlCEa#j4pfBIwo)n^|vU3mo=v%O~4;!*@tk${-~#tm2G$6lXtVgVB_G5BKn{X6M-+YBD78j=hJLyK2hull%0KN)C6P zk#*1pLzps1J-5+w2*Ap@Q2@_LtEOLB23M|sO@R~FgaKIZsjz?HQ&Z@#d? z{^5Ys*Sv9kg&%#e$*5n21XCp#P7MxAmT9&RM$xS!T0^^)F-3AP9tCfG z6+UCb-6V!ModuKe99k!0IF+BB4}MnAyEA%*3dNL-1xFaY%XsKA`))lUQ)D{qGqzK( z2B9jvt-yQgL4nl?*~)ozHpl+N@kgH?;1FktxYmIUg_k!KxiGwX+T7MICx_bxR~f{VgY3WTI*^$ZAIQ{lVurcmecJmAXS1FS~SL(&Q)PTCIT1t z+_}|;|0ICu%7zy+1)>jDz*4Zhyd0Zk8M7;FKx(ZCw#ZVV)0|GLh4PIZvWdlf$UyL3 z&fI)vh6>K$syYZRX`TT=e>^2iH4E)F@7>CnWX(@2SKJ{qG znf-2f?<(2^duPLSu^v0DsHX)F9`AGiup(bxMJq{B)+{Y_xORDkcAnA76COU@=Y>nl zeEp>jK7V$~Yu8tKvUh^@(8@HuZjM%hvM5NEpw-H$yyE8{+~-?w-eP09htN9QBPxkt z1xO#YDc&Ng0y`d2?QW8+o=58#wn?Ch-uZlomHCY2`8K&$eEUo1gDaQ!eDLuj?@6{wC!ho_7tHCm@U*q!k6 zJ9~@@i=XXpVS}s73R~A??G_>n$EZZ``Q|B9CFgpYcRxI2`?Mlag2LG#lrJWv?Ka(& zWki+*t5sLy>bR%)8ma<28Bve=B&`;z)d@wm0KC9W$JpUMDsQ8@3lUkCGYukM;BAR7 zrjX>QJP&)7Qdp{Bk!%e~o}t?9fF3vbEZ%c@V~*?R=SdUA!)K>dmBZQKyri1ONL!{6G2iuf4&OXWI-0!vLnK z(A-EFrY$S0>ntv>@X6gr{NsQ0kEpCuX zDoZ~2^gjLJ1n)gcX|lYHvzCR$1ukB`M!VhS|M|B+;l-OfB1t=RyFG@(0WyghGj(+2 z^D1gn!guDKp`oC8=P*^!1}Uj$XI@nnUYkmkWrbHhHgAL+9_u(h8R4axY3O`B6NIz4 z<7cRYk43xMB^4FEE<%WN;V4e;Fg|*OxcVLR>Q$@=Dec}tswJ5W+O{-JnM|vIP(h&S z83Vg_`7ghEj(_lbzsZ%2E~cJRl)=uJNDVxbs5T?HkOx#&W3-mM@#;1Hm-Fjf`h$PV z|MBlWX0Z4gh6h}plYHmm0xw>=%-T|qbIbESPZ4jd-Q;L!dA4)N-DjuVz55Y; zx}-}RBzZgVv>k{fhOV-wLR_q)MIJexv)P_NSg!76~X+apQl)w?~+p;n#AKxTZ*u$ezsoO3pb@XZv&+K8T=B?C7wiw8159g134 zS2$y^rbO79jg4hiSJzMtDk^3dp&`5>ng)Qz;#fS#h-4XokW-YEwsQyw3dv|5hWrxtHYmKWz( zTWWLv*$Jx)ZKjpMSci@ROi7?YLYQVA_ov+5JmU9$>oq>OcMv$rAyF_;T!u%OgKeln zQ|x`j2=Gzl8IXS6>5;Y*lpnLZe?(PINwXBK6qD(M+mH5n>Dmh4|MGbRg3aw?KKgu@ z{evNIzO=!&Ut8nwbja<;hp1HHl;rWjkkSj%UXR_8Wm-Twx6HxB@Gswe1WCsHwHsJ3 z@YYg{Cb+61pI<=aIo>;_d)tWd047u1!8Yxsb)Fp#Ip|LjN^yER-A@iK~?(MO* z)FIQM3C&W?v+YCvxn|apytz=DkSPI6XZfolNnj6iA5@o_kOB>5odZf?7C| zM3U(gghdb>v#bx)s5H-UTJhS=RnD(;I2}yc+&*G;p~D~l=svC9I^TKy8Xw+I`Ni#R zLSgHvCljQSq`gkKKVy;Tou?iSz}a9>AcF2siqPzz?XWfqu$VVGoH3 z-Hqk7YeETqqyz@{U60K-= zdOY15pl(0o;P3?JAW2fHvIt?PLXx*yI9HPhRD1_+1tk<{4FjqN>nJQ`7}o>(JN>O;uO4Y|ftGWtX4^vF2r=w#z$Lm&@b3K9AZ7Jug=kJC9EuVc>U%%`s0ey3WU;}Obs7DIwVaK z-hBBSy-vpcr$@9C#bP((Pd|Ffjf?Zl_j0ao%(2i-nUobjfA0YR)?3P=#F`M8BxAw) z{G_4*$%H(sSA_^gF!-53y^-jK(W{OOgRtRw*Zg|p*&Y8LDe*o~jJyvaQmtI!j0}^H z+TrVxG?iqjV>&ItRQPHlL_S5O9i+$!c)OkC? zq^cDudu|5W&HRny=7089Lh3i2`R$;;-^SjADEwc=OAz zji1N4!2h<^3T%n5OI%%I>H#Xfghbx9qb{DhcrWE!I@9Rf~%Q`Nn2A+Mz~3ZbtON0r;l+0 zIe!jsE2NY>-9F*qXh5f(Vx4C=sc~NLaQlSK?IT*PgsBUb<63DdL(hoeGj9 z#S|0DX%T`JkM}?;CPJd5BF%Grk_Bpzk|cRblBYr3>_gEiv6$h2YB0jrhPobO2Kz`U zFp~+s)x{V~weyr>a3p^IU_w1S##IHro}lUhiW1=!LMWtAs2Y@T^g20ODn>=0>1fpK zuxG_z0|F4Iv?5HA1rjDPyfW(IkeXK3rju=m$@UIA2btGtS7fbKWZL852bl*^YR&F=x!QKhSG|9?;+nfSMv{k?>AXpkW452@VP{|ue4S% z!z={nHuhCgX+#uPRn0^@)lf`GlZ@a0+uvvB;Q!+PzH^`Y+^eCU6EWN}*tqGiOu9YRwI%b~wQc+DtWG9dKFWxxE-}~*aasA>v!k3tOLRpyS z9^ruK;wyxN^+n0~Z(QVSudMRcN1OcPKf2BPdn4q^O+=C-37h?UcMqth1yVwur;Mjt z9G*^?mOH5U@ZWuM%$+Ak92|}5wo{fnDJzRD4h}Sf!Gz`cl)5b0+&-drZI$`VvDQ}D zR?eNaW?F?!!`dj2wh_&6fgh@zJB3f)>J?=8}4=V<9EihYVY!zPQ+ zN)Ty^Y_chLVOjY1*9_dicd;jyFB{pDjEPmFU{AC@I_$z)tzDmh3 zrjHhg&KXQS#hDUYO|j(^E0e$@*OA(0D-aHm1iG26CYWkWIrfwjiK}yFrGN*paSEb9 zgzZTu&uL@O;WdBdlJUm4uK2e_{Sxt>bf)sQ9E*C~rydVb9#l(^YDH}g-mA0w zy(wUX2#z}@Xs)m|Z~xh60bL(Y_@kfS#!F3}rd+BFb177l2|szT!}f8>@oQjI{-J0y1r5i)Z-bePpYHaWJ(tC*C0mV(6fWv5afW zSP%9r)-3?LfA+ z5po9x$KRF4IW9Bxkmua0nH}sd4BsXnx}vMnm+BRURn zw&t0v&F-`Um*p(_8DIYN1+)Yc*{Ym{V9vBidVPAGgnL)sqVl9^LL5gt*xcn` z{N^{=&u1jvWNw=2ouw*EMh9c^Sw@kUh|vsJhg@u*VmvGGCL&T$)QN*?rS;qC=X5>l z;8nL;A(<+(upUV867ed)c;n3$a zQO|iS&9K&z=XHY0afc-s)YZ$3ub(py`}>DX#v}5wAc}%O1ceYqrtS`S^1J{J==Xj3Y7K%_RCWvH|Oz;)6-b$1%|ONvLNp2$)v8tVn;Jgn4j+=tHqk!! zNvkispP+Ic!yt&oT~1Q!gwVrucGVpgge4;|Xy-c_MOT8yZa!A=FS?eFuq zEw!lOi4Mny=Xf&d@F%|ay^@f+l0`^H4Ib?>?CbzL)tK@S6Spv;C~8wfUlyP%tUxS| zPRn5_ScrtgY1&b%z907ZZ`ZE0O%frTltYBMnZWlv&l8Xe8uf(g19S8>p4a(`Byy|| zv@CQigDB_GWra@^+W^o&FTZ(!4JvV=0yqykKvZphx%U8-?NMZ7M8QJ@WfDvjbAQJo zodH(2xP4a!9LZ|2xScMa0%UNQyq>uGw{6ferWt((5kJ?sWL$Z@tC;^3Q&k zt*XN7xSo5R^wihEc~4bVeBzNI|MNfiVVrlQS_OZfns=q}%#L<>RW$c+j(vZjqVk5; zG?Da~Px0DouTr{*-r|6w+_jTC001BWNkl3zX} z_N6aKr#oa?R9LSN42UO=3=g(<`RaFWaMnHH&td=GA*nL-R@TU~oYg_Z z+0)A`EcJQ&)*cmsLned-wyG24$Y{zkkfB8hW$A)yp@qD3C=Xs@&=xOwfb-VoipE4A zSjn98U_u8dbnJtJb?5*w2VyqCsS*iZNlKxV!z+WTyNZocR^T8B*=$N2CqWsio<~zW z@glUlU8=HTZ)b}nO^Kq2s5ICl4oXusC(;;29LJP(@$K+%pRz0w@t8=XN<~>!Xst-n zHr7^bKGA9k+3=;^=S>>nwZQ574zCQ1CHwb0W6X zowG&(?7P;{6Z^rj4;VOa+1}b@R;@s*-Vtkm4`+i)oEE9OV>O~b#dr{3hQJI(&?5IZZ@GA8z<>9%FA@oR71 z#0?)MieuW{nC0FQTYD2qr_gbP^NwyiCXNl`X~D{%OB^XScaEs6E@rF!}_g*W`+tJiqv z_905ul_gt|7`Sv{k%38x#4=onSy^28(4YA5-*g{c!TPQ_oE+*SzV{KIs*_0PExk^{ z7e4tYy`@#U3q39^KTXtLFFb$VQ;bAQP$W6Kwiup` zny^1Vk0x0VT_+zWl9P{|^T~NMKW~oLXttj?&WZUHdC4PZSNX4g<_pAWo3!1=@i_N( zr~K=$yu(f=h>Adh!J~MO^%de3c6!L;D~2z;^dnSNMJG*2V@JEtjo{4L zCGWfi@8$O04S(~!_r%$ zK2BSrMAM2Qlu=}P!T|7?kGP0*~fgRmCj+4pM88u_6}a~p`#Rtn4SW6 z!N15=L{Y?o-RJhkmVE9LkNL&HK#UUBmKRy-wYhbFlYiEBY-UA$BWhll0$Wv7C?tw_ ze67V#f9`P(rX}NP#^h+kQm@VH+t(SSj`K?`-{}fv;qhrCFTeCO>T}O~5k*-9l^a!8 zXSJ#wxdkGvgSsEuYo)}T9k9K#$I3#?U~#}=H}&nfl9ge^#Zv=XtpryiG`$B`Q~^9# zA3p@M9$QWkTM%nOdrNGB572CUz;wLB!OngE*qN@xvzYgE&G+lWzkA={n~Xl z@9h#NDeGs>QWPNox1uOYi)cfn;j=G3#iJJ%-S7VUUv}?Yd#D$B3+}ysER&;czcgI* zs~4VE-Nmyt#SEf|swi0OM10}-OH2;;IhyQpIGM4(Gozdwaq(1#$^JG* zEEm>?yuWeC`f>~JJ)1it2E7)>DE1FC)|R?drNufpz1rhwJY{cp#F^zb8}}YC&GG=@ zbKra)IwA;VRn_NKcTcoN=>~FGLyLf>fQScI!>ye2AwaIGAOa%cIW$^`ObCw}31RPQ zF@n0N7L?N(b;qFaRTO32baqr#86EsA&Em0Iax2BT` zWm({zBP|Lh;}Igl!wnD#o?hNNilU$_N{XVudrMUoq-iVMZx{SMtP5UBh!CeOqA14J zMthA1hplWdCj7uU{GlPoByO!Vj#_BNH~hj77`c@8}`{xzG9-d6I|e< zP{dPF#1}sE0{`!;_jsciV@c5UKJsw~nzK|1^(VozR3OEKjDuaY+#np z@abpHvA)#h-p&!5yA#f@5BTQW8(ciy(%h|a)F!@0fkU#rr`QX=&_ze**UOdnF^QXP{9<8)* zwY##lKjPc3zJ@Ets5o>5e0Id8Q!D&Wf9GYEyM`jm5OECq3qd+@9)SO4&$~J2@1KA) zQiNqyaO%{M|MKVl2Ca50kV&HmB;_Cd%U|b>D^oUeeYYi)C#g;<>X+q-n~*;UV`o zrgb1x@$BQ5ykMD5C(;DfD~lagmwV!!Z{)(m1!xFi&WRVuXJc|el=j&ylSeOK@Q*$9 zEW>_Z7TPJU%oy$O_?@ki!*L-EPXSNxX(%hAI3{UDto1wWO*FQc61&WwUu?@b6{ekt zs| zY7xgqwzsy}stP>NYZ=b2EO7gw;1HbkWV^eFKx=uqPK7;2T)^*FmRRe+;ZeePGU4v^ zH+`?=dG`6|BuQf)-hJEoDl3Pp1D<&7Ogvm{(=yI?Vnwgl3!+pAoo)|{gN+ zG^N!_=yh8>`S>N?UK_Y~-n}c&K66?9n!&b$d=O8Ks zy^T?2Wvk$!RfVtCmVskX@401J1Q?WaIA>^31$j~8tfedqiXynND_sy7O%x{>6QQ+1 zB#^SJs-mn4s;UUm*0p1Jk|bDSoOQ$~q$6b6j6BZ+1gSwW)POYaJho1j{>)Ce56`4h zn!Vj!lHN+-o;2bX*3s>xtn?GG;av8PW;FrbW2M<@MHc%#AB=XPs!Fmf^Q{zYRfsER z1e+2G9!8>q;i|a6wTTm~^;BNrr-xh~YM#7&hFMf|zXovCCBJnvQ-9oF{ z!^sD(t#!35^6*i;yMM*qyZx>^bMbj4N?|-`9pIs7PA&1m#RaZh*{4j_5ieNp#eQr9 z@|PMPCm`Q<1l1dAOd(2B>}~PM;f%lk*I%NY7R+V==NkeA9gOhGg7LwQACC^nYqPUX zZy4u(ssPT93c?oyuv!D3OBD0XL*jdmN?RkrvVQtHY}pbm!Ykk6}Y0pJ4cji z#?whaz?2!~^Z=&2q#XNdG#cm)0dF1#%W<+1sw)k-yZKW8yiQDNZW>uOV^%bbx&S9T zcV?Y0fANQS@`>}57E*1A<3JyD&Ve|Njt+Uaai4>O5&gj;`vC1q88UqdPc;y-H1{i_=_DaJcTWE4gnt8lau@!d2M?Mu8Z5UXh9Uso64xeH6Q z+i~!%s6%sSOLT2s_E(pH{Q2gyH0U$zwGm%=1WD2^-YZrX6p7@Nwg6w^oySnpjV!Gg zv4z7TXn&jp_`13pl(+QBKlB%via+tZx%su9|Gyqm>(jfslB^rqV}j9CY(z93N*lcDEyO<7tygZCm;KJ!}-H_&UVOxh_&lNpt>SP6!F zal6GdikXeaR91NOk<)zfl}EXM9U|iy_B-Kk+MIKzSEMWp&aMx+c?8B$J?OQ&`IB3}@j}PpU){#Kio;1JqiKP{u`(Pm%cjI@3+$~f;Ix`M zH#fuiph(u~q+W#pQV@-IRzy6`doQS3X(OyRQKUI{dIjqoRTZ%Q+dDff4Hr2$7;!in zfgd8ZzmG&U?8kYOu6a?`Q&z#~%;=bDSu&mFl$B#T9&>83&-(g02m3n>abCoDr*$C5 z=0)yfBhu}({B$~#R;xqOYU5o=Y{DLt7~zSFr}?`-_qS-JF$nBzJ>majwcyL6&t@+%Or+h1k`N#j~Kb7fW!QcGhzsvqO_wU`=mV7d% z9VyyINMpr?wFUn4)f=oYFYq&8dY*sx`>)eZA{IL_ckXU6ofQlR9j;uxOTXWy(`j>1 z1bB?s9+DL0Jl>8&mqKeyB#0J50U`vV9$zc3`I;zwVu(j;g)&j_qp1p-b-Hj4(FX5p zIr-XCrK-F6Wm(n*lCW<0D8fYHI3j{XA=xX6f~w4qlbs-XQ76iRt*VezC<%#>v*_Be zw`uE$(kN|6(-ftHX=fu{Y;A=%W^SmN#4)XQ8)c3KZG26}4y5*z*Fff71+N5ql8p1A z(Qs~nz$HmCOuKQBS2%B|9HGk~iZYvk1eAwT8XxtrDyEerT)pz9T)X-IoC}RhdT6EbE+}>>LhRza51q$y%H`7omX`*>XUC*eHbCvlV#fZ# z9^MRzb&80uuW7A>SgV|6rQm%B*Iri-H}3i2$^|+LL(0m|;c2bJaQRHnci!2Nsb9f= zOaS>S86PJg-(%!iroD*LTH&e^qTpfCoo(^6Uw)j67uG4VLu^%$71k$7B2i?>#uIin z@A`v-30At|O%J0Zim_&rAJXq8^!p1$ak%`}hQxt-b9>>5Q~by?OZ?h*c2V9D#}P-< zf(Kh8E}dP$XyM|iAz5kp`WyFI8Fs+K=I#VU@#KXe{cgg$w|1$lr=3I`9FDnoW`H)D zhg%19Qca{B4>xxyi!!*%+JJMn-XUd)Kib3CJdnhlZ-BFP;B*3lRWHb4QEZHk8WolX zANs){Ik=lP5G|>%L4dHONy_VQyve=yukeM>eTL^>_$2G=>lCviirI|K(GH{CdyGbh zD3|fnQ%`XH{)n6Vdt{axnh;vvLEhHa)!=3W@+cfi*R5tHb>Heg;gCihjM~`I)(M=S zE0I7QB9{f;m0%K-FDZ%)W29bK9fBoxDJWM1mIC4MFL{FX*Y9%`>iZpBl?~IQ123)u zrM%XWC}q&TL}4*_N?RZflybN#59H8#QE$MB&Us|Mp@!frdJ zb__X|gl?W|XwcmOa-LMMpm2=LDtqK4!am?QK z7XQz${&Ro&>?8D-)@5gFlXh=Nl=dkKM^%<63Bgg6M2K_|B}`@oTRj$7C8s1mD`P#Sq-FqAIg)jYe;-rmrw!T~<#zeGY?Y%8!GC8EIDxxTrPN#!0 znmn(hF{*QjkK;r(?%(Fh8(;H-;ga-*rzkCcxV%EUy+BbNN?z2@Y@IYF{T@(1JN`Jw zjkLje!P=m9S6WA_-KDpBiOucn+`0Ltk0K+s%9&=?l%=om-Wy|B9CT54C$!R7mX?Mn zT!07FGPuoZs-(h58D!xJe7D(jLVsy3IFO%syiH_qwj`>Z&#NLQn@wI@oQJLGwqnx6ptPnN8xBTO5Mgz7z^tsO z&`6ZjMwkWS943lb=na{S_JbR_QaB%=!_83ANWBM+MLG!OuaGH^OnRgo9PT=uu&B?v(n-FeSsIy?SsbBOw9L9*S~1-hIf z&r#DUhX>8?%pV6DVHd1J%8EQM7*D5l?h@wPsQsPHJwDv$5Unw~9j;Bo7omYpD@2?6 zJRR-sLP#>o!1urjS{rifxwSbC%2buZ#34~vT2u8-F*#UZr8Q+|bCX~DH~)$+{n(Gn z)6agA?!rJ``_6axx4-f)+1=d>K45wgdS~!Tp$Lhf^&VFRp%SeeiJNeKb(Ky#r7SZl z8=k$$C}y)Mh1Hn2gD4%GIwh+2gPOzPD`I9;mByq!^3gui@xEVNT9qJwF2QV7gylhx zR6W328z5NX@E;CrJ|2Ir@o@t3y@vNn8BspZbTK(1>P5KenCDIzKKsJO&|-B4F)6yr zuvO{Hd@4KJ4;UR;k4c$K&ZQv^cxkqja8bw?!OBZ0${$%qrTgm?thQ(uy@ns!<62 zcEne{d6SiX%-NL=Po3+r*zfTE#y$@=c0y}6PMIBz5JD2*s~lezNRpzf1f^vj5H$v% zO$)bK$W&d;4KV8yosSwl6R^a-#-#?i$jC$_Ny=n0#alZ!#@jzQWOt`T)Tx0{Flk$95 zf-L?xc&IF<)55d@)Xa$skVNlDw5OA3(j>xK%huK=Mk|yrsb>2ejE?YCRx3sYB5<>* zLrA{TG{%^SqKJGISAdrW&e&91o%0x@7^Efm3MX1tmim+qr<4}!tcZ??tAg?FF4c63 zj$+c`3Q2c?o7+<+e|&>#^DfIzwz>KKO+Pw1Vt@aTtM6TvD2jOd&F^?z#g~8br$uSw zy>lp~z0$@hyjJ45ee;?;c(^HfmeK2Vxp?U!gW;+#D_h$_hu|enQvc4?`~1eQ|2sbY z=@(g9TVpnz@%hhxflt5mnCu;8M5=i&1u+_<0*?OLgAsRk#$+3ZJigGToEdy1!? zdYr*v5$noY#KWLO`Ge7fy^*Cb-p^zvk6k<`Pe1u6tt6&(KSCRW&%^W@oL+{|A5cZ9ixiKAVhvns!BtL1`o2L$8yF5hvm*uRux{ z4F8fS!9)p2sOW1YM3JstoE0XD!+Cj+stZBX@1reBbUVUCidLF1^OkIuktk$wI1DeG zD`>ZSYHxq4UVrPh?JhkgXC8ZAEuX$9ag^5YY>85u$QZOqaGfF3q)$$XUg&f7QlFdI zly?sgm>%wN*#9KM)fKj7!1QR!!pdnny#cca51Hf^>owoGw#|ie%UB0reeHc#m-}R; z<=q<(IkVDdcU&^94!C?_m77;?Gb<}}5<~#Rnp)nw!s!Ap3W+-Sx{}^-LR8&m7mne; zVeOgkP>87DL83G|*2iGaCb_8B4CiXElKC;321VEpoe#3TN(g3;zM3Zhp~Ko#-jCP4 zxp8F3_UmFDL8{m{9zNkSRqdwUG}l;sEdy-nvwD^+(S0s_M|#jhqq zlW@)EiA(Lxf(KugHCMyXSs0*OiyT!oM5^A4L=>g-RHd!qwT(B8$Mo08x|f(79PP@aM+jkl5?-FUn?o46VpClTr)ED_gLaC`GjV+x>ab|6ZbCxU* zf)9;vPhJ#wNfDibiayj?udl0$Fs8!jic%+d9NFxs=J@DZMx4M`JbOmYt!;5x zm=-C~!VqQJsIbA+D~8}naIQ^JW$f(FIM?c;O@gwSM9NXQ;7Wbr^ngd#+x)@1wkO!#NYzoEL}D2Jh_L|6^VWk|xmzM6|Fe9|w}&3#uml`9^-E z{&^$$?g$A@Rawfa(Xj`mB2*+?zqP^k&OWQl1JX3Xi{WTIq0D9&<>)PRdG5uChg&ny z5!Tg#UQ+@4KtaEDmDXxr;R)?^A7ENFhv)c%>O^3ATruP1cm9la^+%1yv?}aZ^=jW# zu;!bGpC7v+W-EO2t2D+>ANZT|6D zDf67d&gu=ULW~Ywpp${VhwudW4{X$PI!G1Z-NP9Rz0})eRqo%t#jJ3?(+N8N-Z|1vi@n`#|3`oH|H+LT zw<&B;K#C(x|Mj=|#IsMy3!iwAC^BA@cv}_(U$4k7tX-6`@ABZ1AN0SrH+TaVqAbX1Kzv4$-n-!-yq9!?rm(cwR3<{npS_6d^VwS-h1anDdmv> z2YLJLx8-+!@2hO@9imM_r`u=uXrG(6?{nw=L%#UR%Pg-fdppf)9)-b6#LiK{LAFJ8 zcay8v-sfxI_y(Oc;?Bbn4|Wdm-Q@uPsi7OeY_)#Ryx^QrAw))qO?ZeClb{tCrFrJr z7kNj;>aA~m#qVw$s)hb3Iha<_!;Od1U0CqDd;30V^(dT{!=o`CA&P^Gd0B<`ZZfO5 z@%|ld+HqN5001BWNklozD&Sy@I$hpcwH z-~(|vZKdq*@54lqO~-z;zv;I&_w;aasN4N>vi``Y&0~*0O_Id;Y6SKuBwrr9pJHb@ ziwgPp?Q3inByIu4pECpMDoAF;>Pohwz_ zE7&sg&XpeTwfBy)4A)MSVsUZ6;YkZu5e2>vp-M~~6 z@k$iFDp-zkp1r&xMp-gfA_PM?=Nv_zGtDeSOQ@)a(V8RzWtw0(giY2uO5Gwag~Ou> z?Ns5Mr^rh$+K6+GG>LfZT#w(ry33d$N-QFlqAExd#m-SlRaqh>wHl-kiZ41Cn9cGc zxb;?+R;*d=r+oJL3tW5eHk+IKc%@nHwdkf1hvOMhq=;feIUVDz#Uw3!6cdX_5f)NU zSkQy{vY%s6q1Na2O`)O==ITy}pa0fzH43HCI^zC=hy24|{6!89M@(ipNm>)Iy(hPt zqbWQ%s<`rSYo6@sv_q@i#uhXBvxw_oyT{lj*k}PKAl{)R1dzuCp1{!wm8E9m3Ht4! z3jz%(H8gta_OqkjXpaBi1jXS?WBT`l1p59&RW1BqltSr9g5nU(#jSsAYl%pi&*8X& zFLgz<0m=B|@6&9$p^MN+NXq|!+mM?GgZSP>gVf(xl<5QXg16yIrKG?(a&evBwxn~h66O7lNB!qC-@&HCRESe zow$0IQ%F(p& zt0odDO02CUi4(G-^sj#BExCH*eI}EfvMeNtBl^9oJo(rqUU>dlAIC9ymemz^#blbv zZ+_)fUVrz#tgO7vbUNeAnX~ffBj-UP_I9@MdXdUmve}f%fi`L2CkP~whVGC*y?KjU z|Kbls@Qg=?RAq+IN{$W=xOlo3uCsR{0#O_>IXaZz_^scO_io&wH&~;)*bleWI}WEK zzVb)k#Cj#4dFiuYEuwUII7}?J_bjh(+(#t~NL=y(|x7sb^SS7+^*-X45Gqipa8@IBBzd>I_OW-@5XU2mi-EC5eJTXI?qK zf0&8qF4lVXjxvTT>m+F!0?(@A@L-QTo6+m_7%ukN&c^)mul^3L*mLdHRwAY&XD;-4 z_rW*${Xh8*-g_z=LAdipHw*l_Lc4w)6)%mbm4J}U#ZUz>Vc|K#fI3S859z56#9LjU&X|-ZT zqX4yRw>!bd2T#A(=WsN_<`Wi|mT_J%8qzeVlkM&8Go6ejWcX~Km0v=WStu&1q=PcS=CgXh`Y~02^dnt5c8uW#V&^kuQ>txD&po{W>QKK^O z!Ax0cBhEurS}N;muNz_O!5x3=&OIEDN{ACaW}yFN$HxiC4=}va;*=t)3WhE3Ppx#t z+KhRSQycG9RVkJj9W9`=CXOIVVoEw&V%TtZLC6oOKr{+3>Q6<$q}RdEvjsU zC>_*L6g9s^5FOEK_vtOIqg3<*^bi`ur{+>Nj_l4K*W_&7+6_u-#t256lZQA_$@B9z z@CiV`iT~F@v?!`F$CepjnHx^|lQPlXM@e5qC*OAt^=i#r9yjc`;XW&cR}s|aU(Nj% z0WHTk>iMx6%)z`vcs#`>NNAEoksx!q`|u97m>{)qfVB?is*uDu>)Y)X%cmX{lXSm- zLiGW>^YL)?_o>}~alrw%!9{~7iWIut<*Qfk^X9E@K~<9FIfe7svJ{_1TpSKDQA%a4 zN02yU^XX4MFTOVZisOj1)%H>UjQrty zN2og^P!aK+UD|I~=%__*`bcjH<21!+jP7*Noo?tFz}gZ-ymgMZ-hEH@4#vcBiira3!j>6vk^*2W;m-Ys+`M&%PdxuD z&O?^Xxbd7KWXK%6qD6 zo1@W$ermY1l<@iI&yeMgM0q9-8U-dx-F=jBU4s>jqH-2jh2o2u7qJwM=(yV}A+UE? zuHD)sQbM|NiE8IMRX(DOf;%{bpfd2SLcv38gE1z&*AfySvzgk;hfgQI>Ad`OV0 z%2IeuVp5a|pYtMtKV=XWbcRf4fzKzV#kBBLlL@owl)^e@ zHp1&xyG+I>*wJSWY>#%yelQKm&y^CNwoI3{TuVV|IUSAoPQ_OJO$kM}l+PZT4xls;(> zR4`=@MV6qXSFp9U&Ame}rHSzeZBN!mqWsVXZrlx6T(hKpT3``iWO z%sL0tlKb0Zo;<(EpT2RAemCZcivu1%+hehtki>@D8~cnW6*uo4;+?~&DXA*>_WmY$ zX?gF)eUvDycNAHuEP&ugN2qqhLQAo@KJX%*ja#>*r7XV6Nn4sssd)zn;Y6?yDiin+ zKph(rHixgBXHVd_nqaTp=_1{_`t3cs{#`_?tb6<;cHkyNLG)}O(}(Sj{I;FL{OcTpd?e@FXuyYr;`?T z=@Oe|jzksG4oOxy9TS@ko_gU7?M{n4n+c*Yapd27_X^i<-IrE-Aw1UxqNv4eI>9=N z=!7@keoxMcbLs`uHC#tl5}XbT6M4${7bAY zsccE7-DNyJ;O@P9vbMGs)VuKV$hlKI|LBN6dFKIM2jfIB5k_ikyZ5!~@<|TPv3aSl z;SmjFGQjmh0Nah>nagK=6e%f7k2Z>IHsjvLCZdCvg7u-OppCAd(%?cpolJS~aEs@j zab84`Wiwe_S?0{zfGo=(3Tt#onvavwd4J6ZWg+Y8zMX*A0+B#xkt1(7tjdry`55gh z#(BnmDY#0|7?PyzZJtw^R4@gV3#xEskt6lHuT5}5Ptw5i%W~!(4y6#_CUN*3kE;#& zJXKZ9p*BU4<2-cQDX9_0(;0jF2M912p5o5lHr4b1;|s7o3R>P*nTV>p1Y{^}5M!{F zMfr+T-8G(CO(_ueFR$>%8`pTSv&qKxBP5+RM};G?&@~mQf!)0cacqce1(ne0#5nIc z8i%>2oi?-5(M|$PNqHe{$2jMh*NKj7UokdH%$5aXmjn@(6f-Q>h9Lg}fOPdv597?A_hXadq8bl-e zWnI)tF=GKY4rqpAOgVap#Skwql6K1g$JP2IPl}HL@*@L`kH$vnh6y?2T2`T~%FO>#e)r z+|L#feu&7dYIbw6pF0SU-Mm#dGf$oq@qOQab4Z#X%~L4OpxmQ-fH!*(>(P4=74}=Z z_%ptr5kyB+afhSfm@*&vy%Vo3)o9`*BaMYoJ|zlf0!}6VYzpU-b%v@ml*N>Ky5oAi zzO1aAAkvB|L>0tIOr#vU2V=%`u*y@?wQ)`ZnNp9 zL1+*cri5TkjdzF1!sN!Gl+Pm&Kq(iHJ_(cv&r?<6A=oHNr7UMoi7z6wC|T8uIPvb{6l^jeE)Q8PFmv$5LYvC~Vuc5UA$%7$r+sWpYPiBezS+Ok9f zY-+3`jx4F0QXdRRSKBn=rVNK8+;|(}2wT;ZC_h06jzUVjE6}6Ua6k3X4-1F+WIGf; z3zE?MAb$jfPz#vWp`54M7;CAG^`U&GLW%d}&&P+TxQV!md)IzIRaSn|q2tBoWCNXQ zq0)Q!O}^uw-}zIICOG_eIXK)wM;URF5k(1&Mn>%_tgF#+OLW}C)&*H}i7acA7qf-P zaPb@G{MSdjh6Q)n+ggf>5ETi|(o8f`8e(c-Vp0VE#P)I6kx%wNlI z=FY)%GGRO!GaL?yq!K~MYfutNk|abL9H}^>_qb*c-}b`>%PsytrL+_A0J(P>@sy9c zEJ4pRRvgZ%plNyMwQzxtCE*jyF%WOK2%;XQ4d;15SyjYo6I2tT2xEqlrU@|$EsnZY zqN4_RUXo@7agzRc6vRDpO&?j-TKe5KXV!ae`^KT@<_b1>jd$rQi8+@)+o>G zwl${A$;kQWvyZu6w;{89MiOghE$-&cJ5rQ}H1Za%jYfubkYp(~2t7*!x9)6n^5jV; zA~MT!dhIq(pWouEuiVFIjm|RA2?n1{AKdaNzC*?apslkt&CPc)chOC0V^m<*=OX-Qi7C%~E-t9&|q z6l_+bDE9h#7;fMjXPU^Jp_a(@1~({wr= zU*Kmww|4SLnaxTp1}&D+c#J`4HJij*7>=e~ed8wo!(L9O*WvuR4Njffq#JLt)N7HK zh7X=!W9MK*mT7wZ4tIA4Jbq@CQ=7|_dozCiBd3WY#fv}KCc<$3%sTtSlC8BSVjcTO z6P`J@!sWO3*xnm+YQ4wHZ`@;Kaug~IibCqP14$Yvyc?71Zc$|&irN>jg!@Uv+cnRp z^Je^j>hLCsN`O95(nq&?6g5bs(N&I^nkY$-rcjE;#un#lk|gEA*-dOQrp!xj-q~kt z6q{QcoZae?nK8~q#jKsiM`;^{1NCl*`R;hFP4Pan{=8H!&%M#@iaIxDy*yN zw=+8Jl)N$=4+@O+W&l2cpvEa3{=5rTyLC7RJcGeMKQ^Fbo|zyxKbR6nmGpSy&Sm!Z zc39ik^x>mQp_L}inyjp>GrE13+1L@K4Rln6>=lpx*TzxgIpz4S%i@ZYr$3<5v#!_EiM1k9TU2bUqbPH* z6)H@e1#grvcQ<-R;XAKt!oNnr^~D>;_y^ce(hSDb&N_&qNamjAB^vDx!z$&a%eRmKhjmn7wiJerb9-f z30b>=tqp0EAS#hY>TpD;xJ8sE=p-UZTU1p=Rp#hM^PRu(hpSo$UhNT{cT)L4K2y3V z((=)de8^q7xg&dn!l&h0!(=wa1uclo=|B#@8HXa+-(v56EfA`zU^pD$&@`Jp6g7e+ zHZ@wu-e5pdf6$7is!E^#@E*VK(Uxug{UKUV(V}r6AUSniphEh%;1C;H&_}L`;C$YU zNJu7r1nmGGTJc((aZD#;U++c^^zNi7LP|l{5;{n!HBvDN}3)Z8?pi(Wy zSa&=eQkFR?Y0`)SKV1}Y98=Ua&UuQ(a6FbdLS&33j- zDoelBDNR|{n5ssn7Cq-rK60xn?LU(#N}gED_^&(iHQh(fbeIiae3hDIknTRF z>4@=Y;HUQjQ4|qr<*YT%ijq#JLr=$U@8FQ5cK#c^}1&*Ph2-hTaMj`w%S^PC6Axm#Y} zl5Q*J{_O)M+ilK2{XDsf*yuONV$J7&?jo;Ud%)iQ5uf|S6TEcg9@bh`Ix)l1l)-3* zbFi`2rtx;nXq*R=6~P6qp|v1c3lR&p!b%EJu#^v8%c8)UKt1)2u}E?nB?goMO0-tqOG3ptZ8%|6T=Y+TigsYxLX!Cr@^%U5nMVWo{i=R@#acyURzP zy@0bdH@6RopSgh14La_Sk3W8r_2m{Xz5XT_&pye~@d3+bkI(($r?`FdI#(Zzc*iHPAZryr{$N#L!QMs`u%0L%97i6?lT-riQ)!GG^ajOmow`8kVK}Oz3>59Sv%!z z{8iBYSc8g$d$(`9EBB|8M_t6!Xr+jf)L3gDEJ^d|#~m^6uOGeMZ$N&+^28&LCptWY zT@*QrIM7Wha1|oTAH=gU)>Kqcf;KfuTO6KGJ3mmVJm$vz zV@CNlMr)RqyR3GbY&S@#Loh`~AKGgt^yqqz}@hgEopK)t)f_JVH3(cwPR$%v)ZlT3yqTs1Y3LBM{PkT zJ|jRxQRD?l>fVJM$YT2Z$n|=UfAfJ<4rgniUc47its`*UJQ6ZL1Qye|_x#P?JfN&5 zOlK34tVP$d?|@U+wKqwy4vSBL zcHx=OI-)M8z6te^h1ekU^cL6-<5Up#TTE@J9VEdCW=v)QL@W z6gyXXQTz6TU9R1@MIx4}nxJcMI8at4N@=jhBSy6)4h?NSo?)t*w9_Pxl|SsA2^1 zx&Qzm07*naRK@x87rX->;1kXktI}(Z}R7pZk0K z*}wTiuDm^vgZ(|G(;+xTk{XOLj7LKTM|+|0g1V}`Q<8#ayH8_fl~@a{M#gwJq9_Zp zW(%dX%w~mj+f7&3wHq7_)Y0(>C5B)6#B-e4TH?!p`A4?cZPDng$XD-PlVWh63y(eN zlJ=UkVvn-Rf#0*VxcM`| zJby}SkGOkXn`b46Q)nG@Va_ca9Oo$O+&wB<+QdZ>W_*a4nsPj%5hEof%JIj4 z@^6UK26qliK6GN0fBM^>qutc3WjWt|{Y^(cmH+S`{4$^UonK{Rwa@vrlz;sf-(+NZ{NSyb2>uze0bSR6ZbT9gJG|rCoHpp3MLBPjv+y=? z4g=mQT^`bFt#ue@SYGL}vC>EB0lT9d8|oK>rrBvRt1L|XP^>bJ?Sm;ROD&Gad7vdq zpwkM6!-CDV7Wu5EHX&%(z}%i}?majkXfAac;2h(;!eD*#gJ(3vu_B8UwS~M6$Vi-W zpttzaw_f9CKlU71Bg53*4!#cO%<|GQT4^5a>@pk=Jc~&N84^TG&Z#ht@l(#KtY|lc zNL!-BNfJk)PWO6*2m3>=Y}Zsar>?!F-rnFYlS$6a2V;^*lNS}p042gKFX^=s8nI%n z*JN*Rz|QUgy$qts0khID%!GEDaN&s)PKqgOy+~G@u-Vsil0IeCVKAPt+HbkDr%p)L zY_oGP;t!XFH(q{$rCtjar#Ne=YfEh^Y?Uu;46E8=OzmxTD~qv~xvs-lkCNyp3clsS z(cuvX2fLg;wMEuwQkI5;y&d*;AMiI{`Z7*pe(TqNlMi0HMAmH6=q%%aMv^cc9`env ze1Q*LdX`g33#|ghBNTk|186}Mn-{otiCpe-&bT~wR zh%ojD`te>%M5wBYqy0V7MvLYCGJ9!CNeMa%!BKuP97PdYYaim2mo%&;PLfAojfeCr z|GE63HFrY8Q>_#r8oi*2Jwnr4G}|V?>>g!ND*7Qh-@BJX7z~anii)%uc{|(?tQJKv zA{BMzQ{r)9dag88T`-%BNs{Fsd7T!3(htA1^HVxwL&`Ow`AbuxwB_Az!m6v1DxV?F z5{X465p^9im{$DY>YH48_KAgnMk{1_d5JgQx=oo+u!#?H6LFA~D%n zOI=m6zklF`u62#JHMVr9SkXvgYU`(*SQgVy=fD^*Ko#dGii)kJjHgbla(H+^RU0~4 zgEZ2Z@fI&%y}{P%C6}bB6lHS1Z{8(~k$?PKKjRAB6&trGiI|o(r`LMC_~tGzT-ik@F(^+LGj)yi z>FQVoA2`$FxsxptrHGRlV=V1haqIdLJJ(*Ksw(f^W4&9=(@#C_KKQ{)^7R*9Vmunt zYPE>9qAYW&vLucapZd8^a`NO!H=X6!x+ac=(PYNP<{JO-OwXM-vBmR`ofT^x2ct2= zX~iFW^#)h&4TD3HA4KR#`$@E$7hT?Y&lpEp*SM;}YE2v|hDSRb-hYG5wI%obvp*-_ zF8A#Att;-r$-epIFMmXzxv(Cs^|ZZgYpLprC^V@8Bymhx>egctCxX&3T6?#sByI4WuYDh@ zn-oSkv)Ln08eBZN%4a|RBsbou`Ma;|BNNB-=U4d9lV^DO#x6yfGb7gCv9_ksYh9glC2J^_S`M8!)|VnqEJg0MVJxV~TLg#Q(mRy-5tp7hgGlA+EU`a`Oww@e z=8VJRZA$AznyW|&v8(+7y)?4iET?%lurkN!ycN*lAf$OzWS?ef%;UgFMwNE|6%F1d8y7JGQKltlK1?TX* zTx%?~@xJ3qdAg7_-ZexA2NGu;_qMmWcYmA5E}o~;?oeCd&8x5T*MIrvZ0}F#_B*tj z8AUO3twtsnPb`yWO{TLMZ;$rqudL8t*JxF%)@DmNmoX>K;-+cqGTd1=p2u z7^)~0Q3_*gtSKKR^)mODcZ)*UPyKjgipL{0`#X^k5n((WP*oM}UX#gWM5Mt+KEN!B zGS7_;mqhSWwc0B3yrk6*((@3FA_6L|GCoflU(__0Ia9(1kQ<(Tm9! zbKjI7(SInVsH&2|(LO{?v`)}k(AqaIqGNPq@TupXIu*w$S)lB)8& z=KBwJD65jc|GA%aM^z$mmeKC@*j!y=z2D|fzxgJwynTe|coDd1tVL-dU0z11h`K6x zW~;|P{ne-0J{XY3F(;PWL`wM93or7**Iq$KkwlTAs*L3Mj8iAJ+~5DrU*k{y^v`(v z<~4f#C6tOVb%m))o_hQOpZSGPIweS1l`?al$)1~5R!*$1q3YZ%HDkVTbVYWrx-jESw8;Z zXZZJj=XZ!=Uql}6?eNyMS6EqDBkip7&68Vv@4Mgg6JlU8$z?Ror6_Z8)=|~Q_1g_u zTU!T-=r1qP>$hFA5!t7nenQ2OlkdFnbu}CeS=v-C7C+BcqAAN686`IN1+A$Kc@r8> zZgTVPHh=Qv%Zv{mFiX$iRG$|vZ_{WrxOZ4`YQ4kYAm^3qyL8$q-?_X^nkFYalzSz358vA|20?{hdP&~faw00eUYBa4B9H4hyD7iJhrJe^Sm8mA4^8c{)S zU@-#HXb~@OQ6D{ka)iY)8XVzdz*Cn#$oVrL;q7bJ5iA>rU-1*ZzhJztT z2fGaHc~RYyeBsOAV5wzjHX?WJ?fcx%&x$nKyn6jD{_M~GZ#LIj?wj9!nQ8WfO1Dn% z$AA81%Gt<`#shcz2v*NM!`H|$U7mN=M z_GpIk0}JO7+bE9dciKo!C}9!s=;`gW+Fd_9 z&?*c}eN$EzB~|6=nOgh3JxgOoM|a&{eC4~mIyo(Ra}`q+R7JshMiEhbHR`C>-+gMm zzkb^FegpDj*021^W79wQ+gEl)bdC0t*QsuE?f!(S28l9kU7*DKlE;zI>MT>&6~{+! z+uY2QZEaB1Nk|3t$VXikM9Q$f)+LDyMP6a7bB#pFyeq$Rf0xU5Ml7#g)hBMuML1bK~xP#-kDUb`H@> zvA@5^?YGC=-X4gm#x$~wByCdUGcTq$6}VceS~=sO%yTpatwxhb`IKwF^%w+$HQu7p z54|N!v^7YAvj&2bh38_&-m=wNoHcB&o#!LZUs&iIlB`1}6K?!qox$iXjV$Hp=*X?F zuThpwcX+rjt4kf~*$lBW)|T4TRl#U9rmkvl0Xr|$o#)1yP_(Pi0RE_D>YC$&2Pm;l zN3qzzNu4`f%?ngS;Y=NbzQW=0fV`*{0$(-v9Cm@T`a{i!wSHq&Q7XPT_h`VpJk~NV z9l)77c%g?CCP_b;>g6~(*r6;dtW(VLDWdW2I>F(`qj4b(S0IXFVuzcJ52egAnyn6g zHZ@0X9-%5Zz-iCDhERMx(%iZ5Uke1vTQGY1#3P52V$oPVY@i-#6htWU8Pmy#MkgUo z5?9U?N^5^*okd3pN;|A65#1opT4ZTL5-B-89#a-M&A9WP4ankU#dD|UQ~*zh@?m0L zY#t~Bi~JG)_pG&?-R$z~KmR0Uah~JjAuCPoPOtam_F2taH#AyB7(b;H=PVoRtMchj zeu6K3!!_c03z0PblVPkcLPk!PftgbGH`^BMSMOl_~vdDen`3sEdi0!fE$@3>T zz0~ByN|*b$@AB%69jposzJO>!qk=OONa5(lj;NmT;j^nWvzXCnjG)lYk~O=C(mr5P z`RkSEGkNC8$6fZ1{vj`Z?^SN!-;>H%R+jrb^Vk`8>A7df(paWb?3->M3v05frKcIAetLeIGVAdohI_+=@mMSgvrD^O`P6X;pST3 zi)W3U0}xbYL6)TQ%b)tFd-{nBJlNf1Hk(Pa)p6&}Y`NubTgs}$8Y4bqN4v7DSnhS@ zSAOZ!oH_TnbXrYry!{5#;XY43eF-HosTUbBf0`G!(!4>(Kkju^VU6`E?@Ch|pAXS$ z^<=nn*X=#HMHDNXEnE~OD4j}GRbs6Xg_e9e!j=PKC|i`_x5wp-n7F`OWa|J)-m@FX2B*mVOp3#ptan%dlck2!6YNthl|XO7X&xo zF=cLO;ivP;&27&m?6V#vbQ0VHorT(^{jJO7(&Hk)#1vLxTRKP8G&PINBt`+xBU8_O-(ot@S%ym?5w)#S00=lFwf z+@qga$<>y;aWHfJepjY)R{rOIdzEgd#aqWKvVUvaomqcOzH)Pq?>~5pQo8c`e!|Z2 zz*9K^t)hVDdv`oPw4Bp>L9FtkbiAH2O&f@HD3vUBR#Cp`uWJ*2Z*Tz=g+!63jEf4| zLs*b9DYW|x3eF=i8YU2JDmv;vIPygyK_%D9<^IW)ik;$y2D5`}yj1uo`SUQ5eb|5E<>-~DHI)x_myT(DD96;}W0)Ob z>lrjwc=gVRIF6j_oJTJ=|u4<{ggqAgk>A@f0r-vEs<8#{I-;YPYj54;NjR59h>Dtl;b^@2vwOg zolJ<5RFqCg;)p7aFtyJ~an7Qm7#%eh?mSuqV+>_wuyu~L);C#m{&Aqwg%?4Ir#y+8 zyL{9*S39jDQOX~%#`(`6i~lIkfe#J9T%h|yAK;OXBAB{nG(7g2BBgK=fkY@(`2sUa zeRH4`%K2tcD@7xXWUxPBI!S4^JBt88kLdW{@2q9vQ1s~gn7a;zM0pjQdYovKJW?dQ z1G;&SrsEx->R|)Y?ya!g@5^kshmKoBalANyeTabdLh3l7Ds!)Ms0zwrMyuWZ5nsG- zV#IkzlzD#59Fg%t`H+4sf|V$sK%w>&XvM;2ugU4CD}_`#|2ld6N%c zdRFExPl9iBpM3lRt!9%~U%$eG-Ce4xCQUSFA3Mi~p8tSbTV0W=s)9Dh8!F6-(!GB9 zikvxfjMG9)8EH|URM-3bzRHJ%~jSv_ls_lmkt%VM2o~4sjG^zEYUie`~6ZB z1!qof@>{?0>vUU9lt59I3=kURZ(vRBH8SGSzK1Yy5YHM|YA8;w_Bg%1#AG~V zeW^=Xm;BtvK1ix&7)0v2^31b9UoFcLt(0u8^*OPzJSYE&wT7aY$vYZRCz6*Xo9nB5 z)Wy-wy@b_O;m7c~C3aU8qStOm6Q{1_Ghp&F^ z>-NM(S3rv+Qu!n|)>KYwjn?9n_~NT7D_U7fZH%*ZC0K8mcHNUVZudW>RKsp8Js6IQ0Zck}=n8 zA(~dRfzb`5zeTdVhBk)MI=*~)mwvl}v5;3O(pjNExV#radTYb%)_rD$4Tcx~y@^0w z6x3x++H8cOh=WLDjf1K{ssfc{i_Oo?^MW*ZCqYkvHj^PBM9p>>Ca5r2a8%P7wyH=v z9Rxy7g~e5tdYTjUyGWyj?XDry0nP3*P7m4HJ?0xPU1K~gIeliG`+Ec4-g7*4?vmuj zN`BA^U{NPW*o-G<`{X_fa!{l$j-#Uh)32~fJ zm6dN)@Q9s`VytzGL5qak4$<9jIMMKnTOn zt#t%N?q3|?O#uv^Kk|u)U~51O~{T3Xmv2zu(eRFJkA#%l(>KS*ZgPy z=ofkHiN}G&Q?&wJSm}ojdBrTJDs!r;CXoW4NUzbVWVpX$|MG9X;{N#iPCe*6FFH*a z4MxnyL)xlvEmePgt+)2lk2qA`Uq9t~zXACPE7ROnt{PC6n_>#$tizi-8GrNbH#v8z zPZW8&Q5=al2Ul_|U%AC! zeSeQhdXXsBv{TLfqF{UbfYoja*06s#Vm4dh_Pu>>-#z5{$2QqqYGbBT%3_Sx!B4-n z3Zk$Qfz}YE5~mqfGGCwLEb_85&OlvT~) z;l3R1@6hS?IXc+m_-LO-8nIDFoH=)qm8B)YJwV3^rf@{gp_Mo#N*>KBefI?XowTL8 zF0r;E(!RRXaYB@2-hBICJW-@6mV zqEt*Ad1S((Q4)p2Ci0u+f}=DSUH<5Mc251Ms&YXUQc9!aMi9~`r~psTKfMi&bWxT# zQ&E?>r;;tgQ2-^u<>=wm_Z_c`e;uV`uLF4maeA-!8-Ry*HZkw|h8$%v^WTToR8{T| zOr4-~j8h>HQ52i1p}R5PHu) zfU}N%BjSk@%iO(n!`U*I3#ZP?bT;M0=YN6MxB46(ANgldt4C;wij!MwY;CMC7>tP6m9C@36 zOzWqRPHW1lCee;0){MtB#dP45SV@zZrFKN5C0Jkw-+kxpG0W0FsLez>9eMR{KAU2! z@qu>%%CgQ;*EPLFQIB`rs7OUbF)d1FMNO--M7z}_R?hDS0gV$0&&eE?5)f-K`Glh* z#o_)ArkW8&nkpZYsu~l=R5siL^Y&H(ovi21+ z{@EQ(E4EIaVP$!R$=-mX_U*F{@2xH?s_7J+B_vrEnpS_U(#X+i`ohNv-dW6Qo_y}( za`){OuD|&b`M{}mf0?wA+C;^I%UxcSZdO#Ps4NG^W5HS%ClOWc?@nti$D@L~_jWnj zzfY?fJ5dQc_wUKeFTYBE`2ksXgM0V3{je;A7Fz2a+={Xw4tvLFFm%(&5alM)$P%@> zaZXQ)MEaYL@v-MVE~_i6M3M3ZerUQPSCVN*BT*jvb_$d)=J!SwJIAHpYb4N|9NgX+ zFCtbg!7-9WdXV2&s|s5b#Er&+f;w;3>&jrN3LSzZ!FlbC4fl;Pi$YZ;nYXZ?(^!M% z5G+xeL7E~uP%*97VyZYM?RNbc=?uEjqRJ;sheuSkrP*KS%-JoBbF3`2Sy}1vjThhG z#jD$-X^L@ffh;9i!tzRo>1aw-)|@`G!GqlagW;IIY+09rlO$c&c_ZvV>MMVKOaz zqac3&#(Kn|({A`Q_`LE+co5Lz<~IHFVb|PNT={{d5szkR6?AQW&S9n!*8hU^|qiImW5CUiR)Pn=q!*U5N&R`cNx zoF&U*b`K}$IL4V2Nn*$X)ya68iVl+m=Rj^v9%!| zzVrc%HN;7i(P+ZG?fdTH`Sa52v}h`aat0#_3;VYpzDYz;7}z~Hv=Oz+i-N0{U&lE^ zr2Nmbb{{jH1xrj%w=~8V_<~SYg{aa`*5f2W2SjY16XYo&iphAwm;UyPWLcY8UeRA( z=Iq&XY_6}lW}+lkKFfhH&G&gq53^vLgGpr=%}SRSd%SVwb=lqBb**ksW|Jv-KI55Z zR){p>OlVkCpv?gb8)xT4LWAR+FI=p%{&sebIF4LVRC4?7eK(rSq@6`P`NWf~uPyts z*;$e#hWW(UdFo0z%SlB+7IX-rIiBRa^6C{fSK8FIr%zV3!C1jKVK|=2^#_Kd-5Ogc z)lTzdd-Qj#FTd<=-Puu@IFu|)rPuA#XtwBd`#5L$^54D2&cU8b6YaE8 zG8&ie_VyuBoQUXz-Th-aOY3CK2G;rpTq)&|+0g78iRD`_yyyl8ckRyJq1?JZR?=MK z;%teX!Pkkf)TUmbf}W13F;=+w_5n&Sd9#DU4_$mFjo;gu7r5eu(&8L-Sy5LNx|xM3 zyMOLQAkG@7X45y@!N9`{ogFG|5;d9#W?{s!cviz6EXsI_R+cVq`8g-gIUj_ok|cbN z(A+qSv-4@c4fgRG6>FroMm?RNQlU;d^!sgwqbaXmzQc*FmBl$)2cfr85!U*U$ctw- z86J-rk7t}eyGc=0jK?#2{SLQp-Dm$`%*Q|W485f;2g4a4eBwhF(IR~3)f*UNoE9aI zpIxWZ%DA_EK%?EDx71~_eT;|>4fY)E5F)KZ(H@$yK&f&zAP{&VKEdXGuIX4f>p6m} zqs3GPv^UII3^KwwmL?I)ZLb+Qo*HIFy)Y0FgwspM#Dn+#Q z1m8XAaOaP&^QrIM;d39q$Pp-)JQN;-CD3-~QVF_}~6F?{#Rszy3e0_ZyI(u>Sdf z{m*w^{wM$CpC0X2pPp33MO~F-jTSrkDgO5_-{Qntm#3aO!)$7t4oa-K^HLo9dA4)T zhrKBie*SPWGq=-A;*`mF%K!C+7x~g#5oY-uq9g7dOu2sNh$zxD+bzb0p{yK7&SLB7fJgT@pyot4j>8y>dD!zU9 z3R$azbub-|*lOnd?8mI<4C6eVCv5Pd`~edzNBkz?B+xh993=4U3Z+mw@vc5-EC$6q zsKZm0yd|$;mY3{~48uq>n;EKF;K4pICEe8)SFa2hl@ro-L7I&)4yR#pqZ;lp&!3m=|O7HE&>kG;ZJz-Y7Us`B1q4%LhGs>ONkIC2})}!(GWEP^zCpePzL7p1MjYn-~Bm! zuw0s^fePRcdJ!EcSY}bQ`=Pm~tZ6YK;(g@j7wuuo@$i-BqIxfaeB{nhpdv*Q$0!wf zZ4v5``z2g|frG)2>o;#Y>l|<0x-GAK?*-B{VrgYFxHKhH#%EP2HMiyUg@ALGvYI!_ zbF-|6-)t1JMyjf2I-T8{a$!Ngw*kY=3fno{}rxDWcqvsSi>yRYl_F=-m z_~RGJqPgX(rK&Bp^+kMbEqPI3D@Q%kQVtJM<~}W5KyfH5YbU)Wxd`ocn@IaSpd`&$ zKY0p5lluK@N8(H^N@=1vqS@+GSch_&wat^PIfum&#|cVljH^kL#19k#mGp(nd-BEC zCrs#wOIA@ygKuu{ppv8cTm%yual{w7PJ~kTQSA;`Pi-m&1Dab~NE*G{tq*?=S!4Zu zSo?EA2gJx)heUJxXis+(<~b6=T&MBSGwI=XusB?-3;XLkHV$t&XXj6oo%cq88msZ! zm<8wcAs%L{UVq-)3BR%l#zS$Cp*@heuIDUKn2Z-Zj=&dL&Bm z(rY(39OV?&a&P;9&wlE8k|^TkYuoG`jYzYEe!tD#?E|XmlnbX;xwCUDckb=ESzgG6 zlPl~U4H2!ecD}FrM$lOkHc&yuI*7j?8LX)Y6{~RX^9bA={#Pk)vJz?H*rOVSsZeng zXt{GU$)FRmmNd~cQjHTKHHyisVonBdI7(w#>a|E385~Tpq80-6vZ`6?G-x&wCVS)X z-WOj8R(uADv6fCVqnlXDqDC4q-^51K-R+q$r9~Ma{M=*;TBxsqLVMlE7|L7XsWyMdGBbQTGqW@?R|sq=t>eNZKYa z;uvr&rL|;7wk$W2DvPv8QIt3j@9_=y-N!qhd(ZeA_TH<1?B6->QIadkm0?(3AAlhF zhI`Ms=bYbf@3q(P>ehk0v}b9v-k`(uG}Y^Euz0v)f^v8Sne5doJpIDm8{vQb-5>w4 zPt!vW-7#TI{b}h2ulcbD*${WbjRC!WWD1HyxE zxQl=gTPITNT2$3RBzR=0B_h*A8$uItZLX0`N224SWBm5-KaP(*Im2Z2VIaxiy~oz> zq)Cl-07~50nL;FBbAKA61`_Kn7Hv^Yiny4MlWZjbzRAxC7d^$VP{Gc~JraR4}YFXYvQOr=zrZ6^Z zPB-G*17mI6Xp~Lk0k-fypmsIT%EikLqhZ&I__49+=J#SB@R ze8XaR@%8flUm`vc}+O zfILf)=Pg*nkl+wA8Ds7+8H1{>FdQDm`4n_J?|1P`MCL!FZ+Ji4@zk1)Xewk90?mu; zoB21*-*W+&RUTX0dstm+V`+IES6;m?-A+QSzQJgCjOCRUvNU$4VjDN?-a8ng*j+7z z*dre?n#s*ZZ=T9T1hn!LhlfY<;>&wfmbL8c?$JXJJ%qQ~j9fVcnH1XxM{pEREanS8 zAWkf=4hOL9HqzxjHV7!WcP0>fH{D`(i>E^xYzl91^_$x< zbu$F`K(IC;p*R`dIfr&;aNj)_q}ytdwH9OzUcOo2`d*C_!zs$Drpf34t1peQvbsXE zTI8vlQ+Shsnzq3ZG^tH9ur)BP3}3l^jDPjHSI89wb`ED)YGvrPj%okk0Q(0MtRL)C zI~xEJBzTXlt(&y7y^EEVCDk`OUBCsflU)okT}qh=CgCqTze#@v#gxMuCJQ~UtBW7$2QyZ zTAWxoTcMj0cyxrp;Q-TmLcIS1(rJNgaEKsi0t61zqa&162_}Y6fK4pYG~OS`G>dnM zh5KomHjN$t;smp@YOVowO#P(T>>vn(SMJ3aXXwP)v*>i%cAG_7?B#L`R+ zWFRyfjb>rI$Ve3cG#|Prx7W4v4NQ~5D9z;Sm=YxMbtHl?H$~G;=z<8LoFdc?+-_lG zt%pvxg^lG7&fc|#N56Un#u!w`L!{ka%s80Wp@DJw^g6mptZTXF?lYLad<&)X==M6; zJ)FS8q2J5V>vl06Pq4Ax!>czB@WSOSyyxu?V5#3lvOlDqgAwjNQ{k--oW~Q--Ndx0 zVXXxx23ekCR+I=nEba%~v{aAJIbN&SaI-duX-C}rfCU0JCfBsq39yz>)B#f$PgrJE1)C<#{VlFLjwf{tDUL>PM6juC24V_|(qaF&1dnUX3Wq#R z5vaMhHf?(a1QQsw4+zGh-Ahr9>)4vyJIvoTWfid0TS8HI5P2jl&GVhVN8)uU$#Y14 z0bAus9FL~-@|6;JW)Cg7j=Rq6VK$x7_Q6ob(jnJ+BT;V!!Dis10v83U*#v&LgT#-n zoyhC|^Ww?m*FOGFf8`nam;dBXxL>L7lx{%24L|cUKePA${8#_rlf$Zb_qdqd%{D=j zb>LR-!WWNojQ{P6_%DC(81H`TMYKDuSg1`NsSr8mCFU}k7_C6nq_A+DW-EfLS6-D* zeC8>9>Sap@{fEF=E4Hi+0uNdYTbkcw7!=ct=Hn9>AYpJ*+!cpn#q=v6c3vV0@n%If z4!TR);ND4C=U~XeyAr|-ledX%jjE`KZ3-I#tSJ{Y9}pJ{))whWv8eX zzx&2`q4y3x#1^<@3=A7wz4{{l>9778e&WafHr{{sZj`laqU!O)AhuGh&|5u?N8bBa zaN{$NV^Yo_bq$yV%n57?93AeXbE1#)=TBqrc#6aQ0em$BB^d$;olXa<%Y9)(M zA#Zhn*#v`wJtX-Q?L7AKpP#q@0fqoHZHmjXz~R9G>e(0@Cr&NC_Tnoyd#L&1J4Pm( z#scv-;!VU_uuXuZ1t1Pv6ccMqh+_I)Vq#Qu-c9A}H-z)&7Me|6+UntOFv4JPgbNoh zpxurGt6UA(r0FsTffz>Z9L9$S7*8v7vUa@5-42^B{vDU+%_527>4de(VzcT3A&@0z zhGPbE5_{j9`PU&(FxVS=Jav7Da<)UqlM;J_44qkq8^sjUqY=)YWb|4Yf_E^+U{*QY zdTj@jSpjQPAUJedDFO)7X(6sIvD9tTy?0+&6p^=+95-$r;memxgnSu;Ns8+))_8p9 z8iIF#N$}D^1!ocv0Tyw(yof*&i)8&Ij5V;S#Y=}CS0CFUL$R*FdjUh>s{$4^df5SN zsE8%NiD2(=NUJMrIJbHdlS$khRCQdGq?tjm9-n>o3OZM>Q!7uAwORlfOeDjwHjvkb zl>SL15>T-o=9q;of^sU^eXG zxfcVNmqFbgrnA>@b236`QtwQX!G}CfttJ6D))1K_0XMT~7H4}*nELs(%z`;VQPm*d zEZPHs!SE!Yl_j8a4gqbPI@QO@QWux6?LdfOQxg~FOb~AFHPkdiXuf0Ywk1dsf=JeU zTARY*=AQ)+^9%@D_CV}jcaEm&kxq#Q5A0>uVnR2wpt^ztK`&3R%Zzln zzerzVjwxrYG{OCMpT_aQ0K?kj(&;tq?H>cK#Qhgf;$Sew{=p$0y#GATpIpXs!!ZsI zj&bjqHLNeSU@R~lPmx-SQQ>ent+BqAfY_j_;-=PnU^bm$aRrkY`JWGFT-4kJA6xV` zKU+rAiHhRJQCtP@tN8OM=l29Gh8fNqZIF+RQ3B%6b$7S8oyx||x&(1^QwPD`cmg!T zc8!VM9770T0K;;&NFgTTSd(#Qca$p7lE{>C2+zWBr&ZX6%|z1c`MG7wsM2gULUJUPs; z`>AdD;mZf~fk#f`(uEDQ+AWwYfia#82|}o2e||P#2&$@-?d@GW`SdmVy(eD7)58ra zR__6lBpy?PnkdBW`4!US-Y=s0gr-mSq8=^&6K)SsTO3u-CyzFZFJc0xS&V|X8N4S1 z?}Wq?yhDge$3hSXJob|;5-a{GEH0n90`-MA&M z-q^>q^zq_JwcIT*!abz=awD2owXU18%wj#*h_I;$Yg z!HtKoOUp1xild70hmXHVQlG`WmoDPw^_Q^H&#`gpQgbpRSWMuSc(G=~ATVs2qs1wz z*|?d@(M8O#@JJ};P+M!8OIE@3b08Ep$-CP zfX%=*K>$O*sFCBbr>@}p9(fBG9yhPOfOflu6L(#ZRvSd~^tIPNllTuCWLXD^og%Su zDAr;x(d4Jk>n1`7FhsB%&}p~O&SKB^ScUxhLdW>CirZ0R5)2OaaddcqcDIicr!PWG z3$+l0lbC01V7{$CI2SMVea#BBYBBY0dR(k=h{; z3UO8g#f7AV1Y}~x zq&HA#QW+&Is;m}sh?+K~EFM-o(!{_v?`bTr0sUpT*#y2WwcbFvd(Cy}sN@W-iC^B+U(vWI!PrUdxrM=|d%HlJk$A$T(np3Q6KV(OoS5Igqa z_U9fUfabMFAzqh)2;BVIH9yUy`9`LBMM8)hl;E4wk)~cz>cx9B)DFJI80;V5rQLlP zli+wbL3wlt%$nJ#7kctU~7K_ zniL4LHm+ShhOa8@A5E}37{a6}-tzDn+|>zk?bR#fMu$R^J*sLa@ji^jE>D6NVkT-% zvMC+|kpu}aiCGfC8xzwZVv07b^8#Z~$GVTEy;%IY8)krvsYOU6G;cH`27wa- zf>3bcyk`~%5PLEyKw$4{qEHEgB#1~L>x@akMl5_O-i79o!a-mx3C&v~hj?Wd68Jy> ziLhm`3nU^CLt+RBMBupg5Wv*UgKkPA0};cq_zJ;;$UqW{VePD;P;;E+h`1PFA@M>? zh)LJXAn!UB&)v0RfBU`fJpY+r_99ff;S0kT#HX1R}>MVo%(#eF<>brTPtdKGUv*O3c%^|8`lqNSxC@>Yh? z!M+?FkFa+*!pqn8@zkpmJU3XvLH=fKQ(0Q>(e23g{IM~vUEd;*z$WunrcG@^(}g0`9)g(GR8=#$x&mAQ zNDY`CBm^w?TFBcS91o8LG=LLB+-@N;>mVB=r(;j@iAP_e^=^WMLkhO-oz= zLU%;mDc-aJH0e4yj3uObCw5e6j=4G7SxCd!AifuB}Sla_*us=S;?$J!%_|OU3x^)YCTQA`BnG5Lj zR`Ct%^@SMyV@|NtUq`1GVx5W+AS6x1EEaG>no)@&$aBJ(GiPF(URoqcES^LB@0eo? z2#iTEolbG}l@~BPKEl~cZ@_~OpM^~_7@H!=TOj8F#E92dUcQB!yGK~<<#_5VPvi8N zQ)U0eg>hNdE3Nj|6_YgIkI@wP6Ju@tWU~RWP5J>q6btep%}ERi3@1qQ*g48@tfRP{ zYSnaix#Q#`Zl(-olL>BIy^N)`yKw64eXv;`{~R+62MBo($F{v_P9hBgCgT}4#iKGg zY(|UDEU*cJcx)Fnd>tUpqq|?@u2X&VPqy*E#S>Uv?&8YU0MEX%g^kr7%IO|>O;B3G zOGh4bR5sCnAjw*=X$vV)Gb2IZgNu3d#(#jXHG!svdJ4au{C!9#21i~ z;pf*bAm-l3P&5`ZR}etp7-gTo%@DvO@#Hx8MU-@L@P`0$?)GO9@nj)*2cLFvcreBT zmo{L0jh*dX)IzxL{5q;Spq>>#IYvD#VC)?=V$B95%yWEvvw@)byD=_kV?cfW_+G!^ zBbh%|UR+-!2*fpQP@6@)t1E=Na!6Gnj1Li-fo;BdZZUUOPA%Y7X9k;8~bGncM+33H1?+pMb;~VkZLQh`K~XCinrv7cjB2QUG@Y zxWmB2keiU8G(@FGNCR^}1W7Gu%!IKEuI>l%r_)}rJvq(ntt}>3r#P5cuoV{Ld{}ml zS4d>iX4-VwV{4Z- zxAu~DyX96B$7xoy>Vq5AQ`d+42yFO#_gT?Ka}79|7R@O znMf36(nPY2ea#lxDf>0;daCBdR>T9(jEG?2?FPWU-b z@-@dlxxdr_0FFs*bybraW?<>e;woN~XsRbFcK70hiLjl}0j!$^q zqF-EQVOduhpzHDx4M&f;>O_MYcjqCIVD4T>x1~5UvCQ|I&9=cUPahyBZ;tt{iZgc77ag)< z|AY+)I|I?TIjy+8;$Ni`1|uJ5HH)T#qd4zJ!8LJvopcWK<~#}c6NuBufFm!~*bS-2 z{Pj^ESR1|h+}+=LP}95tcSE^Vx~;$;Jl8mB&YA-@yD$YpMY8?`A(7coWqnPF56|G% z3N*ee(^8gpgmzO2bfUyf?JP&q^KcHk5DiwO(F@^`D6z@8jB+G$<1pP5TOsiQBV6^Q zG14<2ApB;^*qKvs8Vzml{{Dy?{-VS!0zHBX09wd_Mdb?Kg6ZypYj zxrCr^Gm)iYdi@Y%r}@_wKT4Io*>s90or>m_wdD2 zh_FcLcgry-8w4spchkmJwfFO=wOR)+{PJW}FXU=Et!hX}jw;ALfl9NT;p@9i0ixk# z#K6S8f$BKTvgsD>u)J z8I(sPvY^6ZumLPitjTqQR~8!`(!nLyIB)jiKLUD&uLk;`RZ~T<02^N7Kj(1H!WORW z8#$2o#(&bgI*+nZd!n{I2mR(iT6CA%qm-`V>&pzXy}a~H@H~%8sv8Hcf`BZOv|j~` zQZC9@FuW>Mj{1Mo*(uifAMG*e4*X)!*Li>{mB^@So$YWS0p8?zfMvk)={Wi~?RH#MRJh zGL{Jxfljh)oQvkx2AZefAuXwVKlRiY4}#lS)t+DLE;+1#&^hYGtE2?mW5NR{a{;W8 zRPhncRZthp6ccS{X4@M@F+lo<*p!WeEXEp+P>w6=$5#Vir1rhhzh=V&u&S5RVin1z{7N0);U8Z{SSxq>V41~dX(X~1_?TVfzDSX7 z8iT9Mrk*_B$%(ZQ%=+y`UdA`4uCuHKKd*y2{~v|Q2U18!Y)X5;Bv(?|oz$%5Ypn;Cp5{GBBV<@Se&x*juZcU1%H0%u)KW zG%*`L_GNTCy0~&3X@006h{JUmUL0G;ppe{vn(rrw(A}RoUuW=rG)mhM0st08*Kkb= z0C9SP2%hsSoIU7GG69^2+!EovI-%rJ32Y>%WY%&Rd@qZkQuX!^6=n>FV4{RI5{2*v zjEpVMSKf-h<#!Ln|N~VyNFjy zzy5rLcS@K8Th|{&r&85db0x!(^nSNdU6LR={UnH(ew28a83u2)!VVa;iRb&Fsg~XT zTb&Jav42N0Ct~#wrpvbUwr6OEWNjJg_Yx{pgdR`!kqR+Yvw@?owhDPFPIdAtp9q}v zJ%vS;<3n2l0@;TCGkG;5KNCdGVD77B+{*>y-{4X){y1@ED9gFVMPPAYsz$3uk-$xvm1sQZ z97~}VcfbR@$*Oqh-;i7&CoKwNm#GYSSI<(sZAxc;Ihz`-5XWv4dg7|nUFj%)tm7lr?yZrZ&4=@!2&bg2&@> zQVsHY7Qn>xPR%#4IR|IbrGSGq%=WT*TO1b+buU!SR>p;iRnrwBkb6AB^R(uE^pVtv zBw};5acHO!Yc^ z?6s+nZ8Jj5AjRro3Z{G$p6XJc5s5#V{`oKk;yM4sY}`&gD(F&ta`vDQ-*47{OgjX@snrexCi+6Z(N*Ow{y91W;_n-ypwIz! zP(znU9G$0dD#X|g{a$ks)N&L%8FaE)P|_tUlU)dxmx|uYQB4W4&!(0UaSSuKi&*=*i4esf=uzXybzFYX) z8}=*(0v|X>-(-m`_cmJN)1I9Ug4K>}Ha1n1-j%Zu85|;$Qw&pf&%3*~&kJ=AoWwtw zO6*UxAn<}`IYT2U&A#;t`A(gbsOJG`WUnzKX08yBv3Wz|l z^x%l+OQ$kTf(ZBg{wYH{{OQ1)2(5hxw0r>MT8`$4eL!v>@-g?DJHBYdc z7e=ktGJI&b(uwF#IKHs3)Trc|D@f~qoj{+dabMG&Quq@Pe(rLWe^+4WHJ`El z4Hojve_!JI!tu<-9*4+#|AQMl2aT6&W2(Q`y|X_XBrzDag|PAcOfL3AV5Y+GeT>Yy zU|I3Ia5U)a?Rs)n2*8ag(t&N$v<|nOe2S%MpJ?YqYNZw@TXh1wXqWkFTwkxO7X>cw zh)yGADiZ4aoDpjHkbW;`dt`0ON>f@CVptx>_vcv6-^$miH&8J3&q3W%*BOzL>}>G^ zM>t5Er*wV6X08wiMl>#?pIf=(nfOF)zlY87@bElS_nLeLplrX4y6I%I{n{#>8qr1b zWa|Nx>Wby~&1_}=CoR>}&7MJ_oA^1u*7Z=8ZPgTXa#VQd&&;x7iee`I-dp(qmip zRmDh#x}EKQc=7m%&eldd&COZGy76Yr?CCDeh~yN4eXWknU-L`z=|(tNT&YwdVTUs8 zS_AizQ_^<;XY|05s_L=N2Vn*!FQ``FKQbWtbG|0N^@m9!Z{vd~9XMI(u0%OZ1{Z}X zOlgaYB*t`Yg4+)j%B}IUjPlyzxc#7mA!2LJU<+-k@VyDE7lqzI`3kiHvxjzd%YvJn zIGh=|2F+&~z4UOwEO;jW{B&pMAwv7hg6_lZ)&jFHgt`*>>&^nSl=@PcL)$axn8mPq8C^qEBoJerCJeC(gAlAHV> zSV=hbaT)e*$}%#Sx3Sh$2o8R-mu8OT30bxKj>)Y#XdZrftQwNDR}kKN^)*YU9P^#b{f*5Rf1n#(F2 zsKsf_UrdE<=h*@&mHl$G>?2Qt&!qqoFOsrhPl~6@sLvJ$8;c-Qu?{3b?%lgO_JJZc z*{w%^M27DEJhQ-x=2xtMtI*QFPr;zimLo5eyIgT))tkP79xLCQMY3V_a|DCvOudpg z*8YmGig6d^ZY0^o#+K~(B*bGbflJXej{RDrA8f>Oor{8Mo5x^&bvZf2#iO>B zR*7Om(XP^GWZM>%blQOZe)}(^InqTmH2c%Dn(=_r4CM)HY^%vxlLFGjg-JKFU{mZa zM5qYr8uUE#4co2sWYZX8yFdixuJ% zonrW;xVG;3!pqD$DsJ0-0}riQ%0n%2sA*q$&H?qwlQ$2PZLzGRUkdZbxeWXhFxmcr zc<>e8ZQAGXxEU^kyr9kL!xi)Th9kd27PqpMb7yVEJL5(r_h6C&*us{KB4O>gcONP4 z0Y)EjNTly{;y5<`md#~WX#STU?F#){ zkMs}s=P-fyYh@>&K4q3MPduzA9IBT-semNo4`*aD400E)$28+|@+}*yWtfLyYhonx zg{6+)WZY74VYRESU)F>(f3Ws;bDK5bV=8P-c^LT7#cVdyzx;HV)S-D18%BKklTe2_ z-kY)|Vhl+idNd=FD2_Q*c+NI@1~#g6+erHvib^B~V&%o(VG-q8znwwX7pI*o*j=`X z+?K%C{u8m@nSRVO?78O)t*+=TYggXpg~h}Y=)ws}N1*V-2ve{ByEsJBxgpOFs6e#= zKsPe{I@I#-mbtzQFguWo0{-MF;wKWk`i8}b+CV{1#LLpLWOI-CI`5tzk@|#rHmD6wIiS1 zM&5IH0Z{IcM;zB1%tUjwOk1^_NW-$X$mx~{^ zm7{!~NBj#r^bf;giS0^C=b+fRWB#UA$={5|=7%o72P2^GMEarS}+rS%>6AK6F?6>+(Ic*7(QDdFOng zyS%RS`9{(O$LLXZJ_SITFQt`>c2LY`RNHIOmL?xnb z+x~&(@xO&LB6|a?jNw8~NAn2hOZoPA-G?0M@;`j+uw!!B!e!8IZ%p;@#ZWP6eBH;8 zbn$3VTrCcN=P8{)_7UQ3;?8`7aujK`k_aM~{-J#3+c|hb)s#pZ=Dn+PvTGq`C~B5b zJ+##LGCDe#xFeAib_hE*;Hiv*0J4iL?~+H?x#;?+v4MR}c8Fs!0O$c`DYiMm`vlnW z!Wt%heg%fx3cK5~;vYt;v_^7neVL?Z59dHZ9kL7zF~iv?mJ1Xz`seMzp?n1M_GCt0 z#O=h_6_pBd@aQRZG;hi|EGH;LVqr7S{J%(Ht-h3>Td7l&iFXEwoNZAHr`zw+Rhqh4 zWAFJn?C#kSDJG4x>^o0<$l&(wxYpyY9;krgwC>g1rwk6A7K||7&PDX( za96!#)2B!OIzGKw#05I=P?(-8l&zfyVarmK>@&u|I;`^vq4I+V6i{hQrwuWtj&)O0;JBdt;Y*Fn~xM{cly}zZ=1bnZ%+{?QNrd`Dcl?$4tX$S+p-f!Hl>78;sGz-xn{>L&8_Gke$)S2osJpYr3ZsU@A z=*&FJhYXRqqu`a_i%VsQR?#b_)>@#b#Yi;pEx15Ca`6U&vt1$X3z*ll?oCuU08E<< zia@km)-Tx41rYD6ujTC-oBXf8?tejfs6%*nHF=2NNzaZ)B$H<4b1XiKA@>nvHq0vy{$bmI^PGhvf+4m_`aiX{ zLbDD(6HV076jkn z8pP!Ty+e=d8(Q7OH-(~!*rpZ|RlGv%>A&wlr*zAftRT!8ay6}uaKEUS`@abOe?yk$ hKYjimG^Z7(FrfcTar=YWFp(bh0fuTXP{{68;){3-wd literal 0 HcmV?d00001 diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.h b/bsp/hpmicro/hpm6750evk2/rtconfig.h new file mode 100644 index 0000000000..2d0a43e80d --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.h @@ -0,0 +1,243 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50001 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_RTC + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers Config */ + +#define SOC_HPM6000 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_RTC + +#endif diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.py b/bsp/hpmicro/hpm6750evk2/rtconfig.py new file mode 100644 index 0000000000..77251ab7eb --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.py @@ -0,0 +1,108 @@ +# Copyright 2021-2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +CHIP_NAME='HPM6750' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + CFLAGS = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig_preinc.h b/bsp/hpmicro/hpm6750evk2/rtconfig_preinc.h new file mode 100644 index 0000000000..e7dfc93ff5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/rtconfig_preinc.h @@ -0,0 +1,16 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HAVE_CCONFIG_H +#define HPM6750 +#define RT_USING_NEWLIBC +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/SConscript b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/SConscript new file mode 100644 index 0000000000..3e8dd931d3 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/SConscript @@ -0,0 +1,22 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c new file mode 100644 index 0000000000..b0bab335d5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/port_gcc.S new file mode 100644 index 0000000000..2708b48e45 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S new file mode 100644 index 0000000000..5c47c92afe --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + + /* Enable LMM1 clock */ + la t0, 0xF4000800 + lw t1, 0(t0) + ori t1, t1, 0x80 + sw t1, 0(t0) + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + /* Initialize trap_entry base */ + la t0, SW_handler + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/vectors.S new file mode 100644 index 0000000000..9e9227b4ad --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/vectors.S @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + .section .vector_table, "a" + .global __vector_table + .align 9 +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_E IRQ handler */ + IRQ_HANDLER 15 /* GPIO1_F IRQ handler */ + IRQ_HANDLER 16 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 19 /* ADC0 IRQ handler */ + IRQ_HANDLER 20 /* ADC1 IRQ handler */ + IRQ_HANDLER 21 /* ADC2 IRQ handler */ + IRQ_HANDLER 22 /* ADC3 IRQ handler */ + IRQ_HANDLER 23 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 25 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 26 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 27 /* SPI0 IRQ handler */ + IRQ_HANDLER 28 /* SPI1 IRQ handler */ + IRQ_HANDLER 29 /* SPI2 IRQ handler */ + IRQ_HANDLER 30 /* SPI3 IRQ handler */ + IRQ_HANDLER 31 /* UART0 IRQ handler */ + IRQ_HANDLER 32 /* UART1 IRQ handler */ + IRQ_HANDLER 33 /* UART2 IRQ handler */ + IRQ_HANDLER 34 /* UART3 IRQ handler */ + IRQ_HANDLER 35 /* UART4 IRQ handler */ + IRQ_HANDLER 36 /* UART5 IRQ handler */ + IRQ_HANDLER 37 /* UART6 IRQ handler */ + IRQ_HANDLER 38 /* UART7 IRQ handler */ + IRQ_HANDLER 39 /* UART8 IRQ handler */ + IRQ_HANDLER 40 /* UART9 IRQ handler */ + IRQ_HANDLER 41 /* UART10 IRQ handler */ + IRQ_HANDLER 42 /* UART11 IRQ handler */ + IRQ_HANDLER 43 /* UART12 IRQ handler */ + IRQ_HANDLER 44 /* UART13 IRQ handler */ + IRQ_HANDLER 45 /* UART14 IRQ handler */ + IRQ_HANDLER 46 /* UART15 IRQ handler */ + IRQ_HANDLER 47 /* CAN0 IRQ handler */ + IRQ_HANDLER 48 /* CAN1 IRQ handler */ + IRQ_HANDLER 49 /* CAN2 IRQ handler */ + IRQ_HANDLER 50 /* CAN3 IRQ handler */ + IRQ_HANDLER 51 /* PTPC IRQ handler */ + IRQ_HANDLER 52 /* WDG0 IRQ handler */ + IRQ_HANDLER 53 /* WDG1 IRQ handler */ + IRQ_HANDLER 54 /* WDG2 IRQ handler */ + IRQ_HANDLER 55 /* WDG3 IRQ handler */ + IRQ_HANDLER 56 /* MBX0_CA IRQ handler */ + IRQ_HANDLER 57 /* MBX0_CB IRQ handler */ + IRQ_HANDLER 58 /* MBX1_CA IRQ handler */ + IRQ_HANDLER 59 /* MBX1_CB IRQ handler */ + IRQ_HANDLER 60 /* TMR0 IRQ handler */ + IRQ_HANDLER 61 /* TMR1 IRQ handler */ + IRQ_HANDLER 62 /* TMR2 IRQ handler */ + IRQ_HANDLER 63 /* TMR3 IRQ handler */ + IRQ_HANDLER 64 /* TMR4 IRQ handler */ + IRQ_HANDLER 65 /* TMR5 IRQ handler */ + IRQ_HANDLER 66 /* TMR6 IRQ handler */ + IRQ_HANDLER 67 /* TMR7 IRQ handler */ + IRQ_HANDLER 68 /* I2C0 IRQ handler */ + IRQ_HANDLER 69 /* I2C1 IRQ handler */ + IRQ_HANDLER 70 /* I2C2 IRQ handler */ + IRQ_HANDLER 71 /* I2C3 IRQ handler */ + IRQ_HANDLER 72 /* PWM0 IRQ handler */ + IRQ_HANDLER 73 /* HAL0 IRQ handler */ + IRQ_HANDLER 74 /* ENC0 IRQ handler */ + IRQ_HANDLER 75 /* PWM1 IRQ handler */ + IRQ_HANDLER 76 /* HAL1 IRQ handler */ + IRQ_HANDLER 77 /* ENC1 IRQ handler */ + IRQ_HANDLER 78 /* PWM2 IRQ handler */ + IRQ_HANDLER 79 /* HAL2 IRQ handler */ + IRQ_HANDLER 80 /* ENC2 IRQ handler */ + IRQ_HANDLER 81 /* PWM3 IRQ handler */ + IRQ_HANDLER 82 /* HAL3 IRQ handler */ + IRQ_HANDLER 83 /* ENC3 IRQ handler */ + IRQ_HANDLER 84 /* SDP IRQ handler */ + IRQ_HANDLER 85 /* XPI0 IRQ handler */ + IRQ_HANDLER 86 /* XPI1 IRQ handler */ + IRQ_HANDLER 87 /* XDMA IRQ handler */ + IRQ_HANDLER 88 /* HDMA IRQ handler */ + IRQ_HANDLER 89 /* DRAM IRQ handler */ + IRQ_HANDLER 90 /* RNG IRQ handler */ + IRQ_HANDLER 91 /* I2S0 IRQ handler */ + IRQ_HANDLER 92 /* I2S1 IRQ handler */ + IRQ_HANDLER 93 /* I2S2 IRQ handler */ + IRQ_HANDLER 94 /* I2S3 IRQ handler */ + IRQ_HANDLER 95 /* I2SCLASSD IRQ handler */ + IRQ_HANDLER 96 /* I2SPDM IRQ handler */ + IRQ_HANDLER 97 /* CAM0 IRQ handler */ + IRQ_HANDLER 98 /* CAM1 IRQ handler */ + IRQ_HANDLER 99 /* LCD_D0 IRQ handler */ + IRQ_HANDLER 100 /* LCD_D1 IRQ handler */ + IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */ + IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */ + IRQ_HANDLER 103 /* JPEG IRQ handler */ + IRQ_HANDLER 104 /* NTM0 IRQ handler */ + IRQ_HANDLER 105 /* NTM1 IRQ handler */ + IRQ_HANDLER 106 /* USB0 IRQ handler */ + IRQ_HANDLER 107 /* USB1 IRQ handler */ + IRQ_HANDLER 108 /* ENET0 IRQ handler */ + IRQ_HANDLER 109 /* ENET1 IRQ handler */ + IRQ_HANDLER 110 /* SDXC0 IRQ handler */ + IRQ_HANDLER 111 /* SDXC1 IRQ handler */ + IRQ_HANDLER 112 /* SEC_EVENT IRQ handler */ + IRQ_HANDLER 113 /* PMIC_GPIO IRQ handler */ + IRQ_HANDLER 114 /* PMIC_WDG IRQ handler */ + IRQ_HANDLER 115 /* PMIC_TMR IRQ handler */ + IRQ_HANDLER 116 /* PMIC_UART IRQ handler */ + IRQ_HANDLER 117 /* VAD IRQ handler */ + IRQ_HANDLER 118 /* FUSE IRQ handler */ + IRQ_HANDLER 119 /* SECMON IRQ handler */ + IRQ_HANDLER 120 /* BATT_RTC IRQ handler */ + IRQ_HANDLER 121 /* BUTTON IRQ handler */ + IRQ_HANDLER 122 /* BATT_GPIO IRQ handler */ + IRQ_HANDLER 123 /* VIOLATION IRQ handler */ + IRQ_HANDLER 124 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 125 /* CLK_FAIL IRQ handler */ + IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c new file mode 100644 index 0000000000..b87eaee524 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/bsp/hpmicro/hpm6750evk2/startup/SConscript b/bsp/hpmicro/hpm6750evk2/startup/SConscript new file mode 100644 index 0000000000..2708fb6742 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') diff --git a/bsp/hpmicro/hpm6750evkmini/.config b/bsp/hpmicro/hpm6750evkmini/.config index 140d6f1798..214da8c2eb 100644 --- a/bsp/hpmicro/hpm6750evkmini/.config +++ b/bsp/hpmicro/hpm6750evkmini/.config @@ -8,6 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=8 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -32,7 +33,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -# CONFIG_RT_DEBUG is not set +# CONFIG_RT_USING_DEBUG is not set # # Inter-Thread communication @@ -42,12 +43,12 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -71,10 +72,10 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set # CONFIG_RT_USING_CACHE is not set -CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_RT_USING_HW_ATOMIC is not set # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -102,6 +103,10 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# # CONFIG_RT_USING_DFS is not set # CONFIG_RT_USING_FAL is not set @@ -159,7 +164,19 @@ CONFIG_RT_USING_RTC=y # # C/C++ and POSIX layer # -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # POSIX (Portable Operating System Interface) layer @@ -198,9 +215,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases @@ -225,7 +244,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -243,6 +261,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # CONFIG_PKG_USING_WLAN_WICED is not set # CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -350,7 +373,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # LVGL: powerful and easy-to-use embedded GUI library # # CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set @@ -425,6 +447,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set # # system packages @@ -461,6 +484,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_PARTITION is not set @@ -496,6 +521,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set # # peripheral libraries and drivers @@ -560,6 +588,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_BALANCE is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_ADT74XX is not set # CONFIG_PKG_USING_MAX17048 is not set @@ -580,6 +609,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -592,7 +622,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -650,14 +679,18 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -676,7 +709,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set # # miscellaneous packages @@ -723,7 +760,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -748,8 +784,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -896,14 +933,21 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -937,7 +981,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # # Signal IO @@ -978,9 +1021,10 @@ CONFIG_BSP_USING_RTC=y # CONFIG_BSP_USING_TOUCH is not set # CONFIG_BSP_USING_LCD is not set # CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_PDMA is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set -CONFIG_BSP_USING_DRAM=y +CONFIG_BSP_USING_FEMC=y CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_XPI_FLASH is not set # CONFIG_BSP_USING_PWM is not set diff --git a/bsp/hpmicro/hpm6750evkmini/README.md b/bsp/hpmicro/hpm6750evkmini/README.md new file mode 100644 index 0000000000..aab8844e17 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/README.md @@ -0,0 +1,116 @@ +# HPMicro HPM6750EVKMINI BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM6750EVKMINI development board. + +The document consists of the following parts: + +- HPM6750EVKMINI Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6750EVKMINI is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Display, Audio， motor control，etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | Supported by RT-Thread Industry IO | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6750EVKMINI RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6750evkmini) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/README_zh.md b/bsp/hpmicro/hpm6750evkmini/README_zh.md new file mode 100644 index 0000000000..7f4b7b2804 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/README_zh.md @@ -0,0 +1,115 @@ +# 先楫 HPM6750EVKMINI BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6750EVKMINI 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6750EVKMINI 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM6750EVKMINI 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于显示、音频和电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | 由RT-Thread Industry IO扩展板提供支持 | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| SDIO | √ | | +| RTC | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evkmini.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6750EVKMINI RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6750evkmini) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/board/Kconfig b/bsp/hpmicro/hpm6750evkmini/board/Kconfig index 2962d5d953..bf463b7e2c 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/Kconfig +++ b/bsp/hpmicro/hpm6750evkmini/board/Kconfig @@ -5,7 +5,6 @@ config SOC_HPM6000 select SOC_SERIES_HPM6000 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN - select RT_USING_HW_ATOMIC default y menu "On-chip Peripheral Drivers" @@ -45,18 +44,6 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA default n - config BSP_UART0_RX_DMA_CHANNEL - int "Set UART0 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART0_TX_DMA_CHANNEL - int "Set UART0 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART0_RX_BUFSIZE int "Set UART0 RX buffer size" range 64 65535 @@ -83,18 +70,6 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA default n - config BSP_UART6_RX_DMA_CHANNEL - int "Set UART6 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART6_TX_DMA_CHANNEL - int "Set UART6 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART6_RX_BUFSIZE int "Set UART6 RX buffer size" range 64 65535 @@ -121,18 +96,6 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA default n - config BSP_UART13_RX_DMA_CHANNEL - int "Set UART13 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART13_TX_DMA_CHANNEL - int "Set UART13 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART13_RX_BUFSIZE int "Set UART13 RX buffer size" range 64 65535 @@ -159,18 +122,6 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA default n - config BSP_UART14_RX_DMA_CHANNEL - int "Set UART14 RX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA - default 0 - - config BSP_UART14_TX_DMA_CHANNEL - int "Set UART14 TX DMA CHANNEL" - range 0 7 - depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA - default 1 - config BSP_UART14_RX_BUFSIZE int "Set UART14 RX buffer size" range 64 65535 @@ -252,6 +203,11 @@ menu "On-chip Peripheral Drivers" bool "Enable LVGL" default n select PKG_USING_LVGL if BSP_USING_LVGL + select BSP_USING_PDMA if BSP_USING_LVGL + + menuconfig BSP_USING_PDMA + bool "Enable PDMA" + default n menuconfig BSP_USING_GPTMR bool "Enable GPTMR" @@ -293,8 +249,8 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_DRAM - bool "Enable DRAM" + menuconfig BSP_USING_FEMC + bool "Enable FEMC" default y menuconfig INIT_EXT_RAM_FOR_DATA bool "INIT_EXT_RAM_FOR_DATA" @@ -304,7 +260,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_XPI_FLASH bool "Enable XPI FLASH" default n - select PKG_USING_FAL if BSP_USING_XPI_FLASH + select RT_USING_FAL if BSP_USING_XPI_FLASH menuconfig BSP_USING_PWM bool "Enable PWM" @@ -400,17 +356,15 @@ menu "On-chip Peripheral Drivers" bool "Enable ADC2" default n endif - if !BSP_USING_ADC12 - menuconfig BSP_USING_ADC16 - bool "Enable ADC16" + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" default n if BSP_USING_ADC16 config BSP_USING_ADC3 bool "Enable ADC3" default n endif - endif - endif + endif endmenu diff --git a/bsp/hpmicro/hpm6750evkmini/board/SConscript b/bsp/hpmicro/hpm6750evkmini/board/SConscript index 1444a9e948..6245c5f443 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/SConscript +++ b/bsp/hpmicro/hpm6750evkmini/board/SConscript @@ -10,7 +10,6 @@ src = Split(""" rw007_port.c eth_phy_port.c fal_flash_port.c - trap_gcc.S """) CPPPATH = [cwd] diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.c b/bsp/hpmicro/hpm6750evkmini/board/board.c index e26970e0e7..de9188fdf0 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -11,7 +11,7 @@ #include "hpm_i2c_drv.h" #include "hpm_gpio_drv.h" #include "hpm_debug_console.h" -#include "hpm_dram_drv.h" +#include "hpm_femc_drv.h" #include "pinmux.h" #include "hpm_pmp_drv.h" #include "assert.h" @@ -20,6 +20,7 @@ #include "hpm_sdxc_drv.h" #include "hpm_sdxc_soc_drv.h" #include "hpm_pllctl_drv.h" +#include "hpm_pcfg_drv.h" static board_timer_cb timer_cb; @@ -82,7 +83,7 @@ __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90 void board_init_console(void) { -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; /* Configure the UART clock to 24MHz */ @@ -116,7 +117,7 @@ void board_print_clock_freq(void) printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); printf("display:\t %luHz\n", clock_get_frequency(clock_display)); printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); @@ -128,6 +129,7 @@ void board_print_clock_freq(void) void board_init_uart(UART_Type *ptr) { init_uart_pins(ptr); + board_init_uart_clock(ptr); } void board_init_ahb(void) @@ -183,10 +185,10 @@ void board_init_sdram_pins(void) init_sdram_pins(); } -uint32_t board_init_dram_clock(void) +uint32_t board_init_femc_clock(void) { - clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ - return clock_get_frequency(clock_dram); + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ + return clock_get_frequency(clock_femc); } void board_power_cycle_lcd(void) @@ -212,11 +214,29 @@ void board_init_lcd(void) { board_init_lcd_clock(); init_lcd_pins(BOARD_LCD_BASE); - board_power_cycle_lcd(); +} - board_delay_ms(10); - board_power_cycle_lcd(); +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + + config->resolution_x = BOARD_LCD_WIDTH; + config->resolution_y = BOARD_LCD_HEIGHT; + + config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; + config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; + config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; + + config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; + config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; + config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; + + config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; + config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; + config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; + config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; + config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; } void board_delay_ms(uint32_t ms) @@ -312,73 +332,49 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0; - + clock_name_t clock_name = clock_uart0; + bool need_init_clock = true; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart0); - } - else if (ptr == HPM_UART1) { - clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart1); - } - else if (ptr == HPM_UART2) { - clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart2); - } - else if (ptr == HPM_UART3) { - clock_set_source_divider(clock_uart3, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart3); - } - else if (ptr == HPM_UART4) { - clock_set_source_divider(clock_uart4, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart4); - } - else if (ptr == HPM_UART5) { - clock_set_source_divider(clock_uart5, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart5); - } - else if (ptr == HPM_UART6) { - clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart6); - } - else if (ptr == HPM_UART7) { - clock_set_source_divider(clock_uart7, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart7); - } - else if (ptr == HPM_UART8) { - clock_set_source_divider(clock_uart8, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart8); - } - else if (ptr == HPM_UART9) { - clock_set_source_divider(clock_uart9, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart9); - } - else if (ptr == HPM_UART10) { - clock_set_source_divider(clock_uart10, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart10); - } - else if (ptr == HPM_UART11) { - clock_set_source_divider(clock_uart11, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart11); - } - else if (ptr == HPM_UART12) { - clock_set_source_divider(clock_uart12, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart12); - } - else if (ptr == HPM_UART13) { - clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart13); - } - else if (ptr == HPM_UART14) { - clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart14); - } - else if (ptr == HPM_UART15) { - clock_set_source_divider(clock_uart15, clk_src_osc24m, 1); - freq = clock_get_frequency(clock_uart15); - } - else { + clock_name = clock_uart0; + } else if (ptr == HPM_UART1) { + clock_name = clock_uart1; + } else if (ptr == HPM_UART2) { + clock_name = clock_uart2; + } else if (ptr == HPM_UART3) { + clock_name = clock_uart3; + } else if (ptr == HPM_UART4) { + clock_name = clock_uart4; + } else if (ptr == HPM_UART5) { + clock_name = clock_uart5; + } else if (ptr == HPM_UART6) { + clock_name = clock_uart6; + } else if (ptr == HPM_UART7) { + clock_name = clock_uart7; + } else if (ptr == HPM_UART8) { + clock_name = clock_uart8; + } else if (ptr == HPM_UART9) { + clock_name = clock_uart9; + } else if (ptr == HPM_UART10) { + clock_name = clock_uart10; + } else if (ptr == HPM_UART11) { + clock_name = clock_uart11; + } else if (ptr == HPM_UART12) { + clock_name = clock_uart12; + } else if (ptr == HPM_UART13) { + clock_name = clock_uart13; + } else if (ptr == HPM_UART14) { + clock_name = clock_uart14; + } else if (ptr == HPM_UART15) { + clock_name = clock_uart15; + } else { /* Unsupported instance */ + need_init_clock = false; + } + + if (need_init_clock) { + clock_set_source_divider(clock_name, clk_src_osc24m, 1); + clock_add_to_group(clock_name, 0); + freq = clock_get_frequency(clock_name); } return freq; @@ -532,7 +528,7 @@ void board_init_clock(void) clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); clock_add_to_group(clock_gptmr0, 0); @@ -543,13 +539,6 @@ void board_init_clock(void) clock_add_to_group(clock_gptmr5, 0); clock_add_to_group(clock_gptmr6, 0); clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); - clock_add_to_group(clock_uart6, 0); - clock_add_to_group(clock_uart13, 0); - clock_add_to_group(clock_uart14, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -606,12 +595,17 @@ void board_init_clock(void) clock_add_to_group(clock_i2s2, 0); clock_add_to_group(clock_i2s3, 0); + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + /* Add the CPU1 clock to Group1 */ clock_add_to_group(clock_mchtmr1, 1); clock_add_to_group(clock_mbx1, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); - /* Connect Group0 to CPU0 */ - clock_connect_group_to_cpu(0, 0); + /* Bump up DCDC voltage to 1200mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1200); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); @@ -812,23 +806,24 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) */ void _init_ext_ram(void) { - uint32_t dram_clk_in_hz; + uint32_t femc_clk_in_hz; + clock_add_to_group(clock_femc, 0); board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); + femc_clk_in_hz = board_init_femc_clock(); - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); + femc_default_config(HPM_FEMC, &config); + config.dqs = FEMC_DQS_INTERNAL; + femc_init(HPM_FEMC, &config); - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.precharge_to_act_in_ns = 18; /* Trp */ sdram_config.act_to_rw_in_ns = 18; /* Trcd */ @@ -841,7 +836,7 @@ void _init_ext_ram(void) sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ sdram_config.act_to_act_in_ns = 12; /* Trrd */ sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED; sdram_config.cs = BOARD_SDRAM_CS; sdram_config.base_address = BOARD_SDRAM_ADDRESS; @@ -852,13 +847,15 @@ void _init_ext_ram(void) sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; sdram_config.delay_cell_value = 29; - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } void board_init_sd_pins(SDXC_Type *ptr) { if (ptr == HPM_SDXC1) { init_sdxc_pins(ptr, false); + init_sdxc_card_detection_pin(ptr); + init_sdxc_vsel_pin(ptr); } else { while (1) { @@ -866,6 +863,24 @@ void board_init_sd_pins(SDXC_Type *ptr) } } +void board_sd_power_switch(SDXC_Type *ptr, bool on_off) +{ + /* This feature is not supported by current board*/ +} + +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) +{ + sdxc_switch_to_1v8_signal(ptr, true); + init_sdxc_pins(ptr, true); +} + +bool board_sd_detect_card(SDXC_Type *ptr) +{ + return sdxc_is_card_inserted(ptr); +} + + + uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) { uint32_t actual_freq = 0; @@ -908,6 +923,22 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) return actual_freq; } +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ + clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ + } else if (ptr == HPM_ENET1) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ + clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { if (internal == false) { @@ -927,17 +958,6 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) return status_success; } -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) -{ - sdxc_switch_to_1v8_signal(ptr, true); - init_sdxc_pins(ptr, true); -} - -bool board_sd_detect_card(SDXC_Type *ptr) -{ - return sdxc_is_card_inserted(ptr); -} - void board_init_rgb_pwm_pins(void) { init_led_pins_as_pwm(); @@ -961,9 +981,20 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) return status_success; } -void board_reset_enet_phy(ENET_Type *ptr) +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) { - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); - board_delay_ms(BOARD_ENET1_PHY_RST_TIME); - gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); + if (ptr == HPM_ENET1) { + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + board_delay_ms(BOARD_ENET1_PHY_RST_TIME); + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr) +{ + return enet_pbl_32; } diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.h b/bsp/hpmicro/hpm6750evkmini/board/board.h index 416bd1925f..57820cb8bb 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/board.h +++ b/bsp/hpmicro/hpm6750evkmini/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,6 +13,8 @@ #include "hpm_soc_feature.h" #include "hpm_clock_drv.h" #include "hpm_enet_drv.h" +#include "hpm_otp_drv.h" +#include "hpm_lcdc_drv.h" #include "pinmux.h" #define BOARD_NAME "hpm6750evkmini" @@ -34,10 +36,10 @@ #define BOARD_APP_UART_CLK_NAME clock_uart0 #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #define BOARD_CONSOLE_BASE HPM_UART0 #define BOARD_CONSOLE_CLK_NAME clock_uart0 #define BOARD_CONSOLE_BAUDRATE (115200UL) @@ -50,21 +52,65 @@ /* sdram section */ #define BOARD_SDRAM_ADDRESS (0x40000000UL) #define BOARD_SDRAM_SIZE (16*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS #define BOARD_SDRAM_REFRESH_COUNT (4096UL) #define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) /* lcd section */ -#define BOARD_LCD_BASE HPM_LCDC -#define BOARD_LCD_IRQ IRQn_LCDC_D0 -#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_POWER_GPIO_PIN 12 -#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23 +/* + * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} + * + * HSPW: Horizontal Synchronization Pulse width + * HBP: Horizontal Back Porch + * HFP: Horizontal Front Porch + * VSPW: Vertical Synchronization Pulse width + * VBP: Vertical Back Porch + * VFP: Vertical Front Porch + * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active + * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active + * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active + * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active + * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active + */ +#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 +#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 +#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 +#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 +#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 +#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 +#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 +#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 +#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 +#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 +#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 + +#if defined(PANEL_TM070RDH13) + +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH 800 +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + +#else + +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH 800 +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + +#endif /* i2c section */ #define BOARD_APP_I2C_BASE HPM_I2C0 @@ -147,6 +193,15 @@ #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00000000U) /* lcd section */ +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_POWER_GPIO_PIN 12 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23 + #ifndef BOARD_LCD_WIDTH #define BOARD_LCD_WIDTH (800) #endif @@ -158,13 +213,41 @@ #define BOARD_PDMA_BASE HPM_PDMA /* enet section */ +#define BOARD_ENET0_RST_GPIO +#define BOARD_ENET0_RST_GPIO_INDEX +#define BOARD_ENET0_RST_GPIO_PIN + +#define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) + +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif + +#if __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + + #define BOARD_ENET1_RST_GPIO HPM_GPIO0 #define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOD #define BOARD_ENET1_RST_GPIO_PIN (15U) -#define BOARD_ENET1_INF enet_inf_rmii + +#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ #define BOARD_ENET1_INT_REF_CLK (0U) #define BOARD_ENET1_PHY_RST_TIME (30) + +#if BOARD_ENET1_INF +#define BOARD_ENET1_TX_DLY (0U) +#define BOARD_ENET1_RX_DLY (0U) +#endif + +#if __USE_ENET_PTP #define BOARD_ENET1_PTP_CLOCK (clock_ptp1) +#endif + /* adc section */ #define BOARD_APP_ADC12_BASE HPM_ADC0 #define BOARD_APP_ADC16_BASE HPM_ADC3 @@ -266,10 +349,11 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); +void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); -uint32_t board_init_dram_clock(void); +uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); @@ -314,6 +398,7 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); void board_init_sd_pins(SDXC_Type *ptr); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); bool board_sd_detect_card(SDXC_Type *ptr); void board_init_usb_pins(void); @@ -332,14 +417,11 @@ void board_init_rgb_pwm_pins(void); void board_timer_create(uint32_t ms, void *cb); -/* Initialize enet pins */ hpm_stat_t board_init_enet_pins(ENET_Type *ptr); - -/* Initialize enet reference clock in RMII mode */ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); - -/* Reset an enet PHY */ -void board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +uint8_t board_enet_get_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg index 686495c1a9..0c0dc2e3c4 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # openocd flash driver argument: diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg index b9ae112104..3f17d2cd77 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg index 580d98ef85..ff9a94ba6a 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg index 4fb0fba2e7..010869c87a 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg index fd8f04428c..d50578d3a8 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg index e9d6e6d698..00b431e533 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg index c053c1d16d..abaeb2f373 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg @@ -1 +1,50 @@ -riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534 +riscv expose_csrs 262=scounteren +riscv expose_csrs 800=mcountinhibit +riscv expose_csrs 1984=milmb +riscv expose_csrs 1985=mdlmb +riscv expose_csrs 1986=mecc_code +riscv expose_csrs 1987=mnvec +riscv expose_csrs 1988=mxstatus +riscv expose_csrs 1989=mpft_ctl +riscv expose_csrs 1990=mhsp_ctl +riscv expose_csrs 1991=msp_bound +riscv expose_csrs 1992=msp_base +riscv expose_csrs 1993=mdcause +riscv expose_csrs 1994=mcache_ctl +riscv expose_csrs 1995=mcctlbeginaddr +riscv expose_csrs 1996=mcctlcommand +riscv expose_csrs 1997=mcctldata +riscv expose_csrs 1998=mcounterwen +riscv expose_csrs 1999=mcounterinten +riscv expose_csrs 2000=mmisc_ctl +riscv expose_csrs 2001=mcountermask_m +riscv expose_csrs 2002=mcountermask_s +riscv expose_csrs 2003=mcountermask_u +riscv expose_csrs 2004=mcounterovf +riscv expose_csrs 2005=mslideleg +riscv expose_csrs 2015=mclk_ctl +riscv expose_csrs 2016=dexc2dbg +riscv expose_csrs 2017=ddcause +riscv expose_csrs 2048=uitb +riscv expose_csrs 2049=ucode +riscv expose_csrs 2057=udcause +riscv expose_csrs 2059=ucctlbeginaddr +riscv expose_csrs 2060=ucctlcommand +riscv expose_csrs 2500=slie +riscv expose_csrs 2501=slip +riscv expose_csrs 2505=sdcause +riscv expose_csrs 2509=scctldata +riscv expose_csrs 2511=scounterinten +riscv expose_csrs 2513=scountermask_m +riscv expose_csrs 2514=scountermask_s +riscv expose_csrs 2515=scountermask_u +riscv expose_csrs 2516=scounterovf +riscv expose_csrs 2528=scountinhibit +riscv expose_csrs 2531=shpmevent3 +riscv expose_csrs 2532=shpmevent4 +riscv expose_csrs 2533=shpmevent5 +riscv expose_csrs 2534=shpmevent6 +riscv expose_csrs 4032=micm_cfg +riscv expose_csrs 4033=mdcm_cfg +riscv expose_csrs 4034=mmsc_cfg +riscv expose_csrs 4035=mmsc_cfg2 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg index 3a0460204f..610d4c578b 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -1,5 +1,7 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause +# + set _CHIP hpm6750 set _CPUTAPID 0x1000563D @@ -12,27 +14,48 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are targets $_TARGET0 -set _TARGET1 $_CHIP.cpu1 -target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +proc dmi_write {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc dmi_read {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc dmi_write_memory {addr value} { + dmi_write 0x39 ${addr} + dmi_write 0x3C ${value} +} + +proc dmi_read_memory {addr} { + set sbcs [expr 0x100000 | [dmi_read 0x38]] + dmi_write 0x38 ${sbcs} + dmi_write 0x39 ${addr} + set value [dmi_read 0x3C] + return ${value} +} proc release_core1 {} { # set start point for core1 - $::_TARGET0 riscv dmi_write 0x39 0xF4002C08 - $::_TARGET0 riscv dmi_write 0x3C 0x20016284 + dmi_write_memory 0xF4002C08 0x20016284 # set boot flag for core1 - $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C - $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9 + dmi_write_memory 0xF4002C0C 0xC1BEF1A9 # release core1 - $::_TARGET0 riscv dmi_write 0x39 0xF4002C00 - $::_TARGET0 riscv dmi_write 0x3C 0x1000 + dmi_write_memory 0xF4002C00 0x1000 } -$_TARGET1 configure -event reset-deassert-pre release_core1 -$_TARGET1 configure -event examine-start release_core1 -$_TARGET1 configure -event examine-end { - $::_TARGET1 arp_examine +$_TARGET0 configure -event examine-end { + release_core1 +} + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET1 arp_poll + release_core1 } -$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg index 8e2bbe5f19..44c232b962 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause set _CHIP hpm6750 diff --git a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c index d025d1b3eb..ee4efc0bd9 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c +++ b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -101,14 +101,14 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr return PHY_STATUS_OK; } -static rt_ssize_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) { *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); return size; } -static rt_ssize_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) { enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); @@ -149,13 +149,14 @@ static void phy_poll_status(void *parameter) { int ret; phy_info_t phy_info; - rt_uint32_t status; + rt_bool_t status; rt_device_t dev; rt_phy_msg_t msg; rt_uint32_t speed, duplex; phy_device_t *phy_dev; struct eth_device* eth_dev; char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; + enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps}; eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; @@ -186,6 +187,8 @@ static void phy_poll_status(void *parameter) { LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]); + enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex); } } } diff --git a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h index 78b4350edb..1aab1b3c57 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h +++ b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h b/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h index 207d026da7..781dbe865d 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h +++ b/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -31,10 +31,11 @@ extern struct fal_flash_dev nor_flash0; #define FAL_PART_TABLE \ { \ {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ - {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 1*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 2*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 6*1024*1024, 1*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 7*1024*1024, 1*1024*1024, 0}, \ } #endif /* FAL_PART_HAS_TABLE_CFG */ -#endif /* PKG_USING_FAL */ +#endif /* RT_USING_FAL */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c b/bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c index a664b13fa8..2642e5123d 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c +++ b/bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,6 +8,7 @@ * 2022-03-09 hpmicro First implementation * 2022-08-01 hpmicro Fixed random crashing during kvdb_init * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build * */ #include @@ -20,25 +21,26 @@ #if defined(FLASH_XIP) && (FLASH_XIP == 1) +static rt_base_t s_interrupt_level; #define FAL_ENTER_CRITICAL() do {\ - rt_enter_critical();\ - disable_irq_from_intc();\ + rt_enter_critical(); \ fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ }while(0) #define FAL_EXIT_CRITICAL() do {\ ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ fencei();\ rt_exit_critical();\ - enable_irq_from_intc();\ + rt_hw_interrupt_enable(s_interrupt_level);\ }while(0) #define FAL_RAMFUNC __attribute__((section(".isr_vector"))) #else -#define FAL_ENTER_CRITICAL() +#define FAL_ENTER_CRITICAL() rt_enter_critical() -#define FAL_EXIT_CRITICAL() +#define FAL_EXIT_CRITICAL() rt_exit_critical() #define FAL_RAMFUNC diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld index 91de858fb1..c8b1045f8b 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld @@ -1,24 +1,26 @@ /* - * Copyright 2021 - 2022 hpmicro + * Copyright 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0, LENGTH = 256K DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -57,29 +59,33 @@ SECTIONS __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + .fast : AT(etext + __data_end__ - __tdata_start__) { . = ALIGN(8); __ramfunc_start__ = .; *(.fast) /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) - KEEP(*cpuport.o (.text .text* .rodata .rodata*)) - KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) KEEP(*irq.o (.text .text* .rodata .rodata*)) KEEP(*clock.o (.text .text* .rodata .rodata*)) KEEP(*kservice.o (.text .text* .rodata .rodata*)) KEEP(*scheduler.o (.text .text* .rodata .rodata*)) - KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) KEEP(*idle.o (.text .text* .rodata .rodata*)) KEEP(*ipc.o (.text .text* .rodata .rodata*)) KEEP(*thread.o (.text .text* .rodata .rodata*)) - KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) KEEP(*timer.o (.text .text* .rodata .rodata*)) KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + . = ALIGN(8); __ramfunc_end__ = .; } > AXI_SRAM @@ -145,7 +151,46 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); - .data : AT(etext) { + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -153,8 +198,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -181,10 +224,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -196,61 +241,64 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > SDRAM - __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; - - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .bss : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.tbss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.tcommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; - .heap : { + .heap(NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; __heap_end__ = .; - } > SDRAM + } > AXI_SRAM .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); - } > SDRAM + } > AXI_SRAM - .stack : { + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; . = ALIGN(8); PROVIDE (_stack = .); - PROVIDE( __rt_rvstack = . ); PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; + } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld new file mode 100644 index 0000000000..c967b2fcf5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld @@ -0,0 +1,297 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld index 5450273021..0d07141814 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld @@ -1,30 +1,33 @@ /* - * Copyright 2021 - 2022 hpmicro + * Copyright 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; MEMORY { ILM (wx) : ORIGIN = 0, LENGTH = 256K DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - /* It's alias address of core0 ILM+DLM, but accessing via system bus */ - CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K - /* It's alias address of core1 ILM+DLM, but accessing via system bus */ - CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE - NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } SECTIONS { + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) @@ -32,11 +35,6 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > AXI_SRAM - .text : { . = ALIGN(8); *(.text) @@ -98,8 +96,46 @@ SECTIONS KEEP(*(.rel*)) } > AXI_SRAM + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM - .data : AT(etext) { + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -107,15 +143,13 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) KEEP(*(.got*)) KEEP(*(.got)) - KEEP(*(.gcc_execpt_table)) - KEEP(*(.gcc_execpt_table.*)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) . = ALIGN(8); PROVIDE(__preinit_array_start = .); @@ -135,10 +169,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -153,62 +189,71 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __data_start__) { + .fast : AT(etext + __data_end__ - __tdata_start__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) __noncacheable_bss_end__ = .; . = ALIGN(8); - } > NONCACHEABLE - __noncacheable_start__ = ORIGIN(NONCACHEABLE); - __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE); + } > NONCACHEABLE_RAM - .bss : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.tbss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.tcommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) } > DLM - .stack : { + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); } > DLM .framebuffer (NOLOAD) : { KEEP(*(.framebuffer)) - } > SDRAM + } > AXI_SRAM - .heap : { + .heap (NOLOAD) : { . = ALIGN(8); __heap_start__ = .; . += HEAP_SIZE; __heap_end__ = .; + } > AXI_SRAM + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + . += SDRAM_SIZE; + __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld new file mode 100644 index 0000000000..34d67d4523 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld @@ -0,0 +1,252 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c index d9baae0c41..abe1e4603b 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c @@ -1,10 +1,18 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ + #include "board.h" void init_uart_pins(UART_Type *ptr) @@ -111,47 +119,47 @@ void init_i2c_pins(I2C_Type *ptr) void init_sdram_pins(void) { - HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_DRAM_DQ_14; - HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_DRAM_DQ_15; - HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_DRAM_DQ_12; - HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_DRAM_DQ_13; - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_DRAM_DQ_00; - HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_DRAM_DQ_10; - HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_DRAM_DQ_11; - HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_DRAM_DQ_01; - HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_DRAM_DQ_08; - HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_DRAM_DQ_09; - HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_DRAM_DQ_04; - HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DRAM_DQ_03; - HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DRAM_DQ_02; - HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_DRAM_DQ_07; - HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_DRAM_DQ_06; - HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_DRAM_DQ_05; + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_FEMC_DQ_14; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_DQ_15; + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_FEMC_DQ_12; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_FEMC_DQ_13; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_DQ_00; + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_DQ_10; + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_FEMC_DQ_11; + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_FEMC_DQ_01; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_FEMC_DQ_08; + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_FEMC_DQ_09; + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_DQ_04; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_FEMC_DQ_03; + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_FEMC_DQ_02; + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_DQ_07; + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_FEMC_DQ_06; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_DQ_05; - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_DRAM_A_11; - HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_DRAM_A_09; - HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_DRAM_A_10; - HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_DRAM_A_08; - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_DRAM_A_07; - HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_DRAM_A_06; - HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_DRAM_A_01; - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_DRAM_A_00; - HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_DRAM_A_05; - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_DRAM_A_04; - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_DRAM_A_03; - HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_DRAM_A_02; + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_A_11; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_A_09; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_A_10; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_A_08; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_A_07; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_A_06; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_A_01; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_A_00; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_A_05; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_A_04; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_A_03; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_A_02; - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_DRAM_BA1; - HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_DRAM_BA0; - HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_DRAM_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_DRAM_CLK; - HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_DRAM_CKE; - HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_DRAM_CS_0; - HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_DRAM_RAS; - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_DRAM_CAS; - HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_DRAM_WE; - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DRAM_DM_0; - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DRAM_DM_1; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_BA1; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_BA0; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_CLK; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_CKE; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_CS_0; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_RAS; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_FEMC_CAS; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_FEMC_WE; + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_DM_0; + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_DM_1; } void init_gpio_pins(void) @@ -358,17 +366,29 @@ void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) /* SDXC1.DATA3 */ HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; - - /* SDXC1.CDN */ - HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_SDC1_CDN; - HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl; - - /* SDXC1.VSEL */ - HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_SDC1_VSEL; - HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl; } } +void init_sdxc_power_pin(SDXC_Type *ptr) +{ + +} +void init_sdxc_vsel_pin(SDXC_Type *ptr) +{ + /* SDXC1.VSEL */ + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_SDC1_VSEL; + HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_sdxc_card_detection_pin(SDXC_Type *ptr) +{ + /* SDXC1.CDN */ + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_SDC1_CDN; + HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); +} + void init_clk_obs_pins(void) { HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; @@ -411,5 +431,3 @@ void init_led_pins_as_gpio(void) HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; } - - diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h index b785fd3445..44664ae7f0 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -36,6 +36,9 @@ void init_pwm_pins(PWM_Type *ptr); void init_adc_pins(void); void init_usb_pins(USB_Type *ptr); void init_can_pins(CAN_Type *ptr); +void init_sdxc_power_pin(SDXC_Type *ptr); +void init_sdxc_vsel_pin(SDXC_Type *ptr); +void init_sdxc_card_detection_pin(SDXC_Type *ptr); void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); void init_adc_bldc_pins(void); diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c index e0c7898a79..a684a369d3 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -107,6 +107,12 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) rt_interrupt_leave(); } +void rt_hw_us_delay(rt_uint32_t us) +{ + clock_cpu_delay_us(us); +} + + void rt_hw_cpu_reset(void) { HPM_PPOR->RESET_ENABLE = (1UL << 31); diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h index e310e58f98..100b5dbb0a 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c b/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c index 276631285a..5ce069ff64 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c +++ b/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c @@ -1,13 +1,13 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ #include -#ifdef RT_USING_WIFI +#if defined(RT_USING_WIFI) && defined(BSP_USING_SPI1) #include #include #include @@ -118,4 +118,4 @@ void spi_wifi_int_cmd(rt_bool_t cmd) rt_pin_irq_enable(RW007_INT_BUSY_PIN, cmd); } -#endif /* RT_USING_WIFI */ +#endif /* if defined(RT_USING_WIFI) && defined(BSP_USING_SPI1) */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/trap_gcc.S b/bsp/hpmicro/hpm6750evkmini/board/trap_gcc.S deleted file mode 100644 index 40de7b31c5..0000000000 --- a/bsp/hpmicro/hpm6750evkmini/board/trap_gcc.S +++ /dev/null @@ -1,12 +0,0 @@ -#include "cpuport.h" - - .globl rt_hw_do_after_save_above - .type rt_hw_do_after_save_above,@function -rt_hw_do_after_save_above: - addi sp, sp, -4 - STORE ra, 0 * REGBYTES(sp) - csrr a0, mscratch - call trap_entry - LOAD ra, 0 * REGBYTES(sp) - addi sp, sp, 4 - ret \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/figures/board.png b/bsp/hpmicro/hpm6750evkmini/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..5159b7bd6d8e555f45497c1213b5c1a1043257d0 GIT binary patch literal 149625 zcmb4qWl&wgv**Pg|WA=`+)Prl-!Cp6;IC#C%ne#X$Xt3IG5wd~8DrY%8 zHvj;~{XYd}6GY(+08j$tr6e@H*G_t@g2_fa=%4Z`Kk!G5g>i(TW0@ezamJdJ{=jF| z*K1_ezY?vZn=tb0$*|WmI)1DfbW2Gc0P0aQ>4lUqs+AB)18C*2Xp@mLbDa{%DyQGt z+t`Eq0km`)EOW1~Swi=o9y&TY0UpyjWhxpiKtfCdqJRENZEL55rN&*#C&6 zoiE}4A>=Oqb^jwu9{$6JjIHkfzXgz)ME}Dq8H@QJ=KrY_9>xD={vS&H*AU_V4=F-4 znP2e#bb1g#;BFJeQv3C>2><`Q|G%d29bU4C{-1JUb;!3_v;Rla|KYU$uQC7sq~2{V z=2hv}eb^_*j65IeBIF^jE71F3 zTXe-MM`h6M<7s|be>Db|t~d(_MxGX9(1jFME`$!75?zB+ak)l4U%NC-5}69)i^7bH zUOg3UvZl$G6p2u|2ME2jsT_Tu6{sdXL(*Cv*p!yS+kDQ_pTR+NV#ii8o8QWs3IpOm zuJ*4%x4}uR^H=pLNh6R-B70ZF&Ka1kh5;GNPjJ~o9e8wYCYtp}4z>kYW^{ly95$v{ z4U{$b@^G;cRGD&IVf~YmsN%u>@Jw<^Mk39wuAqGUFHELcKsybhDNtTS5+(Hmx^)KZ z*I9T1TEOY!JdZuJa`|XdFkNNQ?h`h5swoP14SxX`);~0ag_W%{J=#i1!`Djx^PiY1*^^eL=3tqO}3T%h{cxg+&+fM9093!_p$ygkEXU+BV8G9U@cd za&U%>rr{_&XR|Spfy1$YEU=t?l(1+_&(BW;`};f++|3{mq8(0X7J^-p2{MK8l`UDaTXfkzo$qtvE_@idg>OpAm^>sQZ&sQ+QX zfgOU}HUC}aULG>xE5ZIIK|hf(&R`m<%fyFX!TTkNb}E)C+?1#$p#tb7tIn+fouB_G zHCf8!5f|J-kHy_g6{OC)XPp&bhLr#-(pHArAg)B7xL2)!j> z`cN5We0Hs)NK>pB#kzK3Xwy#A{g!@q!4l*LZYQx{H3IyXf(tHPKy?c$D{@hm1Z{<3 zyxfrOq9J{7rUX0=y80w61TVA*P>~f8459{^*~l5&nAy4zaHCOgTww#rC?=~*Op%u* zi6G07m;|%%%jjlUVG)#A(Y)}XSza|R0&Gz1HR$pvX*|z`7c$^ zu4rJ;7oXWktZJg!>}?x17$#&XNuuhki1}<7d7$FLY&Mh)HaI{XUBX0J(l#2uhj>N{ zZ8*gQF|)*E7zdtuIUByETUHq!2FA=ZSl2EC9#(PUW zaLUatJLIqo&;NR;CIE`#634cnSi`!-W#i*YLHX0vQKv*xDNC(scYJE`<6rt^-*1+k zf_9H4KB-zgAw4~dy==Y3Rjw53G141Lqn{&?;!&?t)#{N*~76tI~o&S~?yqM?ZzmI181TB28Pg`uibXa*2*NQo~8 z>MtcZzbsqx!4ua|)OhMMv8iAwACp+mbD;O|f$O#!?m|yVnpm_E@Gtd)WIibS@1Jcv zCwv#tmil_)@T+?-Qs?#R;LiX%Bw%;{eUII#^K8wZQ)hfiC}FS!gGw>(@tS=Td+LsR zGzn1uekf9%e(qOIRO07{grwteq9m|uE_<}6&YJF7Nkmj}%65|FF52VWRdq_LRC%Fi+XF*tZEIg^S$OWtb^v?^&MsZ499pPoXvOA-n$Ti( z5NzM}1&|LNaLivFuw8q;7;9PI+IYFlNiu^Gi&m+H$~_`O4XT=7{@;wze1@j55F%lB~rOyQ}Xv7BV(ju5lWz>ME7wk17R~!z{$T+GW z#+U5gw(sAdbwS&3gLW(N!jDp#RTKPPhC#y_>4O^$N?v7&yb8l`NV4R=Jp5WkPqvmBCe46_3 zHELF(;Lp;$)WQB>XaQVex5H0H>HdDwOuhb%KAh9IBkce@qRzuK(c8zF6aSOnVhevd~J#x5163@|>O$nAj(7fAdyLY@!5 zzB~FI=;DelOfF9LzCpzdeI6%lr-o*;f7>~EPi?&qGF;P`N80FKs*H??pVvcg;@ca7 z-WPC@WSeZNZUb7*VB5V%SYnlbsgo#(JcY?-Pf2HJ#AsG)bay%BQ7>d1Rcxq|2b`>a zbI8UiwV5oJDboGbeHtp&YOL_3{nqe4z7n`fM;Cv$6t(Pdd}xHkrNlEr{~_T_?85`< z8jtdp4q(}-qx`6eC%jVUtjiAGQ5lt55s*nds1=seXc!<0EiEaYAs1|Xr$j#C#;uM< z*|uCU-sbXHmElVc+UcjTIaL_^_A_1`jB2ubada|EpaGP6@}n`%qsR+M`lQRk$C@<; zs`Fk=UsK2~72tGrHoFn`aGbkNvs?ub&=Y=IcUju*bdw`exZY?B0IM;}rq10Nd=`x4 z9pvwRYf)dL{qyUf|HE(rcN(w_@|-Xsc7f5i;%()x=n_HR?W@$=H?Rg6Atyj$>!@V`*^T~Yee>6pia;`{&zzR zp)pn~`h-8F*987d@xH~S2snn95Y0}fR|0JLwUV>0{jEGRw)q^``XrXpkB+TEP39xu z=pp%u;fTwCL=i!b#R8HXwW-ph77;G$()RNN{i@;EJ7Hr^J6lb%ieJRl z|7>B~2a6_NRlDJH?`w8D4ipRtf@?c=L%)fo!JaB@PwTcYUHYEa#<(_P&&xlf4eWsd zE4aAhW$)coBuI&*PhnzjHLCt6b=uXNc&NN$4#Ia2yFu?WL2KpO?IIpukeZ>Fzr$Bs zeN|d_pl>+OKqHHLpAs;|g+}hrAFocm7B#;bw2-?36QHtSx-KrJw5F{$NI6uXY@7QV7>W?fjT#Kb8JfoB~~6 zq4B*Ob!|=cg<%E;t<+itfImWErYC<~;@|S#n5tvlBYfWqdRSciLy8Aejlo%9SBkqFL4x>p5%eNT ze1{2nU4ou(E(MmNc7U3IZjEEV>bf5@j-5Kd^`D=Y*!>Sz#~yvBXsCFu*Zt|p<1A8^ z&)UZ#J#&{Ri^NH7b4y{>wG)ELD;FBC5FHt=%L4fNcw_w?m)wW0T+ zOO>7Aqk^@un@f?Y9yM+gUp3jo#?~Vn)gOMR_i@a7@`^n>^>Kv_HUSkcYI@z*x$_{C z)1PiX6NFzA3wi@gYvHE=>6Hmg@!s>_vafK1UY=JWA;m}(&m-&sZZ4ga=uLC(=}}rN zT~**K=$8A$L|t!#5qrR4)4QuTq=Cb@KAaTT_OwCqGAQHC*1)p9j>ITIqf0w) zdOD37d)!LqIbp9qfJf>w9#q6iw3Chau#5TV35fH2+CZ98jW84nIEbhy$ha8yS2aHq^be;S% zsD&>qWwb@nZFOb-A&`|Le3nk=)NZ{r7)1z@xvp7dA?NK(Ngi0_)NsfXX}3C=z4R7t zNUDNy=FJJ6j5Zug?;a>uqWzig>+3-;FlbP|h;IPM3SUZ(T{H5b9DeN3tDUY@k{%%# z2N;Z~O49+*a&rW#QI8Wup5&a0brV;?3UI*}x0Rnr`bHmebA&WmJ_)zlor|xNPUyfq zKpKN<+lkx$-25u~c@rCeDQZv5%G)v3y1uxAi?Ge)^pZ8Qf*}>?zQ4h3$tkevPPR7? zqZ_R|kmk&g=o5z|JQCo&q7hSGy)2)!SgnDAB5tEqfu~^ZM=zV8L{40zbF3~0)?Ca0 zAmU`!9aI!|ar3-h!1>`yE#xm8p%@aQ1!Ibc2|;tAD~$W}AIP*@Ktlw3GJ_m*4j-{K z;M^}RqjZLP%E(_N48{et*&^lX*Z{za$hxwGvm*aL59WTjle~(Ox&dEe)HkQT$5E1Q zyq{=6SAJqNFo((JvjuNA+6sPZs?GQd34rQUrC&L2|JJJ7@_Ri}WQR&I5Pd~NXB7Xa z#MS}}2q&Pv%I4oBO?Q>yybFPIko>Ok4yEdKc&&}Px(elz{^Z;kNNx*GR+!(GGW~jEQbgr z$gELVznU87_^bc%U}wIkDoI{Vv#2{GM93Caw}V-KS_?p$H#Kr1$3eUHrJ2F8Mn4Od zLr~i`Zko)T;b6U|6_JBWM`379rw*Z1o6D^FC>E~WMDbnO=?RQ<7IYJ5{3xMcqRIC`C*!}!17!CrhYbW4@|ZP``j@2Xagm&V7b0w54!SX?SWiGy zp7nlZtm3AIp$HnufRj`~T?!!uR2I*O{I?7+q&eC5md~5|>NvsH!fQ?}080m*@dyj% z9F}J2Y&}#<83)rs2@p0|HKBDo^rpsck{WG#OG_KPSuV(><5qIob^6Rj>miC>8l5ht zhXZqakjl&spe>Gh9M)s{A)w0MK+5)|`ZOMpIokGY+A(KuyukxNAFAPH!HJR~yoxo5 zQk``?#u+$JQ3Me9xp@G}7dP5o=BKI8${-G6c5sE5a-5wN>*X<@__awR-+s0fN325R{!pu%J+x76_&-c~7(ETw%u zJ<6Yv{i^`kC(F`X_q!=T-TTYs@HQE0Sy-4xr*f=W>g`#1!e^+{0W8$5%_s5(Q~ue5_4!)tX?BA3UP-O z=SuFpu9a0>ahnyvx<@Mq2&P5|!4=ph9R^}foQUP*>Og8)n=|bU~+AJ=UcJ-+x zYChi|%#Wj7{xt4>Y6vqHGvF-Pzc?BH8TVMgJ#jVewoB+B!E9>5y`j?7xjQgwVtkwG z)m-++w)nB9tM_u+_|chh@dfXjH#wO|#stN^-bmMilh26Lja6e!!PU~=KLZ1?XG%KE zyj+}^h3q6v)uR-z!v(G`oer1sgyLY`ON{JXw{f%xO(z1ZYmHO|D8`^_h?@kXSKVIE z%M)46!BDH(wr{PhMI9eEbg~tJ3WjpNt|#4^oGOSJdB6W6yG3Z(^Zh`sgCWNy4U}QY zWiH?J`&oGgZZtWnnDU-r$TqbCWlrV z%Zw@_oQ*BBB{G{;>sh^Yw|T;@cmv6QCQgc4r3q-?+LJ3)-SZ;e%3+$R)>W^&=I4zn z&bkItXRr6ojfABVRmRI7oU?F zaC`Nif-#XL4#wsb`pJbYp}uf!F4Hx<4qDI|*AeX+r+v)G`NT;b=r<(?T&p9Q}mGnS`t`4^(k@8q83_# zv(gEq)KQiHz~M;RB}h+d3LY{hrbnuq&{Ko;P^rXYdBv4gu_ffJ3t$R(anY7)kw_$& zSML3#5!LK)7S@u2u}sdw$2?fu`}9KLI5P>3bw+h*J^K@?U@{ToN!x>lOJ>l>!ikH=Um z;Dp$dJN=yX=l8b!y!yZ&A6D}ey2jrd;>y%xrh!kZbI^3)D0{%CL-)xQu{Y0gCHgt% z*8-589ad(*->HD*Qno6gC-j$6Y(sN*LsX$Adx@@hU#q9u)ZSId?)saPD0f*kArNV- zx}Ou;dA3J5y*Ke{STXUbr=+Ute7oNY;<3`heGQgsz0bB|@3k1r_T^;9QG+Ti5?H;; zD2GIt)ift%AdaMt*;Y`Oa5(5yEIlJ3#-c3@G@`SR$4EsWY+asO?@VlUAI~P62W(`; z=kRN?&@o!-Crhy&hEjN2+!GJk-;|(>-`v)qAUd+;om4H-ub^kElB(5McEn_5nVCY` zf*4C42+7dme7;a-%K@-L^&SEA1QXSjgw-Uj-4d$F^hXM%U4DpFDjU>3ooDq2W4Z_| zslS@`k;Ae-qLp24M(o!BkG>GGNL%3B32qQtd65I8+X`D}A8ow{o!9=v4^}09Q?7r* zY`@oJ*7!td+;^GPPH6o!W?y+lt;E1y{dTBXy!s$;VE%ZeXi}1Nr%xhi-0BdKbTlMI zLdL~Kn4Bj%;ctn#elWS|cEwL<%<-_n;L6_oL3C&~7Sj7#6?Ae+0s?K-AdflH^d9DZ z-*`Fl3Od=PFz9`ZtuhWA?w38w)n{dqVNI$dYu^AX{?n`_LV*w0+<4|M zT6`@lD`JvC6Zohd;@T6@t--eLf0_<>yJ8o^jW5kyLg~ly^*kFre|-ze%lyPTco|$b zCcp`U21sBDAgJ+Cvs=A*9bQ+GyA+EL)c4p&PtvI=<=&v(8~yVyZP?^H?A)ULG6xaC zMcdQ=)V1g}AzNCCzM!y%Qqyeeo@*?W6kP$p`#3AHNF!g|D7IrAIGZ4j3Y4+>diXW5VXb| zO-wq7J>syI9Bp$Tj>@5e%o_ssapg@bX00;(()(MAh7UkoZMvq$y$uULuiWL$)zKW8 zT&OvMa*(SB5B0=}@w`mHoYR9`gDIj{w4I&t#JzMtE)632yMmBEzCra8!bd5ndwj_BZ$O?WrH+g zz?gL9R59L^`abeHi*u{ar+^tcDkbiL6Q3mnOf*m1hvME_Kfq4{H?ZsB!AWRn-yeg(hFlZD zvJs;td^_LVZ%_b_Kc=H9kKt{%)I4LF;`+iuPC`OF`L2`~STjE}r^jCF+=S<{A@NOb zh_4%z%$rIDHpP~+>1FBKF@Jwe+`8|_WHXh)$Y&}(n;RXq=EFZdoX|Y(h`DrGNu@DY zNP?xLD*C;6R7CKu@!K05Q$eRBi*Xrw?4-WdqI@~M(#vLS@QbH;nyW^~$Sqaw3s zPOw_=%b$)}R61c2>VTOZph-2&yYBuL#J=Q62v7pTq{^WF&K?90VY_eMPb{T-%4D2Pqj?YAn$ zMvvuPRdPU~rCra45Qocnl1De_-vYvDUo;}G)KYlA8hf`K>Pl0GpqYu`wD}LOU4|!t zG`$u4l=*V5#Ufz^P1x`qg?n}$l_koeKWEk6TuKHs=;Ay)D#B%{lqu{n2P<*qv!s2Q ze-Rj1RFV)Em+Na|%hAi5M5Latl9)YG8rCO4kuSJF^?mqnEWl_LUPFEtT<@jw`DD6V z$FQWpx#McHOxKhMrZ7KnUh(ORgDU@1+}B4dX0=*>~fgK=kTD(oc}K zYSy#u+Y-58{S;$yngYY`e36z~M?svY^RYDz?$yRsxEW_tLSez8j^0_}Vm0B|$=_mY zlg=YUNvZqZy5*2|1v9g%iIGQL18qtKX<|Y_@IPB-X$(rzoJtY2JY5q^B+UFf4ImDL zFVsW84av&fO*S#lhf^-$rIwKU!sZNduTNQyt}S;vY^gM%sk4|OfI&RzaVIp}>X+$UDSCr}X0%d$ud;q&~!O8jg=IhPS zsN^$4L8$o-VsOo|AK8cimm$K}i;k2!SdOr7$oe{#Z4L*1_UEH>!<5ss-l3(Gsef8| zMIg}6tzT`HwXDvitxi0K;}zR#nEy`Pi;3VHh$QvG1MJUKthkmB3_cmJbVQO^Yn<-9 zaz4Klp$8+~wG|||?Hrxntu{2U5XX@T3JR@Q8~1eaTZWG64E_6gBt3U-TF#G;&;gBW zkpkEAWce1EYg0|1v45X^CRHv4Xl~5o1k~+PWR`XWF4-vsl&)wuA{hdfRv;3UbZtdaZv;fUaQ~kErv~d`3)U)Fol}PISXKdso znoQZ#C*m=#%}KSwd@3@BUDfHAd(k(md_leqf~~MJa~u{#|3Fal%cQj;Hip>+9Ado^ zVqw}dw_G%P{|ipO)j*Ju-S?8$ko-yUt(bBmFy6DmMItVt#7%cD%Q>!I$PbW*QASM5F*;eUDRay*=o(Q+epa#2=&`AJeI zY&9qzx24K-ntXF}E2RB)mBSAAm5se=t;0w9&d{mD>^b8k%kil4yTeQReUF_t2au87 ze4@+f8l$fJp~lI7czp2+ql?RY{pw$S8@+UKItf|pY(4L^^FqHLp0*Bz*p9HTyBi(5?KNkf zX$2(P)vY$z7@l+WV9(|UU2ElRKK^Cd=~Sy^+n=y|&DMeJL>{w$URY|gKksJD!0c~Q6(|M}3;wske_)f0I9S0kK|BD-H<^wHoELBFutW&Vr} zfY!0*MsSt>wAOasew|P8FHaxn;l1>6Wr?>uF=!`fGhl_kz_2)b^bWk_UdST`91p0PUwgES=undg@7+8mfSi-C(g;|FI>OXYc3lqAC40G@D-y zY1&4#De%R>ta}5(k_qt6uHXG1=5)}4khAss;eMi}#;qiA-{qH7JN^RXN^D!nED|GY zhn!djmiXu^hM$RScxcreLVT&GdJ3g(*TW+e8zLfx6?lrl$&*8>xkY~`2MTg?3-UAb zKZ}a!xO6ohf{lENd}c%vzmW-`7OL0MYK-B+nhh?Di}7hq>D<9s^N=JNKWj{E3+8`^|4+lS3X3HG3)et@qhCvq0>= z^&KvIZ~xAVsq^)=^VvUKGi|?ZYZBr={ke(&4jV3)16ehDAHYrp;8a#TyOBhd#F-`C zs?^3#c<%CJvBwi{E|5ysoMqe$!E0F5NN@vaN=(ZhM$WoM_Gg@aYrd|`&XZ}Zh>j6k zZ_HmjlvOVd+U)2|8T_y0R!w7)MUB25s^^dTXArCJ^)yk5-~1pW+2;MFO^^O9UtJpI zpButtpN&0#Ka~S>*+HodhX%yKNv@*Cfd@rayK0Ktg*@@mmQp`FY2Suk*2Qd>WftF1 zKEGMH@ScJ*`hv5>UMqS7U&fw!=b{3ii#=)g9w1c1NA?Pc`n5tNRnkeIU{%^Z>mbIz zrPLMa_hNU&bpd;Bk`?{^A#t^xcPVjopZQuYhM{lqt_y%o@3Gmc%?ngBijdra2aoN)9Fqs|&A?L#;+4%bFH>}+}4Ua4)5gS01~yiB!cfn)n=!RI73xoCGU zSaG`gJdY%$U&yYsza%czYg&hFqZy!_v??2inb)Ton2sDD!w=FF)9GA6^jYY5Id@q( zc@E0SeBZPB?-=72C2LR$Qx`Zt+E2UYdD<<8el3uy4_iid&v(VDuz|;srH*cJfvYPw zaJn|7Z3y&2eZ-CN9$P{Qh2xCrIxzV+NYElk4?hf5E${HAiCR(9CEol&+Q3(&r! z=M{uPEJp5GzuN+;b$PrQL45+Jeqs%CV)Z=F&%T>aZ})*OGzGysr^k&!FGVDw>54>` zTA(ND2nz;zC#zoaWRqohXLHSTFF5DCJB+}K-8PkUy5Lg6Z*}4YhvD>rS53zGImYX) zfn;*r7aes0X9>_Zk*^3))iQ$7uvQa*lixFYjb2_YnZRdmzK!oOiBsvVM(+LGyBZ@u z>0uU+;`_c?i;;0hi;&3C!F2Eat;+Yc-WNDVMBDQ%s@TcldposqJcnm=oBeu889DWV z_1i)VlMisZ5%+Ii8bI_e`Tg>$%9s#%$qxBS10Nk-{AU_SMrBA(d0_CKsg9kCb$(yb=pT^L;$#CWh=34NM54uU8jS(>N+9_pZ^6x55$2 zi-LT8#zY1&em^pdIY>0@)~zVRWhlwl`tq8(>-OHzc4(KI4-X#v9AU=hm*Ur^nO?~w zl&T^7FI%v1o%1Z?wxE$-)N(4IwPY2-Fg5Av0c6Gi(R&g6+dGAR^#+v;pIb%IKGwb8 z9WD*#G%xcTctr5z%i5)Wg+x)(eC08Ha%mbqpNTQ3x%+d8qT?6g>L=cSm%&6P+e4Ih zVa08bC)AFghF2?>LHG~u`5mm(8ps%; zQKfT-UL&&mXK`ggWOmE1)R?zqVelKI_Ig^RSTX-h8MDSwZZDvf}0FNP+^td(s)xuRxLUC$?>`1?#6A&^c73+CcemOKDW%3rFsk` zUn90`zRdb^Rr86JLA7k*@J!=s%p#=>uZ}m6n*8vezc$W#isROS8_+J4_d&^C!2$=M z^7kHcR;%=scEtAE3-GC7*C+OO|HGm~m&#Ff^>LGt%gkX57Z`Dy@Vg^?&+D00K|yNG zCy4jN^XAh}W54H|R!7}p;r&OfGE*pEXAC(Q;%)B?9p3# z8uq=c`%@q-7=Qx2Y&D5lt}<-q5SAE7D0A$+?%EA{oiXgO0bJJJ)xSsN)ONj8>N~4@ zcH%<$1n0O~8}1u6zL!2@QuyxtxNgmui2r9_5zqja7B_yXss%xB50$(uC?3>^O4i>$ zKC|6fTF_BuiJVTtYY1b@V}+N+o%RL{D5x4q-8r>0r79az?|i4({R zm^6LTt^>oJ23Y6?8La z1#@$U6dR8#rOg48Il1Q+_0wF9J2l!fyf|UR&?7I3JP=XbOZ9ovqaL%olsEVvlI(kq z(onUgFm>oCcsk5I?fwR`8=o!o8H>Zi1kfg9Rs`JebH?eb3`sk&n8IkR;K_a)y~GCO z?Z`Zz8kh5n0B-;83^d&;(Pu{k$;gURC+Zh3K8Sk4iwAlAFb{4!7m;)N?AncNQZFVS zA~lbVb=2~=xC;~R;M|T-6+!4*u1VN@>dZHc8(OSrCT*V5Fz&8|_aTiD7$Bd0+I9o=?*3bZ&kxTyU1C>_;`wvSWpw7^(YT6Qm5A zfOkKk5m(UyZ;^uDKc0e4A3gm&7Fdj+&RRpw_7i3sV{ma&T$fv7S96gI?ayaIen>ij z_pL!z8wwoejK*{)@H_GA{+73qOT)#uWZd1j3-dNUM}MB~c!N6>c(X|J$JhX0QBjCc z*H?L$S0k5wvcj)IYZCI4g-|1xN4kFG6<03m z0nwadS|WA2erD3*Q2_tk?|nNkXjm1gZ*&@dg5y>Oh+Tl8tzG!9V>q(SfZa6!@hkJ^Vf9n=MtSqG@mZ$OZ|bKz!`!V#4cp(o5oD~m6$0?$ zW=v`9QW%=%x3-=h9(1#;D>k>&KeR_Mbnm2A2A_&bta8 zU#z^&12R+;6tb0Wt93bV24%^g`;bHzS5~0OB1(g{dYTus!3rIGZ?FqkEe|3b#z6M? zAed+=8mFL@uFZepfye!QZr3hO!Drs)Kq&Zo5+1a!dtegO&Ry}sin!SQhYN8RPJLtM@i}jOs-wex`L51ey zOO4Qd0_(#zgXg&c>nEOL^5A%A9Wc^*tu8}YAH6)%(~!5feSMlH1rY6WGn$ne#c|}} zA+LFo0a` z0iX5KSQH~3H2F4>wPmX!_S(`3!?vF)9>L0OwuMfnMW~di4cSY3@}BOE>t;nA9hRki z2DONkc`YQjdp@3=TeVA*{vI91BsDuzS6Ar;L@YQVdidXkD0^q&0Yzn2(?nZWi@%xJ zz(F{}-veID-d`?40yJiV+D}*A{?tJp;Db9TId@Ch2Cdky&{le`M4Wt%gC1Lqb24-A zuB2`>16^F+8)&%AX=D=r@!+iaYyq*?K1(1t&+l%L**EXG+k0+BcKWBbmzpLZfk`lsOPod`# zoWR3M3KJ(vISe+#;{qlsvs2cR&HINoIS-U3JahIUIu83ctMg7_zScF%D$;r9Nsox` z=1)?*E^PGPTwVVQRfPvHU_7X8jID6?%IgmMW%E1sWuFPgKS(gj!f>FQW=hIX+pRbX z-&cPB=l0414lLkbeZy82V5=n&tT4YIhD3&qWXkc= zeB-BfGc*8kNg7l94Ez}fB_lL%Gtkg4kJ2H>yf{^Pr3r3npmlfO$n`_8(tPx)nY(=m z?98~D;6{$#Qu>;=(KFqeW0PJcdp4p+Exsz9jw4qI-XWz0Bf-!$G6HdfHnI>-n+leM zqDciG0I$kON2jxj1)~pne!oind2=cg!Q_^C4rMfkE_5Z6hq%vv<8TWve30)|(+gc3 z3`CnmMk&B3LAP8ikFaNxy&vK;&J;rYZL?bU|=c2)el2 zP=Tdp`PdyrYYQNv97HZ5nLy{;h8Kvi=teEX)LU6dE>AvD@tPmf*;mZkWDUlTvFFM% zb&*^R-g)f27kYPo?{XA9_uzMGaKLcnu%lw#@L4EHtM)hj$vphhyY+Yj=f`ke3oyYE zUIvsh5H5efoSeo7c$3W)r`pC`L^uT$t6lTlv?}K$q+jQq@Ei85{>Bem+46S_GVZ0K z3u{lmT;VXVW$rbq?Ya!dpqzKF%%AyFP(9EZ+Vs_M(M5%yTm6sv& z|H`n*iSvse1|Pjn_j&Lh*bU zT$)t-&=#)h4FrASOuGj z1h|jYG^MM&f3yt>ifGZ4Q(k0vK2q6)WQCi`veq3cd|@<8;=yZ%8EpQ|PgNX>Ais4h z!bq>4P1}c95}E>!)u-w38H<&dx_XroVSxvIm^NbGqCNjEjis3foi7~Fk2R14Y_e#? z_qzq9mca8gz_TpyP+?rP1k(@NcP5mHQ-<=$qlH9UJ_J)YmMof#xZsBsqSr^Zn)Jcj z)U+Tf&bSC;p;0fZr&2u%%V*Fhh9~`D{#-3@r@ThXQDTafe3AAoX|~$%^f?y6CTSj+ zR9Nm{O_!Ap;C!Ac#T=wGZJaITVf%N#sfZUvuIO0wIU7BcmJ!^4pa4#dx%r*!V&1`# z#J=@B+0%t-9CTQET&ugagln}-i7&V0%Bd4%vJW{I>+JrlQNCOfz^CmqVP`Z!Ipc=g zD&p$CC688QuU`>Q!oTIV71ki932!hF3Urcp+(SK?E`=c#`g|FhHQkyQX(dN+GeB*8 z*847d?mgo)l)C(WzY?^|*m7QxEcQMTb1nXf`__`CnaOIle81`krY#$ zC1bu`4->?l%=q2a5-=>e*%+Tr zX0a)=!A?z!{C5uYIblJM|G1n{rREcGLR2c7*RFh8@uvt@L)tu6XpFzH7wr2n#tc@H zdhS7b3OW^X^PVN)4W`4U&rHv7md~KImAf11*7b{Z{n4?eNJTTBZnh+MrXG&}RB-fg zSkgu3AS^HyJClDd6QeM@4o2ytlD&-56cCF^)h_by@>2)^28S=4Ct{v8lbDu`W+@NA zA*8k5Xs%D4<8xJHSS}Q*7giLbOi$mA4ohT#h1dM=jwJQ60@9#b^EwMX7MxP3E^ajb z8d95A1uiyBY=3qpk6dtcRty3PVpt(DYlH7~O9jn(k?ApxP(S?poqi;WNJ3*o4=T}*4&QZy!_oDGDG^y*Z$_K zgUb_%@#~KZg8j0)fXAwZ*B+Kmv(1Gr%>3xa_pG!YV_Q7cP@W?TGu;H!*G*H7ZS#Zm#{ZJi^x6v}N0DZ>jZ+2W*BiXu{03^h#`d?49 zwSMTh?3|!^W%G$V%CHRXKy=QI3umb z<50yFSg%5BZn$yiHr->gLes_G^>#$zf9eUS&g#!#VqI_z%cGB!;Gl%r@q9_quIcXR zB(*?DinJE!BYik*vBd!BnIr;-k=Nz#Sdc^eQuMjL^PmUgvoIk8LUuWir_Ozz8ydy} z62&?!pQVigU7!=6L@&0B0m)`^^cWm%g1lkG=qMHX7X7qPr-)8<2h$*HwjzNjuyU@) zM043Yee@`RG2K5e*R4jrj|t~N&q6}A0TJ`dwMgee&3+WREEJ%^-;6%gJ&DJ50NR>{ z;k938H48=20IIBHH$g>-kV!Ikd#=+Wt&QDO0qp37Jf7iFjup&080W{;=9ZJyisKDgB@VEps}xO-iJMx}s_Ic??;8&7!TNm8v)^HkC|+<^=89 zuJ7D^+r8zg23!>)0|Pyv!PVNNb`xty%GQxj#Ud933X6urt!%=2E#>d=IK7Cxp6DcCz~|y`|Ht~+zqDC0Hs~_`p-+Ze&O2X-w8g(bPj6x^#HvlYotzD=5nO^Y}-G-NQEW0MDN%71b4^ zdIp&>o&qdoLB2oP$iKmN`lb0O6Ic}m{URhKsjAJNpYy$F7OK--Y__pG4tj_S8>H%* z!ukNQ8p2xL=oG?NJ#!M%1#0?Je@B5^I{f^7*t+c_pwMczN?iaiB?cXK#tuyprq7{% z7?(2|gGc*2+zkaqoRwSL(K$YQ_Gx1$Iw>_WAXZTUAU=VXq;_~1{4swtm;<32g49u2 zS?+W5TZ}&SM^pPtqoU4?UaRe4cWLp+VduW_+S4?->Z7J4|F<$GD;wfFz36vFGhtZ0 zj8xas(cRf2cm=i5{h4!h10(MrJ-0~qgT*xOZs#<)GPBtpao_U@Rfm;*7lK?p5v23k z4T5r%IMp=6@#M8pq>0ir1z#V`6Itc}W;V>}jYq7>?s$MdJY(ROmk<$IY8t~SWo}(W zns3|1^uPadw`@ZCQ(|}E{1OW;S$yMQTv#XSNyCz=AG(thyX4>i8CEo+PR`bawhA70 z&^Jt%v`z$!TZ|UjMDiIq*WsJ&gaD)*LjHU7MAOv0(OPX|jsKy~*)=v~0MkmEC^ zd+rqH{wH8G??-ADBC3)~{Wgf(_=h6rtDd4X%MSgzUNx;4qbgGl;hV+c)adc*SlBM` zuf1$_fxHD*_PU@J4^@UC;zePpDhlG5K$JwDD9H`r5V4%pW2XI2(OJgAzb zN=q?O;ix^3Lc5BNWMmOitZ~2&-8IAey;#R7<1!?<2El(bE z4dTl|Q}}X8`M&^(Kz6?dbo9t^nP}VHKssYDt8lvu>u&vfiPjDaCkrHIG~8BGS0&EYI6 zC@U&77f#i46SN||c|yD}BVqtZCcN=PA{>nNboB&>hST8)qL>1qfB^D@8elkj3Ni*< z-XSPoMB~Z0o~tursYJg&Cad6b7NoOk@1c$fA(TldA$K|XPx5F?ZhWTJ*Y<@X=Uj3j z0TfM&yWiSr5Omd3s$#M1qJ=YO&YbhtzdSrR;%jJ_amVdnZribSZ&#m+@#JwJFQ_~5 z3q{55rRT0fEatz!(X{NTDBrcEg&W6VCULMFXCrrkI8ReSr`|A*%|mSykxR{q08c)m z@0sKC4+5V%@;GOI?s>}!E6RASZtspA3l=U+OVa+^Odcu*3rffMhbm=QMnj ze7_dS1DF(1YOp%K@|AD(kBpA_0~Uj+p{6Pvj~#w@H^FGZise^cdF}o8|9-T0K%0X! zqq&h+6tcB#S0a(Rbmc0WUPEP(WsuEmzW=`8TWk}Z#tf#B(BO?nT%8j2}BQR{m z?YB~j8J44}>P>ss{{2ym@i+;a($BK^PXde|kF*Rga9Yd-17So@4Sa5o%W5^8O&09; z`G5ZF2MY`BilUTHo#OR-@ySOkFDd9BIx8I#g7CNkR5TIq9v-YNF6CGukqlpY&iq}6 zj|3ti0AMk;x!n<;Kj@es3^dPg8X6pmhC({CP2d75k^Q5-k9!DPHg6>Wh)|tTQ&>`1 zK4W@iWu@Kf5O@J0KnN2=DKL~0N@X844FJm*FU-n{*XKQQwBz`@ zyA$CU{U|tP!BJmu)CY)t{;7WffRz3)R%#ZD+3qPF?C!O>J&?&xt*?IVh1b@6>6%z9 zt25aniL~2OG~x>az?eU*wYmWMSo}f2SRfRA;NIVpjEZRvkNz|Xmb~@!3kHW10OFzO z{&)5(h|+BO!<}H7sN*!ycrv~3VEdZ$R&8$CiGi}5M$if~7cIQuhT9Gv>HOaJe{$ci ze;OVbe9v2;V!&19rS0v9=FXX^(`d^JUElup_X~@w$7jJzCKL$`0)WBbT)cGAoW}Fz zY-)Ju@PT+To|V*43;?Wpy%`j}MGs?Vwu)sPW+f>Cz;H4iOPQLNuDamTn-KuXM5DnG zPG``YJsP7c85@-(={sNl_FX^vkw17+rvj^EW;c}g9pBklRww~veZ49n1(kD;b{$1V z7sE0**DI^j7(NT}p8!xZ-ugrcp)x|4GW0!to6%@e%E)xanWtQb)A{?~+{18&U^qDD z^}e>jt4bnsf|Bicd=CYqc8BGT+rObP7$sFv6-C4GEXyEZUfHy%qpbx1h@z?#13-b@ z;dT~m-rb4`$;wGdRulrNk^un1pbIYl{F^VmFniIWfzCm}Vzue)Gv_afr6Vp^$&2D^ z{*Jxy@i$5H9Ph3yo;|y%a>{gr-UJMbC{-0IsY)!FipEkQZ%|S)2yw}HM9C&BHk*QY z%xVReDX%JVn7CZUU@{uaRh3g$tytF4(YbZ&j==G*Ps1}3jm9=T{rtHXuMB#9Ca1$w zUe?guG&B+bfJYwwhp5U_AuP*u_xJzwXTQ#-v#Ty!-JKKoJni<4AKxWX`p~cbq^6XQ z@H{K$Oz$|*QCwO`7-nWu?XK;+1B1a2cPJ$mNdr|_5YsUR5IUg*Iqgk z3Ph0+U;zO^KoL4{#*&Zl1#&77AL{~ubRuCg z8I-`7H=N=a#$nb10AkK+j#7fLkw{9f5iC}N&mYVtgXw6$B7>S9kk*&Y~_@dbhf_+Ch0FLJsjcwnNgHy_jJCB%> zA)l(M90dZD0E)$;Mx)klv$v_g^7GhV|Bh>1(A4hy#8(&3SjvEHB_$7>qr z4UL9M%iMtuP}Ni0NhXz$b0@FlO_lO)oVg2QC()0IPee)4=>%C-h@x6;mgYsx(`PoB ztxg_uszT!;^mg?P^bL&k_QoRKY{Gxa0cCnB%D`(4g~dfxGiH=lPN^y@#T+O^t!-?o zZER|7+qdPFSF*9V&SU|AbU4D~YI!A_Kj&Oq3Y;oGBIPJdG;eb|X+nfffynY{x7IKL zJ7jWxNv}Wk;`l$AoW;4UAcXOCw_bhiZPyV+Aq;~lLYPtjj$s)JEgQCTIWj29JveGc z(OY!@0GL-q5s}FSl1XAlE)sD{P7Vc8Ad~>m{5j`Eck{`zq5?qUtj6BXf!gNAqVlqG zrz?^X0|OiK92O>z0p=cnbXM``cuHw3*Z!l+DdSI_SsPQ8o{k=qL7NCCipo5!(J*|p z%jUF-s;VZ_6_pj!n(AA&Z#UbluJWq$S6>VOI2}H4s2zCFYqbC{ZF-%kLP1H%D=)rm zH=EiI><`7mEM=-I%XYQytgftjYty=!wM}M&e*dA}!KhkZHl@dQaMT|b7z{v@Dfxjv zKVmPiae^)$PX*rEI5>E0*0gGdK@5XaiG+q>RViiURgutmCX>WGV=PM#BL>B1Lk5m;{6#8;J!%NdPcq zk^n64_l}PFoux%mCW};+(P;pHd@5a^{EoCS*kVBzAW5ryS7mdYZV#Zfpg+QBgh0H`<$oHLUKhr_@yP*_sa z9rjV6?&2ZZ=mE~C?0Y;Pp;W;)d$?SVhb|St5JoUG~#ls>=WzPovpcp6uf)G;AP>>OojQ47a zguc0T`@}T*fj=>tmHd)%xUv3y#%pBN9W;Xix)q1|6gyt^J_Y-;SayN_m=Cg z+p%ZQ&bK$N{KC~5gQa@re1<_ft*+GLIl8}&#`#o{ zd0u|IWVB^lVa5x4;1%@~78J^YDz!k|u zgG2d65%eCbna@J}#}MI9NQd6f5M5QWDmttAcFgDd`MnR?3M`moYU}FfEnZgSDH!ql z21f?_26{r#1{n#RL%j_%<_!gc65;(3|KMP+oQe`AqA989?CPnU)(8NyqB;v~cir{l zv?z%=m790oeqG4Muejz$3vbCP$``M>%4{^gy{moSj$I5^I04UFyriH05m-3 zb~-P+<{BO$StVPy?}!c!d?X__qqchCIV)yNYv6fJB%Rr_Z};}y#{<1RY9>L5BFki= z7wN+kREl@7@71RV^ft?y&s|`kC9e?Qofm-}uHii=2fb!aFx^(`ogOJ^93szxUmT9)I$x&tI;n zlwdBEi4XLTNh;w5j(|Em)BylGy#Zl17>S0W(P$(vZ)Vf3J#A*A2>?{Ry0+!-;Y6%T zUz1FW7Ogp+NIn0`n_v6#%{^URstWIQz6-`;_x|Az=Pg~BiH&*3hDA}q4CgLz##3TE znMowXxeF@`itO8acZv$+*=&A^rX-nC$|6936&pb74O4V3cg-jwCi0o|L(c3l1h=HR= z2O1luhf>P@5BYwgudi|0^5!{95AAz5*wdjmXhE6(!lMt{&1~Pv7#wew|?!L005YszhD93^y{DayGF~N5>ivy9GsmyBAV1`Va2Sf(F!spR3!`o zMW&p1RfX=41Sgg@#M98TMr?VLV=9Z1&0s!x9 z6OVQs27oKC{Cs;?N88>542z}Q44TL(>#+!;q44uBy_O&GL^2D|Hx5Oz8ez~I^3>H% znX?$=bVkgGlB`Hnr-(^WRuzS)6jKE$getO36jdcG%OjRW7-?CC@GRmr3<5omk%o6# ztjCXb%2{P-C^R$#0Kny>x%V8M=rQDSW@_4;3amW4g>Dbla3D#Fq5?q9E9kQj|FLKC+;~z(xYJyntI+9rTNez4Q=vhxpd_Ph=PquVQ8%xqygHtYMv`%=5~I;* zGFobH843Wu&X;f&cl% zRo7kXEUmEV^b6-S#DfFsj3)>#^$Y*S(fEB2CLb;(&6gv zJVpSfmX&_}_G@HSVK8GeyAB-Kw{g?vi{{knd22!n06;tt0)PT{@nerZaosgnloS^X zXW~-!-wuMu+V>u7ZI`K{Qi=%$0xAHeK-FtvuPr@=b?V*$6-0{|GE`JF7Z+kf?oA2^)_fq*ZPOt0JUcJty@ zS&7bFw9KqC_xq!9NxAX*FaGtZrvj1Kv0Yo1E~p#p>3jRFcgl*LS6^{iDjRFxw|zWG zR1`&4)skWdW;n#Mm@}yIsn65+Iv&GAA5kd|goA^_LoCm6EE@=f3Z3@ZbC>KL z9@Xm%48!U5reHXu*A?`2?J2LFIeS{gKi0moe9cG3d`f|Gd$W(Ll$+v-z%u=j{%cMyo-r z=7pD@yX?}HPdxJERo7pA|1W;~t^fM|NZ$uZ;Np+1fbJZeh`j1q2%l6{x@<0;(O@0y zIyR?y_UBeE$H2ew=BwLw?HS)8o=BREC(TCTSQ1nK1bIvG6XQDon63IB|DSI=3Y@{Q z{^$SovdQHX#T3UdL{twQot%j)rxdMy?7`^h=&WhQV?(1I8~7C$T}T9rn2Jo9J!f`Z zZOe|GE~jbL%EbeNgDaM-7Ae`Yd-MFp8PUPc1IPN!CexY=Rs@5Ct*v{e*Vjo{pul(> zZUhjFC)$s6D1hI7>BWoY)M3mN=#4UElQD1m_MNxf`Hfp|zQ$>HIc>H+`ONX%YBRar z7DQ+?kqrcMN*Gvnn)Lu+$#r!oQqE&JXFbj4sx3A5)>9@gZ$jCuRt4ustN=7x=G$yn4XwM;mfu>mvkeklm%dHt#)$oVIzxv%Hg>E|l2u8ip zZsizkb(;LKbVjC5tMQ7uvLd5pd5*P}m9QA*ENt%U9ZdvB#(|5;R-;L8XpAr*jPo!Gfm8dW(5Z_# zlNT}hN8Z)wJ;u#~ig^HmFr0p(jcD%5g^rSveS7u{9_`MZhWLwne~U422&gIStYv1^HOG9>=MTP7XmiZ|{tu4q-*PY+QDv1PMNyU3LxTVi35T-D zupnqwUwQ$j*C3i^k(kb8C9JDkxMbJ9_U)UtPpzrVh_Wb3N}eT^gQP@)bwF;p>4v2% z&PgT$;ozviYZWQoJJk8s#@z=G3^z45oU>vVN`X~};^}IKePi3cmtJW(XK`~=({zrN>t-|| zj-^!4>)1CoYLE7`1MF~`j2z&Yow@JucD4h=IJ z?RbIynV9e=woTAZ(8*55CYuHT;<3oQ+1CL8V$R%R?l4>K{jYE8?H>P_HN(dmlbNA8tvk?Gf2{-6ZY;A4zkA$SGJUBGEW$PvY&=*$%NCFF(K_vxF zMVcmMlJS`B*qDFYJDW)+wPf*9tF@q{u~ehemsZtm+_886wl_I7oep}PHs=@b{2oz7 zRh0o_MIkK9FbpF}>W*EzyZ5#Y_I3e4U&mg^WZK*I_8vXFWc5Xx-`b@l1E;33pmMBm z{$&@=nSbt~j?s0`J(`L3{(rnf&ph?iH@@{jC<;8{_TlakMch4S0`Oq7~PD&vyT)oI#RNUP$bki+&+;`8< z@~g^+_aD`n4TtvcH5g4}qXVsNJ;Ou2p>XIw`Q2bB_Pam+bw*8<%kAmw_Qs(F5Gt*z z8jGfkg#`sVy|cV*U}SWBzBJoQx3}ybi2y*x_fAV?eWS=|6rx0l2B@>~GER`2(Y`9zE@nJ+CUa+YrCnxSI4%)H z90sjb%VlGbGCMNq1OSX4@9NhKOerm!Qr&UU1q&;xrdq9Ty>`M_m^avOD{pi-Z4dtW ziBrx{mXohP_v)>;|5!nCBp#zwVK6eAtY(er>3{s~q$-?YJ`3@m2v9@Ggz3l0`UHtc z+Gy3;ovuwSTP#Mts;Yv)XYh_0i$#C``zHztOaLGVJYckA%NrqoaQCk57PB)OCz<5n z$nk9nNnFRrqWC8$njZ>!AHEiFyZD_FXSkGY3-ZloSN^a?tfXu3xVo((+ zbI3<2#uykt$6I$&2Ht-0nbSG+fv2SCva7E%Sc@Ki?)9$L7M7&o|7%e>GBEi1>#tn# zh3gpxFJH81=ca8j|KOP?hQIs?F&MKfk%_DjMNv2mp?)Or?3otfKlY2IC-4-927L|7 z&Mhjb81wl~WDWiL*S`ROluWat%pjBzWdvZeX!JV$e*_kF4R`m9Fbq}|^47*SM#E|a zPA>@8-F|D+yoK-VY+ZHHWyiaF_Z>Z$2?S%&NHmr~0KD&r<@o5bOFy^&(1Ep&JhAGM z&)xK;Tl;#3?OI1wO_e06``VA~-oB3jl`xK^vcI_R&pMr^an5X6R1nJmViO5)IvlGO z&%+3mYz8PqB3`T2J?!lQ0If!7KXmBWp$>+@3+K%TfK*20w5PstF01MCE3Xm749F7$ zrHE2C8K^Fsv2fmHS6*^wHW@w8wle`x;xflZMq(o)y#fDe$H8UR0f5aYZxc1fWEF>CWEDUX5&jP(*%LuGJ&m;vvC{$EX4nZ8v;rh0*ERq zODQNSn{Tes7&Wp&ykp)kTzM@3V9cMc`6*XOVg>+QX6v_ZyVg=t6df9&I@5EnzNFV_ zSWjUz77hD*wLH)8;BvZ(^g1ys_Vx8laT#?=NQb~gS;!v^tD-mxJ+Rp7}bh0~Ae34fXO+5~Vz>Z`6E9qfN&n?l~pNbfMA3zCPB>eDRTvRGA$zj z0!ZZ$VldI*ae?Rl!Nd!WuQQtRj_ifO?09-&p@shs{`1Q~LVTYkzv*&p3`% zvl&&+0A@@Ei(YG7-?HWT-~5)U>Wfc2^b$q_0}_FZh#q|Gkstl^SE`(jr_+ex#@p*` z29w!nZ{6L3kfvvNc=3Yz*8TgElEQPC0wBx`_(Y?SjYR<*Wd{8q$IwhR0RR-MfH;9+ zJtZEkPDe3=DWM4b!y_~5>N!qBDab^mVwy;j#$+-ZEC8U<7*e58DIEn6vl;Q=Xh^0Y zE7I^tfTTp1jt79Op3_)u$!H|+{Sc5804PT^CDTMWktB*g;LSZzIv{C*WieIM$QTd6 zGpv+N0b)VUj17*(7>xh@i@U$@ z`Kuu(d!@nf!gEgtq|Zo`AOAM~KB<%ffONXb(CV?h_}a5N4t@2OZ^IcZK_C!`Jo)15 zI)UdoMgp~_e#Rx2U8ew(6;r)K!}Zlw>$dK!EVR#?-Q3bUZ_S!sT2fT=^fS-A+q&nMKmOk6Xy2~3jg{4RjsK!I5OUgV zfl#QXyy{@bklkU_7#(V2v!z!-m!I4BG~n*swB6(`NkzzU1Kzu zmd%@;5Ah!~e-p49v@6fMVEtRK3K~3rVY9(l0RMRA%wI$R06dS29eM!pCr(;evpNi! z_(c9?x99-CY|;mVv1z3R{!k3Rf1|wJGLe(|V$zAIVB`FzHP_zM)7LFepYp`x4fQht;J|@HhmLjpC&PI27q1=vqjm4j+8Gr?BVL60q3%&B61eSa zw;4^=zP{cCs}^tEyuQT5SGmp6(OyYLTy_1PuAU5INO8#SbpH1}KW8!X*ZY6-<=gJC z+8jwy+PrSjeoLd%+HBrAv*%?q6I0j5P20MT9T9YzU;gs9L*5YpV3DD;#J%?UC--gH ztjHo}S%t`oC$7oC{nGnvd_Z$~T<2do1CBxRBc4frDfpi%{Z2LO%L1^@<&Rkj(7 zf{@8(Vb~7<{S>*AS${S$6qmCqFOsYDb2OeVWF z6-Y3QFC3C(YPZ=!;c!+IyZgG+{!sJzb2(nO{Ms0rhQ$AUKn=|&i!?W>n(g*jXaez!jE2AV!*3#nL1&@gZ!;Kf{Mc54n<4Kf7V& zn(NlSvU&fm%{)yLLYPkzv1|Xnwo9(MCXtK-fTwQW=;7UGSWCym?KZY-ea^^==Pq8h zYiDakq4w-n;U@yU+hOzu6SZa5BLgRp6cGggSAogzn{bbb#Zwlu)*p%iK&9K->y6k= z+R>A3z8w}_;son${)FzZ1H0P2;V=Rkji1DRdGLWh2^>!ml4QBR_h9q93lg!Y*`yuv zjzuH!4>yK2)t>XtTka|-j)g{w>@a`nnoPp)D4Nzg)O)O_=iObcU55_eeCOATi%Xt+ z`1d7?=L3Kc>tz)JP#+2RnTl&`8tbEhsLvaC_nnr;<|VJZy#C9#+#;*u;w3BI+_3J6 z$Dd{a4@F|P-*U&_{`vp_s49(w;!cb8+N-aoKme#HOIT4__a46J;%fjA7I+Fkfjsy8 zKU+4vsS=6+u^72L9-iYZ24ggtc;xT*-+J>`03Z~PzxeWVmt3;O>+N0l>_1XT(cyFt zj0|^ljZqe2q1e=h=?i8}HvllHY#^5Qd&4fbtx&H60H@0W09m_16G{$@1*u9jykK(J zv>b|!g?w4rt;eI`FzpXXp^;<##{nSe?RQL>Nhrb$bHTEe0F+@6rYMz8 zeiq_Cp-s+6fHCD%BB_*9LBg?c1P~^o3;-q7C67M-piaZw`IYZ5obG+ffQc=fh&{9J zEuBs%aM?$E0kgw;?U(OtAb3yP9!^r?@g%6UYD(S4&2LPd-ZU6X4fJ#l^!BP!mgk0y zX46=Pn?7@XD11y&RY70{oy8YOZVes=fRrdEv(l^Y>;?c0Z{!#@m}f{GOJaeE-g*btFOz!0ZKc7p=PNnYHVN5523Q5&*)O z$zvXpq`=A0hLAJ4rOK%iH!_(Z(&XFsP!2`O3wfgaB0x?IXi{1-e_}bXBAJ}XqkB4! z&uW@a5lov=cX-!!G$|nrdG-ZWC+pv7O>?F+O|=LGa~45d8r5Q}^q1#YjVAwFIRE`z z_|<3y!m%2yAd7M+C375(B~+_H6O3kcdJX`@w3HFmR8q`{s>3D3V`%`$ii+8)k3~|^ zj3Oy?ES%2wsgL_)h2tV-kd|d+N?C$9%&-KdGijD#o0l|S^2IOvBNVr@o(u3 zrmW1!fckrmTkLkPKf0%FcgLZ9LxY2=JfTcMa-Gj=ju(_qQ&>%I#W?rLI6uhijXd?w zryJ_)95%Z*lfW92cJ}v{7JFI_92xFC3>3ui79+sNx(}(qa2yj2jDGE= z8x$2$KxEvF5s~gA2gXk^mbu0{z`u!O-o18cfBNG59DzD`Ad}JgpCKF{0TUKNT0Ef-2ciN7O1_eg# zYds1l=pOSt2LKf%1+qp?$z)l%JD&Srgb+sH27QsyNZc0*3miJ~z@r#2%b@bI(j)!% zZ+mAaWwn$-L({Bd9UZT(d+F9Mf3+3%N0ERnr0%*`_RxO=vFDMn|RGo@n zdTaeNk3OK}+BZ_N3;^8#vMBd=9=hc68)nX08cW6qkqD>;jlp6tZf|W1jvQtMEUPMu z$lN*2-u{k2$Txe*lDwdpXUZ(V$m4VaKx6Gpj36tMj_zLH@bL>SzDANk^KU|YRHX*1 zxoQ5YhyJ!UHgpJ6_0!pu0RUZHolUbAAOvOQWeBs(2MRec1OtFs;~bCYCf<`sMhsR{ zJeGzJ6#J#QX{>u71OPmD8VD~KP6NPre4ohWBPjszhTb>7jz-0tO9)cO7cLkC2p#L{ zW;Sg;w6(?Vai6&VH@|Zi0Ay0>P&CCdkQNoJQm55`{{tpQG@jhNY4_$$y8(b@**`zF z&SKOV3_700Wz`i#Oh+R=0Eoq76yaxI+yFES83{1(n@3_fs}N5*1Xkh*7BMZfK9{r zbB(>Os-m~wJ#4X>`}$Ac579T|E4Jvp7<(mJdBWXRC6VJ93NSJj1_0hL5d@C(`dyaE zgb#zzP~TMKDJyh){L#_TXt>GcwAux$y&;PHfka}QhX3+wul99!1bop;SFObKQ~Hkm z?*wWlRO3%~b&dkZUmp3r%VN6i)^8zv1}2*wO%coyrBN(iA0qthD$fe2OA>awyxI2n%m0Kn#Q z_YU+F6cz)3+ivxSA~uUL5%bTiuXR{8+go;EB|<>O_}@^8AsFJ(#6!Qimr#WT6%Zw# z))*i1`&a-#sI0)Dw_22FFsC`&)O~e zKq7+>a$5Bt?RZ*@IshPIh9?{V#0j(M_4V0Id~9I&jyt~<3kUr{pCo00B8}cuRZr?vX$Jrl_J~Zd0SXpu}BJptTKYO-7nd6;*hqmRH9UBplD! zjK15%|AL;GiAo=mCNjI_jrh}X==QD&ERH$%3A~V%WB`a}mGMTFX;Uj&j}KX_W?wLR_9J66=oo=Zi897WC8y$^C&qUG;55R< zt#3vniK*37`g)HZZ*6b>-d&tvrBw3RlaD?0SW@C|zqziWtc*b{P@>an*-xdb-~Uda zhF}7KI0T4D90D=dK{H^39BTlS#}?2j@W(iTK>*rNQ*13P6QxvzqQ13d zi;9p+Nv*E{yW zZ|@BSNBba2h>}sr-=BGA#nJ_%nW)EI($Tr4=-h>STVFy{rIex^){#$*@|mbQnJwjY zbSVJ>ps4D5pprbQLzIP0o}KNZ`A;M{ufUb>21KX)ktdT(s_^I2XM*1kpF!`jWXdZc z4-5?hg8_hHScA}mctfTA*GXIAPj@6Dk{1U_naUOGx2qo$1Mn2 z- z+Q&NEuDkl0b}B#k;FD#gp09rCrUQp|w(UM#GNqo^8QKpYm{L)4-Q{cc9NOQ}+s9xg ztE%<0n!fYx@5hp;zxvfZG&3 z%Cc&;o8!?0CCL@}deQ^Oe4L0@ES zs9#@DniVs9_U;9MU?RCHho7M(vGXy3=Al zgLH|k;I09`J`~3+GwkQ(jBDrN4%xffhJ{=RMfn5_pg=cq>0C$|M)AdS(i>_ z6bi9;Xnyl5DVyEC`y!-m%C6~t|BNf%N-rD#& z0IXfVCE**x2p`zn8ufLaziin%n_FIfZezprs%tM?)v~i?up6e-&qN4$hx<3a^4eYB z|E|aF9QFACfY%w!wvtF_V05uu~Mppv@;DL?x5pj0&i%tQY_aii_G?+Y;f- zcsi2>U}XXT7%*iR0OCvS1M6Kf04w_7f8$1gN~#P1I*zf}4XFUD!uy6%DJ#cf zA-&6ma@e{^WWPUvF+Qc_*XaztK*Se_m`o;}-3fp(VS%ATLm>bdkMAG6_4l0`M}`9v zk|~i`)@nYrg-6Q@0HC*+0ASwgbLY-%^tjwEr)kHw?V~xbtD>q}mK7qQ5yY^ucqkeR z?rqyT(A)o?OyAK|`kj^ym8DfilL-KVfnf%rR5s&u75wX8FMRQa8w^%w_rNFsq%v8X z%|i%HCbIybQYI^Av;fgm^6{r%yX^9dzxl%-gd>SaEMqnr0HD8j=$`-nk(f#AExNdv ze&DYUL<5n^nT=Y5L1SR1*UT6{0i(`7y>`YMZ@j!<(ei!mJMAX3)vSH?Ur$b{nKgIe z;_(n4Ol1)uyI#<1^%q}wsoUF|XP^-&xY;eTkvIPBSh0=smnN&LK(P;ocRI*e)tFbODuDtQKFRH*6I-L9ExWk~? zv2Fbup^%Q}j_4T{Ha-tdBXCeOMh2jYT1e9So3~DSP zaY{}|L|_5HZZrMv*FW{R?YDpRyYL=k5Hu-cLIFS~BrYm2<^_P>y=@EyRUs4s#uzc6 zs8prEGMM4mHD9>SZngtvR0>?ipA{SoMnHk6%0JisGZP#|gi={vzWlu5fwJ0(jAkO1 z6%`f&rW!#=rn2d*Y%yr#@i;>4gAf1pmg{fYXwysn0h$*E&e>S=Ik8hElk1Mr=0sF- z-7#|Ra+pc*BnPMDwPgSyK!i|=C%&bsr)sdUIYdGhB>+U|q%(y^H_=;=$;yaOmLQeM zQ$9%kCr&|ia1O&^FlHGR0Rl=n&Y*}Y;&WG#dpL0}d{e;tcJC2Z&W$Kig4dU+nS_G( z?b#0uAoV2pA{6i!7Z!wr-gR%jk@Ss##|8j8g8%?li!PoE@j~vkM7eU#kh6C3`4YBq z(W~6RJ9A;3=6FFON1YZ^AR0$9MgRz5F_Ktu*=j0DWT?Al&UwRoTkg2ywtIf?6951) zdDl0-Vt3dN9-NSg7jwq5`SFo*T&BE}IOLMhy!H+fa~eJb0HD9ecmMs5PuvTG0PrRN zOrKVhiNsUhz{9`%`A}4>nK55qT>lRpsD>v&O-?|<+?XHj9L2fzHnKlg9h z*1NCOU^Hi?Ogs{`7I^OY*$)?=yIK^bP$X742XP3w9d-aHsjTiE>{3+GAMn*wO--cJ z7L(BziX(z}7WW=Ma@}`-PJyCqV#l7=y5@Obz3W@fq9Tstetyq?2^u~nWjAcuAc=A; zBHjAMtAJtih#zH`NFw#u#~#f@)7RW|C1o%{Dgdw?D`*UH!Vs3xX?4J}Sy5v3Jg^u5 z*jz7OzLTBJp>Tx503ZOC2oY5k07QwX6S`qJXR$ohEB^-}05Ce(ecwHIkAKoQXYu0Y z^Lu)SO)LXePdX)0K#H19X3|@C?6%s?3(uSDuo(oF;m$%6<+Bj~ku0`OfW8W00Wkn4 z<#)rw-XHz&o|7Jm4>+2f1ps@2Ta?llG+eS_%ZBBvFOpQ)*0Qa+zOn7#p{nv?062X7 zctJr`_p!FhLaWtedu{6>msLNfsp)7>=d@|FodwhS!(Nub46o@pdaTN0^u{u~_p~CQ zvzlfBz^;~U3szj>_4(W1Tt9EYya9mPsda}BAHDtNTf6#4#Xv$}u&DmqWne6x;`uYP zhFAu(3>Hgf7Ji-b1wj5E?Bf$kcuX*E)q?j4S(gmXj~wiaoSED&p>nn zU>RqTDhLT$eP>U{%tC8;WY6B?2bWaW=XV|)92^`R9Ph&%3&#~ncA2yv;lm#YB>|Ar zt`8pT$$wa45jY~%)isU(XFNH9J{39L0MIaVR&QUo=gQCR-@kwUoW^iMc3JdRhm8<& zq~rMFxibNvw{LJpO?6SBb7U+qIOLB%a7+?yh4jp5V%2miI@(<167AnHH#$NvjP;&X$CZSyY(wNXVuohWy)V#*_fZ@fx#< zw>km9&iMd!z((Ty*x1zuUve7ni$dOS^3 zMc(+rn}~+r8ahfTY-HJ6?)(PJpqfh0`PW|g_H$1GoCaHHYMOPyC07svG60$2w-ZV! zQB^_-r9c5FRS5tFhRCu%66+fr+V}2`RM2`v3U8S z^H;Bt3A*nO4@8De@<02|cfVU!Il~){{_ftN#eCkgzhA0Cw`^|%09D3=$Br-*tLXi) zc!Uld>-3ag@aC(nds_G2dfT;|x3-;jPqWLu^qfVL*GLgQc}6#xbtm#8Ee3rwc@pw& zHJ;itk#7a?MKcAKiO^hVHII#JL*~jp%yIw_8tvTs*0J8>Jx%AH3iOwj6(S^^n8klo zo6|l~jQCS&mwxj6W8SgDhuc>yJFj=ln+Qg0>t?+6#!FLc8&pc~{p|x+U3q!^^qRTN zhgrfI9j2FGdTrTxs{;PvO1pX0(hHw_VeOWeUO8yCy!iU-J>C0W+O$n;c3JfX0C@6W zFAQ{b40I1&xOzFEh+!ZpX3E@Vk5R#TgVv-O85v&t;tOt@b81cH%P&18XtZfbJ$S4W z0J=JkSCkfks+{nyq4O_TX)P-7`opvTAA9c|9#?g(53jxVIcItwje3_X$(Cig7i?^7 zaKS(*p$0;L^!!2+Zn()Uxg_K!`EoDGO+pBS65>Dzy&5p?y<4_qOR{>GruTB{-rpai z85>iRJmI;|eK`N9%*>gy&)IwJwchovcg>ym40;+s1^_+BRace_O!@_k5Cz{@pt!&m z9Ls!M6Mx=g7xd(Bk!C_#T}AbH?My|cS~65nS?BZ=a~LTK1%N=yRIQ47hkIGc-9hv$}dJ7`B)Uu95<(DQPh=J~PaNBy2dOv;`wpFKm|6Gy^DhFMgE60FHj0yjKmY(B z07*naRI0$jv7`=3cDs=PRn<(L-E+7rWwTjgu|&S&DKAB*?>t9}aab##pQR#v?3rt2m zUb+G?N<|qF{HclmM219xP?EI>^gXD7-YES3k>3=#9AEtMw?Fb!g2m=6EVVoA(MYuI z*ddeCy=C`~+R7>bXqYkkbl*U!$4MDT8K&1;wjJ&Y2Dgc#ln@n?NI&$)Kc_|Ui(mbQ z-D-#$3<}ktmy^tCXPJV<^)A@QEssY^P%5fm|@o;L|JKwzjbuE)` zIO_8$9PyFh>deicqW`TZ0)0jV*#r(;cWUtm9n9Xx=S&Y+YW%aR%4{YcMc6$r^v~d^ z_(3dhuN|8YJrWxx@}oo;L?w`4(cyZ->u?O+dw2w)tnS&QkEKc}Ohp%BGk$H$>34Oy zm0aSYhe5N8rV`UF#AQ&{WWVbD1x8fp&xHI+SgUOi=Lf{pkVd{2Ix<1_I(y~-`} zLIQYW0fT#=KT3g?q;(W8t+eRIrv}Utq=xq{F5I-XhxEI9G=pK+-e_xVk_ta8yO%@qKH-cQY}(U z8H;R!(dVBEa+fVlteU%5VSRnF%pF# z<3K=qm@6O4NsWf0tA5Rr4IDtY^QD3fh<<@uaai{#e&h0qZZv@Xee6~Wa1p5?!wwxM zXjvHRUnz0%vtwdmG;aor=bL<|@o0|1CvA>dx@DfM_gG>V66iE#km~u->O#t%q``=ISnbN!v z>^paE4)F#L-3--JW)<6TYi4#cJN0ti%&rngH1+&80`ED>rW-FV17#U?noPl!&tS+D zhT>hEqR>>A&&~;FYj>mRSSxppe4C#CVgJ!(J4Z(3OQ5J$VC&n9DIr|%)e>^RPD7cy z0!`~$-y?F;2x0Wd?7d6%)7124|D(9`;oI@-EICy0?7Ml=jGh=S`7qmPW~mBt0B9RD z2cSyO0;Jue5ldns4K6=9Nu?Gr|2_p#F>oG26H-Bhbo=T|eXQ#ChA@W%eETiExfL1H zHHC5z0S6&g9QJxEuGfGH3j&N0l4-NaNC{REdqNZu*ZN3RVSvUBt}tVzcX-I zbMZ!JNe>x7{5~ewqy|ma?fA5-Zp+BTNIQmO3X7}0*5E$7R>yZi)9m}ONla3FBQCP@ zYq7g@b#LI(_v5>RtNBh#UQb7P@swRFvrvMR)y0mf_tqvo1zEO2n){STAOOs3v613) zC(dEW(3GhCtbjNSr{A{?Ee`{+Xno7@pbtMj?DnYg8^oq_))hkuP5Q3hK#`z~CORjU zSs^!TY#^Cv9lAH%$dWcoO#C2Dh-Io?L5Dgkr!XRmC@+dG9BrJb7)-)oEk-6cwCN!O z!p=mjwkS%N91I}%)8Wkt6gz9hCl3V;N0Tc@eY(VPCI|p}BPn& z{=NKmeOY^}??Mo5!O!QTk0Eypuf%L^vQ9GbxD_fqtxj)F!0~o!&6}an=Z$}hqa#N$ zj<_TO=guq1K7O|8=YvkN}vLd$=yC*merQ*QBMdDz6`p+7L~MSigNMsQ8E*T z2f)eDm_}=VgH00NMvW?FF_9QZR}z__6Uulmu^64gcjzsu+B2(=6%^o6*I6=~yGmIy zCllS1Z#qPZQxF>sht9Q(hIm{2@j*Uc6JKXO3qqYuKz3g9rguF(yqLdvj&p9+>R(x# z+hJr#!Dz6MDC+4xiDT-E4bW@xE8SE(a`TLuz(dFmWu*G!c`K!D{jIe>>9C-&arnTI zmn^}`NX3CJN`ewcon5}eZ;z#HG8U*aQ0Xcoeh&9tYkPlx#?m>$ck)#rISwv&p1Z4Kyl>?K_!Y;z?@ywxtW(qnz9<5)O{flV&T-X=%&f zt@K?Xr}YFdO9Xxu8p$2Ruj?%A=y-Df{F;^-tq+O{Ja2;9uoQf+RubIalzTJ*Ktyt8 zNex4)k=+rvP!?^+PzA*sm2f~Er;dh69%bz?t6LQ#9z~ENBjYv~5ddG$`i<(KwnGdF zZf~xlTEl% zdkh^4UYnio&a>ODpyw8|Rx||68W^xUON16G_ibfGRt&^%?bLe}N&iruMf;L_=HFDr zfDho@mHK+Om5wBjsGFdrnPB3nE%2AO5Qt1Vm8;^C%8U?AOrT6>F%XxFQi%6^+(|#wz$7kVs+S z$l#84ljXi4zwckGKvcu#GnL$M*R&eX<~PuoDF6mh&zf&JZvQU-LTuP`{{wG(A_@;? zO^z!QQ<5Cs67iJ1Qe7k2PRpNR7FVV4ahVrRfpFE<>Db|AodKx-HkqYvpEw(reR4uf zaP*%wplivRNr~F_0$0Gth*g8m^mH8gy4wE zEwMopl+m!5XHptU{cKnxnA3s=)J&vkML_Y5{)LLnj*_|uy;?sHs;S>W+^dpYOI{HC0qOhP{P3lL%S z*=Sq7pq91F!1La7)2RFI#;{(SfpiG|sQ;%U392h^_Q<(Nt|)N1apB`V6m|;QMYU3) zv|+`!V4qfLDP5hOzR5h))YQBi8B;-_0-!~W0aSKwM7>y;c`OLVTKa7lE4IwP@Np2V z@(adt)bhrV07MUsb8Gk^7jr@-XNJw`X|LmH%Zhu6>YVXO*o~odEb~Mf=s(w&q4ifL=TluC;fr(^355ksSQ9 z2hgcl3=EZi&2K7Am>)vT9f^IQ9=Nu!9wNzwQjT@S!1~6_<-o_PXsg0N0=&*q8S#7cVHo zZiwzB^#APLNW!jZSHonTUMgY5rpG)WW6i=J zn#fFBrtmQ;3G7ZcuTB;K)Y}sOyBp)sYZD%+r~{J_IUX?aw`f-I zsyra&IV`i&mXlOW;;om;?*;$oBUpA^ek*$MLjkZE^ezv65OMQd#dx1Lct^pYRN*ZE zY%wbG%%`qMpoQOces@(?MnM*8jAa{17fGRPl`K(gUbU=hjJpXe7lZrT-L%DGEUdV4 zfRF*JCC?9hOlyJo2}HQB#b{z^WC1X_=mev(E7cqs^kqD}aB!Uty-&{v%i__FggKVE zo=5J`hFa4u_lp^Nnfg%BlNwXbT-}u!q416_$DWy~agYNjQ$a!M<@0Ub~gE>pq8Ry}NGdk^QRjr(6qf%a_!qMx6NI*htLg z@%y{4AZ2y{Xrt4#Di9qtJ}eV9*w|#YwI-!RJgC2=nXT5K#~@MV>M~+TV>Dn~MMx&Z zBdP0`dZ*w1$>rZwmq2G5yYC=WbX72x3)~!#ss|BTTruMb$r}vaBjt1WLFdzsV z+zbzkzx!HznHniVq_1O#2Gr%*#u5?6a)26m%~+YoasL91k zyPiK8t<-T)g9N&A4MCQETsWU;b$GtOO5Eu6x4uhP+GsRIqPiKK;^Udai@p>vLZ2yYJj6 zRWa2Sl(8v%ae$r24xjOS(1Ao&Ip4ZhR>Q-NCDWS6!{fiH0%$e4y(Nk2S25|Zwe^EPqBqV}J{H`}8!G=Cw?ku_ zwnvMPMrEL37zhECy5{{;TPU#OE_3&=v+}9$tR6LH!AjFmAnzW*WM}HRy{$~e1sreB z;>(&T1?DtWRXMo1)p?z*ojkv-bBYU+B#jpMb4g{Y|64)T>)v5W85-}GVgXF-u5BM) zla}ln)({k2T4u{_A0tkcz`65>5>36@mD4qaY$871=ns@grMzmZ#OnlytW3O*oqx>cS>Z)d7W=;p%$li-M;J}Hgm~L6Bz@ey&Vs0p?s!5P)^?KFpAxnNUFM>G z^u3nUwc8y)z2tX1=@H;Y#(?eA#ek4B42&>UnJ56RfC5n2{>oAcykCMJP~hh-+x>q1 zkvt?**>2^un2^F)X-n|DlORx>#0=o@FBw=hcyDcBMAMpximK8RNJ;F$0It&{7UTm) z&;hGW7XSYAAtrQ(WL&ADf5eUL(!c;eromw$^x+{G%ufv-7RS35WlONcrdN+X?`c~e zYiDk$Jctb9p)oN{oCe+ts|CVwlUL8W4qLYwbX%L?LKn>~jEIq*0Wo?OElpJeLj%%M ziXTf~B0co?QQ{^p+_;jyGC{N-r>@m#P*J8cOHrXy#h&Xn|0PXY9R-x-@$rb)Ze}bL zRDthq*$^NOT=@H()gqOY$paMJJqQpfu6P9vD<}I*X6d~1(?KoqC=S;qvtwh?+tff0 ztiaqn&zfDm60Ehfz>=R_ir7>F8JxSNypL~%8sVmMnw>d;+tR zwA$R=C8_Rpp=5`sXsz>D9!FIfc;6}Ri3UfMMcWWd>AZ}km4E`Y)P|E+|JADM6SAI} z?YxFscKy-Un7sELOREFT<}E!RTITJ{w$OSCHUc7(D>Y6S$zMimyN~~j`CZlHU<*Ep zi>2Qaf4usJubtnG(3o3G4}qiPv8a$*;x2EUvZ9fX344;2GL!#3VC{rh(lWjmT^}Y5 ztLfE{il}2(>2mT&crH@EzRDz5p9CBH^8M&~aJ#+Vc>CuKwsAQC{r5TE4n0q@K)hVI zR;CStbC>+iwiVknm3O#A=Pc+~L_ZYpW9&Vw;Wy^^XRt8`de`Mor#Ejw+kypMD=!jB zN%YLM7I_fP0rW3!1Uj9==)Ol4YMPFzL+VPkQk1SL>w6O-HuVzNEPc5$_;45l$F2>) zQQ-*R|Ie4d=%6bAUWtXs^%$YZSkTBvfhLp`sLw!t+jt8Noyk1$3Tt*&_}wM?2ySz_ zj;h=8gtKgXgzOa}RTi|JF;x^aWnE+JyEQ4=ELAdb)TG0!q@m$mYwP+GZN?ld&)76B z$2D+B$b2eS*zoIwR+SW@Xl{|q*3(v8Gs{JaUlJiI ztwWeAt;UV+4K4|Q;L!uDFtkDtXlGii8H{ZT}JLYd74vwO6#r96L z)>as0hMYi!ni7JMLoaUOifG1(r zx|FkpRB~yZKwU_79kx=jSc5ot61xOQMiX(hApw!?#5>!GNgId&+Q@%vt*{~xv3u$= z3avRQ$*j@V#)c$deh_IAG&Kwf4tliOL`41`2o@YPSDRG#_fqi`pp0GYN05O z24mB@x}ICej?IKUqQ;jIAvS*{#`gu0hoRJn{u^_bcbGz$Z<$L7BJ?gS8PyMKMW@vu z*(wMC5#OXn`!oCZ(YfXC4eoVpA|5&d)?vl1Hrn&9?bYzo+^fq`YX|PB< zlM!jT*cUgK&~kC%ot(A=9x4&Y*tj?vjtciHOJk#B@oxY2kH7s$s{^(j`c7k;dMwK% z!bZa=nGBkGD@uC1iWE`RfXinpSV<}i_E{d+@;4@?Zg}wZ6Dm`NJ5X?mncnvDC~20E z&!zZh3VtE@){4My4i^i?Fi~_ZsH^LGyk0s1mpzgd<5X27P(X+}wA_{Sp%%PeEWYVX zszAgXPgYNJC1s1}R=}Cy2Dc1m%83i$`2A?VG)!CZ{i$W+CC+3o)Ch5>4BH~13<*fw zNhh74G=Kv#Nryb~{BZcm3fYMJ(P&>a=o5c%es@^m!F)$Yeu|F&G0>CN&a+K zJ|HYeRfPI{f5u_4GaQbIM+MU7fR54jxEb*^8$OP4!x!V(awc{MgFcAf2_5 zf4ssv6JkV5=$F&UQKP!%SIC;_rqwvnb5sQfJML!N%fBVtIu3;O!`hBmzXO}F z`dHD*2@QwGDaSDwaL<)<#_9L zmg(cP&yNTm=A-WgOs7Eq-1j(zSmS&ko+z!Zp`&x~=dAU`|B@fj>a?mb0(G3({}{1h z!;>f*z2)O&6 zFB6#7d z@Gj!j!A#l+nW)zmhYfwJzljMI@3pOF^vZgAb1b@z>TC*77bo0rxZup88Z4O{E_HN5 z_D7I&2ca1~hH8bGPDy|orW{XBF*SgySjL(df;t%Rw0=){FmF!{hpjPXB_or}f|H35 z_6EgQ7{$@UX{7Fb#l)2C(>7}F6k?Jgs=I}ev_QOq@2Y0L!M`zmqZwHk1WxbFAjGtI zzZuiDtML8L3y>2zn)n4c__X@^2fs-59a+<7+1MRD1lN3TZg>El@TIj^L&YR3Y7}U9 z;k$6K*3Yr@zxnae`+lHXMO%r)rwB2QaGH19`+oLAz&}qo9M?3xqJD^3| zSn=0X7)w=G|6vX!YNT@Bi19W5+VyY5IDkz$dgSKx^I?9X&xmKQht@c^$)jGCbMnIi zlLz#nmkq=ao+uFgRf%oJ=3mb3gTiyd$Q1m;YS%gKT{2CS9SAqq|CO0yE1T|to?M>p z5~F&#8Ful4D-JTg@=uvKB$Ouf{i#xsTHvwZI_-tTt;{9iYQ zifCZm?EG{^$x~9_?*#qge^N^n-M#0%S^0c7F{$3-+$YQ?fDRaXc?J6$(t37&AN`!k zvhRXmzWtjN7y6pyzID^HiY)(`?^br0dWkv!7Ct$9vWg{yc_8{q3nrH&g%v)#5KO_T z52INcg}f4R`Z;K-tUL^2X9lX&X~ELg-?Qah3J<4-d^sTbX3B z0lQ=3E7#928$=K4D;%oYg?N)@Rlon+9&2^FX7Y))|Msp-iGj_bR0$JU?#DkpA%5NW z|L#?_BAB3r>24h}w~K)}LX0r77x>hK^=!f%w_(qz>qg9bKHuGR*!uk@CRtgy?1JBU zN>vF|a2$upAtw2!DfUSed>x&Zl802 z9TCg`D%W%Gx2gxi^L6)jRW$H>8bV2Lj}N?hE>H@8oJgX4Te%PJY9)paP?KA1C=R>+ zaxSFKfOYqF5SW)GcOJn691XIqJof*F5=`&aDMkmj{r&v%inV6^702etzJ)6$Yt8_G z{1C)edol|86fBwQhu@W>_jI|PQnN;=lx!dXfsu3X@0&@!zFTj*nhsC9n%#aEkx4n4 z)m^tGX`?JA*9~yszh>Y0RQ7i6U7*gS_VmbZfhDT=Cs1#E*J(zH9x?2ZThtu^q0s8; zb9mnMX%=ev?R;Et^Sy(qnV1*hBC-WuMHnq@D#v*>lN~_4`Ye_RzW?9IBO}Sh#*Sdk z+B~kOq;X7VP~pf$v#6``es;K6_h&n7L<0s{q{**HqZU`EY@ z1V;Ws0;LVr*|(hM9g^{+UW2hjs}ccI`t4@R-B^-O)rj*~*5bl}%(>RM(0HJGztFkL zzlSclYA$-}6{S`Lal1SDOUJMP^Ues4uZQGCgnx*VQd5~k@|<(BVu<)|3WqRN!$Rye_^FCLG02&EZ4(UNL_LdA82Wp%Cg2Ron zZ3(D(I zlw^NykMMJb)Cv}0Tyln>7%hdV3DUWnl;^C(#hTv^3%=pD(=q4qG=M9NO2vK?R)Ox2D3-6`Sd)QUI5W>ZKIY+h|Z> zxC&!$guHEz`5Nk;pb{i9iCc+q`B_#P0yPuk8M}MM7`&<2O42dyK4M_mpt;a>jz?h| zCMWa~R%T~eSMZ^xtB?6Hw>A(q*KX~~!sEN+aU#V_tNqOgx;T-htgI?YrXvOzb~)p2 z`vk5V|6po8%w$(INFGP%l%Iy$Br?sZo;>(g#A3A$^H^FN-Bc6Ln}V+Ia-pzF#) z^%eEHu6H+e8ARwSFv|S;(!u}VG8s`3Y21kQ95KIBdDlu6>zNyNmwo$b*9hz3hRa>c zrjSx9EBg}i7|O+x+S5@3I65h~6^y?x1Pd)h(KkRcOlmC#5s=~W6%&Pw&=S0hJ^h|n z7y$(tRmd`dV+0xTwU|W)tuUIopBhm^85x2yKnMz2OB@d?K0Co9SCtJpATrSfWz`5C z$D&Y#rX>F>EhGS$tRP?J_DNW~E$pipPALv^EYvSl3i1_0-Zh$z_H|YPHkiyX2rG_} zXd$CRSSDGSL$+oL$ly}rl^~&)I`Ign zQbR!FT!914B7eCz&N*ABta5yp?%MvG9o(y0=01;zw)y|7T}rEA!@DhzLP9M&EG0%z zGwYfJEcZ7LUQUP03%3H;iQW2MCwhJDuc7OGGSML5TN&h0O}`$P42C{eJPSF zg6fBp$=Qs599bhe>KcBPO_Q8NdJQH6s*3h3sI9iMu_-@nCaZFUlG=RzW_kqqicL0Z zR}6D6OS)p+nU!)hoaqy7Drpl%eAQvC`9?kgFfb?*=5qNz2N07o`-RC-(|4FR-6d7c zeUDQ$-PS)OpBiCOw%#XbvlcFgi|Pd3LGS?WJPg&CltLUjprpXFWZbmwcbcP$ZpzqZ zn`vl9LlTmbyvWWLnrXpslU`p|U7lagm=s;oy$2RQl?JLnxG1@j7?4o))$Bvu+D6fA zT}4_6tbo>p*?KLDKY9Dv?vE4fsqv6t^_Ch++lus0;XXwini(?eD93%z`(5X6J5UQv zoMT)pxGt5YDcCx)diGh8Ht)_9K;0fj9aql%|@!*PF zw4u63dNdK15F#K#@DEuw4Gn#HRn5y!-v=}Iha$ypEBDMZj;yM3k{YSsRw~1bT844p z(?c;gnROQeva!0h_iy5<;75rReYM#a8fl2)Rr%$?pu{~(SS6FFLsav8>f5lYI_A^* zkzv8RTh*@TvGdNi)Mf7R>&DD-N>CI5N*O0=HDlEdjPb|Z{r=<%3j$eE!~1r4WIPU1 zcUL(yFi~kcIA;c?j?mUmW7$p??t4EFQ&T%yw88f=#Ycvsmf{o*1{FF|>!_-#D`|Jx zt}UNj&kqFd@QE5($lCg?K?j^Sy?yuUyoW}7O-xBUTXSu19yVBGvjqnd{iVE3py9dN zpIX-}S{MhQokL!RN-e!ma+BzD@m{P_QV1{X4E&$=VS7-3O|KWsxG{dqxi(Q0CV}9f5#E<2$d&V9;r-BAP`L7==`9w(7TMm zm5v!z1%9n-bf9GqR=H+24GgP&~PbdkH5l17T$1la9teUC6`j1N&BYhH&j)=YHCe z!*=j6*}+DpuB{Ii4Nq4D9$bs`t3% z%agL~)YTcK8tq&|k-K5jsMTpWp>-GE7+htjti0lDd-*xu_qx*tTj@y9aZ|O0B*EHS zk+3>_gBx^O+x?#QaW`~TP;h2>(Y|MkaVjQF3auLxMwRP%{1}^7+SHr8n#ar>;+Doq{HM|+v%z&-m9OlSp`iq@wd2REFlTX)y>v=No?ICer7OQT3 z8=r4TjUip?I@`zP|)MRg%T}hgq0^Ll%{djX7M=s zuI47s=Ln4%Bl-ANPep9ihPChXZ)+U2?HT`OZo(dm5=vekc|Ujr9v45nh}nSJgL^o) z7W~eVBvs4;4m(kyTO$|r)!2VG^SJIPdk62;EMJBa0;ol1qtCxN*a@68!}<0yQaI1X z8GhFeQMD{ZvS0D${lPv<+vF*iNno9=j|_~!wiHouy`Kg{T&?E}<0#yD`|c$KeOWk0 zw^R}1T4(k-9=V$X@w@yLi8(@EG2pCg3AJG$XfJ-v;zqQ*m@igk5ud%LV&`_{K}UuRjgbb}6+m-*<=g%v0CqpS$#=O+Mf zl*^WgIhJyPF^fH6s{85Qwq?ouuBFBED7PnEoeG`+s`gFpq4dyz69*cs;)26aeg6>0 zcsirNOx`JdR9RVEd3`SbjN)=KQ?MK>qQaVW@TC+E+N;Mn|1g4yzLS7s;7FR1Osm8` z+*`s_mIaN7h`2guc4a0v4brS>&6duV4&g`P7lpD#LSA=`6wI{b6@llqa3zbv&RZ|- zuVA5yyD?^RnBzq5m1}t)ABPagI zYTUc$sTBRcf@1*6rDdS6uB2~Dm$zN1UGu+Hdl)YQ;-wErP_*Yjlp%{V_6FWhmfVA? zVPzr>g8aSG3ektJM|>5Lx!528$k)qqVBlvMxtn)ZMC3U>D)@G#6{aNrwnv5*3DN&^ zb)i#_Uqzs(;DASOvcpgMNn?h7j85HI?rV4o@!9dxaKAZr-S5|ltgcO-_VN;^jlxL- zUsHT$-H7Sue-8dX9ACjwT`HrV&+FyY#Pjuvq0hJSB8D`C87DiXTo=waOk7tU?VK7{ z66pOM;h@VBPJIXKY)tjii{FTK_WZs6vMxR>HP+gvxU%tfxug|VNX&$B&hi^yi8*k; zYt;*+v1hOsDHJ%CcDYN4mIxBC;y#*BV&@PZ-6%ZHlwqEgsed=2lyQ6NBHYHpU@bh`I5;?CponREHjfiFR|G zebquQVOwf`HqpDbHYx(;!r->LQR_SYOx-KDaBi%4i2Ps2dY1kKOJI}D~SGiPC246g+pjt)rUQmju!X{S`|jD_ zWvh=~*S|y5viT%unZ=TtZ>NzrN1rSC$4OitT{D;I0c}8FjN+9jOsJN zZ*_G~UGiMKECf66;|4@VBvX@LpUl})+BWYg%9cg~C=z!|$8wS5+}^)sRAdQy=ger7 zm(L%3TiY}BHGDhhnJbpUeH&5q&%Q+Y;9r1s=9@eIF;!AR(ek8jym)*|7P`= zj>+R)y{hwEkc7UTSYXQGS`Os$(@^y-kc?w{-phM+S&ABou=o>8h>J^ndXe+9mm3dV zU0r`;zTM<~3L>wq&;2*77Kw+J!t!z&6yW~dN@F8>cc~`3l35y}l7&A_fqeGdHmMR( z=yR_TbUqn3Tg|maLneB|QECrWHEge~QN)q-H*0HOXWxP`vT-lq@hvH9(-v#+Ju(>X zVNH*NqU^$fEqxFb?vf@E=j!REQ8~ny*68xnU!5&vYoj|pHzE-LRc0j5|0*L&MbUhp zkl1A3Qy5MtHb>xX{YIC6gb{G;uycz$O#HEO!S7ev)3jhhDhJY7TFe!2W+6kFvB_Rw zCAxd+^w|@rwB~3U$X}2*Gn%V(1&lz)EV!#CJBa!ya3(5)yqmr{F<~Lk&vM`{Gh_%n#13zXQ81%a~(ghsVEq@*0Wv| z>;20g8dGE?Dc|QA5KY=_YR$|0q0s2 z_LMbjK$3pXv6PEPx#0*7Fkx#`xTDPISX%Rv2f_!b)`STfjGB$Q~ z_jM}21E2FdKRG00RYmuntfBKN0aAk_+v_V`S2&M5TJ`(4$cix{f0o2#Qe|RvR-8G( zx2w-^_XJ-F$ZSq7^mL<5ah%uOh`n}3+J*|WWD-zvc{bQV&&xuExCN2<(=KI zfJ%a+^Fs7qcr4Gi(mv-}4Yui%Ja{#%4v6jP8t;eR`@_{q?3!+meOCWxRTHzbAkL44 zo{vSf6+LC;yZtzptL(XeJ6Q20g*<^)pYfp9`}=98-uIS^*FGrk&+HzzhHoeP+4;+} z)F=3v^T*H^m)nhX>#}HTulKq!H&_zka2A_))3~gM@7wRhdd{cVjD6RCnyD)rv1G$? zy^jX6{O+X454_K=!uegNVU=|74&v@yZy&P%;ht$Pd%1pFnyNWIgc_(o4|nt5nV^%$ zI^E04?d@ztVawDE7Q&mdD(`(8&Ek%A4B=f^6L#^DNjC7c#U6!+ud8g#2{+;!!iZ7s z=SC`St+zsb8cdA-R7*|6@YQRt;Jlj2r-vNk38KMmeS<#g4h>owVTHMU{@zni5F-6{*$tR3AE9MJ`i(pwCqI ze0F(Jld80}bIUruJQ6z{+>aGeG@H*0NBwVg9)MjpXIHKW0xtRLY%l=Qz~oIkB{m!O z%oTm-4LI+sg*fSC44|Z>xA)51RUBLxepP_9{I=iG$H)E}QO?YT41kt>X~&v>6(;dl zY1D>=(v`Fm0~q~Y!MMuyFUvJttTO?)NZmu~sBvWn(|LqfH=R>vl=0LxH8>fU#A`42 zXDN9d9{Ya;`)=*-L)6uqDBl9f!re7F83YzQJNx(WreOA>CZg7fW^`IRs_0(wpu!)@ z*eXh#4sPnYogQ*HiES^mSlnB44>PK%qhl0Mbm?IXwtkNw>d=U%*C(=2k#(0AMrHn? zTQMBMnMZ_X_L*CMf{c@$s5JC??PH}W>GjhPw{BTAN=F)5Flqd?GZ7)1%mw$1c$(>mYhnE^D47= z4$sFuVQ~gg#bk7Q`C{$UBtb7mREGY>%mmWxmk41O_GuBy3gjn*|7yk^an%YF(aV# zoiYpK?ExBVDR*Dbq&bbj`9<%ww(yrO4!d=awJ>=cRl%1wf9ZBOOs`0`@1t4PRAmE+ zwxBf9;+dHb54?jZy=}+8pN^BsFQMTjFl1T1dNwt*UN?J(r28IT8}?{b{XDHR7XBf; zg!vi>Do+K9eWy8FO?6iAV8pZ~??FKeE7jQYSqNKO_8yu$*z7e8k6rR_ei>a`-gKMv zVxOk)eBa>QIvbAV@KRBS%#J}ofOZsAG&zt@&4DAU+Kga@ z8Yu=;drByWLi8K`BA=%x*1-&u8hn##&rK8H~L0wcu0 zpEd8THD9SR^E-=g^luG#qHP;j6yZe}@WSv9lHfi7e#C>BMqMP}TEDH1cVS)6-%gO> z3J9R_Ivm)GEYQ%@)nz;2WP1^dYQavsB=Lk&{!zoWRoe0Uj|@0_4|DT&_2`m=2mF=w z%ltXKcQcb)Px3I+C@yQ?y`MWe6Ifrxi}!h}!7DVqff55VrmVI5>DturWlTD$G;Eg! zA(*Ja)V7j4hCAavx6Xmj@B>*we5=PgsmN~L|NZY)({DxqIQ!lGbhI;c%CX7$H%@_A zmFO@ukN-(_d@c25;~e6!wT3s9Ax~XJqsjbcCN`ClhA0_SfHo*qTh8cvlt49w1qVqx z{^P>_#cH;Ti6w7()s06VyE8}r5FA*7oUxZq^?&+HTuCQ0KX+uA%@J6TYbf}{3iQj= z>dmlGsU8P3ZOKCCTL;uGH%T^-P>4r9=TWN6;iM&Ft^3^kV-eN>Hw5PLdKwMvuA-OC z-iWIJ73_$q@>N;SEe<}c$9LoK@>#6D`zQF$hJEJK;0AzId_0`j_L23C`ID<+U>L6N zx&PJ)eFp4sOXuMpD7#p1CIa4{R=ly~f7UsicW+~`=x)^cUpWKtR4Uy_$_5?>tAbyn z%Vs)v7LSt#lw8h{U7Zpf*?dboTxWatkVL0*SXJXog1tY#?i{bs+90f~f2RWY-p*u$ zdvXg&b(b>n_3a-%`@b#(FsW(lCt@&FW!SQm$K~;UW7V3RoDkq~bCmO3rE*IPn@rW_ z$cWBVLjZ1ld&fh?<@jh(e9v&bzgx8zR+?SfmHFzlXc}+HBq9L>L$4*n*eK(CXl63- zVWJ``5hH_>Xe;0aAD&+FX zkN0k#FJCQKLI`2ls>G@=_Nlc`Tk!tR3n1}3pYyMJva5^h*{b{FvabET##4i7``e6W7vCPWGt!-xB}?JaZyn&av~}a%OZgcL(@?(@H_Y zUV<&<_e5Ns4sB5b1W=}Ba(5w~JnSNZ@k!$gRI&KpbtV);_78b}4`v3|xFbw9wihyR zUf^z-#a~Ca39*Qh!(#qdzwu)){PRTkj3C8G;nicRyl&?lGU(khgk<73J^iYqEgx_%aX_8?8!bU%Ye z#XTu4hBlCcCkP&u%XOK3i)&;{Lxgp)+35Mq_qeF&mpGotu07pNP9ZYaUHIxqZ9Cc7 zmC3Q*!hG!B!WrHS+)$;eN-IuJlq6U^mMgzBVZRqIIZ9*&!eYdZ8hE=`2~VeJV5kb! zPt~)@&H;c#ljqXz2*;0-nl{~J@_rmt=`s&6utTIYK)M!us|XBAo+8UUfWiILO+QKV z2_!s7pkAke~ZVwacz$o;Wdw}fxJXS z(bxDl1G`51Gr&!cqd&G=HxP>1 z@tugwkeZ};J|kem=vT=Cn2!7MIxFz77~-UUdf^lB7Xd2f7f&*eKqEZxttYtaKF3Jg z4BR#+mmb|sAafYt4^Fa-@CA=hmgYO=+HUWT?7_`&7_>Vb7oMC%MK!q2DE%J*073u0 zL?*Jtql_-f2k*QxZt`4>+K6l#f+PSL12~hI};o<5dgGN3_9l7&F<;Cp|PA*06! z@q>G^?I;u!B9itC&2XWaQjn{(vH&mvki>!Z_Wq8J%qE#uNT^*M?Oh%10MOIj+0)(0 zFd#~VNHUG_?1l4hUH`CIrkBCijAj)W20UX)z^<5=H=!;W{HxB%%l) zN;wb)6cGs|0|g*oLjGZu=suTHph)%tr`RBkF3WqIFlGGA>2nDpf=B=)qh3pEb@7x4 zK;5!ru`G)F&z^hz`RAl`WYLW)@4xRM0Ej1J8g(|;R|c|R=G;T`W;Gr?UQ$!_!yo>b z0Df!BJNIq8#~q3c5A{r~o4W7FUaPrKCwp`ZZdaYm#nU=9_#jcrezPJSOBnE?UiNaZ@>KlMWIa0C!^~E2G<0Qzs#wp zfVw0q3x{Hc3C8bz`v;%0trENCuG>~x3rlH?ox#Yi-8-%l#9p*0 z%MXPjKA+Edq5T}9aZYYG9m~do6i4?DcSi!wa9W^fjU@2By&VAH3MB}lMyaG)^GmEo z#c<{>r zfJwTe@vPr7ykf-?jZRxyIl&W85`=QIyrQZ$7)?!^G_8BsTV6J%&l>`oF0PmW@M#rD z7>eRJ_U!573m2{)H*MNb+sTmvq<__`Fwc7Xy$?$v=2J1CaXq$Sv&bw$EJJl>+2t=t*Iz2v=^6`pKouqS!_MSL-XsV z*EgTFIV`(&yoQrWy%^zSUX)P;^~E`c$s}zNk`xihsKf1j`o))dUf}e4jL7iN@WrMk zlf`VxFRU!7>Kf>qP*byg@4nhGV+K8e7hl^A1h2YdJpg=g@H8LiwFd2tw{0-$bi4MR z?C$SlD0;;$Oj3~E+PYV*)$k&PDGH;@&d1ujI%tZXIJWlm`E#ZDRtbTOz*b=0wf#U% zY3;4_{*!(jlBB#=J!c#}&qPBVE`=r5cqMuVP0M3lvt->WMr z?Q3s({u$gR`1G4_%@N2KW(cQ3z zqv4VQ>A-2T0di8&u|d-4-^vZaqfb1}6XuoYpBYzO6!r&sUPKhI6iu-ljZrGe0|H(U zfe=JUI20N66gixnC?YdCYE5qAA2|tBW&)?AM`@I8Nd{st7!W`tq#Rc$Iayd46iESv zG)CisrHfyC?QMb24uM|jC@GybIjlFXzD<&|KS3!d^TN4{G%N)G{cg|fnUkm2jwcAq z5+I;;8soGvMgZt@xd0=FLC3Lbj0wi*<`v6+`0qc-x7s*X^WyJcy5;88txXpP2Kpi% z_ug$==Ph1(>pfo?9O!Yn-Gac=2Zv17)cZfz|tEU`QCn$Mj#YScgb&tLPRpkdjx zB;^@QhR41F0HTZwYz4;~&dr@Nt$)~QGub#+{ZIe)q$Crf&>v^c$sYJ?)w*$YvoHct z5(yz%wf3L>^*=>Pq-mC8*p`kK1|y4EAB)CPf~00pz~_rZ<5S0vXDLvt)f`|Tuwwbj zP%`QX1{Td<{Qj$ND_D9qDvzoKhy)_Bw3##{&-BV zYg5te0-;49I8#SnIU9h{veI&{rk6s$MilDm?{iozdpL``SC!&zv@gRp$4J^PR6h|Ho9I=QA~1V4XRAUMwwawHHtZv$v%OE@inY+mf79 zXZs?bF%pS<$^btR4BG70lptRT91$chyLqivZy{G4^)XC#=PR|_O6|6*w(KzJ0ifUO z7i7pco2>@Did8*$|K0!RJO3X@0tnKxPhHTcSpaB1eKedD-hcI#qX+i;BiTut=g9XA z`5Z+jjArAvzWrSwa!Y5cn$vANaA@v~8KG$W^tr|bvnP84F}p?g{2yQZ=kI^7qrGG5 zgo%k%{K^0LSCz8iiE&B-ImxFfhDH<+f+>OtqM!KA<5Qkn*r;E|P!mjomJAAJA&M8<1ZuAnIzAy~C=+2K#lLW_gahHm<^}+;+43%QblMy>W5-NR zrsLI<>rOYF^9~I$G?kSg{#&&0|N8_CMp;Rmr6_AHIwFVwVALD$yYH(2@QL;v0Ms0* ztt>F-6>D^CAROCw=)lz=Xp9l_?#^9$HI@>I%928}&3?MR9suf3oul-oO%H#Em&Au3 zd90#hJkO`@Ubl{=Vae>N`V})v>_rJaT~lEB$-n)_PyXx4xbxzte^SrT@W~^4=Pq2` z+~*u_IrCTP?U@S}tX{RwY_jCudFIXC`?tK#QgK2)6M7PG`k(pZ(*TePc$rGa-_7(x zm`}!uAY3UsUOsNj;)N?{M1(84CEsNDl~7zvV;7G#cPB$7f1pp?C1psKw#9V=BnWfzwAA>&u{Y%JV2ZJO*fSi1@8Up|# zf0>onX^gk5S)1n5dk!8f&a=i-Q2@fHQw90?OXke?_IDoNw<0ZA?4{B1)n} z2>>7qX74&!Ez zPU&jzkYs_#`0>ZT(%E#Ec!iHJJia4r=Oc6VK9YHMm~Zez5%xl<>fZf#WyzGg=WvW!50s; zbqv~!mZN8n8+AqvrwaH(RuiY9vmGUb`#CNPkO-120%4FO5Q=ad6Hd~4PT~m%B+Vir znrH}lb(Fe*RYzlSoh=U$SyK2;6idsAbTZ91i1Bc~!KUI;vVak$C`^eGB@-DVAd(0e zC=h^H4IBXYVre_a0)ST;%G?~&>M%waAxf{+JFNCZBKqQMuiv%)_IYy``NGkqOO_w} zU=Nj<3HUl`^4dT(WMs(^31uEJ7>yH&*BiA)i}}8LA5p2)pQb5}2Ahd<6jqFzFv$~% z@7w#~RpK~bAR{1?O7jDKy+MBSse6x0id_DIT{WH zL*5goq5v@H^jFn}^2@6+&HfJ__US)9wf;-@KCtPoZT9?+_G}j;K2B?cxbO4rQiK2_ zf)UoJnHv@?TE29R-QwU75I`wWZs{K0zJ0r^`}pVbTh_|_Xj0;x-rPH}MEvh*`XL0E z0_n1oH;vhP>}=byvuyx?6p)vpu+?s()GTH(5fP?vUq?swPc&UyThh`pASmd>C45ti z2`~(zXo{k+Kji(yTl&)NYj^G0|IM#F`1a;^$5of?-TL;dnKMot@-3Ww!?w3xEGsJo zfX=oqA(fE418rxHb~HAeuySV(AFH%!-`l)({Vi)w9y_*p>9P;@?0)#(yIy+f)eW20 zKl}2l58Se%21V04ji$J`c=nVDCY}0R zYqLqK8gzQf3aS8L*zK+^FS+X7=I3Q&8do5SqI}#NvglQ@L@>`L=cp1~w6&b3*a3T?p_YXPy2YSei85X-~^Vk7l{d*_v6e^>|VMAWG@yp85T(8>TE-x$YC25`h8$&u~v`Lp&(PKJH@-O_i6A z&nqlN2e^N_{(Z0m)i8DMaHgyfH$1{8=QXeSVX$wOl4ru6?o_6 zlq_R_g3>~h)$Z=+B1wz|0I*tYTi$s!*xlt1M$|N(GH82^vGZe70U*uevnYir&HSUP*gsl$h+P8vVh`L;$# z-ZXzo^FSazJWxHhD$?6AdCE8d7*kqgO$UmM`b1ZYPDb-4jqSeBJa1g_g)`QgvSI+3 zH)+EAde!o|vv<6|b@r@jJ9q79ICcELe)X&M8#iu#f6ImXMnb6DZ@qcP`yZaKKlY2? zz?~b{zy9v#KxCvsWS-68zN8AmqS-UY)Qpv-^t9=9!_J=JVRu?e9zIgv(dLe%;uQ<0 z>$H}V^0CQCusqKU0Eb-X8YK}7+(0B$mV#mcKAa#lPD(;Z%{udS7sGNwlFRMZ@snn= zY7L?o?@&i95o~SgH=DJy>T1n;eIyntE-Z@1QauAhDo(q9{}F#YEmNawoVj}Y{_y-W zE~n3Ew!O0D?T9~ls<9COP9HrPjYd!G+0H7Ekt|&YYOV!PLnw*?iow~vmE6-P`T({iRJ(APk&^0 zSQjt7(I1Vq_4JmP6}3b~b*v3Ey1jc3#(gdogk&J4CH4sw^E%Ib6bl8~TF`m|`fzB046DVmgfxrZikx_1FcAm(QFwGlOi% zL>5HJ7fkFueC*JNTX8CwX-kapqkWlN|6WPa$?az&q@d~jzC3n-2$Vl5nXbJFbdwuseTd|ou(zrz-rXI zAmt996Db}5)D(y^p=mU8-rT$IdSJ-uF0>oByz|!46DQ;SjjLDQ^zPQpg_X57t9`Ju zO=Z*w$<*1VW&ogo2qG{P7KAiSAwHeTX{YeKkb#JD0*6?VNA(6lSgWGVrPU$=TH~-7 z)U?WMw3y|Th!8Vw(zv~QwsV{<&M_R%=a*Ob{0W;?<3&hcT$O6>$sap0UVq+JTAq@G zg0a&)zUT5wN+eOVmyJscptBVdg0y-&W|&3G=6~($Uv~w(k3aVKjofipt zO2@;#Vdur6&W^sWA&KV=jLu$EHPqe|j|2grx~$yU-QOMz9`r^X2JJwh)=ts1o@F#_ z9Er|o%I)?8fWu}ix0OW$E-5VofWc;u@+n#+>k)6(GHY(S!c4>B&?q8us0`W_3xC<4?c&uT1eW zkgtmgfAJT(Jf|F?(Y|pk8F~AS*XPcx;gnYrWeky}>Y7)|i9B-hqXKlH)NypUojs<(Hbr?E-J%Hu$V#3i z$Q6zRQh&QM5F?Qg_6qj3mZmTTc_!#gtW=)F`yq{QM%;Vi8j5R5YY9*dso# z*tlWt06?qNn+=wp;ekc7X7vqre(=G8dpB+9>gq-SG);?y zl$V!Gs#@88dau3E?j805Kw)7X091^b04yi->CgD=hd$Wd)_88sEq6|te8cT)Z(Y6W zrmnv3#>TUq?H4`$-Jke%lg;WVDl09o96Po)&rzsRt4C#toIKxhaPNWc_H$T@17rMx zMsV)prA~i*_06|%2FH=(#}9S(iZb~-nt==;>S~+~L=%c)E;cvTPM!7bZ+`3TUAqD< zZxJVS_CWpVAB94p%DNfo^L7JigiIzKg|N+LGH49|U@@C$nzh+2oJM0X7z{?8*<=O) zy~&VB!~no%x5Z-#y~$KoS_%Mpb}LP(3T$?bPHWGz06>A=1^{}UTCFiSY<7d*#HrM0 z&YYg7H|^NDyKZ9L(PKw+2K|m5dneUSIe7Rm0317Y6achZtv?c2zF=W69IBmE&a$k= zU|hCfo_DQL^9~V^tsY90RX*4BOqB4$(0_A z-fECQB3Q;Or$O10QNc(=tuvdfg*Yw6-TiX;SWKw`{(g(KG#2(mqCtzvF|OF&I(XUf z2FKBDU0ndsdZB6Q`~^fHH?LaJ>ly@rV`oo|DX)-lHU=cuOM+YzphnIl(@``F0Fppx z834c+38{5zNs!`+*yhb!XHFfzaPg{M=S-LucfhFib(wZ|FOWHL%FOi4(TCAqz&uf4urLqk`;GZGF9 zf{+rV-hqC9JTd)-nV7M;{*#)>jY3B1eW_4(YGR`vIH3aK;!Nu$;0*=!7hbvmQno~KrhpgD%kOjkjY z;|ad2Z}4ROiJps1$?y=7axS<|Mw2L^bJegBp> z!l9^|<*LR_Mu^s63IL+Yw{plKi*s}!r8AWze(4IsLLov3k`c%mt5n8ek5pM@>F91}HD*zw__QpFIOO92nBD>Z^qE?ZKTR`?H<02u zT_l*+>l{4;d?^WP001BWNklCKs=lS=;)QODf%3%($mIN) zCIFyl0syTSnsamY>0dvSSLjG3d07UEL6MNRqQJiC9+pyZ!H_2&kE&RTWr0;`MKMVv z84v=%!=WKp+h9piF=A0Vk@EWdL%x_T-yCs8jcRp98Wk(3DQ8p@ECWr4lF0-wAWD@A zdS!%yeix(DG8KAJkc5~AGb|xQ;G^-Vlh#`pwYI=yqZl@nOlDcF%0%#cU9Ig+{R3{j z!Fu#$y-{bi<>i-aiZ}1rzI4Iz<0tns%A_Ocdg{|PIBUJc}~HHuoo4YO{V<9Lf6L>1)jfPsor8^HI$fyhI7X-iO*ZK#O3!GKs9~F zLI7wyb(|vd%-K_y&RX2i_)+JDi>J>u7db2oXU&*1V~VAC%uqC(PWOCXoe&rr+Wyw_ zAH1h3A3JICwAo{;s<#L=Ka=Urzk`sx~c9~3C0C1SJnT*TL@4U!q*llk=uh&x_?R$@7 z(mOwVCz%SKIejP+cAjrMG3*%v03?gSSS%JA3?=3IV+Run_o?HDh#1|zZ41K)2lj5$ z>gcWSzN9s&Hox_P#>9QN=S`YJyZ3HQCesy#7PW?Rxxz#i(8pVqaM&9P`w##D!XRL1 z`Mk%uZQDEJCRXp=xw*WurnsQ^cxM*?oUA`HIOr_3*#ThIgzDCT!G?>SDm4oLzF3T< zn275#ZB(sI6Za(mAQ;McJV_@Nb$WLe*o_X2Dj1CiqOoyP#vFb9H5dO(Fc@30aMqf_ z3PA{Fe41oBNnvXLo-G6Z(ey1^#V%RAN)V;Kp4Q^x^39vy85nj?99x!7L|Kk1E-nNH zXJpLCbur;<n5Pe>Q5YzqN*BwVFkw6>-G48SI6QF z7US||H|;xqiUfL$w)}jv?xBr$#}i>+DA3v7z_Oa#Z@#nXLbE>-1%Ul04|s=r5|UU@ zQ(A1cxAb?X1ym@IsgK5dZfg zK$BTf6ed^8t|0`=AnVPxlqd$nk=%!uFI`w*F`hniRz}q4$hsR>RiIa?G9J(Q=8L7J z`7PZ&4x6Rv!Uc^=Jv=z9H)#4@g91qIpc?=Ud52|*&SP9;*z|^^G$gU8vvLL8YB~dh%frFTe6G*hzx`# zhzMAcWF!;vi{CywZ_YT0k2N>9nQi)^zTt2@?ej;{Y1tVJ+bkxwnFuK8-EgAcM8D3AMXgnH^Bs@k zKuX||jN4lp$4r>Q3q)%!*P4Mb7mKo>H(2xl2|}N5?M$VEn2gTf$!VoZ%AaUD>mZ6! z?oT;rK@nPEDOnVG0L(A|AjTpCPWM2|1ppvQG8D~at;tB4B*paVpIa~e$9mUG#g3XU}bXh>;s6#79%q;l{jFC?H)2E$=EMwF$DgET^bxdNXt7_%!g z8J7u>DGGFY&L4k3zW1d>wb z50)r~r2tDxZ-_Z8kN`*Fnu?10rpAdijAohA)k}^3YIaj_MjT!=q8J*lkDfF$J_6|`d z8zQ6GL^Pf4-ZY;E02ToU*;6H+Fr!+Q0Z~8*#S=tjUUDoOPp6I^YsgXpx}EWO=Ic0} zdS;U{+EUhL}I2Z%~t=>RUGDXuMBcKUK(`+h@ z2uK762E#2E+W_dMZckIU2LS53vI?)F($88&)=5-)6)~LK?+XTF=j%__RafPel-7-( z*wNcvT3obn{ydB&%=5_%0q?qrzb4OfndTIh#7xiUX12tq&zwFtV|ra_S>-3TR#aGS z%d5aNd4vUN*%uw4>GxPD#jV)0+#+gi*V0F*e4i6jpI zg%(4fD+mBqlV->h`}5zeDYnFt>F%Mc4|IN>(d7<*avTYSe7tl+eRV&&OUeDcxY-o|NB2af9p+a zp8MnPCB-ecp51y)rjX*T#Qb3ZkO;|^(;Ue_W2?ti8H}bs-;Q2qh{hrvZSChS_L%dm zcAHtEuHIKflrbVDr4;~BH-4;dpo0i0i><&LO<64Y-e_DBWk84`$YQgUR*cn0<6~jh#s0O&zUdG6^2^G{lvl@M(J>QeEVyC%%-J)({rF`jo?=u$(0z|Re4)8z#=IH3 zUw?P~L-)S@+Ph0vFT<4d$}?|7gVAfSX82I>(C)nwg@=K3Hn*~fY<=rh0bvz_7oYCn zILwYFZCp3;U#K|%DdPbdO?sCvL;whj001X(CdQPB=pOc! z3UjrYSW1caN92x`KgmSO;3gyZ%q8%L;^~*=8B&56OJ!467>4nMQ^_=MF>(ZCL6l93 zlriEcyM_gTe7i}IA>VHD_@e+&RcT2^1T4!AtBGJz;Lw|O8c#S5K#Y1d%Q3Mi1^_8{ z7a|#j*dPE2F$ho&(BMZNJ=;?%8UT2ZArX!2dGA%YR7g2z-EzgS0FOpmAg6zj{qPeH z-9K;cLK+i7t26i`v4)1T&pi7|*74#=VP4U>b0>fQhnK2q#{A&> z-&326m@0Sq{4B+Yv>pHun+44<&l8EL8P(*v$<57YX0KjVY_q15@~$m=mfo~bh$jI7 zt4t)KP_s;&B3PXiauXW^P#6(O#uNq`vzWt}2ndM?XpAtz96}f)f-c>g5kZI}AR_`2 z0*SB;0RRa=kYox23zSSF1cXAAPE99MBDpR@b`7pvh)mNI0MHx@k^~vSbczB1OtX1; zwyY)k`04=RNC*JxPn|k-zRj9vFD)sKq_3VXFUyil(N;%sJm9RXo!H&d+|tsqaN&GL z8?UOY@Wx{lAt|0{85#fvorCd!d)}O-PrdM>zxUj?zV&^*(Q)E@tHH#IaSj9?u3uO7 z@TcRM^tmGdpjGtQec==UB(7GaA?%GC?b?VxZZvBBzNpofExOdz9VoQv9afXstPX?| z01%8NE*WibT+X0tvRjLJY<&i>kQ4}JZcUjqPtG=_=TKjciM`HHf_(QBE;fF)Uuz5Du> zv6IHNG6FrKs*^pOQ6JRYIRnfQ>BOy zM2W}{pfJuU$kQs$)jt^UhiOKm9DWd+Ess+(CgqriV;P^%kNzgz`2TfYyqu$8V*tZE8lE+C&iqA7WW;rKx1pflbG6hbnxZqi2mwTW`K;*6amg->}m;q&MknDrXPqo1^H*__2Qr>&m9jKRe3?u~c`Xb|{> zKr>u0k}!;&tkLKxjN*bwVM?pkFcgC+N|q!<(HLdDL_|Q81W}Y&3ZFi;&#cjum6lNy z<#GGB?%ug*?fSZ!aR?y_Q4#_gVV7@^LhRq*^7-Fp;ssI4@FQsoAxy=6-pmmQL(v&( zJYi^w5_vujNWQexkn*px6A%#t9N2&GWYfhwhpnQb(w~eF5CP#_9j^?7MJ6Q4^L#1+ z2p3n4+4tdrp1z?q%NG?C6&lPIAsWI6BT?j7t;g@{ZEuT&-1DbT+PQ5frv|f>@&`N` zb4hQ=ZLgU*avREhak)4&m)eu7hLNjgr5Lqb1d~c8FMq5NU_{4cU!)X3L&7i$VBwSp z6qQ(BQmmUvpA`}b#ue6tps41KRF6`k{2YHqxeZ#m4Ti=en8fAxnj>!rshr{p&Y}Ui zx>O2Wkkbnag)@0TD3O#1fp8=#5dsKtH04p$%G4|y2_+0>H6_ZSKoS6=(WIlu>T!mN z3{H2XyvPC+>Ff6w%y3OlpZjD#U{1n1H(Cl#m|Hp{nn1Dy0H@EM@9Fq)^_YsmzG1&_r`Blo`CZ8z8Hvyj zKKj7U_ukAisQq47OKX?eVqU&#;gNlVI*UVXvMo31eyrS&kM;|`Ae=km_s>_PR zcp~3nym+B=T$wdEFhJ8Val%AG(c|lC-h1_(i_P7XGW~8?KIf*{lcrCdwe|Jq4(&P4 zX{h`XyV+#gzwcx`#!sA7Za#jxwAjI@RDHui0z}O*6vI#yBZ{IR2y$9T5t)dhBuhk; zG2r|n>#aAhljI~#A*0^PC*ybBcFX=_`;PA121Ei`l0XC*lF9f#e(O8eP5c*rQA)OD zTu5gpAR1X<;aCi%Bt5IYY?59b@u4uyEnB^K-5u+I)%0|=b@dNNqhXPZ7Cs=7005Qa z>i|G>cM=K-l8BIGFy%R{7Q!M)Mu?$gno5hQ+Ulx+UmcD{x;lHj!Jyqz;0-v75ql{r zef=6erhiG#gf5q#^!gJjEu}d12>^%$lb04?^EgLHGQC5A%$c{-6$xBXZ#Ec8e3~0z zWSPFU71Qtj(uU%S8t*{6+wW0v+@y&!o_gv(U4iIdWw7cdjKAmZ`_G;`3;+}A>R7cQ z5DGN3y_D@7wa#ErPpT@ZEHatcN_Pz)N@p%GBtk&zR5Pbfbq{!L`Nc-FrmLfGaJV0M z{*n8?zGvGXPB!)pboZ(m+%xD0I5~Yn#le#o5T*+(dc97&eDz|TK}#cf%Uipq){d*K zopI*ekx0US*M>Q%SS-a$h+@9>z*?)tUOQzDtJbIZ1k36ePL&%djUg`;^U9JS@XGu_ zc+|d|@h}{YQcN)qRn%sV;v`8B__QFT0l-!?;kt?c;<5M~bA})QpcE`7;{_Xax}=ou z8SE}BwETJ8j1W~jrALy_S?!Zv2C zZOqsJ0yde}Aa2Zr83chuh$JHlt6qKec@QJj6Q)gFxX{RZJpt#1mTtEg|!vD2?x z^Q(`k^!Jqdgb|ixLR~{F{)Ioitk;`NMh(Iu031De;;&`j0if~1#os>t-vtiKkZUM@ z<%xid2~aM-lVcM+l81YogyJGd0|043GMMdaR^D1&R?^Ym6AmT-psa49KR8fcRplJ& zShHrn%M&ykwMmb6)%*$ZK(M{b#j&cCfNTcKlv(4C?K=PfG{=~A+P7ZcI)Ba$GnZ_j z8J41GR;_0_Ev2M2=`LC4IlNY-vuC3mLX^5JnLh&|1OWj=1Cg#;;gJ9Va!KXq>n8q- z#NvgFLC{bPAX)^5$|UYkB$Z0ZNLH)03+62{8}$T@q>JY;ic63i1_)ZWYWZCoHv*&X z>}>6Gx;i?0Bgt@%{hG-u3HidWy!k2sE_d0I(MqJ^a{rpMCX>!IqO% zRTU3B{OxC6dcCU5w0PlaNybDL&$hN6-tlHpfqmK9djQ}MfA|flcr4Dd!+I3hi@}Ty79&})8{Vv;K2UXOO`(U z%!~g1mc=)&S-NP|(KC%f|Ip$EiyN9Q?tJsr!eaZE?tMfg_;$fB9Q6BZ_4Il!%fmF@?;(X@Oh;J1CGsVx)Ff);e9$GUODVm0y=+B2k#3D0u|&Q@BjZ zMm0k6AAwAAh)oXBVvEWulgYTVe*giYRGg!*R7xcV2L~|_9W7fllsBA>DyB|dId9Iq zc+Bq!x&UD6#2GLA=^3ZXd+AS%aCIn@XHWwrrz8@Lq|63YJeu`eQwkhMDFB^HkrGNM zfDuD0?}&4> z09lr3O?O3A$>J4b8_yis{r1j#?|;Y_aeDfP7@8J>p>#SKOQs?TFsYHMyokoQ!|lVI z-YbY{wMxdAQK3jE;toh*2?ND)EJHA=C@-k1n^#yl6(QgiqC{?R8Ff}fPfSHJUOJ`v z*xHI>ItrOOU4&%NESk|N0A`l3L@DniVm^(|cHP8(ftRGLLyy3~FOE6&dy6j`PO}MXgw| zV%Q&Bf731PeFH`S-KPRxC>3 zD6F<nVwu0ES;`Z_OEQB$lN z-n@->J;>15<@cREb7tP0c}Bf4&GWx{>X+fx`k#Myl_TG{chAY+z1I!^gM$OxcWpPD z%m^owF|ntuH*4QN=5j}p1$q@AVm7Eg_s4H-??l_SmK8Y?fk;Xkc(M6> zpT~dpY&`*jt_Z?K8E6Vviketi9!bQF*{m56}e1B_MNy)Jz2d7M}8&37u9BN69&zfGEG4aL4CDW!&4+ot|Aprp8#Wk(n zZJ!YAeuf*%H*l`V#|mFpm6y+1uxPluMWV6JQ2+pDM=8KrW&eY;l-~RQv-h20a#UB^ z=iUlko%7_;1Z8QI140s#NJ0pZ$vN4^IO1LKI;L` zvqsX4CeQTDbk5zC?!DiS?y4D$kYGt``%(Rwc{)^A)xG!JbKdiw_x$zutCub5I^O#9 za~qv*$E6ovkOkN>ob}a@8;(VmEm`*3rtL$a;mRxOT8|!CzxjKi6b&gu#U0E@+;D~eo5MhDsefKf~lW0di{h!I8{ zVvI4Mj8KFzLWnTJ2n9eT6%EE10z@eRgn&{`5P>m_dB6xbK$I~C9M6|K>9VpO5kiOo zp3TC7pAd{F}6kZe%f@Hq%!fTsu`pEUKZr`>0wdbp=e6)}P z&dqZiBbaJb;JNR8@7qkzP98rY)ZHDArW(gL9XQtJ4ekln)?RV-RL#gF@QeWfvhV=x zl4VN~x)38qfiYdi7`trJH@^Cyz;lQb`@4I*64G@Vjz^cwodE!Y@kmXeM&tyC)$VjU z&OdL_xPXsP;o!CxomRYh2fH;m(dbFc+*@C%=^bi52HLw>0*$@yzC0Z&z4RR^}^%x>E4uiC#=`5Pe1-*`Vw&-$OlZk9azy$!YWWK(_ zjWCME^P&X-Kq{?x-4XyqG6i%x)tZgLghsF+ljdZ)>NZ$?Q92oOdYl}LzZjM?3lHT8|jXpCb>0`AV6 zZ`->4`A{q+h~i-Pz=qdf1s<}=$bmzLe8C2tkpLx>Y5fDSM6zw_)G0GASWXC~RA<1t z`-a1z7~;5rp8h}l{5JrQ$i`CX_>~{Ib-3$TAsvnn4Q7gYx7$w%5iKId0`QosS~eF0 z0MK~@jVVJe7RhdaIb{Z<#p(b6$>qfe2qhwK!5r3!jt~Y0M3bp1=W}TQaCvL0%O6$I z001BWNkl*2TjaQ(POm&?=E)yZqc7dO6i?C7DY+Dd;Q*x%cwVT;u% z6fzhKxR8oH{JkG^cD4qc&W9fQZaiD~*z#qwrq$0qf7Q0bhuLXG?>u0}=&yeNr%3nF zd2?s2zVeomDUmh0bN|8qfj$6eJG}e+`7;3Fn-< z_~H8>`0D&wbM|i8Flpu#QS$72bEiN_`-#r4{OcExrd_h~;?j9`D0NV~61AyfVW*t7Tw0+;} zg595pMG^p)U2u`gP)A=!&^u3nGC@U@I12drzpjI;Rc#FzA zaymV3dn$d35-cZhRRM>FVO-Dw0Dh+!&#D}tc(Tyg;El!eK94PtDwsC6!exu53e(3` zxAwhzQn?KShu@Q6BvG{E$Bu^j244a21_RGL`KP%H=2X`={8}9o4mUaxPj>ivUnt(FpM7*?%IQQ_I|;_q+eC*YB&YYaANr$!lN*=o=WKKxaZKJ{l||TRVh&!X*<~#Pvk6iDOgp#Xwj0O+t)MD^~$=Je*ep# z=L?zwh*8RPiZMoroH%s&$iAbcvKPV#qreao1u(P$K@fRhG(6B&%%qB$R63VHoF$!( z1As*-SN1aePD{hAE;rQ(0LYmn!dO@3XeL8Q`N!mJ8UTW|<4RZ%B`R<15a&$%2X$bh zk_}S=09dCWasc3RyVLQc*X8Q(4;?!E=;f;}Jpa6l&UPMPyoG<}rH%UzwA<{`xTXe< zf9q*c-%xk&z4x~sZ^NLTH*tc~8(6Y%k;{VRVm?6@Br5z#8f8S{4C-%jN)Js;b$n()9Ur7tCGI)7`;y zLVHKsw*5ym#uFWnZ?2dj#q!3Vjz>6N zaJao=t~sAisJVjEbIR+H@L)ERX9#IPvdK&~EvHi1OfD;DGd2vMX_(O|lWO;z7`*w` zHKNUq5a)0Q?Joa06aPV{Tg&!J`^4w6vi!n^^_bV(Uf)nM&WoxJ_V%8k6-w^<8$O-Aug}!G9d)x!w2^7+PQhbf(tQE zfiaEfPKm}7)D#;LjCCrC<+3%vWp{o=O2Ejb$cmoNYCYk!ggF40*C0Hf!D@MMg7bOkMZND|UCycxQ#GF;UZM>+1xbGM!u{T8rsOsOvam%+yu>n>tV~m-|OD@yCw0 z{=c7p0|3TNpAsF413)320DxFH$#KN#cKO||Xe@o}4OcB*y7EjWK9`R1yc7wC9{uGn z_Z>Ouv{`($6{bqKDKcIves3H%?xL%1Dnz5%bVTCF^UuGON@uTHeMN6)d&BriMWilV z`jP+lv;UBDF{P;1PiU4^nodN6K3^u6=NMSs-fT9PiAL>KK{b`C46+($kV&YPp$!#E56Sgs4gwqYUxD2rn>71Vj+#y}`OzG^*?6QKrN|7-@lt7Jp4+HkHfA zq8PM-u6e8Ks_UBC_U|hjS)=s7bjO8Eg6B}M${$TJPBofZ*gOD`PltJ)m)rpW(BuLZ zEJ`+Ib9oG?noq@}9)D0*WL3#Kyk0p~juNakS0P`(91rinNBi-vu%NPN&^kEZgH0g~io831Z4JSF<#a5!64?G`Plqc>Su;YcR(01yb+ zMS%~;GLl8`IIXE{F_tQhHSy+dVzym8i-||v9rxVv@OOVE3T82?>0RQtHSs1L(`Ift z#_y|UPeh|I*fjAUzv(KsE9kItc{y(vZG@1u>;78)mQk8(n)p&&Smm+}8=On8lYa*$ zzWnQHy%aEc!m+4vea4+K005WMapk3#IUKn4_+ZP72|D6q!=Xq2XDx5FGQxlMbDwo+6Idrc9`R;+Ic~g5`MY_Q!ww$ZOk95+Y!R zE?Cy`)9*i0EF^dD-u@py{NYeaMwDrWa>-X7{7kX^_+MV$_qEU7P(5--Q=lLIUWOL0Ekc`=i^Lg;h~<`P_JN2HeF``FmA&1 zNekDU^Wr~XpvFM7$FSCT4q;wMWpb-8yY#$;E4=QrC%#chZSm5j=dD_^+U4+Oa>>JO zUHkX!eTxJyMgqqT^@sX~+MB8>mtC;9ln(R+g68TfGA3c(9<+Vp)A#3PDv4q)oAJ0E zJwxGYuP2@^{^SSWvm@=S(TUCxogv0xkO#y{5cUfCE4b>zFV_;W1_iVMd1s zJ5-s9*0KHtrHm?axa$N1pp+2G5QF$YceuC1YAx>~+3>Jn6Euxrglw)LFvchv8cYDA zr3eN9a;XRcU_gnc=VHTv05PBpVMMdB2*ON998Vb_l#UJ}j4?*ZaKvgPMboJmP{52Y zWZ6>e$v!PB$-W?6BR+L9xaZn+`j&yarKbSfU2TYyvyUSc-!;q zv^?2@UQyRidF1ho;&PtREClRAEU(2gsWYw|fZqP$uI~0kHq|+BvZ}VKmCM#L%5L1VWP3qnw*WVub(+}ibX=Is;QKlJh2I5+TC-sY24IQGLlZ@7c8Fd^;Q&; z!vN6N-*#}%wpU);3;@+0DKx4ZpN=Jeu!`|Gsyl-GyYycr$sXx$ZK|tx*-^N=6#$%p zDr~5<>be2|9MI844gf$2`5QEe|9HJyX^FYOTP!+ZTK?TrmjFTLQx9fy0}R-FPe zbv8^dRW;ZAfI^;Tm9n|dab-EDMA1}uHYTL84MdGz z@Ft50jmQi00N}9MXU&*4Z%#u;S64;tgxcDs(Dd%_{Os{Bf8l-rPz&mW#^5zqEao`W zexlc6wcmF4UH|>xPpQScQVc!w$Nv(Uh8P3JKKrRpKlAkO5A5F=>Fv{XH4;hRxaK;W zVCA_PFFya5jq9I1Z~l_G^OD_z!?%6rlfU@MV?4r5lg6Joe9~jF*z9(WLqKt{Py_&M z)X>QVV>PM9s2KgfI76?Zl!;}8If6Aq?R$Ek>#qxX>c%w_OeLF35ClMoQXMhMVS(xd z5YnlFka$Xbf6l~zfWXs8SY1LG%m^A2Lc+1wrI%fF`K4E${Un7<8X+#1N-Ui}?b3^u zOP-)cy3?-9w|^cp=CDrAdh)zwE4RG1{yX3N&TpQ3Rv?^6m3a#my*$vneCY&0nq(C& zm|fBJMj8N)9z6;G(MT@?y^z(tp5Ra<`G0ly;b?U0);9-+dljNu#bct?t+SEvl(z_X z-+3cpS|l=9T{#~KeCLVXOXp7(L{U|g1i&R1Eqryu&Z5dnZ5{vg=jYSOjKg6`XNv#x z#INJABH|Gxq~~PcbI-j305+#xmveV~;ueK+{XK(A>*^_w0e}*O@Vi$E>Nt5|-g&F1 z5$C=Ghjtw5)ps1UlcL>baX4I+RaK(bW`LzK0N8^yC5?KbpA#_n5Y`tpNxrP)UX@yt zQbH)Dm4U!38#leQ?&aHVSabg3OU`r>o6D^h3O1K}=fU=l-pv7@8vqh={tUYcVvL@@ zh48cI`8d z|F3TFnj3C=;gzkoTz{3vTiYLwx*WDbA$#76D}MU$ze$jVf5b!h`H~`o^ z0m*{?{Pgpc0jDomuJY%Nq=llY0MOgn=dP@B0{~IHes8E7I359j+hqj+ixmT98Xfg) z8PKAfAs>X9IK|Ta5p2wxISqFp}Q5j*B z007Z-Uf`pN#I3hnzi7d7ug7(27;8=#4giXo7(!w`lbAQ9dHVDz{)$>j;0~NPxnuWs z7?mzVl$HSj-uA+aYxAjaRlwWP*%gna7Ol9jzpKX?izAU+HDSJ$LG#3>8*l$4!UDej zR*cBf$#sW&hv&|os}d?85HW1sv*(TV8w}i_yq%bI4kOltJ$traapjfaH0ka?IKFwj ztZGj^`}C)8yWL`O<&#lf;HFGy7A+!1h*I4j2w1JQ6RmBO=oDjyv1$nEMUA;`w)y6a zHbN$#VY)$PoK8+l3^D^4;S67!nE6sel$J+h6=;d^3{4nAG!l%m!GhNf$&~oufKGG_ zcq9cnq90R!#b%Q#Jhn)xU^B7~evdR5O4QW);_*BHRC;VjyJ7}ZLdPH^ctjs~#1}Vy z!l<+u(R(?q^og0(7|1FKU4J2LR|98v5N+e@rG~gsI#2 zo-n4d2mn(jPi&sp_`6>`zF_u5t0U`jdKku(k$gI9ce^;mr4p&Ow!XQ`E-nqRz++cUSKw3o&E^V_I7gHHza25nX(lr$TM5D2k zW;DYx6Q?R~rsFcHTqZT#)!$ua)4QBiuFA@Z7v3`aY7e6%8V(@@(*$tnlyIyZhz!uikRQnuX_Ie5O-aT>&MZ1%Tb{UBiPh zhutEpT2_)x$sbYcxcO^H{TQxdVSN@S6_IJvy4DLk-{lIuz1OmX;Y_* zoG!~Li)f)bd+N#m?vEwjQMiB@01U?R@7L|mnlkO$k6fFKboKRzW-naAan@uidfzvH z1OR(>@9R8%>}&Vm2P{GhU%IcIZmL!b65a? z>prrkzvr0C;oSV%mUKG()h~Ts?mx8X{FR4#I!k9eyL|_ML_GEL|NKEb7KWKK`n!+E z6S1nQ=9kvKfb=8-M1WBs9Dvj1& z07%B7R_psyaY`8>G67NK`7>l%{uZ;X|8OS0P{@_SXN)*NJVhW{tN@UVB{WU<`8|7f z@7}WYjXQ3*ddBP}Z{-Ry0I)f{NJZZHEFF`3u0L3js(p5EEZ9+jkia`9g%2k(v(?tcjdr9_g5eKmbYSDeQkx!!9V`{7jv0BV~8?p zk!vAwg&m`er$RrUb06=}f-&p5x1*&Q)D_(wm%gK(;(?6V#r8mCt%)A8)W-YmFV0g&o zuLOWdXJ^0%b+ygE`t>igT!h02pibiHfBgG@?%n@-V{Pr`4bK63DUs~@{_rQ7cWES@;o9XU8`@)bD1feMeNE5k9ZD&RgPxUnd)@S$C=ZOLf% zzq=vj-dV5ffoK{4+PceKoO(j((eHK+r#_sk6%h#U8InZ^)igK8LW7g1PHSnIoh~RG z#~(g&ARUifwDPh8`ww&+Z#6&staUpsPS|MA%^&7b+~eIiDCcOM0SjnA!P29Gt7 z%L0I^Dg-0UVFJLty`Jp*htd5lW?TR97&WHji4Xu_v)Ka20cZfQYuC;_JNMmq&8iu* z7oX`QHkVf}Ub89|zs&E!2!AIDoLW;UC%wtB*$Lodx=*wWb@fd~LVTvkW> zc|0kH!W_dN!tBYWlTNpno$LDaVVHOZI%NPLA_iDw2+^|U35O9!b#mU^1(T=Gt_=82 z`PK+`00BTD6UUsWYr4y3p`y*|^39vS;NXdqogF6tK+l)wj43LsF|gSkI+F#_oh`~r zY~ZC$J&Wfrl_bGiJwB6<0$?6v#MlqM{lh(bwoGVhc;VSU5pCe+yFc2ved`6wuiDdo zf>A0OfnKJl7(k6^;30;j0mnb|*p}tDo4rr3zw~Z z_L(^g=K#Qh`HMn>;a~pvhoAexXRNN^U!VKSk$pQbC5()~7re21X*%MN007hwco@Zi zqQ+;8i$AS)X;kgLabae!C_1(w)JPBQ(?A`w;>lFGGPl=J%p3-cF$UOp8ffJ48bl*Q z(!e%SR0ZbXmQN^Pol(Sz97a)TWBE$6%v+?{FSYp;VdF8VUfu=n#Z&xlI_j#SQZqHp`x+Wfp-2a7#Y!df_hrhn=#b^6dga^Qgee1#RR@Mc> z1JOA%nt%V~qdj}~1}lP-=FFWqZHDFby#U~=tWLxup`PIx^HwxX?C9w~0izU+ylPP? z0aFZAMHXzLX5db`v3n^+11mECC`!i8gi;ABjArkcq6?x(n9e98RM&})dCqBd0?{cu zN1FWL57}7irD4%jP2_n1&^2AvHH%d^bnIyBiH_^8TIq4mKBK3MF+$*Udlib(u|xpi z#XWB-XD(esl%}%jwpTVxZ5-#XpR{Gieol=|pD+PSzD#Uj#2f*9{h_bRxp>Qj`cyhg zboQIaA3xOA{g;=v%szkqyv3{D`E739+s%t($F4+eWI*xhMIV#^fR@fORr~Mim>lOq?v^#J6Xv4U1T|FHOX3lWAeWEB7idubrttd(uBXbw}r~5uXYxdk? zJ{}qFm#hwdMfHz=`tZq)zPAQ4F#rJ3C;*fwnm&&h&ME*GbSalsc@%Uqp4i1K%U-u?D zgQ6!Tj2AvAev4elXRPpZ@6K%`d-j#nqp9^XP&1SS(|@Y*wpF67XqO zQUCzLRJZ5(ikK66E^B6QjRE;tQ8UmtfTBcmQw(`2`IEyV9tR{f!#x+0s_+t{s z&tEvl<@7Z-HunyO?z#6<>({Lt?&|@7pZ@Hph=R{!J>83civ>>+0Q95^>B8IFqe%9D z4eM=KzjepX{cf)f0MwkE$jLs3L?w?!k}g?sQC3kH(GInC9^Cgc08k0!W$l3n9+Y)D ze#%TikQl=rTRCEA?TQ0qjADk>zEmeN%z1A#(j5uw3{i>&GIq8ktqyN7M-gKjPUO=* zyZb#3Xfm6nL}$7#r*ny1L9mG@yCTU{L8a7gl{C!Vbp2(iaKGE`1ULuOeDDX+bq**1 zhzRkB>5O3`785xE0FE9$($m#<HT^~+xpv^+5`j2~%iT}A_# zna?sxjW8PFvWO*0PY$d+XSDz?pn%JoNMt34%?q@~?@+U9Jd>L`p(0aM1q)wQ;VQ~8 z9&<3NLALpvO|;5n@0d?xWdAggnvrJQK!9<8u<)uMG_*U=(S`9AphhI7r(fJS9FJ87 z0?)p*Zpota|LJSr)HG5k7IjJ(1A)gpC)g#+vG(KF-G1X`7hY-+_<#NSSF?Q?KnOTC zXL6%evba57kHY~#lbN&*pekxnmUr$wW(=G;Ub^74A;bh8OIRor3njiX0PtdYuFA!7 zUd_kd2})sFa0-R`o!9rW}Dp$2%ph$Mt~76q?4IwM5fs3^DI7p z>7GM}AOfje=G|@8nM|sou0bWWfpO#8I*(m^-L)LB6obX9uB)zX5JYMBp(F3{-gR9o z%DQB67TD=>jT``ogi8z$6O1s22z{TQJcp38vJn9M#(tnHS~`na_Tq2XB8?Uh8#1zgs_ zSgt1ENahR4c)k;W1Ms^Xc9G8%)#)vhhll%h?frMVEC>@|+*#dx0LbMEk3IR+Z8zQk z0Db-40I*`w63HS?TQKkA_k4O_u-|XzeGSd_)QPFfmt3=a5nzE5ZLq&HK9sOlG;P_v z0~`DI&mVb2Q{>t@ucoT`Bvo{op#L+5_WD=1>^pGS@A0Gy=^guz6cil`Fqk68j~r>k zT+8^$)q%>KT%ZIvj2Yr71wu3qp@OUdz>RCJ-L&~N0I0009_lMAYuu04Bp#Y&3On7undrMs>3d;j`?rt83AMc0|mc!U@R5o3xuz#KvE zNsJ}vbuO6M0sxv)z<6wF1|tLjY))6_V0g`%s}Hwz9NW9+{d(kXZy=qFIjb5!ckicC z1+7?=F^3RF7Qy0kyMOqDho5--kva1h1Hhl2`gJxHzGT%^)%6WO{?DHkQ=vco<~LVe zcb()4KK#9ZM`{l99M$yGHjlSA@xg#&Ae;k$O25_PwTBW}0H_H##?|}V2I6ScewNpm z$L`p>zqPT(mC6?0_X()KofuVV$EvFg*3<+h*VR&l{`lu-mMoqp@LW?}-KRhG`M+-7 zI%7hEMwKa5p8gatEvo5xUJOz_1pv8pyrZkXs;2S8V7XTF`wu_t^;RSjq5i&3kIPq4 zS^c9QeW$B8{2{EiXgtI7oX0)F#9e*y(wlF)`|yF+BZJYpX>-PnYwYXm`R4b&|Jz^x zicsvZIR5=7-`~4+eTCoO*>UW^v0jJMcHNpQx(7O$;IsL>k3R9+rOOw2+}_{)?n(2U z4u4QB<~ok4d8h|%#3c|#o_f;7KZy4&6$16J)a_)tf>m- zd0ok-lY;<|NyfsVuJF)Mp{R-?XJ*uS(Q?kjfAC&BHCP0cNxD)jDpcUg&^(U;V8X;E zk2fe;U5JemL}jOhsFVQ)Mu;Bj>`*v?5Hx+t^urx(eLa2L2pwZ2Xf@Mol2Kc0RtDt@ zMwJ9(z;uj(GGgHnaHs^4Fd!VEKr{}3;?p_=nTogw#y}I40mtzTP0jP>&X=+gmI;%5 z0RXl<{#~2P)--*3?UcznE=P{9{o!{2034n%aa`5ZDHklg1by3txNyQK+hNl^Tf*4`%a3F3lJ+ zf+U^R&5D_n7?Xs=#@-H$E&Ce5_ly*mD4O*|6aaP{I^5R&?TSioe`vsVpj9JC)nu7s z0KkX>$5bWnw!3e<_O=brKCxxfj^>(~t1rEJpy%*YYhRo`XLfDPxI#8p$mQ#snyiBD z+N)Q$9Xpv##X^ImX~Mkf`YD>G3fN+EIREg+M+KW@(W3d&XU%!x`4@)=LZ!>_Ne-X4 zLJ$zs3x01fm(HqM8D-K8zaAUF+6WQL@FL_~5dZ-3iEyvOZXIabrOO2ZT%dM5FA4xm zR|{0vF`#@dFNro0bDW4(qMV8$oHOws*ddtx&kzHErn(wV0HvT56Zz6a?d=Zbvg+)X z8E|Hv21b|xvblWC<0liI!;;uPFjSV*cn3#ar5`xn=?z*f)}ov*=99;d_axJKuls!~ zJ90Z+a~CaMv|tHVmEn^IiV@2Z@B<^89BcX;>9+lG?`t7rPG`PW`~ z`Ayefx9i}+&9AH<>S}uzSK@QJw!XQexl-~sE&v7-Ck1c3;U)weVepejzD+P~o;G97 zwCU9q)fnT}lkJJf(2QAgeJ)o))^_hZV7GHKrng9l!*n-MKjF&}>DJ70eAYZVn$TQ>Z4_ntQ` zgtT?V2nDCRGn>lfGvUE_vVPK3tFM|XmJ5_V^Qq5Fnli1BO%4u+B#x`CZ~X4V-;5{z zZ@RfnYo2iT-S_O<_xilKb3B27POwU~Z~n(44hZ=XGdfG z&;2BAK{< zCY1t!Y`$Dx7x4R1iL9=lW7K@`2csiSZt3VB2nReatIsayasUvh@&`)&n9v!!w=$p{ z<_ej_;Uk9>9o08Adn^6XbTS2JR3e=*V-7FyJdXzl`v$`CbSj6rZmJPc5&>X1nzUND zTW+{MFY7zDZ4W0S@A?K8G*mWM1)RZJ$>Hwax>hfwMXPnpXB;j8bUpi4@*}BqoGQ8> zQMVi(+O;up@QtRKb7zg4bp98T3UAUC+To`!8O3&B82M8gH#516So$X4o z@Y`QK_TbmQbIV=#03%tsAQuY{edD2ABK4)u-qW(;B0+N4tabt8C!Q=r8IM2p-vJv2 z07WKVx0FZ}llc$HzE=f(z~e-Gq>%VnSH};3_#Zx>E0#=F*N??gs49CL?t`su-F+R2 zbirHOge2!rA9+O8)d?;0;?XplfSMbdy?)=o!0@#3Eu8~Bdv@*xP1gtk1Q;P*CrAf| z8N!(3kRXbCj~^ZV69e%`Q##T;Gz#zV_->S|;Z4IT1d`sQKUzB=C|X0f5eER40{) zlSC<3P$f|+LMC5OheE@EETzg6Q(S(eDYFrU@*MC2KYzg-#9M&zy+eI@HDAIBut_Q~ zP~(=lv;XPyUoI4~7D4RkZ~y*xzt3Y17+{{)@+tt_dhHbrmF|g?Ch|7#;yDX`{p&}& zhXynbA%q!2sv)1t8EH}zeYO~iB8sloyX`FvE z%1f3{qu{dnC)Uos0gwOyN^aO{h>gfHr5Ir(@O?xMAz- zuWxuE9Sw_uNDVy1)K)N4p=QO?#K|q;Wcd807ryjAkKb|kXS%yXPlui^y_L@96iq=q zzG>BEbu|s4kbV72>)br~$YpCV#?isyBb~j7Clkl{ZK4ZO-Gr!;! zHKwUBaVrziGQKsogaveTx@5FD+=dpAK_W5*h!`7t86)%=v*L-4RTV~*=@@hd7DN3R z8EuAT}o*XWR)U90;r%a2d(z;n1RxBKBJ#pQwck8;!^Bl(^P1g}1 zi@*~G?Y$ixq25{3ra$}QU-GexrfZZ@2Fz@mT-3{ui`jPE4xB72NY}v_FHJ5Y${^k+ z@gk*KQByM6w6Uy2kK0Lr0*B&5aet*3G(Db3Io!@rUw?U_Y2{#Dd3_y0Sk;-s>GK3C zrZ!GlaaFbCv};5Q561dCjsXBqGyN%ARa?^@8v+1LRnD3C58j6|NQww!N|_0lW>X1O z)@o{k!?AEIo48=nOs}uS}vRF z@9R3=)~>?XgxkgqTLd02Sa1>mB*_f`P1SXd#-_3(e6(GT4ZaN?;&Qh%)SQymqZ%W6 zCYK9GQ$2%;R3bXpu$7v1qMo1XmPx|g<9RR>&do6BzH zPfhO1k)i!Z4$|tz^Dnq`@!W4d@?TF3oILyvpLu<-0%LyOiq&g3t~+wHb>&4Dik$7u z?OPR9d*Ow(tFF8<(Y-&>zB4p9kjzikZ9n$KuYALN@pq5>1ON&QM4$!AM6+yL<0~3!KK}7f96EYr@}y~=zpk-DjOL=X%dODtyhXg0EmZ^rEUkgbk=%WC>)8Et0?qh zE)@X)=yH_#l#kS42-F|tTZ(>wI4X>_xs}6#E#9ISFK!`$Y*?Z7Y8yW z3IH%QCvjL;^Hgx@vK;R_L5nF(mVxLzW2eKJ1phr%w^|Su-p;~*=AZw0Lepemlp#cQ zT_*$>6gBO?9{E{%c%XKC(?j3-ekPj%#2BLh=qnF?H8K?W;sc+b&^(zC%JYKVZvVxv zpV;%p>wh~po=j&`$%3pCZj|6+ESE}V-a^@UQgzkPP}uAe4ggM()=2!L|NiZ8G)+0o zI0OJhSI>^pVGNj!bqoII$=@CC314&B0szQoa!BGcsRAK7p)@o&%qSHxUnr`afDxhu z7^A@9w7_#b<6J>!Dw)+(-Q#s9<5|Wi!=Nde&1Pdm36962mB%=&6xAM!2!sJeI?*i_ zjxwak>Nyktfgc1wmK6YCB5(6LLcQG>V*pST8VuUJJ_n%$VLnro_jPn$_!ewD1OSCp zjJMcSRkvCsPQWVF0YG3Tb3h*xx+_IRDJn3k1-r?|z!DDtH32UNthS;$;19Z7{@r`u z)T#E`)=ikRTCDb1Y`COd%NbQ#c8N32gXYhgG~QQ{8R~L~0024@Gs)z}Z3p{}vP`$j zX}~GS@3Hj^4DrMnJGwqFWd$;#S5-sB&@v)O90bug@iGhlWLN5S*GqUcr|FBf%(!%`@!6~4ewI8tBj4-F>(v6M^!5axMgDJPrv?>%_u z?VkVuj1fbCfM#{=uYdTH&1Mhy>k9cqIz9C74}YhkzVV8SR!yHdSCm{G?fawA!GHP2 zx8fN}sR~p_47*$wx7&shi6(NXqzV8Q4N4zMr^~TXUo>x^wgdp=Y*CVU0D$DE&RK>ow2rVv6+`VUUTjAmX=DV^NK63X>6KWT{W(2DRj z`aL!Pa01-+weJR|tT<&S=LrCq)ze0btVXS&B-Q zExq90dp~{q9k+k%)1PQrxDaDYRb!(}xtvP!ss^@4f4BJu~gSDeo&Y!@NJrjDca%w~M}a--rCw zPjz*5R%Yald(S=hoZ8y5i!VNJ>cqySOBc_bGkNaZ*%zL*VB*9HS6_a9Z&g+GJKw#7GjaDlR~rVs>)x9X7SZIVC9pyuudhfon*`^(_N)u`whRp(ibjV3 z;QnuZ`Od4)sw7!ynf00AVsvqqyS1dxsIpLEgr3F}a)s;oqu z_jU~dKs1>IfN54=n3O)&P z@!HI%`;bgBk_rt2KqM6PmN@?VXZ7q$Z`o97;`kZ~AtT=^BnUN)Z5$2whx!%{^ya_fCJnjF=qUKT80e(hBw{X^lCUoW<){&>u1 zcSM3woBjBkP09w|(K4H;C-}?6VANuL{{_D_&k-@peS~Rn%3gPN_BEE6gUJ%@( zsDFI@eHsnOiehzpu*3J%bI&B>alyrc88c(H;-DS@0AFRL-R6*x#6Gba|6jBM1p>@I z<;hBm+-!q?)L-eVPU^Y<1_)(z&E|Bt-R{Hf$IK>^&ut5YhGVG|*Y#+0sHmid(+D<_ zLRHKqMP{Hq48DH%-FM%6&sA4m(Q>SFT=lrV!J*r4zwMD|%608k>}L~1_(#>C-pM-v&)w5lQ}K)GE|Nd|%?gaMGi5(17X1&I*A zjB+kG;uK-TB?U9e41*yMiYj9c6j9Bf$Uu@T>6$?~m1IfN4V^J85Wy1XkkmCvmH~jE zFWRl2|B(?QE1@n6Aq$WlUe1v~%xkxnlzQFXA_RyFFql^CaumAoa57>O8tjbs?eWx2 zEb`bh1v8{Vbzh(doS;Cgs;W#dU_^D6$!N!|f_ywuh5!H{07*naRD=M4P&8pGb@>x1 z*`#2M6Y&&h{8x`W$S}F!{PU*HnR9skNmzWTS+&VRa4PbAjNovnFAxR*S;EnHrlm7t zQX!NwD(tFB5++4bn5gk7w|?VpUqyq+*DDAgzrPjZ=l;t>6|X$~=lw@}iP zsZ;~O5kLqb9RvXQoQ~s$%X(`6>erhVUU=_)4?O;>$3PDYR^a@gQxYgb006}k;jL>{ z)HK%ufZ63hSYEzr-BmZ-eDKgQvq^S(i~5H~r!2a#ec!(N@y*2IsCL+*flxFYTX5dO z4O@2_>BR9{kuSP96S;Y)<|$Q7Ze9@Az0)&HlpA^ zp8u4OO*0inj5q;-F+mD1xR&QJoRVVukUt6lW&pwYyqQy{jGef0)4E6^v2glKMOC7y zWPfk(FCO^G{XhEg@W|kf-3QDjQx&l@>IB}NT-^fAs7%9cBe~E$|)_AHgo{M zEVngKp33McB_VtzZbFcq2nG@oTnMBYd~B@`3k(>I1R}MSo>WS6d#nIp2qY6Eo#@6P zz+F~}WKvOHQd;6EEdiQev}VO(ve{&ljVKDII&g*+69@wV76JpO9C5(`69ok4+&~Cn z3fFP!pu<=&HUq|p)oU?4}y?;Hpo?T_{OGd5c`rVs>3 zqIBuv@z;O-`=5TAc3;(P_x)_s`>(w9?nlWK1%Q@g{zGk}v!_)yROiqbO8AMjLvYal zr~i2JoA=#+(^qbL_K#0umOee?ClrhUU@)5LT)SJgn4ET-B$0ia*X`f(MoZIVrb>;KN?HcO_-(;Q*A|cJUR-* zCKEkFu}Ky^G@XT4lwGukUrGi(Vkl|p6qJ(gZt0Fey1P3hM{p?V4(aX^kZzFf1}W)= zJNK@2|Akp|_Ivj4?EO5AzeW%7y!dPXLHmN?O-Ibziq(L-V}%dTRwFMlAG>^dlTkmk zKRp=2B>=Jm!YE41ZGmUx#%%+#17h)Jy3+`GQ(i2%F3p0)MONX$K0O7v!)Jecb7_G@ zuX12=l|r6SRx2cXnp(~!SJipj-15YZZ_-)AfylT*M=_(jlJzlxslr=c-C9W(L1|)# zv;YMWJ{c{DQ-umN(TNQ7cjw@1MC~jyqeS&8s-XrcRHfZZMZP|DeHN~r@$(pJW;`c& zmMFlO-BOWDD$rBU9vk&hoJlcP_$W)?OC%t*sOn zZP;vvd~sEq%i2AUfBN6oPaCq4ZvE!Qr4#};!KeY4fO?uAssLiT$2IWlj|D0aCV^JP zaJxZJ@|N+IDRgRG`26?n%P#84zES;d$GmdjE}hslsbeQ+zIihkUA%TEteQIgBuDJ? zXKcjd_pES-tRN1bmr63NFHA-?(TNd^iNcQfS&khr3lD$w^bAGj#-I<3b|VSi&-OQ> zjwB|-EB`N8w1<)xgoYM7d73Hk&UZ_-ZS_MCzJNVBl7w~dAQ2aH4pGiL1#xU~Y-7XO zdYfZ!T9TF}EcdX~tmxN@u<=Ni;gIB$&e2+qh%DS)iYApH_R0txq+$RC>ON}uEcVEu zQ{`Ba^o7NEP;>a?e6f1BWKj;)rb`*{T~Q5=H6|jP4hJNuH+hRiQHE7yNtc{x(RMUW ziiXoj;s(YrItp4(;X{#e?*y(cE+<@ryjU1OcjtFl00;F>m<7Lt3ZoeUB^Vl!Zyo!+ zkA?6rN33#4q*}O6o2$OP{cibUf~K6iceG}mT+cM|$cLEl=LwQm7xDm5j9bZ&& znI%+MSSmn_fF#M=LrH|7%uXdvz3?UZi1fXU{E2HZ)btMszC7OM3gKnvC-pP3-lQO5UN+h0nUrh+h&ZGsO}fWD-uv6OPy7e$QgRh%8Hbk z&jg63X#0%0n=2RhA_7?d37z%(BF{(J$ngE67U}A3c+yTrF!vTlZ2n0iU^+DV_me;? zY3YcagRQN$Q{UXF*&C&I+jS}SQD(!Z)y(nbbhr+>Elz89mRiSmN3NgO-9}brZqDFK zXZcVQ=lEWCfA#G|zL@ppYV+G z+?%izFsM2#>WjzIu?#ly19o0JM(oHD7D{M_v&n>YV1ilfP0(c=&qyzm%R5M}O3GY! zaUT0uNILd!Y2m2t0cYy?v)H$jDIuC*VHA2??{X3p05e};y;m1!*CE0Gmy5( zn2^;GqFJoTXps?JfnVN}F~t4jtOCfO*sz&$$(b}r22HK$OjafbM3gv;1zihN#7}4L-9itHu_zz2&GSlUANpq0vt1Ipt`(s;e+s=JKeBHQj>*P;?gS< zA1uDG$tX{+t~2buU11@oia~{-*-oV3QA~={cX|b0H1lXK0X&`2lFibWasH!4!?%LK zv(RnW*bFgPS76Azxr58?6pi_`1gMX8TYP~PV13YIRCR;rbVz;Gqsp{mL{KdANQRm&$Z&Z5! zB{he<3^q1G0#%Rz#hkps6^-4Rog$xkK21B}v>0!HhNGq~ z_Oa!+G^ip96@J8~bAK$nJh5%U-?HL(TgOjUE4k)XYk!IV_94yBS(8OA{T1$xuZ zPKi!LMTsjO#I~;i!0{lF8$rmHh`ikyYQ!{D-~kW~wF#}98b<=mELF7M4aEeG-2RiM)5@U5ac~^@K%igX0UQ1uOtX9Oi(y( zSv`K434Ow7twt6`u$lw4d4a8vx7;T$pI~A4gM#SrN*J=AGLz+v{4X)D8!*GE*bt>T zDJqQ)oxNl0J(bcp?nBH+;!EmHCcAN7|6*%%bIq3f1@Zw-v?zE>&mz8pNo?<)c1?kQ z9ghKAxRFm!KjIiTA56O*V~WmAg(QILBgl{LpS9bRkWt=*r~+$oO_)Qqz3(kfi2m{t zu<`NrUVeS@U&3c0!f(viI513*-_EvSA-w1j7 zW2P#yz*0F((}rwdN)|!!<2UvL5`sWa3W8!byM5pI_!E7a=99EhHqAzyZp)#mAR=3) z0b4^Ong3Jw`dpknC9aq#f@#LU)_>e8g6r9;iBIeDdxCpumJ+fYKp5iYm$Fum)#Qew z8~nBkfQ=0wJ&aS~17C!iYGhW4Qy4MvT~FI}Hmq;It~xikvvci(GI72*XgtU@l-T-B zh~wI`p{|x_a{%NOc(Y&)cAT zLGBMh)j)Jm1me_}rg=Lx&AL42fUQE$mgBm={z|)jU$yo0V%@I3PLCdd`oo`6H)TKA zmoRdCtGdvuh=vW|RTLSNV`I5j7}N=+K}IS&x3?`90?p=8N9Ngdv+Azi0N=+-`vMGD z%8Evf%s3qdCTS#n3+GR^747+ zEZf%k@1?PHNqR(pfbJ$3);zljr=(c9sQ1AU!xs^8ClN3y1$R=^sr^bRa4hCzL}zH75hXDV)WkWbg>| zCNEwQImb(o_4_ZNmgSJ74`c@A4H69k( zVWN?)l#)R}NHsVFVg`cEqV<6+BTm3?n0cvFzy*V);<28u8pxEt4Lw&D*^2l|4u#`n zKz6DGfmZd+KY8+x9Hxdb0xzm2VSxIT-P)-@J6SCb~ z@Z#7GC%U8@Q&nAMwW6^ z-{UM(n_Z>>0;KTUSN?VC7Y`O3q*LJFcgwlxP0BIcv77>yZQCXOZJTak= zP|k4tc&Z8GSyzj}W;kV}>>vw{Za?DhOykbS81QQg1v9R0AGT1LZ7^s%_4s)=1CIa! zEML>z3{x(n*EBUyBPfmng5D@5nZxxQgvZtYktc1Rj_%+`V?w19NX!-IHKn*mT$mGJ zkr;{q;agI9{#pX>^SlYLKEJy(?Y96#9MQ;Kb_Bw{f|J)d*2mVgJ1W zGC0J|G?Syr`DD3LZzj^U+T0yKPeAHRS{Eqr{CjCkNl7_|>XpAut1bKC9WVUbgyXiV z&7bL6GbBdGJU+#E(W)~+Y0U~cZ+BC_C6LI3OT@h#(sa>}fG~unmR%tk_UzlObwBNL zY#qBJ^yDz5XyDs^5vXGUbjK95L<}XBgI`-IK+=@3p&83r?r(S;?XSZ}KMZ}Q=2!)M zZ^&tpN$H2wjqKDE{b(i4GPs+eIOZz_^6^j<1}J+>@7vgZIu`F}f5hMo%Jdz#@c8m4 z5wQ?7ns>8!and z!jG68d)0c&bNN@x%BA*2{T*Us{m1dN2Fvj*{|%j^dO6OUlSTg_6vFbw#wioEk1ZFi zg)u)G+{v<*R-F2`IB#zpjZ}mV+fnN1V8}spb2JumXTxSIwlRm)n z`GACEp*mnDk8?kr1wAN!NOu|!kOQ&R5+d>fVmjj?*|N;#{7Ar3oSWd)SxZsk#C~)i zH8LJ2eUouuM=8aWTiy~mTo5u~UY8avIr{cJp@G%bap8XXsy{x!SQI_`r8aF084*TH zm=_cV$zZ)eMy%Gg55^H;K;$H*sVrR_h(92?f57hAJNL!`q0~SvCfhTxU>adCQSk|V zV#3L0@%IE5^;}Zyt~uf3vwpQdMzIwaFSj-WUuJ25e^K@~@TB9_kK}dYHTw@FV=7$j z@>tH)CtO+|bt`&ki@Ad2`+;~-glU_%`ffhSo!{j&e7-isDi9g&hHu~aR2H-rs`Opkr+Y+kXMO3s4QZ4-%CkzkvR zv3tboRh=&nv1-=Z z5}mr)DT!mCl`?rX+OHR11pi@=Ku3+(3au}$uFJSR$gKEIN|Cv^@RwY7f>y0v1u`Sr z+VSpB|S4X!K->hG3iB(ZlF~ z3Z;GRkB8%NWNLto1kNlWy&cvWB6>LHyJV%05#f4>L8V9)vL&$~G7V>E3+c1u3>K%X z@dFbJ&c31U4zsLC!ar?5>rzt%Q>x;qOH z@xE!lP$LA&bvuT3om-Fh9+v)YI=M|<5ySH$T|v(&)c4x>1V3zBJI&^x;%B%2SCo%m zv2_EAY=0fxcKVn|86xc;Xn$@utIXmJ80VXKIpw)_FZ=-)PCp2-*2zah?qvuKov*Xs z`GSDF^OSf?b8|*l0dmAmyAlC5HXxmDPNv1t-pQiq?lG>mp|dib&y z2!r@tMEvLR_a=wss16ftg?AG5p1k#*yeD1s+&O15M@2mICt+l zKrTEdLS|CHkrfJy z6th=qEnfiuuf4ssw5)@Z{KitmZ|Rti)T65FGX3^xbEp`XMk0H+Xg-c~*}EAJ7-qJ8 z>OQ#tk#*E|qJaH+SDdYw*Zup5lNCp0(xU5clM*o_~jj+v&# z)l(1?zkB!Y+}QaAMJAT~Sft%^Jj7dXlpb`Gq-n|SN3Sc!u0Q;qHAf2f-%VSfapxC; zeVuMf96)^QoT#vW8~gR57+VNZr%T~`WdbzspZb~(UB#{n@HnmrI{)2)!AxE!e~xYc zETeFR%x7`J(cE1=leqc`t@@@m2pjzrIXc4n6t#o%7@su!BY)D#t_*b|iI2~2U-l2`uPA|`r+Qd#4bh_O@ z^Mwp~jXO6!9=E&_%L$s6(jthG9O0tUH_OGNpc)c^ObqigoHlyG=tOe{fA2a==AA3b z6OH~tR{gD+5KSv84v14ab?=m@_z-6NSVYU>jhFxa{W}14hUqWX1Uk+@rDVm=&Hk<`FV#FF4TlRV6Z8g~g@lV2ZKT7%A>TCi4yIn3yMbRt%pSI}%Mf+* zh#7RiL8h{$l=;3!l&^^gL<_)O)FFZ~jBdZ0amdLDMn$3KmhbtbK{R!%As6MqH}Mu5 z)S%{4EDY2!t-gJaA`DpuwfKzp_|g(XC(FxwneN>yuH)BQW}E&G1NW0??0F2VE2XlJ!V9&W9dUP_k6y9|ve|s! zb?h{rG3dpA&z9*LE`}R91i}G>OlWZU0*Cnc_fu?Z!vg<}ox$gx6(-t5<7uUOTr)q^ zl`hbKHtupiGR}UEk?M1`m{_j2P`V|hIG}d^Gc`NEW~t^1Q=Q?)*Vb0bs*zQ0_%C+4 z1OpVVS(4Y-?NHmca@ugj9d3H)@7uH*Fme*jA|=yH(;EtB!hf&+6=LYUX#RTshXRQv zf47is{q<%(@To345Z?FOt+y}A+Cu+5qv|_!oN)KR*L#++1LQ9iI@o?`LK6QAV@rm= zP%ravXlSl)T>79s_s$zS-zQ(&qFYOf#Z^I)x~s?e%oC;apHV0kD915}uiZHKHB1zW zXVQR-KeGH1DBWq0G!r1GNIf3UYerR=oE?K+uC~`q$mRF|W#3Ro({OEhCY@kNEKP;> ztLz+mgXZNvD-ro$|8sb&*0P^9zwT?fw8I3b=xV0TS%00dhM7^7z4?Iy%y2>(%^S=w zEyuWrh`90#8ol%`o3XVj>U3E%(4gRa4VYQqDa>qUawA8#c95GBAi9bnu=x5&)Gtrk881UuPrDv zz=k5FWUIg%wIv3x0bb=ZqQV`_J@?G)x5eVM{lC#dj)I7Khph#M2nwZ;x(#IN2PhmE zKMGORY?01a2)GW#kBw-5iK0S*9}>ENZ|%=>Wjt#x`^&YM^-tn5VMr!GgVZ=n3+>3> z?}A?<$ivngANMOtZK$*Gw=~L<%?S;;I0S>ZUMn>nYoU8gE?E4AFS0(Hd@;VuZ>riK zYI%%&^;P)Y_X@t135R?sOIB7%%hN*~NdSV7n&4m*Q9h*aAGtts=6^ysk7dnvy~>niy_(Sk6&pr_a!$Wg4y5 z^H`H(`-{(yUM2kdF&^Xf8V|Z%L?oZn!g-;}hA2rDODLu53({q1cWq*%q}>N?O12#J zhrj7ni-uB{KeFhEP)Y|lQg4$T<@&cgSDbC7+%c)6Sw@I*Z%p}`k?_n^sUrCFjE=8q`P_GwDXqqc8}6t zTJ!;x8NyP%!D6ohCIaRvjJv!}x8R3aHpdU$2sX)U`US$Zw2=UK(I?4DKHWP8qZNlD z+3{w1@Rrv=;=y0y%|hkvC8)Y}V7*!fiAN&$GkWw{-9fMs+d5u=64xa3<=<6m-O`e) z9hrm*;5XH`&!eG<8+PoD`QH!L_sq;TWSos90W5g+rL~m{aQw&)5oE{7r=N?be5u9p zWvfn5YdMAe+eyWv9bFPZ!*y^k>g_x0OksBmDXDL5g4O$016y?an%Wvl87WI^(_cJ& z%0@;m^waLBe+Ry#$Qg0ljj!CFZati4#eT&jQSjfT1Y4$6nuB00aH1jmHqk7Y9!g9E zhMCE!fs=VHmDB&s&1h?>5{^%bJa68j`-Nu`cPGuSYiP~jZ;bMr+%#-|D9l(UYjmAx zn{;sR?6MfkWhG63{c?Qg11vCzG8JOky4MU$B3nMFu;uyNsh{(^ykFjK^!LMIauGHI z71VqVkZ*zXCH2{PqT(N9D5m@?Zb4IEyd4*1T>Z|_s6?c`_6c{j#eKf;hw=9Nk8&wp5 zEchm)yS}IWYW37_x3Dm8?K7)*bz3>M~mx$kpJs9&^H^J8>vg z!E|_Oa1$ww=B_ z7_QaE$H%M1*sN8Xy7s2*!9|>mMX+u%0uBxiyGwke;PKP(hb14lKEMxyMgo-U`XTHW z$QgLuIH-De$0JG!RBspn5+O8Ke<-q%XoJ8|S}^G14#@M%37n)LD`BpRq)kA2$sJ0d zU%i=K#x(4@i;wAoj}QrUbd(Oc{DT~QwaloooxmD`AXbl0$J49&krHzd2G%#fep0KHz#1dE^aoB#`- z?Nl_u`)^zwyNyT2&&##|CGp>wkL`aw__QpiTTN2T`ph)5PEKKT_nDOe^t`wr(_p$< z$6H|(xzfJ3akp4*ZpTZV%i4bh{K~Zj{xIR$)h*5F`FKH^3(c{m)%eNg7|Dd@5CAFW z-(2>Tj)__-4*z>BvP6~MsT}gxJ1(c~0&EQnlJdhqSQvqnR;?hO9JQK5r-V>0Vh*KO z%e?;SH6pvCwGe#xa$!(A5xv`MbfJdO(8H81YpK!xXs3j;$zG4$bCb`bY;oJE{ok~) zZ96@{yR?Q7^3kYv(*B(6z}_{@U`l1uA-?W6hDKyfqW3W~pwU|HBaIqlCWsSPT+Ym0 zV^DH5q9D$H@)m$3E?>BL>31vXZ*d)ADY{px6LVVZprq@pk*#d>OhzJtc*Vp1GjUna zh|&dh+XPUvI4YGK;sd4ft6bR@;dwY!^GJYlLS50HPCsp#SJB%ilmxBzCOxNMoE7Ki z+0fh#V`DFbdi)+X&zC26(i<)w4P6CWCPG7rO^#x^By@V}DKoCHue2k-_>$=0^-gU! zcMU5nXwb#mn+c)_&&bHMK9MMypcQ{gQ=AIUH4Q!$13<)Ws50W*ZThfXCu;cja$flL zih_lHM4+nOv(H@N{aa(A*gmx(B6G#$UA|AViXQDRTbHwRMgTi{a+HMti~!26LIZ~0 zOQ=$XDgIliaX0R`PM*sjpcQ8{w@8Tk&qj-Ye;@_k1H6PjPVF|&kNnY(Y{~_J5lTpI?dNIG><#J@dsMIugIK||Aen(}=M%J=c=CkxDN()3|JI$tcf zpLd*82D{Ovd%NUk6gUuGb3V-y5W}e#m?GzY&XBq{2<8p+x8C>1-(4qs27;tuc;{TQ z17D4Z07R{wdL;FQ71~iTaj(BS=f1ZTqddy9#GFNED;?Vr>n}bxNvtCx08m=2 zbkF(cKmO5s^5w&G;eV6)8&y#|A*suPs zYe&gDUaD81WYl0l-_wAM^5IHS(j$jIjizmIP@+fXwp;K%qzq{z)UkRs>nE4o8!xVxV*9I zveQVXkh;YOzx|V0+^xXC=MzyjulppPk2>|`&;P{08Jy_A(R@|c#*!Ygj>_dftGln3 zFQe|Ioc~afh(i(0Ywa2rWru?ES683m(<4vK!yLx!;yTHFD|O?jUl4=HeLX^v9V-lY zR+f3#c+=!b-(IRV^=>jTd3^g%Gx@P6m#8?bXodh&6PSc6-KIQ7Pn-tn(EuCUzaFPT zKfhr~L=gf-_yY0@wkr;8)FT#se%+sbpoVNBp<**iQk9zDc4qD=RtMN^%TU-KAD^@x zx0@GM4r?CGBmO!aOD~QsE3N$L|KtfT&7CKWAMcU!9oy?pk{zF%7Vr1rK$qx`X#$pK zxuL*DZOenq)8-ToTIj$oIr=GZVzU>;#wY8th5rm-wAwa$S;0%D}LyG4Ajt5ySm+d9}^QpN@^Q$*Fhn=p;7uMOL_YX3;XKz zW^({ztl4hLt*y>$svTu@Ko4oNzNtrZNo8qLkdAGs>vF>Jbj1S%EX^XN&sQJ-6*;;R z7!k`zz?9YR)2l(JJZL7YYL*&+GR~t0gb^f^ z4suY1$rf~0+Vt!!W(OpI@P328$EC&tJz}a#K+a+66a?a8`ux&34*v~56X|nyS|d^| z$kII@(!!is-X2jL2sWCMIwzx#(}}y?nR(tYDb4zD%;QG(sll(%KL$l8v(v{-*W+18 zz1IpSWxmIg7XP6}ve$3g!Nu)HP~qSvIlyN8%dqmS!+Y+`!W7RNtCf`W*0{!OdNV64 z=0m$djn1{1+u_%kw;%YAR=c_yEGIrx9ukRh9lYKny|#Lvtxauqo)aWpPIR*1U!OS& zC4ypspxING-HDk(7vN__1)08@v8wL=Wzt}&rqeS? ziseq6FoT2BQ-NB`=c3tXr2Lo(;_bThXdxF@!;|1p)arsX0%E{G__1K<(#ZQcQooHUB*|9J1da;uq_p_AjGhN;C zzr&^v;b8?}9I|7Speb3fhJYwP8@L91{dN7xqC0*u8;fq$d4AqPIUQtR1=XYL1JdSN zn5ht`lV!n*EEfOu)7o3Tl|p+XbJ}&bju&t^iqU8QV}3eZh$`sFjR1^? zKj#x>Hw=Oqv*fKXMD9lwhI9nUEUkr}mLe#If(DY3EI{&ytt0lG&!=bp)jl(cXr_8? zK6*_Ra_Vaud%uYY>`?&X)&BYmDo}vAq+;w? z$IBOwA!LeDih~D);ST)_EXXY(2A)#MPy?Zh?=arvDVDFb(r^e?f9d_JdDh_zPY~{G zNXAOJmS)}nnU77ycqP$G%nJT9m83Q}zqz&4Avn?6#ak65^>au946$W{2w7;bgSoyQyR9+zw(;sko zmmi%6`Xv?!pND#~_msJvN`9O0rFN;}L?-s1qRm-jrn-ePHrBPh-b)sIbQpfs3k_j| z7#OMZc@JZVMskMG{c&-6weplnbKU@OnJ;|yMl&LiRnQT8r^Zh!8%@cYZIY{+ck(LI z8~t|sKX$#$kxI>h4_Y_=9BEXwUTyvNu}!*=@Aw0~M*89n#phS&f$(oFipeA(u!%;) zUdP5v+K9u}8)!OP)8J(W%g-U&fjqIQ;!!;7)GN*p4=g`0?M;sBED zuq{P7VTN@$0){hK+^I-4^?SY}%Y;}Wz?I4K-^k}#lV2a=w(~JbC(=YbpC6J&k~2D7 zwjXM)m4FSm6cL?Hi{raJGir8sgYACu$K$sgo^$1j^lBiquWQ!bKr8qI$mzS2xqar$ zCdtgClhZ`_PZ1~T`EB?s0Urg(Jgho1k~3_^qX}N9q&xswwbj41ne>4OAHaZ{C%Gyt zC%m#pZgODm`lx-k0ghzQVkTzy_3O>_f0SQ+8@Hck>%b51hyH~WS}V~Y6GP>28{b>B z^%B0C|s^4}IxY!O8St~A~NcHD5gl<}I@yV~<-HXO{;!SbpyL=d(B2p+ueQ3319>&JXo^ziw(%`xsrR#{eO+TRrKoPi$ z@{6W*%GvF-$(uN@2TXzDG~IQCA9bF`^$U%R&1bwEbz8cM$99;s5Q<_+^QGhZ^ZOH9 zIDee+CLSC$eNNlGN!l9{h`h{LLRN}k(Rwc>&rBTGXF6&pN8)wcIX4}?=dDmhazN_l zV~16C{g>1M>j5bvkKI)xrcb$9*nRq{;b>l*dApKG-C&-~tlIiDXGGIT)lhw%w`F^f z9k5Ch)_1CJEF7>qkIUp5C@;;pRAj3c087Fz{`||!aPyb~AUaoH-&KYRlymag&e8@Jw<>H3PZK(-dprmR*@oZ+`<*UeG>Vncsl|NR9N&h@~@S*9`dB53x~ zr^yDJlcNTu?da9-iLYxUsko9mAmd>y+^3WBB(f33}=5#fc zwtA1&lmTz2;Rt=e%V!(i&vy?aehh+m4WY2 zW+_y*?mZK}(uQ&4D_cDO#*4CIP7-5q6cE<_@YR!l^y}imX`?db;d0lbJ!{3ccZ)kL zWiE-aBPd@m@STD0(F~&O2kj#c0(O*xgUSjs80xQ)Hh&W?!76My>9%raHF9yLc!Z-9a)?MewT$h+ zvx8Cd*8S$&4K%FZ*r{8N4BerlBbIgfJP?DS5QF`v3T>m+dY`XtgFiqrSBfjzYRvlOX~898Xwx*^lbuMuF4~=? zD;6B=HefjdWdC{#Rv=L;+4WbFd%RpyMpj%74b}rU{+VhQ;)21TyH62 z5VVFR{V5l}zsE)kiKe$UZ_*Ecgm#9(1z92&@@_^UMf0)IUY{wr8@8R_lR!Ve?mct; z?sMwco}lj1)DcWN4F=hR;D8&SJ1d@j$MY=hl*ljuYfUMTV?&p|B^GM z(CPAO%+LXO|3amPPZMy03;Y#9TU&ERMfG|m9J8)iQLYddfWQil&4vQ+*H?v$XAf~h z9wHvN9oCivJ+{`q>AMoY5>mZf3UkFGqe4a*6`u!P{!o0Vy!sl-XU$fp$O}1RYJzeo4-sW17Mw=szCif581R ztK^^J&8&&E+uRm=@*|dDK->VocTd5*vH#m+BmE&-Whag#pXJ}ZBPWh){A6Zw6H42VFMhwlKzD=d95SuAs}XC zh*(sCk;|+mUfKY9k&+z=&$*0<^MY%G-s|Mxjx(OG5B8e}Y(2?v*V5nmG=D79*{I%q zdpbW9G4y(Ask8jt@(^E!MQ(p`a+)sUIDRQ3zz(rtE9dZfZjf4Pz#B_Sn+LEY#Nr2W#sl-hX7i znAdFbyft*2DkPAq42GCZ@1$x;iHplNLr#<11nAMwhChi0rB0Y*N>2Z_>3Ws99f+UG ze%{(gSH-4SfoYE1b;YY(!sG1(Fj3n{qgAJbRnubr%Rj3wW1!iP8)&}0sk)CYCEy=!FR9rjI^xJI{jemtjWO^A_@+RWNBz@h_xl-;UY=l3oziSP|9qCc)2Z{GS{W; zB2_&4wE7V3O3=K}RQP_f`KinKITRtn*0DuNjZBknZP(V5@^_tn=c3(+d?iizOwHzdRJMB$6tJym6cIQ{LKZ6k&=p*EfUI3WM}$|*U;3|_;KlWX<|Ou68epu zJ6wT7ECo`F2tuQxO8gYfnNO@VKEs!Nnozn%K`xDpd$4-FUD*^6^I%#3hqHL1M7_cG z%rWqB8AK#=z7w8S$Vqaf@E*s+zG8qQ%+c}Wet6cnM=)S>O62Ww7bfs{dlKlop&6Ds zWaB*V8yisXIsm(=$#rffyYa90)SH2d((X9%t*yHgfz77nEe9a<38Mw3#B|DR2pDvQ zg{f|WxZ`|#4skN7YV!2sCX!xiTW(YsQIfpi$gq6N`kF=^LnB96pUtNfXn?Uue;8!& zC$UsgNqJG|=JBjs|G>6$`k0oHE;=BCMLtLDIe)@q&;%dX7cd&o`NKuv+CJ_^M}w#M zvywGc?R?MbpQ#_3I8ig1M@(PMWxf#IZlU1R0B6ZuukX(ymEQ~+(qO9gAdrOy9{4Sk z9$K%#a_ZFlN%U9Hp>BoGH`G{~@6fRO`e9H!HNO}yzp%^e^Q}UO8Eoc|mFe%vaW!A` z*3{(wm!4NV3CTzSPJ`*hjEc`ioVs{$#Vg(d!@E`&dH!14Kv-Y>?#XRWz)-myj%aiq zxu6$Ys_eb5{wHeM9=P4=mNljBXI-)7rr^gjMxj4zxy&k@zQXxF3RT$0N$SNDrx$X> z@+b7Bu$jx__f2G6Wwvf3X(Xe&M}r)}5i2{zH*P;57c*5|A@=`)59 zaUzztp+lHZ)!|w{{>0BeN%$%$CH6?Iy#MBQ$)n@3U3?pe!=~H&e4Uk@9<)(!)SzSe zr7;rCANST-YdS?j1KU;ftw0?|pMT%q}RUOZAog|^>j>n03ANzA+sPxMna zqk+JYT3z24EYa7A)yN{;1wQfoAu9dB;`sMj^#HxdYd#dkcKj8^?%+~?J zF-LfMYqu^W%+1Z=@i%Yr8*@JO$BvhNnr>02?hp$^$}bL=>7Nlr&7;&+|3Lim43}=Z zd~c_}UN)U9cpVR(?lHNZU^#N9M}d|5B?LUX2#Lu2{{^q7jwTcGvqcc~dU zVJ(~Jihi1CzgD{}&|`wNUN#vfRVKjNmn?*xEWyPbL7sbUubvH>A-cp3og$vKw}2$3AS&R~c`7}6D?S~> z8J$;oz?E-Sj87#BUDa;<;xS4c|{Zv?+H~RDa_ZymT@0Kq38HoOtG51VewazN6EoP1|9zPz0ek|8z zaM}CmIJpHjB=ej&nQuP90z}Eq*o)z?^pQ|HDZz>FgRVfe>qv4D)7W)G!lQox)Y;K- zf+p@Y+lOP`Uf^+1Bl%z!&kZ8CK_hS=JCXQyB7;_$09i@cE(MoiiLxN@9&j$K_78%`w4Vinor2~+~k9;VGB(8l;}nX>Xe|TUelo5@rV_Vr=*^K1V0W^rZLP2Nli7@%}&KVWNUa7$4v(m!p! zuR+abso%fb#CEvR;row~JmMzP#@^7gm$mduY?$=C$h{g|A1hhYU4I(yZU1a4v;4>f zl=Ve2ne)?t;L1rhX(ogMU@&^vxuCJg>%QDN$-FQ~6AZCYcebDH`}}e*EZ2ujgS5r_ z4o_JH|Bz7R@noO=g_A-@F#WAK9|myl)INHm^E&DZ{2MWT`Iw%6mrzBsz}odXdr215 zw9w$yH+_ASeg5bVRPSsl%o+HM4SHFb`I*gK5es+(E~uzqZ;?6{xqnI^GH5hgJ5O$` z5b&rlsD~_O>~;u|3xyhz)lh|Sq+Sg*N_YnDHhPLIcthroh`3-3-!zTHz*j6kUPD^` z{a3{6c>nO@y?jTaO)EV?(rh733$8aE>wn>7HdV|V11WtD2&3jD^wKn+FYX+l%V&){ zniS>fIjo0vub@!ri7Fi=haU(4m)tNO4~iliQ2iebC5uky7K|aw)}h?SA&aR@FRCd_ zrK5e2Z;PU=tjy~ql>x3N4MYJX426IkTOav&uY3q6G18_NGr`rjT#mSTk+(WNa8Uwd za^D0^$t3E8AnjLI<_3Y=CX6e0!+=FP037+yFWwt(lSC~+Z)wg=bHt?&L}A5YvXiUs zg{|s^l`N0AVLTmu_?pJiOuT9^TlSEK_~Lgtc{KBJX^UGYFk`coL%*Ar}O

    • %=If*dEFb|z?xM<9DDwGc5UCq+a7u&&mTJuVVT**2Cse7 z8+qqjeuQ)9PxIsxPcK_=%FIgBA^9(-T()RF%9D=MZ(O#6QqE4+72&OdJ3Aa(laR!5 z_*?w<77`CmP^>)91!-krUQ#++PAQdh+R4&}mG7K`+@YIhKc~wVvBouM%6I6#!HJVw z1(1{~qX4z2O76WRIDhV}@etWwA(YLWUKH6tBeN3J?pkHv?|F(iNeOU8alKwg6bb~n zVA&Z-8^ip<5=oMh&xbS@mxy$P#nD7|-LZ}S{!a1buYHq=*(Uh_hSzMsh!VGEtIST$ zV!QyICd5gKRD#v3hv}?T7`t_w$*CDqA<;%7u}ECgq=do>NorYc@TBM5o=mLWgfno> ziWLwyBZ`F_VGy!r{dz84zD%`NWofBKzO#>VA%|Hm_XK$*&}2w{_8bTx3_~uQInC1K z6dU*Mqv%VTiOw2vGQvu>PiA3hLJF)@6!UrJYjrG^wS8T@@1Y0y+?T(}%2(Zk@$)P+ zBg*A6dscMt-o1CbaKU_@To{tZ2`?Ny$LIg{TVi&4lIgiBOZA9P{n=k)wC4F^7r5`u z4`UlO!hD`jede!;mS!0npW^D}QL(sGLwG*rT)^nf1a8 zqC^v?9^SegkTfy%8lANzW^Y}mF*k!(ZbL;8wpk<67Np5ysX?f4`PoB&O&t;~gmUKy zAahO+7FIgx-msOhe-N1~AfqN<{O$pU)=#r_?>^3-JjLSJb-FwH2>be(Xf*MyB@_aU zYn%l&DlHG-_3+$?@Fe`{b!J%q=$YySiyMYVK(fa`_qszK8WB zK`tbh3&l78{xRycng~OmAP6(S!7@HR!Rzkb!$*Jl*RiI-{^y=1X)F;{mmrr1VHhY2 zqH>;8IP2xW^PS+|NR%I9jMLaP8g)n$(x^c`4Ux@7Y-0l7&)Lq7P9c>~KJe)uT*=tY ztBhW`Kr?oGNScrVAI=EC^YSiB1!oT|GR+tQbkZb_>&tXSW3%%_K$?OJ6wJ{7)_JkK zL;fR|wfNF@{?lIc&v(7j0Q^uarHu5@M9w!iwZz5}TT53iq?)F*`L1fnDObccO-3Ea zc;3cZ^4W%)4}Gk)BuVPT!qz$ueq$&E{&GjIvrRFt+~y;*2d}B!Oy2huDnp-x?B9}% zZtwkofv=xA6qN#ncBUonpp%eC6XZM+;|ho*)#N=Fbf%O-SSPqkMSyS9<)0PYA*qB5 z4AaI^*P3ROl2;zS6lkej6Cf3yA7J7by=p7;ts%_iVOa;^{_v$lW@w-1d&I`shidDb zYFbMONuWHMMiWR$CGePDsxp7<5aanGcfIHR6x!NZ93RK`JT~pv#>mJie)OK5Jp9mW zxj8-0Vn*{>m|s9CpI`szhp06gOy0Uhp;)AEU?(S!pP;>5Kq^I7TZt2g4zp#~PGsP7 z_~1c0x_TVip(IK;7ay&is8{(i<3n19w(6GH)CHkoO_pQ~%4VWYDe!cPwt{9xvXQMK z6epr~h_GZyI24IdDLuDk2O2??qg@wP6FbW|LFrF0gsmZl3MiXNhJ`< zN8@Ogz7*NS)FoXb1v%g6^5rXxO-$3-+fSiqkgnlXG^Jvx5tAuC5W>+aP4>BY0{l#T zI#x}oH-WhtYuk&|W4%lZ^Q0?MeI-%K!xNS?YO8KP$rKg`pqeg9Mp7zde4v$Xpk@x%v_wU`qzxl(@aq7}Fl;`8yl;_S|hin=cH6tb` zCbNtajmR9VT)3L&Y-okR3YATh-2E@INsQ-t6bc2-TpT6c{d&^X+ZkWD#rT;Mtl7Sk z!j5&s`F5_~o}k&NktQ+ixd1<^(U_eh#>4L(ATE?KQ39rknx7^}nvULS+ytN{d@{x$ ze2+$>fvqmNuPX&op>latzCaojh_po*D0Zx1^&X$uD;GF_`V4*B??9YA#r&z4=-9cB z-clF!W=w*co_QIv?+ceGkF^NT=gO7q{O-s9l=k*E%Ei2M;=(X9J;UVO5_?|rMp7kd zmkG1R;**m1Jfzjk&oAI9kDJ$Ta^%G$T)uLhzTR%~`5ao;oQoKOMl$7KGfLn~i&9FYX@c(u z1c4&1Mvlsp(eJ?N{Bk)5PzWK=X>(a0B*@awjdq3t%Z@)UQ(RkCLB5}z<5@k@+9O+2 zyyaoe@@e1F7}@3Tm95WL<%X6w#{ZwMR~mpHg5~+XkeM&Ll#p0K#Z#odhY(Qlef$j7 zR}!R^C}XMQd;$T@)S-jc7`&)PWnr4BMnYw9m9w+6SutmvQ%@`K#^T1%j(6>z1%ngw zwuL@Rx95oB1c7jK;&t^bi!9?7ikhK| zO<^*Z6G1geiLFIg_qEnm5D4MEE}R%vSWBF03ZBQ}y>G<|#qFh-wQIJK@95#`^UqL; znl$5txmv`~@GxI{_6WQ0-bX#rjNM{rXoz|obN=#GCg+xT%>(zbJ42?+#S#I~ zRtPzD>;%J`HnDBz4(i%2^M5shAiE9-SFB+j$J+=HMkBLAUMoeA6>}Q!kRU+`h0f?J z#nfV?Ae1&MG+bjTvjWs+c90HH5*fOib${8RPKI!`3j2H(=@4fk^A@>7N`X`!)(RvE zo;7ZAAS4C_N|Gc7li8fMxac}dC015oaKC4YhgBX|u8m^j23xmnXXN+^l2|jidL=7X z4)fB1gLIV3Y~6DQ$B&O->P^BRU}(cSOx)z;nRE2saSu^jJGG8M7GlF-`wI4K+sX^y zdW6k)_OoK$TF#yrq4!PiKfJt3(NY+qW z>ug48O${>Uflf6dLrG1`3JI1EG>7nK8V%u6qOCE@h*(QFt99yf0?^Y=npqAK!9qmL>LTn^S?C5SeFU2N?wtRs|2+p0ph|(!W2oi1Zd{>YtDG-U%ZfGI!f&fWY zuo^>Z46zK5!jeiycM@nss@?aS6sbI3_26sCb#zgWQZYJ zlCGiOeaBAf7V_3r&tQM?C&=XrJpJMk{`|||VR2!JPk!({ zJb3pWlBj_fgjBU)`fU$!@WeUJUb@C#J^liZy>x+z$P#pRJK=i1$leEE%e9k77(IC$ zTW?~GCT=uIwIuXByda>~s8h@ngxklTr(?&f2-@~_I4H)m$-5Ly8ZeeeOheV_aJxOwT|v$j!*vKar$}(=q?5j zFHtUbk!sE8wK1+-8D)HOj@kJt9qnauVMxA^BOiu%QgQC;9KZkZPqJq18ou?N?{fL( zBAp%m)GnMNiDUHAJSCY@uh-DhBcIO^D326aoSZ;u7ra^1f;ehAw?E}kuT@#q*XDvO zg>}iw%DH!WB0-X%{Jd43FXDy^{jwOej?g;B^YhLYSV+>OmQjN;JydI2DI9{B%l)71 zy=RnVXMOJZd*7W-u5;>C&Ygq0)#{*DD17%d}fec^%fe+aK{*|xP ze|uHj|C-0|8i4-^j&iA_eBUQDB!*>?H1zZ!>sXP#U58XzhNK=Ul9r;&P$a`5{l`v{ z?d-vB$dHo(J62}-*I(=+>|6uU4KHp*n}KMmXh^*=uq5chMPQ&qw$hd)my9tnJj{iY z$Jw}bGwD>4<8zB7ni{bT5qSo{kpeeVBrJo4xmkn|WOF$dYd#@bjwB6(a?RCw0KD+r z5)eV4Qy0UKPz6|)aWOJ}X-zJKZXytnirLgWA6p2dX;O@+D0*vP5JZKEkdkU-&RjYK z0zV8Xg@G=pL^Sb^rV*xiVRm2&K^=i*7*xXmGc<5)i`MoIK<5pdoh#8~IK*4pm>wM^ z-`>H8zW7hNp)f6Oc*#!w@RMI=ezrg+8Ryo!K7pCcaM_lvxCajN^fSA;>Z;dqyhb9UtU$}Rmh}8#R4~d&N}}JqmQI-v$r!}N z=}H(CLQ!GEyjXk?| zlS?GHWXmRw9y&s}SVo$X?zOA&>NWNsJH_(Lufoi=GF~WBUbU6xxJ@c%@$38U!>Uxc zV&~;N_4F>V9Guop&Xof4Yd4ZCO)`1vI8%coSZn&oWitd?q^eDcesHm%7KXTJ<~0l> zlFjK!zVCV3V5@~$SY~9mh^FaFa;YU*j{g1lJUV-oHpKH{hq2$HqHKGB5Y3fvC8BOyM5crYA$uLkV#4;nSC;B@jrNnk(XfK2| z7)U7)mKl8x64NlW<~~p?ma7P9kV|4_TWdoS3Gg zt%YPvGCDSjna)zHxR_xGmO(KH@zH|~Qw7-4AdH#|hd_H_gn^I-zLXF;qzs7>J$I-e zlwkM)jua@V4Z%_c+K4LwLPB9uck3MAyBp82@r1zjLj4_&bpO(bb)zZFMg_9c`!xS?u{91d;P9x?V1U7$gE;=uk-$ z#p1#ObIRhO;{(J9aWOHoU97qG#Z+CN2^Hs&QzIDCAQ7{u`62f|wVScoB5Su^jue7w z5Yp3QU|ALlolZWsut03><*ZwM89}8&OVVL&Tb8-`0(B+m9~|R~wY^Lf%8X7;bH%D| z)~r~@{rgWcTMsZJT9ZOx#S_@JMHPcdPmq+5X>4M;TxPCRBQR|Yx6GTac?soGiLpXi z|6U?RPhU5l6{mesV3%vr#!*nm#>GGhMM45A%SdTp8wS$0u}ae<+f!`3ZU@y`6;BB) z4ig&;001BWNklDn<#3mG30J-emUVevFexX*44VUoPoQQdNT*VylQFhz-pJ742z#F2OuEX!8*(b18?b{zaLL`j2@@mY2s zJVD6~>0Pm!vN6i!RDpQ1f#UQCpS|lny!ItKse2xl;}Ekgq+tV4T%5x+Z9=7}*6Vn+ zQbZo}=s$CYr=EF=zGZzRk||UeQmv$bI>K;BCKDuN9NSP-^>jc_|Dzxft}8`rUbL@LXPqlb9p{(Ep@8Kuo`9w8R-M2uA0A|AJiJ0_NGdD2XorsaryK95KI zJ|V1!>V7b15ESzHrp3w0nfmzL!hBO(@8an6bp7AI@|FK*Ap-wNkKZ)_|5F@6P%D?I z6)LD&g;=gY&d=cb5%IwHh*>5U62mb`8E|P+jNy}KX>2m+?v2sWmSY{=`!lBBW>8 z3N0&=;4AGbh#3$XHhUg_41A9lzvZ2nGC(S*27=AjIbdbe>R}(i2KS+%)ln@S;gBVgnHhh#4l8dMzqsL{tEaC=4x{t{U3# zi+X`lLNs;#&7GhrG#)VH=!@V&-6IhNE|ol&dKe(%FyZrpi2M-CsOFkc{(%~Dz{GkE?2TX$?@_w)OB;^|#%xO4-(t5@MFEfMe)Bt4(N zb1@79KPvPLq0M7vv|bJcAawA~#ReeI&5xngrb7=oQgfv;ctdD$4GY6mFOG6^b`puVe{NNFSQVC&5 zmTlZXP_1&{;1O0_el;T7!qh?;B_tg!O|&H)&g^{}t5TtRQ$|F*u_=|yq>@Q(m=6PN$HuGI zF>MFe*FRHGc=Z~|WP(~AEgX%+Za6X)WDLF)fp7 zrHXA^xSo$fVq21Gtxh5yr(CUK83qVV19M^y)mjbPa&SG5F!V8{L8a!BOeLvTYnq57 z1odi_MBJfVtrL&O2|TUMH%*gjwL(KCP2KgdoY+Nwk;0%-trCwpxSk&+amJ~;b>gv@ z#)&FOCgapB0iNlVN|!dIMqQ>d4fuY5 zZQEQJ9HCS!feJ9Cfv;C|QNBPxPbzKK|veGFPl}+q-Vz#OZzphJKA3OA#6d)#9Sg<4{`i=_v)N9Mx2c zU~vv_Zi=~M`-ru6(Gb)*H!;T#e*HY-HJ@s&&eYgAp63&@ZCdhqT;Hc&clFOdmLl8M zg)(dc365#u`601{Nw6?WX>yDQ`wKku&O)I;EFNdWrR(YG zY{d)o0LZo^!-IqDym2SD-S!UpPoE~6&2dwXm4v}p;YDExpTzrkkzZ#v3z+SgBMOh=o62p2m_Z`EUw93!o)E{ zT(2Mu*{tb+p~k67VGxGC{cBg5gIaSVF-b+B!SXl ziH%tY+wif|?IasoWJ^;Pg@qMMQ!e{Iy?o16-}&v;Xa9MR-!%aLKOJEhrsq9+i&N)& z&z?Vb-F2(RF=U>UZK^~|kC0B1T0P=zOC3_7KYSXuJ6;q+YEBgHG z*h$Wo6zkRvS9+owHu45T@3Pno1%p2iq~|*t!|ZiQ)MHd!FA% zQ!c}X%P!^kp`)l`8D$DqtY3#)DRboTF?zRMg_Un(VzGjc0%6b|HyL~WNo2jmw(G8C z&y!E^xpU|E$(R0$@BHyCy!~&!jaMsk=IDMlUUvi4`5A`ChOu(ZoP6qW(hVtG*Cm}! z<9jZ?=aEh&nVFqq#meQJ?LUic+t`l9?DQ_t4yjav!Se&;oAQj#50lR~VwfhAvs0{E-plb5Ct0(0 zEweMT6c-CLH#akIevrFH*6e4I+PN+z3SZf2I= zt~Sn{zCdehi!NZ#j?&iJ#L50Mw6`_mdI4@NMKYOW|DFSE*}RdF(Q)P%N_4JXkJ-@3 z$mlrfwl2Ds_330;J4U5eXLezcw$@f;EKW^Yl)Q+*Bos!paS8z?B}V9Lsh?q?l~fV( z6cr6LB6*e8Q6YrB2Kb>us;I~gLjt8`hqlmL215nJBVT|pw3%4v9E2|GI~4P<2 z8AJ%_T#mrgod2Y$C7eXLEHMb6iMIsT$N05%kh&eXZYL&oq$>ws5&Mr`>xY+R|mRDwO z=s4Rl76}P~yMS3<)IbW~$BM<7oF8LiVTxqmTEbWgq<+uC2c9QBb)L;Dx(S>rv&Ayw zr{`#2vkoVjWtIei6~_!cLPHQ529A)JQc+eR^R+r%tzE=TgYwD!Oq_<+wHsJ0m3YIJ zWo%rvj8x2~A)Dj#59}tW6j4IZx^gv4oWToqs9-D>qqVI?b+osMQn4tcrH#0nfE8jU zQWS?LDNIdKPQ_`;#C0A>5YW`rNGg@Wact_Lz)7a4%+E46yGT!OA1xj2{OE^2;?CRt zfVTEd9(m#sZhFOw5ehC`806aPuH%_!e$C9}0KQwJS_`5AT;asiBJey$1_v-51KT!$ zIQQRsAHITou7QKk?WZA~qHo1Y&h($;=>C07PtBlINU>byhL@~Fnl_RbvR4QW^;;xU8@F-4gE z4=mmOQysr+0RBHb`Y&8qpGl~f)vM)~9XtB;rdoBOEuC;knH4Tyo@aP+o)e=5;Z_q& zdvg@3njJ1pQ#- z*cOhdsRUlIlp~;6)!BjafVgQe@4H;FW-ZU2IK$Xnkssc53zG{azPJB8*>oI> z0AE^|j)fceI*2FQP=xA*0363Osd^scPu+`UJ2YJJQXL2u=yXXTqnPlh;X$D>hYExt z{yT@SEi{oMmq?HozNSDVGZbrXv{lfD0Af;V2>^NY8BWDinW7qS~bM^M^oH%}p@u_i4C&9$X1PcoVGR>`6PK>yepnSqWPwWx8 z5cYjv8>EC083+|-;37f@3`fg!BFO?mCq@T?i|;{iI+l`kb>nA*3S}se<`P;#Zxq4+ zHzGTUP}6EuRJaF`78&J&uQ#VlK}x?laYcoMN{d1CHaEZ$0)MHuQ3^vWnX({6M*8TY zF2%wCDYTZ<58;KDEK0Nvv}{X6CffN(H##*lO;fIsOEzuf#G%7@#WKPWEL*>xYPHIl z<0t9fvIDZMOe|LLBFtu6(q?@BGnnN9+poQbea}6EnQJDud^I=U{V)9dFK*#W@BTer z{@#zUX5Bg(8*>~!e~uNGT*kf!f5EDiz5MLozQ--MzK0Kg_%Aqhs-GhV_wl!1`aG|C z&CNXf)Wh6%`<-mxwuKvZ?&Ljpet=!iJjQj`-^iyv`3X*)KEorAJ;`^!{Z+PJel?Fj zc0d2+Q+LzZ)x~RG^J?Dy_IGk%@3UNY!%O+=&wP@?{5)U(+SmEf55C1qU-^67f8Q_o z+rR%OLa)mE?tC||f782o^pOX-`Au)*u0MV+VHongAKk+bzxOS+Y}w8|Klv^{_~B2O zUnucsfA%N5>CJEF@rUo_UANuAjW51|m8(|p;Sc>4d!KupE3dwuZ+z=(JaGSm96Wf4 z|Mm}G=0!VS&XZ3($_MZI5Zkw2%BIUMQH*nWqe2k|a{dZopb0>fP=XWtUIKm^3J;6_Z{9QJ0 z-o|~u_#r?2<%8<3kA7NYdRNi1_EJXrPjlkXVNM-8i5K`xPfxS0DMre%_{A?DAlHz? zm4+s-M2&P91_&iUN&@`_#}JVLRcOhHp+b~j$FLj>E?NsCxtSzD5DEh+qJaV;B9lbO zP}9<8a3wGzuRljqrS$tt#Q-@?TH(|ENS*Iv0DMaa`923gl+G4}jX zY|B=cZ@N@W%*`^tu*ix20SeWCo8S62nzI>{QWU1AkcBzE^qEhvb;Cw{x4`1U0*(_S znP~&%@$eH*@cys-RGViTBz7{x`0@R;&-C-qxBiZmeSIul1mF4oKjn!-yJ_CE1AJ3A z5mo~H0BLCug#x64#+ZYW5;NCCcEdL2j~`(4$RYB5D_JO2*|~KCUCkMeoFBu)C-AkN zUKo1Sg6c%_WUpiL04Bhy(^Z}v1+w??W;X*^Itu{*&}=T$cH~nOG^t7QmHHwk0%g9*U&1MMo0%l27nVM_VBl#|19g)ucD`~ zld0Jm#wMpZapE-fS{cW-F|0UkU0qm4NTuvkl>w&d;MOZxRszG+86du2MFoD;aBC^9 zG;9!1tCU!=YB?YH(1-Er6-?7an6XG^7<~^#NX(W@P0unmI;!uNC`>7TSJ(dEJbw2< z{RbZd11e_4F5FZuFW%~v$8J>8k#2E@`H2A*%ij1xyy3o?x%qux|F>WN%|fg_Jz1{P zuslPot&fVWSHWHoAcGL)2ZX*P^j%bKn%d|%mRF@vDIut2yd1Q}D3 z^=gcsIzV58!5@F%y}bBEFTz(LBcqf2>hWjTb@Cwjwm!Ps^6YxzNj~=0mvZwqq~vjawupx$ z@B=Dgh=|8%&8D>h*bA|xE*N8`MEd%s?1zeSrHYqo!ZRI`VW_1gN=1Z~2)P$(X0SBP zi=-138HJZ<0#fLLAnC*yeCmGG*Z}cY+=6FW#1L5jCn=EDY3m80CA9xx-t{8=eKh@w zl2ph16vL$MdQ@sPlwl!NNGNOs0xL@Y zRQkoDf*^W+Ez{EfEfw?;J!i=*5d=sBgtYYL=Qr@KdQGn%cZp7-6~YQX)CGZqUhxM? zVMdy7q{Lp5wnVb2r7g>nA=^MtMujvl5@14rFvLbTTuU1$fr$QGpkJ(B*o1+PDOB{n zEzQa&q5)mpju=QnP4W;z|9`0H>FFc@jvPFMU#ei)CVlJHQZJV{dF(iyTdzVkwlP_% z;)gm1qcLGKc6c|kw7})pUc;WfdkO3`%Qj!ZNHt(O+sVs5^>u#m$8YBGZ+wyWf9YF1 z^YBBg*su{lP$Y6KtZVP(l1ny_PN$IuDx1rSQfZM&wMd{O4?p%8D_8ciP+VYgW`?Tk zarDG-+S@xge&PhFh8(`{F+MR$CfCTJ!-r^TYi7DoU}W?H4GkHNA3wtSb!*tae?L9F z9oUY=g`q(joANyT=tCqD4rk8{apv4P9NXg9@guBQzKlbM4${}x%f#3S`}Xfvxuz!Z z=o3#6Pp3F}c0ipS7!dWk%Tv3a!HFk$^zkQY>FiKly*=Wd`|l;5Y2eAHpHii|OQlv7 z&+pl#GMTh^{K?0al0rPQ`vC1-UChlF*tPo!@{Ktjed=lAreJtvl*304vTF58o_zWl zmakaO(Gw?Gv3eO{81l&D50OYF*?;gLjuU5eY@Fx!?xCTviF+SlwQI0!2g9@=G7bu*DO5z-aw2bqjLsXKEuyzo z+B0Kdg??1zM~Boo4BC8U>y4SAH;vNNQ+)#U!Z|4nlDS{f(O zTUjI8_BlfPLxNCYnA!v4hYCU;F96$!4BJ)=)6hsoFPg?H1#3E6$>p0kcIpg=4U)QMRJHX`x@DUxxAXO9msIxvXUkYW9bW!R=nbuW7rt??9&V-dF1Q~&|5-)`huOXNAoW^}*WUD6 z)~sHxo_l@|4Ym}suFFEPNUmC@b^Zch|I}R!4fONG6OS-7G)OX;=7uXTqyN-t<}aKf z-mx~~)Q8k7Rnmzxi^T=PP|@0)Cs8jjH(SMTY{Sa7lizqbg=2fEj4SpO;_STRuekL! zJ2^jB;{5n5UFjHAKP2YFs3CCTF$~jUe!ifIUZIa^nZha{9{WzyW#L`ynG$tzM9 z0j}~1To2a|s7Vur#P{lSw&rPTZ9!TFHUS;&9h@JXrd+Ct=XUMJHbXT!JV?0~3MEZe zT)LH?-E%)fr%&^SmtR9mOFLmu0u@p$E>bELSy(s?p^KCTrE-OGxytIb8xYc@xuchb z#WHhV9oJJV&Q3ErJV7R#A=Q>+`La$Bu&_|Tb-}hALbQ}F2SSg_ z!#bI8{q#T`f5fLV#hSq=O9Wgu>8L2j2r}W5|dU6FDdJTMQx- zXk_|SI+!I0L-e3tQyGltb*M;U6-q0b{0l^=r&^xxBMl4F(0JA$)Q{(@kRUQV3Z-Qe z7aN?&_kh$aXsKVGZu)$*PBfCh38keGwjq(BPZ$L`g-f4-G)UPAd==8SZZ&SL#(^Wp zS+(s7%*J+R$~Enk5R!b-Vd~IxgbTB5zw#;$9@tOaO0aVK)r^!}=3I|JN{nii#LzMB z`O81x*uXF!`Qks*)VGY36Ju^@2zTfRJFi&7W6vI?DW4?_6$|t8Y~HewCwCoTS$7NZ zn1komaS|y`ojy-{Tb@mqUc%7e5VZixl^W@ULpGbIRw+=c)>tUj=xA-k^A##^QHHJN zrl-W()yt_=>-hC5RwmEzz#v1wK;?*TK;;_Nv2raTLUMbeoJ)AJ=9 zOVZlX#N6y0@wmg(Oo7IHj)nPooR~vXa|`pc^K^7HbLQ+2t*woO3f#I&IvHc3ut-Bg zlF*2$z;i{lRAOXemUV0T7@uAslZvr8zd)&6;o57qF)%nmGHzp-7L`hcmX;>YUl^vX zCCBdFM_9MIms;Ipcw~ahw{7C-XZN!G%F8)Fxk%kglF8+nDJ;^xWjlR6-Iz+7MyD4R z+0xz2*3~`y%i{--iKLdqDI&Sc3#MeHmU#b$ZVrUr6556YX;Ak=LeC|XnyMrtnurqG z=07>%>9G;Id%H-r_cC5rR9$E>eF6bx zBTi*ujt0xbOr|Ln7qGo51G7cCmaoFCRj?(5Bj<1z3XIRrl5J{58G>BTa=ds3I~K>W zZ34H>g^_WBz^7F6Xlu&T)Q}=>8jPPlg5#JZyH{ffD9=t}#4}VXRl?#N9ZfmPcACIW zGc`HNU%&n;Lbt}h{NiD*?@g$lTuQv+#aDCW_)%pUQe3iO6F>UtuXy&rY2J40?KHKv z@(&N~;l#iw@u~BCUEEAJbYA~&-4*bXRyc5 z^P=7~cfRSR>bu|jz8D%DVRE_vVZim*ZKrqHGXD9VXK{Nr@XGBQSkc+SbNxdc8!PbQ z4ZU>abNuMwAZH%C2hR^^dHLJ0g$7h)%Cijbdz#+f9`X$t8dQy3TPM$)pCXq{bL*>a z;9r0G3#N|lM%GKzN+qi05?}b-$B4xf-1opE>fZYv5ih;z^{n516Bp^Bn4OxSTwFw$4t}kITd%Wa%VliZb~&h!WIWF914kJho95~(Hu0H{{v|su->ede zxHx{|B=5cBJ!HC;@%|5fj5XbjbTwE6p2xE8HoCieSS;%hE~Ns>6_;wQitj62udc7{ zp``!xxri?2(GZW3jvEMNl4(e>Y*jZ~wr-)dt&_ut_b@j-O)4JaP49RQweq~q1hEoG z!-@+1=%OE;tDsLA&#j6Pg001BWNklFzEhacXs;rh@2zpLQ>_c(sH0r)K+N-1M>>cSmoPTl`!A}B8FU9k>7 zP@Fk^ynk$B@~cOVP5$VMU;N^j{@b?$V70AUW{wxFV!4D@tFbseMR}o2ZF-!bFiqfl z1iqdw87k1mE7L@%fKXV3GIkNsC`=QK7}yS>CBd}G#%<=$o#5shcc}mR`HzYI{*%nj z7ievXfe7(^kEy9qR`jmovd%{Cf9@D7ufC3l2WHtf{y0IX6FE=MERs$pbpAl(0f>gM zIF>=+x|};TL}O6poEsmje8d-#i2UCm#A{}-Gd8sqb~?Bu;aewJd*rCKQy7zs`t zJxXiuay`Ko>SC^dAjDWI5)A_yvY-_15}r_KdCC&?B!ZG(BmoJb&3H;JF)^q|VJ>bM;zl$UO*1kzqB2y(%!p#7Ld;c{5iHw4 zCDTM>M>l;fU6}PM!q9B=B}}S_jIk0CH8nv*LD4~MfzpUp)6mR(z0L<)>PftayaAz# zrtCsXpnPdypx=m|f=0~kCHsdKC!|WqND`!V`b&k;5>-Ym z`6eT;i4LICCSnn#sv1#BR1gJx30~l$D_)RpAt3N{@Kg|OHY}+NIw^F!Dk3Jk6q=%w zPbVpj4svYYepYW-5A`aCkDj1s%MPr38w-^>i**mfH0a63nK-x$V}6S5*IdiK{Ri+2 zhu+QG87F`^XuNkLy!EDfBE+JSuEFh%bRXeAO6tC#7}}X1`|iN^eSZAI zpYV5I`XsM-<(v8VU*5%6{@XXnH#YH_*S?H9-}6U2aQ{zu@B98-+<+eZNXFvNscii#Eyy5k)RxQm<;@M|*^T|(q zlwUvb`@H9lcdPsEdq{M)xAD$*y^UW#@f>%)`xc%$IZD+?Q7RQVHZa2BXP;sJ;~u`} zB2A0x)Fk^Uq%`<5pBaP6h^dDKt!7`p~+8re4wdgR#f2lN;mhGWoi_w??LFH zl%S4AsD>(tJU}7!nu`iU>}ZRz#8*d!c!mMehNVUxMJnCE^wn8r< zYd_}1;8{NYC%1BDY?9CY>wWymn_tb9YkK&?kM74+HSYeyw{ZBvD4+h$FS+XS%_I{s z9zJ~lRW0(7cm5u~c>Fm|4h(VQwhd$(8+dHbA*S4bSMAtLx+vLy^ei`DyPfTqtmWyw zhd6rb0&m>8gPP}Y?=y#3)z!>fuHVdkdya8tc8pi=*o;ykM-hB=DFgoS zmDlk1-@k{~Y+6ZgYmULG8OATY1{Xy_gdjEPE{ru2YhT7owr}LGZo3)n{4ja%7rx5D z)8|QBl7-;`+**~mWpVlCm+_)&uB5Z8hm$8yu~@1Ig}$Z_OwIGHUp`7pW0vCl9EF(~ zIyyUX%SEQArfA4Ekj`e2i8PNMALG{pzb2W@;Fu;AH=tT_xgp)i$3OFFzWdE@iNKrW zjyvvT=gVKgUwz{z)a)ehc=PLd_nTkG&+qv;&po$`Lr0E~Or~&51K+D*ST?p{5PD_e zMu-S^GZHL0bEED5H9Nu>bD;DGO?VE@tQu@3B5C%&51c9sJ z5ke4gItctaf$y?39a;(tTRL*NENyMqFw)+|fxUY;f2JSX4#_vQ(%9HWrXfo@DOF?2 z6(dts`J#8dEB2AwZfhRyKb9&~ro^h=?!rws-97>Toz?Gu`{Q>Fz;E%GEls`Z;K8Rp zeeB@w%`wa1`kgOgY;tPi%=y93yz!0i`6f{NzxsE+8FPf?;ud}Cu8UWgCooG$6<{?q zMv0x;@Ts}$0+Sac9m=wBEDK>cxQRyM$pn^d<10yL9Q@G%x_g`WhcA3e3=W>Avuio+ ztsN-kQ+MmcoD3@P7`$+ZRm-|b`W3utoiLMSuvjOZiczk) zj-EVE|D*S_<@Il2!^&O^6c-8={%!X$`s)^9zLN(IpCjqmWRr0Q8?r1c%+lJ?MgRE= zG%Q~S(T&rP0vSTl3!;0Ril|5`GWqK1d!RzC&sS)2jPXL+Z6tm{C~!T^MVCO`*Z5Br zNmWXoPD@>ya+?v=LMMZ2GEoqQn306VHcX7@#_t9JmXLT-=O+ZAE+*RAS^+^I1w)Hf zLNkRjlR6No?qbE`7aNx_3@#dFT|dB#55-!HNOQCi9O9|6f6inwY zC2d9%`ydFhqQD(rg&LI^aV9Opzyj*gV`!?AP6@RPO;xdN8!IwmF4nZ^&5#l$1)=L9 z3`yK^=xfSQ93J7q-aTBh=~7&!IC=O8eVebqX=$fWs#5g>9LuCLVKcse7hz$F?N?pJ zzJ2?tDZ$q3u4AC=GgtFSN4|=zZIZA}oJ^7-VROeP{+56K=zID0r|#mtpZ>2HLSmZ+ z8`rI+F`uV7-$YQas_m#duhHGrMmm)smun#A*mQQb)6&vJcXu0}TV`si zi5sumLGSWDs^vv&+oYqhhsL%J3@1(|o28?@9fc&B&4FQ2t<`94Yh~lc4P+V`S-HHE z_O>?i`8?g--B^x8Z{KoqjRmrqBt4z2Sf)X1zL8uugJqetx3`K^Dn-3oR_RnySSBRm zNen~(?2^eO-CZ5DwY92xwIWvZ_0ZAL&W3fXX>M*J-H^xgT*4rrx2KC-LxzTi1{xc4 zcwU``T#jTaf$MoRw=`kLVhEw=?CNI4$~DB3N%D<(Vc8C*Vbk2!Ng|yhpU-moz&-3b zdY+A!ZQ`bDcJT7`JtSimoh^-cN>W-}Wcy{8GFq(Al+TmQ<}fV_KLp?RF;p0xLjn;s z0KOkYlCe-1`XZV*N`bIq2<1ZrT_#G-4wM8!9g-w;W`kx10jP^;&rsdyd45_^Yfx-)1 zh;kUJ3hIG}83dSyBr1cZ zFaP#y>^X9rOV_MoLq5(Qy+@Pqpw&`9mz6J;7V9SkLO-RyMV#`P4rRvZgi5E3Vy6adLw7%e%PkhAnhw;(Ys; z5Al(kuSW#|cYXaHh7@>A-Pzx0h(9+WjO?jqEi-=q&fiaI#bt+Yt_Kr3zOB+T* z!$w*Teh7}^sJ7NtQCxgpdmL<=`Pmtk_4SHassZ1t5x6eOu~DW?sWeZvp@C$~VPSrO zWXxi*Sfn|hC2rXoLyVvvXlaTrN<+pA3#{vIW^G3kcK-|wi8KOL=J96dKoy)Z|$FpDV9k~9UgGqXH2aDfxYPEjmXNTyO03I(Por}SOR ziBU4+%npoDogAUBuaDV6k+HE+()lLBda-I9KktjJ~dB_C2?U!GS>*i$%&6g<(1*lLpdGMiNgA>d=#a zJGw_$TK=N~e6PY19(QRWuylSJhOIpV=wQ>1&K`P}ucTToGdDMj?^O{hpyr0yW+;L% zRGD=4kH7ti58i3pR&!s=wpid-X>Dz<%+8!08K0Q?VXbC=cH6dX-fyMo`(OO{T?6o2 zIL7D4`$WBX_sKnvz2)HEeO&pXm$6~vTAq0PpkbI*fw$7Mw%vdX;Q7#DOEf?AxJtFB2;7@ zgS0I;HF%PDzWMbC0_F<~tiR+c=H|vYdf+*x$4~fuE7lupHoiy{7w6b==}I=O?qUDA zGvpdllnM)+Jv2aDQyx2+rt10Fi6k--P%*-#c`O2%2`F19YRnl>7_6c2|jAi2~ zy$Jwa2)m&Ui9$#mr7ni{B;#@XP=|%-Yy+J;5GWNTZ%TwvI{j4WDYa=xVp3uV{r8Nh z_;#a6%LAA)>?UsTBrz-n5M)sb=qX0RFsXN z_XxHj2!upRiDPQ*yB|q{%qWdDM573`RZ$oDp_ByCMxYV^N{6$Q>Mr%b#SntD1SJ)o zQuxsg&W{>OKUBn|pdRS$N6a)Z5D^|$%Md)44A9^O0d|D?3?hwn$@2(Rh+~+%2Qt4uVq$WFK%q{Y>K8x%<*!sCnG$Et z^sB&kMX^$0d}dBqw#CrsFrM#It-ETbP@+_>h|>cXh$S-|K5~d+xx|UH7ijBhSEX`A z-233eDwWBJlc!HnE-sQtCOCBXkcuZ$;^4u3%C=0gFgMM}&;W^eoU!3^IJTu0=4M2Q zK-w`*_MgSDkIz zONE4ONCF@X^guy3kQ%M)M~2R&Ylml2aVqkcZ@zHVWwKD71uck4dXRfeF zT?q`KbW`v7RO(fvAu(fdP>MJZ$3jR!rChuAg* z=xlA`+5Lz3-o1~K&o+>2Y~+#W_A|R!VRCw!)_jg)VV04>0eaI&eCPg;a!1UZ4D>|E*n3<(stMT2R{E8P}v5B=S`uNqukFjn2 zawex{FvE~?%_W~oV3!vdyKs)TU%Q$2zU~Gl7s|Z)@=NH*H&Cv7WRr2aa#;%1GNTid zbhovTiKjSl>Lll87Na6vOQPl%OKe%cg5P`nYt)e=#~F(|;+D7E%!WWmS<*e4#&3X=;&Z( zp+r3hsg$co(%M*7v@j=Xu-iduI0ZqTYM8BwOw_7#nP2FaZK_NQjdg zAmM~_6H3TQ2q8D+fFXo{3B|$K7>u!vE3R@;wfab-GNU>gO`qAb`&*vp{_$+doOL<( ztb6m{3C~*6lC(6VnXUc4@2`BnpKm14ZI0F^&hSK{&zUPZUFv+r&5`|=fb%oe=EY7W?KqA_NmXZ|G+^$ z|C!G`^N(Nq;T^x?Lt@L8Ewi`YvNe{Gw%y#Ec1I^_8<$F(1#M=M;Kh?Vl#U1^O`sI% zOaqISEn~PG(l>AphR!fPGi^#hA&F(1*tBK^*Ic)rN~J==7Nk7~ZQDHf^Iu>UhUw~R zr~h<6j+esd=0oN$Ue3G)bL~obT2D<4lgYN=c`3TvTY07TO>STMPMRB+@fZKx$IXko zxZ{Q`RI63SC#QLC?-9z8M1@tFC}O8=?1as%>?~|4$>nl%w70Nm-a?Lz&G3uE{p1`; zYeSm0#x!;mpp@o48}DNK(SE-5#7h+PNzfXpBO-OlB&rEQQ~X)NOszwGNzWbvvc6h0 z(|ds?6p|)Jh?ZWJlL0m0E;oQ<|Z* zWqvIL5|ciw(1xCanO{c2;4+(g<}i2B3eHa#C?o57wovgocSyg~{s(7YZ-kK(@6LWyes$ zrm?jhJ3dH7#KDQ7y|gGt8rzGLZD`WcwnZY5BA!YMFP70GNP@l2CWq+-Id4YMho z$)GILl*N-7(wPkDrW`_>ZJOmJa1#k+EJc7L8d3@J`2tO?9W->##kUeg-@vR~LVG|4$jJR6ttzk)iuYVQ{&!jupGK*-&*)K&T=U7G>g=jW#%IuVuDC<`sgu(2i6)J zNyV??rPHKRafT~!J5{4lsFAS4TCs>}9+4xc0x9yw29hh@fw&eFbM5xdUiiC)^rCw~7AMMEY- zuBi=FjkDu<9c$|nI$xt)tFfTFlW#n^jiFLRHl60@hfnd+=?T18%=px_#;=oX9*&|s&!anc(Nci ztzJq&IXu1RC@r}(>$~PrtJY{qdEEV;ck;Ohf5G9&3Od`4mu#T5I?j*(`eVf7G5+a+ zpYweGC~hi66e?mfMJfuMSQ@KRLRHGxei`8$LzKsmjz?=tI}JGtFP31zlI08!U*zJ2 zGZacyY|Fgwv0S3iM@Sc?Li}36@c%uJw{RP89W&UHSaysstb)=AVV-wUSVKySAgB`WR6@@vf)2m`2BBke%%24|2#^m9w`0u z_?$7<@r=OUZDP)tbOr+8cR>HNNM9fYn z6Dh|{#1oFKZ8UaUTO|g9YNe{Drlv%w1-51DO0`0%qC~Ye%HZA+oOqH2L6r!F%tVG? zjUbAKDfCYB;;Fq@IzlN$=p+zc0!v!7v^3K{aFXSVZlF{#>h0#{E_UyHhT);}EL^-= z%$l{73l|2+WE&Zsn4-Bk$Ki{Uj2$`-VZd;q%zZz9k(h*)osE2O^Ag7Md7Vh4L{mcs z&x>*9{1EA60?&15Zf&JfDYO60?ezAa*aiPi7UDw;iT{76uA#jJ`rptyC#ht3+W$IuRq2Ow^6Z z5*Y+UQNZ4P`w2=#x>s%FVzEL)+@n;OVd7*z;nWyFJ#p7E%>H_?S`- zFfqgYR0B#!jFzg@vaMXGDjF*_RNZLiS~j`H47MLo2qjY!lf2p6F9I*gp^IhFpC2XO zF^_LP^bE=NS-f`i0!6P;j7=7J;OXtc>zdE@<0Dv|3+WpzQ}TV`Ld|lDUO_-K)D%|?TXzehRG~k&5MUGFr?F*3la0qRyMJ4bl;_=3@3p6fX%l*&1fo@;Gz^PNrnFwfIwwA9x z@Dw9t`O^1(#=CF2nrpXg;K^+}No2AtY|P;$Z2su(-=t71@;CQ>lTZBq@3LUd98L~i zB<6XSL_C*Gw?dj`AB<7lj})lT$keo|>yR~pRzQT-vQC@Qs3;_|9bDVSv23C!#K!{5 zV&2k444oUKFfobcIE0u4=rgC!(SPD3)VGkjPQSVYY#jSR7M z(*_E@&*0Dq8#i5nBaJV?mVy95GM!=YbUzo*50c6?BSUkS2+9SzyE~Y*Xc2{(849(C z(dh!4*RN*xfx|?Wh3&-&kbL`xkMO>Cy`8Ur@w2?P?=Z!3mFuru&y{OeaOV6VKYsiv z>`XJ~3N;ot=J?iAudra<6*!h;!K_Z+cjr4fdHy0w#`wkVH<_x0T%4)#_dj@)wX0X* zHssi{bt}?!*>iS;x2<2n-0p5Z{DHf8AF z%-Kn+jXyKNi`(|_?mO;a<*GG=wHfYv=rN8C6-YERl28GsPadPWF-!Nt#q{ml%XbeQ zVRRYuM3;zu0}5JdqH5R>xPK7ji9bp!DK@oYc1XC0-{E06c>_}uru`|s@o0|R{Y z_dd)Mk3A`>l?s#NBfRaVtC=;cbLH|?t5<3bC{;%-N_12~1A!kv2$ts}^$h*}r*XZQ zD3xnW7plUxEga9ovK-xzNs2HCbfhDaaSJz=7GV@>r4_c6LJCRE4|G^9LLx&YmJt`H zN{kOpV8vpTD;Cde+rx?_OGzeUVtRU%bSBH%4L1-5KJj=05M;7Bo_pa%Mkl9eZ_8oV zid?gDAy+S(i{sb~j!klIc$_``7dUiw7+WYIwWe6E7*lVhMlunjsjZ811O1%uJIwU( z1*XQwaik`B-BK2H&(hmoJ|nDD6Sfy)-@#sbX3xXb5kxgYBjHCyRgfmJ)E9MgZ(wxf zm!vikKt*4s5mA@L=o(Ph%?qtA6F_VPHpNR`Q(PfX0>V07$Jduqa;>_tRbNI>Dy4~# z#xzSvRL8JMVKlx9Ll`o!dW{h3vO!kYI|E5nH)|_YRHuzV-8^UleM|?TsOJ(9X<_~i zr3gcXUnw&ymto!Fg#@Jn!-WdF-#kWBQzMRLQeV^Q6mP%vR$hGmdBzWftlYSnlLz)9 zOEYxGJsM`WkxnMwVx89|LDJ}S0I;Qz--xhEF5%MMkYLl+wOB}A|N8x`UpkMsty;kU z`N4Nmt%bOLnWak?bM)dA2Tu*skWO8u2}QClxez7<3AkJc)q)7iGLu&egOjyvo7R-a zH7i%rkV>6ECp-sw>&Odk=Hx z&7oob62ABN3v9e%Bf=6iCz{!FqMyBo?qki$*VuFT1Yx8}rjrazPV#||e}*uOINm?N zbR}fx(E+AP6+FiU+eX%}cjuCpxV~u<2z+f?PBRz~MA}@pw$Rw3K2WJ|sm#Q_o(q7$ z@mv}@IBQodVQORqtu*6Play<|p}h&og|R70Q{!}YRcUBw!45;>O#~ijSn@7^KDO5dbfx$hBSe)$q#mopzJlD@M1JJrx-eUl;)Nex@XT}*RI`UbFHkpX$1#IF0%JqkJ6IMl5ET|9@&J- z6t6MQWx5;?#j{8^MlIPyF*!+Cs}WabQ(D!EC^DX`gtW*uHSxWd_EMY}VRHI)-mzgB zLzC0Q(<$=Pd75Xi296*t3n?Yrx9<=!%hRp7tT^j~?b#>=ukAfZLIm`*wDRJ~ z3rrNtBw}eIzk;v@r;37aKev-xHmu<1I}TBiE`hWul*=re)j`jRL5_|VF3W7}c%0C7 z(YAx@#&lCtqcBOo8oxY4r4}OWIJTGuX>i<;0x4|*zd{&P>(5tBar!)=vhd5AtH?~Refq&<4Qr= zhO|;Ncjv@-zM`LhfUWOO7_RGLiA&Utx`?E1Fx6TkEO|Lt%C^Mi*V2}T^DUx~ny{$}3oHkNvJ?o*#!(8# zFPmneK1~o-eJU-fKghLtNMEAhXwxJ(c72r}MRiTCnH*|q3fD+!l$Q0-ATxC^(|vgv zZz+XIP}V@8xGet>LJ&m}krp_@tdniam~q4U-wVQkL@Wkj!2H%MAHCy7X0^5Oqvu}3 zYiPoDO=4y&nWFFLG4|}bacq&(LkJS{^V()Iu2FpPNOXHU@GnBq5X zxq*kD-G-aWa2iGE`$R#&(peqs+&#p!h_PhD7Iaf9H6KJ^E*Wm9b4vWb8G@zdP@`17n=wT2TX`#}nvm`9`)VGt2X zo7Z=2$4xa5C`~4lCNCt?aY-kWgtZDSF+m~KO>?op*^?((e#I38e!z)ChuFMj6Z>}W zrmd@s6>HXTZtwy+2$|iK;OF=L1=T=N@qM1#eTZY{M{r^Zv{uY-O3;~2;N5XEFYZ6a zsrtuI5Yl35rpU|t`tZXtPPUQmxwAQc7p;JJ*APZ3Fn>4|Y#J346Y>g3S=1H_uzNH18ySfz^7F%Lgm zF(@c_bZdf`6%kY`hHj@WB@LSgqT{8p zv5?Zx?drLr$V)zZgrNml4pLf#zDZ8E>=;U!5YYdT7W6-E68@jRH@AZ5*Y*G9^XmrS ze{ycV_0~hu3a^d3D%uBDaPa~Cr< zIYm=L7K<|7vpR5NaV`#Bpj;{tMP+=)GZS4RD&;CcP-EeurOcT(mk;0lTTJE)q?0kK z)e6LxE85&n*4N$(UFS?+a?*aC=`7X$popm z$K-T@TD3+kQX&ZF5(bfolwzh(WO&aGY}dnfVGc!{}g^{iXA*qBd zq~qdwuCR1S5JV!`*`z(s!*U#vjK%O=2g{4|{EOR!U7ce2s^z#X-AqI_rLu2~yOGTU z&+Whx5=SZ$@dQc7VxYgDvqyVL&bqtFz~ zmSv^_+OjBDssv$x{T&6FX3BE>zfmumvux&H7 z4#E(-j;V|g=4*6ZV>p%)9Vvn^AdDiElw=w*2Gc1nO)8Z!2x{XgxI_yvR%V4n5eb*D zT;NZC_XDh7v4p9yVcMG-iO1vIeC2xPFI>p$`wsKf?>vBTV{F>Ii3@{+Y~S_@S6#i8 z-or;3FIJg&<29T_iZIheEZab?doF|uEuG7{d_xG5*h1q(w;oxypu9F7oQu9M>4?M>v>%|EW+%~VBg)JFk=?puM zo#FK8BsD*zRPzxk#ByBX$s|p2mzK?I2!enGT^)Sz-S6Pd!6`Z$QoL{LDki7$T)S>L zgCpa7{E_X9#+wKW6%$@&S)>y&M)tiy`OFDsFJ8jHv7-!M7$Tj`uZ!+jA7p zog_VLA;Z-O?ZmL_6eUk-d=+6^5uuRyVMwJ`B{yp}N=3v{DNaw!P$(6#9EVqTA0U-T zV%siK38drk%FiDop6kFyQi~##RIJ*#j-$POboBHPMw&`tnpLY-uy5~v+B!QJ8=oYV zYvp)4UE&*kPlz2MA zQi_Y`&Qh8frlX}9#>Od>%FOL<=f~gqGJWR<`S0I(fIt4|hj?n+ZZ>Y*$jUiA6a$~; zTocRItl{jLb2wgt)?AKbgBO^$d>N+(hnevsT6-2SJb0FtwoV$eX@(_qb{P5JhSkfs z_jhjRQxE+DwO|PnIIv?UYqo4==*(IA_U~ui#*G}>cYsVbLsw@zwMvDK)<$BZag&Y5?kzgs(1xyCfe{^({c473CnJRIOq;akR9kjgPW?=`s^;6e=9g zHPc8X40r%2OimD$3uvXuH8zq+r?_xxfTn~)uC2{Tt^z}TOC%E{Qb`UTI6zdZfr_|x z<4V5z*+1sog)@vzOd_SF+gqDyYHk&O_s}!E_~v0+vMEN6_c1XvLL!@`rMZ!qWAl!i zuH(JGaU0v7dxXfZv3%JQw(Wd`iQ!@L`58(xMZO*sx#hYwY+N&+bSAC0@7^Q+^;_R& zVq}O_%a^jeyMc*(fnPlOF#hmy)~{WupWC*RRU57rUGo;Qe9bg>zvou=z4<0h*#to` zPs3=Ro?q4?Zly^M2ULqQR0>s=-|}|mE?B^!pT17M;*;p?K}J5G_?vrKyl??Er74ta z-1CKdskAR({N|3m4{OUy5hs4vZ#x_d-o!RO)8yadUBMiuUNipi#U4XoDKrxJ!#H0 z>G6>fF>qm=@$q2>&!5J1JzO`A3Tr3?rBZ=nsX{|zGhJ;t4h-duRJ2@S{j$X*6EXH5 z>1Avxj~$CM={hK-aBT}^)l=PV2N#Vr0=DA)X7OMvR<*A2k0I9lt*Pk;7L9}8-w z_B-Bv54Bo_QmJIpNi7>89U%!2(h@gxnIuZ31=)sHq!ctYG$W+MvTVA$<{1Ko<)DSY zuT>EOEZa7dgMLHn|ORzFRu)hdGA#lxOVA0rfUHUdpdb~?{Qw*dzkx-&yASb?pZo|>7*O;BT*u?; zFMOY3NwIFpe7bWvhNhQkIKeU59_FGmBD z`56jQ2FGd5HSx&7)7-mbfLuCl0?std_&%OvA+Su2gl$u-)R-7KPPQS# z*|BNf`)6OGwY{BfyARQnZ9*x5n@Dha@FJDa#;=9AXl&1A&6-slJAM)`7Q=NN&J6Uk zdhHr|5BDM+m&TS>W{&ou{D4x)XR1)9DU-m7CmA?9#DkALgX4KDUcQukzJwH((XiJu z94_TUs4zqbi%6M=W6Y9FoIQnh9EQfH(Hd;mV`zMe`yPLR*Y@n?{Ll!`?l{PyW2gAd zKmU8Su3p4VTQ~9Ip%a`LIE55~=9V0XU)x5{f`tqZ4pI&!8@FD|f$iIfIS$L$tmeX* zGl(eUdFXaDkZG74LrEhq-WZjCbFBHCs2W6MOdW z*8!5@sTpF46i3et@r5t{E4N&^QnzJd;*UObr?~Gs-)GP6eN63#kACEX{L{VPAn97H zx%pjY$e{(*T0pvIKI0SP93D7FCK)Hf;_UD+J?dEM&fh>&B=kkA1}u%g%D& z^Sk-Yt!r@5R4YX+*Q24a0k0b2ST@sz5`IvlA)7*?uq}(p{0yaO^D|`vR9RY4V8zzP+V9S=r`qj(1V%-`_ z)hbFu+;OPYd}_XrU#Sp9aQ$_+vU&40#A7j{(5GB35l>_(RjM2tcu)wS7SuR$;taF9 zJDJKCdHAQ#vS4m6on76!wWUo&ewkv$=gisj1ho=fi&u#^4)qf#iR;?LfNvZ0dZlG^kVpa#cVp=IAtF~ZP3@+uyw()4TwVu!g_F}M*@)$MlnPUnX2xmh$`OVUwrzkF`mI9ia?K?K*cQL?2qC$= z#nZ+YXg2INj+Y{+&0G!<`+uqG0JBveA0Ph}tAYQV=hqFuuQ*3e9C>fjbK2LeS%pGl z+ZK(DSyU9&3q*m^Qn@U-S^+=XvxtxaGFHS#kNc#U~5I76u!31dNT|z z-&B;Y>(#YF3CrLoqkwWD&)E0`?QN~3vmI0elMt+fGD28bj#noa*!*%5xgSCyRFtYU zerx?&Ui#wK+5hw*;_I%#YHXnx8NGcN8M2U4zCn>%Hi+wb6uzx57w^k3k=eeK`qKe&$v@BJbl z|LcEZ-;TXJ@x8Co*4n~tU;7!8@kUe>U^@;%D>~9C94|(xTBTU?v4C?W&D;L+K0b2Y z8s^RJ=3k!Ofz#YUs6zheJ-5&pk275DbthFeD?Q0hy(mz z4?f0iSFPtuU;GlKQl9s}=biew=Ux;|?X#J4?X5@^5lVs7=6zlc0t&uOvozBv+jgkr zr|9VFq*|?DNsBR=Wc0!W@r3cvL|PCakT z*REyX;iE_?S+;r&r%s+kYC$bO!_4#~G1uYqpSXvw{^V%}jvQg@pZzX@u=wQPe~YRg z5>F&aWwK0Oyol|(1Yt-u(r76OgPM_+**4mCkWoaXRHPV95UXc~#G2dKdE_|hM1qo% z{P?LCSh->e^Lsj(85!blzw^m}jO{Ln?LcoIK|`1;ES7(d&O=Xk8X zaw~O5jvhm4h4O3k?%&7tH{M8Mro!p-!)U+4k-p>f z^&R8+Z97=FbUC#!pjHhHVvssdydH?Bgg{5;+Lprb{RKw0AuyR4TGy{vrBNy(&;o?w z%FP>aU6mP<(u2g@Ifg?W-83oLh6bkgAWxjQ>t>y>^A=Edv0QKdYajt zopiM{bNip{X3^|f{M%1{#{KvIko8OFux#;MJ!kPsv3SukuGzAIu~G%0q3DOSbaj&T z1e>qgN@q5vTQUju>^&fw=Pc%iEt~c7`E$g}+jnthWRz7)7V-559-}m;n_Jf{<=N++ zClzj_Bc*A}HImDvXw5Y+GQ@e%a*Mdh2l3jed-J=m(1gR zcYTQdvx9o3qJ?Fd>5cD)*tSjN3fg++Fmdc4<#LfysA-wM2q%`HSoKLe)@7utBL(r8 zOBi!`dAi6;kM71PO;bI%1JX^jZ@QZJ*je<C)&;|ir)d~>_ypGv? z?#bQ!boVhr>7az55=Qu59El>GOz??Me}Tob+Q~JyXxp`MEL((ONTpn4Xy_tq)~qC* zN|I}A;MH9RgtzA~QX7ByuuXOI?i7A|1js-?XAS|4kdE4pUS!F4@` zCiA?pYnXM5=dftO0?OJ#hBYjaG#hl=rWX2C1B=1qM+hdT@RqD3nNFKjc?6bYL;acN zNQi_n_SQs1=p;yIJ<_3%t~t0~f+&ip)&iW!3^FaLu_T~Fq7V$Z?~)7eE$;uNV|H-A zeCm4NUvadK@T)Vt6^QpspG#xvmwHzr0BK1a&!db8sfnvCwpkNS4OR(>rI8I8`eN+iQ`B!kya5Z42X=f1tBav zSK!zXgxZ*MEE`*x?Ly4+jAlDjIF3!F79ed4Pa4WWwN^ulh$yO=7fJ{d2_E<$;|NUC zU`t7*PU=*Vt_P}w*g_L1hzLoGkd))%*^(eMfn>FcPh4qyRV5M@mTePHrwO$&^Gdj! zj4Lpyke614BJlCN82(J2^56y9N;B-niX4iu3VXg5~(TBH${MXg%K z5f-j%)mNdCm}?`vIF@Ch{3>C&NKM;>K|m_*VOf$OsG;i{2&p8cC?c$usTQWGRIAhi zMJ19r9dod9E&R<#-;ZlsT6=`s=fX&hg+Y``9uk$Mo^pD>VOcC& zvyPK}eMB=e#2p7E1#JtL@bKxt zeC>M=(b?TiCX?jWt(z!Rs{G6S5A(KbxANfgZ}9pXJ2|{z8S9tKr@OU;LG>_h+T(z4TUA=u=hfN zqi^nI#m4oFUA)NNU3-v15R1k5=zDMDBX`_@6$D&=c;AgE7Xl1@Ek7=1Z!L<5OxX? z{>ewhU3b2ZYAw_=ktN>PzEeE)%=27#^;Y^Xj`RA_GmK44v!J_$OeRe%ndbRdc8Z?X zEG^k2LAamOr!MfdFMmsv{g5z>Xl>5$lb=0HdqODn-(3Bwt8UU48|Q?cmj^aD`%#7TrQ?QzMyFf?^?0S_<^^IMuNcWF|)?(}wSQ zc$OsLNbE>3apX<>#tvc~J@xm6q~aT$zZ4R;o()kA6_Hk#|F16vPD*J}iy~}WqMN$d zT@7(98->EcA?6opN+T^XD$?V1vUu?#uD$je;_(El z*RI0$VpOKaSTJuk@rLVhTe?wR3K{bd%Ak`=g#x8~ogIbw~&OE43IJ*3F+;m&771;Vs4OeOG%Ugpq%;twz_tX2&>gA3 z!IuF@4+9I&^ROLVpbHcz4`m933c>daoLs@_O`B%X2N;G$_0m8DF%;&Yyw(xolQP3=+_0LL2>5`1c@r#m(3B{K__XV6tlt{!uDMifI zE1Hl(V(6I`OCW{b)R+ZPfGUJk1quWP5ywOr24N5q`kpojnwkm}$`GUuoU%=Wcr>C9 zkU(Kb$erp#~uvCh7f>gpPzhKVT(DTxLC|LO2DQ$Qw=6i02;&~f79eJokt z#@1K2U|J^9_c1M-(UCEZAKb&8Km8ef(>Z>$wFe)Ifm35x0v1*kbKm_t>ALroD9z z-+k}|Ga}02Lmj+1mcb1}qD4id-GJ|2x1RT0c0NCU>{+(FzKi$$({=ptz6bd6hpwTa zu7-d9=3Tu1^2>PijV@|Sl0@QCHu?Ui&+y7Xlwrw;8RH#W>U>(AxT{(Zz%KdB~sIH}?tdt|&M_939 z1>GGT*tW&8WlK49U_azs645A=nKad{Ev#O%ibDqv@#vEWsA_7af9p1O?(blBCPlKe zl*LOI)7v+|z|b)3&s|S%Zy$+7jJlc%4s>+0Z0S-?4)l?m7{`i4Sk%6RwC8hV&t446 zVrn`?dwm7_j`s4+JMZS6+rNTo8a(ju<0Rrq?tAc$-1Dt}!Ez#O+qQ$|MT`07FCL*p z1YCB>1-#JRkC%5zCX+a(qW|C?E@-V_`GT`3DJ@~uvL&oowSvyh1MGP9uhdpoaQ%ih zzWSke;n)tjoX6wOKFjwXe1gvXhiPB2l!a{zF$BE&+D~gw6Lag?vap3;{`O(+{K{u&nN!PyPrk@&JNFSu#E@Z#W!Yr&d1liY3_~;b zJwMQC*rq59RP@$V6ov>wXc?brTSVgt0w=1|gu{@rsTB6yh4`T&^&cFC=nmnm2atBROXtWsOb9Y>tWUgUG2_Ufy;9H`pf@FI&z# zFFKz^O|=|+`(@drys@8|iAl<8YVnGy@pEau^3Cs4QCY#__BI?**r1yRxj+u5SkQCdm7SmAm; zQ|To%p7`8VXnH4YKEX6er@))Jl~*&3CR{OFFlV#>#S%F^3&HwzF^dZrbWg z`0;nY!HJ;}f*_#0q?o&3?c}kZal%-PX&DmabBs?+A(GW3l$L`D8B%Q9XA;kSDG8*` zhViA;+a7f~XMcVGKohcc%G-< z8N((BLZl2RDoXO|OS^H3N;ou@;+AjR&8pUVE;?&DOWT+5$}1fRr6?jqm?lz&WR#+) zvIg=lcEkY{YB`WFh$)xIjg{=4RB=lKCRucE%C$?&(l(0iD3#X zLlTR{k%mn}eGP$8N;2l)d3oZ|C`$T;Ol?8L5zNk}89sRm!W^NWLkWct4wjW52r?+8 zGm#w2!4M9C4D`7rOpHhzq?Rd1;&I}U2w68sH_vOmDH<($LrSRzWUwI&njD?*1Rn_P0{? zPCuWf)SP~9RWQ{k!cgG_nu(wHLxcdwGBJc8kw|K~PGPzdh9R+tmgRVXA{sTxX0j*@ zVvdbt*%(qMY#Tu6d1SL`tisAT?*#=MpMla{xo(V<0woYi^WlZi8;W!uvIjOJJP&K_ zTo@*qOqP+c8A2zf=|(ajHFk=z zu~FO*Vu=`*Z89797(%a+9bw{yAu-dy0i1|K!qPvR>v_Zt_{x_)!$&{yCNt?Y%C<2L zK~+@+HKj>fl0JjuIeNEmL6taM_0K;*sDLm2>>&&xsHv!6PIC)Cy8Ax<_J^Nw{#h%z z>TCBU1_}=@jVrzFF6SG;CHP@j^s;OSK znwP)!ekv;}NV`6vFnGtm|Aw}^JA{A}}f za=9!o9`2*O@d)``j@e^x;!lpTZ1rloj~!=xVv3L6a1}RSycQ=KVQ1%Y)-7L5I*`m+ zvYbuNzfAA(V_2rilu^QokxA~p?Ru)qO6VING3ft%gUG;8w00^OfHWTjj-md zm2{sNpto;;i_Tw9Z+|~QC~0b_=g{F!7A;-I$nY=|qoX7ohegZU85%ytL^jW&MN0_W zER}O~!}9Jgeuro*!8<8?OyI^Z+>Rkb7A###pdg=4lNSbe-uHWM zzUg{~3D|WcP1Vda3FT8?UCvj&{G~H@pq;y3;povWmMm?d&^4gbH5k>Sbr|NoFP{kbxvxSxaSIJ?SvS5~A>bv{WHf3STOu(n;Pz2!g!F+WJy{ z@xhxJA3a4ZVsrh)>$v&z-{KEX|CPMqaO}-~ZhX&2iAHR4W{kn2R{D)%suz_KDwuVB zx>ISM+1EoLEK)Nm_Kb{TnHHm)p6BX!yo1iyo+p<}lM5tclPNy_-FtB&5f;{0^Wk?~ z!pXCi5Or(}0oPu6IR|AK!z#+$sA6^5d+?@D;iprWPLz4`=P@-q%gBsJMav?}<56~< z7@@OwH`9}oy#4B1>Fw<$<%UdWvt(SK*7`~stI9b0T{m*gRhKb6Il=s5 zk8sxy|AWQzni-p%rn#|^oks_>Io&cblm<2gfzQN53gN_%N|5mbJrJ?<5ae|Fx39G9 zwbZc*RN*`eByJE=k&MtSo{ww=)DV8i~V&A?4lov6q*226wI?g zQ1H}QrXEa5blSX%Cm9T4+`oSqQw7Y9kK-uG+7<0Q{QM5S`QaP*WZUmT(^chAAb?oaF`t#rSDh|k%}tnTjvw{0a6G;)6(yyWlO6jL;+Q2zB;~ zc2N|!QDLaPhK5HNf-4Q}15m0!>JvJbLxotTD$s!pLTOSQw{iWDP)QsoqBrx&D7kz{ zYC1F3b7Jtit-B9z`MU+)NB>`!g8%KWe>4Dp=Tc$dSpYIY&AyIF82UsbF}zTbC{17* z;QJv$Ni0j?2cgy%ntD=y#<(8p!rU|krlAUrflenAMW zpEDgn5Gwqjz`QS1_ez}(%N1upcS;FN^Q}TQ3^khG3nYFhi8+>@7C`~+365o883q|I zz!Cz>6!^ZxHVr~42@1~}i#V7DxW4Anhk=J7q@IMMWl`nj6@>D%a!*Hk`wA>2^)y|E zDAUjeDxp`WcA@xI+7YdbYn^R?k*q{yQmEMsM53DFlMOI!3nLaI%w~159vFDSNBJot z*%=xZwP0H&uIHawBiojNVcDoc)25Up@clwMs4Tqu`sN;qMe%akGyLOZNeTIE7C%rp zwu4CsNFCm#bTLqrh!IO92!lWy3vCC}iJ-h3Ml{LbAmXp!g&!Un7O+x?t zwrMgkJV@@)c47-wQnIj}sNpb?5BcoZzeo4c<1{xlpe&8cbR37>-Ti#*?mtttWHl<{ z&^LUFKfJVqv3$t(@qm?=U(MFt`^g8Ag)3L{fiHZ68{Tz2Lq`syN=K<*vytJvOQ=GG zZIO&P#0`U4&!eWKh`!kw+CO&}6PfH816Wl<3#CP6{CV%2c=-;-W?iZ)N=cNI@$Fy! z2_rqp-u?f{tv6iFS?6uw>E~bMTfcssoo@~?mJgXz5~Fig@*mId<=I_bjOG<3<7pmw zdJ|F_tbWJ)F&h@)RyJ|hOZ%y;uEvSRczXMOnkq^tDlX=YqkRl@A0js~$*ObK(s%3# zxtSCT)?diZF_&}GK4ZhveD;UGWKru};zh-jH!t95*FFw*93h{}W6WDcFfz+4oxS{d z`$0F?_!3?y~+bLi|k!s0~>nHU;i zW^|OOZL?_Q3I>LT$mBg5o9426-(D(8O0+1!_gL4yh^Cq{3@?w2CKwzZ;pWTEC8tbE zqb8Aff^D5AIDYgPrEv>Ca9LPa#*OE%;a89Tg)lqAJzxAVe|YMz96$I5M|*aolu2Vl zBfGc1%3$9RgT1|Kc4kJDmc;2heu9;2&LWdZGd1h;j<>&!(z*sd^PRhhl+BV4CB894 zd)p%J`Ip=18=au8yp)_5@~L|t<>bUTl@Wta+;}C;RVB=%GmNHvcJ_`il+SWxe<#I_ zEd(OM#&ec)?S`}X-Lo$-Ha5e;#fxyFF#_8$VIXF^Z|0 zZxOXk0@GnQ?c&Oih-Kh~S~988!-Al2=kTS%mm#hn5K2ML4~Rr#7?!|_Cz-proqK-s z5a(^YfY$b9?AY=$K_*SSX+9_C^-$i}iU_heNV2}5JRW0Wte*p~Z|9wtY^0*RoHzFD zqoSb^Um5)9*AFu~J;QASLpU*B-`~OG+vYQWP6O37b;K<|7?@6!p`AzA(s7b( z%-~~}T!w9~!jlRw2vJh<$Jh4r@XI^NPEO$UcH&5vs4|I&TK07x<&N9G%f3ThG%s9C ztfUl?pW(^MQfkVI5kfFMonmflGZ&qI9?QP{WnO;nSvKW74AWvbCzvR0B9^QraNhu)|96SZd%(PlJz_yl|}Rp4Dr%mUtn%k zk_1`){cB(5CqKJSJ+pha=&ml|+_RT4H8H~A@F*2!&DcsY9R?UeheDc$fvaTU_iEq< zK3-w_V1V9IBQ)`+;Hg6@+%V7*GNm2hr_HER>Q#NjFtC7#A&}7sL8KB#Nqo=8aH7PM z#YEx>N{ZstH8${{&picYRRqE$6ebzFm=_NBQX(^~U$Y!DQN)<%;FX%FMnygnCmSt6 zIldn7DFrfMYI>FrT(O3x;yC|u-@`abhilJUL-$j!G3e`o)oDqMloCThDsVAO3)3)& z6qoV6O*?5RJ&0`@M3D$Dhc7|8dB!IukW!LyeLT-6m&+pz6DOX8Fx16;pbPxc;t181 zWdweJZ75MzRY5!=P+_2v*Fs{N0zVXl1!Y25KuAYylW4@$fQ&HI!`46$u>?s0v8c}6 zu#i+%H_)_r&Hn9s_P*ygk3QG=UtSpgH@yDQ0Q{Xx7(u8CBm2DXV_7za(9>#^A_#S< zZWIiHp095d!Z5(nT6h(>_#uRA5A?|25GJZn_)7(rS(xq%c#Dpua4dmsnV@tb47yQJQa@fO6?VZ(aJqR3 zLS5WTsR~8Do}$^7PCs^K?)8g zfu=gSzDGKnCy?lHHOItrvtSs+ii&vl^*zict4UPUV44<1u>>L#!56xaNccWkDai&B zlBLW}jni_ngDR21Z*FCXlN+o@c- zmQhzCg8;|2nF)LOi7V+oxMEhV0t$0| zsR_$~j;^Cfr5GI*(n0B0rmgLR$SFFO60aH_xG!~a}&lf&KJnAr$$upbH^ZeE~_{1&O zadKo#dz=(J@#0r$YN+MMU;PZ}OqPgcF`LbCYIKDA@Aw*lF!{@CZ?Lw;X5oUB44>-d z`M++)cA~ufT{rUP(H?PVd>^S)nzD*gx(@B-X!j8=yy|*>^}rwa<-I@UyPy9E-}vz_ zxOC(BY&>f@?JW&tJ)ilF4Gatouw!2bAHQ+~<5QCiPo-(Bt0oz>u%l64J-mx`jg`!d zjnR>Z=&31+;}(W#@z~bAeEKJU((=ZZ<1|&25X_7+K0JaE`o!W9s+(E}ObZ{F92+MY zahS=v9GlEjQeFbCBp0MH41r}B%y=OYL+BKCsRtvb08df~3sk6x!`A*$K7Qw~IB&^3 zq!nRr|0o$N!P~F7l98S+!d#l$K5!F>XoMHH?!xd=SV;D6c>zm6<%$hlxuTVZMvLQ{ z;G&B!;Gzr8=gq+(lI7LBwDTZ;+j|g|DC32_n`o>oA?F6Xi{p5qB$ajXfSRf%PIh$jp7ksF!8gCo$oMeBBV%MU zGhA{03hW@mi4)z_%%6v8nw;wIrSHuGQBH>J+_i_<)HGLIcrMG^T4-O=PD4WrSAO`* zc#%3tD)LfK%?$;_i=hI{Xp}&P_)_cZ^HLHu45VQYNQEB+IF^L~vO!Rgfa)_T@O^|Z zFzqN+jm^Z1im0qCXEvP{1B1h)XEQ8Z(8}twS1H3Zg=q>@VcYJ8l8n*=JEH*NunJib zN+|*fXDoo`mAxvQzQrV8J0%aHm1$?g%gh6=5H*i|W zOS~*!S-QA+AU6#=S{IA@q= zIJRIGigOD+GdNvhYK^`?BBiet=K>IsGhY`-y+KeC6?mx7Lt!Ee-3f+}uKWWwnqp#I{Uw=;u@D>4Y#WU5KNp0?N-5_IW}W9VSb*o|$&L16pk+M~$HomLq0qWtp$tOb*T^wj z|DJ+SQC(eul1hztbcuLOVA&3e)1f{3V3)ooSJ;+8KIfhZ3sOqr*bboe;g%gCR4&;} z8liM>QV>dHI)yY$B2p3cQ%EJ4mI~93VA&=zlAvf#E0$?eT2aAdrjd_tn9uh=crBTH zhVk)n`c9r?^|Iw`+jEek-AC}TcXU&qu-2Uiax#QVA6gM~H zc@i^O#>(~U+5g5)>KdCUud3qEp1riMSjkJzzd&XxMa{;`7)~ql`5cjGl-cQNhIamq zn=UzvTP|FUDWE(VwyzLr>C#M)qYd%gd{nn@EiJv%IyQIdwHiU~W|jVWygv`WkwAjxdvRsXb>S=}0k|bdDO+=jR`| znz(I{ck{T)B#>~+dvE1CU-=mCy!tAh-n^M7{$!eZ?wj$H%po z#fdUKJBV&C0j{ihO6UHd; z7Pqr-(R?;ucmWE7APkwF7$=wWh(}Dur&HYe?Vobb*FMXp`+rE<^Lc68PR5cp)x{3` z_U_`j=l;s_C2hQ8{c;S;(sVkn8{`OHqIc=y{br@5hq-d{gSO-%`-qoZUq zS@O!DynPwcwy20ZjPKt`(w*U-&s$4r+-5eDV_VlTl8y7QtLGpBMbt8N$RC1C-q+K8 zrErA63qqo%-o~EBH-}PBri}tY3MB|#m(^7|>~J zfPcF2de$syQ`cX4vFINj<-YqL;9o!X9zOQ%pJJESQ#Ef9K@gIg8pSEAAR3D@F`Fhd zY;4OUZd=5Plb9;tMDKCpMa9@|QU9>c@E#7xEb@Bm)U zWlA|XmW3ld-JF$H;3N_n#VRGD&}>P-5eA`to z9*dsiUu5gfz071>UfQyqJAV9Y9)Id(@uAyVkTNJFkLyrPQJ}-2AS_J8ZK2cQr3wkr z11}{dfzZEWfxiEXP;U)R58Y00n*$jVH4KWP5z@o`j13Rq%wLL#L$yDr^k2B~UDtAO*AA*0n%TW$2SSC2m;(sB ztil%-kz_F?rXc1RT=lkVsIMs_@O?t1kWzc#grVyc%TUU)EiK(uK|vg>C!0ztlyHz3 z7z79vfUt=ti#ahc*0XAP+dqo`{}0zc8i2oZB}&Rv-_S50|Kt}6tmcTuBpN18B#M$D zQCkp=#;|RZ;BRH(B@yqvM4HwW0@wAh=c7o1fl-khPnzIp>XrLf`Jze3lat0zS902P4LmOB`FnV zLC5ZgZ$Yux){9M>uq_i(fzZm_}q8 zhEB;<1x}s}H4ao*NJ8>b;CMb0vzas4F%*a}M3^>bG*w~1Tg+euQm+b2g@@U(m0BZU zaAb^|Z@iAn-v2?q@s;Cb^Dfb71R;U~UR59D(L{pK4+=VeNyLe8>_`v7Fho&FDJX^S z>-Sws%`HCtekvKBp)i@IS(x;g2-Cu{OnlER&DPq#&GnXu9-_Qi9 zRGMWaHnnZ-{BhHZOrGfB(L2A+v(Nm6$6tSu#_MOe)3dYq=?p_7V;mnCAd?U9 zeHWpiIyK0(YtEv%ww%_QGHNTTcx=;VUROCD{Qbk+`K|v+ZD|>`rDc5PmTRyqi#79F zn0E7Av2Fz|O$}TPeW}TkG=3J-~Q_V;2j&+Q5K5<@VWO~$E6#F z7(983Q>R8q&(2a*lw`sDW^gkMPo-FJ-o>brO3F-wk*O)(*;>xJg^f(6GgOomap=Sl zdDo}0p^keWc$n9B@5YrTmJl>m6!XiE-#~du5%2xhJ$(Ag3utX^p{KW>Rr8xjM58Qh zYvV`v{hn+tr)6rUg&9k7qHl;GohI4PNPk}+wrSCK^au)rmW2y=W7iRoaL&4Q9P8*H zoXt=iFD92uQ$DweISUqYaMw<}$w?y71a>6CK>rZk9bMR^l>|XZaY+eF+7~e}c#*L~(Hu-JPART)BdglP8%NoxpT#T9>WlXCX&pZ zQ_D!-aq{UD=U;p-VJ^+$>SBs2t2uuB1fRa~HoD&IXLfR&hNdPS-~2a(u*hZecy5k( zX(^6nGCDEEm%n>A(ds%9u?VS=8GJuQ@9|z{^^4sMUD!FG7@%XntO(YiQ(|6p<)cAx>aJFN7@jre_eM1A|qZ8b{@e)GS zi&0!jSO;;JFtztGx&I zk}QgguA|4Qk3-_3JFIkJWxL`6-DBHJP~v<%b&EFo~ikX+zn znifh4ydXfJ@Pm+eB0<~YMU0#{&U8A@_TCxF&c2lTb0jmzyZF;HFH%`IhXt+8xON0t z@Ly?@xWEeo4D{qa8~B)psRvNPASZQLqiLAh7lz*Udtsp{&cEXZKGCyh!H{6(mhk zN*pIzKp1-%Z=JFlJRXD;MJ&!;*2dkxeS|$d{U{l*wylw}vI?Hw^a2-Ou%7c*FJ^2e z!<)zZn3~OCmRKM|qD3C*Op5(oCrHL(lqMrQ`{FK=i6nW~)#s+~V;Clhh*@Z)l#m4l zhGAF+N~~y;D77u9}U3Yxz?;%C0=^r1)g|% zGjm&7aXlYD2#}#BMp&l)1C-jCOBe)LhQtrl84X|<$}@&u+p^At^~eIU%J=ou#J0`C z;}jAomEI5t!zxIJ6yh{-#~%`t<{0fw-d-j%`qo?Bn}zddFcEjL)C{($}f0Ealb@ ze}IpD?{`FMOE_(RR)+p_6MzZ>@-j*?QB2&?Pb>;QJ4PW;L7OX1GfYpvQdAgXI}T!I zhPtT1=HK7P?;d?j9q;WI&;8{o(zCO~sw>I6K88>_Bf*Yoqpq7r2BAK<3p%M~+}4^y% zo93wLnF+CX-##{NenChjh(@A>fy;SoS28(zlKQ$T_34j)Q2g>Yf8gZsNj`D$D$>Dz zP7I#p+_}}<_ot^x);4nAe|(-zf7`|%{D8U3R}zmp+;;1Gc;=)3N_y`WYF1x>u%nob zjr0fS(KI(fU3od%I(wLzoT4&nvgL>BsE{mHHPp2uu1M@>G-vq<0Nvo~LhVZc{@^b5ZInGX?<*i43kgk>O;Fu<-CP!#pvW&(>i#W7vH^IaNv1km5B$vrxMI#hfR53Vo zl4vwaTl*5adwOsp5tgr7#ZZ4Ao&Ei+UbTXOfs>@h$1p5G+a+UwAg9i8!wB^T_kBaKSk%sjDbq!-~r>ZHEUR zeFh~1;xPvy667rtDIu9m^5)EO8R)Tp}a&O1bPO$FZU zgt%EE;9w1shqmVwq~ID;GV3y?BWVLZt|WNe;alH469h zY*5&=DupMt6d?>aLjXDr4p2%`Tvp1f11X|UZQ;3Xd->=)E~GdSW!sM3eDIo$l-1Vb z3Wt-afa#$b(qrTL{%b#EFOWP{+as#q|uMN^avZK4i?fM_gA z|G*GqW0QmmUV7zjHf?$lCt|aBUK5v`zm7*Yy~v!>80}3}Y~Qt;vsSF&{TteO_4luk zagrF8LEN@bZkGJiBxZS4!5r-AX3NlYpiqX|3t*c}Oiwa7lj6&t{&;~515dos$!}jh z!2GHtw}0+Kl*Mi0i6o)#bKkRDu?!PKK(4UaH4EEZ+p>sRRzb3>!zSZ~AYz%AhR&mj zTPA5g&}QFIqcVNNAme&SA+VIhFb!=24t>g7moQV;OiU?k6lu-h#!MzDHNXlrRj#eDG*W? zGz?0Uxg>BJL0V|65W3-12#6ICjm3yWqnMUS%r>#|(?uIMZnU;+*%JI0l!5=hxc<=q z{GH1{%+6_OWbHX;F)}tmaZ(qLmT6*`CYekI&kJzfJRqTHnA<^t${j)!|Mzg=&gHzLZ=ZsmYxe3hNcUh zmg1Xcfj*=P{$>?0J(Hqg!5pNQ#T4LsE=1ym2h=xJr2>Ru5H}@;A8N@`=z($CNUcBg zA`DQX&;*FW>nlv$gb-Ll;JY51H$6ptWrg_I2S3OsKKCV+PG>}YLp`CCguaJTLQ8)P z1K)LVoCt<#76OwD5GH}|VLOhV-uM9}MR6LN8pvd_%wOEb8{4*%&ANo4hYUla@fen6 zk`D^{S0Rv6Hx4=k6{^L&(2VjjIm&T3r%G3{_`qGly?)){!kDZ{_N%G{YZ_rp*%e*3+mtWb+ z4I5ShFn`GsdWTOjw&P{uWz~Sh8yMiMYd^rNTeor7FMr3{m5a#d@roHNl3U9{99BUtBd&Y< z#k90G^Xzl4kv5|ux_Alsejncp8SLzYo_$2my_!sI1K)f7O+Zl}x3MQWIQzEi_{AMx zr*~wWvEh?!Sh1K3&)+}_i;_ePWWegWA}nF>7EEwFJNEA1hXJT@SWN|UeS1zZkyPITD5v3)i9Nd49#+pjbS+k11-d?6A zQ$%fx+Ll&k#>a7UE_HKTIez3Q3)_}(;%FD;<&{L^G5U`6uzb}TMh6F&4J1c<2Qg4o zSC&&6k8$AeVJeHG8WUJrhLjsM2ph+!Lo`q~;cJ-?aG zLmhnMTVLnuD=uVkXqcX(N6BV$_`Xlhb(u|P=pP>E_mA8`b89R4P!LH4?Am{blkYs2 zNTL{1C}tIMFCMrLd$VBE%WbP*A`^7St?@=LKu`si#gcQ&Fw!u%8L07xPc;_ z%@K*mF^VdfOr`lBH(gD2Nu1f7PtWKSzdzi8vXVq>3(w6Fi$(aC8!ji7h?AL_W^5)+ zLwzlVAqadQI}#(|SR^e2(}1G`L)^2o7g;|KqizoAAWwbU1~RD>7cFX_Wl=lb2lnAl zkD`>s55V<&V)1x^d?%Tjp5c9;co*%9Tj)M=jP}LtR9Drq`_Lgy^!Bo4{}Ha;u$0M> zAr9`^PHK9Fb(g)3s8IN}jU{yI_UN1aOt}+blLX)ecA}$nxX)u}#dG3t^eCM+t;^j)R_O4!B*JZ_urHrTY-22F8 zF4`=^eK-IBAOJ~3K~%7w(6TXY3nc@T?;{O^92P-7hX{dKq9C1?1^S6uK%tum%O(k{@G^#&;PLyyeESvsc?7e4joacS+{kxz3Y+v*a zkN`WyDvA;%QO&X}TaHU)E4JfuQkEDdl|VXyFRIlVF+%|v$XeAGwZO-#hi@6WN~P+e>jv4zCY)-O za-~Wv7DK6XL4~4{h{uR067_~5x}dHU=s^%h<`_lP^@)-3H^P@)(ffnz2lY)xB>xGe ztWWx>kLe>{Kv*|P)!eAszak+r^q(~bkpNOBok(!(=rPt0bdpNg6zWE;NCFhrB{h-5 z;0i5AMC`Aqo4B%muZMhy`i6l})(fp@GoUI0#d8P)4BXU-4FR4T>tN(I#nWJ_B+Q_~kYwC`nB_qEcH z?P2YvP54#}1t=Gb_$VZk2~t`*oSVI@q+&PGm`Td1=_#hCT4~6puUOC+ShJc^G0(__ zF_x)y zlWg5}J(cBUd_U5MrkymVqM%w9olQyZd;6^{OJG@XU2%h6M3_~Q@1lg_3L zhHmiHho4}$qk-S};CnF@n3~y2duJD){kQMp_#Rr_aU*3!*K&gpi9}ZgzU$H5)6Kdy zt5H;i*Y>?mZefXJJcb(2P;-0^9X}1aPUZ3?vJFkNcC=F}mYJKIk5aaUprNsm{tfFm zJv2<*v`MB?jEs!1Y1=l+%XtRRo}*T&kx8ZTyb6x*Ge4iBcl|~#j}6m5u!{5NhiJ-V zh}jn7qvzSa^IA?HJ3=S}%8H;Rout2~o%uqM)t#-}vSTB0+myOt3ZZDcZSO9&ukJ)> zI<{qES{9*%njaE|0d`m+T%JYx0aMenv^6&}GdIiqzyBxHYHoCii%2eK7zVno<9R+- zEW!TQ4>Qo;OJ}Bmv(*AlwL)`yJ4-dm{-Z-|+qy-rUfm}yU0UF!R}ZrPmDdU5X|fwT zNG9U+_phZ|a~Ya_j*-y``Zp~zJ#?BNmcjR2zWlw%F)ahludz6B9(!#oV-uIe@VQZ% zTAFBVY^1rliNFuIZp%jb+KF*dh$Z=}Cl3*CYKs5~QsUJMB7{JZA%5Mp70Ci6P7s+y z6%l=|)VR z!9#<@HeHV&1jJQXoSx!RF=TyvBl+bVmuKfWF}A?jg2N|&^CPV5X=i+V9I0ryj!W9q zS&6A(zI!Xjj~*eeyWDg4^(-wcAT%2*)5K3-J4k0+ijBS9j7?1Qp|{?_ z*}_kF;Mhf+hDKCWa3zJB!Y}poQY#i2Jaab6L-9QHda)J;0Wy>ni$$*4Fo33pa!r4~ z*tT^G4Gk?=W`@(FqsTBox(+Wr_Z)jZ`d&V8?>jhuah94JB89@T=VI$RPPIm|dli0j zJJN_W?~ztti4u6j=zdUyKzbfoJ4tIc#dYgf@zB0O2FIqkYv(3DuxBG@CuZ2Zb`822 zCs%roH3O^p#l6>ZVrq%=BYC8*qREh$rbBUo!q73|b^^mRF$8EzKp+Kv{WD%xi=-9k zZcNb7(SVuCaB=by>9|fuuSKB8P(^fKR$Y&UVj17{A|Ht+naZy)TCq@cjhLbk;G^gU zi}@vta)GY6#xHE{WAFA&Y#CTZxl&Kyxdos!mNtHB3X? z#84uXuTT_p!;G3i1<{pAiIe|-6p8;u&KnKD&pDQ5g`VSZVQdV?aadYhx+?jJ#bP8= z2{M^9ssf6licHFssf3Od&k#?fXiUd24ISH#qbP!=rgjp^G__hqXlm5m3Zde=j&QxG zlXo3I`X>kjd`~jBaG4)G{sft9qZ}C-6@}#$6wO2kiSK$CdY#oDvqU{7_$uQ*2%|Mx zWay2YNrt9g#ezaz!!IM3;AE@hMe9)=NS6rxGjmF|&0U$x&9dwD6|4+#^n$8Rfx8o~2kSN58AUk8om06fOFIa~%iGuu#>=YoKX5 zgaOq`830#?ShkH}=&Y=)kWMG%#KaWM&5fKnJuI~Ps$0`_LOrvwsoK? z3d^}Us(ZIHF+NEpcTse-WjS(kkbGf9-0`N{866oV)zCoKs=BslelpeZEZaa4o@<_SYYb% z0;kW8v5=di;s%@@pJq{sV>Ea1m9P98nx=AobdvbG-JBB+o`9m~Vz+l8T0;z7qw4!) zEQ{%rhiJ1DZoK6dj!xxx;IU`XVllF37nv@*l%0?!wZ?mH*~P+giE_DuX4<^(-gmNR z$0m|78_Ur6{I?z@SE{hOr>f7tWny^Y-nG zj*Vm6HUn!1n3F%Sg zvjcx_ir&sve)PoCTsS{WV>&K>k}rr_wIxV(;D?n4G>$t-KeEc0m}Y#rM%jY{7iO5vEpo%P+i|794Iw5V9#&ClmFDJo5ZL4qTX{G22KgHc#AuT4)k@UX(*nb#S~W zd?~2=({x>nh2)7T&|m16*N^vB?{eARRt>+i?&X_kCYNiRgqWlkg67qhQbiX_ejMpCKd|R ze4n#pQ%vTIoSIr-ZC@8(d+0}OSldreQyMMwsW~2o9%cK)j3h1bI5Iy=?)-6D+dFAp zwFWN;@q~_wKvlpODg+KeVSx|bx`TUf+RDiEJP-cpC+t|;!=BCk2&Y0A24qu-=-yRS zOjAb}0#(zoV-~`Q@xY5Gc<|T+L9&VR;yg)bg9hc`DtO!yJeFAT5^mF85O_O=XmJVqFXGGVLC&s-8`FAQ;EY?2@hXvk*S zux^06-+a5=`wKh7axLKS#5~UqPBM}!QBe&P%f<_QRPnP~D4|L;LkGK)htAFsvtq>K zDcm4rc`-*`Lb9h1qcOvh=boCML!aVL*3R z3%X(A`4LYwl@hw95wk7y zSd6u8>%@}`{@*VW|BIYA8i1d30u&O7Byme)E(oxNLJ$P?wWr5Qu|&1zk~CEmRiRSS zMA#g|bVBk=c~NW3U|A-LW@G6Z<>CsdhBi{EG)7FKs1YyNN*HLGjbSv`X$B#xrXkb} zXU-mGxsb=LR>U>ete3CsJ0=Xv!tnxBT_Fg39LGh|w5x_(&kxZx1w&JDy%0YL>uI_5 zz%c4b1NE(dq16L$>e~zEfvy{bfeVU(rtA2Di{m)7wl&k%+QQ;O zj;ZNc>{tv<*O{KaELz)JDHTgBFRx%)CaxE0{!K$CVH?DoGIaKIQz#S}9l3yQXK|fs zJ-7`j6_@3*%fT040mTHvB;C@?)cgvHzd%cC6MyjOuObYaRRe2LRE1E2=Tssdb0W^c z{nG*~$ylz+>nF!}>V+d1rcU4oES0LH;}#ul&1}AAlgOVRB%RHWTPpC^U;G-^?ApZ* zdvE2hzVQPpiplM7zJpJH>j%8PZy$}_tGF=vGEYAHJcUw)^;@?@Z0@N`w6`=ORE=y) zD@Hs?4U@sqX@2=Q&Sl0l*{@Z^@LpH_m z*fcd^5}#e7SgCQ}NB#!{9u;4*>)IXs;K}EB`pF+rojb`7o;%Iv>u=6duA&Krn&%O>43t_4KcB;G zYT(F`qx24}C6P?hwrw{#Ptq(DI$Pq@sx^M+U%ro#pP|7vS#m=(r$lZ35h5Ih+z@tSOGMSFmN49i zjip!?i@7C^4IaVBHna1F8?cfILSSfckVG;`wy}|s;qz?TvW1IdW0V#bkeLR~=H{{O z7**e6?Z)j~93Lf>$xvNhAq+$E%LQ6nJ2-RtG~IoDOio_J3kAi+924ixuy^}ro_Xys zpZ?6}_{492lz~<4VsR-?;CpiL%!s(_7v4*AYYW$H?w4COuNQ8uOs(oMTd1=C$O-Pe zc@Nb}g>-i-wi?phkftGKj4nrZf0qzz=@Nmc*|Y4p{hC$KKvMc zt9v&AVJDKz%`Z`NBN9p?k)YDh z$aq9yoYR+;;QLeC)sf z8u$OjXJw_KTP*v6xDJL}#@EvXwIYTPh*%OY3+^N)!uA*Qa=k&Po1fo0k>HZ}3uYx@|R7-n_fIsnd`K8+_u|o^}H2{Ed( z+8eW?t*MzsS1_>>l4;CRT*|R<=^};PJOgVt5{8g6b&|S9%=ZZaRS9Uc49YPBC3Fag zOt6mQpeafOoCqb2jZM7p(rc7lpQ;o*b>IwLt<6%6XT+kb3f(l(G>vM_;i)Hn$YOql z{;fA~!@zbDhDNI$$5bP#QaK1Pl&B%dSSBC{g8$4+$zoA(6NNSf zoJtK@ETD=A(`qXslK%)v$&;9hB#<7sICAs|L&uKt`A_^RhsPKA-M{`K_kZL*j$fFhxwDH>evv=^mHT+&xfl7@Z$H92 z@4lV4@4b!(e)tS0N2bWwF|oO&>1W2qH_rd|ywL#soU^pJtSM@=V!R@!`5E>xGVyAv zf^EkTBA~4`ixEppR0|o@>PA{AgaAb|@O_WKck8LHetlgGfl%?i2)n4Nkz~cNQW)k6 z<&``tf|XK*<&`q?3rkp~3Z`M8X_0{yBEY7U(RAK2wE9H^rmo-xVHENrsT-Gpy8I=m zJBBq?K~w&d$CjUwOtd>TIuQY z%OaaKX=-X@sFX*yW5^IXI@=i-=;5Oud>HGZYIe3>`g6A{N65 z!pNYetGJF!rn!rig(Y+)V8>l=Vf4&tE=^3**w%r!Qea@$9+npu@q>_mK5zlGtYEhH zG4Du}SQ;~xLP?}~?k6vUQv{*Xlj&cxA-1K`+tA9IzHS~HIzknde14hPg&a!4W8&-}{n;#E8%Kr^7ZW)*K4u8oH*_peZa3o*)(1X>MzyT5I6q_&BaZD^PTTmE&_&LrDohKPjL_VJoG-MrR7fIAq zO~v;D+)4>Ug-g@Zc(p32vWFH1ghIvhe0(Gbm0EFyWJe#4>u~JoF%(5ZC8V{d4?CS< zc;r0WwnoK&abba$jt&$nPJU^L`Nbu6U%Q?0i3!p%o3w3Gny(RSYmZEyK^P^QRx6+g z@@{~un^ZlOn4wcHS7_?!WNEp;#CQ$cGRZbHh`zoa?tRzWP!&PKL};PI>h2~+#-^oZ zXhKueh$0e3{+&cJjjo$iN-GSk?qOhH745A}965SScC>ehFz{JgT;SBHld`R?L(I+2 zk!{G5NW`gCs_42J@!wqsGjNbW!0?3$KKr>Zv2N{ZmTRH-031Q%zUkA?lC}+;T8*+3 zaN)uvxrJF`rp~eD8VjeUNhXpkSBgx%whz*cbZps;CBU#-(3?8=&JUj9#qa(T9qnD> z1NW_9S}DH$_~X2GVM(}6t8uDTno}lU{=gl4?$Mv}p4+#Pux;-D@lo_d5>fXbIiakh zLZjlyLt-i_%QXiOG{-DRW;s-Jk%1(p1~})=@LsF*_rUCGQg6HFg zA(qrp>R4&r&?r|OhKGh}$;RpK?&6t!gT!JD{Pd+)NG`VVC%^YwxPd~YR77uSLgc2n zw0{u4l*e&gieA8rB*GY`AtOhNj^KlF+b_o`;kng@rj1$s`F| z(v(T!6c*7nl~gj$4IBIE%A`niv_crLd}&5tsHB=3WGogJF1qv`htr4liB%0P{Q4jL z3M~y;p8d(QeE-oOQY)1(bp=&OnsgOg6zOP;kw{u7nuaYB;JP@Di|+^Ms)lYGxK$TX zoQHVa$FJxwrK)HC<&?O1L+!K&6bFWXhz$7g{bz>g^XSkN=!{)#bVTI9*16hfn+Ad zt=m^~&E~a~$`zJ!Gqg50lFYP2P-E++)yyu;^Tabhr7@M@?YHh`b6+bL7fVb@pBE1t zWy{9(?A>!c$IguKwwrhHu@CEykt2%VC&?U=AELxw?sYU)%yNW}~k&A{_R3{^$dMYIJ# zqUjcjq7sGyiXLG&{Xi0+A~XZMfLv}#jE-I;lg*Gy+Qe*&mX@Y^o`4cf^@-#=S0??6 z3WgHVifV3TidU8B{T;uKFRQP^BS}&;{Z}LIU0weNswxP=upS;3ea|v=1VLmb3qp_r zDFnW(<3*i{td#Ns-@yo~Yc@ZB6ztqgrZ<85~hZc z)n%kqkb+3s5wmD%?cnnCGzlSj{PF+b;m3c-%dZ_ky()WBK!nlM-}mr5uO2<`6NXU& za4a6jG&E+Xr-{cbvJH)78?#)RnkJn|)7I8XsazqMOfWfqF~R`WYB)8Al2gO7Ed*d$ zHma&pER_fXKgw$e0}NfosaEh^m%Hx1jhk+~PL7UGiT(SJvNAi(cOUo$rm6Apx4*>D z#1g;ur=O#}s~2BtAXExVdH&{;_jCWRydPcHDOYR6EQ`gJ75@GUUtuw~z~4XcFRWj) zmigQQf$yQ}1}#m^Jo4;IZ0Ktz+tkdt(Tk{xpsA^el}Z&|QRr{7*?H3@UOaW4QXx-g zLz<)GqjdDGLJEb~Uw)ZNZl2uODC_V22*opp*`8In`-Yv2P0vueJjul2{oHc>cG?;< zOioTRdT9c6-Fn849AM8itGQ$WrF{g{9Fw@28sV>6FG{zHb&5A%2b_|N?DJ8$OT$svYAhcEs8XXtG2;K4^8 zC(+!+U@XIr4-au^>tm|u+?Hw&*@^p&n^_zI-+uq9Geg2EYbmUUW5o^}1=cXI3r9B--20>)_ zL=uF4WPX$a&vg-XXryJDgr0+;Y6O)Ep=KcbfS!TXShk5oxtj42(Z7f&B&vocz*b>w zHplq*INP>tW8%UH%X4$|4fGRhY~s|h<7m3Z?(44Q(!@nn0hvsOvC#{x*|3?5qr-G| zbyKQV$u?$bZE4}u@CDSCZaRBbvuIg}z{9dFR;n(A{1WeZ+j}sK7H@Weqz2cEae^}peMG2xw%VxP!rnj|$x9!@@@BPmI;+D;;I6r)g1YK1C z03ZNKL_t)Z@$=_M#!XC9muq|4#GX6u3v|a_sOSKJwpwnc~U{O71+Hwr^&9 zehypH>E65zKL{|EXV49kAkj!>^KO;}y!ZZ3@r!rdfUavC9Uf=jbQ!m23+0*%s-(EG zOn-A4TlyHG&)W6|Yyzr582z4*g!S;DT3DyF2|=}1V{;q=&*j33L)?y$@S-WMFfC9d zP9jB%t)Z(Psbrk))vM*{p;Mx}yB8xC=VSNopnu0!f*>Gc8+`HP%Z#5s!ppC|M0;BU z)6~1O%!<$yuiA`XsVV`13`ce&P}G^E0Sz z+v&OSZZzFye0++ho_w5BLzAr8aT^*TE0-^E$L3x>{mCzIetd-IpML?*513q$vbU>U zOi$0y-r5iW6)X!y)eyobB-)g>#dX%KUBjOB?R@w{AHnxRUORRY6-h%}CzEL7lmGKG z1cA%99(e-kd-OCV@l_Q?su5{T`uIWgo(Kh1i$&9TP5cbG8A!q~PTq%C&rL=7FX>jk z^XhRPJANJ+Na9_+{NcYpf^L{(dI$LGPY&|n{<9RTRXVaM48z18=qHuQaO%hbgy+$> zZ8xrBQgbS}il7=mSoeJRdYoL<(x$s5OS-w4RCA*= zRZmok1w7wIs4D)fq?8Dyp53gf)Ix~@sD^=^Orq;LJ_<40rmdxkz;}=mEK?zsP7_Nt$YbZm*?av? z(Z6O5a|=1{ym1%D&W4SX zRp9v&T__l)iIf4pR{^1*sWwtZK_{Wmas3b!jbu74HBA*l(dyC?!SZr3ngoPDBV~nB z);Ycc$Bl}1!IfNqXngP15nxfWWwc5J>VY=l)z>4y)RZfpTwG6HeI9}1qSZ-4SB%9G z;xr2P@;!$zaHS#;wvbqM99)-5%|%xgG#Oy0)8sBsV2@*Cgyu9%#-NKn5BP0Pd!qlQPy zFluIW6;;=<;}#NFUM`YOB?tqL(UCD?@i?VokxDv^rt4fdJH+LgIV{^kO37kwkudb} zb4w(X30m7)n4hm8LrFYlQz|XipRtC}LQGxd-h1Ccv5*tBN`VG9XrFtr6TFJHr8%jiygP<=;>l${aWt6X%{2I z!)Wm&-+t^F8WI+-9y-M*Kk@qv%?IQQ1z60XrJCrl4Hk~PjP4ZKvVA9~jvd2`W!UlN zTX8ju*^)!eD_|#*4312&v|Qp{Z@*JqyL~->@F$;@U2R?Bxz`TxwFe&N{qK3J*t2^l z-+A;&N;MZl)1yKiiK1(?_jI$ITS7>QX4w>1mI-QZ6l7#XhUkV&lr7H^u|s zdx-ANc6=!~dU`}W^yI6=Vm5ENaWfq)ZLC_|CzlHap=;6Pw_L3usUsOxotc?=6jfpO zb=R_c_jNq`+>7YC!NWiJ5iPB)^bf3N|GooQwoO}WGoBw%sn*D3)08VNx~9<@*RjJI zAOF}#s8(voP^C~i4(_F%S$z&Qmkwg)a5Cy5|^$l*cg}y?jP&G9Q#|)yN$xzeq9Tzw7LAMFQ zh-gy_!BC(f+e{b+gfhfbq77}K;u3F2W5@{FPz?naUf+ij`gCpCO+M7fmx_@bRZ(%m zkOToz)2N1$Qn^BLZkFmw2?L4mxwIzw5Y-}zgo;evHH51nRfU@G6ND~F!=xeEK-H}=a&$ko z8DouV(xa;gJK(ZkVFHs0&!A-5=%GZFK@^CF#IG0pSA2+y5LW>SVJJb-P=taM3RZJB zs&vVhe5!#(Jei@rBdQ<#0BVlU`SA&{^_pu*rn5Y??>NPZ%YQt#kIe(CuymDs_U=Nn zY+ichRetOJ@1!Z6PaVGE8wf(E2OdVj8&D4ci=yn7uY~Qkp+i$&DKKkh6V)Mo|lqzMKo0}qO(9l_O3v(>x^9Tew9;zbo^(c+>)uX5Q zv%ma1zVhimWY2XwxSU_%@xT27-94RD%SE1e>L>`?~kS`Rd`XR-_5=*%S9LHs3Y6eYH*)Xt*um9*dy4qW*R%_I%6ea;B zy69?arM;t#;js(iqrd-2blqTl^fEFG`114wk2XEVQrV@ax0iIxqN%l&&wlZ%#FO7; zsZimAANl}(;8Q{8ufO~NsYHyC$vNJ)eGjQrf&)VnjLfc3ELSL$YCQ1hvpn|9%Q%ip z#xe-QklwyNTGwpg^-~uJY87T@W+{{^#Em5A7TS)R>1u9Z@#t%4l>%FL?BvXm!}zIY zI=5WMR86v6D_$i)S(b?%kK;Kt_Uyi%zP^4iY+=UY*r^Pa0B*bSdft7{J9z2k{S=p% zF*B_ML4fCZtlzSk+1w%{qZin^aRat(P*eo#Hm*ZxDzQY8YRy4YMYJ}TpoBg_5D>Z! zK^^mJSr!Ii#LO0=F5C0bbc6A8XIYw?V_?I266qv|4;-Skt(~qlYdLuE0G-`E*rv(Y z*eL5ZZDH)f2rVrwgb3!Qr&zmwBd3lZ$I3R+v*8++oq%E(B7{P|SSDZfaXg>tg2RSD zW#54#Jo)rXyz_nUXYZYNGB|jevqK~7-o6PlW-@$kgyW~qbJwa(%*`*Ln>MIgM8EL@ zQpp5|4;^7)egUCq%*@U)J2%gzOEaWW$%u;PxL9_Ke14gl>yd75p*As(<2XpSLNcA^ z!G|B``W;(n@9L(lt(k?zdC}9`jTuX`p|^>iJ8z(^rCls6EmEn~c*ncm#lhieZo2Ju zQgORZ6p7Mgmsd(0er-R?CtqW+tDmYGLvPBm6#5aF#aE~yp<3a_)opzFPd~tc(Mw!h zF7ulk`Y4nf1PTdFWyuN9>MBL*Bq)t&6JTg67cMVQEtmM^z1#VNZ$3dPVY9X&&e5RE z=B{Q4eYR{^$LZ6944yg1sUt@@dh`?zKJ*X^^NUQ+Eutt&L`D$`nM9n{wifRH_$OGq zW;F+opAl{VxrI5BF`Jb@q647}34)NY-lQlpL?p8qii%q)vow2&8`ci+8^8VMtSry+ zz+=y1DIqaarLVV_Uwr3##mGbs8TwIpq^^@~ZR63$A7gO!QEc0mhmRZ=uOB)|Lqj`$ zD5D@eO^XUkz_Kh-=`^k%kjpRg`7eHfn{U~RuB-Cw*+HIr_66}9zw^6H&Mu(YF@|TB znLK!!x4h*p3|;5^;2^$k5Gl_U0-;7*VM(3lCXhk{B^qW4qAhPAqnI`!gE}g-zWhan z(2w3vN(6rWZqyJmARoAq_YEB(0%EBo*^SpS=Y=f0WgG-TsAy8+N`W3qMCehgR+yig z$1fHULQ<_(qR`7Aj3l#2Vy4a6(NP|H>J?NW`0U?&oV_>g;LL@~G^Apr5;jWQLY0Ds zWExF1St^xC*cu%@z4)~n&T>9_#+FSY2|=xfOOfE>6qaEUm;s@tWu-M@fFr@-oj7MOp?A_V&u{^&52XE)f#u+YVyjV zLC#O*7`}L!Z5!5b>rL15)T>7jfv?V&oHuIP|AX_!!}>YL@%_-UY;04D&|fmFhga3V zhS5|)%7AoI!}B7;m8~HK5-$|e)D%&5CAJD(cjji1!?ZK8mU%bUPyH zP+x)SR+Je~4-Jbp51=VZJ&zzV#j2VH(yzAwGU8K9iJ_?kVR*G8_k%hWNJPy*5OB4T zP!#dAhNA9s5cQ_#%8^%GK}3e&u+HYc(nRRGLa1njL_UCOEl>jqieDwAMr4PCp@F7R zs=AS3&d~AY6&X>4AWisXoXIitz$eq(%JRw*sZ0a56+@BH&(qq}L?xeRX=WN*b$RDI z@4*e>2ai9)%JK?Ai4p}3)5fV)aH>^0JKJdMXs22(6NDj`re>%*4qgy(hF4aK^!9dR zS*E;vc~&Hn2}}fr8mFIbJTYxVS{NvyaB6CeDtHa`wVSs;V{@O2d?$}{wR%+PI?F7uSb<=uWR1S|!5g3A0 zdn2VR(_~dw8^tq6P|A6B?%vJmg9mWZt#oeO z$yCLq?0Q#O?TV^$^3oDJo1188>)@lm{RukSTRC;=9NVtDi7;Kj3k6R+^%Kqy4KXow zndZKAB0soH~u~M6w_$12kkr zlo2Yr5=NmmLPUl;8A5%#RrOp{35FS=Y&UOQM?9V4_~9cowY1SSFu?I62kGx0pj4_d zH#5nm&09D>G(=-dGg1h0^9!t6w~?XaN3dFZNe*o0VyPP4$eKcPV|Sx^9PR6mOU@4)hfCCia2#{5-BC?*YuDv0l$W#85qe1Hg4L2(Y2Nre)>~V=@g-i zrs9UK(bm<&`rX$vxPL$5;xH|peT1&K8a5~hv4l!8Ve|ah0{4ICSuU?Ql+7%Uofzlv zj~`{yvq@jKH=@wg)5#T~qFxCE3!p(4IJGLzoIB4gdv3rFB`=;hhvNm*Jdb1N$GGpd z-BhbpTr`AXV`(aF9UVYOduJORy}bm!k0K&+nWjX6bNNDnBPUPec|N)sry2-iF$+=h zs0BfUd1F`6tAwn@g2oI5wn*S_(;=f*|&;Y*Qe^9 zFXw7isY+8d+Ph2Lz21L#p6542U?hC)zTHfXkI`tfs8p&v{NF!B&a+v(Xo!Vc=NSN` zpg|l<4jp@#1LtQc^%VH&BcElk+#|Mb-Ap5bOfJvHb*nfLG%!#sTQbV})yqlQCOvC6 zq*IH8$HRM0_ItAw30wq+xem{{1LAT`hroi?$I$+%gB zZDHGns@2Vs2~C_*9vXr~ zLOqH(H?zR8<0q*$nza3pTBD8ccSO`lfRa_GXxQ|)HjmX|BGKU|O(hVCB86_aT|)y%oo?OW zn$T35m-2hBeL0)ftYUg{lBm_B(&`X}A*+^-FxcORn@TY{|`OSHUPin zD8mw3J|i_GqdW02ObvW8EfZ6MZ5p`Q9Cjjcy%b(LO)8Zll}ZVeB%LcT+?&JpvgGnb zdU^_g+x;yT&tQ9r&^E55OZC$QteZ+9Op8;e$1n^N$1*W&8%0-#uM|-jA%w2XlSIK~ zNQw{`|It_r&oBX^t_MJf%bNjRggdrw0D?$jb+-wkdua)@u26fR)xS%Qgy=$a^`;}0 z$>4epolZy`M3_q9w_1?S6G?#|qI07YozaidMr(nf5H;vbor5^0cW{V$txB<2q+PF5 zo1DV5EuugJyVhTI1;R9$K5>}8{Fm=jo0;U~sc~G_qo_GKg(k z*e2w1c}hJ6j-5Ee{{2T;zI2paCPN&@96ESdjE)XbEcWP(YbD5KQ>3ToICEy4-o7#$ zHmzss;sq{ToW%89R;^sdT&2eRTm{Fruq+#4S}fFBK%3*o&+x>sKL#VC=#KQ*#xr+P0arMXfcW&lyzxXY}nHkQWy@;|cCQcsV;yvHw!t<}=IoIu=>>9MH z3ydxr<=t<83$yhm_dW6?GW6-R+t{|nhE>b?*Ux>L+4(BPLLSSp$!4>>?B*Rj=b9@} zhRKu1#;CX2q#T=fy#1~C3AB8lO)D0&w6BM=vo-dgouKIl}V`yHTAQ8?WBM-lunyqzVjg+RjWT0x3yZ7VRj)HciN8 zc<54{T05XT(9em3d$}|@ON7CfzyAyRmz|>ATjDoQ?&h&4cGHR#2WEUy10!6u{YvKN zW;uB92&>m`V0fUP{rmP~8y1sOQ&cNeo#UU+(v#0)C_NEFDZ)4*>>3$KbW=~aDUdQD zHcYPCx|u>I&90~SQRwL*Q!4ZHoX*8O&8gx@@dwuU&-EmNAOZEgTq7E zmPNDGhVJGt2m;QZyFjT}qTLC2>Z$#7sta7ac!@aMi|wV!*dE#8#q2+HoF$8f>B$wC zT4-_V>?G^9Y~jqQGc^5#m8;gNh93&c6pWo7M>*$t$&OoDwtN|en?hldb}XhQCpfxi zFDurqx!%FVBas%JkeFD#OxMtO2o^2s<4JLRMe91C=Rr ze73=jH@<*{MuU5f&ymRu(CYZS>8ztHLkQb6NSih`4!-PQm>zz;foL@l*u-HCJL5qlFbo?vlcpW`OjYabKX8n( zi?jHFPZCGU6#8@HxGuKq3EAcB#IdFnYsQU%QU+2cgh@ouXz}!sGweEe0>`rGEA_B; z)lxQZ-ay|-89R(=)@rmOAJ1_S(je+2*ipb@Ghs!NVnLP(43mN>bvmLDC?)8`5)+9) z2a8B4@$x-<>7l)xoS4OQQ;5s}WCk$N_0#DvVyvPts{!`ZX{HwHM1=t?+e68S$h3$| zi#TONA`zJkVNl0z*T`gZUyhJ%JBcZ^K1j~TTX8=-^pguv?GgDu0%SW z(wJ-nuB%g8ve`6lrbpG=3e$42u?13!`AU;yu1XL|q@3V{}5?n{?A}_~%#)mQ_6tCG!RXjE#* zIKsBI)WFT8u!P{$o;|GDw2^`JtN6~hzE81`;r18ZLFoG&K5(duJdg1_m({CQ5Jv&^ zMg!9@nVOnrWMq(ZCQYSM=j53S2qgJjnw2Y;V|0N|m1>=l(GgmWI*#KYyBXc%r%y9K zUtwslpH9ceFbpjX5CSC(sdBrlL)`#lQU!bvnjrJ&wXP3;$C|5X=dja=o=ZOUafJwJ}*|RTFLQ) z2eCbudMh9?n*8L~5AmUo{25Oi9p~jnd03ZNKL_t)qJTlp# z+3`tr>P$rjduxK|se`=s`i;Eewi|ffwO3H}Bfk36`x&dX+5Eb@c*U(ZvTemuc^wEj!$-!LZ?qA8i|FwjhCP>*ZSv=z`wFYptY&hyihue%mT9qP?_T=)`xzY>#t&mE zVL~;O-2LPG=JOKe-n>YO!kDb`I=*950=tyy;pd{FqJ@A-f+?*EA7G zf<)1uaR?^QvvB4N*I&Jrsrd@c^ON+Ja)ePt=yxzhhg_jRb*f6MvcUFRZ>QF1aO}u& zR;=4Vxv$KwojY+%6XAITzK@s95j1L4X6Fb!kG|0%makZ@jrxX#N+RO!PbP|)lG zH)7ji{NzdYj-O%46+7s(JM4bsVM;xDay@zWJ^mX;R;;1X_Gz~otXQ^`1AF!`vV1vl zk}x+r%er;zIJ{>!cA<~Vvh_?f15}(~8U}$>h&Z8Dsqvy6+t{>rB?s>N5vH5r(z!D{ z@$h|Wy4n_{oJVi(a)w4n89#cEpZxI07?#DFH7nJU!LrENihM3ZV5h11A&>7n&286h zWZjw-oI7^`(=aI&3tA%BotVc`VhWSPM^EthqfhX@cfTDkSLBO7dH~<;p^(qfld`z^ zIX98IX$SLD6I2%}LMVej|L_O6;fCw@>bJhb-QT^3Uq14b5SE2V66{Qd8&)jGPZY`E zO7g`XdeSb5Vd9Oh0Cyi_Pw!;QbGP%EPks>3Gx0keq!MJaX)M#>{KOP*eD_~cX;dim zj$*beWTZmm^F(Vlk*EaMaWE0YN)dJmv7k2%3RsXf_Z=Q5n@;h)eP>arEW6H5adfst zs@Th=z~Jw``z!i-atPDHPr&MQP)f^2gzCyQh3d*&Og&*v5`>|p6prmsZ8Z7LcfQAk zvsJ9CZo+aMgjD2Qhm2_u)#t&Z+a~cJ@zE+W|O3&$@GQ{D3ywo zOJx!%S-)-#Po2KR7k>U5cI?>Bxq8T{{bS6vn!NF|-{-2bgR2q}!$1j>i}f~593rQn z0dpcj2!q7X638f#m_li&WjE|XD21}jE`eVA1Hv%W9vWfLj1_T`;JOYNHohMc#sSLl zs3ZwVlwepUmz^92k_dxFqCiQkuH057k(TgAAw<6Zy-|qgI0!@gUyL{=?uJ8nHpDW) zG)-JLtvoL+92XG=9a8-Topz-Z%CI$0!f?7mG6NL@hQx3TR7YZaE^P~*-o20GCr+tm zt1WQS^p*3(Nfs%kumoV(T^SBorXcPTbY&8g#4!mFgfW315KD(Rj8(yT&P1B*N6sd#UIo3a9&> z5I~q{!+d19j71h>2QKQ@Xc!o#fz|aB(%tF{!zM~%5(K%lhfby z09Rc3yS(_NFQ;Cwa~ag7b9=Q!Nf_E4?C6Re%hb`JIy^{VVO*Bp1EM?W7ta*_m%mBf zAJg50bg9Ea8+QzyhDoBpLK8we?GEi$t82VfWGrw@Nj*+T6d)9-xJ@UCF-#MeglOhG z*pK_-)-*=Q2_0dChnVRiMNph!C=hn{?#_xzWaslWTvKM-I0);Flso6N~b z6L}32%N8gZQ>#?S<+C8c@f^HVib}PPA7~1r5;|jADVUm^rqgNboOcARW&kbkQg$C#&o{{4;j$ zJIQrBuA*75GcmKDR;|Vpdrxp^Y=)P-WV>j$A7!wwk5}Ken5n?vAAj~3U-*MpGd(lU zmmb^2bGI$wy?4EW_kQ!2sM;ys^T)4b-I7s0^Dkebzg%MdruAx|kQOy%vVO3Kpa0~C ze0g$;wjXlK^IyOhcb?+G)3e~ZV7quhi{$Jv`bv3-L!u`RuyONdj_%t>I|wKZ4RPZ5 zd8`u`D36TNtW{|>8Ylzk>0{T!k1?`%F^A7j(X2HnEm_S)r$n{d;ppjcE=|udJX&Mh z#`P>693&2Wk|1F5(xuEDcmlK2Wc}7{9NfPb;pQoC*v?ohBnU&&woR-wU{7{ED`BI_ zi>_UTvgdg`pXI&p{$tvH#Q*rfN4fLm&&TUu#2@{^gM9dJ{|7f*e-PSlQgDh$|jhC(9ROioX1TPUj3Y_kl7+}WtPu=<|F*^r@zSAg*vM@ZsPF4 zgREGymTJ95b$*U@>o;)f-~rNw64^DIm=6`DREpkQhB!)SMKO-$PzyqeJ$)?c&9ii% zzz5&^4$?xge%)G8Yql8aD{<`PIjZ$0S3LhY-1+<)QBqRKr^Q?U>zzEd=Qso99lZK#=GA6b{;t} zMrzj>vtwsDb?!Wwbe7fYHjv6@DW)Bk4-}D7(&Jk6XH)#a8(+(dpMM8YoFL-}$8o{3 zD5e~~z3T*Ls~rN%<>Kj+v^zf8rEBO}x)%S^S!QRZx%d8`E6*{+Lk~TURDxo$!1CqG z@U66x2qA5UxrKQ?@q(?a9_r=y?tT<91w2C!OQe*9UH_M5=z_#jI(3C~mcMxD7zjZs zog#ER{^I^aSgu29nyu7sC+Pw#%jQF``okvDRSTs7MA(iLO@%>*u z#Knn8Jj=vQrE#()=I7^e(&^|^JmA|H<$rHHV|TY^5%pxyCt3MHDADldJ` zmAv`Z>!<`i6AKOA`Nbcze>x;YVwgh5Re~nJcQ?|B6V&*37tsM?1U=i*;>|QnlytJK^%0`{}hNAC1Qli z;0T961sptmn*ArnXm@lw%e_5bWI|qLK-I7V*j%>?f=4g_J7v@ z!_mgf8s*+1N+`l8Aqv{aB-E1yrEm-ZX}toCF3ZF{(0ij?Q#rqXzxhwC`lwu5D9W3lU{u}l{* zXx1;#_O%S?a*=Kt0>d#;620Dz5EeVo} zZak^JbggbAsOLhfBMG7e*RgShA`U}bFOTh|0fkH=(w2dl1Z0p*cVY(01+tc6E{+Jo zki_p`#4)*Cj!v^qCYz(#Y7zMwxRoRl!?uW&!b86v5vUArS(O*a*Lq;g z)1N1fVob{>3OYEB%bBrpMn;C{=_ydFH%O;ECMTw8wOTliOO(Vorb!gXxSqq%@BmS) zrzTQLq=L!GY0{ZAmTl5*cQ7rJbS6!`UdOU6!YI*(PS>H)@^u3y3~bwA$wH{M$h$2qMm$ID#+@C=JpG1%}y1B53N?Jz zIm^XkCpk6SM41+y*%_>)%{P8>JXz0T?XpGu;=xDw?B~D4^PjVgLe>!1U$u?(otVC~Nm;a*xp11@JNHl; zS%xSK;S8rSZHvSZM6=V#Y>{a{WZkx_2u>fPHao-CYqzt1=PuH@94he17YdYmOEe}g zk1#MNF-NvoqEsq!{Lo=?xg378&VgNH ztl6>+k;F9pkX+p1qj$ZMKl#kRvGc(PS-fgB()W=`f@4{rOaunPxqRD5gkhtEMH2bc z7bdykmaDk&nkzVWVS@Qai^Ee1mnJ9q^!whcV*>uyOMiPVe7? z6~`=DvzCbj(jq39x>*APVkNOm2P>r|e};faCD6SmY(q;}TGcvx_8q~r3^I;`g~D+xmM>q-rSli4Hhd%r zN-9iY(5O{eyLl@smMtbdG)t7up<>M;sQZf8vS8U-5+(3Fhw-_2{{Fl7Vzp|#=(*Rj zZq+ire*aF!<{DHYMTCiG+qgg?&fzNtO}C(n#w+73g@R+7)AI5pS6Lt!w_ zY_-AlTi3DY@ChnSpZN>pY~Q?=eN#0m={}mmq2foFrb#~S(FuHvxWgxY@N25gCU@Sl zgC~xh=Gbf-+sP2f7$GzX-nKP`SxHG4MS37*=we;QNmqJfkg_bS+5%ChjmQI5 z4DH2>lSBtgq+EJZISu)AU6DySs?n-btF;g+c_uVN+YkhXZQ&Jiw5R8>Ob634Sg6-H zer}wLGZoU=94nSDN5&yTeZ35ni!_3OLMDZsC~VhZW`3S?(^FWcjc2Lbdc)C4oRuRRK5Mot@`Zwe?QMQ0KerN zd}?pl+n3|bZ+N+evRHylUTd>^3R#ASM@VI|q*ETLbPm^bNvCxdyf6%U@)=CaL6~|1 z*3HjBf7C5>+Zxi%EI^?UNRV+iRl(Le!z9#yPGW@6W@ITX+N}ywYHxy)ahC<4^h!+p zdm2!X=u0P&ItOx`aTbjZ{V# z02V221a?wcO|+B=Nup<)BneTXJr#ZsQtI`{=X2O9VPvo$({^aL+vKtZ8m$I#6l2?V z_qA9^bb}Ih&C049(N?K9`03An&ZP^JTzU1?%r8`t!oV^O62l-0LQ4H5;y7kvVv2Mo zO%x|ITOGQAWg1!TcNpp~GBh;E)YLTTbeeR^#jj^P*c=*4M-2%pA8o=LS}io=Oo!IP3#!&h@N8R1C5V$)2W%iPdWy(oDM=hLFVZX? z8e(pI4BJcT$#;_A*)~BC&}_CzWiphPEMx5C34~>nEfkqLe-5{AnBzzH6J#oExNel` zEnEnqF1NzM zbsXAZNSGuDrI12&0eH~#Ll$Mz7}+8db2WzQiO%4_K@~$D%Co}p5Vm!3v6ArjFbV@b7N#Y7aR}&a!~;uPI1+>*Ryc^G#gefWq7ckX1htIRAzqi zIDhoEPx5CU{tFHqI7)wiAHpzoRHKr#+a3B!S^oMj-pjo|{vmfEr2)irwkb3$r zyW>XNFiE=k|3-I$8OD*GY9^Xqu7uL&Q>mzT0*q20#)@?q=`0%;_4C5#-N4MbVJyQS zn@aQ4Q%^HdrSOB0Tdum6H$3lZF3ry2xemFWB0u`&Uc77`D{K=BlbKo@-_4OO6d33$ zW0Z%OJh6{Lu|%g`XYBYfZoK+R?zrJvCa0%Kq~y?{qul=1*Rf^!BHsGGzvREZ@^(J> z$8Y6jAN?n)K}0%VPIG*dANG2ri6hZV~8U{DRIxy1Nkp7TI@JYwN@a!y2E_Tv1(G<%^Q_o34J!uXFwxJqR0`8|m1!Cxk_o5JU*yu% z1b&pz*WXVmo5ph-h6Waq%4CtD&*IT#%1L>m(`b@J9hUU3X7yFum>NH?#!j3TYnP5t zYc_S7pJh^yI%EYHN>EDWi6RYDn^OwPW%8~|vzX(;%mVFJTX>$Y3K+ugbU1kY3@67g zar-SduyMtxYG1k_B0nLQbBLSsxJk@XFH6p~NgF*pnbikpy)@zk@IxT2Z1W zk3tvgi3A}eNfe-zK_U|b3e(h+3t^ZTmW`njk~l^xfnn-Zmu)GMr29}q>+uakPyF?E zRIkodH``MPO;OZx9xa`TyRn_7ssAjK%S7PI5~9oLKiU|4Ip;s=)-2s*Qvjk^|3j2&a%on5N!9mZy)eU5hflC&^$KJdv1|Wf zZrZepg}GVmBxJC!jAcM5Z0@=538oi9T2_vZuMKZcKm2RX96u^1W)^tGoo{02Q|Gkb z!_`r;hGAe8OGHx978V^$lE^0|eUesGy!no+`O#1B#V{-~=@i)&8#r|0F!frKq22=Rg$kW;R_wU>MoyeM%f!?)eIpxi zvT4G0hZE$&rH?x4CbM{GKDB)UK@lre0ZhLptpi^&EJHV>xB zD4UPG<+X%i%%|>ol*iAUBiGYQ%XSHrP5_!2A0s+@lGNty*tr667;t%3EDS?8JcbF& z)|2=x0Fv%h%d>4-z7M8BBD>HqLvIx5G6hs3bt51QqA0|0J>v2p7$zd_22==xXCAT% zm@3w}_uV={smtLSdNU!S2rW-d6Si8+SE^bqAf!wZsVp5lr6acE7|ZiW{I-abm{XIJ zT%4Y!kjYa@r4a(khDGm-|rP4|TZDF~NsLjqn5C91ajSlsCgHEe0;yB^VrD-CW zFjDTpwHyp#V5ck;kaANrTMg!F6@~}PEHW%2B?)DotY@=OZ_-YLn47P%P;Fw_9_X@j%5IqgltCgD!~seO5~;76?tEXb4u#T%x6%aB%MTyfE%cu; zMxiG|PFMP)Az|GMRA`6(q~7yoYy(3W)PfMlbMaDXI(|U0x0ho7Agy+jI8oT9qo;9FVY%ir z5v7;oN)0Z@mzvDA6Mk^-Z_kEllcfEi;Cr|VJAN+`KeeG-9_4-#ac4mx&2M^<=(in!pL-*g$ z+{`pDdg<>FmzMI#(?{5{bu)>SJowZhddidh{_}6(?r(mZg?f`W-@JvJx2)sX#ToAT z$uHPAm}hE!fklfJlg{TEyLg^QAN(w-Qjw9tUOIk26#86y&2~b60?V;U%YY0qCDWxL zC86aJ34?-dGLX*`%%5dxR`AZ(zlgW|;eEX0-G9KhesVv9#jLvZc{hnadGKev|1aLf z2R`)YT)(W0+`5X%>1p0@=bQNZ&wQS{e&-Gz`1PZ#UbB)vd(Yc=*&lrv(@kO8Hb+he zB$ka3k^?7CVDFqAcAmUIU%7{mee}Z!l-}&vHo0t;O1+6~8alSuaY+}72qjs% zbU6cq{nTcr=mY`F1{U+-x8KDt9^J*`PwoacO%${#Wz#6bWWHAC)i1o2p^;IJkDn*) zSco_xPzIJ|kVFxER?JJEdku!|QcSy)d$O!pJj%Ua{~SMg=m`wRC6n@KwmM|k>!)U-|w$bXqO`?NcA)_BZ}F@}k4! z)HGvf$GG*@8&whqqEs%?Y5NS1^s8*jqPMqK3=A&e2S5A)%hqgFs~3-oSKRSjzVz*T zxc7nIFml5kw3n!a0EUN7euimkY zS{U=iCr^S9Ow~G!E?uHt{py#ATD?xA(V(|nS+H{5a!3n6^(*d!I-C(}DZwtonOV4>b*rW4cKlZ7N?Axc;^)X(hX1f4Z2 zSiE?Yfxcc=50+UvP-fr46w)?`Wk^HlZK2&eL@{vr=RbNCONR&eiG9-(Z(@rE-lKi_&gs$vcueI^|hv-BRHi96Dz%*$4-DW|m zt{+V2^mBO-*46W?{{R_t(;3XgtBAt@BaT3I(`~v9mQo3^VF7w*XQMZ%+M{4no1JHI zA%{w*KqgfEfD0F=80s(K+Lpj{P1m-R3PZxc7e>k>YIkV2TO2-fiurm2$99P&xVAyc zOObJ1GNoZsJq4AtnzX|hKdK??H4H~@9)nsFzuv-1+4T1nX?6nL7zv1Ej6l$AwQy{k zN~Mah1S(N9TOHDw6rD~7)g_YmmkR7Zb&=C&Cy3Gc{)Q>AU56k2_+FCd-^8_>H_~X< z$k;AI82E&wF%U_IE%}hBV>4qal$W92=^(?91pV0+-8WBl3zq1acT*vf7}-@W7y>*) zko8g|iK6NIBq)#x5|>EoF{}`m(+Iookzt}tQ}XQjPoHNSfZuY0q@^&xbsd&2TSGdN zqZ27y%fPl3h6*s0j=&<3Sah|0iC#yUrXWlNhSGZZsQWMwU9)KrL^_qH`=t<`w` zGka~Mi<6jQxr8YrnzagMwuot3mxJx}1uS(=zY+r1G>8*T@>RmXbPSq7iyz$g5T$I2 zLb;dWB}**<^Aq0-=kj|v2*4oT1OanHU z1|A+eZh0Q77Y}j6_A7YL2R_QhTAiD2y^Xtnd@omQTuatAn3$gB#!ahPvScZ)>+r63 zyoK+7{~pedkJH=Vk5UT1(iOed_(}Jvz>r ziCKRAk00l=U-~BR|L`Z+a@`Jo`pf1>F zzyMY{O;D?{cke;cnG7F#=i5-iB24tKVs4?rvcX=y`-=zpr@McKT^?rD(nXk+OBC`M zjvhOvMh1F$$qS#WFdQ&UWD?_-tsPZ8pX#4yO3CW{JLtR$itD-s2sNHB!N zPZSUDJ|y1y`)}17nE4sDZM~Y~r;gGI6IQKQ&J%~v5C%Sbs~x_*cbsf*nNBA{1|d<>u;ca(ZO&ICd{pg`nyytt5G2U_coA3OJ2Yz%fU;XyaVd)C`)^8<~ zPSc7as-2G3(+h!26bELfNTlS(Yp&u0|MFcntXjrhue^f?51nHFY@0WH>MQ)-?brWL z_TD?p&g-uC{j7Jrb+_qFGpbg#Bukd%ZYOper#DCgoIp4P2m}Za67C5QAOTJaNgzNd zF$qbWVkb^WaNK+B*p}676|2|LNYiI_f6H3y{IT8{=i!oj&w1|s>s~KCk475J*52kqc#PG``VckJYhf zuvVH@Y=gnL{(}bQqgXdZ?D$NMO z5S68zIC%ycmT`g*tu!W0Skm9c>ZO~weDg*Mfsd0F5tRx?rMNXsk|ktuof5Dz7~#~3 z!!&Dih@n+D=){*HDl;gZQYaKi zvj$4%MY<5U)`-*9SW?+elD=h431+Kj1ExR;7ag3L8e{|+*0|! zJB|(CvQ2?KfQ*D@qKJHpmJ4hMNT$r9z&G$L)xZ(C+mB;KNxti#l(yj^0$h{xB(c0{ zgKZqNGNfcV?Z_TLPTs&Ml@X_kNZQAwwFXB}bcI#(rx`5;r9y$$>=eyvon|?t-D;Dy zWBg7Zbbf)x;Ca>$+YdZE*9OEaXaNk0Obd!8fI>cxG$A9P0@iC6iHn`<=ujb55jj=T1!sIlA-8~#Rb(T`4lh6L`Kk>}dJL%}| z!S#G=4OlGEp04qMKm8PEXInUNouVg6QpMi=hnc)^o*mB}Boqma*-8HR^S82cc!+f? zN4Rp+8ZJytqJi&+_9PPxH376{$Ds zl#3; zfBZG&jtU?B_$NU);*LANM=QxhD@pm?Klmg12Zs3INB)ediAk0(AK^2f`5eo8O8D)0 zeB&~m3dUa8O|iF+%9iVxs?~Eu&yM1Q>J0rNWwcZ#DQ`ndk0?vgK|nG;L(kG78bO6Z zxkB~uF&bm1xbphzNtC8OF^+3A${3P%f*VG(YBgHQu=?WljGaD(7lzitPTS%_gcZ(@ zjxn-qDfQ_o#!tRL!T0&mfju@HZrY5U(=#)IY@J;X}Adg7ibqKff1=qGQ#1 zn(c&EW^)I$$ia==yucWPBOM&qYJ{S|=iGtksGXm{-!hDLT@VuKdra4wJn+OG_U_ot zTi^H^I?4qedS*Z0`r(7DTCQHhrqyh+j0W|Z zq8@f&w4$tHsu{S20&aDd?kHqN_{3p|!k{roW02A%FpBp4Bt1Pn)ao^chnI46Yyu+# zGNTz@zJh_lCA{#$VdDi6y~8VnK3TJ_HeN_OO_)D%03#&MvURwn5-QDbT^DT(9){^g z8xzM+twP+QUY)}aLW+^k{;`u((_t6WeyFCm^wZ;@W z_}3rpqoj7y)!E68J^QE@JE5Z+5nANjXib)%mzJw)K`NCbdGVN2T=N_oa;h7SgGm*r z%ohDvs*o-8t<%=xXxqsXzH(YgelS~#5WMIBv|w>(?D;2+4IWF=j85Ohm9Et#2!VDS z;<$~>3PwbMi0f7Jp7;Dd(-%&$d(R6Z2z}PC9AIj$Au^-by?Ynlz5p!+QK7_OZ!csD z$CEUh3G=l&OP4LdEq9R2&vO3EsPLkI!L@6Rke$qqo)JPoAU)C~p^;>0ZEy<_UPlMn z{5)>t6E_nIg(87;$#jMcC8fkV@r0gBAqY4$O`+yNr}b=h`Nbu!9mCBD{ZsmB7)$hn)ZKVz4T=L z7weAiJ+}Yd@BQ`Lj5hDiGDRV@qD+~m4tkzMI3A9)qkDVc=0&?}_Z+QqzI?u^2n)tr zHQ(0|3H`dKYfLaHA-2XeF8?Qv{wQQ#NZr2tk$^q{R9G=MEymwK3{4 zM_8nE7yf%1siw2y;TnY>MhIgFeFu|ow2Ld>=%wqBrWt;2aVn)_ABQ85TCudJ$nZdg zmtS`UYgUc$gS#HI0zISIcG(u1jT)I!HmF4#n|%=YXk{@7S2|>gjSrEokJ5&ySimug zC<)%uG&l&C9RiO>cZXXOACY+t!Pjt*7QYPdp@k=@*N9^T$un>{@~< z_wwi8d4Ol86n$H-XxHb>iU^>_Js5cYtdiFTwa*3<1zKWGgN9gIS(A`m{ zIycR#;eOVy8m8bo6dgk;3c2i+uVQ4yQf3+{S8ThKy$6r*-EV$_y#rn1qM<>fj9}{g z1ff5|iPL9z=+P&6^hZzgnm50VRD_&7dK8^ylqwarU3(4Z_U^zrxtGy{d+F}&1q>4t zEu?gqoSY_An%U_&;v_-3F3;|Ip3cq+2M!)a=RVK7_8g>CE^+qkdBV`=$k9{zbjr5Oo#FD={TxS+A7j(ySF(TSvv{>8L+dZ*z~1MO-LtH{>`KlY*he}y3u%H|tl*Z* z>^%J#&;9Wy;MzAp5aq%oE9&Fu6i6RmCv?iwluSlrW*XC|Qt9kOwHpiu2CqIrt2IwH zdK}{j8ik0mbO|s_6CnK1>Y*052pb}3w8qV+morLWkm$ILUnrrpW^mOS8qFq7*u`kO z#$SBLBJws7wjBqefMCiJ-GexB}%U6Hr?aVh? z{MOg*#~96>zw=h^c?kj41aE(Q;g7)08aE$ayLrN-ko-Xkh_4_d{aGrI8v4ia4(1x!E>I*VfRUPXaieN0wTH3W2Z%p4K$e47WDJ zmwxrlT)u7@$H&Imwq^y79XQFmZ+jHu6mWDt^;Iu|K-S*U(r1m%3x79{oRzkS*I9<| zdWgU$ZnbUW@e{XSbn&rxeNGKkES|pF8gMM4a?-UwlcxD?Z9}4kb)OU35T_c@U>qwD z*Ba?abhRO}G@$59_V0Pp96xbd_^w1HZPV9T7M+zogyYa|HE20LMOWgX(d`)R2wVk& zeO-)A%`$%B0)t6HyU`Mr?oQgZ2F=NFp;`%Pb)KkHCR8?*Ok+snj4%iYdpl7D7n2%X z(V|&x(Tv-inVh8~@(BV-7H2e*Hc~hY^_G~cr!*T4E*kEmmQ8V{nt<;iRY*NL4HI7)|DUdhy z_F0ZKxJn~kAGu*0+6!sNZ9DKX)<`8a0-;g@*9YOEb2P+ppjn;q{)>|CrS((ROAWwJ zS#xu9k7r81yATCbN(Fphpt1y|9kj}bn>CElgn=!*jn+7h#E~AZ?~=xC9Fd_Hd~c=Q zPfVr>0@o%UHWQ?@Vi;oteh}v4tc(TlBF!h8un^*vch1=2+jGTYvEWLP+tfj-w6#*h zj>a(g=SLfqveX_gM;o!0zaVHZsL0$WuuVBpmNo}a6S82-T$+DSC(m9&xVqvnZgge{Qf0MDSNF5cJ6(i zzx(?yan*HKqj7Mh6$ysEN0xZ_VF3s0)*v!Lp%B>suUsXqv;yJa=HWtdJEp(4gC$D_ z*}L}uTeoiH^qDcHXJ#oB3(QPSGC4U3SX)-dfv8X-%`zO};5ZV4AqXQX1()lu-OkF@ zt9k5+XX)!HQ@(O5S6;r|T)Jh8*#F!fjvhV6#QAe#|AAw??vr05aSQls*Yml@Um$D8 zlzK;SL&>I1Tlkf}w<4Oev>GikZ8$qQOR1-y!{c+DI5)vFPd>%_CMUUO`xch2SW47U zvR=~NUDVqdFTdtW&doR3eQugNzIzvMdhJcT;|({l_2RW$ef@R(_<{TR)!+K>V$0Ue zTz%uqIDP62H@)E&l*(|!h}XaRCZ0WXioMI0ktQ*dCr)tc`4*R~UBSL59--1v#`kRz z;1>e2ETvp3F;}gV=!9Z1va|?e@LWm9Kp(DjI6FFq=X*GgLuY4&EceLwJQtN^lq(&~ z)Z3hV@Y}F_EzaOlW-gqhnpy5A7+Mo!lm>2KVt$@qxp5oc{pPp0?k!sw9vS8v|MF#a z?w35cx|4Ukd^@}EzlV3d>1Jl@4RqW_N*6~sw3`j9Nf{dC$bkc_ShJ4#=_$s}o@Hps z5;{9OICJ12JxhkkYBd`sBwdWrlmnO9*$XsVJ#=>s8~OhC3)JW5(Xoq^R*MqHmOf`Eeu_dAqO>MWl03azT3t?#fZN>w5KbXi6{&R!;m%Gw)5DI=jl0f zicMEs&i>td2&0fqTeq@z$J1am%eP(5+1=057(GLh#+3YCHox+9RNHN)dX|$)53xXz zlrAdMnAs`*>UoKj(Nk}3@Jl!~OvCa4>&aE6wm{19O>>eVXKV`Iz*KAsdrt{{p!5k;FX zV2mb=eB4SW`=5Kx(m!sx1}~|T9es|jEmzU<1KLSK8YlGnaQyrvakI$>-~2Lu{~zw) z2Twi6J6?7L4?X=X%eqQP0q?wW17CRRD5j%xk-n(3qVD-b<$h-OKTV~(kNWHkeZxy} z(k9W!O8iQJ2%3=QMU9aOC4?WF2PwwKT>#ySB!{?ay3jF(zb}>I+qf{>8yOI;*(*!|)_Iv`* z0!gm01@3&K0n%oxSZipFR}Axix3niRg(JZ8U6MGleXGe)d@0dx!0yxMNwwmhoiFgf zfiq-CgdZ$Y-xe4hi+{=WYiMJe60Jcmh=Bzq2v}V0$M$ zTl}kRQS57kogPRj^TuPLIanAUfI{b5Vu5fZS(@PZK5nT@ZE^ycrSx=lil?5~DQ4$t z6r&I!9Ku3{ATfB3KzJS0^QlAV2lVxH(Mn^RXOPA$?dd^Fi;X*u1kWQX7rAiyEJ>?P zXHO5$A3wp_6DN%qg`!X>5PCKjL!JnXavZ9Yv%*hX1d+#zk)@OZ--4Igp-?Q~`5vvf z4aQJ#C5d#XwVU)+B5JLenasg27D-)~vFREI&Rih$mms@+Dp83>+D02gS5#)Ak)SYC zJj0f|G#iA+K^X0j({U-*XLaE=0{Ti%chJ1Fa2VAgm5R8#{qCBDd~*aTAgbdGT-W zC&|mH-!M#ajC`$^_F1E{F~m!001BWNklLnbqx}NGiS$`nwdu! z%|e8+>j=VC%W+*ByrYpwVFg`EWeDt)q^GNssmW>PX6JDIke`^Y1GJYSW~DFMj_^zJv{Qv zPI`+)HeI})Vxh=4?z|mT#@!>`+;#V(96Edw>a$#P?KRZr=6T}{S90y88+qWN$5{3Y zZ==*d!f*ZFZ!>lBFdH^)qVie@`uzG0JYe{lExJoD7Etln}tVHnV! z9^>5~elK^nX4$dh**pQ(P>g(xc1hFNj(9z9u^{qXk0=VsvWze+;(I>Qvzn4Dvs3^_ zN`fGusWr_wBarZ=zxy~-vXi@ZAI2{fP)gwn%gddc8KHAv3ES7N6(~mm)p~;rLuFu)j)8s-?c2xd4I7xAnBeT` zvkVOluw-PI1G{(8F|>k#m1{Y%cc-P(VXXMO5OMs(X})*wqox&S!jY2m7be(u;E)J> zAL)5)yZU9^{m}hPjF0oTrW6(^l?o(D%GC5Mp63x3Di~u3Jde5g8mUr? z%@I-(1fB&#l_E(~TOc_OQQ)JL;;XlPlX|0$=SfB<=FL6#J|ymad>7%sGAMT72w?+? zQ1tirQxChi`VBwBp{IXD!<=I6C6{nu*Df|(atYh7zLveao~4;8mS21cS<+(i4w{Pdf zg;A=tDt#T1*?!sO;-BxkpUoTA@aApnxcjN^lEqy_Jv~V2;bCC>9L5bu-2gWTD0z~3 zt!OL5FTG+rU7i*5n=GZ#jxoZz#Q4%d7^~|Fuic19TGZ-IuH3MaiE16%4dxH-rDOAU zVmsnQ2+4)1X<4`X%)fzuMa)>Rf*5f?34}dJS0#+~Z zXe2Qmr6Pa*kq^+-*-2{bXX4&n2l?Tir;3No@CcN0N?@amyRu%<+>axp~_LuH3X1*YkO5&jDHq-2K#E zp4#~wGjns4%4OQJK-nwfdk*dS7Oja#tB5G_Kl zG{SWdN)sn(P6=^dEdF2oFLDuzRn_Ad9+j;M_E660Tjzcg0Mh3 zJ4FgAxz(sfx2Zur!Azev3iK$gvNCO>VM3Q9`WQ)O$kk(9_My3(Q zW=5PGui^@a>q|unL4h=Lh*eCgGCaqgxnyldyo9o=d8V3jQkL!1u&tBwEk;=i>1uhvTqz)x91 zIL-p)B(R!ubWX{UPHz3Bz?hgcGdZ;u_Q3 z7vdyO$1?_#YYZGmfL;&`+hv75wrG})Sfuwvfn z$4JwZVzEG)X^x*fOQ~F9-RfoZba&-KA;tWB4bS(im8EoXT#17wOEPH?B9qta2KT5aGJ?R82=GFNSoWs1A+dxD1^ewtKiQLDF! zN+ph*nINk-sPy&n7oYk9Z7msIy_Q%jFxJY^$+@t`^^l$2Jl9aX`LlPBj-7=g&%yEy z6gFH!mL@FkDzRq!Rix*R^P20nvuv=B>3WMZ7sh$-FT9Nd=jRz(zLHP;;rrS1!ZBL4 zd9MH2oA~)RzlQ%P229M?Iehd49Z7|ce)#wJmoMGM{de8NKyRZU-Xcp!q$xoZ(rUHQT9GN}>+hvjt!gCr{laI|9g6HoGM?|LgJ#nDrvm}VW{_h~fS_>Ms*2^~X2 zRQdR}caxo$ZL)y(IT5Ic@udN+$lBR@2 zgn>`H-3APSCvgHFV>FFs3mID9bd|eeDQ&?A;Rw2V`}w!8ew(j;B}7*+siqN2Qqs2r!g7x>>(vD;uxBkv)&zPZR`n_w{k&)M+lh{BlM%Y~sv;{Rj+8 zw_ZuStkZ{%o*0KTT9sN6lV`he)S!%WzV4#oH=ovmk)Vt+O&*s?>k3SF4LNw zV&a*niTe9_?dxC3p3~!0wM(U=gU4Pt#pSD)vwh=QnsGv$*<@KMz;gtS;~=CYj^jmi za)~E7a^^h8&QGyo%cV>lJxuG+Ub@$AW(+ttF~y~8SMch~FX391IPJ;|Mq6)6U}EIKZrKDFTCg4;5F-5u{c4ne(^bd zCodn(BDF{4g5HHQ#4OTH7Lb283<-oorWJ9XoJ-u!g)|=0_hD`lbN)0+C{n*n*xgU; z*oMJ45|i6+Cqm-*p|zmQGd!}mjcPXt9G`Mu2TG+lMljIR!+fodBVCiFsc5ug+|Wfx z=o#$CNi@dMw3|&*6i#ZO-6mBjQ552Kb{JJ}2%R=jnIbGict}o;jq>4-d`R5WwRtTKGJXn3BYpl^ghCrH(xUFbPi9%TWPbm>5&j!fF z!@_Y9j(xv42GVx=BCX-2^?$owY5;!9($cja{Fp@%ugOtwnfv*Q+y-m`g%?8Lx_}Xj zNV&*OJe4Aknz3BB1(B*9-P_-i1p#hOA@OprT%}Ad3U=~wsK_^2K)lFhw;ui$y~uLo ze$Tb^AU}_qw}rb{6f2W|PY7FF3*lH=lH-zTh3{HHY3S#^`$pjVA!#!v%M4*47bgpG znxV9!ySoeN`F6~gi?v+oAW<~6)eC5)(P?Z&#Y)-7y~xY7Ite>raWKLm!{FwE2;vDGVJdWeg)z!swJ9jfRHAA`5kxz8&;ik35^E?dJKGgD%?Q`S^O{rKw<;CvI zg)w_=Uci#!0p9+WHz2g(j_?1F`|iG%Qr{p$+pcFO$#A5gm`_jY#$LaxGNN{suE=G& zzmNHJ9mSq*qNIkDE_DUn-9rp?lo;u$5V(>b9XJNYaOlKY&dpRA=nDKCLWc zetwRZU2z%5&P_0{98OKlb8h?s7bd2t)!Hmu;?ddJ&FI)Tt+Ue%O*O5x>--E;=SJDG zX)|*t4pOhyhzdoFu{3~U5K*f&C`3N>Mic1>y1FV<=W7IEi0ipznWkE;(P*}99);u3 z-P1#wWlT)YPzXJI-zROiNt2YQSfDmDg}0=WjT<-8PE*Stb!1Le)}&f<&l9^?vvw`( zHf&(ovZX8?9%A|Gi#T!i9KU|cTlt6E@8axSor(D-uJ6-wLRM^8j~9g;*zq*0mM>>^ zVx04*PBS<>j9&;jxN`?#sZ7+-$?4HCy2=G~bp|JJX-S_-se}P410yV1y4(uggv;R< z_OpEBYK8^}Xw>T*c;PUakPMB4wCjx*n{Daf`yRDM)6$U~3oxWfk~^VT&RrNrBuQdJ z=kn&hR4V50MVGm`DoSgTI3abfHX!ED0vktMwU*MFNe%Lmx~>=UB1vq*n5 z#9MyuZ43=9;npwx3j;&LEFI{=FDS0u^cG5`5)VFqoOf>7z`Ef}x#iGNZn|O)5My|c|V)M&yd#(7RkNq{Hrze^2 zG;DeAJ4F)T#^|Y&EFW2eCj^e`;$|75Rz((yP$=LTL!miC_3(4_c6T$hdJCTCTiS@{ z6W8XsP@ka^lqfD=!*_nPo57wAHf`HV$#WU*@8jObpJMywi}{oHy_A0-=Q3^abR=a_j12Kr8E7WqSM3(nG4uIzBC+^Fl0oQ;Yn7%-Ri>b{6>k zpSgicM>@Iw;*}h|FiX~sFiOcL_*!(=aNVeEPlL$-hYNs7=ylaMEXOBX#m zMS5&6>A*_p8ML=?y~QS>kTzlB1Q#tEMED_RPn@ASbDnTuIc*^UjZ`VhC_9C=0zZTs z*rrkns;wq|=u;>aNZVD0Mus^*Hj$rep5p`(GEiwoVhq)(87g6knO2p^59ka_WHM!X zW`^F85u%<>v}yCmE*Aj-(tXVZAM(PQ@13jEL zewuIo+il{?>rSAu212B!REb2bRtFp$1J!DkzP?^MJ3FntxFcyBjWW>TXx0w*k*EpI z%(T$L!I2KNc8eeHJAw3FHmz8Ki^TUljIrlv61ORNK04D}T^YC)|Gt}F8F9Rn))e^U1S|8Bk10Q{8Y z`@V(4jmgEl;L4u>B_xZfxULk7Za$b78w4qB@!xD^c@b=jTd+2f#^eowuueO!<1Ffs zoSYSzX4-NMg~$_lbGD>e;7r;Nh~?-D+6knYA@CiNRO49JeCrmJHy(j!`FE0>o|Ioh z7)Yc8NouJ?3y6xFbN_wM^4sGiMhHt!N;91|8TN4*ZHNjbgpk%}-{d+lrAf3P$ub=2 z5O^MLJ0($yI8zA6eNhyYA0pa59jGj`2evB_+K!n$UlJz?BW0IA`1xPqp&$K-^XJF$ z`~u@+qX;xYTSULvs53W{5XUh>#KavXq9`Pc0^04AsNh+OmC~p*LkI^)x*R=m7R(u> z>r(3IKnRCSYlQ3N_N0a^O&5z##}NpXSj5vnu^6J1Asp(Xx2wR?Wy_hK7zYWfmJZNt zHM!=pHGJx$A7ID+lYI7D_p)(lgrhANr&uAYS8>~I%H2J9tr~ywrmK0!HJ5N?>;jpF z{+=#Wnj#&CcYpp)&Q?Y-?sb$Z6)FXrR(<01 zX&mWuZn{c1IKuG@=lH;%f1c{>EIk85%+zDv`#XQc`H4x~s3<=Ej$h#D-H*}P-HmFu z*!}EIE?qm!ufF4#xaa%d=b?ulVQ8=~f4{25#wyD)d_SO6wse`fxp}&}I_#uKI2fY{ zTuHOpM7ln{@6u?t@V%6FJH`(p95R0MeedCHHRJXlzd%$f+fPaE5^~XsJ*AK@96!mHRm=IS-?)X(|NFz-@#J%S`9r_P@L)f0|J{!g zSIX3;CkdK!Of>6+o=4JZ@s>Bej;>0XnYlS$aq};5-@}jdl`njO`NSuQ6Dl2*+|5R! zwWgz^OrvS7JU!n-2-_GqPDq+&XsrmN5Z7@?JeM@hn4O(NDVxKgGlld#lmX9^oIQ1l zlgE#;YSk+K^uxc&gO5JW)QslmUw;D+KJYMS&+NxBnkXtT(T2*Z^;~+*)g0Ng2ehJR zV8}M(LefSu*GL(t^fIt{8)FCdVzQL}r7QBi%R#pjNTKD2)RV;OhX4=Aj78q3C(fIC zbCPo40!=U(#$gV4;+OtEx$fT8{#bNcjY#^;*i*Z$jk`Qv}Noi9IekTyP}lQX>j zij8!yS;dZ{XSnnJN4e?x>*y`|%w>iwC_#6@ibWS7e%Hm-DN-w{XHP(F9{-{ZQ0_t$ zHO3M24h-Q;k8jE|k;(%y(>tHpi)@qJuZ za%q2w>fCwe&l_&M=4!f2A^-NF_pofRk1syBgD7q?d*nGLod(WpuA;lAk7u7dA}-r< zvDtjd7J?uoOBG=lv2OKx)~;KP0DK3eYa6Qi_$cDkQN+L!3ad8~Hs_c-u$$h&B@C=y z$N0&k)TYKUSb!*QHo5iBKgh0whk5Y!+u8Q^H}j4gZ|1lE{Bz9A&GD|M9;ehh#LVO* zcV4=Vu|~#`@fo}@Lc1OK5&m(J0VX_qP5rqOlwMMPoB6LG4#gGT?`XOKa@>k5;e)dLM z^(G3BMzcjLj+s1inB#}{QLYr}?i&_`QbZ}V*&%TpQ!JIpv|@HSWDJqAy`uxd};NBMr*Q#DULCAB5y#LpU`YzY0(+r;~<16!@N1b7UF5DZDB1f)h13eD{#&EICc*+ zd692X?geCD2(j1{EKCQqwgO(6r}Qdq?Lf6Lc=E;2E=&D!P})ucq$3uraY=JqO_{s< zIQe5RM*Jj2bFr~e%1#eN{utvl!*?wOD$5Ke7bx4N$5Mc_HjAik-Ugs`g4PPpwZ(p> z6;gV%S}i(DC0x(L5%yZd!V@bT7Lo#mu-71rwMNufKY#TT$WTPaioqUkzTrv&FEP`z z^Wx6$-A9@x2n@bwxtYB^UAV5KTrOb@wA*cFXXoteDm}E(q-lnOMRJ7nNE3}8_&Gfb z!Z4yyual)IJw092>P>JQip7X_t4*sNbi z_wVP9Z+)HjzyAaDbVR)3#_O1vkGW>kMcnn75A%V4yqzySxR+mj&310yvX;NQ?Yo>h zu#4|c>}J=0bW`c+<(jLm4=G(+@H>J;D>9`}NrD&HkI7(vFReHsO;TJb7$2YImS6l0iaq@dZM~KT zk~BvK<1Ay%P#**3fORA5_{N=gaq!p?-uus=;8TD9Mdr_)5eN0zaqr;BEFj#piO756-~hrrRi`PDb@#e06lwsosGH#N&!uHDKbyPoIK zXZG;nUwap;275U^KF+2kz5LUk{uQ(HRXQpav{Bst-S5!=PC>E0)luU3fqi`N{lCpC zZ@Ph7|M~N{fzO9N@CU?cf>M^2&`~LoCf5E_YwL{EQ7JJuU$qD)AYGR*3=l#>qlr=( zGEWgs)66!Z!Zz)#R*S8hH}Ix6yqY+U`OqJJgeVGm<7;2X_=QnE@!|KeecP2JX^XDT zZjPKh#VddLgBa;Cv~m@Dp87F5jBp)?3zJj0#Q{p4U7R>ON|eRupupIHy_|btpA}DP zg?1#a<4|075wg^aYZMwoHgO&mw+Vufsd`gY9TyUNV;6f%gY^bCXNQtS#$JJn)* zVu~<~gyTo%?1fP@g050TmkXo9V{CSwTD^&DG#l5h;#JpP!G~_Wo#RzaM@NCIS*1hO z3DJ1cLj!3haEw8w3GIrH=@`H_HB6i!rH5}c?W)3r1uhyH;LM(97+SxP<->yvM{vg- z-{P5PcJjH8|1r(_91lPG2&d1FVzlA4uX{ZgEx(rU+;ta^J^nZ&BTKpZlC?~?G^1zF zvb{Uv;bRF+N1?M685S5leVUJd@*l;wzyAQI&d)I0)_mu#he&?)13dWHliYaot8t{H zon$zXfno)BG;{Gc?S|n)RGKdW6R01-gbt(17o{B&`N}kDujTuezS= zR}Zsv*$5}58$=!53`G&Y^|Lo~&l5YCo}K0D?OQorO*r$TT^IzlxmkKvuA@CSO*@P6 zq7rqjEMGnc-?eaXJkJWMl}5;gQFyNXu(dh9A5v=0k<5&9pwiDRU%cD8Vz>cB5l-MD z^4kd(?6a*kB>%bYcbpeT*BGSdBRxAMH0gqlY~i#v`5C7$l`hoU%ksl6f2`!^j^p5Z z0j)H_ZD>k8gH-Evf^xUj88{9yQ@AQ26N2ja1$5)Qb^gmT%7u{r-X3}@9Z)RLR!TUo zptrA^RHdM?<{`$q2E|EAIx~Y74s&UZLJ;B@XrwV6K6oM!gIH0@^1Tz17K&K!L~1W^$kXDFT8>4jr6 z8ia6|ot;N#8P#UXx+@9j@9JfIdJ<_g1q8!=9kkjhGg*Q{Q0(m@iyJ((?XUrv39nK7j0-4ELml4 z`T^Em(7rzeDl<5qHAZMB@k=7$|Bdxh1MpK;F$!!qDlAZtQ~50lVytL%foE@B%Pf_} z6LJwj&oawTjsi)V8Pd!Oe-G$SfRq-h-|{o!v!DD7mu}l;)~y~AH@@s@UVh`NxcAxBe&L@7jlZ%2S{Kt1>k}0Rc7rycD zeC#)F;SJYc&ew0fmFWxT_|hjo%DMSEfATlC^775gSl(AA*pu={fB89j$`N1v=TB2> zHTe7&zsZHMF&w3M^3FTh`0^XM3C# zFgOy4oeEvp{S>7zq7VgmmYckx|&DVeUFzVQ_WJ+H-g`&cb(MGjpS@4Lb^46jsLQsRWx2_{ zfsHA42pF&lU=mXTKYB?hZ-9h!0we(^0RjOGalnvZ1Gd3-Y=o<9%U18wjAlmD=ia&f zw7uUy_PHbRuElR9|9h{cHMXvF@3~j^?EO67=UZ5_W<77d_4WE=pZ+Y@U2&m!>l@zy z!06CX{^=`UBMePgQWQpXb`(gIW+pKfzoqj0La3b(rr>DS8$c??PsO&jZMJfm-lTD4 zKEs<|^)f#7@jnLO+u!?FJvKTj-tqfyCkkg7pPa_?B~ctvsmwA{E}@iSz?a$=s3zw%Pn_2ls#i%cd<0;nXxa~&)+N*G~%5Jko+ zHlOELJ6v?hCQQ>Ag zc<{;RdD;0JdG%G7aMKrmNN;x+8&)nw>V%Ce7O{5OVz!;LmKUBqL8D&d`W0P#^^V)A z2N7`!jA)fCP!fd@#EBw_V`IN6EaP6KG#|h7du%%QV)O+YdEl`p`Ku4!!M1Z&@Xdd} zhl%kC)~#DZ*3Gi*!t)p#AEnuBvUc@ZNGs3tyPjjLROiM0N4WOV3wh$19fV=bpS}C_ zoT?{O=BDv{pR?AVLs#A-ZUs!t*Ksyp%KAbF-Hj=ZkB)HOw#&KsrdM&Q6_QN?e8(o~ z>cQ#k#t&-D?R%d7?r!>5uVZM>3pC0ztlM@qx@Re^dX+eeaH4>(ZQskoyAE^9wcEJw zq33vZXqs?fIkG&(<=Za65{mAO&3WtBGN@dBH8g{YBIZkT6tX@#$kC|Hn?hNq{CuGh zZ8~bA3_V8*beyK`N{LR#<-&2mvX~z_f*#t7y68r%CCf=#0k-cN=bqU3>o1^CTA!}_ z+Xz+4zZDpb7Scj`9&W3F92+9;>O)&Dh;-u9ZW4q*Cj$JenX2nE9+MK{*l5ABISPG? zX-$rj^E_-M{fh>fY$f=%O{graL}TT0RA(koK?zF=nyn^RD$Pw92*-Z zQ^?@iHkM8xiFKu36%&&svcAu3X^tRlVS6r?Ws$@oU}0-b80|NtWC3$kjZ*TsS%k@N~Kw5W~OyV zN2l=oEPIb0XW2kMiB|ZwOPGX&tuh(uky9RJWf5TP!P~hErj|M5$OjT3PgAQF3Lxx7!pT(QXb>hacay z(*oNR%eHM9=NxU^avaKoZ+!cQ{P@0ybfaY^53Oc{C5s1Gyr>`FcbPBG(`*Jb%Qd9sVA&25 zZIXZ;$Dq(bi$=X^T!gfy6-%NZr01N~#EGU{u9C}TnK(5;9EM~v9!e$TvspTd1?DP^ z6pa-qZKdC%n8U}8bLhx1y?Vn&@!ZaRV*kEF#M;$AdEnO^J#t)p;C=7VYu2764xF0j zmrv~AjW=G)*0Wb(3B}mV3_{vu3LRW<{#Ja?qko`)Wi7^536s;atUc>20wLHpe2Tgj z^e^hC)@pForZs&1fhRcs+>NYVzLf7gb(l9^c@b~C@oFC0@fEb~@&DcNRyMC&#h!&;5_^q1$gE3PZ++Pm=U?@$ze~WWHJB&hOsKj-9)h3MJOSAVWhZnHrx!R;Stf z=tBh6c?!imNutQ-G9*gjc`k8m8nr&;UgdXIDXG!%6>PxYmo_~QwdQNF(4y$9XyQIidwbCv%7Y4!^NBF?dzw| z-NUvEwlZ5PF*7+%r4o`^)K4pH(X(tN^=6A^qlwo$z(0KdM=V*qi2nXw2A3~qac?)m zwR!Q_Fn{^J+j(Tii_A<yZ?yz>0?hbcJhRFElaOkw@yq> zOmhD(K20W95VNzhTzc_E438dTa&nr{p<#1B0@NBj4bYv-@UI`ao$EgHHC{Y2!Y!BI zjBN@2_Ivl?CIPR#e6uc%j)@Z|jx$%TaP5^B;n)sCqZ9h*sd@3r*S?-(}1&+q5X2cAOP9&XYkFBL`KGkaOOZ>l&Z z44WiK=H@EA<<-}*YEdsy(BztnxAK#Re$6i*-Og*S{0O;XCoL_x=O_2^)?037@1AF= z)*H;tjAQF2z5Rn69~z=#(Mk?HvxC{W63;*TEJt>|Kxy{XG)Ip!y8i&>nd|uKXFpDP zzQjzq!c3*kw}1K=k391tpZokrxnj#%9650kjpXExUG!8>F*SM&X`8*ZQme9P$r6^W zT+PXY`>0h*EI;pJCMU)z@86F#xR%&*5IP|)^zeMW#q&RU0^$2ueinqrj$HoupTEy1 zZo7%sU4J#(_Z;RcKYN&orbf+9(%s#O9X7FoI(8J%tj?o~{R^5k9mSBOXuC+E{&r~A zLimYSXdkwiMx!-1gFbcA zG!FyI%DsQVA-hmIMm2!Zu=hH-i#2;-E!KOM*mUDRa<^C_=Ov zMtdX-^(2?^3Ci;*M}FGyy3MKRr>{l5|>OCKgf5 z0-C6_#<3->R%}GVLJ)+paru!l)gZ*!mc&hic2qhFG1Q}lAU`Zi&>aj=;5SvaUxM1b7x`j1RL!5mn|uD{R}wcO-71i$-D&7cc#A6#~n#u`t|Nuo#`K z((^1T^ zZrvJ^I9wP*qZRplmZ6bxq-}F@c$B`LPC7e^_`ZvmFET$nN2OXbO<7yKY)R(k>jbS9 z5B~CTp5M7&BuaB)_!LT5OjI8h)n-5|jM3lviHM_s-X(*4`dz=rQ+tna_`m`D*S~^l zE2MwvGWP7*#V0@em&{kH6gxWzB25d62#fFBeJ@YVYQjb9z|T^x)>yxCIs2a4jdEOe z9X?6M^9h=D&Rx5b6Qg5nTD6pswadt5eTJtdDdh85g)VlVs_}(y-^kTDZLKcW>tV_dm*#B?I*K^dK!sKI-9$vzD@F_io0grbvBG;8AU&s?hF>k;5dVcZWkMZt5{UV9wvvJF2UU&1WIB@tFx88gMPwzX% z3x|eq90yQTCa1_bE>pFTshQ(!nlE$vYj2>tr<;|F`x)%(;lUmI*|KIivoq6NzU3UE zDB^9my^*K)pJ2XRCb2xe`n~(9luH6>A;SNrsWg>R1!`rmZASk3pZLt5{T;1l1J8Ac zVui5X)V)X0XtWU0!gXCd&&6>ZBes+p*Ku%MmwKZ?Hshn>*l1Exk-g`+%vWkywh5rh z=5zf0SH8*Lf8`tGyLxFToAOKvc8@?din_;9m0Ql{6_=bx^qx2I>+Mg_ zm$f;1^bpGO_{!b)@$$S#iG1NxfRp2GxTozZB31~1) zKx`T)R2wxMOGiuBE#=84_hqlY`DWh!u8%M`{(?Gu@PIsV ze3U{VD;?J+XjTb>kVZ4M;zW}uf#+IUt59WfMJs3px>lfs?ICtOmLzXTb5dGc0o|x!mc6OFH3>^aoTDnlo>Y14t zfd-RtQLY#jc~A?Ae_?5;?P*drr?O73%4m}8e0f5 zI(kV1@V{6uH2}Y5C5hG|^|4M;G`+n{NSEQKwGsS!%lPlxwlEqaX>9d^@HExNApb0+ z20KzNAPK;NU>4fog)lcW>0WyVB~pQ*5~WQ?l5#WKD)}}_ueGrVw1sibu`QA64K%S5 zZI?A8loF@uKW$o)pXLQbvAIrL8doCF*j9V`pi$cRB_~m6g1Cg4cvxtB-=o;u$Lz!@ z3K^f0N?5dF72~HSQAtd_+2Vo=&f}fG|7IpfhuN@cGkcGZ@#kOt4%uv$Kq+#*Nn(yQ zxY9U`M2V)MZEk=6r^yuxboVc&Hakrm1*kYCm&!Rrb_b^vc4{QwkS0sO0@>7mkdzIXGvNO2AB6yiz1RjH*fps zr}*c;|3^OXflpFcyoBEVURps5OG^A~9@qB?q6BR@Tyn+b44)j~#PCTnzDE=%*b++R zd9>DM!v{Rq_|t<}D0n+MJBV5_g?tW`BqU1FY_@3BYi6PXBvF8ENeaaxt5*&3%!wC~ zT7$N5G7fRA$%PkerL&OdvB#gHtE0eKgG>0vPakE`>UDhL?XTz8zuwM{o%`5u?zw#U zvP-!A6Mv1iERsYaJfC{4#^XDl#Sd!y`8U3Ra9l=4PceM-5E~YCa$vT>zuxx%zR{@B)=qoIEi^`S?NVcihGeS8k(k zV2FIiORYVYv2CZsV6B2=p;?^Z5M^@1G7E0X#YsB(+dOS&|WIj zrSe!U|lwB|E z7p{Y71~IN@5_H2T0U<>kC&F_a62KP9&iR6T#vzlt$P!uP4u0j7?`}8EtGz6rRjMPR;i8GoFL6jKLVLodSMbJv$w`BYR!%p@b5@yTa>T3vaTEL+Ct*aVJaammG7ShHd&mHBzS^w!si6Qfhy zv*Qqtlzv3La|QOsMU0+2$s4Y^kijLlG1%cVGJJwdF1m=O7X0u>Kc?uy@7;PElZ}Y& zFCL(!Ee490ap}41`SREA;>|bTz~_Je7KSIL`0C&M4HtCf_|=YG3}kK5Q7qEi+sik8 z^b4}LzX7C0hbP&*tf1E|?c>z+oxAwJ z@4rFUrpJY-mpJnD6FjqSfLmX28PDh!`TU>#1%LB}zd}R-!u5#~O&EqOUcMUPSS-%D z937wIV}JBXvXSz&1+snx2S*!?sw?mfU$I}h@@-?@piF1d>E(Z{Kj<|vOG zBML)WL5sLnux5-M(FP9Ac`V1A{9kjgkgY`Hd-4B zp-O}JvY8CEdfjkirO~J$1jRzm(1cXNe5FR5MA#a_#Mt&Vs|}*LAwKxWALq&|FX6eT zpVrRMq*%FpDfb*Sh#Iszmel1E`{Bqw27p~aKzy0zt#67mRIn_KlvylBgdJZ8s~xw zuHqeU{vBR^^BWi%JBpj@A&e7t9UtYfy+?WY_zVLXi^uk#;Kd_DIN2P>kDp*gheNK| zNz!T(MJ+71i09ZOD&mpt&v5KD z;GrliTE-kQO~mC4ovmJQ;X#}IU$@crG-O7HXV@~HA>b8KB2%%a6cXXus3?8@BnF)r z>&JFVZ@a8ZDLcZF==4lHeK5SM@tIG5n(5hDqA;ST zr@+b;OPHOjGd3~JsmUp9%OMKtj0_#;>1TJ+YK3H6hgeDSg&bbar(UTeEkWMRA~ZPC z!S-|5tp<*5qqLSFR7Y12kKBJRm0BQ{Eg2BDouRwCM|2glBr3s{wxQri(*%WKD73KX z=qP}S3B#C7HcO+?L?r=QCv z*cQ_E5JDrQ(ormh)(Y1_C$SQ?P}J)ImK4+)RRr@?>yXRl$mH^3NsgI0By3iVpq=9sJY5kAaOAWwpSxReP=~M`+5~46k1u`0x zz;)8#EDRDSrNDKJIJFr>DJ{r&=Zkbo0Br=`!m-R3+e(qVI8kZQ-<}5O(~oP@aA<8D zgR~Yzsl8pC7{?iM3PT#DX_7<{DT(X()Mut>Rp((~36)BPr=NO? zBSXW4I2;r+)M~M1!&3hGb06oM-}w%^_8j7o?fZ?T zr&0@k>G^z)D2lKwiIv(?HX02O(xA~vh+{j<&dxDEU!k|RhsDd5;JPkHkDg$zWC~Ov zr7^ciU4z0fq!ok)K^Ep9)tJI7j3U5iZ1fbDUvxGfdf$iGzGJ_B;DJYlN@A?2!N~M` z82|tv07*naRJs*QXw?hiJ@0)F|MG7?;v0|dq0l#o4in<(Q@r_iZe-J{B|P-2$C+x_ zT(NB{V-u%%^7-A!Yz`-%;o0Y(r6cRIwOcSzt}!__#q2;QzkkcCDAfaGuE0GH{h0cR zL+t<6eZ2c~U*_Mwe-Dq}_k9YvEVq8@3&gI^Yp=ZwE1PF-W>zfSyqa^@uhEB(9@Skr zSFAhxT>j!qck+rGu4AS=k6-NM!mF<~hmr=TKEns!^cjA1_uc&B;m7Fi>>!)ELMH_);o57iwH%RmS zjpCR%j>%^;v_i{>@Rg=jZ?J5jlN)Y*6^na|eDQC-py$d}@tRk>jO8l_xqST~7hm{C zG{T6!o-Rt2D)0F0msoYdMSS-^??<;9yyg|x@q6$72tlpNJKp+6&VP14+jqRkXK%fp z*I%=Z&W<9V{Q3_mPtS0{*&BKFHQQ)ZYkcoV_mNq?j=AwsZhP}htY5x}9S4W#%XqBr zEAZsgPwFjOwura9`JIf69Oj{i?xVB2SC5R0ix0m4V`v@og)jUCm*#s}yr`FDgMDo1 z^EfegiY?0rC{-Jrs<*Hb&2mo@Iv%GQ0m5|+4_zfVjzcD&r!hChnyldJOSkf-x4w;| z$Bt90)>*T1kXOI*8aAvMWbe}_s4pqfT`cg#zT^De&v($XYAyRFCwT6Q-{N;)btPAC zTt(l?wOF|hECgPzi`m(6G8vCdwu30DQ7Gh5VZieB8+mZ&0d9NkjlAjiZsVb+cXG!o zujI0eFXRUgJi=_H&XOfd*?Re9EFS3N&98YmyGt=MvvZugZZ#KQx{Vj7>MUC}$g065 zthjWX$nwlNpcIi7j5V9I;t0!j@KIQvi_n@{Gce+C1X!sk*Em%ekM(qtx?ngVErYmf zfzXOZDXBh1#_OWsrXzo7Y^RaioR1Qi_g@ zM^~}Hc%^~m*d!`B-2e!g9!@Fxe4)Q8ws=W;4QdGDycJi4%gzG9LqG((igMN+nck20TD31Tn&j zkkU0xf)ZF67Ym7wVr-=aw$a3eO(o30CdRjw62g~`ok55I--cQ(VXj;zPC&JqAT6Pj z5NYR#wdTagDbC+~HbEQ{Br*G+f0i3xehnAB>~c)W=>t-PVVNWjg|J+F&t-aMj>q>8 zu`g~=B4b4RCgvQZDOF=-LRi}rG@Td|kwlyCfwo?10RA`Yr3T=)EK4AjO41_PAo3dH zx+^>2EO_)U+3XRwsYgFU%|oS zql^xZqy>7!;X&A(NQFhBO?M!Z3f~vq^qlwMT`55C{@D5sc{g3j*bFS z2wJTG$Fb?}>%w&$q_o&@&Kl+`HAY9rjgTsijGK*C zCd*&{<>we2=x1_boQ-F%#dU0BjoR5ouB(sH=@L^R>@O*r_dkhLk(isE(@Xn1SiFCN zox2Z<`tyfavu-_367c-v+sSoyqoRn`%mmN=^habphn}8pgC=`EGL8v?0Nb``=T}5w zNJmGJW}`t6M#PDsh*_3nXcUf}Cf^2FwoMY6pJA&-xjfISZ@LxHy$sd20>`y!H>I&l#k@e-X7-#CtyQQO@7ER{z1-1hpL*#6vZ z{9FzpB|eJxzUFGa^OIk2!=>lqT8eec2Dqp{!{rxkWO-gt9y_F$4-SggUUxnxPmXfs z8?Pdl%u}t^$$2&zVk`lTdX1UsIgT9L&G_g^4j&$(SR5Dg(aNgM%v|3Fzo3pim$jhUNo)^6=x_xNQsndEd|2 za?Tq5>4y*SulGMrZq-`KyC#XEm>2%yTde9Sa;OfIb4_0PXWw8}d(38g`P6++QS?1d zH4;Qd659@85TjDdOKCgw`W8`Xnz+$GW^;5EJ85W(rcUWUq++cz1F|q^xR=RbB?e3h zl|o|vSR6;jH(wipsFdwuTAXIrq@rBu+6xng_J(bodfKA`O!1wb4N?edK}1+>V5x}Y zz%CL$4+Dc~ygdlp1;<5)0YazZ-!lcr$r&^x&Itc%kLue6{{m>$=Kq_&Z)=6Lp<1m{ zE?1~jn?{2s9TXl~wCLy@pu2l9vvZS_%kv~E5x4yAtN7`?_p|Td34&PT*iK4Y5?C@r zq$8@WGPb3d96QCz{%(9LAy(RIG(zcnCUrOoO-6~5pkhU}UT5vvL2{j4#5j1Khow!} zrG-Y?lG=QopwYlW;M$&{^h$~AdB!!!5e7U8qEw(Kk&cDZib}OglqBSGS#-p9i&mw9CoJ%db6cWga#@Q)!I6`vMsZ|<(g|7D1#Rg2%NGwYJy&9`8c=PRvk{dM zv-1^#dJ8Qe*O8-IuJXB0eVQv@b`6V{E+ykhEv3+lmaUWdLJ_4BEXzh%4p~oG`P zG7q#1<2cdC)ao-%G(ntTr>Op!t39<9sR)WxHf2eXP8!U0srGy=U50O*j&9o*b;fhI z|0_upN+l#oj8=)co;XI>E?y>&s8o?Ep%sP{vIT_WkVGL$Dc<@AZ>QA?*|gzoKKQP@}3Bw~3a5*#fzB3tglaZ$JP#7vpmI?}tu)8=*IuSqFY6U!BZuiN6u9iX4SLnt z8^z&~DJD-IBj>v;S=7n<|KJwR-+4q&mzqKX7i>J6Fx$y=yh)guqH>&0EJ-LI=RV&y@fY;TFMsUZ6K1VDam@9Msg%?wquizvx#}6Lnfkz(Z_^~6pqoapF zTU5&P;_%_ac%Ez0r5#7i&QDXX)tH%{CRRGN@wAXa8vTf6kbTFtkW%6}4vy;}rJ!1? zr^W&amTe(Zg8$&2V8?T^RtFUv|9{hMIKoqXY*hw=R!cmC%u`S5Kw(Uo!7Fu07B z{oNcpc@omurd24gW1`M8PyT?U(PYgz8*z$Vv}T6LW_>fEj3ctXL#x%K8YBqYCzs1| z&z_T5C(1}agH#$lxRS(i2$~`1Z#tPH3$N!VnQO5n7{^f<_JeyzzVw8d#@}5O(yT{d`))>(j-(!i=@s1%A6hY5zIV z7A&Wao#`ed%(-o;gksjER;{yY#d2!(3L1y$nK4cd9l;`?*wM%A>=e_}(^M-}1{N=& zr?)ADx|9#z!Fv67AR`K@0kNd#F|` z%*{==dm?&!yU1sX_?~(HDvn8N0oqB3BZcGoI0@9^n2xS)wAO@;fLgPOsMiSM5GieN zjlRusELycD^?JZurHW+_?AF99zoooQmd19ed0us z&t;jOE>S5rxct%q^2H7u$3t2WL@l&-uszpMA%zXGFtwF!OhR<3k3wi<8Zy_`9?Fz` zU|ABaVse)Mk`3tpV!hM={FY@o8N$Q_Pqjt0ZI65dGHAkBVQX<3;g=?8CQiVyO*0V1 z=72Z8`*OiLEKW@K9z-z;qbIP>+@RY_fYL^1VB4vGKB*&6NfGKvA);K~Mh>n?y+4v5`U{ zr4i!=QA`e_F>oylB_vU!Ng5`A>)L$p?jN)M>~%b`Bci+5K`!H)H=mv-wj~itkX|%;) zwj~H#E&M{3&dwqxSy?eLIZLfp!*y4h1ZB^NLN{$*&yvLhjGdYUA()(+rc$Zmx_0V` zp^>&rwc2F5)ncZ!L+m*;!tCrEyZ0Q%$>w=-*D;h*^z?MoyXIG7swF9O_Yfc7L(kf+ zG;E0wl3cL^4Mv3QcsQPq%G#oT^;snOUdD!wvV6q~Itm4*rlxfgw{$L>6Zbsw1Q&1J z#MZ5nKfLn?-2S)U=8jih&Qz(&*ptukikDqUxfyWVb=w$N)WOTQoo9m392?j55ROB$ z(crA5ee@NwG^J3?P0^_&CH)X%AupjDVNIFwkcG7&mj~7 z&vQ*+To|FW#?P4GG|RH^TsQsR#wevwi8c+8PBk-WIGE!a0eF-oJo>ArXf#ZwM5Eax z4kL1%1$z4X2%?C0z3o=EY+6ruA;-krJoh}fokq3FyWjc-&K~Ti(QJ~<Y^ko9$2TU|xIl7c+e5?YEKfjlJnPn>KRi zUH^$=DRi!bzxvkCDV65Le5HcaiXcu1s#Q=L>DWws`5S!U@9tz~wnPwyW|Ah2Z@$3T zqh_)h{ETlJD5bD1%QV%g&{AW>)JiLoL}9zeEy(i)wqw(31_%LuHpkb$^?kl`*MHz= z^UOz*ax>x=kM9A`$Gz_f^VwTAw(W?F=hMA(Ik`+o7$-!H8gF{VRh(?Vtv6iG?xQF9 z<>Sxu_M5L`_x=Nf;Ti^(EM(=nZqr16i%XxI=1+{90 zAc}d}E3W0h@Ho#6PjU5@b2xr-g!9i{#XWmQ@hycTCH3LM*ippl&FA4cHanhtnrk;K z)*CmSBXWhJ?&$2~*=L>=?|tWc7#^R}^I;+qH;2-e5l~~ODx$L&gpJ?X$^E~0n6KS= zCm;RbAA&G@z9Vd0&!rVK@H2VFhDSv?@~~9IO&6@AS1qSftMRTky`GFhRwUR#26h=oP5I^gsO~X(66c*o18x6NfmZ0wu~=bJ{Ly@ft)MR1zTk3~Fi^ z>xD;==Uzp!WGy<1j0;iwdPtu?iBBV2?c%;&{GZu`ocaERG?tN;P1g7MkMDd1R1?c~ z$z<{fp-AEumAPpWENl_eY$ZgI=IH)?G%78wx?n8{7Nyxq5jE%7e{?^!C}gm|$kuJ= zGcr0t&WCKqK{_5X>>)lj-p7knl(K-e7yFs3aCDZedH!(*B$t zShkGbQ+?t;?|l?hqAkZ2N@<7_9Vdy9j!hg!CWOKF(cY4ItgIBmI^Lh~ve z!=7GZ0nHDhWZ_!c)_77JMfo+AijXvGG#Y14ArKuCKMER;ZLg+yZ8?Z(FF5z>1O zr8RLBk;^zJB^LJ7GtC&HC>0iq)cQ1uu^l_52E|y8V~~ha1R82#LL9e<<8hKCL0C4P z>#}|K0d^lB$4%d#n=9bDo^f{o8m)ltjv^V~XJUE^&z1qI zID}C|7_|N`d+!-$=T+W&|JGVh+imvrq8W|4Y!zF!2Z?EbX1-Vf{9BXbU1*PG9; z*QdEgTeI8qtaac2`(N0)bt8Sf-K1Kxvb;*7HM6q|=+wF%b*46Pl9JEm@O_UXhfiRD zjT_gqe*Fmfe2(dJ^Q5Vvr?-b%twFt3BS{jvy9zkM1~Mt-pwk5F|0HO&Lc&xqeex{F zpFRLc@VdwaE>~TBEj^_Yj~#f1zx$)VCU@zjTzCBq?0IJgyw| zt#V{~fnHxRzHX4N-aeZ8EJO`-qd|Wl*mdC+Cg+yvDi-~?mf9&@z5VnK ztwRe%;3`}+^?H?yuDF6b?)ed~y5_g}(~o?B_y3Q-V$0|dg9H7%>g8v7Wv1o)m3tZ5^sO)D>=Q|;?dh4%0L=p_aVj|lF^uCO3#H6lKtP%zRDvj!F+&?bNz1XvI!$S#IWsXqyShRtOmTAsMmKL~`t(Vn zi6a!ox6)A7HdZ+b<+wJDRXOPOTdc*t6ChG;9aroDc%DPwLDEh3vs4JzC9bZpa_|Y{ zzyNIBWrewM)Ipo*cx4OEM=qX4EX^RxgXpgQ=b-b-+LY=}W00Vdh_pON`-)c~{9L9v zP?igBuz%lL>9H1Pzvf7!&vX9aC+dHjRxC3*iAT|Mc;d0g*)z0W`mW5S;AQ3 zI6kg#t$3S_I&q|Fhbcm)6iYr)nBaIm{ax$voP?8SmU;T{6k|hs=2LW*un|z_PD3m=}(NbEYgy+})=k&=KReXPtYA+%g*llG zU{-W@z>f~SNN4#28F+48BZSDZP|O;Cu7jaSX|m=-tXY3rYfwo$45>Gp6!U#Jj$UK_ z2mxWNv**q75i(z8=~#QQB(W0@iNI3=2^4%6CxxaEv{UXln8DXhKDG58*ltF%~pe7e%G(?pSORX zzU>$D%u@&1<`~Qj)|mo*!Ve#&unc zu@kj+7@;yGG1V!7?~=wL)oPtWF^}uIwA+wI5n-#1P%h=J0w4M4hpDL&xBT!?l<%P( zpJUG+X6nIvdD)-+K386`mm?ErXe=+WGCRe_{sJp1K?%+AL(ftgTt~az<^`8u%J+YK z03!sF^9^h&1R_b;GB(1_t(%!VJB6w@dF@MIz;C?sjrdZaOhT*K!ts1IA-Ls^`_V>{ z#0e{>k7Lq=FcmmD$X^jU8H+AXwd6^8nINW!+A!U6488_!X+ z+964t;JOY*Yl6%j$)qWbdILZ3iQ@z%C53#RiHRwqcAIif53AK0lan(H4)t4tpVl<1 zi(LMKtNDw+`Z#B&&hm}#e4og`xzke|+V>#R3-E-YkoVbn?TctNn=H@F5QZ&ki!=Q0 zFTV~E*16@@A9C#IH0Nd)cyQlST(y0S*Ic^?trPYin_y(m#mGH-kgE#}=3NT;JVvJs z4-GLs*vGNSbNt5ZUd|O81_^v0sZ+GD1z=B4550weO1(+76;f-5#Hl8YBQ_59@W?aA zx%1wKm^?GZ-+bv-MhAKsD|y_0-y_r)=Xv^Egc^hvN2}&sb@^fF{@r6W~p$+I(8|iw_p^ONmvfzyaxJuv{&ARTQ z*|TH2Xsyif$i9csNG`kfdNDXOj1+>L?;(N$fBLP5p>-GA3UKo$Kgyqc?RJhVHj&)} zB%J5cBe0Ez>%!LEm?*^XoYdNm=(W2a(=%WXh7N^OLs0Hz`NUy@e35E(m1uc|cC(wY zjhi_)ae~^!5&W&Y@p3LAYLhnVBvPSsMM5bNLLsEWU>&ziHi5Ix18c$nVF4bI<+m8u z$86k28srciWM8QBXj8|GGO`-s}$=jjNBO?+M;41y$#Y+zV<0OL4_B(~EB zlTlY)Cu>y9d8eT4|E_&DTCY8SM<{IN0v2>ILfY&NgWdlX^!62L6>>BiEenV#hhko# zWRXfW#3T`z1cQTgU6Ldrmv`B+Wt7SJ7QNkNe9r+Bnot|FVSLayju1(jiZDuzQi7n= zO`+DnQ7OGWc^a-{WwlA6%O}YDtj=Hg4Q@-Mh-i%e34QjSTJ1kcYKt!G46Z@=vBb#)=<3MrKn$Eo?h z!$$?iAkrjGF|qbMk9HUfgiDfWp_DXANs}aqC`!cYa>cAvs`~QFcW}uiJNdz#_d2UB zFlmW)yUz0BGD8D>APt@`IW@J4<9qn|07nTt*QHtw*>lMi3=a*mytGWC*&>Q1u?kSi z!9kN4f$;)}BGN?L>4-@&8NE%~gjP(NlEm@z8i4=8dcFbp8B1#`R*NA!d@a&#usnO6 z@z4b4MJaIJe_seIzDZJzmkD3vG<^=Y@_ec=WO)LapjTv>0Uhpt=Ruw3LaDXLlWeck zb~2jDeVb&%>lKQb@YGi}d&P5=Ig0M~5v%XK;{KX20mU z4u=jNqQ9@linf&vM>~1)3}F-_RA$|1z;z``z|^@}c3rrck9_!7*?;g5`=5B4i4&(e zee4kDwysA+t94GasMad3{k>wML8XQb5tc^c6gjv|XNf>`{t2kI}6ca?gDa@f#ofO*~i83L|u?ky(MG z)0Dxk0^2ul)7omhzYFH8v?&P^~ryGj||#LU(tWD2zz8rX3{=^mg;E zcf5hcg(W`zM}I<+CR}vkHoE)zxNhe-W5aKuR$oOM*s=3szWn|B`R0$FWT;#w)`ky# z`1eQ+Y~C=8a&koHR&eSK4nK4cONa9uJ$c6b-p4*Be)pZPXKrEH(r1)JNQ+!|v`xp) z&T-%2GprwOkRKdF3yH~eBJ*<#96oWHzP=tD-)FVffF#KpBf-qVGN1X{x0qg7B*+)J z>5h9bCZ$j;5-7#j@85^(1$Z(=1s-FUTuY;}%-r##^pA~0_W%voW7|t#$)|6-kFVbI zI3?dB)`mI(VOKv(S|D5>yx=^2L~#;FAzmv(T)>~GzWQzQ;KDe!R{`K-M!=@7o#L00+~6tkVK$dj8xzS$RL*? z;^usz-$A>TS`%^!1g$v1Ew5wX(tgq;B`D<4La=!BAhXjm3~$;-eCjyv@w>EgehU%xvCMBXDy8QM0x7 zc>BGjSW|gevjy!uZ)#nCFb0#I$F3Ba=0+1WZKz-ncr;d5iBo9T1=U81<4Al@qK%Ky z37!(fLb0+MGJSRtA?>tH>y+IWU#_J37Q*i`tCa?+4r#~ee9nt8I%gfu6a`a6=QJzT zCaDIrqB~zACZ$=g6G-3cr-T3r&BZ1{LcLk%*rBJ4Qks#Gb!yM$S5d9jOto6&@h6V5 zT8s6Wsk6+@Es0vKo-Qsd$ocstl`9nVYIKKq$J<_Qlu}lA@qaHPl_QcwxIv+yq;!Q) zjsZ=aq{8!yc)l@VxGbd9S_)x|!AK!!g-x?u6~b{9j+87cFVku@k*-832%~t7J&~r? z`LL_In;>7NvOGtUO2Q;%C2Eu8%9Qc}QcB_|rWr&?9-0;*K~{w z^iNoXx@&2>I#afr42?O@yYH+H(a6}b-P-dSV+-dLn^N2nBBvQ0Qe(3OAj==he*Y6- zfU&s*8ruZ4LW{6CncZmML0;N1oSj@)D^jCDq$$N>ARN~xiDF2T%x_#7NjZIblJy%lFf+f5kkV3jv>~7Kag@V} zGZTavy~_x}#`U9|IWtAG)n;_v5c#eyK#;}}u9Ecic60RjDWXJMPIuNMcJ=ns*J|^k z7hG;!p~b{A2iZE-&&~@r^IO09KE{Uocx>NeG@1)MdEfxPUg+38i9V5B5X5K}k8s6xFQi}++D5Vc z@@puFm}~cJXWQ1TX76>sAf!~h=pBE=o8Rzq{^IXHCvLj+KiGWD^?drayNUfGLP#8) z+R#JKC5~fS$|Lsjh~tZvE3RA$#UcgYrK`Eb{E1^!S1Sx|-p0VlI?^aY=oC*$jO)|2 z^HPe^#Z?MLj1Z2U-Wbh#V}*dmfYO@fr3I#s9-?>CPSo%iCmy>G9Yu^?b`8CIUrfDG zqh=&V3WVdZ(h5;Rpk29!7z;;X(v;}nqnJh$vE`+tX~NPCemFZ@+HS- z>RjAADki2Y9GjeH&!$TewMlm6Q{0@-xy2>EaOVTeM2gj?9>Rnn>800WIw-hu?FO90 zASEWr=%kPpwAt);E%H4Z@phWPP!k0KI1;5np($;=fX0cZm_K)p(T$s#K68@B(Wh9y zaSQo;K($h3cHtal-=W9L)5@9+A+v%#BYha*Sbly6TA3`d8f@VuGWu4U)!bSt*61Rs zMrB47#!;BSvw?GA&7ME0UYmY(ig-!7<}jyXOG!%8gd|Q;QqZa_L)Zf0Ao~V!i#^00 zD^QcA6>E!TnJj+?$FWXGrjs&kto}f!gsm2>Rs>}$xQ}9u69o8$5~fi@Dn+TwBaTwq zk;Zd0o(t6$1irux4DDtEp%bf}(6Ko?aX6h_s5*cCsaxc$UU&(C7oZ#=qbPEv(HMLN zhPs%VnrC69M$VUn?F8c}PzgjDH}Hrv@oSXEOq`lVXo2r|%q-0!ayfaymcjIUcRj2Y z7FWfA1Bd15sr$w3!itHLR3NOrAs={7SGh<#5=lFLBwPPtr2%e-Jg{-NoLapD5lkXyoW2*tsosd&Qs0}U# zX@oV-kdFDOZ|eE=Q`hqiz|UAx3ej=NaitZY#A%xO@mm4!bCK^<>&*M#A;WcWv(#M! zAgq;VlBMXXEHb@=tUuQ()HV(x69`&+&N$V$j%^k?Q-#j5B4OM3b{dq9UcpWVvgROr ze22!fK(1)*yhoF2WT{!R>Ym@F&eE9(u8Idk}nqUJeM$utb2>=SQOl7 z1_pW&q+)!-n7Q(rE5)HB6C6D}!Pjp21}lrR?A*E41i8FeS++R|Mc-p}Wrb>`!Ve#K zh(G?&`^YsEk6C3&(J?K%olI^I&Xj7t58a?P-$@M z9d~o>&;UcDqnv!?alUrjcX`E2uVd@zAd4%jRBClLZWv=|WWby`yCkkL0xzG(ldh3Y z58Zj6mDP$kIx)q}T!nn8k7pl$g0A5)jFgP-+|9z-De7}G437-+qka2%;<0@e(T@_k z%jGN&!MZ|uu7i*Y*Y#}^83e>pgwdLONAR6pp}yxLe3wQmBnW((%@)g*I+aR|8*lw4 ztJ>q(N)ty4ddg+CUbu^;**TIVrqtcTGY9tb)WO4Mcwk7xsixTusWsaiJwCzV6KBx| zydbbPut|dFdq|z&2+hi|18{Ob!JDqf>*=ShTQr+(Uh@mDWdDIDiNc6ImtBqH2dqYz zrD|O)R~r~5kmY`EyZb(7rl(C$S3#8Xo;f=`E#`0jCQ>;}OiYT`y!sUew5YeLjIJBO zRiGS2Y7DK67S*{)wKia~WM6G{C0c8gqtH@i6p@r-K8Ndh*7sc)yui9DxsIY%t+Bi^ zPob;G#w}a8`Kz~xb8{8IFt%>coH~7zSglnV87#AL$6g-1|3}oF0zHAE_L8gE|HM;B z6Eo0VWXrY-MXpewzOcyb!iqUQxggrOxIvzJoU-7S!0WP`iYv$!3Yf4>a_mu3Az<63 z;1_ZH6jw_0!Z}u&b@YbK^z7b?o;=0U;4#gRHcgsDUxOe36w@khBuwL}B7EqpCPrnyf)+vlez`QiE_DOs)j6 zrctl6_vfzR&hc@+dh6|!O9kP1K0&Dq6SsNvz)`CS>gnOdeZ5?_Z5^+_;X0Ino9}*z z&;I+j37s5m~GXVZ&VNxC=hqH*d7OEa^KZ`i{8xk(zUOSD=ZM!0ycM}77jN@$F>l-D$)S14&+ z;gqq0OALsNB18sCiRYM1xY?m%(qxUdO?J%+VeAyw*fYp6F~&%=QP$Z-D(eJg8wkwL1J73QaoW47!@2w=rpq8w57ZT^k%n(3X(TyQEQ@G?i--1g#}537!IBB+WEn z_Z2U9)~)+bo;iBjgxZL_?;^AoaiXQ;In-KpW@Zzr%_c!1N7xDx#t_z5(Wys@q1kAn zgl&pitu|p4(=^~D3C(uQUH3l0H@+LWVY`JZ!E+VmuA;ISzM`+M%I-`8$-@j zgb3m=M7F9V)fG}VXZJ*7Sph}}9AWT^@`Z4fg4f0F8qcMmDX3YfAcKnX$M+P|ZX$t)<(b00e%|57Q7 zfMgq)HWs}m=?Hnx-@8f(k~QI$UB-~56n9vW=hK2a_Mc$Ad~KVPO$kzyxe=V7UI0kf zPBg4@kRVRZ2a{PO!1|RNl zvkFZvp93LTt=3prTt)~<97QazR0#r~IJL3uQaTvKTIg71rAm^-+mZ;Lt|SEmkS^_0xzFwp?@(MhNyDImPF{dF(k7`yQgFt3)nv`R=|aMXuDtnNz3u(yia+*oo7iwGhfBm-G3T8^6Ki znMwS7fz|kHjBne{P_f8`ms~<^c82P?v-A!0QyLuN3t#;@L0D&ebO@cMEH76uM&o*} zWh%8JgtAH1%|^?jZK*B(+s!sn6rvnO9NA#CT;8Wvt6M}ojtP8)aD9$fH15`I3~cE} z8O_4+XQ({>IQ>Jzbd}4rnsrW}Ti`SQa*O!vzuW?jk5ee~)o=WO+rIZB+U>UJALu7R z5hW=bwryphvO*Ju%J)*6J&K#eG@4CT>kTFfIZjW_F!6_f$LSMCF~X&9_y@#po_&u! zA%6A!?16mlr{Ccbt14>*4EB+nc= zif{r90?)U>XZUuzXTI`H+}=TUY~RWYcceH*AY9u}JDyLFFVaj>(((Wz zjx5(*IV93WW6;$KtSnF&SVya?j5o4@?!F=1G{RQ`9NRz&qtUo1&qYZ=m}H=b5>_yp zxkAc}C$3xvH>hJo_-p70EOZn? z*tRLj##q{sv=ezLB`PT3yU?sRaRVPemm`WIbP^$yhe<=?SmU~qs2$R1rJxg{*y{Dr z5vo`)(usucJ2dKbF+Y1IEd&nIXf-}Q#FkB)X{^rJ9ta_Y5HzZ*2$PbAsrBp69HFcm zT8c7Oo1`%`!#08Apb&&%8`pL597BJ>!R;Mj{XiMd4=9(4qPr`g-EQJI9))rdg{D=V zV|a8uANar<_4xW>wrv@b?Pl};82e{chyZPj(MCzvQAP-3loa@ZW15YY^gVPGHbmb* zula>Hyxj?MuAZ5!>EYq=aA<5ac>Ku;>3b3(9h6c$wC^Ng7*fb78lgRpOF6;Hs-4bv z_YW{}W)g|u!tK4}T!rUa7p-XBX2jqqiPjkt!fGLnF*pJc%IX7*#&HBBkf!>lSSdcg ze%5-v0r(k93L%6s_>LV5dP0!*+>F<6GAABeP&-NzCn=#$kwOq@y#|d)A#gHk4@w|W zS>bO*z#aNchsu*C29x<5cR2cqKHpSy=sTUIjroa&KnQ{7iZx1P2jx#Qk+PDOn{M?5 z>Du4Z8L9(Wcm5nrgUR;dG@~XdDc0yf_N>T6#%W5vSR|LTqEDq1($7_h;r6kMC71ocB@#K@w5aa^ZjSMn0*hi(Zijj(_9U@(y zI5t_Zh+yM}Q2@?NPJ^&cHd-5^44vJ1;Z|ym7OrFC*_W4B*}Q3tTCGN`?ct^zh41+! zNlYtDm^(4W!N(5@yd0`fpu4Nc-rbk6wA$c-hxhZt`yL|S-9vf9P6o!tIeTW3G>%!G znc?Z2;l!zHnVMZ3nL2%1B1J-B0T&!GpA0{Y)8ER?QdY9+{MNXW6UnD@b$YNA#T^X?$TZC zy<|7dc1Yj|0^etN^A;B7=2)&&$?v*~wi{r^w$l~~JJ$8_sb7B!|NTq1G22vJwr!k$ z`kfDR<2UZ$-@bek>-X&C_dfDr-t(5%^N+WFi_x^Tz3%`3AOJ~3K~!xQK)X$MUk|I5 z3ZuTuYi@WEQDc?#WP6TDQ>0Y1S}g{5?`5Ihgr+ex>ul;Lw8r1q_)go zf9T!Z{lv4}x&J7It|Hx~g58^{6{0xet#5cOFTdfXj1Bek(7q>m`s^Hy*l^utJ9y`- zu19zt8%Kxv;nOG4%{orLKzAWe(r%KRoz)5{louHJUocA$GP?I?l6k!^YCMgM^jK;|o=}eBoEDS2uhB!`aL1;o&CQop6 zDdw_^w$f;~Z5~Au5k-*+Tu(?T`S(YTu;}{8avxDUgd{-*UdClt%<6#G{NCL~y@xzB$t~SYc^{~3QNYq&6;GtvO@QPP)%?&T($nldDbQ{mK zdG|~A@|}mCVE4Kr|N5b~^5Q@IEGiB8A8&ja_dIo+uA;*)U41d-Vu2?o=eh6X0wVA` zyZhSyEYcXYx=P@=$U=z*j@{qEPK%^KD~GC3tlPYu*~3p0pF79c#?4fgRxqh1Y&3}) zRdkx32aB}EV0r&ibqYe(3@0=;lqpWMwUU$uDQqB9XS8goe9>AEm_S-Iy`x>|G_J;K zJPcTe9+_R!sUQqv>-3^yFbP@<90jRxaa~2y(ik*B5YRT}IqpT-os#7R2*<$`%0!#? zAkz3e#Y;#$*TqQ5!om`LeH&JZDo99hq@-Ms zEL82as+5a#Je;<*fL?B`T03snVR*0~-*IWD2|A6qZuknuMn??M0%6!RXC|gaVvH#F z<;b-SVU$o=Ss+XjDl2u)O)qfqo-O7DSML;Y*vjr1!}&SCMb;h1AxVv>$K_&Ixh#vt zoY7i{IBW?=VdBV$Fp7Bf>t30Tt{>KSediAG%u~;(3wK50<-hnE^P(58=tIvQXWwJb zie{^Y>$wz5-6HTDbYd9-+9ZsO4X|nJW-h*W?Ex>>;9sZLo*B!NE+29VlW_)9&PQSV@aSBazZn> zVJmYJM>%=oC>yu$VCM7$jcOG?Zqk?csf8}<#QKFA~cp5XR7 ze!!M3n^|c@EEWctJA0OT9J67|W-b^X;dkEmPM&(^AiH<$;Dwi7$j`s%YWD29kip(= zzW0NB*fKuC<(FN?3tn&)TgKP1Wy2^dbMu^d@^Nnd`ZrOY$3VFYfhONSg4f;4w+~Hn zruJ=0zK1I%Q`H7%itEU^Mb>rYSX`ZBW@ef_*IYx`J;J;U5Cda;=i#ULUtjnNalJ{t z+(l3-anZUSKKzN_#Sa`l`!6^0=o5!%wI=EA>B03JTI~?e7o<^$#9lY;W}SRK&+N<` z-TnOtDQPuBg1lg6eu>RnHn6m?NTM~lVu|_1WgIWS9~veWHn2_LfP~4|VQBLnWTVMH zfB9B6{ZJmwbV6QvR2Jr#x_TFHe)UTUW6k3S zp62iW=y&+^zkQv*{fE!|B4&mYqTYmm>e)S!{KpclOYBdlJp67`;Y!T%0Ja*(Hv{qPkJl5qE z>xYW$o2g@5*ER#WJZ<4H*{m?LT;=4%B%8>3~D z$!CvJsn!`P_z*{s&z*Mz5{jTzg>w^lSf@4_1o(vlS}LSY(9*FU>N-X1l!ouqQz$UM zu*htZ(A(c@3#mB4;Mu(%`?i!Xp8Y28@G{;0Q}^ZB$mMtSr&LZUe<~Hx&_(Dn<5+!y(U~EEpxtgW($mez#vPoTI7JdSZGK6V zSQCR(a(v<(uJ6)a^0;98b}>FSWC~q9rcmr-NRUa)s&H z3h)2m`*o|)kl(oZPKHLx_Wo2*sjT1yDUO#Xa3JGQp_HOgYgziOF?8jNC?xn2<+#>q z$#rRkOXi(#z21~cg%}~+AK(A|G>NL}u6vG)@aZ#Xlh9~Ihz#Td*tu<#XAT}#SHIv& zv-ip?Y1LP4qh>P05}i_SG^kXXrrm0ZVxbUd5$NG{gCa=`i}Q=5Nn*4S(s3M~-v0!x zb|@Y{Frf|}oRKF_FU#q(i@Lj~!20oRT=&8&b(Cn)PCVh~iYTS1)@oELE9kh1FbPKG zDV7IWzkVajD-|S$G)`zo39?YIbS^9qqBB<~C;Mz-W9u=|xeA3uC`I6l=QRNTh4p*` z@H1A@UX3NjA`wX&M|EYQU3)fl=sE`51So04MLOVrs`Z+|fyj=(G}VOKSR7B-04i+0 z9x{u$?udRng5oqa_>NdBv^yxh*5_S_Y@u#!kdiBj6RR2Mkp8W9EaU92sfi7avR}WW zB%W(U!$~66xcyO*qJ+YC9pcO;$hr{8wbyC=va?1&C{kmm71{`cpBHVT(88jduB(Wn z1f>*7lG08MG6~U9Xvg+}PkZ7p+RGs~>>w5{O`Q_zgnF7VvSkO06Gu3C{3zQuZeptW zEZh3Z-1Mc-^Y7pII$!(hEj;naG{$JFGcbaar>59AzK*S1HWJ4++o92HF+H<@@8>aD z;FMH?p}}6APi&9OrFE&6vqpQk~YUrPTG(#&qWGp(X{OO z(VCUY3Z5r<$&0UMWu?NgqbC>}>Sprf)9A)LAN{R&@wT_Vm;Hwi^RoB+E~n&!T*v(eZH}xci6P@C(1lp<}1nxNZa0N`-S1licu{ z*Kqusw-fZQW1)JILb1&5tFGe9U;GLK7j7j^U8==0!V5A6hain2W~D?9ZsZ-;UxY-n zZ{MSgt{dav!2?{jZJ7D#6lGE#`tgsMTdC1s+DqP1EHqkl?YWkU%F)cyn{|>>EOqn1 zp;P?lZQtbb(ZFozM{F7{nR~u>BaO%xpZb%J@SX4dfRF#_|K#M{3ay|UQ7BWHJ50IM zO`sH`gMBQ{oTaZ^q*1Fezr0K#m#5im(z|{G|MLM6%j z9zn54Wnq!h`cY1uJx7240Qv52HtfEHw(DEn&Y6=m;*_Y_;>_Ft*}c2tPP=m_}`x?tB5)_b8OR7+k->(wB5fWDHH= z0usk080@~GlNg~~z>sqs(sq+(vq`C#M++O2X0-KqcO1`#E21+hp~0k}OpH>)SkW;8~t|<}i*@_@2w~a6eb<-D7I)SolSU*2)}j*|CG)eA6#- z!zXW~YCP*fuM_JEBpq_Ti4Gxq*`qtND(GQ3!4{V zUFan3R)Ql^j7g9gQf?>Kg2Xf-NzuaEqB_`XPlFW>qe+B|k&d-?CL!t2Pg77j2FHdw z8Dj;;N*JVxiL{F~7!5(dV1FM%msy;fMY}%LLXk$K@drk6hS%drMI}y%qXg-=7I@02 zBAxSX?Q_c-6M@MrUhRZHYfUkq<1hZ^Z)wyT{J-qIca&vEeee6JsvS=5KApR#dvYFW zq)`@JsCuh1QJ3L(kRE#1Pui^NSqs&f^6RR9OMN56u*rGNunv$DCdMXuWONcd%R)eIP zuvA?VKl#B=%mo*3Nw%MRf$|+kyRPf>b$QHILV}i{lv5-IoY$vrnQ1+p8Xk{Hm%WDTy+V;am3v0ESX%%rj+Z5q2UeW3SHD|byg3r zXL@>^T6K}G?m?swqUZP9|z+8JsCjuK>iWoK5X-y<$rm$B7V95(|e&#Gs88 z8w*x=jv4`uheoDj*MwM0Oe??%8i-7%edv`(Y&4Z-gTA$!nH@dFsgoyIw{{&jT)K&e zcHfOFB5uF!8{GKXw==g;#c`~Ag_4ppXUCbDnMWyQbp?^e^L;xF)&|E>L_t6l#jIU3 zf;O5~D?ny)gd#y?eX8}k6<0eBLi%>pox~WS5GE!u5(%g@y;d8IpUvVo>Rf&0#cbHH zmdBsm!}eFblviH=GH!m&D>-oR0J%ahQ&VU7*0;Z7YK^8?wQDPLevw2hkjwbI_mBUS zll%AZ&bPge_r3Ey;)Wj6|{s98NNW(}+$l$;r^-6_&{{UgnD#9?Pi;$`PPt)1mOQ#28 zCr=Qd$n^G8=v#%>n#$}fb4yjS#R5}jPob1YZlE8bT&lGimDy=tcf~F?Zdy;AD=@BI znr#SOpI8*|l%l(%gP%RV4_O}M@Y!klhDT_I7J+}+)mI}6ojiX3{Y=a+(N)T$Tn80p zXjT_U;t-=;ykdv7O>8v?8Vy^Bd6^YKz0rvcfO9e^0hPegv|e`kMf~cCXOQI{RFWXI zMmjEmY$J`ZHqAPw9R^r;5tV`xsT-73==vfiXfrm^M&%NoetJIwL#F6csWvDSOY{#8 z5px`4Bst$_W^SG^ipWYs)o6%P>WEZnb_w{t%N@ViEp|Wh6zlGKnA7tOOssHBrKh)-#d?Fzz9Amm zdq0ouIlu+y@8pRS3PjGaJB2bUxjT?!l_5ZDx3 zUn&aHK?>KN8RmJnxfomM$J!90(l9iGG%?D=7$Iz6o|M+&)JTkp(b%&7Ng+}6;7{^2i-?I}gZF6MOP5=!gLZGCg-D)v4J4H{qOi{W_ojpr-T?XUksW+Oo zDN+u?@o+rHz9-9Cx)pknS#cIJDQ_G=q?0D26w>opSd4h|i6^+={0lheyo)&JyvrfY zlhtU_s7=6Ic@Mt+mA|7|TjbCGk53Dqnps*}GH1?CilYbji|>5@4yyGQLqolEl*{