Add board-level support for ES7210 4-ch ADC on lckfb-szpi-esp32s3:
- configs/es7210/defconfig: Board configuration with I2C0, I2S0,
ES7210 driver enabled. I2S pins: BCLK=14, DIN=12, MCLK=38, WS=13,
sample rate 48kHz.
- src/esp32s3_board_es7210.c: Board init registering ES7210 on I2C0
bus with I2S0 as audio transport
- src/esp32s3_bringup.c: Call ES7210 board init on startup; skip
generic I2S audio device registration on I2S0 when ES7210 is
enabled to avoid conflicting audio device on the same port
- src/esp32s3-szpi.h: ES7210 I2C address and device path defines
- src/Make.defs: Build integration for CONFIG_AUDIO_ES7210
Tested: 48kHz/2ch/16bit recording on ESP32-S3 (lckfb-szpi N16R8),
verified with nxrecorder and es7210_test.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Use static lower-half instances per timer and select the channel
through Kconfig and board data instead of passing runtime PWM
routing into the driver.
This keeps the HT32 PWM support aligned with the existing NuttX
pattern and documents the esk32 single-device TMR3 routing.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Document the HT32F491x3 ESK32 board, build steps,
flashing flow, and validation commands. Add WSL and
PowerShell flash backends plus a Python wrapper.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Add UVC configuration for lckfb-szpi-esp32s3 board based on gc0308
camera config, with USB OTG and UVC gadget driver enabled in
standalone (non-composite) mode.
- defconfig: enable ESP32S3_OTG, USBUVC, UVC example app
- board doc: add uvc section with usage and host verification
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add detailed steps for copying nuttx.bin to eMMC via u-boot USB Mass
Storage (ums) mode, which exposes the eMMC as a USB drive on the host
PC for easy file transfer.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Fix 269 occurrences of duplicate "the" word typo found in 209 files
across source code, header files, and configuration.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Remove the CONFIG_K210_WITH_QEMU option and associated conditional
code paths. The reasons for removal are:
* Simplifies code path for real hardware by removing QEMU workarounds
* The current QEMU target uses sifive_u machine, which is not designed
for K210 emulation
* For RISC-V QEMU simulation, the qemu-rv (rv-virt) target is a better
choice
* Renode can be used as an alternative for K210 simulation if needed
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add WDT driver for K210 with support for both WDT0 and WDT1 peripherals.
This includes:
- Add k210_wdt.c and k210_wdt.h driver files with interrupt-based
watchdog timer functionality
- Add hardware register definitions in k210_wdt.h
- Add K210_WDT, K210_WDT0, K210_WDT1 Kconfig options
- Add memory map definitions for WDT0 (0x50400000) and WDT1 (0x50410000)
- Reorder WDT IRQ definitions (IRQ 21, 22) before UART0 (IRQ 33) in irq.h
- Add WDT initialization in board bringup for maix-bit
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add a minimal GC0308 camera configuration based on nsh. Unlike the
full camera config, this only enables the GC0308 DVP camera driver
(I2C, PCA9557, LEDC, CAM, VIDEO) and camcap example, without ADB,
SDMMC, LCD, PSRAM or other peripherals.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add camera configuration for lckfb-szpi-esp32s3 board with GC0308
sensor on DVP interface. Includes board-level camera initialization,
DVP GPIO pin mapping, and V4L2 video pipeline setup.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add sysctl driver for K210 SoC providing clock and reset control:
- Clock enable/disable with two-stage APB/peripheral enable pattern
- Peripheral reset control with proper timing
- Clock frequency query for PLL, CPU, APB buses, and peripherals
- PLL frequency calculation and CPU frequency configuration
The sysctl driver is built unconditionally for K210 boards as it
provides essential clock and reset control functionality.
Add Kconfig option:
- K210_CPU_FREQ: Target CPU frequency in Hz (default 400MHz)
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Three fixes to make LPUART1 work as NSH console on Nucleo-L552ZE-Q:
1. stm32l5_lowputc: add LPUART-specific BRR formula (256 * fCK / baud)
instead of reusing the standard USART divisor calculation.
2. stm32_boot: enable VDDIO2 and reconfigure LPUART1 GPIOs (PG7/PG8)
in board_initialize. The low-level setup runs before VDDIO2 is
enabled, so GPIOG writes silently fail.
3. stm32l5_serial: fix LPUART1 apbclock (PCLK1 not PCLK2), add
LPUART BRR branch in setformat, cast to uint64_t to prevent
32-bit overflow in (fCK << 8).
Also switch nsh defconfig from USART3 to LPUART1, add GPIO_LPUART1
pin definitions in board.h, and update board documentation.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
This commit adds documentation entries for ESP32-P4 chip and its
board (ESP32-P4 Function-EV-Board).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This patch adds support for the user button on nuclo-h743zi2 board
(and nucleo-h753zi2 which is also a MB1364 board design) and enables
button support and example in nucleo-h743zi2:jumbo configuration selector.
Signed-off-by: Peter Barada <peter.barada@gmail.com>
Aligns `CONFIG_INTERPRETER_*` options to `CONFIG_INTERPRETERS_*` to be
consistent with other interpreters.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Alan Carvalho de Assis
Daniel Monteiro
wangjianyu3
simbit18
Felipe Moura
Filipe Cavalcanti
Piyush Patle
Eren Terzioglu
raiden00pl
buxiasen
Huang Qi
anjiahao
zhangyu117
Tiago Medicci Serrano
Michal Matias
Maarten Zanders
Matteo Golin
Peter Barada