arch/tricore: support tc4evb board.

add new chip named tc4xx and board tc4evb Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-05-22 05:42:05 +08:00 · 2026-01-29 16:59:34 +08:00
parent 4be3075a5c
commit 72be575b1a
66 changed files with 7307 additions and 4525 deletions
@@ -31,8 +31,8 @@ The core Chip implementation is based on Infineon Low Level Drivers (iLLDs).
 The unified API is more friendly to developers familiar with Infineon SDK/HAL.
 We can get more code examples on Infineon's official Github: `AURIX_code_examples <https://github.com/Infineon/AURIX_code_examples>`__

-``TC3xx``
-  This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx microcontroller family.
+``TC3xx/TC4xx``
+  This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx/TC4xx microcontroller family.

 .. toctree::
   :maxdepth: 1
@@ -0,0 +1,55 @@
+==================
+TRIBOARD_TC4X9_COM
+==================
+
+This port should work on TRIBOARD_TC4X9_COM with a proper CPU.
+The mandatory CPU features are:
+
+* System Timer (STM)
+* Asynchronous Serial Interface(ASCLIN) UART
+* IRQs are managed by Interrupt Router(INT), IR Service Request Control Registers(SRC).
+
+Toolchains
+==========
+
+Currently, only the Infineon’s AURIX™ GCC toolchain is tested.
+
+Configurations
+==============
+
+Common Configuration Notes
+--------------------------
+
+1. Each TRIBOARD_TC4X9_COM configuration is maintained in a sub-directory
+   and can be selected as follow::
+
+     tools/configure.sh triboard_tc4x9_com:<subdir>
+
+   Where ``<subdir>`` is one of the configuration sub-directories described in
+   the following paragraph.
+
+   NuttX Shell::
+
+     tools/configure.sh triboard_tc4x9_com:nsh
+
+2. These configurations use the mconf-based configuration tool.  To
+   change a configurations using that tool, you should:
+
+   a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+      see additional README.txt files in the NuttX tools repository.
+
+   b. Execute ``make menuconfig`` in nuttx/ in order to start the
+      reconfiguration process.
+
+3. By default, all configurations assume the Linux.  This is easily
+   reconfigured::
+
+     CONFIG_HOST_LINUX=y
+
+Configuration Sub-Directories
+-----------------------------
+
+ostest
+------
+
+The "standard" NuttX examples/ostest configuration.
@@ -0,0 +1,23 @@
+=============
+TriCore/TC4DA
+=============
+
+**TriCore/TC4DA** An TriCore flat address port was ported in NuttX-12.0. It
+consists of the following features:
+
+- Runs in Supervisor Mode.
+- IRQs are managed by Interrupt Router (INT), IR Service Request Control Registers (SRC).
+- Used System timer (STM) for systick.
+
+This kernel with ostest have been tested with
+
+-  Infineon's AURIX™ TC4DA Evaluation Board: TRIBOARD_TC4X9_COM
+
+Supported Boards
+================
+
+.. toctree::
+   :glob:
+   :maxdepth: 1
+
+   boards/*/*
@@ -54,7 +54,7 @@ config ARCH_FAMILY
 	default "tc1v8"		if ARCH_TC1V8

 config ARCH_CHIP_TC3XX
-	bool "infineon aurix tc3xx"
+	bool
 	select ARCH_TC1V6
 	select ARCH_HAVE_ADDRENV
 	select ARCH_HAVE_I2CRESET
@@ -67,7 +67,7 @@ config ARCH_CHIP_TC3XX
 		Infineon aurix tc3xx (six cores)

 config ARCH_CHIP_TC4XX
-	bool "infineon aurix tc4xx"
+	bool
 	select ARCH_TC1V8
 	select ARCH_HAVE_ADDRENV
 	select ARCH_HAVE_I2CRESET
@@ -123,10 +123,21 @@ config HAVE_SECURITY_CORE
 	--help--
 		In addition to the 6 cores, tc4xx also has one more security core.

+config CPU_COREID
+	int "TRICORE CPU CORE ID"
+	default 0
+	range 0 6
+
 if ARCH_CHIP_TC3XX
 source "arch/tricore/src/tc3xx/Kconfig"
 endif
+if ARCH_CHIP_TC4XX
+source "arch/tricore/src/tc4xx/Kconfig"
+endif
 if ARCH_CHIP_TC397
 source "arch/tricore/src/tc397/Kconfig"
 endif
+if ARCH_CHIP_TC4DA
+source "arch/tricore/src/tc4da/Kconfig"
+endif
 endif # ARCH_TRICORE
@@ -157,6 +157,7 @@ extern "C"
 /****************************************************************************
 * Public Types
 ****************************************************************************/
+
 struct xcptcontext
 {
 #ifdef CONFIG_ENABLE_ALL_SIGNALS
@@ -0,0 +1,48 @@
+/****************************************************************************
+ * arch/tricore/include/tc4da/chip.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H
+#define __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_TRICORE_INCLUDE_TC4DA_CHIP_H */
@@ -0,0 +1,71 @@
+/****************************************************************************
+ * arch/tricore/include/tc4da/irq.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H
+#define __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define TRICORE_UART_RX_IRQ      173
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_TRICORE_INCLUDE_TC4DA_IRQ_H */
@@ -19,6 +19,7 @@
 # the License.
 #
 # ##############################################################################
+
 add_subdirectory(${ARCH_SUBDIR})
 add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip)
 add_subdirectory(common)
@@ -22,6 +22,7 @@

 include $(TOPDIR)/Make.defs
 include chip/Make.defs
+include common/Make.defs

 ifeq ($(CONFIG_ARCH_CHIP_TC3XX),y)
 ARCH_SUBDIR = tc3xx
@@ -31,7 +31,7 @@ elseif(CONFIG_ARCH_CHIP_TC4XX)
  set(ARCH_SUBDIR tc4xx)
 endif()

-include(chip.cmake)
+include(${CMAKE_CURRENT_LIST_DIR}/chip.cmake)

 set(TOOLCHAIN_PREFIX tricore-elf)
 set(CMAKE_LIBRARY_ARCHITECTURE ${TOOLCHAIN_PREFIX})
@@ -27,6 +27,7 @@
 #include <stdint.h>

 #include "tricore_internal.h"
+#include "IfxCpu_cfg.h"

 /****************************************************************************
 * Pre-processor Definitions
@@ -38,7 +38,7 @@

 #  include <IfxCpu_reg.h>
 #  include <Ifx_Ssw_Compilers.h>
-#  include <Tricore/Compilers/Compilers.h>
+#  include <Compilers/Compilers.h>
 #  include <IfxCpu_Intrinsics.h>
 #endif

@@ -216,7 +216,12 @@ void up_affinity_irq(int irq, cpu_set_t cpuset)
   * so routing to the first cpu in cpuset.
   */

+#ifdef CONFIG_ARCH_CHIP_TC3XX
  IfxSrc_init(src, ffs(cpuset) - 1, irq_prio);
+#else
+  IfxSrc_init(src, ffs(cpuset) - 1, irq_prio, IfxSrc_VmId_none);
+#endif
+
  IfxSrc_enable(src);
 }

@@ -29,7 +29,12 @@

 #include "Ifx_Types.h"
 #include "IfxCpu.h"
-#include "IfxScuWdt.h"
+
+#ifdef CONFIG_ARCH_CHIP_TC4XX
+#  include "IfxWtu.h"
+#else
+#  include "IfxScuWdt.h"
+#endif

 /****************************************************************************
 * Private Functions
@@ -46,7 +51,12 @@ static void core_main(void)
  /* Wait for CPU sync event */

  IfxCpu_emitEvent(&g_sync_event);
+
+#if defined(CONFIG_ARCH_CHIP_TC3XX)
  IfxCpu_waitEvent(&g_sync_event, 1);
+#else
+  IfxCpu_waitEvent(&g_sync_event, UINT32_MAX, 1);
+#endif

  if (IfxCpu_getCoreIndex() == 0)
    {
@@ -0,0 +1,68 @@
+/****************************************************************************
+ * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H
+#define __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define DEVICE_TC39XB  1
+#define IFX_PIN_PACKAGE_LFBGA292  1
+
+#define IFX_CFG_SCU_XTAL_FREQUENCY      (20000000)
+#define IFX_CFG_SCU_PLL_FREQUENCY       (300000000)
+#define IFX_CFG_SCU_PLL1_FREQUENCY      (320000000)
+#define IFX_CFG_SCU_PLL2_FREQUENCY      (200000000)
+
+#define IFX_CFG_CPU_CLOCK_FREQUENCY     IFX_CFG_SCU_PLL_FREQUENCY
+
+#define ISR_PRIORITY_STM_TICK          1
+#define ISR_PRIORITY_GETH_DMA0_TX      2
+#define ISR_PRIORITY_GETH_DMA0_RX      3
+
+#ifdef CONFIG_TRICORE_BL
+#  define IFX_CFG_SSW_ENABLE_TRICORE0 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE1 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE2 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE3 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE4 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE5 0
+#else
+#  define IFX_CFG_SSW_ENABLE_TRICORE0 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE1 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE2 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE3 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE4 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE5 1
+#endif
+
+#define IFX_CFG_SSW_ENABLE_INDIVIDUAL_C_INIT (1U)
+
+#endif /* __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_H */
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "Ifx_Cfg_Ssw.h"
+#include "Ifx_Ssw_Infra.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#if defined(__TASKING__)
+#pragma optimize RL
+#elif defined(__GNUC__)
+#pragma GCC optimize ("O1")
+#endif
+
+#if (IFX_CFG_SSW_ENABLE_LBIST == 1)
+void Ifx_Ssw_Lbist(void)
+{
+  if (!IfxScuLbist_isDone())
+    {
+      if(Ifx_Ssw_isColdPoweronReset())
+        {
+          IfxScuLbist_triggerInline(&IfxScuLbist_defaultConfig);
+        }
+    }
+
+  if (!IfxScuLbist_evaluateResult(IfxScuLbist_defaultConfig.signature))
+    {
+       __debug();
+       while(1);
+    }
+
+    Ifx_Ssw_jumpBackToLink();
+}
+#endif
+
+#if defined(__TASKING__)
+#pragma endoptimize
+#elif defined(__GNUC__)
+#pragma GCC reset_options
+#endif
@@ -0,0 +1,111 @@
+/****************************************************************************
+ * arch/tricore/src/illd/tc3xx/Configurations/Ifx_Cfg_Ssw.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H
+#define __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "Ifx_Cfg.h"
+#include "Ifx_Ssw.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef IFX_CFG_SSW_ENABLE_LBIST
+#define IFX_CFG_SSW_ENABLE_LBIST          (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_MONBIST
+#define IFX_CFG_SSW_ENABLE_MONBIST        (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_PLL_INIT
+#define IFX_CFG_SSW_ENABLE_PLL_INIT       (1U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_MBIST
+#define IFX_CFG_SSW_ENABLE_MBIST          (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_SMU
+#define IFX_CFG_SSW_ENABLE_SMU            (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_EMEM_INIT
+#define IFX_CFG_SSW_ENABLE_EMEM_INIT      (0U)
+#endif
+
+#ifndef IFX_SCU_FLASHWAITSTATECHECK
+#define IFX_SCU_FLASHWAITSTATECHECK       (0U)
+#endif
+
+#if IFX_CFG_SSW_ENABLE_LBIST == 1U
+#include "IfxScuLbist.h"
+
+extern void Ifx_Ssw_Lbist(void);
+#define IFX_CFG_SSW_CALLOUT_LBIST()               \
+{                                                 \
+  Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Lbist); \
+}
+#endif
+
+#if IFX_CFG_SSW_ENABLE_MONBIST == 1U
+#include "IfxSmuStdby.h"
+
+extern void Ifx_Ssw_Monbist(void);
+#define IFX_CFG_SSW_CALLOUT_MONBIST()               \
+{                                                   \
+  Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Monbist); \
+}
+#endif
+
+#if IFX_CFG_SSW_ENABLE_PLL_INIT == 1U
+#include "IfxScuCcu.h"
+
+#define IFX_CFG_SSW_CALLOUT_PLL_INIT()                    \
+{                                                         \
+  if (IfxScuCcu_init(&IfxScuCcu_defaultClockConfig) == 1) \
+    {                                                     \
+      __debug();                                          \
+    }                                                     \
+}
+
+#endif
+
+#if IFX_CFG_SSW_ENABLE_MBIST == 1U
+#include "IfxMtu.h"
+
+#define IFX_CFG_SSW_CALLOUT_MBIST()                             \
+{                                                               \
+  IFX_EXTERN const IfxMtu_MbistConfig *const mbistGangConfig[]; \
+  if (IfxMtu_runMbistAll(mbistGangConfig) == 1U)                \
+    {                                                           \
+      __debug();                                                \
+    }                                                           \
+}
+
+#endif
+#endif /* __ARCH_TRICORE_SRC_ILLD_TC3XX_CONFIGURATIONS_IFX_CFG_SSW_H */
@@ -0,0 +1,60 @@
+diff --git a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c
+index f893b3e7e4b..e86811079d2 100644
+--- a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c
+++ b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c
+@@ -45,6 +45,12 @@
+ /*-------------------------Infrastructure Functions---------------------------*/
+ /******************************************************************************/
+ 
+IFX_SSW_WEAK void hardware_init_hook(void)
+{}
+
+IFX_SSW_WEAK void software_init_hook(void)
+{}
+
+ unsigned short Ifx_Ssw_getCpuWatchdogPassword(Ifx_SCU_WDTCPU *watchdog)
+ {
+     return Ifx_Ssw_getCpuWatchdogPasswordInline(watchdog);
+@@ -200,6 +206,7 @@ void Ifx_Ssw_doCppInit(void)
+ {
+     Ifx_Ssw_C_InitInline();
+ 
+#ifndef __NuttX__
+ 	#ifdef __TASKING__
+ 		extern void _main(void); /* cpp initialization */
+ 		_main();
+@@ -219,10 +226,12 @@ void Ifx_Ssw_doCppInit(void)
+ 		extern void _main(void); /* cpp initialization */
+ 		_main();
+ 	#endif
+#endif /* __NuttX__ */
+ }
+ 
+ void Ifx_Ssw_doCppExit(int status)
+ {
+#ifndef __NuttX__
+ 	#ifdef __TASKING__
+ 		extern void _doexit(void); /* cpp deinitialization */
+ 		_doexit();
+@@ -239,7 +248,7 @@ void Ifx_Ssw_doCppExit(int status)
+ 		extern void exit(int); /* cpp deinitialization */
+ 		exit(0);
+ 	#endif
+-
+#endif /* __NuttX__ */
+ }
+ 
+ 
+diff --git a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c
+index 0c6b0771bf0..4b68b8b4121 100644
+--- a/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c
+++ b/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c
+@@ -344,7 +344,7 @@ void IfxCpu_Trap_vectorTable0(void)
+     /* Map Instruction Error trap to its handler for CPU0 */
+     IfxCpu_Tsr_CallTSR(IfxCpu_Trap_instructionError);
+     /*  Map Context Management Error trap to its handler for CPU0 */
+-    IfxCpu_Tsr_CallCSATSR(IfxCpu_Trap_contextManagementError);
+    IfxCpu_Tsr_CallTSR(IfxCpu_Trap_contextManagementError);
+     /* Map Bus Error trap to its handler for CPU0 */
+     IfxCpu_Tsr_CallTSR(IfxCpu_Trap_busError);
+     /* Map Assertion trap to its handler for CPU0 */
@@ -0,0 +1,79 @@
+/****************************************************************************
+ * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H
+#define __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#define DEVICE_TC4DX  1
+
+#define IFX_CFG_CLOCK_XTAL_FREQUENCY    (25000000)
+#define IFX_CFG_CLOCK_SYSPLL_FREQUENCY  (500000000)
+#define IFX_CFG_CLOCK_PPUPLL_FREQUENCY  (450000000)
+#define IFX_CFG_CLOCK_PERPLL1_FREQUENCY (160000000)
+#define IFX_CFG_CLOCK_PERPLL2_FREQUENCY (200000000)
+#define IFX_CFG_CLOCK_PERPLL3_FREQUENCY (200000000)
+
+#define IFX_CFG_CPU_CLOCK_FREQUENCY     IFX_CFG_CLOCK_SYSPLL_FREQUENCY
+
+#define IFX_PROT_ENABLED                0
+#define IFX_CFG_VIRTUALIZATION_DISABLED 1
+#define IFX_CFG_STM_MORPHING_ENABLE     1
+#define IFX_CLOCK_BYPASS_FOSC_F         0
+
+#define IFX_STM_RESOULTION              IFX_CFG_CLOCK_SYSPLL_FREQUENCY
+
+#define IFX_CFG_INTERRUPT_INTERVAL      (0.003)
+
+#define IFX_CFG_CPU0_PRIO               10
+#define IFX_CFG_CPU1_PRIO               10
+#define IFX_CFG_CPU2_PRIO               10
+#define IFX_CFG_CPU3_PRIO               10
+#define IFX_CFG_CPU4_PRIO               10
+#define IFX_CFG_CPU5_PRIO               10
+
+#define ISR_PRIORITY_STM0_TICK          1
+#define ISR_PRIORITY_GETH0_DMA0_TX      2
+#define ISR_PRIORITY_GETH0_DMA0_RX      3
+
+#ifdef CONFIG_TRICORE_BL
+#  define IFX_CFG_SSW_ENABLE_TRICORE0 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE1 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE2 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE3 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE4 0
+#  define IFX_CFG_SSW_ENABLE_TRICORE5 0
+#else
+#  define IFX_CFG_SSW_ENABLE_TRICORE0 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE1 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE2 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE3 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE4 1
+#  define IFX_CFG_SSW_ENABLE_TRICORE5 1
+#endif
+
+#endif /* __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_H */
@@ -0,0 +1,211 @@
+/****************************************************************************
+ * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <string.h>
+
+#include "Ifx_Cfg_Ssw.h"
+#include "Ifx_Ssw_Infra.h"
+
+#if (IFX_CFG_SSW_ENABLE_LBIST == 1)
+#include "IfxApProt.h"
+#include "IfxTriLbist.h"
+#endif
+
+#include "IfxVmt.h"
+#include "IfxPmsPm.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#if defined(__TASKING__)
+#pragma optimize RL
+#elif defined(__GNUC__)
+#pragma GCC optimize ("O1")
+#endif
+
+#if (IFX_CFG_SSW_ENABLE_LBIST == 1)
+void Ifx_Ssw_Lbist(void)
+{
+  uint16 result;
+
+  IfxApProt_setState((Ifx_PROT_PROT *)&TRI_PROTSE, IfxApProt_State_config);
+  TRI_ACCEN_WRA.U = 0xFFFFFFFFU;
+  TRI_ACCEN_WRB.U = 0xFFFFFFFFU;
+  IfxApProt_setState((Ifx_PROT_PROT *)&TRI_PROTSE, IfxApProt_State_run);
+
+  result = IfxTriLbist_evaluateResult(&IfxTriLbist_keyOnDefaultConfig.signature[0]);
+
+  if (result)
+    {
+      if (IfxTriLbist_getFailCount() >= 2)
+        {
+          Ifx_Ssw_debug();
+        }
+      else
+        {
+          IfxTriLbist_incrementFailCount();
+        }
+
+      IfxTriLbist_resetLbist();
+      IfxTriLbist_triggerInline(&IfxTriLbist_keyOnDefaultConfig);
+    }
+}
+#endif
+
+#if (IFX_CFG_SSW_ENABLE_MONBIST == 1)
+void Ifx_Ssw_Monbist(void)
+{
+}
+#endif
+
+#if (IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM == 1)
+void Ifx_Ssw_MbistDsprsDmaRam(void)
+{
+}
+#endif
+
+#if IFX_CFG_SSW_ENABLE_PLL_INIT == 1U
+#include "IfxClock.h"
+
+void Ifx_Ssw_PowerOnCrystalOsc(void)
+{
+  Ifx_CLOCK_OSCCON scuOsccon;
+  unsigned int     initError         = 0U;
+  unsigned int     timeoutCycleCount = IFX_CFG_SSW_CCUCON_LCK_BIT_TIMEOUT_COUNT;
+  scuOsccon.U = CLOCK_OSCCON.U;
+
+#if (IFX_CFG_SSW_CLOCK_EXT_CLOCK == 1)
+  scuOsccon.B.MODE = 2U;
+#else
+  scuOsccon.B.MODE = 0U;
+#endif
+
+  while (CLOCK_CCUSTAT.B.LCK != 0U)
+    {
+      IFX_CFG_SSW_LOOP_TIMEOUT_CHECK(timeoutCycleCount, initError);
+    }
+
+  CLOCK_OSCCON.U = scuOsccon.U;
+
+  if (initError)
+    {
+      Ifx_Ssw_debug();
+    }
+}
+
+void Ifx_Ssw_PllInit(void)
+{
+  if (IfxClock_init(&IfxClock_defaultClockConfig) != 0U)
+    {
+      __debug();
+    }
+}
+#endif
+
+#if IFX_CFG_SSW_ENABLE_MBIST == 1U
+void Ifx_Ssw_Mbist(void)
+{
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu0);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu1);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu2);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu3);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu4);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu5);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu6);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu7);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu8);
+  IfxVmt_clearSram(IfxVmt_MbistSel_lmu9);
+
+  /* clear CAN Message RAM */
+
+  IfxVmt_clearSram(IfxVmt_MbistSel_mcan0);
+  IfxVmt_clearSram(IfxVmt_MbistSel_mcan1);
+  IfxVmt_clearSram(IfxVmt_MbistSel_mcan2);
+  IfxVmt_clearSram(IfxVmt_MbistSel_mcan3);
+  IfxVmt_clearSram(IfxVmt_MbistSel_mcan4);
+}
+#endif
+
+#if IFX_CFG_SSW_ENABLE_SMU == 1U
+void Ifx_Ssw_Smu(void)
+{
+}
+#endif
+
+#if (IFX_CFG_SSW_ENABLE_KEYOFF_LBIST == 1)
+void Ifx_Ssw_Keyoff_Lbist(void)
+{
+}
+#endif
+
+#if IFX_CFG_SSW_ENABLE_KEYOFF_MBIST == 1U
+void Ifx_Ssw_Keyoff_Mbist(void)
+{
+}
+#endif
+
+#if (IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM == 1)
+void Ifx_Ssw_Keyoff_MbistDsprsDmaRam(void)
+{
+}
+#endif
+
+#if IFX_CFG_SSW_ENABLE_AP_INIT == 1U
+void weak_function Ifx_Ssw_AP_Init(void)
+{
+}
+#endif
+
+void Ifx_Ssw_MultiCore_Sync_Cpu0(void)
+{
+}
+
+void Ifx_Ssw_MultiCore_Sync_Cpu1(void)
+{
+}
+
+void Ifx_Ssw_MultiCore_Sync_Cpu2(void)
+{
+}
+
+void Ifx_Ssw_MultiCore_Sync_Cpu3(void)
+{
+}
+
+void Ifx_Ssw_MultiCore_Sync_Cpu4(void)
+{
+}
+
+void Ifx_Ssw_MultiCore_Sync_Cpu5(void)
+{
+}
+
+#if defined(__TASKING__)
+#pragma endoptimize
+#elif defined(__GNUC__)
+#pragma GCC reset_options
+#endif
@@ -0,0 +1,81 @@
+/****************************************************************************
+ * arch/tricore/src/illd/tc4xx/Configurations/Ifx_Cfg_Ssw.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H
+#define __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "Ifx_Cfg.h"
+#include "Ifx_Ssw.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef IFX_CFG_SSW_ENABLE_LBIST
+#define IFX_CFG_SSW_ENABLE_LBIST                         (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_MONBIST
+#define IFX_CFG_SSW_ENABLE_MONBIST                       (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM
+#define IFX_CFG_SSW_ENABLE_MBIST_DSPRS_DMARAM            (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_XTALSRC_CHECK
+#define IFX_CFG_SSW_ENABLE_XTALSRC_CHECK                 (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_PLL_INIT
+#define IFX_CFG_SSW_ENABLE_PLL_INIT                      (1U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_MBIST
+#define IFX_CFG_SSW_ENABLE_MBIST                         (1U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_SMU
+#define IFX_CFG_SSW_ENABLE_SMU                           (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_AP_INIT
+#define IFX_CFG_SSW_ENABLE_AP_INIT                       (1U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_LBIST
+#define IFX_CFG_SSW_ENABLE_KEYOFF_LBIST                  (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_MBIST
+#define IFX_CFG_SSW_ENABLE_KEYOFF_MBIST                  (0U)
+#endif
+
+#ifndef IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM
+#define IFX_CFG_SSW_ENABLE_KEYOFF_MBIST_DSPRS_DMARAM     (0U)
+#endif
+
+#endif /* __ARCH_TRICORE_SRC_ILLD_TC4XX_CONFIGURATIONS_IFX_CFG_SSW_H */
@@ -0,0 +1,33 @@
+diff --git a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c
+index cf3c6c74010..f386599481e 100644
+--- a/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c
+++ b/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c
+@@ -429,6 +429,7 @@ void Ifx_Ssw_doCppInit(void)
+ {
+     Ifx_Ssw_C_InitInline();
+ 
+#ifndef __NuttX__
+ #ifdef __TASKING__
+     extern void _main(void); /* cpp initialization */
+     _main();
+@@ -451,10 +452,12 @@ void Ifx_Ssw_doCppInit(void)
+ #elif defined(__DCC__)
+     /* Cpp Init part of the init_main called in C Init Inline */
+ #endif
+#endif
+ }
+ 
+ void Ifx_Ssw_doCppExit(int status)
+ {
+#ifndef __NuttX__
+ #ifdef __TASKING__
+     extern void _doexit(void); /* cpp deinitialization */
+     _doexit();
+@@ -474,6 +477,7 @@ void Ifx_Ssw_doCppExit(int status)
+     extern void exit(int); /* cpp deinitialization */
+     exit(0);
+ #endif
+#endif
+ }
+ 
+ 
@@ -19,19 +19,3 @@
 # the License.
 #
 # ##############################################################################
-
-if(CONFIG_ARCH_CHIP_TC397)
-  if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/tc397)
-    FetchContent_Declare(
-      tc397
-      URL https://github.com/wangchdo/tc397_sdk/archive/refs/heads/master.tar.gz
-          SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/tc397 BINARY_DIR
-          ${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/${CONFIG_ARCH_CHIP}/tc397)
-    FetchContent_GetProperties(tc397)
-    if(NOT tc397_POPULATED)
-      FetchContent_Populate(tc397)
-    endif()
-  endif()
-
-  add_subdirectory(tc397)
-endif()
@@ -19,31 +19,3 @@
 # under the License.
 #
 ############################################################################
-ifeq ($(CONFIG_ARCH_CHIP_TC397),y)
-  -include tc397/tc397/Make.defs
-endif
-
-TC397_UNPACK  = tc397
-TC397_COMMIT  = master
-TC397_URL     = https://github.com/wangchdo/tc397_sdk/archive/refs/heads
-TC397_TARBALL = tc397/$(TC397_UNPACK).tar.gz
-TC397_DIR     = tc397_sdk-master
-
-$(TC397_TARBALL):
-	$(call DOWNLOAD,$(TC397_URL),$(TC397_COMMIT).tar.gz,$(TC397_TARBALL))
-
-tc397/.tc397_unpack: $(TC397_TARBALL)
-	$(Q) echo "Unpacking: TC397"
-	$(Q) tar xzf $(TC397_TARBALL) -C tc397
-	$(Q) mv tc397/$(TC397_DIR) tc397/$(TC397_UNPACK)
-	$(Q) touch tc397/.tc397_unpack
-
-
-ifeq ($(wildcard tc397/$(TC397_UNPACK)/.git),)
-context:: tc397/.tc397_unpack
-
-distclean::
-	$(call DELFILE, tc397/.tc397_unpack)
-	$(call DELFILE, $(TC397_TARBALL))
-	$(call DELDIR, tc397/$(TC397_UNPACK))
-endif
@@ -31,3 +31,131 @@ if(CONFIG_TRICORE_TOOLCHAIN_TASKING)
    nuttx PRIVATE
    --library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip)
 endif()
+
+set(ILLD_UNPACK "${CMAKE_CURRENT_SOURCE_DIR}/../illd/tc3xx")
+set(ILLD_TARBALL "${ILLD_UNPACK}/illd.tar.gz")
+set(ILLD_UNPACK_NAME "illd_release_tc3x-main")
+set(ILLD_SRC "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}/src/BaseSw")
+set(ILLD_URL
+    "https://github.com/Infineon/illd_release_tc3x/archive/refs/heads/main.tar.gz"
+)
+
+set(CONFIG_DIR "${ILLD_UNPACK}/Configurations")
+set(ILLD_DIR "${ILLD_UNPACK}/Libraries/src")
+set(PATCHES_DIR "${ILLD_UNPACK}/patches")
+
+if(NOT EXISTS "${ILLD_DIR}/Libraries")
+  file(MAKE_DIRECTORY "${ILLD_UNPACK}")
+  file(DOWNLOAD "${ILLD_URL}" "${ILLD_TARBALL}" SHOW_PROGRESS)
+
+  message(STATUS "Unpacking: ILLD for tc3xx")
+  execute_process(
+    COMMAND ${CMAKE_COMMAND} -E tar xzf "${ILLD_TARBALL}"
+    WORKING_DIRECTORY "${ILLD_UNPACK}"
+    RESULT_VARIABLE tar_result)
+  if(NOT tar_result EQUAL 0)
+    message(FATAL_ERROR "Failed to unpack ${ILLD_TARBALL}")
+  endif()
+
+  file(MAKE_DIRECTORY "${ILLD_DIR}/Libraries")
+
+  execute_process(COMMAND ${CMAKE_COMMAND} -E copy_directory "${ILLD_SRC}/"
+                          "${ILLD_DIR}/Libraries/" RESULT_VARIABLE copy_result)
+  if(NOT copy_result EQUAL 0)
+    message(
+      FATAL_ERROR
+        "Failed to stage ILLD from ${ILLD_SRC} to ${ILLD_DIR}/Libraries")
+  endif()
+
+  file(REMOVE_RECURSE "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}")
+endif()
+
+file(GLOB PATCH_FILES "${PATCHES_DIR}/*.patch")
+
+foreach(PATCH ${PATCH_FILES})
+  execute_process(
+    COMMAND git apply --reverse --check ${PATCH}
+    WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo
+                                          # root
+    RESULT_VARIABLE PATCH_NEEDED
+    OUTPUT_QUIET ERROR_QUIET)
+
+  if(PATCH_NEEDED EQUAL 0)
+    message(STATUS "Patch ${PATCH} already applied, skipping.")
+  else()
+    execute_process(
+      COMMAND git apply --whitespace=nowarn ${PATCH}
+      WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo
+                                            # root
+      RESULT_VARIABLE APPLY_RESULT)
+    if(NOT APPLY_RESULT EQUAL 0)
+      message(FATAL_ERROR "Failed to apply patch ${PATCH}!")
+    else()
+      message(STATUS "Successfully applied patch ${PATCH}.")
+    endif()
+  endif()
+endforeach()
+
+set(SDK_INCDIR
+    "${CONFIG_DIR}"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Src/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Timer"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x"
+    "${ILLD_DIR}/Libraries/Infra/Platform"
+    "${ILLD_DIR}/Libraries/Infra/Platform/Tricore"
+    "${ILLD_DIR}/Libraries/Infra/Sfr/TC39xB"
+    "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore"
+    "${ILLD_DIR}/Libraries/Service/CpuGeneric")
+
+target_include_directories(arch PRIVATE ${SDK_INCDIR})
+target_include_directories(nuttx PRIVATE ${SDK_INCDIR})
+
+set_property(
+  TARGET nuttx
+  APPEND
+  PROPERTY NUTTX_INCLUDE_DIRECTORIES ${SDK_INCDIR})
+
+set(SDK_CSRCS
+    "${CONFIG_DIR}/Ifx_Cfg_Ssw.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x/IfxAsclin_PinMap_TC39xB_LFBGA292.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsEvr.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsPm.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Port/Std/IfxPort.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuCcu.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuEru.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuLbist.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuRcu.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuWdt.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Src/Std/IfxSrc.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Stm/Std/IfxStm.c"
+    "${ILLD_DIR}/Libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c"
+    "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c"
+    "${ILLD_DIR}/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Tc0.c")
+
+target_sources(nuttx PRIVATE ${SDK_CSRCS})
+
+if(NOT CONFIG_TRICORE_TOOLCHAIN_TASKING)
+  target_compile_options(nuttx PRIVATE -Wno-undef -Wno-strict-prototypes
+                                       -Wno-shadow)
+  target_compile_options(nuttx PRIVATE -fstrict-volatile-bitfields)
+  target_compile_options(nuttx PRIVATE -Wno-unused-parameter
+                                       -Wno-unused-but-set-parameter)
+  target_compile_options(nuttx PRIVATE -Wno-implicit-fallthrough)
+else()
+  nuttx_add_extra_library(
+    "${CMAKE_CURRENT_LIST_DIR}/illd/prebuilts/tc162/cinit.o")
+endif()
@@ -47,4 +47,99 @@ EXTRA_LIBS += libos$(LIBEXT)

 endif

-LIBPATHS   += $(CURDIR)
+ILLD_UNPACK = illd/tc3xx
+ILLD_TARBALL = $(ILLD_UNPACK)/illd.tar.gz
+ILLD_UNPACK_NAME = illd_release_tc3x-main
+ILLD_SRC = $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)/src/BaseSw
+ILLD_URL = https://github.com/Infineon/illd_release_tc3x/archive/refs/heads
+
+$(ILLD_TARBALL):
+	$(call DOWNLOAD,$(ILLD_URL),main.tar.gz,$(ILLD_TARBALL))
+
+$(ILLD_UNPACK)/.illd_unpack: $(ILLD_TARBALL)
+	$(Q) echo "Unpacking: ILLD"
+	$(Q) tar xzf $(ILLD_TARBALL) -C $(ILLD_UNPACK)
+	$(Q) mkdir -p $(ILLD_UNPACK)/Libraries/src/Libraries
+	$(Q) mv $(ILLD_SRC)/* $(ILLD_UNPACK)/Libraries/src/Libraries/
+	$(Q) rm -rf $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)
+	$(Q) touch $(ILLD_UNPACK)/.illd_unpack
+
+ifeq ($(wildcard $(ILLD_UNPACK)/.git),)
+context:: $(ILLD_UNPACK)/.illd_unpack
+
+distclean::
+	$(call DELFILE, $(ILLD_UNPACK)/.illd_unpack)
+	$(call DELFILE, $(ILLD_TARBALL))
+	$(call DELDIR, $(ILLD_UNPACK)/Libraries/src/Libraries)
+endif
+
+CONFIG_DIR = $(ILLD_UNPACK)/Configurations
+ILLD_DIR = $(ILLD_UNPACK)/Libraries/src
+PATCHES_DIR = $(ILLD_UNPACK)/patches
+PATCH_FILES = $(wildcard $(CURDIR)/$(PATCHES_DIR)/*.patch)
+
+apply_change_patches:
+	@if [ -n "$(PATCH_FILES)" ]; then \
+		for p in $(PATCH_FILES); do \
+			if git -C "$(CURDIR)" apply --reverse --check "$$p" >/dev/null 2>&1; then \
+				echo "-- Patch $$p already applied, skipping."; \
+			else \
+				if git -C "$(CURDIR)" apply --whitespace=nowarn "$$p" >/dev/null 2>&1; then \
+					echo "-- Successfully applied patch $$p."; \
+				else \
+					echo "-- Failed to apply patch $$p!"; \
+					exit 1; \
+				fi; \
+			fi; \
+		done; \
+	fi
+
+context:: apply_change_patches
+
+SDK_INCDIR += ${CONFIG_DIR}
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Src/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Timer
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform/Tricore
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Sfr/TC39xB
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Service/CpuGeneric
+
+SDK_CSRCS += ${CONFIG_DIR}/Ifx_Cfg_Ssw.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_PinMap/TC39x/IfxAsclin_PinMap_TC39xB_LFBGA292.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsEvr.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Pms/Std/IfxPmsPm.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Port/Std/IfxPort.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuCcu.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuEru.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuLbist.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuRcu.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Scu/Std/IfxScuWdt.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Src/Std/IfxSrc.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Stm/Std/IfxStm.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Platform/Tricore/Compilers/CompilerTasking.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Infra.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC3xx/Tricore/Ifx_Ssw_Tc0.c
+
+CFLAGS += $(addprefix ${INCDIR_PREFIX},$(SDK_INCDIR))
+
+VPATH += $(dir $(SDK_CSRCS))
+
+HEAD_CSRC += $(notdir $(SDK_CSRCS))
+
+LIBPATHS += $(CURDIR)
@@ -29,9 +29,9 @@ ifeq ($(CONFIG_ARCH_CHIP_TC397),y)
    ARCHCPUFLAGS += -mtc162
  endif

-  ARCHINCLUDES += ${INCDIR_PREFIX}$(CHIP_DIR)/tc397/Libraries/iLLD/TC39B/Tricore/Cpu/Std
-  ARCHINCLUDES += ${INCDIR_PREFIX}$(CHIP_DIR)/tc397/Libraries/Infra/Platform
-  ARCHINCLUDES += ${INCDIR_PREFIX}$(CHIP_DIR)/tc397/Configurations
+  ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/iLLD/TC3xx/Tricore/Cpu/Std
+  ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Libraries/src/Libraries/Infra/Platform
+  ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc3xx/Configurations
 endif

 include $(TOPDIR)/arch/tricore/src/common/Toolchain.defs
@@ -0,0 +1,21 @@
+# ##############################################################################
+# arch/tricore/src/tc4da/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
@@ -0,0 +1,5 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
@@ -0,0 +1,21 @@
+############################################################################
+# arch/tricore/src/tc4da/Make.defs
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
@@ -0,0 +1,33 @@
+/****************************************************************************
+ * arch/tricore/src/tc4da/chip.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_TRICORE_SRC_TC4DA_CHIP_H
+#define __ARCH_TRICORE_SRC_TC4DA_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#define UART_PIN_RX IfxAsclin0_RXA_F_P14_1_IN     /* UART receive port pin  */
+#define UART_PIN_TX IfxAsclin0_TX_F_P14_0_OUT     /* UART transmit port pin */
+
+#endif /* __ARCH_TRICORE_SRC_TC4DA_CHIP_H */
@@ -0,0 +1,192 @@
+# ##############################################################################
+# arch/tricore/src/tc4xx/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS tc4xx_timerisr.c tc4xx_serial.c)
+
+target_sources(arch PRIVATE ${SRCS})
+
+if(CONFIG_TRICORE_TOOLCHAIN_TASKING)
+  nuttx_add_kernel_library(c_fpu)
+  target_sources(c_fpu PRIVATE tc4xx_libc.c)
+  target_link_options(
+    nuttx PRIVATE
+    --library-directory=${CMAKE_BINARY_DIR}/arch/tricore/src/exclude_chip)
+endif()
+
+set(ILLD_UNPACK "${CMAKE_CURRENT_SOURCE_DIR}/../illd/tc4xx")
+set(ILLD_TARBALL "${ILLD_UNPACK}/illd.tar.gz")
+set(ILLD_UNPACK_NAME "illd_release_tc4x-main")
+set(ILLD_SRC "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}/src/Libraries")
+set(ILLD_URL
+    "https://github.com/Infineon/illd_release_tc4x/archive/refs/heads/main.tar.gz"
+)
+
+set(CONFIG_DIR "${ILLD_UNPACK}/Configurations")
+set(ILLD_DIR "${ILLD_UNPACK}/Libraries/src")
+set(PATCHES_DIR "${ILLD_UNPACK}/patches")
+
+if(NOT EXISTS "${ILLD_DIR}/Libraries")
+  file(MAKE_DIRECTORY "${ILLD_UNPACK}")
+  file(DOWNLOAD "${ILLD_URL}" "${ILLD_TARBALL}")
+
+  message(STATUS "Unpacking: ILLD for tc4xx")
+  execute_process(
+    COMMAND ${CMAKE_COMMAND} -E tar xzf "${ILLD_TARBALL}"
+    WORKING_DIRECTORY "${ILLD_UNPACK}"
+    RESULT_VARIABLE tar_result)
+  if(NOT tar_result EQUAL 0)
+    message(FATAL_ERROR "Failed to unpack ${ILLD_TARBALL}")
+  endif()
+
+  file(MAKE_DIRECTORY "${ILLD_DIR}/Libraries")
+
+  execute_process(COMMAND ${CMAKE_COMMAND} -E copy_directory "${ILLD_SRC}/"
+                          "${ILLD_DIR}/Libraries/" RESULT_VARIABLE copy_result)
+  if(NOT copy_result EQUAL 0)
+    message(
+      FATAL_ERROR
+        "Failed to stage ILLD from ${ILLD_SRC} to ${ILLD_DIR}/Libraries")
+  endif()
+
+  file(REMOVE_RECURSE "${ILLD_UNPACK}/${ILLD_UNPACK_NAME}")
+endif()
+
+file(GLOB PATCH_FILES "${PATCHES_DIR}/*.patch")
+
+foreach(PATCH ${PATCH_FILES})
+  execute_process(
+    COMMAND git apply --reverse --check ${PATCH}
+    WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo
+                                          # root
+    RESULT_VARIABLE PATCH_NEEDED
+    OUTPUT_QUIET ERROR_QUIET)
+
+  if(PATCH_NEEDED EQUAL 0)
+    message(STATUS "Patch ${PATCH} already applied, skipping.")
+  else()
+    execute_process(
+      COMMAND git apply --whitespace=nowarn ${PATCH}
+      WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} # Patches are applied from the repo
+                                            # root
+      RESULT_VARIABLE APPLY_RESULT)
+    if(NOT APPLY_RESULT EQUAL 0)
+      message(FATAL_ERROR "Failed to apply patch ${PATCH}!")
+    else()
+      message(STATUS "Successfully applied patch ${PATCH}.")
+    endif()
+  endif()
+endforeach()
+
+set(SDK_INCDIR
+    "${CONFIG_DIR}"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/ArcEV"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Asc"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Lin"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Atom"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Tom"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Crc"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Scr"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_PinMap"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_PinMap/TC4Dx"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Can/Can"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Can/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Flash/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/I2c/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Pms/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Scu/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smu/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Src/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Timer"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Vmt/Std"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Wtu/Std"
+    "${ILLD_DIR}/Libraries/Infra/Platform"
+    "${ILLD_DIR}/Libraries/Infra/Sfr/TC4Dx"
+    "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore"
+    "${ILLD_DIR}/Libraries/Service/CpuGeneric"
+    "${ILLD_DIR}/Libraries/Infra/Platform/Compilers")
+
+target_include_directories(arch PRIVATE ${SDK_INCDIR})
+target_include_directories(nuttx PRIVATE ${SDK_INCDIR})
+
+set_property(
+  TARGET nuttx
+  APPEND
+  PROPERTY NUTTX_INCLUDE_DIRECTORIES ${SDK_INCDIR})
+
+set(SDK_CSRCS
+    "${CONFIG_DIR}/Ifx_Cfg_Ssw.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxAp_cfg.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxDma_cfg.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx/IfxAsclin_PinMap_TC4Dx_BGA436_COM.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Std/IfxAsclin.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApApu.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApProt.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std/IfxClock.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Dma/IfxDma_Dma.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Std/IfxDma.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std/IfxPort.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std/IfxSrc.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmmRst.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smu/Std/IfxSmu.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Vmt/Std/IfxVmt.c"
+    "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Wtu/Std/IfxWtu.c"
+    "${ILLD_DIR}/Libraries/Infra/Platform/Compilers/CompilerTasking.c"
+    "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c"
+    "${ILLD_DIR}/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Tc0.c")
+
+target_sources(nuttx PRIVATE ${SDK_CSRCS})
+
+if(NOT CONFIG_TRICORE_TOOLCHAIN_TASKING)
+  target_compile_options(nuttx PRIVATE -Wno-undef -Wno-strict-prototypes
+                                       -Wno-shadow)
+  target_compile_options(nuttx PRIVATE -fstrict-volatile-bitfields)
+  target_compile_options(nuttx PRIVATE -Wno-unused-parameter
+                                       -Wno-unused-but-set-parameter)
+  target_compile_options(nuttx PRIVATE -Wno-implicit-fallthrough)
+endif()
+
+target_compile_definitions(
+  arch PRIVATE -DSRC_GPSR00=SRC_GPSR0SR0 -DSRC_CPU_CPU0_SB=SRC_CPU0SB
+               -DMODULE_STM0=MODULE_CPU0 -DSRC_STM0SR0=SRC_STMCPU0_SR2)
@@ -0,0 +1,18 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "TC4XX Configuration Options"
+
+menu "TC4XX Peripheral Support"
+
+# These are the peripheral selections proper
+
+config TC4XX_UART0
+	bool "TC4XX UART0"
+	default y
+	select UART0_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+endmenu
@@ -0,0 +1,180 @@
+############################################################################
+# arch/tricore/src/tc4xx/Make.defs
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+CHIP_CSRCS += tc4xx_timerisr.c
+CHIP_CSRCS += tc4xx_serial.c
+
+VPATH += tc4xx
+
+ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y)
+
+tc4xx_libc$(OBJEXT): tc4xx_libc.c
+	$(call COMPILE, $<, $@)
+
+libc_fpu$(LIBEXT): tc4xx_libc$(OBJEXT)
+	$(call ARCHIVE, $@, $<)
+
+EXTRA_LIBS += libc_fpu$(LIBEXT)
+
+else
+
+tc4xx_dummy$(OBJEXT): tc4xx_dummy.c
+	$(call COMPILE, $<, $@)
+
+libos$(LIBEXT): tc4xx_dummy$(OBJEXT)
+	$(call ARCHIVE, $@, $<)
+
+EXTRA_LIBS += libos$(LIBEXT)
+
+endif
+
+ILLD_UNPACK = illd/tc4xx
+ILLD_TARBALL = $(ILLD_UNPACK)/illd.tar.gz
+ILLD_UNPACK_NAME = illd_release_tc4x-main
+ILLD_SRC = $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)/src/Libraries
+ILLD_URL = https://github.com/Infineon/illd_release_tc4x/archive/refs/heads
+
+$(ILLD_TARBALL):
+	$(call DOWNLOAD,$(ILLD_URL),main.tar.gz,$(ILLD_TARBALL))
+
+$(ILLD_UNPACK)/.illd_unpack: $(ILLD_TARBALL)
+	$(Q) echo "Unpacking: ILLD"
+	$(Q) tar xzf $(ILLD_TARBALL) -C $(ILLD_UNPACK)
+	$(Q) mkdir -p $(ILLD_UNPACK)/Libraries/src/Libraries
+	$(Q) mv $(ILLD_SRC)/* $(ILLD_UNPACK)/Libraries/src/Libraries/
+	$(Q) rm -rf $(ILLD_UNPACK)/$(ILLD_UNPACK_NAME)
+	$(Q) touch $(ILLD_UNPACK)/.illd_unpack
+
+ifeq ($(wildcard $(ILLD_UNPACK)/.git),)
+context:: $(ILLD_UNPACK)/.illd_unpack
+
+distclean::
+	$(call DELFILE, $(ILLD_UNPACK)/.illd_unpack)
+	$(call DELFILE, $(ILLD_TARBALL))
+	$(call DELDIR, $(ILLD_UNPACK)/Libraries/src/Libraries)
+endif
+
+CONFIG_DIR = $(ILLD_UNPACK)/Configurations
+ILLD_DIR = $(ILLD_UNPACK)/Libraries/src
+PATCHES_DIR = $(ILLD_UNPACK)/patches
+
+PATCH_FILES = $(wildcard $(CURDIR)/$(PATCHES_DIR)/*.patch)
+
+apply_change_patches:
+	@if [ -n "$(PATCH_FILES)" ]; then \
+		for p in $(PATCH_FILES); do \
+			if git -C "$(CURDIR)" apply --reverse --check "$$p" >/dev/null 2>&1; then \
+				echo "-- Patch $$p already applied, skipping."; \
+			else \
+				if git -C "$(CURDIR)" apply --whitespace=nowarn "$$p" >/dev/null 2>&1; then \
+					echo "-- Successfully applied patch $$p."; \
+				else \
+					echo "-- Failed to apply patch $$p!"; \
+					exit 1; \
+				fi; \
+			fi; \
+		done; \
+	fi
+
+context:: apply_change_patches
+
+SDK_INCDIR += ${CONFIG_DIR}
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/ArcEV
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Asc
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Lin
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Atom
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Egtm/Tom
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Crc
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Fce/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Scr
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_PinMap
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_PinMap/TC4Dx
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Can/Can
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Can/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Flash/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/I2c/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Pms/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Scu/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smu/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Src/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Timer
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Vmt/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Wtu/Std
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Sfr/TC4Dx
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Service/CpuGeneric
+SDK_INCDIR += $(ILLD_DIR)/Libraries/Infra/Platform/Compilers
+
+SDK_CSRCS += $(CONFIG_DIR)/Ifx_Cfg_Ssw.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxAp_cfg.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_Impl/IfxDma_cfg.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/_PinMap/TC4Dx/IfxAsclin_PinMap_TC4Dx_BGA436_COM.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Asclin/Std/IfxAsclin.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApApu.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Ap/Std/IfxApProt.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Clock/Std/IfxClock.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Dma/IfxDma_Dma.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Dma/Std/IfxDma.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Port/Std/IfxPort.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std/IfxSrc.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmmRst.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smu/Std/IfxSmu.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Vmt/Std/IfxVmt.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Wtu/Std/IfxWtu.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Platform/Compilers/CompilerTasking.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Infra.c
+SDK_CSRCS += $(ILLD_DIR)/Libraries/Infra/Ssw/TC4xx/Tricore/Ifx_Ssw_Tc0.c
+
+CFLAGS += $(addprefix ${INCDIR_PREFIX},$(SDK_INCDIR))
+CFLAGS += -DSRC_CPU_CPU0_SB=SRC_CPU0SB
+CFLAGS += -DSRC_GPSR00=SRC_GPSR0SR0
+CFLAGS += -DMODULE_STM0=MODULE_CPU0
+CFLAGS += -DSRC_STM0SR0=SRC_STMCPU0_SR2
+
+VPATH += $(dir $(SDK_CSRCS))
+
+HEAD_CSRC += $(notdir $(SDK_CSRCS))
+
+LIBPATHS += $(CURDIR)
@@ -0,0 +1,39 @@
+############################################################################
+# arch/tricore/src/tc4xx/Toolchain.defs
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+ifeq ($(CONFIG_ARCH_CHIP_TC4XX),y)
+  ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y)
+    ARCHCPUFLAGS += --misrac-version=2004 --user-mode=hypervisor
+    ARCHCPUFLAGS += --default-near-size=0
+    LDFLAGS      += -Ctc4dx
+  else
+    ARCHCPUFLAGS += -mcpu=tc4DAx
+    ARCHCPUFLAGS += -mtc18
+endif
+
+  ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/iLLD/TC4xx/Tricore/Cpu/Std
+  ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Platform
+  ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Libraries/src/Libraries/Infra/Platform/Compilers
+  ARCHINCLUDES += ${INCDIR_PREFIX}$(TOPDIR)/arch/tricore/src/illd/tc4xx/Configurations
+endif
+
+include $(TOPDIR)/arch/tricore/src/common/Toolchain.defs
@@ -0,0 +1,29 @@
+/****************************************************************************
+ * arch/tricore/src/tc4xx/tc4xx_dummy.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
@@ -0,0 +1,86 @@
+/****************************************************************************
+ * arch/tricore/src/tc4xx/tc4xx_libc.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/* TODO:
+ * The data copy from flash to ram reuses the implementation in tricore sdk.
+ * The next update will reimplement _c_init() to abandon the copy code.
+ *
+ * Usage: ltc [options] files
+ * -i --user-provided-initialization-code
+ *
+ *         the user provides his own initialization
+ *         routine, do not emit the copytable
+ *
+ * void _c_init(void)
+ * {
+ * }
+ */
+
+/* The implementation of libc is introduced by default in the Tricore
+ * toolchain, in nuttx we made a fake libc_fpu.a library to bypass
+ * this issue, but the linker will still generate markup code,
+ * add a few definitions to fool the linker.
+ */
+
+void __printf_float(void)
+{
+}
+
+void __printf_int(void)
+{
+}
+
+void __printf_llong(void)
+{
+}
+
+void _main(void)
+{
+}
+
+void _doexit(void)
+{
+}
+
+/* BUG, Workaround for tasking compiler:
+ *
+ * ltc E106: unresolved external: regulator_gpio_init -
+ *                                (drivers_initialize.o)
+ * ltc F019: unrecoverable error: fatal link error
+ *
+ */
+
+int regulator_gpio_init(void *iodev, void *desc)
+{
+  return 0;
+}
@@ -0,0 +1,61 @@
+/****************************************************************************
+ * arch/tricore/src/tc4xx/tc4xx_timerisr.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/irq.h>
+#include <nuttx/kmalloc.h>
+
+#include <nuttx/timers/oneshot.h>
+#include <nuttx/timers/arch_alarm.h>
+
+#include "tricore_internal.h"
+
+#include "IfxStm.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+  struct oneshot_lowerhalf_s *lower;
+
+  lower = tricore_systimer_initialize(&MODULE_CPU0,
+                                      TRICORE_SRC2IRQ(&SRC_STMCPU0_SR2),
+                                      SCU_FREQUENCY);
+
+  DEBUGASSERT(lower != NULL);
+
+  up_alarm_set_lowerhalf(lower);
+}
@@ -2409,6 +2409,13 @@ config ARCH_BOARD_A2G_TC397_5V_TFT
 		This options selects support for NuttX on the Infineon's AURIX board
 		board featuring the TC397 6Quad CPU.

+config ARCH_BOARD_TRIBOARD_TC4X9_COM
+	bool "Infineon's AURIX TC4DA board: TRIBOARD_TC4X9_COM"
+	depends on ARCH_CHIP_TC4DA
+	---help---
+		This options selects support for NuttX on the Infineon's AURIX board
+		board featuring the TC4DA 6Quad CPU.
+
 config ARCH_BOARD_QEMU_ARMV7A
 	bool "Qemu ARMv7a CPUs board"
 	depends on ARCH_CHIP_QEMU_ARM
@@ -3802,6 +3809,7 @@ config ARCH_BOARD
 	default "starpro64"                    if ARCH_BOARD_EIC7700X_STARPRO64
 	default "sabre-6quad"                  if ARCH_BOARD_SABRE_6QUAD
 	default "a2g-tc397-5v-tft"             if ARCH_BOARD_A2G_TC397_5V_TFT
+	default "triboard_tc4x9_com"           if ARCH_BOARD_TRIBOARD_TC4X9_COM
 	default "qemu-armv7a"                  if ARCH_BOARD_QEMU_ARMV7A
 	default "qemu-armv7r"                  if ARCH_BOARD_QEMU_ARMV7R
 	default "qemu-armv8a"                  if ARCH_BOARD_QEMU_ARMV8A
@@ -33,6 +33,310 @@
 * Pre-processor Definitions
 ****************************************************************************/

+#define BANKA_CORE0_PFLASH_KERNEL_START 0x80000000
+#define BANKA_CORE0_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE0_PFLASH_USER_START 0x80180000
+#define BANKA_CORE0_PFLASH_USER_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE1_PFLASH_KERNEL_START 0x80300000
+#define BANKA_CORE1_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE1_PFLASH_USER_START 0x80480000
+#define BANKA_CORE1_PFLASH_USER_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE2_PFLASH_KERNEL_START 0x80600000
+#define BANKA_CORE2_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE2_PFLASH_USER_START 0x80780000
+#define BANKA_CORE2_PFLASH_USER_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE3_PFLASH_KERNEL_START 0x80900000
+#define BANKA_CORE3_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE3_PFLASH_USER_START 0x80A80000
+#define BANKA_CORE3_PFLASH_USER_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE4_PFLASH_KERNEL_START 0x80C00000
+#define BANKA_CORE4_PFLASH_KERNEL_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE4_PFLASH_USER_START 0x80D80000
+#define BANKA_CORE4_PFLASH_USER_SIZE 0x180000 /* 1536KB */
+#define BANKA_CORE5_PFLASH_KERNEL_START 0x80F00000
+#define BANKA_CORE5_PFLASH_KERNEL_SIZE 0x80000 /* 512KB */
+#define BANKA_CORE5_PFLASH_USER_START 0x80F80000
+#define BANKA_CORE5_PFLASH_USER_SIZE 0x80000 /* 512KB */
+#define CORE0_STACK_KERNEL_START 0x70000000
+#define CORE0_STACK_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE0_STACK_USER_START 0x70008000
+#define CORE0_STACK_USER_SIZE 0x8000 /* 32KB */
+#define CORE0_DSPR_KERNEL_START 0x70010000
+#define CORE0_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */
+#define CORE0_DSPR_USER_START 0x7003C000
+#define CORE0_DSPR_USER_SIZE 0x0 /* 0KB */
+#define CORE0_PSPR_KERNEL_START 0x70100000
+#define CORE0_PSPR_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE0_PSPR_USER_START 0x70108000
+#define CORE0_PSPR_USER_SIZE 0x8000 /* 32KB */
+#define CORE0_DLMU_KERNEL_START 0x90000000
+#define CORE0_DLMU_KERNEL_SIZE 0x0 /* 0KB */
+#define CORE0_DLMU_USER_START 0x90000000
+#define CORE0_DLMU_USER_SIZE 0x10000 /* 64KB */
+#define CORE1_STACK_KERNEL_START 0x60000000
+#define CORE1_STACK_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE1_STACK_USER_START 0x60008000
+#define CORE1_STACK_USER_SIZE 0x8000 /* 32KB */
+#define CORE1_DSPR_KERNEL_START 0x60010000
+#define CORE1_DSPR_KERNEL_SIZE 0x2C000 /* 176KB */
+#define CORE1_DSPR_USER_START 0x6003C000
+#define CORE1_DSPR_USER_SIZE 0x0 /* 0KB */
+#define CORE1_PSPR_KERNEL_START 0x60100000
+#define CORE1_PSPR_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE1_PSPR_USER_START 0x60108000
+#define CORE1_PSPR_USER_SIZE 0x8000 /* 32KB */
+#define CORE1_DLMU_KERNEL_START 0x90010000
+#define CORE1_DLMU_KERNEL_SIZE 0x0 /* 0KB */
+#define CORE1_DLMU_USER_START 0x90010000
+#define CORE1_DLMU_USER_SIZE 0x10000 /* 64KB */
+#define CORE2_STACK_KERNEL_START 0x50000000
+#define CORE2_STACK_KERNEL_SIZE 0x6000 /* 24KB */
+#define CORE2_STACK_USER_START 0x50006000
+#define CORE2_STACK_USER_SIZE 0x5000 /* 20KB */
+#define CORE2_DSPR_KERNEL_START 0x5000B000
+#define CORE2_DSPR_KERNEL_SIZE 0xD000 /* 52KB */
+#define CORE2_DSPR_USER_START 0x50018000
+#define CORE2_DSPR_USER_SIZE 0x0 /* 0KB */
+#define CORE2_PSPR_KERNEL_START 0x50100000
+#define CORE2_PSPR_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE2_PSPR_USER_START 0x50108000
+#define CORE2_PSPR_USER_SIZE 0x8000 /* 32KB */
+#define CORE2_DLMU_KERNEL_START 0x90020000
+#define CORE2_DLMU_KERNEL_SIZE 0x0 /* 0KB */
+#define CORE2_DLMU_USER_START 0x90020000
+#define CORE2_DLMU_USER_SIZE 0x10000 /* 64KB */
+#define CORE3_STACK_KERNEL_START 0x40000000
+#define CORE3_STACK_KERNEL_SIZE 0x6000 /* 24KB */
+#define CORE3_STACK_USER_START 0x40006000
+#define CORE3_STACK_USER_SIZE 0x5000 /* 20KB */
+#define CORE3_DSPR_KERNEL_START 0x4000B000
+#define CORE3_DSPR_KERNEL_SIZE 0xD000 /* 52KB */
+#define CORE3_DSPR_USER_START 0x40018000
+#define CORE3_DSPR_USER_SIZE 0x0 /* 0KB */
+#define CORE3_PSPR_KERNEL_START 0x40100000
+#define CORE3_PSPR_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE3_PSPR_USER_START 0x40108000
+#define CORE3_PSPR_USER_SIZE 0x8000 /* 32KB */
+#define CORE3_DLMU_KERNEL_START 0x90030000
+#define CORE3_DLMU_KERNEL_SIZE 0x0 /* 0KB */
+#define CORE3_DLMU_USER_START 0x90030000
+#define CORE3_DLMU_USER_SIZE 0x10000 /* 64KB */
+#define CORE4_STACK_KERNEL_START 0x30000000
+#define CORE4_STACK_KERNEL_SIZE 0x6000 /* 24KB */
+#define CORE4_STACK_USER_START 0x30006000
+#define CORE4_STACK_USER_SIZE 0x5000 /* 20KB */
+#define CORE4_DSPR_KERNEL_START 0x3000B000
+#define CORE4_DSPR_KERNEL_SIZE 0xD000 /* 52KB */
+#define CORE4_DSPR_USER_START 0x30018000
+#define CORE4_DSPR_USER_SIZE 0x0 /* 0KB */
+#define CORE4_PSPR_KERNEL_START 0x30100000
+#define CORE4_PSPR_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE4_PSPR_USER_START 0x30108000
+#define CORE4_PSPR_USER_SIZE 0x8000 /* 32KB */
+#define CORE4_DLMU_KERNEL_START 0x90100000
+#define CORE4_DLMU_KERNEL_SIZE 0x0 /* 0KB */
+#define CORE4_DLMU_USER_START 0x90100000
+#define CORE4_DLMU_USER_SIZE 0x10000 /* 64KB */
+#define CORE5_STACK_KERNEL_START 0x10000000
+#define CORE5_STACK_KERNEL_SIZE 0x6000 /* 24KB */
+#define CORE5_STACK_USER_START 0x10006000
+#define CORE5_STACK_USER_SIZE 0x5000 /* 20KB */
+#define CORE5_DSPR_KERNEL_START 0x1000B000
+#define CORE5_DSPR_KERNEL_SIZE 0xD000 /* 52KB */
+#define CORE5_DSPR_USER_START 0x10018000
+#define CORE5_DSPR_USER_SIZE 0x0 /* 0KB */
+#define CORE5_PSPR_KERNEL_START 0x10100000
+#define CORE5_PSPR_KERNEL_SIZE 0x8000 /* 32KB */
+#define CORE5_PSPR_USER_START 0x10108000
+#define CORE5_PSPR_USER_SIZE 0x8000 /* 32KB */
+#define CORE5_DLMU_KERNEL_START 0x90110000
+#define CORE5_DLMU_KERNEL_SIZE 0x0 /* 0KB */
+#define CORE5_DLMU_USER_START 0x90110000
+#define CORE5_DLMU_USER_SIZE 0x10000 /* 64KB */
+#define LMU0_UNUSED_START 0xB0040000
+#define LMU0_UNUSED_SIZE 0x40000 /* 256KB */
+#define LMU1_UNUSED_START 0xB0080000
+#define LMU1_UNUSED_SIZE 0x40000 /* 256KB */
+#define LMU2_UNUSED_START 0xB00C0000
+#define LMU2_UNUSED_SIZE 0x40000 /* 256KB */
+#define DFLASH0_NVM_START 0xAF000000
+#define DFLASH0_NVM_SIZE 0x40000 /* 256KB */
+#define DFLASH0_MANUFACTURY_START 0xAF040000
+#define DFLASH0_MANUFACTURY_SIZE 0x2800 /* 10K */
+#define DFLASH0_BSWLOG_START 0xAF042800
+#define DFLASH0_BSWLOG_SIZE 0x10000 /* 64K */
+#define DFLASH0_TRAPINFO_START 0xAF052800
+#define DFLASH0_TRAPINFO_SIZE 0x4000 /* 16K */
+#define DFLASH0_DFXLOG_START 0xAF056800
+#define DFLASH0_DFXLOG_SIZE 0x4000 /* 16K */
+#define DFLASH0_UNUSED_START 0xAF05A800
+#define DFLASH0_UNUSED_SIZE 0xA5800 /* 662K */
+#define UCB0_START 0xAF400000
+#define UCB0_SIZE 0x6000 /* 24K */
+#define PERIPHERALS_START 0xF0000000
+#define PERIPHERALS_SIZE 0xB720000 /* 187520K */
+#define CORE0_DCACHE_START 0x7003C000
+#define CORE0_DCACHE_SIZE 0x4000 /* 16K */
+#define CORE1_DCACHE_START 0x6003C000
+#define CORE1_DCACHE_SIZE 0x4000 /* 16K */
+#define CORE2_DCACHE_START 0x50018000
+#define CORE2_DCACHE_SIZE 0x4000 /* 16K */
+#define CORE3_DCACHE_START 0x40018000
+#define CORE3_DCACHE_SIZE 0x4000 /* 16K */
+#define CORE4_DCACHE_START 0x30018000
+#define CORE4_DCACHE_SIZE 0x4000 /* 16K */
+#define CORE5_DCACHE_START 0x10018000
+#define CORE5_DCACHE_SIZE 0x4000 /* 16K */
+
+/****************************************************************************
+ * Common macros
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BUILD_FLAT
+
+#  define CORE0_PFLASH_KERNEL_START  BANKA_CORE0_PFLASH_KERNEL_START
+#  define CORE0_PFLASH_KERNEL_SIZE   BANKA_CORE0_PFLASH_KERNEL_SIZE
+#  define CORE1_PFLASH_KERNEL_START  BANKA_CORE1_PFLASH_KERNEL_START
+#  define CORE1_PFLASH_KERNEL_SIZE   BANKA_CORE1_PFLASH_KERNEL_SIZE
+#  define CORE2_PFLASH_KERNEL_START  BANKA_CORE2_PFLASH_KERNEL_START
+#  define CORE2_PFLASH_KERNEL_SIZE   BANKA_CORE2_PFLASH_KERNEL_SIZE
+#  define CORE3_PFLASH_KERNEL_START  BANKA_CORE3_PFLASH_KERNEL_START
+#  define CORE3_PFLASH_KERNEL_SIZE   BANKA_CORE3_PFLASH_KERNEL_SIZE
+#  define CORE4_PFLASH_KERNEL_START  BANKA_CORE4_PFLASH_KERNEL_START
+#  define CORE4_PFLASH_KERNEL_SIZE   BANKA_CORE4_PFLASH_KERNEL_SIZE
+#  define CORE5_PFLASH_KERNEL_START  BANKA_CORE5_PFLASH_KERNEL_START
+#  define CORE5_PFLASH_KERNEL_SIZE   BANKA_CORE5_PFLASH_KERNEL_SIZE
+
+#else
+
+#  define CORE0_PFLASH_KERNEL_START  BANKA_CORE0_PFLASH_KERNEL_START
+#  define CORE0_PFLASH_KERNEL_SIZE   BANKA_CORE0_PFLASH_KERNEL_SIZE
+#  define CORE0_PFLASH_USER_START    BANKA_CORE0_PFLASH_USER_START
+#  define CORE0_PFLASH_USER_SIZE     BANKA_CORE0_PFLASH_USER_SIZE
+
+#  define CORE1_PFLASH_KERNEL_START  BANKA_CORE1_PFLASH_KERNEL_START
+#  define CORE1_PFLASH_KERNEL_SIZE   BANKA_CORE1_PFLASH_KERNEL_SIZE
+#  define CORE1_PFLASH_USER_START    BANKA_CORE1_PFLASH_USER_START
+#  define CORE1_PFLASH_USER_SIZE     BANKA_CORE1_PFLASH_USER_SIZE
+
+#  define CORE2_PFLASH_KERNEL_START  BANKA_CORE2_PFLASH_KERNEL_START
+#  define CORE2_PFLASH_KERNEL_SIZE   BANKA_CORE2_PFLASH_KERNEL_SIZE
+#  define CORE2_PFLASH_USER_START    BANKA_CORE2_PFLASH_USER_START
+#  define CORE2_PFLASH_USER_SIZE     BANKA_CORE2_PFLASH_USER_SIZE
+
+#  define CORE3_PFLASH_KERNEL_START  BANKA_CORE3_PFLASH_KERNEL_START
+#  define CORE3_PFLASH_KERNEL_SIZE   BANKA_CORE3_PFLASH_KERNEL_SIZE
+#  define CORE3_PFLASH_USER_START    BANKA_CORE3_PFLASH_USER_START
+#  define CORE3_PFLASH_USER_SIZE     BANKA_CORE3_PFLASH_USER_SIZE
+
+#  define CORE4_PFLASH_KERNEL_START  BANKA_CORE4_PFLASH_KERNEL_START
+#  define CORE4_PFLASH_KERNEL_SIZE   BANKA_CORE4_PFLASH_KERNEL_SIZE
+#  define CORE4_PFLASH_USER_START    BANKA_CORE4_PFLASH_USER_START
+#  define CORE4_PFLASH_USER_SIZE     BANKA_CORE4_PFLASH_USER_SIZE
+
+#  define CORE5_PFLASH_KERNEL_START  BANKA_CORE5_PFLASH_KERNEL_START
+#  define CORE5_PFLASH_KERNEL_SIZE   BANKA_CORE5_PFLASH_KERNEL_SIZE
+#  define CORE5_PFLASH_USER_START    BANKA_CORE5_PFLASH_USER_START
+#  define CORE5_PFLASH_USER_SIZE     BANKA_CORE5_PFLASH_USER_SIZE
+
+#endif
+
+#define BL_PFLASH_START             BANKA_BL_PFLASH_START
+#define BL_PFLASH_SIZE              BANKA_BL_PFLASH_SIZE
+#define BL_DLMU_START               CORE0_DLMU_KERNEL_START
+#define BL_DLMU_SIZE                CORE0_DLMU_KERNEL_SIZE
+#define BL_DSPR_START               CORE0_DSPR_KERNEL_START
+#define BL_DSPR_SIZE                CORE0_DSPR_KERNEL_SIZE
+#define BL_PSPR_START               CORE0_PSPR_KERNEL_START
+#define BL_PSPR_SIZE                CORE0_PSPR_KERNEL_SIZE
+#define MBF_HASH_START              BANKA_MBF_HASH_START
+#define MBF_HASH_SIZE               BANKA_MBF_HASH_SIZE
+
+#define NC_START(addr)    \
+  ((addr) >= 0x80000000 && (addr) <= 0x9FFFFFFF ? (addr) + 0x20000000 : (addr))
+
+#define AURIX_PERIPHERAL_BASE_ADDR   0xF0000000
+#define AURIX_PERIPHERAL_SIZE        0x0B720000
+
+#define DSPR_LOCAL_START             0xD0000000
+#define PSPR_LOCAL_START             0xC0000000
+
+#define BACKGROUND_START             0x0
+#define BACKGROUND_SIZE              0xFFFFFFFF
+
+#define CORE0_DCACHE_KERNEL_START    0x7003C000
+#define CORE0_DCACHE_KERNEL_SIZE     0x4000
+#define CORE1_DCACHE_KERNEL_START    0x6003C000
+#define CORE1_DCACHE_KERNEL_SIZE     0x4000
+#define CORE2_DCACHE_KERNEL_START    0x50018000
+#define CORE2_DCACHE_KERNEL_SIZE     0x4000
+#define CORE3_DCACHE_KERNEL_START    0x40018000
+#define CORE3_DCACHE_KERNEL_SIZE     0x4000
+#define CORE4_DCACHE_KERNEL_START    0x30018000
+#define CORE4_DCACHE_KERNEL_SIZE     0x4000
+#define CORE5_DCACHE_KERNEL_START    0x10018000
+#define CORE5_DCACHE_KERNEL_SIZE     0x4000
+
+#define CORE_PFLASH_KERNEL_START(COREID)           CORE##COREID##_PFLASH_KERNEL_START
+#define CORE_PFLASH_KERNEL_SIZE(COREID)            CORE##COREID##_PFLASH_KERNEL_SIZE
+#define GENERATE_CORE_PFLASH_KERNEL_START(COREID)  CORE_PFLASH_KERNEL_START(COREID)
+#define GENERATE_CORE_PFLASH_KERNEL_SIZE(COREID)   CORE_PFLASH_KERNEL_SIZE(COREID)
+
+#define CORE_STACK_KERNEL_START(COREID)            CORE##COREID##_STACK_KERNEL_START
+#define CORE_STACK_KERNEL_SIZE(COREID)             CORE##COREID##_STACK_KERNEL_SIZE
+#define GENERATE_CORE_STACK_KERNEL_START(COREID)   CORE_STACK_KERNEL_START(COREID)
+#define GENERATE_CORE_STACK_KERNEL_SIZE(COREID)    CORE_STACK_KERNEL_SIZE(COREID)
+
+#define CORE_DSPR_KERNEL_START(COREID)             CORE##COREID##_DSPR_KERNEL_START
+#define CORE_DSPR_KERNEL_SIZE(COREID)              CORE##COREID##_DSPR_KERNEL_SIZE
+#define GENERATE_CORE_DSPR_KERNEL_START(COREID)    CORE_DSPR_KERNEL_START(COREID)
+#define GENERATE_CORE_DSPR_KERNEL_SIZE(COREID)     CORE_DSPR_KERNEL_SIZE(COREID)
+
+#define CORE_PSPR_KERNEL_START(COREID)             CORE##COREID##_PSPR_KERNEL_START
+#define CORE_PSPR_KERNEL_SIZE(COREID)              CORE##COREID##_PSPR_KERNEL_SIZE
+#define GENERATE_CORE_PSPR_KERNEL_START(COREID)    CORE_PSPR_KERNEL_START(COREID)
+#define GENERATE_CORE_PSPR_KERNEL_SIZE(COREID)     CORE_PSPR_KERNEL_SIZE(COREID)
+
+#define CORE_DLMU_KERNEL_START(COREID)             CORE##COREID##_DLMU_KERNEL_START
+#define CORE_DLMU_KERNEL_SIZE(COREID)              CORE##COREID##_DLMU_KERNEL_SIZE
+#define GENERATE_CORE_DLMU_KERNEL_START(COREID)    CORE_DLMU_KERNEL_START(COREID)
+#define GENERATE_CORE_DLMU_KERNEL_SIZE(COREID)     CORE_DLMU_KERNEL_SIZE(COREID)
+
+#define CORE_DCACHE_KERNEL_START(COREID)           CORE##COREID##_DCACHE_KERNEL_START
+#define CORE_DCACHE_KERNEL_SIZE(COREID)            CORE##COREID##_DCACHE_KERNEL_SIZE
+#define GENERATE_CORE_DCACHE_KERNEL_START(COREID)  CORE_DCACHE_KERNEL_START(COREID)
+#define GENERATE_CORE_DCACHE_KERNEL_SIZE(COREID)   CORE_DCACHE_KERNEL_SIZE(COREID)
+
+#ifndef CONFIG_BUILD_FLAT
+
+#define CORE_PFLASH_USER_START(COREID)             CORE##COREID##_PFLASH_USER_START
+#define CORE_PFLASH_USER_SIZE(COREID)              CORE##COREID##_PFLASH_USER_SIZE
+#define GENERATE_CORE_PFLASH_USER_START(COREID)    CORE_PFLASH_USER_START(COREID)
+#define GENERATE_CORE_PFLASH_USER_SIZE(COREID)     CORE_PFLASH_USER_SIZE(COREID)
+
+#define CORE_STACK_USER_START(COREID)              CORE##COREID##_STACK_USER_START
+#define CORE_STACK_USER_SIZE(COREID)               CORE##COREID##_STACK_USER_SIZE
+#define GENERATE_CORE_STACK_USER_START(COREID)     CORE_STACK_USER_START(COREID)
+#define GENERATE_CORE_STACK_USER_SIZE(COREID)      CORE_STACK_USER_SIZE(COREID)
+
+#define CORE_DSPR_USER_START(COREID)               CORE##COREID##_DSPR_USER_START
+#define CORE_DSPR_USER_SIZE(COREID)                CORE##COREID##_DSPR_USER_SIZE
+#define GENERATE_CORE_DSPR_USER_START(COREID)      CORE_DSPR_USER_START(COREID)
+#define GENERATE_CORE_DSPR_USER_SIZE(COREID)       CORE_DSPR_USER_SIZE(COREID)
+
+#define CORE_PSPR_USER_START(COREID)               CORE##COREID##_PSPR_USER_START
+#define CORE_PSPR_USER_SIZE(COREID)                CORE##COREID##_PSPR_USER_SIZE
+#define GENERATE_CORE_PSPR_USER_START(COREID)      CORE_PSPR_USER_START(COREID)
+#define GENERATE_CORE_PSPR_USER_SIZE(COREID)       CORE_PSPR_USER_SIZE(COREID)
+
+#define CORE_DLMU_USER_START(COREID)               CORE##COREID##_DLMU_USER_START
+#define CORE_DLMU_USER_SIZE(COREID)                CORE##COREID##_DLMU_USER_SIZE
+#define GENERATE_CORE_DLMU_USER_START(COREID)      CORE_DLMU_USER_START(COREID)
+#define GENERATE_CORE_DLMU_USER_SIZE(COREID)       CORE_DLMU_USER_SIZE(COREID)
+
+#endif
+
 /****************************************************************************
 * Public Data
 ****************************************************************************/
@@ -58,4 +362,5 @@ extern "C"
 #endif

 #endif /* __ASSEMBLY__ */
+
 #endif /* __BOARDS_TRICORE_TC397_A2G_TC397_5V_TFT_INCLUDE_BOARD_MEMORYMAP_H */
@@ -0,0 +1,264 @@
+/****************************************************************************
+ * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Gnuc_Tricore_Tc.lsl.user
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include "arch/board/board_memorymap.h"
+
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT("elf32-tricore")
+OUTPUT_ARCH("tricore")
+
+LCF_PFLASH_USER_START = GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID);
+LCF_PFLASH_USER_SIZE  = GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID);
+LCF_DLMU_USER_START   = GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID);
+LCF_DLMU_USER_SIZE    = GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID);
+LCF_USTACK_START      = GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID);
+LCF_USTACK_SIZE       = GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID);
+
+MEMORY
+{
+    upfls (rx!p): org = LCF_PFLASH_USER_START, len = LCF_PFLASH_USER_SIZE
+    upfls_nc (rx!p): org = NC_START(LCF_PFLASH_USER_START), len = LCF_PFLASH_USER_SIZE
+
+    cpu_udlmu (w!xp): org = LCF_DLMU_USER_START, len = LCF_DLMU_USER_SIZE
+    cpu_udlmu_nc (w!xp): org = NC_START(LCF_DLMU_USER_START), len = LCF_DLMU_USER_SIZE
+
+    ustack (w!xp): org = LCF_USTACK_START, len = LCF_USTACK_SIZE
+}
+
+/* map cached and non cached addresses */
+REGION_MIRROR("upfls", "upfls_nc")
+REGION_MIRROR("cpu_udlmu", "cpu_udlmu_nc")
+
+/*Un comment one of the below statement groups to enable CpuX DMI RAM to hold global variables*/
+
+/*Code Sections, selectable by toolchain*/
+CORE_ID = GLOBAL;
+SECTIONS
+{
+    .userspace : ALIGN(64)
+    {
+        _suserspace = ABSOLUTE(.);
+        KEEP(*(.userspace))
+        . = ALIGN(64); /* userspace align to 64 to keep the address continuous for MBF */
+        _euserspace = ABSOLUTE(.);
+    } > upfls
+
+    CORE_SEC(.text) : FLAGS(axl)
+    {
+        _stext = ABSOLUTE(.);
+        *(.text)
+        *(.text.*)
+        *(.zrodata)
+        *(.zrodata.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.gnu.linkonce.r.*)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.t.*)
+        *(.gnu.warning)        /* .gnu.warning sections are handled specially by elf32.em. */
+        . = ALIGN(4);
+        _etext = ABSOLUTE(.);
+    } > upfls
+
+    /*
+     * Code executed before calling main extra section for C++ constructor init
+     *  -------------------------End-----------------------------------------
+     */
+
+    /*
+     * C++ exception handling tables.  NOTE: gcc emits .eh_frame
+     * sections when compiling C sources with debugging enabled (-g).
+     * If you can be sure that your final application consists
+     * exclusively of C objects (i.e., no C++ objects), you may use
+     * the -R option of the "strip" and "objcopy" utilities to remove
+     * the .eh_frame section from the executable.
+     */
+    .eh_frame_hdr : ALIGN(8)
+    {
+        KEEP (*(.eh_frame_hdr))
+        . = ALIGN(8);
+    } > upfls
+
+    .eh_frame : ALIGN(8)
+    {
+        __EH_FRAME_BEGIN__ = . ;
+        KEEP (*(.eh_frame))
+        __EH_FRAME_END__ = . ;
+        . = ALIGN(8);
+    } > upfls
+
+    /*
+     * Constructors and destructors.
+     */
+    .ctors : FLAGS(ar)
+    {
+        _sinit = ABSOLUTE(.);
+        /*
+         * Code executed before calling main extra section for C++ constructor init
+         *  -------------------------Start-----------------------------------------
+         */
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
+        /*
+         * Code executed before calling main extra section for C++ constructor init
+         *  -------------------------End-----------------------------------------
+         */
+        _einit = ABSOLUTE(.);
+        . = ALIGN(8);
+    } > upfls
+    .dtors : FLAGS(ar)
+    {
+        __DTOR_LIST__ = . ;
+        LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2);
+        /*
+         * Code executed before calling main extra section for C++ destructor init
+         *  -------------------------Start-----------------------------------------
+         */
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+        /*
+         * Code executed before calling main extra section for C++ destructor init
+         *  -------------------------End-----------------------------------------
+         */
+        LONG(0) ;
+        __DTOR_END__ = . ;
+        . = ALIGN(8);
+    } > upfls
+
+    _eronly = ABSOLUTE(.);
+
+    /*
+     * DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the
+     * beginning of the section, so we begin them at 0.
+     */
+    /*
+     * DWARF 1
+     */
+    .comment         0 : { *(.comment) }
+    .debug           0 : { *(.debug) }
+    .line            0 : { *(.line) }
+    /*
+     * GNU DWARF 1 extensions
+     */
+    .debug_srcinfo   0 : { *(.debug_srcinfo) }
+    .debug_sfnames   0 : { *(.debug_sfnames) }
+    /*
+     * DWARF 1.1 and DWARF 2
+     */
+    .debug_aranges   0 : { *(.debug_aranges) }
+    .debug_pubnames  0 : { *(.debug_pubnames) }
+    /*
+     * DWARF 2
+     */
+    .debug_info      0 : { *(.debug_info) }
+    .debug_abbrev    0 : { *(.debug_abbrev) }
+    .debug_line      0 : { *(.debug_line) }
+    .debug_frame     0 : { *(.debug_frame) }
+    .debug_str       0 : { *(.debug_str) }
+    .debug_loc       0 : { *(.debug_loc) }
+    .debug_macinfo   0 : { *(.debug_macinfo) }
+    .debug_ranges    0 : { *(.debug_ranges) }
+    /*
+     * SGI/MIPS DWARF 2 extensions
+     */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /*
+     * Optional sections that may only appear when relocating.
+     */
+    /*
+     * Optional sections that may appear regardless of relocating.
+     */
+    .version_info    0 : { *(.version_info) }
+    .boffs           0 : { KEEP (*(.boffs)) }
+}
+
+/*Far Data Sections, selectable by toolchain*/
+CORE_ID = GLOBAL;
+SECTIONS
+{
+    CORE_SEC(.stack) (NOLOAD) : FLAGS(aw)
+    {
+        *(.dtcm_stack)
+        *(.dtcm_stack.*)
+    } > ustack
+
+    CORE_SEC(.data) : FLAGS(awzl)
+    {
+        _sdata = ABSOLUTE(.);
+        *(.data)
+        *(.data.*)
+        *(.zdata)
+        *(.zdata.*)
+        *(.gnu.linkonce.d.*)
+        *(.gnu.linkonce.z.*)
+        . = ALIGN(2);
+        _edata = ABSOLUTE(.);
+    } > cpu_udlmu AT> upfls
+
+    CORE_SEC(.bss) (NOLOAD): FLAGS(awz)
+    {
+        _sbss = ABSOLUTE(.);
+        *(.bss)
+        *(.bss.*)
+        *(.zbss)
+        *(.zbss.*)
+        *(.bbss)
+        *(.bbss.*)
+        *(.gnu.linkonce.zb.*)
+        . = ALIGN(4);
+        _ebss = ABSOLUTE(.);
+    } > cpu_udlmu
+
+    .heap (NOLOAD) : FLAGS(aw)
+    {
+        _sheap = ABSOLUTE(.);
+        _eheap = ABSOLUTE(LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE);
+    } > cpu_udlmu
+
+    _sdata_pflash = LOADADDR(.data);
+}
+
+#if CONFIG_CPU_COREID == 5
+/* This sections is added to reserve last 4 bytes of flash in core5's user
+ * space. This is because the car's diagnostic service will query this area,
+ * and if the area has been erased but not written to, the query will cause
+ * an exception. Since the page size of pflash is 32 bytes, we reserve 32
+ * bytes instead of 4 bytes.
+ */
+
+CORE_ID = GLOBAL;
+SECTIONS
+{
+    .flash_reserve (LCF_PFLASH_USER_START + LCF_PFLASH_USER_SIZE - 32) : {
+        . = ALIGN(32);
+        FILL(0x55);
+        . = . + 28;
+        LONG(0x55555555);
+    } > upfls
+}
+#endif
@@ -0,0 +1,189 @@
+/****************************************************************************
+ * boards/tricore/tc397/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.user
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include "arch/board/board_memorymap.h"
+
+#define LCF_PFLASH_USER_START   GENERATE_CORE_PFLASH_USER_START(CONFIG_CPU_COREID)
+#define LCF_PFLASH_USER_SIZE    GENERATE_CORE_PFLASH_USER_SIZE(CONFIG_CPU_COREID)
+#define LCF_DLMU_USER_START     GENERATE_CORE_DLMU_USER_START(CONFIG_CPU_COREID)
+#define LCF_DLMU_USER_SIZE      GENERATE_CORE_DLMU_USER_SIZE(CONFIG_CPU_COREID)
+#define LCF_USTACK_START        GENERATE_CORE_STACK_USER_START(CONFIG_CPU_COREID)
+#define LCF_USTACK_SIZE         GENERATE_CORE_STACK_USER_SIZE(CONFIG_CPU_COREID)
+
+#define LCF_HEAP_SIZE           4k
+
+#include "tc1v1_6_2.lsl"
+
+// Specify a multi-core processor environment (mpe)
+
+processor mpe
+{
+    derivative = tc39;
+}
+
+derivative tc39
+{
+    core tc
+    {
+        architecture = TC1V1.6.2;
+        space_id_offset = 100;           // add 100 to all space IDs in the architecture definition
+        copytable_space = vtc:linear;    // use the copy table in the virtual core for 'bss' and initialized data sections
+    }
+
+    core vtc
+    {
+        architecture = TC1V1.6.2;
+        import tc;                     // add all address spaces of core tc to core vtc for linking and locating
+    }
+
+    bus sri
+    {
+        mau = 8;
+        width = 32;
+
+        // map shared addresses one-to-one to real cores and virtual cores
+        map (dest=bus:tc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
+        map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
+    }
+
+    memory upfls
+    {
+        mau = 8;
+        size = LCF_PFLASH_USER_SIZE;
+        type = rom;
+        map     cached (dest=bus:sri, dest_offset=LCF_PFLASH_USER_START, size=LCF_PFLASH_USER_SIZE);
+        map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_PFLASH_USER_START), reserved, size=LCF_PFLASH_USER_SIZE);
+    }
+
+    memory cpu_udlmu
+    {
+        mau = 8;
+        size = LCF_DLMU_USER_SIZE;
+        type = ram;
+        map     cached (dest=bus:sri, dest_offset=LCF_DLMU_USER_START, size=LCF_DLMU_USER_SIZE);
+        map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_USER_START), reserved, size=LCF_DLMU_USER_SIZE);
+    }
+
+    memory ustack
+    {
+        mau = 8;
+        size = LCF_USTACK_SIZE;
+        type = ram;
+        map not_cached (dest=bus:sri, dest_offset=LCF_USTACK_START, size=LCF_USTACK_SIZE);  
+    }
+
+    /*Section setup for the copy table*/
+    section_setup :vtc:linear
+    {
+        copytable
+        (
+            align = 4,
+            dest = linear,
+            table
+            {
+                symbol = "_lc_ub_table_tc";
+                space = :tc:linear, :tc:abs24, :tc:abs18;
+            }
+        );
+    }
+
+    section_setup :vtc:linear
+    {
+        heap "uheap" (min_size = LCF_HEAP_SIZE, align = 4);
+    }
+
+    /* user stack section */
+    section_layout :vtc:linear
+    {
+        group ustack(ordered, contiguous, nocopy, run_addr=mem:ustack)
+        {
+            select "(.dtcm_stack|.dtcm_stack.*)";
+        }
+    }
+
+    /*Sections located at absolute fixed address*/
+    section_layout :vtc:linear
+    {
+        group userspace(ordered, run_addr=LCF_PFLASH_USER_START)
+        {
+            select "(.userspace|.userspace.*)";
+        }
+        "_suserspace" = "_lc_gb_userspace";
+        "_euserspace" = "_lc_ge_userspace";
+
+        group text(ordered, run_addr=mem:upfls)
+        {
+            select "(.text|.text.*)";
+            select "(.zrodata|.zrodata.*)";
+            select "(.rodata|.rodata.*)";
+        }
+        "_stext" = "_lc_gb_text";
+        "_etext" = "_lc_ge_text";
+    }
+
+    /* Data & Bss section */
+    section_layout :vtc:linear
+    {
+        group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu/not_cached)
+        {
+            select "(.data.uncached.*)";
+            select "(.bss.uncached.*)";
+        }
+
+        group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_udlmu)
+        {
+            group udata
+            {
+                select "(.data|.data.*)";
+                select "(.zdata|.zdata.*)";
+            }
+            "_sdata" = "_lc_gb_udata";
+            "_edata" = "_lc_ge_udata";
+
+            /* bss section */
+            group ubss
+            {
+                select "(.bss|.bss.*)";
+                select "(.zbss|.zbss.*)";
+                select "(.bbss|.bbss.*)";
+            }
+            "_sbss" = "_lc_gb_ubss";
+            "_ebss" = "_lc_ge_ubss";
+
+            /* heap section */
+            group uheap
+            {
+                heap "uheap" (size = LCF_HEAP_SIZE);
+            }
+            "_sheap" = "_ebss";
+            "_eheap" = LCF_DLMU_USER_START + LCF_DLMU_USER_SIZE;
+        }
+
+        group udata_rom(ordered, contiguous, load_addr=mem:upfls)
+        {
+            select "(.data|.data.*)";
+            select "(.zdata|.zdata.*)";
+        }
+        "_sdata_pflash" = "_lc_gb_udata_rom";
+        #include "symbol_share.ld"
+    }
+}
@@ -25,9 +25,15 @@ include $(TOPDIR)/tools/Config.mk
 include $(TOPDIR)/arch/tricore/src/tc3xx/Toolchain.defs

 ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y)
-  ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_Tasking_Tricore_Tc.lsl
+  TRICORE_TOOLCHAIN := Tasking
 else
-  ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_Gnuc_Tricore_Tc.lsl
+  TRICORE_TOOLCHAIN := Gnuc
+endif
+
+ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.kernel
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+  ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_$(TRICORE_TOOLCHAIN)_Tricore_Tc.lsl.user
 endif

 CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
@@ -24,13 +24,19 @@ set(SRCS tc397_appinit.c tc397_boardinit.c tc397_bringup.c)

 target_sources(board PRIVATE ${SRCS})

-# TODO: make this the default and then allow boards to redefine
 if(CONFIG_TRICORE_TOOLCHAIN_TASKING)
-  set_property(
-    GLOBAL PROPERTY LD_SCRIPT
-                    "${NUTTX_BOARD_DIR}/scripts/Lcf_Tasking_Tricore_Tc.lsl")
+  set(toolchain "Tasking")
 else()
-  set_property(
-    GLOBAL PROPERTY LD_SCRIPT
-                    "${NUTTX_BOARD_DIR}/scripts/Lcf_Gnuc_Tricore_Tc.lsl")
+  set(toolchain "Gnuc")
+endif()
+
+set_property(
+  GLOBAL
+  PROPERTY LD_SCRIPT
+           "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.kernel")
+if(CONFIG_BUILD_PROTECTED)
+  set_property(
+    GLOBAL
+    PROPERTY LD_SCRIPT_USER
+             "${NUTTX_BOARD_DIR}/scripts/Lcf_${toolchain}_Tricore_Tc.lsl.user")
 endif()
@@ -0,0 +1,23 @@
+# ##############################################################################
+# boards/tricore/tc4da/triboard_tc4x9_com/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+add_subdirectory(src)
--- a/Show More
+++ b/Show More