Remove the CONFIG_K210_WITH_QEMU option and associated conditional
code paths. The reasons for removal are:
* Simplifies code path for real hardware by removing QEMU workarounds
* The current QEMU target uses sifive_u machine, which is not designed
for K210 emulation
* For RISC-V QEMU simulation, the qemu-rv (rv-virt) target is a better
choice
* Renode can be used as an alternative for K210 simulation if needed
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
All CI Builds have been failing since 18 hours ago. That's because ASF Infrastructure Team has mandated that we use the Specific Versions of GitHub Actions for Docker, stated below:
- https://github.com/apache/infrastructure-actions/blob/main/actions.yml
- Which generates: https://github.com/apache/infrastructure-actions/blob/main/approved_patterns.yml
```yaml
docker/build-push-action:
10e90e3645eae34f1e60eeb005ba3a3d33f178e8:
tag: v6.19.2
docker/login-action:
c94ce9fb468520275223c153574b00df6fe4bcc9:
tag: v3.7.0
docker/metadata-action:
c299e40c65443455700f0fdfc63efafe5b349051:
tag: v5.10.0
docker/setup-buildx-action:
8d2750c68a42422c14e847fe6c8ac0403b4cbd6f:
tag: v3.12.0
```
This PR reverts our GitHub Actions for Docker to the versions stated above.
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
This patch fixes [BUG #18558] for stm32 by aligning _ebss symbol(used
as base of idle stack) in linker files to 8-byte boundary to conform
to AAPCS-32.
Signed-off-by: Peter Barada <peter.barada@gmail.com>
The WiFi driver refactor (662c1e0bbb) renamed the Kconfig symbol
from CONFIG_ESPRESSIF_WLAN to CONFIG_ESPRESSIF_WIFI, but several
ESP32-S3 board bringup files were not updated. This caused
board_wlan_init() to be compiled out, so the wlan0 interface
never appeared.
Update the preprocessor guards in all affected boards:
- esp32s3-box
- esp32s3-eye
- esp32s3-korvo-2
- esp32s3-lcd-ev
- lckfb-szpi-esp32s3
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
If power down mode is set, trying to read ID ends in an infinite loop
because w25_waitwritecomplete never returns as status register never
signalizes write complete. Therefore ensure the device is not in a
power down mode before trying to read from it.
This can be an issue if the board is trying to check for more NOR
memories on one SPI bus and one chip select. For example GD25 driver
returns the memory to power down state after read id is finished,
therefore board initialization is stuck in an infinite loop if it first
checks for GD25 and then fallbacks to W25.
The commit fixes the possible issue by ensuring W25 is brought back
to normal operation mode before trying to obtain the manufacturer ID.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Removes optional keyword causing selection to fail on the
automatic bringup of SPI flash device.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Fix duplicate watchdog prompts in Kconfig by using unique WDOG0, WDOG1,
WDOG2 names instead of generic 'watchdog' label. This matches the UART
peripheral naming convention in the same file and makes it clear which
watchdog is being configured in menuconfig.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This bl602evb:elf configuration has caused job risc-v-01 to fail on several occasions.
riscv-none-elf-ld: cannot find /github/workspace/sources/nuttx/arch/risc-v/src/crt0.o: No such file or directory
https://github.com/apache/nuttx/pull/17792
Added -bl602evb:elf to the risc-v-01.dat file to skip the build.
Signed-off-by: simbit18 <simbit18@gmail.com>
This commit adds the possibility to check for expander errors when
reading the data. This is optional if glerr_check or interr_check
fields in configuration are not zero.
If not zero, read operation also reads ISO1I813T_GLERR and
ISO1I813T_INTERR register and returns error if there is some error.
The user can control which errors he wants to check with
glerr_check and interr_check masks.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Remove CONFIG_FTL_WRITEBUFFER, CONFIG_DRVR_WRITEBUFFER,
CONFIG_DRVR_READAHEAD, and CONFIG_DRVR_INVALIDATE from the
nxboot-loader and mcuboot-loader defconfigs.
FTL write buffering delays physical flash commits, which can cause
data loss on power failure during OTA updates. Bootloaders require
immediate write durability and should not use buffered writes.
Signed-off-by: Neil Berkman <neil@xuku.com>
ftl_write() unconditionally routes writes through rwb_write() when
FTL_HAVE_RWBUFFER is defined, ignoring the O_DIRECT flag stored in
dev->oflags. This means callers that open with O_DIRECT expecting
unbuffered writes still get their data buffered in RAM.
The O_DIRECT flag is already checked in ftl_flush() to select
between direct and read-modify-write paths, but the buffering
decision in ftl_write() never consults it.
Add O_DIRECT checks in both ftl_write() and ftl_read() to bypass
rwbuffer entirely when the flag is set. For writes, go directly to
ftl_flush() and normalize the return value to match the block
driver convention (nsectors on success). For reads, go directly to
ftl_reload(), bypassing any read-ahead cache.
This gives O_DIRECT callers a complete bypass of the rwbuffer layer
for both reads and writes, matching the documented contract.
Signed-off-by: Neil Berkman <neil@xuku.com>
The ESP32*_SPIFLASH_AUTO_BRINGUP option allows disabling automatic bringup.
This causes /dev/mtdblock0 to show up instead of always mounting a file system.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The ESPRESSIF_SPIFLASH_AUTO_BRINGUP option allows disabling automatic bringup.
This causes /dev/mtdblock0 to show up instead of always mounting a file system.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Add WDT driver for K210 with support for both WDT0 and WDT1 peripherals.
This includes:
- Add k210_wdt.c and k210_wdt.h driver files with interrupt-based
watchdog timer functionality
- Add hardware register definitions in k210_wdt.h
- Add K210_WDT, K210_WDT0, K210_WDT1 Kconfig options
- Add memory map definitions for WDT0 (0x50400000) and WDT1 (0x50410000)
- Reorder WDT IRQ definitions (IRQ 21, 22) before UART0 (IRQ 33) in irq.h
- Add WDT initialization in board bringup for maix-bit
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This update enhances the SDIO documentation by including a reference to the card initialization flowchart in the MMC/SD physical layer specification. This addition aims to provide implementers with a clearer understanding of the complete card initialization and command sequence.
Signed-off-by: Arjav Patel <arjav1528@gmail.com>
This update clarifies the call-flow for the SDIO lower-half driver implementation by providing a simplified example of the interaction between the MMCSD upper-half and the lower-half. It details the command sequence for handling R2 responses, improving the understanding of the expected behavior during card identification and initialization.
Signed-off-by: Arjav Patel <arjav1528@gmail.com>
This update adds a reference to the SDIO Driver Documentation for implementers of SDIO lower-half drivers, emphasizing the importance of understanding R2/CSD response handling and the correct implementation of the lower-half interface.
Signed-off-by: Arjav Patel <arjav1528@gmail.com>
This update expands the documentation for implementing an SDIO lower-half driver, detailing the required interface, call-flow, and handling of the R2 response format. It emphasizes the importance of byte-shifting when the CRC is stripped by the hardware, providing reference implementations for clarity.
Signed-off-by: Arjav Patel <arjav1528@gmail.com>
This update adds comprehensive documentation regarding the 136-bit response format for SDIO, including the structure of the response, CRC handling, and necessary byte-shifting for alignment. This information is crucial for developers implementing or maintaining SDIO drivers.
Signed-off-by: Arjav Patel <arjav1528@gmail.com>
Replace pyelftools and capstone Python library dependencies with
subprocess calls to standard toolchain binaries (readelf, objdump,
addr2line). This eliminates all external Python package requirements,
removes manual DWARF parsing, and reduces the code from 818 to 563
lines.
Works with both GNU and LLVM toolchains via the -p/--prefix option:
-p arm-none-eabi- (GCC cross-compiler)
-p llvm- (LLVM/clang toolchain)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Added break to the dotest Blacklist and CMake loop: it stops at the first match instead of continuing unnecessarily.
Signed-off-by: simbit18 <simbit18@gmail.com>
Add a minimal GC0308 camera configuration based on nsh. Unlike the
full camera config, this only enables the GC0308 DVP camera driver
(I2C, PCA9557, LEDC, CAM, VIDEO) and camcap example, without ADB,
SDMMC, LCD, PSRAM or other peripherals.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add camera configuration for lckfb-szpi-esp32s3 board with GC0308
sensor on DVP interface. Includes board-level camera initialization,
DVP GPIO pin mapping, and V4L2 video pipeline setup.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add ESP32-S3 CAM controller driver implementing the NuttX imgdata
interface. Supports 8-bit DVP camera input with DMA-based frame
capture, VSYNC interrupt handling, and PSRAM frame buffer allocation.
The driver is sensor-agnostic: resolution and pixel format are
negotiated at runtime through the V4L2 pipeline. XCLK output
(24 MHz) is started during initialization for sensor communication.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add support for the GalaxyCore GC0308 VGA CMOS image sensor.
The driver implements the NuttX imgsensor interface and supports
VGA (640x480), QVGA (320x240), and QQVGA (160x120) resolutions
via Kconfig selection. Output format is RGB565X (big-endian).
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add big-endian RGB565 (RGB565X) pixel format throughout the V4L2
video pipeline:
- IMGDATA_PIX_FMT_RGB565X in imgdata.h
- IMGSENSOR_PIX_FMT_RGB565X in imgsensor.h
- Format conversion and buffer size handling in v4l2_cap.c
This is needed by 8-bit DVP camera sensors that output RGB565 in
big-endian byte order (high byte first on the data bus).
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add sysctl driver for K210 SoC providing clock and reset control:
- Clock enable/disable with two-stage APB/peripheral enable pattern
- Peripheral reset control with proper timing
- Clock frequency query for PLL, CPU, APB buses, and peripherals
- PLL frequency calculation and CPU frequency configuration
The sysctl driver is built unconditionally for K210 boards as it
provides essential clock and reset control functionality.
Add Kconfig option:
- K210_CPU_FREQ: Target CPU frequency in Hz (default 400MHz)
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Huang Qi
Michal Lenc
Lup Yuen Lee
Peter Barada
wangjianyu3
simbit18
Carlos Sanchez
Filipe Cavalcanti
Neil Berkman
Eren Terzioglu
Arjav Patel
Xiang Xiao