mirror of
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arch/arm/src/stm32h5: add support for HW RNG.
Driver copied from stm32f7, which includes CEIS/SEIS clearing per reference manual. Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
This commit is contained in:
Carlos Sanchez
committed by
Xiang Xiao
Xiang Xiao
parent
2554d210a5
commit
ff29b04e66
@@ -68,6 +68,10 @@ if(CONFIG_STM32H5_FDCAN_CHARDRIVER)
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list(APPEND SRCS stm32_fdcan.c)
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endif()
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if(CONFIG_STM32H5_RNG)
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list(APPEND SRCS stm32_rng.c)
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endif()
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if(CONFIG_STM32H5_ICACHE)
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list(APPEND SRCS stm32_icache.c)
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endif()
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@@ -356,6 +356,11 @@ config STM32H5_ADC2
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default n
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select STM32H5_ADC
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config STM32H5_RNG
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bool "RNG"
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default n
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select ARCH_HAVE_RNG
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config STM32H5_DMA1
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bool "DMA1"
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default n
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@@ -64,6 +64,10 @@ ifeq ($(CONFIG_STM32H5_FDCAN_CHARDRIVER),y)
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CHIP_CSRCS += stm32_fdcan.c
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endif
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ifeq ($(CONFIG_STM32H5_RNG),y)
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CHIP_CSRCS += stm32_rng.c
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endif
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ifeq ($(CONFIG_STM32H5_ICACHE),y)
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CHIP_CSRCS += stm32_icache.c
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endif
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@@ -0,0 +1,64 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/hardware/stm32_rng.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RNG_H
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#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RNG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
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#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
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#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
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/* Register Addresses *******************************************************/
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#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET)
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#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET)
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#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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/* RNG Control Register */
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#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */
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#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */
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/* RNG Status Register */
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#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */
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#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */
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#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */
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#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
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#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
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#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RNG_H */
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@@ -0,0 +1,330 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/stm32_rng.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/mutex.h>
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#include <nuttx/fs/fs.h>
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#include <nuttx/drivers/drivers.h>
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#include "hardware/stm32_rng.h"
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#include "arm_internal.h"
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#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static int stm32_rng_initialize(void);
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static int stm32_rnginterrupt(int irq, void *context, void *arg);
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static void stm32_rngenable(void);
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static void stm32_rngdisable(void);
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static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t);
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct rng_dev_s
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{
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mutex_t rd_devlock; /* Threads can only exclusively access the RNG */
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sem_t rd_readsem; /* To block until the buffer is filled */
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char *rd_buf;
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size_t rd_buflen;
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uint32_t rd_lastval;
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bool rd_first;
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static struct rng_dev_s g_rngdev =
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{
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.rd_devlock = NXMUTEX_INITIALIZER,
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.rd_readsem = SEM_INITIALIZER(0),
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};
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static const struct file_operations g_rngops =
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{
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NULL, /* open */
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NULL, /* close */
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stm32_rngread, /* read */
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};
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/****************************************************************************
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* Private functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_rng_initialize
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****************************************************************************/
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static int stm32_rng_initialize(void)
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{
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_info("Initializing RNG\n");
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if (irq_attach(STM32_IRQ_RNG, stm32_rnginterrupt, NULL))
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{
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/* We could not attach the ISR to the interrupt */
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_info("Could not attach IRQ.\n");
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return -EAGAIN;
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}
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return OK;
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}
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/****************************************************************************
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* Name: stm32_rngenable
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****************************************************************************/
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static void stm32_rngenable(void)
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{
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uint32_t regval;
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g_rngdev.rd_first = true;
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/* Enable generation and interrupts */
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regval = getreg32(STM32_RNG_CR);
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regval |= RNG_CR_RNGEN;
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regval |= RNG_CR_IE;
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putreg32(regval, STM32_RNG_CR);
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up_enable_irq(STM32_IRQ_RNG);
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}
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/****************************************************************************
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* Name: stm32_rngdisable
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****************************************************************************/
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static void stm32_rngdisable(void)
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{
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uint32_t regval;
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up_disable_irq(STM32_IRQ_RNG);
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regval = getreg32(STM32_RNG_CR);
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regval &= ~RNG_CR_IE;
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regval &= ~RNG_CR_RNGEN;
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putreg32(regval, STM32_RNG_CR);
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}
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/****************************************************************************
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* Name: stm32_rnginterrupt
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****************************************************************************/
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static int stm32_rnginterrupt(int irq, void *context, void *arg)
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{
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uint32_t rngsr;
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uint32_t data;
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rngsr = getreg32(STM32_RNG_SR);
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if (rngsr & RNG_SR_CEIS) /* Check for clock error int stat */
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{
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/* Clear it, we will try again. */
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putreg32(rngsr & ~RNG_SR_CEIS, STM32_RNG_SR);
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return OK;
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}
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if (rngsr & RNG_SR_SEIS) /* Check for seed error in int stat */
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{
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uint32_t crval;
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/* Clear seed error, then disable/enable the rng and try again. */
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putreg32(rngsr & ~RNG_SR_SEIS, STM32_RNG_SR);
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crval = getreg32(STM32_RNG_CR);
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crval &= ~RNG_CR_RNGEN;
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putreg32(crval, STM32_RNG_CR);
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crval |= RNG_CR_RNGEN;
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putreg32(crval, STM32_RNG_CR);
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return OK;
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}
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if (!(rngsr & RNG_SR_DRDY)) /* Data ready must be set */
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{
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/* This random value is not valid, we will try again. */
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return OK;
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}
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data = getreg32(STM32_RNG_DR);
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/* As required by the FIPS PUB (Federal Information Processing Standard
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* Publication) 140-2, the first random number generated after setting the
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* RNGEN bit should not be used, but saved for comparison with the next
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* generated random number. Each subsequent generated random number has to
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* be compared with the previously generated number. The test fails if any
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* two compared numbers are equal (continuous random number generator
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* test).
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*/
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if (g_rngdev.rd_first)
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{
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g_rngdev.rd_first = false;
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g_rngdev.rd_lastval = data;
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return OK;
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}
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if (g_rngdev.rd_lastval == data)
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{
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/* Two subsequent same numbers, we will try again. */
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return OK;
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}
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/* If we get here, the random number is valid. */
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g_rngdev.rd_lastval = data;
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if (g_rngdev.rd_buflen >= 4)
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{
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g_rngdev.rd_buflen -= 4;
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*(uint32_t *)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data;
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}
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else
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{
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while (g_rngdev.rd_buflen > 0)
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{
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g_rngdev.rd_buf[--g_rngdev.rd_buflen] = (char)data;
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data >>= 8;
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}
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}
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if (g_rngdev.rd_buflen == 0)
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{
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/* Buffer filled, stop further interrupts. */
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stm32_rngdisable();
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nxsem_post(&g_rngdev.rd_readsem);
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}
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return OK;
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}
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/****************************************************************************
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* Name: stm32_rngread
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****************************************************************************/
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static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen)
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{
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int ret;
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ret = nxmutex_lock(&g_rngdev.rd_devlock);
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if (ret < 0)
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{
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return ret;
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}
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/* We've got the device semaphore, proceed with reading */
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/* Reset the operation semaphore with 0 for blocking until the
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* buffer is filled from interrupts.
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*/
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nxsem_reset(&g_rngdev.rd_readsem, 0);
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g_rngdev.rd_buflen = buflen;
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g_rngdev.rd_buf = buffer;
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/* Enable RNG with interrupts */
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stm32_rngenable();
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/* Wait until the buffer is filled */
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ret = nxsem_wait(&g_rngdev.rd_readsem);
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/* Free RNG via the device mutex for next use */
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nxmutex_unlock(&g_rngdev.rd_devlock);
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return ret < 0 ? ret : buflen;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: devrandom_register
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*
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* Description:
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* Initialize the RNG hardware and register the /dev/random driver.
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* Must be called BEFORE devurandom_register.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_DEV_RANDOM
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void devrandom_register(void)
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{
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stm32_rng_initialize();
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register_driver("/dev/random", &g_rngops, 0444, NULL);
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}
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#endif
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/****************************************************************************
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* Name: devurandom_register
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*
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* Description:
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* Register /dev/urandom
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_DEV_URANDOM_ARCH
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void devurandom_register(void)
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{
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#ifndef CONFIG_DEV_RANDOM
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stm32_rng_initialize();
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#endif
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register_driver("/dev/urandom", &g_rngops, 0444, NULL);
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}
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#endif
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#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
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@@ -63,8 +63,15 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
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/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
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#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48)
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# if STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK
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# define STM32H5_USE_HSI48 1
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# if defined(STM32H5_CLKUSB_SEL)
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# if (STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK)
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# define STM32H5_USE_HSI48 1
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# endif
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# endif
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# if defined(STM32H5_CLKRNG_SEL)
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# if (STM32H5_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK)
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# define STM32H5_USE_HSI48 1
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# endif
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# endif
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#endif
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@@ -1194,12 +1201,23 @@ void stm32_stdclockconfig(void)
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putreg32(regval, STM32_RCC_CCIPR3);
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#endif
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/* Configure USB source clock */
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#if defined(STM32H5_CLKUSB_SEL)
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regval = getreg32(STM32_RCC_CCIPR4);
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regval &= ~RCC_CCIPR4_USBSEL_MASK;
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regval |= STM32H5_CLKUSB_SEL;
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putreg32(regval, STM32_RCC_CCIPR4);
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#endif
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/* Configure RNG source clock */
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#if defined(STM32H5_CLKRNG_SEL)
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regval = getreg32(STM32_RCC_CCIPR5);
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regval &= ~RCC_CCIPR5_RNGSEL_MASK;
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regval |= STM32H5_CLKRNG_SEL;
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putreg32(regval, STM32_RCC_CCIPR5);
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#endif
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}
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}
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#endif
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@@ -161,6 +161,10 @@
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# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE
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#endif
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#if defined(CONFIG_STM32H5_RNG)
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# define STM32H5_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK
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#endif
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/* Enable LSE (for the RTC) */
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#define STM32_USE_LSE 1
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