4e07680554
TLS: Forgot to add a file before last commit
2016-03-11 12:30:04 -06:00
87e7e135ba
i.MX6: GIC decode and prioritization logic
2016-03-11 09:49:00 -06:00
bc0fb5453a
i.MX6: A little more GIC initialization logic
2016-03-11 09:00:49 -06:00
1909dc8239
TLS: Move up_tls_info() to an inline function. Simplify TLS implementation.
2016-03-11 07:17:02 -06:00
78e4ca2bc7
ARM: Partial implementation of TLS
2016-03-10 19:29:21 -06:00
5445a1af83
Add a common ARM implementation of up_tls_info()
2016-03-10 18:10:17 -06:00
a9b880a02b
STM32L4: Fix a small error that prevent a clean compilation
2016-03-10 15:58:08 -06:00
3d6519a223
Implement Cortex-A9 up_cpu_index() using the MPIDR register. Thanks Alan.
2016-03-10 14:02:58 -06:00
1e5c4a83de
Add stm32L4 I2C driver
2016-03-10 11:00:41 -06:00
8e66043d7a
Rename current_regs in STM32L4 for consistency with other platforms
2016-03-10 10:08:40 -06:00
f4f03e6f02
Add port to the stm32L4
2016-03-10 09:59:16 -06:00
a94febb551
MPCore: Fix missing header file inclusion; Add GIC-based implementations of up_enabable_irq(0 and up_disable_irq()
2016-03-10 08:37:34 -06:00
5c75f83b55
ARMv7-A GIC: Add definitions for shared interrupt IDs
2016-03-10 07:13:40 -06:00
4a8ac55c9d
All SAM TWI: g_twiops should be both static and const
2016-03-09 18:11:55 -06:00
400aead74a
i.MX6: Add definitions for private processor interrupt IDs
2016-03-09 18:11:28 -06:00
51be83aa3a
ARM: Fix missing header file. Update comments in all *_irq.c files.
2016-03-09 15:08:58 -06:00
4d4f54a789
Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs
2016-03-09 13:41:48 -06:00
7b0a696498
i.MX6: Add a system timer based on the i.MX6 GPT
2016-03-09 12:16:44 -06:00
725e6878c4
i.MX6: Finish bit definitions in GPT header file
2016-03-09 09:31:36 -06:00
80dce6dba1
i.MX6: Add incomplete GPT header file
2016-03-09 09:08:01 -06:00
613786ff3d
ARMv7-A: Add global timer header file
2016-03-09 08:36:22 -06:00
a2052d006c
Fix what I believe to be typos in SAMV7 timer
2016-03-08 17:26:01 -06:00
72eef9f628
Ensure that CONFIG_ARMV7M_STACKCHECK works on the samv7
2016-03-08 17:22:07 -06:00
85a7ca1ddd
i.MX6: Fill in some 'Missing logic' that depended on CCM definitions. Correct confusion with boot media configuration.
2016-03-08 16:49:09 -06:00
145853a930
i.MX6: Complete CCM header file
2016-03-08 13:54:43 -06:00
73de0d9114
SAMV7: TWIHS: Correct Error Handling
2016-03-08 06:47:22 -06:00
945e137382
SAMV7: TWIHS: Correct timeout calculation; correct some issues with Multi-Message-Transfer
2016-03-08 06:44:41 -06:00
f46298105a
i.MX6: Add skeleton clockconfig file. Fix some naming problems. Add some warnings.
2016-03-07 16:14:13 -06:00
0d7edfd370
i.MX6: Add CCM header file
2016-03-07 15:01:38 -06:00
3b1812b50f
i.MX6 UART: Update periperal clock logic; Remove use of UART bits from i.MX1 that don't exist in i.MX6
2016-03-07 14:08:53 -06:00
912008a883
i.MX6: Finish off some missing IOMUXC register bit definitions
2016-03-07 12:22:27 -06:00
012f1c0e90
i.MX6: Some fixes for compiling imx_lowput.c. Still some missing clocking definitions.
2016-03-07 09:02:29 -06:00
a67de9ce24
i.MX6: Add imx_lowputc.c; repartition some serial logic
2016-03-07 08:21:03 -06:00
1992d57294
i.MX6: Add pin multiplexing header file
2016-03-06 21:30:37 -06:00
dd7a4fb6a4
i.MX6: Modify encoding of GPIOs; add support for peripherals
2016-03-06 16:19:14 -06:00
be594b8932
i.MX6 Add more IOMUX logic
2016-03-06 15:44:54 -06:00
2b0124b9f2
i.MX6: Add a little more GPIO/IOMUX logic
2016-03-06 13:49:34 -06:00
cbf7401dfb
i.MX6 GPIO: Add IOMUXC logic to set pin as a GPIO
2016-03-06 12:24:24 -06:00
0f825eed3d
i.MX6: Add PADCTL register offsets
2016-03-06 09:37:43 -06:00
af76adf06f
i.MX6: Simply some IOMUXC naming
2016-03-06 08:54:45 -06:00
dd27fce4eb
Remove some whitespace at the end of the line
2016-03-05 09:18:30 -06:00
56eebbbfe1
i.MX6: Add some basic, incomplete GPIO controls
2016-03-05 09:16:08 -06:00
d938c1cd8c
SAMV7: Use sem_reset() instead of sem_init() to set a semaphore count
2016-03-05 07:44:18 -06:00
5c881e6d2e
i.MX6: minor updates to last commit
2016-03-04 18:44:30 -06:00
5100e7a623
i.MX6: Add some preliminary definitions to handle other family members
2016-03-04 18:43:16 -06:00
f41189d828
i.MX6: Add IOMUXC header file
2016-03-04 16:19:34 -06:00
2297fdb714
SAMV71 and SAME70: Place the Main Oscillator Enable in the board.h
2016-03-04 12:31:54 -06:00
88f0d35bce
i.MX6: Add high-level GPIO header file
2016-03-04 12:27:11 -06:00
910e649616
Add a debug assertion for logic error in previous commit
2016-03-04 10:28:13 -06:00
a115e13e06
SAMV7 MCAN: use FIFO mode instead of QUEUE mode; improve error reporting
...
When using QUEUE mode sometimes the counting semaphore indicates there is no space left in the TX buffers, but in fact there is. This leads to a situation, where all TX buffers are empty and the driver
still waits for space in the buffers. The switch from QUEUE mode to FIFO mode is just a workarround to make the semaphore counting self repairing.
The Error reporting is changed due to some Error Interrupts not reporting states, they are reporting state changes. To keep this into Account the static Error conditions like WARNING, PASSIVE or BUS_OFF are filled in
every time.
2016-03-04 10:15:35 -06:00
Gregory Nutt
Sebastien Lorquet
David Sidrane
Frank Benkert