mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 01:05:54 +08:00
i.MX6 GPIO: Add IOMUXC logic to set pin as a GPIO
This commit is contained in:
Gregory Nutt
@@ -51,13 +51,16 @@
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* Pre-processor Definitions
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************************************************************************************/
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#define GPIO1 0 /* Port 1 index */
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#define GPIO2 1 /* Port 2 index */
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#define GPIO3 2 /* Port 3 index */
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#define GPIO4 3 /* Port 4 index */
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#define GPIO5 4 /* Port 5 index */
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#define GPIO6 5 /* Port 6 index */
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#define GPIO7 6 /* Port 7 index */
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#define GPIO1 0 /* Port 1 index */
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#define GPIO2 1 /* Port 2 index */
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#define GPIO3 2 /* Port 3 index */
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#define GPIO4 3 /* Port 4 index */
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#define GPIO5 4 /* Port 5 index */
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#define GPIO6 5 /* Port 6 index */
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#define GPIO7 6 /* Port 7 index */
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#define IMX_GPIO_NPORTS 7 /* Seven total ports */
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#define IMX_GPIO_NPINS 32 /* Up to 32 pins per port */
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/* GPIO Register Offsets ************************************************************/
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+461
-199
File diff suppressed because it is too large
Load Diff
@@ -41,13 +41,310 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <nuttx/irq.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "imx_iomuxc.h"
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#include "imx_gpio.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define IMX_PADMUX_INVALID 255
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const uint8_t g_gpio1_padmux[IMX_GPIO_NPINS] =
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{
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IMX_PADMUX_GPIO00_INDEX, /* GPIO1 Pin 0 */
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IMX_PADMUX_GPIO01_INDEX, /* GPIO1 Pin 1 */
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IMX_PADMUX_GPIO02_INDEX, /* GPIO1 Pin 2 */
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IMX_PADMUX_GPIO03_INDEX, /* GPIO1 Pin 3 */
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IMX_PADMUX_GPIO04_INDEX, /* GPIO1 Pin 4 */
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IMX_PADMUX_GPIO05_INDEX, /* GPIO1 Pin 5 */
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IMX_PADMUX_GPIO06_INDEX, /* GPIO1 Pin 6 */
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IMX_PADMUX_GPIO07_INDEX, /* GPIO1 Pin 7 */
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IMX_PADMUX_GPIO08_INDEX, /* GPIO1 Pin 8 */
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IMX_PADMUX_GPIO09_INDEX, /* GPIO1 Pin 9 */
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IMX_PADMUX_SD2_CLK_INDEX, /* GPIO1 Pin 10 */
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IMX_PADMUX_SD2_CMD_INDEX, /* GPIO1 Pin 11 */
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IMX_PADMUX_SD2_DATA3_INDEX, /* GPIO1 Pin 12 */
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IMX_PADMUX_SD2_DATA2_INDEX, /* GPIO1 Pin 13 */
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IMX_PADMUX_SD2_DATA1_INDEX, /* GPIO1 Pin 14 */
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IMX_PADMUX_SD2_DATA0_INDEX, /* GPIO1 Pin 15 */
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IMX_PADMUX_SD1_DATA0_INDEX, /* GPIO1 Pin 16 */
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IMX_PADMUX_SD1_DATA1_INDEX, /* GPIO1 Pin 17 */
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IMX_PADMUX_SD1_CMD_INDEX, /* GPIO1 Pin 18 */
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IMX_PADMUX_SD1_DATA2_INDEX, /* GPIO1 Pin 19 */
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IMX_PADMUX_SD1_CLK_INDEX, /* GPIO1 Pin 20 */
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IMX_PADMUX_SD1_DATA3_INDEX, /* GPIO1 Pin 21 */
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IMX_PADMUX_ENET_MDIO_INDEX, /* GPIO1 Pin 22 */
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IMX_PADMUX_ENET_REF_CLK_INDEX, /* GPIO1 Pin 23 */
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IMX_PADMUX_ENET_RX_ER_INDEX, /* GPIO1 Pin 24 */
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IMX_PADMUX_ENET_CRS_DV_INDEX, /* GPIO1 Pin 25 */
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IMX_PADMUX_ENET_RX_DATA1_INDEX, /* GPIO1 Pin 26 */
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IMX_PADMUX_ENET_RX_DATA0_INDEX, /* GPIO1 Pin 27 */
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IMX_PADMUX_ENET_TX_EN_INDEX, /* GPIO1 Pin 28 */
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IMX_PADMUX_ENET_TX_DATA1_INDEX, /* GPIO1 Pin 29 */
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IMX_PADMUX_ENET_TX_DATA0_INDEX, /* GPIO1 Pin 30 */
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IMX_PADMUX_ENET_MDC_INDEX /* GPIO1 Pin 31 */
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};
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static const uint8_t g_gpio2_padmux[IMX_GPIO_NPINS] =
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{
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IMX_PADMUX_NAND_DATA00_INDEX, /* GPIO2 Pin 0 */
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IMX_PADMUX_NAND_DATA01_INDEX, /* GPIO2 Pin 1 */
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IMX_PADMUX_NAND_DATA02_INDEX, /* GPIO2 Pin 2 */
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IMX_PADMUX_NAND_DATA03_INDEX, /* GPIO2 Pin 3 */
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IMX_PADMUX_NAND_DATA04_INDEX, /* GPIO2 Pin 4 */
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IMX_PADMUX_NAND_DATA05_INDEX, /* GPIO2 Pin 5 */
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IMX_PADMUX_NAND_DATA06_INDEX, /* GPIO2 Pin 6 */
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IMX_PADMUX_NAND_DATA07_INDEX, /* GPIO2 Pin 7 */
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IMX_PADMUX_SD4_DATA0_INDEX, /* GPIO2 Pin 8 */
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IMX_PADMUX_SD4_DATA1_INDEX, /* GPIO2 Pin 9 */
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IMX_PADMUX_SD4_DATA2_INDEX, /* GPIO2 Pin 10 */
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IMX_PADMUX_SD4_DATA3_INDEX, /* GPIO2 Pin 11 */
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IMX_PADMUX_SD4_DATA4_INDEX, /* GPIO2 Pin 12 */
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IMX_PADMUX_SD4_DATA5_INDEX, /* GPIO2 Pin 13 */
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IMX_PADMUX_SD4_DATA6_INDEX, /* GPIO2 Pin 14 */
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IMX_PADMUX_SD4_DATA7_INDEX, /* GPIO2 Pin 15 */
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IMX_PADMUX_EIM_ADDR22_INDEX, /* GPIO2 Pin 16 */
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IMX_PADMUX_EIM_ADDR21_INDEX, /* GPIO2 Pin 17 */
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IMX_PADMUX_EIM_ADDR20_INDEX, /* GPIO2 Pin 18 */
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IMX_PADMUX_EIM_ADDR19_INDEX, /* GPIO2 Pin 19 */
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IMX_PADMUX_EIM_ADDR18_INDEX, /* GPIO2 Pin 20 */
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IMX_PADMUX_EIM_ADDR17_INDEX, /* GPIO2 Pin 21 */
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IMX_PADMUX_EIM_ADDR16_INDEX, /* GPIO2 Pin 22 */
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IMX_PADMUX_EIM_CS0_INDEX, /* GPIO2 Pin 23 */
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IMX_PADMUX_EIM_CS1_INDEX, /* GPIO2 Pin 24 */
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IMX_PADMUX_EIM_OE_INDEX, /* GPIO2 Pin 25 */
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IMX_PADMUX_EIM_RW_INDEX, /* GPIO2 Pin 26 */
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IMX_PADMUX_EIM_LBA_INDEX, /* GPIO2 Pin 27 */
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IMX_PADMUX_EIM_EB0_INDEX, /* GPIO2 Pin 28 */
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IMX_PADMUX_EIM_EB1_INDEX, /* GPIO2 Pin 29 */
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IMX_PADMUX_EIM_EB2_INDEX, /* GPIO2 Pin 30 */
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IMX_PADMUX_EIM_EB3_INDEX, /* GPIO2 Pin 31 */
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};
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static const uint8_t g_gpio3_padmux[IMX_GPIO_NPINS] =
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{
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IMX_PADMUX_EIM_AD00_INDEX, /* GPIO3 Pin 0 */
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IMX_PADMUX_EIM_AD01_INDEX, /* GPIO3 Pin 1 */
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IMX_PADMUX_EIM_AD02_INDEX, /* GPIO3 Pin 2 */
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IMX_PADMUX_EIM_AD03_INDEX, /* GPIO3 Pin 3 */
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IMX_PADMUX_EIM_AD04_INDEX, /* GPIO3 Pin 4 */
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IMX_PADMUX_EIM_AD05_INDEX, /* GPIO3 Pin 5 */
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IMX_PADMUX_EIM_AD06_INDEX, /* GPIO3 Pin 6 */
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IMX_PADMUX_EIM_AD07_INDEX, /* GPIO3 Pin 7 */
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IMX_PADMUX_EIM_AD08_INDEX, /* GPIO3 Pin 8 */
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IMX_PADMUX_EIM_AD09_INDEX, /* GPIO3 Pin 9 */
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IMX_PADMUX_EIM_AD10_INDEX, /* GPIO3 Pin 10 */
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IMX_PADMUX_EIM_AD11_INDEX, /* GPIO3 Pin 11 */
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IMX_PADMUX_EIM_AD12_INDEX, /* GPIO3 Pin 12 */
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IMX_PADMUX_EIM_AD13_INDEX, /* GPIO3 Pin 13 */
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IMX_PADMUX_EIM_AD14_INDEX, /* GPIO3 Pin 14 */
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IMX_PADMUX_EIM_AD15_INDEX, /* GPIO3 Pin 15 */
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IMX_PADMUX_EIM_DATA16_INDEX, /* GPIO3 Pin 16 */
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IMX_PADMUX_EIM_DATA17_INDEX, /* GPIO3 Pin 17 */
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IMX_PADMUX_EIM_DATA18_INDEX, /* GPIO3 Pin 18 */
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IMX_PADMUX_EIM_DATA19_INDEX, /* GPIO3 Pin 19 */
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IMX_PADMUX_EIM_DATA20_INDEX, /* GPIO3 Pin 20 */
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IMX_PADMUX_EIM_DATA21_INDEX, /* GPIO3 Pin 21 */
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IMX_PADMUX_EIM_DATA22_INDEX, /* GPIO3 Pin 22 */
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IMX_PADMUX_EIM_DATA23_INDEX, /* GPIO3 Pin 23 */
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IMX_PADMUX_EIM_DATA24_INDEX, /* GPIO3 Pin 24 */
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IMX_PADMUX_EIM_DATA25_INDEX, /* GPIO3 Pin 25 */
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IMX_PADMUX_EIM_DATA26_INDEX, /* GPIO3 Pin 26 */
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IMX_PADMUX_EIM_DATA27_INDEX, /* GPIO3 Pin 27 */
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IMX_PADMUX_EIM_DATA28_INDEX, /* GPIO3 Pin 28 */
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IMX_PADMUX_EIM_DATA29_INDEX, /* GPIO3 Pin 29 */
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IMX_PADMUX_EIM_DATA30_INDEX, /* GPIO3 Pin 30 */
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IMX_PADMUX_EIM_DATA31_INDEX, /* GPIO3 Pin 31 */
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};
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static const uint8_t g_gpio4_padmux[IMX_GPIO_NPINS] =
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{
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IMX_PADMUX_INVALID, /* GPIO4 Pin 0 */
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IMX_PADMUX_INVALID, /* GPIO4 Pin 1 */
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IMX_PADMUX_INVALID, /* GPIO4 Pin 2 */
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IMX_PADMUX_INVALID, /* GPIO4 Pin 3 */
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IMX_PADMUX_INVALID, /* GPIO4 Pin 4 */
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IMX_PADMUX_GPIO19_INDEX, /* GPIO4 Pin 5 */
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IMX_PADMUX_KEY_COL0_INDEX, /* GPIO4 Pin 6 */
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IMX_PADMUX_KEY_ROW0_INDEX, /* GPIO4 Pin 7 */
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IMX_PADMUX_KEY_COL1_INDEX, /* GPIO4 Pin 8 */
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IMX_PADMUX_KEY_ROW1_INDEX, /* GPIO4 Pin 9 */
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IMX_PADMUX_KEY_COL2_INDEX, /* GPIO4 Pin 10 */
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IMX_PADMUX_KEY_ROW2_INDEX, /* GPIO4 Pin 11 */
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IMX_PADMUX_KEY_COL3_INDEX, /* GPIO4 Pin 12 */
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IMX_PADMUX_KEY_ROW3_INDEX, /* GPIO4 Pin 13 */
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IMX_PADMUX_KEY_COL4_INDEX, /* GPIO4 Pin 14 */
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IMX_PADMUX_KEY_ROW4_INDEX, /* GPIO4 Pin 15 */
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IMX_PADMUX_DI0_DISP_CLK_INDEX, /* GPIO4 Pin 16 */
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IMX_PADMUX_DI0_PIN15_INDEX, /* GPIO4 Pin 17 */
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IMX_PADMUX_DI0_PIN02_INDEX, /* GPIO4 Pin 18 */
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IMX_PADMUX_DI0_PIN03_INDEX, /* GPIO4 Pin 19 */
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IMX_PADMUX_DI0_PIN04_INDEX, /* GPIO4 Pin 20 */
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IMX_PADMUX_DISP0_DATA00_INDEX, /* GPIO4 Pin 21 */
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IMX_PADMUX_DISP0_DATA01_INDEX, /* GPIO4 Pin 22 */
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IMX_PADMUX_DISP0_DATA02_INDEX, /* GPIO4 Pin 23 */
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IMX_PADMUX_DISP0_DATA03_INDEX, /* GPIO4 Pin 24 */
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IMX_PADMUX_DISP0_DATA04_INDEX, /* GPIO4 Pin 25 */
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IMX_PADMUX_DISP0_DATA05_INDEX, /* GPIO4 Pin 26 */
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IMX_PADMUX_DISP0_DATA06_INDEX, /* GPIO4 Pin 27 */
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IMX_PADMUX_DISP0_DATA07_INDEX, /* GPIO4 Pin 28 */
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IMX_PADMUX_DISP0_DATA08_INDEX, /* GPIO4 Pin 29 */
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IMX_PADMUX_DISP0_DATA09_INDEX, /* GPIO4 Pin 30 */
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IMX_PADMUX_DISP0_DATA10_INDEX, /* GPIO4 Pin 31 */
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};
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static const uint8_t g_gpio5_padmux[IMX_GPIO_NPINS] =
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{
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IMX_PADMUX_EIM_WAIT_INDEX, /* GPIO5 Pin 0 */
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IMX_PADMUX_INVALID, /* GPIO5 Pin 1 */
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IMX_PADMUX_EIM_ADDR25_INDEX, /* GPIO5 Pin 2 */
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IMX_PADMUX_INVALID, /* GPIO5 Pin 3 */
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IMX_PADMUX_EIM_ADDR24_INDEX, /* GPIO5 Pin 4 */
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IMX_PADMUX_DISP0_DATA11_INDEX, /* GPIO5 Pin 5 */
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IMX_PADMUX_DISP0_DATA12_INDEX, /* GPIO5 Pin 6 */
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IMX_PADMUX_DISP0_DATA13_INDEX, /* GPIO5 Pin 7 */
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IMX_PADMUX_DISP0_DATA14_INDEX, /* GPIO5 Pin 8 */
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IMX_PADMUX_DISP0_DATA15_INDEX, /* GPIO5 Pin 9 */
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IMX_PADMUX_DISP0_DATA16_INDEX, /* GPIO5 Pin 10 */
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IMX_PADMUX_DISP0_DATA17_INDEX, /* GPIO5 Pin 11 */
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IMX_PADMUX_DISP0_DATA18_INDEX, /* GPIO5 Pin 12 */
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IMX_PADMUX_DISP0_DATA19_INDEX, /* GPIO5 Pin 13 */
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IMX_PADMUX_DISP0_DATA20_INDEX, /* GPIO5 Pin 14 */
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IMX_PADMUX_DISP0_DATA21_INDEX, /* GPIO5 Pin 15 */
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IMX_PADMUX_DISP0_DATA22_INDEX, /* GPIO5 Pin 16 */
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IMX_PADMUX_DISP0_DATA23_INDEX, /* GPIO5 Pin 17 */
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IMX_PADMUX_CSI0_PIXCLK_INDEX, /* GPIO5 Pin 18 */
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IMX_PADMUX_CSI0_HSYNC_INDEX, /* GPIO5 Pin 19 */
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IMX_PADMUX_CSI0_DATA_EN_INDEX, /* GPIO5 Pin 20 */
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IMX_PADMUX_CSI0_VSYNC_INDEX, /* GPIO5 Pin 21 */
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IMX_PADMUX_CSI0_DATA04_INDEX, /* GPIO5 Pin 22 */
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IMX_PADMUX_CSI0_DATA05_INDEX, /* GPIO5 Pin 23 */
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IMX_PADMUX_CSI0_DATA06_INDEX, /* GPIO5 Pin 24 */
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IMX_PADMUX_CSI0_DATA07_INDEX, /* GPIO5 Pin 25 */
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IMX_PADMUX_CSI0_DATA08_INDEX, /* GPIO5 Pin 26 */
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IMX_PADMUX_CSI0_DATA09_INDEX, /* GPIO5 Pin 27 */
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IMX_PADMUX_CSI0_DATA10_INDEX, /* GPIO5 Pin 28 */
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IMX_PADMUX_CSI0_DATA11_INDEX, /* GPIO5 Pin 29 */
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IMX_PADMUX_CSI0_DATA12_INDEX, /* GPIO5 Pin 30 */
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IMX_PADMUX_CSI0_DATA13_INDEX, /* GPIO5 Pin 31 */
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};
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static const uint8_t g_gpio6_padmux[IMX_GPIO_NPINS] =
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{
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IMX_PADMUX_CSI0_DATA14_INDEX, /* GPIO6 Pin 0 */
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IMX_PADMUX_CSI0_DATA15_INDEX, /* GPIO6 Pin 1 */
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IMX_PADMUX_CSI0_DATA16_INDEX, /* GPIO6 Pin 2 */
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IMX_PADMUX_CSI0_DATA17_INDEX, /* GPIO6 Pin 3 */
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IMX_PADMUX_CSI0_DATA18_INDEX, /* GPIO6 Pin 4 */
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IMX_PADMUX_CSI0_DATA19_INDEX, /* GPIO6 Pin 5 */
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IMX_PADMUX_EIM_ADDR23_INDEX, /* GPIO6 Pin 6 */
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IMX_PADMUX_NAND_CLE_INDEX, /* GPIO6 Pin 7 */
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IMX_PADMUX_NAND_ALE_INDEX, /* GPIO6 Pin 8 */
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IMX_PADMUX_NAND_WP_INDEX, /* GPIO6 Pin 9 */
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IMX_PADMUX_NAND_READY_INDEX, /* GPIO6 Pin 10 */
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IMX_PADMUX_NAND_CS0_INDEX, /* GPIO6 Pin 11 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 12 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 13 */
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IMX_PADMUX_NAND_CS1_INDEX, /* GPIO6 Pin 14 */
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IMX_PADMUX_NAND_CS2_INDEX, /* GPIO6 Pin 15 */
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IMX_PADMUX_NAND_CS3_INDEX, /* GPIO6 Pin 16 */
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IMX_PADMUX_SD3_DATA7_INDEX, /* GPIO6 Pin 17 */
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IMX_PADMUX_SD3_DATA6_INDEX, /* GPIO6 Pin 18 */
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IMX_PADMUX_RGMII_TXC_INDEX, /* GPIO6 Pin 19 */
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IMX_PADMUX_RGMII_TD0_INDEX, /* GPIO6 Pin 20 */
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IMX_PADMUX_RGMII_TD1_INDEX, /* GPIO6 Pin 21 */
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IMX_PADMUX_RGMII_TD2_INDEX, /* GPIO6 Pin 22 */
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IMX_PADMUX_RGMII_TD3_INDEX, /* GPIO6 Pin 23 */
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IMX_PADMUX_RGMII_RX_CTL_INDEX, /* GPIO6 Pin 24 */
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IMX_PADMUX_RGMII_RD0_INDEX, /* GPIO6 Pin 25 */
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IMX_PADMUX_RGMII_TX_CTL_INDEX, /* GPIO6 Pin 26 */
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IMX_PADMUX_RGMII_RD1_INDEX, /* GPIO6 Pin 27 */
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IMX_PADMUX_RGMII_RD2_INDEX, /* GPIO6 Pin 28 */
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IMX_PADMUX_RGMII_RD3_INDEX, /* GPIO6 Pin 29 */
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IMX_PADMUX_RGMII_RXC_INDEX, /* GPIO6 Pin 30 */
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IMX_PADMUX_EIM_BCLK_INDEX, /* GPIO6 Pin 31 */
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};
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static const uint8_t g_gpio7_padmux[IMX_GPIO_NPINS] =
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{
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IMX_PADMUX_SD3_DATA5_INDEX, /* GPIO7 Pin 0 */
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IMX_PADMUX_SD3_DATA4_INDEX, /* GPIO7 Pin 1 */
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IMX_PADMUX_SD3_CMD_INDEX, /* GPIO7 Pin 2 */
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IMX_PADMUX_SD3_CLK_INDEX, /* GPIO7 Pin 3 */
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IMX_PADMUX_SD3_DATA0_INDEX, /* GPIO7 Pin 4 */
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IMX_PADMUX_SD3_DATA1_INDEX, /* GPIO7 Pin 5 */
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IMX_PADMUX_SD3_DATA2_INDEX, /* GPIO7 Pin 6 */
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IMX_PADMUX_SD3_DATA3_INDEX, /* GPIO7 Pin 7 */
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IMX_PADMUX_SD3_RESET_INDEX, /* GPIO7 Pin 8 */
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IMX_PADMUX_SD4_CMD_INDEX, /* GPIO7 Pin 9 */
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IMX_PADMUX_SD4_CLK_INDEX, /* GPIO7 Pin 10 */
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IMX_PADMUX_GPIO16_INDEX, /* GPIO7 Pin 11 */
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IMX_PADMUX_GPIO17_INDEX, /* GPIO7 Pin 12 */
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IMX_PADMUX_GPIO18_INDEX, /* GPIO7 Pin 13 */
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IMX_PADMUX_INVALID, /* GPIO7 Pin 14 */
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IMX_PADMUX_INVALID, /* GPIO7 Pin 15 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 16 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 17 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 18 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 19 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 20 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 21 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 22 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 23 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 24 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 25 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 26 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 27 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 28 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 29 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 30 */
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IMX_PADMUX_INVALID, /* GPIO6 Pin 31 */
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};
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static FAR const uint8_t *g_gpio_padmux[IMX_GPIO_NPORTS+1] =
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{
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g_gpio1_padmux, /* GPIO1 */
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g_gpio2_padmux, /* GPIO2 */
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g_gpio3_padmux, /* GPIO3 */
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g_gpio4_padmux, /* GPIO4 */
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g_gpio5_padmux, /* GPIO5 */
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g_gpio6_padmux, /* GPIO6 */
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g_gpio7_padmux, /* GPIO7 */
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NULL /* GPIO8 */
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
|
||||
@@ -115,12 +412,30 @@ static inline bool imx_gpio_getinput(int port, int pin)
|
||||
|
||||
static inline int imx_gpio_configinput(gpio_pinset_t pinset, int port, int pin)
|
||||
{
|
||||
FAR const uint8_t *table;
|
||||
uintptr_t regaddr;
|
||||
unsigned int index;
|
||||
|
||||
/* Configure pin as in input */
|
||||
|
||||
imx_gpio_dirin(port, pin);
|
||||
|
||||
/* Configure pin as a GPIO */
|
||||
#warning Missing logic
|
||||
|
||||
table = g_gpio_padmux[port];
|
||||
if (table == NULL)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
index = table[pin];
|
||||
if (index >= IMX_PADMUX_NREGISTERS)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regaddr = IMX_PADMUX_ADDRESS(index);
|
||||
putreg32(PADMUX_MUXMODE_ALT5, regaddr);
|
||||
|
||||
/* Configure pin pad settings */
|
||||
#warning Missing logic
|
||||
|
||||
@@ -0,0 +1,67 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/imx/imx_iomuxc.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMX6_IMX_IOMUXC_H
|
||||
#define __ARCH_ARM_SRC_IMX6_IMX_IOMUXC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip/imx_iomuxc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMX6_IMX_IOMUXC_H */
|
||||
Reference in New Issue
Block a user