mirror of
https://github.com/apache/nuttx.git
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Add support for STM32G474: Modify existing files
Add support for the STM32G474 family of microcontrollers and the
B-G474E-DPOW1 Discovery Board, which features a STM32G474RET6.
This is a major pull request as it adds support for an entirely
new family of STM32. This support is implemented in
arch/arm/src/stm32 and shares implementation with other STM32
families supported by that code, such as the 'L15xx, 'F10xx,
'F20xx, 'F3xxx, and 'F4xxx.
arch/arm/Kconfig:
arch/arm/include/stm32/chip.h:
arch/arm/include/stm32/irq.h:
arch/arm/src/stm32/Kconfig:
arch/arm/src/stm32/hardware/stm32_adc.h:
arch/arm/src/stm32/hardware/stm32_adc_v2.h:
arch/arm/src/stm32/hardware/stm32_dma.h:
arch/arm/src/stm32/hardware/stm32_dma_v1.h:
arch/arm/src/stm32/hardware/stm32_flash.h:
arch/arm/src/stm32/hardware/stm32_i2c.h:
arch/arm/src/stm32/hardware/stm32_i2c_v2.h:
arch/arm/src/stm32/hardware/stm32_memorymap.h:
arch/arm/src/stm32/hardware/stm32_pinmap.h:
arch/arm/src/stm32/hardware/stm32_tim.h:
arch/arm/src/stm32/stm32_allocateheap.c:
arch/arm/src/stm32/stm32_dma.c:
arch/arm/src/stm32/stm32_dma_v1.c:
arch/arm/src/stm32/stm32_dumpgpio.c:
arch/arm/src/stm32/stm32_gpio.c:
arch/arm/src/stm32/stm32_gpio.h:
arch/arm/src/stm32/stm32_lowputc.c:
arch/arm/src/stm32/stm32_rcc.c:
arch/arm/src/stm32/stm32_rcc.h:
arch/arm/src/stm32/stm32_serial.c:
arch/arm/src/stm32/stm32_syscfg.h:
arch/arm/src/stm32/stm32_uart.h:
* Add architectural support to existing NuttX files. This
makes the STM32G474 family parts accessible to the system.
With big thanks for detailed code review:
David Sidrane (davids5)
Mateusz Szafoni (raiden00)
Abdelatif Guettouche (Ouss4)
This commit is contained in:
Nathan Hartman
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
3b4e4c603f
commit
168a4cafc6
+1
-1
@@ -292,7 +292,7 @@ config ARCH_CHIP_SIMPLELINK
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TI SimpleLink CCxxx architectures (ARM Cortex-M3 or M4)
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config ARCH_CHIP_STM32
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bool "STMicro STM32 F1/F2/F3/F4/L1"
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bool "STMicro STM32 F1/F2/F3/F4/G4/L1"
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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@@ -80,6 +80,11 @@
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#else
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# define __HAVE_F4 0
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#endif
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#ifdef CONFIG_STM32_STM32G47XX
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# define __HAVE_G47 1
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#else
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# define __HAVE_G47 0
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#endif
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#ifdef CONFIG_STM32_STM32L15XX
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# define __HAVE_L1 1
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#else
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@@ -87,7 +92,7 @@
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#endif
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#if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \
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__HAVE_L1) != 1)
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__HAVE_G47 + __HAVE_L1) != 1)
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# error "Only one STM32 family must be selected !"
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#endif
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@@ -2267,6 +2272,141 @@
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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#elif defined (CONFIG_ARCH_CHIP_STM32G474C)
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */
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# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA
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* (2) 32-bit general timers TIM2 and 5 with DMA
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* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
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# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NCAN 3 /* FDCAN1-3 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
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* with LPM and BCD support) */
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# define STM32_NGPIO 42 /* GPIOA-C, F-G */
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# define STM32_NADC 5 /* 12-bit ADC1-5 */
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# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined (CONFIG_ARCH_CHIP_STM32G474M)
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */
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# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA
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* (2) 32-bit general timers TIM2 and 5 with DMA
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* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
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# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
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# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NCAN 3 /* FDCAN1-3 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
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* with LPM and BCD support) */
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# define STM32_NGPIO 67 /* GPIOA-G */
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# define STM32_NADC 5 /* 12-bit ADC1-5 */
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# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined (CONFIG_ARCH_CHIP_STM32G474R)
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */
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# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA
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* (2) 32-bit general timers TIM2 and 5 with DMA
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* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
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# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
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# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NCAN 3 /* FDCAN1-3 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
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* with LPM and BCD support) */
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# define STM32_NGPIO 52 /* GPIOA-D, F-G */
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# define STM32_NADC 5 /* 12-bit ADC1-5 */
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# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined (CONFIG_ARCH_CHIP_STM32G474Q)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */
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# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA
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* (2) 32-bit general timers TIM2 and 5 with DMA
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* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
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# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
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# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NCAN 3 /* FDCAN1-3 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
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* with LPM and BCD support) */
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# define STM32_NGPIO 107 /* GPIOA-G */
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# define STM32_NADC 5 /* 12-bit ADC1-5 */
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# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined (CONFIG_ARCH_CHIP_STM32G474V)
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */
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# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA
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* (2) 32-bit general timers TIM2 and 5 with DMA
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* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
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# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
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# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NSPI 4 /* SPI1-4 */
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# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
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# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NCAN 3 /* FDCAN1-3 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
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* with LPM and BCD support) */
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# define STM32_NGPIO 86 /* GPIOA-G */
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# define STM32_NADC 5 /* 12-bit ADC1-5 */
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# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */
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# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#else
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# error "Unsupported STM32 chip"
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#endif
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@@ -95,6 +95,8 @@
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# include <arch/stm32/stm32f37xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32F4XXX)
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# include <arch/stm32/stm32f40xxx_irq.h>
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#elif defined(CONFIG_STM32_STM32G47XX)
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# include <arch/stm32/stm32g47xxx_irq.h>
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#else
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# error "Unsupported STM32 chip"
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#endif
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+347
-11
File diff suppressed because it is too large
Load Diff
@@ -50,7 +50,7 @@
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* b) extended version for F2, F4, F7, L1:
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* 2. STM32 ADC IPv2:
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* a) basic version for F0 and L0
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* b) extended version for F3 (without F37x), H7, L4, L4+
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* b) extended version for F3 (without F37x), G4, H7, L4, L4+
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*
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* We also distinguish the modified STM32 ADC IPv1 core for the L1 family,
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* which differs too much to keep it in the same file as ADC IPv1.
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File diff suppressed because it is too large
Load Diff
@@ -45,7 +45,7 @@
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#include "chip.h"
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/* Include the correct DMA register definitions for selected STM32 DMA IP core:
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* - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4
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* - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4
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* - STM32 DMA IP version 2 - F2, F4, F7, H7
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*/
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@@ -40,7 +40,7 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* This is implementation for STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 */
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/* This is implementation for STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 */
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#define HAVE_IP_DMA_V1 1
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#undef HAVE_IP_DMA_V2
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@@ -54,8 +54,13 @@
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#define DMA1 (0)
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#define DMA2 (1)
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/* These definitions apply to both the STM32 F1 and F3 families
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* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5)
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/* These definitions apply to multiple STM32 families.
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*
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* The STM32 F1 and F3 families have 12 channels total:
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* 7 DMA1 channels(1-7) and 5 DMA2 channels (1-5).
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*
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* The STM32 G4 family has 16 channels total:
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* 8 DMA1 channels(1-8) and 8 DMA2 channels (1-8).
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*/
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#define DMA_CHAN1 (0)
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@@ -65,6 +70,7 @@
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#define DMA_CHAN5 (4)
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#define DMA_CHAN6 (5)
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#define DMA_CHAN7 (6)
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#define DMA_CHAN8 (7)
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/* Register Offsets *****************************************************************/
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@@ -79,6 +85,7 @@
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#define STM32_DMACHAN5_OFFSET 0x0050
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#define STM32_DMACHAN6_OFFSET 0x0064
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#define STM32_DMACHAN7_OFFSET 0x0078
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#define STM32_DMACHAN8_OFFSET 0x008c
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#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
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#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
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@@ -97,6 +104,7 @@
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#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
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#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
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#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
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#define STM32_DMA_CCR8_OFFSET 0x0094 /* DMA channel 8 configuration register */
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#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
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#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
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@@ -105,6 +113,7 @@
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#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
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#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
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#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
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#define STM32_DMA_CNDTR8_OFFSET 0x0098 /* DMA channel 8 number of data register */
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#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
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#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
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@@ -113,6 +122,7 @@
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#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
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#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
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#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
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#define STM32_DMA_CPAR8_OFFSET 0x009c /* DMA channel 8 peripheral address register */
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#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
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#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
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@@ -121,6 +131,7 @@
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#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
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#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
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#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
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#define STM32_DMA_CMAR8_OFFSET 0x00a0 /* DMA channel 8 memory address register */
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#ifdef DMA_HAVE_CSELR
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# define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
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@@ -139,6 +150,9 @@
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#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
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#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
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#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
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#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
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# define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET)
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#endif
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#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
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#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
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@@ -148,6 +162,9 @@
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#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
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#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
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#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
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#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
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# define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET)
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#endif
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#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
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#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
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@@ -157,6 +174,9 @@
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
|
||||
# define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
@@ -166,6 +186,9 @@
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
|
||||
# define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
@@ -176,6 +199,11 @@
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
# define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
# define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
@@ -183,6 +211,11 @@
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
# define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
# define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
@@ -190,6 +223,11 @@
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
# define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
# define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
@@ -197,6 +235,11 @@
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
# define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
# define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
@@ -225,6 +268,8 @@
|
||||
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
|
||||
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
|
||||
#define DMA_ISR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt status */
|
||||
#define DMA_ISR_CHAN8_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN8_SHIFT)
|
||||
|
||||
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
@@ -249,7 +294,14 @@
|
||||
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
|
||||
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
|
||||
#define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT)
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) || defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define DMA_IFCR_ALLCHANNELS (0xffffffff)
|
||||
#else
|
||||
# define DMA_IFCR_ALLCHANNELS (0x0fffffff)
|
||||
#endif
|
||||
|
||||
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
@@ -308,12 +360,30 @@
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
|
||||
# define STM32_DMA1_CHAN8 (7)
|
||||
# define STM32_DMA2_CHAN1 (8)
|
||||
# define STM32_DMA2_CHAN2 (9)
|
||||
# define STM32_DMA2_CHAN3 (10)
|
||||
# define STM32_DMA2_CHAN4 (11)
|
||||
# define STM32_DMA2_CHAN5 (12)
|
||||
# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define STM32_DMA2_CHAN6 (13)
|
||||
# define STM32_DMA2_CHAN7 (14)
|
||||
# define STM32_DMA2_CHAN8 (15)
|
||||
# endif
|
||||
#else
|
||||
# define STM32_DMA2_CHAN1 (7)
|
||||
# define STM32_DMA2_CHAN2 (8)
|
||||
# define STM32_DMA2_CHAN3 (9)
|
||||
# define STM32_DMA2_CHAN4 (10)
|
||||
# define STM32_DMA2_CHAN5 (11)
|
||||
# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define STM32_DMA2_CHAN6 (12)
|
||||
# define STM32_DMA2_CHAN7 (13)
|
||||
# define STM32_DMA2_CHAN8 (14)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
# define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff))
|
||||
@@ -700,6 +770,12 @@
|
||||
# define DMACHAN_TIM18_UP_2 STM32_DMA2_CHAN5
|
||||
# define DMACHAN_DAC2_CH1_2 STM32_DMA2_CHAN5
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
|
||||
/* This family uses a DMAMUX. The code to support this needs to be ported
|
||||
* to this family from STM32L4R.
|
||||
*/
|
||||
|
||||
#else
|
||||
# error "Unknown DMA channel assignments"
|
||||
#endif
|
||||
|
||||
@@ -125,6 +125,11 @@
|
||||
/* STM32F4 has mixed page size */
|
||||
|
||||
# undef STM32_FLASH_PAGESIZE
|
||||
|
||||
# elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# define STM32_FLASH_NPAGES 32
|
||||
# define STM32_FLASH_PAGESIZE 4096
|
||||
|
||||
# endif
|
||||
#endif /* CONFIG_STM32_FLASH_CONFIG_DEFAULT */
|
||||
|
||||
@@ -186,6 +191,22 @@
|
||||
_K(128), _K(128), _K(128), _K(128)}
|
||||
# endif
|
||||
|
||||
/* Define the Valid Configuration the G4 */
|
||||
|
||||
# elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# if defined(CONFIG_STM32_FLASH_CONFIG_B)
|
||||
# define STM32_FLASH_NPAGES 32
|
||||
# define STM32_FLASH_PAGESIZE 4096
|
||||
|
||||
# elif defined(CONFIG_STM32_FLASH_CONFIG_C)
|
||||
# define STM32_FLASH_NPAGES 64
|
||||
# define STM32_FLASH_PAGESIZE 4096
|
||||
|
||||
# elif defined(CONFIG_STM32_FLASH_CONFIG_E)
|
||||
# define STM32_FLASH_NPAGES 128
|
||||
# define STM32_FLASH_PAGESIZE 4096
|
||||
# endif
|
||||
|
||||
/* Define the Valid Configuration the F1 and F3 */
|
||||
|
||||
# else
|
||||
@@ -253,6 +274,24 @@
|
||||
# define STM32_FLASH_WRPR2_OFFSET 0x0080
|
||||
# define STM32_FLASH_WRPR3_OFFSET 0x0084
|
||||
# define STM32_FLASH_WRPR4_OFFSET 0x0088
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# define STM32_FLASH_PDKEYR_OFFSET 0x0004
|
||||
# define STM32_FLASH_KEYR_OFFSET 0x0008
|
||||
# define STM32_FLASH_OPT_KEYR_OFFSET 0x000c
|
||||
# define STM32_FLASH_SR_OFFSET 0x0010
|
||||
# define STM32_FLASH_CR_OFFSET 0x0014
|
||||
# define STM32_FLASH_ECCR_OFFSET 0x0018
|
||||
# define STM32_FLASH_OPTR_OFFSET 0x0020
|
||||
# define STM32_FLASH_PCROP1SR_OFFSET 0x0024
|
||||
# define STM32_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
# define STM32_FLASH_WRP1AR_OFFSET 0x002c
|
||||
# define STM32_FLASH_WRP1BR_OFFSET 0x0030
|
||||
# define STM32_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32_FLASH_WRP2AR_OFFSET 0x004c
|
||||
# define STM32_FLASH_WRP2BR_OFFSET 0x0050
|
||||
# define STM32_FLASH_SEC1R_OFFSET 0x0070
|
||||
# define STM32_FLASH_SEC2R_OFFSET 0x0074
|
||||
#else
|
||||
# define STM32_FLASH_KEYR_OFFSET 0x0004
|
||||
# define STM32_FLASH_OPTKEYR_OFFSET 0x0008
|
||||
@@ -298,6 +337,24 @@
|
||||
# define STM32_FLASH_WRPR2 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR2_OFFSET)
|
||||
# define STM32_FLASH_WRPR3 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR3_OFFSET)
|
||||
# define STM32_FLASH_WRPR4 (STM32_FLASHIF_BASE+STM32_FLASH_WRPR4_OFFSET)
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET)
|
||||
# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
# define STM32_FLASH_OPT_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPT_KEYR_OFFSET)
|
||||
# define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
# define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
# define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET)
|
||||
# define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET)
|
||||
# define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET)
|
||||
# define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET)
|
||||
# define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET)
|
||||
# define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET)
|
||||
# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET)
|
||||
# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET)
|
||||
# define STM32_FLASH_SEC1R (STM32_FLASHIF_BASE+STM32_FLASH_SEC1R_OFFSET)
|
||||
# define STM32_FLASH_SEC2R (STM32_FLASHIF_BASE+STM32_FLASH_SEC2R_OFFSET)
|
||||
#else
|
||||
# define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
|
||||
@@ -335,6 +392,34 @@
|
||||
# define FLASH_ACR_ACC64 (1 << 2) /* Bit 2: 64-bit access */
|
||||
# define FLASH_ACR_SLEEP_PD (1 << 3) /* Bit 3: Flash mode during Sleep */
|
||||
# define FLASH_ACR_RUN_PD (1 << 4) /* Bit 4: Flash mode during Run */
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_ACR_LATENCY_SHIFT (0)
|
||||
# define FLASH_ACR_LATENCY_MASK (0xf << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states = 0..15 */
|
||||
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
|
||||
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */
|
||||
# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */
|
||||
# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */
|
||||
# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */
|
||||
# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */
|
||||
# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */
|
||||
# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */
|
||||
# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */
|
||||
# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait state */
|
||||
# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */
|
||||
# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */
|
||||
# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */
|
||||
# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */
|
||||
# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */
|
||||
# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
|
||||
# define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: FLASH prefetch enable */
|
||||
# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
|
||||
# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
|
||||
# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
|
||||
# define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */
|
||||
# define FLASH_ACR_RUNPD (1 << 13) /* Bit 13: Flash Power Down Mode During Run or Low Power Run */
|
||||
# define FLASH_ACR_SLEEPPD (1 << 14) /* Bit 14: Flash Power Down Mode During Sleep or Low Power Sleep */
|
||||
# define FLASH_ACR_DBG_SWEN (1 << 18) /* Bit 18: Debug Software Enable */
|
||||
#else
|
||||
# define FLASH_ACR_LATENCY_SHIFT (0)
|
||||
# define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
|
||||
@@ -392,6 +477,19 @@
|
||||
# define FLASH_SR_OPTVERR (1 << 11) /* Bit 11: Option validity error */
|
||||
# define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */
|
||||
# define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
|
||||
# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
|
||||
# define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
|
||||
# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
|
||||
# define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
|
||||
# define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
|
||||
# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
|
||||
# define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */
|
||||
# define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */
|
||||
# define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
|
||||
# define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */
|
||||
# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
|
||||
#endif
|
||||
|
||||
/* Program/Erase Control Register (PECR) */
|
||||
@@ -434,13 +532,13 @@
|
||||
# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
|
||||
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
|
||||
# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# define FLASH_CR_SNB_MASK (31 << FLASH_CR_SNB_SHIFT)
|
||||
# define FLASH_CR_SNB(n) (((n % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
|
||||
#else
|
||||
# else
|
||||
# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
|
||||
# define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */
|
||||
#endif
|
||||
# endif
|
||||
# define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
|
||||
# define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
|
||||
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00 program x8 */
|
||||
@@ -451,11 +549,47 @@
|
||||
# define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
|
||||
# define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
|
||||
# define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_CR_PG (1 << 0)
|
||||
# define FLASH_CR_PER (1 << 1)
|
||||
# define FLASH_CR_MER1 (1 << 2)
|
||||
# define FLASH_CR_PNB_SHIFT (3)
|
||||
# define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT)
|
||||
# define FLASH_CR_PNB(n) (((n) << FLASH_CR_PNB_SHIFT) & FLASH_CR_PNB_MASK)
|
||||
# define FLASH_CR_BKER (1 << 11)
|
||||
# define FLASH_CR_MER2 (1 << 15)
|
||||
# define FLASH_CR_START (1 << 16)
|
||||
# define FLASH_CR_OPTSTRT (1 << 17)
|
||||
# define FLASH_CR_FSTPG (1 << 18)
|
||||
# define FLASH_CR_EOPIE (1 << 24)
|
||||
# define FLASH_CR_ERRIE (1 << 25)
|
||||
# define FLASH_CR_RDERRIE (1 << 26)
|
||||
# define FLASH_CR_OBL_LAUNCH (1 << 27)
|
||||
# define FLASH_CR_SEC_PROT1 (1 << 28)
|
||||
# define FLASH_CR_SEC_PROT2 (1 << 29)
|
||||
# define FLASH_CR_OPTLOCK (1 << 30)
|
||||
# define FLASH_CR_LOCK (1 << 31)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */
|
||||
#endif
|
||||
|
||||
/* Flash ECC register (ECCR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_ECCR_ADDR_ECC_SHIFT (0)
|
||||
# define FLASH_ECCR_ADDR_ECC_MASK (0x7ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
|
||||
# define FLASH_ECCR_ADDR_ECC(n) (((n) << FLASH_ECCR_ADDR_ECC_SHIFT) & FLASH_ECCR_ADDR_ECC_MASK)
|
||||
|
||||
# define FLASH_ECCR_BK_ECC (1 << 21)
|
||||
# define FLASH_ECCR_SYSF_ECC (1 << 22)
|
||||
# define FLASH_ECCR_ECCIE (1 << 24)
|
||||
# define FLASH_ECCR_ECCC2 (1 << 28)
|
||||
# define FLASH_ECCR_ECCD2 (1 << 29)
|
||||
# define FLASH_ECCR_ECCC (1 << 30)
|
||||
# define FLASH_ECCR_ECCD (1 << 31)
|
||||
#endif
|
||||
|
||||
/* Flash Option Control Register (OPTCR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
@@ -481,16 +615,145 @@
|
||||
/* Flash Option Control Register (OPTCR1) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */
|
||||
# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */
|
||||
# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
|
||||
# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */
|
||||
# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT)
|
||||
# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */
|
||||
# define FLASH_OPTCR1_BFB2_MASK (1 << FLASH_OPTCR_NWRP_SHIFT)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F446)
|
||||
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */
|
||||
# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */
|
||||
# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Flash option register (OPTR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_OPTR_RDP_SHIFT (0)
|
||||
# define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT)
|
||||
# define FLASH_OPTR_RDP (((n) << FLASH_OPTR_RDP_SHIFT) & FLASH_OPTR_RDP_MASK)
|
||||
# define FLASH_OPTR_BOR_LEV_SHIFT (8)
|
||||
# define FLASH_OPTR_BOR_LEV_MASK (0x7 << FLASH_OPTR_BOR_LEV_SHIFT)
|
||||
# define FLASH_OPTR_BOR_LEV_1_7V (0x0 << FLASH_OPTR_BOR_LEV_SHIFT)
|
||||
# define FLASH_OPTR_BOR_LEV_2_0V (0x1 << FLASH_OPTR_BOR_LEV_SHIFT)
|
||||
# define FLASH_OPTR_BOR_LEV_2_2V (0x2 << FLASH_OPTR_BOR_LEV_SHIFT)
|
||||
# define FLASH_OPTR_BOR_LEV_2_5V (0x3 << FLASH_OPTR_BOR_LEV_SHIFT)
|
||||
# define FLASH_OPTR_BOR_LEV_2_8V (0x4 << FLASH_OPTR_BOR_LEV_SHIFT)
|
||||
# define FLASH_OPTR_NRST_STOP (1 << 12)
|
||||
# define FLASH_OPTR_NRST_STDBY (1 << 13)
|
||||
# define FLASH_OPTR_NRST_SHDW (1 << 14)
|
||||
# define FLASH_OPTR_IWDG_SW (1 << 16)
|
||||
# define FLASH_OPTR_IWDG_STOP (1 << 17)
|
||||
# define FLASH_OPTR_IWDG_STDBY (1 << 18)
|
||||
# define FLASH_OPTR_WWDG_SW (1 << 19)
|
||||
# define FLASH_OPTR_BFB2 (1 << 20)
|
||||
# define FLASH_OPTR_DBANK (1 << 22)
|
||||
# define FLASH_OPTR_NBOOT1 (1 << 23)
|
||||
# define FLASH_OPTR_SRAM_PE (1 << 24)
|
||||
# define FLASH_OPTR_CCMSRAM_RST (1 << 25)
|
||||
# define FLASH_OPTR_NSWBOOT0 (1 << 26)
|
||||
# define FLASH_OPTR_NBOOT0 (1 << 27)
|
||||
# define FLASH_OPTR_NRST_MODE_SHIFT (28)
|
||||
# define FLASH_OPTR_NRST_MODE_MASK (0x3 << FLASH_OPTR_NRST_MODE_SHIFT)
|
||||
# define FLASH_OPTR_NRST_MODE_NRST (0x1 << FLASH_OPTR_NRST_MODE_SHIFT)
|
||||
# define FLASH_OPTR_NRST_MODE_GPIO (0x2 << FLASH_OPTR_NRST_MODE_SHIFT)
|
||||
# define FLASH_OPTR_NRST_MODE_BIDI_NRST (0x3 << FLASH_OPTR_NRST_MODE_SHIFT)
|
||||
# define FLASH_OPTR_IRHEN (1 << 30)
|
||||
#endif
|
||||
|
||||
/* Flash PCROP1 Start Address Register (PCROP1SR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_PCROP1SR_PCROP1_STRT_SHIFT (0)
|
||||
# define FLASH_PCROP1SR_PCROP1_STRT_MASK (0x7fff << FLASH_PCROP1SR_PCROP1_STRT_SHIFT)
|
||||
# define FLASH_PCROP1SR_PCROP1_STRT(n) (((n) << FLASH_PCROP1SR_PCROP1_STRT_SHIFT) & FLASH_PCROP1SR_PCROP1_STRT_MASK)
|
||||
#endif
|
||||
|
||||
/* Flash PCROP1 End Address Register (PCROP1ER) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_PCROP1ER_PCROP1_END_SHIFT (0)
|
||||
# define FLASH_PCROP1ER_PCROP1_END_MASK (0x7fff << FLASH_PCROP1ER_PCROP1_END_SHIFT)
|
||||
# define FLASH_PCROP1ER_PCROP1_END(n) (((n) << FLASH_PCROP1ER_PCROP1_END_SHIFT) & FLASH_PCROP1ER_PCROP1_END_MASK)
|
||||
# define FLASH_PCROP1ER_PCROP_RDP (1 << 31)
|
||||
#endif
|
||||
|
||||
/* Flash Bank 1 WRP Area A Address Register (WRP1AR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_WRP1AR_WRP1A_STRT_SHIFT (0)
|
||||
# define FLASH_WRP1AR_WRP1A_STRT_MASK (0x7f << FLASH_WRP1AR_WRP1A_STRT_SHIFT)
|
||||
# define FLASH_WRP1AR_WRP1A_STRT(n) (((n) << FLASH_WRP1AR_WRP1A_STRT_SHIFT) & FLASH_WRP1AR_WRP1A_STRT_MASK)
|
||||
# define FLASH_WRP1AR_WRP1A_END_SHIFT (16)
|
||||
# define FLASH_WRP1AR_WRP1A_END_MASK (0x7f << FLASH_WRP1AR_WRP1A_END_SHIFT)
|
||||
# define FLASH_WRP1AR_WRP1A_END(n) (((n) << FLASH_WRP1AR_WRP1A_END_SHIFT) & FLASH_WRP1AR_WRP1A_END_MASK)
|
||||
#endif
|
||||
|
||||
/* Flash Bank 1 WRP Area B Address Register (WRPB1R) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_WRP1BR_WRP1B_STRT_SHIFT (0)
|
||||
# define FLASH_WRP1BR_WRP1B_STRT_MASK (0x7f << FLASH_WRP1BR_WRP1B_STRT_SHIFT)
|
||||
# define FLASH_WRP1BR_WRP1B_STRT(n) (((n) << FLASH_WRP1BR_WRP1B_STRT_SHIFT) & FLASH_WRP1BR_WRP1B_STRT_MASK)
|
||||
# define FLASH_WRP1BR_WRP1B_END_SHIFT (16)
|
||||
# define FLASH_WRP1BR_WRP1B_END_MASK (0x7f << FLASH_WRP1BR_WRP1B_END_SHIFT)
|
||||
# define FLASH_WRP1BR_WRP1B_END(n) (((n) << FLASH_WRP1BR_WRP1B_END_SHIFT) & FLASH_WRP1BR_WRP1B_END_MASK)
|
||||
#endif
|
||||
|
||||
/* Flash PCROP2 Start Address Register (PCROP2SR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_PCROP2SR_PCROP2_STRT_SHIFT (0)
|
||||
# define FLASH_PCROP2SR_PCROP2_STRT_MASK (0x7fff << FLASH_PCROP2SR_PCROP2_STRT_SHIFT)
|
||||
# define FLASH_PCROP2SR_PCROP2_STRT(n) (((n) << FLASH_PCROP2SR_PCROP2_STRT_SHIFT) & FLASH_PCROP2SR_PCROP2_STRT_MASK)
|
||||
#endif
|
||||
|
||||
/* Flash PCROP2 End Address Register (PCROP2ER) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_PCROP2ER_PCROP2_END_SHIFT (0)
|
||||
# define FLASH_PCROP2ER_PCROP2_END_MASK (0x7fff << FLASH_PCROP2ER_PCROP2_END_SHIFT)
|
||||
# define FLASH_PCROP2ER_PCROP2_END(n) (((n) << FLASH_PCROP2ER_PCROP2_END_SHIFT) & FLASH_PCROP2ER_PCROP2_END_MASK)
|
||||
#endif
|
||||
|
||||
/* Flash Bank 2 WRP Area A Address Register (WRP2AR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_WRP2AR_WRP2A_STRT_SHIFT (0)
|
||||
# define FLASH_WRP2AR_WRP2A_STRT_MASK (0x7f << FLASH_WRP2AR_WRP2A_STRT_SHIFT)
|
||||
# define FLASH_WRP2AR_WRP2A_STRT(n) (((n) << FLASH_WRP2AR_WRP2A_STRT_SHIFT) & FLASH_WRP2AR_WRP2A_STRT_MASK)
|
||||
# define FLASH_WRP2AR_WRP2A_END_SHIFT (16)
|
||||
# define FLASH_WRP2AR_WRP2A_END_MASK (0x7f << FLASH_WRP2AR_WRP2A_END_SHIFT)
|
||||
# define FLASH_WRP2AR_WRP2A_END(n) (((n) << FLASH_WRP2AR_WRP2A_END_SHIFT) & FLASH_WRP2AR_WRP2A_END_MASK)
|
||||
#endif
|
||||
|
||||
/* Flash Bank 2 WRP Area B Address Register (WRP2BR) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_WRP2BR_WRP2B_STRT_SHIFT (0)
|
||||
# define FLASH_WRP2BR_WRP2B_STRT_MASK (0x7f << FLASH_WRP2BR_WRP2B_STRT_SHIFT)
|
||||
# define FLASH_WRP2BR_WRP2B_STRT(n) (((n) << FLASH_WRP2BR_WRP2B_STRT_SHIFT) & FLASH_WRP2BR_WRP2B_STRT_SHIFT)
|
||||
# define FLASH_WRP2BR_WRP2B_END_SHIFT (16)
|
||||
# define FLASH_WRP2BR_WRP2B_END_MASK (0x7f << FLASH_WRP2BR_WRP2B_END_SHIFT)
|
||||
# define FLASH_WRP2BR_WRP2B_END(n) (((n) << FLASH_WRP2BR_WRP2B_END_SHIFT) & FLASH_WRP2BR_WRP2B_END_MASK)
|
||||
#endif
|
||||
|
||||
/* Flash Securable Area Bank 1 Register (SEC1R) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_SEC1R_SEC_SIZE1_SHIFT (0)
|
||||
# define FLASH_SEC1R_SEC_SIZE1_MASK (0xff << FLASH_SEC1R_SEC_SIZE1_SHIFT)
|
||||
# define FLASH_SEC1R_SEC_SIZE1(n) (((n) << FLASH_SEC1R_SEC_SIZE1_SHIFT) & FLASH_SEC1R_SEC_SIZE1_MASK)
|
||||
# define FLASH_SEC1R_BOOT_LOCK (1 << 16)
|
||||
#endif
|
||||
|
||||
/* Flash Securable Area Bank 2 Register (SEC2R) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define FLASH_SEC2R_SEC_SIZE2_SHIFT (0)
|
||||
# define FLASH_SEC2R_SEC_SIZE2_MASK (0xff << FLASH_SEC2R_SEC_SIZE2_SHIFT)
|
||||
# define FLASH_SEC2R_SEC_SIZE2(n) (((n) << FLASH_SEC2R_SEC_SIZE2_SHIFT) & FLASH_SEC2R_SEC_SIZE2_MASK)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
|
||||
/* There are 2 main types of I2C IP cores among STM32 chips:
|
||||
* 1. STM32 I2C IPv1 - F1, F2, F4 and L1
|
||||
* 2. STM32 I2C IPv2 - G0, L0, F0, F3, F7, H7 and L4
|
||||
* 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_I2C_V1)
|
||||
|
||||
@@ -36,8 +36,8 @@
|
||||
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H
|
||||
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H
|
||||
|
||||
/* This file provide definitions for the STM32 I2C IP core 2 (G0, L0, F0, F3, F7,
|
||||
* H7, and L4).
|
||||
/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0,
|
||||
* G4, H7, L0 and L4).
|
||||
*/
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@@ -57,6 +57,8 @@
|
||||
# include "hardware/stm32f37xxx_memorymap.h"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "hardware/stm32f40xxx_memorymap.h"
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# include "hardware/stm32g47xxx_memorymap.h"
|
||||
#else
|
||||
# error "Unsupported STM32 memory map"
|
||||
#endif
|
||||
|
||||
@@ -131,6 +131,12 @@
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "hardware/stm32f40xxx_pinmap.h"
|
||||
|
||||
/* STM32 G4 Family ******************************************************************/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# include "hardware/stm32g47xxx_pinmap.h"
|
||||
|
||||
#else
|
||||
# error "No pinmap file for this STM32 chip"
|
||||
#endif
|
||||
|
||||
@@ -100,6 +100,10 @@
|
||||
* For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit
|
||||
* The STM32 F1 Value Line and the STM32 F3 have variant general purpose registers
|
||||
* that are not yet fully covered in this header file.
|
||||
* The STM32 G47x also have variant registers that are not yet covered. Check
|
||||
* whether those are similar to the F1 and F3 mentioned above. In
|
||||
* particular, the DCR and DMAR offsets are 0x3dc and 0x3e0, respectively,
|
||||
* as opposed to the values below:
|
||||
*/
|
||||
|
||||
#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
@@ -129,7 +133,13 @@
|
||||
|
||||
#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11/16 option register */
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
/* Advanced Timers - TIM1 and TIM8
|
||||
*
|
||||
* The STM32 G47x have variant registers that are not yet covered. In
|
||||
* particular, the DCR and DMAR offsets are 0x3dc and 0x3e0, respectively,
|
||||
* as opposed to the values below, and there are several additional
|
||||
* registers that are not mentioned below at all.
|
||||
*/
|
||||
|
||||
#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */
|
||||
|
||||
@@ -493,6 +493,94 @@
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* STM32G47xxx family P/Ns have 96KiB of internal RAM in 2 banks, plus 32 KiB
|
||||
* of CCM SRAM (Routine Booster), and the possibility of external RAM via
|
||||
* FSMC:
|
||||
*
|
||||
* All internal RAM is contiguous from address 0x2000:0000 thru 0x2001:FFFF,
|
||||
* but consists of these separate regions:
|
||||
*
|
||||
* SRAM:
|
||||
*
|
||||
* 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3FFF.
|
||||
* 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7FFF.
|
||||
*
|
||||
* CCM SRAM:
|
||||
*
|
||||
* 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7FFF
|
||||
* but also aliased at at 0x2001:8000 thru 0x2001:FFFF to be contiguous
|
||||
* with the SRAM1 and SRAM2.
|
||||
*
|
||||
* Because SRAM1 and SRAM2 are contiguous, they are treated as one region
|
||||
* by this logic.
|
||||
*
|
||||
* REVISIT: I believe that unlike other parts mentioned in this file, the
|
||||
* CCM SRAM *is* accessible to DMA. See Reference Manual (RM0440 Rev 2)
|
||||
* section 2.1.3, DMA-Bus: "This bus connects the AHB master interface of
|
||||
* the DMA to the BusMatrix. The targets of this bus are the SRAM1, SRAM2
|
||||
* and CCM SRAM..." Then, should we exclude CCM SRAM from the heap?
|
||||
*
|
||||
* In addition, external FSMC SRAM may be available.
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
|
||||
/* Set the end of system SRAM */
|
||||
|
||||
# define SRAM1_END 0x20020000
|
||||
|
||||
/* Set the range of CCM SRAM as well (although we may not use it) */
|
||||
|
||||
# define SRAM2_START 0x10000000
|
||||
# define SRAM2_END 0x10008000
|
||||
|
||||
/* There are 4 possible SRAM configurations:
|
||||
*
|
||||
* Configuration 1. System SRAM (only)
|
||||
* CONFIG_MM_REGIONS == 1
|
||||
* CONFIG_STM32_EXTERNAL_RAM NOT defined
|
||||
* CONFIG_STM32_CCMEXCLUDE defined
|
||||
* Configuration 2. System SRAM and CCM SRAM
|
||||
* CONFIG_MM_REGIONS == 2
|
||||
* CONFIG_STM32_EXTERNAL_RAM NOT defined
|
||||
* CONFIG_STM32_CCMEXCLUDE NOT defined
|
||||
* Configuration 3. System SRAM and FSMC SRAM
|
||||
* CONFIG_MM_REGIONS == 2
|
||||
* CONFIG_STM32_EXTERNAL_RAM defined
|
||||
* CONFIG_STM32_CCMEXCLUDE defined
|
||||
* Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
|
||||
* CONFIG_MM_REGIONS == 3
|
||||
* CONFIG_STM32_EXTERNAL_RAM defined
|
||||
* CONFIG_STM32_CCMEXCLUDE NOT defined
|
||||
*
|
||||
* Let's make sure that all definitions are consistent before doing
|
||||
* anything else
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_STM32_EXTERNAL_RAM)
|
||||
# if (CONFIG_MM_REGIONS == 2)
|
||||
/* OK: This is Configuration 3: SRAM and FSMC */
|
||||
|
||||
# elif (CONFIG_MM_REGIONS == 3)
|
||||
/* OK: This is Configuration 3: SRAM, CCM, and FSMC */
|
||||
|
||||
# else
|
||||
# error "Expected CONFIG_MM_REGIONS to be either 2 (SRAM + FSMC) or 3 (SRAM + CCM + FSMC)!"
|
||||
|
||||
# endif
|
||||
# else
|
||||
# if (CONFIG_MM_REGIONS == 1)
|
||||
/* OK: Configuration 1: SRAM only. */
|
||||
|
||||
# elif (CONFIG_MM_REGIONS == 2)
|
||||
/* OK: Configuration 2: SRAM and CCM SRAM. */
|
||||
|
||||
# else
|
||||
# error "Expected CONFIG_MM_REGIONS to be either 1 (SRAM) or 2 (SRAM + CCM)!"
|
||||
|
||||
# endif
|
||||
# endif
|
||||
|
||||
#else
|
||||
# error "Unsupported STM32 chip"
|
||||
#endif
|
||||
|
||||
@@ -43,7 +43,7 @@
|
||||
|
||||
/* This file is only a thin shell that includes the correct DMA
|
||||
* implementation for the selected STM32 IP core:
|
||||
* - STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4
|
||||
* - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4
|
||||
* - STM32 DMA IP version 2 - F2, F4, F7, H7
|
||||
*
|
||||
* The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it
|
||||
|
||||
@@ -56,23 +56,34 @@
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32.h"
|
||||
|
||||
/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L0, L1,
|
||||
* L4.
|
||||
/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, G4, L0,
|
||||
* L1, L4.
|
||||
*
|
||||
* F0, L0 and L4 have the additional CSELR register which is used to remap
|
||||
* the DMA requests for each channel.
|
||||
*
|
||||
* G4 has additional channels in DMA1 and DMA2.
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define DMA1_NCHANNELS 7
|
||||
#if STM32_NDMA > 1
|
||||
# define DMA2_NCHANNELS 5
|
||||
# define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS)
|
||||
#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8)
|
||||
# define DMA1_NCHANNELS 8
|
||||
#else
|
||||
# define DMA_NCHANNELS DMA1_NCHANNELS
|
||||
# define DMA1_NCHANNELS 7
|
||||
#endif
|
||||
|
||||
#if STM32_NDMA > 1
|
||||
# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678)
|
||||
# define DMA2_NCHANNELS 8
|
||||
# else
|
||||
# define DMA2_NCHANNELS 5
|
||||
# endif
|
||||
# define DMA_NCHANNELS (DMA1_NCHANNELS + DMA2_NCHANNELS)
|
||||
#else
|
||||
# define DMA_NCHANNELS DMA1_NCHANNELS
|
||||
#endif
|
||||
|
||||
/* Convert the DMA channel base address to the DMA register block address */
|
||||
@@ -106,80 +117,132 @@ struct stm32_dma_s
|
||||
|
||||
static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
|
||||
{
|
||||
#if DMA1_NCHANNELS > 0
|
||||
{
|
||||
.chan = 0,
|
||||
.irq = STM32_IRQ_DMA1CH1,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 0 */
|
||||
#if DMA1_NCHANNELS > 1
|
||||
{
|
||||
.chan = 1,
|
||||
.irq = STM32_IRQ_DMA1CH2,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 1 */
|
||||
#if DMA1_NCHANNELS > 2
|
||||
{
|
||||
.chan = 2,
|
||||
.irq = STM32_IRQ_DMA1CH3,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 2 */
|
||||
#if DMA1_NCHANNELS > 3
|
||||
{
|
||||
.chan = 3,
|
||||
.irq = STM32_IRQ_DMA1CH4,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 3 */
|
||||
#if DMA1_NCHANNELS > 4
|
||||
{
|
||||
.chan = 4,
|
||||
.irq = STM32_IRQ_DMA1CH5,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 4 */
|
||||
#if DMA1_NCHANNELS > 5
|
||||
{
|
||||
.chan = 5,
|
||||
.irq = STM32_IRQ_DMA1CH6,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 5 */
|
||||
#if DMA1_NCHANNELS > 6
|
||||
{
|
||||
.chan = 6,
|
||||
.irq = STM32_IRQ_DMA1CH7,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 6 */
|
||||
#if DMA1_NCHANNELS > 7
|
||||
{
|
||||
.chan = 7,
|
||||
.irq = STM32_IRQ_DMA1CH8,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(7),
|
||||
},
|
||||
#endif /* DMA1_NCHANNELS > 7 */
|
||||
#if STM32_NDMA > 1
|
||||
#if DMA2_NCHANNELS > 0
|
||||
{
|
||||
.chan = 0,
|
||||
.irq = STM32_IRQ_DMA2CH1,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
|
||||
},
|
||||
#endif /* DMA2_NCHANNELS > 0 */
|
||||
#if DMA2_NCHANNELS > 1
|
||||
{
|
||||
.chan = 1,
|
||||
.irq = STM32_IRQ_DMA2CH2,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
|
||||
},
|
||||
#endif /* DMA2_NCHANNELS > 1 */
|
||||
#if DMA2_NCHANNELS > 2
|
||||
{
|
||||
.chan = 2,
|
||||
.irq = STM32_IRQ_DMA2CH3,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
|
||||
},
|
||||
#endif /* DMA2_NCHANNELS > 2 */
|
||||
#if DMA2_NCHANNELS > 3
|
||||
{
|
||||
.chan = 3,
|
||||
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
.irq = STM32_IRQ_DMA2CH4,
|
||||
#else
|
||||
.irq = STM32_IRQ_DMA2CH45,
|
||||
#endif
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
|
||||
},
|
||||
#endif /* DMA2_NCHANNELS > 3 */
|
||||
#if DMA2_NCHANNELS > 4
|
||||
{
|
||||
.chan = 4,
|
||||
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
.irq = STM32_IRQ_DMA2CH5,
|
||||
#else
|
||||
.irq = STM32_IRQ_DMA2CH45,
|
||||
#endif
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
|
||||
},
|
||||
#endif
|
||||
#endif /* DMA2_NCHANNELS > 4 */
|
||||
#if DMA2_NCHANNELS > 5
|
||||
{
|
||||
.chan = 5,
|
||||
.irq = STM32_IRQ_DMA2CH5,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5),
|
||||
},
|
||||
#endif /* DMA2_NCHANNELS > 5 */
|
||||
#if DMA2_NCHANNELS > 6
|
||||
{
|
||||
.chan = 6,
|
||||
.irq = STM32_IRQ_DMA2CH6,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6),
|
||||
},
|
||||
#endif /* DMA2_NCHANNELS > 6 */
|
||||
#if DMA2_NCHANNELS > 7
|
||||
{
|
||||
.chan = 7,
|
||||
.irq = STM32_IRQ_DMA2CH7,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(7),
|
||||
},
|
||||
#endif /* DMA2_NCHANNELS > 7 */
|
||||
#endif /* STM32_NDMA > 1 */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@@ -268,6 +331,41 @@ static void stm32_dmachandisable(struct stm32_dma_s *dmach)
|
||||
DMA_ISR_CHAN_MASK(dmach->chan));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: irq_to_channel_index
|
||||
*
|
||||
* Description:
|
||||
* Given an IRQ number, find the channel index in the g_dma array.
|
||||
*
|
||||
* Parameters:
|
||||
* irq: IRQ number as passed to stm32_dmainterrupt.
|
||||
*
|
||||
* Returned Value:
|
||||
* On success (IRQ matches a DMA channel), returns index in the g_dma
|
||||
* array from 0 to DMA_NCHANNELS - 1. On failure (IRQ does not match
|
||||
* a DMA channel), returns -1.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int irq_to_channel_index(int irq)
|
||||
{
|
||||
int chndx;
|
||||
|
||||
/* Find the DMA channel that matches this IRQ */
|
||||
|
||||
for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
|
||||
{
|
||||
if (irq == g_dma[chndx].irq)
|
||||
{
|
||||
return chndx;
|
||||
}
|
||||
}
|
||||
|
||||
/* Failed to find the DMA channel for this IRQ */
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmainterrupt
|
||||
*
|
||||
@@ -284,23 +382,8 @@ static int stm32_dmainterrupt(int irq, void *context, FAR void *arg)
|
||||
|
||||
/* Get the channel structure from the interrupt number */
|
||||
|
||||
if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
|
||||
{
|
||||
chndx = irq - STM32_IRQ_DMA1CH1;
|
||||
}
|
||||
else
|
||||
#if STM32_NDMA > 1
|
||||
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
|
||||
#else
|
||||
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
|
||||
#endif
|
||||
{
|
||||
chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
chndx = irq_to_channel_index(irq);
|
||||
if (chndx < 0)
|
||||
{
|
||||
DEBUGPANIC();
|
||||
}
|
||||
|
||||
@@ -224,6 +224,36 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
|
||||
_info(" GPIO%c not enabled: AHB1ENR: %08x\n",
|
||||
g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
DEBUGASSERT(port < STM32_NGPIO_PORTS);
|
||||
|
||||
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
|
||||
g_portchar[port], pinset, base, msg);
|
||||
|
||||
if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
|
||||
{
|
||||
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
|
||||
getreg32(base + STM32_GPIO_MODER_OFFSET),
|
||||
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
|
||||
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
|
||||
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
|
||||
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
|
||||
getreg32(base + STM32_GPIO_IDR_OFFSET),
|
||||
getreg32(base + STM32_GPIO_ODR_OFFSET),
|
||||
getreg32(base + STM32_GPIO_BSRR_OFFSET),
|
||||
getreg32(base + STM32_GPIO_LCKR_OFFSET));
|
||||
_info(" AFRH: %08x AFRL: %08x BRR: %04x\n",
|
||||
getreg32(base + STM32_GPIO_AFRH_OFFSET),
|
||||
getreg32(base + STM32_GPIO_AFRL_OFFSET),
|
||||
getreg32(base + STM32_GPIO_BRR_OFFSET));
|
||||
}
|
||||
else
|
||||
{
|
||||
_info(" GPIO%c not enabled: AHB2ENR: %08x\n",
|
||||
g_portchar[port], getreg32(STM32_RCC_AHB2ENR));
|
||||
}
|
||||
|
||||
#else
|
||||
# error "Unsupported STM32 chip"
|
||||
#endif
|
||||
|
||||
@@ -410,13 +410,14 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_configgpio (for the STM32L15xxx, STM32F20xxx and STM32F40xxx
|
||||
* family)
|
||||
* Name: stm32_configgpio (for the STM32L15xxx, STM32F20xxx, STM32F40xxx,
|
||||
* and STM32G47XX families).
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX)
|
||||
int stm32_configgpio(uint32_t cfgset)
|
||||
{
|
||||
uintptr_t base;
|
||||
@@ -547,11 +548,11 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
{
|
||||
#if defined(CONFIG_STM32_STM32L15XX)
|
||||
default:
|
||||
case GPIO_SPEED_400KHz: /* 400 kHz Very low speed output */
|
||||
case GPIO_SPEED_400KHz: /* 400 kHz Very low speed output */
|
||||
setting = GPIO_OSPEED_400KHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */
|
||||
case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */
|
||||
setting = GPIO_OSPEED_2MHz;
|
||||
break;
|
||||
|
||||
@@ -562,6 +563,23 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
case GPIO_SPEED_40MHz: /* 40 MHz High speed output */
|
||||
setting = GPIO_OSPEED_40MHz;
|
||||
break;
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
default:
|
||||
case GPIO_SPEED_5MHz: /* 5 MHz Low speed output */
|
||||
setting = GPIO_OSPEED_5MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_25MHz: /* 25 MHz Medium speed output */
|
||||
setting = GPIO_OSPEED_25MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */
|
||||
setting = GPIO_OSPEED_50MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_120MHz: /* 120 MHz High speed output */
|
||||
setting = GPIO_OSPEED_120MHz;
|
||||
break;
|
||||
#else
|
||||
default:
|
||||
case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */
|
||||
@@ -655,10 +673,10 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
* Description:
|
||||
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
|
||||
* it into default HiZ state (and possibly mark it's unused) and unlock it
|
||||
* whether it was previously selected as alternative function
|
||||
* (GPIO_ALT|GPIO_CNF_AFPP|...).
|
||||
* whether it was previously selected as an alternative function
|
||||
* (GPIO_ALT | GPIO_CNF_AFPP | ...).
|
||||
*
|
||||
* This is a safety function and prevents hardware from schocks, as
|
||||
* This is a safety function and prevents hardware from shocks, as
|
||||
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
|
||||
* while it should operate in PWM mode could produce excessive on-board
|
||||
* currents and trigger over-current/alarm function.
|
||||
@@ -679,7 +697,8 @@ int stm32_unconfiggpio(uint32_t cfgset)
|
||||
cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
|
||||
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX)
|
||||
cfgset |= GPIO_INPUT | GPIO_FLOAT;
|
||||
#else
|
||||
# error "Unsupported STM32 chip"
|
||||
@@ -705,7 +724,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
|
||||
uint32_t offset;
|
||||
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX)
|
||||
uint32_t bit;
|
||||
#endif
|
||||
unsigned int port;
|
||||
@@ -739,7 +759,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX)
|
||||
|
||||
if (value)
|
||||
{
|
||||
|
||||
@@ -64,6 +64,8 @@
|
||||
# include "hardware/stm32f30xxx_gpio.h"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "hardware/stm32f40xxx_gpio.h"
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# include "hardware/stm32g47xxx_gpio.h"
|
||||
#else
|
||||
# error "Unrecognized STM32 chip"
|
||||
#endif
|
||||
@@ -204,8 +206,8 @@
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX)
|
||||
/* Each port bit of the general-purpose I/O (GPIO) ports can be
|
||||
* individually configured by software in several modes:
|
||||
*
|
||||
@@ -295,16 +297,21 @@
|
||||
#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */
|
||||
#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
|
||||
#if defined(CONFIG_STM32_STM32L15XX)
|
||||
# define GPIO_SPEED_400KHz (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed output */
|
||||
# define GPIO_SPEED_2MHz (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_10MHz (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */
|
||||
# define GPIO_SPEED_40MHz (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */
|
||||
# define GPIO_SPEED_400KHz (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed output */
|
||||
# define GPIO_SPEED_2MHz (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_10MHz (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */
|
||||
# define GPIO_SPEED_40MHz (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */
|
||||
#elif defined(CONFIG_STM32_STM32G47XX) /* With C=50pF, 2.7<VDD<3.6, DS12288 Rev2 Table 59 */
|
||||
# define GPIO_SPEED_5MHz (0 << GPIO_SPEED_SHIFT) /* 5 MHz Low speed output */
|
||||
# define GPIO_SPEED_25MHz (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
|
||||
# define GPIO_SPEED_50MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
|
||||
# define GPIO_SPEED_120MHz (3 << GPIO_SPEED_SHIFT) /* 120 MHz High speed output */
|
||||
#else
|
||||
# define GPIO_SPEED_2MHz (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_25MHz (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
|
||||
# define GPIO_SPEED_50MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
|
||||
# define GPIO_SPEED_2MHz (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_25MHz (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
|
||||
# define GPIO_SPEED_50MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
|
||||
#ifndef CONFIG_STM32_STM32F30XX
|
||||
# define GPIO_SPEED_100MHz (3 << GPIO_SPEED_SHIFT) /* 100 MHz High speed output */
|
||||
# define GPIO_SPEED_100MHz (3 << GPIO_SPEED_SHIFT) /* 100 MHz High speed output */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
@@ -235,7 +235,7 @@
|
||||
# endif
|
||||
|
||||
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
# define USART_CR1_CLRBITS\
|
||||
(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
|
||||
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \
|
||||
@@ -258,7 +258,7 @@
|
||||
# endif
|
||||
|
||||
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
# define USART_CR2_CLRBITS \
|
||||
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
|
||||
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
|
||||
@@ -275,7 +275,7 @@
|
||||
/* CR3 settings */
|
||||
|
||||
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
|
||||
# define USART_CR3_CLRBITS \
|
||||
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
|
||||
@@ -296,7 +296,7 @@
|
||||
/* Calculate USART BAUD rate divider */
|
||||
|
||||
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
@@ -577,7 +577,8 @@ void stm32_lowsetup(void)
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
|
||||
defined(CONFIG_STM32_STM32G47XX)
|
||||
|
||||
void stm32_lowsetup(void)
|
||||
{
|
||||
|
||||
@@ -89,6 +89,8 @@
|
||||
# include "stm32f37xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "stm32f40xxx_rcc.c"
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# include "stm32g47xxx_rcc.c"
|
||||
#else
|
||||
# error "Unsupported STM32 chip"
|
||||
#endif
|
||||
|
||||
@@ -59,6 +59,10 @@
|
||||
# include "hardware/stm32f37xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "hardware/stm32f40xxx_rcc.h"
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# include "hardware/stm32g47xxx_rcc.h"
|
||||
#else
|
||||
# error "Unsupported STM32 chip"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@@ -154,7 +154,7 @@
|
||||
|
||||
# elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
|
||||
# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
|
||||
defined(CONFIG_USART3_RXDMA)
|
||||
@@ -198,7 +198,7 @@
|
||||
# ifndef CONFIG_USART_RXDMAPRIO
|
||||
# if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
# define CONFIG_USART_RXDMAPRIO DMA_CCR_PRIMED
|
||||
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
|
||||
# define CONFIG_USART_RXDMAPRIO DMA_SCR_PRIMED
|
||||
@@ -208,7 +208,7 @@
|
||||
# endif
|
||||
# if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
# if (CONFIG_USART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0
|
||||
# error "Illegal value for CONFIG_USART_RXDMAPRIO"
|
||||
# endif
|
||||
@@ -1177,7 +1177,7 @@ static void up_set_format(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
uint32_t usartdiv8;
|
||||
#else
|
||||
uint32_t usartdiv32;
|
||||
@@ -1192,7 +1192,7 @@ static void up_set_format(struct uart_dev_s *dev)
|
||||
regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
/* This first implementation is for U[S]ARTs that support oversampling
|
||||
* by 8 in additional to the standard oversampling by 16.
|
||||
* With baud rate of fCK / Divider for oversampling by 16.
|
||||
@@ -1882,7 +1882,7 @@ static int up_interrupt(int irq, void *context, void *arg)
|
||||
else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0)
|
||||
{
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G47XX)
|
||||
/* These errors are cleared by writing the corresponding bit to the
|
||||
* interrupt clear register (ICR).
|
||||
*/
|
||||
|
||||
@@ -55,6 +55,8 @@
|
||||
# include "hardware/stm32f37xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "hardware/stm32f40xxx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# include "hardware/stm32g47xxx_syscfg.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
|
||||
@@ -56,6 +56,8 @@
|
||||
# include "hardware/stm32f30xxx_uart.h"
|
||||
#elif defined(CONFIG_STM32_STM32F4XXX)
|
||||
# include "hardware/stm32f40xxx_uart.h"
|
||||
#elif defined(CONFIG_STM32_STM32G47XX)
|
||||
# include "hardware/stm32g47xxx_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32 UART"
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user